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* config/tc-arm.c (s_arm_tls_desceq): Move code into ELF-only
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
c75ef631 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
22109423 135 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 136}
137arch_entry;
138
78f12dd3 139static void update_code_flag (int, int);
e3bb37b5
L		 140static void set_code_flag (int);
141static void set_16bit_gcc_code_flag (int);
142static void set_intel_syntax (int);
1efbbeb4 143static void set_intel_mnemonic (int);
db51cc60 144static void set_allow_index_reg (int);
cb19c032 145static void set_sse_check (int);
e3bb37b5 146static void set_cpu_arch (int);
6482c264 147#ifdef TE_PE
e3bb37b5 148static void pe_directive_secrel (int);
6482c264 149#endif
e3bb37b5
L		 150static void signed_cons (int);
151static char *output_invalid (int c);
ee86248c
JB		 152static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
153 const char *);
154static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
155 const char *);
a7619375 156static int i386_att_operand (char *);
e3bb37b5 157static int i386_intel_operand (char *, int);
ee86248c
JB		 158static int i386_intel_simplify (expressionS *);
159static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 160static const reg_entry *parse_register (char *, char **);
161static char *parse_insn (char *, char *);
162static char *parse_operands (char *, const char *);
163static void swap_operands (void);
4d456e3d 164static void swap_2_operands (int, int);
e3bb37b5
L		 165static void optimize_imm (void);
166static void optimize_disp (void);
d3ce72d0 167static const insn_template *match_template (void);
e3bb37b5
L		 168static int check_string (void);
169static int process_suffix (void);
170static int check_byte_reg (void);
171static int check_long_reg (void);
172static int check_qword_reg (void);
173static int check_word_reg (void);
174static int finalize_imm (void);
175static int process_operands (void);
176static const seg_entry *build_modrm_byte (void);
177static void output_insn (void);
178static void output_imm (fragS *, offsetT);
179static void output_disp (fragS *, offsetT);
29b0f896 180#ifndef I386COFF
e3bb37b5 181static void s_bss (int);
252b5132 182#endif
17d4e2a2
L		 183#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
184static void handle_large_common (int small ATTRIBUTE_UNUSED);
185#endif
252b5132 186
a847613f 187static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 188
c0f3af97
L		 189/* VEX prefix. */
190typedef struct
191{
192 /* VEX prefix is either 2 byte or 3 byte. */
193 unsigned char bytes[3];
194 unsigned int length;
195 /* Destination or source register specifier. */
196 const reg_entry *register_specifier;
197} vex_prefix;
198
252b5132 199/* 'md_assemble ()' gathers together information and puts it into a
47926f60 200 i386_insn. */
252b5132 201
520dc8e8
AM		 202union i386_op
203 {
204 expressionS *disps;
205 expressionS *imms;
206 const reg_entry *regs;
207 };
208
a65babc9
L		 209enum i386_error
210 {
86e026a4 211 operand_size_mismatch,
a65babc9
L		 212 operand_type_mismatch,
213 register_type_mismatch,
214 number_of_operands_mismatch,
215 invalid_instruction_suffix,
216 bad_imm4,
217 old_gcc_only,
218 unsupported_with_intel_mnemonic,
219 unsupported_syntax,
220 unsupported
221 };
222
252b5132
RH		 223struct _i386_insn
224 {
47926f60 225 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 226 insn_template tm;
252b5132 227
7d5e4556
L		 228 /* SUFFIX holds the instruction size suffix for byte, word, dword
229 or qword, if given. */
252b5132
RH		 230 char suffix;
231
47926f60 232 /* OPERANDS gives the number of given operands. */
252b5132
RH		 233 unsigned int operands;
234
235 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
236 of given register, displacement, memory operands and immediate
47926f60 237 operands. */
252b5132
RH		 238 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
239
240 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 241 use OP[i] for the corresponding operand. */
40fb9820 242 i386_operand_type types[MAX_OPERANDS];
252b5132 243
520dc8e8
AM		 244 /* Displacement expression, immediate expression, or register for each
245 operand. */
246 union i386_op op[MAX_OPERANDS];
252b5132 247
3e73aa7c
JH		 248 /* Flags for operands. */
249 unsigned int flags[MAX_OPERANDS];
250#define Operand_PCrel 1
251
252b5132 252 /* Relocation type for operand */
f86103b7 253 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 254
252b5132
RH		 255 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
256 the base index byte below. */
257 const reg_entry *base_reg;
258 const reg_entry *index_reg;
259 unsigned int log2_scale_factor;
260
261 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 262 explicit segment overrides are given. */
ce8a8b2f 263 const seg_entry *seg[2];
252b5132
RH		 264
265 /* PREFIX holds all the given prefix opcodes (usually null).
266 PREFIXES is the number of prefix opcodes. */
267 unsigned int prefixes;
268 unsigned char prefix[MAX_PREFIXES];
269
270 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 271 addressing modes of this insn are encoded. */
252b5132 272 modrm_byte rm;
3e73aa7c 273 rex_byte rex;
252b5132 274 sib_byte sib;
c0f3af97 275 vex_prefix vex;
b6169b20
L		 276
277 /* Swap operand in encoding. */
4473e004 278 unsigned int swap_operand;
891edac4 279
f8a5c266
L		 280 /* Force 32bit displacement in encoding. */
281 unsigned int disp32_encoding;
282
891edac4 283 /* Error message. */
a65babc9 284 enum i386_error error;
252b5132
RH		 285 };
286
287typedef struct _i386_insn i386_insn;
288
289/* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
32137342 291const char extra_symbol_chars[] = "*%-(["
252b5132 292#ifdef LEX_AT
32137342
NC		 293 "@"
294#endif
295#ifdef LEX_QM
296 "?"
252b5132 297#endif
32137342 298 ;
252b5132 299
29b0f896
AM		 300#if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 302 && !defined (TE_GNU) \
29b0f896 303 && !defined (TE_LINUX) \
32137342 304 && !defined (TE_NETWARE) \
29b0f896
AM		 305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
252b5132 307/* This array holds the chars that always start a comment. If the
b3b91714
AM		 308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310const char *i386_comment_chars = "#/";
311#define SVR4_COMMENT_CHARS 1
252b5132 312#define PREFIX_SEPARATOR '\\'
252b5132 313
b3b91714
AM		 314#else
315const char *i386_comment_chars = "#";
316#define PREFIX_SEPARATOR '/'
317#endif
318
252b5132
RH		 319/* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 323 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
252b5132 326 '/' isn't otherwise defined. */
b3b91714 327const char line_comment_chars[] = "#/";
252b5132 328
63a0b638 329const char line_separator_chars[] = ";";
252b5132 330
ce8a8b2f
AM		 331/* Chars that can be used to separate mant from exp in floating point
332 nums. */
252b5132
RH		 333const char EXP_CHARS[] = "eE";
334
ce8a8b2f
AM		 335/* Chars that mean this number is a floating point constant
336 As in 0f12.456
337 or 0d1.2345e12. */
252b5132
RH		 338const char FLT_CHARS[] = "fFdDxX";
339
ce8a8b2f 340/* Tables for lexical analysis. */
252b5132
RH		 341static char mnemonic_chars[256];
342static char register_chars[256];
343static char operand_chars[256];
344static char identifier_chars[256];
345static char digit_chars[256];
346
ce8a8b2f 347/* Lexical macros. */
252b5132
RH		 348#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349#define is_operand_char(x) (operand_chars[(unsigned char) x])
350#define is_register_char(x) (register_chars[(unsigned char) x])
351#define is_space_char(x) ((x) == ' ')
352#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353#define is_digit_char(x) (digit_chars[(unsigned char) x])
354
0234cb7c 355/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 356static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
357
358/* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
47926f60 361 assembler instruction). */
252b5132 362static char save_stack[32];
ce8a8b2f 363static char *save_stack_p;
252b5132
RH		 364#define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366#define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
368
47926f60 369/* The instruction we're assembling. */
252b5132
RH		 370static i386_insn i;
371
372/* Possible templates for current insn. */
373static const templates *current_templates;
374
31b2323c
L		 375/* Per instruction expressionS buffers: max displacements & immediates. */
376static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
377static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 378
47926f60 379/* Current operand we are working on. */
ee86248c 380static int this_operand = -1;
252b5132 381
3e73aa7c
JH		 382/* We support four different modes. FLAG_CODE variable is used to distinguish
383 these. */
384
385enum flag_code {
386 CODE_32BIT,
387 CODE_16BIT,
388 CODE_64BIT };
389
390static enum flag_code flag_code;
4fa24527 391static unsigned int object_64bit;
3e73aa7c
JH		 392static int use_rela_relocations = 0;
393
351f65ca
L		 394/* The ELF ABI to use. */
395enum x86_elf_abi
396{
397 I386_ABI,
398 X86_64_LP64_ABI,
399 X86_64_ILP32_ABI
400};
401
402static enum x86_elf_abi x86_elf_abi = I386_ABI;
403
3e73aa7c 404/* The names used to print error messages. */
b77a7acd 405static const char *flag_code_names[] =
3e73aa7c
JH		 406 {
407 "32",
408 "16",
409 "64"
410 };
252b5132 411
47926f60
KH		 412/* 1 for intel syntax,
413 0 if att syntax. */
414static int intel_syntax = 0;
252b5132 415
1efbbeb4
L		 416/* 1 for intel mnemonic,
417 0 if att mnemonic. */
418static int intel_mnemonic = !SYSV386_COMPAT;
419
5209009a 420/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 421static int old_gcc = OLDGCC_COMPAT;
422
a60de03c
JB		 423/* 1 if pseudo registers are permitted. */
424static int allow_pseudo_reg = 0;
425
47926f60
KH		 426/* 1 if register prefix % not required. */
427static int allow_naked_reg = 0;
252b5132 428
ba104c83 429/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 430static int allow_index_reg = 0;
431
daf50ae7
L		 432static enum
433 {
434 sse_check_none = 0,
435 sse_check_warning,
436 sse_check_error
437 }
438sse_check;
439
2ca3ace5
L		 440/* Register prefix used for error message. */
441static const char *register_prefix = "%";
442
47926f60
KH		 443/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
444 leave, push, and pop instructions so that gcc has the same stack
445 frame as in 32 bit mode. */
446static char stackop_size = '\0';
eecb386c 447
12b55ccc
L		 448/* Non-zero to optimize code alignment. */
449int optimize_align_code = 1;
450
47926f60
KH		 451/* Non-zero to quieten some warnings. */
452static int quiet_warnings = 0;
a38cf1db 453
47926f60
KH		 454/* CPU name. */
455static const char *cpu_arch_name = NULL;
6305a203 456static char *cpu_sub_arch_name = NULL;
a38cf1db 457
47926f60 458/* CPU feature flags. */
40fb9820
L		 459static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
460
ccc9c027
L		 461/* If we have selected a cpu we are generating instructions for. */
462static int cpu_arch_tune_set = 0;
463
9103f4f4 464/* Cpu we are generating instructions for. */
fbf3f584 465enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 466
467/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 468static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 469
ccc9c027 470/* CPU instruction set architecture used. */
fbf3f584 471enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 472
9103f4f4 473/* CPU feature flags of instruction set architecture used. */
fbf3f584 474i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 475
fddf5b5b
AM		 476/* If set, conditional jumps are not automatically promoted to handle
477 larger than a byte offset. */
478static unsigned int no_cond_jump_promotion = 0;
479
c0f3af97
L		 480/* Encode SSE instructions with VEX prefix. */
481static unsigned int sse2avx;
482
539f890d
L		 483/* Encode scalar AVX instructions with specific vector length. */
484static enum
485 {
486 vex128 = 0,
487 vex256
488 } avxscalar;
489
29b0f896 490/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 491static symbolS *GOT_symbol;
29b0f896 492
a4447b93
RH		 493/* The dwarf2 return column, adjusted for 32 or 64 bit. */
494unsigned int x86_dwarf2_return_column;
495
496/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
497int x86_cie_data_alignment;
498
252b5132 499/* Interface to relax_segment.
fddf5b5b
AM		 500 There are 3 major relax states for 386 jump insns because the
501 different types of jumps add different sizes to frags when we're
502 figuring out what sort of jump to choose to reach a given label. */
252b5132 503
47926f60 504/* Types. */
93c2a809
AM		 505#define UNCOND_JUMP 0
506#define COND_JUMP 1
507#define COND_JUMP86 2
fddf5b5b 508
47926f60 509/* Sizes. */
252b5132
RH		 510#define CODE16 1
511#define SMALL 0
29b0f896 512#define SMALL16 (SMALL | CODE16)
252b5132 513#define BIG 2
29b0f896 514#define BIG16 (BIG | CODE16)
252b5132
RH		 515
516#ifndef INLINE
517#ifdef __GNUC__
518#define INLINE __inline__
519#else
520#define INLINE
521#endif
522#endif
523
fddf5b5b
AM		 524#define ENCODE_RELAX_STATE(type, size) \
525 ((relax_substateT) (((type) << 2) | (size)))
526#define TYPE_FROM_RELAX_STATE(s) \
527 ((s) >> 2)
528#define DISP_SIZE_FROM_RELAX_STATE(s) \
529 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 530
531/* This table is used by relax_frag to promote short jumps to long
532 ones where necessary. SMALL (short) jumps may be promoted to BIG
533 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
534 don't allow a short jump in a 32 bit code segment to be promoted to
535 a 16 bit offset jump because it's slower (requires data size
536 prefix), and doesn't work, unless the destination is in the bottom
537 64k of the code segment (The top 16 bits of eip are zeroed). */
538
539const relax_typeS md_relax_table[] =
540{
24eab124
AM		 541 /* The fields are:
542 1) most positive reach of this state,
543 2) most negative reach of this state,
93c2a809 544 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 545 4) which index into the table to try if we can't fit into this one. */
252b5132 546
fddf5b5b 547 /* UNCOND_JUMP states. */
93c2a809
AM		 548 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
549 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
550 /* dword jmp adds 4 bytes to frag:
551 0 extra opcode bytes, 4 displacement bytes. */
252b5132 552 {0, 0, 4, 0},
93c2a809
AM		 553 /* word jmp adds 2 byte2 to frag:
554 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 555 {0, 0, 2, 0},
556
93c2a809
AM		 557 /* COND_JUMP states. */
558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
559 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
560 /* dword conditionals adds 5 bytes to frag:
561 1 extra opcode byte, 4 displacement bytes. */
562 {0, 0, 5, 0},
fddf5b5b 563 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 564 1 extra opcode byte, 2 displacement bytes. */
565 {0, 0, 3, 0},
566
567 /* COND_JUMP86 states. */
568 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
569 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
570 /* dword conditionals adds 5 bytes to frag:
571 1 extra opcode byte, 4 displacement bytes. */
572 {0, 0, 5, 0},
573 /* word conditionals add 4 bytes to frag:
574 1 displacement byte and a 3 byte long branch insn. */
575 {0, 0, 4, 0}
252b5132
RH		 576};
577
9103f4f4
L		 578static const arch_entry cpu_arch[] =
579{
89507696
JB		 580 /* Do not replace the first two entries - i386_target_format()
581 relies on them being there in this order. */
8a2c8fef 582 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 583 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 584 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 585 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 586 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 587 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 588 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 589 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 590 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 591 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 592 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 593 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 594 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 595 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 596 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 597 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 598 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 599 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 600 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 601 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 602 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 603 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 604 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 605 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 606 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 607 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 608 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 609 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 610 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 611 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 612 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 613 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 614 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 615 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 616 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 617 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 618 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 619 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 620 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 621 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 622 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 623 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 624 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 625 CPU_L1OM_FLAGS, 0, 0 },
8a2c8fef 626 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 627 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 628 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 629 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 630 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 631 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 632 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 633 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 634 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 635 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 636 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 637 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 638 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 639 CPU_AMDFAM10_FLAGS, 0, 0 },
68339fdf 640 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1,
22109423 641 CPU_BDVER1_FLAGS, 0, 0 },
8a2c8fef 642 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 643 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 644 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 645 CPU_287_FLAGS, 0, 0 },
8a2c8fef 646 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 647 CPU_387_FLAGS, 0, 0 },
8a2c8fef 648 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 649 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 650 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 651 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 652 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 653 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 654 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 655 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 656 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 657 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 658 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 659 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 660 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 661 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 662 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 663 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 664 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 665 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 666 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 667 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 668 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 669 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 670 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 671 CPU_AVX_FLAGS, 0, 0 },
8a2c8fef 672 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 673 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 674 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 675 CPU_VMX_FLAGS, 0, 0 },
8a2c8fef 676 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 677 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 678 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 679 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 680 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 681 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 682 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 683 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 684 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 685 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 686 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 687 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 688 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 689 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 690 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 691 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 692 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 693 CPU_F16C_FLAGS, 0, 0 },
8a2c8fef 694 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 695 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 696 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 697 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 698 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 699 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 700 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 701 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 702 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 703 CPU_MOVBE_FLAGS, 0, 0 },
8a2c8fef 704 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 705 CPU_EPT_FLAGS, 0, 0 },
8a2c8fef 706 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 707 CPU_CLFLUSH_FLAGS, 0, 0 },
708 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
709 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 710 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 711 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 712 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 713 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 714 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 715 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 716 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 717 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 718 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 719 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 720 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 721 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 722 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 723 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 724 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 725 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 726 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 727 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 728 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
729 CPU_BMI_FLAGS, 0, 0 },
e413e4e9
AM		 730};
731
704209c0 732#ifdef I386COFF
a6c24e68
NC		 733/* Like s_lcomm_internal in gas/read.c but the alignment string
734 is allowed to be optional. */
735
736static symbolS *
737pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
738{
739 addressT align = 0;
740
741 SKIP_WHITESPACE ();
742
7ab9ffdd 743 if (needs_align
a6c24e68
NC		 744 && *input_line_pointer == ',')
745 {
746 align = parse_align (needs_align - 1);
7ab9ffdd 747
a6c24e68
NC		 748 if (align == (addressT) -1)
749 return NULL;
750 }
751 else
752 {
753 if (size >= 8)
754 align = 3;
755 else if (size >= 4)
756 align = 2;
757 else if (size >= 2)
758 align = 1;
759 else
760 align = 0;
761 }
762
763 bss_alloc (symbolP, size, align);
764 return symbolP;
765}
766
704209c0 767static void
a6c24e68
NC		 768pe_lcomm (int needs_align)
769{
770 s_comm_internal (needs_align * 2, pe_lcomm_internal);
771}
704209c0 772#endif
a6c24e68 773
29b0f896
AM		 774const pseudo_typeS md_pseudo_table[] =
775{
776#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
777 {"align", s_align_bytes, 0},
778#else
779 {"align", s_align_ptwo, 0},
780#endif
781 {"arch", set_cpu_arch, 0},
782#ifndef I386COFF
783 {"bss", s_bss, 0},
a6c24e68
NC		 784#else
785 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 786#endif
787 {"ffloat", float_cons, 'f'},
788 {"dfloat", float_cons, 'd'},
789 {"tfloat", float_cons, 'x'},
790 {"value", cons, 2},
d182319b 791 {"slong", signed_cons, 4},
29b0f896
AM		 792 {"noopt", s_ignore, 0},
793 {"optim", s_ignore, 0},
794 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
795 {"code16", set_code_flag, CODE_16BIT},
796 {"code32", set_code_flag, CODE_32BIT},
797 {"code64", set_code_flag, CODE_64BIT},
798 {"intel_syntax", set_intel_syntax, 1},
799 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 800 {"intel_mnemonic", set_intel_mnemonic, 1},
801 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 802 {"allow_index_reg", set_allow_index_reg, 1},
803 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 804 {"sse_check", set_sse_check, 0},
3b22753a
L		 805#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
806 {"largecomm", handle_large_common, 0},
07a53e5c 807#else
e3bb37b5 808 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 809 {"loc", dwarf2_directive_loc, 0},
810 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 811#endif
6482c264
NC		 812#ifdef TE_PE
813 {"secrel32", pe_directive_secrel, 0},
814#endif
29b0f896
AM		 815 {0, 0, 0}
816};
817
818/* For interface with expression (). */
819extern char *input_line_pointer;
820
821/* Hash table for instruction mnemonic lookup. */
822static struct hash_control *op_hash;
823
824/* Hash table for register lookup. */
825static struct hash_control *reg_hash;
826\f
252b5132 827void
e3bb37b5 828i386_align_code (fragS *fragP, int count)
252b5132 829{
ce8a8b2f
AM		 830 /* Various efficient no-op patterns for aligning code labels.
831 Note: Don't try to assemble the instructions in the comments.
832 0L and 0w are not legal. */
252b5132
RH		 833 static const char f32_1[] =
834 {0x90}; /* nop */
835 static const char f32_2[] =
ccc9c027 836 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 837 static const char f32_3[] =
838 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
839 static const char f32_4[] =
840 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
841 static const char f32_5[] =
842 {0x90, /* nop */
843 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
844 static const char f32_6[] =
845 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
846 static const char f32_7[] =
847 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
848 static const char f32_8[] =
849 {0x90, /* nop */
850 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
851 static const char f32_9[] =
852 {0x89,0xf6, /* movl %esi,%esi */
853 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
854 static const char f32_10[] =
855 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
856 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
857 static const char f32_11[] =
858 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
859 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
860 static const char f32_12[] =
861 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
862 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
863 static const char f32_13[] =
864 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
865 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
866 static const char f32_14[] =
867 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
868 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 869 static const char f16_3[] =
870 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 871 static const char f16_4[] =
872 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
873 static const char f16_5[] =
874 {0x90, /* nop */
875 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
876 static const char f16_6[] =
877 {0x89,0xf6, /* mov %si,%si */
878 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
879 static const char f16_7[] =
880 {0x8d,0x74,0x00, /* lea 0(%si),%si */
881 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
882 static const char f16_8[] =
883 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
884 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 885 static const char jump_31[] =
886 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
887 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
888 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
889 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 890 static const char *const f32_patt[] = {
891 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 892 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 893 };
894 static const char *const f16_patt[] = {
76bc74dc 895 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 896 };
ccc9c027
L		 897 /* nopl (%[re]ax) */
898 static const char alt_3[] =
899 {0x0f,0x1f,0x00};
900 /* nopl 0(%[re]ax) */
901 static const char alt_4[] =
902 {0x0f,0x1f,0x40,0x00};
903 /* nopl 0(%[re]ax,%[re]ax,1) */
904 static const char alt_5[] =
905 {0x0f,0x1f,0x44,0x00,0x00};
906 /* nopw 0(%[re]ax,%[re]ax,1) */
907 static const char alt_6[] =
908 {0x66,0x0f,0x1f,0x44,0x00,0x00};
909 /* nopl 0L(%[re]ax) */
910 static const char alt_7[] =
911 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
912 /* nopl 0L(%[re]ax,%[re]ax,1) */
913 static const char alt_8[] =
914 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
915 /* nopw 0L(%[re]ax,%[re]ax,1) */
916 static const char alt_9[] =
917 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
918 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
919 static const char alt_10[] =
920 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
921 /* data16
922 nopw %cs:0L(%[re]ax,%[re]ax,1) */
923 static const char alt_long_11[] =
924 {0x66,
925 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
926 /* data16
927 data16
928 nopw %cs:0L(%[re]ax,%[re]ax,1) */
929 static const char alt_long_12[] =
930 {0x66,
931 0x66,
932 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
933 /* data16
934 data16
935 data16
936 nopw %cs:0L(%[re]ax,%[re]ax,1) */
937 static const char alt_long_13[] =
938 {0x66,
939 0x66,
940 0x66,
941 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
942 /* data16
943 data16
944 data16
945 data16
946 nopw %cs:0L(%[re]ax,%[re]ax,1) */
947 static const char alt_long_14[] =
948 {0x66,
949 0x66,
950 0x66,
951 0x66,
952 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
953 /* data16
954 data16
955 data16
956 data16
957 data16
958 nopw %cs:0L(%[re]ax,%[re]ax,1) */
959 static const char alt_long_15[] =
960 {0x66,
961 0x66,
962 0x66,
963 0x66,
964 0x66,
965 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
966 /* nopl 0(%[re]ax,%[re]ax,1)
967 nopw 0(%[re]ax,%[re]ax,1) */
968 static const char alt_short_11[] =
969 {0x0f,0x1f,0x44,0x00,0x00,
970 0x66,0x0f,0x1f,0x44,0x00,0x00};
971 /* nopw 0(%[re]ax,%[re]ax,1)
972 nopw 0(%[re]ax,%[re]ax,1) */
973 static const char alt_short_12[] =
974 {0x66,0x0f,0x1f,0x44,0x00,0x00,
975 0x66,0x0f,0x1f,0x44,0x00,0x00};
976 /* nopw 0(%[re]ax,%[re]ax,1)
977 nopl 0L(%[re]ax) */
978 static const char alt_short_13[] =
979 {0x66,0x0f,0x1f,0x44,0x00,0x00,
980 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
981 /* nopl 0L(%[re]ax)
982 nopl 0L(%[re]ax) */
983 static const char alt_short_14[] =
984 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
985 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
986 /* nopl 0L(%[re]ax)
987 nopl 0L(%[re]ax,%[re]ax,1) */
988 static const char alt_short_15[] =
989 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
990 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
991 static const char *const alt_short_patt[] = {
992 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
993 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
994 alt_short_14, alt_short_15
995 };
996 static const char *const alt_long_patt[] = {
997 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
998 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
999 alt_long_14, alt_long_15
1000 };
252b5132 1001
76bc74dc
L		 1002 /* Only align for at least a positive non-zero boundary. */
1003 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1004 return;
3e73aa7c 1005
ccc9c027
L		 1006 /* We need to decide which NOP sequence to use for 32bit and
1007 64bit. When -mtune= is used:
4eed87de 1008
76bc74dc
L		 1009 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1010 PROCESSOR_GENERIC32, f32_patt will be used.
1011 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1012 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1013 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1014 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
68339fdf 1015 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
69dd9865 1016 will be used.
ccc9c027 1017
76bc74dc 1018 When -mtune= isn't used, alt_long_patt will be used if
22109423 1019 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1020 be used.
ccc9c027
L		 1021
1022 When -march= or .arch is used, we can't use anything beyond
1023 cpu_arch_isa_flags. */
1024
1025 if (flag_code == CODE_16BIT)
1026 {
ccc9c027 1027 if (count > 8)
33fef721 1028 {
76bc74dc
L		 1029 memcpy (fragP->fr_literal + fragP->fr_fix,
1030 jump_31, count);
1031 /* Adjust jump offset. */
1032 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1033 }
76bc74dc
L		 1034 else
1035 memcpy (fragP->fr_literal + fragP->fr_fix,
1036 f16_patt[count - 1], count);
252b5132 1037 }
33fef721 1038 else
ccc9c027
L		 1039 {
1040 const char *const *patt = NULL;
1041
fbf3f584 1042 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1043 {
1044 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1045 switch (cpu_arch_tune)
1046 {
1047 case PROCESSOR_UNKNOWN:
1048 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1049 optimize with nops. */
1050 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1051 patt = alt_long_patt;
ccc9c027
L		 1052 else
1053 patt = f32_patt;
1054 break;
ccc9c027
L		 1055 case PROCESSOR_PENTIUMPRO:
1056 case PROCESSOR_PENTIUM4:
1057 case PROCESSOR_NOCONA:
ef05d495 1058 case PROCESSOR_CORE:
76bc74dc 1059 case PROCESSOR_CORE2:
bd5295b2 1060 case PROCESSOR_COREI7:
3632d14b 1061 case PROCESSOR_L1OM:
76bc74dc
L		 1062 case PROCESSOR_GENERIC64:
1063 patt = alt_long_patt;
1064 break;
ccc9c027
L		 1065 case PROCESSOR_K6:
1066 case PROCESSOR_ATHLON:
1067 case PROCESSOR_K8:
4eed87de 1068 case PROCESSOR_AMDFAM10:
68339fdf 1069 case PROCESSOR_BDVER1:
ccc9c027
L		 1070 patt = alt_short_patt;
1071 break;
76bc74dc 1072 case PROCESSOR_I386:
ccc9c027
L		 1073 case PROCESSOR_I486:
1074 case PROCESSOR_PENTIUM:
1075 case PROCESSOR_GENERIC32:
1076 patt = f32_patt;
1077 break;
4eed87de 1078 }
ccc9c027
L		 1079 }
1080 else
1081 {
fbf3f584 1082 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1083 {
1084 case PROCESSOR_UNKNOWN:
e6a14101 1085 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1086 PROCESSOR_UNKNOWN. */
1087 abort ();
1088 break;
1089
76bc74dc 1090 case PROCESSOR_I386:
ccc9c027
L		 1091 case PROCESSOR_I486:
1092 case PROCESSOR_PENTIUM:
ccc9c027
L		 1093 case PROCESSOR_K6:
1094 case PROCESSOR_ATHLON:
1095 case PROCESSOR_K8:
4eed87de 1096 case PROCESSOR_AMDFAM10:
68339fdf 1097 case PROCESSOR_BDVER1:
ccc9c027
L		 1098 case PROCESSOR_GENERIC32:
1099 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1100 with nops. */
1101 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1102 patt = alt_short_patt;
1103 else
1104 patt = f32_patt;
1105 break;
76bc74dc
L		 1106 case PROCESSOR_PENTIUMPRO:
1107 case PROCESSOR_PENTIUM4:
1108 case PROCESSOR_NOCONA:
1109 case PROCESSOR_CORE:
ef05d495 1110 case PROCESSOR_CORE2:
bd5295b2 1111 case PROCESSOR_COREI7:
3632d14b 1112 case PROCESSOR_L1OM:
22109423 1113 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1114 patt = alt_long_patt;
1115 else
1116 patt = f32_patt;
1117 break;
1118 case PROCESSOR_GENERIC64:
76bc74dc 1119 patt = alt_long_patt;
ccc9c027 1120 break;
4eed87de 1121 }
ccc9c027
L		 1122 }
1123
76bc74dc
L		 1124 if (patt == f32_patt)
1125 {
1126 /* If the padding is less than 15 bytes, we use the normal
1127 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1128 its offset. */
1129 int limit;
76ba9986 1130
711eedef
L		 1131 /* For 64bit, the limit is 3 bytes. */
1132 if (flag_code == CODE_64BIT
1133 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1134 limit = 3;
1135 else
1136 limit = 15;
1137 if (count < limit)
76bc74dc
L		 1138 memcpy (fragP->fr_literal + fragP->fr_fix,
1139 patt[count - 1], count);
1140 else
1141 {
1142 memcpy (fragP->fr_literal + fragP->fr_fix,
1143 jump_31, count);
1144 /* Adjust jump offset. */
1145 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1146 }
1147 }
1148 else
1149 {
1150 /* Maximum length of an instruction is 15 byte. If the
1151 padding is greater than 15 bytes and we don't use jump,
1152 we have to break it into smaller pieces. */
1153 int padding = count;
1154 while (padding > 15)
1155 {
1156 padding -= 15;
1157 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1158 patt [14], 15);
1159 }
1160
1161 if (padding)
1162 memcpy (fragP->fr_literal + fragP->fr_fix,
1163 patt [padding - 1], padding);
1164 }
ccc9c027 1165 }
33fef721 1166 fragP->fr_var = count;
252b5132
RH		 1167}
1168
c6fb90c8 1169static INLINE int
0dfbf9d7 1170operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1171{
0dfbf9d7 1172 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1173 {
1174 case 3:
0dfbf9d7 1175 if (x->array[2])
c6fb90c8
L		 1176 return 0;
1177 case 2:
0dfbf9d7 1178 if (x->array[1])
c6fb90c8
L		 1179 return 0;
1180 case 1:
0dfbf9d7 1181 return !x->array[0];
c6fb90c8
L		 1182 default:
1183 abort ();
1184 }
40fb9820
L		 1185}
1186
c6fb90c8 1187static INLINE void
0dfbf9d7 1188operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1189{
0dfbf9d7 1190 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1191 {
1192 case 3:
0dfbf9d7 1193 x->array[2] = v;
c6fb90c8 1194 case 2:
0dfbf9d7 1195 x->array[1] = v;
c6fb90c8 1196 case 1:
0dfbf9d7 1197 x->array[0] = v;
c6fb90c8
L		 1198 break;
1199 default:
1200 abort ();
1201 }
1202}
40fb9820 1203
c6fb90c8 1204static INLINE int
0dfbf9d7
L		 1205operand_type_equal (const union i386_operand_type *x,
1206 const union i386_operand_type *y)
c6fb90c8 1207{
0dfbf9d7 1208 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1209 {
1210 case 3:
0dfbf9d7 1211 if (x->array[2] != y->array[2])
c6fb90c8
L		 1212 return 0;
1213 case 2:
0dfbf9d7 1214 if (x->array[1] != y->array[1])
c6fb90c8
L		 1215 return 0;
1216 case 1:
0dfbf9d7 1217 return x->array[0] == y->array[0];
c6fb90c8
L		 1218 break;
1219 default:
1220 abort ();
1221 }
1222}
40fb9820 1223
0dfbf9d7
L		 1224static INLINE int
1225cpu_flags_all_zero (const union i386_cpu_flags *x)
1226{
1227 switch (ARRAY_SIZE(x->array))
1228 {
1229 case 3:
1230 if (x->array[2])
1231 return 0;
1232 case 2:
1233 if (x->array[1])
1234 return 0;
1235 case 1:
1236 return !x->array[0];
1237 default:
1238 abort ();
1239 }
1240}
1241
1242static INLINE void
1243cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1244{
1245 switch (ARRAY_SIZE(x->array))
1246 {
1247 case 3:
1248 x->array[2] = v;
1249 case 2:
1250 x->array[1] = v;
1251 case 1:
1252 x->array[0] = v;
1253 break;
1254 default:
1255 abort ();
1256 }
1257}
1258
1259static INLINE int
1260cpu_flags_equal (const union i386_cpu_flags *x,
1261 const union i386_cpu_flags *y)
1262{
1263 switch (ARRAY_SIZE(x->array))
1264 {
1265 case 3:
1266 if (x->array[2] != y->array[2])
1267 return 0;
1268 case 2:
1269 if (x->array[1] != y->array[1])
1270 return 0;
1271 case 1:
1272 return x->array[0] == y->array[0];
1273 break;
1274 default:
1275 abort ();
1276 }
1277}
c6fb90c8
L		 1278
1279static INLINE int
1280cpu_flags_check_cpu64 (i386_cpu_flags f)
1281{
1282 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1283 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1284}
1285
c6fb90c8
L		 1286static INLINE i386_cpu_flags
1287cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1288{
c6fb90c8
L		 1289 switch (ARRAY_SIZE (x.array))
1290 {
1291 case 3:
1292 x.array [2] &= y.array [2];
1293 case 2:
1294 x.array [1] &= y.array [1];
1295 case 1:
1296 x.array [0] &= y.array [0];
1297 break;
1298 default:
1299 abort ();
1300 }
1301 return x;
1302}
40fb9820 1303
c6fb90c8
L		 1304static INLINE i386_cpu_flags
1305cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1306{
c6fb90c8 1307 switch (ARRAY_SIZE (x.array))
40fb9820 1308 {
c6fb90c8
L		 1309 case 3:
1310 x.array [2] |= y.array [2];
1311 case 2:
1312 x.array [1] |= y.array [1];
1313 case 1:
1314 x.array [0] |= y.array [0];
40fb9820
L		 1315 break;
1316 default:
1317 abort ();
1318 }
40fb9820
L		 1319 return x;
1320}
1321
309d3373
JB		 1322static INLINE i386_cpu_flags
1323cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1324{
1325 switch (ARRAY_SIZE (x.array))
1326 {
1327 case 3:
1328 x.array [2] &= ~y.array [2];
1329 case 2:
1330 x.array [1] &= ~y.array [1];
1331 case 1:
1332 x.array [0] &= ~y.array [0];
1333 break;
1334 default:
1335 abort ();
1336 }
1337 return x;
1338}
1339
c0f3af97
L		 1340#define CPU_FLAGS_ARCH_MATCH 0x1
1341#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1342#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1343#define CPU_FLAGS_PCLMUL_MATCH 0x8
1344#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1345
a5ff0eb2 1346#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1347 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1348 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1349#define CPU_FLAGS_PERFECT_MATCH \
1350 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1351
1352/* Return CPU flags match bits. */
3629bb00 1353
40fb9820 1354static int
d3ce72d0 1355cpu_flags_match (const insn_template *t)
40fb9820 1356{
c0f3af97
L		 1357 i386_cpu_flags x = t->cpu_flags;
1358 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1359
1360 x.bitfield.cpu64 = 0;
1361 x.bitfield.cpuno64 = 0;
1362
0dfbf9d7 1363 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1364 {
1365 /* This instruction is available on all archs. */
1366 match |= CPU_FLAGS_32BIT_MATCH;
1367 }
3629bb00
L		 1368 else
1369 {
c0f3af97 1370 /* This instruction is available only on some archs. */
3629bb00
L		 1371 i386_cpu_flags cpu = cpu_arch_flags;
1372
1373 cpu.bitfield.cpu64 = 0;
1374 cpu.bitfield.cpuno64 = 0;
1375 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1376 if (!cpu_flags_all_zero (&cpu))
1377 {
a5ff0eb2
L		 1378 if (x.bitfield.cpuavx)
1379 {
ce2f5b3c 1380 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1381 if (cpu.bitfield.cpuavx)
1382 {
1383 /* Check SSE2AVX. */
1384 if (!t->opcode_modifier.sse2avx|| sse2avx)
1385 {
1386 match |= (CPU_FLAGS_ARCH_MATCH
1387 | CPU_FLAGS_AVX_MATCH);
1388 /* Check AES. */
1389 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1390 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1391 /* Check PCLMUL. */
1392 if (!x.bitfield.cpupclmul
1393 || cpu.bitfield.cpupclmul)
1394 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1395 }
1396 }
1397 else
1398 match |= CPU_FLAGS_ARCH_MATCH;
1399 }
1400 else
c0f3af97
L		 1401 match |= CPU_FLAGS_32BIT_MATCH;
1402 }
3629bb00 1403 }
c0f3af97 1404 return match;
40fb9820
L		 1405}
1406
c6fb90c8
L		 1407static INLINE i386_operand_type
1408operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1409{
c6fb90c8
L		 1410 switch (ARRAY_SIZE (x.array))
1411 {
1412 case 3:
1413 x.array [2] &= y.array [2];
1414 case 2:
1415 x.array [1] &= y.array [1];
1416 case 1:
1417 x.array [0] &= y.array [0];
1418 break;
1419 default:
1420 abort ();
1421 }
1422 return x;
40fb9820
L		 1423}
1424
c6fb90c8
L		 1425static INLINE i386_operand_type
1426operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1427{
c6fb90c8 1428 switch (ARRAY_SIZE (x.array))
40fb9820 1429 {
c6fb90c8
L		 1430 case 3:
1431 x.array [2] |= y.array [2];
1432 case 2:
1433 x.array [1] |= y.array [1];
1434 case 1:
1435 x.array [0] |= y.array [0];
40fb9820
L		 1436 break;
1437 default:
1438 abort ();
1439 }
c6fb90c8
L		 1440 return x;
1441}
40fb9820 1442
c6fb90c8
L		 1443static INLINE i386_operand_type
1444operand_type_xor (i386_operand_type x, i386_operand_type y)
1445{
1446 switch (ARRAY_SIZE (x.array))
1447 {
1448 case 3:
1449 x.array [2] ^= y.array [2];
1450 case 2:
1451 x.array [1] ^= y.array [1];
1452 case 1:
1453 x.array [0] ^= y.array [0];
1454 break;
1455 default:
1456 abort ();
1457 }
40fb9820
L		 1458 return x;
1459}
1460
1461static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1462static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1463static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1464static const i386_operand_type inoutportreg
1465 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1466static const i386_operand_type reg16_inoutportreg
1467 = OPERAND_TYPE_REG16_INOUTPORTREG;
1468static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1469static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1470static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1471static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1472static const i386_operand_type anydisp
1473 = OPERAND_TYPE_ANYDISP;
40fb9820 1474static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1475static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1476static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1477static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1478static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1479static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1480static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1481static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1482static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1483static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1484static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1485static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1486
1487enum operand_type
1488{
1489 reg,
40fb9820
L		 1490 imm,
1491 disp,
1492 anymem
1493};
1494
c6fb90c8 1495static INLINE int
40fb9820
L		 1496operand_type_check (i386_operand_type t, enum operand_type c)
1497{
1498 switch (c)
1499 {
1500 case reg:
1501 return (t.bitfield.reg8
1502 || t.bitfield.reg16
1503 || t.bitfield.reg32
1504 || t.bitfield.reg64);
1505
40fb9820
L		 1506 case imm:
1507 return (t.bitfield.imm8
1508 || t.bitfield.imm8s
1509 || t.bitfield.imm16
1510 || t.bitfield.imm32
1511 || t.bitfield.imm32s
1512 || t.bitfield.imm64);
1513
1514 case disp:
1515 return (t.bitfield.disp8
1516 || t.bitfield.disp16
1517 || t.bitfield.disp32
1518 || t.bitfield.disp32s
1519 || t.bitfield.disp64);
1520
1521 case anymem:
1522 return (t.bitfield.disp8
1523 || t.bitfield.disp16
1524 || t.bitfield.disp32
1525 || t.bitfield.disp32s
1526 || t.bitfield.disp64
1527 || t.bitfield.baseindex);
1528
1529 default:
1530 abort ();
1531 }
2cfe26b6
AM		 1532
1533 return 0;
40fb9820
L		 1534}
1535
5c07affc
L		 1536/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1537 operand J for instruction template T. */
1538
1539static INLINE int
d3ce72d0 1540match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1541{
1542 return !((i.types[j].bitfield.byte
1543 && !t->operand_types[j].bitfield.byte)
1544 || (i.types[j].bitfield.word
1545 && !t->operand_types[j].bitfield.word)
1546 || (i.types[j].bitfield.dword
1547 && !t->operand_types[j].bitfield.dword)
1548 || (i.types[j].bitfield.qword
1549 && !t->operand_types[j].bitfield.qword));
1550}
1551
1552/* Return 1 if there is no conflict in any size on operand J for
1553 instruction template T. */
1554
1555static INLINE int
d3ce72d0 1556match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1557{
1558 return (match_reg_size (t, j)
1559 && !((i.types[j].bitfield.unspecified
1560 && !t->operand_types[j].bitfield.unspecified)
1561 || (i.types[j].bitfield.fword
1562 && !t->operand_types[j].bitfield.fword)
1563 || (i.types[j].bitfield.tbyte
1564 && !t->operand_types[j].bitfield.tbyte)
1565 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1566 && !t->operand_types[j].bitfield.xmmword)
1567 || (i.types[j].bitfield.ymmword
1568 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1569}
1570
1571/* Return 1 if there is no size conflict on any operands for
1572 instruction template T. */
1573
1574static INLINE int
d3ce72d0 1575operand_size_match (const insn_template *t)
5c07affc
L		 1576{
1577 unsigned int j;
1578 int match = 1;
1579
1580 /* Don't check jump instructions. */
1581 if (t->opcode_modifier.jump
1582 || t->opcode_modifier.jumpbyte
1583 || t->opcode_modifier.jumpdword
1584 || t->opcode_modifier.jumpintersegment)
1585 return match;
1586
1587 /* Check memory and accumulator operand size. */
1588 for (j = 0; j < i.operands; j++)
1589 {
1590 if (t->operand_types[j].bitfield.anysize)
1591 continue;
1592
1593 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1594 {
1595 match = 0;
1596 break;
1597 }
1598
1599 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1600 {
1601 match = 0;
1602 break;
1603 }
1604 }
1605
891edac4 1606 if (match)
5c07affc 1607 return match;
891edac4
L		 1608 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1609 {
1610mismatch:
86e026a4 1611 i.error = operand_size_mismatch;
891edac4
L		 1612 return 0;
1613 }
5c07affc
L		 1614
1615 /* Check reverse. */
9c2799c2 1616 gas_assert (i.operands == 2);
5c07affc
L		 1617
1618 match = 1;
1619 for (j = 0; j < 2; j++)
1620 {
1621 if (t->operand_types[j].bitfield.acc
1622 && !match_reg_size (t, j ? 0 : 1))
891edac4 1623 goto mismatch;
5c07affc
L		 1624
1625 if (i.types[j].bitfield.mem
1626 && !match_mem_size (t, j ? 0 : 1))
891edac4 1627 goto mismatch;
5c07affc
L		 1628 }
1629
1630 return match;
1631}
1632
c6fb90c8 1633static INLINE int
40fb9820
L		 1634operand_type_match (i386_operand_type overlap,
1635 i386_operand_type given)
1636{
1637 i386_operand_type temp = overlap;
1638
1639 temp.bitfield.jumpabsolute = 0;
7d5e4556 1640 temp.bitfield.unspecified = 0;
5c07affc
L		 1641 temp.bitfield.byte = 0;
1642 temp.bitfield.word = 0;
1643 temp.bitfield.dword = 0;
1644 temp.bitfield.fword = 0;
1645 temp.bitfield.qword = 0;
1646 temp.bitfield.tbyte = 0;
1647 temp.bitfield.xmmword = 0;
c0f3af97 1648 temp.bitfield.ymmword = 0;
0dfbf9d7 1649 if (operand_type_all_zero (&temp))
891edac4 1650 goto mismatch;
40fb9820 1651
891edac4
L		 1652 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1653 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1654 return 1;
1655
1656mismatch:
a65babc9 1657 i.error = operand_type_mismatch;
891edac4 1658 return 0;
40fb9820
L		 1659}
1660
7d5e4556 1661/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1662 unless the expected operand type register overlap is null.
1663 Note that Acc in a template matches every size of reg. */
1664
c6fb90c8 1665static INLINE int
40fb9820
L		 1666operand_type_register_match (i386_operand_type m0,
1667 i386_operand_type g0,
1668 i386_operand_type t0,
1669 i386_operand_type m1,
1670 i386_operand_type g1,
1671 i386_operand_type t1)
1672{
1673 if (!operand_type_check (g0, reg))
1674 return 1;
1675
1676 if (!operand_type_check (g1, reg))
1677 return 1;
1678
1679 if (g0.bitfield.reg8 == g1.bitfield.reg8
1680 && g0.bitfield.reg16 == g1.bitfield.reg16
1681 && g0.bitfield.reg32 == g1.bitfield.reg32
1682 && g0.bitfield.reg64 == g1.bitfield.reg64)
1683 return 1;
1684
1685 if (m0.bitfield.acc)
1686 {
1687 t0.bitfield.reg8 = 1;
1688 t0.bitfield.reg16 = 1;
1689 t0.bitfield.reg32 = 1;
1690 t0.bitfield.reg64 = 1;
1691 }
1692
1693 if (m1.bitfield.acc)
1694 {
1695 t1.bitfield.reg8 = 1;
1696 t1.bitfield.reg16 = 1;
1697 t1.bitfield.reg32 = 1;
1698 t1.bitfield.reg64 = 1;
1699 }
1700
891edac4
L		 1701 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1702 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1703 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1704 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1705 return 1;
1706
a65babc9 1707 i.error = register_type_mismatch;
891edac4
L		 1708
1709 return 0;
40fb9820
L		 1710}
1711
252b5132 1712static INLINE unsigned int
40fb9820 1713mode_from_disp_size (i386_operand_type t)
252b5132 1714{
40fb9820
L		 1715 if (t.bitfield.disp8)
1716 return 1;
1717 else if (t.bitfield.disp16
1718 || t.bitfield.disp32
1719 || t.bitfield.disp32s)
1720 return 2;
1721 else
1722 return 0;
252b5132
RH		 1723}
1724
1725static INLINE int
e3bb37b5 1726fits_in_signed_byte (offsetT num)
252b5132
RH		 1727{
1728 return (num >= -128) && (num <= 127);
47926f60 1729}
252b5132
RH		 1730
1731static INLINE int
e3bb37b5 1732fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1733{
1734 return (num & 0xff) == num;
47926f60 1735}
252b5132
RH		 1736
1737static INLINE int
e3bb37b5 1738fits_in_unsigned_word (offsetT num)
252b5132
RH		 1739{
1740 return (num & 0xffff) == num;
47926f60 1741}
252b5132
RH		 1742
1743static INLINE int
e3bb37b5 1744fits_in_signed_word (offsetT num)
252b5132
RH		 1745{
1746 return (-32768 <= num) && (num <= 32767);
47926f60 1747}
2a962e6d 1748
3e73aa7c 1749static INLINE int
e3bb37b5 1750fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1751{
1752#ifndef BFD64
1753 return 1;
1754#else
1755 return (!(((offsetT) -1 << 31) & num)
1756 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1757#endif
1758} /* fits_in_signed_long() */
2a962e6d 1759
3e73aa7c 1760static INLINE int
e3bb37b5 1761fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1762{
1763#ifndef BFD64
1764 return 1;
1765#else
1766 return (num & (((offsetT) 2 << 31) - 1)) == num;
1767#endif
1768} /* fits_in_unsigned_long() */
252b5132 1769
a683cc34
SP		 1770static INLINE int
1771fits_in_imm4 (offsetT num)
1772{
1773 return (num & 0xf) == num;
1774}
1775
40fb9820 1776static i386_operand_type
e3bb37b5 1777smallest_imm_type (offsetT num)
252b5132 1778{
40fb9820 1779 i386_operand_type t;
7ab9ffdd 1780
0dfbf9d7 1781 operand_type_set (&t, 0);
40fb9820
L		 1782 t.bitfield.imm64 = 1;
1783
1784 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1785 {
1786 /* This code is disabled on the 486 because all the Imm1 forms
1787 in the opcode table are slower on the i486. They're the
1788 versions with the implicitly specified single-position
1789 displacement, which has another syntax if you really want to
1790 use that form. */
40fb9820
L		 1791 t.bitfield.imm1 = 1;
1792 t.bitfield.imm8 = 1;
1793 t.bitfield.imm8s = 1;
1794 t.bitfield.imm16 = 1;
1795 t.bitfield.imm32 = 1;
1796 t.bitfield.imm32s = 1;
1797 }
1798 else if (fits_in_signed_byte (num))
1799 {
1800 t.bitfield.imm8 = 1;
1801 t.bitfield.imm8s = 1;
1802 t.bitfield.imm16 = 1;
1803 t.bitfield.imm32 = 1;
1804 t.bitfield.imm32s = 1;
1805 }
1806 else if (fits_in_unsigned_byte (num))
1807 {
1808 t.bitfield.imm8 = 1;
1809 t.bitfield.imm16 = 1;
1810 t.bitfield.imm32 = 1;
1811 t.bitfield.imm32s = 1;
1812 }
1813 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1814 {
1815 t.bitfield.imm16 = 1;
1816 t.bitfield.imm32 = 1;
1817 t.bitfield.imm32s = 1;
1818 }
1819 else if (fits_in_signed_long (num))
1820 {
1821 t.bitfield.imm32 = 1;
1822 t.bitfield.imm32s = 1;
1823 }
1824 else if (fits_in_unsigned_long (num))
1825 t.bitfield.imm32 = 1;
1826
1827 return t;
47926f60 1828}
252b5132 1829
847f7ad4 1830static offsetT
e3bb37b5 1831offset_in_range (offsetT val, int size)
847f7ad4 1832{
508866be 1833 addressT mask;
ba2adb93 1834
847f7ad4
AM		 1835 switch (size)
1836 {
508866be
L		 1837 case 1: mask = ((addressT) 1 << 8) - 1; break;
1838 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1839 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1840#ifdef BFD64
1841 case 8: mask = ((addressT) 2 << 63) - 1; break;
1842#endif
47926f60 1843 default: abort ();
847f7ad4
AM		 1844 }
1845
9de868bf
L		 1846#ifdef BFD64
1847 /* If BFD64, sign extend val for 32bit address mode. */
1848 if (flag_code != CODE_64BIT
1849 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1850 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1851 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1852#endif
ba2adb93 1853
47926f60 1854 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1855 {
1856 char buf1[40], buf2[40];
1857
1858 sprint_value (buf1, val);
1859 sprint_value (buf2, val & mask);
1860 as_warn (_("%s shortened to %s"), buf1, buf2);
1861 }
1862 return val & mask;
1863}
1864
c32fa91d
L		 1865enum PREFIX_GROUP
1866{
1867 PREFIX_EXIST = 0,
1868 PREFIX_LOCK,
1869 PREFIX_REP,
1870 PREFIX_OTHER
1871};
1872
1873/* Returns
1874 a. PREFIX_EXIST if attempting to add a prefix where one from the
1875 same class already exists.
1876 b. PREFIX_LOCK if lock prefix is added.
1877 c. PREFIX_REP if rep/repne prefix is added.
1878 d. PREFIX_OTHER if other prefix is added.
1879 */
1880
1881static enum PREFIX_GROUP
e3bb37b5 1882add_prefix (unsigned int prefix)
252b5132 1883{
c32fa91d 1884 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1885 unsigned int q;
252b5132 1886
29b0f896
AM		 1887 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1888 && flag_code == CODE_64BIT)
b1905489 1889 {
161a04f6
L		 1890 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1891 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1892 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1893 ret = PREFIX_EXIST;
b1905489
JB		 1894 q = REX_PREFIX;
1895 }
3e73aa7c 1896 else
b1905489
JB		 1897 {
1898 switch (prefix)
1899 {
1900 default:
1901 abort ();
1902
1903 case CS_PREFIX_OPCODE:
1904 case DS_PREFIX_OPCODE:
1905 case ES_PREFIX_OPCODE:
1906 case FS_PREFIX_OPCODE:
1907 case GS_PREFIX_OPCODE:
1908 case SS_PREFIX_OPCODE:
1909 q = SEG_PREFIX;
1910 break;
1911
1912 case REPNE_PREFIX_OPCODE:
1913 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1914 q = REP_PREFIX;
1915 ret = PREFIX_REP;
1916 break;
1917
b1905489 1918 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1919 q = LOCK_PREFIX;
1920 ret = PREFIX_LOCK;
b1905489
JB		 1921 break;
1922
1923 case FWAIT_OPCODE:
1924 q = WAIT_PREFIX;
1925 break;
1926
1927 case ADDR_PREFIX_OPCODE:
1928 q = ADDR_PREFIX;
1929 break;
1930
1931 case DATA_PREFIX_OPCODE:
1932 q = DATA_PREFIX;
1933 break;
1934 }
1935 if (i.prefix[q] != 0)
c32fa91d 1936 ret = PREFIX_EXIST;
b1905489 1937 }
252b5132 1938
b1905489 1939 if (ret)
252b5132 1940 {
b1905489
JB		 1941 if (!i.prefix[q])
1942 ++i.prefixes;
1943 i.prefix[q] |= prefix;
252b5132 1944 }
b1905489
JB		 1945 else
1946 as_bad (_("same type of prefix used twice"));
252b5132 1947
252b5132
RH		 1948 return ret;
1949}
1950
1951static void
78f12dd3 1952update_code_flag (int value, int check)
eecb386c 1953{
78f12dd3
L		 1954 PRINTF_LIKE ((*as_error));
1955
1e9cc1c2 1956 flag_code = (enum flag_code) value;
40fb9820
L		 1957 if (flag_code == CODE_64BIT)
1958 {
1959 cpu_arch_flags.bitfield.cpu64 = 1;
1960 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1961 }
1962 else
1963 {
1964 cpu_arch_flags.bitfield.cpu64 = 0;
1965 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1966 }
1967 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 1968 {
78f12dd3
L		 1969 if (check)
1970 as_error = as_fatal;
1971 else
1972 as_error = as_bad;
1973 (*as_error) (_("64bit mode not supported on `%s'."),
1974 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1975 }
40fb9820 1976 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 1977 {
78f12dd3
L		 1978 if (check)
1979 as_error = as_fatal;
1980 else
1981 as_error = as_bad;
1982 (*as_error) (_("32bit mode not supported on `%s'."),
1983 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1984 }
eecb386c
AM		 1985 stackop_size = '\0';
1986}
1987
78f12dd3
L		 1988static void
1989set_code_flag (int value)
1990{
1991 update_code_flag (value, 0);
1992}
1993
eecb386c 1994static void
e3bb37b5 1995set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1996{
1e9cc1c2 1997 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 1998 if (flag_code != CODE_16BIT)
1999 abort ();
2000 cpu_arch_flags.bitfield.cpu64 = 0;
2001 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2002 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2003}
2004
2005static void
e3bb37b5 2006set_intel_syntax (int syntax_flag)
252b5132
RH		 2007{
2008 /* Find out if register prefixing is specified. */
2009 int ask_naked_reg = 0;
2010
2011 SKIP_WHITESPACE ();
29b0f896 2012 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2013 {
2014 char *string = input_line_pointer;
2015 int e = get_symbol_end ();
2016
47926f60 2017 if (strcmp (string, "prefix") == 0)
252b5132 2018 ask_naked_reg = 1;
47926f60 2019 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2020 ask_naked_reg = -1;
2021 else
d0b47220 2022 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2023 *input_line_pointer = e;
2024 }
2025 demand_empty_rest_of_line ();
c3332e24 2026
252b5132
RH		 2027 intel_syntax = syntax_flag;
2028
2029 if (ask_naked_reg == 0)
f86103b7
AM		 2030 allow_naked_reg = (intel_syntax
2031 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2032 else
2033 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2034
ee86248c 2035 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2036
e4a3b5a4 2037 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2038 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2039 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2040}
2041
1efbbeb4
L		 2042static void
2043set_intel_mnemonic (int mnemonic_flag)
2044{
e1d4d893 2045 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2046}
2047
db51cc60
L		 2048static void
2049set_allow_index_reg (int flag)
2050{
2051 allow_index_reg = flag;
2052}
2053
cb19c032
L		 2054static void
2055set_sse_check (int dummy ATTRIBUTE_UNUSED)
2056{
2057 SKIP_WHITESPACE ();
2058
2059 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2060 {
2061 char *string = input_line_pointer;
2062 int e = get_symbol_end ();
2063
2064 if (strcmp (string, "none") == 0)
2065 sse_check = sse_check_none;
2066 else if (strcmp (string, "warning") == 0)
2067 sse_check = sse_check_warning;
2068 else if (strcmp (string, "error") == 0)
2069 sse_check = sse_check_error;
2070 else
2071 as_bad (_("bad argument to sse_check directive."));
2072 *input_line_pointer = e;
2073 }
2074 else
2075 as_bad (_("missing argument for sse_check directive"));
2076
2077 demand_empty_rest_of_line ();
2078}
2079
8a9036a4
L		 2080static void
2081check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2082 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2083{
2084#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2085 static const char *arch;
2086
2087 /* Intel LIOM is only supported on ELF. */
2088 if (!IS_ELF)
2089 return;
2090
2091 if (!arch)
2092 {
2093 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2094 use default_arch. */
2095 arch = cpu_arch_name;
2096 if (!arch)
2097 arch = default_arch;
2098 }
2099
3632d14b 2100 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2101 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2102 || new_flag.bitfield.cpul1om)
8a9036a4 2103 return;
76ba9986 2104
8a9036a4
L		 2105 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2106#endif
2107}
2108
e413e4e9 2109static void
e3bb37b5 2110set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2111{
47926f60 2112 SKIP_WHITESPACE ();
e413e4e9 2113
29b0f896 2114 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2115 {
2116 char *string = input_line_pointer;
2117 int e = get_symbol_end ();
91d6fa6a 2118 unsigned int j;
40fb9820 2119 i386_cpu_flags flags;
e413e4e9 2120
91d6fa6a 2121 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2122 {
91d6fa6a 2123 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2124 {
91d6fa6a 2125 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2126
5c6af06e
JB		 2127 if (*string != '.')
2128 {
91d6fa6a 2129 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2130 cpu_sub_arch_name = NULL;
91d6fa6a 2131 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2132 if (flag_code == CODE_64BIT)
2133 {
2134 cpu_arch_flags.bitfield.cpu64 = 1;
2135 cpu_arch_flags.bitfield.cpuno64 = 0;
2136 }
2137 else
2138 {
2139 cpu_arch_flags.bitfield.cpu64 = 0;
2140 cpu_arch_flags.bitfield.cpuno64 = 1;
2141 }
91d6fa6a
NC		 2142 cpu_arch_isa = cpu_arch[j].type;
2143 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2144 if (!cpu_arch_tune_set)
2145 {
2146 cpu_arch_tune = cpu_arch_isa;
2147 cpu_arch_tune_flags = cpu_arch_isa_flags;
2148 }
5c6af06e
JB		 2149 break;
2150 }
40fb9820 2151
22109423 2152 if (!cpu_arch[j].negated)
309d3373 2153 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2154 cpu_arch[j].flags);
309d3373
JB		 2155 else
2156 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2157 cpu_arch[j].flags);
0dfbf9d7 2158 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2159 {
6305a203
L		 2160 if (cpu_sub_arch_name)
2161 {
2162 char *name = cpu_sub_arch_name;
2163 cpu_sub_arch_name = concat (name,
91d6fa6a 2164 cpu_arch[j].name,
1bf57e9f 2165 (const char *) NULL);
6305a203
L		 2166 free (name);
2167 }
2168 else
91d6fa6a 2169 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2170 cpu_arch_flags = flags;
5c6af06e
JB		 2171 }
2172 *input_line_pointer = e;
2173 demand_empty_rest_of_line ();
2174 return;
e413e4e9
AM		 2175 }
2176 }
91d6fa6a 2177 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2178 as_bad (_("no such architecture: `%s'"), string);
2179
2180 *input_line_pointer = e;
2181 }
2182 else
2183 as_bad (_("missing cpu architecture"));
2184
fddf5b5b
AM		 2185 no_cond_jump_promotion = 0;
2186 if (*input_line_pointer == ','
29b0f896 2187 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2188 {
2189 char *string = ++input_line_pointer;
2190 int e = get_symbol_end ();
2191
2192 if (strcmp (string, "nojumps") == 0)
2193 no_cond_jump_promotion = 1;
2194 else if (strcmp (string, "jumps") == 0)
2195 ;
2196 else
2197 as_bad (_("no such architecture modifier: `%s'"), string);
2198
2199 *input_line_pointer = e;
2200 }
2201
e413e4e9
AM		 2202 demand_empty_rest_of_line ();
2203}
2204
8a9036a4
L		 2205enum bfd_architecture
2206i386_arch (void)
2207{
3632d14b 2208 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2209 {
2210 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2211 || flag_code != CODE_64BIT)
2212 as_fatal (_("Intel L1OM is 64bit ELF only"));
2213 return bfd_arch_l1om;
2214 }
2215 else
2216 return bfd_arch_i386;
2217}
2218
b9d79e03
JH		 2219unsigned long
2220i386_mach ()
2221{
351f65ca 2222 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2223 {
3632d14b 2224 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2225 {
351f65ca
L		 2226 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2227 || default_arch[6] != '\0')
8a9036a4
L		 2228 as_fatal (_("Intel L1OM is 64bit ELF only"));
2229 return bfd_mach_l1om;
2230 }
351f65ca 2231 else if (default_arch[6] == '\0')
8a9036a4 2232 return bfd_mach_x86_64;
351f65ca
L		 2233 else
2234 return bfd_mach_x64_32;
8a9036a4 2235 }
b9d79e03
JH		 2236 else if (!strcmp (default_arch, "i386"))
2237 return bfd_mach_i386_i386;
2238 else
2239 as_fatal (_("Unknown architecture"));
2240}
b9d79e03 2241\f
252b5132
RH		 2242void
2243md_begin ()
2244{
2245 const char *hash_err;
2246
47926f60 2247 /* Initialize op_hash hash table. */
252b5132
RH		 2248 op_hash = hash_new ();
2249
2250 {
d3ce72d0 2251 const insn_template *optab;
29b0f896 2252 templates *core_optab;
252b5132 2253
47926f60
KH		 2254 /* Setup for loop. */
2255 optab = i386_optab;
252b5132
RH		 2256 core_optab = (templates *) xmalloc (sizeof (templates));
2257 core_optab->start = optab;
2258
2259 while (1)
2260 {
2261 ++optab;
2262 if (optab->name == NULL
2263 || strcmp (optab->name, (optab - 1)->name) != 0)
2264 {
2265 /* different name --> ship out current template list;
47926f60 2266 add to hash table; & begin anew. */
252b5132
RH		 2267 core_optab->end = optab;
2268 hash_err = hash_insert (op_hash,
2269 (optab - 1)->name,
5a49b8ac 2270 (void *) core_optab);
252b5132
RH		 2271 if (hash_err)
2272 {
252b5132
RH		 2273 as_fatal (_("Internal Error: Can't hash %s: %s"),
2274 (optab - 1)->name,
2275 hash_err);
2276 }
2277 if (optab->name == NULL)
2278 break;
2279 core_optab = (templates *) xmalloc (sizeof (templates));
2280 core_optab->start = optab;
2281 }
2282 }
2283 }
2284
47926f60 2285 /* Initialize reg_hash hash table. */
252b5132
RH		 2286 reg_hash = hash_new ();
2287 {
29b0f896 2288 const reg_entry *regtab;
c3fe08fa 2289 unsigned int regtab_size = i386_regtab_size;
252b5132 2290
c3fe08fa 2291 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2292 {
5a49b8ac 2293 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2294 if (hash_err)
3e73aa7c
JH		 2295 as_fatal (_("Internal Error: Can't hash %s: %s"),
2296 regtab->reg_name,
2297 hash_err);
252b5132
RH		 2298 }
2299 }
2300
47926f60 2301 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2302 {
29b0f896
AM		 2303 int c;
2304 char *p;
252b5132
RH		 2305
2306 for (c = 0; c < 256; c++)
2307 {
3882b010 2308 if (ISDIGIT (c))
252b5132
RH		 2309 {
2310 digit_chars[c] = c;
2311 mnemonic_chars[c] = c;
2312 register_chars[c] = c;
2313 operand_chars[c] = c;
2314 }
3882b010 2315 else if (ISLOWER (c))
252b5132
RH		 2316 {
2317 mnemonic_chars[c] = c;
2318 register_chars[c] = c;
2319 operand_chars[c] = c;
2320 }
3882b010 2321 else if (ISUPPER (c))
252b5132 2322 {
3882b010 2323 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2324 register_chars[c] = mnemonic_chars[c];
2325 operand_chars[c] = c;
2326 }
2327
3882b010 2328 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2329 identifier_chars[c] = c;
2330 else if (c >= 128)
2331 {
2332 identifier_chars[c] = c;
2333 operand_chars[c] = c;
2334 }
2335 }
2336
2337#ifdef LEX_AT
2338 identifier_chars['@'] = '@';
32137342
NC		 2339#endif
2340#ifdef LEX_QM
2341 identifier_chars['?'] = '?';
2342 operand_chars['?'] = '?';
252b5132 2343#endif
252b5132 2344 digit_chars['-'] = '-';
c0f3af97 2345 mnemonic_chars['_'] = '_';
791fe849 2346 mnemonic_chars['-'] = '-';
0003779b 2347 mnemonic_chars['.'] = '.';
252b5132
RH		 2348 identifier_chars['_'] = '_';
2349 identifier_chars['.'] = '.';
2350
2351 for (p = operand_special_chars; *p != '\0'; p++)
2352 operand_chars[(unsigned char) *p] = *p;
2353 }
2354
2355#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2356 if (IS_ELF)
252b5132
RH		 2357 {
2358 record_alignment (text_section, 2);
2359 record_alignment (data_section, 2);
2360 record_alignment (bss_section, 2);
2361 }
2362#endif
a4447b93
RH		 2363
2364 if (flag_code == CODE_64BIT)
2365 {
2366 x86_dwarf2_return_column = 16;
2367 x86_cie_data_alignment = -8;
2368 }
2369 else
2370 {
2371 x86_dwarf2_return_column = 8;
2372 x86_cie_data_alignment = -4;
2373 }
252b5132
RH		 2374}
2375
2376void
e3bb37b5 2377i386_print_statistics (FILE *file)
252b5132
RH		 2378{
2379 hash_print_statistics (file, "i386 opcode", op_hash);
2380 hash_print_statistics (file, "i386 register", reg_hash);
2381}
2382\f
252b5132
RH		 2383#ifdef DEBUG386
2384
ce8a8b2f 2385/* Debugging routines for md_assemble. */
d3ce72d0 2386static void pte (insn_template *);
40fb9820 2387static void pt (i386_operand_type);
e3bb37b5
L		 2388static void pe (expressionS *);
2389static void ps (symbolS *);
252b5132
RH		 2390
2391static void
e3bb37b5 2392pi (char *line, i386_insn *x)
252b5132 2393{
09137c09 2394 unsigned int j;
252b5132
RH		 2395
2396 fprintf (stdout, "%s: template ", line);
2397 pte (&x->tm);
09f131f2
JH		 2398 fprintf (stdout, " address: base %s index %s scale %x\n",
2399 x->base_reg ? x->base_reg->reg_name : "none",
2400 x->index_reg ? x->index_reg->reg_name : "none",
2401 x->log2_scale_factor);
2402 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2403 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2404 fprintf (stdout, " sib: base %x index %x scale %x\n",
2405 x->sib.base, x->sib.index, x->sib.scale);
2406 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2407 (x->rex & REX_W) != 0,
2408 (x->rex & REX_R) != 0,
2409 (x->rex & REX_X) != 0,
2410 (x->rex & REX_B) != 0);
09137c09 2411 for (j = 0; j < x->operands; j++)
252b5132 2412 {
09137c09
SP		 2413 fprintf (stdout, " #%d: ", j + 1);
2414 pt (x->types[j]);
252b5132 2415 fprintf (stdout, "\n");
09137c09
SP		 2416 if (x->types[j].bitfield.reg8
2417 || x->types[j].bitfield.reg16
2418 || x->types[j].bitfield.reg32
2419 || x->types[j].bitfield.reg64
2420 || x->types[j].bitfield.regmmx
2421 || x->types[j].bitfield.regxmm
2422 || x->types[j].bitfield.regymm
2423 || x->types[j].bitfield.sreg2
2424 || x->types[j].bitfield.sreg3
2425 || x->types[j].bitfield.control
2426 || x->types[j].bitfield.debug
2427 || x->types[j].bitfield.test)
2428 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2429 if (operand_type_check (x->types[j], imm))
2430 pe (x->op[j].imms);
2431 if (operand_type_check (x->types[j], disp))
2432 pe (x->op[j].disps);
252b5132
RH		 2433 }
2434}
2435
2436static void
d3ce72d0 2437pte (insn_template *t)
252b5132 2438{
09137c09 2439 unsigned int j;
252b5132 2440 fprintf (stdout, " %d operands ", t->operands);
47926f60 2441 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2442 if (t->extension_opcode != None)
2443 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2444 if (t->opcode_modifier.d)
252b5132 2445 fprintf (stdout, "D");
40fb9820 2446 if (t->opcode_modifier.w)
252b5132
RH		 2447 fprintf (stdout, "W");
2448 fprintf (stdout, "\n");
09137c09 2449 for (j = 0; j < t->operands; j++)
252b5132 2450 {
09137c09
SP		 2451 fprintf (stdout, " #%d type ", j + 1);
2452 pt (t->operand_types[j]);
252b5132
RH		 2453 fprintf (stdout, "\n");
2454 }
2455}
2456
2457static void
e3bb37b5 2458pe (expressionS *e)
252b5132 2459{
24eab124 2460 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2461 fprintf (stdout, " add_number %ld (%lx)\n",
2462 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2463 if (e->X_add_symbol)
2464 {
2465 fprintf (stdout, " add_symbol ");
2466 ps (e->X_add_symbol);
2467 fprintf (stdout, "\n");
2468 }
2469 if (e->X_op_symbol)
2470 {
2471 fprintf (stdout, " op_symbol ");
2472 ps (e->X_op_symbol);
2473 fprintf (stdout, "\n");
2474 }
2475}
2476
2477static void
e3bb37b5 2478ps (symbolS *s)
252b5132
RH		 2479{
2480 fprintf (stdout, "%s type %s%s",
2481 S_GET_NAME (s),
2482 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2483 segment_name (S_GET_SEGMENT (s)));
2484}
2485
7b81dfbb 2486static struct type_name
252b5132 2487 {
40fb9820
L		 2488 i386_operand_type mask;
2489 const char *name;
252b5132 2490 }
7b81dfbb 2491const type_names[] =
252b5132 2492{
40fb9820
L		 2493 { OPERAND_TYPE_REG8, "r8" },
2494 { OPERAND_TYPE_REG16, "r16" },
2495 { OPERAND_TYPE_REG32, "r32" },
2496 { OPERAND_TYPE_REG64, "r64" },
2497 { OPERAND_TYPE_IMM8, "i8" },
2498 { OPERAND_TYPE_IMM8, "i8s" },
2499 { OPERAND_TYPE_IMM16, "i16" },
2500 { OPERAND_TYPE_IMM32, "i32" },
2501 { OPERAND_TYPE_IMM32S, "i32s" },
2502 { OPERAND_TYPE_IMM64, "i64" },
2503 { OPERAND_TYPE_IMM1, "i1" },
2504 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2505 { OPERAND_TYPE_DISP8, "d8" },
2506 { OPERAND_TYPE_DISP16, "d16" },
2507 { OPERAND_TYPE_DISP32, "d32" },
2508 { OPERAND_TYPE_DISP32S, "d32s" },
2509 { OPERAND_TYPE_DISP64, "d64" },
2510 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2511 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2512 { OPERAND_TYPE_CONTROL, "control reg" },
2513 { OPERAND_TYPE_TEST, "test reg" },
2514 { OPERAND_TYPE_DEBUG, "debug reg" },
2515 { OPERAND_TYPE_FLOATREG, "FReg" },
2516 { OPERAND_TYPE_FLOATACC, "FAcc" },
2517 { OPERAND_TYPE_SREG2, "SReg2" },
2518 { OPERAND_TYPE_SREG3, "SReg3" },
2519 { OPERAND_TYPE_ACC, "Acc" },
2520 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2521 { OPERAND_TYPE_REGMMX, "rMMX" },
2522 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2523 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2524 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2525};
2526
2527static void
40fb9820 2528pt (i386_operand_type t)
252b5132 2529{
40fb9820 2530 unsigned int j;
c6fb90c8 2531 i386_operand_type a;
252b5132 2532
40fb9820 2533 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2534 {
2535 a = operand_type_and (t, type_names[j].mask);
0349dc08 2536 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2537 fprintf (stdout, "%s, ", type_names[j].name);
2538 }
252b5132
RH		 2539 fflush (stdout);
2540}
2541
2542#endif /* DEBUG386 */
2543\f
252b5132 2544static bfd_reloc_code_real_type
3956db08 2545reloc (unsigned int size,
64e74474
AM		 2546 int pcrel,
2547 int sign,
2548 bfd_reloc_code_real_type other)
252b5132 2549{
47926f60 2550 if (other != NO_RELOC)
3956db08 2551 {
91d6fa6a 2552 reloc_howto_type *rel;
3956db08
JB		 2553
2554 if (size == 8)
2555 switch (other)
2556 {
64e74474
AM		 2557 case BFD_RELOC_X86_64_GOT32:
2558 return BFD_RELOC_X86_64_GOT64;
2559 break;
2560 case BFD_RELOC_X86_64_PLTOFF64:
2561 return BFD_RELOC_X86_64_PLTOFF64;
2562 break;
2563 case BFD_RELOC_X86_64_GOTPC32:
2564 other = BFD_RELOC_X86_64_GOTPC64;
2565 break;
2566 case BFD_RELOC_X86_64_GOTPCREL:
2567 other = BFD_RELOC_X86_64_GOTPCREL64;
2568 break;
2569 case BFD_RELOC_X86_64_TPOFF32:
2570 other = BFD_RELOC_X86_64_TPOFF64;
2571 break;
2572 case BFD_RELOC_X86_64_DTPOFF32:
2573 other = BFD_RELOC_X86_64_DTPOFF64;
2574 break;
2575 default:
2576 break;
3956db08 2577 }
e05278af
JB		 2578
2579 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2580 if (size == 4 && flag_code != CODE_64BIT)
2581 sign = -1;
2582
91d6fa6a
NC		 2583 rel = bfd_reloc_type_lookup (stdoutput, other);
2584 if (!rel)
3956db08 2585 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2586 else if (size != bfd_get_reloc_size (rel))
3956db08 2587 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2588 bfd_get_reloc_size (rel),
3956db08 2589 size);
91d6fa6a 2590 else if (pcrel && !rel->pc_relative)
3956db08 2591 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2592 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2593 && !sign)
91d6fa6a 2594 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2595 && sign > 0))
3956db08
JB		 2596 as_bad (_("relocated field and relocation type differ in signedness"));
2597 else
2598 return other;
2599 return NO_RELOC;
2600 }
252b5132
RH		 2601
2602 if (pcrel)
2603 {
3e73aa7c 2604 if (!sign)
3956db08 2605 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2606 switch (size)
2607 {
2608 case 1: return BFD_RELOC_8_PCREL;
2609 case 2: return BFD_RELOC_16_PCREL;
2610 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2611 case 8: return BFD_RELOC_64_PCREL;
252b5132 2612 }
3956db08 2613 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2614 }
2615 else
2616 {
3956db08 2617 if (sign > 0)
e5cb08ac 2618 switch (size)
3e73aa7c
JH		 2619 {
2620 case 4: return BFD_RELOC_X86_64_32S;
2621 }
2622 else
2623 switch (size)
2624 {
2625 case 1: return BFD_RELOC_8;
2626 case 2: return BFD_RELOC_16;
2627 case 4: return BFD_RELOC_32;
2628 case 8: return BFD_RELOC_64;
2629 }
3956db08
JB		 2630 as_bad (_("cannot do %s %u byte relocation"),
2631 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2632 }
2633
0cc9e1d3 2634 return NO_RELOC;
252b5132
RH		 2635}
2636
47926f60
KH		 2637/* Here we decide which fixups can be adjusted to make them relative to
2638 the beginning of the section instead of the symbol. Basically we need
2639 to make sure that the dynamic relocations are done correctly, so in
2640 some cases we force the original symbol to be used. */
2641
252b5132 2642int
e3bb37b5 2643tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2644{
6d249963 2645#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2646 if (!IS_ELF)
31312f95
AM		 2647 return 1;
2648
a161fe53
AM		 2649 /* Don't adjust pc-relative references to merge sections in 64-bit
2650 mode. */
2651 if (use_rela_relocations
2652 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2653 && fixP->fx_pcrel)
252b5132 2654 return 0;
31312f95 2655
8d01d9a9
AJ		 2656 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2657 and changed later by validate_fix. */
2658 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2659 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2660 return 0;
2661
ce8a8b2f 2662 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2663 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2664 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2665 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2666 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2667 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2668 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2669 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2670 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2671 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2672 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2673 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2674 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2675 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2676 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2677 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2678 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2679 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2680 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2681 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2682 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2683 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2684 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2685 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2686 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2687 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2688 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2689 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2690 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2691 return 0;
31312f95 2692#endif
252b5132
RH		 2693 return 1;
2694}
252b5132 2695
b4cac588 2696static int
e3bb37b5 2697intel_float_operand (const char *mnemonic)
252b5132 2698{
9306ca4a
JB		 2699 /* Note that the value returned is meaningful only for opcodes with (memory)
2700 operands, hence the code here is free to improperly handle opcodes that
2701 have no operands (for better performance and smaller code). */
2702
2703 if (mnemonic[0] != 'f')
2704 return 0; /* non-math */
2705
2706 switch (mnemonic[1])
2707 {
2708 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2709 the fs segment override prefix not currently handled because no
2710 call path can make opcodes without operands get here */
2711 case 'i':
2712 return 2 /* integer op */;
2713 case 'l':
2714 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2715 return 3; /* fldcw/fldenv */
2716 break;
2717 case 'n':
2718 if (mnemonic[2] != 'o' /* fnop */)
2719 return 3; /* non-waiting control op */
2720 break;
2721 case 'r':
2722 if (mnemonic[2] == 's')
2723 return 3; /* frstor/frstpm */
2724 break;
2725 case 's':
2726 if (mnemonic[2] == 'a')
2727 return 3; /* fsave */
2728 if (mnemonic[2] == 't')
2729 {
2730 switch (mnemonic[3])
2731 {
2732 case 'c': /* fstcw */
2733 case 'd': /* fstdw */
2734 case 'e': /* fstenv */
2735 case 's': /* fsts[gw] */
2736 return 3;
2737 }
2738 }
2739 break;
2740 case 'x':
2741 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2742 return 0; /* fxsave/fxrstor are not really math ops */
2743 break;
2744 }
252b5132 2745
9306ca4a 2746 return 1;
252b5132
RH		 2747}
2748
c0f3af97
L		 2749/* Build the VEX prefix. */
2750
2751static void
d3ce72d0 2752build_vex_prefix (const insn_template *t)
c0f3af97
L		 2753{
2754 unsigned int register_specifier;
2755 unsigned int implied_prefix;
2756 unsigned int vector_length;
2757
2758 /* Check register specifier. */
2759 if (i.vex.register_specifier)
2760 {
2761 register_specifier = i.vex.register_specifier->reg_num;
2762 if ((i.vex.register_specifier->reg_flags & RegRex))
2763 register_specifier += 8;
2764 register_specifier = ~register_specifier & 0xf;
2765 }
2766 else
2767 register_specifier = 0xf;
2768
fa99fab2
L		 2769 /* Use 2-byte VEX prefix by swappping destination and source
2770 operand. */
2771 if (!i.swap_operand
2772 && i.operands == i.reg_operands
7f399153 2773 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2774 && i.tm.opcode_modifier.s
2775 && i.rex == REX_B)
2776 {
2777 unsigned int xchg = i.operands - 1;
2778 union i386_op temp_op;
2779 i386_operand_type temp_type;
2780
2781 temp_type = i.types[xchg];
2782 i.types[xchg] = i.types[0];
2783 i.types[0] = temp_type;
2784 temp_op = i.op[xchg];
2785 i.op[xchg] = i.op[0];
2786 i.op[0] = temp_op;
2787
9c2799c2 2788 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2789
2790 i.rex = REX_R;
2791 xchg = i.rm.regmem;
2792 i.rm.regmem = i.rm.reg;
2793 i.rm.reg = xchg;
2794
2795 /* Use the next insn. */
2796 i.tm = t[1];
2797 }
2798
539f890d
L		 2799 if (i.tm.opcode_modifier.vex == VEXScalar)
2800 vector_length = avxscalar;
2801 else
2802 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2803
2804 switch ((i.tm.base_opcode >> 8) & 0xff)
2805 {
2806 case 0:
2807 implied_prefix = 0;
2808 break;
2809 case DATA_PREFIX_OPCODE:
2810 implied_prefix = 1;
2811 break;
2812 case REPE_PREFIX_OPCODE:
2813 implied_prefix = 2;
2814 break;
2815 case REPNE_PREFIX_OPCODE:
2816 implied_prefix = 3;
2817 break;
2818 default:
2819 abort ();
2820 }
2821
2822 /* Use 2-byte VEX prefix if possible. */
7f399153 2823 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 2824 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 2825 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2826 {
2827 /* 2-byte VEX prefix. */
2828 unsigned int r;
2829
2830 i.vex.length = 2;
2831 i.vex.bytes[0] = 0xc5;
2832
2833 /* Check the REX.R bit. */
2834 r = (i.rex & REX_R) ? 0 : 1;
2835 i.vex.bytes[1] = (r << 7
2836 | register_specifier << 3
2837 | vector_length << 2
2838 | implied_prefix);
2839 }
2840 else
2841 {
2842 /* 3-byte VEX prefix. */
2843 unsigned int m, w;
2844
f88c9eb0 2845 i.vex.length = 3;
f88c9eb0 2846
7f399153 2847 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2848 {
7f399153
L		 2849 case VEX0F:
2850 m = 0x1;
80de6e00 2851 i.vex.bytes[0] = 0xc4;
7f399153
L		 2852 break;
2853 case VEX0F38:
2854 m = 0x2;
80de6e00 2855 i.vex.bytes[0] = 0xc4;
7f399153
L		 2856 break;
2857 case VEX0F3A:
2858 m = 0x3;
80de6e00 2859 i.vex.bytes[0] = 0xc4;
7f399153
L		 2860 break;
2861 case XOP08:
5dd85c99
SP		 2862 m = 0x8;
2863 i.vex.bytes[0] = 0x8f;
7f399153
L		 2864 break;
2865 case XOP09:
f88c9eb0
SP		 2866 m = 0x9;
2867 i.vex.bytes[0] = 0x8f;
7f399153
L		 2868 break;
2869 case XOP0A:
f88c9eb0
SP		 2870 m = 0xa;
2871 i.vex.bytes[0] = 0x8f;
7f399153
L		 2872 break;
2873 default:
2874 abort ();
f88c9eb0 2875 }
c0f3af97 2876
c0f3af97
L		 2877 /* The high 3 bits of the second VEX byte are 1's compliment
2878 of RXB bits from REX. */
2879 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2880
2881 /* Check the REX.W bit. */
2882 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2883 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2884 {
2885 if (w)
2886 abort ();
2887
1ef99a7b 2888 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2889 w = 1;
2890 }
2891
2892 i.vex.bytes[2] = (w << 7
2893 | register_specifier << 3
2894 | vector_length << 2
2895 | implied_prefix);
2896 }
2897}
2898
65da13b5
L		 2899static void
2900process_immext (void)
2901{
2902 expressionS *exp;
2903
2904 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2905 {
1fed0ba1
L		 2906 /* SSE3 Instructions have the fixed operands with an opcode
2907 suffix which is coded in the same place as an 8-bit immediate
2908 field would be. Here we check those operands and remove them
2909 afterwards. */
65da13b5
L		 2910 unsigned int x;
2911
2912 for (x = 0; x < i.operands; x++)
2913 if (i.op[x].regs->reg_num != x)
2914 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2915 register_prefix, i.op[x].regs->reg_name, x + 1,
2916 i.tm.name);
2917
2918 i.operands = 0;
65da13b5
L		 2919 }
2920
c0f3af97 2921 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2922 which is coded in the same place as an 8-bit immediate field
2923 would be. Here we fake an 8-bit immediate operand from the
2924 opcode suffix stored in tm.extension_opcode.
2925
c1e679ec 2926 AVX instructions also use this encoding, for some of
c0f3af97 2927 3 argument instructions. */
65da13b5 2928
9c2799c2 2929 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2930 && (i.operands <= 2
2931 || (i.tm.opcode_modifier.vex
2932 && i.operands <= 4)));
65da13b5
L		 2933
2934 exp = &im_expressions[i.imm_operands++];
2935 i.op[i.operands].imms = exp;
2936 i.types[i.operands] = imm8;
2937 i.operands++;
2938 exp->X_op = O_constant;
2939 exp->X_add_number = i.tm.extension_opcode;
2940 i.tm.extension_opcode = None;
2941}
2942
252b5132
RH		 2943/* This is the guts of the machine-dependent assembler. LINE points to a
2944 machine dependent instruction. This function is supposed to emit
2945 the frags/bytes it assembles to. */
2946
2947void
65da13b5 2948md_assemble (char *line)
252b5132 2949{
40fb9820 2950 unsigned int j;
252b5132 2951 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2952 const insn_template *t;
252b5132 2953
47926f60 2954 /* Initialize globals. */
252b5132
RH		 2955 memset (&i, '\0', sizeof (i));
2956 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2957 i.reloc[j] = NO_RELOC;
252b5132
RH		 2958 memset (disp_expressions, '\0', sizeof (disp_expressions));
2959 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2960 save_stack_p = save_stack;
252b5132
RH		 2961
2962 /* First parse an instruction mnemonic & call i386_operand for the operands.
2963 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2964 start of a (possibly prefixed) mnemonic. */
252b5132 2965
29b0f896
AM		 2966 line = parse_insn (line, mnemonic);
2967 if (line == NULL)
2968 return;
252b5132 2969
29b0f896 2970 line = parse_operands (line, mnemonic);
ee86248c 2971 this_operand = -1;
29b0f896
AM		 2972 if (line == NULL)
2973 return;
252b5132 2974
29b0f896
AM		 2975 /* Now we've parsed the mnemonic into a set of templates, and have the
2976 operands at hand. */
2977
2978 /* All intel opcodes have reversed operands except for "bound" and
2979 "enter". We also don't reverse intersegment "jmp" and "call"
2980 instructions with 2 immediate operands so that the immediate segment
050dfa73 2981 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2982 if (intel_syntax
2983 && i.operands > 1
29b0f896 2984 && (strcmp (mnemonic, "bound") != 0)
30123838 2985 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2986 && !(operand_type_check (i.types[0], imm)
2987 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2988 swap_operands ();
2989
ec56d5c0
JB		 2990 /* The order of the immediates should be reversed
2991 for 2 immediates extrq and insertq instructions */
2992 if (i.imm_operands == 2
2993 && (strcmp (mnemonic, "extrq") == 0
2994 || strcmp (mnemonic, "insertq") == 0))
2995 swap_2_operands (0, 1);
2996
29b0f896
AM		 2997 if (i.imm_operands)
2998 optimize_imm ();
2999
b300c311
L		 3000 /* Don't optimize displacement for movabs since it only takes 64bit
3001 displacement. */
3002 if (i.disp_operands
f8a5c266 3003 && !i.disp32_encoding
b300c311
L		 3004 && (flag_code != CODE_64BIT
3005 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 3006 optimize_disp ();
3007
3008 /* Next, we find a template that matches the given insn,
3009 making sure the overlap of the given operands types is consistent
3010 with the template operand types. */
252b5132 3011
fa99fab2 3012 if (!(t = match_template ()))
29b0f896 3013 return;
252b5132 3014
daf50ae7 3015 if (sse_check != sse_check_none
81f8a913 3016 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3017 && (i.tm.cpu_flags.bitfield.cpusse
3018 || i.tm.cpu_flags.bitfield.cpusse2
3019 || i.tm.cpu_flags.bitfield.cpusse3
3020 || i.tm.cpu_flags.bitfield.cpussse3
3021 || i.tm.cpu_flags.bitfield.cpusse4_1
3022 || i.tm.cpu_flags.bitfield.cpusse4_2))
3023 {
3024 (sse_check == sse_check_warning
3025 ? as_warn
3026 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3027 }
3028
321fd21e
L		 3029 /* Zap movzx and movsx suffix. The suffix has been set from
3030 "word ptr" or "byte ptr" on the source operand in Intel syntax
3031 or extracted from mnemonic in AT&T syntax. But we'll use
3032 the destination register to choose the suffix for encoding. */
3033 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3034 {
321fd21e
L		 3035 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3036 there is no suffix, the default will be byte extension. */
3037 if (i.reg_operands != 2
3038 && !i.suffix
7ab9ffdd 3039 && intel_syntax)
321fd21e
L		 3040 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3041
3042 i.suffix = 0;
cd61ebfe 3043 }
24eab124 3044
40fb9820 3045 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3046 if (!add_prefix (FWAIT_OPCODE))
3047 return;
252b5132 3048
c1ba0266
L		 3049 /* Check for lock without a lockable instruction. Destination operand
3050 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3051 if (i.prefix[LOCK_PREFIX]
3052 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3053 || i.mem_operands == 0
3054 || (i.tm.base_opcode != 0x86
3055 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3056 {
3057 as_bad (_("expecting lockable instruction after `lock'"));
3058 return;
3059 }
3060
29b0f896 3061 /* Check string instruction segment overrides. */
40fb9820 3062 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3063 {
3064 if (!check_string ())
5dd0794d 3065 return;
fc0763e6 3066 i.disp_operands = 0;
29b0f896 3067 }
5dd0794d 3068
29b0f896
AM		 3069 if (!process_suffix ())
3070 return;
e413e4e9 3071
bc0844ae
L		 3072 /* Update operand types. */
3073 for (j = 0; j < i.operands; j++)
3074 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3075
29b0f896
AM		 3076 /* Make still unresolved immediate matches conform to size of immediate
3077 given in i.suffix. */
3078 if (!finalize_imm ())
3079 return;
252b5132 3080
40fb9820 3081 if (i.types[0].bitfield.imm1)
29b0f896 3082 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3083
9afe6eb8
L		 3084 /* We only need to check those implicit registers for instructions
3085 with 3 operands or less. */
3086 if (i.operands <= 3)
3087 for (j = 0; j < i.operands; j++)
3088 if (i.types[j].bitfield.inoutportreg
3089 || i.types[j].bitfield.shiftcount
3090 || i.types[j].bitfield.acc
3091 || i.types[j].bitfield.floatacc)
3092 i.reg_operands--;
40fb9820 3093
c0f3af97
L		 3094 /* ImmExt should be processed after SSE2AVX. */
3095 if (!i.tm.opcode_modifier.sse2avx
3096 && i.tm.opcode_modifier.immext)
65da13b5 3097 process_immext ();
252b5132 3098
29b0f896
AM		 3099 /* For insns with operands there are more diddles to do to the opcode. */
3100 if (i.operands)
3101 {
3102 if (!process_operands ())
3103 return;
3104 }
40fb9820 3105 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3106 {
3107 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3108 as_warn (_("translating to `%sp'"), i.tm.name);
3109 }
252b5132 3110
c0f3af97 3111 if (i.tm.opcode_modifier.vex)
fa99fab2 3112 build_vex_prefix (t);
c0f3af97 3113
5dd85c99
SP		 3114 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3115 instructions may define INT_OPCODE as well, so avoid this corner
3116 case for those instructions that use MODRM. */
3117 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3118 && !i.tm.opcode_modifier.modrm
3119 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3120 {
3121 i.tm.base_opcode = INT3_OPCODE;
3122 i.imm_operands = 0;
3123 }
252b5132 3124
40fb9820
L		 3125 if ((i.tm.opcode_modifier.jump
3126 || i.tm.opcode_modifier.jumpbyte
3127 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3128 && i.op[0].disps->X_op == O_constant)
3129 {
3130 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3131 the absolute address given by the constant. Since ix86 jumps and
3132 calls are pc relative, we need to generate a reloc. */
3133 i.op[0].disps->X_add_symbol = &abs_symbol;
3134 i.op[0].disps->X_op = O_symbol;
3135 }
252b5132 3136
40fb9820 3137 if (i.tm.opcode_modifier.rex64)
161a04f6 3138 i.rex |= REX_W;
252b5132 3139
29b0f896
AM		 3140 /* For 8 bit registers we need an empty rex prefix. Also if the
3141 instruction already has a prefix, we need to convert old
3142 registers to new ones. */
773f551c 3143
40fb9820 3144 if ((i.types[0].bitfield.reg8
29b0f896 3145 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3146 || (i.types[1].bitfield.reg8
29b0f896 3147 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3148 || ((i.types[0].bitfield.reg8
3149 || i.types[1].bitfield.reg8)
29b0f896
AM		 3150 && i.rex != 0))
3151 {
3152 int x;
726c5dcd 3153
29b0f896
AM		 3154 i.rex |= REX_OPCODE;
3155 for (x = 0; x < 2; x++)
3156 {
3157 /* Look for 8 bit operand that uses old registers. */
40fb9820 3158 if (i.types[x].bitfield.reg8
29b0f896 3159 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3160 {
29b0f896
AM		 3161 /* In case it is "hi" register, give up. */
3162 if (i.op[x].regs->reg_num > 3)
a540244d 3163 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3164 "instruction requiring REX prefix."),
a540244d 3165 register_prefix, i.op[x].regs->reg_name);
773f551c 3166
29b0f896
AM		 3167 /* Otherwise it is equivalent to the extended register.
3168 Since the encoding doesn't change this is merely
3169 cosmetic cleanup for debug output. */
3170
3171 i.op[x].regs = i.op[x].regs + 8;
773f551c 3172 }
29b0f896
AM		 3173 }
3174 }
773f551c 3175
7ab9ffdd 3176 if (i.rex != 0)
29b0f896
AM		 3177 add_prefix (REX_OPCODE | i.rex);
3178
3179 /* We are ready to output the insn. */
3180 output_insn ();
3181}
3182
3183static char *
e3bb37b5 3184parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3185{
3186 char *l = line;
3187 char *token_start = l;
3188 char *mnem_p;
5c6af06e 3189 int supported;
d3ce72d0 3190 const insn_template *t;
b6169b20 3191 char *dot_p = NULL;
29b0f896
AM		 3192
3193 /* Non-zero if we found a prefix only acceptable with string insns. */
3194 const char *expecting_string_instruction = NULL;
45288df1 3195
29b0f896
AM		 3196 while (1)
3197 {
3198 mnem_p = mnemonic;
3199 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3200 {
b6169b20
L		 3201 if (*mnem_p == '.')
3202 dot_p = mnem_p;
29b0f896
AM		 3203 mnem_p++;
3204 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3205 {
29b0f896
AM		 3206 as_bad (_("no such instruction: `%s'"), token_start);
3207 return NULL;
3208 }
3209 l++;
3210 }
3211 if (!is_space_char (*l)
3212 && *l != END_OF_INSN
e44823cf
JB		 3213 && (intel_syntax
3214 || (*l != PREFIX_SEPARATOR
3215 && *l != ',')))
29b0f896
AM		 3216 {
3217 as_bad (_("invalid character %s in mnemonic"),
3218 output_invalid (*l));
3219 return NULL;
3220 }
3221 if (token_start == l)
3222 {
e44823cf 3223 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3224 as_bad (_("expecting prefix; got nothing"));
3225 else
3226 as_bad (_("expecting mnemonic; got nothing"));
3227 return NULL;
3228 }
45288df1 3229
29b0f896 3230 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3231 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3232
29b0f896
AM		 3233 if (*l != END_OF_INSN
3234 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3235 && current_templates
40fb9820 3236 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3237 {
c6fb90c8 3238 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3239 {
3240 as_bad ((flag_code != CODE_64BIT
3241 ? _("`%s' is only supported in 64-bit mode")
3242 : _("`%s' is not supported in 64-bit mode")),
3243 current_templates->start->name);
3244 return NULL;
3245 }
29b0f896
AM		 3246 /* If we are in 16-bit mode, do not allow addr16 or data16.
3247 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3248 if ((current_templates->start->opcode_modifier.size16
3249 || current_templates->start->opcode_modifier.size32)
29b0f896 3250 && flag_code != CODE_64BIT
40fb9820 3251 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3252 ^ (flag_code == CODE_16BIT)))
3253 {
3254 as_bad (_("redundant %s prefix"),
3255 current_templates->start->name);
3256 return NULL;
45288df1 3257 }
29b0f896
AM		 3258 /* Add prefix, checking for repeated prefixes. */
3259 switch (add_prefix (current_templates->start->base_opcode))
3260 {
c32fa91d 3261 case PREFIX_EXIST:
29b0f896 3262 return NULL;
c32fa91d 3263 case PREFIX_REP:
29b0f896
AM		 3264 expecting_string_instruction = current_templates->start->name;
3265 break;
c32fa91d
L		 3266 default:
3267 break;
29b0f896
AM		 3268 }
3269 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3270 token_start = ++l;
3271 }
3272 else
3273 break;
3274 }
45288df1 3275
30a55f88 3276 if (!current_templates)
b6169b20 3277 {
f8a5c266
L		 3278 /* Check if we should swap operand or force 32bit displacement in
3279 encoding. */
30a55f88
L		 3280 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3281 i.swap_operand = 1;
f8a5c266
L		 3282 else if (mnem_p - 4 == dot_p
3283 && dot_p[1] == 'd'
3284 && dot_p[2] == '3'
3285 && dot_p[3] == '2')
3286 i.disp32_encoding = 1;
30a55f88
L		 3287 else
3288 goto check_suffix;
3289 mnem_p = dot_p;
3290 *dot_p = '\0';
d3ce72d0 3291 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3292 }
3293
29b0f896
AM		 3294 if (!current_templates)
3295 {
b6169b20 3296check_suffix:
29b0f896
AM		 3297 /* See if we can get a match by trimming off a suffix. */
3298 switch (mnem_p[-1])
3299 {
3300 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3301 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3302 i.suffix = SHORT_MNEM_SUFFIX;
3303 else
29b0f896
AM		 3304 case BYTE_MNEM_SUFFIX:
3305 case QWORD_MNEM_SUFFIX:
3306 i.suffix = mnem_p[-1];
3307 mnem_p[-1] = '\0';
d3ce72d0
NC		 3308 current_templates = (const templates *) hash_find (op_hash,
3309 mnemonic);
29b0f896
AM		 3310 break;
3311 case SHORT_MNEM_SUFFIX:
3312 case LONG_MNEM_SUFFIX:
3313 if (!intel_syntax)
3314 {
3315 i.suffix = mnem_p[-1];
3316 mnem_p[-1] = '\0';
d3ce72d0
NC		 3317 current_templates = (const templates *) hash_find (op_hash,
3318 mnemonic);
29b0f896
AM		 3319 }
3320 break;
252b5132 3321
29b0f896
AM		 3322 /* Intel Syntax. */
3323 case 'd':
3324 if (intel_syntax)
3325 {
9306ca4a 3326 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3327 i.suffix = SHORT_MNEM_SUFFIX;
3328 else
3329 i.suffix = LONG_MNEM_SUFFIX;
3330 mnem_p[-1] = '\0';
d3ce72d0
NC		 3331 current_templates = (const templates *) hash_find (op_hash,
3332 mnemonic);
29b0f896
AM		 3333 }
3334 break;
3335 }
3336 if (!current_templates)
3337 {
3338 as_bad (_("no such instruction: `%s'"), token_start);
3339 return NULL;
3340 }
3341 }
252b5132 3342
40fb9820
L		 3343 if (current_templates->start->opcode_modifier.jump
3344 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3345 {
3346 /* Check for a branch hint. We allow ",pt" and ",pn" for
3347 predict taken and predict not taken respectively.
3348 I'm not sure that branch hints actually do anything on loop
3349 and jcxz insns (JumpByte) for current Pentium4 chips. They
3350 may work in the future and it doesn't hurt to accept them
3351 now. */
3352 if (l[0] == ',' && l[1] == 'p')
3353 {
3354 if (l[2] == 't')
3355 {
3356 if (!add_prefix (DS_PREFIX_OPCODE))
3357 return NULL;
3358 l += 3;
3359 }
3360 else if (l[2] == 'n')
3361 {
3362 if (!add_prefix (CS_PREFIX_OPCODE))
3363 return NULL;
3364 l += 3;
3365 }
3366 }
3367 }
3368 /* Any other comma loses. */
3369 if (*l == ',')
3370 {
3371 as_bad (_("invalid character %s in mnemonic"),
3372 output_invalid (*l));
3373 return NULL;
3374 }
252b5132 3375
29b0f896 3376 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3377 supported = 0;
3378 for (t = current_templates->start; t < current_templates->end; ++t)
3379 {
c0f3af97
L		 3380 supported |= cpu_flags_match (t);
3381 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3382 goto skip;
5c6af06e 3383 }
3629bb00 3384
c0f3af97 3385 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3386 {
3387 as_bad (flag_code == CODE_64BIT
3388 ? _("`%s' is not supported in 64-bit mode")
3389 : _("`%s' is only supported in 64-bit mode"),
3390 current_templates->start->name);
3391 return NULL;
3392 }
c0f3af97 3393 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3394 {
3629bb00 3395 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3396 current_templates->start->name,
41aacd83 3397 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3398 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3399 return NULL;
29b0f896 3400 }
3629bb00
L		 3401
3402skip:
3403 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3404 && (flag_code != CODE_16BIT))
29b0f896
AM		 3405 {
3406 as_warn (_("use .code16 to ensure correct addressing mode"));
3407 }
252b5132 3408
29b0f896 3409 /* Check for rep/repne without a string instruction. */
f41bbced 3410 if (expecting_string_instruction)
29b0f896 3411 {
f41bbced
JB		 3412 static templates override;
3413
3414 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3415 if (t->opcode_modifier.isstring)
f41bbced
JB		 3416 break;
3417 if (t >= current_templates->end)
3418 {
3419 as_bad (_("expecting string instruction after `%s'"),
64e74474 3420 expecting_string_instruction);
f41bbced
JB		 3421 return NULL;
3422 }
3423 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3424 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3425 break;
3426 override.end = t;
3427 current_templates = &override;
29b0f896 3428 }
252b5132 3429
29b0f896
AM		 3430 return l;
3431}
252b5132 3432
29b0f896 3433static char *
e3bb37b5 3434parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3435{
3436 char *token_start;
3138f287 3437
29b0f896
AM		 3438 /* 1 if operand is pending after ','. */
3439 unsigned int expecting_operand = 0;
252b5132 3440
29b0f896
AM		 3441 /* Non-zero if operand parens not balanced. */
3442 unsigned int paren_not_balanced;
3443
3444 while (*l != END_OF_INSN)
3445 {
3446 /* Skip optional white space before operand. */
3447 if (is_space_char (*l))
3448 ++l;
3449 if (!is_operand_char (*l) && *l != END_OF_INSN)
3450 {
3451 as_bad (_("invalid character %s before operand %d"),
3452 output_invalid (*l),
3453 i.operands + 1);
3454 return NULL;
3455 }
3456 token_start = l; /* after white space */
3457 paren_not_balanced = 0;
3458 while (paren_not_balanced || *l != ',')
3459 {
3460 if (*l == END_OF_INSN)
3461 {
3462 if (paren_not_balanced)
3463 {
3464 if (!intel_syntax)
3465 as_bad (_("unbalanced parenthesis in operand %d."),
3466 i.operands + 1);
3467 else
3468 as_bad (_("unbalanced brackets in operand %d."),
3469 i.operands + 1);
3470 return NULL;
3471 }
3472 else
3473 break; /* we are done */
3474 }
3475 else if (!is_operand_char (*l) && !is_space_char (*l))
3476 {
3477 as_bad (_("invalid character %s in operand %d"),
3478 output_invalid (*l),
3479 i.operands + 1);
3480 return NULL;
3481 }
3482 if (!intel_syntax)
3483 {
3484 if (*l == '(')
3485 ++paren_not_balanced;
3486 if (*l == ')')
3487 --paren_not_balanced;
3488 }
3489 else
3490 {
3491 if (*l == '[')
3492 ++paren_not_balanced;
3493 if (*l == ']')
3494 --paren_not_balanced;
3495 }
3496 l++;
3497 }
3498 if (l != token_start)
3499 { /* Yes, we've read in another operand. */
3500 unsigned int operand_ok;
3501 this_operand = i.operands++;
7d5e4556 3502 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3503 if (i.operands > MAX_OPERANDS)
3504 {
3505 as_bad (_("spurious operands; (%d operands/instruction max)"),
3506 MAX_OPERANDS);
3507 return NULL;
3508 }
3509 /* Now parse operand adding info to 'i' as we go along. */
3510 END_STRING_AND_SAVE (l);
3511
3512 if (intel_syntax)
3513 operand_ok =
3514 i386_intel_operand (token_start,
3515 intel_float_operand (mnemonic));
3516 else
a7619375 3517 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3518
3519 RESTORE_END_STRING (l);
3520 if (!operand_ok)
3521 return NULL;
3522 }
3523 else
3524 {
3525 if (expecting_operand)
3526 {
3527 expecting_operand_after_comma:
3528 as_bad (_("expecting operand after ','; got nothing"));
3529 return NULL;
3530 }
3531 if (*l == ',')
3532 {
3533 as_bad (_("expecting operand before ','; got nothing"));
3534 return NULL;
3535 }
3536 }
7f3f1ea2 3537
29b0f896
AM		 3538 /* Now *l must be either ',' or END_OF_INSN. */
3539 if (*l == ',')
3540 {
3541 if (*++l == END_OF_INSN)
3542 {
3543 /* Just skip it, if it's \n complain. */
3544 goto expecting_operand_after_comma;
3545 }
3546 expecting_operand = 1;
3547 }
3548 }
3549 return l;
3550}
7f3f1ea2 3551
050dfa73 3552static void
4d456e3d 3553swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3554{
3555 union i386_op temp_op;
40fb9820 3556 i386_operand_type temp_type;
050dfa73 3557 enum bfd_reloc_code_real temp_reloc;
4eed87de 3558
050dfa73
MM		 3559 temp_type = i.types[xchg2];
3560 i.types[xchg2] = i.types[xchg1];
3561 i.types[xchg1] = temp_type;
3562 temp_op = i.op[xchg2];
3563 i.op[xchg2] = i.op[xchg1];
3564 i.op[xchg1] = temp_op;
3565 temp_reloc = i.reloc[xchg2];
3566 i.reloc[xchg2] = i.reloc[xchg1];
3567 i.reloc[xchg1] = temp_reloc;
3568}
3569
29b0f896 3570static void
e3bb37b5 3571swap_operands (void)
29b0f896 3572{
b7c61d9a 3573 switch (i.operands)
050dfa73 3574 {
c0f3af97 3575 case 5:
b7c61d9a 3576 case 4:
4d456e3d 3577 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3578 case 3:
3579 case 2:
4d456e3d 3580 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3581 break;
3582 default:
3583 abort ();
29b0f896 3584 }
29b0f896
AM		 3585
3586 if (i.mem_operands == 2)
3587 {
3588 const seg_entry *temp_seg;
3589 temp_seg = i.seg[0];
3590 i.seg[0] = i.seg[1];
3591 i.seg[1] = temp_seg;
3592 }
3593}
252b5132 3594
29b0f896
AM		 3595/* Try to ensure constant immediates are represented in the smallest
3596 opcode possible. */
3597static void
e3bb37b5 3598optimize_imm (void)
29b0f896
AM		 3599{
3600 char guess_suffix = 0;
3601 int op;
252b5132 3602
29b0f896
AM		 3603 if (i.suffix)
3604 guess_suffix = i.suffix;
3605 else if (i.reg_operands)
3606 {
3607 /* Figure out a suffix from the last register operand specified.
3608 We can't do this properly yet, ie. excluding InOutPortReg,
3609 but the following works for instructions with immediates.
3610 In any case, we can't set i.suffix yet. */
3611 for (op = i.operands; --op >= 0;)
40fb9820 3612 if (i.types[op].bitfield.reg8)
7ab9ffdd 3613 {
40fb9820
L		 3614 guess_suffix = BYTE_MNEM_SUFFIX;
3615 break;
3616 }
3617 else if (i.types[op].bitfield.reg16)
252b5132 3618 {
40fb9820
L		 3619 guess_suffix = WORD_MNEM_SUFFIX;
3620 break;
3621 }
3622 else if (i.types[op].bitfield.reg32)
3623 {
3624 guess_suffix = LONG_MNEM_SUFFIX;
3625 break;
3626 }
3627 else if (i.types[op].bitfield.reg64)
3628 {
3629 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3630 break;
252b5132 3631 }
29b0f896
AM		 3632 }
3633 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3634 guess_suffix = WORD_MNEM_SUFFIX;
3635
3636 for (op = i.operands; --op >= 0;)
40fb9820 3637 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3638 {
3639 switch (i.op[op].imms->X_op)
252b5132 3640 {
29b0f896
AM		 3641 case O_constant:
3642 /* If a suffix is given, this operand may be shortened. */
3643 switch (guess_suffix)
252b5132 3644 {
29b0f896 3645 case LONG_MNEM_SUFFIX:
40fb9820
L		 3646 i.types[op].bitfield.imm32 = 1;
3647 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3648 break;
3649 case WORD_MNEM_SUFFIX:
40fb9820
L		 3650 i.types[op].bitfield.imm16 = 1;
3651 i.types[op].bitfield.imm32 = 1;
3652 i.types[op].bitfield.imm32s = 1;
3653 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3654 break;
3655 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3656 i.types[op].bitfield.imm8 = 1;
3657 i.types[op].bitfield.imm8s = 1;
3658 i.types[op].bitfield.imm16 = 1;
3659 i.types[op].bitfield.imm32 = 1;
3660 i.types[op].bitfield.imm32s = 1;
3661 i.types[op].bitfield.imm64 = 1;
29b0f896 3662 break;
252b5132 3663 }
252b5132 3664
29b0f896
AM		 3665 /* If this operand is at most 16 bits, convert it
3666 to a signed 16 bit number before trying to see
3667 whether it will fit in an even smaller size.
3668 This allows a 16-bit operand such as $0xffe0 to
3669 be recognised as within Imm8S range. */
40fb9820 3670 if ((i.types[op].bitfield.imm16)
29b0f896 3671 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3672 {
29b0f896
AM		 3673 i.op[op].imms->X_add_number =
3674 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3675 }
40fb9820 3676 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3677 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3678 == 0))
3679 {
3680 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3681 ^ ((offsetT) 1 << 31))
3682 - ((offsetT) 1 << 31));
3683 }
40fb9820 3684 i.types[op]
c6fb90c8
L		 3685 = operand_type_or (i.types[op],
3686 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3687
29b0f896
AM		 3688 /* We must avoid matching of Imm32 templates when 64bit
3689 only immediate is available. */
3690 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3691 i.types[op].bitfield.imm32 = 0;
29b0f896 3692 break;
252b5132 3693
29b0f896
AM		 3694 case O_absent:
3695 case O_register:
3696 abort ();
3697
3698 /* Symbols and expressions. */
3699 default:
9cd96992
JB		 3700 /* Convert symbolic operand to proper sizes for matching, but don't
3701 prevent matching a set of insns that only supports sizes other
3702 than those matching the insn suffix. */
3703 {
40fb9820 3704 i386_operand_type mask, allowed;
d3ce72d0 3705 const insn_template *t;
9cd96992 3706
0dfbf9d7
L		 3707 operand_type_set (&mask, 0);
3708 operand_type_set (&allowed, 0);
40fb9820 3709
4eed87de
AM		 3710 for (t = current_templates->start;
3711 t < current_templates->end;
3712 ++t)
c6fb90c8
L		 3713 allowed = operand_type_or (allowed,
3714 t->operand_types[op]);
9cd96992
JB		 3715 switch (guess_suffix)
3716 {
3717 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3718 mask.bitfield.imm64 = 1;
3719 mask.bitfield.imm32s = 1;
9cd96992
JB		 3720 break;
3721 case LONG_MNEM_SUFFIX:
40fb9820 3722 mask.bitfield.imm32 = 1;
9cd96992
JB		 3723 break;
3724 case WORD_MNEM_SUFFIX:
40fb9820 3725 mask.bitfield.imm16 = 1;
9cd96992
JB		 3726 break;
3727 case BYTE_MNEM_SUFFIX:
40fb9820 3728 mask.bitfield.imm8 = 1;
9cd96992
JB		 3729 break;
3730 default:
9cd96992
JB		 3731 break;
3732 }
c6fb90c8 3733 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3734 if (!operand_type_all_zero (&allowed))
c6fb90c8 3735 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3736 }
29b0f896 3737 break;
252b5132 3738 }
29b0f896
AM		 3739 }
3740}
47926f60 3741
29b0f896
AM		 3742/* Try to use the smallest displacement type too. */
3743static void
e3bb37b5 3744optimize_disp (void)
29b0f896
AM		 3745{
3746 int op;
3e73aa7c 3747
29b0f896 3748 for (op = i.operands; --op >= 0;)
40fb9820 3749 if (operand_type_check (i.types[op], disp))
252b5132 3750 {
b300c311 3751 if (i.op[op].disps->X_op == O_constant)
252b5132 3752 {
91d6fa6a 3753 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3754
40fb9820 3755 if (i.types[op].bitfield.disp16
91d6fa6a 3756 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3757 {
3758 /* If this operand is at most 16 bits, convert
3759 to a signed 16 bit number and don't use 64bit
3760 displacement. */
91d6fa6a 3761 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3762 i.types[op].bitfield.disp64 = 0;
b300c311 3763 }
40fb9820 3764 if (i.types[op].bitfield.disp32
91d6fa6a 3765 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3766 {
3767 /* If this operand is at most 32 bits, convert
3768 to a signed 32 bit number and don't use 64bit
3769 displacement. */
91d6fa6a
NC		 3770 op_disp &= (((offsetT) 2 << 31) - 1);
3771 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3772 i.types[op].bitfield.disp64 = 0;
b300c311 3773 }
91d6fa6a 3774 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3775 {
40fb9820
L		 3776 i.types[op].bitfield.disp8 = 0;
3777 i.types[op].bitfield.disp16 = 0;
3778 i.types[op].bitfield.disp32 = 0;
3779 i.types[op].bitfield.disp32s = 0;
3780 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3781 i.op[op].disps = 0;
3782 i.disp_operands--;
3783 }
3784 else if (flag_code == CODE_64BIT)
3785 {
91d6fa6a 3786 if (fits_in_signed_long (op_disp))
28a9d8f5 3787 {
40fb9820
L		 3788 i.types[op].bitfield.disp64 = 0;
3789 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3790 }
0e1147d9 3791 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3792 && fits_in_unsigned_long (op_disp))
40fb9820 3793 i.types[op].bitfield.disp32 = 1;
b300c311 3794 }
40fb9820
L		 3795 if ((i.types[op].bitfield.disp32
3796 || i.types[op].bitfield.disp32s
3797 || i.types[op].bitfield.disp16)
91d6fa6a 3798 && fits_in_signed_byte (op_disp))
40fb9820 3799 i.types[op].bitfield.disp8 = 1;
252b5132 3800 }
67a4f2b7
AO		 3801 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3802 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3803 {
3804 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3805 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3806 i.types[op].bitfield.disp8 = 0;
3807 i.types[op].bitfield.disp16 = 0;
3808 i.types[op].bitfield.disp32 = 0;
3809 i.types[op].bitfield.disp32s = 0;
3810 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3811 }
3812 else
b300c311 3813 /* We only support 64bit displacement on constants. */
40fb9820 3814 i.types[op].bitfield.disp64 = 0;
252b5132 3815 }
29b0f896
AM		 3816}
3817
43f3e2ee 3818/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 3819 operand types. */
3820
3821static int
3822VEX_check_operands (const insn_template *t)
3823{
3824 if (!t->opcode_modifier.vex)
3825 return 0;
3826
3827 /* Only check VEX_Imm4, which must be the first operand. */
3828 if (t->operand_types[0].bitfield.vec_imm4)
3829 {
3830 if (i.op[0].imms->X_op != O_constant
3831 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 3832 {
a65babc9 3833 i.error = bad_imm4;
891edac4
L		 3834 return 1;
3835 }
a683cc34
SP		 3836
3837 /* Turn off Imm8 so that update_imm won't complain. */
3838 i.types[0] = vec_imm4;
3839 }
3840
3841 return 0;
3842}
3843
d3ce72d0 3844static const insn_template *
e3bb37b5 3845match_template (void)
29b0f896
AM		 3846{
3847 /* Points to template once we've found it. */
d3ce72d0 3848 const insn_template *t;
40fb9820 3849 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3850 i386_operand_type overlap4;
29b0f896 3851 unsigned int found_reverse_match;
40fb9820
L		 3852 i386_opcode_modifier suffix_check;
3853 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3854 int addr_prefix_disp;
a5c311ca 3855 unsigned int j;
3629bb00 3856 unsigned int found_cpu_match;
45664ddb 3857 unsigned int check_register;
29b0f896 3858
c0f3af97
L		 3859#if MAX_OPERANDS != 5
3860# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3861#endif
3862
29b0f896 3863 found_reverse_match = 0;
539e75ad 3864 addr_prefix_disp = -1;
40fb9820
L		 3865
3866 memset (&suffix_check, 0, sizeof (suffix_check));
3867 if (i.suffix == BYTE_MNEM_SUFFIX)
3868 suffix_check.no_bsuf = 1;
3869 else if (i.suffix == WORD_MNEM_SUFFIX)
3870 suffix_check.no_wsuf = 1;
3871 else if (i.suffix == SHORT_MNEM_SUFFIX)
3872 suffix_check.no_ssuf = 1;
3873 else if (i.suffix == LONG_MNEM_SUFFIX)
3874 suffix_check.no_lsuf = 1;
3875 else if (i.suffix == QWORD_MNEM_SUFFIX)
3876 suffix_check.no_qsuf = 1;
3877 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3878 suffix_check.no_ldsuf = 1;
29b0f896 3879
01559ecc
L		 3880 /* Must have right number of operands. */
3881 i.error = number_of_operands_mismatch;
3882
45aa61fe 3883 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3884 {
539e75ad
L		 3885 addr_prefix_disp = -1;
3886
29b0f896
AM		 3887 if (i.operands != t->operands)
3888 continue;
3889
50aecf8c 3890 /* Check processor support. */
a65babc9 3891 i.error = unsupported;
c0f3af97
L		 3892 found_cpu_match = (cpu_flags_match (t)
3893 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3894 if (!found_cpu_match)
3895 continue;
3896
e1d4d893 3897 /* Check old gcc support. */
a65babc9 3898 i.error = old_gcc_only;
e1d4d893
L		 3899 if (!old_gcc && t->opcode_modifier.oldgcc)
3900 continue;
3901
3902 /* Check AT&T mnemonic. */
a65babc9 3903 i.error = unsupported_with_intel_mnemonic;
e1d4d893 3904 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3905 continue;
3906
891edac4 3907 /* Check AT&T/Intel syntax. */
a65babc9 3908 i.error = unsupported_syntax;
5c07affc
L		 3909 if ((intel_syntax && t->opcode_modifier.attsyntax)
3910 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3911 continue;
3912
20592a94 3913 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 3914 i.error = invalid_instruction_suffix;
567e4e96
L		 3915 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3916 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3917 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3918 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3919 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3920 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3921 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3922 continue;
3923
5c07affc 3924 if (!operand_size_match (t))
7d5e4556 3925 continue;
539e75ad 3926
5c07affc
L		 3927 for (j = 0; j < MAX_OPERANDS; j++)
3928 operand_types[j] = t->operand_types[j];
3929
45aa61fe
AM		 3930 /* In general, don't allow 64-bit operands in 32-bit mode. */
3931 if (i.suffix == QWORD_MNEM_SUFFIX
3932 && flag_code != CODE_64BIT
3933 && (intel_syntax
40fb9820 3934 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3935 && !intel_float_operand (t->name))
3936 : intel_float_operand (t->name) != 2)
40fb9820 3937 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3938 && !operand_types[0].bitfield.regxmm
3939 && !operand_types[0].bitfield.regymm)
40fb9820 3940 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3941 && !!operand_types[t->operands > 1].bitfield.regxmm
3942 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3943 && (t->base_opcode != 0x0fc7
3944 || t->extension_opcode != 1 /* cmpxchg8b */))
3945 continue;
3946
192dc9c6
JB		 3947 /* In general, don't allow 32-bit operands on pre-386. */
3948 else if (i.suffix == LONG_MNEM_SUFFIX
3949 && !cpu_arch_flags.bitfield.cpui386
3950 && (intel_syntax
3951 ? (!t->opcode_modifier.ignoresize
3952 && !intel_float_operand (t->name))
3953 : intel_float_operand (t->name) != 2)
3954 && ((!operand_types[0].bitfield.regmmx
3955 && !operand_types[0].bitfield.regxmm)
3956 || (!operand_types[t->operands > 1].bitfield.regmmx
3957 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3958 continue;
3959
29b0f896 3960 /* Do not verify operands when there are none. */
50aecf8c 3961 else
29b0f896 3962 {
c6fb90c8 3963 if (!t->operands)
2dbab7d5
L		 3964 /* We've found a match; break out of loop. */
3965 break;
29b0f896 3966 }
252b5132 3967
539e75ad
L		 3968 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3969 into Disp32/Disp16/Disp32 operand. */
3970 if (i.prefix[ADDR_PREFIX] != 0)
3971 {
40fb9820 3972 /* There should be only one Disp operand. */
539e75ad
L		 3973 switch (flag_code)
3974 {
3975 case CODE_16BIT:
40fb9820
L		 3976 for (j = 0; j < MAX_OPERANDS; j++)
3977 {
3978 if (operand_types[j].bitfield.disp16)
3979 {
3980 addr_prefix_disp = j;
3981 operand_types[j].bitfield.disp32 = 1;
3982 operand_types[j].bitfield.disp16 = 0;
3983 break;
3984 }
3985 }
539e75ad
L		 3986 break;
3987 case CODE_32BIT:
40fb9820
L		 3988 for (j = 0; j < MAX_OPERANDS; j++)
3989 {
3990 if (operand_types[j].bitfield.disp32)
3991 {
3992 addr_prefix_disp = j;
3993 operand_types[j].bitfield.disp32 = 0;
3994 operand_types[j].bitfield.disp16 = 1;
3995 break;
3996 }
3997 }
539e75ad
L		 3998 break;
3999 case CODE_64BIT:
40fb9820
L		 4000 for (j = 0; j < MAX_OPERANDS; j++)
4001 {
4002 if (operand_types[j].bitfield.disp64)
4003 {
4004 addr_prefix_disp = j;
4005 operand_types[j].bitfield.disp64 = 0;
4006 operand_types[j].bitfield.disp32 = 1;
4007 break;
4008 }
4009 }
539e75ad
L		 4010 break;
4011 }
539e75ad
L		 4012 }
4013
56ffb741
L		 4014 /* We check register size if needed. */
4015 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4016 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4017 switch (t->operands)
4018 {
4019 case 1:
40fb9820 4020 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4021 continue;
4022 break;
4023 case 2:
8b38ad71
L		 4024 /* xchg %eax, %eax is a special case. It is an aliase for nop
4025 only in 32bit mode and we can use opcode 0x90. In 64bit
4026 mode, we can't use 0x90 for xchg %eax, %eax since it should
4027 zero-extend %eax to %rax. */
4028 if (flag_code == CODE_64BIT
4029 && t->base_opcode == 0x90
0dfbf9d7
L		 4030 && operand_type_equal (&i.types [0], &acc32)
4031 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4032 continue;
b6169b20
L		 4033 if (i.swap_operand)
4034 {
4035 /* If we swap operand in encoding, we either match
4036 the next one or reverse direction of operands. */
4037 if (t->opcode_modifier.s)
4038 continue;
4039 else if (t->opcode_modifier.d)
4040 goto check_reverse;
4041 }
4042
29b0f896 4043 case 3:
fa99fab2
L		 4044 /* If we swap operand in encoding, we match the next one. */
4045 if (i.swap_operand && t->opcode_modifier.s)
4046 continue;
f48ff2ae 4047 case 4:
c0f3af97 4048 case 5:
c6fb90c8 4049 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4050 if (!operand_type_match (overlap0, i.types[0])
4051 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4052 || (check_register
4053 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4054 operand_types[0],
4055 overlap1, i.types[1],
4056 operand_types[1])))
29b0f896
AM		 4057 {
4058 /* Check if other direction is valid ... */
40fb9820 4059 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4060 continue;
4061
b6169b20 4062check_reverse:
29b0f896 4063 /* Try reversing direction of operands. */
c6fb90c8
L		 4064 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4065 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4066 if (!operand_type_match (overlap0, i.types[0])
4067 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4068 || (check_register
4069 && !operand_type_register_match (overlap0,
4070 i.types[0],
4071 operand_types[1],
4072 overlap1,
4073 i.types[1],
4074 operand_types[0])))
29b0f896
AM		 4075 {
4076 /* Does not match either direction. */
4077 continue;
4078 }
4079 /* found_reverse_match holds which of D or FloatDR
4080 we've found. */
40fb9820 4081 if (t->opcode_modifier.d)
8a2ed489 4082 found_reverse_match = Opcode_D;
40fb9820 4083 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4084 found_reverse_match = Opcode_FloatD;
4085 else
4086 found_reverse_match = 0;
40fb9820 4087 if (t->opcode_modifier.floatr)
8a2ed489 4088 found_reverse_match |= Opcode_FloatR;
29b0f896 4089 }
f48ff2ae 4090 else
29b0f896 4091 {
f48ff2ae 4092 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4093 switch (t->operands)
4094 {
c0f3af97
L		 4095 case 5:
4096 overlap4 = operand_type_and (i.types[4],
4097 operand_types[4]);
d1cbb4db 4098 case 4:
c6fb90c8
L		 4099 overlap3 = operand_type_and (i.types[3],
4100 operand_types[3]);
d1cbb4db 4101 case 3:
c6fb90c8
L		 4102 overlap2 = operand_type_and (i.types[2],
4103 operand_types[2]);
d1cbb4db
L		 4104 break;
4105 }
29b0f896 4106
f48ff2ae
L		 4107 switch (t->operands)
4108 {
c0f3af97
L		 4109 case 5:
4110 if (!operand_type_match (overlap4, i.types[4])
4111 || !operand_type_register_match (overlap3,
4112 i.types[3],
4113 operand_types[3],
4114 overlap4,
4115 i.types[4],
4116 operand_types[4]))
4117 continue;
f48ff2ae 4118 case 4:
40fb9820 4119 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4120 || (check_register
4121 && !operand_type_register_match (overlap2,
4122 i.types[2],
4123 operand_types[2],
4124 overlap3,
4125 i.types[3],
4126 operand_types[3])))
f48ff2ae
L		 4127 continue;
4128 case 3:
4129 /* Here we make use of the fact that there are no
4130 reverse match 3 operand instructions, and all 3
4131 operand instructions only need to be checked for
4132 register consistency between operands 2 and 3. */
40fb9820 4133 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4134 || (check_register
4135 && !operand_type_register_match (overlap1,
4136 i.types[1],
4137 operand_types[1],
4138 overlap2,
4139 i.types[2],
4140 operand_types[2])))
f48ff2ae
L		 4141 continue;
4142 break;
4143 }
29b0f896 4144 }
f48ff2ae 4145 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4146 slip through to break. */
4147 }
3629bb00 4148 if (!found_cpu_match)
29b0f896
AM		 4149 {
4150 found_reverse_match = 0;
4151 continue;
4152 }
c0f3af97 4153
a683cc34
SP		 4154 /* Check if VEX operands are valid. */
4155 if (VEX_check_operands (t))
4156 continue;
4157
29b0f896
AM		 4158 /* We've found a match; break out of loop. */
4159 break;
4160 }
4161
4162 if (t == current_templates->end)
4163 {
4164 /* We found no match. */
a65babc9
L		 4165 const char *err_msg;
4166 switch (i.error)
4167 {
4168 default:
4169 abort ();
86e026a4 4170 case operand_size_mismatch:
a65babc9
L		 4171 err_msg = _("operand size mismatch");
4172 break;
4173 case operand_type_mismatch:
4174 err_msg = _("operand type mismatch");
4175 break;
4176 case register_type_mismatch:
4177 err_msg = _("register type mismatch");
4178 break;
4179 case number_of_operands_mismatch:
4180 err_msg = _("number of operands mismatch");
4181 break;
4182 case invalid_instruction_suffix:
4183 err_msg = _("invalid instruction suffix");
4184 break;
4185 case bad_imm4:
4186 err_msg = _("Imm4 isn't the first operand");
4187 break;
4188 case old_gcc_only:
4189 err_msg = _("only supported with old gcc");
4190 break;
4191 case unsupported_with_intel_mnemonic:
4192 err_msg = _("unsupported with Intel mnemonic");
4193 break;
4194 case unsupported_syntax:
4195 err_msg = _("unsupported syntax");
4196 break;
4197 case unsupported:
4198 err_msg = _("unsupported");
4199 break;
4200 }
4201 as_bad (_("%s for `%s'"), err_msg,
891edac4 4202 current_templates->start->name);
fa99fab2 4203 return NULL;
29b0f896 4204 }
252b5132 4205
29b0f896
AM		 4206 if (!quiet_warnings)
4207 {
4208 if (!intel_syntax
40fb9820
L		 4209 && (i.types[0].bitfield.jumpabsolute
4210 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4211 {
4212 as_warn (_("indirect %s without `*'"), t->name);
4213 }
4214
40fb9820
L		 4215 if (t->opcode_modifier.isprefix
4216 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4217 {
4218 /* Warn them that a data or address size prefix doesn't
4219 affect assembly of the next line of code. */
4220 as_warn (_("stand-alone `%s' prefix"), t->name);
4221 }
4222 }
4223
4224 /* Copy the template we found. */
4225 i.tm = *t;
539e75ad
L		 4226
4227 if (addr_prefix_disp != -1)
4228 i.tm.operand_types[addr_prefix_disp]
4229 = operand_types[addr_prefix_disp];
4230
29b0f896
AM		 4231 if (found_reverse_match)
4232 {
4233 /* If we found a reverse match we must alter the opcode
4234 direction bit. found_reverse_match holds bits to change
4235 (different for int & float insns). */
4236
4237 i.tm.base_opcode ^= found_reverse_match;
4238
539e75ad
L		 4239 i.tm.operand_types[0] = operand_types[1];
4240 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4241 }
4242
fa99fab2 4243 return t;
29b0f896
AM		 4244}
4245
4246static int
e3bb37b5 4247check_string (void)
29b0f896 4248{
40fb9820
L		 4249 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4250 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4251 {
4252 if (i.seg[0] != NULL && i.seg[0] != &es)
4253 {
a87af027 4254 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4255 i.tm.name,
a87af027
JB		 4256 mem_op + 1,
4257 register_prefix);
29b0f896
AM		 4258 return 0;
4259 }
4260 /* There's only ever one segment override allowed per instruction.
4261 This instruction possibly has a legal segment override on the
4262 second operand, so copy the segment to where non-string
4263 instructions store it, allowing common code. */
4264 i.seg[0] = i.seg[1];
4265 }
40fb9820 4266 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4267 {
4268 if (i.seg[1] != NULL && i.seg[1] != &es)
4269 {
a87af027 4270 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4271 i.tm.name,
a87af027
JB		 4272 mem_op + 2,
4273 register_prefix);
29b0f896
AM		 4274 return 0;
4275 }
4276 }
4277 return 1;
4278}
4279
4280static int
543613e9 4281process_suffix (void)
29b0f896
AM		 4282{
4283 /* If matched instruction specifies an explicit instruction mnemonic
4284 suffix, use it. */
40fb9820
L		 4285 if (i.tm.opcode_modifier.size16)
4286 i.suffix = WORD_MNEM_SUFFIX;
4287 else if (i.tm.opcode_modifier.size32)
4288 i.suffix = LONG_MNEM_SUFFIX;
4289 else if (i.tm.opcode_modifier.size64)
4290 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4291 else if (i.reg_operands)
4292 {
4293 /* If there's no instruction mnemonic suffix we try to invent one
4294 based on register operands. */
4295 if (!i.suffix)
4296 {
4297 /* We take i.suffix from the last register operand specified,
4298 Destination register type is more significant than source
381d071f
L		 4299 register type. crc32 in SSE4.2 prefers source register
4300 type. */
4301 if (i.tm.base_opcode == 0xf20f38f1)
4302 {
40fb9820
L		 4303 if (i.types[0].bitfield.reg16)
4304 i.suffix = WORD_MNEM_SUFFIX;
4305 else if (i.types[0].bitfield.reg32)
4306 i.suffix = LONG_MNEM_SUFFIX;
4307 else if (i.types[0].bitfield.reg64)
4308 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4309 }
9344ff29 4310 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4311 {
40fb9820 4312 if (i.types[0].bitfield.reg8)
20592a94
L		 4313 i.suffix = BYTE_MNEM_SUFFIX;
4314 }
381d071f
L		 4315
4316 if (!i.suffix)
4317 {
4318 int op;
4319
20592a94
L		 4320 if (i.tm.base_opcode == 0xf20f38f1
4321 || i.tm.base_opcode == 0xf20f38f0)
4322 {
4323 /* We have to know the operand size for crc32. */
4324 as_bad (_("ambiguous memory operand size for `%s`"),
4325 i.tm.name);
4326 return 0;
4327 }
4328
381d071f 4329 for (op = i.operands; --op >= 0;)
40fb9820 4330 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4331 {
40fb9820
L		 4332 if (i.types[op].bitfield.reg8)
4333 {
4334 i.suffix = BYTE_MNEM_SUFFIX;
4335 break;
4336 }
4337 else if (i.types[op].bitfield.reg16)
4338 {
4339 i.suffix = WORD_MNEM_SUFFIX;
4340 break;
4341 }
4342 else if (i.types[op].bitfield.reg32)
4343 {
4344 i.suffix = LONG_MNEM_SUFFIX;
4345 break;
4346 }
4347 else if (i.types[op].bitfield.reg64)
4348 {
4349 i.suffix = QWORD_MNEM_SUFFIX;
4350 break;
4351 }
381d071f
L		 4352 }
4353 }
29b0f896
AM		 4354 }
4355 else if (i.suffix == BYTE_MNEM_SUFFIX)
4356 {
2eb952a4
L		 4357 if (intel_syntax
4358 && i.tm.opcode_modifier.ignoresize
4359 && i.tm.opcode_modifier.no_bsuf)
4360 i.suffix = 0;
4361 else if (!check_byte_reg ())
29b0f896
AM		 4362 return 0;
4363 }
4364 else if (i.suffix == LONG_MNEM_SUFFIX)
4365 {
2eb952a4
L		 4366 if (intel_syntax
4367 && i.tm.opcode_modifier.ignoresize
4368 && i.tm.opcode_modifier.no_lsuf)
4369 i.suffix = 0;
4370 else if (!check_long_reg ())
29b0f896
AM		 4371 return 0;
4372 }
4373 else if (i.suffix == QWORD_MNEM_SUFFIX)
4374 {
955e1e6a
L		 4375 if (intel_syntax
4376 && i.tm.opcode_modifier.ignoresize
4377 && i.tm.opcode_modifier.no_qsuf)
4378 i.suffix = 0;
4379 else if (!check_qword_reg ())
29b0f896
AM		 4380 return 0;
4381 }
4382 else if (i.suffix == WORD_MNEM_SUFFIX)
4383 {
2eb952a4
L		 4384 if (intel_syntax
4385 && i.tm.opcode_modifier.ignoresize
4386 && i.tm.opcode_modifier.no_wsuf)
4387 i.suffix = 0;
4388 else if (!check_word_reg ())
29b0f896
AM		 4389 return 0;
4390 }
c0f3af97
L		 4391 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4392 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4393 {
c0f3af97 4394 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4395 should check if it is a valid suffix. */
4396 }
40fb9820 4397 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4398 /* Do nothing if the instruction is going to ignore the prefix. */
4399 ;
4400 else
4401 abort ();
4402 }
40fb9820 4403 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4404 && !i.suffix
4405 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4406 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4407 {
4408 i.suffix = stackop_size;
4409 }
9306ca4a
JB		 4410 else if (intel_syntax
4411 && !i.suffix
40fb9820
L		 4412 && (i.tm.operand_types[0].bitfield.jumpabsolute
4413 || i.tm.opcode_modifier.jumpbyte
4414 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4415 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4416 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4417 {
4418 switch (flag_code)
4419 {
4420 case CODE_64BIT:
40fb9820 4421 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4422 {
4423 i.suffix = QWORD_MNEM_SUFFIX;
4424 break;
4425 }
4426 case CODE_32BIT:
40fb9820 4427 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4428 i.suffix = LONG_MNEM_SUFFIX;
4429 break;
4430 case CODE_16BIT:
40fb9820 4431 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4432 i.suffix = WORD_MNEM_SUFFIX;
4433 break;
4434 }
4435 }
252b5132 4436
9306ca4a 4437 if (!i.suffix)
29b0f896 4438 {
9306ca4a
JB		 4439 if (!intel_syntax)
4440 {
40fb9820 4441 if (i.tm.opcode_modifier.w)
9306ca4a 4442 {
4eed87de
AM		 4443 as_bad (_("no instruction mnemonic suffix given and "
4444 "no register operands; can't size instruction"));
9306ca4a
JB		 4445 return 0;
4446 }
4447 }
4448 else
4449 {
40fb9820 4450 unsigned int suffixes;
7ab9ffdd 4451
40fb9820
L		 4452 suffixes = !i.tm.opcode_modifier.no_bsuf;
4453 if (!i.tm.opcode_modifier.no_wsuf)
4454 suffixes |= 1 << 1;
4455 if (!i.tm.opcode_modifier.no_lsuf)
4456 suffixes |= 1 << 2;
fc4adea1 4457 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4458 suffixes |= 1 << 3;
4459 if (!i.tm.opcode_modifier.no_ssuf)
4460 suffixes |= 1 << 4;
4461 if (!i.tm.opcode_modifier.no_qsuf)
4462 suffixes |= 1 << 5;
4463
4464 /* There are more than suffix matches. */
4465 if (i.tm.opcode_modifier.w
9306ca4a 4466 || ((suffixes & (suffixes - 1))
40fb9820
L		 4467 && !i.tm.opcode_modifier.defaultsize
4468 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4469 {
4470 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4471 return 0;
4472 }
4473 }
29b0f896 4474 }
252b5132 4475
9306ca4a
JB		 4476 /* Change the opcode based on the operand size given by i.suffix;
4477 We don't need to change things for byte insns. */
4478
582d5edd
L		 4479 if (i.suffix
4480 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4481 && i.suffix != XMMWORD_MNEM_SUFFIX
4482 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4483 {
4484 /* It's not a byte, select word/dword operation. */
40fb9820 4485 if (i.tm.opcode_modifier.w)
29b0f896 4486 {
40fb9820 4487 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4488 i.tm.base_opcode |= 8;
4489 else
4490 i.tm.base_opcode |= 1;
4491 }
0f3f3d8b 4492
29b0f896
AM		 4493 /* Now select between word & dword operations via the operand
4494 size prefix, except for instructions that will ignore this
4495 prefix anyway. */
ca61edf2 4496 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4497 {
ca61edf2
L		 4498 /* The address size override prefix changes the size of the
4499 first operand. */
40fb9820
L		 4500 if ((flag_code == CODE_32BIT
4501 && i.op->regs[0].reg_type.bitfield.reg16)
4502 || (flag_code != CODE_32BIT
4503 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4504 if (!add_prefix (ADDR_PREFIX_OPCODE))
4505 return 0;
4506 }
4507 else if (i.suffix != QWORD_MNEM_SUFFIX
4508 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4509 && !i.tm.opcode_modifier.ignoresize
4510 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4511 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4512 || (flag_code == CODE_64BIT
40fb9820 4513 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4514 {
4515 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4516
40fb9820 4517 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4518 prefix = ADDR_PREFIX_OPCODE;
252b5132 4519
29b0f896
AM		 4520 if (!add_prefix (prefix))
4521 return 0;
24eab124 4522 }
252b5132 4523
29b0f896
AM		 4524 /* Set mode64 for an operand. */
4525 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4526 && flag_code == CODE_64BIT
40fb9820 4527 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4528 {
4529 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4530 need rex64. cmpxchg8b is also a special case. */
4531 if (! (i.operands == 2
4532 && i.tm.base_opcode == 0x90
4533 && i.tm.extension_opcode == None
0dfbf9d7
L		 4534 && operand_type_equal (&i.types [0], &acc64)
4535 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4536 && ! (i.operands == 1
4537 && i.tm.base_opcode == 0xfc7
4538 && i.tm.extension_opcode == 1
40fb9820
L		 4539 && !operand_type_check (i.types [0], reg)
4540 && operand_type_check (i.types [0], anymem)))
f6bee062 4541 i.rex |= REX_W;
46e883c5 4542 }
3e73aa7c 4543
29b0f896
AM		 4544 /* Size floating point instruction. */
4545 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4546 if (i.tm.opcode_modifier.floatmf)
543613e9 4547 i.tm.base_opcode ^= 4;
29b0f896 4548 }
7ecd2f8b 4549
29b0f896
AM		 4550 return 1;
4551}
3e73aa7c 4552
29b0f896 4553static int
543613e9 4554check_byte_reg (void)
29b0f896
AM		 4555{
4556 int op;
543613e9 4557
29b0f896
AM		 4558 for (op = i.operands; --op >= 0;)
4559 {
4560 /* If this is an eight bit register, it's OK. If it's the 16 or
4561 32 bit version of an eight bit register, we will just use the
4562 low portion, and that's OK too. */
40fb9820 4563 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4564 continue;
4565
9344ff29
L		 4566 /* crc32 doesn't generate this warning. */
4567 if (i.tm.base_opcode == 0xf20f38f0)
4568 continue;
4569
40fb9820
L		 4570 if ((i.types[op].bitfield.reg16
4571 || i.types[op].bitfield.reg32
4572 || i.types[op].bitfield.reg64)
4573 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4574 {
4575 /* Prohibit these changes in the 64bit mode, since the
4576 lowering is more complicated. */
4577 if (flag_code == CODE_64BIT
40fb9820 4578 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4579 {
2ca3ace5
L		 4580 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4581 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4582 i.suffix);
4583 return 0;
4584 }
4585#if REGISTER_WARNINGS
4586 if (!quiet_warnings
40fb9820 4587 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4588 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4589 register_prefix,
40fb9820 4590 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4591 ? REGNAM_AL - REGNAM_AX
4592 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4593 register_prefix,
29b0f896
AM		 4594 i.op[op].regs->reg_name,
4595 i.suffix);
4596#endif
4597 continue;
4598 }
4599 /* Any other register is bad. */
40fb9820
L		 4600 if (i.types[op].bitfield.reg16
4601 || i.types[op].bitfield.reg32
4602 || i.types[op].bitfield.reg64
4603 || i.types[op].bitfield.regmmx
4604 || i.types[op].bitfield.regxmm
c0f3af97 4605 || i.types[op].bitfield.regymm
40fb9820
L		 4606 || i.types[op].bitfield.sreg2
4607 || i.types[op].bitfield.sreg3
4608 || i.types[op].bitfield.control
4609 || i.types[op].bitfield.debug
4610 || i.types[op].bitfield.test
4611 || i.types[op].bitfield.floatreg
4612 || i.types[op].bitfield.floatacc)
29b0f896 4613 {
a540244d
L		 4614 as_bad (_("`%s%s' not allowed with `%s%c'"),
4615 register_prefix,
29b0f896
AM		 4616 i.op[op].regs->reg_name,
4617 i.tm.name,
4618 i.suffix);
4619 return 0;
4620 }
4621 }
4622 return 1;
4623}
4624
4625static int
e3bb37b5 4626check_long_reg (void)
29b0f896
AM		 4627{
4628 int op;
4629
4630 for (op = i.operands; --op >= 0;)
4631 /* Reject eight bit registers, except where the template requires
4632 them. (eg. movzb) */
40fb9820
L		 4633 if (i.types[op].bitfield.reg8
4634 && (i.tm.operand_types[op].bitfield.reg16
4635 || i.tm.operand_types[op].bitfield.reg32
4636 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4637 {
a540244d
L		 4638 as_bad (_("`%s%s' not allowed with `%s%c'"),
4639 register_prefix,
29b0f896
AM		 4640 i.op[op].regs->reg_name,
4641 i.tm.name,
4642 i.suffix);
4643 return 0;
4644 }
4645 /* Warn if the e prefix on a general reg is missing. */
4646 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4647 && i.types[op].bitfield.reg16
4648 && (i.tm.operand_types[op].bitfield.reg32
4649 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4650 {
4651 /* Prohibit these changes in the 64bit mode, since the
4652 lowering is more complicated. */
4653 if (flag_code == CODE_64BIT)
252b5132 4654 {
2ca3ace5
L		 4655 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4656 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4657 i.suffix);
4658 return 0;
252b5132 4659 }
29b0f896
AM		 4660#if REGISTER_WARNINGS
4661 else
a540244d
L		 4662 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4663 register_prefix,
29b0f896 4664 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4665 register_prefix,
29b0f896
AM		 4666 i.op[op].regs->reg_name,
4667 i.suffix);
4668#endif
252b5132 4669 }
29b0f896 4670 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4671 else if (i.types[op].bitfield.reg64
4672 && (i.tm.operand_types[op].bitfield.reg32
4673 || i.tm.operand_types[op].bitfield.acc))
252b5132 4674 {
34828aad 4675 if (intel_syntax
ca61edf2 4676 && i.tm.opcode_modifier.toqword
40fb9820 4677 && !i.types[0].bitfield.regxmm)
34828aad 4678 {
ca61edf2 4679 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4680 i.suffix = QWORD_MNEM_SUFFIX;
4681 }
4682 else
4683 {
4684 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4685 register_prefix, i.op[op].regs->reg_name,
4686 i.suffix);
4687 return 0;
4688 }
29b0f896
AM		 4689 }
4690 return 1;
4691}
252b5132 4692
29b0f896 4693static int
e3bb37b5 4694check_qword_reg (void)
29b0f896
AM		 4695{
4696 int op;
252b5132 4697
29b0f896
AM		 4698 for (op = i.operands; --op >= 0; )
4699 /* Reject eight bit registers, except where the template requires
4700 them. (eg. movzb) */
40fb9820
L		 4701 if (i.types[op].bitfield.reg8
4702 && (i.tm.operand_types[op].bitfield.reg16
4703 || i.tm.operand_types[op].bitfield.reg32
4704 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4705 {
a540244d
L		 4706 as_bad (_("`%s%s' not allowed with `%s%c'"),
4707 register_prefix,
29b0f896
AM		 4708 i.op[op].regs->reg_name,
4709 i.tm.name,
4710 i.suffix);
4711 return 0;
4712 }
4713 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4714 else if ((i.types[op].bitfield.reg16
4715 || i.types[op].bitfield.reg32)
4716 && (i.tm.operand_types[op].bitfield.reg32
4717 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4718 {
4719 /* Prohibit these changes in the 64bit mode, since the
4720 lowering is more complicated. */
34828aad 4721 if (intel_syntax
ca61edf2 4722 && i.tm.opcode_modifier.todword
40fb9820 4723 && !i.types[0].bitfield.regxmm)
34828aad 4724 {
ca61edf2 4725 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4726 i.suffix = LONG_MNEM_SUFFIX;
4727 }
4728 else
4729 {
4730 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4731 register_prefix, i.op[op].regs->reg_name,
4732 i.suffix);
4733 return 0;
4734 }
252b5132 4735 }
29b0f896
AM		 4736 return 1;
4737}
252b5132 4738
29b0f896 4739static int
e3bb37b5 4740check_word_reg (void)
29b0f896
AM		 4741{
4742 int op;
4743 for (op = i.operands; --op >= 0;)
4744 /* Reject eight bit registers, except where the template requires
4745 them. (eg. movzb) */
40fb9820
L		 4746 if (i.types[op].bitfield.reg8
4747 && (i.tm.operand_types[op].bitfield.reg16
4748 || i.tm.operand_types[op].bitfield.reg32
4749 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4750 {
a540244d
L		 4751 as_bad (_("`%s%s' not allowed with `%s%c'"),
4752 register_prefix,
29b0f896
AM		 4753 i.op[op].regs->reg_name,
4754 i.tm.name,
4755 i.suffix);
4756 return 0;
4757 }
4758 /* Warn if the e prefix on a general reg is present. */
4759 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4760 && i.types[op].bitfield.reg32
4761 && (i.tm.operand_types[op].bitfield.reg16
4762 || i.tm.operand_types[op].bitfield.acc))
252b5132 4763 {
29b0f896
AM		 4764 /* Prohibit these changes in the 64bit mode, since the
4765 lowering is more complicated. */
4766 if (flag_code == CODE_64BIT)
252b5132 4767 {
2ca3ace5
L		 4768 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4769 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4770 i.suffix);
4771 return 0;
252b5132 4772 }
29b0f896
AM		 4773 else
4774#if REGISTER_WARNINGS
a540244d
L		 4775 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4776 register_prefix,
29b0f896 4777 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4778 register_prefix,
29b0f896
AM		 4779 i.op[op].regs->reg_name,
4780 i.suffix);
4781#endif
4782 }
4783 return 1;
4784}
252b5132 4785
29b0f896 4786static int
40fb9820 4787update_imm (unsigned int j)
29b0f896 4788{
bc0844ae 4789 i386_operand_type overlap = i.types[j];
40fb9820
L		 4790 if ((overlap.bitfield.imm8
4791 || overlap.bitfield.imm8s
4792 || overlap.bitfield.imm16
4793 || overlap.bitfield.imm32
4794 || overlap.bitfield.imm32s
4795 || overlap.bitfield.imm64)
0dfbf9d7
L		 4796 && !operand_type_equal (&overlap, &imm8)
4797 && !operand_type_equal (&overlap, &imm8s)
4798 && !operand_type_equal (&overlap, &imm16)
4799 && !operand_type_equal (&overlap, &imm32)
4800 && !operand_type_equal (&overlap, &imm32s)
4801 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4802 {
4803 if (i.suffix)
4804 {
40fb9820
L		 4805 i386_operand_type temp;
4806
0dfbf9d7 4807 operand_type_set (&temp, 0);
7ab9ffdd 4808 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4809 {
4810 temp.bitfield.imm8 = overlap.bitfield.imm8;
4811 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4812 }
4813 else if (i.suffix == WORD_MNEM_SUFFIX)
4814 temp.bitfield.imm16 = overlap.bitfield.imm16;
4815 else if (i.suffix == QWORD_MNEM_SUFFIX)
4816 {
4817 temp.bitfield.imm64 = overlap.bitfield.imm64;
4818 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4819 }
4820 else
4821 temp.bitfield.imm32 = overlap.bitfield.imm32;
4822 overlap = temp;
29b0f896 4823 }
0dfbf9d7
L		 4824 else if (operand_type_equal (&overlap, &imm16_32_32s)
4825 || operand_type_equal (&overlap, &imm16_32)
4826 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4827 {
40fb9820 4828 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4829 overlap = imm16;
40fb9820 4830 else
65da13b5 4831 overlap = imm32s;
29b0f896 4832 }
0dfbf9d7
L		 4833 if (!operand_type_equal (&overlap, &imm8)
4834 && !operand_type_equal (&overlap, &imm8s)
4835 && !operand_type_equal (&overlap, &imm16)
4836 && !operand_type_equal (&overlap, &imm32)
4837 && !operand_type_equal (&overlap, &imm32s)
4838 && !operand_type_equal (&overlap, &imm64))
29b0f896 4839 {
4eed87de
AM		 4840 as_bad (_("no instruction mnemonic suffix given; "
4841 "can't determine immediate size"));
29b0f896
AM		 4842 return 0;
4843 }
4844 }
40fb9820 4845 i.types[j] = overlap;
29b0f896 4846
40fb9820
L		 4847 return 1;
4848}
4849
4850static int
4851finalize_imm (void)
4852{
bc0844ae 4853 unsigned int j, n;
29b0f896 4854
bc0844ae
L		 4855 /* Update the first 2 immediate operands. */
4856 n = i.operands > 2 ? 2 : i.operands;
4857 if (n)
4858 {
4859 for (j = 0; j < n; j++)
4860 if (update_imm (j) == 0)
4861 return 0;
40fb9820 4862
bc0844ae
L		 4863 /* The 3rd operand can't be immediate operand. */
4864 gas_assert (operand_type_check (i.types[2], imm) == 0);
4865 }
29b0f896
AM		 4866
4867 return 1;
4868}
4869
c0f3af97
L		 4870static int
4871bad_implicit_operand (int xmm)
4872{
91d6fa6a
NC		 4873 const char *ireg = xmm ? "xmm0" : "ymm0";
4874
c0f3af97
L		 4875 if (intel_syntax)
4876 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4877 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4878 else
4879 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4880 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4881 return 0;
4882}
4883
29b0f896 4884static int
e3bb37b5 4885process_operands (void)
29b0f896
AM		 4886{
4887 /* Default segment register this instruction will use for memory
4888 accesses. 0 means unknown. This is only for optimizing out
4889 unnecessary segment overrides. */
4890 const seg_entry *default_seg = 0;
4891
2426c15f 4892 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 4893 {
91d6fa6a
NC		 4894 unsigned int dupl = i.operands;
4895 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4896 unsigned int j;
4897
c0f3af97 4898 /* The destination must be an xmm register. */
9c2799c2 4899 gas_assert (i.reg_operands
91d6fa6a 4900 && MAX_OPERANDS > dupl
7ab9ffdd 4901 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4902
4903 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4904 {
c0f3af97 4905 /* The first operand is implicit and must be xmm0. */
9c2799c2 4906 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4907 if (i.op[0].regs->reg_num != 0)
4908 return bad_implicit_operand (1);
4909
8cd7925b 4910 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 4911 {
4912 /* Keep xmm0 for instructions with VEX prefix and 3
4913 sources. */
4914 goto duplicate;
4915 }
e2ec9d29 4916 else
c0f3af97
L		 4917 {
4918 /* We remove the first xmm0 and keep the number of
4919 operands unchanged, which in fact duplicates the
4920 destination. */
4921 for (j = 1; j < i.operands; j++)
4922 {
4923 i.op[j - 1] = i.op[j];
4924 i.types[j - 1] = i.types[j];
4925 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4926 }
4927 }
4928 }
4929 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4930 {
91d6fa6a 4931 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 4932 && (i.tm.opcode_modifier.vexsources
4933 == VEX3SOURCES));
c0f3af97
L		 4934
4935 /* Add the implicit xmm0 for instructions with VEX prefix
4936 and 3 sources. */
4937 for (j = i.operands; j > 0; j--)
4938 {
4939 i.op[j] = i.op[j - 1];
4940 i.types[j] = i.types[j - 1];
4941 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4942 }
4943 i.op[0].regs
4944 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4945 i.types[0] = regxmm;
c0f3af97
L		 4946 i.tm.operand_types[0] = regxmm;
4947
4948 i.operands += 2;
4949 i.reg_operands += 2;
4950 i.tm.operands += 2;
4951
91d6fa6a 4952 dupl++;
c0f3af97 4953 dest++;
91d6fa6a
NC		 4954 i.op[dupl] = i.op[dest];
4955 i.types[dupl] = i.types[dest];
4956 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 4957 }
c0f3af97
L		 4958 else
4959 {
4960duplicate:
4961 i.operands++;
4962 i.reg_operands++;
4963 i.tm.operands++;
4964
91d6fa6a
NC		 4965 i.op[dupl] = i.op[dest];
4966 i.types[dupl] = i.types[dest];
4967 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 4968 }
4969
4970 if (i.tm.opcode_modifier.immext)
4971 process_immext ();
4972 }
4973 else if (i.tm.opcode_modifier.firstxmm0)
4974 {
4975 unsigned int j;
4976
4977 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4978 gas_assert (i.reg_operands
7ab9ffdd
L		 4979 && (operand_type_equal (&i.types[0], &regxmm)
4980 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4981 if (i.op[0].regs->reg_num != 0)
4982 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4983
4984 for (j = 1; j < i.operands; j++)
4985 {
4986 i.op[j - 1] = i.op[j];
4987 i.types[j - 1] = i.types[j];
4988
4989 /* We need to adjust fields in i.tm since they are used by
4990 build_modrm_byte. */
4991 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4992 }
4993
e2ec9d29
L		 4994 i.operands--;
4995 i.reg_operands--;
e2ec9d29
L		 4996 i.tm.operands--;
4997 }
4998 else if (i.tm.opcode_modifier.regkludge)
4999 {
5000 /* The imul $imm, %reg instruction is converted into
5001 imul $imm, %reg, %reg, and the clr %reg instruction
5002 is converted into xor %reg, %reg. */
5003
5004 unsigned int first_reg_op;
5005
5006 if (operand_type_check (i.types[0], reg))
5007 first_reg_op = 0;
5008 else
5009 first_reg_op = 1;
5010 /* Pretend we saw the extra register operand. */
9c2799c2 5011 gas_assert (i.reg_operands == 1
7ab9ffdd 5012 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5013 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5014 i.types[first_reg_op + 1] = i.types[first_reg_op];
5015 i.operands++;
5016 i.reg_operands++;
29b0f896
AM		 5017 }
5018
40fb9820 5019 if (i.tm.opcode_modifier.shortform)
29b0f896 5020 {
40fb9820
L		 5021 if (i.types[0].bitfield.sreg2
5022 || i.types[0].bitfield.sreg3)
29b0f896 5023 {
4eed87de
AM		 5024 if (i.tm.base_opcode == POP_SEG_SHORT
5025 && i.op[0].regs->reg_num == 1)
29b0f896 5026 {
a87af027 5027 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5028 return 0;
29b0f896 5029 }
4eed87de
AM		 5030 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5031 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5032 i.rex |= REX_B;
4eed87de
AM		 5033 }
5034 else
5035 {
7ab9ffdd 5036 /* The register or float register operand is in operand
85f10a01 5037 0 or 1. */
40fb9820 5038 unsigned int op;
7ab9ffdd
L		 5039
5040 if (i.types[0].bitfield.floatreg
5041 || operand_type_check (i.types[0], reg))
5042 op = 0;
5043 else
5044 op = 1;
4eed87de
AM		 5045 /* Register goes in low 3 bits of opcode. */
5046 i.tm.base_opcode |= i.op[op].regs->reg_num;
5047 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5048 i.rex |= REX_B;
40fb9820 5049 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5050 {
4eed87de
AM		 5051 /* Warn about some common errors, but press on regardless.
5052 The first case can be generated by gcc (<= 2.8.1). */
5053 if (i.operands == 2)
5054 {
5055 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5056 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5057 register_prefix, i.op[!intel_syntax].regs->reg_name,
5058 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5059 }
5060 else
5061 {
5062 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5063 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5064 register_prefix, i.op[0].regs->reg_name);
4eed87de 5065 }
29b0f896
AM		 5066 }
5067 }
5068 }
40fb9820 5069 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5070 {
5071 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5072 must be put into the modrm byte). Now, we make the modrm and
5073 index base bytes based on all the info we've collected. */
29b0f896
AM		 5074
5075 default_seg = build_modrm_byte ();
5076 }
8a2ed489 5077 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5078 {
5079 default_seg = &ds;
5080 }
40fb9820 5081 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5082 {
5083 /* For the string instructions that allow a segment override
5084 on one of their operands, the default segment is ds. */
5085 default_seg = &ds;
5086 }
5087
75178d9d
L		 5088 if (i.tm.base_opcode == 0x8d /* lea */
5089 && i.seg[0]
5090 && !quiet_warnings)
30123838 5091 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5092
5093 /* If a segment was explicitly specified, and the specified segment
5094 is not the default, use an opcode prefix to select it. If we
5095 never figured out what the default segment is, then default_seg
5096 will be zero at this point, and the specified segment prefix will
5097 always be used. */
29b0f896
AM		 5098 if ((i.seg[0]) && (i.seg[0] != default_seg))
5099 {
5100 if (!add_prefix (i.seg[0]->seg_prefix))
5101 return 0;
5102 }
5103 return 1;
5104}
5105
5106static const seg_entry *
e3bb37b5 5107build_modrm_byte (void)
29b0f896
AM		 5108{
5109 const seg_entry *default_seg = 0;
c0f3af97 5110 unsigned int source, dest;
8cd7925b 5111 int vex_3_sources;
c0f3af97
L		 5112
5113 /* The first operand of instructions with VEX prefix and 3 sources
5114 must be VEX_Imm4. */
8cd7925b 5115 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5116 if (vex_3_sources)
5117 {
91d6fa6a 5118 unsigned int nds, reg_slot;
4c2c6516 5119 expressionS *exp;
c0f3af97 5120
922d8de8 5121 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5122 && i.tm.opcode_modifier.immext)
5123 {
5124 dest = i.operands - 2;
5125 gas_assert (dest == 3);
5126 }
922d8de8 5127 else
a683cc34 5128 dest = i.operands - 1;
c0f3af97 5129 nds = dest - 1;
922d8de8 5130
a683cc34
SP		 5131 /* There are 2 kinds of instructions:
5132 1. 5 operands: 4 register operands or 3 register operands
5133 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5134 VexW0 or VexW1. The destination must be either XMM or YMM
5135 register.
5136 2. 4 operands: 4 register operands or 3 register operands
5137 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5138 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5139 || (i.reg_operands == 3 && i.mem_operands == 1))
5140 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5141 && (i.tm.opcode_modifier.veximmext
5142 || (i.imm_operands == 1
5143 && i.types[0].bitfield.vec_imm4
5144 && (i.tm.opcode_modifier.vexw == VEXW0
5145 || i.tm.opcode_modifier.vexw == VEXW1)
5146 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5147 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5148
5149 if (i.imm_operands == 0)
5150 {
5151 /* When there is no immediate operand, generate an 8bit
5152 immediate operand to encode the first operand. */
5153 exp = &im_expressions[i.imm_operands++];
5154 i.op[i.operands].imms = exp;
5155 i.types[i.operands] = imm8;
5156 i.operands++;
5157 /* If VexW1 is set, the first operand is the source and
5158 the second operand is encoded in the immediate operand. */
5159 if (i.tm.opcode_modifier.vexw == VEXW1)
5160 {
5161 source = 0;
5162 reg_slot = 1;
5163 }
5164 else
5165 {
5166 source = 1;
5167 reg_slot = 0;
5168 }
5169
5170 /* FMA swaps REG and NDS. */
5171 if (i.tm.cpu_flags.bitfield.cpufma)
5172 {
5173 unsigned int tmp;
5174 tmp = reg_slot;
5175 reg_slot = nds;
5176 nds = tmp;
5177 }
5178
24981e7b
L		 5179 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5180 &regxmm)
a683cc34
SP		 5181 || operand_type_equal (&i.tm.operand_types[reg_slot],
5182 &regymm));
5183 exp->X_op = O_constant;
5184 exp->X_add_number
5185 = ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5186 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5187 << 4);
a683cc34 5188 }
922d8de8 5189 else
a683cc34
SP		 5190 {
5191 unsigned int imm_slot;
5192
5193 if (i.tm.opcode_modifier.vexw == VEXW0)
5194 {
5195 /* If VexW0 is set, the third operand is the source and
5196 the second operand is encoded in the immediate
5197 operand. */
5198 source = 2;
5199 reg_slot = 1;
5200 }
5201 else
5202 {
5203 /* VexW1 is set, the second operand is the source and
5204 the third operand is encoded in the immediate
5205 operand. */
5206 source = 1;
5207 reg_slot = 2;
5208 }
5209
5210 if (i.tm.opcode_modifier.immext)
5211 {
5212 /* When ImmExt is set, the immdiate byte is the last
5213 operand. */
5214 imm_slot = i.operands - 1;
5215 source--;
5216 reg_slot--;
5217 }
5218 else
5219 {
5220 imm_slot = 0;
5221
5222 /* Turn on Imm8 so that output_imm will generate it. */
5223 i.types[imm_slot].bitfield.imm8 = 1;
5224 }
5225
24981e7b
L		 5226 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5227 &regxmm)
5228 || operand_type_equal (&i.tm.operand_types[reg_slot],
5229 &regymm));
a683cc34
SP		 5230 i.op[imm_slot].imms->X_add_number
5231 |= ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5232 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5233 << 4);
a683cc34
SP		 5234 }
5235
5236 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5237 || operand_type_equal (&i.tm.operand_types[nds],
5238 &regymm));
dae39acc 5239 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5240 }
5241 else
5242 source = dest = 0;
29b0f896
AM		 5243
5244 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5245 implicit registers do not count. If there are 3 register
5246 operands, it must be a instruction with VexNDS. For a
5247 instruction with VexNDD, the destination register is encoded
5248 in VEX prefix. If there are 4 register operands, it must be
5249 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5250 if (i.mem_operands == 0
5251 && ((i.reg_operands == 2
2426c15f 5252 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5253 || (i.reg_operands == 3
2426c15f 5254 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5255 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5256 {
cab737b9
L		 5257 switch (i.operands)
5258 {
5259 case 2:
5260 source = 0;
5261 break;
5262 case 3:
c81128dc
L		 5263 /* When there are 3 operands, one of them may be immediate,
5264 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5265 the first operand must be shift count register (cl) or it
5266 is an instruction with VexNDS. */
9c2799c2 5267 gas_assert (i.imm_operands == 1
7ab9ffdd 5268 || (i.imm_operands == 0
2426c15f 5269 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5270 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5271 if (operand_type_check (i.types[0], imm)
5272 || i.types[0].bitfield.shiftcount)
5273 source = 1;
5274 else
5275 source = 0;
cab737b9
L		 5276 break;
5277 case 4:
368d64cc
L		 5278 /* When there are 4 operands, the first two must be 8bit
5279 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5280 one.
5281
5282 For instructions with VexNDS, if the first operand
5283 an imm8, the source operand is the 2nd one. If the last
5284 operand is imm8, the source operand is the first one. */
9c2799c2 5285 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5286 && i.types[0].bitfield.imm8
5287 && i.types[1].bitfield.imm8)
2426c15f 5288 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5289 && i.imm_operands == 1
5290 && (i.types[0].bitfield.imm8
5291 || i.types[i.operands - 1].bitfield.imm8)));
9f2670f2
L		 5292 if (i.imm_operands == 2)
5293 source = 2;
5294 else
c0f3af97
L		 5295 {
5296 if (i.types[0].bitfield.imm8)
5297 source = 1;
5298 else
5299 source = 0;
5300 }
c0f3af97
L		 5301 break;
5302 case 5:
cab737b9
L		 5303 break;
5304 default:
5305 abort ();
5306 }
5307
c0f3af97
L		 5308 if (!vex_3_sources)
5309 {
5310 dest = source + 1;
5311
2426c15f 5312 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5313 {
5314 /* For instructions with VexNDS, the register-only
f12dc422
L		 5315 source operand must be 32/64bit integer, XMM or
5316 YMM register. It is encoded in VEX prefix. We
5317 need to clear RegMem bit before calling
5318 operand_type_equal. */
5319
5320 i386_operand_type op;
5321 unsigned int vvvv;
5322
5323 /* Check register-only source operand when two source
5324 operands are swapped. */
5325 if (!i.tm.operand_types[source].bitfield.baseindex
5326 && i.tm.operand_types[dest].bitfield.baseindex)
5327 {
5328 vvvv = source;
5329 source = dest;
5330 }
5331 else
5332 vvvv = dest;
5333
5334 op = i.tm.operand_types[vvvv];
fa99fab2 5335 op.bitfield.regmem = 0;
c0f3af97 5336 if ((dest + 1) >= i.operands
f12dc422
L		 5337 || (op.bitfield.reg32 != 1
5338 && !op.bitfield.reg64 != 1
5339 && !operand_type_equal (&op, &regxmm)
fa99fab2 5340 && !operand_type_equal (&op, &regymm)))
c0f3af97 5341 abort ();
f12dc422 5342 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 5343 dest++;
5344 }
5345 }
29b0f896
AM		 5346
5347 i.rm.mode = 3;
5348 /* One of the register operands will be encoded in the i.tm.reg
5349 field, the other in the combined i.tm.mode and i.tm.regmem
5350 fields. If no form of this instruction supports a memory
5351 destination operand, then we assume the source operand may
5352 sometimes be a memory operand and so we need to store the
5353 destination in the i.rm.reg field. */
40fb9820
L		 5354 if (!i.tm.operand_types[dest].bitfield.regmem
5355 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5356 {
5357 i.rm.reg = i.op[dest].regs->reg_num;
5358 i.rm.regmem = i.op[source].regs->reg_num;
5359 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5360 i.rex |= REX_R;
29b0f896 5361 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5362 i.rex |= REX_B;
29b0f896
AM		 5363 }
5364 else
5365 {
5366 i.rm.reg = i.op[source].regs->reg_num;
5367 i.rm.regmem = i.op[dest].regs->reg_num;
5368 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5369 i.rex |= REX_B;
29b0f896 5370 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5371 i.rex |= REX_R;
29b0f896 5372 }
161a04f6 5373 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5374 {
40fb9820
L		 5375 if (!i.types[0].bitfield.control
5376 && !i.types[1].bitfield.control)
c4a530c5 5377 abort ();
161a04f6 5378 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5379 add_prefix (LOCK_PREFIX_OPCODE);
5380 }
29b0f896
AM		 5381 }
5382 else
5383 { /* If it's not 2 reg operands... */
c0f3af97
L		 5384 unsigned int mem;
5385
29b0f896
AM		 5386 if (i.mem_operands)
5387 {
5388 unsigned int fake_zero_displacement = 0;
99018f42 5389 unsigned int op;
4eed87de 5390
7ab9ffdd
L		 5391 for (op = 0; op < i.operands; op++)
5392 if (operand_type_check (i.types[op], anymem))
5393 break;
7ab9ffdd 5394 gas_assert (op < i.operands);
29b0f896
AM		 5395
5396 default_seg = &ds;
5397
5398 if (i.base_reg == 0)
5399 {
5400 i.rm.mode = 0;
5401 if (!i.disp_operands)
5402 fake_zero_displacement = 1;
5403 if (i.index_reg == 0)
5404 {
5405 /* Operand is just <disp> */
20f0a1fc 5406 if (flag_code == CODE_64BIT)
29b0f896
AM		 5407 {
5408 /* 64bit mode overwrites the 32bit absolute
5409 addressing by RIP relative addressing and
5410 absolute addressing is encoded by one of the
5411 redundant SIB forms. */
5412 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5413 i.sib.base = NO_BASE_REGISTER;
5414 i.sib.index = NO_INDEX_REGISTER;
fc225355 5415 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5416 ? disp32s : disp32);
20f0a1fc 5417 }
fc225355
L		 5418 else if ((flag_code == CODE_16BIT)
5419 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5420 {
5421 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5422 i.types[op] = disp16;
20f0a1fc
NC		 5423 }
5424 else
5425 {
5426 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5427 i.types[op] = disp32;
29b0f896
AM		 5428 }
5429 }
5430 else /* !i.base_reg && i.index_reg */
5431 {
db51cc60
L		 5432 if (i.index_reg->reg_num == RegEiz
5433 || i.index_reg->reg_num == RegRiz)
5434 i.sib.index = NO_INDEX_REGISTER;
5435 else
5436 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5437 i.sib.base = NO_BASE_REGISTER;
5438 i.sib.scale = i.log2_scale_factor;
5439 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5440 i.types[op].bitfield.disp8 = 0;
5441 i.types[op].bitfield.disp16 = 0;
5442 i.types[op].bitfield.disp64 = 0;
29b0f896 5443 if (flag_code != CODE_64BIT)
40fb9820
L		 5444 {
5445 /* Must be 32 bit */
5446 i.types[op].bitfield.disp32 = 1;
5447 i.types[op].bitfield.disp32s = 0;
5448 }
29b0f896 5449 else
40fb9820
L		 5450 {
5451 i.types[op].bitfield.disp32 = 0;
5452 i.types[op].bitfield.disp32s = 1;
5453 }
29b0f896 5454 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5455 i.rex |= REX_X;
29b0f896
AM		 5456 }
5457 }
5458 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5459 else if (i.base_reg->reg_num == RegRip ||
5460 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5461 {
5462 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5463 i.types[op].bitfield.disp8 = 0;
5464 i.types[op].bitfield.disp16 = 0;
5465 i.types[op].bitfield.disp32 = 0;
5466 i.types[op].bitfield.disp32s = 1;
5467 i.types[op].bitfield.disp64 = 0;
71903a11 5468 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5469 if (! i.disp_operands)
5470 fake_zero_displacement = 1;
29b0f896 5471 }
40fb9820 5472 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5473 {
5474 switch (i.base_reg->reg_num)
5475 {
5476 case 3: /* (%bx) */
5477 if (i.index_reg == 0)
5478 i.rm.regmem = 7;
5479 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5480 i.rm.regmem = i.index_reg->reg_num - 6;
5481 break;
5482 case 5: /* (%bp) */
5483 default_seg = &ss;
5484 if (i.index_reg == 0)
5485 {
5486 i.rm.regmem = 6;
40fb9820 5487 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5488 {
5489 /* fake (%bp) into 0(%bp) */
40fb9820 5490 i.types[op].bitfield.disp8 = 1;
252b5132 5491 fake_zero_displacement = 1;
29b0f896
AM		 5492 }
5493 }
5494 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5495 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5496 break;
5497 default: /* (%si) -> 4 or (%di) -> 5 */
5498 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5499 }
5500 i.rm.mode = mode_from_disp_size (i.types[op]);
5501 }
5502 else /* i.base_reg and 32/64 bit mode */
5503 {
5504 if (flag_code == CODE_64BIT
40fb9820
L		 5505 && operand_type_check (i.types[op], disp))
5506 {
5507 i386_operand_type temp;
0dfbf9d7 5508 operand_type_set (&temp, 0);
40fb9820
L		 5509 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5510 i.types[op] = temp;
5511 if (i.prefix[ADDR_PREFIX] == 0)
5512 i.types[op].bitfield.disp32s = 1;
5513 else
5514 i.types[op].bitfield.disp32 = 1;
5515 }
20f0a1fc 5516
29b0f896
AM		 5517 i.rm.regmem = i.base_reg->reg_num;
5518 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5519 i.rex |= REX_B;
29b0f896
AM		 5520 i.sib.base = i.base_reg->reg_num;
5521 /* x86-64 ignores REX prefix bit here to avoid decoder
5522 complications. */
5523 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5524 {
5525 default_seg = &ss;
5526 if (i.disp_operands == 0)
5527 {
5528 fake_zero_displacement = 1;
40fb9820 5529 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5530 }
5531 }
5532 else if (i.base_reg->reg_num == ESP_REG_NUM)
5533 {
5534 default_seg = &ss;
5535 }
5536 i.sib.scale = i.log2_scale_factor;
5537 if (i.index_reg == 0)
5538 {
5539 /* <disp>(%esp) becomes two byte modrm with no index
5540 register. We've already stored the code for esp
5541 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5542 Any base register besides %esp will not use the
5543 extra modrm byte. */
5544 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5545 }
5546 else
5547 {
db51cc60
L		 5548 if (i.index_reg->reg_num == RegEiz
5549 || i.index_reg->reg_num == RegRiz)
5550 i.sib.index = NO_INDEX_REGISTER;
5551 else
5552 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5553 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5554 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5555 i.rex |= REX_X;
29b0f896 5556 }
67a4f2b7
AO		 5557
5558 if (i.disp_operands
5559 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5560 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5561 i.rm.mode = 0;
5562 else
5563 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5564 }
252b5132 5565
29b0f896
AM		 5566 if (fake_zero_displacement)
5567 {
5568 /* Fakes a zero displacement assuming that i.types[op]
5569 holds the correct displacement size. */
5570 expressionS *exp;
5571
9c2799c2 5572 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5573 exp = &disp_expressions[i.disp_operands++];
5574 i.op[op].disps = exp;
5575 exp->X_op = O_constant;
5576 exp->X_add_number = 0;
5577 exp->X_add_symbol = (symbolS *) 0;
5578 exp->X_op_symbol = (symbolS *) 0;
5579 }
c0f3af97
L		 5580
5581 mem = op;
29b0f896 5582 }
c0f3af97
L		 5583 else
5584 mem = ~0;
252b5132 5585
8c43a48b 5586 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5587 {
5588 if (operand_type_check (i.types[0], imm))
5589 i.vex.register_specifier = NULL;
5590 else
5591 {
5592 /* VEX.vvvv encodes one of the sources when the first
5593 operand is not an immediate. */
1ef99a7b 5594 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5595 i.vex.register_specifier = i.op[0].regs;
5596 else
5597 i.vex.register_specifier = i.op[1].regs;
5598 }
5599
5600 /* Destination is a XMM register encoded in the ModRM.reg
5601 and VEX.R bit. */
5602 i.rm.reg = i.op[2].regs->reg_num;
5603 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5604 i.rex |= REX_R;
5605
5606 /* ModRM.rm and VEX.B encodes the other source. */
5607 if (!i.mem_operands)
5608 {
5609 i.rm.mode = 3;
5610
1ef99a7b 5611 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5612 i.rm.regmem = i.op[1].regs->reg_num;
5613 else
5614 i.rm.regmem = i.op[0].regs->reg_num;
5615
5616 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5617 i.rex |= REX_B;
5618 }
5619 }
2426c15f 5620 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5621 {
5622 i.vex.register_specifier = i.op[2].regs;
5623 if (!i.mem_operands)
5624 {
5625 i.rm.mode = 3;
5626 i.rm.regmem = i.op[1].regs->reg_num;
5627 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5628 i.rex |= REX_B;
5629 }
5630 }
29b0f896
AM		 5631 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5632 (if any) based on i.tm.extension_opcode. Again, we must be
5633 careful to make sure that segment/control/debug/test/MMX
5634 registers are coded into the i.rm.reg field. */
f88c9eb0 5635 else if (i.reg_operands)
29b0f896 5636 {
99018f42 5637 unsigned int op;
7ab9ffdd
L		 5638 unsigned int vex_reg = ~0;
5639
5640 for (op = 0; op < i.operands; op++)
5641 if (i.types[op].bitfield.reg8
5642 || i.types[op].bitfield.reg16
5643 || i.types[op].bitfield.reg32
5644 || i.types[op].bitfield.reg64
5645 || i.types[op].bitfield.regmmx
5646 || i.types[op].bitfield.regxmm
5647 || i.types[op].bitfield.regymm
5648 || i.types[op].bitfield.sreg2
5649 || i.types[op].bitfield.sreg3
5650 || i.types[op].bitfield.control
5651 || i.types[op].bitfield.debug
5652 || i.types[op].bitfield.test)
5653 break;
c0209578 5654
7ab9ffdd
L		 5655 if (vex_3_sources)
5656 op = dest;
2426c15f 5657 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5658 {
5659 /* For instructions with VexNDS, the register-only
5660 source operand is encoded in VEX prefix. */
5661 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5662
7ab9ffdd 5663 if (op > mem)
c0f3af97 5664 {
7ab9ffdd
L		 5665 vex_reg = op++;
5666 gas_assert (op < i.operands);
c0f3af97
L		 5667 }
5668 else
c0f3af97 5669 {
f12dc422
L		 5670 /* Check register-only source operand when two source
5671 operands are swapped. */
5672 if (!i.tm.operand_types[op].bitfield.baseindex
5673 && i.tm.operand_types[op + 1].bitfield.baseindex)
5674 {
5675 vex_reg = op;
5676 op += 2;
5677 gas_assert (mem == (vex_reg + 1)
5678 && op < i.operands);
5679 }
5680 else
5681 {
5682 vex_reg = op + 1;
5683 gas_assert (vex_reg < i.operands);
5684 }
c0f3af97 5685 }
7ab9ffdd 5686 }
2426c15f 5687 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 5688 {
f12dc422 5689 /* For instructions with VexNDD, the register destination
7ab9ffdd 5690 is encoded in VEX prefix. */
f12dc422
L		 5691 if (i.mem_operands == 0)
5692 {
5693 /* There is no memory operand. */
5694 gas_assert ((op + 2) == i.operands);
5695 vex_reg = op + 1;
5696 }
5697 else
5698 {
5699 /* There are only 2 operands. */
5700 gas_assert (op < 2 && i.operands == 2);
5701 vex_reg = 1;
5702 }
7ab9ffdd
L		 5703 }
5704 else
5705 gas_assert (op < i.operands);
99018f42 5706
7ab9ffdd
L		 5707 if (vex_reg != (unsigned int) ~0)
5708 {
f12dc422 5709 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 5710
f12dc422
L		 5711 if (type->bitfield.reg32 != 1
5712 && type->bitfield.reg64 != 1
5713 && !operand_type_equal (type, &regxmm)
5714 && !operand_type_equal (type, &regymm))
7ab9ffdd 5715 abort ();
f88c9eb0 5716
7ab9ffdd
L		 5717 i.vex.register_specifier = i.op[vex_reg].regs;
5718 }
5719
1b9f0c97
L		 5720 /* Don't set OP operand twice. */
5721 if (vex_reg != op)
7ab9ffdd 5722 {
1b9f0c97
L		 5723 /* If there is an extension opcode to put here, the
5724 register number must be put into the regmem field. */
5725 if (i.tm.extension_opcode != None)
5726 {
5727 i.rm.regmem = i.op[op].regs->reg_num;
5728 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5729 i.rex |= REX_B;
5730 }
5731 else
5732 {
5733 i.rm.reg = i.op[op].regs->reg_num;
5734 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5735 i.rex |= REX_R;
5736 }
7ab9ffdd 5737 }
252b5132 5738
29b0f896
AM		 5739 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5740 must set it to 3 to indicate this is a register operand
5741 in the regmem field. */
5742 if (!i.mem_operands)
5743 i.rm.mode = 3;
5744 }
252b5132 5745
29b0f896 5746 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5747 if (i.tm.extension_opcode != None)
29b0f896
AM		 5748 i.rm.reg = i.tm.extension_opcode;
5749 }
5750 return default_seg;
5751}
252b5132 5752
29b0f896 5753static void
e3bb37b5 5754output_branch (void)
29b0f896
AM		 5755{
5756 char *p;
f8a5c266 5757 int size;
29b0f896
AM		 5758 int code16;
5759 int prefix;
5760 relax_substateT subtype;
5761 symbolS *sym;
5762 offsetT off;
5763
f8a5c266
L		 5764 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
5765 size = i.disp32_encoding ? BIG : SMALL;
29b0f896
AM		 5766
5767 prefix = 0;
5768 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5769 {
29b0f896
AM		 5770 prefix = 1;
5771 i.prefixes -= 1;
5772 code16 ^= CODE16;
252b5132 5773 }
29b0f896
AM		 5774 /* Pentium4 branch hints. */
5775 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5776 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5777 {
29b0f896
AM		 5778 prefix++;
5779 i.prefixes--;
5780 }
5781 if (i.prefix[REX_PREFIX] != 0)
5782 {
5783 prefix++;
5784 i.prefixes--;
2f66722d
AM		 5785 }
5786
29b0f896
AM		 5787 if (i.prefixes != 0 && !intel_syntax)
5788 as_warn (_("skipping prefixes on this instruction"));
5789
5790 /* It's always a symbol; End frag & setup for relax.
5791 Make sure there is enough room in this frag for the largest
5792 instruction we may generate in md_convert_frag. This is 2
5793 bytes for the opcode and room for the prefix and largest
5794 displacement. */
5795 frag_grow (prefix + 2 + 4);
5796 /* Prefix and 1 opcode byte go in fr_fix. */
5797 p = frag_more (prefix + 1);
5798 if (i.prefix[DATA_PREFIX] != 0)
5799 *p++ = DATA_PREFIX_OPCODE;
5800 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5801 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5802 *p++ = i.prefix[SEG_PREFIX];
5803 if (i.prefix[REX_PREFIX] != 0)
5804 *p++ = i.prefix[REX_PREFIX];
5805 *p = i.tm.base_opcode;
5806
5807 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 5808 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 5809 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 5810 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 5811 else
f8a5c266 5812 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 5813 subtype |= code16;
3e73aa7c 5814
29b0f896
AM		 5815 sym = i.op[0].disps->X_add_symbol;
5816 off = i.op[0].disps->X_add_number;
3e73aa7c 5817
29b0f896
AM		 5818 if (i.op[0].disps->X_op != O_constant
5819 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5820 {
29b0f896
AM		 5821 /* Handle complex expressions. */
5822 sym = make_expr_symbol (i.op[0].disps);
5823 off = 0;
5824 }
3e73aa7c 5825
29b0f896
AM		 5826 /* 1 possible extra opcode + 4 byte displacement go in var part.
5827 Pass reloc in fr_var. */
5828 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5829}
3e73aa7c 5830
29b0f896 5831static void
e3bb37b5 5832output_jump (void)
29b0f896
AM		 5833{
5834 char *p;
5835 int size;
3e02c1cc 5836 fixS *fixP;
29b0f896 5837
40fb9820 5838 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5839 {
5840 /* This is a loop or jecxz type instruction. */
5841 size = 1;
5842 if (i.prefix[ADDR_PREFIX] != 0)
5843 {
5844 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5845 i.prefixes -= 1;
5846 }
5847 /* Pentium4 branch hints. */
5848 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5849 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5850 {
5851 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5852 i.prefixes--;
3e73aa7c
JH		 5853 }
5854 }
29b0f896
AM		 5855 else
5856 {
5857 int code16;
3e73aa7c 5858
29b0f896
AM		 5859 code16 = 0;
5860 if (flag_code == CODE_16BIT)
5861 code16 = CODE16;
3e73aa7c 5862
29b0f896
AM		 5863 if (i.prefix[DATA_PREFIX] != 0)
5864 {
5865 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5866 i.prefixes -= 1;
5867 code16 ^= CODE16;
5868 }
252b5132 5869
29b0f896
AM		 5870 size = 4;
5871 if (code16)
5872 size = 2;
5873 }
9fcc94b6 5874
29b0f896
AM		 5875 if (i.prefix[REX_PREFIX] != 0)
5876 {
5877 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5878 i.prefixes -= 1;
5879 }
252b5132 5880
29b0f896
AM		 5881 if (i.prefixes != 0 && !intel_syntax)
5882 as_warn (_("skipping prefixes on this instruction"));
e0890092 5883
29b0f896
AM		 5884 p = frag_more (1 + size);
5885 *p++ = i.tm.base_opcode;
e0890092 5886
3e02c1cc
AM		 5887 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5888 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5889
5890 /* All jumps handled here are signed, but don't use a signed limit
5891 check for 32 and 16 bit jumps as we want to allow wrap around at
5892 4G and 64k respectively. */
5893 if (size == 1)
5894 fixP->fx_signed = 1;
29b0f896 5895}
e0890092 5896
29b0f896 5897static void
e3bb37b5 5898output_interseg_jump (void)
29b0f896
AM		 5899{
5900 char *p;
5901 int size;
5902 int prefix;
5903 int code16;
252b5132 5904
29b0f896
AM		 5905 code16 = 0;
5906 if (flag_code == CODE_16BIT)
5907 code16 = CODE16;
a217f122 5908
29b0f896
AM		 5909 prefix = 0;
5910 if (i.prefix[DATA_PREFIX] != 0)
5911 {
5912 prefix = 1;
5913 i.prefixes -= 1;
5914 code16 ^= CODE16;
5915 }
5916 if (i.prefix[REX_PREFIX] != 0)
5917 {
5918 prefix++;
5919 i.prefixes -= 1;
5920 }
252b5132 5921
29b0f896
AM		 5922 size = 4;
5923 if (code16)
5924 size = 2;
252b5132 5925
29b0f896
AM		 5926 if (i.prefixes != 0 && !intel_syntax)
5927 as_warn (_("skipping prefixes on this instruction"));
252b5132 5928
29b0f896
AM		 5929 /* 1 opcode; 2 segment; offset */
5930 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5931
29b0f896
AM		 5932 if (i.prefix[DATA_PREFIX] != 0)
5933 *p++ = DATA_PREFIX_OPCODE;
252b5132 5934
29b0f896
AM		 5935 if (i.prefix[REX_PREFIX] != 0)
5936 *p++ = i.prefix[REX_PREFIX];
252b5132 5937
29b0f896
AM		 5938 *p++ = i.tm.base_opcode;
5939 if (i.op[1].imms->X_op == O_constant)
5940 {
5941 offsetT n = i.op[1].imms->X_add_number;
252b5132 5942
29b0f896
AM		 5943 if (size == 2
5944 && !fits_in_unsigned_word (n)
5945 && !fits_in_signed_word (n))
5946 {
5947 as_bad (_("16-bit jump out of range"));
5948 return;
5949 }
5950 md_number_to_chars (p, n, size);
5951 }
5952 else
5953 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5954 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5955 if (i.op[0].imms->X_op != O_constant)
5956 as_bad (_("can't handle non absolute segment in `%s'"),
5957 i.tm.name);
5958 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5959}
a217f122 5960
29b0f896 5961static void
e3bb37b5 5962output_insn (void)
29b0f896 5963{
2bbd9c25
JJ		 5964 fragS *insn_start_frag;
5965 offsetT insn_start_off;
5966
29b0f896
AM		 5967 /* Tie dwarf2 debug info to the address at the start of the insn.
5968 We can't do this after the insn has been output as the current
5969 frag may have been closed off. eg. by frag_var. */
5970 dwarf2_emit_insn (0);
5971
2bbd9c25
JJ		 5972 insn_start_frag = frag_now;
5973 insn_start_off = frag_now_fix ();
5974
29b0f896 5975 /* Output jumps. */
40fb9820 5976 if (i.tm.opcode_modifier.jump)
29b0f896 5977 output_branch ();
40fb9820
L		 5978 else if (i.tm.opcode_modifier.jumpbyte
5979 || i.tm.opcode_modifier.jumpdword)
29b0f896 5980 output_jump ();
40fb9820 5981 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5982 output_interseg_jump ();
5983 else
5984 {
5985 /* Output normal instructions here. */
5986 char *p;
5987 unsigned char *q;
47465058 5988 unsigned int j;
331d2d0d 5989 unsigned int prefix;
4dffcebc 5990
c0f3af97
L		 5991 /* Since the VEX prefix contains the implicit prefix, we don't
5992 need the explicit prefix. */
5993 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5994 {
c0f3af97 5995 switch (i.tm.opcode_length)
bc4bd9ab 5996 {
c0f3af97
L		 5997 case 3:
5998 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5999 {
c0f3af97
L		 6000 prefix = (i.tm.base_opcode >> 24) & 0xff;
6001 goto check_prefix;
6002 }
6003 break;
6004 case 2:
6005 if ((i.tm.base_opcode & 0xff0000) != 0)
6006 {
6007 prefix = (i.tm.base_opcode >> 16) & 0xff;
6008 if (i.tm.cpu_flags.bitfield.cpupadlock)
6009 {
4dffcebc 6010check_prefix:
c0f3af97 6011 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6012 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6013 != REPE_PREFIX_OPCODE))
6014 add_prefix (prefix);
6015 }
6016 else
4dffcebc
L		 6017 add_prefix (prefix);
6018 }
c0f3af97
L		 6019 break;
6020 case 1:
6021 break;
6022 default:
6023 abort ();
bc4bd9ab 6024 }
c0f3af97
L		 6025
6026 /* The prefix bytes. */
6027 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6028 if (*q)
6029 FRAG_APPEND_1_CHAR (*q);
0f10071e 6030 }
252b5132 6031
c0f3af97
L		 6032 if (i.tm.opcode_modifier.vex)
6033 {
6034 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6035 if (*q)
6036 switch (j)
6037 {
6038 case REX_PREFIX:
6039 /* REX byte is encoded in VEX prefix. */
6040 break;
6041 case SEG_PREFIX:
6042 case ADDR_PREFIX:
6043 FRAG_APPEND_1_CHAR (*q);
6044 break;
6045 default:
6046 /* There should be no other prefixes for instructions
6047 with VEX prefix. */
6048 abort ();
6049 }
6050
6051 /* Now the VEX prefix. */
6052 p = frag_more (i.vex.length);
6053 for (j = 0; j < i.vex.length; j++)
6054 p[j] = i.vex.bytes[j];
6055 }
252b5132 6056
29b0f896 6057 /* Now the opcode; be careful about word order here! */
4dffcebc 6058 if (i.tm.opcode_length == 1)
29b0f896
AM		 6059 {
6060 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6061 }
6062 else
6063 {
4dffcebc 6064 switch (i.tm.opcode_length)
331d2d0d 6065 {
4dffcebc 6066 case 3:
331d2d0d
L		 6067 p = frag_more (3);
6068 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6069 break;
6070 case 2:
6071 p = frag_more (2);
6072 break;
6073 default:
6074 abort ();
6075 break;
331d2d0d 6076 }
0f10071e 6077
29b0f896
AM		 6078 /* Put out high byte first: can't use md_number_to_chars! */
6079 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6080 *p = i.tm.base_opcode & 0xff;
6081 }
3e73aa7c 6082
29b0f896 6083 /* Now the modrm byte and sib byte (if present). */
40fb9820 6084 if (i.tm.opcode_modifier.modrm)
29b0f896 6085 {
4a3523fa
L		 6086 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6087 | i.rm.reg << 3
6088 | i.rm.mode << 6));
29b0f896
AM		 6089 /* If i.rm.regmem == ESP (4)
6090 && i.rm.mode != (Register mode)
6091 && not 16 bit
6092 ==> need second modrm byte. */
6093 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6094 && i.rm.mode != 3
40fb9820 6095 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6096 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6097 | i.sib.index << 3
6098 | i.sib.scale << 6));
29b0f896 6099 }
3e73aa7c 6100
29b0f896 6101 if (i.disp_operands)
2bbd9c25 6102 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6103
29b0f896 6104 if (i.imm_operands)
2bbd9c25 6105 output_imm (insn_start_frag, insn_start_off);
29b0f896 6106 }
252b5132 6107
29b0f896
AM		 6108#ifdef DEBUG386
6109 if (flag_debug)
6110 {
7b81dfbb 6111 pi ("" /*line*/, &i);
29b0f896
AM		 6112 }
6113#endif /* DEBUG386 */
6114}
252b5132 6115
e205caa7
L		 6116/* Return the size of the displacement operand N. */
6117
6118static int
6119disp_size (unsigned int n)
6120{
6121 int size = 4;
40fb9820
L		 6122 if (i.types[n].bitfield.disp64)
6123 size = 8;
6124 else if (i.types[n].bitfield.disp8)
6125 size = 1;
6126 else if (i.types[n].bitfield.disp16)
6127 size = 2;
e205caa7
L		 6128 return size;
6129}
6130
6131/* Return the size of the immediate operand N. */
6132
6133static int
6134imm_size (unsigned int n)
6135{
6136 int size = 4;
40fb9820
L		 6137 if (i.types[n].bitfield.imm64)
6138 size = 8;
6139 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6140 size = 1;
6141 else if (i.types[n].bitfield.imm16)
6142 size = 2;
e205caa7
L		 6143 return size;
6144}
6145
29b0f896 6146static void
64e74474 6147output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6148{
6149 char *p;
6150 unsigned int n;
252b5132 6151
29b0f896
AM		 6152 for (n = 0; n < i.operands; n++)
6153 {
40fb9820 6154 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6155 {
6156 if (i.op[n].disps->X_op == O_constant)
6157 {
e205caa7 6158 int size = disp_size (n);
29b0f896 6159 offsetT val;
252b5132 6160
29b0f896
AM		 6161 val = offset_in_range (i.op[n].disps->X_add_number,
6162 size);
6163 p = frag_more (size);
6164 md_number_to_chars (p, val, size);
6165 }
6166 else
6167 {
f86103b7 6168 enum bfd_reloc_code_real reloc_type;
e205caa7 6169 int size = disp_size (n);
40fb9820 6170 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6171 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6172
e205caa7 6173 /* We can't have 8 bit displacement here. */
9c2799c2 6174 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6175
29b0f896
AM		 6176 /* The PC relative address is computed relative
6177 to the instruction boundary, so in case immediate
6178 fields follows, we need to adjust the value. */
6179 if (pcrel && i.imm_operands)
6180 {
29b0f896 6181 unsigned int n1;
e205caa7 6182 int sz = 0;
252b5132 6183
29b0f896 6184 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6185 if (operand_type_check (i.types[n1], imm))
252b5132 6186 {
e205caa7
L		 6187 /* Only one immediate is allowed for PC
6188 relative address. */
9c2799c2 6189 gas_assert (sz == 0);
e205caa7
L		 6190 sz = imm_size (n1);
6191 i.op[n].disps->X_add_number -= sz;
252b5132 6192 }
29b0f896 6193 /* We should find the immediate. */
9c2799c2 6194 gas_assert (sz != 0);
29b0f896 6195 }
520dc8e8 6196
29b0f896 6197 p = frag_more (size);
2bbd9c25 6198 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6199 if (GOT_symbol
2bbd9c25 6200 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6201 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6202 || reloc_type == BFD_RELOC_X86_64_32S
6203 || (reloc_type == BFD_RELOC_64
6204 && object_64bit))
d6ab8113
JB		 6205 && (i.op[n].disps->X_op == O_symbol
6206 || (i.op[n].disps->X_op == O_add
6207 && ((symbol_get_value_expression
6208 (i.op[n].disps->X_op_symbol)->X_op)
6209 == O_subtract))))
6210 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6211 {
6212 offsetT add;
6213
6214 if (insn_start_frag == frag_now)
6215 add = (p - frag_now->fr_literal) - insn_start_off;
6216 else
6217 {
6218 fragS *fr;
6219
6220 add = insn_start_frag->fr_fix - insn_start_off;
6221 for (fr = insn_start_frag->fr_next;
6222 fr && fr != frag_now; fr = fr->fr_next)
6223 add += fr->fr_fix;
6224 add += p - frag_now->fr_literal;
6225 }
6226
4fa24527 6227 if (!object_64bit)
7b81dfbb
AJ		 6228 {
6229 reloc_type = BFD_RELOC_386_GOTPC;
6230 i.op[n].imms->X_add_number += add;
6231 }
6232 else if (reloc_type == BFD_RELOC_64)
6233 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6234 else
7b81dfbb
AJ		 6235 /* Don't do the adjustment for x86-64, as there
6236 the pcrel addressing is relative to the _next_
6237 insn, and that is taken care of in other code. */
d6ab8113 6238 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6239 }
062cd5e7 6240 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6241 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6242 }
6243 }
6244 }
6245}
252b5132 6246
29b0f896 6247static void
64e74474 6248output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6249{
6250 char *p;
6251 unsigned int n;
252b5132 6252
29b0f896
AM		 6253 for (n = 0; n < i.operands; n++)
6254 {
40fb9820 6255 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6256 {
6257 if (i.op[n].imms->X_op == O_constant)
6258 {
e205caa7 6259 int size = imm_size (n);
29b0f896 6260 offsetT val;
b4cac588 6261
29b0f896
AM		 6262 val = offset_in_range (i.op[n].imms->X_add_number,
6263 size);
6264 p = frag_more (size);
6265 md_number_to_chars (p, val, size);
6266 }
6267 else
6268 {
6269 /* Not absolute_section.
6270 Need a 32-bit fixup (don't support 8bit
6271 non-absolute imms). Try to support other
6272 sizes ... */
f86103b7 6273 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6274 int size = imm_size (n);
6275 int sign;
29b0f896 6276
40fb9820 6277 if (i.types[n].bitfield.imm32s
a7d61044 6278 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6279 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6280 sign = 1;
e205caa7
L		 6281 else
6282 sign = 0;
520dc8e8 6283
29b0f896
AM		 6284 p = frag_more (size);
6285 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6286
2bbd9c25
JJ		 6287 /* This is tough to explain. We end up with this one if we
6288 * have operands that look like
6289 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6290 * obtain the absolute address of the GOT, and it is strongly
6291 * preferable from a performance point of view to avoid using
6292 * a runtime relocation for this. The actual sequence of
6293 * instructions often look something like:
6294 *
6295 * call .L66
6296 * .L66:
6297 * popl %ebx
6298 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6299 *
6300 * The call and pop essentially return the absolute address
6301 * of the label .L66 and store it in %ebx. The linker itself
6302 * will ultimately change the first operand of the addl so
6303 * that %ebx points to the GOT, but to keep things simple, the
6304 * .o file must have this operand set so that it generates not
6305 * the absolute address of .L66, but the absolute address of
6306 * itself. This allows the linker itself simply treat a GOTPC
6307 * relocation as asking for a pcrel offset to the GOT to be
6308 * added in, and the addend of the relocation is stored in the
6309 * operand field for the instruction itself.
6310 *
6311 * Our job here is to fix the operand so that it would add
6312 * the correct offset so that %ebx would point to itself. The
6313 * thing that is tricky is that .-.L66 will point to the
6314 * beginning of the instruction, so we need to further modify
6315 * the operand so that it will point to itself. There are
6316 * other cases where you have something like:
6317 *
6318 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6319 *
6320 * and here no correction would be required. Internally in
6321 * the assembler we treat operands of this form as not being
6322 * pcrel since the '.' is explicitly mentioned, and I wonder
6323 * whether it would simplify matters to do it this way. Who
6324 * knows. In earlier versions of the PIC patches, the
6325 * pcrel_adjust field was used to store the correction, but
6326 * since the expression is not pcrel, I felt it would be
6327 * confusing to do it this way. */
6328
d6ab8113 6329 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6330 || reloc_type == BFD_RELOC_X86_64_32S
6331 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6332 && GOT_symbol
6333 && GOT_symbol == i.op[n].imms->X_add_symbol
6334 && (i.op[n].imms->X_op == O_symbol
6335 || (i.op[n].imms->X_op == O_add
6336 && ((symbol_get_value_expression
6337 (i.op[n].imms->X_op_symbol)->X_op)
6338 == O_subtract))))
6339 {
2bbd9c25
JJ		 6340 offsetT add;
6341
6342 if (insn_start_frag == frag_now)
6343 add = (p - frag_now->fr_literal) - insn_start_off;
6344 else
6345 {
6346 fragS *fr;
6347
6348 add = insn_start_frag->fr_fix - insn_start_off;
6349 for (fr = insn_start_frag->fr_next;
6350 fr && fr != frag_now; fr = fr->fr_next)
6351 add += fr->fr_fix;
6352 add += p - frag_now->fr_literal;
6353 }
6354
4fa24527 6355 if (!object_64bit)
d6ab8113 6356 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6357 else if (size == 4)
d6ab8113 6358 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6359 else if (size == 8)
6360 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6361 i.op[n].imms->X_add_number += add;
29b0f896 6362 }
29b0f896
AM		 6363 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6364 i.op[n].imms, 0, reloc_type);
6365 }
6366 }
6367 }
252b5132
RH		 6368}
6369\f
d182319b
JB		 6370/* x86_cons_fix_new is called via the expression parsing code when a
6371 reloc is needed. We use this hook to get the correct .got reloc. */
6372static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6373static int cons_sign = -1;
6374
6375void
e3bb37b5 6376x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6377 expressionS *exp)
d182319b
JB		 6378{
6379 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6380
6381 got_reloc = NO_RELOC;
6382
6383#ifdef TE_PE
6384 if (exp->X_op == O_secrel)
6385 {
6386 exp->X_op = O_symbol;
6387 r = BFD_RELOC_32_SECREL;
6388 }
6389#endif
6390
6391 fix_new_exp (frag, off, len, exp, 0, r);
6392}
6393
718ddfc0
JB		 6394#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6395# define lex_got(reloc, adjust, types) NULL
6396#else
f3c180ae
AM		 6397/* Parse operands of the form
6398 <symbol>@GOTOFF+<nnn>
6399 and similar .plt or .got references.
6400
6401 If we find one, set up the correct relocation in RELOC and copy the
6402 input string, minus the `@GOTOFF' into a malloc'd buffer for
6403 parsing by the calling routine. Return this buffer, and if ADJUST
6404 is non-null set it to the length of the string we removed from the
6405 input line. Otherwise return NULL. */
6406static char *
91d6fa6a 6407lex_got (enum bfd_reloc_code_real *rel,
64e74474 6408 int *adjust,
40fb9820 6409 i386_operand_type *types)
f3c180ae 6410{
7b81dfbb
AJ		 6411 /* Some of the relocations depend on the size of what field is to
6412 be relocated. But in our callers i386_immediate and i386_displacement
6413 we don't yet know the operand size (this will be set by insn
6414 matching). Hence we record the word32 relocation here,
6415 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6416 static const struct {
6417 const char *str;
cff8d58a 6418 int len;
4fa24527 6419 const enum bfd_reloc_code_real rel[2];
40fb9820 6420 const i386_operand_type types64;
f3c180ae 6421 } gotrel[] = {
cff8d58a
L		 6422 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6423 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6424 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6425 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6426 BFD_RELOC_X86_64_PLT32 },
40fb9820 6427 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6428 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6429 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6430 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6431 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6432 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6433 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6434 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6435 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6436 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6437 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6438 BFD_RELOC_X86_64_TLSGD },
40fb9820 6439 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6440 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6441 _dummy_first_bfd_reloc_code_real },
40fb9820 6442 OPERAND_TYPE_NONE },
cff8d58a
L		 6443 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6444 BFD_RELOC_X86_64_TLSLD },
40fb9820 6445 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6446 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6447 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6448 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6449 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6450 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6451 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6452 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6453 _dummy_first_bfd_reloc_code_real },
40fb9820 6454 OPERAND_TYPE_NONE },
cff8d58a
L		 6455 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6456 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6457 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6458 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6459 _dummy_first_bfd_reloc_code_real },
40fb9820 6460 OPERAND_TYPE_NONE },
cff8d58a
L		 6461 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6462 _dummy_first_bfd_reloc_code_real },
40fb9820 6463 OPERAND_TYPE_NONE },
cff8d58a
L		 6464 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6465 BFD_RELOC_X86_64_GOT32 },
40fb9820 6466 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6467 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6468 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6469 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6470 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6471 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6472 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6473 };
6474 char *cp;
6475 unsigned int j;
6476
718ddfc0
JB		 6477 if (!IS_ELF)
6478 return NULL;
6479
f3c180ae 6480 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6481 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6482 return NULL;
6483
47465058 6484 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6485 {
cff8d58a 6486 int len = gotrel[j].len;
28f81592 6487 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6488 {
4fa24527 6489 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6490 {
28f81592
AM		 6491 int first, second;
6492 char *tmpbuf, *past_reloc;
f3c180ae 6493
91d6fa6a 6494 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6495 if (adjust)
6496 *adjust = len;
f3c180ae 6497
3956db08
JB		 6498 if (types)
6499 {
6500 if (flag_code != CODE_64BIT)
40fb9820
L		 6501 {
6502 types->bitfield.imm32 = 1;
6503 types->bitfield.disp32 = 1;
6504 }
3956db08
JB		 6505 else
6506 *types = gotrel[j].types64;
6507 }
6508
f3c180ae
AM		 6509 if (GOT_symbol == NULL)
6510 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6511
28f81592 6512 /* The length of the first part of our input line. */
f3c180ae 6513 first = cp - input_line_pointer;
28f81592
AM		 6514
6515 /* The second part goes from after the reloc token until
67c11a9b 6516 (and including) an end_of_line char or comma. */
28f81592 6517 past_reloc = cp + 1 + len;
67c11a9b
AM		 6518 cp = past_reloc;
6519 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6520 ++cp;
6521 second = cp + 1 - past_reloc;
28f81592
AM		 6522
6523 /* Allocate and copy string. The trailing NUL shouldn't
6524 be necessary, but be safe. */
1e9cc1c2 6525 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6526 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6527 if (second != 0 && *past_reloc != ' ')
6528 /* Replace the relocation token with ' ', so that
6529 errors like foo@GOTOFF1 will be detected. */
6530 tmpbuf[first++] = ' ';
6531 memcpy (tmpbuf + first, past_reloc, second);
6532 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6533 return tmpbuf;
6534 }
6535
4fa24527
JB		 6536 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6537 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6538 return NULL;
6539 }
6540 }
6541
6542 /* Might be a symbol version string. Don't as_bad here. */
6543 return NULL;
6544}
6545
f3c180ae 6546void
e3bb37b5 6547x86_cons (expressionS *exp, int size)
f3c180ae 6548{
ee86248c
JB		 6549 intel_syntax = -intel_syntax;
6550
3c7b9c2c 6551 exp->X_md = 0;
4fa24527 6552 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6553 {
6554 /* Handle @GOTOFF and the like in an expression. */
6555 char *save;
6556 char *gotfree_input_line;
6557 int adjust;
6558
6559 save = input_line_pointer;
3956db08 6560 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6561 if (gotfree_input_line)
6562 input_line_pointer = gotfree_input_line;
6563
6564 expression (exp);
6565
6566 if (gotfree_input_line)
6567 {
6568 /* expression () has merrily parsed up to the end of line,
6569 or a comma - in the wrong buffer. Transfer how far
6570 input_line_pointer has moved to the right buffer. */
6571 input_line_pointer = (save
6572 + (input_line_pointer - gotfree_input_line)
6573 + adjust);
6574 free (gotfree_input_line);
3992d3b7
AM		 6575 if (exp->X_op == O_constant
6576 || exp->X_op == O_absent
6577 || exp->X_op == O_illegal
0398aac5 6578 || exp->X_op == O_register
3992d3b7
AM		 6579 || exp->X_op == O_big)
6580 {
6581 char c = *input_line_pointer;
6582 *input_line_pointer = 0;
6583 as_bad (_("missing or invalid expression `%s'"), save);
6584 *input_line_pointer = c;
6585 }
f3c180ae
AM		 6586 }
6587 }
6588 else
6589 expression (exp);
ee86248c
JB		 6590
6591 intel_syntax = -intel_syntax;
6592
6593 if (intel_syntax)
6594 i386_intel_simplify (exp);
f3c180ae
AM		 6595}
6596#endif
6597
9f32dd5b
L		 6598static void
6599signed_cons (int size)
6482c264 6600{
d182319b
JB		 6601 if (flag_code == CODE_64BIT)
6602 cons_sign = 1;
6603 cons (size);
6604 cons_sign = -1;
6482c264
NC		 6605}
6606
d182319b 6607#ifdef TE_PE
6482c264
NC		 6608static void
6609pe_directive_secrel (dummy)
6610 int dummy ATTRIBUTE_UNUSED;
6611{
6612 expressionS exp;
6613
6614 do
6615 {
6616 expression (&exp);
6617 if (exp.X_op == O_symbol)
6618 exp.X_op = O_secrel;
6619
6620 emit_expr (&exp, 4);
6621 }
6622 while (*input_line_pointer++ == ',');
6623
6624 input_line_pointer--;
6625 demand_empty_rest_of_line ();
6626}
6482c264
NC		 6627#endif
6628
252b5132 6629static int
70e41ade 6630i386_immediate (char *imm_start)
252b5132
RH		 6631{
6632 char *save_input_line_pointer;
f3c180ae 6633 char *gotfree_input_line;
252b5132 6634 segT exp_seg = 0;
47926f60 6635 expressionS *exp;
40fb9820
L		 6636 i386_operand_type types;
6637
0dfbf9d7 6638 operand_type_set (&types, ~0);
252b5132
RH		 6639
6640 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6641 {
31b2323c
L		 6642 as_bad (_("at most %d immediate operands are allowed"),
6643 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6644 return 0;
6645 }
6646
6647 exp = &im_expressions[i.imm_operands++];
520dc8e8 6648 i.op[this_operand].imms = exp;
252b5132
RH		 6649
6650 if (is_space_char (*imm_start))
6651 ++imm_start;
6652
6653 save_input_line_pointer = input_line_pointer;
6654 input_line_pointer = imm_start;
6655
3956db08 6656 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6657 if (gotfree_input_line)
6658 input_line_pointer = gotfree_input_line;
252b5132
RH		 6659
6660 exp_seg = expression (exp);
6661
83183c0c 6662 SKIP_WHITESPACE ();
252b5132 6663 if (*input_line_pointer)
f3c180ae 6664 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6665
6666 input_line_pointer = save_input_line_pointer;
f3c180ae 6667 if (gotfree_input_line)
ee86248c
JB		 6668 {
6669 free (gotfree_input_line);
6670
6671 if (exp->X_op == O_constant || exp->X_op == O_register)
6672 exp->X_op = O_illegal;
6673 }
6674
6675 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6676}
252b5132 6677
ee86248c
JB		 6678static int
6679i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6680 i386_operand_type types, const char *imm_start)
6681{
6682 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6683 {
313c53d1
L		 6684 if (imm_start)
6685 as_bad (_("missing or invalid immediate expression `%s'"),
6686 imm_start);
3992d3b7 6687 return 0;
252b5132 6688 }
3e73aa7c 6689 else if (exp->X_op == O_constant)
252b5132 6690 {
47926f60 6691 /* Size it properly later. */
40fb9820 6692 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 6693 /* If not 64bit, sign extend val. */
6694 if (flag_code != CODE_64BIT
4eed87de
AM		 6695 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6696 exp->X_add_number
6697 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6698 }
4c63da97 6699#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6700 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6701 && exp_seg != absolute_section
47926f60 6702 && exp_seg != text_section
24eab124
AM		 6703 && exp_seg != data_section
6704 && exp_seg != bss_section
6705 && exp_seg != undefined_section
f86103b7 6706 && !bfd_is_com_section (exp_seg))
252b5132 6707 {
d0b47220 6708 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6709 return 0;
6710 }
6711#endif
bb8f5920
L		 6712 else if (!intel_syntax && exp->X_op == O_register)
6713 {
313c53d1
L		 6714 if (imm_start)
6715 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6716 return 0;
6717 }
252b5132
RH		 6718 else
6719 {
6720 /* This is an address. The size of the address will be
24eab124 6721 determined later, depending on destination register,
3e73aa7c 6722 suffix, or the default for the section. */
40fb9820
L		 6723 i.types[this_operand].bitfield.imm8 = 1;
6724 i.types[this_operand].bitfield.imm16 = 1;
6725 i.types[this_operand].bitfield.imm32 = 1;
6726 i.types[this_operand].bitfield.imm32s = 1;
6727 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6728 i.types[this_operand] = operand_type_and (i.types[this_operand],
6729 types);
252b5132
RH		 6730 }
6731
6732 return 1;
6733}
6734
551c1ca1 6735static char *
e3bb37b5 6736i386_scale (char *scale)
252b5132 6737{
551c1ca1
AM		 6738 offsetT val;
6739 char *save = input_line_pointer;
252b5132 6740
551c1ca1
AM		 6741 input_line_pointer = scale;
6742 val = get_absolute_expression ();
6743
6744 switch (val)
252b5132 6745 {
551c1ca1 6746 case 1:
252b5132
RH		 6747 i.log2_scale_factor = 0;
6748 break;
551c1ca1 6749 case 2:
252b5132
RH		 6750 i.log2_scale_factor = 1;
6751 break;
551c1ca1 6752 case 4:
252b5132
RH		 6753 i.log2_scale_factor = 2;
6754 break;
551c1ca1 6755 case 8:
252b5132
RH		 6756 i.log2_scale_factor = 3;
6757 break;
6758 default:
a724f0f4
JB		 6759 {
6760 char sep = *input_line_pointer;
6761
6762 *input_line_pointer = '\0';
6763 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6764 scale);
6765 *input_line_pointer = sep;
6766 input_line_pointer = save;
6767 return NULL;
6768 }
252b5132 6769 }
29b0f896 6770 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6771 {
6772 as_warn (_("scale factor of %d without an index register"),
24eab124 6773 1 << i.log2_scale_factor);
252b5132 6774 i.log2_scale_factor = 0;
252b5132 6775 }
551c1ca1
AM		 6776 scale = input_line_pointer;
6777 input_line_pointer = save;
6778 return scale;
252b5132
RH		 6779}
6780
252b5132 6781static int
e3bb37b5 6782i386_displacement (char *disp_start, char *disp_end)
252b5132 6783{
29b0f896 6784 expressionS *exp;
252b5132
RH		 6785 segT exp_seg = 0;
6786 char *save_input_line_pointer;
f3c180ae 6787 char *gotfree_input_line;
40fb9820
L		 6788 int override;
6789 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6790 int ret;
252b5132 6791
31b2323c
L		 6792 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6793 {
6794 as_bad (_("at most %d displacement operands are allowed"),
6795 MAX_MEMORY_OPERANDS);
6796 return 0;
6797 }
6798
0dfbf9d7 6799 operand_type_set (&bigdisp, 0);
40fb9820
L		 6800 if ((i.types[this_operand].bitfield.jumpabsolute)
6801 || (!current_templates->start->opcode_modifier.jump
6802 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6803 {
40fb9820 6804 bigdisp.bitfield.disp32 = 1;
e05278af 6805 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6806 if (flag_code == CODE_64BIT)
6807 {
6808 if (!override)
6809 {
6810 bigdisp.bitfield.disp32s = 1;
6811 bigdisp.bitfield.disp64 = 1;
6812 }
6813 }
6814 else if ((flag_code == CODE_16BIT) ^ override)
6815 {
6816 bigdisp.bitfield.disp32 = 0;
6817 bigdisp.bitfield.disp16 = 1;
6818 }
e05278af
JB		 6819 }
6820 else
6821 {
6822 /* For PC-relative branches, the width of the displacement
6823 is dependent upon data size, not address size. */
e05278af 6824 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6825 if (flag_code == CODE_64BIT)
6826 {
6827 if (override || i.suffix == WORD_MNEM_SUFFIX)
6828 bigdisp.bitfield.disp16 = 1;
6829 else
6830 {
6831 bigdisp.bitfield.disp32 = 1;
6832 bigdisp.bitfield.disp32s = 1;
6833 }
6834 }
6835 else
e05278af
JB		 6836 {
6837 if (!override)
6838 override = (i.suffix == (flag_code != CODE_16BIT
6839 ? WORD_MNEM_SUFFIX
6840 : LONG_MNEM_SUFFIX));
40fb9820
L		 6841 bigdisp.bitfield.disp32 = 1;
6842 if ((flag_code == CODE_16BIT) ^ override)
6843 {
6844 bigdisp.bitfield.disp32 = 0;
6845 bigdisp.bitfield.disp16 = 1;
6846 }
e05278af 6847 }
e05278af 6848 }
c6fb90c8
L		 6849 i.types[this_operand] = operand_type_or (i.types[this_operand],
6850 bigdisp);
252b5132
RH		 6851
6852 exp = &disp_expressions[i.disp_operands];
520dc8e8 6853 i.op[this_operand].disps = exp;
252b5132
RH		 6854 i.disp_operands++;
6855 save_input_line_pointer = input_line_pointer;
6856 input_line_pointer = disp_start;
6857 END_STRING_AND_SAVE (disp_end);
6858
6859#ifndef GCC_ASM_O_HACK
6860#define GCC_ASM_O_HACK 0
6861#endif
6862#if GCC_ASM_O_HACK
6863 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6864 if (i.types[this_operand].bitfield.baseIndex
24eab124 6865 && displacement_string_end[-1] == '+')
252b5132
RH		 6866 {
6867 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6868 constraint within gcc asm statements.
6869 For instance:
6870
6871 #define _set_tssldt_desc(n,addr,limit,type) \
6872 __asm__ __volatile__ ( \
6873 "movw %w2,%0\n\t" \
6874 "movw %w1,2+%0\n\t" \
6875 "rorl $16,%1\n\t" \
6876 "movb %b1,4+%0\n\t" \
6877 "movb %4,5+%0\n\t" \
6878 "movb $0,6+%0\n\t" \
6879 "movb %h1,7+%0\n\t" \
6880 "rorl $16,%1" \
6881 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6882
6883 This works great except that the output assembler ends
6884 up looking a bit weird if it turns out that there is
6885 no offset. You end up producing code that looks like:
6886
6887 #APP
6888 movw $235,(%eax)
6889 movw %dx,2+(%eax)
6890 rorl $16,%edx
6891 movb %dl,4+(%eax)
6892 movb $137,5+(%eax)
6893 movb $0,6+(%eax)
6894 movb %dh,7+(%eax)
6895 rorl $16,%edx
6896 #NO_APP
6897
47926f60 6898 So here we provide the missing zero. */
24eab124
AM		 6899
6900 *displacement_string_end = '0';
252b5132
RH		 6901 }
6902#endif
3956db08 6903 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6904 if (gotfree_input_line)
6905 input_line_pointer = gotfree_input_line;
252b5132 6906
24eab124 6907 exp_seg = expression (exp);
252b5132 6908
636c26b0
AM		 6909 SKIP_WHITESPACE ();
6910 if (*input_line_pointer)
6911 as_bad (_("junk `%s' after expression"), input_line_pointer);
6912#if GCC_ASM_O_HACK
6913 RESTORE_END_STRING (disp_end + 1);
6914#endif
636c26b0 6915 input_line_pointer = save_input_line_pointer;
636c26b0 6916 if (gotfree_input_line)
ee86248c
JB		 6917 {
6918 free (gotfree_input_line);
6919
6920 if (exp->X_op == O_constant || exp->X_op == O_register)
6921 exp->X_op = O_illegal;
6922 }
6923
6924 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6925
6926 RESTORE_END_STRING (disp_end);
6927
6928 return ret;
6929}
6930
6931static int
6932i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6933 i386_operand_type types, const char *disp_start)
6934{
6935 i386_operand_type bigdisp;
6936 int ret = 1;
636c26b0 6937
24eab124
AM		 6938 /* We do this to make sure that the section symbol is in
6939 the symbol table. We will ultimately change the relocation
47926f60 6940 to be relative to the beginning of the section. */
1ae12ab7 6941 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6942 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6943 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6944 {
636c26b0 6945 if (exp->X_op != O_symbol)
3992d3b7 6946 goto inv_disp;
636c26b0 6947
e5cb08ac 6948 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 6949 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
6950 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 6951 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6952 exp->X_op = O_subtract;
6953 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6954 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6955 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6956 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6957 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6958 else
29b0f896 6959 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6960 }
252b5132 6961
3992d3b7
AM		 6962 else if (exp->X_op == O_absent
6963 || exp->X_op == O_illegal
ee86248c 6964 || exp->X_op == O_big)
2daf4fd8 6965 {
3992d3b7
AM		 6966 inv_disp:
6967 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6968 disp_start);
3992d3b7 6969 ret = 0;
2daf4fd8
AM		 6970 }
6971
0e1147d9
L		 6972 else if (flag_code == CODE_64BIT
6973 && !i.prefix[ADDR_PREFIX]
6974 && exp->X_op == O_constant)
6975 {
6976 /* Since displacement is signed extended to 64bit, don't allow
6977 disp32 and turn off disp32s if they are out of range. */
6978 i.types[this_operand].bitfield.disp32 = 0;
6979 if (!fits_in_signed_long (exp->X_add_number))
6980 {
6981 i.types[this_operand].bitfield.disp32s = 0;
6982 if (i.types[this_operand].bitfield.baseindex)
6983 {
6984 as_bad (_("0x%lx out range of signed 32bit displacement"),
6985 (long) exp->X_add_number);
6986 ret = 0;
6987 }
6988 }
6989 }
6990
4c63da97 6991#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6992 else if (exp->X_op != O_constant
6993 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6994 && exp_seg != absolute_section
6995 && exp_seg != text_section
6996 && exp_seg != data_section
6997 && exp_seg != bss_section
6998 && exp_seg != undefined_section
6999 && !bfd_is_com_section (exp_seg))
24eab124 7000 {
d0b47220 7001 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 7002 ret = 0;
24eab124 7003 }
252b5132 7004#endif
3956db08 7005
40fb9820
L		 7006 /* Check if this is a displacement only operand. */
7007 bigdisp = i.types[this_operand];
7008 bigdisp.bitfield.disp8 = 0;
7009 bigdisp.bitfield.disp16 = 0;
7010 bigdisp.bitfield.disp32 = 0;
7011 bigdisp.bitfield.disp32s = 0;
7012 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 7013 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 7014 i.types[this_operand] = operand_type_and (i.types[this_operand],
7015 types);
3956db08 7016
3992d3b7 7017 return ret;
252b5132
RH		 7018}
7019
eecb386c 7020/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 7021 Return 1 on success, 0 on a failure. */
7022
252b5132 7023static int
e3bb37b5 7024i386_index_check (const char *operand_string)
252b5132 7025{
3e73aa7c 7026 int ok;
fc0763e6 7027 const char *kind = "base/index";
24eab124 7028#if INFER_ADDR_PREFIX
eecb386c
AM		 7029 int fudged = 0;
7030
24eab124
AM		 7031 tryprefix:
7032#endif
3e73aa7c 7033 ok = 1;
fc0763e6
JB		 7034 if (current_templates->start->opcode_modifier.isstring
7035 && !current_templates->start->opcode_modifier.immext
7036 && (current_templates->end[-1].opcode_modifier.isstring
7037 || i.mem_operands))
7038 {
7039 /* Memory operands of string insns are special in that they only allow
7040 a single register (rDI, rSI, or rBX) as their memory address. */
7041 unsigned int expected;
7042
7043 kind = "string address";
7044
7045 if (current_templates->start->opcode_modifier.w)
7046 {
7047 i386_operand_type type = current_templates->end[-1].operand_types[0];
7048
7049 if (!type.bitfield.baseindex
7050 || ((!i.mem_operands != !intel_syntax)
7051 && current_templates->end[-1].operand_types[1]
7052 .bitfield.baseindex))
7053 type = current_templates->end[-1].operand_types[1];
7054 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
7055 }
7056 else
7057 expected = 3 /* rBX */;
7058
7059 if (!i.base_reg || i.index_reg
7060 || operand_type_check (i.types[this_operand], disp))
7061 ok = -1;
7062 else if (!(flag_code == CODE_64BIT
7063 ? i.prefix[ADDR_PREFIX]
7064 ? i.base_reg->reg_type.bitfield.reg32
7065 : i.base_reg->reg_type.bitfield.reg64
7066 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7067 ? i.base_reg->reg_type.bitfield.reg32
7068 : i.base_reg->reg_type.bitfield.reg16))
7069 ok = 0;
7070 else if (i.base_reg->reg_num != expected)
7071 ok = -1;
7072
7073 if (ok < 0)
7074 {
7075 unsigned int j;
7076
7077 for (j = 0; j < i386_regtab_size; ++j)
7078 if ((flag_code == CODE_64BIT
7079 ? i.prefix[ADDR_PREFIX]
7080 ? i386_regtab[j].reg_type.bitfield.reg32
7081 : i386_regtab[j].reg_type.bitfield.reg64
7082 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7083 ? i386_regtab[j].reg_type.bitfield.reg32
7084 : i386_regtab[j].reg_type.bitfield.reg16)
7085 && i386_regtab[j].reg_num == expected)
7086 break;
9c2799c2 7087 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 7088 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7089 operand_string,
7090 intel_syntax ? '[' : '(',
7091 register_prefix,
7092 i386_regtab[j].reg_name,
7093 intel_syntax ? ']' : ')');
7094 ok = 1;
7095 }
7096 }
7097 else if (flag_code == CODE_64BIT)
64e74474 7098 {
64e74474 7099 if ((i.base_reg
40fb9820
L		 7100 && ((i.prefix[ADDR_PREFIX] == 0
7101 && !i.base_reg->reg_type.bitfield.reg64)
7102 || (i.prefix[ADDR_PREFIX]
7103 && !i.base_reg->reg_type.bitfield.reg32))
7104 && (i.index_reg
9a04903e
JB		 7105 || i.base_reg->reg_num !=
7106 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7107 || (i.index_reg
40fb9820
L		 7108 && (!i.index_reg->reg_type.bitfield.baseindex
7109 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7110 && i.index_reg->reg_num != RegRiz
7111 && !i.index_reg->reg_type.bitfield.reg64
7112 )
40fb9820 7113 || (i.prefix[ADDR_PREFIX]
db51cc60 7114 && i.index_reg->reg_num != RegEiz
40fb9820 7115 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7116 ok = 0;
3e73aa7c
JH		 7117 }
7118 else
7119 {
7120 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7121 {
7122 /* 16bit checks. */
7123 if ((i.base_reg
40fb9820
L		 7124 && (!i.base_reg->reg_type.bitfield.reg16
7125 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7126 || (i.index_reg
40fb9820
L		 7127 && (!i.index_reg->reg_type.bitfield.reg16
7128 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7129 || !(i.base_reg
7130 && i.base_reg->reg_num < 6
7131 && i.index_reg->reg_num >= 6
7132 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7133 ok = 0;
7134 }
7135 else
e5cb08ac 7136 {
3e73aa7c
JH		 7137 /* 32bit checks. */
7138 if ((i.base_reg
40fb9820 7139 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7140 || (i.index_reg
db51cc60
L		 7141 && ((!i.index_reg->reg_type.bitfield.reg32
7142 && i.index_reg->reg_num != RegEiz)
40fb9820 7143 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7144 ok = 0;
3e73aa7c
JH		 7145 }
7146 }
7147 if (!ok)
24eab124
AM		 7148 {
7149#if INFER_ADDR_PREFIX
fc0763e6 7150 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7151 {
7152 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7153 i.prefixes += 1;
b23bac36
AM		 7154 /* Change the size of any displacement too. At most one of
7155 Disp16 or Disp32 is set.
7156 FIXME. There doesn't seem to be any real need for separate
7157 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7158 Removing them would probably clean up the code quite a lot. */
4eed87de 7159 if (flag_code != CODE_64BIT
40fb9820
L		 7160 && (i.types[this_operand].bitfield.disp16
7161 || i.types[this_operand].bitfield.disp32))
7162 i.types[this_operand]
c6fb90c8 7163 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7164 fudged = 1;
24eab124
AM		 7165 goto tryprefix;
7166 }
eecb386c 7167 if (fudged)
fc0763e6
JB		 7168 as_bad (_("`%s' is not a valid %s expression"),
7169 operand_string,
7170 kind);
eecb386c 7171 else
c388dee8 7172#endif
fc0763e6 7173 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7174 operand_string,
fc0763e6
JB		 7175 flag_code_names[i.prefix[ADDR_PREFIX]
7176 ? flag_code == CODE_32BIT
7177 ? CODE_16BIT
7178 : CODE_32BIT
7179 : flag_code],
7180 kind);
24eab124 7181 }
20f0a1fc 7182 return ok;
24eab124 7183}
252b5132 7184
fc0763e6 7185/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7186 on error. */
252b5132 7187
252b5132 7188static int
a7619375 7189i386_att_operand (char *operand_string)
252b5132 7190{
af6bdddf
AM		 7191 const reg_entry *r;
7192 char *end_op;
24eab124 7193 char *op_string = operand_string;
252b5132 7194
24eab124 7195 if (is_space_char (*op_string))
252b5132
RH		 7196 ++op_string;
7197
24eab124 7198 /* We check for an absolute prefix (differentiating,
47926f60 7199 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7200 if (*op_string == ABSOLUTE_PREFIX)
7201 {
7202 ++op_string;
7203 if (is_space_char (*op_string))
7204 ++op_string;
40fb9820 7205 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7206 }
252b5132 7207
47926f60 7208 /* Check if operand is a register. */
4d1bb795 7209 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7210 {
40fb9820
L		 7211 i386_operand_type temp;
7212
24eab124
AM		 7213 /* Check for a segment override by searching for ':' after a
7214 segment register. */
7215 op_string = end_op;
7216 if (is_space_char (*op_string))
7217 ++op_string;
40fb9820
L		 7218 if (*op_string == ':'
7219 && (r->reg_type.bitfield.sreg2
7220 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7221 {
7222 switch (r->reg_num)
7223 {
7224 case 0:
7225 i.seg[i.mem_operands] = &es;
7226 break;
7227 case 1:
7228 i.seg[i.mem_operands] = &cs;
7229 break;
7230 case 2:
7231 i.seg[i.mem_operands] = &ss;
7232 break;
7233 case 3:
7234 i.seg[i.mem_operands] = &ds;
7235 break;
7236 case 4:
7237 i.seg[i.mem_operands] = &fs;
7238 break;
7239 case 5:
7240 i.seg[i.mem_operands] = &gs;
7241 break;
7242 }
252b5132 7243
24eab124 7244 /* Skip the ':' and whitespace. */
252b5132
RH		 7245 ++op_string;
7246 if (is_space_char (*op_string))
24eab124 7247 ++op_string;
252b5132 7248
24eab124
AM		 7249 if (!is_digit_char (*op_string)
7250 && !is_identifier_char (*op_string)
7251 && *op_string != '('
7252 && *op_string != ABSOLUTE_PREFIX)
7253 {
7254 as_bad (_("bad memory operand `%s'"), op_string);
7255 return 0;
7256 }
47926f60 7257 /* Handle case of %es:*foo. */
24eab124
AM		 7258 if (*op_string == ABSOLUTE_PREFIX)
7259 {
7260 ++op_string;
7261 if (is_space_char (*op_string))
7262 ++op_string;
40fb9820 7263 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7264 }
7265 goto do_memory_reference;
7266 }
7267 if (*op_string)
7268 {
d0b47220 7269 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7270 return 0;
7271 }
40fb9820
L		 7272 temp = r->reg_type;
7273 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7274 i.types[this_operand] = operand_type_or (i.types[this_operand],
7275 temp);
7d5e4556 7276 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7277 i.op[this_operand].regs = r;
24eab124
AM		 7278 i.reg_operands++;
7279 }
af6bdddf
AM		 7280 else if (*op_string == REGISTER_PREFIX)
7281 {
7282 as_bad (_("bad register name `%s'"), op_string);
7283 return 0;
7284 }
24eab124 7285 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7286 {
24eab124 7287 ++op_string;
40fb9820 7288 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7289 {
d0b47220 7290 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7291 return 0;
7292 }
7293 if (!i386_immediate (op_string))
7294 return 0;
7295 }
7296 else if (is_digit_char (*op_string)
7297 || is_identifier_char (*op_string)
e5cb08ac 7298 || *op_string == '(')
24eab124 7299 {
47926f60 7300 /* This is a memory reference of some sort. */
af6bdddf 7301 char *base_string;
252b5132 7302
47926f60 7303 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7304 char *displacement_string_start;
7305 char *displacement_string_end;
252b5132 7306
24eab124 7307 do_memory_reference:
24eab124 7308 if ((i.mem_operands == 1
40fb9820 7309 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7310 || i.mem_operands == 2)
7311 {
7312 as_bad (_("too many memory references for `%s'"),
7313 current_templates->start->name);
7314 return 0;
7315 }
252b5132 7316
24eab124
AM		 7317 /* Check for base index form. We detect the base index form by
7318 looking for an ')' at the end of the operand, searching
7319 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7320 after the '('. */
af6bdddf 7321 base_string = op_string + strlen (op_string);
c3332e24 7322
af6bdddf
AM		 7323 --base_string;
7324 if (is_space_char (*base_string))
7325 --base_string;
252b5132 7326
47926f60 7327 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7328 displacement_string_start = op_string;
7329 displacement_string_end = base_string + 1;
252b5132 7330
24eab124
AM		 7331 if (*base_string == ')')
7332 {
af6bdddf 7333 char *temp_string;
24eab124
AM		 7334 unsigned int parens_balanced = 1;
7335 /* We've already checked that the number of left & right ()'s are
47926f60 7336 equal, so this loop will not be infinite. */
24eab124
AM		 7337 do
7338 {
7339 base_string--;
7340 if (*base_string == ')')
7341 parens_balanced++;
7342 if (*base_string == '(')
7343 parens_balanced--;
7344 }
7345 while (parens_balanced);
c3332e24 7346
af6bdddf 7347 temp_string = base_string;
c3332e24 7348
24eab124 7349 /* Skip past '(' and whitespace. */
252b5132
RH		 7350 ++base_string;
7351 if (is_space_char (*base_string))
24eab124 7352 ++base_string;
252b5132 7353
af6bdddf 7354 if (*base_string == ','
4eed87de
AM		 7355 || ((i.base_reg = parse_register (base_string, &end_op))
7356 != NULL))
252b5132 7357 {
af6bdddf 7358 displacement_string_end = temp_string;
252b5132 7359
40fb9820 7360 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7361
af6bdddf 7362 if (i.base_reg)
24eab124 7363 {
24eab124
AM		 7364 base_string = end_op;
7365 if (is_space_char (*base_string))
7366 ++base_string;
af6bdddf
AM		 7367 }
7368
7369 /* There may be an index reg or scale factor here. */
7370 if (*base_string == ',')
7371 {
7372 ++base_string;
7373 if (is_space_char (*base_string))
7374 ++base_string;
7375
4eed87de
AM		 7376 if ((i.index_reg = parse_register (base_string, &end_op))
7377 != NULL)
24eab124 7378 {
af6bdddf 7379 base_string = end_op;
24eab124
AM		 7380 if (is_space_char (*base_string))
7381 ++base_string;
af6bdddf
AM		 7382 if (*base_string == ',')
7383 {
7384 ++base_string;
7385 if (is_space_char (*base_string))
7386 ++base_string;
7387 }
e5cb08ac 7388 else if (*base_string != ')')
af6bdddf 7389 {
4eed87de
AM		 7390 as_bad (_("expecting `,' or `)' "
7391 "after index register in `%s'"),
af6bdddf
AM		 7392 operand_string);
7393 return 0;
7394 }
24eab124 7395 }
af6bdddf 7396 else if (*base_string == REGISTER_PREFIX)
24eab124 7397 {
af6bdddf 7398 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7399 return 0;
7400 }
252b5132 7401
47926f60 7402 /* Check for scale factor. */
551c1ca1 7403 if (*base_string != ')')
af6bdddf 7404 {
551c1ca1
AM		 7405 char *end_scale = i386_scale (base_string);
7406
7407 if (!end_scale)
af6bdddf 7408 return 0;
24eab124 7409
551c1ca1 7410 base_string = end_scale;
af6bdddf
AM		 7411 if (is_space_char (*base_string))
7412 ++base_string;
7413 if (*base_string != ')')
7414 {
4eed87de
AM		 7415 as_bad (_("expecting `)' "
7416 "after scale factor in `%s'"),
af6bdddf
AM		 7417 operand_string);
7418 return 0;
7419 }
7420 }
7421 else if (!i.index_reg)
24eab124 7422 {
4eed87de
AM		 7423 as_bad (_("expecting index register or scale factor "
7424 "after `,'; got '%c'"),
af6bdddf 7425 *base_string);
24eab124
AM		 7426 return 0;
7427 }
7428 }
af6bdddf 7429 else if (*base_string != ')')
24eab124 7430 {
4eed87de
AM		 7431 as_bad (_("expecting `,' or `)' "
7432 "after base register in `%s'"),
af6bdddf 7433 operand_string);
24eab124
AM		 7434 return 0;
7435 }
c3332e24 7436 }
af6bdddf 7437 else if (*base_string == REGISTER_PREFIX)
c3332e24 7438 {
af6bdddf 7439 as_bad (_("bad register name `%s'"), base_string);
24eab124 7440 return 0;
c3332e24 7441 }
24eab124
AM		 7442 }
7443
7444 /* If there's an expression beginning the operand, parse it,
7445 assuming displacement_string_start and
7446 displacement_string_end are meaningful. */
7447 if (displacement_string_start != displacement_string_end)
7448 {
7449 if (!i386_displacement (displacement_string_start,
7450 displacement_string_end))
7451 return 0;
7452 }
7453
7454 /* Special case for (%dx) while doing input/output op. */
7455 if (i.base_reg
0dfbf9d7
L		 7456 && operand_type_equal (&i.base_reg->reg_type,
7457 &reg16_inoutportreg)
24eab124
AM		 7458 && i.index_reg == 0
7459 && i.log2_scale_factor == 0
7460 && i.seg[i.mem_operands] == 0
40fb9820 7461 && !operand_type_check (i.types[this_operand], disp))
24eab124 7462 {
65da13b5 7463 i.types[this_operand] = inoutportreg;
24eab124
AM		 7464 return 1;
7465 }
7466
eecb386c
AM		 7467 if (i386_index_check (operand_string) == 0)
7468 return 0;
5c07affc 7469 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7470 i.mem_operands++;
7471 }
7472 else
ce8a8b2f
AM		 7473 {
7474 /* It's not a memory operand; argh! */
24eab124
AM		 7475 as_bad (_("invalid char %s beginning operand %d `%s'"),
7476 output_invalid (*op_string),
7477 this_operand + 1,
7478 op_string);
7479 return 0;
7480 }
47926f60 7481 return 1; /* Normal return. */
252b5132
RH		 7482}
7483\f
ee7fcc42
AM		 7484/* md_estimate_size_before_relax()
7485
7486 Called just before relax() for rs_machine_dependent frags. The x86
7487 assembler uses these frags to handle variable size jump
7488 instructions.
7489
7490 Any symbol that is now undefined will not become defined.
7491 Return the correct fr_subtype in the frag.
7492 Return the initial "guess for variable size of frag" to caller.
7493 The guess is actually the growth beyond the fixed part. Whatever
7494 we do to grow the fixed or variable part contributes to our
7495 returned value. */
7496
252b5132
RH		 7497int
7498md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7499 fragS *fragP;
7500 segT segment;
252b5132 7501{
252b5132 7502 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7503 check for un-relaxable symbols. On an ELF system, we can't relax
7504 an externally visible symbol, because it may be overridden by a
7505 shared library. */
7506 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7507#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7508 || (IS_ELF
31312f95 7509 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7510 || S_IS_WEAK (fragP->fr_symbol)
7511 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7512 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7513#endif
7514#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7515 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7516 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7517#endif
7518 )
252b5132 7519 {
b98ef147
AM		 7520 /* Symbol is undefined in this segment, or we need to keep a
7521 reloc so that weak symbols can be overridden. */
7522 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7523 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7524 unsigned char *opcode;
7525 int old_fr_fix;
f6af82bd 7526
ee7fcc42 7527 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7528 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7529 else if (size == 2)
f6af82bd
AM		 7530 reloc_type = BFD_RELOC_16_PCREL;
7531 else
7532 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7533
ee7fcc42
AM		 7534 old_fr_fix = fragP->fr_fix;
7535 opcode = (unsigned char *) fragP->fr_opcode;
7536
fddf5b5b 7537 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7538 {
fddf5b5b
AM		 7539 case UNCOND_JUMP:
7540 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7541 opcode[0] = 0xe9;
252b5132 7542 fragP->fr_fix += size;
062cd5e7
AS		 7543 fix_new (fragP, old_fr_fix, size,
7544 fragP->fr_symbol,
7545 fragP->fr_offset, 1,
7546 reloc_type);
252b5132
RH		 7547 break;
7548
fddf5b5b 7549 case COND_JUMP86:
412167cb
AM		 7550 if (size == 2
7551 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7552 {
7553 /* Negate the condition, and branch past an
7554 unconditional jump. */
7555 opcode[0] ^= 1;
7556 opcode[1] = 3;
7557 /* Insert an unconditional jump. */
7558 opcode[2] = 0xe9;
7559 /* We added two extra opcode bytes, and have a two byte
7560 offset. */
7561 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7562 fix_new (fragP, old_fr_fix + 2, 2,
7563 fragP->fr_symbol,
7564 fragP->fr_offset, 1,
7565 reloc_type);
fddf5b5b
AM		 7566 break;
7567 }
7568 /* Fall through. */
7569
7570 case COND_JUMP:
412167cb
AM		 7571 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7572 {
3e02c1cc
AM		 7573 fixS *fixP;
7574
412167cb 7575 fragP->fr_fix += 1;
3e02c1cc
AM		 7576 fixP = fix_new (fragP, old_fr_fix, 1,
7577 fragP->fr_symbol,
7578 fragP->fr_offset, 1,
7579 BFD_RELOC_8_PCREL);
7580 fixP->fx_signed = 1;
412167cb
AM		 7581 break;
7582 }
93c2a809 7583
24eab124 7584 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7585 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7586 opcode[1] = opcode[0] + 0x10;
f6af82bd 7587 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7588 /* We've added an opcode byte. */
7589 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7590 fix_new (fragP, old_fr_fix + 1, size,
7591 fragP->fr_symbol,
7592 fragP->fr_offset, 1,
7593 reloc_type);
252b5132 7594 break;
fddf5b5b
AM		 7595
7596 default:
7597 BAD_CASE (fragP->fr_subtype);
7598 break;
252b5132
RH		 7599 }
7600 frag_wane (fragP);
ee7fcc42 7601 return fragP->fr_fix - old_fr_fix;
252b5132 7602 }
93c2a809 7603
93c2a809
AM		 7604 /* Guess size depending on current relax state. Initially the relax
7605 state will correspond to a short jump and we return 1, because
7606 the variable part of the frag (the branch offset) is one byte
7607 long. However, we can relax a section more than once and in that
7608 case we must either set fr_subtype back to the unrelaxed state,
7609 or return the value for the appropriate branch. */
7610 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7611}
7612
47926f60
KH		 7613/* Called after relax() is finished.
7614
7615 In: Address of frag.
7616 fr_type == rs_machine_dependent.
7617 fr_subtype is what the address relaxed to.
7618
7619 Out: Any fixSs and constants are set up.
7620 Caller will turn frag into a ".space 0". */
7621
252b5132
RH		 7622void
7623md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7624 bfd *abfd ATTRIBUTE_UNUSED;
7625 segT sec ATTRIBUTE_UNUSED;
29b0f896 7626 fragS *fragP;
252b5132 7627{
29b0f896 7628 unsigned char *opcode;
252b5132 7629 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7630 offsetT target_address;
7631 offsetT opcode_address;
252b5132 7632 unsigned int extension = 0;
847f7ad4 7633 offsetT displacement_from_opcode_start;
252b5132
RH		 7634
7635 opcode = (unsigned char *) fragP->fr_opcode;
7636
47926f60 7637 /* Address we want to reach in file space. */
252b5132 7638 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7639
47926f60 7640 /* Address opcode resides at in file space. */
252b5132
RH		 7641 opcode_address = fragP->fr_address + fragP->fr_fix;
7642
47926f60 7643 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7644 displacement_from_opcode_start = target_address - opcode_address;
7645
fddf5b5b 7646 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7647 {
47926f60
KH		 7648 /* Don't have to change opcode. */
7649 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7650 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7651 }
7652 else
7653 {
7654 if (no_cond_jump_promotion
7655 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7656 as_warn_where (fragP->fr_file, fragP->fr_line,
7657 _("long jump required"));
252b5132 7658
fddf5b5b
AM		 7659 switch (fragP->fr_subtype)
7660 {
7661 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7662 extension = 4; /* 1 opcode + 4 displacement */
7663 opcode[0] = 0xe9;
7664 where_to_put_displacement = &opcode[1];
7665 break;
252b5132 7666
fddf5b5b
AM		 7667 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7668 extension = 2; /* 1 opcode + 2 displacement */
7669 opcode[0] = 0xe9;
7670 where_to_put_displacement = &opcode[1];
7671 break;
252b5132 7672
fddf5b5b
AM		 7673 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7674 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7675 extension = 5; /* 2 opcode + 4 displacement */
7676 opcode[1] = opcode[0] + 0x10;
7677 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7678 where_to_put_displacement = &opcode[2];
7679 break;
252b5132 7680
fddf5b5b
AM		 7681 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7682 extension = 3; /* 2 opcode + 2 displacement */
7683 opcode[1] = opcode[0] + 0x10;
7684 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7685 where_to_put_displacement = &opcode[2];
7686 break;
252b5132 7687
fddf5b5b
AM		 7688 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7689 extension = 4;
7690 opcode[0] ^= 1;
7691 opcode[1] = 3;
7692 opcode[2] = 0xe9;
7693 where_to_put_displacement = &opcode[3];
7694 break;
7695
7696 default:
7697 BAD_CASE (fragP->fr_subtype);
7698 break;
7699 }
252b5132 7700 }
fddf5b5b 7701
7b81dfbb
AJ		 7702 /* If size if less then four we are sure that the operand fits,
7703 but if it's 4, then it could be that the displacement is larger
7704 then -/+ 2GB. */
7705 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7706 && object_64bit
7707 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7708 + ((addressT) 1 << 31))
7709 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7710 {
7711 as_bad_where (fragP->fr_file, fragP->fr_line,
7712 _("jump target out of range"));
7713 /* Make us emit 0. */
7714 displacement_from_opcode_start = extension;
7715 }
47926f60 7716 /* Now put displacement after opcode. */
252b5132
RH		 7717 md_number_to_chars ((char *) where_to_put_displacement,
7718 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7719 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7720 fragP->fr_fix += extension;
7721}
7722\f
252b5132
RH		 7723/* Apply a fixup (fixS) to segment data, once it has been determined
7724 by our caller that we have all the info we need to fix it up.
7725
7726 On the 386, immediates, displacements, and data pointers are all in
7727 the same (little-endian) format, so we don't need to care about which
7728 we are handling. */
7729
94f592af 7730void
55cf6793 7731md_apply_fix (fixP, valP, seg)
47926f60
KH		 7732 /* The fix we're to put in. */
7733 fixS *fixP;
47926f60 7734 /* Pointer to the value of the bits. */
c6682705 7735 valueT *valP;
47926f60
KH		 7736 /* Segment fix is from. */
7737 segT seg ATTRIBUTE_UNUSED;
252b5132 7738{
94f592af 7739 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7740 valueT value = *valP;
252b5132 7741
f86103b7 7742#if !defined (TE_Mach)
93382f6d
AM		 7743 if (fixP->fx_pcrel)
7744 {
7745 switch (fixP->fx_r_type)
7746 {
5865bb77
ILT		 7747 default:
7748 break;
7749
d6ab8113
JB		 7750 case BFD_RELOC_64:
7751 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7752 break;
93382f6d 7753 case BFD_RELOC_32:
ae8887b5 7754 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7755 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7756 break;
7757 case BFD_RELOC_16:
7758 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7759 break;
7760 case BFD_RELOC_8:
7761 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7762 break;
7763 }
7764 }
252b5132 7765
a161fe53 7766 if (fixP->fx_addsy != NULL
31312f95 7767 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7768 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7769 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7770 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7771 && !use_rela_relocations)
252b5132 7772 {
31312f95
AM		 7773 /* This is a hack. There should be a better way to handle this.
7774 This covers for the fact that bfd_install_relocation will
7775 subtract the current location (for partial_inplace, PC relative
7776 relocations); see more below. */
252b5132 7777#ifndef OBJ_AOUT
718ddfc0 7778 if (IS_ELF
252b5132
RH		 7779#ifdef TE_PE
7780 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7781#endif
7782 )
7783 value += fixP->fx_where + fixP->fx_frag->fr_address;
7784#endif
7785#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7786 if (IS_ELF)
252b5132 7787 {
6539b54b 7788 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7789
6539b54b 7790 if ((sym_seg == seg
2f66722d 7791 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7792 && sym_seg != absolute_section))
af65af87 7793 && !generic_force_reloc (fixP))
2f66722d
AM		 7794 {
7795 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7796 bfd_install_relocation subtracts them out again. I think
7797 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7798 it. FIXME. */
7799 value += fixP->fx_where + fixP->fx_frag->fr_address;
7800 }
252b5132
RH		 7801 }
7802#endif
7803#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7804 /* For some reason, the PE format does not store a
7805 section address offset for a PC relative symbol. */
7806 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7807 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7808 value += md_pcrel_from (fixP);
7809#endif
7810 }
fbeb56a4
DK		 7811#if defined (OBJ_COFF) && defined (TE_PE)
7812 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7813 {
7814 value -= S_GET_VALUE (fixP->fx_addsy);
7815 }
7816#endif
252b5132
RH		 7817
7818 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7819 and we must not disappoint it. */
252b5132 7820#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7821 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7822 switch (fixP->fx_r_type)
7823 {
7824 case BFD_RELOC_386_PLT32:
3e73aa7c 7825 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7826 /* Make the jump instruction point to the address of the operand. At
7827 runtime we merely add the offset to the actual PLT entry. */
7828 value = -4;
7829 break;
31312f95 7830
13ae64f3
JJ		 7831 case BFD_RELOC_386_TLS_GD:
7832 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7833 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7834 case BFD_RELOC_386_TLS_IE:
7835 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7836 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7837 case BFD_RELOC_X86_64_TLSGD:
7838 case BFD_RELOC_X86_64_TLSLD:
7839 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7840 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7841 value = 0; /* Fully resolved at runtime. No addend. */
7842 /* Fallthrough */
7843 case BFD_RELOC_386_TLS_LE:
7844 case BFD_RELOC_386_TLS_LDO_32:
7845 case BFD_RELOC_386_TLS_LE_32:
7846 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7847 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7848 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7849 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7850 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7851 break;
7852
67a4f2b7
AO		 7853 case BFD_RELOC_386_TLS_DESC_CALL:
7854 case BFD_RELOC_X86_64_TLSDESC_CALL:
7855 value = 0; /* Fully resolved at runtime. No addend. */
7856 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7857 fixP->fx_done = 0;
7858 return;
7859
00f7efb6
JJ		 7860 case BFD_RELOC_386_GOT32:
7861 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7862 value = 0; /* Fully resolved at runtime. No addend. */
7863 break;
47926f60
KH		 7864
7865 case BFD_RELOC_VTABLE_INHERIT:
7866 case BFD_RELOC_VTABLE_ENTRY:
7867 fixP->fx_done = 0;
94f592af 7868 return;
47926f60
KH		 7869
7870 default:
7871 break;
7872 }
7873#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7874 *valP = value;
f86103b7 7875#endif /* !defined (TE_Mach) */
3e73aa7c 7876
3e73aa7c 7877 /* Are we finished with this relocation now? */
c6682705 7878 if (fixP->fx_addsy == NULL)
3e73aa7c 7879 fixP->fx_done = 1;
fbeb56a4
DK		 7880#if defined (OBJ_COFF) && defined (TE_PE)
7881 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7882 {
7883 fixP->fx_done = 0;
7884 /* Remember value for tc_gen_reloc. */
7885 fixP->fx_addnumber = value;
7886 /* Clear out the frag for now. */
7887 value = 0;
7888 }
7889#endif
3e73aa7c
JH		 7890 else if (use_rela_relocations)
7891 {
7892 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7893 /* Remember value for tc_gen_reloc. */
7894 fixP->fx_addnumber = value;
3e73aa7c
JH		 7895 value = 0;
7896 }
f86103b7 7897
94f592af 7898 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7899}
252b5132 7900\f
252b5132 7901char *
499ac353 7902md_atof (int type, char *litP, int *sizeP)
252b5132 7903{
499ac353
NC		 7904 /* This outputs the LITTLENUMs in REVERSE order;
7905 in accord with the bigendian 386. */
7906 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7907}
7908\f
2d545b82 7909static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7910
252b5132 7911static char *
e3bb37b5 7912output_invalid (int c)
252b5132 7913{
3882b010 7914 if (ISPRINT (c))
f9f21a03
L		 7915 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7916 "'%c'", c);
252b5132 7917 else
f9f21a03 7918 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7919 "(0x%x)", (unsigned char) c);
252b5132
RH		 7920 return output_invalid_buf;
7921}
7922
af6bdddf 7923/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7924
7925static const reg_entry *
4d1bb795 7926parse_real_register (char *reg_string, char **end_op)
252b5132 7927{
af6bdddf
AM		 7928 char *s = reg_string;
7929 char *p;
252b5132
RH		 7930 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7931 const reg_entry *r;
7932
7933 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7934 if (*s == REGISTER_PREFIX)
7935 ++s;
7936
7937 if (is_space_char (*s))
7938 ++s;
7939
7940 p = reg_name_given;
af6bdddf 7941 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7942 {
7943 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7944 return (const reg_entry *) NULL;
7945 s++;
252b5132
RH		 7946 }
7947
6588847e
DN		 7948 /* For naked regs, make sure that we are not dealing with an identifier.
7949 This prevents confusing an identifier like `eax_var' with register
7950 `eax'. */
7951 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7952 return (const reg_entry *) NULL;
7953
af6bdddf 7954 *end_op = s;
252b5132
RH		 7955
7956 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7957
5f47d35b 7958 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7959 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7960 {
5f47d35b
AM		 7961 if (is_space_char (*s))
7962 ++s;
7963 if (*s == '(')
7964 {
af6bdddf 7965 ++s;
5f47d35b
AM		 7966 if (is_space_char (*s))
7967 ++s;
7968 if (*s >= '0' && *s <= '7')
7969 {
db557034 7970 int fpr = *s - '0';
af6bdddf 7971 ++s;
5f47d35b
AM		 7972 if (is_space_char (*s))
7973 ++s;
7974 if (*s == ')')
7975 {
7976 *end_op = s + 1;
1e9cc1c2 7977 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7978 know (r);
7979 return r + fpr;
5f47d35b 7980 }
5f47d35b 7981 }
47926f60 7982 /* We have "%st(" then garbage. */
5f47d35b
AM		 7983 return (const reg_entry *) NULL;
7984 }
7985 }
7986
a60de03c
JB		 7987 if (r == NULL || allow_pseudo_reg)
7988 return r;
7989
0dfbf9d7 7990 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7991 return (const reg_entry *) NULL;
7992
192dc9c6
JB		 7993 if ((r->reg_type.bitfield.reg32
7994 || r->reg_type.bitfield.sreg3
7995 || r->reg_type.bitfield.control
7996 || r->reg_type.bitfield.debug
7997 || r->reg_type.bitfield.test)
7998 && !cpu_arch_flags.bitfield.cpui386)
7999 return (const reg_entry *) NULL;
8000
309d3373
JB		 8001 if (r->reg_type.bitfield.floatreg
8002 && !cpu_arch_flags.bitfield.cpu8087
8003 && !cpu_arch_flags.bitfield.cpu287
8004 && !cpu_arch_flags.bitfield.cpu387)
8005 return (const reg_entry *) NULL;
8006
192dc9c6
JB		 8007 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
8008 return (const reg_entry *) NULL;
8009
8010 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
8011 return (const reg_entry *) NULL;
8012
40f12533
L		 8013 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
8014 return (const reg_entry *) NULL;
8015
db51cc60 8016 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 8017 if (!allow_index_reg
db51cc60
L		 8018 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
8019 return (const reg_entry *) NULL;
8020
a60de03c
JB		 8021 if (((r->reg_flags & (RegRex64 | RegRex))
8022 || r->reg_type.bitfield.reg64)
40fb9820 8023 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 8024 || !operand_type_equal (&r->reg_type, &control))
1ae00879 8025 && flag_code != CODE_64BIT)
20f0a1fc 8026 return (const reg_entry *) NULL;
1ae00879 8027
b7240065
JB		 8028 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
8029 return (const reg_entry *) NULL;
8030
252b5132
RH		 8031 return r;
8032}
4d1bb795
JB		 8033
8034/* REG_STRING starts *before* REGISTER_PREFIX. */
8035
8036static const reg_entry *
8037parse_register (char *reg_string, char **end_op)
8038{
8039 const reg_entry *r;
8040
8041 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
8042 r = parse_real_register (reg_string, end_op);
8043 else
8044 r = NULL;
8045 if (!r)
8046 {
8047 char *save = input_line_pointer;
8048 char c;
8049 symbolS *symbolP;
8050
8051 input_line_pointer = reg_string;
8052 c = get_symbol_end ();
8053 symbolP = symbol_find (reg_string);
8054 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
8055 {
8056 const expressionS *e = symbol_get_value_expression (symbolP);
8057
0398aac5 8058 know (e->X_op == O_register);
4eed87de 8059 know (e->X_add_number >= 0
c3fe08fa 8060 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 8061 r = i386_regtab + e->X_add_number;
8062 *end_op = input_line_pointer;
8063 }
8064 *input_line_pointer = c;
8065 input_line_pointer = save;
8066 }
8067 return r;
8068}
8069
8070int
8071i386_parse_name (char *name, expressionS *e, char *nextcharP)
8072{
8073 const reg_entry *r;
8074 char *end = input_line_pointer;
8075
8076 *end = *nextcharP;
8077 r = parse_register (name, &input_line_pointer);
8078 if (r && end <= input_line_pointer)
8079 {
8080 *nextcharP = *input_line_pointer;
8081 *input_line_pointer = 0;
8082 e->X_op = O_register;
8083 e->X_add_number = r - i386_regtab;
8084 return 1;
8085 }
8086 input_line_pointer = end;
8087 *end = 0;
ee86248c 8088 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8089}
8090
8091void
8092md_operand (expressionS *e)
8093{
ee86248c
JB		 8094 char *end;
8095 const reg_entry *r;
4d1bb795 8096
ee86248c
JB		 8097 switch (*input_line_pointer)
8098 {
8099 case REGISTER_PREFIX:
8100 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8101 if (r)
8102 {
8103 e->X_op = O_register;
8104 e->X_add_number = r - i386_regtab;
8105 input_line_pointer = end;
8106 }
ee86248c
JB		 8107 break;
8108
8109 case '[':
9c2799c2 8110 gas_assert (intel_syntax);
ee86248c
JB		 8111 end = input_line_pointer++;
8112 expression (e);
8113 if (*input_line_pointer == ']')
8114 {
8115 ++input_line_pointer;
8116 e->X_op_symbol = make_expr_symbol (e);
8117 e->X_add_symbol = NULL;
8118 e->X_add_number = 0;
8119 e->X_op = O_index;
8120 }
8121 else
8122 {
8123 e->X_op = O_absent;
8124 input_line_pointer = end;
8125 }
8126 break;
4d1bb795
JB		 8127 }
8128}
8129
252b5132 8130\f
4cc782b5 8131#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8132const char *md_shortopts = "kVQ:sqn";
252b5132 8133#else
12b55ccc 8134const char *md_shortopts = "qn";
252b5132 8135#endif
6e0b89ee 8136
3e73aa7c 8137#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8138#define OPTION_64 (OPTION_MD_BASE + 1)
8139#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8140#define OPTION_MARCH (OPTION_MD_BASE + 3)
8141#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8142#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8143#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8144#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8145#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8146#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8147#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8148#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
40a9833c 8149#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
351f65ca 8150#define OPTION_N32 (OPTION_MD_BASE + 13)
b3b91714 8151
99ad8390
NC		 8152struct option md_longopts[] =
8153{
3e73aa7c 8154 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 8155#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8156 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 8157 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 8158#endif
8159#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8160 {"n32", no_argument, NULL, OPTION_N32},
6e0b89ee 8161#endif
b3b91714 8162 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8163 {"march", required_argument, NULL, OPTION_MARCH},
8164 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8165 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8166 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8167 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8168 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8169 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8170 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8171 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
539f890d 8172 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8173 {NULL, no_argument, NULL, 0}
8174};
8175size_t md_longopts_size = sizeof (md_longopts);
8176
8177int
9103f4f4 8178md_parse_option (int c, char *arg)
252b5132 8179{
91d6fa6a 8180 unsigned int j;
6305a203 8181 char *arch, *next;
9103f4f4 8182
252b5132
RH		 8183 switch (c)
8184 {
12b55ccc
L		 8185 case 'n':
8186 optimize_align_code = 0;
8187 break;
8188
a38cf1db
AM		 8189 case 'q':
8190 quiet_warnings = 1;
252b5132
RH		 8191 break;
8192
8193#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8194 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8195 should be emitted or not. FIXME: Not implemented. */
8196 case 'Q':
252b5132
RH		 8197 break;
8198
8199 /* -V: SVR4 argument to print version ID. */
8200 case 'V':
8201 print_version_id ();
8202 break;
8203
a38cf1db
AM		 8204 /* -k: Ignore for FreeBSD compatibility. */
8205 case 'k':
252b5132 8206 break;
4cc782b5
ILT		 8207
8208 case 's':
8209 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8210 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8211 break;
99ad8390 8212#endif
321098a5
L		 8213#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8214 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 8215 case OPTION_64:
8216 {
8217 const char **list, **l;
8218
3e73aa7c
JH		 8219 list = bfd_target_list ();
8220 for (l = list; *l != NULL; l++)
8620418b 8221 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8222 || strcmp (*l, "coff-x86-64") == 0
8223 || strcmp (*l, "pe-x86-64") == 0
8224 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8225 {
8226 default_arch = "x86_64";
8227 break;
8228 }
3e73aa7c 8229 if (*l == NULL)
6e0b89ee 8230 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 8231 free (list);
8232 }
8233 break;
8234#endif
252b5132 8235
351f65ca
L		 8236#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8237 case OPTION_N32:
8238 if (IS_ELF)
8239 {
8240 const char **list, **l;
8241
8242 list = bfd_target_list ();
8243 for (l = list; *l != NULL; l++)
8244 if (CONST_STRNEQ (*l, "elf32-x86-64"))
8245 {
8246 default_arch = "x86_64:32";
8247 break;
8248 }
8249 if (*l == NULL)
8250 as_fatal (_("No compiled in support for 32bit x86_64"));
8251 free (list);
8252 }
8253 else
8254 as_fatal (_("32bit x86_64 is only supported for ELF"));
8255 break;
8256#endif
8257
6e0b89ee
AM		 8258 case OPTION_32:
8259 default_arch = "i386";
8260 break;
8261
b3b91714
AM		 8262 case OPTION_DIVIDE:
8263#ifdef SVR4_COMMENT_CHARS
8264 {
8265 char *n, *t;
8266 const char *s;
8267
8268 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8269 t = n;
8270 for (s = i386_comment_chars; *s != '\0'; s++)
8271 if (*s != '/')
8272 *t++ = *s;
8273 *t = '\0';
8274 i386_comment_chars = n;
8275 }
8276#endif
8277 break;
8278
9103f4f4 8279 case OPTION_MARCH:
6305a203
L		 8280 arch = xstrdup (arg);
8281 do
9103f4f4 8282 {
6305a203
L		 8283 if (*arch == '.')
8284 as_fatal (_("Invalid -march= option: `%s'"), arg);
8285 next = strchr (arch, '+');
8286 if (next)
8287 *next++ = '\0';
91d6fa6a 8288 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8289 {
91d6fa6a 8290 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8291 {
6305a203 8292 /* Processor. */
1ded5609
JB		 8293 if (! cpu_arch[j].flags.bitfield.cpui386)
8294 continue;
8295
91d6fa6a 8296 cpu_arch_name = cpu_arch[j].name;
6305a203 8297 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8298 cpu_arch_flags = cpu_arch[j].flags;
8299 cpu_arch_isa = cpu_arch[j].type;
8300 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8301 if (!cpu_arch_tune_set)
8302 {
8303 cpu_arch_tune = cpu_arch_isa;
8304 cpu_arch_tune_flags = cpu_arch_isa_flags;
8305 }
8306 break;
8307 }
91d6fa6a
NC		 8308 else if (*cpu_arch [j].name == '.'
8309 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8310 {
8311 /* ISA entension. */
8312 i386_cpu_flags flags;
309d3373 8313
49021df2 8314 if (!cpu_arch[j].negated)
309d3373 8315 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8316 cpu_arch[j].flags);
309d3373
JB		 8317 else
8318 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 8319 cpu_arch[j].flags);
0dfbf9d7 8320 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8321 {
8322 if (cpu_sub_arch_name)
8323 {
8324 char *name = cpu_sub_arch_name;
8325 cpu_sub_arch_name = concat (name,
91d6fa6a 8326 cpu_arch[j].name,
1bf57e9f 8327 (const char *) NULL);
6305a203
L		 8328 free (name);
8329 }
8330 else
91d6fa6a 8331 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203
L		 8332 cpu_arch_flags = flags;
8333 }
8334 break;
ccc9c027 8335 }
9103f4f4 8336 }
6305a203 8337
91d6fa6a 8338 if (j >= ARRAY_SIZE (cpu_arch))
6305a203
L		 8339 as_fatal (_("Invalid -march= option: `%s'"), arg);
8340
8341 arch = next;
9103f4f4 8342 }
6305a203 8343 while (next != NULL );
9103f4f4
L		 8344 break;
8345
8346 case OPTION_MTUNE:
8347 if (*arg == '.')
8348 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
91d6fa6a 8349 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8350 {
91d6fa6a 8351 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8352 {
ccc9c027 8353 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8354 cpu_arch_tune = cpu_arch [j].type;
8355 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8356 break;
8357 }
8358 }
91d6fa6a 8359 if (j >= ARRAY_SIZE (cpu_arch))
9103f4f4
L		 8360 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8361 break;
8362
1efbbeb4
L		 8363 case OPTION_MMNEMONIC:
8364 if (strcasecmp (arg, "att") == 0)
8365 intel_mnemonic = 0;
8366 else if (strcasecmp (arg, "intel") == 0)
8367 intel_mnemonic = 1;
8368 else
8369 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8370 break;
8371
8372 case OPTION_MSYNTAX:
8373 if (strcasecmp (arg, "att") == 0)
8374 intel_syntax = 0;
8375 else if (strcasecmp (arg, "intel") == 0)
8376 intel_syntax = 1;
8377 else
8378 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8379 break;
8380
8381 case OPTION_MINDEX_REG:
8382 allow_index_reg = 1;
8383 break;
8384
8385 case OPTION_MNAKED_REG:
8386 allow_naked_reg = 1;
8387 break;
8388
8389 case OPTION_MOLD_GCC:
8390 old_gcc = 1;
1efbbeb4
L		 8391 break;
8392
c0f3af97
L		 8393 case OPTION_MSSE2AVX:
8394 sse2avx = 1;
8395 break;
8396
daf50ae7
L		 8397 case OPTION_MSSE_CHECK:
8398 if (strcasecmp (arg, "error") == 0)
8399 sse_check = sse_check_error;
8400 else if (strcasecmp (arg, "warning") == 0)
8401 sse_check = sse_check_warning;
8402 else if (strcasecmp (arg, "none") == 0)
8403 sse_check = sse_check_none;
8404 else
8405 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8406 break;
8407
539f890d
L		 8408 case OPTION_MAVXSCALAR:
8409 if (strcasecmp (arg, "128") == 0)
8410 avxscalar = vex128;
8411 else if (strcasecmp (arg, "256") == 0)
8412 avxscalar = vex256;
8413 else
8414 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg);
8415 break;
8416
252b5132
RH		 8417 default:
8418 return 0;
8419 }
8420 return 1;
8421}
8422
8a2c8fef
L		 8423#define MESSAGE_TEMPLATE \
8424" "
8425
8426static void
1ded5609 8427show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 8428{
8429 static char message[] = MESSAGE_TEMPLATE;
8430 char *start = message + 27;
8431 char *p;
8432 int size = sizeof (MESSAGE_TEMPLATE);
8433 int left;
8434 const char *name;
8435 int len;
8436 unsigned int j;
8437
8438 p = start;
8439 left = size - (start - message);
8440 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8441 {
8442 /* Should it be skipped? */
8443 if (cpu_arch [j].skip)
8444 continue;
8445
8446 name = cpu_arch [j].name;
8447 len = cpu_arch [j].len;
8448 if (*name == '.')
8449 {
8450 /* It is an extension. Skip if we aren't asked to show it. */
8451 if (ext)
8452 {
8453 name++;
8454 len--;
8455 }
8456 else
8457 continue;
8458 }
8459 else if (ext)
8460 {
8461 /* It is an processor. Skip if we show only extension. */
8462 continue;
8463 }
1ded5609
JB		 8464 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
8465 {
8466 /* It is an impossible processor - skip. */
8467 continue;
8468 }
8a2c8fef
L		 8469
8470 /* Reserve 2 spaces for ", " or ",\0" */
8471 left -= len + 2;
8472
8473 /* Check if there is any room. */
8474 if (left >= 0)
8475 {
8476 if (p != start)
8477 {
8478 *p++ = ',';
8479 *p++ = ' ';
8480 }
8481 p = mempcpy (p, name, len);
8482 }
8483 else
8484 {
8485 /* Output the current message now and start a new one. */
8486 *p++ = ',';
8487 *p = '\0';
8488 fprintf (stream, "%s\n", message);
8489 p = start;
8490 left = size - (start - message) - len - 2;
8491
8492 gas_assert (left >= 0);
8493
8494 p = mempcpy (p, name, len);
8495 }
8496 }
8497
8498 *p = '\0';
8499 fprintf (stream, "%s\n", message);
8500}
8501
252b5132 8502void
8a2c8fef 8503md_show_usage (FILE *stream)
252b5132 8504{
4cc782b5
ILT		 8505#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8506 fprintf (stream, _("\
a38cf1db
AM		 8507 -Q ignored\n\
8508 -V print assembler version number\n\
b3b91714
AM		 8509 -k ignored\n"));
8510#endif
8511 fprintf (stream, _("\
12b55ccc 8512 -n Do not optimize code alignment\n\
b3b91714
AM		 8513 -q quieten some warnings\n"));
8514#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8515 fprintf (stream, _("\
a38cf1db 8516 -s ignored\n"));
b3b91714 8517#endif
321098a5
L		 8518#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8519 || defined (TE_PE) || defined (TE_PEP))
751d281c 8520 fprintf (stream, _("\
351f65ca 8521 --32/--64/--n32 generate 32bit/64bit/n32bit code\n"));
751d281c 8522#endif
b3b91714
AM		 8523#ifdef SVR4_COMMENT_CHARS
8524 fprintf (stream, _("\
8525 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8526#else
8527 fprintf (stream, _("\
b3b91714 8528 --divide ignored\n"));
4cc782b5 8529#endif
9103f4f4 8530 fprintf (stream, _("\
6305a203 8531 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 8532 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 8533 show_arch (stream, 0, 1);
8a2c8fef
L		 8534 fprintf (stream, _("\
8535 EXTENSION is combination of:\n"));
1ded5609 8536 show_arch (stream, 1, 0);
6305a203 8537 fprintf (stream, _("\
8a2c8fef 8538 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 8539 show_arch (stream, 0, 0);
ba104c83 8540 fprintf (stream, _("\
c0f3af97
L		 8541 -msse2avx encode SSE instructions with VEX prefix\n"));
8542 fprintf (stream, _("\
daf50ae7
L		 8543 -msse-check=[none|error|warning]\n\
8544 check SSE instructions\n"));
8545 fprintf (stream, _("\
539f890d
L		 8546 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8547 length\n"));
8548 fprintf (stream, _("\
ba104c83
L		 8549 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8550 fprintf (stream, _("\
8551 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8552 fprintf (stream, _("\
8553 -mindex-reg support pseudo index registers\n"));
8554 fprintf (stream, _("\
8555 -mnaked-reg don't require `%%' prefix for registers\n"));
8556 fprintf (stream, _("\
8557 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8558}
8559
3e73aa7c 8560#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8561 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8562 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8563
8564/* Pick the target format to use. */
8565
47926f60 8566const char *
e3bb37b5 8567i386_target_format (void)
252b5132 8568{
351f65ca
L		 8569 if (!strncmp (default_arch, "x86_64", 6))
8570 {
8571 update_code_flag (CODE_64BIT, 1);
8572 if (default_arch[6] == '\0')
8573 x86_elf_abi = X86_64_LP64_ABI;
8574 else
8575 x86_elf_abi = X86_64_ILP32_ABI;
8576 }
3e73aa7c 8577 else if (!strcmp (default_arch, "i386"))
78f12dd3 8578 update_code_flag (CODE_32BIT, 1);
3e73aa7c
JH		 8579 else
8580 as_fatal (_("Unknown architecture"));
89507696
JB		 8581
8582 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8583 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8584 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8585 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8586
252b5132
RH		 8587 switch (OUTPUT_FLAVOR)
8588 {
9384f2ff 8589#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8590 case bfd_target_aout_flavour:
47926f60 8591 return AOUT_TARGET_FORMAT;
4c63da97 8592#endif
9384f2ff
AM		 8593#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8594# if defined (TE_PE) || defined (TE_PEP)
8595 case bfd_target_coff_flavour:
8596 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8597# elif defined (TE_GO32)
0561d57c
JK		 8598 case bfd_target_coff_flavour:
8599 return "coff-go32";
9384f2ff 8600# else
252b5132
RH		 8601 case bfd_target_coff_flavour:
8602 return "coff-i386";
9384f2ff 8603# endif
4c63da97 8604#endif
3e73aa7c 8605#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8606 case bfd_target_elf_flavour:
3e73aa7c 8607 {
351f65ca
L		 8608 const char *format;
8609
8610 switch (x86_elf_abi)
4fa24527 8611 {
351f65ca
L		 8612 default:
8613 format = ELF_TARGET_FORMAT;
8614 break;
8615 case X86_64_LP64_ABI:
8616 use_rela_relocations = 1;
4fa24527 8617 object_64bit = 1;
351f65ca
L		 8618 format = ELF_TARGET_FORMAT64;
8619 break;
8620 case X86_64_ILP32_ABI:
4fa24527 8621 use_rela_relocations = 1;
351f65ca
L		 8622 object_64bit = 1;
8623 format = ELF_TARGET_FORMAT32;
8624 break;
4fa24527 8625 }
3632d14b 8626 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 8627 {
351f65ca 8628 if (x86_elf_abi != X86_64_LP64_ABI)
8a9036a4
L		 8629 as_fatal (_("Intel L1OM is 64bit only"));
8630 return ELF_TARGET_L1OM_FORMAT;
8631 }
8632 else
351f65ca 8633 return format;
3e73aa7c 8634 }
e57f8c65
TG		 8635#endif
8636#if defined (OBJ_MACH_O)
8637 case bfd_target_mach_o_flavour:
8638 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8639#endif
252b5132
RH		 8640 default:
8641 abort ();
8642 return NULL;
8643 }
8644}
8645
47926f60 8646#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8647
8648#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8649void
8650i386_elf_emit_arch_note (void)
a847613f 8651{
718ddfc0 8652 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8653 {
8654 char *p;
8655 asection *seg = now_seg;
8656 subsegT subseg = now_subseg;
8657 Elf_Internal_Note i_note;
8658 Elf_External_Note e_note;
8659 asection *note_secp;
8660 int len;
8661
8662 /* Create the .note section. */
8663 note_secp = subseg_new (".note", 0);
8664 bfd_set_section_flags (stdoutput,
8665 note_secp,
8666 SEC_HAS_CONTENTS | SEC_READONLY);
8667
8668 /* Process the arch string. */
8669 len = strlen (cpu_arch_name);
8670
8671 i_note.namesz = len + 1;
8672 i_note.descsz = 0;
8673 i_note.type = NT_ARCH;
8674 p = frag_more (sizeof (e_note.namesz));
8675 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8676 p = frag_more (sizeof (e_note.descsz));
8677 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8678 p = frag_more (sizeof (e_note.type));
8679 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8680 p = frag_more (len + 1);
8681 strcpy (p, cpu_arch_name);
8682
8683 frag_align (2, 0, 0);
8684
8685 subseg_set (seg, subseg);
8686 }
8687}
8688#endif
252b5132 8689\f
252b5132
RH		 8690symbolS *
8691md_undefined_symbol (name)
8692 char *name;
8693{
18dc2407
ILT		 8694 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8695 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8696 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8697 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8698 {
8699 if (!GOT_symbol)
8700 {
8701 if (symbol_find (name))
8702 as_bad (_("GOT already in symbol table"));
8703 GOT_symbol = symbol_new (name, undefined_section,
8704 (valueT) 0, &zero_address_frag);
8705 };
8706 return GOT_symbol;
8707 }
252b5132
RH		 8708 return 0;
8709}
8710
8711/* Round up a section size to the appropriate boundary. */
47926f60 8712
252b5132
RH		 8713valueT
8714md_section_align (segment, size)
ab9da554 8715 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8716 valueT size;
8717{
4c63da97
AM		 8718#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8719 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8720 {
8721 /* For a.out, force the section size to be aligned. If we don't do
8722 this, BFD will align it for us, but it will not write out the
8723 final bytes of the section. This may be a bug in BFD, but it is
8724 easier to fix it here since that is how the other a.out targets
8725 work. */
8726 int align;
8727
8728 align = bfd_get_section_alignment (stdoutput, segment);
8729 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8730 }
252b5132
RH		 8731#endif
8732
8733 return size;
8734}
8735
8736/* On the i386, PC-relative offsets are relative to the start of the
8737 next instruction. That is, the address of the offset, plus its
8738 size, since the offset is always the last part of the insn. */
8739
8740long
e3bb37b5 8741md_pcrel_from (fixS *fixP)
252b5132
RH		 8742{
8743 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8744}
8745
8746#ifndef I386COFF
8747
8748static void
e3bb37b5 8749s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8750{
29b0f896 8751 int temp;
252b5132 8752
8a75718c
JB		 8753#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8754 if (IS_ELF)
8755 obj_elf_section_change_hook ();
8756#endif
252b5132
RH		 8757 temp = get_absolute_expression ();
8758 subseg_set (bss_section, (subsegT) temp);
8759 demand_empty_rest_of_line ();
8760}
8761
8762#endif
8763
252b5132 8764void
e3bb37b5 8765i386_validate_fix (fixS *fixp)
252b5132
RH		 8766{
8767 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8768 {
23df1078
JH		 8769 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8770 {
4fa24527 8771 if (!object_64bit)
23df1078
JH		 8772 abort ();
8773 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8774 }
8775 else
8776 {
4fa24527 8777 if (!object_64bit)
d6ab8113
JB		 8778 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8779 else
8780 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8781 }
252b5132
RH		 8782 fixp->fx_subsy = 0;
8783 }
8784}
8785
252b5132
RH		 8786arelent *
8787tc_gen_reloc (section, fixp)
ab9da554 8788 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8789 fixS *fixp;
8790{
8791 arelent *rel;
8792 bfd_reloc_code_real_type code;
8793
8794 switch (fixp->fx_r_type)
8795 {
3e73aa7c
JH		 8796 case BFD_RELOC_X86_64_PLT32:
8797 case BFD_RELOC_X86_64_GOT32:
8798 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8799 case BFD_RELOC_386_PLT32:
8800 case BFD_RELOC_386_GOT32:
8801 case BFD_RELOC_386_GOTOFF:
8802 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8803 case BFD_RELOC_386_TLS_GD:
8804 case BFD_RELOC_386_TLS_LDM:
8805 case BFD_RELOC_386_TLS_LDO_32:
8806 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8807 case BFD_RELOC_386_TLS_IE:
8808 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8809 case BFD_RELOC_386_TLS_LE_32:
8810 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8811 case BFD_RELOC_386_TLS_GOTDESC:
8812 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8813 case BFD_RELOC_X86_64_TLSGD:
8814 case BFD_RELOC_X86_64_TLSLD:
8815 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8816 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8817 case BFD_RELOC_X86_64_GOTTPOFF:
8818 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8819 case BFD_RELOC_X86_64_TPOFF64:
8820 case BFD_RELOC_X86_64_GOTOFF64:
8821 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8822 case BFD_RELOC_X86_64_GOT64:
8823 case BFD_RELOC_X86_64_GOTPCREL64:
8824 case BFD_RELOC_X86_64_GOTPC64:
8825 case BFD_RELOC_X86_64_GOTPLT64:
8826 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8827 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8828 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8829 case BFD_RELOC_RVA:
8830 case BFD_RELOC_VTABLE_ENTRY:
8831 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8832#ifdef TE_PE
8833 case BFD_RELOC_32_SECREL:
8834#endif
252b5132
RH		 8835 code = fixp->fx_r_type;
8836 break;
dbbaec26
L		 8837 case BFD_RELOC_X86_64_32S:
8838 if (!fixp->fx_pcrel)
8839 {
8840 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8841 code = fixp->fx_r_type;
8842 break;
8843 }
252b5132 8844 default:
93382f6d 8845 if (fixp->fx_pcrel)
252b5132 8846 {
93382f6d
AM		 8847 switch (fixp->fx_size)
8848 {
8849 default:
b091f402
AM		 8850 as_bad_where (fixp->fx_file, fixp->fx_line,
8851 _("can not do %d byte pc-relative relocation"),
8852 fixp->fx_size);
93382f6d
AM		 8853 code = BFD_RELOC_32_PCREL;
8854 break;
8855 case 1: code = BFD_RELOC_8_PCREL; break;
8856 case 2: code = BFD_RELOC_16_PCREL; break;
8857 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8858#ifdef BFD64
8859 case 8: code = BFD_RELOC_64_PCREL; break;
8860#endif
93382f6d
AM		 8861 }
8862 }
8863 else
8864 {
8865 switch (fixp->fx_size)
8866 {
8867 default:
b091f402
AM		 8868 as_bad_where (fixp->fx_file, fixp->fx_line,
8869 _("can not do %d byte relocation"),
8870 fixp->fx_size);
93382f6d
AM		 8871 code = BFD_RELOC_32;
8872 break;
8873 case 1: code = BFD_RELOC_8; break;
8874 case 2: code = BFD_RELOC_16; break;
8875 case 4: code = BFD_RELOC_32; break;
937149dd 8876#ifdef BFD64
3e73aa7c 8877 case 8: code = BFD_RELOC_64; break;
937149dd 8878#endif
93382f6d 8879 }
252b5132
RH		 8880 }
8881 break;
8882 }
252b5132 8883
d182319b
JB		 8884 if ((code == BFD_RELOC_32
8885 || code == BFD_RELOC_32_PCREL
8886 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8887 && GOT_symbol
8888 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8889 {
4fa24527 8890 if (!object_64bit)
d6ab8113
JB		 8891 code = BFD_RELOC_386_GOTPC;
8892 else
8893 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8894 }
7b81dfbb
AJ		 8895 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8896 && GOT_symbol
8897 && fixp->fx_addsy == GOT_symbol)
8898 {
8899 code = BFD_RELOC_X86_64_GOTPC64;
8900 }
252b5132
RH		 8901
8902 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8903 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8904 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8905
8906 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8907
3e73aa7c
JH		 8908 if (!use_rela_relocations)
8909 {
8910 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8911 vtable entry to be used in the relocation's section offset. */
8912 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8913 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8914#if defined (OBJ_COFF) && defined (TE_PE)
8915 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8916 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8917 else
8918#endif
c6682705 8919 rel->addend = 0;
3e73aa7c
JH		 8920 }
8921 /* Use the rela in 64bit mode. */
252b5132 8922 else
3e73aa7c 8923 {
062cd5e7
AS		 8924 if (!fixp->fx_pcrel)
8925 rel->addend = fixp->fx_offset;
8926 else
8927 switch (code)
8928 {
8929 case BFD_RELOC_X86_64_PLT32:
8930 case BFD_RELOC_X86_64_GOT32:
8931 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8932 case BFD_RELOC_X86_64_TLSGD:
8933 case BFD_RELOC_X86_64_TLSLD:
8934 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8935 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8936 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8937 rel->addend = fixp->fx_offset - fixp->fx_size;
8938 break;
8939 default:
8940 rel->addend = (section->vma
8941 - fixp->fx_size
8942 + fixp->fx_addnumber
8943 + md_pcrel_from (fixp));
8944 break;
8945 }
3e73aa7c
JH		 8946 }
8947
252b5132
RH		 8948 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8949 if (rel->howto == NULL)
8950 {
8951 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8952 _("cannot represent relocation type %s"),
252b5132
RH		 8953 bfd_get_reloc_code_name (code));
8954 /* Set howto to a garbage value so that we can keep going. */
8955 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8956 gas_assert (rel->howto != NULL);
252b5132
RH		 8957 }
8958
8959 return rel;
8960}
8961
ee86248c 8962#include "tc-i386-intel.c"
54cfded0 8963
a60de03c
JB		 8964void
8965tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8966{
a60de03c
JB		 8967 int saved_naked_reg;
8968 char saved_register_dot;
54cfded0 8969
a60de03c
JB		 8970 saved_naked_reg = allow_naked_reg;
8971 allow_naked_reg = 1;
8972 saved_register_dot = register_chars['.'];
8973 register_chars['.'] = '.';
8974 allow_pseudo_reg = 1;
8975 expression_and_evaluate (exp);
8976 allow_pseudo_reg = 0;
8977 register_chars['.'] = saved_register_dot;
8978 allow_naked_reg = saved_naked_reg;
8979
e96d56a1 8980 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8981 {
a60de03c
JB		 8982 if ((addressT) exp->X_add_number < i386_regtab_size)
8983 {
8984 exp->X_op = O_constant;
8985 exp->X_add_number = i386_regtab[exp->X_add_number]
8986 .dw2_regnum[flag_code >> 1];
8987 }
8988 else
8989 exp->X_op = O_illegal;
54cfded0 8990 }
54cfded0
AM		 8991}
8992
8993void
8994tc_x86_frame_initial_instructions (void)
8995{
a60de03c
JB		 8996 static unsigned int sp_regno[2];
8997
8998 if (!sp_regno[flag_code >> 1])
8999 {
9000 char *saved_input = input_line_pointer;
9001 char sp[][4] = {"esp", "rsp"};
9002 expressionS exp;
a4447b93 9003
a60de03c
JB		 9004 input_line_pointer = sp[flag_code >> 1];
9005 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 9006 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 9007 sp_regno[flag_code >> 1] = exp.X_add_number;
9008 input_line_pointer = saved_input;
9009 }
a4447b93 9010
a60de03c 9011 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 9012 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9013}
d2b2c203
DJ		 9014
9015int
9016i386_elf_section_type (const char *str, size_t len)
9017{
9018 if (flag_code == CODE_64BIT
9019 && len == sizeof ("unwind") - 1
9020 && strncmp (str, "unwind", 6) == 0)
9021 return SHT_X86_64_UNWIND;
9022
9023 return -1;
9024}
bb41ade5 9025
ad5fec3b
EB		 9026#ifdef TE_SOLARIS
9027void
9028i386_solaris_fix_up_eh_frame (segT sec)
9029{
9030 if (flag_code == CODE_64BIT)
9031 elf_section_type (sec) = SHT_X86_64_UNWIND;
9032}
9033#endif
9034
bb41ade5
AM		 9035#ifdef TE_PE
9036void
9037tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9038{
91d6fa6a 9039 expressionS exp;
bb41ade5 9040
91d6fa6a
NC		 9041 exp.X_op = O_secrel;
9042 exp.X_add_symbol = symbol;
9043 exp.X_add_number = 0;
9044 emit_expr (&exp, size);
bb41ade5
AM		 9045}
9046#endif
3b22753a
L		 9047
9048#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9049/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9050
01e1a5bc 9051bfd_vma
3b22753a
L		 9052x86_64_section_letter (int letter, char **ptr_msg)
9053{
9054 if (flag_code == CODE_64BIT)
9055 {
9056 if (letter == 'l')
9057 return SHF_X86_64_LARGE;
9058
8f3bae45 9059 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9060 }
3b22753a 9061 else
8f3bae45 9062 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9063 return -1;
9064}
9065
01e1a5bc 9066bfd_vma
3b22753a
L		 9067x86_64_section_word (char *str, size_t len)
9068{
8620418b 9069 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9070 return SHF_X86_64_LARGE;
9071
9072 return -1;
9073}
9074
9075static void
9076handle_large_common (int small ATTRIBUTE_UNUSED)
9077{
9078 if (flag_code != CODE_64BIT)
9079 {
9080 s_comm_internal (0, elf_common_parse);
9081 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9082 }
9083 else
9084 {
9085 static segT lbss_section;
9086 asection *saved_com_section_ptr = elf_com_section_ptr;
9087 asection *saved_bss_section = bss_section;
9088
9089 if (lbss_section == NULL)
9090 {
9091 flagword applicable;
9092 segT seg = now_seg;
9093 subsegT subseg = now_subseg;
9094
9095 /* The .lbss section is for local .largecomm symbols. */
9096 lbss_section = subseg_new (".lbss", 0);
9097 applicable = bfd_applicable_section_flags (stdoutput);
9098 bfd_set_section_flags (stdoutput, lbss_section,
9099 applicable & SEC_ALLOC);
9100 seg_info (lbss_section)->bss = 1;
9101
9102 subseg_set (seg, subseg);
9103 }
9104
9105 elf_com_section_ptr = &_bfd_elf_large_com_section;
9106 bss_section = lbss_section;
9107
9108 s_comm_internal (0, elf_common_parse);
9109
9110 elf_com_section_ptr = saved_com_section_ptr;
9111 bss_section = saved_bss_section;
9112 }
9113}
9114#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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