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Add mangled names to addr2line -i output.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
aef6203b 3 2000, 2001, 2002, 2003, 2004, 2005
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 107static void output_imm PARAMS ((fragS *insn_start_frag,
108 offsetT insn_start_off));
109static void output_disp PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
29b0f896
AM		 111#ifndef I386COFF
112static void s_bss PARAMS ((int));
252b5132 113#endif
17d4e2a2
L		 114#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
115static void handle_large_common (int small ATTRIBUTE_UNUSED);
116#endif
252b5132 117
a847613f 118static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 119
252b5132 120/* 'md_assemble ()' gathers together information and puts it into a
47926f60 121 i386_insn. */
252b5132 122
520dc8e8
AM		 123union i386_op
124 {
125 expressionS *disps;
126 expressionS *imms;
127 const reg_entry *regs;
128 };
129
252b5132
RH		 130struct _i386_insn
131 {
47926f60 132 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 133 template tm;
134
135 /* SUFFIX holds the instruction mnemonic suffix if given.
136 (e.g. 'l' for 'movl') */
137 char suffix;
138
47926f60 139 /* OPERANDS gives the number of given operands. */
252b5132
RH		 140 unsigned int operands;
141
142 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
143 of given register, displacement, memory operands and immediate
47926f60 144 operands. */
252b5132
RH		 145 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
146
147 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 148 use OP[i] for the corresponding operand. */
252b5132
RH		 149 unsigned int types[MAX_OPERANDS];
150
520dc8e8
AM		 151 /* Displacement expression, immediate expression, or register for each
152 operand. */
153 union i386_op op[MAX_OPERANDS];
252b5132 154
3e73aa7c
JH		 155 /* Flags for operands. */
156 unsigned int flags[MAX_OPERANDS];
157#define Operand_PCrel 1
158
252b5132 159 /* Relocation type for operand */
f86103b7 160 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 161
252b5132
RH		 162 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
163 the base index byte below. */
164 const reg_entry *base_reg;
165 const reg_entry *index_reg;
166 unsigned int log2_scale_factor;
167
168 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 169 explicit segment overrides are given. */
ce8a8b2f 170 const seg_entry *seg[2];
252b5132
RH		 171
172 /* PREFIX holds all the given prefix opcodes (usually null).
173 PREFIXES is the number of prefix opcodes. */
174 unsigned int prefixes;
175 unsigned char prefix[MAX_PREFIXES];
176
177 /* RM and SIB are the modrm byte and the sib byte where the
178 addressing modes of this insn are encoded. */
179
180 modrm_byte rm;
3e73aa7c 181 rex_byte rex;
252b5132
RH		 182 sib_byte sib;
183 };
184
185typedef struct _i386_insn i386_insn;
186
187/* List of chars besides those in app.c:symbol_chars that can start an
188 operand. Used to prevent the scrubber eating vital white-space. */
32137342 189const char extra_symbol_chars[] = "*%-(["
252b5132 190#ifdef LEX_AT
32137342
NC		 191 "@"
192#endif
193#ifdef LEX_QM
194 "?"
252b5132 195#endif
32137342 196 ;
252b5132 197
29b0f896
AM		 198#if (defined (TE_I386AIX) \
199 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
200 && !defined (TE_LINUX) \
32137342 201 && !defined (TE_NETWARE) \
29b0f896
AM		 202 && !defined (TE_FreeBSD) \
203 && !defined (TE_NetBSD)))
252b5132 204/* This array holds the chars that always start a comment. If the
ce8a8b2f 205 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 206const char comment_chars[] = "#/";
207#define PREFIX_SEPARATOR '\\'
252b5132
RH		 208
209/* This array holds the chars that only start a comment at the beginning of
210 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 211 .line and .file directives will appear in the pre-processed output.
212 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 213 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 214 #NO_APP at the beginning of its output.
215 Also note that comments started like this one will always work if
252b5132 216 '/' isn't otherwise defined. */
0d9f6d04 217const char line_comment_chars[] = "#";
29b0f896 218
252b5132 219#else
29b0f896
AM		 220/* Putting '/' here makes it impossible to use the divide operator.
221 However, we need it for compatibility with SVR4 systems. */
222const char comment_chars[] = "#";
223#define PREFIX_SEPARATOR '/'
224
0d9f6d04 225const char line_comment_chars[] = "/#";
252b5132
RH		 226#endif
227
63a0b638 228const char line_separator_chars[] = ";";
252b5132 229
ce8a8b2f
AM		 230/* Chars that can be used to separate mant from exp in floating point
231 nums. */
252b5132
RH		 232const char EXP_CHARS[] = "eE";
233
ce8a8b2f
AM		 234/* Chars that mean this number is a floating point constant
235 As in 0f12.456
236 or 0d1.2345e12. */
252b5132
RH		 237const char FLT_CHARS[] = "fFdDxX";
238
ce8a8b2f 239/* Tables for lexical analysis. */
252b5132
RH		 240static char mnemonic_chars[256];
241static char register_chars[256];
242static char operand_chars[256];
243static char identifier_chars[256];
244static char digit_chars[256];
245
ce8a8b2f 246/* Lexical macros. */
252b5132
RH		 247#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
248#define is_operand_char(x) (operand_chars[(unsigned char) x])
249#define is_register_char(x) (register_chars[(unsigned char) x])
250#define is_space_char(x) ((x) == ' ')
251#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
252#define is_digit_char(x) (digit_chars[(unsigned char) x])
253
0234cb7c 254/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 255static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
256
257/* md_assemble() always leaves the strings it's passed unaltered. To
258 effect this we maintain a stack of saved characters that we've smashed
259 with '\0's (indicating end of strings for various sub-fields of the
47926f60 260 assembler instruction). */
252b5132 261static char save_stack[32];
ce8a8b2f 262static char *save_stack_p;
252b5132
RH		 263#define END_STRING_AND_SAVE(s) \
264 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
265#define RESTORE_END_STRING(s) \
266 do { *(s) = *--save_stack_p; } while (0)
267
47926f60 268/* The instruction we're assembling. */
252b5132
RH		 269static i386_insn i;
270
271/* Possible templates for current insn. */
272static const templates *current_templates;
273
47926f60 274/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 275static expressionS disp_expressions[2], im_expressions[2];
276
47926f60
KH		 277/* Current operand we are working on. */
278static int this_operand;
252b5132 279
3e73aa7c
JH		 280/* We support four different modes. FLAG_CODE variable is used to distinguish
281 these. */
282
283enum flag_code {
284 CODE_32BIT,
285 CODE_16BIT,
286 CODE_64BIT };
f3c180ae 287#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 288
289static enum flag_code flag_code;
4fa24527 290static unsigned int object_64bit;
3e73aa7c
JH		 291static int use_rela_relocations = 0;
292
293/* The names used to print error messages. */
b77a7acd 294static const char *flag_code_names[] =
3e73aa7c
JH		 295 {
296 "32",
297 "16",
298 "64"
299 };
252b5132 300
47926f60
KH		 301/* 1 for intel syntax,
302 0 if att syntax. */
303static int intel_syntax = 0;
252b5132 304
47926f60
KH		 305/* 1 if register prefix % not required. */
306static int allow_naked_reg = 0;
252b5132 307
47926f60
KH		 308/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
309 leave, push, and pop instructions so that gcc has the same stack
310 frame as in 32 bit mode. */
311static char stackop_size = '\0';
eecb386c 312
12b55ccc
L		 313/* Non-zero to optimize code alignment. */
314int optimize_align_code = 1;
315
47926f60
KH		 316/* Non-zero to quieten some warnings. */
317static int quiet_warnings = 0;
a38cf1db 318
47926f60
KH		 319/* CPU name. */
320static const char *cpu_arch_name = NULL;
5c6af06e 321static const char *cpu_sub_arch_name = NULL;
a38cf1db 322
47926f60 323/* CPU feature flags. */
29b0f896 324static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 325
fddf5b5b
AM		 326/* If set, conditional jumps are not automatically promoted to handle
327 larger than a byte offset. */
328static unsigned int no_cond_jump_promotion = 0;
329
29b0f896 330/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 331static symbolS *GOT_symbol;
29b0f896 332
a4447b93
RH		 333/* The dwarf2 return column, adjusted for 32 or 64 bit. */
334unsigned int x86_dwarf2_return_column;
335
336/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
337int x86_cie_data_alignment;
338
252b5132 339/* Interface to relax_segment.
fddf5b5b
AM		 340 There are 3 major relax states for 386 jump insns because the
341 different types of jumps add different sizes to frags when we're
342 figuring out what sort of jump to choose to reach a given label. */
252b5132 343
47926f60 344/* Types. */
93c2a809
AM		 345#define UNCOND_JUMP 0
346#define COND_JUMP 1
347#define COND_JUMP86 2
fddf5b5b 348
47926f60 349/* Sizes. */
252b5132
RH		 350#define CODE16 1
351#define SMALL 0
29b0f896 352#define SMALL16 (SMALL | CODE16)
252b5132 353#define BIG 2
29b0f896 354#define BIG16 (BIG | CODE16)
252b5132
RH		 355
356#ifndef INLINE
357#ifdef __GNUC__
358#define INLINE __inline__
359#else
360#define INLINE
361#endif
362#endif
363
fddf5b5b
AM		 364#define ENCODE_RELAX_STATE(type, size) \
365 ((relax_substateT) (((type) << 2) | (size)))
366#define TYPE_FROM_RELAX_STATE(s) \
367 ((s) >> 2)
368#define DISP_SIZE_FROM_RELAX_STATE(s) \
369 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 370
371/* This table is used by relax_frag to promote short jumps to long
372 ones where necessary. SMALL (short) jumps may be promoted to BIG
373 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
374 don't allow a short jump in a 32 bit code segment to be promoted to
375 a 16 bit offset jump because it's slower (requires data size
376 prefix), and doesn't work, unless the destination is in the bottom
377 64k of the code segment (The top 16 bits of eip are zeroed). */
378
379const relax_typeS md_relax_table[] =
380{
24eab124
AM		 381 /* The fields are:
382 1) most positive reach of this state,
383 2) most negative reach of this state,
93c2a809 384 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 385 4) which index into the table to try if we can't fit into this one. */
252b5132 386
fddf5b5b 387 /* UNCOND_JUMP states. */
93c2a809
AM		 388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
390 /* dword jmp adds 4 bytes to frag:
391 0 extra opcode bytes, 4 displacement bytes. */
252b5132 392 {0, 0, 4, 0},
93c2a809
AM		 393 /* word jmp adds 2 byte2 to frag:
394 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 395 {0, 0, 2, 0},
396
93c2a809
AM		 397 /* COND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
400 /* dword conditionals adds 5 bytes to frag:
401 1 extra opcode byte, 4 displacement bytes. */
402 {0, 0, 5, 0},
fddf5b5b 403 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 404 1 extra opcode byte, 2 displacement bytes. */
405 {0, 0, 3, 0},
406
407 /* COND_JUMP86 states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
412 {0, 0, 5, 0},
413 /* word conditionals add 4 bytes to frag:
414 1 displacement byte and a 3 byte long branch insn. */
415 {0, 0, 4, 0}
252b5132
RH		 416};
417
e413e4e9
AM		 418static const arch_entry cpu_arch[] = {
419 {"i8086", Cpu086 },
420 {"i186", Cpu086|Cpu186 },
421 {"i286", Cpu086|Cpu186|Cpu286 },
422 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
423 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
5c6af06e
JB		 424 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
425 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
426 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
427 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
428 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
429 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
430 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
431 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
432 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
433 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
434 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
435 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
30123838 436 {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
5c6af06e
JB		 437 {".mmx", CpuMMX },
438 {".sse", CpuMMX|CpuMMX2|CpuSSE },
439 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
bf50992e 440 {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
5c6af06e
JB		 441 {".3dnow", CpuMMX|Cpu3dnow },
442 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
443 {".padlock", CpuPadLock },
30123838
JB		 444 {".pacifica", CpuSVME },
445 {".svme", CpuSVME },
e413e4e9
AM		 446 {NULL, 0 }
447};
448
29b0f896
AM		 449const pseudo_typeS md_pseudo_table[] =
450{
451#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
452 {"align", s_align_bytes, 0},
453#else
454 {"align", s_align_ptwo, 0},
455#endif
456 {"arch", set_cpu_arch, 0},
457#ifndef I386COFF
458 {"bss", s_bss, 0},
459#endif
460 {"ffloat", float_cons, 'f'},
461 {"dfloat", float_cons, 'd'},
462 {"tfloat", float_cons, 'x'},
463 {"value", cons, 2},
464 {"noopt", s_ignore, 0},
465 {"optim", s_ignore, 0},
466 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
467 {"code16", set_code_flag, CODE_16BIT},
468 {"code32", set_code_flag, CODE_32BIT},
469 {"code64", set_code_flag, CODE_64BIT},
470 {"intel_syntax", set_intel_syntax, 1},
471 {"att_syntax", set_intel_syntax, 0},
c6682705 472 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
29b0f896 473 {"loc", dwarf2_directive_loc, 0},
3b22753a
L		 474#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
475 {"largecomm", handle_large_common, 0},
476#endif
6482c264
NC		 477#ifdef TE_PE
478 {"secrel32", pe_directive_secrel, 0},
479#endif
29b0f896
AM		 480 {0, 0, 0}
481};
482
483/* For interface with expression (). */
484extern char *input_line_pointer;
485
486/* Hash table for instruction mnemonic lookup. */
487static struct hash_control *op_hash;
488
489/* Hash table for register lookup. */
490static struct hash_control *reg_hash;
491\f
252b5132
RH		 492void
493i386_align_code (fragP, count)
494 fragS *fragP;
495 int count;
496{
ce8a8b2f
AM		 497 /* Various efficient no-op patterns for aligning code labels.
498 Note: Don't try to assemble the instructions in the comments.
499 0L and 0w are not legal. */
252b5132
RH		 500 static const char f32_1[] =
501 {0x90}; /* nop */
502 static const char f32_2[] =
503 {0x89,0xf6}; /* movl %esi,%esi */
504 static const char f32_3[] =
505 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
506 static const char f32_4[] =
507 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
508 static const char f32_5[] =
509 {0x90, /* nop */
510 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
511 static const char f32_6[] =
512 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
513 static const char f32_7[] =
514 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
515 static const char f32_8[] =
516 {0x90, /* nop */
517 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
518 static const char f32_9[] =
519 {0x89,0xf6, /* movl %esi,%esi */
520 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
521 static const char f32_10[] =
522 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
523 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
524 static const char f32_11[] =
525 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
526 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
527 static const char f32_12[] =
528 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
529 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
530 static const char f32_13[] =
531 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
532 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
533 static const char f32_14[] =
534 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
535 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
536 static const char f32_15[] =
537 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
538 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 539 static const char f16_3[] =
540 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 541 static const char f16_4[] =
542 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
543 static const char f16_5[] =
544 {0x90, /* nop */
545 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
546 static const char f16_6[] =
547 {0x89,0xf6, /* mov %si,%si */
548 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
549 static const char f16_7[] =
550 {0x8d,0x74,0x00, /* lea 0(%si),%si */
551 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
552 static const char f16_8[] =
553 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
554 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
555 static const char *const f32_patt[] = {
556 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
557 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
558 };
559 static const char *const f16_patt[] = {
c3332e24 560 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 561 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
562 };
563
33fef721
JH		 564 if (count <= 0 || count > 15)
565 return;
3e73aa7c 566
33fef721
JH		 567 /* The recommended way to pad 64bit code is to use NOPs preceded by
568 maximally four 0x66 prefixes. Balance the size of nops. */
569 if (flag_code == CODE_64BIT)
252b5132 570 {
33fef721
JH		 571 int i;
572 int nnops = (count + 3) / 4;
573 int len = count / nnops;
574 int remains = count - nnops * len;
575 int pos = 0;
576
577 for (i = 0; i < remains; i++)
252b5132 578 {
33fef721
JH		 579 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
580 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
581 pos += len + 1;
582 }
583 for (; i < nnops; i++)
584 {
585 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
586 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
587 pos += len;
252b5132 588 }
252b5132 589 }
33fef721
JH		 590 else
591 if (flag_code == CODE_16BIT)
592 {
593 memcpy (fragP->fr_literal + fragP->fr_fix,
594 f16_patt[count - 1], count);
595 if (count > 8)
596 /* Adjust jump offset. */
597 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
598 }
599 else
600 memcpy (fragP->fr_literal + fragP->fr_fix,
601 f32_patt[count - 1], count);
602 fragP->fr_var = count;
252b5132
RH		 603}
604
252b5132
RH		 605static INLINE unsigned int
606mode_from_disp_size (t)
607 unsigned int t;
608{
3e73aa7c 609 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 610}
611
612static INLINE int
613fits_in_signed_byte (num)
847f7ad4 614 offsetT num;
252b5132
RH		 615{
616 return (num >= -128) && (num <= 127);
47926f60 617}
252b5132
RH		 618
619static INLINE int
620fits_in_unsigned_byte (num)
847f7ad4 621 offsetT num;
252b5132
RH		 622{
623 return (num & 0xff) == num;
47926f60 624}
252b5132
RH		 625
626static INLINE int
627fits_in_unsigned_word (num)
847f7ad4 628 offsetT num;
252b5132
RH		 629{
630 return (num & 0xffff) == num;
47926f60 631}
252b5132
RH		 632
633static INLINE int
634fits_in_signed_word (num)
847f7ad4 635 offsetT num;
252b5132
RH		 636{
637 return (-32768 <= num) && (num <= 32767);
47926f60 638}
3e73aa7c
JH		 639static INLINE int
640fits_in_signed_long (num)
641 offsetT num ATTRIBUTE_UNUSED;
642{
643#ifndef BFD64
644 return 1;
645#else
646 return (!(((offsetT) -1 << 31) & num)
647 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
648#endif
649} /* fits_in_signed_long() */
650static INLINE int
651fits_in_unsigned_long (num)
652 offsetT num ATTRIBUTE_UNUSED;
653{
654#ifndef BFD64
655 return 1;
656#else
657 return (num & (((offsetT) 2 << 31) - 1)) == num;
658#endif
659} /* fits_in_unsigned_long() */
252b5132
RH		 660
661static int
662smallest_imm_type (num)
847f7ad4 663 offsetT num;
252b5132 664{
a847613f 665 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 666 {
667 /* This code is disabled on the 486 because all the Imm1 forms
668 in the opcode table are slower on the i486. They're the
669 versions with the implicitly specified single-position
670 displacement, which has another syntax if you really want to
671 use that form. */
672 if (num == 1)
3e73aa7c 673 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 674 }
252b5132 675 return (fits_in_signed_byte (num)
3e73aa7c 676 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 677 : fits_in_unsigned_byte (num)
3e73aa7c 678 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 679 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 680 ? (Imm16 | Imm32 | Imm32S | Imm64)
681 : fits_in_signed_long (num)
682 ? (Imm32 | Imm32S | Imm64)
683 : fits_in_unsigned_long (num)
684 ? (Imm32 | Imm64)
685 : Imm64);
47926f60 686}
252b5132 687
847f7ad4
AM		 688static offsetT
689offset_in_range (val, size)
690 offsetT val;
691 int size;
692{
508866be 693 addressT mask;
ba2adb93 694
847f7ad4
AM		 695 switch (size)
696 {
508866be
L		 697 case 1: mask = ((addressT) 1 << 8) - 1; break;
698 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 699 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 700#ifdef BFD64
701 case 8: mask = ((addressT) 2 << 63) - 1; break;
702#endif
47926f60 703 default: abort ();
847f7ad4
AM		 704 }
705
ba2adb93 706 /* If BFD64, sign extend val. */
3e73aa7c
JH		 707 if (!use_rela_relocations)
708 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
709 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 710
47926f60 711 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 712 {
713 char buf1[40], buf2[40];
714
715 sprint_value (buf1, val);
716 sprint_value (buf2, val & mask);
717 as_warn (_("%s shortened to %s"), buf1, buf2);
718 }
719 return val & mask;
720}
721
252b5132
RH		 722/* Returns 0 if attempting to add a prefix where one from the same
723 class already exists, 1 if non rep/repne added, 2 if rep/repne
724 added. */
725static int
726add_prefix (prefix)
727 unsigned int prefix;
728{
729 int ret = 1;
730 int q;
731
29b0f896
AM		 732 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
733 && flag_code == CODE_64BIT)
3e73aa7c
JH		 734 q = REX_PREFIX;
735 else
736 switch (prefix)
737 {
738 default:
739 abort ();
740
741 case CS_PREFIX_OPCODE:
742 case DS_PREFIX_OPCODE:
743 case ES_PREFIX_OPCODE:
744 case FS_PREFIX_OPCODE:
745 case GS_PREFIX_OPCODE:
746 case SS_PREFIX_OPCODE:
747 q = SEG_PREFIX;
748 break;
252b5132 749
3e73aa7c
JH		 750 case REPNE_PREFIX_OPCODE:
751 case REPE_PREFIX_OPCODE:
752 ret = 2;
753 /* fall thru */
754 case LOCK_PREFIX_OPCODE:
755 q = LOCKREP_PREFIX;
756 break;
252b5132 757
3e73aa7c
JH		 758 case FWAIT_OPCODE:
759 q = WAIT_PREFIX;
760 break;
252b5132 761
3e73aa7c
JH		 762 case ADDR_PREFIX_OPCODE:
763 q = ADDR_PREFIX;
764 break;
252b5132 765
3e73aa7c
JH		 766 case DATA_PREFIX_OPCODE:
767 q = DATA_PREFIX;
768 break;
769 }
252b5132 770
29b0f896 771 if (i.prefix[q] != 0)
252b5132
RH		 772 {
773 as_bad (_("same type of prefix used twice"));
774 return 0;
775 }
776
777 i.prefixes += 1;
778 i.prefix[q] = prefix;
779 return ret;
780}
781
782static void
3e73aa7c 783set_code_flag (value)
e5cb08ac 784 int value;
eecb386c 785{
3e73aa7c
JH		 786 flag_code = value;
787 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
788 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
789 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
790 {
791 as_bad (_("64bit mode not supported on this CPU."));
792 }
793 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
794 {
795 as_bad (_("32bit mode not supported on this CPU."));
796 }
eecb386c
AM		 797 stackop_size = '\0';
798}
799
800static void
3e73aa7c
JH		 801set_16bit_gcc_code_flag (new_code_flag)
802 int new_code_flag;
252b5132 803{
3e73aa7c
JH		 804 flag_code = new_code_flag;
805 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
806 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 807 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 808}
809
810static void
811set_intel_syntax (syntax_flag)
eecb386c 812 int syntax_flag;
252b5132
RH		 813{
814 /* Find out if register prefixing is specified. */
815 int ask_naked_reg = 0;
816
817 SKIP_WHITESPACE ();
29b0f896 818 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 819 {
820 char *string = input_line_pointer;
821 int e = get_symbol_end ();
822
47926f60 823 if (strcmp (string, "prefix") == 0)
252b5132 824 ask_naked_reg = 1;
47926f60 825 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 826 ask_naked_reg = -1;
827 else
d0b47220 828 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 829 *input_line_pointer = e;
830 }
831 demand_empty_rest_of_line ();
c3332e24 832
252b5132
RH		 833 intel_syntax = syntax_flag;
834
835 if (ask_naked_reg == 0)
f86103b7
AM		 836 allow_naked_reg = (intel_syntax
837 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 838 else
839 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 840
841 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
842 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 843}
844
e413e4e9
AM		 845static void
846set_cpu_arch (dummy)
47926f60 847 int dummy ATTRIBUTE_UNUSED;
e413e4e9 848{
47926f60 849 SKIP_WHITESPACE ();
e413e4e9 850
29b0f896 851 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 852 {
853 char *string = input_line_pointer;
854 int e = get_symbol_end ();
855 int i;
856
857 for (i = 0; cpu_arch[i].name; i++)
858 {
859 if (strcmp (string, cpu_arch[i].name) == 0)
860 {
5c6af06e
JB		 861 if (*string != '.')
862 {
863 cpu_arch_name = cpu_arch[i].name;
864 cpu_sub_arch_name = NULL;
865 cpu_arch_flags = (cpu_arch[i].flags
866 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
867 break;
868 }
869 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
870 {
871 cpu_sub_arch_name = cpu_arch[i].name;
872 cpu_arch_flags |= cpu_arch[i].flags;
873 }
874 *input_line_pointer = e;
875 demand_empty_rest_of_line ();
876 return;
e413e4e9
AM		 877 }
878 }
879 if (!cpu_arch[i].name)
880 as_bad (_("no such architecture: `%s'"), string);
881
882 *input_line_pointer = e;
883 }
884 else
885 as_bad (_("missing cpu architecture"));
886
fddf5b5b
AM		 887 no_cond_jump_promotion = 0;
888 if (*input_line_pointer == ','
29b0f896 889 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 890 {
891 char *string = ++input_line_pointer;
892 int e = get_symbol_end ();
893
894 if (strcmp (string, "nojumps") == 0)
895 no_cond_jump_promotion = 1;
896 else if (strcmp (string, "jumps") == 0)
897 ;
898 else
899 as_bad (_("no such architecture modifier: `%s'"), string);
900
901 *input_line_pointer = e;
902 }
903
e413e4e9
AM		 904 demand_empty_rest_of_line ();
905}
906
b9d79e03
JH		 907unsigned long
908i386_mach ()
909{
910 if (!strcmp (default_arch, "x86_64"))
911 return bfd_mach_x86_64;
912 else if (!strcmp (default_arch, "i386"))
913 return bfd_mach_i386_i386;
914 else
915 as_fatal (_("Unknown architecture"));
916}
b9d79e03 917\f
252b5132
RH		 918void
919md_begin ()
920{
921 const char *hash_err;
922
47926f60 923 /* Initialize op_hash hash table. */
252b5132
RH		 924 op_hash = hash_new ();
925
926 {
29b0f896
AM		 927 const template *optab;
928 templates *core_optab;
252b5132 929
47926f60
KH		 930 /* Setup for loop. */
931 optab = i386_optab;
252b5132
RH		 932 core_optab = (templates *) xmalloc (sizeof (templates));
933 core_optab->start = optab;
934
935 while (1)
936 {
937 ++optab;
938 if (optab->name == NULL
939 || strcmp (optab->name, (optab - 1)->name) != 0)
940 {
941 /* different name --> ship out current template list;
47926f60 942 add to hash table; & begin anew. */
252b5132
RH		 943 core_optab->end = optab;
944 hash_err = hash_insert (op_hash,
945 (optab - 1)->name,
946 (PTR) core_optab);
947 if (hash_err)
948 {
252b5132
RH		 949 as_fatal (_("Internal Error: Can't hash %s: %s"),
950 (optab - 1)->name,
951 hash_err);
952 }
953 if (optab->name == NULL)
954 break;
955 core_optab = (templates *) xmalloc (sizeof (templates));
956 core_optab->start = optab;
957 }
958 }
959 }
960
47926f60 961 /* Initialize reg_hash hash table. */
252b5132
RH		 962 reg_hash = hash_new ();
963 {
29b0f896 964 const reg_entry *regtab;
252b5132
RH		 965
966 for (regtab = i386_regtab;
967 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
968 regtab++)
969 {
970 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
971 if (hash_err)
3e73aa7c
JH		 972 as_fatal (_("Internal Error: Can't hash %s: %s"),
973 regtab->reg_name,
974 hash_err);
252b5132
RH		 975 }
976 }
977
47926f60 978 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 979 {
29b0f896
AM		 980 int c;
981 char *p;
252b5132
RH		 982
983 for (c = 0; c < 256; c++)
984 {
3882b010 985 if (ISDIGIT (c))
252b5132
RH		 986 {
987 digit_chars[c] = c;
988 mnemonic_chars[c] = c;
989 register_chars[c] = c;
990 operand_chars[c] = c;
991 }
3882b010 992 else if (ISLOWER (c))
252b5132
RH		 993 {
994 mnemonic_chars[c] = c;
995 register_chars[c] = c;
996 operand_chars[c] = c;
997 }
3882b010 998 else if (ISUPPER (c))
252b5132 999 {
3882b010 1000 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1001 register_chars[c] = mnemonic_chars[c];
1002 operand_chars[c] = c;
1003 }
1004
3882b010 1005 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1006 identifier_chars[c] = c;
1007 else if (c >= 128)
1008 {
1009 identifier_chars[c] = c;
1010 operand_chars[c] = c;
1011 }
1012 }
1013
1014#ifdef LEX_AT
1015 identifier_chars['@'] = '@';
32137342
NC		 1016#endif
1017#ifdef LEX_QM
1018 identifier_chars['?'] = '?';
1019 operand_chars['?'] = '?';
252b5132 1020#endif
252b5132 1021 digit_chars['-'] = '-';
791fe849 1022 mnemonic_chars['-'] = '-';
252b5132
RH		 1023 identifier_chars['_'] = '_';
1024 identifier_chars['.'] = '.';
1025
1026 for (p = operand_special_chars; *p != '\0'; p++)
1027 operand_chars[(unsigned char) *p] = *p;
1028 }
1029
1030#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1031 if (IS_ELF)
252b5132
RH		 1032 {
1033 record_alignment (text_section, 2);
1034 record_alignment (data_section, 2);
1035 record_alignment (bss_section, 2);
1036 }
1037#endif
a4447b93
RH		 1038
1039 if (flag_code == CODE_64BIT)
1040 {
1041 x86_dwarf2_return_column = 16;
1042 x86_cie_data_alignment = -8;
1043 }
1044 else
1045 {
1046 x86_dwarf2_return_column = 8;
1047 x86_cie_data_alignment = -4;
1048 }
252b5132
RH		 1049}
1050
1051void
1052i386_print_statistics (file)
1053 FILE *file;
1054{
1055 hash_print_statistics (file, "i386 opcode", op_hash);
1056 hash_print_statistics (file, "i386 register", reg_hash);
1057}
1058\f
252b5132
RH		 1059#ifdef DEBUG386
1060
ce8a8b2f 1061/* Debugging routines for md_assemble. */
252b5132
RH		 1062static void pi PARAMS ((char *, i386_insn *));
1063static void pte PARAMS ((template *));
1064static void pt PARAMS ((unsigned int));
1065static void pe PARAMS ((expressionS *));
1066static void ps PARAMS ((symbolS *));
1067
1068static void
1069pi (line, x)
1070 char *line;
1071 i386_insn *x;
1072{
09f131f2 1073 unsigned int i;
252b5132
RH		 1074
1075 fprintf (stdout, "%s: template ", line);
1076 pte (&x->tm);
09f131f2
JH		 1077 fprintf (stdout, " address: base %s index %s scale %x\n",
1078 x->base_reg ? x->base_reg->reg_name : "none",
1079 x->index_reg ? x->index_reg->reg_name : "none",
1080 x->log2_scale_factor);
1081 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1082 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1083 fprintf (stdout, " sib: base %x index %x scale %x\n",
1084 x->sib.base, x->sib.index, x->sib.scale);
1085 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1086 (x->rex & REX_MODE64) != 0,
1087 (x->rex & REX_EXTX) != 0,
1088 (x->rex & REX_EXTY) != 0,
1089 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1090 for (i = 0; i < x->operands; i++)
1091 {
1092 fprintf (stdout, " #%d: ", i + 1);
1093 pt (x->types[i]);
1094 fprintf (stdout, "\n");
1095 if (x->types[i]
3f4438ab 1096 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1097 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1098 if (x->types[i] & Imm)
520dc8e8 1099 pe (x->op[i].imms);
252b5132 1100 if (x->types[i] & Disp)
520dc8e8 1101 pe (x->op[i].disps);
252b5132
RH		 1102 }
1103}
1104
1105static void
1106pte (t)
1107 template *t;
1108{
09f131f2 1109 unsigned int i;
252b5132 1110 fprintf (stdout, " %d operands ", t->operands);
47926f60 1111 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1112 if (t->extension_opcode != None)
1113 fprintf (stdout, "ext %x ", t->extension_opcode);
1114 if (t->opcode_modifier & D)
1115 fprintf (stdout, "D");
1116 if (t->opcode_modifier & W)
1117 fprintf (stdout, "W");
1118 fprintf (stdout, "\n");
1119 for (i = 0; i < t->operands; i++)
1120 {
1121 fprintf (stdout, " #%d type ", i + 1);
1122 pt (t->operand_types[i]);
1123 fprintf (stdout, "\n");
1124 }
1125}
1126
1127static void
1128pe (e)
1129 expressionS *e;
1130{
24eab124 1131 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1132 fprintf (stdout, " add_number %ld (%lx)\n",
1133 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1134 if (e->X_add_symbol)
1135 {
1136 fprintf (stdout, " add_symbol ");
1137 ps (e->X_add_symbol);
1138 fprintf (stdout, "\n");
1139 }
1140 if (e->X_op_symbol)
1141 {
1142 fprintf (stdout, " op_symbol ");
1143 ps (e->X_op_symbol);
1144 fprintf (stdout, "\n");
1145 }
1146}
1147
1148static void
1149ps (s)
1150 symbolS *s;
1151{
1152 fprintf (stdout, "%s type %s%s",
1153 S_GET_NAME (s),
1154 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1155 segment_name (S_GET_SEGMENT (s)));
1156}
1157
1158struct type_name
1159 {
1160 unsigned int mask;
1161 char *tname;
1162 }
1163
29b0f896 1164static const type_names[] =
252b5132
RH		 1165{
1166 { Reg8, "r8" },
1167 { Reg16, "r16" },
1168 { Reg32, "r32" },
09f131f2 1169 { Reg64, "r64" },
252b5132
RH		 1170 { Imm8, "i8" },
1171 { Imm8S, "i8s" },
1172 { Imm16, "i16" },
1173 { Imm32, "i32" },
09f131f2
JH		 1174 { Imm32S, "i32s" },
1175 { Imm64, "i64" },
252b5132
RH		 1176 { Imm1, "i1" },
1177 { BaseIndex, "BaseIndex" },
1178 { Disp8, "d8" },
1179 { Disp16, "d16" },
1180 { Disp32, "d32" },
09f131f2
JH		 1181 { Disp32S, "d32s" },
1182 { Disp64, "d64" },
252b5132
RH		 1183 { InOutPortReg, "InOutPortReg" },
1184 { ShiftCount, "ShiftCount" },
1185 { Control, "control reg" },
1186 { Test, "test reg" },
1187 { Debug, "debug reg" },
1188 { FloatReg, "FReg" },
1189 { FloatAcc, "FAcc" },
1190 { SReg2, "SReg2" },
1191 { SReg3, "SReg3" },
1192 { Acc, "Acc" },
1193 { JumpAbsolute, "Jump Absolute" },
1194 { RegMMX, "rMMX" },
3f4438ab 1195 { RegXMM, "rXMM" },
252b5132
RH		 1196 { EsSeg, "es" },
1197 { 0, "" }
1198};
1199
1200static void
1201pt (t)
1202 unsigned int t;
1203{
29b0f896 1204 const struct type_name *ty;
252b5132 1205
09f131f2
JH		 1206 for (ty = type_names; ty->mask; ty++)
1207 if (t & ty->mask)
1208 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1209 fflush (stdout);
1210}
1211
1212#endif /* DEBUG386 */
1213\f
252b5132 1214static bfd_reloc_code_real_type
3956db08
JB		 1215reloc (unsigned int size,
1216 int pcrel,
1217 int sign,
1218 bfd_reloc_code_real_type other)
252b5132 1219{
47926f60 1220 if (other != NO_RELOC)
3956db08
JB		 1221 {
1222 reloc_howto_type *reloc;
1223
1224 if (size == 8)
1225 switch (other)
1226 {
1227 case BFD_RELOC_X86_64_TPOFF32:
1228 other = BFD_RELOC_X86_64_TPOFF64;
1229 break;
1230 case BFD_RELOC_X86_64_DTPOFF32:
1231 other = BFD_RELOC_X86_64_DTPOFF64;
1232 break;
1233 default:
1234 break;
1235 }
1236 reloc = bfd_reloc_type_lookup (stdoutput, other);
1237 if (!reloc)
1238 as_bad (_("unknown relocation (%u)"), other);
1239 else if (size != bfd_get_reloc_size (reloc))
1240 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1241 bfd_get_reloc_size (reloc),
1242 size);
1243 else if (pcrel && !reloc->pc_relative)
1244 as_bad (_("non-pc-relative relocation for pc-relative field"));
1245 else if ((reloc->complain_on_overflow == complain_overflow_signed
1246 && !sign)
1247 || (reloc->complain_on_overflow == complain_overflow_unsigned
1248 && sign > 0))
1249 as_bad (_("relocated field and relocation type differ in signedness"));
1250 else
1251 return other;
1252 return NO_RELOC;
1253 }
252b5132
RH		 1254
1255 if (pcrel)
1256 {
3e73aa7c 1257 if (!sign)
3956db08 1258 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1259 switch (size)
1260 {
1261 case 1: return BFD_RELOC_8_PCREL;
1262 case 2: return BFD_RELOC_16_PCREL;
1263 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1264 case 8: return BFD_RELOC_64_PCREL;
252b5132 1265 }
3956db08 1266 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1267 }
1268 else
1269 {
3956db08 1270 if (sign > 0)
e5cb08ac 1271 switch (size)
3e73aa7c
JH		 1272 {
1273 case 4: return BFD_RELOC_X86_64_32S;
1274 }
1275 else
1276 switch (size)
1277 {
1278 case 1: return BFD_RELOC_8;
1279 case 2: return BFD_RELOC_16;
1280 case 4: return BFD_RELOC_32;
1281 case 8: return BFD_RELOC_64;
1282 }
3956db08
JB		 1283 as_bad (_("cannot do %s %u byte relocation"),
1284 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1285 }
1286
bfb32b52 1287 abort ();
252b5132
RH		 1288 return BFD_RELOC_NONE;
1289}
1290
47926f60
KH		 1291/* Here we decide which fixups can be adjusted to make them relative to
1292 the beginning of the section instead of the symbol. Basically we need
1293 to make sure that the dynamic relocations are done correctly, so in
1294 some cases we force the original symbol to be used. */
1295
252b5132 1296int
c0c949c7 1297tc_i386_fix_adjustable (fixP)
31312f95 1298 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1299{
6d249963 1300#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1301 if (!IS_ELF)
31312f95
AM		 1302 return 1;
1303
a161fe53
AM		 1304 /* Don't adjust pc-relative references to merge sections in 64-bit
1305 mode. */
1306 if (use_rela_relocations
1307 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1308 && fixP->fx_pcrel)
252b5132 1309 return 0;
31312f95 1310
8d01d9a9
AJ		 1311 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1312 and changed later by validate_fix. */
1313 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1314 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1315 return 0;
1316
ce8a8b2f 1317 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1318 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1319 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1320 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1321 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1322 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1323 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1324 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1325 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1326 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1327 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1328 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1329 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1330 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1331 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1332 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1333 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1334 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1335 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1336 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1337 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1338 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1339 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
252b5132
RH		 1340 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1341 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1342 return 0;
31312f95 1343#endif
252b5132
RH		 1344 return 1;
1345}
252b5132 1346
29b0f896 1347static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1348
1349static int
252b5132 1350intel_float_operand (mnemonic)
29b0f896 1351 const char *mnemonic;
252b5132 1352{
9306ca4a
JB		 1353 /* Note that the value returned is meaningful only for opcodes with (memory)
1354 operands, hence the code here is free to improperly handle opcodes that
1355 have no operands (for better performance and smaller code). */
1356
1357 if (mnemonic[0] != 'f')
1358 return 0; /* non-math */
1359
1360 switch (mnemonic[1])
1361 {
1362 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1363 the fs segment override prefix not currently handled because no
1364 call path can make opcodes without operands get here */
1365 case 'i':
1366 return 2 /* integer op */;
1367 case 'l':
1368 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1369 return 3; /* fldcw/fldenv */
1370 break;
1371 case 'n':
1372 if (mnemonic[2] != 'o' /* fnop */)
1373 return 3; /* non-waiting control op */
1374 break;
1375 case 'r':
1376 if (mnemonic[2] == 's')
1377 return 3; /* frstor/frstpm */
1378 break;
1379 case 's':
1380 if (mnemonic[2] == 'a')
1381 return 3; /* fsave */
1382 if (mnemonic[2] == 't')
1383 {
1384 switch (mnemonic[3])
1385 {
1386 case 'c': /* fstcw */
1387 case 'd': /* fstdw */
1388 case 'e': /* fstenv */
1389 case 's': /* fsts[gw] */
1390 return 3;
1391 }
1392 }
1393 break;
1394 case 'x':
1395 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1396 return 0; /* fxsave/fxrstor are not really math ops */
1397 break;
1398 }
252b5132 1399
9306ca4a 1400 return 1;
252b5132
RH		 1401}
1402
1403/* This is the guts of the machine-dependent assembler. LINE points to a
1404 machine dependent instruction. This function is supposed to emit
1405 the frags/bytes it assembles to. */
1406
1407void
1408md_assemble (line)
1409 char *line;
1410{
252b5132 1411 int j;
252b5132
RH		 1412 char mnemonic[MAX_MNEM_SIZE];
1413
47926f60 1414 /* Initialize globals. */
252b5132
RH		 1415 memset (&i, '\0', sizeof (i));
1416 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1417 i.reloc[j] = NO_RELOC;
252b5132
RH		 1418 memset (disp_expressions, '\0', sizeof (disp_expressions));
1419 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1420 save_stack_p = save_stack;
252b5132
RH		 1421
1422 /* First parse an instruction mnemonic & call i386_operand for the operands.
1423 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1424 start of a (possibly prefixed) mnemonic. */
252b5132 1425
29b0f896
AM		 1426 line = parse_insn (line, mnemonic);
1427 if (line == NULL)
1428 return;
252b5132 1429
29b0f896
AM		 1430 line = parse_operands (line, mnemonic);
1431 if (line == NULL)
1432 return;
252b5132 1433
29b0f896
AM		 1434 /* Now we've parsed the mnemonic into a set of templates, and have the
1435 operands at hand. */
1436
1437 /* All intel opcodes have reversed operands except for "bound" and
1438 "enter". We also don't reverse intersegment "jmp" and "call"
1439 instructions with 2 immediate operands so that the immediate segment
1440 precedes the offset, as it does when in AT&T mode. "enter" and the
1441 intersegment "jmp" and "call" instructions are the only ones that
1442 have two immediate operands. */
1443 if (intel_syntax && i.operands > 1
1444 && (strcmp (mnemonic, "bound") != 0)
30123838 1445 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1446 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1447 swap_operands ();
1448
1449 if (i.imm_operands)
1450 optimize_imm ();
1451
b300c311
L		 1452 /* Don't optimize displacement for movabs since it only takes 64bit
1453 displacement. */
1454 if (i.disp_operands
1455 && (flag_code != CODE_64BIT
1456 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1457 optimize_disp ();
1458
1459 /* Next, we find a template that matches the given insn,
1460 making sure the overlap of the given operands types is consistent
1461 with the template operand types. */
252b5132 1462
29b0f896
AM		 1463 if (!match_template ())
1464 return;
252b5132 1465
cd61ebfe
AM		 1466 if (intel_syntax)
1467 {
1468 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1469 if (SYSV386_COMPAT
1470 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1471 i.tm.base_opcode ^= FloatR;
1472
1473 /* Zap movzx and movsx suffix. The suffix may have been set from
1474 "word ptr" or "byte ptr" on the source operand, but we'll use
1475 the suffix later to choose the destination register. */
1476 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1477 {
1478 if (i.reg_operands < 2
1479 && !i.suffix
1480 && (~i.tm.opcode_modifier
1481 & (No_bSuf
1482 | No_wSuf
1483 | No_lSuf
1484 | No_sSuf
1485 | No_xSuf
1486 | No_qSuf)))
1487 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1488
1489 i.suffix = 0;
1490 }
cd61ebfe 1491 }
24eab124 1492
29b0f896
AM		 1493 if (i.tm.opcode_modifier & FWait)
1494 if (!add_prefix (FWAIT_OPCODE))
1495 return;
252b5132 1496
29b0f896
AM		 1497 /* Check string instruction segment overrides. */
1498 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1499 {
1500 if (!check_string ())
5dd0794d 1501 return;
29b0f896 1502 }
5dd0794d 1503
29b0f896
AM		 1504 if (!process_suffix ())
1505 return;
e413e4e9 1506
29b0f896
AM		 1507 /* Make still unresolved immediate matches conform to size of immediate
1508 given in i.suffix. */
1509 if (!finalize_imm ())
1510 return;
252b5132 1511
29b0f896
AM		 1512 if (i.types[0] & Imm1)
1513 i.imm_operands = 0; /* kludge for shift insns. */
1514 if (i.types[0] & ImplicitRegister)
1515 i.reg_operands--;
1516 if (i.types[1] & ImplicitRegister)
1517 i.reg_operands--;
1518 if (i.types[2] & ImplicitRegister)
1519 i.reg_operands--;
252b5132 1520
29b0f896
AM		 1521 if (i.tm.opcode_modifier & ImmExt)
1522 {
02fc3089
L		 1523 expressionS *exp;
1524
ca164297
L		 1525 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1526 {
67c1ffbe 1527 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1528 operands with an opcode suffix which is coded in the same
1529 place as an 8-bit immediate field would be. Here we check
1530 those operands and remove them afterwards. */
1531 unsigned int x;
1532
a4622f40 1533 for (x = 0; x < i.operands; x++)
ca164297
L		 1534 if (i.op[x].regs->reg_num != x)
1535 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1536 i.op[x].regs->reg_name, x + 1, i.tm.name);
1537 i.operands = 0;
1538 }
1539
29b0f896
AM		 1540 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1541 opcode suffix which is coded in the same place as an 8-bit
1542 immediate field would be. Here we fake an 8-bit immediate
1543 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1544
29b0f896 1545 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1546
29b0f896
AM		 1547 exp = &im_expressions[i.imm_operands++];
1548 i.op[i.operands].imms = exp;
1549 i.types[i.operands++] = Imm8;
1550 exp->X_op = O_constant;
1551 exp->X_add_number = i.tm.extension_opcode;
1552 i.tm.extension_opcode = None;
1553 }
252b5132 1554
29b0f896
AM		 1555 /* For insns with operands there are more diddles to do to the opcode. */
1556 if (i.operands)
1557 {
1558 if (!process_operands ())
1559 return;
1560 }
1561 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1562 {
1563 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1564 as_warn (_("translating to `%sp'"), i.tm.name);
1565 }
252b5132 1566
29b0f896
AM		 1567 /* Handle conversion of 'int $3' --> special int3 insn. */
1568 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1569 {
1570 i.tm.base_opcode = INT3_OPCODE;
1571 i.imm_operands = 0;
1572 }
252b5132 1573
29b0f896
AM		 1574 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1575 && i.op[0].disps->X_op == O_constant)
1576 {
1577 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1578 the absolute address given by the constant. Since ix86 jumps and
1579 calls are pc relative, we need to generate a reloc. */
1580 i.op[0].disps->X_add_symbol = &abs_symbol;
1581 i.op[0].disps->X_op = O_symbol;
1582 }
252b5132 1583
29b0f896
AM		 1584 if ((i.tm.opcode_modifier & Rex64) != 0)
1585 i.rex |= REX_MODE64;
252b5132 1586
29b0f896
AM		 1587 /* For 8 bit registers we need an empty rex prefix. Also if the
1588 instruction already has a prefix, we need to convert old
1589 registers to new ones. */
773f551c 1590
29b0f896
AM		 1591 if (((i.types[0] & Reg8) != 0
1592 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1593 || ((i.types[1] & Reg8) != 0
1594 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1595 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1596 && i.rex != 0))
1597 {
1598 int x;
726c5dcd 1599
29b0f896
AM		 1600 i.rex |= REX_OPCODE;
1601 for (x = 0; x < 2; x++)
1602 {
1603 /* Look for 8 bit operand that uses old registers. */
1604 if ((i.types[x] & Reg8) != 0
1605 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1606 {
29b0f896
AM		 1607 /* In case it is "hi" register, give up. */
1608 if (i.op[x].regs->reg_num > 3)
0477af35 1609 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1610 i.op[x].regs->reg_name);
773f551c 1611
29b0f896
AM		 1612 /* Otherwise it is equivalent to the extended register.
1613 Since the encoding doesn't change this is merely
1614 cosmetic cleanup for debug output. */
1615
1616 i.op[x].regs = i.op[x].regs + 8;
773f551c 1617 }
29b0f896
AM		 1618 }
1619 }
773f551c 1620
29b0f896
AM		 1621 if (i.rex != 0)
1622 add_prefix (REX_OPCODE | i.rex);
1623
1624 /* We are ready to output the insn. */
1625 output_insn ();
1626}
1627
1628static char *
1629parse_insn (line, mnemonic)
1630 char *line;
1631 char *mnemonic;
1632{
1633 char *l = line;
1634 char *token_start = l;
1635 char *mnem_p;
5c6af06e
JB		 1636 int supported;
1637 const template *t;
29b0f896
AM		 1638
1639 /* Non-zero if we found a prefix only acceptable with string insns. */
1640 const char *expecting_string_instruction = NULL;
45288df1 1641
29b0f896
AM		 1642 while (1)
1643 {
1644 mnem_p = mnemonic;
1645 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1646 {
1647 mnem_p++;
1648 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1649 {
29b0f896
AM		 1650 as_bad (_("no such instruction: `%s'"), token_start);
1651 return NULL;
1652 }
1653 l++;
1654 }
1655 if (!is_space_char (*l)
1656 && *l != END_OF_INSN
e44823cf
JB		 1657 && (intel_syntax
1658 || (*l != PREFIX_SEPARATOR
1659 && *l != ',')))
29b0f896
AM		 1660 {
1661 as_bad (_("invalid character %s in mnemonic"),
1662 output_invalid (*l));
1663 return NULL;
1664 }
1665 if (token_start == l)
1666 {
e44823cf 1667 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1668 as_bad (_("expecting prefix; got nothing"));
1669 else
1670 as_bad (_("expecting mnemonic; got nothing"));
1671 return NULL;
1672 }
45288df1 1673
29b0f896
AM		 1674 /* Look up instruction (or prefix) via hash table. */
1675 current_templates = hash_find (op_hash, mnemonic);
47926f60 1676
29b0f896
AM		 1677 if (*l != END_OF_INSN
1678 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1679 && current_templates
1680 && (current_templates->start->opcode_modifier & IsPrefix))
1681 {
2dd88dca
JB		 1682 if (current_templates->start->cpu_flags
1683 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1684 {
1685 as_bad ((flag_code != CODE_64BIT
1686 ? _("`%s' is only supported in 64-bit mode")
1687 : _("`%s' is not supported in 64-bit mode")),
1688 current_templates->start->name);
1689 return NULL;
1690 }
29b0f896
AM		 1691 /* If we are in 16-bit mode, do not allow addr16 or data16.
1692 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1693 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1694 && flag_code != CODE_64BIT
1695 && (((current_templates->start->opcode_modifier & Size32) != 0)
1696 ^ (flag_code == CODE_16BIT)))
1697 {
1698 as_bad (_("redundant %s prefix"),
1699 current_templates->start->name);
1700 return NULL;
45288df1 1701 }
29b0f896
AM		 1702 /* Add prefix, checking for repeated prefixes. */
1703 switch (add_prefix (current_templates->start->base_opcode))
1704 {
1705 case 0:
1706 return NULL;
1707 case 2:
1708 expecting_string_instruction = current_templates->start->name;
1709 break;
1710 }
1711 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1712 token_start = ++l;
1713 }
1714 else
1715 break;
1716 }
45288df1 1717
29b0f896
AM		 1718 if (!current_templates)
1719 {
1720 /* See if we can get a match by trimming off a suffix. */
1721 switch (mnem_p[-1])
1722 {
1723 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 1724 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1725 i.suffix = SHORT_MNEM_SUFFIX;
1726 else
29b0f896
AM		 1727 case BYTE_MNEM_SUFFIX:
1728 case QWORD_MNEM_SUFFIX:
1729 i.suffix = mnem_p[-1];
1730 mnem_p[-1] = '\0';
1731 current_templates = hash_find (op_hash, mnemonic);
1732 break;
1733 case SHORT_MNEM_SUFFIX:
1734 case LONG_MNEM_SUFFIX:
1735 if (!intel_syntax)
1736 {
1737 i.suffix = mnem_p[-1];
1738 mnem_p[-1] = '\0';
1739 current_templates = hash_find (op_hash, mnemonic);
1740 }
1741 break;
252b5132 1742
29b0f896
AM		 1743 /* Intel Syntax. */
1744 case 'd':
1745 if (intel_syntax)
1746 {
9306ca4a 1747 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 1748 i.suffix = SHORT_MNEM_SUFFIX;
1749 else
1750 i.suffix = LONG_MNEM_SUFFIX;
1751 mnem_p[-1] = '\0';
1752 current_templates = hash_find (op_hash, mnemonic);
1753 }
1754 break;
1755 }
1756 if (!current_templates)
1757 {
1758 as_bad (_("no such instruction: `%s'"), token_start);
1759 return NULL;
1760 }
1761 }
252b5132 1762
29b0f896
AM		 1763 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1764 {
1765 /* Check for a branch hint. We allow ",pt" and ",pn" for
1766 predict taken and predict not taken respectively.
1767 I'm not sure that branch hints actually do anything on loop
1768 and jcxz insns (JumpByte) for current Pentium4 chips. They
1769 may work in the future and it doesn't hurt to accept them
1770 now. */
1771 if (l[0] == ',' && l[1] == 'p')
1772 {
1773 if (l[2] == 't')
1774 {
1775 if (!add_prefix (DS_PREFIX_OPCODE))
1776 return NULL;
1777 l += 3;
1778 }
1779 else if (l[2] == 'n')
1780 {
1781 if (!add_prefix (CS_PREFIX_OPCODE))
1782 return NULL;
1783 l += 3;
1784 }
1785 }
1786 }
1787 /* Any other comma loses. */
1788 if (*l == ',')
1789 {
1790 as_bad (_("invalid character %s in mnemonic"),
1791 output_invalid (*l));
1792 return NULL;
1793 }
252b5132 1794
29b0f896 1795 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 1796 supported = 0;
1797 for (t = current_templates->start; t < current_templates->end; ++t)
1798 {
1799 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1800 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1801 supported |= 1;
1802 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1803 supported |= 2;
1804 }
1805 if (!(supported & 2))
1806 {
1807 as_bad (flag_code == CODE_64BIT
1808 ? _("`%s' is not supported in 64-bit mode")
1809 : _("`%s' is only supported in 64-bit mode"),
1810 current_templates->start->name);
1811 return NULL;
1812 }
1813 if (!(supported & 1))
29b0f896 1814 {
5c6af06e
JB		 1815 as_warn (_("`%s' is not supported on `%s%s'"),
1816 current_templates->start->name,
1817 cpu_arch_name,
1818 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 1819 }
1820 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1821 {
1822 as_warn (_("use .code16 to ensure correct addressing mode"));
1823 }
252b5132 1824
29b0f896 1825 /* Check for rep/repne without a string instruction. */
f41bbced 1826 if (expecting_string_instruction)
29b0f896 1827 {
f41bbced
JB		 1828 static templates override;
1829
1830 for (t = current_templates->start; t < current_templates->end; ++t)
1831 if (t->opcode_modifier & IsString)
1832 break;
1833 if (t >= current_templates->end)
1834 {
1835 as_bad (_("expecting string instruction after `%s'"),
1836 expecting_string_instruction);
1837 return NULL;
1838 }
1839 for (override.start = t; t < current_templates->end; ++t)
1840 if (!(t->opcode_modifier & IsString))
1841 break;
1842 override.end = t;
1843 current_templates = &override;
29b0f896 1844 }
252b5132 1845
29b0f896
AM		 1846 return l;
1847}
252b5132 1848
29b0f896
AM		 1849static char *
1850parse_operands (l, mnemonic)
1851 char *l;
1852 const char *mnemonic;
1853{
1854 char *token_start;
3138f287 1855
29b0f896
AM		 1856 /* 1 if operand is pending after ','. */
1857 unsigned int expecting_operand = 0;
252b5132 1858
29b0f896
AM		 1859 /* Non-zero if operand parens not balanced. */
1860 unsigned int paren_not_balanced;
1861
1862 while (*l != END_OF_INSN)
1863 {
1864 /* Skip optional white space before operand. */
1865 if (is_space_char (*l))
1866 ++l;
1867 if (!is_operand_char (*l) && *l != END_OF_INSN)
1868 {
1869 as_bad (_("invalid character %s before operand %d"),
1870 output_invalid (*l),
1871 i.operands + 1);
1872 return NULL;
1873 }
1874 token_start = l; /* after white space */
1875 paren_not_balanced = 0;
1876 while (paren_not_balanced || *l != ',')
1877 {
1878 if (*l == END_OF_INSN)
1879 {
1880 if (paren_not_balanced)
1881 {
1882 if (!intel_syntax)
1883 as_bad (_("unbalanced parenthesis in operand %d."),
1884 i.operands + 1);
1885 else
1886 as_bad (_("unbalanced brackets in operand %d."),
1887 i.operands + 1);
1888 return NULL;
1889 }
1890 else
1891 break; /* we are done */
1892 }
1893 else if (!is_operand_char (*l) && !is_space_char (*l))
1894 {
1895 as_bad (_("invalid character %s in operand %d"),
1896 output_invalid (*l),
1897 i.operands + 1);
1898 return NULL;
1899 }
1900 if (!intel_syntax)
1901 {
1902 if (*l == '(')
1903 ++paren_not_balanced;
1904 if (*l == ')')
1905 --paren_not_balanced;
1906 }
1907 else
1908 {
1909 if (*l == '[')
1910 ++paren_not_balanced;
1911 if (*l == ']')
1912 --paren_not_balanced;
1913 }
1914 l++;
1915 }
1916 if (l != token_start)
1917 { /* Yes, we've read in another operand. */
1918 unsigned int operand_ok;
1919 this_operand = i.operands++;
1920 if (i.operands > MAX_OPERANDS)
1921 {
1922 as_bad (_("spurious operands; (%d operands/instruction max)"),
1923 MAX_OPERANDS);
1924 return NULL;
1925 }
1926 /* Now parse operand adding info to 'i' as we go along. */
1927 END_STRING_AND_SAVE (l);
1928
1929 if (intel_syntax)
1930 operand_ok =
1931 i386_intel_operand (token_start,
1932 intel_float_operand (mnemonic));
1933 else
1934 operand_ok = i386_operand (token_start);
1935
1936 RESTORE_END_STRING (l);
1937 if (!operand_ok)
1938 return NULL;
1939 }
1940 else
1941 {
1942 if (expecting_operand)
1943 {
1944 expecting_operand_after_comma:
1945 as_bad (_("expecting operand after ','; got nothing"));
1946 return NULL;
1947 }
1948 if (*l == ',')
1949 {
1950 as_bad (_("expecting operand before ','; got nothing"));
1951 return NULL;
1952 }
1953 }
7f3f1ea2 1954
29b0f896
AM		 1955 /* Now *l must be either ',' or END_OF_INSN. */
1956 if (*l == ',')
1957 {
1958 if (*++l == END_OF_INSN)
1959 {
1960 /* Just skip it, if it's \n complain. */
1961 goto expecting_operand_after_comma;
1962 }
1963 expecting_operand = 1;
1964 }
1965 }
1966 return l;
1967}
7f3f1ea2 1968
29b0f896
AM		 1969static void
1970swap_operands ()
1971{
1972 union i386_op temp_op;
1973 unsigned int temp_type;
f86103b7 1974 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 1975 int xchg1 = 0;
1976 int xchg2 = 0;
252b5132 1977
29b0f896
AM		 1978 if (i.operands == 2)
1979 {
1980 xchg1 = 0;
1981 xchg2 = 1;
1982 }
1983 else if (i.operands == 3)
1984 {
1985 xchg1 = 0;
1986 xchg2 = 2;
1987 }
1988 temp_type = i.types[xchg2];
1989 i.types[xchg2] = i.types[xchg1];
1990 i.types[xchg1] = temp_type;
1991 temp_op = i.op[xchg2];
1992 i.op[xchg2] = i.op[xchg1];
1993 i.op[xchg1] = temp_op;
1994 temp_reloc = i.reloc[xchg2];
1995 i.reloc[xchg2] = i.reloc[xchg1];
1996 i.reloc[xchg1] = temp_reloc;
1997
1998 if (i.mem_operands == 2)
1999 {
2000 const seg_entry *temp_seg;
2001 temp_seg = i.seg[0];
2002 i.seg[0] = i.seg[1];
2003 i.seg[1] = temp_seg;
2004 }
2005}
252b5132 2006
29b0f896
AM		 2007/* Try to ensure constant immediates are represented in the smallest
2008 opcode possible. */
2009static void
2010optimize_imm ()
2011{
2012 char guess_suffix = 0;
2013 int op;
252b5132 2014
29b0f896
AM		 2015 if (i.suffix)
2016 guess_suffix = i.suffix;
2017 else if (i.reg_operands)
2018 {
2019 /* Figure out a suffix from the last register operand specified.
2020 We can't do this properly yet, ie. excluding InOutPortReg,
2021 but the following works for instructions with immediates.
2022 In any case, we can't set i.suffix yet. */
2023 for (op = i.operands; --op >= 0;)
2024 if (i.types[op] & Reg)
252b5132 2025 {
29b0f896
AM		 2026 if (i.types[op] & Reg8)
2027 guess_suffix = BYTE_MNEM_SUFFIX;
2028 else if (i.types[op] & Reg16)
2029 guess_suffix = WORD_MNEM_SUFFIX;
2030 else if (i.types[op] & Reg32)
2031 guess_suffix = LONG_MNEM_SUFFIX;
2032 else if (i.types[op] & Reg64)
2033 guess_suffix = QWORD_MNEM_SUFFIX;
2034 break;
252b5132 2035 }
29b0f896
AM		 2036 }
2037 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2038 guess_suffix = WORD_MNEM_SUFFIX;
2039
2040 for (op = i.operands; --op >= 0;)
2041 if (i.types[op] & Imm)
2042 {
2043 switch (i.op[op].imms->X_op)
252b5132 2044 {
29b0f896
AM		 2045 case O_constant:
2046 /* If a suffix is given, this operand may be shortened. */
2047 switch (guess_suffix)
252b5132 2048 {
29b0f896
AM		 2049 case LONG_MNEM_SUFFIX:
2050 i.types[op] |= Imm32 | Imm64;
2051 break;
2052 case WORD_MNEM_SUFFIX:
2053 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2054 break;
2055 case BYTE_MNEM_SUFFIX:
2056 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2057 break;
252b5132 2058 }
252b5132 2059
29b0f896
AM		 2060 /* If this operand is at most 16 bits, convert it
2061 to a signed 16 bit number before trying to see
2062 whether it will fit in an even smaller size.
2063 This allows a 16-bit operand such as $0xffe0 to
2064 be recognised as within Imm8S range. */
2065 if ((i.types[op] & Imm16)
2066 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2067 {
29b0f896
AM		 2068 i.op[op].imms->X_add_number =
2069 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2070 }
2071 if ((i.types[op] & Imm32)
2072 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2073 == 0))
2074 {
2075 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2076 ^ ((offsetT) 1 << 31))
2077 - ((offsetT) 1 << 31));
2078 }
2079 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2080
29b0f896
AM		 2081 /* We must avoid matching of Imm32 templates when 64bit
2082 only immediate is available. */
2083 if (guess_suffix == QWORD_MNEM_SUFFIX)
2084 i.types[op] &= ~Imm32;
2085 break;
252b5132 2086
29b0f896
AM		 2087 case O_absent:
2088 case O_register:
2089 abort ();
2090
2091 /* Symbols and expressions. */
2092 default:
9cd96992
JB		 2093 /* Convert symbolic operand to proper sizes for matching, but don't
2094 prevent matching a set of insns that only supports sizes other
2095 than those matching the insn suffix. */
2096 {
2097 unsigned int mask, allowed = 0;
2098 const template *t;
2099
2100 for (t = current_templates->start; t < current_templates->end; ++t)
2101 allowed |= t->operand_types[op];
2102 switch (guess_suffix)
2103 {
2104 case QWORD_MNEM_SUFFIX:
2105 mask = Imm64 | Imm32S;
2106 break;
2107 case LONG_MNEM_SUFFIX:
2108 mask = Imm32;
2109 break;
2110 case WORD_MNEM_SUFFIX:
2111 mask = Imm16;
2112 break;
2113 case BYTE_MNEM_SUFFIX:
2114 mask = Imm8;
2115 break;
2116 default:
2117 mask = 0;
2118 break;
2119 }
2120 if (mask & allowed)
2121 i.types[op] &= mask;
2122 }
29b0f896 2123 break;
252b5132 2124 }
29b0f896
AM		 2125 }
2126}
47926f60 2127
29b0f896
AM		 2128/* Try to use the smallest displacement type too. */
2129static void
2130optimize_disp ()
2131{
2132 int op;
3e73aa7c 2133
29b0f896 2134 for (op = i.operands; --op >= 0;)
b300c311 2135 if (i.types[op] & Disp)
252b5132 2136 {
b300c311 2137 if (i.op[op].disps->X_op == O_constant)
252b5132 2138 {
b300c311 2139 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2140
b300c311
L		 2141 if ((i.types[op] & Disp16)
2142 && (disp & ~(offsetT) 0xffff) == 0)
2143 {
2144 /* If this operand is at most 16 bits, convert
2145 to a signed 16 bit number and don't use 64bit
2146 displacement. */
2147 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2148 i.types[op] &= ~Disp64;
2149 }
2150 if ((i.types[op] & Disp32)
2151 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2152 {
2153 /* If this operand is at most 32 bits, convert
2154 to a signed 32 bit number and don't use 64bit
2155 displacement. */
2156 disp &= (((offsetT) 2 << 31) - 1);
2157 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2158 i.types[op] &= ~Disp64;
2159 }
2160 if (!disp && (i.types[op] & BaseIndex))
2161 {
2162 i.types[op] &= ~Disp;
2163 i.op[op].disps = 0;
2164 i.disp_operands--;
2165 }
2166 else if (flag_code == CODE_64BIT)
2167 {
2168 if (fits_in_signed_long (disp))
28a9d8f5
L		 2169 {
2170 i.types[op] &= ~Disp64;
2171 i.types[op] |= Disp32S;
2172 }
b300c311
L		 2173 if (fits_in_unsigned_long (disp))
2174 i.types[op] |= Disp32;
2175 }
2176 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2177 && fits_in_signed_byte (disp))
2178 i.types[op] |= Disp8;
252b5132 2179 }
b300c311
L		 2180 else
2181 /* We only support 64bit displacement on constants. */
2182 i.types[op] &= ~Disp64;
252b5132 2183 }
29b0f896
AM		 2184}
2185
2186static int
2187match_template ()
2188{
2189 /* Points to template once we've found it. */
2190 const template *t;
2191 unsigned int overlap0, overlap1, overlap2;
2192 unsigned int found_reverse_match;
2193 int suffix_check;
2194
2195#define MATCH(overlap, given, template) \
2196 ((overlap & ~JumpAbsolute) \
2197 && (((given) & (BaseIndex | JumpAbsolute)) \
2198 == ((overlap) & (BaseIndex | JumpAbsolute))))
2199
2200 /* If given types r0 and r1 are registers they must be of the same type
2201 unless the expected operand type register overlap is null.
2202 Note that Acc in a template matches every size of reg. */
2203#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2204 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2205 || ((g0) & Reg) == ((g1) & Reg) \
2206 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2207
2208 overlap0 = 0;
2209 overlap1 = 0;
2210 overlap2 = 0;
2211 found_reverse_match = 0;
2212 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2213 ? No_bSuf
2214 : (i.suffix == WORD_MNEM_SUFFIX
2215 ? No_wSuf
2216 : (i.suffix == SHORT_MNEM_SUFFIX
2217 ? No_sSuf
2218 : (i.suffix == LONG_MNEM_SUFFIX
2219 ? No_lSuf
2220 : (i.suffix == QWORD_MNEM_SUFFIX
2221 ? No_qSuf
2222 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2223 ? No_xSuf : 0))))));
2224
20f0a1fc
NC		 2225 t = current_templates->start;
2226 if (i.suffix == QWORD_MNEM_SUFFIX
2227 && flag_code != CODE_64BIT
9306ca4a
JB		 2228 && (intel_syntax
2229 ? !(t->opcode_modifier & IgnoreSize)
2230 && !intel_float_operand (t->name)
2231 : intel_float_operand (t->name) != 2)
20f0a1fc
NC		 2232 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2233 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2234 && (t->base_opcode != 0x0fc7
2235 || t->extension_opcode != 1 /* cmpxchg8b */))
2236 t = current_templates->end;
2237 for (; t < current_templates->end; t++)
29b0f896
AM		 2238 {
2239 /* Must have right number of operands. */
2240 if (i.operands != t->operands)
2241 continue;
2242
2243 /* Check the suffix, except for some instructions in intel mode. */
2244 if ((t->opcode_modifier & suffix_check)
2245 && !(intel_syntax
9306ca4a 2246 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2247 continue;
2248
2249 /* Do not verify operands when there are none. */
2250 else if (!t->operands)
2251 {
2252 if (t->cpu_flags & ~cpu_arch_flags)
2253 continue;
2254 /* We've found a match; break out of loop. */
2255 break;
2256 }
252b5132 2257
29b0f896
AM		 2258 overlap0 = i.types[0] & t->operand_types[0];
2259 switch (t->operands)
2260 {
2261 case 1:
2262 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2263 continue;
2264 break;
2265 case 2:
2266 case 3:
2267 overlap1 = i.types[1] & t->operand_types[1];
2268 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2269 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2270 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2271 t->operand_types[0],
2272 overlap1, i.types[1],
2273 t->operand_types[1]))
2274 {
2275 /* Check if other direction is valid ... */
2276 if ((t->opcode_modifier & (D | FloatD)) == 0)
2277 continue;
2278
2279 /* Try reversing direction of operands. */
2280 overlap0 = i.types[0] & t->operand_types[1];
2281 overlap1 = i.types[1] & t->operand_types[0];
2282 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2283 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2284 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2285 t->operand_types[1],
2286 overlap1, i.types[1],
2287 t->operand_types[0]))
2288 {
2289 /* Does not match either direction. */
2290 continue;
2291 }
2292 /* found_reverse_match holds which of D or FloatDR
2293 we've found. */
2294 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2295 }
2296 /* Found a forward 2 operand match here. */
2297 else if (t->operands == 3)
2298 {
2299 /* Here we make use of the fact that there are no
2300 reverse match 3 operand instructions, and all 3
2301 operand instructions only need to be checked for
2302 register consistency between operands 2 and 3. */
2303 overlap2 = i.types[2] & t->operand_types[2];
2304 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2305 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2306 t->operand_types[1],
2307 overlap2, i.types[2],
2308 t->operand_types[2]))
2309
2310 continue;
2311 }
2312 /* Found either forward/reverse 2 or 3 operand match here:
2313 slip through to break. */
2314 }
2315 if (t->cpu_flags & ~cpu_arch_flags)
2316 {
2317 found_reverse_match = 0;
2318 continue;
2319 }
2320 /* We've found a match; break out of loop. */
2321 break;
2322 }
2323
2324 if (t == current_templates->end)
2325 {
2326 /* We found no match. */
2327 as_bad (_("suffix or operands invalid for `%s'"),
2328 current_templates->start->name);
2329 return 0;
2330 }
252b5132 2331
29b0f896
AM		 2332 if (!quiet_warnings)
2333 {
2334 if (!intel_syntax
2335 && ((i.types[0] & JumpAbsolute)
2336 != (t->operand_types[0] & JumpAbsolute)))
2337 {
2338 as_warn (_("indirect %s without `*'"), t->name);
2339 }
2340
2341 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2342 == (IsPrefix | IgnoreSize))
2343 {
2344 /* Warn them that a data or address size prefix doesn't
2345 affect assembly of the next line of code. */
2346 as_warn (_("stand-alone `%s' prefix"), t->name);
2347 }
2348 }
2349
2350 /* Copy the template we found. */
2351 i.tm = *t;
2352 if (found_reverse_match)
2353 {
2354 /* If we found a reverse match we must alter the opcode
2355 direction bit. found_reverse_match holds bits to change
2356 (different for int & float insns). */
2357
2358 i.tm.base_opcode ^= found_reverse_match;
2359
2360 i.tm.operand_types[0] = t->operand_types[1];
2361 i.tm.operand_types[1] = t->operand_types[0];
2362 }
2363
2364 return 1;
2365}
2366
2367static int
2368check_string ()
2369{
2370 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2371 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2372 {
2373 if (i.seg[0] != NULL && i.seg[0] != &es)
2374 {
2375 as_bad (_("`%s' operand %d must use `%%es' segment"),
2376 i.tm.name,
2377 mem_op + 1);
2378 return 0;
2379 }
2380 /* There's only ever one segment override allowed per instruction.
2381 This instruction possibly has a legal segment override on the
2382 second operand, so copy the segment to where non-string
2383 instructions store it, allowing common code. */
2384 i.seg[0] = i.seg[1];
2385 }
2386 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2387 {
2388 if (i.seg[1] != NULL && i.seg[1] != &es)
2389 {
2390 as_bad (_("`%s' operand %d must use `%%es' segment"),
2391 i.tm.name,
2392 mem_op + 2);
2393 return 0;
2394 }
2395 }
2396 return 1;
2397}
2398
2399static int
543613e9 2400process_suffix (void)
29b0f896
AM		 2401{
2402 /* If matched instruction specifies an explicit instruction mnemonic
2403 suffix, use it. */
2404 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2405 {
2406 if (i.tm.opcode_modifier & Size16)
2407 i.suffix = WORD_MNEM_SUFFIX;
2408 else if (i.tm.opcode_modifier & Size64)
2409 i.suffix = QWORD_MNEM_SUFFIX;
2410 else
2411 i.suffix = LONG_MNEM_SUFFIX;
2412 }
2413 else if (i.reg_operands)
2414 {
2415 /* If there's no instruction mnemonic suffix we try to invent one
2416 based on register operands. */
2417 if (!i.suffix)
2418 {
2419 /* We take i.suffix from the last register operand specified,
2420 Destination register type is more significant than source
2421 register type. */
2422 int op;
543613e9 2423
29b0f896
AM		 2424 for (op = i.operands; --op >= 0;)
2425 if ((i.types[op] & Reg)
2426 && !(i.tm.operand_types[op] & InOutPortReg))
2427 {
2428 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2429 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2430 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2431 LONG_MNEM_SUFFIX);
2432 break;
2433 }
2434 }
2435 else if (i.suffix == BYTE_MNEM_SUFFIX)
2436 {
2437 if (!check_byte_reg ())
2438 return 0;
2439 }
2440 else if (i.suffix == LONG_MNEM_SUFFIX)
2441 {
2442 if (!check_long_reg ())
2443 return 0;
2444 }
2445 else if (i.suffix == QWORD_MNEM_SUFFIX)
2446 {
2447 if (!check_qword_reg ())
2448 return 0;
2449 }
2450 else if (i.suffix == WORD_MNEM_SUFFIX)
2451 {
2452 if (!check_word_reg ())
2453 return 0;
2454 }
2455 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2456 /* Do nothing if the instruction is going to ignore the prefix. */
2457 ;
2458 else
2459 abort ();
2460 }
9306ca4a
JB		 2461 else if ((i.tm.opcode_modifier & DefaultSize)
2462 && !i.suffix
2463 /* exclude fldenv/frstor/fsave/fstenv */
2464 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2465 {
2466 i.suffix = stackop_size;
2467 }
9306ca4a
JB		 2468 else if (intel_syntax
2469 && !i.suffix
2470 && ((i.tm.operand_types[0] & JumpAbsolute)
2471 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2472 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2473 && i.tm.extension_opcode <= 3)))
2474 {
2475 switch (flag_code)
2476 {
2477 case CODE_64BIT:
2478 if (!(i.tm.opcode_modifier & No_qSuf))
2479 {
2480 i.suffix = QWORD_MNEM_SUFFIX;
2481 break;
2482 }
2483 case CODE_32BIT:
2484 if (!(i.tm.opcode_modifier & No_lSuf))
2485 i.suffix = LONG_MNEM_SUFFIX;
2486 break;
2487 case CODE_16BIT:
2488 if (!(i.tm.opcode_modifier & No_wSuf))
2489 i.suffix = WORD_MNEM_SUFFIX;
2490 break;
2491 }
2492 }
252b5132 2493
9306ca4a 2494 if (!i.suffix)
29b0f896 2495 {
9306ca4a
JB		 2496 if (!intel_syntax)
2497 {
2498 if (i.tm.opcode_modifier & W)
2499 {
2500 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2501 return 0;
2502 }
2503 }
2504 else
2505 {
2506 unsigned int suffixes = ~i.tm.opcode_modifier
2507 & (No_bSuf
2508 | No_wSuf
2509 | No_lSuf
2510 | No_sSuf
2511 | No_xSuf
2512 | No_qSuf);
2513
2514 if ((i.tm.opcode_modifier & W)
2515 || ((suffixes & (suffixes - 1))
2516 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2517 {
2518 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2519 return 0;
2520 }
2521 }
29b0f896 2522 }
252b5132 2523
9306ca4a
JB		 2524 /* Change the opcode based on the operand size given by i.suffix;
2525 We don't need to change things for byte insns. */
2526
29b0f896
AM		 2527 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2528 {
2529 /* It's not a byte, select word/dword operation. */
2530 if (i.tm.opcode_modifier & W)
2531 {
2532 if (i.tm.opcode_modifier & ShortForm)
2533 i.tm.base_opcode |= 8;
2534 else
2535 i.tm.base_opcode |= 1;
2536 }
0f3f3d8b 2537
29b0f896
AM		 2538 /* Now select between word & dword operations via the operand
2539 size prefix, except for instructions that will ignore this
2540 prefix anyway. */
2541 if (i.suffix != QWORD_MNEM_SUFFIX
9306ca4a
JB		 2542 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2543 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
9146926a
AM		 2544 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2545 || (flag_code == CODE_64BIT
2546 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2547 {
2548 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2549
29b0f896
AM		 2550 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2551 prefix = ADDR_PREFIX_OPCODE;
252b5132 2552
29b0f896
AM		 2553 if (!add_prefix (prefix))
2554 return 0;
24eab124 2555 }
252b5132 2556
29b0f896
AM		 2557 /* Set mode64 for an operand. */
2558 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2559 && flag_code == CODE_64BIT
29b0f896 2560 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2561 i.rex |= REX_MODE64;
3e73aa7c 2562
29b0f896
AM		 2563 /* Size floating point instruction. */
2564 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2565 if (i.tm.opcode_modifier & FloatMF)
2566 i.tm.base_opcode ^= 4;
29b0f896 2567 }
7ecd2f8b 2568
29b0f896
AM		 2569 return 1;
2570}
3e73aa7c 2571
29b0f896 2572static int
543613e9 2573check_byte_reg (void)
29b0f896
AM		 2574{
2575 int op;
543613e9 2576
29b0f896
AM		 2577 for (op = i.operands; --op >= 0;)
2578 {
2579 /* If this is an eight bit register, it's OK. If it's the 16 or
2580 32 bit version of an eight bit register, we will just use the
2581 low portion, and that's OK too. */
2582 if (i.types[op] & Reg8)
2583 continue;
2584
2585 /* movzx and movsx should not generate this warning. */
2586 if (intel_syntax
2587 && (i.tm.base_opcode == 0xfb7
2588 || i.tm.base_opcode == 0xfb6
2589 || i.tm.base_opcode == 0x63
2590 || i.tm.base_opcode == 0xfbe
2591 || i.tm.base_opcode == 0xfbf))
2592 continue;
2593
65ec77d2 2594 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 2595 {
2596 /* Prohibit these changes in the 64bit mode, since the
2597 lowering is more complicated. */
2598 if (flag_code == CODE_64BIT
2599 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2600 {
0f3f3d8b 2601 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2602 i.op[op].regs->reg_name,
2603 i.suffix);
2604 return 0;
2605 }
2606#if REGISTER_WARNINGS
2607 if (!quiet_warnings
2608 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2609 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2610 (i.op[op].regs + (i.types[op] & Reg16
2611 ? REGNAM_AL - REGNAM_AX
2612 : REGNAM_AL - REGNAM_EAX))->reg_name,
2613 i.op[op].regs->reg_name,
2614 i.suffix);
2615#endif
2616 continue;
2617 }
2618 /* Any other register is bad. */
2619 if (i.types[op] & (Reg | RegMMX | RegXMM
2620 | SReg2 | SReg3
2621 | Control | Debug | Test
2622 | FloatReg | FloatAcc))
2623 {
2624 as_bad (_("`%%%s' not allowed with `%s%c'"),
2625 i.op[op].regs->reg_name,
2626 i.tm.name,
2627 i.suffix);
2628 return 0;
2629 }
2630 }
2631 return 1;
2632}
2633
2634static int
2635check_long_reg ()
2636{
2637 int op;
2638
2639 for (op = i.operands; --op >= 0;)
2640 /* Reject eight bit registers, except where the template requires
2641 them. (eg. movzb) */
2642 if ((i.types[op] & Reg8) != 0
2643 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2644 {
2645 as_bad (_("`%%%s' not allowed with `%s%c'"),
2646 i.op[op].regs->reg_name,
2647 i.tm.name,
2648 i.suffix);
2649 return 0;
2650 }
2651 /* Warn if the e prefix on a general reg is missing. */
2652 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2653 && (i.types[op] & Reg16) != 0
2654 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2655 {
2656 /* Prohibit these changes in the 64bit mode, since the
2657 lowering is more complicated. */
2658 if (flag_code == CODE_64BIT)
252b5132 2659 {
0f3f3d8b 2660 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2661 i.op[op].regs->reg_name,
2662 i.suffix);
2663 return 0;
252b5132 2664 }
29b0f896
AM		 2665#if REGISTER_WARNINGS
2666 else
2667 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2668 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2669 i.op[op].regs->reg_name,
2670 i.suffix);
2671#endif
252b5132 2672 }
29b0f896
AM		 2673 /* Warn if the r prefix on a general reg is missing. */
2674 else if ((i.types[op] & Reg64) != 0
2675 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2676 {
0f3f3d8b 2677 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2678 i.op[op].regs->reg_name,
2679 i.suffix);
2680 return 0;
2681 }
2682 return 1;
2683}
252b5132 2684
29b0f896
AM		 2685static int
2686check_qword_reg ()
2687{
2688 int op;
252b5132 2689
29b0f896
AM		 2690 for (op = i.operands; --op >= 0; )
2691 /* Reject eight bit registers, except where the template requires
2692 them. (eg. movzb) */
2693 if ((i.types[op] & Reg8) != 0
2694 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2695 {
2696 as_bad (_("`%%%s' not allowed with `%s%c'"),
2697 i.op[op].regs->reg_name,
2698 i.tm.name,
2699 i.suffix);
2700 return 0;
2701 }
2702 /* Warn if the e prefix on a general reg is missing. */
2703 else if (((i.types[op] & Reg16) != 0
2704 || (i.types[op] & Reg32) != 0)
2705 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2706 {
2707 /* Prohibit these changes in the 64bit mode, since the
2708 lowering is more complicated. */
0f3f3d8b 2709 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2710 i.op[op].regs->reg_name,
2711 i.suffix);
2712 return 0;
252b5132 2713 }
29b0f896
AM		 2714 return 1;
2715}
252b5132 2716
29b0f896
AM		 2717static int
2718check_word_reg ()
2719{
2720 int op;
2721 for (op = i.operands; --op >= 0;)
2722 /* Reject eight bit registers, except where the template requires
2723 them. (eg. movzb) */
2724 if ((i.types[op] & Reg8) != 0
2725 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2726 {
2727 as_bad (_("`%%%s' not allowed with `%s%c'"),
2728 i.op[op].regs->reg_name,
2729 i.tm.name,
2730 i.suffix);
2731 return 0;
2732 }
2733 /* Warn if the e prefix on a general reg is present. */
2734 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2735 && (i.types[op] & Reg32) != 0
2736 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2737 {
29b0f896
AM		 2738 /* Prohibit these changes in the 64bit mode, since the
2739 lowering is more complicated. */
2740 if (flag_code == CODE_64BIT)
252b5132 2741 {
0f3f3d8b 2742 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2743 i.op[op].regs->reg_name,
2744 i.suffix);
2745 return 0;
252b5132 2746 }
29b0f896
AM		 2747 else
2748#if REGISTER_WARNINGS
2749 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2750 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2751 i.op[op].regs->reg_name,
2752 i.suffix);
2753#endif
2754 }
2755 return 1;
2756}
252b5132 2757
29b0f896
AM		 2758static int
2759finalize_imm ()
2760{
2761 unsigned int overlap0, overlap1, overlap2;
2762
2763 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 2764 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 2765 && overlap0 != Imm8 && overlap0 != Imm8S
2766 && overlap0 != Imm16 && overlap0 != Imm32S
2767 && overlap0 != Imm32 && overlap0 != Imm64)
2768 {
2769 if (i.suffix)
2770 {
2771 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2772 ? Imm8 | Imm8S
2773 : (i.suffix == WORD_MNEM_SUFFIX
2774 ? Imm16
2775 : (i.suffix == QWORD_MNEM_SUFFIX
2776 ? Imm64 | Imm32S
2777 : Imm32)));
2778 }
2779 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2780 || overlap0 == (Imm16 | Imm32)
2781 || overlap0 == (Imm16 | Imm32S))
2782 {
2783 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2784 ? Imm16 : Imm32S);
2785 }
2786 if (overlap0 != Imm8 && overlap0 != Imm8S
2787 && overlap0 != Imm16 && overlap0 != Imm32S
2788 && overlap0 != Imm32 && overlap0 != Imm64)
2789 {
2790 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2791 return 0;
2792 }
2793 }
2794 i.types[0] = overlap0;
2795
2796 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 2797 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 2798 && overlap1 != Imm8 && overlap1 != Imm8S
2799 && overlap1 != Imm16 && overlap1 != Imm32S
2800 && overlap1 != Imm32 && overlap1 != Imm64)
2801 {
2802 if (i.suffix)
2803 {
2804 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2805 ? Imm8 | Imm8S
2806 : (i.suffix == WORD_MNEM_SUFFIX
2807 ? Imm16
2808 : (i.suffix == QWORD_MNEM_SUFFIX
2809 ? Imm64 | Imm32S
2810 : Imm32)));
2811 }
2812 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2813 || overlap1 == (Imm16 | Imm32)
2814 || overlap1 == (Imm16 | Imm32S))
2815 {
2816 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2817 ? Imm16 : Imm32S);
2818 }
2819 if (overlap1 != Imm8 && overlap1 != Imm8S
2820 && overlap1 != Imm16 && overlap1 != Imm32S
2821 && overlap1 != Imm32 && overlap1 != Imm64)
2822 {
2823 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2824 return 0;
2825 }
2826 }
2827 i.types[1] = overlap1;
2828
2829 overlap2 = i.types[2] & i.tm.operand_types[2];
2830 assert ((overlap2 & Imm) == 0);
2831 i.types[2] = overlap2;
2832
2833 return 1;
2834}
2835
2836static int
2837process_operands ()
2838{
2839 /* Default segment register this instruction will use for memory
2840 accesses. 0 means unknown. This is only for optimizing out
2841 unnecessary segment overrides. */
2842 const seg_entry *default_seg = 0;
2843
2844 /* The imul $imm, %reg instruction is converted into
2845 imul $imm, %reg, %reg, and the clr %reg instruction
2846 is converted into xor %reg, %reg. */
2847 if (i.tm.opcode_modifier & regKludge)
2848 {
2849 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2850 /* Pretend we saw the extra register operand. */
2851 assert (i.op[first_reg_op + 1].regs == 0);
2852 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2853 i.types[first_reg_op + 1] = i.types[first_reg_op];
2854 i.reg_operands = 2;
2855 }
2856
2857 if (i.tm.opcode_modifier & ShortForm)
2858 {
2859 /* The register or float register operand is in operand 0 or 1. */
2860 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2861 /* Register goes in low 3 bits of opcode. */
2862 i.tm.base_opcode |= i.op[op].regs->reg_num;
2863 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2864 i.rex |= REX_EXTZ;
2865 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2866 {
2867 /* Warn about some common errors, but press on regardless.
2868 The first case can be generated by gcc (<= 2.8.1). */
2869 if (i.operands == 2)
2870 {
2871 /* Reversed arguments on faddp, fsubp, etc. */
2872 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2873 i.op[1].regs->reg_name,
2874 i.op[0].regs->reg_name);
2875 }
2876 else
2877 {
2878 /* Extraneous `l' suffix on fp insn. */
2879 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2880 i.op[0].regs->reg_name);
2881 }
2882 }
2883 }
2884 else if (i.tm.opcode_modifier & Modrm)
2885 {
2886 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2887 must be put into the modrm byte). Now, we make the modrm and
2888 index base bytes based on all the info we've collected. */
29b0f896
AM		 2889
2890 default_seg = build_modrm_byte ();
2891 }
2892 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2893 {
2894 if (i.tm.base_opcode == POP_SEG_SHORT
2895 && i.op[0].regs->reg_num == 1)
2896 {
2897 as_bad (_("you can't `pop %%cs'"));
2898 return 0;
2899 }
2900 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2901 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2902 i.rex |= REX_EXTZ;
2903 }
2904 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2905 {
2906 default_seg = &ds;
2907 }
2908 else if ((i.tm.opcode_modifier & IsString) != 0)
2909 {
2910 /* For the string instructions that allow a segment override
2911 on one of their operands, the default segment is ds. */
2912 default_seg = &ds;
2913 }
2914
30123838
JB		 2915 if ((i.tm.base_opcode == 0x8d /* lea */
2916 || (i.tm.cpu_flags & CpuSVME))
2917 && i.seg[0] && !quiet_warnings)
2918 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 2919
2920 /* If a segment was explicitly specified, and the specified segment
2921 is not the default, use an opcode prefix to select it. If we
2922 never figured out what the default segment is, then default_seg
2923 will be zero at this point, and the specified segment prefix will
2924 always be used. */
29b0f896
AM		 2925 if ((i.seg[0]) && (i.seg[0] != default_seg))
2926 {
2927 if (!add_prefix (i.seg[0]->seg_prefix))
2928 return 0;
2929 }
2930 return 1;
2931}
2932
2933static const seg_entry *
2934build_modrm_byte ()
2935{
2936 const seg_entry *default_seg = 0;
2937
2938 /* i.reg_operands MUST be the number of real register operands;
2939 implicit registers do not count. */
2940 if (i.reg_operands == 2)
2941 {
2942 unsigned int source, dest;
2943 source = ((i.types[0]
2944 & (Reg | RegMMX | RegXMM
2945 | SReg2 | SReg3
2946 | Control | Debug | Test))
2947 ? 0 : 1);
2948 dest = source + 1;
2949
2950 i.rm.mode = 3;
2951 /* One of the register operands will be encoded in the i.tm.reg
2952 field, the other in the combined i.tm.mode and i.tm.regmem
2953 fields. If no form of this instruction supports a memory
2954 destination operand, then we assume the source operand may
2955 sometimes be a memory operand and so we need to store the
2956 destination in the i.rm.reg field. */
2957 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2958 {
2959 i.rm.reg = i.op[dest].regs->reg_num;
2960 i.rm.regmem = i.op[source].regs->reg_num;
2961 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2962 i.rex |= REX_EXTX;
2963 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2964 i.rex |= REX_EXTZ;
2965 }
2966 else
2967 {
2968 i.rm.reg = i.op[source].regs->reg_num;
2969 i.rm.regmem = i.op[dest].regs->reg_num;
2970 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2971 i.rex |= REX_EXTZ;
2972 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2973 i.rex |= REX_EXTX;
2974 }
c4a530c5
JB		 2975 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
2976 {
2977 if (!((i.types[0] | i.types[1]) & Control))
2978 abort ();
2979 i.rex &= ~(REX_EXTX | REX_EXTZ);
2980 add_prefix (LOCK_PREFIX_OPCODE);
2981 }
29b0f896
AM		 2982 }
2983 else
2984 { /* If it's not 2 reg operands... */
2985 if (i.mem_operands)
2986 {
2987 unsigned int fake_zero_displacement = 0;
2988 unsigned int op = ((i.types[0] & AnyMem)
2989 ? 0
2990 : (i.types[1] & AnyMem) ? 1 : 2);
2991
2992 default_seg = &ds;
2993
2994 if (i.base_reg == 0)
2995 {
2996 i.rm.mode = 0;
2997 if (!i.disp_operands)
2998 fake_zero_displacement = 1;
2999 if (i.index_reg == 0)
3000 {
3001 /* Operand is just <disp> */
20f0a1fc 3002 if (flag_code == CODE_64BIT)
29b0f896
AM		 3003 {
3004 /* 64bit mode overwrites the 32bit absolute
3005 addressing by RIP relative addressing and
3006 absolute addressing is encoded by one of the
3007 redundant SIB forms. */
3008 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3009 i.sib.base = NO_BASE_REGISTER;
3010 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 3011 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3012 }
3013 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3014 {
3015 i.rm.regmem = NO_BASE_REGISTER_16;
3016 i.types[op] = Disp16;
3017 }
3018 else
3019 {
3020 i.rm.regmem = NO_BASE_REGISTER;
3021 i.types[op] = Disp32;
29b0f896
AM		 3022 }
3023 }
3024 else /* !i.base_reg && i.index_reg */
3025 {
3026 i.sib.index = i.index_reg->reg_num;
3027 i.sib.base = NO_BASE_REGISTER;
3028 i.sib.scale = i.log2_scale_factor;
3029 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3030 i.types[op] &= ~Disp;
3031 if (flag_code != CODE_64BIT)
3032 i.types[op] |= Disp32; /* Must be 32 bit */
3033 else
3034 i.types[op] |= Disp32S;
3035 if ((i.index_reg->reg_flags & RegRex) != 0)
3036 i.rex |= REX_EXTY;
3037 }
3038 }
3039 /* RIP addressing for 64bit mode. */
3040 else if (i.base_reg->reg_type == BaseIndex)
3041 {
3042 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3043 i.types[op] &= ~ Disp;
29b0f896
AM		 3044 i.types[op] |= Disp32S;
3045 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 3046 if (! i.disp_operands)
3047 fake_zero_displacement = 1;
29b0f896
AM		 3048 }
3049 else if (i.base_reg->reg_type & Reg16)
3050 {
3051 switch (i.base_reg->reg_num)
3052 {
3053 case 3: /* (%bx) */
3054 if (i.index_reg == 0)
3055 i.rm.regmem = 7;
3056 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3057 i.rm.regmem = i.index_reg->reg_num - 6;
3058 break;
3059 case 5: /* (%bp) */
3060 default_seg = &ss;
3061 if (i.index_reg == 0)
3062 {
3063 i.rm.regmem = 6;
3064 if ((i.types[op] & Disp) == 0)
3065 {
3066 /* fake (%bp) into 0(%bp) */
3067 i.types[op] |= Disp8;
252b5132 3068 fake_zero_displacement = 1;
29b0f896
AM		 3069 }
3070 }
3071 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3072 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3073 break;
3074 default: /* (%si) -> 4 or (%di) -> 5 */
3075 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3076 }
3077 i.rm.mode = mode_from_disp_size (i.types[op]);
3078 }
3079 else /* i.base_reg and 32/64 bit mode */
3080 {
3081 if (flag_code == CODE_64BIT
3082 && (i.types[op] & Disp))
20f0a1fc
NC		 3083 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3084
29b0f896
AM		 3085 i.rm.regmem = i.base_reg->reg_num;
3086 if ((i.base_reg->reg_flags & RegRex) != 0)
3087 i.rex |= REX_EXTZ;
3088 i.sib.base = i.base_reg->reg_num;
3089 /* x86-64 ignores REX prefix bit here to avoid decoder
3090 complications. */
3091 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3092 {
3093 default_seg = &ss;
3094 if (i.disp_operands == 0)
3095 {
3096 fake_zero_displacement = 1;
3097 i.types[op] |= Disp8;
3098 }
3099 }
3100 else if (i.base_reg->reg_num == ESP_REG_NUM)
3101 {
3102 default_seg = &ss;
3103 }
3104 i.sib.scale = i.log2_scale_factor;
3105 if (i.index_reg == 0)
3106 {
3107 /* <disp>(%esp) becomes two byte modrm with no index
3108 register. We've already stored the code for esp
3109 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3110 Any base register besides %esp will not use the
3111 extra modrm byte. */
3112 i.sib.index = NO_INDEX_REGISTER;
3113#if !SCALE1_WHEN_NO_INDEX
3114 /* Another case where we force the second modrm byte. */
3115 if (i.log2_scale_factor)
3116 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3117#endif
29b0f896
AM		 3118 }
3119 else
3120 {
3121 i.sib.index = i.index_reg->reg_num;
3122 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3123 if ((i.index_reg->reg_flags & RegRex) != 0)
3124 i.rex |= REX_EXTY;
3125 }
3126 i.rm.mode = mode_from_disp_size (i.types[op]);
3127 }
252b5132 3128
29b0f896
AM		 3129 if (fake_zero_displacement)
3130 {
3131 /* Fakes a zero displacement assuming that i.types[op]
3132 holds the correct displacement size. */
3133 expressionS *exp;
3134
3135 assert (i.op[op].disps == 0);
3136 exp = &disp_expressions[i.disp_operands++];
3137 i.op[op].disps = exp;
3138 exp->X_op = O_constant;
3139 exp->X_add_number = 0;
3140 exp->X_add_symbol = (symbolS *) 0;
3141 exp->X_op_symbol = (symbolS *) 0;
3142 }
3143 }
252b5132 3144
29b0f896
AM		 3145 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3146 (if any) based on i.tm.extension_opcode. Again, we must be
3147 careful to make sure that segment/control/debug/test/MMX
3148 registers are coded into the i.rm.reg field. */
3149 if (i.reg_operands)
3150 {
3151 unsigned int op =
3152 ((i.types[0]
3153 & (Reg | RegMMX | RegXMM
3154 | SReg2 | SReg3
3155 | Control | Debug | Test))
3156 ? 0
3157 : ((i.types[1]
3158 & (Reg | RegMMX | RegXMM
3159 | SReg2 | SReg3
3160 | Control | Debug | Test))
3161 ? 1
3162 : 2));
3163 /* If there is an extension opcode to put here, the register
3164 number must be put into the regmem field. */
3165 if (i.tm.extension_opcode != None)
3166 {
3167 i.rm.regmem = i.op[op].regs->reg_num;
3168 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3169 i.rex |= REX_EXTZ;
3170 }
3171 else
3172 {
3173 i.rm.reg = i.op[op].regs->reg_num;
3174 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3175 i.rex |= REX_EXTX;
3176 }
252b5132 3177
29b0f896
AM		 3178 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3179 must set it to 3 to indicate this is a register operand
3180 in the regmem field. */
3181 if (!i.mem_operands)
3182 i.rm.mode = 3;
3183 }
252b5132 3184
29b0f896
AM		 3185 /* Fill in i.rm.reg field with extension opcode (if any). */
3186 if (i.tm.extension_opcode != None)
3187 i.rm.reg = i.tm.extension_opcode;
3188 }
3189 return default_seg;
3190}
252b5132 3191
29b0f896
AM		 3192static void
3193output_branch ()
3194{
3195 char *p;
3196 int code16;
3197 int prefix;
3198 relax_substateT subtype;
3199 symbolS *sym;
3200 offsetT off;
3201
3202 code16 = 0;
3203 if (flag_code == CODE_16BIT)
3204 code16 = CODE16;
3205
3206 prefix = 0;
3207 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3208 {
29b0f896
AM		 3209 prefix = 1;
3210 i.prefixes -= 1;
3211 code16 ^= CODE16;
252b5132 3212 }
29b0f896
AM		 3213 /* Pentium4 branch hints. */
3214 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3215 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3216 {
29b0f896
AM		 3217 prefix++;
3218 i.prefixes--;
3219 }
3220 if (i.prefix[REX_PREFIX] != 0)
3221 {
3222 prefix++;
3223 i.prefixes--;
2f66722d
AM		 3224 }
3225
29b0f896
AM		 3226 if (i.prefixes != 0 && !intel_syntax)
3227 as_warn (_("skipping prefixes on this instruction"));
3228
3229 /* It's always a symbol; End frag & setup for relax.
3230 Make sure there is enough room in this frag for the largest
3231 instruction we may generate in md_convert_frag. This is 2
3232 bytes for the opcode and room for the prefix and largest
3233 displacement. */
3234 frag_grow (prefix + 2 + 4);
3235 /* Prefix and 1 opcode byte go in fr_fix. */
3236 p = frag_more (prefix + 1);
3237 if (i.prefix[DATA_PREFIX] != 0)
3238 *p++ = DATA_PREFIX_OPCODE;
3239 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3240 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3241 *p++ = i.prefix[SEG_PREFIX];
3242 if (i.prefix[REX_PREFIX] != 0)
3243 *p++ = i.prefix[REX_PREFIX];
3244 *p = i.tm.base_opcode;
3245
3246 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3247 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3248 else if ((cpu_arch_flags & Cpu386) != 0)
3249 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3250 else
3251 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3252 subtype |= code16;
3e73aa7c 3253
29b0f896
AM		 3254 sym = i.op[0].disps->X_add_symbol;
3255 off = i.op[0].disps->X_add_number;
3e73aa7c 3256
29b0f896
AM		 3257 if (i.op[0].disps->X_op != O_constant
3258 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3259 {
29b0f896
AM		 3260 /* Handle complex expressions. */
3261 sym = make_expr_symbol (i.op[0].disps);
3262 off = 0;
3263 }
3e73aa7c 3264
29b0f896
AM		 3265 /* 1 possible extra opcode + 4 byte displacement go in var part.
3266 Pass reloc in fr_var. */
3267 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3268}
3e73aa7c 3269
29b0f896
AM		 3270static void
3271output_jump ()
3272{
3273 char *p;
3274 int size;
3e02c1cc 3275 fixS *fixP;
29b0f896
AM		 3276
3277 if (i.tm.opcode_modifier & JumpByte)
3278 {
3279 /* This is a loop or jecxz type instruction. */
3280 size = 1;
3281 if (i.prefix[ADDR_PREFIX] != 0)
3282 {
3283 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3284 i.prefixes -= 1;
3285 }
3286 /* Pentium4 branch hints. */
3287 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3288 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3289 {
3290 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3291 i.prefixes--;
3e73aa7c
JH		 3292 }
3293 }
29b0f896
AM		 3294 else
3295 {
3296 int code16;
3e73aa7c 3297
29b0f896
AM		 3298 code16 = 0;
3299 if (flag_code == CODE_16BIT)
3300 code16 = CODE16;
3e73aa7c 3301
29b0f896
AM		 3302 if (i.prefix[DATA_PREFIX] != 0)
3303 {
3304 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3305 i.prefixes -= 1;
3306 code16 ^= CODE16;
3307 }
252b5132 3308
29b0f896
AM		 3309 size = 4;
3310 if (code16)
3311 size = 2;
3312 }
9fcc94b6 3313
29b0f896
AM		 3314 if (i.prefix[REX_PREFIX] != 0)
3315 {
3316 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3317 i.prefixes -= 1;
3318 }
252b5132 3319
29b0f896
AM		 3320 if (i.prefixes != 0 && !intel_syntax)
3321 as_warn (_("skipping prefixes on this instruction"));
e0890092 3322
29b0f896
AM		 3323 p = frag_more (1 + size);
3324 *p++ = i.tm.base_opcode;
e0890092 3325
3e02c1cc
AM		 3326 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3327 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3328
3329 /* All jumps handled here are signed, but don't use a signed limit
3330 check for 32 and 16 bit jumps as we want to allow wrap around at
3331 4G and 64k respectively. */
3332 if (size == 1)
3333 fixP->fx_signed = 1;
29b0f896 3334}
e0890092 3335
29b0f896
AM		 3336static void
3337output_interseg_jump ()
3338{
3339 char *p;
3340 int size;
3341 int prefix;
3342 int code16;
252b5132 3343
29b0f896
AM		 3344 code16 = 0;
3345 if (flag_code == CODE_16BIT)
3346 code16 = CODE16;
a217f122 3347
29b0f896
AM		 3348 prefix = 0;
3349 if (i.prefix[DATA_PREFIX] != 0)
3350 {
3351 prefix = 1;
3352 i.prefixes -= 1;
3353 code16 ^= CODE16;
3354 }
3355 if (i.prefix[REX_PREFIX] != 0)
3356 {
3357 prefix++;
3358 i.prefixes -= 1;
3359 }
252b5132 3360
29b0f896
AM		 3361 size = 4;
3362 if (code16)
3363 size = 2;
252b5132 3364
29b0f896
AM		 3365 if (i.prefixes != 0 && !intel_syntax)
3366 as_warn (_("skipping prefixes on this instruction"));
252b5132 3367
29b0f896
AM		 3368 /* 1 opcode; 2 segment; offset */
3369 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3370
29b0f896
AM		 3371 if (i.prefix[DATA_PREFIX] != 0)
3372 *p++ = DATA_PREFIX_OPCODE;
252b5132 3373
29b0f896
AM		 3374 if (i.prefix[REX_PREFIX] != 0)
3375 *p++ = i.prefix[REX_PREFIX];
252b5132 3376
29b0f896
AM		 3377 *p++ = i.tm.base_opcode;
3378 if (i.op[1].imms->X_op == O_constant)
3379 {
3380 offsetT n = i.op[1].imms->X_add_number;
252b5132 3381
29b0f896
AM		 3382 if (size == 2
3383 && !fits_in_unsigned_word (n)
3384 && !fits_in_signed_word (n))
3385 {
3386 as_bad (_("16-bit jump out of range"));
3387 return;
3388 }
3389 md_number_to_chars (p, n, size);
3390 }
3391 else
3392 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3393 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3394 if (i.op[0].imms->X_op != O_constant)
3395 as_bad (_("can't handle non absolute segment in `%s'"),
3396 i.tm.name);
3397 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3398}
a217f122 3399
29b0f896
AM		 3400static void
3401output_insn ()
3402{
2bbd9c25
JJ		 3403 fragS *insn_start_frag;
3404 offsetT insn_start_off;
3405
29b0f896
AM		 3406 /* Tie dwarf2 debug info to the address at the start of the insn.
3407 We can't do this after the insn has been output as the current
3408 frag may have been closed off. eg. by frag_var. */
3409 dwarf2_emit_insn (0);
3410
2bbd9c25
JJ		 3411 insn_start_frag = frag_now;
3412 insn_start_off = frag_now_fix ();
3413
29b0f896
AM		 3414 /* Output jumps. */
3415 if (i.tm.opcode_modifier & Jump)
3416 output_branch ();
3417 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3418 output_jump ();
3419 else if (i.tm.opcode_modifier & JumpInterSegment)
3420 output_interseg_jump ();
3421 else
3422 {
3423 /* Output normal instructions here. */
3424 char *p;
3425 unsigned char *q;
252b5132 3426
bc4bd9ab
MK		 3427 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3428 more higher byte to specify a prefix the instruction
3429 requires. */
3430 if ((i.tm.base_opcode & 0xff0000) != 0)
3431 {
3432 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3433 {
3434 unsigned int prefix;
3435 prefix = (i.tm.base_opcode >> 16) & 0xff;
3436
3437 if (prefix != REPE_PREFIX_OPCODE
3438 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3439 add_prefix (prefix);
3440 }
3441 else
3442 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
0f10071e 3443 }
252b5132 3444
29b0f896
AM		 3445 /* The prefix bytes. */
3446 for (q = i.prefix;
3447 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3448 q++)
3449 {
3450 if (*q)
3451 {
3452 p = frag_more (1);
3453 md_number_to_chars (p, (valueT) *q, 1);
3454 }
3455 }
252b5132 3456
29b0f896
AM		 3457 /* Now the opcode; be careful about word order here! */
3458 if (fits_in_unsigned_byte (i.tm.base_opcode))
3459 {
3460 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3461 }
3462 else
3463 {
bc4bd9ab 3464 p = frag_more (2);
0f10071e 3465
29b0f896
AM		 3466 /* Put out high byte first: can't use md_number_to_chars! */
3467 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3468 *p = i.tm.base_opcode & 0xff;
3469 }
3e73aa7c 3470
29b0f896
AM		 3471 /* Now the modrm byte and sib byte (if present). */
3472 if (i.tm.opcode_modifier & Modrm)
3473 {
3474 p = frag_more (1);
3475 md_number_to_chars (p,
3476 (valueT) (i.rm.regmem << 0
3477 | i.rm.reg << 3
3478 | i.rm.mode << 6),
3479 1);
3480 /* If i.rm.regmem == ESP (4)
3481 && i.rm.mode != (Register mode)
3482 && not 16 bit
3483 ==> need second modrm byte. */
3484 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3485 && i.rm.mode != 3
3486 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3487 {
3488 p = frag_more (1);
3489 md_number_to_chars (p,
3490 (valueT) (i.sib.base << 0
3491 | i.sib.index << 3
3492 | i.sib.scale << 6),
3493 1);
3494 }
3495 }
3e73aa7c 3496
29b0f896 3497 if (i.disp_operands)
2bbd9c25 3498 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3499
29b0f896 3500 if (i.imm_operands)
2bbd9c25 3501 output_imm (insn_start_frag, insn_start_off);
29b0f896 3502 }
252b5132 3503
29b0f896
AM		 3504#ifdef DEBUG386
3505 if (flag_debug)
3506 {
3507 pi (line, &i);
3508 }
3509#endif /* DEBUG386 */
3510}
252b5132 3511
29b0f896 3512static void
2bbd9c25
JJ		 3513output_disp (insn_start_frag, insn_start_off)
3514 fragS *insn_start_frag;
3515 offsetT insn_start_off;
29b0f896
AM		 3516{
3517 char *p;
3518 unsigned int n;
252b5132 3519
29b0f896
AM		 3520 for (n = 0; n < i.operands; n++)
3521 {
3522 if (i.types[n] & Disp)
3523 {
3524 if (i.op[n].disps->X_op == O_constant)
3525 {
3526 int size;
3527 offsetT val;
252b5132 3528
29b0f896
AM		 3529 size = 4;
3530 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3531 {
3532 size = 2;
3533 if (i.types[n] & Disp8)
3534 size = 1;
3535 if (i.types[n] & Disp64)
3536 size = 8;
3537 }
3538 val = offset_in_range (i.op[n].disps->X_add_number,
3539 size);
3540 p = frag_more (size);
3541 md_number_to_chars (p, val, size);
3542 }
3543 else
3544 {
f86103b7 3545 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3546 int size = 4;
3547 int sign = 0;
3548 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3549
3550 /* The PC relative address is computed relative
3551 to the instruction boundary, so in case immediate
3552 fields follows, we need to adjust the value. */
3553 if (pcrel && i.imm_operands)
3554 {
3555 int imm_size = 4;
3556 unsigned int n1;
252b5132 3557
29b0f896
AM		 3558 for (n1 = 0; n1 < i.operands; n1++)
3559 if (i.types[n1] & Imm)
252b5132 3560 {
29b0f896 3561 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3562 {
29b0f896
AM		 3563 imm_size = 2;
3564 if (i.types[n1] & (Imm8 | Imm8S))
3565 imm_size = 1;
3566 if (i.types[n1] & Imm64)
3567 imm_size = 8;
252b5132 3568 }
29b0f896 3569 break;
252b5132 3570 }
29b0f896
AM		 3571 /* We should find the immediate. */
3572 if (n1 == i.operands)
3573 abort ();
3574 i.op[n].disps->X_add_number -= imm_size;
3575 }
520dc8e8 3576
29b0f896
AM		 3577 if (i.types[n] & Disp32S)
3578 sign = 1;
3e73aa7c 3579
29b0f896
AM		 3580 if (i.types[n] & (Disp16 | Disp64))
3581 {
3582 size = 2;
3583 if (i.types[n] & Disp64)
3584 size = 8;
3585 }
520dc8e8 3586
29b0f896 3587 p = frag_more (size);
2bbd9c25 3588 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 3589 if (GOT_symbol
2bbd9c25 3590 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113
JB		 3591 && (((reloc_type == BFD_RELOC_32
3592 || reloc_type == BFD_RELOC_X86_64_32S)
3593 && (i.op[n].disps->X_op == O_symbol
3594 || (i.op[n].disps->X_op == O_add
3595 && ((symbol_get_value_expression
3596 (i.op[n].disps->X_op_symbol)->X_op)
3597 == O_subtract))))
3598 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 3599 {
3600 offsetT add;
3601
3602 if (insn_start_frag == frag_now)
3603 add = (p - frag_now->fr_literal) - insn_start_off;
3604 else
3605 {
3606 fragS *fr;
3607
3608 add = insn_start_frag->fr_fix - insn_start_off;
3609 for (fr = insn_start_frag->fr_next;
3610 fr && fr != frag_now; fr = fr->fr_next)
3611 add += fr->fr_fix;
3612 add += p - frag_now->fr_literal;
3613 }
3614
4fa24527 3615 if (!object_64bit)
d6ab8113
JB		 3616 reloc_type = BFD_RELOC_386_GOTPC;
3617 else
3618 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25
JJ		 3619 i.op[n].disps->X_add_number += add;
3620 }
062cd5e7 3621 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3622 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3623 }
3624 }
3625 }
3626}
252b5132 3627
29b0f896 3628static void
2bbd9c25
JJ		 3629output_imm (insn_start_frag, insn_start_off)
3630 fragS *insn_start_frag;
3631 offsetT insn_start_off;
29b0f896
AM		 3632{
3633 char *p;
3634 unsigned int n;
252b5132 3635
29b0f896
AM		 3636 for (n = 0; n < i.operands; n++)
3637 {
3638 if (i.types[n] & Imm)
3639 {
3640 if (i.op[n].imms->X_op == O_constant)
3641 {
3642 int size;
3643 offsetT val;
b4cac588 3644
29b0f896
AM		 3645 size = 4;
3646 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3647 {
3648 size = 2;
3649 if (i.types[n] & (Imm8 | Imm8S))
3650 size = 1;
3651 else if (i.types[n] & Imm64)
3652 size = 8;
3653 }
3654 val = offset_in_range (i.op[n].imms->X_add_number,
3655 size);
3656 p = frag_more (size);
3657 md_number_to_chars (p, val, size);
3658 }
3659 else
3660 {
3661 /* Not absolute_section.
3662 Need a 32-bit fixup (don't support 8bit
3663 non-absolute imms). Try to support other
3664 sizes ... */
f86103b7 3665 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3666 int size = 4;
3667 int sign = 0;
3668
3669 if ((i.types[n] & (Imm32S))
a7d61044
JB		 3670 && (i.suffix == QWORD_MNEM_SUFFIX
3671 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 3672 sign = 1;
3673 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3674 {
3675 size = 2;
3676 if (i.types[n] & (Imm8 | Imm8S))
3677 size = 1;
3678 if (i.types[n] & Imm64)
3679 size = 8;
3680 }
520dc8e8 3681
29b0f896
AM		 3682 p = frag_more (size);
3683 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 3684
2bbd9c25
JJ		 3685 /* This is tough to explain. We end up with this one if we
3686 * have operands that look like
3687 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3688 * obtain the absolute address of the GOT, and it is strongly
3689 * preferable from a performance point of view to avoid using
3690 * a runtime relocation for this. The actual sequence of
3691 * instructions often look something like:
3692 *
3693 * call .L66
3694 * .L66:
3695 * popl %ebx
3696 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3697 *
3698 * The call and pop essentially return the absolute address
3699 * of the label .L66 and store it in %ebx. The linker itself
3700 * will ultimately change the first operand of the addl so
3701 * that %ebx points to the GOT, but to keep things simple, the
3702 * .o file must have this operand set so that it generates not
3703 * the absolute address of .L66, but the absolute address of
3704 * itself. This allows the linker itself simply treat a GOTPC
3705 * relocation as asking for a pcrel offset to the GOT to be
3706 * added in, and the addend of the relocation is stored in the
3707 * operand field for the instruction itself.
3708 *
3709 * Our job here is to fix the operand so that it would add
3710 * the correct offset so that %ebx would point to itself. The
3711 * thing that is tricky is that .-.L66 will point to the
3712 * beginning of the instruction, so we need to further modify
3713 * the operand so that it will point to itself. There are
3714 * other cases where you have something like:
3715 *
3716 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3717 *
3718 * and here no correction would be required. Internally in
3719 * the assembler we treat operands of this form as not being
3720 * pcrel since the '.' is explicitly mentioned, and I wonder
3721 * whether it would simplify matters to do it this way. Who
3722 * knows. In earlier versions of the PIC patches, the
3723 * pcrel_adjust field was used to store the correction, but
3724 * since the expression is not pcrel, I felt it would be
3725 * confusing to do it this way. */
3726
d6ab8113
JB		 3727 if ((reloc_type == BFD_RELOC_32
3728 || reloc_type == BFD_RELOC_X86_64_32S)
29b0f896
AM		 3729 && GOT_symbol
3730 && GOT_symbol == i.op[n].imms->X_add_symbol
3731 && (i.op[n].imms->X_op == O_symbol
3732 || (i.op[n].imms->X_op == O_add
3733 && ((symbol_get_value_expression
3734 (i.op[n].imms->X_op_symbol)->X_op)
3735 == O_subtract))))
3736 {
2bbd9c25
JJ		 3737 offsetT add;
3738
3739 if (insn_start_frag == frag_now)
3740 add = (p - frag_now->fr_literal) - insn_start_off;
3741 else
3742 {
3743 fragS *fr;
3744
3745 add = insn_start_frag->fr_fix - insn_start_off;
3746 for (fr = insn_start_frag->fr_next;
3747 fr && fr != frag_now; fr = fr->fr_next)
3748 add += fr->fr_fix;
3749 add += p - frag_now->fr_literal;
3750 }
3751
4fa24527 3752 if (!object_64bit)
d6ab8113
JB		 3753 reloc_type = BFD_RELOC_386_GOTPC;
3754 else
3755 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 3756 i.op[n].imms->X_add_number += add;
29b0f896 3757 }
29b0f896
AM		 3758 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3759 i.op[n].imms, 0, reloc_type);
3760 }
3761 }
3762 }
252b5132
RH		 3763}
3764\f
718ddfc0
JB		 3765#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3766# define lex_got(reloc, adjust, types) NULL
3767#else
f3c180ae
AM		 3768/* Parse operands of the form
3769 <symbol>@GOTOFF+<nnn>
3770 and similar .plt or .got references.
3771
3772 If we find one, set up the correct relocation in RELOC and copy the
3773 input string, minus the `@GOTOFF' into a malloc'd buffer for
3774 parsing by the calling routine. Return this buffer, and if ADJUST
3775 is non-null set it to the length of the string we removed from the
3776 input line. Otherwise return NULL. */
3777static char *
3956db08
JB		 3778lex_got (enum bfd_reloc_code_real *reloc,
3779 int *adjust,
3780 unsigned int *types)
f3c180ae 3781{
f3c180ae
AM		 3782 static const struct {
3783 const char *str;
4fa24527 3784 const enum bfd_reloc_code_real rel[2];
3956db08 3785 const unsigned int types64;
f3c180ae 3786 } gotrel[] = {
4fa24527
JB		 3787 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
3788 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
3789 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
3790 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
3791 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
3792 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
3793 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
3794 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3795 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
3796 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3797 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
3798 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
3799 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 3800 };
3801 char *cp;
3802 unsigned int j;
3803
718ddfc0
JB		 3804 if (!IS_ELF)
3805 return NULL;
3806
f3c180ae
AM		 3807 for (cp = input_line_pointer; *cp != '@'; cp++)
3808 if (is_end_of_line[(unsigned char) *cp])
3809 return NULL;
3810
3811 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3812 {
3813 int len;
3814
3815 len = strlen (gotrel[j].str);
28f81592 3816 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 3817 {
4fa24527 3818 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 3819 {
28f81592
AM		 3820 int first, second;
3821 char *tmpbuf, *past_reloc;
f3c180ae 3822
4fa24527 3823 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 3824 if (adjust)
3825 *adjust = len;
f3c180ae 3826
3956db08
JB		 3827 if (types)
3828 {
3829 if (flag_code != CODE_64BIT)
3830 *types = Imm32|Disp32;
3831 else
3832 *types = gotrel[j].types64;
3833 }
3834
f3c180ae
AM		 3835 if (GOT_symbol == NULL)
3836 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3837
3838 /* Replace the relocation token with ' ', so that
3839 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3840
3841 /* The length of the first part of our input line. */
f3c180ae 3842 first = cp - input_line_pointer;
28f81592
AM		 3843
3844 /* The second part goes from after the reloc token until
3845 (and including) an end_of_line char. Don't use strlen
3846 here as the end_of_line char may not be a NUL. */
3847 past_reloc = cp + 1 + len;
3848 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3849 ;
3850 second = cp - past_reloc;
3851
3852 /* Allocate and copy string. The trailing NUL shouldn't
3853 be necessary, but be safe. */
3854 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3855 memcpy (tmpbuf, input_line_pointer, first);
3856 tmpbuf[first] = ' ';
28f81592
AM		 3857 memcpy (tmpbuf + first + 1, past_reloc, second);
3858 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3859 return tmpbuf;
3860 }
3861
4fa24527
JB		 3862 as_bad (_("@%s reloc is not supported with %d-bit output format"),
3863 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 3864 return NULL;
3865 }
3866 }
3867
3868 /* Might be a symbol version string. Don't as_bad here. */
3869 return NULL;
3870}
3871
3872/* x86_cons_fix_new is called via the expression parsing code when a
3873 reloc is needed. We use this hook to get the correct .got reloc. */
f86103b7 3874static enum bfd_reloc_code_real got_reloc = NO_RELOC;
f3c180ae
AM		 3875
3876void
3877x86_cons_fix_new (frag, off, len, exp)
3878 fragS *frag;
3879 unsigned int off;
3880 unsigned int len;
3881 expressionS *exp;
3882{
3956db08 3883 enum bfd_reloc_code_real r = reloc (len, 0, -1, got_reloc);
f3c180ae
AM		 3884 got_reloc = NO_RELOC;
3885 fix_new_exp (frag, off, len, exp, 0, r);
3886}
3887
3888void
3889x86_cons (exp, size)
3890 expressionS *exp;
3891 int size;
3892{
4fa24527 3893 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 3894 {
3895 /* Handle @GOTOFF and the like in an expression. */
3896 char *save;
3897 char *gotfree_input_line;
3898 int adjust;
3899
3900 save = input_line_pointer;
3956db08 3901 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 3902 if (gotfree_input_line)
3903 input_line_pointer = gotfree_input_line;
3904
3905 expression (exp);
3906
3907 if (gotfree_input_line)
3908 {
3909 /* expression () has merrily parsed up to the end of line,
3910 or a comma - in the wrong buffer. Transfer how far
3911 input_line_pointer has moved to the right buffer. */
3912 input_line_pointer = (save
3913 + (input_line_pointer - gotfree_input_line)
3914 + adjust);
3915 free (gotfree_input_line);
3916 }
3917 }
3918 else
3919 expression (exp);
3920}
3921#endif
3922
6482c264
NC		 3923#ifdef TE_PE
3924
6482c264
NC		 3925void
3926x86_pe_cons_fix_new (frag, off, len, exp)
3927 fragS *frag;
3928 unsigned int off;
3929 unsigned int len;
3930 expressionS *exp;
3931{
3956db08 3932 enum bfd_reloc_code_real r = reloc (len, 0, -1, NO_RELOC);
6482c264
NC		 3933
3934 if (exp->X_op == O_secrel)
3935 {
3936 exp->X_op = O_symbol;
3937 r = BFD_RELOC_32_SECREL;
3938 }
3939
3940 fix_new_exp (frag, off, len, exp, 0, r);
3941}
3942
3943static void
3944pe_directive_secrel (dummy)
3945 int dummy ATTRIBUTE_UNUSED;
3946{
3947 expressionS exp;
3948
3949 do
3950 {
3951 expression (&exp);
3952 if (exp.X_op == O_symbol)
3953 exp.X_op = O_secrel;
3954
3955 emit_expr (&exp, 4);
3956 }
3957 while (*input_line_pointer++ == ',');
3958
3959 input_line_pointer--;
3960 demand_empty_rest_of_line ();
3961}
3962
3963#endif
3964
252b5132
RH		 3965static int i386_immediate PARAMS ((char *));
3966
3967static int
3968i386_immediate (imm_start)
3969 char *imm_start;
3970{
3971 char *save_input_line_pointer;
f3c180ae 3972 char *gotfree_input_line;
252b5132 3973 segT exp_seg = 0;
47926f60 3974 expressionS *exp;
3956db08 3975 unsigned int types = ~0U;
252b5132
RH		 3976
3977 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3978 {
d0b47220 3979 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3980 return 0;
3981 }
3982
3983 exp = &im_expressions[i.imm_operands++];
520dc8e8 3984 i.op[this_operand].imms = exp;
252b5132
RH		 3985
3986 if (is_space_char (*imm_start))
3987 ++imm_start;
3988
3989 save_input_line_pointer = input_line_pointer;
3990 input_line_pointer = imm_start;
3991
3956db08 3992 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 3993 if (gotfree_input_line)
3994 input_line_pointer = gotfree_input_line;
252b5132
RH		 3995
3996 exp_seg = expression (exp);
3997
83183c0c 3998 SKIP_WHITESPACE ();
252b5132 3999 if (*input_line_pointer)
f3c180ae 4000 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4001
4002 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4003 if (gotfree_input_line)
4004 free (gotfree_input_line);
252b5132 4005
2daf4fd8 4006 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4007 {
47926f60 4008 /* Missing or bad expr becomes absolute 0. */
d0b47220 4009 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4010 imm_start);
252b5132
RH		 4011 exp->X_op = O_constant;
4012 exp->X_add_number = 0;
4013 exp->X_add_symbol = (symbolS *) 0;
4014 exp->X_op_symbol = (symbolS *) 0;
252b5132 4015 }
3e73aa7c 4016 else if (exp->X_op == O_constant)
252b5132 4017 {
47926f60 4018 /* Size it properly later. */
3e73aa7c
JH		 4019 i.types[this_operand] |= Imm64;
4020 /* If BFD64, sign extend val. */
4021 if (!use_rela_relocations)
4022 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4023 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4024 }
4c63da97 4025#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4026 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4027 && exp_seg != absolute_section
47926f60 4028 && exp_seg != text_section
24eab124
AM		 4029 && exp_seg != data_section
4030 && exp_seg != bss_section
4031 && exp_seg != undefined_section
f86103b7 4032 && !bfd_is_com_section (exp_seg))
252b5132 4033 {
d0b47220 4034 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4035 return 0;
4036 }
4037#endif
4038 else
4039 {
4040 /* This is an address. The size of the address will be
24eab124 4041 determined later, depending on destination register,
3e73aa7c
JH		 4042 suffix, or the default for the section. */
4043 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4044 i.types[this_operand] &= types;
252b5132
RH		 4045 }
4046
4047 return 1;
4048}
4049
551c1ca1 4050static char *i386_scale PARAMS ((char *));
252b5132 4051
551c1ca1 4052static char *
252b5132
RH		 4053i386_scale (scale)
4054 char *scale;
4055{
551c1ca1
AM		 4056 offsetT val;
4057 char *save = input_line_pointer;
252b5132 4058
551c1ca1
AM		 4059 input_line_pointer = scale;
4060 val = get_absolute_expression ();
4061
4062 switch (val)
252b5132 4063 {
551c1ca1 4064 case 1:
252b5132
RH		 4065 i.log2_scale_factor = 0;
4066 break;
551c1ca1 4067 case 2:
252b5132
RH		 4068 i.log2_scale_factor = 1;
4069 break;
551c1ca1 4070 case 4:
252b5132
RH		 4071 i.log2_scale_factor = 2;
4072 break;
551c1ca1 4073 case 8:
252b5132
RH		 4074 i.log2_scale_factor = 3;
4075 break;
4076 default:
a724f0f4
JB		 4077 {
4078 char sep = *input_line_pointer;
4079
4080 *input_line_pointer = '\0';
4081 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4082 scale);
4083 *input_line_pointer = sep;
4084 input_line_pointer = save;
4085 return NULL;
4086 }
252b5132 4087 }
29b0f896 4088 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4089 {
4090 as_warn (_("scale factor of %d without an index register"),
24eab124 4091 1 << i.log2_scale_factor);
252b5132
RH		 4092#if SCALE1_WHEN_NO_INDEX
4093 i.log2_scale_factor = 0;
4094#endif
4095 }
551c1ca1
AM		 4096 scale = input_line_pointer;
4097 input_line_pointer = save;
4098 return scale;
252b5132
RH		 4099}
4100
4101static int i386_displacement PARAMS ((char *, char *));
4102
4103static int
4104i386_displacement (disp_start, disp_end)
4105 char *disp_start;
4106 char *disp_end;
4107{
29b0f896 4108 expressionS *exp;
252b5132
RH		 4109 segT exp_seg = 0;
4110 char *save_input_line_pointer;
f3c180ae 4111 char *gotfree_input_line;
252b5132 4112 int bigdisp = Disp32;
3956db08 4113 unsigned int types = Disp;
252b5132 4114
3e73aa7c 4115 if (flag_code == CODE_64BIT)
7ecd2f8b 4116 {
29b0f896 4117 if (i.prefix[ADDR_PREFIX] == 0)
3956db08 4118 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b
JH		 4119 }
4120 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4121 bigdisp = Disp16;
252b5132
RH		 4122 i.types[this_operand] |= bigdisp;
4123
4124 exp = &disp_expressions[i.disp_operands];
520dc8e8 4125 i.op[this_operand].disps = exp;
252b5132
RH		 4126 i.disp_operands++;
4127 save_input_line_pointer = input_line_pointer;
4128 input_line_pointer = disp_start;
4129 END_STRING_AND_SAVE (disp_end);
4130
4131#ifndef GCC_ASM_O_HACK
4132#define GCC_ASM_O_HACK 0
4133#endif
4134#if GCC_ASM_O_HACK
4135 END_STRING_AND_SAVE (disp_end + 1);
4136 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4137 && displacement_string_end[-1] == '+')
252b5132
RH		 4138 {
4139 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4140 constraint within gcc asm statements.
4141 For instance:
4142
4143 #define _set_tssldt_desc(n,addr,limit,type) \
4144 __asm__ __volatile__ ( \
4145 "movw %w2,%0\n\t" \
4146 "movw %w1,2+%0\n\t" \
4147 "rorl $16,%1\n\t" \
4148 "movb %b1,4+%0\n\t" \
4149 "movb %4,5+%0\n\t" \
4150 "movb $0,6+%0\n\t" \
4151 "movb %h1,7+%0\n\t" \
4152 "rorl $16,%1" \
4153 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4154
4155 This works great except that the output assembler ends
4156 up looking a bit weird if it turns out that there is
4157 no offset. You end up producing code that looks like:
4158
4159 #APP
4160 movw $235,(%eax)
4161 movw %dx,2+(%eax)
4162 rorl $16,%edx
4163 movb %dl,4+(%eax)
4164 movb $137,5+(%eax)
4165 movb $0,6+(%eax)
4166 movb %dh,7+(%eax)
4167 rorl $16,%edx
4168 #NO_APP
4169
47926f60 4170 So here we provide the missing zero. */
24eab124
AM		 4171
4172 *displacement_string_end = '0';
252b5132
RH		 4173 }
4174#endif
3956db08 4175 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4176 if (gotfree_input_line)
4177 input_line_pointer = gotfree_input_line;
252b5132 4178
24eab124 4179 exp_seg = expression (exp);
252b5132 4180
636c26b0
AM		 4181 SKIP_WHITESPACE ();
4182 if (*input_line_pointer)
4183 as_bad (_("junk `%s' after expression"), input_line_pointer);
4184#if GCC_ASM_O_HACK
4185 RESTORE_END_STRING (disp_end + 1);
4186#endif
4187 RESTORE_END_STRING (disp_end);
4188 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4189 if (gotfree_input_line)
4190 free (gotfree_input_line);
636c26b0 4191
24eab124
AM		 4192 /* We do this to make sure that the section symbol is in
4193 the symbol table. We will ultimately change the relocation
47926f60 4194 to be relative to the beginning of the section. */
1ae12ab7 4195 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4196 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4197 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4198 {
636c26b0
AM		 4199 if (exp->X_op != O_symbol)
4200 {
4201 as_bad (_("bad expression used with @%s"),
4202 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4203 ? "GOTPCREL"
4204 : "GOTOFF"));
4205 return 0;
4206 }
4207
e5cb08ac 4208 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4209 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4210 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4211 exp->X_op = O_subtract;
4212 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4213 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4214 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4215 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4216 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4217 else
29b0f896 4218 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4219 }
252b5132 4220
2daf4fd8
AM		 4221 if (exp->X_op == O_absent || exp->X_op == O_big)
4222 {
47926f60 4223 /* Missing or bad expr becomes absolute 0. */
d0b47220 4224 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4225 disp_start);
4226 exp->X_op = O_constant;
4227 exp->X_add_number = 0;
4228 exp->X_add_symbol = (symbolS *) 0;
4229 exp->X_op_symbol = (symbolS *) 0;
4230 }
4231
4c63da97 4232#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4233 if (exp->X_op != O_constant
45288df1 4234 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4235 && exp_seg != absolute_section
45288df1
AM		 4236 && exp_seg != text_section
4237 && exp_seg != data_section
4238 && exp_seg != bss_section
31312f95 4239 && exp_seg != undefined_section
f86103b7 4240 && !bfd_is_com_section (exp_seg))
24eab124 4241 {
d0b47220 4242 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4243 return 0;
4244 }
252b5132 4245#endif
3956db08
JB		 4246
4247 if (!(i.types[this_operand] & ~Disp))
4248 i.types[this_operand] &= types;
4249
252b5132
RH		 4250 return 1;
4251}
4252
e5cb08ac 4253static int i386_index_check PARAMS ((const char *));
252b5132 4254
eecb386c 4255/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4256 Return 1 on success, 0 on a failure. */
4257
252b5132 4258static int
eecb386c
AM		 4259i386_index_check (operand_string)
4260 const char *operand_string;
252b5132 4261{
3e73aa7c 4262 int ok;
24eab124 4263#if INFER_ADDR_PREFIX
eecb386c
AM		 4264 int fudged = 0;
4265
24eab124
AM		 4266 tryprefix:
4267#endif
3e73aa7c 4268 ok = 1;
30123838
JB		 4269 if ((current_templates->start->cpu_flags & CpuSVME)
4270 && current_templates->end[-1].operand_types[0] == AnyMem)
4271 {
4272 /* Memory operands of SVME insns are special in that they only allow
4273 rAX as their memory address and ignore any segment override. */
4274 unsigned RegXX;
4275
4276 /* SKINIT is even more restrictive: it always requires EAX. */
4277 if (strcmp (current_templates->start->name, "skinit") == 0)
4278 RegXX = Reg32;
4279 else if (flag_code == CODE_64BIT)
4280 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4281 else
4282 RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4283 ? Reg16
4284 : Reg32;
4285 if (!i.base_reg
4286 || !(i.base_reg->reg_type & Acc)
4287 || !(i.base_reg->reg_type & RegXX)
4288 || i.index_reg
4289 || (i.types[0] & Disp))
4290 ok = 0;
4291 }
4292 else if (flag_code == CODE_64BIT)
20f0a1fc
NC		 4293 {
4294 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4295
4296 if ((i.base_reg
4297 && ((i.base_reg->reg_type & RegXX) == 0)
4298 && (i.base_reg->reg_type != BaseIndex
4299 || i.index_reg))
4300 || (i.index_reg
4301 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4302 != (RegXX | BaseIndex))))
4303 ok = 0;
3e73aa7c
JH		 4304 }
4305 else
4306 {
4307 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4308 {
4309 /* 16bit checks. */
4310 if ((i.base_reg
29b0f896
AM		 4311 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4312 != (Reg16 | BaseIndex)))
3e73aa7c 4313 || (i.index_reg
29b0f896
AM		 4314 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4315 != (Reg16 | BaseIndex))
4316 || !(i.base_reg
4317 && i.base_reg->reg_num < 6
4318 && i.index_reg->reg_num >= 6
4319 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4320 ok = 0;
4321 }
4322 else
e5cb08ac 4323 {
3e73aa7c
JH		 4324 /* 32bit checks. */
4325 if ((i.base_reg
4326 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4327 || (i.index_reg
29b0f896
AM		 4328 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4329 != (Reg32 | BaseIndex))))
e5cb08ac 4330 ok = 0;
3e73aa7c
JH		 4331 }
4332 }
4333 if (!ok)
24eab124
AM		 4334 {
4335#if INFER_ADDR_PREFIX
20f0a1fc 4336 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4337 {
4338 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4339 i.prefixes += 1;
b23bac36
AM		 4340 /* Change the size of any displacement too. At most one of
4341 Disp16 or Disp32 is set.
4342 FIXME. There doesn't seem to be any real need for separate
4343 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4344 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4345 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
29b0f896 4346 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4347 fudged = 1;
24eab124
AM		 4348 goto tryprefix;
4349 }
eecb386c
AM		 4350 if (fudged)
4351 as_bad (_("`%s' is not a valid base/index expression"),
4352 operand_string);
4353 else
c388dee8 4354#endif
eecb386c
AM		 4355 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4356 operand_string,
3e73aa7c 4357 flag_code_names[flag_code]);
24eab124 4358 }
20f0a1fc 4359 return ok;
24eab124 4360}
252b5132 4361
252b5132 4362/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4363 on error. */
252b5132 4364
252b5132
RH		 4365static int
4366i386_operand (operand_string)
4367 char *operand_string;
4368{
af6bdddf
AM		 4369 const reg_entry *r;
4370 char *end_op;
24eab124 4371 char *op_string = operand_string;
252b5132 4372
24eab124 4373 if (is_space_char (*op_string))
252b5132
RH		 4374 ++op_string;
4375
24eab124 4376 /* We check for an absolute prefix (differentiating,
47926f60 4377 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4378 if (*op_string == ABSOLUTE_PREFIX)
4379 {
4380 ++op_string;
4381 if (is_space_char (*op_string))
4382 ++op_string;
4383 i.types[this_operand] |= JumpAbsolute;
4384 }
252b5132 4385
47926f60 4386 /* Check if operand is a register. */
af6bdddf
AM		 4387 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4388 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 4389 {
24eab124
AM		 4390 /* Check for a segment override by searching for ':' after a
4391 segment register. */
4392 op_string = end_op;
4393 if (is_space_char (*op_string))
4394 ++op_string;
4395 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4396 {
4397 switch (r->reg_num)
4398 {
4399 case 0:
4400 i.seg[i.mem_operands] = &es;
4401 break;
4402 case 1:
4403 i.seg[i.mem_operands] = &cs;
4404 break;
4405 case 2:
4406 i.seg[i.mem_operands] = &ss;
4407 break;
4408 case 3:
4409 i.seg[i.mem_operands] = &ds;
4410 break;
4411 case 4:
4412 i.seg[i.mem_operands] = &fs;
4413 break;
4414 case 5:
4415 i.seg[i.mem_operands] = &gs;
4416 break;
4417 }
252b5132 4418
24eab124 4419 /* Skip the ':' and whitespace. */
252b5132
RH		 4420 ++op_string;
4421 if (is_space_char (*op_string))
24eab124 4422 ++op_string;
252b5132 4423
24eab124
AM		 4424 if (!is_digit_char (*op_string)
4425 && !is_identifier_char (*op_string)
4426 && *op_string != '('
4427 && *op_string != ABSOLUTE_PREFIX)
4428 {
4429 as_bad (_("bad memory operand `%s'"), op_string);
4430 return 0;
4431 }
47926f60 4432 /* Handle case of %es:*foo. */
24eab124
AM		 4433 if (*op_string == ABSOLUTE_PREFIX)
4434 {
4435 ++op_string;
4436 if (is_space_char (*op_string))
4437 ++op_string;
4438 i.types[this_operand] |= JumpAbsolute;
4439 }
4440 goto do_memory_reference;
4441 }
4442 if (*op_string)
4443 {
d0b47220 4444 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4445 return 0;
4446 }
4447 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4448 i.op[this_operand].regs = r;
24eab124
AM		 4449 i.reg_operands++;
4450 }
af6bdddf
AM		 4451 else if (*op_string == REGISTER_PREFIX)
4452 {
4453 as_bad (_("bad register name `%s'"), op_string);
4454 return 0;
4455 }
24eab124 4456 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4457 {
24eab124
AM		 4458 ++op_string;
4459 if (i.types[this_operand] & JumpAbsolute)
4460 {
d0b47220 4461 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4462 return 0;
4463 }
4464 if (!i386_immediate (op_string))
4465 return 0;
4466 }
4467 else if (is_digit_char (*op_string)
4468 || is_identifier_char (*op_string)
e5cb08ac 4469 || *op_string == '(')
24eab124 4470 {
47926f60 4471 /* This is a memory reference of some sort. */
af6bdddf 4472 char *base_string;
252b5132 4473
47926f60 4474 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4475 char *displacement_string_start;
4476 char *displacement_string_end;
252b5132 4477
24eab124 4478 do_memory_reference:
24eab124
AM		 4479 if ((i.mem_operands == 1
4480 && (current_templates->start->opcode_modifier & IsString) == 0)
4481 || i.mem_operands == 2)
4482 {
4483 as_bad (_("too many memory references for `%s'"),
4484 current_templates->start->name);
4485 return 0;
4486 }
252b5132 4487
24eab124
AM		 4488 /* Check for base index form. We detect the base index form by
4489 looking for an ')' at the end of the operand, searching
4490 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4491 after the '('. */
af6bdddf 4492 base_string = op_string + strlen (op_string);
c3332e24 4493
af6bdddf
AM		 4494 --base_string;
4495 if (is_space_char (*base_string))
4496 --base_string;
252b5132 4497
47926f60 4498 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4499 displacement_string_start = op_string;
4500 displacement_string_end = base_string + 1;
252b5132 4501
24eab124
AM		 4502 if (*base_string == ')')
4503 {
af6bdddf 4504 char *temp_string;
24eab124
AM		 4505 unsigned int parens_balanced = 1;
4506 /* We've already checked that the number of left & right ()'s are
47926f60 4507 equal, so this loop will not be infinite. */
24eab124
AM		 4508 do
4509 {
4510 base_string--;
4511 if (*base_string == ')')
4512 parens_balanced++;
4513 if (*base_string == '(')
4514 parens_balanced--;
4515 }
4516 while (parens_balanced);
c3332e24 4517
af6bdddf 4518 temp_string = base_string;
c3332e24 4519
24eab124 4520 /* Skip past '(' and whitespace. */
252b5132
RH		 4521 ++base_string;
4522 if (is_space_char (*base_string))
24eab124 4523 ++base_string;
252b5132 4524
af6bdddf
AM		 4525 if (*base_string == ','
4526 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4527 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4528 {
af6bdddf 4529 displacement_string_end = temp_string;
252b5132 4530
af6bdddf 4531 i.types[this_operand] |= BaseIndex;
252b5132 4532
af6bdddf 4533 if (i.base_reg)
24eab124 4534 {
24eab124
AM		 4535 base_string = end_op;
4536 if (is_space_char (*base_string))
4537 ++base_string;
af6bdddf
AM		 4538 }
4539
4540 /* There may be an index reg or scale factor here. */
4541 if (*base_string == ',')
4542 {
4543 ++base_string;
4544 if (is_space_char (*base_string))
4545 ++base_string;
4546
4547 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4548 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4549 {
af6bdddf 4550 base_string = end_op;
24eab124
AM		 4551 if (is_space_char (*base_string))
4552 ++base_string;
af6bdddf
AM		 4553 if (*base_string == ',')
4554 {
4555 ++base_string;
4556 if (is_space_char (*base_string))
4557 ++base_string;
4558 }
e5cb08ac 4559 else if (*base_string != ')')
af6bdddf
AM		 4560 {
4561 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4562 operand_string);
4563 return 0;
4564 }
24eab124 4565 }
af6bdddf 4566 else if (*base_string == REGISTER_PREFIX)
24eab124 4567 {
af6bdddf 4568 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4569 return 0;
4570 }
252b5132 4571
47926f60 4572 /* Check for scale factor. */
551c1ca1 4573 if (*base_string != ')')
af6bdddf 4574 {
551c1ca1
AM		 4575 char *end_scale = i386_scale (base_string);
4576
4577 if (!end_scale)
af6bdddf 4578 return 0;
24eab124 4579
551c1ca1 4580 base_string = end_scale;
af6bdddf
AM		 4581 if (is_space_char (*base_string))
4582 ++base_string;
4583 if (*base_string != ')')
4584 {
4585 as_bad (_("expecting `)' after scale factor in `%s'"),
4586 operand_string);
4587 return 0;
4588 }
4589 }
4590 else if (!i.index_reg)
24eab124 4591 {
af6bdddf
AM		 4592 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4593 *base_string);
24eab124
AM		 4594 return 0;
4595 }
4596 }
af6bdddf 4597 else if (*base_string != ')')
24eab124 4598 {
af6bdddf
AM		 4599 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4600 operand_string);
24eab124
AM		 4601 return 0;
4602 }
c3332e24 4603 }
af6bdddf 4604 else if (*base_string == REGISTER_PREFIX)
c3332e24 4605 {
af6bdddf 4606 as_bad (_("bad register name `%s'"), base_string);
24eab124 4607 return 0;
c3332e24 4608 }
24eab124
AM		 4609 }
4610
4611 /* If there's an expression beginning the operand, parse it,
4612 assuming displacement_string_start and
4613 displacement_string_end are meaningful. */
4614 if (displacement_string_start != displacement_string_end)
4615 {
4616 if (!i386_displacement (displacement_string_start,
4617 displacement_string_end))
4618 return 0;
4619 }
4620
4621 /* Special case for (%dx) while doing input/output op. */
4622 if (i.base_reg
4623 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4624 && i.index_reg == 0
4625 && i.log2_scale_factor == 0
4626 && i.seg[i.mem_operands] == 0
4627 && (i.types[this_operand] & Disp) == 0)
4628 {
4629 i.types[this_operand] = InOutPortReg;
4630 return 1;
4631 }
4632
eecb386c
AM		 4633 if (i386_index_check (operand_string) == 0)
4634 return 0;
24eab124
AM		 4635 i.mem_operands++;
4636 }
4637 else
ce8a8b2f
AM		 4638 {
4639 /* It's not a memory operand; argh! */
24eab124
AM		 4640 as_bad (_("invalid char %s beginning operand %d `%s'"),
4641 output_invalid (*op_string),
4642 this_operand + 1,
4643 op_string);
4644 return 0;
4645 }
47926f60 4646 return 1; /* Normal return. */
252b5132
RH		 4647}
4648\f
ee7fcc42
AM		 4649/* md_estimate_size_before_relax()
4650
4651 Called just before relax() for rs_machine_dependent frags. The x86
4652 assembler uses these frags to handle variable size jump
4653 instructions.
4654
4655 Any symbol that is now undefined will not become defined.
4656 Return the correct fr_subtype in the frag.
4657 Return the initial "guess for variable size of frag" to caller.
4658 The guess is actually the growth beyond the fixed part. Whatever
4659 we do to grow the fixed or variable part contributes to our
4660 returned value. */
4661
252b5132
RH		 4662int
4663md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4664 fragS *fragP;
4665 segT segment;
252b5132 4666{
252b5132 4667 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4668 check for un-relaxable symbols. On an ELF system, we can't relax
4669 an externally visible symbol, because it may be overridden by a
4670 shared library. */
4671 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4672#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4673 || (IS_ELF
31312f95
AM		 4674 && (S_IS_EXTERNAL (fragP->fr_symbol)
4675 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4676#endif
4677 )
252b5132 4678 {
b98ef147
AM		 4679 /* Symbol is undefined in this segment, or we need to keep a
4680 reloc so that weak symbols can be overridden. */
4681 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 4682 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 4683 unsigned char *opcode;
4684 int old_fr_fix;
f6af82bd 4685
ee7fcc42
AM		 4686 if (fragP->fr_var != NO_RELOC)
4687 reloc_type = fragP->fr_var;
b98ef147 4688 else if (size == 2)
f6af82bd
AM		 4689 reloc_type = BFD_RELOC_16_PCREL;
4690 else
4691 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4692
ee7fcc42
AM		 4693 old_fr_fix = fragP->fr_fix;
4694 opcode = (unsigned char *) fragP->fr_opcode;
4695
fddf5b5b 4696 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4697 {
fddf5b5b
AM		 4698 case UNCOND_JUMP:
4699 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4700 opcode[0] = 0xe9;
252b5132 4701 fragP->fr_fix += size;
062cd5e7
AS		 4702 fix_new (fragP, old_fr_fix, size,
4703 fragP->fr_symbol,
4704 fragP->fr_offset, 1,
4705 reloc_type);
252b5132
RH		 4706 break;
4707
fddf5b5b 4708 case COND_JUMP86:
412167cb
AM		 4709 if (size == 2
4710 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4711 {
4712 /* Negate the condition, and branch past an
4713 unconditional jump. */
4714 opcode[0] ^= 1;
4715 opcode[1] = 3;
4716 /* Insert an unconditional jump. */
4717 opcode[2] = 0xe9;
4718 /* We added two extra opcode bytes, and have a two byte
4719 offset. */
4720 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4721 fix_new (fragP, old_fr_fix + 2, 2,
4722 fragP->fr_symbol,
4723 fragP->fr_offset, 1,
4724 reloc_type);
fddf5b5b
AM		 4725 break;
4726 }
4727 /* Fall through. */
4728
4729 case COND_JUMP:
412167cb
AM		 4730 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4731 {
3e02c1cc
AM		 4732 fixS *fixP;
4733
412167cb 4734 fragP->fr_fix += 1;
3e02c1cc
AM		 4735 fixP = fix_new (fragP, old_fr_fix, 1,
4736 fragP->fr_symbol,
4737 fragP->fr_offset, 1,
4738 BFD_RELOC_8_PCREL);
4739 fixP->fx_signed = 1;
412167cb
AM		 4740 break;
4741 }
93c2a809 4742
24eab124 4743 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4744 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4745 opcode[1] = opcode[0] + 0x10;
f6af82bd 4746 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4747 /* We've added an opcode byte. */
4748 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4749 fix_new (fragP, old_fr_fix + 1, size,
4750 fragP->fr_symbol,
4751 fragP->fr_offset, 1,
4752 reloc_type);
252b5132 4753 break;
fddf5b5b
AM		 4754
4755 default:
4756 BAD_CASE (fragP->fr_subtype);
4757 break;
252b5132
RH		 4758 }
4759 frag_wane (fragP);
ee7fcc42 4760 return fragP->fr_fix - old_fr_fix;
252b5132 4761 }
93c2a809 4762
93c2a809
AM		 4763 /* Guess size depending on current relax state. Initially the relax
4764 state will correspond to a short jump and we return 1, because
4765 the variable part of the frag (the branch offset) is one byte
4766 long. However, we can relax a section more than once and in that
4767 case we must either set fr_subtype back to the unrelaxed state,
4768 or return the value for the appropriate branch. */
4769 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4770}
4771
47926f60
KH		 4772/* Called after relax() is finished.
4773
4774 In: Address of frag.
4775 fr_type == rs_machine_dependent.
4776 fr_subtype is what the address relaxed to.
4777
4778 Out: Any fixSs and constants are set up.
4779 Caller will turn frag into a ".space 0". */
4780
252b5132
RH		 4781void
4782md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4783 bfd *abfd ATTRIBUTE_UNUSED;
4784 segT sec ATTRIBUTE_UNUSED;
29b0f896 4785 fragS *fragP;
252b5132 4786{
29b0f896 4787 unsigned char *opcode;
252b5132 4788 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4789 offsetT target_address;
4790 offsetT opcode_address;
252b5132 4791 unsigned int extension = 0;
847f7ad4 4792 offsetT displacement_from_opcode_start;
252b5132
RH		 4793
4794 opcode = (unsigned char *) fragP->fr_opcode;
4795
47926f60 4796 /* Address we want to reach in file space. */
252b5132 4797 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4798
47926f60 4799 /* Address opcode resides at in file space. */
252b5132
RH		 4800 opcode_address = fragP->fr_address + fragP->fr_fix;
4801
47926f60 4802 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4803 displacement_from_opcode_start = target_address - opcode_address;
4804
fddf5b5b 4805 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4806 {
47926f60
KH		 4807 /* Don't have to change opcode. */
4808 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4809 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4810 }
4811 else
4812 {
4813 if (no_cond_jump_promotion
4814 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4815 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4816
fddf5b5b
AM		 4817 switch (fragP->fr_subtype)
4818 {
4819 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4820 extension = 4; /* 1 opcode + 4 displacement */
4821 opcode[0] = 0xe9;
4822 where_to_put_displacement = &opcode[1];
4823 break;
252b5132 4824
fddf5b5b
AM		 4825 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4826 extension = 2; /* 1 opcode + 2 displacement */
4827 opcode[0] = 0xe9;
4828 where_to_put_displacement = &opcode[1];
4829 break;
252b5132 4830
fddf5b5b
AM		 4831 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4832 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4833 extension = 5; /* 2 opcode + 4 displacement */
4834 opcode[1] = opcode[0] + 0x10;
4835 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4836 where_to_put_displacement = &opcode[2];
4837 break;
252b5132 4838
fddf5b5b
AM		 4839 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4840 extension = 3; /* 2 opcode + 2 displacement */
4841 opcode[1] = opcode[0] + 0x10;
4842 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4843 where_to_put_displacement = &opcode[2];
4844 break;
252b5132 4845
fddf5b5b
AM		 4846 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4847 extension = 4;
4848 opcode[0] ^= 1;
4849 opcode[1] = 3;
4850 opcode[2] = 0xe9;
4851 where_to_put_displacement = &opcode[3];
4852 break;
4853
4854 default:
4855 BAD_CASE (fragP->fr_subtype);
4856 break;
4857 }
252b5132 4858 }
fddf5b5b 4859
47926f60 4860 /* Now put displacement after opcode. */
252b5132
RH		 4861 md_number_to_chars ((char *) where_to_put_displacement,
4862 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4863 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4864 fragP->fr_fix += extension;
4865}
4866\f
47926f60
KH		 4867/* Size of byte displacement jmp. */
4868int md_short_jump_size = 2;
4869
4870/* Size of dword displacement jmp. */
4871int md_long_jump_size = 5;
252b5132 4872
252b5132
RH		 4873void
4874md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4875 char *ptr;
4876 addressT from_addr, to_addr;
ab9da554
ILT		 4877 fragS *frag ATTRIBUTE_UNUSED;
4878 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4879{
847f7ad4 4880 offsetT offset;
252b5132
RH		 4881
4882 offset = to_addr - (from_addr + 2);
47926f60
KH		 4883 /* Opcode for byte-disp jump. */
4884 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4885 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4886}
4887
4888void
4889md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4890 char *ptr;
4891 addressT from_addr, to_addr;
a38cf1db
AM		 4892 fragS *frag ATTRIBUTE_UNUSED;
4893 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4894{
847f7ad4 4895 offsetT offset;
252b5132 4896
a38cf1db
AM		 4897 offset = to_addr - (from_addr + 5);
4898 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4899 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4900}
4901\f
4902/* Apply a fixup (fixS) to segment data, once it has been determined
4903 by our caller that we have all the info we need to fix it up.
4904
4905 On the 386, immediates, displacements, and data pointers are all in
4906 the same (little-endian) format, so we don't need to care about which
4907 we are handling. */
4908
94f592af 4909void
55cf6793 4910md_apply_fix (fixP, valP, seg)
47926f60
KH		 4911 /* The fix we're to put in. */
4912 fixS *fixP;
47926f60 4913 /* Pointer to the value of the bits. */
c6682705 4914 valueT *valP;
47926f60
KH		 4915 /* Segment fix is from. */
4916 segT seg ATTRIBUTE_UNUSED;
252b5132 4917{
94f592af 4918 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4919 valueT value = *valP;
252b5132 4920
f86103b7 4921#if !defined (TE_Mach)
93382f6d
AM		 4922 if (fixP->fx_pcrel)
4923 {
4924 switch (fixP->fx_r_type)
4925 {
5865bb77
ILT		 4926 default:
4927 break;
4928
d6ab8113
JB		 4929 case BFD_RELOC_64:
4930 fixP->fx_r_type = BFD_RELOC_64_PCREL;
4931 break;
93382f6d 4932 case BFD_RELOC_32:
ae8887b5 4933 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 4934 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4935 break;
4936 case BFD_RELOC_16:
4937 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4938 break;
4939 case BFD_RELOC_8:
4940 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4941 break;
4942 }
4943 }
252b5132 4944
a161fe53 4945 if (fixP->fx_addsy != NULL
31312f95 4946 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 4947 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 4948 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4949 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4950 && !use_rela_relocations)
252b5132 4951 {
31312f95
AM		 4952 /* This is a hack. There should be a better way to handle this.
4953 This covers for the fact that bfd_install_relocation will
4954 subtract the current location (for partial_inplace, PC relative
4955 relocations); see more below. */
252b5132 4956#ifndef OBJ_AOUT
718ddfc0 4957 if (IS_ELF
252b5132
RH		 4958#ifdef TE_PE
4959 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4960#endif
4961 )
4962 value += fixP->fx_where + fixP->fx_frag->fr_address;
4963#endif
4964#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4965 if (IS_ELF)
252b5132 4966 {
6539b54b 4967 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 4968
6539b54b 4969 if ((sym_seg == seg
2f66722d 4970 || (symbol_section_p (fixP->fx_addsy)
6539b54b 4971 && sym_seg != absolute_section))
ae6063d4 4972 && !generic_force_reloc (fixP))
2f66722d
AM		 4973 {
4974 /* Yes, we add the values in twice. This is because
6539b54b
AM		 4975 bfd_install_relocation subtracts them out again. I think
4976 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 4977 it. FIXME. */
4978 value += fixP->fx_where + fixP->fx_frag->fr_address;
4979 }
252b5132
RH		 4980 }
4981#endif
4982#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 4983 /* For some reason, the PE format does not store a
4984 section address offset for a PC relative symbol. */
4985 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 4986 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 4987 value += md_pcrel_from (fixP);
4988#endif
4989 }
4990
4991 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 4992 and we must not disappoint it. */
252b5132 4993#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4994 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 4995 switch (fixP->fx_r_type)
4996 {
4997 case BFD_RELOC_386_PLT32:
3e73aa7c 4998 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4999 /* Make the jump instruction point to the address of the operand. At
5000 runtime we merely add the offset to the actual PLT entry. */
5001 value = -4;
5002 break;
31312f95 5003
13ae64f3
JJ		 5004 case BFD_RELOC_386_TLS_GD:
5005 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5006 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5007 case BFD_RELOC_386_TLS_IE:
5008 case BFD_RELOC_386_TLS_GOTIE:
bffbf940
JJ		 5009 case BFD_RELOC_X86_64_TLSGD:
5010 case BFD_RELOC_X86_64_TLSLD:
5011 case BFD_RELOC_X86_64_GOTTPOFF:
00f7efb6
JJ		 5012 value = 0; /* Fully resolved at runtime. No addend. */
5013 /* Fallthrough */
5014 case BFD_RELOC_386_TLS_LE:
5015 case BFD_RELOC_386_TLS_LDO_32:
5016 case BFD_RELOC_386_TLS_LE_32:
5017 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5018 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5019 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5020 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5021 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5022 break;
5023
5024 case BFD_RELOC_386_GOT32:
5025 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5026 value = 0; /* Fully resolved at runtime. No addend. */
5027 break;
47926f60
KH		 5028
5029 case BFD_RELOC_VTABLE_INHERIT:
5030 case BFD_RELOC_VTABLE_ENTRY:
5031 fixP->fx_done = 0;
94f592af 5032 return;
47926f60
KH		 5033
5034 default:
5035 break;
5036 }
5037#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5038 *valP = value;
f86103b7 5039#endif /* !defined (TE_Mach) */
3e73aa7c 5040
3e73aa7c 5041 /* Are we finished with this relocation now? */
c6682705 5042 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5043 fixP->fx_done = 1;
5044 else if (use_rela_relocations)
5045 {
5046 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5047 /* Remember value for tc_gen_reloc. */
5048 fixP->fx_addnumber = value;
3e73aa7c
JH		 5049 value = 0;
5050 }
f86103b7 5051
94f592af 5052 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5053}
252b5132 5054\f
252b5132
RH		 5055#define MAX_LITTLENUMS 6
5056
47926f60
KH		 5057/* Turn the string pointed to by litP into a floating point constant
5058 of type TYPE, and emit the appropriate bytes. The number of
5059 LITTLENUMS emitted is stored in *SIZEP. An error message is
5060 returned, or NULL on OK. */
5061
252b5132
RH		 5062char *
5063md_atof (type, litP, sizeP)
2ab9b79e 5064 int type;
252b5132
RH		 5065 char *litP;
5066 int *sizeP;
5067{
5068 int prec;
5069 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5070 LITTLENUM_TYPE *wordP;
5071 char *t;
5072
5073 switch (type)
5074 {
5075 case 'f':
5076 case 'F':
5077 prec = 2;
5078 break;
5079
5080 case 'd':
5081 case 'D':
5082 prec = 4;
5083 break;
5084
5085 case 'x':
5086 case 'X':
5087 prec = 5;
5088 break;
5089
5090 default:
5091 *sizeP = 0;
5092 return _("Bad call to md_atof ()");
5093 }
5094 t = atof_ieee (input_line_pointer, type, words);
5095 if (t)
5096 input_line_pointer = t;
5097
5098 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5099 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5100 the bigendian 386. */
5101 for (wordP = words + prec - 1; prec--;)
5102 {
5103 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5104 litP += sizeof (LITTLENUM_TYPE);
5105 }
5106 return 0;
5107}
5108\f
87c245cc 5109static char output_invalid_buf[8];
252b5132 5110
252b5132
RH		 5111static char *
5112output_invalid (c)
5113 int c;
5114{
3882b010 5115 if (ISPRINT (c))
252b5132
RH		 5116 sprintf (output_invalid_buf, "'%c'", c);
5117 else
5118 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
5119 return output_invalid_buf;
5120}
5121
af6bdddf 5122/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5123
5124static const reg_entry *
5125parse_register (reg_string, end_op)
5126 char *reg_string;
5127 char **end_op;
5128{
af6bdddf
AM		 5129 char *s = reg_string;
5130 char *p;
252b5132
RH		 5131 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5132 const reg_entry *r;
5133
5134 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5135 if (*s == REGISTER_PREFIX)
5136 ++s;
5137
5138 if (is_space_char (*s))
5139 ++s;
5140
5141 p = reg_name_given;
af6bdddf 5142 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5143 {
5144 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5145 return (const reg_entry *) NULL;
5146 s++;
252b5132
RH		 5147 }
5148
6588847e
DN		 5149 /* For naked regs, make sure that we are not dealing with an identifier.
5150 This prevents confusing an identifier like `eax_var' with register
5151 `eax'. */
5152 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5153 return (const reg_entry *) NULL;
5154
af6bdddf 5155 *end_op = s;
252b5132
RH		 5156
5157 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5158
5f47d35b 5159 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5160 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5161 {
5f47d35b
AM		 5162 if (is_space_char (*s))
5163 ++s;
5164 if (*s == '(')
5165 {
af6bdddf 5166 ++s;
5f47d35b
AM		 5167 if (is_space_char (*s))
5168 ++s;
5169 if (*s >= '0' && *s <= '7')
5170 {
5171 r = &i386_float_regtab[*s - '0'];
af6bdddf 5172 ++s;
5f47d35b
AM		 5173 if (is_space_char (*s))
5174 ++s;
5175 if (*s == ')')
5176 {
5177 *end_op = s + 1;
5178 return r;
5179 }
5f47d35b 5180 }
47926f60 5181 /* We have "%st(" then garbage. */
5f47d35b
AM		 5182 return (const reg_entry *) NULL;
5183 }
5184 }
5185
1ae00879 5186 if (r != NULL
20f0a1fc 5187 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5188 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5189 && flag_code != CODE_64BIT)
20f0a1fc 5190 return (const reg_entry *) NULL;
1ae00879 5191
252b5132
RH		 5192 return r;
5193}
5194\f
4cc782b5 5195#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5196const char *md_shortopts = "kVQ:sqn";
252b5132 5197#else
12b55ccc 5198const char *md_shortopts = "qn";
252b5132 5199#endif
6e0b89ee 5200
252b5132 5201struct option md_longopts[] = {
3e73aa7c
JH		 5202#define OPTION_32 (OPTION_MD_BASE + 0)
5203 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 5204#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 5205#define OPTION_64 (OPTION_MD_BASE + 1)
5206 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5207#endif
252b5132
RH		 5208 {NULL, no_argument, NULL, 0}
5209};
5210size_t md_longopts_size = sizeof (md_longopts);
5211
5212int
5213md_parse_option (c, arg)
5214 int c;
ab9da554 5215 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 5216{
5217 switch (c)
5218 {
12b55ccc
L		 5219 case 'n':
5220 optimize_align_code = 0;
5221 break;
5222
a38cf1db
AM		 5223 case 'q':
5224 quiet_warnings = 1;
252b5132
RH		 5225 break;
5226
5227#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5228 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5229 should be emitted or not. FIXME: Not implemented. */
5230 case 'Q':
252b5132
RH		 5231 break;
5232
5233 /* -V: SVR4 argument to print version ID. */
5234 case 'V':
5235 print_version_id ();
5236 break;
5237
a38cf1db
AM		 5238 /* -k: Ignore for FreeBSD compatibility. */
5239 case 'k':
252b5132 5240 break;
4cc782b5
ILT		 5241
5242 case 's':
5243 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5244 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5245 break;
6e0b89ee 5246
3e73aa7c
JH		 5247 case OPTION_64:
5248 {
5249 const char **list, **l;
5250
3e73aa7c
JH		 5251 list = bfd_target_list ();
5252 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 5253 if (strcmp (*l, "elf64-x86-64") == 0)
5254 {
5255 default_arch = "x86_64";
5256 break;
5257 }
3e73aa7c 5258 if (*l == NULL)
6e0b89ee 5259 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5260 free (list);
5261 }
5262 break;
5263#endif
252b5132 5264
6e0b89ee
AM		 5265 case OPTION_32:
5266 default_arch = "i386";
5267 break;
5268
252b5132
RH		 5269 default:
5270 return 0;
5271 }
5272 return 1;
5273}
5274
5275void
5276md_show_usage (stream)
5277 FILE *stream;
5278{
4cc782b5
ILT		 5279#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5280 fprintf (stream, _("\
a38cf1db
AM		 5281 -Q ignored\n\
5282 -V print assembler version number\n\
5283 -k ignored\n\
12b55ccc 5284 -n Do not optimize code alignment\n\
a38cf1db
AM		 5285 -q quieten some warnings\n\
5286 -s ignored\n"));
5287#else
5288 fprintf (stream, _("\
12b55ccc 5289 -n Do not optimize code alignment\n\
a38cf1db 5290 -q quieten some warnings\n"));
4cc782b5 5291#endif
252b5132
RH		 5292}
5293
3e73aa7c
JH		 5294#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5295 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5296
5297/* Pick the target format to use. */
5298
47926f60 5299const char *
252b5132
RH		 5300i386_target_format ()
5301{
3e73aa7c
JH		 5302 if (!strcmp (default_arch, "x86_64"))
5303 set_code_flag (CODE_64BIT);
5304 else if (!strcmp (default_arch, "i386"))
5305 set_code_flag (CODE_32BIT);
5306 else
5307 as_fatal (_("Unknown architecture"));
252b5132
RH		 5308 switch (OUTPUT_FLAVOR)
5309 {
4c63da97
AM		 5310#ifdef OBJ_MAYBE_AOUT
5311 case bfd_target_aout_flavour:
47926f60 5312 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5313#endif
5314#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5315 case bfd_target_coff_flavour:
5316 return "coff-i386";
4c63da97 5317#endif
3e73aa7c 5318#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5319 case bfd_target_elf_flavour:
3e73aa7c 5320 {
e5cb08ac 5321 if (flag_code == CODE_64BIT)
4fa24527
JB		 5322 {
5323 object_64bit = 1;
5324 use_rela_relocations = 1;
5325 }
4ada7262 5326 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5327 }
4c63da97 5328#endif
252b5132
RH		 5329 default:
5330 abort ();
5331 return NULL;
5332 }
5333}
5334
47926f60 5335#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5336
5337#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5338void i386_elf_emit_arch_note ()
5339{
718ddfc0 5340 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 5341 {
5342 char *p;
5343 asection *seg = now_seg;
5344 subsegT subseg = now_subseg;
5345 Elf_Internal_Note i_note;
5346 Elf_External_Note e_note;
5347 asection *note_secp;
5348 int len;
5349
5350 /* Create the .note section. */
5351 note_secp = subseg_new (".note", 0);
5352 bfd_set_section_flags (stdoutput,
5353 note_secp,
5354 SEC_HAS_CONTENTS | SEC_READONLY);
5355
5356 /* Process the arch string. */
5357 len = strlen (cpu_arch_name);
5358
5359 i_note.namesz = len + 1;
5360 i_note.descsz = 0;
5361 i_note.type = NT_ARCH;
5362 p = frag_more (sizeof (e_note.namesz));
5363 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5364 p = frag_more (sizeof (e_note.descsz));
5365 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5366 p = frag_more (sizeof (e_note.type));
5367 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5368 p = frag_more (len + 1);
5369 strcpy (p, cpu_arch_name);
5370
5371 frag_align (2, 0, 0);
5372
5373 subseg_set (seg, subseg);
5374 }
5375}
5376#endif
252b5132 5377\f
252b5132
RH		 5378symbolS *
5379md_undefined_symbol (name)
5380 char *name;
5381{
18dc2407
ILT		 5382 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5383 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5384 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5385 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5386 {
5387 if (!GOT_symbol)
5388 {
5389 if (symbol_find (name))
5390 as_bad (_("GOT already in symbol table"));
5391 GOT_symbol = symbol_new (name, undefined_section,
5392 (valueT) 0, &zero_address_frag);
5393 };
5394 return GOT_symbol;
5395 }
252b5132
RH		 5396 return 0;
5397}
5398
5399/* Round up a section size to the appropriate boundary. */
47926f60 5400
252b5132
RH		 5401valueT
5402md_section_align (segment, size)
ab9da554 5403 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5404 valueT size;
5405{
4c63da97
AM		 5406#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5407 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5408 {
5409 /* For a.out, force the section size to be aligned. If we don't do
5410 this, BFD will align it for us, but it will not write out the
5411 final bytes of the section. This may be a bug in BFD, but it is
5412 easier to fix it here since that is how the other a.out targets
5413 work. */
5414 int align;
5415
5416 align = bfd_get_section_alignment (stdoutput, segment);
5417 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5418 }
252b5132
RH		 5419#endif
5420
5421 return size;
5422}
5423
5424/* On the i386, PC-relative offsets are relative to the start of the
5425 next instruction. That is, the address of the offset, plus its
5426 size, since the offset is always the last part of the insn. */
5427
5428long
5429md_pcrel_from (fixP)
5430 fixS *fixP;
5431{
5432 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5433}
5434
5435#ifndef I386COFF
5436
5437static void
5438s_bss (ignore)
ab9da554 5439 int ignore ATTRIBUTE_UNUSED;
252b5132 5440{
29b0f896 5441 int temp;
252b5132 5442
8a75718c
JB		 5443#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5444 if (IS_ELF)
5445 obj_elf_section_change_hook ();
5446#endif
252b5132
RH		 5447 temp = get_absolute_expression ();
5448 subseg_set (bss_section, (subsegT) temp);
5449 demand_empty_rest_of_line ();
5450}
5451
5452#endif
5453
252b5132
RH		 5454void
5455i386_validate_fix (fixp)
5456 fixS *fixp;
5457{
5458 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5459 {
23df1078
JH		 5460 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5461 {
4fa24527 5462 if (!object_64bit)
23df1078
JH		 5463 abort ();
5464 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5465 }
5466 else
5467 {
4fa24527 5468 if (!object_64bit)
d6ab8113
JB		 5469 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5470 else
5471 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 5472 }
252b5132
RH		 5473 fixp->fx_subsy = 0;
5474 }
5475}
5476
252b5132
RH		 5477arelent *
5478tc_gen_reloc (section, fixp)
ab9da554 5479 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5480 fixS *fixp;
5481{
5482 arelent *rel;
5483 bfd_reloc_code_real_type code;
5484
5485 switch (fixp->fx_r_type)
5486 {
3e73aa7c
JH		 5487 case BFD_RELOC_X86_64_PLT32:
5488 case BFD_RELOC_X86_64_GOT32:
5489 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5490 case BFD_RELOC_386_PLT32:
5491 case BFD_RELOC_386_GOT32:
5492 case BFD_RELOC_386_GOTOFF:
5493 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5494 case BFD_RELOC_386_TLS_GD:
5495 case BFD_RELOC_386_TLS_LDM:
5496 case BFD_RELOC_386_TLS_LDO_32:
5497 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5498 case BFD_RELOC_386_TLS_IE:
5499 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5500 case BFD_RELOC_386_TLS_LE_32:
5501 case BFD_RELOC_386_TLS_LE:
bffbf940
JJ		 5502 case BFD_RELOC_X86_64_TLSGD:
5503 case BFD_RELOC_X86_64_TLSLD:
5504 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5505 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 5506 case BFD_RELOC_X86_64_GOTTPOFF:
5507 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 5508 case BFD_RELOC_X86_64_TPOFF64:
5509 case BFD_RELOC_X86_64_GOTOFF64:
5510 case BFD_RELOC_X86_64_GOTPC32:
252b5132
RH		 5511 case BFD_RELOC_RVA:
5512 case BFD_RELOC_VTABLE_ENTRY:
5513 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 5514#ifdef TE_PE
5515 case BFD_RELOC_32_SECREL:
5516#endif
252b5132
RH		 5517 code = fixp->fx_r_type;
5518 break;
dbbaec26
L		 5519 case BFD_RELOC_X86_64_32S:
5520 if (!fixp->fx_pcrel)
5521 {
5522 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5523 code = fixp->fx_r_type;
5524 break;
5525 }
252b5132 5526 default:
93382f6d 5527 if (fixp->fx_pcrel)
252b5132 5528 {
93382f6d
AM		 5529 switch (fixp->fx_size)
5530 {
5531 default:
b091f402
AM		 5532 as_bad_where (fixp->fx_file, fixp->fx_line,
5533 _("can not do %d byte pc-relative relocation"),
5534 fixp->fx_size);
93382f6d
AM		 5535 code = BFD_RELOC_32_PCREL;
5536 break;
5537 case 1: code = BFD_RELOC_8_PCREL; break;
5538 case 2: code = BFD_RELOC_16_PCREL; break;
5539 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 5540#ifdef BFD64
5541 case 8: code = BFD_RELOC_64_PCREL; break;
5542#endif
93382f6d
AM		 5543 }
5544 }
5545 else
5546 {
5547 switch (fixp->fx_size)
5548 {
5549 default:
b091f402
AM		 5550 as_bad_where (fixp->fx_file, fixp->fx_line,
5551 _("can not do %d byte relocation"),
5552 fixp->fx_size);
93382f6d
AM		 5553 code = BFD_RELOC_32;
5554 break;
5555 case 1: code = BFD_RELOC_8; break;
5556 case 2: code = BFD_RELOC_16; break;
5557 case 4: code = BFD_RELOC_32; break;
937149dd 5558#ifdef BFD64
3e73aa7c 5559 case 8: code = BFD_RELOC_64; break;
937149dd 5560#endif
93382f6d 5561 }
252b5132
RH		 5562 }
5563 break;
5564 }
252b5132 5565
d6ab8113 5566 if ((code == BFD_RELOC_32 || code == BFD_RELOC_32_PCREL)
252b5132
RH		 5567 && GOT_symbol
5568 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 5569 {
4fa24527 5570 if (!object_64bit)
d6ab8113
JB		 5571 code = BFD_RELOC_386_GOTPC;
5572 else
5573 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 5574 }
252b5132
RH		 5575
5576 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5577 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5578 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5579
5580 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 5581
3e73aa7c
JH		 5582 if (!use_rela_relocations)
5583 {
5584 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5585 vtable entry to be used in the relocation's section offset. */
5586 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5587 rel->address = fixp->fx_offset;
252b5132 5588
c6682705 5589 rel->addend = 0;
3e73aa7c
JH		 5590 }
5591 /* Use the rela in 64bit mode. */
252b5132 5592 else
3e73aa7c 5593 {
062cd5e7
AS		 5594 if (!fixp->fx_pcrel)
5595 rel->addend = fixp->fx_offset;
5596 else
5597 switch (code)
5598 {
5599 case BFD_RELOC_X86_64_PLT32:
5600 case BFD_RELOC_X86_64_GOT32:
5601 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5602 case BFD_RELOC_X86_64_TLSGD:
5603 case BFD_RELOC_X86_64_TLSLD:
5604 case BFD_RELOC_X86_64_GOTTPOFF:
062cd5e7
AS		 5605 rel->addend = fixp->fx_offset - fixp->fx_size;
5606 break;
5607 default:
5608 rel->addend = (section->vma
5609 - fixp->fx_size
5610 + fixp->fx_addnumber
5611 + md_pcrel_from (fixp));
5612 break;
5613 }
3e73aa7c
JH		 5614 }
5615
252b5132
RH		 5616 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5617 if (rel->howto == NULL)
5618 {
5619 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5620 _("cannot represent relocation type %s"),
252b5132
RH		 5621 bfd_get_reloc_code_name (code));
5622 /* Set howto to a garbage value so that we can keep going. */
5623 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5624 assert (rel->howto != NULL);
5625 }
5626
5627 return rel;
5628}
5629
64a0c779
DN		 5630\f
5631/* Parse operands using Intel syntax. This implements a recursive descent
5632 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5633 Programmer's Guide.
5634
5635 FIXME: We do not recognize the full operand grammar defined in the MASM
5636 documentation. In particular, all the structure/union and
5637 high-level macro operands are missing.
5638
5639 Uppercase words are terminals, lower case words are non-terminals.
5640 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5641 bars '|' denote choices. Most grammar productions are implemented in
5642 functions called 'intel_<production>'.
5643
5644 Initial production is 'expr'.
5645
9306ca4a 5646 addOp + | -
64a0c779
DN		 5647
5648 alpha [a-zA-Z]
5649
9306ca4a
JB		 5650 binOp & | AND | \| | OR | ^ | XOR
5651
64a0c779
DN		 5652 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5653
5654 constant digits [[ radixOverride ]]
5655
9306ca4a 5656 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 5657
5658 digits decdigit
b77a7acd
AJ		 5659 | digits decdigit
5660 | digits hexdigit
64a0c779
DN		 5661
5662 decdigit [0-9]
5663
9306ca4a
JB		 5664 e04 e04 addOp e05
5665 | e05
5666
5667 e05 e05 binOp e06
b77a7acd 5668 | e06
64a0c779
DN		 5669
5670 e06 e06 mulOp e09
b77a7acd 5671 | e09
64a0c779
DN		 5672
5673 e09 OFFSET e10
a724f0f4
JB		 5674 | SHORT e10
5675 | + e10
5676 | - e10
9306ca4a
JB		 5677 | ~ e10
5678 | NOT e10
64a0c779
DN		 5679 | e09 PTR e10
5680 | e09 : e10
5681 | e10
5682
5683 e10 e10 [ expr ]
b77a7acd 5684 | e11
64a0c779
DN		 5685
5686 e11 ( expr )
b77a7acd 5687 | [ expr ]
64a0c779
DN		 5688 | constant
5689 | dataType
5690 | id
5691 | $
5692 | register
5693
a724f0f4 5694 => expr expr cmpOp e04
9306ca4a 5695 | e04
64a0c779
DN		 5696
5697 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5698 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5699
5700 hexdigit a | b | c | d | e | f
b77a7acd 5701 | A | B | C | D | E | F
64a0c779
DN		 5702
5703 id alpha
b77a7acd 5704 | id alpha
64a0c779
DN		 5705 | id decdigit
5706
9306ca4a 5707 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 5708
5709 quote " | '
5710
5711 register specialRegister
b77a7acd 5712 | gpRegister
64a0c779
DN		 5713 | byteRegister
5714
5715 segmentRegister CS | DS | ES | FS | GS | SS
5716
9306ca4a 5717 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 5718 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5719 | TR3 | TR4 | TR5 | TR6 | TR7
5720
64a0c779
DN		 5721 We simplify the grammar in obvious places (e.g., register parsing is
5722 done by calling parse_register) and eliminate immediate left recursion
5723 to implement a recursive-descent parser.
5724
a724f0f4
JB		 5725 expr e04 expr'
5726
5727 expr' cmpOp e04 expr'
5728 | Empty
9306ca4a
JB		 5729
5730 e04 e05 e04'
5731
5732 e04' addOp e05 e04'
5733 | Empty
64a0c779
DN		 5734
5735 e05 e06 e05'
5736
9306ca4a 5737 e05' binOp e06 e05'
b77a7acd 5738 | Empty
64a0c779
DN		 5739
5740 e06 e09 e06'
5741
5742 e06' mulOp e09 e06'
b77a7acd 5743 | Empty
64a0c779
DN		 5744
5745 e09 OFFSET e10 e09'
a724f0f4
JB		 5746 | SHORT e10'
5747 | + e10'
5748 | - e10'
5749 | ~ e10'
5750 | NOT e10'
b77a7acd 5751 | e10 e09'
64a0c779
DN		 5752
5753 e09' PTR e10 e09'
b77a7acd 5754 | : e10 e09'
64a0c779
DN		 5755 | Empty
5756
5757 e10 e11 e10'
5758
5759 e10' [ expr ] e10'
b77a7acd 5760 | Empty
64a0c779
DN		 5761
5762 e11 ( expr )
b77a7acd 5763 | [ expr ]
64a0c779
DN		 5764 | BYTE
5765 | WORD
5766 | DWORD
9306ca4a 5767 | FWORD
64a0c779 5768 | QWORD
9306ca4a
JB		 5769 | TBYTE
5770 | OWORD
5771 | XMMWORD
64a0c779
DN		 5772 | .
5773 | $
5774 | register
5775 | id
5776 | constant */
5777
5778/* Parsing structure for the intel syntax parser. Used to implement the
5779 semantic actions for the operand grammar. */
5780struct intel_parser_s
5781 {
5782 char *op_string; /* The string being parsed. */
5783 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5784 int op_modifier; /* Operand modifier. */
64a0c779 5785 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 5786 int in_offset; /* >=1 if parsing operand of offset. */
5787 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 5788 const reg_entry *reg; /* Last register reference found. */
5789 char *disp; /* Displacement string being built. */
a724f0f4 5790 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 5791 };
5792
5793static struct intel_parser_s intel_parser;
5794
5795/* Token structure for parsing intel syntax. */
5796struct intel_token
5797 {
5798 int code; /* Token code. */
5799 const reg_entry *reg; /* Register entry for register tokens. */
5800 char *str; /* String representation. */
5801 };
5802
5803static struct intel_token cur_token, prev_token;
5804
50705ef4
AM		 5805/* Token codes for the intel parser. Since T_SHORT is already used
5806 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5807#define T_NIL -1
5808#define T_CONST 1
5809#define T_REG 2
5810#define T_BYTE 3
5811#define T_WORD 4
9306ca4a
JB		 5812#define T_DWORD 5
5813#define T_FWORD 6
5814#define T_QWORD 7
5815#define T_TBYTE 8
5816#define T_XMMWORD 9
50705ef4 5817#undef T_SHORT
9306ca4a
JB		 5818#define T_SHORT 10
5819#define T_OFFSET 11
5820#define T_PTR 12
5821#define T_ID 13
5822#define T_SHL 14
5823#define T_SHR 15
64a0c779
DN		 5824
5825/* Prototypes for intel parser functions. */
5826static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5827static void intel_get_token PARAMS ((void));
5828static void intel_putback_token PARAMS ((void));
5829static int intel_expr PARAMS ((void));
9306ca4a 5830static int intel_e04 PARAMS ((void));
cce0cbdc 5831static int intel_e05 PARAMS ((void));
cce0cbdc 5832static int intel_e06 PARAMS ((void));
cce0cbdc 5833static int intel_e09 PARAMS ((void));
a724f0f4 5834static int intel_bracket_expr PARAMS ((void));
cce0cbdc 5835static int intel_e10 PARAMS ((void));
cce0cbdc 5836static int intel_e11 PARAMS ((void));
64a0c779 5837
64a0c779
DN		 5838static int
5839i386_intel_operand (operand_string, got_a_float)
5840 char *operand_string;
5841 int got_a_float;
5842{
5843 int ret;
5844 char *p;
5845
a724f0f4
JB		 5846 p = intel_parser.op_string = xstrdup (operand_string);
5847 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
5848
5849 for (;;)
64a0c779 5850 {
a724f0f4
JB		 5851 /* Initialize token holders. */
5852 cur_token.code = prev_token.code = T_NIL;
5853 cur_token.reg = prev_token.reg = NULL;
5854 cur_token.str = prev_token.str = NULL;
5855
5856 /* Initialize parser structure. */
5857 intel_parser.got_a_float = got_a_float;
5858 intel_parser.op_modifier = 0;
5859 intel_parser.is_mem = 0;
5860 intel_parser.in_offset = 0;
5861 intel_parser.in_bracket = 0;
5862 intel_parser.reg = NULL;
5863 intel_parser.disp[0] = '\0';
5864 intel_parser.next_operand = NULL;
5865
5866 /* Read the first token and start the parser. */
5867 intel_get_token ();
5868 ret = intel_expr ();
5869
5870 if (!ret)
5871 break;
5872
9306ca4a
JB		 5873 if (cur_token.code != T_NIL)
5874 {
5875 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5876 current_templates->start->name, cur_token.str);
5877 ret = 0;
5878 }
64a0c779
DN		 5879 /* If we found a memory reference, hand it over to i386_displacement
5880 to fill in the rest of the operand fields. */
9306ca4a 5881 else if (intel_parser.is_mem)
64a0c779
DN		 5882 {
5883 if ((i.mem_operands == 1
5884 && (current_templates->start->opcode_modifier & IsString) == 0)
5885 || i.mem_operands == 2)
5886 {
5887 as_bad (_("too many memory references for '%s'"),
5888 current_templates->start->name);
5889 ret = 0;
5890 }
5891 else
5892 {
5893 char *s = intel_parser.disp;
5894 i.mem_operands++;
5895
a724f0f4
JB		 5896 if (!quiet_warnings && intel_parser.is_mem < 0)
5897 /* See the comments in intel_bracket_expr. */
5898 as_warn (_("Treating `%s' as memory reference"), operand_string);
5899
64a0c779
DN		 5900 /* Add the displacement expression. */
5901 if (*s != '\0')
a4622f40
AM		 5902 ret = i386_displacement (s, s + strlen (s));
5903 if (ret)
a724f0f4
JB		 5904 {
5905 /* Swap base and index in 16-bit memory operands like
5906 [si+bx]. Since i386_index_check is also used in AT&T
5907 mode we have to do that here. */
5908 if (i.base_reg
5909 && i.index_reg
5910 && (i.base_reg->reg_type & Reg16)
5911 && (i.index_reg->reg_type & Reg16)
5912 && i.base_reg->reg_num >= 6
5913 && i.index_reg->reg_num < 6)
5914 {
5915 const reg_entry *base = i.index_reg;
5916
5917 i.index_reg = i.base_reg;
5918 i.base_reg = base;
5919 }
5920 ret = i386_index_check (operand_string);
5921 }
64a0c779
DN		 5922 }
5923 }
5924
5925 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 5926 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 5927 || intel_parser.reg == NULL)
5928 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 5929
5930 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
5931 ret = 0;
5932 if (!ret || !intel_parser.next_operand)
5933 break;
5934 intel_parser.op_string = intel_parser.next_operand;
5935 this_operand = i.operands++;
64a0c779
DN		 5936 }
5937
5938 free (p);
5939 free (intel_parser.disp);
5940
5941 return ret;
5942}
5943
a724f0f4
JB		 5944#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5945
5946/* expr e04 expr'
5947
5948 expr' cmpOp e04 expr'
5949 | Empty */
64a0c779
DN		 5950static int
5951intel_expr ()
5952{
a724f0f4
JB		 5953 /* XXX Implement the comparison operators. */
5954 return intel_e04 ();
9306ca4a
JB		 5955}
5956
a724f0f4 5957/* e04 e05 e04'
9306ca4a 5958
a724f0f4 5959 e04' addOp e05 e04'
9306ca4a
JB		 5960 | Empty */
5961static int
5962intel_e04 ()
5963{
a724f0f4 5964 int nregs = -1;
9306ca4a 5965
a724f0f4 5966 for (;;)
9306ca4a 5967 {
a724f0f4
JB		 5968 if (!intel_e05())
5969 return 0;
9306ca4a 5970
a724f0f4
JB		 5971 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5972 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 5973
a724f0f4
JB		 5974 if (cur_token.code == '+')
5975 nregs = -1;
5976 else if (cur_token.code == '-')
5977 nregs = NUM_ADDRESS_REGS;
5978 else
5979 return 1;
64a0c779 5980
a724f0f4
JB		 5981 strcat (intel_parser.disp, cur_token.str);
5982 intel_match_token (cur_token.code);
5983 }
64a0c779
DN		 5984}
5985
64a0c779
DN		 5986/* e05 e06 e05'
5987
9306ca4a 5988 e05' binOp e06 e05'
64a0c779
DN		 5989 | Empty */
5990static int
5991intel_e05 ()
5992{
a724f0f4 5993 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 5994
a724f0f4 5995 for (;;)
64a0c779 5996 {
a724f0f4
JB		 5997 if (!intel_e06())
5998 return 0;
5999
6000 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6001 {
6002 char str[2];
6003
6004 str[0] = cur_token.code;
6005 str[1] = 0;
6006 strcat (intel_parser.disp, str);
6007 }
6008 else
6009 break;
9306ca4a 6010
64a0c779
DN		 6011 intel_match_token (cur_token.code);
6012
a724f0f4
JB		 6013 if (nregs < 0)
6014 nregs = ~nregs;
64a0c779 6015 }
a724f0f4
JB		 6016 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6017 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6018 return 1;
4a1805b1 6019}
64a0c779
DN		 6020
6021/* e06 e09 e06'
6022
6023 e06' mulOp e09 e06'
b77a7acd 6024 | Empty */
64a0c779
DN		 6025static int
6026intel_e06 ()
6027{
a724f0f4 6028 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6029
a724f0f4 6030 for (;;)
64a0c779 6031 {
a724f0f4
JB		 6032 if (!intel_e09())
6033 return 0;
9306ca4a 6034
a724f0f4
JB		 6035 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6036 {
6037 char str[2];
9306ca4a 6038
a724f0f4
JB		 6039 str[0] = cur_token.code;
6040 str[1] = 0;
6041 strcat (intel_parser.disp, str);
6042 }
6043 else if (cur_token.code == T_SHL)
6044 strcat (intel_parser.disp, "<<");
6045 else if (cur_token.code == T_SHR)
6046 strcat (intel_parser.disp, ">>");
6047 else
6048 break;
9306ca4a 6049
a724f0f4 6050 intel_match_token (cur_token.code);
64a0c779 6051
a724f0f4
JB		 6052 if (nregs < 0)
6053 nregs = ~nregs;
64a0c779 6054 }
a724f0f4
JB		 6055 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6056 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6057 return 1;
64a0c779
DN		 6058}
6059
a724f0f4
JB		 6060/* e09 OFFSET e09
6061 | SHORT e09
6062 | + e09
6063 | - e09
6064 | ~ e09
6065 | NOT e09
9306ca4a
JB		 6066 | e10 e09'
6067
64a0c779 6068 e09' PTR e10 e09'
b77a7acd 6069 | : e10 e09'
64a0c779
DN		 6070 | Empty */
6071static int
6072intel_e09 ()
6073{
a724f0f4
JB		 6074 int nregs = ~NUM_ADDRESS_REGS;
6075 int in_offset = 0;
6076
6077 for (;;)
64a0c779 6078 {
a724f0f4
JB		 6079 /* Don't consume constants here. */
6080 if (cur_token.code == '+' || cur_token.code == '-')
6081 {
6082 /* Need to look one token ahead - if the next token
6083 is a constant, the current token is its sign. */
6084 int next_code;
6085
6086 intel_match_token (cur_token.code);
6087 next_code = cur_token.code;
6088 intel_putback_token ();
6089 if (next_code == T_CONST)
6090 break;
6091 }
6092
6093 /* e09 OFFSET e09 */
6094 if (cur_token.code == T_OFFSET)
6095 {
6096 if (!in_offset++)
6097 ++intel_parser.in_offset;
6098 }
6099
6100 /* e09 SHORT e09 */
6101 else if (cur_token.code == T_SHORT)
6102 intel_parser.op_modifier |= 1 << T_SHORT;
6103
6104 /* e09 + e09 */
6105 else if (cur_token.code == '+')
6106 strcat (intel_parser.disp, "+");
6107
6108 /* e09 - e09
6109 | ~ e09
6110 | NOT e09 */
6111 else if (cur_token.code == '-' || cur_token.code == '~')
6112 {
6113 char str[2];
64a0c779 6114
a724f0f4
JB		 6115 if (nregs < 0)
6116 nregs = ~nregs;
6117 str[0] = cur_token.code;
6118 str[1] = 0;
6119 strcat (intel_parser.disp, str);
6120 }
6121
6122 /* e09 e10 e09' */
6123 else
6124 break;
6125
6126 intel_match_token (cur_token.code);
64a0c779
DN		 6127 }
6128
a724f0f4 6129 for (;;)
9306ca4a 6130 {
a724f0f4
JB		 6131 if (!intel_e10 ())
6132 return 0;
9306ca4a 6133
a724f0f4
JB		 6134 /* e09' PTR e10 e09' */
6135 if (cur_token.code == T_PTR)
6136 {
6137 char suffix;
9306ca4a 6138
a724f0f4
JB		 6139 if (prev_token.code == T_BYTE)
6140 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6141
a724f0f4
JB		 6142 else if (prev_token.code == T_WORD)
6143 {
6144 if (current_templates->start->name[0] == 'l'
6145 && current_templates->start->name[2] == 's'
6146 && current_templates->start->name[3] == 0)
6147 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6148 else if (intel_parser.got_a_float == 2) /* "fi..." */
6149 suffix = SHORT_MNEM_SUFFIX;
6150 else
6151 suffix = WORD_MNEM_SUFFIX;
6152 }
64a0c779 6153
a724f0f4
JB		 6154 else if (prev_token.code == T_DWORD)
6155 {
6156 if (current_templates->start->name[0] == 'l'
6157 && current_templates->start->name[2] == 's'
6158 && current_templates->start->name[3] == 0)
6159 suffix = WORD_MNEM_SUFFIX;
6160 else if (flag_code == CODE_16BIT
6161 && (current_templates->start->opcode_modifier
435acd52 6162 & (Jump | JumpDword)))
a724f0f4
JB		 6163 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6164 else if (intel_parser.got_a_float == 1) /* "f..." */
6165 suffix = SHORT_MNEM_SUFFIX;
6166 else
6167 suffix = LONG_MNEM_SUFFIX;
6168 }
9306ca4a 6169
a724f0f4
JB		 6170 else if (prev_token.code == T_FWORD)
6171 {
6172 if (current_templates->start->name[0] == 'l'
6173 && current_templates->start->name[2] == 's'
6174 && current_templates->start->name[3] == 0)
6175 suffix = LONG_MNEM_SUFFIX;
6176 else if (!intel_parser.got_a_float)
6177 {
6178 if (flag_code == CODE_16BIT)
6179 add_prefix (DATA_PREFIX_OPCODE);
6180 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6181 }
6182 else
6183 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6184 }
64a0c779 6185
a724f0f4
JB		 6186 else if (prev_token.code == T_QWORD)
6187 {
6188 if (intel_parser.got_a_float == 1) /* "f..." */
6189 suffix = LONG_MNEM_SUFFIX;
6190 else
6191 suffix = QWORD_MNEM_SUFFIX;
6192 }
64a0c779 6193
a724f0f4
JB		 6194 else if (prev_token.code == T_TBYTE)
6195 {
6196 if (intel_parser.got_a_float == 1)
6197 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6198 else
6199 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6200 }
9306ca4a 6201
a724f0f4 6202 else if (prev_token.code == T_XMMWORD)
9306ca4a 6203 {
a724f0f4
JB		 6204 /* XXX ignored for now, but accepted since gcc uses it */
6205 suffix = 0;
9306ca4a 6206 }
64a0c779 6207
f16b83df 6208 else
a724f0f4
JB		 6209 {
6210 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6211 return 0;
6212 }
6213
435acd52
JB		 6214 /* Operands for jump/call using 'ptr' notation denote absolute
6215 addresses. */
6216 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6217 i.types[this_operand] |= JumpAbsolute;
6218
a724f0f4
JB		 6219 if (current_templates->start->base_opcode == 0x8d /* lea */)
6220 ;
6221 else if (!i.suffix)
6222 i.suffix = suffix;
6223 else if (i.suffix != suffix)
6224 {
6225 as_bad (_("Conflicting operand modifiers"));
6226 return 0;
6227 }
64a0c779 6228
9306ca4a
JB		 6229 }
6230
a724f0f4
JB		 6231 /* e09' : e10 e09' */
6232 else if (cur_token.code == ':')
9306ca4a 6233 {
a724f0f4
JB		 6234 if (prev_token.code != T_REG)
6235 {
6236 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6237 segment/group identifier (which we don't have), using comma
6238 as the operand separator there is even less consistent, since
6239 there all branches only have a single operand. */
6240 if (this_operand != 0
6241 || intel_parser.in_offset
6242 || intel_parser.in_bracket
6243 || (!(current_templates->start->opcode_modifier
6244 & (Jump|JumpDword|JumpInterSegment))
6245 && !(current_templates->start->operand_types[0]
6246 & JumpAbsolute)))
6247 return intel_match_token (T_NIL);
6248 /* Remember the start of the 2nd operand and terminate 1st
6249 operand here.
6250 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6251 another expression), but it gets at least the simplest case
6252 (a plain number or symbol on the left side) right. */
6253 intel_parser.next_operand = intel_parser.op_string;
6254 *--intel_parser.op_string = '\0';
6255 return intel_match_token (':');
6256 }
9306ca4a 6257 }
64a0c779 6258
a724f0f4 6259 /* e09' Empty */
64a0c779 6260 else
a724f0f4 6261 break;
64a0c779 6262
a724f0f4
JB		 6263 intel_match_token (cur_token.code);
6264
6265 }
6266
6267 if (in_offset)
6268 {
6269 --intel_parser.in_offset;
6270 if (nregs < 0)
6271 nregs = ~nregs;
6272 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 6273 {
a724f0f4 6274 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 6275 return 0;
6276 }
a724f0f4
JB		 6277 intel_parser.op_modifier |= 1 << T_OFFSET;
6278 }
9306ca4a 6279
a724f0f4
JB		 6280 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6281 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6282 return 1;
6283}
64a0c779 6284
a724f0f4
JB		 6285static int
6286intel_bracket_expr ()
6287{
6288 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6289 const char *start = intel_parser.op_string;
6290 int len;
6291
6292 if (i.op[this_operand].regs)
6293 return intel_match_token (T_NIL);
6294
6295 intel_match_token ('[');
6296
6297 /* Mark as a memory operand only if it's not already known to be an
6298 offset expression. If it's an offset expression, we need to keep
6299 the brace in. */
6300 if (!intel_parser.in_offset)
6301 {
6302 ++intel_parser.in_bracket;
435acd52
JB		 6303
6304 /* Operands for jump/call inside brackets denote absolute addresses. */
6305 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6306 i.types[this_operand] |= JumpAbsolute;
6307
a724f0f4
JB		 6308 /* Unfortunately gas always diverged from MASM in a respect that can't
6309 be easily fixed without risking to break code sequences likely to be
6310 encountered (the testsuite even check for this): MASM doesn't consider
6311 an expression inside brackets unconditionally as a memory reference.
6312 When that is e.g. a constant, an offset expression, or the sum of the
6313 two, this is still taken as a constant load. gas, however, always
6314 treated these as memory references. As a compromise, we'll try to make
6315 offset expressions inside brackets work the MASM way (since that's
6316 less likely to be found in real world code), but make constants alone
6317 continue to work the traditional gas way. In either case, issue a
6318 warning. */
6319 intel_parser.op_modifier &= ~was_offset;
64a0c779 6320 }
a724f0f4
JB		 6321 else
6322 strcat (intel_parser.disp, "[");
6323
6324 /* Add a '+' to the displacement string if necessary. */
6325 if (*intel_parser.disp != '\0'
6326 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6327 strcat (intel_parser.disp, "+");
64a0c779 6328
a724f0f4
JB		 6329 if (intel_expr ()
6330 && (len = intel_parser.op_string - start - 1,
6331 intel_match_token (']')))
64a0c779 6332 {
a724f0f4
JB		 6333 /* Preserve brackets when the operand is an offset expression. */
6334 if (intel_parser.in_offset)
6335 strcat (intel_parser.disp, "]");
6336 else
6337 {
6338 --intel_parser.in_bracket;
6339 if (i.base_reg || i.index_reg)
6340 intel_parser.is_mem = 1;
6341 if (!intel_parser.is_mem)
6342 {
6343 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6344 /* Defer the warning until all of the operand was parsed. */
6345 intel_parser.is_mem = -1;
6346 else if (!quiet_warnings)
6347 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6348 }
6349 }
6350 intel_parser.op_modifier |= was_offset;
64a0c779 6351
a724f0f4 6352 return 1;
64a0c779 6353 }
a724f0f4 6354 return 0;
64a0c779
DN		 6355}
6356
6357/* e10 e11 e10'
6358
6359 e10' [ expr ] e10'
b77a7acd 6360 | Empty */
64a0c779
DN		 6361static int
6362intel_e10 ()
6363{
a724f0f4
JB		 6364 if (!intel_e11 ())
6365 return 0;
64a0c779 6366
a724f0f4 6367 while (cur_token.code == '[')
64a0c779 6368 {
a724f0f4 6369 if (!intel_bracket_expr ())
21d6c4af 6370 return 0;
64a0c779
DN		 6371 }
6372
a724f0f4 6373 return 1;
64a0c779
DN		 6374}
6375
64a0c779 6376/* e11 ( expr )
b77a7acd 6377 | [ expr ]
64a0c779
DN		 6378 | BYTE
6379 | WORD
6380 | DWORD
9306ca4a 6381 | FWORD
64a0c779 6382 | QWORD
9306ca4a
JB		 6383 | TBYTE
6384 | OWORD
6385 | XMMWORD
4a1805b1 6386 | $
64a0c779
DN		 6387 | .
6388 | register
6389 | id
6390 | constant */
6391static int
6392intel_e11 ()
6393{
a724f0f4 6394 switch (cur_token.code)
64a0c779 6395 {
a724f0f4
JB		 6396 /* e11 ( expr ) */
6397 case '(':
64a0c779
DN		 6398 intel_match_token ('(');
6399 strcat (intel_parser.disp, "(");
6400
6401 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 6402 {
6403 strcat (intel_parser.disp, ")");
6404 return 1;
6405 }
a724f0f4 6406 return 0;
4a1805b1 6407
a724f0f4
JB		 6408 /* e11 [ expr ] */
6409 case '[':
a724f0f4 6410 return intel_bracket_expr ();
64a0c779 6411
a724f0f4
JB		 6412 /* e11 $
6413 | . */
6414 case '.':
64a0c779
DN		 6415 strcat (intel_parser.disp, cur_token.str);
6416 intel_match_token (cur_token.code);
21d6c4af
DN		 6417
6418 /* Mark as a memory operand only if it's not already known to be an
6419 offset expression. */
a724f0f4 6420 if (!intel_parser.in_offset)
21d6c4af 6421 intel_parser.is_mem = 1;
64a0c779
DN		 6422
6423 return 1;
64a0c779 6424
a724f0f4
JB		 6425 /* e11 register */
6426 case T_REG:
6427 {
6428 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 6429
a724f0f4 6430 intel_match_token (T_REG);
64a0c779 6431
a724f0f4
JB		 6432 /* Check for segment change. */
6433 if (cur_token.code == ':')
6434 {
6435 if (!(reg->reg_type & (SReg2 | SReg3)))
6436 {
6437 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6438 return 0;
6439 }
6440 else if (i.seg[i.mem_operands])
6441 as_warn (_("Extra segment override ignored"));
6442 else
6443 {
6444 if (!intel_parser.in_offset)
6445 intel_parser.is_mem = 1;
6446 switch (reg->reg_num)
6447 {
6448 case 0:
6449 i.seg[i.mem_operands] = &es;
6450 break;
6451 case 1:
6452 i.seg[i.mem_operands] = &cs;
6453 break;
6454 case 2:
6455 i.seg[i.mem_operands] = &ss;
6456 break;
6457 case 3:
6458 i.seg[i.mem_operands] = &ds;
6459 break;
6460 case 4:
6461 i.seg[i.mem_operands] = &fs;
6462 break;
6463 case 5:
6464 i.seg[i.mem_operands] = &gs;
6465 break;
6466 }
6467 }
6468 }
64a0c779 6469
a724f0f4
JB		 6470 /* Not a segment register. Check for register scaling. */
6471 else if (cur_token.code == '*')
6472 {
6473 if (!intel_parser.in_bracket)
6474 {
6475 as_bad (_("Register scaling only allowed in memory operands"));
6476 return 0;
6477 }
64a0c779 6478
a724f0f4
JB		 6479 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6480 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6481 else if (i.index_reg)
6482 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 6483
a724f0f4
JB		 6484 /* What follows must be a valid scale. */
6485 intel_match_token ('*');
6486 i.index_reg = reg;
6487 i.types[this_operand] |= BaseIndex;
64a0c779 6488
a724f0f4
JB		 6489 /* Set the scale after setting the register (otherwise,
6490 i386_scale will complain) */
6491 if (cur_token.code == '+' || cur_token.code == '-')
6492 {
6493 char *str, sign = cur_token.code;
6494 intel_match_token (cur_token.code);
6495 if (cur_token.code != T_CONST)
6496 {
6497 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6498 cur_token.str);
6499 return 0;
6500 }
6501 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6502 strcpy (str + 1, cur_token.str);
6503 *str = sign;
6504 if (!i386_scale (str))
6505 return 0;
6506 free (str);
6507 }
6508 else if (!i386_scale (cur_token.str))
64a0c779 6509 return 0;
a724f0f4
JB		 6510 intel_match_token (cur_token.code);
6511 }
64a0c779 6512
a724f0f4
JB		 6513 /* No scaling. If this is a memory operand, the register is either a
6514 base register (first occurrence) or an index register (second
6515 occurrence). */
6516 else if (intel_parser.in_bracket && !(reg->reg_type & (SReg2 | SReg3)))
6517 {
64a0c779 6518
a724f0f4
JB		 6519 if (!i.base_reg)
6520 i.base_reg = reg;
6521 else if (!i.index_reg)
6522 i.index_reg = reg;
6523 else
6524 {
6525 as_bad (_("Too many register references in memory operand"));
6526 return 0;
6527 }
64a0c779 6528
a724f0f4
JB		 6529 i.types[this_operand] |= BaseIndex;
6530 }
4a1805b1 6531
a724f0f4
JB		 6532 /* Offset modifier. Add the register to the displacement string to be
6533 parsed as an immediate expression after we're done. */
6534 else if (intel_parser.in_offset)
6535 {
6536 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6537 strcat (intel_parser.disp, reg->reg_name);
6538 }
64a0c779 6539
a724f0f4
JB		 6540 /* It's neither base nor index nor offset. */
6541 else if (!intel_parser.is_mem)
6542 {
6543 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6544 i.op[this_operand].regs = reg;
6545 i.reg_operands++;
6546 }
6547 else
6548 {
6549 as_bad (_("Invalid use of register"));
6550 return 0;
6551 }
64a0c779 6552
a724f0f4
JB		 6553 /* Since registers are not part of the displacement string (except
6554 when we're parsing offset operands), we may need to remove any
6555 preceding '+' from the displacement string. */
6556 if (*intel_parser.disp != '\0'
6557 && !intel_parser.in_offset)
6558 {
6559 char *s = intel_parser.disp;
6560 s += strlen (s) - 1;
6561 if (*s == '+')
6562 *s = '\0';
6563 }
4a1805b1 6564
a724f0f4
JB		 6565 return 1;
6566 }
6567
6568 /* e11 BYTE
6569 | WORD
6570 | DWORD
6571 | FWORD
6572 | QWORD
6573 | TBYTE
6574 | OWORD
6575 | XMMWORD */
6576 case T_BYTE:
6577 case T_WORD:
6578 case T_DWORD:
6579 case T_FWORD:
6580 case T_QWORD:
6581 case T_TBYTE:
6582 case T_XMMWORD:
6583 intel_match_token (cur_token.code);
64a0c779 6584
a724f0f4
JB		 6585 if (cur_token.code == T_PTR)
6586 return 1;
6587
6588 /* It must have been an identifier. */
6589 intel_putback_token ();
6590 cur_token.code = T_ID;
6591 /* FALLTHRU */
6592
6593 /* e11 id
6594 | constant */
6595 case T_ID:
6596 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 6597 {
6598 symbolS *symbolP;
6599
a724f0f4
JB		 6600 /* The identifier represents a memory reference only if it's not
6601 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 6602 symbolP = symbol_find(cur_token.str);
6603 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6604 intel_parser.is_mem = 1;
6605 }
a724f0f4 6606 /* FALLTHRU */
64a0c779 6607
a724f0f4
JB		 6608 case T_CONST:
6609 case '-':
6610 case '+':
6611 {
6612 char *save_str, sign = 0;
64a0c779 6613
a724f0f4
JB		 6614 /* Allow constants that start with `+' or `-'. */
6615 if (cur_token.code == '-' || cur_token.code == '+')
6616 {
6617 sign = cur_token.code;
6618 intel_match_token (cur_token.code);
6619 if (cur_token.code != T_CONST)
6620 {
6621 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6622 cur_token.str);
6623 return 0;
6624 }
6625 }
64a0c779 6626
a724f0f4
JB		 6627 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6628 strcpy (save_str + !!sign, cur_token.str);
6629 if (sign)
6630 *save_str = sign;
64a0c779 6631
a724f0f4
JB		 6632 /* Get the next token to check for register scaling. */
6633 intel_match_token (cur_token.code);
64a0c779 6634
a724f0f4
JB		 6635 /* Check if this constant is a scaling factor for an index register. */
6636 if (cur_token.code == '*')
6637 {
6638 if (intel_match_token ('*') && cur_token.code == T_REG)
6639 {
6640 const reg_entry *reg = cur_token.reg;
6641
6642 if (!intel_parser.in_bracket)
6643 {
6644 as_bad (_("Register scaling only allowed in memory operands"));
6645 return 0;
6646 }
6647
6648 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6649 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6650 else if (i.index_reg)
6651 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6652
6653 /* The constant is followed by `* reg', so it must be
6654 a valid scale. */
6655 i.index_reg = reg;
6656 i.types[this_operand] |= BaseIndex;
6657
6658 /* Set the scale after setting the register (otherwise,
6659 i386_scale will complain) */
6660 if (!i386_scale (save_str))
64a0c779 6661 return 0;
a724f0f4
JB		 6662 intel_match_token (T_REG);
6663
6664 /* Since registers are not part of the displacement
6665 string, we may need to remove any preceding '+' from
6666 the displacement string. */
6667 if (*intel_parser.disp != '\0')
6668 {
6669 char *s = intel_parser.disp;
6670 s += strlen (s) - 1;
6671 if (*s == '+')
6672 *s = '\0';
6673 }
6674
6675 free (save_str);
6676
6677 return 1;
6678 }
64a0c779 6679
a724f0f4
JB		 6680 /* The constant was not used for register scaling. Since we have
6681 already consumed the token following `*' we now need to put it
6682 back in the stream. */
64a0c779 6683 intel_putback_token ();
a724f0f4 6684 }
64a0c779 6685
a724f0f4
JB		 6686 /* Add the constant to the displacement string. */
6687 strcat (intel_parser.disp, save_str);
6688 free (save_str);
64a0c779 6689
a724f0f4
JB		 6690 return 1;
6691 }
64a0c779
DN		 6692 }
6693
64a0c779
DN		 6694 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6695 return 0;
6696}
6697
64a0c779
DN		 6698/* Match the given token against cur_token. If they match, read the next
6699 token from the operand string. */
6700static int
6701intel_match_token (code)
e5cb08ac 6702 int code;
64a0c779
DN		 6703{
6704 if (cur_token.code == code)
6705 {
6706 intel_get_token ();
6707 return 1;
6708 }
6709 else
6710 {
0477af35 6711 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 6712 return 0;
6713 }
6714}
6715
64a0c779
DN		 6716/* Read a new token from intel_parser.op_string and store it in cur_token. */
6717static void
6718intel_get_token ()
6719{
6720 char *end_op;
6721 const reg_entry *reg;
6722 struct intel_token new_token;
6723
6724 new_token.code = T_NIL;
6725 new_token.reg = NULL;
6726 new_token.str = NULL;
6727
4a1805b1 6728 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6729 cur_token to prev_token. */
6730 if (prev_token.str)
6731 free (prev_token.str);
6732
6733 prev_token = cur_token;
6734
6735 /* Skip whitespace. */
6736 while (is_space_char (*intel_parser.op_string))
6737 intel_parser.op_string++;
6738
6739 /* Return an empty token if we find nothing else on the line. */
6740 if (*intel_parser.op_string == '\0')
6741 {
6742 cur_token = new_token;
6743 return;
6744 }
6745
6746 /* The new token cannot be larger than the remainder of the operand
6747 string. */
a724f0f4 6748 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 6749 new_token.str[0] = '\0';
6750
6751 if (strchr ("0123456789", *intel_parser.op_string))
6752 {
6753 char *p = new_token.str;
6754 char *q = intel_parser.op_string;
6755 new_token.code = T_CONST;
6756
6757 /* Allow any kind of identifier char to encompass floating point and
6758 hexadecimal numbers. */
6759 while (is_identifier_char (*q))
6760 *p++ = *q++;
6761 *p = '\0';
6762
6763 /* Recognize special symbol names [0-9][bf]. */
6764 if (strlen (intel_parser.op_string) == 2
4a1805b1 6765 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6766 || intel_parser.op_string[1] == 'f'))
6767 new_token.code = T_ID;
6768 }
6769
64a0c779
DN		 6770 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6771 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6772 {
6773 new_token.code = T_REG;
6774 new_token.reg = reg;
6775
6776 if (*intel_parser.op_string == REGISTER_PREFIX)
6777 {
6778 new_token.str[0] = REGISTER_PREFIX;
6779 new_token.str[1] = '\0';
6780 }
6781
6782 strcat (new_token.str, reg->reg_name);
6783 }
6784
6785 else if (is_identifier_char (*intel_parser.op_string))
6786 {
6787 char *p = new_token.str;
6788 char *q = intel_parser.op_string;
6789
6790 /* A '.' or '$' followed by an identifier char is an identifier.
6791 Otherwise, it's operator '.' followed by an expression. */
6792 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6793 {
9306ca4a
JB		 6794 new_token.code = '.';
6795 new_token.str[0] = '.';
64a0c779
DN		 6796 new_token.str[1] = '\0';
6797 }
6798 else
6799 {
6800 while (is_identifier_char (*q) || *q == '@')
6801 *p++ = *q++;
6802 *p = '\0';
6803
9306ca4a
JB		 6804 if (strcasecmp (new_token.str, "NOT") == 0)
6805 new_token.code = '~';
6806
6807 else if (strcasecmp (new_token.str, "MOD") == 0)
6808 new_token.code = '%';
6809
6810 else if (strcasecmp (new_token.str, "AND") == 0)
6811 new_token.code = '&';
6812
6813 else if (strcasecmp (new_token.str, "OR") == 0)
6814 new_token.code = '|';
6815
6816 else if (strcasecmp (new_token.str, "XOR") == 0)
6817 new_token.code = '^';
6818
6819 else if (strcasecmp (new_token.str, "SHL") == 0)
6820 new_token.code = T_SHL;
6821
6822 else if (strcasecmp (new_token.str, "SHR") == 0)
6823 new_token.code = T_SHR;
6824
6825 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 6826 new_token.code = T_BYTE;
6827
6828 else if (strcasecmp (new_token.str, "WORD") == 0)
6829 new_token.code = T_WORD;
6830
6831 else if (strcasecmp (new_token.str, "DWORD") == 0)
6832 new_token.code = T_DWORD;
6833
9306ca4a
JB		 6834 else if (strcasecmp (new_token.str, "FWORD") == 0)
6835 new_token.code = T_FWORD;
6836
64a0c779
DN		 6837 else if (strcasecmp (new_token.str, "QWORD") == 0)
6838 new_token.code = T_QWORD;
6839
9306ca4a
JB		 6840 else if (strcasecmp (new_token.str, "TBYTE") == 0
6841 /* XXX remove (gcc still uses it) */
6842 || strcasecmp (new_token.str, "XWORD") == 0)
6843 new_token.code = T_TBYTE;
6844
6845 else if (strcasecmp (new_token.str, "XMMWORD") == 0
6846 || strcasecmp (new_token.str, "OWORD") == 0)
6847 new_token.code = T_XMMWORD;
64a0c779
DN		 6848
6849 else if (strcasecmp (new_token.str, "PTR") == 0)
6850 new_token.code = T_PTR;
6851
6852 else if (strcasecmp (new_token.str, "SHORT") == 0)
6853 new_token.code = T_SHORT;
6854
6855 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6856 {
6857 new_token.code = T_OFFSET;
6858
6859 /* ??? This is not mentioned in the MASM grammar but gcc
6860 makes use of it with -mintel-syntax. OFFSET may be
6861 followed by FLAT: */
6862 if (strncasecmp (q, " FLAT:", 6) == 0)
6863 strcat (new_token.str, " FLAT:");
6864 }
6865
6866 /* ??? This is not mentioned in the MASM grammar. */
6867 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 6868 {
6869 new_token.code = T_OFFSET;
6870 if (*q == ':')
6871 strcat (new_token.str, ":");
6872 else
6873 as_bad (_("`:' expected"));
6874 }
64a0c779
DN		 6875
6876 else
6877 new_token.code = T_ID;
6878 }
6879 }
6880
9306ca4a
JB		 6881 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
6882 {
6883 new_token.code = *intel_parser.op_string;
6884 new_token.str[0] = *intel_parser.op_string;
6885 new_token.str[1] = '\0';
6886 }
6887
6888 else if (strchr ("<>", *intel_parser.op_string)
6889 && *intel_parser.op_string == *(intel_parser.op_string + 1))
6890 {
6891 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
6892 new_token.str[0] = *intel_parser.op_string;
6893 new_token.str[1] = *intel_parser.op_string;
6894 new_token.str[2] = '\0';
6895 }
6896
64a0c779 6897 else
0477af35 6898 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 6899
6900 intel_parser.op_string += strlen (new_token.str);
6901 cur_token = new_token;
6902}
6903
64a0c779
DN		 6904/* Put cur_token back into the token stream and make cur_token point to
6905 prev_token. */
6906static void
6907intel_putback_token ()
6908{
a724f0f4
JB		 6909 if (cur_token.code != T_NIL)
6910 {
6911 intel_parser.op_string -= strlen (cur_token.str);
6912 free (cur_token.str);
6913 }
64a0c779 6914 cur_token = prev_token;
4a1805b1 6915
64a0c779
DN		 6916 /* Forget prev_token. */
6917 prev_token.code = T_NIL;
6918 prev_token.reg = NULL;
6919 prev_token.str = NULL;
6920}
54cfded0 6921
a4447b93 6922int
54cfded0
AM		 6923tc_x86_regname_to_dw2regnum (const char *regname)
6924{
6925 unsigned int regnum;
6926 unsigned int regnames_count;
089dfecd 6927 static const char *const regnames_32[] =
54cfded0 6928 {
a4447b93
RH		 6929 "eax", "ecx", "edx", "ebx",
6930 "esp", "ebp", "esi", "edi",
089dfecd
JB		 6931 "eip", "eflags", NULL,
6932 "st0", "st1", "st2", "st3",
6933 "st4", "st5", "st6", "st7",
6934 NULL, NULL,
6935 "xmm0", "xmm1", "xmm2", "xmm3",
6936 "xmm4", "xmm5", "xmm6", "xmm7",
6937 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 6938 "mm4", "mm5", "mm6", "mm7",
6939 "fcw", "fsw", "mxcsr",
6940 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
6941 "tr", "ldtr"
54cfded0 6942 };
089dfecd 6943 static const char *const regnames_64[] =
54cfded0 6944 {
089dfecd
JB		 6945 "rax", "rdx", "rcx", "rbx",
6946 "rsi", "rdi", "rbp", "rsp",
6947 "r8", "r9", "r10", "r11",
54cfded0 6948 "r12", "r13", "r14", "r15",
089dfecd
JB		 6949 "rip",
6950 "xmm0", "xmm1", "xmm2", "xmm3",
6951 "xmm4", "xmm5", "xmm6", "xmm7",
6952 "xmm8", "xmm9", "xmm10", "xmm11",
6953 "xmm12", "xmm13", "xmm14", "xmm15",
6954 "st0", "st1", "st2", "st3",
6955 "st4", "st5", "st6", "st7",
6956 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 6957 "mm4", "mm5", "mm6", "mm7",
6958 "rflags",
6959 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
6960 "fs.base", "gs.base", NULL, NULL,
6961 "tr", "ldtr",
6962 "mxcsr", "fcw", "fsw"
54cfded0 6963 };
089dfecd 6964 const char *const *regnames;
54cfded0
AM		 6965
6966 if (flag_code == CODE_64BIT)
6967 {
6968 regnames = regnames_64;
0cea6190 6969 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 6970 }
6971 else
6972 {
6973 regnames = regnames_32;
0cea6190 6974 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 6975 }
6976
6977 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 6978 if (regnames[regnum] != NULL
6979 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 6980 return regnum;
6981
54cfded0
AM		 6982 return -1;
6983}
6984
6985void
6986tc_x86_frame_initial_instructions (void)
6987{
a4447b93
RH		 6988 static unsigned int sp_regno;
6989
6990 if (!sp_regno)
6991 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
6992 ? "rsp" : "esp");
6993
6994 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
6995 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 6996}
d2b2c203
DJ		 6997
6998int
6999i386_elf_section_type (const char *str, size_t len)
7000{
7001 if (flag_code == CODE_64BIT
7002 && len == sizeof ("unwind") - 1
7003 && strncmp (str, "unwind", 6) == 0)
7004 return SHT_X86_64_UNWIND;
7005
7006 return -1;
7007}
bb41ade5
AM		 7008
7009#ifdef TE_PE
7010void
7011tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7012{
7013 expressionS expr;
7014
7015 expr.X_op = O_secrel;
7016 expr.X_add_symbol = symbol;
7017 expr.X_add_number = 0;
7018 emit_expr (&expr, size);
7019}
7020#endif
3b22753a
L		 7021
7022#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7023/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7024
7025int
7026x86_64_section_letter (int letter, char **ptr_msg)
7027{
7028 if (flag_code == CODE_64BIT)
7029 {
7030 if (letter == 'l')
7031 return SHF_X86_64_LARGE;
7032
7033 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7034 }
7035 else
7036 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7037 return -1;
7038}
7039
7040int
7041x86_64_section_word (char *str, size_t len)
7042{
7043 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7044 return SHF_X86_64_LARGE;
7045
7046 return -1;
7047}
7048
7049static void
7050handle_large_common (int small ATTRIBUTE_UNUSED)
7051{
7052 if (flag_code != CODE_64BIT)
7053 {
7054 s_comm_internal (0, elf_common_parse);
7055 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7056 }
7057 else
7058 {
7059 static segT lbss_section;
7060 asection *saved_com_section_ptr = elf_com_section_ptr;
7061 asection *saved_bss_section = bss_section;
7062
7063 if (lbss_section == NULL)
7064 {
7065 flagword applicable;
7066 segT seg = now_seg;
7067 subsegT subseg = now_subseg;
7068
7069 /* The .lbss section is for local .largecomm symbols. */
7070 lbss_section = subseg_new (".lbss", 0);
7071 applicable = bfd_applicable_section_flags (stdoutput);
7072 bfd_set_section_flags (stdoutput, lbss_section,
7073 applicable & SEC_ALLOC);
7074 seg_info (lbss_section)->bss = 1;
7075
7076 subseg_set (seg, subseg);
7077 }
7078
7079 elf_com_section_ptr = &_bfd_elf_large_com_section;
7080 bss_section = lbss_section;
7081
7082 s_comm_internal (0, elf_common_parse);
7083
7084 elf_com_section_ptr = saved_com_section_ptr;
7085 bss_section = saved_bss_section;
7086 }
7087}
7088#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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