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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
e3bb37b5
L		 58static void set_code_flag (int);
59static void set_16bit_gcc_code_flag (int);
60static void set_intel_syntax (int);
db51cc60 61static void set_allow_index_reg (int);
e3bb37b5 62static void set_cpu_arch (int);
6482c264 63#ifdef TE_PE
e3bb37b5 64static void pe_directive_secrel (int);
6482c264 65#endif
e3bb37b5
L		 66static void signed_cons (int);
67static char *output_invalid (int c);
68static int i386_operand (char *);
69static int i386_intel_operand (char *, int);
70static const reg_entry *parse_register (char *, char **);
71static char *parse_insn (char *, char *);
72static char *parse_operands (char *, const char *);
73static void swap_operands (void);
4d456e3d 74static void swap_2_operands (int, int);
e3bb37b5
L		 75static void optimize_imm (void);
76static void optimize_disp (void);
77static int match_template (void);
78static int check_string (void);
79static int process_suffix (void);
80static int check_byte_reg (void);
81static int check_long_reg (void);
82static int check_qword_reg (void);
83static int check_word_reg (void);
84static int finalize_imm (void);
85f10a01 85static void process_drex (void);
e3bb37b5
L		 86static int process_operands (void);
87static const seg_entry *build_modrm_byte (void);
88static void output_insn (void);
89static void output_imm (fragS *, offsetT);
90static void output_disp (fragS *, offsetT);
29b0f896 91#ifndef I386COFF
e3bb37b5 92static void s_bss (int);
252b5132 93#endif
17d4e2a2
L		 94#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
95static void handle_large_common (int small ATTRIBUTE_UNUSED);
96#endif
252b5132 97
a847613f 98static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 99
252b5132 100/* 'md_assemble ()' gathers together information and puts it into a
47926f60 101 i386_insn. */
252b5132 102
520dc8e8
AM		 103union i386_op
104 {
105 expressionS *disps;
106 expressionS *imms;
107 const reg_entry *regs;
108 };
109
252b5132
RH		 110struct _i386_insn
111 {
47926f60 112 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 113 template tm;
114
115 /* SUFFIX holds the instruction mnemonic suffix if given.
116 (e.g. 'l' for 'movl') */
117 char suffix;
118
47926f60 119 /* OPERANDS gives the number of given operands. */
252b5132
RH		 120 unsigned int operands;
121
122 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
123 of given register, displacement, memory operands and immediate
47926f60 124 operands. */
252b5132
RH		 125 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
126
127 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 128 use OP[i] for the corresponding operand. */
40fb9820 129 i386_operand_type types[MAX_OPERANDS];
252b5132 130
520dc8e8
AM		 131 /* Displacement expression, immediate expression, or register for each
132 operand. */
133 union i386_op op[MAX_OPERANDS];
252b5132 134
3e73aa7c
JH		 135 /* Flags for operands. */
136 unsigned int flags[MAX_OPERANDS];
137#define Operand_PCrel 1
138
252b5132 139 /* Relocation type for operand */
f86103b7 140 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 141
252b5132
RH		 142 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
143 the base index byte below. */
144 const reg_entry *base_reg;
145 const reg_entry *index_reg;
146 unsigned int log2_scale_factor;
147
148 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 149 explicit segment overrides are given. */
ce8a8b2f 150 const seg_entry *seg[2];
252b5132
RH		 151
152 /* PREFIX holds all the given prefix opcodes (usually null).
153 PREFIXES is the number of prefix opcodes. */
154 unsigned int prefixes;
155 unsigned char prefix[MAX_PREFIXES];
156
157 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 158 addressing modes of this insn are encoded. DREX is the byte
159 added by the SSE5 instructions. */
252b5132
RH		 160
161 modrm_byte rm;
3e73aa7c 162 rex_byte rex;
252b5132 163 sib_byte sib;
85f10a01 164 drex_byte drex;
252b5132
RH		 165 };
166
167typedef struct _i386_insn i386_insn;
168
169/* List of chars besides those in app.c:symbol_chars that can start an
170 operand. Used to prevent the scrubber eating vital white-space. */
32137342 171const char extra_symbol_chars[] = "*%-(["
252b5132 172#ifdef LEX_AT
32137342
NC		 173 "@"
174#endif
175#ifdef LEX_QM
176 "?"
252b5132 177#endif
32137342 178 ;
252b5132 179
29b0f896
AM		 180#if (defined (TE_I386AIX) \
181 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 182 && !defined (TE_GNU) \
29b0f896 183 && !defined (TE_LINUX) \
32137342 184 && !defined (TE_NETWARE) \
29b0f896
AM		 185 && !defined (TE_FreeBSD) \
186 && !defined (TE_NetBSD)))
252b5132 187/* This array holds the chars that always start a comment. If the
b3b91714
AM		 188 pre-processor is disabled, these aren't very useful. The option
189 --divide will remove '/' from this list. */
190const char *i386_comment_chars = "#/";
191#define SVR4_COMMENT_CHARS 1
252b5132 192#define PREFIX_SEPARATOR '\\'
252b5132 193
b3b91714
AM		 194#else
195const char *i386_comment_chars = "#";
196#define PREFIX_SEPARATOR '/'
197#endif
198
252b5132
RH		 199/* This array holds the chars that only start a comment at the beginning of
200 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 201 .line and .file directives will appear in the pre-processed output.
202 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 203 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 204 #NO_APP at the beginning of its output.
205 Also note that comments started like this one will always work if
252b5132 206 '/' isn't otherwise defined. */
b3b91714 207const char line_comment_chars[] = "#/";
252b5132 208
63a0b638 209const char line_separator_chars[] = ";";
252b5132 210
ce8a8b2f
AM		 211/* Chars that can be used to separate mant from exp in floating point
212 nums. */
252b5132
RH		 213const char EXP_CHARS[] = "eE";
214
ce8a8b2f
AM		 215/* Chars that mean this number is a floating point constant
216 As in 0f12.456
217 or 0d1.2345e12. */
252b5132
RH		 218const char FLT_CHARS[] = "fFdDxX";
219
ce8a8b2f 220/* Tables for lexical analysis. */
252b5132
RH		 221static char mnemonic_chars[256];
222static char register_chars[256];
223static char operand_chars[256];
224static char identifier_chars[256];
225static char digit_chars[256];
226
ce8a8b2f 227/* Lexical macros. */
252b5132
RH		 228#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
229#define is_operand_char(x) (operand_chars[(unsigned char) x])
230#define is_register_char(x) (register_chars[(unsigned char) x])
231#define is_space_char(x) ((x) == ' ')
232#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
233#define is_digit_char(x) (digit_chars[(unsigned char) x])
234
0234cb7c 235/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 236static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
237
238/* md_assemble() always leaves the strings it's passed unaltered. To
239 effect this we maintain a stack of saved characters that we've smashed
240 with '\0's (indicating end of strings for various sub-fields of the
47926f60 241 assembler instruction). */
252b5132 242static char save_stack[32];
ce8a8b2f 243static char *save_stack_p;
252b5132
RH		 244#define END_STRING_AND_SAVE(s) \
245 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
246#define RESTORE_END_STRING(s) \
247 do { *(s) = *--save_stack_p; } while (0)
248
47926f60 249/* The instruction we're assembling. */
252b5132
RH		 250static i386_insn i;
251
252/* Possible templates for current insn. */
253static const templates *current_templates;
254
31b2323c
L		 255/* Per instruction expressionS buffers: max displacements & immediates. */
256static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
257static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 258
47926f60
KH		 259/* Current operand we are working on. */
260static int this_operand;
252b5132 261
3e73aa7c
JH		 262/* We support four different modes. FLAG_CODE variable is used to distinguish
263 these. */
264
265enum flag_code {
266 CODE_32BIT,
267 CODE_16BIT,
268 CODE_64BIT };
f3c180ae 269#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 270
271static enum flag_code flag_code;
4fa24527 272static unsigned int object_64bit;
3e73aa7c
JH		 273static int use_rela_relocations = 0;
274
275/* The names used to print error messages. */
b77a7acd 276static const char *flag_code_names[] =
3e73aa7c
JH		 277 {
278 "32",
279 "16",
280 "64"
281 };
252b5132 282
47926f60
KH		 283/* 1 for intel syntax,
284 0 if att syntax. */
285static int intel_syntax = 0;
252b5132 286
47926f60
KH		 287/* 1 if register prefix % not required. */
288static int allow_naked_reg = 0;
252b5132 289
db51cc60
L		 290/* 1 if fake index register, eiz/riz, is allowed . */
291static int allow_index_reg = 0;
292
2ca3ace5
L		 293/* Register prefix used for error message. */
294static const char *register_prefix = "%";
295
47926f60
KH		 296/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299static char stackop_size = '\0';
eecb386c 300
12b55ccc
L		 301/* Non-zero to optimize code alignment. */
302int optimize_align_code = 1;
303
47926f60
KH		 304/* Non-zero to quieten some warnings. */
305static int quiet_warnings = 0;
a38cf1db 306
47926f60
KH		 307/* CPU name. */
308static const char *cpu_arch_name = NULL;
5c6af06e 309static const char *cpu_sub_arch_name = NULL;
a38cf1db 310
47926f60 311/* CPU feature flags. */
40fb9820
L		 312static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
313
314/* Bitwise NOT of cpu_arch_flags. */
315static i386_cpu_flags cpu_arch_flags_not;
a38cf1db 316
ccc9c027
L		 317/* If we have selected a cpu we are generating instructions for. */
318static int cpu_arch_tune_set = 0;
319
9103f4f4
L		 320/* Cpu we are generating instructions for. */
321static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
322
323/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 324static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 325
ccc9c027
L		 326/* CPU instruction set architecture used. */
327static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
328
9103f4f4 329/* CPU feature flags of instruction set architecture used. */
40fb9820 330static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 331
fddf5b5b
AM		 332/* If set, conditional jumps are not automatically promoted to handle
333 larger than a byte offset. */
334static unsigned int no_cond_jump_promotion = 0;
335
29b0f896 336/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 337static symbolS *GOT_symbol;
29b0f896 338
a4447b93
RH		 339/* The dwarf2 return column, adjusted for 32 or 64 bit. */
340unsigned int x86_dwarf2_return_column;
341
342/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
343int x86_cie_data_alignment;
344
252b5132 345/* Interface to relax_segment.
fddf5b5b
AM		 346 There are 3 major relax states for 386 jump insns because the
347 different types of jumps add different sizes to frags when we're
348 figuring out what sort of jump to choose to reach a given label. */
252b5132 349
47926f60 350/* Types. */
93c2a809
AM		 351#define UNCOND_JUMP 0
352#define COND_JUMP 1
353#define COND_JUMP86 2
fddf5b5b 354
47926f60 355/* Sizes. */
252b5132
RH		 356#define CODE16 1
357#define SMALL 0
29b0f896 358#define SMALL16 (SMALL | CODE16)
252b5132 359#define BIG 2
29b0f896 360#define BIG16 (BIG | CODE16)
252b5132
RH		 361
362#ifndef INLINE
363#ifdef __GNUC__
364#define INLINE __inline__
365#else
366#define INLINE
367#endif
368#endif
369
fddf5b5b
AM		 370#define ENCODE_RELAX_STATE(type, size) \
371 ((relax_substateT) (((type) << 2) | (size)))
372#define TYPE_FROM_RELAX_STATE(s) \
373 ((s) >> 2)
374#define DISP_SIZE_FROM_RELAX_STATE(s) \
375 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 376
377/* This table is used by relax_frag to promote short jumps to long
378 ones where necessary. SMALL (short) jumps may be promoted to BIG
379 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
380 don't allow a short jump in a 32 bit code segment to be promoted to
381 a 16 bit offset jump because it's slower (requires data size
382 prefix), and doesn't work, unless the destination is in the bottom
383 64k of the code segment (The top 16 bits of eip are zeroed). */
384
385const relax_typeS md_relax_table[] =
386{
24eab124
AM		 387 /* The fields are:
388 1) most positive reach of this state,
389 2) most negative reach of this state,
93c2a809 390 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 391 4) which index into the table to try if we can't fit into this one. */
252b5132 392
fddf5b5b 393 /* UNCOND_JUMP states. */
93c2a809
AM		 394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
396 /* dword jmp adds 4 bytes to frag:
397 0 extra opcode bytes, 4 displacement bytes. */
252b5132 398 {0, 0, 4, 0},
93c2a809
AM		 399 /* word jmp adds 2 byte2 to frag:
400 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 401 {0, 0, 2, 0},
402
93c2a809
AM		 403 /* COND_JUMP states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
406 /* dword conditionals adds 5 bytes to frag:
407 1 extra opcode byte, 4 displacement bytes. */
408 {0, 0, 5, 0},
fddf5b5b 409 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 410 1 extra opcode byte, 2 displacement bytes. */
411 {0, 0, 3, 0},
412
413 /* COND_JUMP86 states. */
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
416 /* dword conditionals adds 5 bytes to frag:
417 1 extra opcode byte, 4 displacement bytes. */
418 {0, 0, 5, 0},
419 /* word conditionals add 4 bytes to frag:
420 1 displacement byte and a 3 byte long branch insn. */
421 {0, 0, 4, 0}
252b5132
RH		 422};
423
9103f4f4
L		 424static const arch_entry cpu_arch[] =
425{
426 {"generic32", PROCESSOR_GENERIC32,
40fb9820 427 CPU_GENERIC32_FLAGS },
9103f4f4 428 {"generic64", PROCESSOR_GENERIC64,
40fb9820 429 CPU_GENERIC64_FLAGS },
9103f4f4 430 {"i8086", PROCESSOR_UNKNOWN,
40fb9820 431 CPU_NONE_FLAGS },
9103f4f4 432 {"i186", PROCESSOR_UNKNOWN,
40fb9820 433 CPU_I186_FLAGS },
9103f4f4 434 {"i286", PROCESSOR_UNKNOWN,
40fb9820 435 CPU_I286_FLAGS },
76bc74dc 436 {"i386", PROCESSOR_I386,
40fb9820 437 CPU_I386_FLAGS },
9103f4f4 438 {"i486", PROCESSOR_I486,
40fb9820 439 CPU_I486_FLAGS },
9103f4f4 440 {"i586", PROCESSOR_PENTIUM,
40fb9820 441 CPU_I586_FLAGS },
9103f4f4 442 {"i686", PROCESSOR_PENTIUMPRO,
40fb9820 443 CPU_I686_FLAGS },
9103f4f4 444 {"pentium", PROCESSOR_PENTIUM,
40fb9820 445 CPU_I586_FLAGS },
9103f4f4 446 {"pentiumpro",PROCESSOR_PENTIUMPRO,
40fb9820 447 CPU_I686_FLAGS },
9103f4f4 448 {"pentiumii", PROCESSOR_PENTIUMPRO,
40fb9820 449 CPU_P2_FLAGS },
9103f4f4 450 {"pentiumiii",PROCESSOR_PENTIUMPRO,
40fb9820 451 CPU_P3_FLAGS },
9103f4f4 452 {"pentium4", PROCESSOR_PENTIUM4,
40fb9820 453 CPU_P4_FLAGS },
9103f4f4 454 {"prescott", PROCESSOR_NOCONA,
40fb9820 455 CPU_CORE_FLAGS },
9103f4f4 456 {"nocona", PROCESSOR_NOCONA,
40fb9820 457 CPU_NOCONA_FLAGS },
ef05d495 458 {"yonah", PROCESSOR_CORE,
40fb9820 459 CPU_CORE_FLAGS },
ef05d495 460 {"core", PROCESSOR_CORE,
40fb9820 461 CPU_CORE_FLAGS },
ef05d495 462 {"merom", PROCESSOR_CORE2,
40fb9820 463 CPU_CORE2_FLAGS },
ef05d495 464 {"core2", PROCESSOR_CORE2,
40fb9820 465 CPU_CORE2_FLAGS },
9103f4f4 466 {"k6", PROCESSOR_K6,
40fb9820 467 CPU_K6_FLAGS },
9103f4f4 468 {"k6_2", PROCESSOR_K6,
40fb9820 469 CPU_K6_2_FLAGS },
9103f4f4 470 {"athlon", PROCESSOR_ATHLON,
40fb9820 471 CPU_ATHLON_FLAGS },
9103f4f4 472 {"sledgehammer", PROCESSOR_K8,
40fb9820 473 CPU_K8_FLAGS },
9103f4f4 474 {"opteron", PROCESSOR_K8,
40fb9820 475 CPU_K8_FLAGS },
9103f4f4 476 {"k8", PROCESSOR_K8,
40fb9820 477 CPU_K8_FLAGS },
050dfa73 478 {"amdfam10", PROCESSOR_AMDFAM10,
40fb9820 479 CPU_AMDFAM10_FLAGS },
9103f4f4 480 {".mmx", PROCESSOR_UNKNOWN,
40fb9820 481 CPU_MMX_FLAGS },
9103f4f4 482 {".sse", PROCESSOR_UNKNOWN,
40fb9820 483 CPU_SSE_FLAGS },
9103f4f4 484 {".sse2", PROCESSOR_UNKNOWN,
40fb9820 485 CPU_SSE2_FLAGS },
9103f4f4 486 {".sse3", PROCESSOR_UNKNOWN,
40fb9820 487 CPU_SSE3_FLAGS },
ef05d495 488 {".ssse3", PROCESSOR_UNKNOWN,
40fb9820 489 CPU_SSSE3_FLAGS },
42903f7f 490 {".sse4.1", PROCESSOR_UNKNOWN,
40fb9820 491 CPU_SSE4_1_FLAGS },
381d071f 492 {".sse4.2", PROCESSOR_UNKNOWN,
40fb9820 493 CPU_SSE4_2_FLAGS },
381d071f 494 {".sse4", PROCESSOR_UNKNOWN,
40fb9820 495 CPU_SSE4_2_FLAGS },
9103f4f4 496 {".3dnow", PROCESSOR_UNKNOWN,
40fb9820 497 CPU_3DNOW_FLAGS },
9103f4f4 498 {".3dnowa", PROCESSOR_UNKNOWN,
40fb9820 499 CPU_3DNOWA_FLAGS },
9103f4f4 500 {".padlock", PROCESSOR_UNKNOWN,
40fb9820 501 CPU_PADLOCK_FLAGS },
9103f4f4 502 {".pacifica", PROCESSOR_UNKNOWN,
40fb9820 503 CPU_SVME_FLAGS },
9103f4f4 504 {".svme", PROCESSOR_UNKNOWN,
40fb9820 505 CPU_SVME_FLAGS },
050dfa73 506 {".sse4a", PROCESSOR_UNKNOWN,
40fb9820 507 CPU_SSE4A_FLAGS },
050dfa73 508 {".abm", PROCESSOR_UNKNOWN,
40fb9820 509 CPU_ABM_FLAGS },
85f10a01
MM		 510 {".sse5", PROCESSOR_UNKNOWN,
511 CPU_SSE5_FLAGS },
e413e4e9
AM		 512};
513
29b0f896
AM		 514const pseudo_typeS md_pseudo_table[] =
515{
516#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
517 {"align", s_align_bytes, 0},
518#else
519 {"align", s_align_ptwo, 0},
520#endif
521 {"arch", set_cpu_arch, 0},
522#ifndef I386COFF
523 {"bss", s_bss, 0},
524#endif
525 {"ffloat", float_cons, 'f'},
526 {"dfloat", float_cons, 'd'},
527 {"tfloat", float_cons, 'x'},
528 {"value", cons, 2},
d182319b 529 {"slong", signed_cons, 4},
29b0f896
AM		 530 {"noopt", s_ignore, 0},
531 {"optim", s_ignore, 0},
532 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
533 {"code16", set_code_flag, CODE_16BIT},
534 {"code32", set_code_flag, CODE_32BIT},
535 {"code64", set_code_flag, CODE_64BIT},
536 {"intel_syntax", set_intel_syntax, 1},
537 {"att_syntax", set_intel_syntax, 0},
db51cc60
L		 538 {"allow_index_reg", set_allow_index_reg, 1},
539 {"disallow_index_reg", set_allow_index_reg, 0},
3b22753a
L		 540#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
541 {"largecomm", handle_large_common, 0},
07a53e5c 542#else
e3bb37b5 543 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 544 {"loc", dwarf2_directive_loc, 0},
545 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 546#endif
6482c264
NC		 547#ifdef TE_PE
548 {"secrel32", pe_directive_secrel, 0},
549#endif
29b0f896
AM		 550 {0, 0, 0}
551};
552
553/* For interface with expression (). */
554extern char *input_line_pointer;
555
556/* Hash table for instruction mnemonic lookup. */
557static struct hash_control *op_hash;
558
559/* Hash table for register lookup. */
560static struct hash_control *reg_hash;
561\f
252b5132 562void
e3bb37b5 563i386_align_code (fragS *fragP, int count)
252b5132 564{
ce8a8b2f
AM		 565 /* Various efficient no-op patterns for aligning code labels.
566 Note: Don't try to assemble the instructions in the comments.
567 0L and 0w are not legal. */
252b5132
RH		 568 static const char f32_1[] =
569 {0x90}; /* nop */
570 static const char f32_2[] =
ccc9c027 571 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 572 static const char f32_3[] =
573 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
574 static const char f32_4[] =
575 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
576 static const char f32_5[] =
577 {0x90, /* nop */
578 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
579 static const char f32_6[] =
580 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
581 static const char f32_7[] =
582 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
583 static const char f32_8[] =
584 {0x90, /* nop */
585 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
586 static const char f32_9[] =
587 {0x89,0xf6, /* movl %esi,%esi */
588 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
589 static const char f32_10[] =
590 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
591 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
592 static const char f32_11[] =
593 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
594 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
595 static const char f32_12[] =
596 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
597 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
598 static const char f32_13[] =
599 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
601 static const char f32_14[] =
602 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
603 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 604 static const char f16_3[] =
605 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 606 static const char f16_4[] =
607 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
608 static const char f16_5[] =
609 {0x90, /* nop */
610 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
611 static const char f16_6[] =
612 {0x89,0xf6, /* mov %si,%si */
613 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
614 static const char f16_7[] =
615 {0x8d,0x74,0x00, /* lea 0(%si),%si */
616 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
617 static const char f16_8[] =
618 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
619 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 620 static const char jump_31[] =
621 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
622 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
623 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
624 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 625 static const char *const f32_patt[] = {
626 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 627 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 628 };
629 static const char *const f16_patt[] = {
76bc74dc 630 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 631 };
ccc9c027
L		 632 /* nopl (%[re]ax) */
633 static const char alt_3[] =
634 {0x0f,0x1f,0x00};
635 /* nopl 0(%[re]ax) */
636 static const char alt_4[] =
637 {0x0f,0x1f,0x40,0x00};
638 /* nopl 0(%[re]ax,%[re]ax,1) */
639 static const char alt_5[] =
640 {0x0f,0x1f,0x44,0x00,0x00};
641 /* nopw 0(%[re]ax,%[re]ax,1) */
642 static const char alt_6[] =
643 {0x66,0x0f,0x1f,0x44,0x00,0x00};
644 /* nopl 0L(%[re]ax) */
645 static const char alt_7[] =
646 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
647 /* nopl 0L(%[re]ax,%[re]ax,1) */
648 static const char alt_8[] =
649 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
650 /* nopw 0L(%[re]ax,%[re]ax,1) */
651 static const char alt_9[] =
652 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
653 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
654 static const char alt_10[] =
655 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* data16
657 nopw %cs:0L(%[re]ax,%[re]ax,1) */
658 static const char alt_long_11[] =
659 {0x66,
660 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
661 /* data16
662 data16
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_12[] =
665 {0x66,
666 0x66,
667 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
668 /* data16
669 data16
670 data16
671 nopw %cs:0L(%[re]ax,%[re]ax,1) */
672 static const char alt_long_13[] =
673 {0x66,
674 0x66,
675 0x66,
676 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
677 /* data16
678 data16
679 data16
680 data16
681 nopw %cs:0L(%[re]ax,%[re]ax,1) */
682 static const char alt_long_14[] =
683 {0x66,
684 0x66,
685 0x66,
686 0x66,
687 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
688 /* data16
689 data16
690 data16
691 data16
692 data16
693 nopw %cs:0L(%[re]ax,%[re]ax,1) */
694 static const char alt_long_15[] =
695 {0x66,
696 0x66,
697 0x66,
698 0x66,
699 0x66,
700 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
701 /* nopl 0(%[re]ax,%[re]ax,1)
702 nopw 0(%[re]ax,%[re]ax,1) */
703 static const char alt_short_11[] =
704 {0x0f,0x1f,0x44,0x00,0x00,
705 0x66,0x0f,0x1f,0x44,0x00,0x00};
706 /* nopw 0(%[re]ax,%[re]ax,1)
707 nopw 0(%[re]ax,%[re]ax,1) */
708 static const char alt_short_12[] =
709 {0x66,0x0f,0x1f,0x44,0x00,0x00,
710 0x66,0x0f,0x1f,0x44,0x00,0x00};
711 /* nopw 0(%[re]ax,%[re]ax,1)
712 nopl 0L(%[re]ax) */
713 static const char alt_short_13[] =
714 {0x66,0x0f,0x1f,0x44,0x00,0x00,
715 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
716 /* nopl 0L(%[re]ax)
717 nopl 0L(%[re]ax) */
718 static const char alt_short_14[] =
719 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
720 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
721 /* nopl 0L(%[re]ax)
722 nopl 0L(%[re]ax,%[re]ax,1) */
723 static const char alt_short_15[] =
724 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
725 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
726 static const char *const alt_short_patt[] = {
727 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
728 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
729 alt_short_14, alt_short_15
730 };
731 static const char *const alt_long_patt[] = {
732 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
733 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
734 alt_long_14, alt_long_15
735 };
252b5132 736
76bc74dc
L		 737 /* Only align for at least a positive non-zero boundary. */
738 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 739 return;
3e73aa7c 740
ccc9c027
L		 741 /* We need to decide which NOP sequence to use for 32bit and
742 64bit. When -mtune= is used:
4eed87de 743
76bc74dc
L		 744 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
745 PROCESSOR_GENERIC32, f32_patt will be used.
746 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
747 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
748 alt_long_patt will be used.
749 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
750 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 751
76bc74dc
L		 752 When -mtune= isn't used, alt_long_patt will be used if
753 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
754 be used.
ccc9c027
L		 755
756 When -march= or .arch is used, we can't use anything beyond
757 cpu_arch_isa_flags. */
758
759 if (flag_code == CODE_16BIT)
760 {
ccc9c027 761 if (count > 8)
33fef721 762 {
76bc74dc
L		 763 memcpy (fragP->fr_literal + fragP->fr_fix,
764 jump_31, count);
765 /* Adjust jump offset. */
766 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 767 }
76bc74dc
L		 768 else
769 memcpy (fragP->fr_literal + fragP->fr_fix,
770 f16_patt[count - 1], count);
252b5132 771 }
33fef721 772 else
ccc9c027
L		 773 {
774 const char *const *patt = NULL;
775
776 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
777 {
778 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
779 switch (cpu_arch_tune)
780 {
781 case PROCESSOR_UNKNOWN:
782 /* We use cpu_arch_isa_flags to check if we SHOULD
783 optimize for Cpu686. */
40fb9820 784 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 785 patt = alt_long_patt;
ccc9c027
L		 786 else
787 patt = f32_patt;
788 break;
ccc9c027
L		 789 case PROCESSOR_PENTIUMPRO:
790 case PROCESSOR_PENTIUM4:
791 case PROCESSOR_NOCONA:
ef05d495 792 case PROCESSOR_CORE:
76bc74dc
L		 793 case PROCESSOR_CORE2:
794 case PROCESSOR_GENERIC64:
795 patt = alt_long_patt;
796 break;
ccc9c027
L		 797 case PROCESSOR_K6:
798 case PROCESSOR_ATHLON:
799 case PROCESSOR_K8:
4eed87de 800 case PROCESSOR_AMDFAM10:
ccc9c027
L		 801 patt = alt_short_patt;
802 break;
76bc74dc 803 case PROCESSOR_I386:
ccc9c027
L		 804 case PROCESSOR_I486:
805 case PROCESSOR_PENTIUM:
806 case PROCESSOR_GENERIC32:
807 patt = f32_patt;
808 break;
4eed87de 809 }
ccc9c027
L		 810 }
811 else
812 {
813 switch (cpu_arch_tune)
814 {
815 case PROCESSOR_UNKNOWN:
816 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
817 PROCESSOR_UNKNOWN. */
818 abort ();
819 break;
820
76bc74dc 821 case PROCESSOR_I386:
ccc9c027
L		 822 case PROCESSOR_I486:
823 case PROCESSOR_PENTIUM:
ccc9c027
L		 824 case PROCESSOR_K6:
825 case PROCESSOR_ATHLON:
826 case PROCESSOR_K8:
4eed87de 827 case PROCESSOR_AMDFAM10:
ccc9c027
L		 828 case PROCESSOR_GENERIC32:
829 /* We use cpu_arch_isa_flags to check if we CAN optimize
830 for Cpu686. */
40fb9820 831 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 832 patt = alt_short_patt;
833 else
834 patt = f32_patt;
835 break;
76bc74dc
L		 836 case PROCESSOR_PENTIUMPRO:
837 case PROCESSOR_PENTIUM4:
838 case PROCESSOR_NOCONA:
839 case PROCESSOR_CORE:
ef05d495 840 case PROCESSOR_CORE2:
40fb9820 841 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 842 patt = alt_long_patt;
843 else
844 patt = f32_patt;
845 break;
846 case PROCESSOR_GENERIC64:
76bc74dc 847 patt = alt_long_patt;
ccc9c027 848 break;
4eed87de 849 }
ccc9c027
L		 850 }
851
76bc74dc
L		 852 if (patt == f32_patt)
853 {
854 /* If the padding is less than 15 bytes, we use the normal
855 ones. Otherwise, we use a jump instruction and adjust
856 its offset. */
857 if (count < 15)
858 memcpy (fragP->fr_literal + fragP->fr_fix,
859 patt[count - 1], count);
860 else
861 {
862 memcpy (fragP->fr_literal + fragP->fr_fix,
863 jump_31, count);
864 /* Adjust jump offset. */
865 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
866 }
867 }
868 else
869 {
870 /* Maximum length of an instruction is 15 byte. If the
871 padding is greater than 15 bytes and we don't use jump,
872 we have to break it into smaller pieces. */
873 int padding = count;
874 while (padding > 15)
875 {
876 padding -= 15;
877 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
878 patt [14], 15);
879 }
880
881 if (padding)
882 memcpy (fragP->fr_literal + fragP->fr_fix,
883 patt [padding - 1], padding);
884 }
ccc9c027 885 }
33fef721 886 fragP->fr_var = count;
252b5132
RH		 887}
888
c6fb90c8
L		 889static INLINE int
890uints_all_zero (const unsigned int *x, unsigned int size)
40fb9820 891{
c6fb90c8
L		 892 switch (size)
893 {
894 case 3:
895 if (x[2])
896 return 0;
897 case 2:
898 if (x[1])
899 return 0;
900 case 1:
901 return !x[0];
902 default:
903 abort ();
904 }
40fb9820
L		 905}
906
c6fb90c8
L		 907static INLINE void
908uints_set (unsigned int *x, unsigned int v, unsigned int size)
40fb9820 909{
c6fb90c8
L		 910 switch (size)
911 {
912 case 3:
913 x[2] = v;
914 case 2:
915 x[1] = v;
916 case 1:
917 x[0] = v;
918 break;
919 default:
920 abort ();
921 }
922}
40fb9820 923
c6fb90c8
L		 924static INLINE int
925uints_equal (const unsigned int *x, const unsigned int *y,
926 unsigned int size)
927{
928 switch (size)
929 {
930 case 3:
931 if (x[2] != y [2])
932 return 0;
933 case 2:
934 if (x[1] != y [1])
935 return 0;
936 case 1:
937 return x[0] == y [0];
938 break;
939 default:
940 abort ();
941 }
942}
40fb9820 943
c6fb90c8
L		 944#define UINTS_ALL_ZERO(x) \
945 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
946#define UINTS_SET(x, v) \
947 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
948#define UINTS_CLEAR(x) \
949 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
950#define UINTS_EQUAL(x, y) \
951 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
952
953static INLINE int
954cpu_flags_check_cpu64 (i386_cpu_flags f)
955{
956 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
957 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 958}
959
c6fb90c8 960static INLINE i386_cpu_flags
40fb9820
L		 961cpu_flags_not (i386_cpu_flags x)
962{
c6fb90c8
L		 963 switch (ARRAY_SIZE (x.array))
964 {
965 case 3:
966 x.array [2] = ~x.array [2];
967 case 2:
968 x.array [1] = ~x.array [1];
969 case 1:
970 x.array [0] = ~x.array [0];
971 break;
972 default:
973 abort ();
974 }
40fb9820
L		 975
976#ifdef CpuUnused
977 x.bitfield.unused = 0;
978#endif
979
980 return x;
981}
982
c6fb90c8
L		 983static INLINE i386_cpu_flags
984cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 985{
c6fb90c8
L		 986 switch (ARRAY_SIZE (x.array))
987 {
988 case 3:
989 x.array [2] &= y.array [2];
990 case 2:
991 x.array [1] &= y.array [1];
992 case 1:
993 x.array [0] &= y.array [0];
994 break;
995 default:
996 abort ();
997 }
998 return x;
999}
40fb9820 1000
c6fb90c8
L		 1001static INLINE i386_cpu_flags
1002cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1003{
c6fb90c8 1004 switch (ARRAY_SIZE (x.array))
40fb9820 1005 {
c6fb90c8
L		 1006 case 3:
1007 x.array [2] |= y.array [2];
1008 case 2:
1009 x.array [1] |= y.array [1];
1010 case 1:
1011 x.array [0] |= y.array [0];
40fb9820
L		 1012 break;
1013 default:
1014 abort ();
1015 }
40fb9820
L		 1016 return x;
1017}
1018
1019static int
1020cpu_flags_match (i386_cpu_flags x)
1021{
1022 i386_cpu_flags not = cpu_arch_flags_not;
1023
1024 not.bitfield.cpu64 = 1;
1025 not.bitfield.cpuno64 = 1;
1026
1027 x.bitfield.cpu64 = 0;
1028 x.bitfield.cpuno64 = 0;
1029
c6fb90c8
L		 1030 not = cpu_flags_and (x, not);
1031 return UINTS_ALL_ZERO (not);
40fb9820
L		 1032}
1033
c6fb90c8
L		 1034static INLINE i386_operand_type
1035operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1036{
c6fb90c8
L		 1037 switch (ARRAY_SIZE (x.array))
1038 {
1039 case 3:
1040 x.array [2] &= y.array [2];
1041 case 2:
1042 x.array [1] &= y.array [1];
1043 case 1:
1044 x.array [0] &= y.array [0];
1045 break;
1046 default:
1047 abort ();
1048 }
1049 return x;
40fb9820
L		 1050}
1051
c6fb90c8
L		 1052static INLINE i386_operand_type
1053operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1054{
c6fb90c8 1055 switch (ARRAY_SIZE (x.array))
40fb9820 1056 {
c6fb90c8
L		 1057 case 3:
1058 x.array [2] |= y.array [2];
1059 case 2:
1060 x.array [1] |= y.array [1];
1061 case 1:
1062 x.array [0] |= y.array [0];
40fb9820
L		 1063 break;
1064 default:
1065 abort ();
1066 }
c6fb90c8
L		 1067 return x;
1068}
40fb9820 1069
c6fb90c8
L		 1070static INLINE i386_operand_type
1071operand_type_xor (i386_operand_type x, i386_operand_type y)
1072{
1073 switch (ARRAY_SIZE (x.array))
1074 {
1075 case 3:
1076 x.array [2] ^= y.array [2];
1077 case 2:
1078 x.array [1] ^= y.array [1];
1079 case 1:
1080 x.array [0] ^= y.array [0];
1081 break;
1082 default:
1083 abort ();
1084 }
40fb9820
L		 1085 return x;
1086}
1087
1088static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1089static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1090static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1091static const i386_operand_type reg16_inoutportreg
1092 = OPERAND_TYPE_REG16_INOUTPORTREG;
1093static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1094static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1095static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1096static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1097static const i386_operand_type anydisp
1098 = OPERAND_TYPE_ANYDISP;
40fb9820
L		 1099static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1100static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1101static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1102static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1103static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1104static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1105static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1106static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1107static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1108static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1109
1110enum operand_type
1111{
1112 reg,
40fb9820
L		 1113 imm,
1114 disp,
1115 anymem
1116};
1117
c6fb90c8 1118static INLINE int
40fb9820
L		 1119operand_type_check (i386_operand_type t, enum operand_type c)
1120{
1121 switch (c)
1122 {
1123 case reg:
1124 return (t.bitfield.reg8
1125 || t.bitfield.reg16
1126 || t.bitfield.reg32
1127 || t.bitfield.reg64);
1128
40fb9820
L		 1129 case imm:
1130 return (t.bitfield.imm8
1131 || t.bitfield.imm8s
1132 || t.bitfield.imm16
1133 || t.bitfield.imm32
1134 || t.bitfield.imm32s
1135 || t.bitfield.imm64);
1136
1137 case disp:
1138 return (t.bitfield.disp8
1139 || t.bitfield.disp16
1140 || t.bitfield.disp32
1141 || t.bitfield.disp32s
1142 || t.bitfield.disp64);
1143
1144 case anymem:
1145 return (t.bitfield.disp8
1146 || t.bitfield.disp16
1147 || t.bitfield.disp32
1148 || t.bitfield.disp32s
1149 || t.bitfield.disp64
1150 || t.bitfield.baseindex);
1151
1152 default:
1153 abort ();
1154 }
1155}
1156
c6fb90c8 1157static INLINE int
40fb9820
L		 1158operand_type_match (i386_operand_type overlap,
1159 i386_operand_type given)
1160{
1161 i386_operand_type temp = overlap;
1162
1163 temp.bitfield.jumpabsolute = 0;
c6fb90c8 1164 if (UINTS_ALL_ZERO (temp))
40fb9820
L		 1165 return 0;
1166
1167 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1168 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1169}
1170
1171/* If given types r0 and r1 are registers they must be of the same type
1172 unless the expected operand type register overlap is null.
1173 Note that Acc in a template matches every size of reg. */
1174
c6fb90c8 1175static INLINE int
40fb9820
L		 1176operand_type_register_match (i386_operand_type m0,
1177 i386_operand_type g0,
1178 i386_operand_type t0,
1179 i386_operand_type m1,
1180 i386_operand_type g1,
1181 i386_operand_type t1)
1182{
1183 if (!operand_type_check (g0, reg))
1184 return 1;
1185
1186 if (!operand_type_check (g1, reg))
1187 return 1;
1188
1189 if (g0.bitfield.reg8 == g1.bitfield.reg8
1190 && g0.bitfield.reg16 == g1.bitfield.reg16
1191 && g0.bitfield.reg32 == g1.bitfield.reg32
1192 && g0.bitfield.reg64 == g1.bitfield.reg64)
1193 return 1;
1194
1195 if (m0.bitfield.acc)
1196 {
1197 t0.bitfield.reg8 = 1;
1198 t0.bitfield.reg16 = 1;
1199 t0.bitfield.reg32 = 1;
1200 t0.bitfield.reg64 = 1;
1201 }
1202
1203 if (m1.bitfield.acc)
1204 {
1205 t1.bitfield.reg8 = 1;
1206 t1.bitfield.reg16 = 1;
1207 t1.bitfield.reg32 = 1;
1208 t1.bitfield.reg64 = 1;
1209 }
1210
1211 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1212 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1213 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1214 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1215}
1216
252b5132 1217static INLINE unsigned int
40fb9820 1218mode_from_disp_size (i386_operand_type t)
252b5132 1219{
40fb9820
L		 1220 if (t.bitfield.disp8)
1221 return 1;
1222 else if (t.bitfield.disp16
1223 || t.bitfield.disp32
1224 || t.bitfield.disp32s)
1225 return 2;
1226 else
1227 return 0;
252b5132
RH		 1228}
1229
1230static INLINE int
e3bb37b5 1231fits_in_signed_byte (offsetT num)
252b5132
RH		 1232{
1233 return (num >= -128) && (num <= 127);
47926f60 1234}
252b5132
RH		 1235
1236static INLINE int
e3bb37b5 1237fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1238{
1239 return (num & 0xff) == num;
47926f60 1240}
252b5132
RH		 1241
1242static INLINE int
e3bb37b5 1243fits_in_unsigned_word (offsetT num)
252b5132
RH		 1244{
1245 return (num & 0xffff) == num;
47926f60 1246}
252b5132
RH		 1247
1248static INLINE int
e3bb37b5 1249fits_in_signed_word (offsetT num)
252b5132
RH		 1250{
1251 return (-32768 <= num) && (num <= 32767);
47926f60 1252}
2a962e6d 1253
3e73aa7c 1254static INLINE int
e3bb37b5 1255fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1256{
1257#ifndef BFD64
1258 return 1;
1259#else
1260 return (!(((offsetT) -1 << 31) & num)
1261 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1262#endif
1263} /* fits_in_signed_long() */
2a962e6d 1264
3e73aa7c 1265static INLINE int
e3bb37b5 1266fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1267{
1268#ifndef BFD64
1269 return 1;
1270#else
1271 return (num & (((offsetT) 2 << 31) - 1)) == num;
1272#endif
1273} /* fits_in_unsigned_long() */
252b5132 1274
40fb9820 1275static i386_operand_type
e3bb37b5 1276smallest_imm_type (offsetT num)
252b5132 1277{
40fb9820
L		 1278 i386_operand_type t;
1279
c6fb90c8 1280 UINTS_CLEAR (t);
40fb9820
L		 1281 t.bitfield.imm64 = 1;
1282
1283 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1284 {
1285 /* This code is disabled on the 486 because all the Imm1 forms
1286 in the opcode table are slower on the i486. They're the
1287 versions with the implicitly specified single-position
1288 displacement, which has another syntax if you really want to
1289 use that form. */
40fb9820
L		 1290 t.bitfield.imm1 = 1;
1291 t.bitfield.imm8 = 1;
1292 t.bitfield.imm8s = 1;
1293 t.bitfield.imm16 = 1;
1294 t.bitfield.imm32 = 1;
1295 t.bitfield.imm32s = 1;
1296 }
1297 else if (fits_in_signed_byte (num))
1298 {
1299 t.bitfield.imm8 = 1;
1300 t.bitfield.imm8s = 1;
1301 t.bitfield.imm16 = 1;
1302 t.bitfield.imm32 = 1;
1303 t.bitfield.imm32s = 1;
1304 }
1305 else if (fits_in_unsigned_byte (num))
1306 {
1307 t.bitfield.imm8 = 1;
1308 t.bitfield.imm16 = 1;
1309 t.bitfield.imm32 = 1;
1310 t.bitfield.imm32s = 1;
1311 }
1312 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1313 {
1314 t.bitfield.imm16 = 1;
1315 t.bitfield.imm32 = 1;
1316 t.bitfield.imm32s = 1;
1317 }
1318 else if (fits_in_signed_long (num))
1319 {
1320 t.bitfield.imm32 = 1;
1321 t.bitfield.imm32s = 1;
1322 }
1323 else if (fits_in_unsigned_long (num))
1324 t.bitfield.imm32 = 1;
1325
1326 return t;
47926f60 1327}
252b5132 1328
847f7ad4 1329static offsetT
e3bb37b5 1330offset_in_range (offsetT val, int size)
847f7ad4 1331{
508866be 1332 addressT mask;
ba2adb93 1333
847f7ad4
AM		 1334 switch (size)
1335 {
508866be
L		 1336 case 1: mask = ((addressT) 1 << 8) - 1; break;
1337 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1338 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1339#ifdef BFD64
1340 case 8: mask = ((addressT) 2 << 63) - 1; break;
1341#endif
47926f60 1342 default: abort ();
847f7ad4
AM		 1343 }
1344
ba2adb93 1345 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1346 if (!use_rela_relocations)
1347 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1348 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1349
47926f60 1350 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1351 {
1352 char buf1[40], buf2[40];
1353
1354 sprint_value (buf1, val);
1355 sprint_value (buf2, val & mask);
1356 as_warn (_("%s shortened to %s"), buf1, buf2);
1357 }
1358 return val & mask;
1359}
1360
252b5132
RH		 1361/* Returns 0 if attempting to add a prefix where one from the same
1362 class already exists, 1 if non rep/repne added, 2 if rep/repne
1363 added. */
1364static int
e3bb37b5 1365add_prefix (unsigned int prefix)
252b5132
RH		 1366{
1367 int ret = 1;
b1905489 1368 unsigned int q;
252b5132 1369
29b0f896
AM		 1370 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1371 && flag_code == CODE_64BIT)
b1905489 1372 {
161a04f6
L		 1373 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1374 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1375 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1376 ret = 0;
1377 q = REX_PREFIX;
1378 }
3e73aa7c 1379 else
b1905489
JB		 1380 {
1381 switch (prefix)
1382 {
1383 default:
1384 abort ();
1385
1386 case CS_PREFIX_OPCODE:
1387 case DS_PREFIX_OPCODE:
1388 case ES_PREFIX_OPCODE:
1389 case FS_PREFIX_OPCODE:
1390 case GS_PREFIX_OPCODE:
1391 case SS_PREFIX_OPCODE:
1392 q = SEG_PREFIX;
1393 break;
1394
1395 case REPNE_PREFIX_OPCODE:
1396 case REPE_PREFIX_OPCODE:
1397 ret = 2;
1398 /* fall thru */
1399 case LOCK_PREFIX_OPCODE:
1400 q = LOCKREP_PREFIX;
1401 break;
1402
1403 case FWAIT_OPCODE:
1404 q = WAIT_PREFIX;
1405 break;
1406
1407 case ADDR_PREFIX_OPCODE:
1408 q = ADDR_PREFIX;
1409 break;
1410
1411 case DATA_PREFIX_OPCODE:
1412 q = DATA_PREFIX;
1413 break;
1414 }
1415 if (i.prefix[q] != 0)
1416 ret = 0;
1417 }
252b5132 1418
b1905489 1419 if (ret)
252b5132 1420 {
b1905489
JB		 1421 if (!i.prefix[q])
1422 ++i.prefixes;
1423 i.prefix[q] |= prefix;
252b5132 1424 }
b1905489
JB		 1425 else
1426 as_bad (_("same type of prefix used twice"));
252b5132 1427
252b5132
RH		 1428 return ret;
1429}
1430
1431static void
e3bb37b5 1432set_code_flag (int value)
eecb386c 1433{
3e73aa7c 1434 flag_code = value;
40fb9820
L		 1435 if (flag_code == CODE_64BIT)
1436 {
1437 cpu_arch_flags.bitfield.cpu64 = 1;
1438 cpu_arch_flags.bitfield.cpuno64 = 0;
1439 cpu_arch_flags_not.bitfield.cpu64 = 0;
1440 cpu_arch_flags_not.bitfield.cpuno64 = 1;
1441 }
1442 else
1443 {
1444 cpu_arch_flags.bitfield.cpu64 = 0;
1445 cpu_arch_flags.bitfield.cpuno64 = 1;
1446 cpu_arch_flags_not.bitfield.cpu64 = 1;
1447 cpu_arch_flags_not.bitfield.cpuno64 = 0;
1448 }
1449 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1450 {
1451 as_bad (_("64bit mode not supported on this CPU."));
1452 }
40fb9820 1453 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1454 {
1455 as_bad (_("32bit mode not supported on this CPU."));
1456 }
eecb386c
AM		 1457 stackop_size = '\0';
1458}
1459
1460static void
e3bb37b5 1461set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1462{
3e73aa7c 1463 flag_code = new_code_flag;
40fb9820
L		 1464 if (flag_code != CODE_16BIT)
1465 abort ();
1466 cpu_arch_flags.bitfield.cpu64 = 0;
1467 cpu_arch_flags.bitfield.cpuno64 = 1;
1468 cpu_arch_flags_not.bitfield.cpu64 = 1;
1469 cpu_arch_flags_not.bitfield.cpuno64 = 0;
9306ca4a 1470 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1471}
1472
1473static void
e3bb37b5 1474set_intel_syntax (int syntax_flag)
252b5132
RH		 1475{
1476 /* Find out if register prefixing is specified. */
1477 int ask_naked_reg = 0;
1478
1479 SKIP_WHITESPACE ();
29b0f896 1480 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1481 {
1482 char *string = input_line_pointer;
1483 int e = get_symbol_end ();
1484
47926f60 1485 if (strcmp (string, "prefix") == 0)
252b5132 1486 ask_naked_reg = 1;
47926f60 1487 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1488 ask_naked_reg = -1;
1489 else
d0b47220 1490 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1491 *input_line_pointer = e;
1492 }
1493 demand_empty_rest_of_line ();
c3332e24 1494
252b5132
RH		 1495 intel_syntax = syntax_flag;
1496
1497 if (ask_naked_reg == 0)
f86103b7
AM		 1498 allow_naked_reg = (intel_syntax
1499 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1500 else
1501 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1502
e4a3b5a4 1503 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1504 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1505 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1506}
1507
db51cc60
L		 1508static void
1509set_allow_index_reg (int flag)
1510{
1511 allow_index_reg = flag;
1512}
1513
e413e4e9 1514static void
e3bb37b5 1515set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1516{
47926f60 1517 SKIP_WHITESPACE ();
e413e4e9 1518
29b0f896 1519 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1520 {
1521 char *string = input_line_pointer;
1522 int e = get_symbol_end ();
9103f4f4 1523 unsigned int i;
40fb9820 1524 i386_cpu_flags flags;
e413e4e9 1525
9103f4f4 1526 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1527 {
1528 if (strcmp (string, cpu_arch[i].name) == 0)
1529 {
5c6af06e
JB		 1530 if (*string != '.')
1531 {
1532 cpu_arch_name = cpu_arch[i].name;
1533 cpu_sub_arch_name = NULL;
40fb9820
L		 1534 cpu_arch_flags = cpu_arch[i].flags;
1535 if (flag_code == CODE_64BIT)
1536 {
1537 cpu_arch_flags.bitfield.cpu64 = 1;
1538 cpu_arch_flags.bitfield.cpuno64 = 0;
1539 }
1540 else
1541 {
1542 cpu_arch_flags.bitfield.cpu64 = 0;
1543 cpu_arch_flags.bitfield.cpuno64 = 1;
1544 }
1545 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
ccc9c027 1546 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1547 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1548 if (!cpu_arch_tune_set)
1549 {
1550 cpu_arch_tune = cpu_arch_isa;
1551 cpu_arch_tune_flags = cpu_arch_isa_flags;
1552 }
5c6af06e
JB		 1553 break;
1554 }
40fb9820 1555
c6fb90c8
L		 1556 flags = cpu_flags_or (cpu_arch_flags,
1557 cpu_arch[i].flags);
1558 if (!UINTS_EQUAL (flags, cpu_arch_flags))
5c6af06e
JB		 1559 {
1560 cpu_sub_arch_name = cpu_arch[i].name;
40fb9820
L		 1561 cpu_arch_flags = flags;
1562 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
5c6af06e
JB		 1563 }
1564 *input_line_pointer = e;
1565 demand_empty_rest_of_line ();
1566 return;
e413e4e9
AM		 1567 }
1568 }
9103f4f4 1569 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1570 as_bad (_("no such architecture: `%s'"), string);
1571
1572 *input_line_pointer = e;
1573 }
1574 else
1575 as_bad (_("missing cpu architecture"));
1576
fddf5b5b
AM		 1577 no_cond_jump_promotion = 0;
1578 if (*input_line_pointer == ','
29b0f896 1579 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1580 {
1581 char *string = ++input_line_pointer;
1582 int e = get_symbol_end ();
1583
1584 if (strcmp (string, "nojumps") == 0)
1585 no_cond_jump_promotion = 1;
1586 else if (strcmp (string, "jumps") == 0)
1587 ;
1588 else
1589 as_bad (_("no such architecture modifier: `%s'"), string);
1590
1591 *input_line_pointer = e;
1592 }
1593
e413e4e9
AM		 1594 demand_empty_rest_of_line ();
1595}
1596
b9d79e03
JH		 1597unsigned long
1598i386_mach ()
1599{
1600 if (!strcmp (default_arch, "x86_64"))
1601 return bfd_mach_x86_64;
1602 else if (!strcmp (default_arch, "i386"))
1603 return bfd_mach_i386_i386;
1604 else
1605 as_fatal (_("Unknown architecture"));
1606}
b9d79e03 1607\f
252b5132
RH		 1608void
1609md_begin ()
1610{
1611 const char *hash_err;
1612
40fb9820
L		 1613 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1614
47926f60 1615 /* Initialize op_hash hash table. */
252b5132
RH		 1616 op_hash = hash_new ();
1617
1618 {
29b0f896
AM		 1619 const template *optab;
1620 templates *core_optab;
252b5132 1621
47926f60
KH		 1622 /* Setup for loop. */
1623 optab = i386_optab;
252b5132
RH		 1624 core_optab = (templates *) xmalloc (sizeof (templates));
1625 core_optab->start = optab;
1626
1627 while (1)
1628 {
1629 ++optab;
1630 if (optab->name == NULL
1631 || strcmp (optab->name, (optab - 1)->name) != 0)
1632 {
1633 /* different name --> ship out current template list;
47926f60 1634 add to hash table; & begin anew. */
252b5132
RH		 1635 core_optab->end = optab;
1636 hash_err = hash_insert (op_hash,
1637 (optab - 1)->name,
1638 (PTR) core_optab);
1639 if (hash_err)
1640 {
252b5132
RH		 1641 as_fatal (_("Internal Error: Can't hash %s: %s"),
1642 (optab - 1)->name,
1643 hash_err);
1644 }
1645 if (optab->name == NULL)
1646 break;
1647 core_optab = (templates *) xmalloc (sizeof (templates));
1648 core_optab->start = optab;
1649 }
1650 }
1651 }
1652
47926f60 1653 /* Initialize reg_hash hash table. */
252b5132
RH		 1654 reg_hash = hash_new ();
1655 {
29b0f896 1656 const reg_entry *regtab;
c3fe08fa 1657 unsigned int regtab_size = i386_regtab_size;
252b5132 1658
c3fe08fa 1659 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1660 {
1661 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1662 if (hash_err)
3e73aa7c
JH		 1663 as_fatal (_("Internal Error: Can't hash %s: %s"),
1664 regtab->reg_name,
1665 hash_err);
252b5132
RH		 1666 }
1667 }
1668
47926f60 1669 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1670 {
29b0f896
AM		 1671 int c;
1672 char *p;
252b5132
RH		 1673
1674 for (c = 0; c < 256; c++)
1675 {
3882b010 1676 if (ISDIGIT (c))
252b5132
RH		 1677 {
1678 digit_chars[c] = c;
1679 mnemonic_chars[c] = c;
1680 register_chars[c] = c;
1681 operand_chars[c] = c;
1682 }
3882b010 1683 else if (ISLOWER (c))
252b5132
RH		 1684 {
1685 mnemonic_chars[c] = c;
1686 register_chars[c] = c;
1687 operand_chars[c] = c;
1688 }
3882b010 1689 else if (ISUPPER (c))
252b5132 1690 {
3882b010 1691 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1692 register_chars[c] = mnemonic_chars[c];
1693 operand_chars[c] = c;
1694 }
1695
3882b010 1696 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1697 identifier_chars[c] = c;
1698 else if (c >= 128)
1699 {
1700 identifier_chars[c] = c;
1701 operand_chars[c] = c;
1702 }
1703 }
1704
1705#ifdef LEX_AT
1706 identifier_chars['@'] = '@';
32137342
NC		 1707#endif
1708#ifdef LEX_QM
1709 identifier_chars['?'] = '?';
1710 operand_chars['?'] = '?';
252b5132 1711#endif
252b5132 1712 digit_chars['-'] = '-';
791fe849 1713 mnemonic_chars['-'] = '-';
0003779b 1714 mnemonic_chars['.'] = '.';
252b5132
RH		 1715 identifier_chars['_'] = '_';
1716 identifier_chars['.'] = '.';
1717
1718 for (p = operand_special_chars; *p != '\0'; p++)
1719 operand_chars[(unsigned char) *p] = *p;
1720 }
1721
1722#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1723 if (IS_ELF)
252b5132
RH		 1724 {
1725 record_alignment (text_section, 2);
1726 record_alignment (data_section, 2);
1727 record_alignment (bss_section, 2);
1728 }
1729#endif
a4447b93
RH		 1730
1731 if (flag_code == CODE_64BIT)
1732 {
1733 x86_dwarf2_return_column = 16;
1734 x86_cie_data_alignment = -8;
1735 }
1736 else
1737 {
1738 x86_dwarf2_return_column = 8;
1739 x86_cie_data_alignment = -4;
1740 }
252b5132
RH		 1741}
1742
1743void
e3bb37b5 1744i386_print_statistics (FILE *file)
252b5132
RH		 1745{
1746 hash_print_statistics (file, "i386 opcode", op_hash);
1747 hash_print_statistics (file, "i386 register", reg_hash);
1748}
1749\f
252b5132
RH		 1750#ifdef DEBUG386
1751
ce8a8b2f 1752/* Debugging routines for md_assemble. */
e3bb37b5 1753static void pte (template *);
40fb9820 1754static void pt (i386_operand_type);
e3bb37b5
L		 1755static void pe (expressionS *);
1756static void ps (symbolS *);
252b5132
RH		 1757
1758static void
e3bb37b5 1759pi (char *line, i386_insn *x)
252b5132 1760{
09f131f2 1761 unsigned int i;
252b5132
RH		 1762
1763 fprintf (stdout, "%s: template ", line);
1764 pte (&x->tm);
09f131f2
JH		 1765 fprintf (stdout, " address: base %s index %s scale %x\n",
1766 x->base_reg ? x->base_reg->reg_name : "none",
1767 x->index_reg ? x->index_reg->reg_name : "none",
1768 x->log2_scale_factor);
1769 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1770 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1771 fprintf (stdout, " sib: base %x index %x scale %x\n",
1772 x->sib.base, x->sib.index, x->sib.scale);
1773 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1774 (x->rex & REX_W) != 0,
1775 (x->rex & REX_R) != 0,
1776 (x->rex & REX_X) != 0,
1777 (x->rex & REX_B) != 0);
85f10a01
MM		 1778 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1779 x->drex.reg, x->drex.rex);
252b5132
RH		 1780 for (i = 0; i < x->operands; i++)
1781 {
1782 fprintf (stdout, " #%d: ", i + 1);
1783 pt (x->types[i]);
1784 fprintf (stdout, "\n");
40fb9820
L		 1785 if (x->types[i].bitfield.reg8
1786 || x->types[i].bitfield.reg16
1787 || x->types[i].bitfield.reg32
1788 || x->types[i].bitfield.reg64
1789 || x->types[i].bitfield.regmmx
1790 || x->types[i].bitfield.regxmm
1791 || x->types[i].bitfield.sreg2
1792 || x->types[i].bitfield.sreg3
1793 || x->types[i].bitfield.control
1794 || x->types[i].bitfield.debug
1795 || x->types[i].bitfield.test)
520dc8e8 1796 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 1797 if (operand_type_check (x->types[i], imm))
520dc8e8 1798 pe (x->op[i].imms);
40fb9820 1799 if (operand_type_check (x->types[i], disp))
520dc8e8 1800 pe (x->op[i].disps);
252b5132
RH		 1801 }
1802}
1803
1804static void
e3bb37b5 1805pte (template *t)
252b5132 1806{
09f131f2 1807 unsigned int i;
252b5132 1808 fprintf (stdout, " %d operands ", t->operands);
47926f60 1809 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1810 if (t->extension_opcode != None)
1811 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 1812 if (t->opcode_modifier.d)
252b5132 1813 fprintf (stdout, "D");
40fb9820 1814 if (t->opcode_modifier.w)
252b5132
RH		 1815 fprintf (stdout, "W");
1816 fprintf (stdout, "\n");
1817 for (i = 0; i < t->operands; i++)
1818 {
1819 fprintf (stdout, " #%d type ", i + 1);
1820 pt (t->operand_types[i]);
1821 fprintf (stdout, "\n");
1822 }
1823}
1824
1825static void
e3bb37b5 1826pe (expressionS *e)
252b5132 1827{
24eab124 1828 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1829 fprintf (stdout, " add_number %ld (%lx)\n",
1830 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1831 if (e->X_add_symbol)
1832 {
1833 fprintf (stdout, " add_symbol ");
1834 ps (e->X_add_symbol);
1835 fprintf (stdout, "\n");
1836 }
1837 if (e->X_op_symbol)
1838 {
1839 fprintf (stdout, " op_symbol ");
1840 ps (e->X_op_symbol);
1841 fprintf (stdout, "\n");
1842 }
1843}
1844
1845static void
e3bb37b5 1846ps (symbolS *s)
252b5132
RH		 1847{
1848 fprintf (stdout, "%s type %s%s",
1849 S_GET_NAME (s),
1850 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1851 segment_name (S_GET_SEGMENT (s)));
1852}
1853
7b81dfbb 1854static struct type_name
252b5132 1855 {
40fb9820
L		 1856 i386_operand_type mask;
1857 const char *name;
252b5132 1858 }
7b81dfbb 1859const type_names[] =
252b5132 1860{
40fb9820
L		 1861 { OPERAND_TYPE_REG8, "r8" },
1862 { OPERAND_TYPE_REG16, "r16" },
1863 { OPERAND_TYPE_REG32, "r32" },
1864 { OPERAND_TYPE_REG64, "r64" },
1865 { OPERAND_TYPE_IMM8, "i8" },
1866 { OPERAND_TYPE_IMM8, "i8s" },
1867 { OPERAND_TYPE_IMM16, "i16" },
1868 { OPERAND_TYPE_IMM32, "i32" },
1869 { OPERAND_TYPE_IMM32S, "i32s" },
1870 { OPERAND_TYPE_IMM64, "i64" },
1871 { OPERAND_TYPE_IMM1, "i1" },
1872 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1873 { OPERAND_TYPE_DISP8, "d8" },
1874 { OPERAND_TYPE_DISP16, "d16" },
1875 { OPERAND_TYPE_DISP32, "d32" },
1876 { OPERAND_TYPE_DISP32S, "d32s" },
1877 { OPERAND_TYPE_DISP64, "d64" },
1878 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1879 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1880 { OPERAND_TYPE_CONTROL, "control reg" },
1881 { OPERAND_TYPE_TEST, "test reg" },
1882 { OPERAND_TYPE_DEBUG, "debug reg" },
1883 { OPERAND_TYPE_FLOATREG, "FReg" },
1884 { OPERAND_TYPE_FLOATACC, "FAcc" },
1885 { OPERAND_TYPE_SREG2, "SReg2" },
1886 { OPERAND_TYPE_SREG3, "SReg3" },
1887 { OPERAND_TYPE_ACC, "Acc" },
1888 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1889 { OPERAND_TYPE_REGMMX, "rMMX" },
1890 { OPERAND_TYPE_REGXMM, "rXMM" },
1891 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 1892};
1893
1894static void
40fb9820 1895pt (i386_operand_type t)
252b5132 1896{
40fb9820 1897 unsigned int j;
c6fb90c8 1898 i386_operand_type a;
252b5132 1899
40fb9820 1900 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 1901 {
1902 a = operand_type_and (t, type_names[j].mask);
1903 if (!UINTS_ALL_ZERO (a))
1904 fprintf (stdout, "%s, ", type_names[j].name);
1905 }
252b5132
RH		 1906 fflush (stdout);
1907}
1908
1909#endif /* DEBUG386 */
1910\f
252b5132 1911static bfd_reloc_code_real_type
3956db08 1912reloc (unsigned int size,
64e74474
AM		 1913 int pcrel,
1914 int sign,
1915 bfd_reloc_code_real_type other)
252b5132 1916{
47926f60 1917 if (other != NO_RELOC)
3956db08
JB		 1918 {
1919 reloc_howto_type *reloc;
1920
1921 if (size == 8)
1922 switch (other)
1923 {
64e74474
AM		 1924 case BFD_RELOC_X86_64_GOT32:
1925 return BFD_RELOC_X86_64_GOT64;
1926 break;
1927 case BFD_RELOC_X86_64_PLTOFF64:
1928 return BFD_RELOC_X86_64_PLTOFF64;
1929 break;
1930 case BFD_RELOC_X86_64_GOTPC32:
1931 other = BFD_RELOC_X86_64_GOTPC64;
1932 break;
1933 case BFD_RELOC_X86_64_GOTPCREL:
1934 other = BFD_RELOC_X86_64_GOTPCREL64;
1935 break;
1936 case BFD_RELOC_X86_64_TPOFF32:
1937 other = BFD_RELOC_X86_64_TPOFF64;
1938 break;
1939 case BFD_RELOC_X86_64_DTPOFF32:
1940 other = BFD_RELOC_X86_64_DTPOFF64;
1941 break;
1942 default:
1943 break;
3956db08 1944 }
e05278af
JB		 1945
1946 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1947 if (size == 4 && flag_code != CODE_64BIT)
1948 sign = -1;
1949
3956db08
JB		 1950 reloc = bfd_reloc_type_lookup (stdoutput, other);
1951 if (!reloc)
1952 as_bad (_("unknown relocation (%u)"), other);
1953 else if (size != bfd_get_reloc_size (reloc))
1954 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1955 bfd_get_reloc_size (reloc),
1956 size);
1957 else if (pcrel && !reloc->pc_relative)
1958 as_bad (_("non-pc-relative relocation for pc-relative field"));
1959 else if ((reloc->complain_on_overflow == complain_overflow_signed
1960 && !sign)
1961 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1962 && sign > 0))
3956db08
JB		 1963 as_bad (_("relocated field and relocation type differ in signedness"));
1964 else
1965 return other;
1966 return NO_RELOC;
1967 }
252b5132
RH		 1968
1969 if (pcrel)
1970 {
3e73aa7c 1971 if (!sign)
3956db08 1972 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1973 switch (size)
1974 {
1975 case 1: return BFD_RELOC_8_PCREL;
1976 case 2: return BFD_RELOC_16_PCREL;
1977 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1978 case 8: return BFD_RELOC_64_PCREL;
252b5132 1979 }
3956db08 1980 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1981 }
1982 else
1983 {
3956db08 1984 if (sign > 0)
e5cb08ac 1985 switch (size)
3e73aa7c
JH		 1986 {
1987 case 4: return BFD_RELOC_X86_64_32S;
1988 }
1989 else
1990 switch (size)
1991 {
1992 case 1: return BFD_RELOC_8;
1993 case 2: return BFD_RELOC_16;
1994 case 4: return BFD_RELOC_32;
1995 case 8: return BFD_RELOC_64;
1996 }
3956db08
JB		 1997 as_bad (_("cannot do %s %u byte relocation"),
1998 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1999 }
2000
bfb32b52 2001 abort ();
252b5132
RH		 2002 return BFD_RELOC_NONE;
2003}
2004
47926f60
KH		 2005/* Here we decide which fixups can be adjusted to make them relative to
2006 the beginning of the section instead of the symbol. Basically we need
2007 to make sure that the dynamic relocations are done correctly, so in
2008 some cases we force the original symbol to be used. */
2009
252b5132 2010int
e3bb37b5 2011tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2012{
6d249963 2013#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2014 if (!IS_ELF)
31312f95
AM		 2015 return 1;
2016
a161fe53
AM		 2017 /* Don't adjust pc-relative references to merge sections in 64-bit
2018 mode. */
2019 if (use_rela_relocations
2020 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2021 && fixP->fx_pcrel)
252b5132 2022 return 0;
31312f95 2023
8d01d9a9
AJ		 2024 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2025 and changed later by validate_fix. */
2026 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2027 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2028 return 0;
2029
ce8a8b2f 2030 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2031 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2032 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2033 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2034 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2035 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2036 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2037 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2038 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2039 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2040 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2041 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2042 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2043 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2044 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2045 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2046 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2047 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2048 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2049 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2050 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2051 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2052 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2053 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2054 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2055 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2056 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2057 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2058 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2059 return 0;
31312f95 2060#endif
252b5132
RH		 2061 return 1;
2062}
252b5132 2063
b4cac588 2064static int
e3bb37b5 2065intel_float_operand (const char *mnemonic)
252b5132 2066{
9306ca4a
JB		 2067 /* Note that the value returned is meaningful only for opcodes with (memory)
2068 operands, hence the code here is free to improperly handle opcodes that
2069 have no operands (for better performance and smaller code). */
2070
2071 if (mnemonic[0] != 'f')
2072 return 0; /* non-math */
2073
2074 switch (mnemonic[1])
2075 {
2076 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2077 the fs segment override prefix not currently handled because no
2078 call path can make opcodes without operands get here */
2079 case 'i':
2080 return 2 /* integer op */;
2081 case 'l':
2082 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2083 return 3; /* fldcw/fldenv */
2084 break;
2085 case 'n':
2086 if (mnemonic[2] != 'o' /* fnop */)
2087 return 3; /* non-waiting control op */
2088 break;
2089 case 'r':
2090 if (mnemonic[2] == 's')
2091 return 3; /* frstor/frstpm */
2092 break;
2093 case 's':
2094 if (mnemonic[2] == 'a')
2095 return 3; /* fsave */
2096 if (mnemonic[2] == 't')
2097 {
2098 switch (mnemonic[3])
2099 {
2100 case 'c': /* fstcw */
2101 case 'd': /* fstdw */
2102 case 'e': /* fstenv */
2103 case 's': /* fsts[gw] */
2104 return 3;
2105 }
2106 }
2107 break;
2108 case 'x':
2109 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2110 return 0; /* fxsave/fxrstor are not really math ops */
2111 break;
2112 }
252b5132 2113
9306ca4a 2114 return 1;
252b5132
RH		 2115}
2116
2117/* This is the guts of the machine-dependent assembler. LINE points to a
2118 machine dependent instruction. This function is supposed to emit
2119 the frags/bytes it assembles to. */
2120
2121void
2122md_assemble (line)
2123 char *line;
2124{
40fb9820 2125 unsigned int j;
252b5132
RH		 2126 char mnemonic[MAX_MNEM_SIZE];
2127
47926f60 2128 /* Initialize globals. */
252b5132
RH		 2129 memset (&i, '\0', sizeof (i));
2130 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2131 i.reloc[j] = NO_RELOC;
252b5132
RH		 2132 memset (disp_expressions, '\0', sizeof (disp_expressions));
2133 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2134 save_stack_p = save_stack;
252b5132
RH		 2135
2136 /* First parse an instruction mnemonic & call i386_operand for the operands.
2137 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2138 start of a (possibly prefixed) mnemonic. */
252b5132 2139
29b0f896
AM		 2140 line = parse_insn (line, mnemonic);
2141 if (line == NULL)
2142 return;
252b5132 2143
29b0f896
AM		 2144 line = parse_operands (line, mnemonic);
2145 if (line == NULL)
2146 return;
252b5132 2147
29b0f896
AM		 2148 /* Now we've parsed the mnemonic into a set of templates, and have the
2149 operands at hand. */
2150
2151 /* All intel opcodes have reversed operands except for "bound" and
2152 "enter". We also don't reverse intersegment "jmp" and "call"
2153 instructions with 2 immediate operands so that the immediate segment
050dfa73 2154 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2155 if (intel_syntax
2156 && i.operands > 1
29b0f896 2157 && (strcmp (mnemonic, "bound") != 0)
30123838 2158 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2159 && !(operand_type_check (i.types[0], imm)
2160 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2161 swap_operands ();
2162
ec56d5c0
JB		 2163 /* The order of the immediates should be reversed
2164 for 2 immediates extrq and insertq instructions */
2165 if (i.imm_operands == 2
2166 && (strcmp (mnemonic, "extrq") == 0
2167 || strcmp (mnemonic, "insertq") == 0))
2168 swap_2_operands (0, 1);
2169
29b0f896
AM		 2170 if (i.imm_operands)
2171 optimize_imm ();
2172
b300c311
L		 2173 /* Don't optimize displacement for movabs since it only takes 64bit
2174 displacement. */
2175 if (i.disp_operands
2176 && (flag_code != CODE_64BIT
2177 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2178 optimize_disp ();
2179
2180 /* Next, we find a template that matches the given insn,
2181 making sure the overlap of the given operands types is consistent
2182 with the template operand types. */
252b5132 2183
29b0f896
AM		 2184 if (!match_template ())
2185 return;
252b5132 2186
cd61ebfe
AM		 2187 if (intel_syntax)
2188 {
2189 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
2190 if (SYSV386_COMPAT
2191 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 2192 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 2193
2194 /* Zap movzx and movsx suffix. The suffix may have been set from
2195 "word ptr" or "byte ptr" on the source operand, but we'll use
2196 the suffix later to choose the destination register. */
2197 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 2198 {
2199 if (i.reg_operands < 2
2200 && !i.suffix
40fb9820
L		 2201 && (!i.tm.opcode_modifier.no_bsuf
2202 || !i.tm.opcode_modifier.no_wsuf
2203 || !i.tm.opcode_modifier.no_lsuf
2204 || !i.tm.opcode_modifier.no_ssuf
2205 || !i.tm.opcode_modifier.no_xsuf
2206 || !i.tm.opcode_modifier.no_qsuf))
9306ca4a
JB		 2207 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2208
2209 i.suffix = 0;
2210 }
cd61ebfe 2211 }
24eab124 2212
40fb9820 2213 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2214 if (!add_prefix (FWAIT_OPCODE))
2215 return;
252b5132 2216
29b0f896 2217 /* Check string instruction segment overrides. */
40fb9820 2218 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2219 {
2220 if (!check_string ())
5dd0794d 2221 return;
29b0f896 2222 }
5dd0794d 2223
29b0f896
AM		 2224 if (!process_suffix ())
2225 return;
e413e4e9 2226
29b0f896
AM		 2227 /* Make still unresolved immediate matches conform to size of immediate
2228 given in i.suffix. */
2229 if (!finalize_imm ())
2230 return;
252b5132 2231
40fb9820 2232 if (i.types[0].bitfield.imm1)
29b0f896 2233 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2234
40fb9820 2235 for (j = 0; j < 3; j++)
c6fb90c8
L		 2236 if (i.types[j].bitfield.inoutportreg
2237 || i.types[j].bitfield.shiftcount
2238 || i.types[j].bitfield.acc
2239 || i.types[j].bitfield.floatacc)
40fb9820
L		 2240 i.reg_operands--;
2241
2242 if (i.tm.opcode_modifier.immext)
29b0f896 2243 {
02fc3089
L		 2244 expressionS *exp;
2245
40fb9820 2246 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
ca164297 2247 {
b7d9ef37 2248 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 2249 operands with an opcode suffix which is coded in the same
2250 place as an 8-bit immediate field would be. Here we check
2251 those operands and remove them afterwards. */
2252 unsigned int x;
2253
a4622f40 2254 for (x = 0; x < i.operands; x++)
ca164297 2255 if (i.op[x].regs->reg_num != x)
a540244d
L		 2256 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2257 register_prefix,
2258 i.op[x].regs->reg_name,
2259 x + 1,
2260 i.tm.name);
ca164297
L		 2261 i.operands = 0;
2262 }
2263
29b0f896
AM		 2264 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2265 opcode suffix which is coded in the same place as an 8-bit
2266 immediate field would be. Here we fake an 8-bit immediate
85f10a01
MM		 2267 operand from the opcode suffix stored in tm.extension_opcode.
2268 SSE5 also uses this encoding, for some of its 3 argument
2269 instructions. */
252b5132 2270
85f10a01
MM		 2271 assert (i.imm_operands == 0
2272 && (i.operands <= 2
2273 || (i.tm.cpu_flags.bitfield.cpusse5
2274 && i.operands <= 3)));
252b5132 2275
29b0f896
AM		 2276 exp = &im_expressions[i.imm_operands++];
2277 i.op[i.operands].imms = exp;
c6fb90c8 2278 UINTS_CLEAR (i.types[i.operands]);
40fb9820
L		 2279 i.types[i.operands].bitfield.imm8 = 1;
2280 i.operands++;
29b0f896
AM		 2281 exp->X_op = O_constant;
2282 exp->X_add_number = i.tm.extension_opcode;
2283 i.tm.extension_opcode = None;
2284 }
252b5132 2285
29b0f896
AM		 2286 /* For insns with operands there are more diddles to do to the opcode. */
2287 if (i.operands)
2288 {
2289 if (!process_operands ())
2290 return;
2291 }
40fb9820 2292 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2293 {
2294 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2295 as_warn (_("translating to `%sp'"), i.tm.name);
2296 }
252b5132 2297
29b0f896
AM		 2298 /* Handle conversion of 'int $3' --> special int3 insn. */
2299 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2300 {
2301 i.tm.base_opcode = INT3_OPCODE;
2302 i.imm_operands = 0;
2303 }
252b5132 2304
40fb9820
L		 2305 if ((i.tm.opcode_modifier.jump
2306 || i.tm.opcode_modifier.jumpbyte
2307 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2308 && i.op[0].disps->X_op == O_constant)
2309 {
2310 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2311 the absolute address given by the constant. Since ix86 jumps and
2312 calls are pc relative, we need to generate a reloc. */
2313 i.op[0].disps->X_add_symbol = &abs_symbol;
2314 i.op[0].disps->X_op = O_symbol;
2315 }
252b5132 2316
40fb9820 2317 if (i.tm.opcode_modifier.rex64)
161a04f6 2318 i.rex |= REX_W;
252b5132 2319
29b0f896
AM		 2320 /* For 8 bit registers we need an empty rex prefix. Also if the
2321 instruction already has a prefix, we need to convert old
2322 registers to new ones. */
773f551c 2323
40fb9820 2324 if ((i.types[0].bitfield.reg8
29b0f896 2325 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2326 || (i.types[1].bitfield.reg8
29b0f896 2327 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2328 || ((i.types[0].bitfield.reg8
2329 || i.types[1].bitfield.reg8)
29b0f896
AM		 2330 && i.rex != 0))
2331 {
2332 int x;
726c5dcd 2333
29b0f896
AM		 2334 i.rex |= REX_OPCODE;
2335 for (x = 0; x < 2; x++)
2336 {
2337 /* Look for 8 bit operand that uses old registers. */
40fb9820 2338 if (i.types[x].bitfield.reg8
29b0f896 2339 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2340 {
29b0f896
AM		 2341 /* In case it is "hi" register, give up. */
2342 if (i.op[x].regs->reg_num > 3)
a540244d 2343 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2344 "instruction requiring REX prefix."),
a540244d 2345 register_prefix, i.op[x].regs->reg_name);
773f551c 2346
29b0f896
AM		 2347 /* Otherwise it is equivalent to the extended register.
2348 Since the encoding doesn't change this is merely
2349 cosmetic cleanup for debug output. */
2350
2351 i.op[x].regs = i.op[x].regs + 8;
773f551c 2352 }
29b0f896
AM		 2353 }
2354 }
773f551c 2355
85f10a01
MM		 2356 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2357 REX prefix. */
2358 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2359 {
2360 i.drex.rex = i.rex;
2361 i.rex = 0;
2362 }
2363 else if (i.rex != 0)
29b0f896
AM		 2364 add_prefix (REX_OPCODE | i.rex);
2365
2366 /* We are ready to output the insn. */
2367 output_insn ();
2368}
2369
2370static char *
e3bb37b5 2371parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2372{
2373 char *l = line;
2374 char *token_start = l;
2375 char *mnem_p;
5c6af06e
JB		 2376 int supported;
2377 const template *t;
29b0f896
AM		 2378
2379 /* Non-zero if we found a prefix only acceptable with string insns. */
2380 const char *expecting_string_instruction = NULL;
45288df1 2381
29b0f896
AM		 2382 while (1)
2383 {
2384 mnem_p = mnemonic;
2385 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2386 {
2387 mnem_p++;
2388 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2389 {
29b0f896
AM		 2390 as_bad (_("no such instruction: `%s'"), token_start);
2391 return NULL;
2392 }
2393 l++;
2394 }
2395 if (!is_space_char (*l)
2396 && *l != END_OF_INSN
e44823cf
JB		 2397 && (intel_syntax
2398 || (*l != PREFIX_SEPARATOR
2399 && *l != ',')))
29b0f896
AM		 2400 {
2401 as_bad (_("invalid character %s in mnemonic"),
2402 output_invalid (*l));
2403 return NULL;
2404 }
2405 if (token_start == l)
2406 {
e44823cf 2407 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2408 as_bad (_("expecting prefix; got nothing"));
2409 else
2410 as_bad (_("expecting mnemonic; got nothing"));
2411 return NULL;
2412 }
45288df1 2413
29b0f896
AM		 2414 /* Look up instruction (or prefix) via hash table. */
2415 current_templates = hash_find (op_hash, mnemonic);
47926f60 2416
29b0f896
AM		 2417 if (*l != END_OF_INSN
2418 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2419 && current_templates
40fb9820 2420 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2421 {
c6fb90c8 2422 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2423 {
2424 as_bad ((flag_code != CODE_64BIT
2425 ? _("`%s' is only supported in 64-bit mode")
2426 : _("`%s' is not supported in 64-bit mode")),
2427 current_templates->start->name);
2428 return NULL;
2429 }
29b0f896
AM		 2430 /* If we are in 16-bit mode, do not allow addr16 or data16.
2431 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2432 if ((current_templates->start->opcode_modifier.size16
2433 || current_templates->start->opcode_modifier.size32)
29b0f896 2434 && flag_code != CODE_64BIT
40fb9820 2435 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2436 ^ (flag_code == CODE_16BIT)))
2437 {
2438 as_bad (_("redundant %s prefix"),
2439 current_templates->start->name);
2440 return NULL;
45288df1 2441 }
29b0f896
AM		 2442 /* Add prefix, checking for repeated prefixes. */
2443 switch (add_prefix (current_templates->start->base_opcode))
2444 {
2445 case 0:
2446 return NULL;
2447 case 2:
2448 expecting_string_instruction = current_templates->start->name;
2449 break;
2450 }
2451 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2452 token_start = ++l;
2453 }
2454 else
2455 break;
2456 }
45288df1 2457
29b0f896
AM		 2458 if (!current_templates)
2459 {
2460 /* See if we can get a match by trimming off a suffix. */
2461 switch (mnem_p[-1])
2462 {
2463 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2464 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2465 i.suffix = SHORT_MNEM_SUFFIX;
2466 else
29b0f896
AM		 2467 case BYTE_MNEM_SUFFIX:
2468 case QWORD_MNEM_SUFFIX:
2469 i.suffix = mnem_p[-1];
2470 mnem_p[-1] = '\0';
2471 current_templates = hash_find (op_hash, mnemonic);
2472 break;
2473 case SHORT_MNEM_SUFFIX:
2474 case LONG_MNEM_SUFFIX:
2475 if (!intel_syntax)
2476 {
2477 i.suffix = mnem_p[-1];
2478 mnem_p[-1] = '\0';
2479 current_templates = hash_find (op_hash, mnemonic);
2480 }
2481 break;
252b5132 2482
29b0f896
AM		 2483 /* Intel Syntax. */
2484 case 'd':
2485 if (intel_syntax)
2486 {
9306ca4a 2487 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2488 i.suffix = SHORT_MNEM_SUFFIX;
2489 else
2490 i.suffix = LONG_MNEM_SUFFIX;
2491 mnem_p[-1] = '\0';
2492 current_templates = hash_find (op_hash, mnemonic);
2493 }
2494 break;
2495 }
2496 if (!current_templates)
2497 {
2498 as_bad (_("no such instruction: `%s'"), token_start);
2499 return NULL;
2500 }
2501 }
252b5132 2502
40fb9820
L		 2503 if (current_templates->start->opcode_modifier.jump
2504 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2505 {
2506 /* Check for a branch hint. We allow ",pt" and ",pn" for
2507 predict taken and predict not taken respectively.
2508 I'm not sure that branch hints actually do anything on loop
2509 and jcxz insns (JumpByte) for current Pentium4 chips. They
2510 may work in the future and it doesn't hurt to accept them
2511 now. */
2512 if (l[0] == ',' && l[1] == 'p')
2513 {
2514 if (l[2] == 't')
2515 {
2516 if (!add_prefix (DS_PREFIX_OPCODE))
2517 return NULL;
2518 l += 3;
2519 }
2520 else if (l[2] == 'n')
2521 {
2522 if (!add_prefix (CS_PREFIX_OPCODE))
2523 return NULL;
2524 l += 3;
2525 }
2526 }
2527 }
2528 /* Any other comma loses. */
2529 if (*l == ',')
2530 {
2531 as_bad (_("invalid character %s in mnemonic"),
2532 output_invalid (*l));
2533 return NULL;
2534 }
252b5132 2535
29b0f896 2536 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2537 supported = 0;
2538 for (t = current_templates->start; t < current_templates->end; ++t)
2539 {
40fb9820 2540 if (cpu_flags_match (t->cpu_flags))
64e74474 2541 supported |= 1;
c6fb90c8 2542 if (cpu_flags_check_cpu64 (t->cpu_flags))
64e74474 2543 supported |= 2;
5c6af06e
JB		 2544 }
2545 if (!(supported & 2))
2546 {
2547 as_bad (flag_code == CODE_64BIT
2548 ? _("`%s' is not supported in 64-bit mode")
2549 : _("`%s' is only supported in 64-bit mode"),
2550 current_templates->start->name);
2551 return NULL;
2552 }
2553 if (!(supported & 1))
29b0f896 2554 {
5c6af06e
JB		 2555 as_warn (_("`%s' is not supported on `%s%s'"),
2556 current_templates->start->name,
2557 cpu_arch_name,
2558 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896 2559 }
40fb9820
L		 2560 else if (!cpu_arch_flags.bitfield.cpui386
2561 && (flag_code != CODE_16BIT))
29b0f896
AM		 2562 {
2563 as_warn (_("use .code16 to ensure correct addressing mode"));
2564 }
252b5132 2565
29b0f896 2566 /* Check for rep/repne without a string instruction. */
f41bbced 2567 if (expecting_string_instruction)
29b0f896 2568 {
f41bbced
JB		 2569 static templates override;
2570
2571 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2572 if (t->opcode_modifier.isstring)
f41bbced
JB		 2573 break;
2574 if (t >= current_templates->end)
2575 {
2576 as_bad (_("expecting string instruction after `%s'"),
64e74474 2577 expecting_string_instruction);
f41bbced
JB		 2578 return NULL;
2579 }
2580 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2581 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2582 break;
2583 override.end = t;
2584 current_templates = &override;
29b0f896 2585 }
252b5132 2586
29b0f896
AM		 2587 return l;
2588}
252b5132 2589
29b0f896 2590static char *
e3bb37b5 2591parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2592{
2593 char *token_start;
3138f287 2594
29b0f896
AM		 2595 /* 1 if operand is pending after ','. */
2596 unsigned int expecting_operand = 0;
252b5132 2597
29b0f896
AM		 2598 /* Non-zero if operand parens not balanced. */
2599 unsigned int paren_not_balanced;
2600
2601 while (*l != END_OF_INSN)
2602 {
2603 /* Skip optional white space before operand. */
2604 if (is_space_char (*l))
2605 ++l;
2606 if (!is_operand_char (*l) && *l != END_OF_INSN)
2607 {
2608 as_bad (_("invalid character %s before operand %d"),
2609 output_invalid (*l),
2610 i.operands + 1);
2611 return NULL;
2612 }
2613 token_start = l; /* after white space */
2614 paren_not_balanced = 0;
2615 while (paren_not_balanced || *l != ',')
2616 {
2617 if (*l == END_OF_INSN)
2618 {
2619 if (paren_not_balanced)
2620 {
2621 if (!intel_syntax)
2622 as_bad (_("unbalanced parenthesis in operand %d."),
2623 i.operands + 1);
2624 else
2625 as_bad (_("unbalanced brackets in operand %d."),
2626 i.operands + 1);
2627 return NULL;
2628 }
2629 else
2630 break; /* we are done */
2631 }
2632 else if (!is_operand_char (*l) && !is_space_char (*l))
2633 {
2634 as_bad (_("invalid character %s in operand %d"),
2635 output_invalid (*l),
2636 i.operands + 1);
2637 return NULL;
2638 }
2639 if (!intel_syntax)
2640 {
2641 if (*l == '(')
2642 ++paren_not_balanced;
2643 if (*l == ')')
2644 --paren_not_balanced;
2645 }
2646 else
2647 {
2648 if (*l == '[')
2649 ++paren_not_balanced;
2650 if (*l == ']')
2651 --paren_not_balanced;
2652 }
2653 l++;
2654 }
2655 if (l != token_start)
2656 { /* Yes, we've read in another operand. */
2657 unsigned int operand_ok;
2658 this_operand = i.operands++;
2659 if (i.operands > MAX_OPERANDS)
2660 {
2661 as_bad (_("spurious operands; (%d operands/instruction max)"),
2662 MAX_OPERANDS);
2663 return NULL;
2664 }
2665 /* Now parse operand adding info to 'i' as we go along. */
2666 END_STRING_AND_SAVE (l);
2667
2668 if (intel_syntax)
2669 operand_ok =
2670 i386_intel_operand (token_start,
2671 intel_float_operand (mnemonic));
2672 else
2673 operand_ok = i386_operand (token_start);
2674
2675 RESTORE_END_STRING (l);
2676 if (!operand_ok)
2677 return NULL;
2678 }
2679 else
2680 {
2681 if (expecting_operand)
2682 {
2683 expecting_operand_after_comma:
2684 as_bad (_("expecting operand after ','; got nothing"));
2685 return NULL;
2686 }
2687 if (*l == ',')
2688 {
2689 as_bad (_("expecting operand before ','; got nothing"));
2690 return NULL;
2691 }
2692 }
7f3f1ea2 2693
29b0f896
AM		 2694 /* Now *l must be either ',' or END_OF_INSN. */
2695 if (*l == ',')
2696 {
2697 if (*++l == END_OF_INSN)
2698 {
2699 /* Just skip it, if it's \n complain. */
2700 goto expecting_operand_after_comma;
2701 }
2702 expecting_operand = 1;
2703 }
2704 }
2705 return l;
2706}
7f3f1ea2 2707
050dfa73 2708static void
4d456e3d 2709swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2710{
2711 union i386_op temp_op;
40fb9820 2712 i386_operand_type temp_type;
050dfa73 2713 enum bfd_reloc_code_real temp_reloc;
4eed87de 2714
050dfa73
MM		 2715 temp_type = i.types[xchg2];
2716 i.types[xchg2] = i.types[xchg1];
2717 i.types[xchg1] = temp_type;
2718 temp_op = i.op[xchg2];
2719 i.op[xchg2] = i.op[xchg1];
2720 i.op[xchg1] = temp_op;
2721 temp_reloc = i.reloc[xchg2];
2722 i.reloc[xchg2] = i.reloc[xchg1];
2723 i.reloc[xchg1] = temp_reloc;
2724}
2725
29b0f896 2726static void
e3bb37b5 2727swap_operands (void)
29b0f896 2728{
b7c61d9a 2729 switch (i.operands)
050dfa73 2730 {
b7c61d9a 2731 case 4:
4d456e3d 2732 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2733 case 3:
2734 case 2:
4d456e3d 2735 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2736 break;
2737 default:
2738 abort ();
29b0f896 2739 }
29b0f896
AM		 2740
2741 if (i.mem_operands == 2)
2742 {
2743 const seg_entry *temp_seg;
2744 temp_seg = i.seg[0];
2745 i.seg[0] = i.seg[1];
2746 i.seg[1] = temp_seg;
2747 }
2748}
252b5132 2749
29b0f896
AM		 2750/* Try to ensure constant immediates are represented in the smallest
2751 opcode possible. */
2752static void
e3bb37b5 2753optimize_imm (void)
29b0f896
AM		 2754{
2755 char guess_suffix = 0;
2756 int op;
252b5132 2757
29b0f896
AM		 2758 if (i.suffix)
2759 guess_suffix = i.suffix;
2760 else if (i.reg_operands)
2761 {
2762 /* Figure out a suffix from the last register operand specified.
2763 We can't do this properly yet, ie. excluding InOutPortReg,
2764 but the following works for instructions with immediates.
2765 In any case, we can't set i.suffix yet. */
2766 for (op = i.operands; --op >= 0;)
40fb9820
L		 2767 if (i.types[op].bitfield.reg8)
2768 {
2769 guess_suffix = BYTE_MNEM_SUFFIX;
2770 break;
2771 }
2772 else if (i.types[op].bitfield.reg16)
252b5132 2773 {
40fb9820
L		 2774 guess_suffix = WORD_MNEM_SUFFIX;
2775 break;
2776 }
2777 else if (i.types[op].bitfield.reg32)
2778 {
2779 guess_suffix = LONG_MNEM_SUFFIX;
2780 break;
2781 }
2782 else if (i.types[op].bitfield.reg64)
2783 {
2784 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 2785 break;
252b5132 2786 }
29b0f896
AM		 2787 }
2788 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2789 guess_suffix = WORD_MNEM_SUFFIX;
2790
2791 for (op = i.operands; --op >= 0;)
40fb9820 2792 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 2793 {
2794 switch (i.op[op].imms->X_op)
252b5132 2795 {
29b0f896
AM		 2796 case O_constant:
2797 /* If a suffix is given, this operand may be shortened. */
2798 switch (guess_suffix)
252b5132 2799 {
29b0f896 2800 case LONG_MNEM_SUFFIX:
40fb9820
L		 2801 i.types[op].bitfield.imm32 = 1;
2802 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2803 break;
2804 case WORD_MNEM_SUFFIX:
40fb9820
L		 2805 i.types[op].bitfield.imm16 = 1;
2806 i.types[op].bitfield.imm32 = 1;
2807 i.types[op].bitfield.imm32s = 1;
2808 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2809 break;
2810 case BYTE_MNEM_SUFFIX:
40fb9820
L		 2811 i.types[op].bitfield.imm8 = 1;
2812 i.types[op].bitfield.imm8s = 1;
2813 i.types[op].bitfield.imm16 = 1;
2814 i.types[op].bitfield.imm32 = 1;
2815 i.types[op].bitfield.imm32s = 1;
2816 i.types[op].bitfield.imm64 = 1;
29b0f896 2817 break;
252b5132 2818 }
252b5132 2819
29b0f896
AM		 2820 /* If this operand is at most 16 bits, convert it
2821 to a signed 16 bit number before trying to see
2822 whether it will fit in an even smaller size.
2823 This allows a 16-bit operand such as $0xffe0 to
2824 be recognised as within Imm8S range. */
40fb9820 2825 if ((i.types[op].bitfield.imm16)
29b0f896 2826 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2827 {
29b0f896
AM		 2828 i.op[op].imms->X_add_number =
2829 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2830 }
40fb9820 2831 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 2832 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2833 == 0))
2834 {
2835 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2836 ^ ((offsetT) 1 << 31))
2837 - ((offsetT) 1 << 31));
2838 }
40fb9820 2839 i.types[op]
c6fb90c8
L		 2840 = operand_type_or (i.types[op],
2841 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 2842
29b0f896
AM		 2843 /* We must avoid matching of Imm32 templates when 64bit
2844 only immediate is available. */
2845 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 2846 i.types[op].bitfield.imm32 = 0;
29b0f896 2847 break;
252b5132 2848
29b0f896
AM		 2849 case O_absent:
2850 case O_register:
2851 abort ();
2852
2853 /* Symbols and expressions. */
2854 default:
9cd96992
JB		 2855 /* Convert symbolic operand to proper sizes for matching, but don't
2856 prevent matching a set of insns that only supports sizes other
2857 than those matching the insn suffix. */
2858 {
40fb9820 2859 i386_operand_type mask, allowed;
9cd96992
JB		 2860 const template *t;
2861
c6fb90c8
L		 2862 UINTS_CLEAR (mask);
2863 UINTS_CLEAR (allowed);
40fb9820 2864
4eed87de
AM		 2865 for (t = current_templates->start;
2866 t < current_templates->end;
2867 ++t)
c6fb90c8
L		 2868 allowed = operand_type_or (allowed,
2869 t->operand_types[op]);
9cd96992
JB		 2870 switch (guess_suffix)
2871 {
2872 case QWORD_MNEM_SUFFIX:
40fb9820
L		 2873 mask.bitfield.imm64 = 1;
2874 mask.bitfield.imm32s = 1;
9cd96992
JB		 2875 break;
2876 case LONG_MNEM_SUFFIX:
40fb9820 2877 mask.bitfield.imm32 = 1;
9cd96992
JB		 2878 break;
2879 case WORD_MNEM_SUFFIX:
40fb9820 2880 mask.bitfield.imm16 = 1;
9cd96992
JB		 2881 break;
2882 case BYTE_MNEM_SUFFIX:
40fb9820 2883 mask.bitfield.imm8 = 1;
9cd96992
JB		 2884 break;
2885 default:
9cd96992
JB		 2886 break;
2887 }
c6fb90c8
L		 2888 allowed = operand_type_and (mask, allowed);
2889 if (!UINTS_ALL_ZERO (allowed))
2890 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 2891 }
29b0f896 2892 break;
252b5132 2893 }
29b0f896
AM		 2894 }
2895}
47926f60 2896
29b0f896
AM		 2897/* Try to use the smallest displacement type too. */
2898static void
e3bb37b5 2899optimize_disp (void)
29b0f896
AM		 2900{
2901 int op;
3e73aa7c 2902
29b0f896 2903 for (op = i.operands; --op >= 0;)
40fb9820 2904 if (operand_type_check (i.types[op], disp))
252b5132 2905 {
b300c311 2906 if (i.op[op].disps->X_op == O_constant)
252b5132 2907 {
b300c311 2908 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2909
40fb9820 2910 if (i.types[op].bitfield.disp16
b300c311
L		 2911 && (disp & ~(offsetT) 0xffff) == 0)
2912 {
2913 /* If this operand is at most 16 bits, convert
2914 to a signed 16 bit number and don't use 64bit
2915 displacement. */
2916 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 2917 i.types[op].bitfield.disp64 = 0;
b300c311 2918 }
40fb9820 2919 if (i.types[op].bitfield.disp32
b300c311
L		 2920 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2921 {
2922 /* If this operand is at most 32 bits, convert
2923 to a signed 32 bit number and don't use 64bit
2924 displacement. */
2925 disp &= (((offsetT) 2 << 31) - 1);
2926 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 2927 i.types[op].bitfield.disp64 = 0;
b300c311 2928 }
40fb9820 2929 if (!disp && i.types[op].bitfield.baseindex)
b300c311 2930 {
40fb9820
L		 2931 i.types[op].bitfield.disp8 = 0;
2932 i.types[op].bitfield.disp16 = 0;
2933 i.types[op].bitfield.disp32 = 0;
2934 i.types[op].bitfield.disp32s = 0;
2935 i.types[op].bitfield.disp64 = 0;
b300c311
L		 2936 i.op[op].disps = 0;
2937 i.disp_operands--;
2938 }
2939 else if (flag_code == CODE_64BIT)
2940 {
2941 if (fits_in_signed_long (disp))
28a9d8f5 2942 {
40fb9820
L		 2943 i.types[op].bitfield.disp64 = 0;
2944 i.types[op].bitfield.disp32s = 1;
28a9d8f5 2945 }
b300c311 2946 if (fits_in_unsigned_long (disp))
40fb9820 2947 i.types[op].bitfield.disp32 = 1;
b300c311 2948 }
40fb9820
L		 2949 if ((i.types[op].bitfield.disp32
2950 || i.types[op].bitfield.disp32s
2951 || i.types[op].bitfield.disp16)
b300c311 2952 && fits_in_signed_byte (disp))
40fb9820 2953 i.types[op].bitfield.disp8 = 1;
252b5132 2954 }
67a4f2b7
AO		 2955 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2956 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2957 {
2958 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2959 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 2960 i.types[op].bitfield.disp8 = 0;
2961 i.types[op].bitfield.disp16 = 0;
2962 i.types[op].bitfield.disp32 = 0;
2963 i.types[op].bitfield.disp32s = 0;
2964 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 2965 }
2966 else
b300c311 2967 /* We only support 64bit displacement on constants. */
40fb9820 2968 i.types[op].bitfield.disp64 = 0;
252b5132 2969 }
29b0f896
AM		 2970}
2971
2972static int
e3bb37b5 2973match_template (void)
29b0f896
AM		 2974{
2975 /* Points to template once we've found it. */
2976 const template *t;
40fb9820 2977 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 2978 unsigned int found_reverse_match;
40fb9820
L		 2979 i386_opcode_modifier suffix_check;
2980 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 2981 int addr_prefix_disp;
a5c311ca 2982 unsigned int j;
c6fb90c8 2983 i386_cpu_flags overlap;
29b0f896 2984
f48ff2ae
L		 2985#if MAX_OPERANDS != 4
2986# error "MAX_OPERANDS must be 4."
2987#endif
2988
29b0f896 2989 found_reverse_match = 0;
539e75ad 2990 addr_prefix_disp = -1;
40fb9820
L		 2991
2992 memset (&suffix_check, 0, sizeof (suffix_check));
2993 if (i.suffix == BYTE_MNEM_SUFFIX)
2994 suffix_check.no_bsuf = 1;
2995 else if (i.suffix == WORD_MNEM_SUFFIX)
2996 suffix_check.no_wsuf = 1;
2997 else if (i.suffix == SHORT_MNEM_SUFFIX)
2998 suffix_check.no_ssuf = 1;
2999 else if (i.suffix == LONG_MNEM_SUFFIX)
3000 suffix_check.no_lsuf = 1;
3001 else if (i.suffix == QWORD_MNEM_SUFFIX)
3002 suffix_check.no_qsuf = 1;
3003 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3004 suffix_check.no_xsuf = 1;
29b0f896 3005
45aa61fe 3006 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3007 {
539e75ad
L		 3008 addr_prefix_disp = -1;
3009
29b0f896
AM		 3010 /* Must have right number of operands. */
3011 if (i.operands != t->operands)
3012 continue;
3013
20592a94 3014 /* Check the suffix, except for some instructions in intel mode. */
40fb9820
L		 3015 if (((t->opcode_modifier.no_bsuf & suffix_check.no_bsuf)
3016 || (t->opcode_modifier.no_wsuf & suffix_check.no_wsuf)
3017 || (t->opcode_modifier.no_lsuf & suffix_check.no_lsuf)
3018 || (t->opcode_modifier.no_ssuf & suffix_check.no_ssuf)
3019 || (t->opcode_modifier.no_qsuf & suffix_check.no_qsuf)
3020 || (t->opcode_modifier.no_xsuf & suffix_check.no_xsuf))
3021 && !(intel_syntax && t->opcode_modifier.ignoresize))
29b0f896
AM		 3022 continue;
3023
a5c311ca
L		 3024 for (j = 0; j < MAX_OPERANDS; j++)
3025 operand_types [j] = t->operand_types [j];
539e75ad 3026
45aa61fe
AM		 3027 /* In general, don't allow 64-bit operands in 32-bit mode. */
3028 if (i.suffix == QWORD_MNEM_SUFFIX
3029 && flag_code != CODE_64BIT
3030 && (intel_syntax
40fb9820 3031 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3032 && !intel_float_operand (t->name))
3033 : intel_float_operand (t->name) != 2)
40fb9820
L		 3034 && ((!operand_types[0].bitfield.regmmx
3035 && !operand_types[0].bitfield.regxmm)
3036 || (!operand_types[t->operands > 1].bitfield.regmmx
3037 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 3038 && (t->base_opcode != 0x0fc7
3039 || t->extension_opcode != 1 /* cmpxchg8b */))
3040 continue;
3041
29b0f896 3042 /* Do not verify operands when there are none. */
c6fb90c8 3043 else
29b0f896 3044 {
c6fb90c8
L		 3045 overlap = cpu_flags_and (t->cpu_flags, cpu_arch_flags_not);
3046 if (!t->operands)
3047 {
3048 if (!UINTS_ALL_ZERO (overlap))
3049 continue;
3050 /* We've found a match; break out of loop. */
3051 break;
3052 }
29b0f896 3053 }
252b5132 3054
539e75ad
L		 3055 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3056 into Disp32/Disp16/Disp32 operand. */
3057 if (i.prefix[ADDR_PREFIX] != 0)
3058 {
40fb9820 3059 /* There should be only one Disp operand. */
539e75ad
L		 3060 switch (flag_code)
3061 {
3062 case CODE_16BIT:
40fb9820
L		 3063 for (j = 0; j < MAX_OPERANDS; j++)
3064 {
3065 if (operand_types[j].bitfield.disp16)
3066 {
3067 addr_prefix_disp = j;
3068 operand_types[j].bitfield.disp32 = 1;
3069 operand_types[j].bitfield.disp16 = 0;
3070 break;
3071 }
3072 }
539e75ad
L		 3073 break;
3074 case CODE_32BIT:
40fb9820
L		 3075 for (j = 0; j < MAX_OPERANDS; j++)
3076 {
3077 if (operand_types[j].bitfield.disp32)
3078 {
3079 addr_prefix_disp = j;
3080 operand_types[j].bitfield.disp32 = 0;
3081 operand_types[j].bitfield.disp16 = 1;
3082 break;
3083 }
3084 }
539e75ad
L		 3085 break;
3086 case CODE_64BIT:
40fb9820
L		 3087 for (j = 0; j < MAX_OPERANDS; j++)
3088 {
3089 if (operand_types[j].bitfield.disp64)
3090 {
3091 addr_prefix_disp = j;
3092 operand_types[j].bitfield.disp64 = 0;
3093 operand_types[j].bitfield.disp32 = 1;
3094 break;
3095 }
3096 }
539e75ad
L		 3097 break;
3098 }
539e75ad
L		 3099 }
3100
c6fb90c8 3101 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3102 switch (t->operands)
3103 {
3104 case 1:
40fb9820 3105 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3106 continue;
3107 break;
3108 case 2:
8b38ad71
L		 3109 /* xchg %eax, %eax is a special case. It is an aliase for nop
3110 only in 32bit mode and we can use opcode 0x90. In 64bit
3111 mode, we can't use 0x90 for xchg %eax, %eax since it should
3112 zero-extend %eax to %rax. */
3113 if (flag_code == CODE_64BIT
3114 && t->base_opcode == 0x90
c6fb90c8
L		 3115 && UINTS_EQUAL (i.types [0], acc32)
3116 && UINTS_EQUAL (i.types [1], acc32))
8b38ad71 3117 continue;
29b0f896 3118 case 3:
f48ff2ae 3119 case 4:
c6fb90c8 3120 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3121 if (!operand_type_match (overlap0, i.types[0])
3122 || !operand_type_match (overlap1, i.types[1])
cb712a9e 3123 /* monitor in SSE3 is a very special case. The first
708587a4 3124 register and the second register may have different
26186d74
L		 3125 sizes. The same applies to crc32 in SSE4.2. It is
3126 also true for invlpga, vmload, vmrun and vmsave in
3127 SVME. */
cb712a9e 3128 || !((t->base_opcode == 0x0f01
26186d74
L		 3129 && (t->extension_opcode == 0xc8
3130 || t->extension_opcode == 0xd8
3131 || t->extension_opcode == 0xda
3132 || t->extension_opcode == 0xdb
3133 || t->extension_opcode == 0xdf))
381d071f 3134 || t->base_opcode == 0xf20f38f1
40fb9820
L		 3135 || operand_type_register_match (overlap0, i.types[0],
3136 operand_types[0],
3137 overlap1, i.types[1],
3138 operand_types[1])))
29b0f896
AM		 3139 {
3140 /* Check if other direction is valid ... */
40fb9820 3141 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3142 continue;
3143
3144 /* Try reversing direction of operands. */
c6fb90c8
L		 3145 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3146 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3147 if (!operand_type_match (overlap0, i.types[0])
3148 || !operand_type_match (overlap1, i.types[1])
3149 || !operand_type_register_match (overlap0, i.types[0],
3150 operand_types[1],
3151 overlap1, i.types[1],
3152 operand_types[0]))
29b0f896
AM		 3153 {
3154 /* Does not match either direction. */
3155 continue;
3156 }
3157 /* found_reverse_match holds which of D or FloatDR
3158 we've found. */
40fb9820 3159 if (t->opcode_modifier.d)
8a2ed489 3160 found_reverse_match = Opcode_D;
40fb9820 3161 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3162 found_reverse_match = Opcode_FloatD;
3163 else
3164 found_reverse_match = 0;
40fb9820 3165 if (t->opcode_modifier.floatr)
8a2ed489 3166 found_reverse_match |= Opcode_FloatR;
29b0f896 3167 }
f48ff2ae 3168 else
29b0f896 3169 {
f48ff2ae 3170 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3171 switch (t->operands)
3172 {
3173 case 4:
c6fb90c8
L		 3174 overlap3 = operand_type_and (i.types[3],
3175 operand_types[3]);
d1cbb4db 3176 case 3:
c6fb90c8
L		 3177 overlap2 = operand_type_and (i.types[2],
3178 operand_types[2]);
d1cbb4db
L		 3179 break;
3180 }
29b0f896 3181
f48ff2ae
L		 3182 switch (t->operands)
3183 {
3184 case 4:
40fb9820
L		 3185 if (!operand_type_match (overlap3, i.types[3])
3186 || !operand_type_register_match (overlap2,
3187 i.types[2],
3188 operand_types[2],
3189 overlap3,
3190 i.types[3],
3191 operand_types[3]))
f48ff2ae
L		 3192 continue;
3193 case 3:
3194 /* Here we make use of the fact that there are no
3195 reverse match 3 operand instructions, and all 3
3196 operand instructions only need to be checked for
3197 register consistency between operands 2 and 3. */
40fb9820
L		 3198 if (!operand_type_match (overlap2, i.types[2])
3199 || !operand_type_register_match (overlap1,
3200 i.types[1],
3201 operand_types[1],
3202 overlap2,
3203 i.types[2],
3204 operand_types[2]))
f48ff2ae
L		 3205 continue;
3206 break;
3207 }
29b0f896 3208 }
f48ff2ae 3209 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3210 slip through to break. */
3211 }
c6fb90c8 3212 if (!UINTS_ALL_ZERO (overlap))
29b0f896
AM		 3213 {
3214 found_reverse_match = 0;
3215 continue;
3216 }
3217 /* We've found a match; break out of loop. */
3218 break;
3219 }
3220
3221 if (t == current_templates->end)
3222 {
3223 /* We found no match. */
3224 as_bad (_("suffix or operands invalid for `%s'"),
3225 current_templates->start->name);
3226 return 0;
3227 }
252b5132 3228
29b0f896
AM		 3229 if (!quiet_warnings)
3230 {
3231 if (!intel_syntax
40fb9820
L		 3232 && (i.types[0].bitfield.jumpabsolute
3233 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3234 {
3235 as_warn (_("indirect %s without `*'"), t->name);
3236 }
3237
40fb9820
L		 3238 if (t->opcode_modifier.isprefix
3239 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3240 {
3241 /* Warn them that a data or address size prefix doesn't
3242 affect assembly of the next line of code. */
3243 as_warn (_("stand-alone `%s' prefix"), t->name);
3244 }
3245 }
3246
3247 /* Copy the template we found. */
3248 i.tm = *t;
539e75ad
L		 3249
3250 if (addr_prefix_disp != -1)
3251 i.tm.operand_types[addr_prefix_disp]
3252 = operand_types[addr_prefix_disp];
3253
29b0f896
AM		 3254 if (found_reverse_match)
3255 {
3256 /* If we found a reverse match we must alter the opcode
3257 direction bit. found_reverse_match holds bits to change
3258 (different for int & float insns). */
3259
3260 i.tm.base_opcode ^= found_reverse_match;
3261
539e75ad
L		 3262 i.tm.operand_types[0] = operand_types[1];
3263 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3264 }
3265
3266 return 1;
3267}
3268
3269static int
e3bb37b5 3270check_string (void)
29b0f896 3271{
40fb9820
L		 3272 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3273 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3274 {
3275 if (i.seg[0] != NULL && i.seg[0] != &es)
3276 {
3277 as_bad (_("`%s' operand %d must use `%%es' segment"),
3278 i.tm.name,
3279 mem_op + 1);
3280 return 0;
3281 }
3282 /* There's only ever one segment override allowed per instruction.
3283 This instruction possibly has a legal segment override on the
3284 second operand, so copy the segment to where non-string
3285 instructions store it, allowing common code. */
3286 i.seg[0] = i.seg[1];
3287 }
40fb9820 3288 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3289 {
3290 if (i.seg[1] != NULL && i.seg[1] != &es)
3291 {
3292 as_bad (_("`%s' operand %d must use `%%es' segment"),
3293 i.tm.name,
3294 mem_op + 2);
3295 return 0;
3296 }
3297 }
3298 return 1;
3299}
3300
3301static int
543613e9 3302process_suffix (void)
29b0f896
AM		 3303{
3304 /* If matched instruction specifies an explicit instruction mnemonic
3305 suffix, use it. */
40fb9820
L		 3306 if (i.tm.opcode_modifier.size16)
3307 i.suffix = WORD_MNEM_SUFFIX;
3308 else if (i.tm.opcode_modifier.size32)
3309 i.suffix = LONG_MNEM_SUFFIX;
3310 else if (i.tm.opcode_modifier.size64)
3311 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3312 else if (i.reg_operands)
3313 {
3314 /* If there's no instruction mnemonic suffix we try to invent one
3315 based on register operands. */
3316 if (!i.suffix)
3317 {
3318 /* We take i.suffix from the last register operand specified,
3319 Destination register type is more significant than source
381d071f
L		 3320 register type. crc32 in SSE4.2 prefers source register
3321 type. */
3322 if (i.tm.base_opcode == 0xf20f38f1)
3323 {
40fb9820
L		 3324 if (i.types[0].bitfield.reg16)
3325 i.suffix = WORD_MNEM_SUFFIX;
3326 else if (i.types[0].bitfield.reg32)
3327 i.suffix = LONG_MNEM_SUFFIX;
3328 else if (i.types[0].bitfield.reg64)
3329 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3330 }
9344ff29 3331 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3332 {
40fb9820 3333 if (i.types[0].bitfield.reg8)
20592a94
L		 3334 i.suffix = BYTE_MNEM_SUFFIX;
3335 }
381d071f
L		 3336
3337 if (!i.suffix)
3338 {
3339 int op;
3340
20592a94
L		 3341 if (i.tm.base_opcode == 0xf20f38f1
3342 || i.tm.base_opcode == 0xf20f38f0)
3343 {
3344 /* We have to know the operand size for crc32. */
3345 as_bad (_("ambiguous memory operand size for `%s`"),
3346 i.tm.name);
3347 return 0;
3348 }
3349
381d071f 3350 for (op = i.operands; --op >= 0;)
40fb9820 3351 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3352 {
40fb9820
L		 3353 if (i.types[op].bitfield.reg8)
3354 {
3355 i.suffix = BYTE_MNEM_SUFFIX;
3356 break;
3357 }
3358 else if (i.types[op].bitfield.reg16)
3359 {
3360 i.suffix = WORD_MNEM_SUFFIX;
3361 break;
3362 }
3363 else if (i.types[op].bitfield.reg32)
3364 {
3365 i.suffix = LONG_MNEM_SUFFIX;
3366 break;
3367 }
3368 else if (i.types[op].bitfield.reg64)
3369 {
3370 i.suffix = QWORD_MNEM_SUFFIX;
3371 break;
3372 }
381d071f
L		 3373 }
3374 }
29b0f896
AM		 3375 }
3376 else if (i.suffix == BYTE_MNEM_SUFFIX)
3377 {
3378 if (!check_byte_reg ())
3379 return 0;
3380 }
3381 else if (i.suffix == LONG_MNEM_SUFFIX)
3382 {
3383 if (!check_long_reg ())
3384 return 0;
3385 }
3386 else if (i.suffix == QWORD_MNEM_SUFFIX)
3387 {
3388 if (!check_qword_reg ())
3389 return 0;
3390 }
3391 else if (i.suffix == WORD_MNEM_SUFFIX)
3392 {
3393 if (!check_word_reg ())
3394 return 0;
3395 }
40fb9820 3396 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3397 /* Do nothing if the instruction is going to ignore the prefix. */
3398 ;
3399 else
3400 abort ();
3401 }
40fb9820 3402 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3403 && !i.suffix
3404 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3405 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3406 {
3407 i.suffix = stackop_size;
3408 }
9306ca4a
JB		 3409 else if (intel_syntax
3410 && !i.suffix
40fb9820
L		 3411 && (i.tm.operand_types[0].bitfield.jumpabsolute
3412 || i.tm.opcode_modifier.jumpbyte
3413 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3414 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3415 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3416 {
3417 switch (flag_code)
3418 {
3419 case CODE_64BIT:
40fb9820 3420 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3421 {
3422 i.suffix = QWORD_MNEM_SUFFIX;
3423 break;
3424 }
3425 case CODE_32BIT:
40fb9820 3426 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3427 i.suffix = LONG_MNEM_SUFFIX;
3428 break;
3429 case CODE_16BIT:
40fb9820 3430 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3431 i.suffix = WORD_MNEM_SUFFIX;
3432 break;
3433 }
3434 }
252b5132 3435
9306ca4a 3436 if (!i.suffix)
29b0f896 3437 {
9306ca4a
JB		 3438 if (!intel_syntax)
3439 {
40fb9820 3440 if (i.tm.opcode_modifier.w)
9306ca4a 3441 {
4eed87de
AM		 3442 as_bad (_("no instruction mnemonic suffix given and "
3443 "no register operands; can't size instruction"));
9306ca4a
JB		 3444 return 0;
3445 }
3446 }
3447 else
3448 {
40fb9820
L		 3449 unsigned int suffixes;
3450
3451 suffixes = !i.tm.opcode_modifier.no_bsuf;
3452 if (!i.tm.opcode_modifier.no_wsuf)
3453 suffixes |= 1 << 1;
3454 if (!i.tm.opcode_modifier.no_lsuf)
3455 suffixes |= 1 << 2;
3456 if (!i.tm.opcode_modifier.no_lsuf)
3457 suffixes |= 1 << 3;
3458 if (!i.tm.opcode_modifier.no_ssuf)
3459 suffixes |= 1 << 4;
3460 if (!i.tm.opcode_modifier.no_qsuf)
3461 suffixes |= 1 << 5;
3462
3463 /* There are more than suffix matches. */
3464 if (i.tm.opcode_modifier.w
9306ca4a 3465 || ((suffixes & (suffixes - 1))
40fb9820
L		 3466 && !i.tm.opcode_modifier.defaultsize
3467 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3468 {
3469 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3470 return 0;
3471 }
3472 }
29b0f896 3473 }
252b5132 3474
9306ca4a
JB		 3475 /* Change the opcode based on the operand size given by i.suffix;
3476 We don't need to change things for byte insns. */
3477
29b0f896
AM		 3478 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
3479 {
3480 /* It's not a byte, select word/dword operation. */
40fb9820 3481 if (i.tm.opcode_modifier.w)
29b0f896 3482 {
40fb9820 3483 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3484 i.tm.base_opcode |= 8;
3485 else
3486 i.tm.base_opcode |= 1;
3487 }
0f3f3d8b 3488
29b0f896
AM		 3489 /* Now select between word & dword operations via the operand
3490 size prefix, except for instructions that will ignore this
3491 prefix anyway. */
26186d74
L		 3492 if (i.tm.base_opcode == 0x0f01
3493 && (i.tm.extension_opcode == 0xc8
3494 || i.tm.extension_opcode == 0xd8
3495 || i.tm.extension_opcode == 0xda
3496 || i.tm.extension_opcode == 0xdb
3497 || i.tm.extension_opcode == 0xdf))
cb712a9e
L		 3498 {
3499 /* monitor in SSE3 is a very special case. The default size
3500 of AX is the size of mode. The address size override
26186d74
L		 3501 prefix will change the size of AX. It is also true for
3502 invlpga, vmload, vmrun and vmsave in SVME. */
40fb9820
L		 3503 if ((flag_code == CODE_32BIT
3504 && i.op->regs[0].reg_type.bitfield.reg16)
3505 || (flag_code != CODE_32BIT
3506 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3507 if (!add_prefix (ADDR_PREFIX_OPCODE))
3508 return 0;
3509 }
3510 else if (i.suffix != QWORD_MNEM_SUFFIX
3511 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3512 && !i.tm.opcode_modifier.ignoresize
3513 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3514 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3515 || (flag_code == CODE_64BIT
40fb9820 3516 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3517 {
3518 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3519
40fb9820 3520 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3521 prefix = ADDR_PREFIX_OPCODE;
252b5132 3522
29b0f896
AM		 3523 if (!add_prefix (prefix))
3524 return 0;
24eab124 3525 }
252b5132 3526
29b0f896
AM		 3527 /* Set mode64 for an operand. */
3528 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3529 && flag_code == CODE_64BIT
40fb9820 3530 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3531 {
3532 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3533 need rex64. cmpxchg8b is also a special case. */
3534 if (! (i.operands == 2
3535 && i.tm.base_opcode == 0x90
3536 && i.tm.extension_opcode == None
c6fb90c8
L		 3537 && UINTS_EQUAL (i.types [0], acc64)
3538 && UINTS_EQUAL (i.types [1], acc64))
d9a5e5e5
L		 3539 && ! (i.operands == 1
3540 && i.tm.base_opcode == 0xfc7
3541 && i.tm.extension_opcode == 1
40fb9820
L		 3542 && !operand_type_check (i.types [0], reg)
3543 && operand_type_check (i.types [0], anymem)))
f6bee062 3544 i.rex |= REX_W;
46e883c5 3545 }
3e73aa7c 3546
29b0f896
AM		 3547 /* Size floating point instruction. */
3548 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3549 if (i.tm.opcode_modifier.floatmf)
543613e9 3550 i.tm.base_opcode ^= 4;
29b0f896 3551 }
7ecd2f8b 3552
29b0f896
AM		 3553 return 1;
3554}
3e73aa7c 3555
29b0f896 3556static int
543613e9 3557check_byte_reg (void)
29b0f896
AM		 3558{
3559 int op;
543613e9 3560
29b0f896
AM		 3561 for (op = i.operands; --op >= 0;)
3562 {
3563 /* If this is an eight bit register, it's OK. If it's the 16 or
3564 32 bit version of an eight bit register, we will just use the
3565 low portion, and that's OK too. */
40fb9820 3566 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3567 continue;
3568
c3ad16c0
L		 3569 /* movzx, movsx, pextrb and pinsrb should not generate this
3570 warning. */
29b0f896
AM		 3571 if (intel_syntax
3572 && (i.tm.base_opcode == 0xfb7
3573 || i.tm.base_opcode == 0xfb6
3574 || i.tm.base_opcode == 0x63
3575 || i.tm.base_opcode == 0xfbe
c3ad16c0
L		 3576 || i.tm.base_opcode == 0xfbf
3577 || i.tm.base_opcode == 0x660f3a14
3578 || i.tm.base_opcode == 0x660f3a20))
29b0f896
AM		 3579 continue;
3580
9344ff29
L		 3581 /* crc32 doesn't generate this warning. */
3582 if (i.tm.base_opcode == 0xf20f38f0)
3583 continue;
3584
40fb9820
L		 3585 if ((i.types[op].bitfield.reg16
3586 || i.types[op].bitfield.reg32
3587 || i.types[op].bitfield.reg64)
3588 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3589 {
3590 /* Prohibit these changes in the 64bit mode, since the
3591 lowering is more complicated. */
3592 if (flag_code == CODE_64BIT
40fb9820 3593 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3594 {
2ca3ace5
L		 3595 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3596 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3597 i.suffix);
3598 return 0;
3599 }
3600#if REGISTER_WARNINGS
3601 if (!quiet_warnings
40fb9820 3602 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3603 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3604 register_prefix,
40fb9820 3605 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3606 ? REGNAM_AL - REGNAM_AX
3607 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3608 register_prefix,
29b0f896
AM		 3609 i.op[op].regs->reg_name,
3610 i.suffix);
3611#endif
3612 continue;
3613 }
3614 /* Any other register is bad. */
40fb9820
L		 3615 if (i.types[op].bitfield.reg16
3616 || i.types[op].bitfield.reg32
3617 || i.types[op].bitfield.reg64
3618 || i.types[op].bitfield.regmmx
3619 || i.types[op].bitfield.regxmm
3620 || i.types[op].bitfield.sreg2
3621 || i.types[op].bitfield.sreg3
3622 || i.types[op].bitfield.control
3623 || i.types[op].bitfield.debug
3624 || i.types[op].bitfield.test
3625 || i.types[op].bitfield.floatreg
3626 || i.types[op].bitfield.floatacc)
29b0f896 3627 {
a540244d
L		 3628 as_bad (_("`%s%s' not allowed with `%s%c'"),
3629 register_prefix,
29b0f896
AM		 3630 i.op[op].regs->reg_name,
3631 i.tm.name,
3632 i.suffix);
3633 return 0;
3634 }
3635 }
3636 return 1;
3637}
3638
3639static int
e3bb37b5 3640check_long_reg (void)
29b0f896
AM		 3641{
3642 int op;
3643
3644 for (op = i.operands; --op >= 0;)
3645 /* Reject eight bit registers, except where the template requires
3646 them. (eg. movzb) */
40fb9820
L		 3647 if (i.types[op].bitfield.reg8
3648 && (i.tm.operand_types[op].bitfield.reg16
3649 || i.tm.operand_types[op].bitfield.reg32
3650 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3651 {
a540244d
L		 3652 as_bad (_("`%s%s' not allowed with `%s%c'"),
3653 register_prefix,
29b0f896
AM		 3654 i.op[op].regs->reg_name,
3655 i.tm.name,
3656 i.suffix);
3657 return 0;
3658 }
3659 /* Warn if the e prefix on a general reg is missing. */
3660 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3661 && i.types[op].bitfield.reg16
3662 && (i.tm.operand_types[op].bitfield.reg32
3663 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3664 {
3665 /* Prohibit these changes in the 64bit mode, since the
3666 lowering is more complicated. */
3667 if (flag_code == CODE_64BIT)
252b5132 3668 {
2ca3ace5
L		 3669 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3670 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3671 i.suffix);
3672 return 0;
252b5132 3673 }
29b0f896
AM		 3674#if REGISTER_WARNINGS
3675 else
a540244d
L		 3676 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3677 register_prefix,
29b0f896 3678 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3679 register_prefix,
29b0f896
AM		 3680 i.op[op].regs->reg_name,
3681 i.suffix);
3682#endif
252b5132 3683 }
29b0f896 3684 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3685 else if (i.types[op].bitfield.reg64
3686 && (i.tm.operand_types[op].bitfield.reg32
3687 || i.tm.operand_types[op].bitfield.acc))
252b5132 3688 {
34828aad
L		 3689 if (intel_syntax
3690 && i.tm.base_opcode == 0xf30f2d
40fb9820 3691 && !i.types[0].bitfield.regxmm)
34828aad
L		 3692 {
3693 /* cvtss2si converts DWORD memory to Reg64. We want
3694 REX byte. */
3695 i.suffix = QWORD_MNEM_SUFFIX;
3696 }
3697 else
3698 {
3699 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3700 register_prefix, i.op[op].regs->reg_name,
3701 i.suffix);
3702 return 0;
3703 }
29b0f896
AM		 3704 }
3705 return 1;
3706}
252b5132 3707
29b0f896 3708static int
e3bb37b5 3709check_qword_reg (void)
29b0f896
AM		 3710{
3711 int op;
252b5132 3712
29b0f896
AM		 3713 for (op = i.operands; --op >= 0; )
3714 /* Reject eight bit registers, except where the template requires
3715 them. (eg. movzb) */
40fb9820
L		 3716 if (i.types[op].bitfield.reg8
3717 && (i.tm.operand_types[op].bitfield.reg16
3718 || i.tm.operand_types[op].bitfield.reg32
3719 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3720 {
a540244d
L		 3721 as_bad (_("`%s%s' not allowed with `%s%c'"),
3722 register_prefix,
29b0f896
AM		 3723 i.op[op].regs->reg_name,
3724 i.tm.name,
3725 i.suffix);
3726 return 0;
3727 }
3728 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 3729 else if ((i.types[op].bitfield.reg16
3730 || i.types[op].bitfield.reg32)
3731 && (i.tm.operand_types[op].bitfield.reg32
3732 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3733 {
3734 /* Prohibit these changes in the 64bit mode, since the
3735 lowering is more complicated. */
34828aad
L		 3736 if (intel_syntax
3737 && i.tm.base_opcode == 0xf20f2d
40fb9820 3738 && !i.types[0].bitfield.regxmm)
34828aad
L		 3739 {
3740 /* cvtsd2si converts QWORD memory to Reg32. We don't want
3741 REX byte. */
3742 i.suffix = LONG_MNEM_SUFFIX;
3743 }
3744 else
3745 {
3746 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3747 register_prefix, i.op[op].regs->reg_name,
3748 i.suffix);
3749 return 0;
3750 }
252b5132 3751 }
29b0f896
AM		 3752 return 1;
3753}
252b5132 3754
29b0f896 3755static int
e3bb37b5 3756check_word_reg (void)
29b0f896
AM		 3757{
3758 int op;
3759 for (op = i.operands; --op >= 0;)
3760 /* Reject eight bit registers, except where the template requires
3761 them. (eg. movzb) */
40fb9820
L		 3762 if (i.types[op].bitfield.reg8
3763 && (i.tm.operand_types[op].bitfield.reg16
3764 || i.tm.operand_types[op].bitfield.reg32
3765 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3766 {
a540244d
L		 3767 as_bad (_("`%s%s' not allowed with `%s%c'"),
3768 register_prefix,
29b0f896
AM		 3769 i.op[op].regs->reg_name,
3770 i.tm.name,
3771 i.suffix);
3772 return 0;
3773 }
3774 /* Warn if the e prefix on a general reg is present. */
3775 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3776 && i.types[op].bitfield.reg32
3777 && (i.tm.operand_types[op].bitfield.reg16
3778 || i.tm.operand_types[op].bitfield.acc))
252b5132 3779 {
29b0f896
AM		 3780 /* Prohibit these changes in the 64bit mode, since the
3781 lowering is more complicated. */
3782 if (flag_code == CODE_64BIT)
252b5132 3783 {
2ca3ace5
L		 3784 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3785 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3786 i.suffix);
3787 return 0;
252b5132 3788 }
29b0f896
AM		 3789 else
3790#if REGISTER_WARNINGS
a540244d
L		 3791 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3792 register_prefix,
29b0f896 3793 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3794 register_prefix,
29b0f896
AM		 3795 i.op[op].regs->reg_name,
3796 i.suffix);
3797#endif
3798 }
3799 return 1;
3800}
252b5132 3801
29b0f896 3802static int
40fb9820 3803update_imm (unsigned int j)
29b0f896 3804{
40fb9820
L		 3805 i386_operand_type overlap;
3806
c6fb90c8 3807 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 3808 if ((overlap.bitfield.imm8
3809 || overlap.bitfield.imm8s
3810 || overlap.bitfield.imm16
3811 || overlap.bitfield.imm32
3812 || overlap.bitfield.imm32s
3813 || overlap.bitfield.imm64)
c6fb90c8
L		 3814 && !UINTS_EQUAL (overlap, imm8)
3815 && !UINTS_EQUAL (overlap, imm8s)
3816 && !UINTS_EQUAL (overlap, imm16)
3817 && !UINTS_EQUAL (overlap, imm32)
3818 && !UINTS_EQUAL (overlap, imm32s)
3819 && !UINTS_EQUAL (overlap, imm64))
29b0f896
AM		 3820 {
3821 if (i.suffix)
3822 {
40fb9820
L		 3823 i386_operand_type temp;
3824
c6fb90c8 3825 UINTS_CLEAR (temp);
40fb9820
L		 3826 if (i.suffix == BYTE_MNEM_SUFFIX)
3827 {
3828 temp.bitfield.imm8 = overlap.bitfield.imm8;
3829 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3830 }
3831 else if (i.suffix == WORD_MNEM_SUFFIX)
3832 temp.bitfield.imm16 = overlap.bitfield.imm16;
3833 else if (i.suffix == QWORD_MNEM_SUFFIX)
3834 {
3835 temp.bitfield.imm64 = overlap.bitfield.imm64;
3836 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3837 }
3838 else
3839 temp.bitfield.imm32 = overlap.bitfield.imm32;
3840 overlap = temp;
29b0f896 3841 }
c6fb90c8
L		 3842 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3843 || UINTS_EQUAL (overlap, imm16_32)
3844 || UINTS_EQUAL (overlap, imm16_32s))
29b0f896 3845 {
c6fb90c8 3846 UINTS_CLEAR (overlap);
40fb9820
L		 3847 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3848 overlap.bitfield.imm16 = 1;
3849 else
3850 overlap.bitfield.imm32s = 1;
29b0f896 3851 }
c6fb90c8
L		 3852 if (!UINTS_EQUAL (overlap, imm8)
3853 && !UINTS_EQUAL (overlap, imm8s)
3854 && !UINTS_EQUAL (overlap, imm16)
3855 && !UINTS_EQUAL (overlap, imm32)
3856 && !UINTS_EQUAL (overlap, imm32s)
3857 && !UINTS_EQUAL (overlap, imm64))
29b0f896 3858 {
4eed87de
AM		 3859 as_bad (_("no instruction mnemonic suffix given; "
3860 "can't determine immediate size"));
29b0f896
AM		 3861 return 0;
3862 }
3863 }
40fb9820 3864 i.types[j] = overlap;
29b0f896 3865
40fb9820
L		 3866 return 1;
3867}
3868
3869static int
3870finalize_imm (void)
3871{
3872 unsigned int j;
29b0f896 3873
40fb9820
L		 3874 for (j = 0; j < 2; j++)
3875 if (update_imm (j) == 0)
3876 return 0;
3877
c6fb90c8 3878 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 3879 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 3880
3881 return 1;
3882}
3883
85f10a01
MM		 3884static void
3885process_drex (void)
3886{
3887 i.drex.modrm_reg = None;
3888 i.drex.modrm_regmem = None;
3889
3890 /* SSE5 4 operand instructions must have the destination the same as
3891 one of the inputs. Figure out the destination register and cache
3892 it away in the drex field, and remember which fields to use for
3893 the modrm byte. */
3894 if (i.tm.opcode_modifier.drex
3895 && i.tm.opcode_modifier.drexv
3896 && i.operands == 4)
3897 {
3898 i.tm.extension_opcode = None;
3899
3900 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3901 if (i.types[0].bitfield.regxmm != 0
3902 && i.types[1].bitfield.regxmm != 0
3903 && i.types[2].bitfield.regxmm != 0
3904 && i.types[3].bitfield.regxmm != 0
3905 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3906 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3907 {
3908 /* Clear the arguments that are stored in drex. */
3909 UINTS_CLEAR (i.types[0]);
3910 UINTS_CLEAR (i.types[3]);
3911 i.reg_operands -= 2;
3912
3913 /* There are two different ways to encode a 4 operand
3914 instruction with all registers that uses OC1 set to
3915 0 or 1. Favor setting OC1 to 0 since this mimics the
3916 actions of other SSE5 assemblers. Use modrm encoding 2
3917 for register/register. Include the high order bit that
3918 is normally stored in the REX byte in the register
3919 field. */
3920 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3921 i.drex.modrm_reg = 2;
3922 i.drex.modrm_regmem = 1;
3923 i.drex.reg = (i.op[3].regs->reg_num
3924 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3925 }
3926
3927 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3928 else if (i.types[0].bitfield.regxmm != 0
3929 && i.types[1].bitfield.regxmm != 0
3930 && (i.types[2].bitfield.regxmm
3931 || operand_type_check (i.types[2], anymem))
3932 && i.types[3].bitfield.regxmm != 0
3933 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3934 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3935 {
3936 /* clear the arguments that are stored in drex */
3937 UINTS_CLEAR (i.types[0]);
3938 UINTS_CLEAR (i.types[3]);
3939 i.reg_operands -= 2;
3940
3941 /* Specify the modrm encoding for memory addressing. Include
3942 the high order bit that is normally stored in the REX byte
3943 in the register field. */
3944 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
3945 i.drex.modrm_reg = 1;
3946 i.drex.modrm_regmem = 2;
3947 i.drex.reg = (i.op[3].regs->reg_num
3948 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3949 }
3950
3951 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3952 else if (i.types[0].bitfield.regxmm != 0
3953 && operand_type_check (i.types[1], anymem) != 0
3954 && i.types[2].bitfield.regxmm != 0
3955 && i.types[3].bitfield.regxmm != 0
3956 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3957 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3958 {
3959 /* Clear the arguments that are stored in drex. */
3960 UINTS_CLEAR (i.types[0]);
3961 UINTS_CLEAR (i.types[3]);
3962 i.reg_operands -= 2;
3963
3964 /* Specify the modrm encoding for memory addressing. Include
3965 the high order bit that is normally stored in the REX byte
3966 in the register field. */
3967 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3968 i.drex.modrm_reg = 2;
3969 i.drex.modrm_regmem = 1;
3970 i.drex.reg = (i.op[3].regs->reg_num
3971 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3972 }
3973
3974 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
3975 else if (i.types[0].bitfield.regxmm != 0
3976 && i.types[1].bitfield.regxmm != 0
3977 && i.types[2].bitfield.regxmm != 0
3978 && i.types[3].bitfield.regxmm != 0
3979 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
3980 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
3981 {
3982 /* clear the arguments that are stored in drex */
3983 UINTS_CLEAR (i.types[2]);
3984 UINTS_CLEAR (i.types[3]);
3985 i.reg_operands -= 2;
3986
3987 /* There are two different ways to encode a 4 operand
3988 instruction with all registers that uses OC1 set to
3989 0 or 1. Favor setting OC1 to 0 since this mimics the
3990 actions of other SSE5 assemblers. Use modrm encoding
3991 2 for register/register. Include the high order bit that
3992 is normally stored in the REX byte in the register
3993 field. */
3994 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
3995 i.drex.modrm_reg = 1;
3996 i.drex.modrm_regmem = 0;
3997
3998 /* Remember the register, including the upper bits */
3999 i.drex.reg = (i.op[3].regs->reg_num
4000 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4001 }
4002
4003 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4004 else if (i.types[0].bitfield.regxmm != 0
4005 && (i.types[1].bitfield.regxmm
4006 || operand_type_check (i.types[1], anymem))
4007 && i.types[2].bitfield.regxmm != 0
4008 && i.types[3].bitfield.regxmm != 0
4009 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4010 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4011 {
4012 /* Clear the arguments that are stored in drex. */
4013 UINTS_CLEAR (i.types[2]);
4014 UINTS_CLEAR (i.types[3]);
4015 i.reg_operands -= 2;
4016
4017 /* Specify the modrm encoding and remember the register
4018 including the bits normally stored in the REX byte. */
4019 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4020 i.drex.modrm_reg = 0;
4021 i.drex.modrm_regmem = 1;
4022 i.drex.reg = (i.op[3].regs->reg_num
4023 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4024 }
4025
4026 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4027 else if (operand_type_check (i.types[0], anymem) != 0
4028 && i.types[1].bitfield.regxmm != 0
4029 && i.types[2].bitfield.regxmm != 0
4030 && i.types[3].bitfield.regxmm != 0
4031 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4032 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4033 {
4034 /* clear the arguments that are stored in drex */
4035 UINTS_CLEAR (i.types[2]);
4036 UINTS_CLEAR (i.types[3]);
4037 i.reg_operands -= 2;
4038
4039 /* Specify the modrm encoding and remember the register
4040 including the bits normally stored in the REX byte. */
4041 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4042 i.drex.modrm_reg = 1;
4043 i.drex.modrm_regmem = 0;
4044 i.drex.reg = (i.op[3].regs->reg_num
4045 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4046 }
4047
4048 else
4049 as_bad (_("Incorrect operands for the '%s' instruction"),
4050 i.tm.name);
4051 }
4052
4053 /* SSE5 instructions with the DREX byte where the only memory operand
4054 is in the 2nd argument, and the first and last xmm register must
4055 match, and is encoded in the DREX byte. */
4056 else if (i.tm.opcode_modifier.drex
4057 && !i.tm.opcode_modifier.drexv
4058 && i.operands == 4)
4059 {
4060 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4061 if (i.types[0].bitfield.regxmm != 0
4062 && (i.types[1].bitfield.regxmm
4063 || operand_type_check(i.types[1], anymem))
4064 && i.types[2].bitfield.regxmm != 0
4065 && i.types[3].bitfield.regxmm != 0
4066 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4067 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4068 {
4069 /* clear the arguments that are stored in drex */
4070 UINTS_CLEAR (i.types[0]);
4071 UINTS_CLEAR (i.types[3]);
4072 i.reg_operands -= 2;
4073
4074 /* Specify the modrm encoding and remember the register
4075 including the high bit normally stored in the REX
4076 byte. */
4077 i.drex.modrm_reg = 2;
4078 i.drex.modrm_regmem = 1;
4079 i.drex.reg = (i.op[3].regs->reg_num
4080 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4081 }
4082
4083 else
4084 as_bad (_("Incorrect operands for the '%s' instruction"),
4085 i.tm.name);
4086 }
4087
4088 /* SSE5 3 operand instructions that the result is a register, being
4089 either operand can be a memory operand, using OC0 to note which
4090 one is the memory. */
4091 else if (i.tm.opcode_modifier.drex
4092 && i.tm.opcode_modifier.drexv
4093 && i.operands == 3)
4094 {
4095 i.tm.extension_opcode = None;
4096
4097 /* Case 1: 3 operand insn, src1 = register. */
4098 if (i.types[0].bitfield.regxmm != 0
4099 && i.types[1].bitfield.regxmm != 0
4100 && i.types[2].bitfield.regxmm != 0)
4101 {
4102 /* Clear the arguments that are stored in drex. */
4103 UINTS_CLEAR (i.types[2]);
4104 i.reg_operands--;
4105
4106 /* Specify the modrm encoding and remember the register
4107 including the high bit normally stored in the REX byte. */
4108 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4109 i.drex.modrm_reg = 1;
4110 i.drex.modrm_regmem = 0;
4111 i.drex.reg = (i.op[2].regs->reg_num
4112 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4113 }
4114
4115 /* Case 2: 3 operand insn, src1 = memory. */
4116 else if (operand_type_check (i.types[0], anymem) != 0
4117 && i.types[1].bitfield.regxmm != 0
4118 && i.types[2].bitfield.regxmm != 0)
4119 {
4120 /* Clear the arguments that are stored in drex. */
4121 UINTS_CLEAR (i.types[2]);
4122 i.reg_operands--;
4123
4124 /* Specify the modrm encoding and remember the register
4125 including the high bit normally stored in the REX
4126 byte. */
4127 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4128 i.drex.modrm_reg = 1;
4129 i.drex.modrm_regmem = 0;
4130 i.drex.reg = (i.op[2].regs->reg_num
4131 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4132 }
4133
4134 /* Case 3: 3 operand insn, src2 = memory. */
4135 else if (i.types[0].bitfield.regxmm != 0
4136 && operand_type_check (i.types[1], anymem) != 0
4137 && i.types[2].bitfield.regxmm != 0)
4138 {
4139 /* Clear the arguments that are stored in drex. */
4140 UINTS_CLEAR (i.types[2]);
4141 i.reg_operands--;
4142
4143 /* Specify the modrm encoding and remember the register
4144 including the high bit normally stored in the REX byte. */
4145 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4146 i.drex.modrm_reg = 0;
4147 i.drex.modrm_regmem = 1;
4148 i.drex.reg = (i.op[2].regs->reg_num
4149 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4150 }
4151
4152 else
4153 as_bad (_("Incorrect operands for the '%s' instruction"),
4154 i.tm.name);
4155 }
4156
4157 /* SSE5 4 operand instructions that are the comparison instructions
4158 where the first operand is the immediate value of the comparison
4159 to be done. */
4160 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4161 {
4162 /* Case 1: 4 operand insn, src1 = reg/memory. */
4163 if (operand_type_check (i.types[0], imm) != 0
4164 && (i.types[1].bitfield.regxmm
4165 || operand_type_check (i.types[1], anymem))
4166 && i.types[2].bitfield.regxmm != 0
4167 && i.types[3].bitfield.regxmm != 0)
4168 {
4169 /* clear the arguments that are stored in drex */
4170 UINTS_CLEAR (i.types[3]);
4171 i.reg_operands--;
4172
4173 /* Specify the modrm encoding and remember the register
4174 including the high bit normally stored in the REX byte. */
4175 i.drex.modrm_reg = 2;
4176 i.drex.modrm_regmem = 1;
4177 i.drex.reg = (i.op[3].regs->reg_num
4178 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4179 }
4180
4181 /* Case 2: 3 operand insn with ImmExt that places the
4182 opcode_extension as an immediate argument. This is used for
4183 all of the varients of comparison that supplies the appropriate
4184 value as part of the instruction. */
4185 else if ((i.types[0].bitfield.regxmm
4186 || operand_type_check (i.types[0], anymem))
4187 && i.types[1].bitfield.regxmm != 0
4188 && i.types[2].bitfield.regxmm != 0
4189 && operand_type_check (i.types[3], imm) != 0)
4190 {
4191 /* clear the arguments that are stored in drex */
4192 UINTS_CLEAR (i.types[2]);
4193 i.reg_operands--;
4194
4195 /* Specify the modrm encoding and remember the register
4196 including the high bit normally stored in the REX byte. */
4197 i.drex.modrm_reg = 1;
4198 i.drex.modrm_regmem = 0;
4199 i.drex.reg = (i.op[2].regs->reg_num
4200 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4201 }
4202
4203 else
4204 as_bad (_("Incorrect operands for the '%s' instruction"),
4205 i.tm.name);
4206 }
4207
4208 else if (i.tm.opcode_modifier.drex
4209 || i.tm.opcode_modifier.drexv
4210 || i.tm.opcode_modifier.drexc)
4211 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4212}
4213
29b0f896 4214static int
e3bb37b5 4215process_operands (void)
29b0f896
AM		 4216{
4217 /* Default segment register this instruction will use for memory
4218 accesses. 0 means unknown. This is only for optimizing out
4219 unnecessary segment overrides. */
4220 const seg_entry *default_seg = 0;
4221
85f10a01
MM		 4222 /* Handle all of the DREX munging that SSE5 needs. */
4223 if (i.tm.opcode_modifier.drex
4224 || i.tm.opcode_modifier.drexv
4225 || i.tm.opcode_modifier.drexc)
4226 process_drex ();
4227
29b0f896
AM		 4228 /* The imul $imm, %reg instruction is converted into
4229 imul $imm, %reg, %reg, and the clr %reg instruction
4230 is converted into xor %reg, %reg. */
40fb9820 4231 if (i.tm.opcode_modifier.regkludge)
29b0f896 4232 {
40fb9820 4233 if (i.tm.cpu_flags.bitfield.cpusse4_1)
42903f7f
L		 4234 {
4235 /* The first operand in instruction blendvpd, blendvps and
4236 pblendvb in SSE4.1 is implicit and must be xmm0. */
4237 assert (i.operands == 3
4238 && i.reg_operands >= 2
c6fb90c8 4239 && UINTS_EQUAL (i.types[0], regxmm));
42903f7f
L		 4240 if (i.op[0].regs->reg_num != 0)
4241 {
4242 if (intel_syntax)
4243 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4244 i.tm.name, register_prefix);
4245 else
4246 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4247 i.tm.name, register_prefix);
4248 return 0;
4249 }
4250 i.op[0] = i.op[1];
4251 i.op[1] = i.op[2];
4252 i.types[0] = i.types[1];
4253 i.types[1] = i.types[2];
4254 i.operands--;
4255 i.reg_operands--;
4256
4257 /* We need to adjust fields in i.tm since they are used by
4258 build_modrm_byte. */
4259 i.tm.operand_types [0] = i.tm.operand_types [1];
4260 i.tm.operand_types [1] = i.tm.operand_types [2];
4261 i.tm.operands--;
4262 }
4263 else
4264 {
40fb9820
L		 4265 unsigned int first_reg_op;
4266
4267 if (operand_type_check (i.types[0], reg))
4268 first_reg_op = 0;
4269 else
4270 first_reg_op = 1;
42903f7f
L		 4271 /* Pretend we saw the extra register operand. */
4272 assert (i.reg_operands == 1
4273 && i.op[first_reg_op + 1].regs == 0);
4274 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4275 i.types[first_reg_op + 1] = i.types[first_reg_op];
4276 i.operands++;
4277 i.reg_operands++;
4278 }
29b0f896
AM		 4279 }
4280
40fb9820 4281 if (i.tm.opcode_modifier.shortform)
29b0f896 4282 {
40fb9820
L		 4283 if (i.types[0].bitfield.sreg2
4284 || i.types[0].bitfield.sreg3)
29b0f896 4285 {
4eed87de
AM		 4286 if (i.tm.base_opcode == POP_SEG_SHORT
4287 && i.op[0].regs->reg_num == 1)
29b0f896 4288 {
4eed87de
AM		 4289 as_bad (_("you can't `pop %%cs'"));
4290 return 0;
29b0f896 4291 }
4eed87de
AM		 4292 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4293 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4294 i.rex |= REX_B;
4eed87de
AM		 4295 }
4296 else
4297 {
85f10a01
MM		 4298 /* The register or float register operand is in operand
4299 0 or 1. */
40fb9820
L		 4300 unsigned int op;
4301
4302 if (i.types[0].bitfield.floatreg
4303 || operand_type_check (i.types[0], reg))
4304 op = 0;
4305 else
4306 op = 1;
4eed87de
AM		 4307 /* Register goes in low 3 bits of opcode. */
4308 i.tm.base_opcode |= i.op[op].regs->reg_num;
4309 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4310 i.rex |= REX_B;
40fb9820 4311 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4312 {
4eed87de
AM		 4313 /* Warn about some common errors, but press on regardless.
4314 The first case can be generated by gcc (<= 2.8.1). */
4315 if (i.operands == 2)
4316 {
4317 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4318 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4319 register_prefix, i.op[1].regs->reg_name,
4320 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4321 }
4322 else
4323 {
4324 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4325 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4326 register_prefix, i.op[0].regs->reg_name);
4eed87de 4327 }
29b0f896
AM		 4328 }
4329 }
4330 }
40fb9820 4331 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4332 {
4333 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4334 must be put into the modrm byte). Now, we make the modrm and
4335 index base bytes based on all the info we've collected. */
29b0f896
AM		 4336
4337 default_seg = build_modrm_byte ();
4338 }
8a2ed489 4339 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4340 {
4341 default_seg = &ds;
4342 }
40fb9820 4343 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4344 {
4345 /* For the string instructions that allow a segment override
4346 on one of their operands, the default segment is ds. */
4347 default_seg = &ds;
4348 }
4349
75178d9d
L		 4350 if (i.tm.base_opcode == 0x8d /* lea */
4351 && i.seg[0]
4352 && !quiet_warnings)
30123838 4353 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4354
4355 /* If a segment was explicitly specified, and the specified segment
4356 is not the default, use an opcode prefix to select it. If we
4357 never figured out what the default segment is, then default_seg
4358 will be zero at this point, and the specified segment prefix will
4359 always be used. */
29b0f896
AM		 4360 if ((i.seg[0]) && (i.seg[0] != default_seg))
4361 {
4362 if (!add_prefix (i.seg[0]->seg_prefix))
4363 return 0;
4364 }
4365 return 1;
4366}
4367
4368static const seg_entry *
e3bb37b5 4369build_modrm_byte (void)
29b0f896
AM		 4370{
4371 const seg_entry *default_seg = 0;
4372
85f10a01
MM		 4373 /* SSE5 4 operand instructions are encoded in such a way that one of
4374 the inputs must match the destination register. Process_drex hides
4375 the 3rd argument in the drex field, so that by the time we get
4376 here, it looks to GAS as if this is a 2 operand instruction. */
4377 if ((i.tm.opcode_modifier.drex
4378 || i.tm.opcode_modifier.drexv
b5016f89 4379 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4380 && i.reg_operands == 2)
4381 {
4382 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4383 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4384
4385 i.rm.reg = reg->reg_num;
4386 i.rm.regmem = regmem->reg_num;
4387 i.rm.mode = 3;
4388 if ((reg->reg_flags & RegRex) != 0)
4389 i.rex |= REX_R;
4390 if ((regmem->reg_flags & RegRex) != 0)
4391 i.rex |= REX_B;
4392 }
4393
29b0f896
AM		 4394 /* i.reg_operands MUST be the number of real register operands;
4395 implicit registers do not count. */
85f10a01 4396 else if (i.reg_operands == 2)
29b0f896
AM		 4397 {
4398 unsigned int source, dest;
cab737b9
L		 4399
4400 switch (i.operands)
4401 {
4402 case 2:
4403 source = 0;
4404 break;
4405 case 3:
c81128dc
L		 4406 /* When there are 3 operands, one of them may be immediate,
4407 which may be the first or the last operand. Otherwise,
4408 the first operand must be shift count register (cl). */
4409 assert (i.imm_operands == 1
4410 || (i.imm_operands == 0
40fb9820
L		 4411 && i.types[0].bitfield.shiftcount));
4412 if (operand_type_check (i.types[0], imm)
4413 || i.types[0].bitfield.shiftcount)
4414 source = 1;
4415 else
4416 source = 0;
cab737b9
L		 4417 break;
4418 case 4:
4419 /* When there are 4 operands, the first two must be immediate
4420 operands. The source operand will be the 3rd one. */
4421 assert (i.imm_operands == 2
40fb9820
L		 4422 && operand_type_check (i.types[0], imm)
4423 && operand_type_check (i.types[1], imm));
cab737b9
L		 4424 source = 2;
4425 break;
4426 default:
4427 abort ();
4428 }
4429
29b0f896
AM		 4430 dest = source + 1;
4431
4432 i.rm.mode = 3;
4433 /* One of the register operands will be encoded in the i.tm.reg
4434 field, the other in the combined i.tm.mode and i.tm.regmem
4435 fields. If no form of this instruction supports a memory
4436 destination operand, then we assume the source operand may
4437 sometimes be a memory operand and so we need to store the
4438 destination in the i.rm.reg field. */
40fb9820
L		 4439 if (!i.tm.operand_types[dest].bitfield.regmem
4440 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4441 {
4442 i.rm.reg = i.op[dest].regs->reg_num;
4443 i.rm.regmem = i.op[source].regs->reg_num;
4444 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4445 i.rex |= REX_R;
29b0f896 4446 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4447 i.rex |= REX_B;
29b0f896
AM		 4448 }
4449 else
4450 {
4451 i.rm.reg = i.op[source].regs->reg_num;
4452 i.rm.regmem = i.op[dest].regs->reg_num;
4453 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4454 i.rex |= REX_B;
29b0f896 4455 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4456 i.rex |= REX_R;
29b0f896 4457 }
161a04f6 4458 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4459 {
40fb9820
L		 4460 if (!i.types[0].bitfield.control
4461 && !i.types[1].bitfield.control)
c4a530c5 4462 abort ();
161a04f6 4463 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4464 add_prefix (LOCK_PREFIX_OPCODE);
4465 }
29b0f896
AM		 4466 }
4467 else
4468 { /* If it's not 2 reg operands... */
4469 if (i.mem_operands)
4470 {
4471 unsigned int fake_zero_displacement = 0;
99018f42 4472 unsigned int op;
4eed87de 4473
85f10a01
MM		 4474 /* This has been precalculated for SSE5 instructions
4475 that have a DREX field earlier in process_drex. */
b5016f89
L		 4476 if (i.tm.opcode_modifier.drex
4477 || i.tm.opcode_modifier.drexv
4478 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4479 op = i.drex.modrm_regmem;
4480 else
4481 {
c0209578
L		 4482 for (op = 0; op < i.operands; op++)
4483 if (operand_type_check (i.types[op], anymem))
4484 break;
4485 assert (op < i.operands);
85f10a01 4486 }
29b0f896
AM		 4487
4488 default_seg = &ds;
4489
4490 if (i.base_reg == 0)
4491 {
4492 i.rm.mode = 0;
4493 if (!i.disp_operands)
4494 fake_zero_displacement = 1;
4495 if (i.index_reg == 0)
4496 {
4497 /* Operand is just <disp> */
20f0a1fc 4498 if (flag_code == CODE_64BIT)
29b0f896
AM		 4499 {
4500 /* 64bit mode overwrites the 32bit absolute
4501 addressing by RIP relative addressing and
4502 absolute addressing is encoded by one of the
4503 redundant SIB forms. */
4504 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4505 i.sib.base = NO_BASE_REGISTER;
4506 i.sib.index = NO_INDEX_REGISTER;
fc225355 4507 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4508 ? disp32s : disp32);
20f0a1fc 4509 }
fc225355
L		 4510 else if ((flag_code == CODE_16BIT)
4511 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4512 {
4513 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4514 i.types[op] = disp16;
20f0a1fc
NC		 4515 }
4516 else
4517 {
4518 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4519 i.types[op] = disp32;
29b0f896
AM		 4520 }
4521 }
4522 else /* !i.base_reg && i.index_reg */
4523 {
db51cc60
L		 4524 if (i.index_reg->reg_num == RegEiz
4525 || i.index_reg->reg_num == RegRiz)
4526 i.sib.index = NO_INDEX_REGISTER;
4527 else
4528 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4529 i.sib.base = NO_BASE_REGISTER;
4530 i.sib.scale = i.log2_scale_factor;
4531 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4532 i.types[op].bitfield.disp8 = 0;
4533 i.types[op].bitfield.disp16 = 0;
4534 i.types[op].bitfield.disp64 = 0;
29b0f896 4535 if (flag_code != CODE_64BIT)
40fb9820
L		 4536 {
4537 /* Must be 32 bit */
4538 i.types[op].bitfield.disp32 = 1;
4539 i.types[op].bitfield.disp32s = 0;
4540 }
29b0f896 4541 else
40fb9820
L		 4542 {
4543 i.types[op].bitfield.disp32 = 0;
4544 i.types[op].bitfield.disp32s = 1;
4545 }
29b0f896 4546 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4547 i.rex |= REX_X;
29b0f896
AM		 4548 }
4549 }
4550 /* RIP addressing for 64bit mode. */
20e192ab 4551 else if (i.base_reg->reg_num == RegRip)
29b0f896
AM		 4552 {
4553 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4554 i.types[op].bitfield.disp8 = 0;
4555 i.types[op].bitfield.disp16 = 0;
4556 i.types[op].bitfield.disp32 = 0;
4557 i.types[op].bitfield.disp32s = 1;
4558 i.types[op].bitfield.disp64 = 0;
71903a11 4559 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4560 if (! i.disp_operands)
4561 fake_zero_displacement = 1;
29b0f896 4562 }
40fb9820 4563 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4564 {
4565 switch (i.base_reg->reg_num)
4566 {
4567 case 3: /* (%bx) */
4568 if (i.index_reg == 0)
4569 i.rm.regmem = 7;
4570 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4571 i.rm.regmem = i.index_reg->reg_num - 6;
4572 break;
4573 case 5: /* (%bp) */
4574 default_seg = &ss;
4575 if (i.index_reg == 0)
4576 {
4577 i.rm.regmem = 6;
40fb9820 4578 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4579 {
4580 /* fake (%bp) into 0(%bp) */
40fb9820 4581 i.types[op].bitfield.disp8 = 1;
252b5132 4582 fake_zero_displacement = 1;
29b0f896
AM		 4583 }
4584 }
4585 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4586 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4587 break;
4588 default: /* (%si) -> 4 or (%di) -> 5 */
4589 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4590 }
4591 i.rm.mode = mode_from_disp_size (i.types[op]);
4592 }
4593 else /* i.base_reg and 32/64 bit mode */
4594 {
4595 if (flag_code == CODE_64BIT
40fb9820
L		 4596 && operand_type_check (i.types[op], disp))
4597 {
4598 i386_operand_type temp;
c6fb90c8 4599 UINTS_CLEAR (temp);
40fb9820
L		 4600 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4601 i.types[op] = temp;
4602 if (i.prefix[ADDR_PREFIX] == 0)
4603 i.types[op].bitfield.disp32s = 1;
4604 else
4605 i.types[op].bitfield.disp32 = 1;
4606 }
20f0a1fc 4607
29b0f896
AM		 4608 i.rm.regmem = i.base_reg->reg_num;
4609 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4610 i.rex |= REX_B;
29b0f896
AM		 4611 i.sib.base = i.base_reg->reg_num;
4612 /* x86-64 ignores REX prefix bit here to avoid decoder
4613 complications. */
4614 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4615 {
4616 default_seg = &ss;
4617 if (i.disp_operands == 0)
4618 {
4619 fake_zero_displacement = 1;
40fb9820 4620 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4621 }
4622 }
4623 else if (i.base_reg->reg_num == ESP_REG_NUM)
4624 {
4625 default_seg = &ss;
4626 }
4627 i.sib.scale = i.log2_scale_factor;
4628 if (i.index_reg == 0)
4629 {
4630 /* <disp>(%esp) becomes two byte modrm with no index
4631 register. We've already stored the code for esp
4632 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4633 Any base register besides %esp will not use the
4634 extra modrm byte. */
4635 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 4636 }
4637 else
4638 {
db51cc60
L		 4639 if (i.index_reg->reg_num == RegEiz
4640 || i.index_reg->reg_num == RegRiz)
4641 i.sib.index = NO_INDEX_REGISTER;
4642 else
4643 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4644 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4645 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4646 i.rex |= REX_X;
29b0f896 4647 }
67a4f2b7
AO		 4648
4649 if (i.disp_operands
4650 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4651 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4652 i.rm.mode = 0;
4653 else
4654 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4655 }
252b5132 4656
29b0f896
AM		 4657 if (fake_zero_displacement)
4658 {
4659 /* Fakes a zero displacement assuming that i.types[op]
4660 holds the correct displacement size. */
4661 expressionS *exp;
4662
4663 assert (i.op[op].disps == 0);
4664 exp = &disp_expressions[i.disp_operands++];
4665 i.op[op].disps = exp;
4666 exp->X_op = O_constant;
4667 exp->X_add_number = 0;
4668 exp->X_add_symbol = (symbolS *) 0;
4669 exp->X_op_symbol = (symbolS *) 0;
4670 }
4671 }
252b5132 4672
29b0f896
AM		 4673 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4674 (if any) based on i.tm.extension_opcode. Again, we must be
4675 careful to make sure that segment/control/debug/test/MMX
4676 registers are coded into the i.rm.reg field. */
4677 if (i.reg_operands)
4678 {
99018f42
L		 4679 unsigned int op;
4680
85f10a01
MM		 4681 /* This has been precalculated for SSE5 instructions
4682 that have a DREX field earlier in process_drex. */
b5016f89
L		 4683 if (i.tm.opcode_modifier.drex
4684 || i.tm.opcode_modifier.drexv
4685 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4686 {
4687 op = i.drex.modrm_reg;
4688 i.rm.reg = i.op[op].regs->reg_num;
4689 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4690 i.rex |= REX_R;
4691 }
4692 else
4693 {
c0209578
L		 4694 for (op = 0; op < i.operands; op++)
4695 if (i.types[op].bitfield.reg8
4696 || i.types[op].bitfield.reg16
4697 || i.types[op].bitfield.reg32
4698 || i.types[op].bitfield.reg64
4699 || i.types[op].bitfield.regmmx
4700 || i.types[op].bitfield.regxmm
4701 || i.types[op].bitfield.sreg2
4702 || i.types[op].bitfield.sreg3
4703 || i.types[op].bitfield.control
4704 || i.types[op].bitfield.debug
4705 || i.types[op].bitfield.test)
4706 break;
4707
4708 assert (op < i.operands);
99018f42 4709
85f10a01
MM		 4710 /* If there is an extension opcode to put here, the
4711 register number must be put into the regmem field. */
c0209578
L		 4712 if (i.tm.extension_opcode != None)
4713 {
4714 i.rm.regmem = i.op[op].regs->reg_num;
4715 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4716 i.rex |= REX_B;
4717 }
4718 else
4719 {
4720 i.rm.reg = i.op[op].regs->reg_num;
4721 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4722 i.rex |= REX_R;
4723 }
85f10a01 4724 }
252b5132 4725
29b0f896
AM		 4726 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4727 must set it to 3 to indicate this is a register operand
4728 in the regmem field. */
4729 if (!i.mem_operands)
4730 i.rm.mode = 3;
4731 }
252b5132 4732
29b0f896 4733 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 4734 if (i.tm.extension_opcode != None
4735 && !(i.tm.opcode_modifier.drex
4736 || i.tm.opcode_modifier.drexv
4737 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 4738 i.rm.reg = i.tm.extension_opcode;
4739 }
4740 return default_seg;
4741}
252b5132 4742
29b0f896 4743static void
e3bb37b5 4744output_branch (void)
29b0f896
AM		 4745{
4746 char *p;
4747 int code16;
4748 int prefix;
4749 relax_substateT subtype;
4750 symbolS *sym;
4751 offsetT off;
4752
4753 code16 = 0;
4754 if (flag_code == CODE_16BIT)
4755 code16 = CODE16;
4756
4757 prefix = 0;
4758 if (i.prefix[DATA_PREFIX] != 0)
252b5132 4759 {
29b0f896
AM		 4760 prefix = 1;
4761 i.prefixes -= 1;
4762 code16 ^= CODE16;
252b5132 4763 }
29b0f896
AM		 4764 /* Pentium4 branch hints. */
4765 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4766 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 4767 {
29b0f896
AM		 4768 prefix++;
4769 i.prefixes--;
4770 }
4771 if (i.prefix[REX_PREFIX] != 0)
4772 {
4773 prefix++;
4774 i.prefixes--;
2f66722d
AM		 4775 }
4776
29b0f896
AM		 4777 if (i.prefixes != 0 && !intel_syntax)
4778 as_warn (_("skipping prefixes on this instruction"));
4779
4780 /* It's always a symbol; End frag & setup for relax.
4781 Make sure there is enough room in this frag for the largest
4782 instruction we may generate in md_convert_frag. This is 2
4783 bytes for the opcode and room for the prefix and largest
4784 displacement. */
4785 frag_grow (prefix + 2 + 4);
4786 /* Prefix and 1 opcode byte go in fr_fix. */
4787 p = frag_more (prefix + 1);
4788 if (i.prefix[DATA_PREFIX] != 0)
4789 *p++ = DATA_PREFIX_OPCODE;
4790 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4791 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4792 *p++ = i.prefix[SEG_PREFIX];
4793 if (i.prefix[REX_PREFIX] != 0)
4794 *p++ = i.prefix[REX_PREFIX];
4795 *p = i.tm.base_opcode;
4796
4797 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4798 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 4799 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 4800 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4801 else
4802 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4803 subtype |= code16;
3e73aa7c 4804
29b0f896
AM		 4805 sym = i.op[0].disps->X_add_symbol;
4806 off = i.op[0].disps->X_add_number;
3e73aa7c 4807
29b0f896
AM		 4808 if (i.op[0].disps->X_op != O_constant
4809 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 4810 {
29b0f896
AM		 4811 /* Handle complex expressions. */
4812 sym = make_expr_symbol (i.op[0].disps);
4813 off = 0;
4814 }
3e73aa7c 4815
29b0f896
AM		 4816 /* 1 possible extra opcode + 4 byte displacement go in var part.
4817 Pass reloc in fr_var. */
4818 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4819}
3e73aa7c 4820
29b0f896 4821static void
e3bb37b5 4822output_jump (void)
29b0f896
AM		 4823{
4824 char *p;
4825 int size;
3e02c1cc 4826 fixS *fixP;
29b0f896 4827
40fb9820 4828 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 4829 {
4830 /* This is a loop or jecxz type instruction. */
4831 size = 1;
4832 if (i.prefix[ADDR_PREFIX] != 0)
4833 {
4834 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4835 i.prefixes -= 1;
4836 }
4837 /* Pentium4 branch hints. */
4838 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4839 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4840 {
4841 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4842 i.prefixes--;
3e73aa7c
JH		 4843 }
4844 }
29b0f896
AM		 4845 else
4846 {
4847 int code16;
3e73aa7c 4848
29b0f896
AM		 4849 code16 = 0;
4850 if (flag_code == CODE_16BIT)
4851 code16 = CODE16;
3e73aa7c 4852
29b0f896
AM		 4853 if (i.prefix[DATA_PREFIX] != 0)
4854 {
4855 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4856 i.prefixes -= 1;
4857 code16 ^= CODE16;
4858 }
252b5132 4859
29b0f896
AM		 4860 size = 4;
4861 if (code16)
4862 size = 2;
4863 }
9fcc94b6 4864
29b0f896
AM		 4865 if (i.prefix[REX_PREFIX] != 0)
4866 {
4867 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4868 i.prefixes -= 1;
4869 }
252b5132 4870
29b0f896
AM		 4871 if (i.prefixes != 0 && !intel_syntax)
4872 as_warn (_("skipping prefixes on this instruction"));
e0890092 4873
29b0f896
AM		 4874 p = frag_more (1 + size);
4875 *p++ = i.tm.base_opcode;
e0890092 4876
3e02c1cc
AM		 4877 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4878 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4879
4880 /* All jumps handled here are signed, but don't use a signed limit
4881 check for 32 and 16 bit jumps as we want to allow wrap around at
4882 4G and 64k respectively. */
4883 if (size == 1)
4884 fixP->fx_signed = 1;
29b0f896 4885}
e0890092 4886
29b0f896 4887static void
e3bb37b5 4888output_interseg_jump (void)
29b0f896
AM		 4889{
4890 char *p;
4891 int size;
4892 int prefix;
4893 int code16;
252b5132 4894
29b0f896
AM		 4895 code16 = 0;
4896 if (flag_code == CODE_16BIT)
4897 code16 = CODE16;
a217f122 4898
29b0f896
AM		 4899 prefix = 0;
4900 if (i.prefix[DATA_PREFIX] != 0)
4901 {
4902 prefix = 1;
4903 i.prefixes -= 1;
4904 code16 ^= CODE16;
4905 }
4906 if (i.prefix[REX_PREFIX] != 0)
4907 {
4908 prefix++;
4909 i.prefixes -= 1;
4910 }
252b5132 4911
29b0f896
AM		 4912 size = 4;
4913 if (code16)
4914 size = 2;
252b5132 4915
29b0f896
AM		 4916 if (i.prefixes != 0 && !intel_syntax)
4917 as_warn (_("skipping prefixes on this instruction"));
252b5132 4918
29b0f896
AM		 4919 /* 1 opcode; 2 segment; offset */
4920 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 4921
29b0f896
AM		 4922 if (i.prefix[DATA_PREFIX] != 0)
4923 *p++ = DATA_PREFIX_OPCODE;
252b5132 4924
29b0f896
AM		 4925 if (i.prefix[REX_PREFIX] != 0)
4926 *p++ = i.prefix[REX_PREFIX];
252b5132 4927
29b0f896
AM		 4928 *p++ = i.tm.base_opcode;
4929 if (i.op[1].imms->X_op == O_constant)
4930 {
4931 offsetT n = i.op[1].imms->X_add_number;
252b5132 4932
29b0f896
AM		 4933 if (size == 2
4934 && !fits_in_unsigned_word (n)
4935 && !fits_in_signed_word (n))
4936 {
4937 as_bad (_("16-bit jump out of range"));
4938 return;
4939 }
4940 md_number_to_chars (p, n, size);
4941 }
4942 else
4943 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4944 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4945 if (i.op[0].imms->X_op != O_constant)
4946 as_bad (_("can't handle non absolute segment in `%s'"),
4947 i.tm.name);
4948 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4949}
a217f122 4950
29b0f896 4951static void
e3bb37b5 4952output_insn (void)
29b0f896 4953{
2bbd9c25
JJ		 4954 fragS *insn_start_frag;
4955 offsetT insn_start_off;
4956
29b0f896
AM		 4957 /* Tie dwarf2 debug info to the address at the start of the insn.
4958 We can't do this after the insn has been output as the current
4959 frag may have been closed off. eg. by frag_var. */
4960 dwarf2_emit_insn (0);
4961
2bbd9c25
JJ		 4962 insn_start_frag = frag_now;
4963 insn_start_off = frag_now_fix ();
4964
29b0f896 4965 /* Output jumps. */
40fb9820 4966 if (i.tm.opcode_modifier.jump)
29b0f896 4967 output_branch ();
40fb9820
L		 4968 else if (i.tm.opcode_modifier.jumpbyte
4969 || i.tm.opcode_modifier.jumpdword)
29b0f896 4970 output_jump ();
40fb9820 4971 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 4972 output_interseg_jump ();
4973 else
4974 {
4975 /* Output normal instructions here. */
4976 char *p;
4977 unsigned char *q;
331d2d0d 4978 unsigned int prefix;
40fb9820 4979 int opc_3b;
252b5132 4980
42903f7f 4981 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
85f10a01
MM		 4982 SSE4 and SSE5 instructions have 3 bytes. We may use one
4983 more higher byte to specify a prefix the instruction
4984 requires. Exclude instructions which are in both SSE4.2
4985 and ABM. */
cf557b51 4986 opc_3b = (i.tm.cpu_flags.bitfield.cpussse3
85f10a01 4987 || i.tm.cpu_flags.bitfield.cpusse5
cf557b51
L		 4988 || i.tm.cpu_flags.bitfield.cpusse4_1
4989 || (i.tm.cpu_flags.bitfield.cpusse4_2
4990 && !i.tm.cpu_flags.bitfield.cpuabm));
40fb9820 4991 if (opc_3b)
bc4bd9ab 4992 {
331d2d0d
L		 4993 if (i.tm.base_opcode & 0xff000000)
4994 {
4995 prefix = (i.tm.base_opcode >> 24) & 0xff;
4996 goto check_prefix;
4997 }
4998 }
4999 else if ((i.tm.base_opcode & 0xff0000) != 0)
5000 {
5001 prefix = (i.tm.base_opcode >> 16) & 0xff;
40fb9820 5002 if (i.tm.cpu_flags.bitfield.cpupadlock)
bc4bd9ab 5003 {
64e74474 5004 check_prefix:
bc4bd9ab
MK		 5005 if (prefix != REPE_PREFIX_OPCODE
5006 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5007 add_prefix (prefix);
5008 }
5009 else
331d2d0d 5010 add_prefix (prefix);
0f10071e 5011 }
252b5132 5012
29b0f896
AM		 5013 /* The prefix bytes. */
5014 for (q = i.prefix;
5015 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
5016 q++)
5017 {
5018 if (*q)
5019 {
5020 p = frag_more (1);
5021 md_number_to_chars (p, (valueT) *q, 1);
5022 }
5023 }
252b5132 5024
29b0f896
AM		 5025 /* Now the opcode; be careful about word order here! */
5026 if (fits_in_unsigned_byte (i.tm.base_opcode))
5027 {
5028 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5029 }
5030 else
5031 {
40fb9820 5032 if (opc_3b)
331d2d0d
L		 5033 {
5034 p = frag_more (3);
5035 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5036 }
5037 else
5038 p = frag_more (2);
0f10071e 5039
29b0f896
AM		 5040 /* Put out high byte first: can't use md_number_to_chars! */
5041 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5042 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5043
5044 /* On SSE5, encode the OC1 bit in the DREX field if this
5045 encoding has multiple formats. */
5046 if (i.tm.opcode_modifier.drex
5047 && i.tm.opcode_modifier.drexv
5048 && DREX_OC1 (i.tm.extension_opcode))
5049 *p |= DREX_OC1_MASK;
29b0f896 5050 }
3e73aa7c 5051
29b0f896 5052 /* Now the modrm byte and sib byte (if present). */
40fb9820 5053 if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5054 {
5055 p = frag_more (1);
5056 md_number_to_chars (p,
5057 (valueT) (i.rm.regmem << 0
5058 | i.rm.reg << 3
5059 | i.rm.mode << 6),
5060 1);
5061 /* If i.rm.regmem == ESP (4)
5062 && i.rm.mode != (Register mode)
5063 && not 16 bit
5064 ==> need second modrm byte. */
5065 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5066 && i.rm.mode != 3
40fb9820 5067 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
29b0f896
AM		 5068 {
5069 p = frag_more (1);
5070 md_number_to_chars (p,
5071 (valueT) (i.sib.base << 0
5072 | i.sib.index << 3
5073 | i.sib.scale << 6),
5074 1);
5075 }
5076 }
3e73aa7c 5077
85f10a01
MM		 5078 /* Write the DREX byte if needed. */
5079 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5080 {
5081 p = frag_more (1);
5082 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5083
5084 /* Encode the OC0 bit if this encoding has multiple
5085 formats. */
5086 if ((i.tm.opcode_modifier.drex
5087 || i.tm.opcode_modifier.drexv)
5088 && DREX_OC0 (i.tm.extension_opcode))
5089 *p |= DREX_OC0_MASK;
5090 }
5091
29b0f896 5092 if (i.disp_operands)
2bbd9c25 5093 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5094
29b0f896 5095 if (i.imm_operands)
2bbd9c25 5096 output_imm (insn_start_frag, insn_start_off);
29b0f896 5097 }
252b5132 5098
29b0f896
AM		 5099#ifdef DEBUG386
5100 if (flag_debug)
5101 {
7b81dfbb 5102 pi ("" /*line*/, &i);
29b0f896
AM		 5103 }
5104#endif /* DEBUG386 */
5105}
252b5132 5106
e205caa7
L		 5107/* Return the size of the displacement operand N. */
5108
5109static int
5110disp_size (unsigned int n)
5111{
5112 int size = 4;
40fb9820
L		 5113 if (i.types[n].bitfield.disp64)
5114 size = 8;
5115 else if (i.types[n].bitfield.disp8)
5116 size = 1;
5117 else if (i.types[n].bitfield.disp16)
5118 size = 2;
e205caa7
L		 5119 return size;
5120}
5121
5122/* Return the size of the immediate operand N. */
5123
5124static int
5125imm_size (unsigned int n)
5126{
5127 int size = 4;
40fb9820
L		 5128 if (i.types[n].bitfield.imm64)
5129 size = 8;
5130 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5131 size = 1;
5132 else if (i.types[n].bitfield.imm16)
5133 size = 2;
e205caa7
L		 5134 return size;
5135}
5136
29b0f896 5137static void
64e74474 5138output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5139{
5140 char *p;
5141 unsigned int n;
252b5132 5142
29b0f896
AM		 5143 for (n = 0; n < i.operands; n++)
5144 {
40fb9820 5145 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5146 {
5147 if (i.op[n].disps->X_op == O_constant)
5148 {
e205caa7 5149 int size = disp_size (n);
29b0f896 5150 offsetT val;
252b5132 5151
29b0f896
AM		 5152 val = offset_in_range (i.op[n].disps->X_add_number,
5153 size);
5154 p = frag_more (size);
5155 md_number_to_chars (p, val, size);
5156 }
5157 else
5158 {
f86103b7 5159 enum bfd_reloc_code_real reloc_type;
e205caa7 5160 int size = disp_size (n);
40fb9820 5161 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5162 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5163
e205caa7 5164 /* We can't have 8 bit displacement here. */
40fb9820 5165 assert (!i.types[n].bitfield.disp8);
e205caa7 5166
29b0f896
AM		 5167 /* The PC relative address is computed relative
5168 to the instruction boundary, so in case immediate
5169 fields follows, we need to adjust the value. */
5170 if (pcrel && i.imm_operands)
5171 {
29b0f896 5172 unsigned int n1;
e205caa7 5173 int sz = 0;
252b5132 5174
29b0f896 5175 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5176 if (operand_type_check (i.types[n1], imm))
252b5132 5177 {
e205caa7
L		 5178 /* Only one immediate is allowed for PC
5179 relative address. */
5180 assert (sz == 0);
5181 sz = imm_size (n1);
5182 i.op[n].disps->X_add_number -= sz;
252b5132 5183 }
29b0f896 5184 /* We should find the immediate. */
e205caa7 5185 assert (sz != 0);
29b0f896 5186 }
520dc8e8 5187
29b0f896 5188 p = frag_more (size);
2bbd9c25 5189 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5190 if (GOT_symbol
2bbd9c25 5191 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5192 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5193 || reloc_type == BFD_RELOC_X86_64_32S
5194 || (reloc_type == BFD_RELOC_64
5195 && object_64bit))
d6ab8113
JB		 5196 && (i.op[n].disps->X_op == O_symbol
5197 || (i.op[n].disps->X_op == O_add
5198 && ((symbol_get_value_expression
5199 (i.op[n].disps->X_op_symbol)->X_op)
5200 == O_subtract))))
5201 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5202 {
5203 offsetT add;
5204
5205 if (insn_start_frag == frag_now)
5206 add = (p - frag_now->fr_literal) - insn_start_off;
5207 else
5208 {
5209 fragS *fr;
5210
5211 add = insn_start_frag->fr_fix - insn_start_off;
5212 for (fr = insn_start_frag->fr_next;
5213 fr && fr != frag_now; fr = fr->fr_next)
5214 add += fr->fr_fix;
5215 add += p - frag_now->fr_literal;
5216 }
5217
4fa24527 5218 if (!object_64bit)
7b81dfbb
AJ		 5219 {
5220 reloc_type = BFD_RELOC_386_GOTPC;
5221 i.op[n].imms->X_add_number += add;
5222 }
5223 else if (reloc_type == BFD_RELOC_64)
5224 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5225 else
7b81dfbb
AJ		 5226 /* Don't do the adjustment for x86-64, as there
5227 the pcrel addressing is relative to the _next_
5228 insn, and that is taken care of in other code. */
d6ab8113 5229 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5230 }
062cd5e7 5231 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5232 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5233 }
5234 }
5235 }
5236}
252b5132 5237
29b0f896 5238static void
64e74474 5239output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5240{
5241 char *p;
5242 unsigned int n;
252b5132 5243
29b0f896
AM		 5244 for (n = 0; n < i.operands; n++)
5245 {
40fb9820 5246 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5247 {
5248 if (i.op[n].imms->X_op == O_constant)
5249 {
e205caa7 5250 int size = imm_size (n);
29b0f896 5251 offsetT val;
b4cac588 5252
29b0f896
AM		 5253 val = offset_in_range (i.op[n].imms->X_add_number,
5254 size);
5255 p = frag_more (size);
5256 md_number_to_chars (p, val, size);
5257 }
5258 else
5259 {
5260 /* Not absolute_section.
5261 Need a 32-bit fixup (don't support 8bit
5262 non-absolute imms). Try to support other
5263 sizes ... */
f86103b7 5264 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5265 int size = imm_size (n);
5266 int sign;
29b0f896 5267
40fb9820 5268 if (i.types[n].bitfield.imm32s
a7d61044 5269 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5270 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5271 sign = 1;
e205caa7
L		 5272 else
5273 sign = 0;
520dc8e8 5274
29b0f896
AM		 5275 p = frag_more (size);
5276 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5277
2bbd9c25
JJ		 5278 /* This is tough to explain. We end up with this one if we
5279 * have operands that look like
5280 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5281 * obtain the absolute address of the GOT, and it is strongly
5282 * preferable from a performance point of view to avoid using
5283 * a runtime relocation for this. The actual sequence of
5284 * instructions often look something like:
5285 *
5286 * call .L66
5287 * .L66:
5288 * popl %ebx
5289 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5290 *
5291 * The call and pop essentially return the absolute address
5292 * of the label .L66 and store it in %ebx. The linker itself
5293 * will ultimately change the first operand of the addl so
5294 * that %ebx points to the GOT, but to keep things simple, the
5295 * .o file must have this operand set so that it generates not
5296 * the absolute address of .L66, but the absolute address of
5297 * itself. This allows the linker itself simply treat a GOTPC
5298 * relocation as asking for a pcrel offset to the GOT to be
5299 * added in, and the addend of the relocation is stored in the
5300 * operand field for the instruction itself.
5301 *
5302 * Our job here is to fix the operand so that it would add
5303 * the correct offset so that %ebx would point to itself. The
5304 * thing that is tricky is that .-.L66 will point to the
5305 * beginning of the instruction, so we need to further modify
5306 * the operand so that it will point to itself. There are
5307 * other cases where you have something like:
5308 *
5309 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5310 *
5311 * and here no correction would be required. Internally in
5312 * the assembler we treat operands of this form as not being
5313 * pcrel since the '.' is explicitly mentioned, and I wonder
5314 * whether it would simplify matters to do it this way. Who
5315 * knows. In earlier versions of the PIC patches, the
5316 * pcrel_adjust field was used to store the correction, but
5317 * since the expression is not pcrel, I felt it would be
5318 * confusing to do it this way. */
5319
d6ab8113 5320 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5321 || reloc_type == BFD_RELOC_X86_64_32S
5322 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5323 && GOT_symbol
5324 && GOT_symbol == i.op[n].imms->X_add_symbol
5325 && (i.op[n].imms->X_op == O_symbol
5326 || (i.op[n].imms->X_op == O_add
5327 && ((symbol_get_value_expression
5328 (i.op[n].imms->X_op_symbol)->X_op)
5329 == O_subtract))))
5330 {
2bbd9c25
JJ		 5331 offsetT add;
5332
5333 if (insn_start_frag == frag_now)
5334 add = (p - frag_now->fr_literal) - insn_start_off;
5335 else
5336 {
5337 fragS *fr;
5338
5339 add = insn_start_frag->fr_fix - insn_start_off;
5340 for (fr = insn_start_frag->fr_next;
5341 fr && fr != frag_now; fr = fr->fr_next)
5342 add += fr->fr_fix;
5343 add += p - frag_now->fr_literal;
5344 }
5345
4fa24527 5346 if (!object_64bit)
d6ab8113 5347 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5348 else if (size == 4)
d6ab8113 5349 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5350 else if (size == 8)
5351 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5352 i.op[n].imms->X_add_number += add;
29b0f896 5353 }
29b0f896
AM		 5354 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5355 i.op[n].imms, 0, reloc_type);
5356 }
5357 }
5358 }
252b5132
RH		 5359}
5360\f
d182319b
JB		 5361/* x86_cons_fix_new is called via the expression parsing code when a
5362 reloc is needed. We use this hook to get the correct .got reloc. */
5363static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5364static int cons_sign = -1;
5365
5366void
e3bb37b5 5367x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5368 expressionS *exp)
d182319b
JB		 5369{
5370 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5371
5372 got_reloc = NO_RELOC;
5373
5374#ifdef TE_PE
5375 if (exp->X_op == O_secrel)
5376 {
5377 exp->X_op = O_symbol;
5378 r = BFD_RELOC_32_SECREL;
5379 }
5380#endif
5381
5382 fix_new_exp (frag, off, len, exp, 0, r);
5383}
5384
718ddfc0
JB		 5385#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5386# define lex_got(reloc, adjust, types) NULL
5387#else
f3c180ae
AM		 5388/* Parse operands of the form
5389 <symbol>@GOTOFF+<nnn>
5390 and similar .plt or .got references.
5391
5392 If we find one, set up the correct relocation in RELOC and copy the
5393 input string, minus the `@GOTOFF' into a malloc'd buffer for
5394 parsing by the calling routine. Return this buffer, and if ADJUST
5395 is non-null set it to the length of the string we removed from the
5396 input line. Otherwise return NULL. */
5397static char *
3956db08 5398lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5399 int *adjust,
40fb9820 5400 i386_operand_type *types)
f3c180ae 5401{
7b81dfbb
AJ		 5402 /* Some of the relocations depend on the size of what field is to
5403 be relocated. But in our callers i386_immediate and i386_displacement
5404 we don't yet know the operand size (this will be set by insn
5405 matching). Hence we record the word32 relocation here,
5406 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5407 static const struct {
5408 const char *str;
4fa24527 5409 const enum bfd_reloc_code_real rel[2];
40fb9820 5410 const i386_operand_type types64;
f3c180ae 5411 } gotrel[] = {
4eed87de
AM		 5412 { "PLTOFF", { 0,
5413 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5414 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5415 { "PLT", { BFD_RELOC_386_PLT32,
5416 BFD_RELOC_X86_64_PLT32 },
40fb9820 5417 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5418 { "GOTPLT", { 0,
5419 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5420 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5421 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5422 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5423 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5424 { "GOTPCREL", { 0,
5425 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5426 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5427 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5428 BFD_RELOC_X86_64_TLSGD },
40fb9820 5429 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5430 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5431 0 },
40fb9820 5432 OPERAND_TYPE_NONE },
4eed87de
AM		 5433 { "TLSLD", { 0,
5434 BFD_RELOC_X86_64_TLSLD },
40fb9820 5435 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5436 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5437 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5438 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5439 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5440 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5441 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5442 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5443 0 },
40fb9820 5444 OPERAND_TYPE_NONE },
4eed87de
AM		 5445 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5446 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5447
5448 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5449 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5450 0 },
40fb9820 5451 OPERAND_TYPE_NONE },
4eed87de
AM		 5452 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5453 0 },
40fb9820 5454 OPERAND_TYPE_NONE },
4eed87de
AM		 5455 { "GOT", { BFD_RELOC_386_GOT32,
5456 BFD_RELOC_X86_64_GOT32 },
40fb9820 5457 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5458 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5459 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5460 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5461 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5462 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5463 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5464 };
5465 char *cp;
5466 unsigned int j;
5467
718ddfc0
JB		 5468 if (!IS_ELF)
5469 return NULL;
5470
f3c180ae 5471 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5472 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5473 return NULL;
5474
5475 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
5476 {
5477 int len;
5478
5479 len = strlen (gotrel[j].str);
28f81592 5480 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5481 {
4fa24527 5482 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5483 {
28f81592
AM		 5484 int first, second;
5485 char *tmpbuf, *past_reloc;
f3c180ae 5486
4fa24527 5487 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5488 if (adjust)
5489 *adjust = len;
f3c180ae 5490
3956db08
JB		 5491 if (types)
5492 {
5493 if (flag_code != CODE_64BIT)
40fb9820
L		 5494 {
5495 types->bitfield.imm32 = 1;
5496 types->bitfield.disp32 = 1;
5497 }
3956db08
JB		 5498 else
5499 *types = gotrel[j].types64;
5500 }
5501
f3c180ae
AM		 5502 if (GOT_symbol == NULL)
5503 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5504
28f81592 5505 /* The length of the first part of our input line. */
f3c180ae 5506 first = cp - input_line_pointer;
28f81592
AM		 5507
5508 /* The second part goes from after the reloc token until
67c11a9b 5509 (and including) an end_of_line char or comma. */
28f81592 5510 past_reloc = cp + 1 + len;
67c11a9b
AM		 5511 cp = past_reloc;
5512 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5513 ++cp;
5514 second = cp + 1 - past_reloc;
28f81592
AM		 5515
5516 /* Allocate and copy string. The trailing NUL shouldn't
5517 be necessary, but be safe. */
5518 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5519 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5520 if (second != 0 && *past_reloc != ' ')
5521 /* Replace the relocation token with ' ', so that
5522 errors like foo@GOTOFF1 will be detected. */
5523 tmpbuf[first++] = ' ';
5524 memcpy (tmpbuf + first, past_reloc, second);
5525 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5526 return tmpbuf;
5527 }
5528
4fa24527
JB		 5529 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5530 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5531 return NULL;
5532 }
5533 }
5534
5535 /* Might be a symbol version string. Don't as_bad here. */
5536 return NULL;
5537}
5538
f3c180ae 5539void
e3bb37b5 5540x86_cons (expressionS *exp, int size)
f3c180ae 5541{
4fa24527 5542 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5543 {
5544 /* Handle @GOTOFF and the like in an expression. */
5545 char *save;
5546 char *gotfree_input_line;
5547 int adjust;
5548
5549 save = input_line_pointer;
3956db08 5550 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5551 if (gotfree_input_line)
5552 input_line_pointer = gotfree_input_line;
5553
5554 expression (exp);
5555
5556 if (gotfree_input_line)
5557 {
5558 /* expression () has merrily parsed up to the end of line,
5559 or a comma - in the wrong buffer. Transfer how far
5560 input_line_pointer has moved to the right buffer. */
5561 input_line_pointer = (save
5562 + (input_line_pointer - gotfree_input_line)
5563 + adjust);
5564 free (gotfree_input_line);
3992d3b7
AM		 5565 if (exp->X_op == O_constant
5566 || exp->X_op == O_absent
5567 || exp->X_op == O_illegal
5568 || exp->X_op == O_register
5569 || exp->X_op == O_big)
5570 {
5571 char c = *input_line_pointer;
5572 *input_line_pointer = 0;
5573 as_bad (_("missing or invalid expression `%s'"), save);
5574 *input_line_pointer = c;
5575 }
f3c180ae
AM		 5576 }
5577 }
5578 else
5579 expression (exp);
5580}
5581#endif
5582
d182319b 5583static void signed_cons (int size)
6482c264 5584{
d182319b
JB		 5585 if (flag_code == CODE_64BIT)
5586 cons_sign = 1;
5587 cons (size);
5588 cons_sign = -1;
6482c264
NC		 5589}
5590
d182319b 5591#ifdef TE_PE
6482c264
NC		 5592static void
5593pe_directive_secrel (dummy)
5594 int dummy ATTRIBUTE_UNUSED;
5595{
5596 expressionS exp;
5597
5598 do
5599 {
5600 expression (&exp);
5601 if (exp.X_op == O_symbol)
5602 exp.X_op = O_secrel;
5603
5604 emit_expr (&exp, 4);
5605 }
5606 while (*input_line_pointer++ == ',');
5607
5608 input_line_pointer--;
5609 demand_empty_rest_of_line ();
5610}
6482c264
NC		 5611#endif
5612
252b5132 5613static int
70e41ade 5614i386_immediate (char *imm_start)
252b5132
RH		 5615{
5616 char *save_input_line_pointer;
f3c180ae 5617 char *gotfree_input_line;
252b5132 5618 segT exp_seg = 0;
47926f60 5619 expressionS *exp;
40fb9820
L		 5620 i386_operand_type types;
5621
c6fb90c8 5622 UINTS_SET (types, ~0);
252b5132
RH		 5623
5624 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5625 {
31b2323c
L		 5626 as_bad (_("at most %d immediate operands are allowed"),
5627 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5628 return 0;
5629 }
5630
5631 exp = &im_expressions[i.imm_operands++];
520dc8e8 5632 i.op[this_operand].imms = exp;
252b5132
RH		 5633
5634 if (is_space_char (*imm_start))
5635 ++imm_start;
5636
5637 save_input_line_pointer = input_line_pointer;
5638 input_line_pointer = imm_start;
5639
3956db08 5640 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5641 if (gotfree_input_line)
5642 input_line_pointer = gotfree_input_line;
252b5132
RH		 5643
5644 exp_seg = expression (exp);
5645
83183c0c 5646 SKIP_WHITESPACE ();
252b5132 5647 if (*input_line_pointer)
f3c180ae 5648 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5649
5650 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5651 if (gotfree_input_line)
5652 free (gotfree_input_line);
252b5132 5653
3992d3b7
AM		 5654 if (exp->X_op == O_absent
5655 || exp->X_op == O_illegal
5656 || exp->X_op == O_big
5657 || (gotfree_input_line
5658 && (exp->X_op == O_constant
5659 || exp->X_op == O_register)))
252b5132 5660 {
3992d3b7 5661 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5662 imm_start);
3992d3b7 5663 return 0;
252b5132 5664 }
3e73aa7c 5665 else if (exp->X_op == O_constant)
252b5132 5666 {
47926f60 5667 /* Size it properly later. */
40fb9820 5668 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5669 /* If BFD64, sign extend val. */
4eed87de
AM		 5670 if (!use_rela_relocations
5671 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5672 exp->X_add_number
5673 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5674 }
4c63da97 5675#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5676 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5677 && exp_seg != absolute_section
47926f60 5678 && exp_seg != text_section
24eab124
AM		 5679 && exp_seg != data_section
5680 && exp_seg != bss_section
5681 && exp_seg != undefined_section
f86103b7 5682 && !bfd_is_com_section (exp_seg))
252b5132 5683 {
d0b47220 5684 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5685 return 0;
5686 }
5687#endif
bb8f5920
L		 5688 else if (!intel_syntax && exp->X_op == O_register)
5689 {
5690 as_bad (_("illegal immediate register operand %s"), imm_start);
5691 return 0;
5692 }
252b5132
RH		 5693 else
5694 {
5695 /* This is an address. The size of the address will be
24eab124 5696 determined later, depending on destination register,
3e73aa7c 5697 suffix, or the default for the section. */
40fb9820
L		 5698 i.types[this_operand].bitfield.imm8 = 1;
5699 i.types[this_operand].bitfield.imm16 = 1;
5700 i.types[this_operand].bitfield.imm32 = 1;
5701 i.types[this_operand].bitfield.imm32s = 1;
5702 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 5703 i.types[this_operand] = operand_type_and (i.types[this_operand],
5704 types);
252b5132
RH		 5705 }
5706
5707 return 1;
5708}
5709
551c1ca1 5710static char *
e3bb37b5 5711i386_scale (char *scale)
252b5132 5712{
551c1ca1
AM		 5713 offsetT val;
5714 char *save = input_line_pointer;
252b5132 5715
551c1ca1
AM		 5716 input_line_pointer = scale;
5717 val = get_absolute_expression ();
5718
5719 switch (val)
252b5132 5720 {
551c1ca1 5721 case 1:
252b5132
RH		 5722 i.log2_scale_factor = 0;
5723 break;
551c1ca1 5724 case 2:
252b5132
RH		 5725 i.log2_scale_factor = 1;
5726 break;
551c1ca1 5727 case 4:
252b5132
RH		 5728 i.log2_scale_factor = 2;
5729 break;
551c1ca1 5730 case 8:
252b5132
RH		 5731 i.log2_scale_factor = 3;
5732 break;
5733 default:
a724f0f4
JB		 5734 {
5735 char sep = *input_line_pointer;
5736
5737 *input_line_pointer = '\0';
5738 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5739 scale);
5740 *input_line_pointer = sep;
5741 input_line_pointer = save;
5742 return NULL;
5743 }
252b5132 5744 }
29b0f896 5745 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 5746 {
5747 as_warn (_("scale factor of %d without an index register"),
24eab124 5748 1 << i.log2_scale_factor);
252b5132 5749 i.log2_scale_factor = 0;
252b5132 5750 }
551c1ca1
AM		 5751 scale = input_line_pointer;
5752 input_line_pointer = save;
5753 return scale;
252b5132
RH		 5754}
5755
252b5132 5756static int
e3bb37b5 5757i386_displacement (char *disp_start, char *disp_end)
252b5132 5758{
29b0f896 5759 expressionS *exp;
252b5132
RH		 5760 segT exp_seg = 0;
5761 char *save_input_line_pointer;
f3c180ae 5762 char *gotfree_input_line;
40fb9820
L		 5763 int override;
5764 i386_operand_type bigdisp, types = anydisp;
3992d3b7 5765 int ret;
252b5132 5766
31b2323c
L		 5767 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5768 {
5769 as_bad (_("at most %d displacement operands are allowed"),
5770 MAX_MEMORY_OPERANDS);
5771 return 0;
5772 }
5773
c6fb90c8 5774 UINTS_CLEAR (bigdisp);
40fb9820
L		 5775 if ((i.types[this_operand].bitfield.jumpabsolute)
5776 || (!current_templates->start->opcode_modifier.jump
5777 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 5778 {
40fb9820 5779 bigdisp.bitfield.disp32 = 1;
e05278af 5780 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 5781 if (flag_code == CODE_64BIT)
5782 {
5783 if (!override)
5784 {
5785 bigdisp.bitfield.disp32s = 1;
5786 bigdisp.bitfield.disp64 = 1;
5787 }
5788 }
5789 else if ((flag_code == CODE_16BIT) ^ override)
5790 {
5791 bigdisp.bitfield.disp32 = 0;
5792 bigdisp.bitfield.disp16 = 1;
5793 }
e05278af
JB		 5794 }
5795 else
5796 {
5797 /* For PC-relative branches, the width of the displacement
5798 is dependent upon data size, not address size. */
e05278af 5799 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 5800 if (flag_code == CODE_64BIT)
5801 {
5802 if (override || i.suffix == WORD_MNEM_SUFFIX)
5803 bigdisp.bitfield.disp16 = 1;
5804 else
5805 {
5806 bigdisp.bitfield.disp32 = 1;
5807 bigdisp.bitfield.disp32s = 1;
5808 }
5809 }
5810 else
e05278af
JB		 5811 {
5812 if (!override)
5813 override = (i.suffix == (flag_code != CODE_16BIT
5814 ? WORD_MNEM_SUFFIX
5815 : LONG_MNEM_SUFFIX));
40fb9820
L		 5816 bigdisp.bitfield.disp32 = 1;
5817 if ((flag_code == CODE_16BIT) ^ override)
5818 {
5819 bigdisp.bitfield.disp32 = 0;
5820 bigdisp.bitfield.disp16 = 1;
5821 }
e05278af 5822 }
e05278af 5823 }
c6fb90c8
L		 5824 i.types[this_operand] = operand_type_or (i.types[this_operand],
5825 bigdisp);
252b5132
RH		 5826
5827 exp = &disp_expressions[i.disp_operands];
520dc8e8 5828 i.op[this_operand].disps = exp;
252b5132
RH		 5829 i.disp_operands++;
5830 save_input_line_pointer = input_line_pointer;
5831 input_line_pointer = disp_start;
5832 END_STRING_AND_SAVE (disp_end);
5833
5834#ifndef GCC_ASM_O_HACK
5835#define GCC_ASM_O_HACK 0
5836#endif
5837#if GCC_ASM_O_HACK
5838 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 5839 if (i.types[this_operand].bitfield.baseIndex
24eab124 5840 && displacement_string_end[-1] == '+')
252b5132
RH		 5841 {
5842 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 5843 constraint within gcc asm statements.
5844 For instance:
5845
5846 #define _set_tssldt_desc(n,addr,limit,type) \
5847 __asm__ __volatile__ ( \
5848 "movw %w2,%0\n\t" \
5849 "movw %w1,2+%0\n\t" \
5850 "rorl $16,%1\n\t" \
5851 "movb %b1,4+%0\n\t" \
5852 "movb %4,5+%0\n\t" \
5853 "movb $0,6+%0\n\t" \
5854 "movb %h1,7+%0\n\t" \
5855 "rorl $16,%1" \
5856 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5857
5858 This works great except that the output assembler ends
5859 up looking a bit weird if it turns out that there is
5860 no offset. You end up producing code that looks like:
5861
5862 #APP
5863 movw $235,(%eax)
5864 movw %dx,2+(%eax)
5865 rorl $16,%edx
5866 movb %dl,4+(%eax)
5867 movb $137,5+(%eax)
5868 movb $0,6+(%eax)
5869 movb %dh,7+(%eax)
5870 rorl $16,%edx
5871 #NO_APP
5872
47926f60 5873 So here we provide the missing zero. */
24eab124
AM		 5874
5875 *displacement_string_end = '0';
252b5132
RH		 5876 }
5877#endif
3956db08 5878 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5879 if (gotfree_input_line)
5880 input_line_pointer = gotfree_input_line;
252b5132 5881
24eab124 5882 exp_seg = expression (exp);
252b5132 5883
636c26b0
AM		 5884 SKIP_WHITESPACE ();
5885 if (*input_line_pointer)
5886 as_bad (_("junk `%s' after expression"), input_line_pointer);
5887#if GCC_ASM_O_HACK
5888 RESTORE_END_STRING (disp_end + 1);
5889#endif
636c26b0 5890 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 5891 if (gotfree_input_line)
5892 free (gotfree_input_line);
3992d3b7 5893 ret = 1;
636c26b0 5894
24eab124
AM		 5895 /* We do this to make sure that the section symbol is in
5896 the symbol table. We will ultimately change the relocation
47926f60 5897 to be relative to the beginning of the section. */
1ae12ab7 5898 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 5899 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5900 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 5901 {
636c26b0 5902 if (exp->X_op != O_symbol)
3992d3b7 5903 goto inv_disp;
636c26b0 5904
e5cb08ac 5905 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 5906 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5907 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 5908 exp->X_op = O_subtract;
5909 exp->X_op_symbol = GOT_symbol;
1ae12ab7 5910 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 5911 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 5912 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5913 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 5914 else
29b0f896 5915 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 5916 }
252b5132 5917
3992d3b7
AM		 5918 else if (exp->X_op == O_absent
5919 || exp->X_op == O_illegal
5920 || exp->X_op == O_big
5921 || (gotfree_input_line
5922 && (exp->X_op == O_constant
5923 || exp->X_op == O_register)))
2daf4fd8 5924 {
3992d3b7
AM		 5925 inv_disp:
5926 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 5927 disp_start);
3992d3b7 5928 ret = 0;
2daf4fd8
AM		 5929 }
5930
4c63da97 5931#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 5932 else if (exp->X_op != O_constant
5933 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5934 && exp_seg != absolute_section
5935 && exp_seg != text_section
5936 && exp_seg != data_section
5937 && exp_seg != bss_section
5938 && exp_seg != undefined_section
5939 && !bfd_is_com_section (exp_seg))
24eab124 5940 {
d0b47220 5941 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 5942 ret = 0;
24eab124 5943 }
252b5132 5944#endif
3956db08 5945
3992d3b7
AM		 5946 RESTORE_END_STRING (disp_end);
5947
40fb9820
L		 5948 /* Check if this is a displacement only operand. */
5949 bigdisp = i.types[this_operand];
5950 bigdisp.bitfield.disp8 = 0;
5951 bigdisp.bitfield.disp16 = 0;
5952 bigdisp.bitfield.disp32 = 0;
5953 bigdisp.bitfield.disp32s = 0;
5954 bigdisp.bitfield.disp64 = 0;
c6fb90c8
L		 5955 if (UINTS_ALL_ZERO (bigdisp))
5956 i.types[this_operand] = operand_type_and (i.types[this_operand],
5957 types);
3956db08 5958
3992d3b7 5959 return ret;
252b5132
RH		 5960}
5961
eecb386c 5962/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 5963 Return 1 on success, 0 on a failure. */
5964
252b5132 5965static int
e3bb37b5 5966i386_index_check (const char *operand_string)
252b5132 5967{
3e73aa7c 5968 int ok;
24eab124 5969#if INFER_ADDR_PREFIX
eecb386c
AM		 5970 int fudged = 0;
5971
24eab124
AM		 5972 tryprefix:
5973#endif
3e73aa7c 5974 ok = 1;
75178d9d 5975 if (flag_code == CODE_64BIT)
64e74474 5976 {
64e74474 5977 if ((i.base_reg
40fb9820
L		 5978 && ((i.prefix[ADDR_PREFIX] == 0
5979 && !i.base_reg->reg_type.bitfield.reg64)
5980 || (i.prefix[ADDR_PREFIX]
5981 && !i.base_reg->reg_type.bitfield.reg32))
5982 && (i.index_reg
20e192ab 5983 || i.base_reg->reg_num != RegRip))
64e74474 5984 || (i.index_reg
40fb9820
L		 5985 && (!i.index_reg->reg_type.bitfield.baseindex
5986 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 5987 && i.index_reg->reg_num != RegRiz
5988 && !i.index_reg->reg_type.bitfield.reg64
5989 )
40fb9820 5990 || (i.prefix[ADDR_PREFIX]
db51cc60 5991 && i.index_reg->reg_num != RegEiz
40fb9820 5992 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 5993 ok = 0;
3e73aa7c
JH		 5994 }
5995 else
5996 {
5997 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
5998 {
5999 /* 16bit checks. */
6000 if ((i.base_reg
40fb9820
L		 6001 && (!i.base_reg->reg_type.bitfield.reg16
6002 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6003 || (i.index_reg
40fb9820
L		 6004 && (!i.index_reg->reg_type.bitfield.reg16
6005 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6006 || !(i.base_reg
6007 && i.base_reg->reg_num < 6
6008 && i.index_reg->reg_num >= 6
6009 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6010 ok = 0;
6011 }
6012 else
e5cb08ac 6013 {
3e73aa7c
JH		 6014 /* 32bit checks. */
6015 if ((i.base_reg
40fb9820 6016 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6017 || (i.index_reg
db51cc60
L		 6018 && ((!i.index_reg->reg_type.bitfield.reg32
6019 && i.index_reg->reg_num != RegEiz)
40fb9820 6020 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6021 ok = 0;
3e73aa7c
JH		 6022 }
6023 }
6024 if (!ok)
24eab124
AM		 6025 {
6026#if INFER_ADDR_PREFIX
20f0a1fc 6027 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6028 {
6029 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6030 i.prefixes += 1;
b23bac36
AM		 6031 /* Change the size of any displacement too. At most one of
6032 Disp16 or Disp32 is set.
6033 FIXME. There doesn't seem to be any real need for separate
6034 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6035 Removing them would probably clean up the code quite a lot. */
4eed87de 6036 if (flag_code != CODE_64BIT
40fb9820
L		 6037 && (i.types[this_operand].bitfield.disp16
6038 || i.types[this_operand].bitfield.disp32))
6039 i.types[this_operand]
c6fb90c8 6040 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6041 fudged = 1;
24eab124
AM		 6042 goto tryprefix;
6043 }
eecb386c
AM		 6044 if (fudged)
6045 as_bad (_("`%s' is not a valid base/index expression"),
6046 operand_string);
6047 else
c388dee8 6048#endif
eecb386c
AM		 6049 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6050 operand_string,
3e73aa7c 6051 flag_code_names[flag_code]);
24eab124 6052 }
20f0a1fc 6053 return ok;
24eab124 6054}
252b5132 6055
252b5132 6056/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6057 on error. */
252b5132 6058
252b5132 6059static int
e3bb37b5 6060i386_operand (char *operand_string)
252b5132 6061{
af6bdddf
AM		 6062 const reg_entry *r;
6063 char *end_op;
24eab124 6064 char *op_string = operand_string;
252b5132 6065
24eab124 6066 if (is_space_char (*op_string))
252b5132
RH		 6067 ++op_string;
6068
24eab124 6069 /* We check for an absolute prefix (differentiating,
47926f60 6070 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6071 if (*op_string == ABSOLUTE_PREFIX)
6072 {
6073 ++op_string;
6074 if (is_space_char (*op_string))
6075 ++op_string;
40fb9820 6076 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6077 }
252b5132 6078
47926f60 6079 /* Check if operand is a register. */
4d1bb795 6080 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6081 {
40fb9820
L		 6082 i386_operand_type temp;
6083
24eab124
AM		 6084 /* Check for a segment override by searching for ':' after a
6085 segment register. */
6086 op_string = end_op;
6087 if (is_space_char (*op_string))
6088 ++op_string;
40fb9820
L		 6089 if (*op_string == ':'
6090 && (r->reg_type.bitfield.sreg2
6091 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6092 {
6093 switch (r->reg_num)
6094 {
6095 case 0:
6096 i.seg[i.mem_operands] = &es;
6097 break;
6098 case 1:
6099 i.seg[i.mem_operands] = &cs;
6100 break;
6101 case 2:
6102 i.seg[i.mem_operands] = &ss;
6103 break;
6104 case 3:
6105 i.seg[i.mem_operands] = &ds;
6106 break;
6107 case 4:
6108 i.seg[i.mem_operands] = &fs;
6109 break;
6110 case 5:
6111 i.seg[i.mem_operands] = &gs;
6112 break;
6113 }
252b5132 6114
24eab124 6115 /* Skip the ':' and whitespace. */
252b5132
RH		 6116 ++op_string;
6117 if (is_space_char (*op_string))
24eab124 6118 ++op_string;
252b5132 6119
24eab124
AM		 6120 if (!is_digit_char (*op_string)
6121 && !is_identifier_char (*op_string)
6122 && *op_string != '('
6123 && *op_string != ABSOLUTE_PREFIX)
6124 {
6125 as_bad (_("bad memory operand `%s'"), op_string);
6126 return 0;
6127 }
47926f60 6128 /* Handle case of %es:*foo. */
24eab124
AM		 6129 if (*op_string == ABSOLUTE_PREFIX)
6130 {
6131 ++op_string;
6132 if (is_space_char (*op_string))
6133 ++op_string;
40fb9820 6134 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6135 }
6136 goto do_memory_reference;
6137 }
6138 if (*op_string)
6139 {
d0b47220 6140 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6141 return 0;
6142 }
40fb9820
L		 6143 temp = r->reg_type;
6144 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6145 i.types[this_operand] = operand_type_or (i.types[this_operand],
6146 temp);
520dc8e8 6147 i.op[this_operand].regs = r;
24eab124
AM		 6148 i.reg_operands++;
6149 }
af6bdddf
AM		 6150 else if (*op_string == REGISTER_PREFIX)
6151 {
6152 as_bad (_("bad register name `%s'"), op_string);
6153 return 0;
6154 }
24eab124 6155 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6156 {
24eab124 6157 ++op_string;
40fb9820 6158 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6159 {
d0b47220 6160 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6161 return 0;
6162 }
6163 if (!i386_immediate (op_string))
6164 return 0;
6165 }
6166 else if (is_digit_char (*op_string)
6167 || is_identifier_char (*op_string)
e5cb08ac 6168 || *op_string == '(')
24eab124 6169 {
47926f60 6170 /* This is a memory reference of some sort. */
af6bdddf 6171 char *base_string;
252b5132 6172
47926f60 6173 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6174 char *displacement_string_start;
6175 char *displacement_string_end;
252b5132 6176
24eab124 6177 do_memory_reference:
24eab124 6178 if ((i.mem_operands == 1
40fb9820 6179 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6180 || i.mem_operands == 2)
6181 {
6182 as_bad (_("too many memory references for `%s'"),
6183 current_templates->start->name);
6184 return 0;
6185 }
252b5132 6186
24eab124
AM		 6187 /* Check for base index form. We detect the base index form by
6188 looking for an ')' at the end of the operand, searching
6189 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6190 after the '('. */
af6bdddf 6191 base_string = op_string + strlen (op_string);
c3332e24 6192
af6bdddf
AM		 6193 --base_string;
6194 if (is_space_char (*base_string))
6195 --base_string;
252b5132 6196
47926f60 6197 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6198 displacement_string_start = op_string;
6199 displacement_string_end = base_string + 1;
252b5132 6200
24eab124
AM		 6201 if (*base_string == ')')
6202 {
af6bdddf 6203 char *temp_string;
24eab124
AM		 6204 unsigned int parens_balanced = 1;
6205 /* We've already checked that the number of left & right ()'s are
47926f60 6206 equal, so this loop will not be infinite. */
24eab124
AM		 6207 do
6208 {
6209 base_string--;
6210 if (*base_string == ')')
6211 parens_balanced++;
6212 if (*base_string == '(')
6213 parens_balanced--;
6214 }
6215 while (parens_balanced);
c3332e24 6216
af6bdddf 6217 temp_string = base_string;
c3332e24 6218
24eab124 6219 /* Skip past '(' and whitespace. */
252b5132
RH		 6220 ++base_string;
6221 if (is_space_char (*base_string))
24eab124 6222 ++base_string;
252b5132 6223
af6bdddf 6224 if (*base_string == ','
4eed87de
AM		 6225 || ((i.base_reg = parse_register (base_string, &end_op))
6226 != NULL))
252b5132 6227 {
af6bdddf 6228 displacement_string_end = temp_string;
252b5132 6229
40fb9820 6230 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6231
af6bdddf 6232 if (i.base_reg)
24eab124 6233 {
24eab124
AM		 6234 base_string = end_op;
6235 if (is_space_char (*base_string))
6236 ++base_string;
af6bdddf
AM		 6237 }
6238
6239 /* There may be an index reg or scale factor here. */
6240 if (*base_string == ',')
6241 {
6242 ++base_string;
6243 if (is_space_char (*base_string))
6244 ++base_string;
6245
4eed87de
AM		 6246 if ((i.index_reg = parse_register (base_string, &end_op))
6247 != NULL)
24eab124 6248 {
af6bdddf 6249 base_string = end_op;
24eab124
AM		 6250 if (is_space_char (*base_string))
6251 ++base_string;
af6bdddf
AM		 6252 if (*base_string == ',')
6253 {
6254 ++base_string;
6255 if (is_space_char (*base_string))
6256 ++base_string;
6257 }
e5cb08ac 6258 else if (*base_string != ')')
af6bdddf 6259 {
4eed87de
AM		 6260 as_bad (_("expecting `,' or `)' "
6261 "after index register in `%s'"),
af6bdddf
AM		 6262 operand_string);
6263 return 0;
6264 }
24eab124 6265 }
af6bdddf 6266 else if (*base_string == REGISTER_PREFIX)
24eab124 6267 {
af6bdddf 6268 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6269 return 0;
6270 }
252b5132 6271
47926f60 6272 /* Check for scale factor. */
551c1ca1 6273 if (*base_string != ')')
af6bdddf 6274 {
551c1ca1
AM		 6275 char *end_scale = i386_scale (base_string);
6276
6277 if (!end_scale)
af6bdddf 6278 return 0;
24eab124 6279
551c1ca1 6280 base_string = end_scale;
af6bdddf
AM		 6281 if (is_space_char (*base_string))
6282 ++base_string;
6283 if (*base_string != ')')
6284 {
4eed87de
AM		 6285 as_bad (_("expecting `)' "
6286 "after scale factor in `%s'"),
af6bdddf
AM		 6287 operand_string);
6288 return 0;
6289 }
6290 }
6291 else if (!i.index_reg)
24eab124 6292 {
4eed87de
AM		 6293 as_bad (_("expecting index register or scale factor "
6294 "after `,'; got '%c'"),
af6bdddf 6295 *base_string);
24eab124
AM		 6296 return 0;
6297 }
6298 }
af6bdddf 6299 else if (*base_string != ')')
24eab124 6300 {
4eed87de
AM		 6301 as_bad (_("expecting `,' or `)' "
6302 "after base register in `%s'"),
af6bdddf 6303 operand_string);
24eab124
AM		 6304 return 0;
6305 }
c3332e24 6306 }
af6bdddf 6307 else if (*base_string == REGISTER_PREFIX)
c3332e24 6308 {
af6bdddf 6309 as_bad (_("bad register name `%s'"), base_string);
24eab124 6310 return 0;
c3332e24 6311 }
24eab124
AM		 6312 }
6313
6314 /* If there's an expression beginning the operand, parse it,
6315 assuming displacement_string_start and
6316 displacement_string_end are meaningful. */
6317 if (displacement_string_start != displacement_string_end)
6318 {
6319 if (!i386_displacement (displacement_string_start,
6320 displacement_string_end))
6321 return 0;
6322 }
6323
6324 /* Special case for (%dx) while doing input/output op. */
6325 if (i.base_reg
c6fb90c8 6326 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
24eab124
AM		 6327 && i.index_reg == 0
6328 && i.log2_scale_factor == 0
6329 && i.seg[i.mem_operands] == 0
40fb9820 6330 && !operand_type_check (i.types[this_operand], disp))
24eab124 6331 {
c6fb90c8 6332 UINTS_CLEAR (i.types[this_operand]);
40fb9820 6333 i.types[this_operand].bitfield.inoutportreg = 1;
24eab124
AM		 6334 return 1;
6335 }
6336
eecb386c
AM		 6337 if (i386_index_check (operand_string) == 0)
6338 return 0;
24eab124
AM		 6339 i.mem_operands++;
6340 }
6341 else
ce8a8b2f
AM		 6342 {
6343 /* It's not a memory operand; argh! */
24eab124
AM		 6344 as_bad (_("invalid char %s beginning operand %d `%s'"),
6345 output_invalid (*op_string),
6346 this_operand + 1,
6347 op_string);
6348 return 0;
6349 }
47926f60 6350 return 1; /* Normal return. */
252b5132
RH		 6351}
6352\f
ee7fcc42
AM		 6353/* md_estimate_size_before_relax()
6354
6355 Called just before relax() for rs_machine_dependent frags. The x86
6356 assembler uses these frags to handle variable size jump
6357 instructions.
6358
6359 Any symbol that is now undefined will not become defined.
6360 Return the correct fr_subtype in the frag.
6361 Return the initial "guess for variable size of frag" to caller.
6362 The guess is actually the growth beyond the fixed part. Whatever
6363 we do to grow the fixed or variable part contributes to our
6364 returned value. */
6365
252b5132
RH		 6366int
6367md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6368 fragS *fragP;
6369 segT segment;
252b5132 6370{
252b5132 6371 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6372 check for un-relaxable symbols. On an ELF system, we can't relax
6373 an externally visible symbol, because it may be overridden by a
6374 shared library. */
6375 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6376#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6377 || (IS_ELF
31312f95
AM		 6378 && (S_IS_EXTERNAL (fragP->fr_symbol)
6379 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 6380#endif
6381 )
252b5132 6382 {
b98ef147
AM		 6383 /* Symbol is undefined in this segment, or we need to keep a
6384 reloc so that weak symbols can be overridden. */
6385 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 6386 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 6387 unsigned char *opcode;
6388 int old_fr_fix;
f6af82bd 6389
ee7fcc42
AM		 6390 if (fragP->fr_var != NO_RELOC)
6391 reloc_type = fragP->fr_var;
b98ef147 6392 else if (size == 2)
f6af82bd
AM		 6393 reloc_type = BFD_RELOC_16_PCREL;
6394 else
6395 reloc_type = BFD_RELOC_32_PCREL;
252b5132 6396
ee7fcc42
AM		 6397 old_fr_fix = fragP->fr_fix;
6398 opcode = (unsigned char *) fragP->fr_opcode;
6399
fddf5b5b 6400 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 6401 {
fddf5b5b
AM		 6402 case UNCOND_JUMP:
6403 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 6404 opcode[0] = 0xe9;
252b5132 6405 fragP->fr_fix += size;
062cd5e7
AS		 6406 fix_new (fragP, old_fr_fix, size,
6407 fragP->fr_symbol,
6408 fragP->fr_offset, 1,
6409 reloc_type);
252b5132
RH		 6410 break;
6411
fddf5b5b 6412 case COND_JUMP86:
412167cb
AM		 6413 if (size == 2
6414 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 6415 {
6416 /* Negate the condition, and branch past an
6417 unconditional jump. */
6418 opcode[0] ^= 1;
6419 opcode[1] = 3;
6420 /* Insert an unconditional jump. */
6421 opcode[2] = 0xe9;
6422 /* We added two extra opcode bytes, and have a two byte
6423 offset. */
6424 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 6425 fix_new (fragP, old_fr_fix + 2, 2,
6426 fragP->fr_symbol,
6427 fragP->fr_offset, 1,
6428 reloc_type);
fddf5b5b
AM		 6429 break;
6430 }
6431 /* Fall through. */
6432
6433 case COND_JUMP:
412167cb
AM		 6434 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6435 {
3e02c1cc
AM		 6436 fixS *fixP;
6437
412167cb 6438 fragP->fr_fix += 1;
3e02c1cc
AM		 6439 fixP = fix_new (fragP, old_fr_fix, 1,
6440 fragP->fr_symbol,
6441 fragP->fr_offset, 1,
6442 BFD_RELOC_8_PCREL);
6443 fixP->fx_signed = 1;
412167cb
AM		 6444 break;
6445 }
93c2a809 6446
24eab124 6447 /* This changes the byte-displacement jump 0x7N
fddf5b5b 6448 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 6449 opcode[1] = opcode[0] + 0x10;
f6af82bd 6450 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 6451 /* We've added an opcode byte. */
6452 fragP->fr_fix += 1 + size;
062cd5e7
AS		 6453 fix_new (fragP, old_fr_fix + 1, size,
6454 fragP->fr_symbol,
6455 fragP->fr_offset, 1,
6456 reloc_type);
252b5132 6457 break;
fddf5b5b
AM		 6458
6459 default:
6460 BAD_CASE (fragP->fr_subtype);
6461 break;
252b5132
RH		 6462 }
6463 frag_wane (fragP);
ee7fcc42 6464 return fragP->fr_fix - old_fr_fix;
252b5132 6465 }
93c2a809 6466
93c2a809
AM		 6467 /* Guess size depending on current relax state. Initially the relax
6468 state will correspond to a short jump and we return 1, because
6469 the variable part of the frag (the branch offset) is one byte
6470 long. However, we can relax a section more than once and in that
6471 case we must either set fr_subtype back to the unrelaxed state,
6472 or return the value for the appropriate branch. */
6473 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 6474}
6475
47926f60
KH		 6476/* Called after relax() is finished.
6477
6478 In: Address of frag.
6479 fr_type == rs_machine_dependent.
6480 fr_subtype is what the address relaxed to.
6481
6482 Out: Any fixSs and constants are set up.
6483 Caller will turn frag into a ".space 0". */
6484
252b5132
RH		 6485void
6486md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 6487 bfd *abfd ATTRIBUTE_UNUSED;
6488 segT sec ATTRIBUTE_UNUSED;
29b0f896 6489 fragS *fragP;
252b5132 6490{
29b0f896 6491 unsigned char *opcode;
252b5132 6492 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6493 offsetT target_address;
6494 offsetT opcode_address;
252b5132 6495 unsigned int extension = 0;
847f7ad4 6496 offsetT displacement_from_opcode_start;
252b5132
RH		 6497
6498 opcode = (unsigned char *) fragP->fr_opcode;
6499
47926f60 6500 /* Address we want to reach in file space. */
252b5132 6501 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6502
47926f60 6503 /* Address opcode resides at in file space. */
252b5132
RH		 6504 opcode_address = fragP->fr_address + fragP->fr_fix;
6505
47926f60 6506 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6507 displacement_from_opcode_start = target_address - opcode_address;
6508
fddf5b5b 6509 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6510 {
47926f60
KH		 6511 /* Don't have to change opcode. */
6512 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6513 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6514 }
6515 else
6516 {
6517 if (no_cond_jump_promotion
6518 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6519 as_warn_where (fragP->fr_file, fragP->fr_line,
6520 _("long jump required"));
252b5132 6521
fddf5b5b
AM		 6522 switch (fragP->fr_subtype)
6523 {
6524 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6525 extension = 4; /* 1 opcode + 4 displacement */
6526 opcode[0] = 0xe9;
6527 where_to_put_displacement = &opcode[1];
6528 break;
252b5132 6529
fddf5b5b
AM		 6530 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6531 extension = 2; /* 1 opcode + 2 displacement */
6532 opcode[0] = 0xe9;
6533 where_to_put_displacement = &opcode[1];
6534 break;
252b5132 6535
fddf5b5b
AM		 6536 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6537 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6538 extension = 5; /* 2 opcode + 4 displacement */
6539 opcode[1] = opcode[0] + 0x10;
6540 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6541 where_to_put_displacement = &opcode[2];
6542 break;
252b5132 6543
fddf5b5b
AM		 6544 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6545 extension = 3; /* 2 opcode + 2 displacement */
6546 opcode[1] = opcode[0] + 0x10;
6547 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6548 where_to_put_displacement = &opcode[2];
6549 break;
252b5132 6550
fddf5b5b
AM		 6551 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6552 extension = 4;
6553 opcode[0] ^= 1;
6554 opcode[1] = 3;
6555 opcode[2] = 0xe9;
6556 where_to_put_displacement = &opcode[3];
6557 break;
6558
6559 default:
6560 BAD_CASE (fragP->fr_subtype);
6561 break;
6562 }
252b5132 6563 }
fddf5b5b 6564
7b81dfbb
AJ		 6565 /* If size if less then four we are sure that the operand fits,
6566 but if it's 4, then it could be that the displacement is larger
6567 then -/+ 2GB. */
6568 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6569 && object_64bit
6570 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6571 + ((addressT) 1 << 31))
6572 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6573 {
6574 as_bad_where (fragP->fr_file, fragP->fr_line,
6575 _("jump target out of range"));
6576 /* Make us emit 0. */
6577 displacement_from_opcode_start = extension;
6578 }
47926f60 6579 /* Now put displacement after opcode. */
252b5132
RH		 6580 md_number_to_chars ((char *) where_to_put_displacement,
6581 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6582 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6583 fragP->fr_fix += extension;
6584}
6585\f
47926f60
KH		 6586/* Size of byte displacement jmp. */
6587int md_short_jump_size = 2;
6588
6589/* Size of dword displacement jmp. */
6590int md_long_jump_size = 5;
252b5132 6591
252b5132
RH		 6592void
6593md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
6594 char *ptr;
6595 addressT from_addr, to_addr;
ab9da554
ILT		 6596 fragS *frag ATTRIBUTE_UNUSED;
6597 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 6598{
847f7ad4 6599 offsetT offset;
252b5132
RH		 6600
6601 offset = to_addr - (from_addr + 2);
47926f60
KH		 6602 /* Opcode for byte-disp jump. */
6603 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 6604 md_number_to_chars (ptr + 1, (valueT) offset, 1);
6605}
6606
6607void
6608md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
6609 char *ptr;
6610 addressT from_addr, to_addr;
a38cf1db
AM		 6611 fragS *frag ATTRIBUTE_UNUSED;
6612 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 6613{
847f7ad4 6614 offsetT offset;
252b5132 6615
a38cf1db
AM		 6616 offset = to_addr - (from_addr + 5);
6617 md_number_to_chars (ptr, (valueT) 0xe9, 1);
6618 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 6619}
6620\f
6621/* Apply a fixup (fixS) to segment data, once it has been determined
6622 by our caller that we have all the info we need to fix it up.
6623
6624 On the 386, immediates, displacements, and data pointers are all in
6625 the same (little-endian) format, so we don't need to care about which
6626 we are handling. */
6627
94f592af 6628void
55cf6793 6629md_apply_fix (fixP, valP, seg)
47926f60
KH		 6630 /* The fix we're to put in. */
6631 fixS *fixP;
47926f60 6632 /* Pointer to the value of the bits. */
c6682705 6633 valueT *valP;
47926f60
KH		 6634 /* Segment fix is from. */
6635 segT seg ATTRIBUTE_UNUSED;
252b5132 6636{
94f592af 6637 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6638 valueT value = *valP;
252b5132 6639
f86103b7 6640#if !defined (TE_Mach)
93382f6d
AM		 6641 if (fixP->fx_pcrel)
6642 {
6643 switch (fixP->fx_r_type)
6644 {
5865bb77
ILT		 6645 default:
6646 break;
6647
d6ab8113
JB		 6648 case BFD_RELOC_64:
6649 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6650 break;
93382f6d 6651 case BFD_RELOC_32:
ae8887b5 6652 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6653 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6654 break;
6655 case BFD_RELOC_16:
6656 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6657 break;
6658 case BFD_RELOC_8:
6659 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6660 break;
6661 }
6662 }
252b5132 6663
a161fe53 6664 if (fixP->fx_addsy != NULL
31312f95 6665 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6666 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6667 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6668 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6669 && !use_rela_relocations)
252b5132 6670 {
31312f95
AM		 6671 /* This is a hack. There should be a better way to handle this.
6672 This covers for the fact that bfd_install_relocation will
6673 subtract the current location (for partial_inplace, PC relative
6674 relocations); see more below. */
252b5132 6675#ifndef OBJ_AOUT
718ddfc0 6676 if (IS_ELF
252b5132
RH		 6677#ifdef TE_PE
6678 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6679#endif
6680 )
6681 value += fixP->fx_where + fixP->fx_frag->fr_address;
6682#endif
6683#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6684 if (IS_ELF)
252b5132 6685 {
6539b54b 6686 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6687
6539b54b 6688 if ((sym_seg == seg
2f66722d 6689 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6690 && sym_seg != absolute_section))
ae6063d4 6691 && !generic_force_reloc (fixP))
2f66722d
AM		 6692 {
6693 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6694 bfd_install_relocation subtracts them out again. I think
6695 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6696 it. FIXME. */
6697 value += fixP->fx_where + fixP->fx_frag->fr_address;
6698 }
252b5132
RH		 6699 }
6700#endif
6701#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6702 /* For some reason, the PE format does not store a
6703 section address offset for a PC relative symbol. */
6704 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6705 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6706 value += md_pcrel_from (fixP);
6707#endif
6708 }
6709
6710 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6711 and we must not disappoint it. */
252b5132 6712#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6713 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6714 switch (fixP->fx_r_type)
6715 {
6716 case BFD_RELOC_386_PLT32:
3e73aa7c 6717 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6718 /* Make the jump instruction point to the address of the operand. At
6719 runtime we merely add the offset to the actual PLT entry. */
6720 value = -4;
6721 break;
31312f95 6722
13ae64f3
JJ		 6723 case BFD_RELOC_386_TLS_GD:
6724 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6725 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6726 case BFD_RELOC_386_TLS_IE:
6727 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6728 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6729 case BFD_RELOC_X86_64_TLSGD:
6730 case BFD_RELOC_X86_64_TLSLD:
6731 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6732 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6733 value = 0; /* Fully resolved at runtime. No addend. */
6734 /* Fallthrough */
6735 case BFD_RELOC_386_TLS_LE:
6736 case BFD_RELOC_386_TLS_LDO_32:
6737 case BFD_RELOC_386_TLS_LE_32:
6738 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6739 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6740 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6741 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6742 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6743 break;
6744
67a4f2b7
AO		 6745 case BFD_RELOC_386_TLS_DESC_CALL:
6746 case BFD_RELOC_X86_64_TLSDESC_CALL:
6747 value = 0; /* Fully resolved at runtime. No addend. */
6748 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6749 fixP->fx_done = 0;
6750 return;
6751
00f7efb6
JJ		 6752 case BFD_RELOC_386_GOT32:
6753 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 6754 value = 0; /* Fully resolved at runtime. No addend. */
6755 break;
47926f60
KH		 6756
6757 case BFD_RELOC_VTABLE_INHERIT:
6758 case BFD_RELOC_VTABLE_ENTRY:
6759 fixP->fx_done = 0;
94f592af 6760 return;
47926f60
KH		 6761
6762 default:
6763 break;
6764 }
6765#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 6766 *valP = value;
f86103b7 6767#endif /* !defined (TE_Mach) */
3e73aa7c 6768
3e73aa7c 6769 /* Are we finished with this relocation now? */
c6682705 6770 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 6771 fixP->fx_done = 1;
6772 else if (use_rela_relocations)
6773 {
6774 fixP->fx_no_overflow = 1;
062cd5e7
AS		 6775 /* Remember value for tc_gen_reloc. */
6776 fixP->fx_addnumber = value;
3e73aa7c
JH		 6777 value = 0;
6778 }
f86103b7 6779
94f592af 6780 md_number_to_chars (p, value, fixP->fx_size);
252b5132 6781}
252b5132 6782\f
252b5132
RH		 6783#define MAX_LITTLENUMS 6
6784
47926f60
KH		 6785/* Turn the string pointed to by litP into a floating point constant
6786 of type TYPE, and emit the appropriate bytes. The number of
6787 LITTLENUMS emitted is stored in *SIZEP. An error message is
6788 returned, or NULL on OK. */
6789
252b5132
RH		 6790char *
6791md_atof (type, litP, sizeP)
2ab9b79e 6792 int type;
252b5132
RH		 6793 char *litP;
6794 int *sizeP;
6795{
6796 int prec;
6797 LITTLENUM_TYPE words[MAX_LITTLENUMS];
6798 LITTLENUM_TYPE *wordP;
6799 char *t;
6800
6801 switch (type)
6802 {
6803 case 'f':
6804 case 'F':
6805 prec = 2;
6806 break;
6807
6808 case 'd':
6809 case 'D':
6810 prec = 4;
6811 break;
6812
6813 case 'x':
6814 case 'X':
6815 prec = 5;
6816 break;
6817
6818 default:
6819 *sizeP = 0;
6820 return _("Bad call to md_atof ()");
6821 }
6822 t = atof_ieee (input_line_pointer, type, words);
6823 if (t)
6824 input_line_pointer = t;
6825
6826 *sizeP = prec * sizeof (LITTLENUM_TYPE);
6827 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
6828 the bigendian 386. */
6829 for (wordP = words + prec - 1; prec--;)
6830 {
6831 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
6832 litP += sizeof (LITTLENUM_TYPE);
6833 }
6834 return 0;
6835}
6836\f
2d545b82 6837static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 6838
252b5132 6839static char *
e3bb37b5 6840output_invalid (int c)
252b5132 6841{
3882b010 6842 if (ISPRINT (c))
f9f21a03
L		 6843 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6844 "'%c'", c);
252b5132 6845 else
f9f21a03 6846 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 6847 "(0x%x)", (unsigned char) c);
252b5132
RH		 6848 return output_invalid_buf;
6849}
6850
af6bdddf 6851/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 6852
6853static const reg_entry *
4d1bb795 6854parse_real_register (char *reg_string, char **end_op)
252b5132 6855{
af6bdddf
AM		 6856 char *s = reg_string;
6857 char *p;
252b5132
RH		 6858 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6859 const reg_entry *r;
6860
6861 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6862 if (*s == REGISTER_PREFIX)
6863 ++s;
6864
6865 if (is_space_char (*s))
6866 ++s;
6867
6868 p = reg_name_given;
af6bdddf 6869 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 6870 {
6871 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 6872 return (const reg_entry *) NULL;
6873 s++;
252b5132
RH		 6874 }
6875
6588847e
DN		 6876 /* For naked regs, make sure that we are not dealing with an identifier.
6877 This prevents confusing an identifier like `eax_var' with register
6878 `eax'. */
6879 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6880 return (const reg_entry *) NULL;
6881
af6bdddf 6882 *end_op = s;
252b5132
RH		 6883
6884 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6885
5f47d35b 6886 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 6887 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 6888 {
5f47d35b
AM		 6889 if (is_space_char (*s))
6890 ++s;
6891 if (*s == '(')
6892 {
af6bdddf 6893 ++s;
5f47d35b
AM		 6894 if (is_space_char (*s))
6895 ++s;
6896 if (*s >= '0' && *s <= '7')
6897 {
db557034 6898 int fpr = *s - '0';
af6bdddf 6899 ++s;
5f47d35b
AM		 6900 if (is_space_char (*s))
6901 ++s;
6902 if (*s == ')')
6903 {
6904 *end_op = s + 1;
db557034
AM		 6905 r = hash_find (reg_hash, "st(0)");
6906 know (r);
6907 return r + fpr;
5f47d35b 6908 }
5f47d35b 6909 }
47926f60 6910 /* We have "%st(" then garbage. */
5f47d35b
AM		 6911 return (const reg_entry *) NULL;
6912 }
6913 }
6914
db51cc60
L		 6915 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6916 if (r != NULL
6917 && !allow_index_reg
6918 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
6919 return (const reg_entry *) NULL;
6920
1ae00879 6921 if (r != NULL
d946b91f 6922 && ((r->reg_flags & (RegRex64 | RegRex))
40fb9820
L		 6923 || r->reg_type.bitfield.reg64)
6924 && (!cpu_arch_flags.bitfield.cpulm
c6fb90c8 6925 || !UINTS_EQUAL (r->reg_type, control))
1ae00879 6926 && flag_code != CODE_64BIT)
20f0a1fc 6927 return (const reg_entry *) NULL;
1ae00879 6928
252b5132
RH		 6929 return r;
6930}
4d1bb795
JB		 6931
6932/* REG_STRING starts *before* REGISTER_PREFIX. */
6933
6934static const reg_entry *
6935parse_register (char *reg_string, char **end_op)
6936{
6937 const reg_entry *r;
6938
6939 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6940 r = parse_real_register (reg_string, end_op);
6941 else
6942 r = NULL;
6943 if (!r)
6944 {
6945 char *save = input_line_pointer;
6946 char c;
6947 symbolS *symbolP;
6948
6949 input_line_pointer = reg_string;
6950 c = get_symbol_end ();
6951 symbolP = symbol_find (reg_string);
6952 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6953 {
6954 const expressionS *e = symbol_get_value_expression (symbolP);
6955
6956 know (e->X_op == O_register);
4eed87de 6957 know (e->X_add_number >= 0
c3fe08fa 6958 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 6959 r = i386_regtab + e->X_add_number;
6960 *end_op = input_line_pointer;
6961 }
6962 *input_line_pointer = c;
6963 input_line_pointer = save;
6964 }
6965 return r;
6966}
6967
6968int
6969i386_parse_name (char *name, expressionS *e, char *nextcharP)
6970{
6971 const reg_entry *r;
6972 char *end = input_line_pointer;
6973
6974 *end = *nextcharP;
6975 r = parse_register (name, &input_line_pointer);
6976 if (r && end <= input_line_pointer)
6977 {
6978 *nextcharP = *input_line_pointer;
6979 *input_line_pointer = 0;
6980 e->X_op = O_register;
6981 e->X_add_number = r - i386_regtab;
6982 return 1;
6983 }
6984 input_line_pointer = end;
6985 *end = 0;
6986 return 0;
6987}
6988
6989void
6990md_operand (expressionS *e)
6991{
6992 if (*input_line_pointer == REGISTER_PREFIX)
6993 {
6994 char *end;
6995 const reg_entry *r = parse_real_register (input_line_pointer, &end);
6996
6997 if (r)
6998 {
6999 e->X_op = O_register;
7000 e->X_add_number = r - i386_regtab;
7001 input_line_pointer = end;
7002 }
7003 }
7004}
7005
252b5132 7006\f
4cc782b5 7007#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7008const char *md_shortopts = "kVQ:sqn";
252b5132 7009#else
12b55ccc 7010const char *md_shortopts = "qn";
252b5132 7011#endif
6e0b89ee 7012
3e73aa7c 7013#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7014#define OPTION_64 (OPTION_MD_BASE + 1)
7015#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7016#define OPTION_MARCH (OPTION_MD_BASE + 3)
7017#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 7018
99ad8390
NC		 7019struct option md_longopts[] =
7020{
3e73aa7c 7021 {"32", no_argument, NULL, OPTION_32},
99ad8390 7022#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7023 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7024#endif
b3b91714 7025 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7026 {"march", required_argument, NULL, OPTION_MARCH},
7027 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 7028 {NULL, no_argument, NULL, 0}
7029};
7030size_t md_longopts_size = sizeof (md_longopts);
7031
7032int
9103f4f4 7033md_parse_option (int c, char *arg)
252b5132 7034{
9103f4f4
L		 7035 unsigned int i;
7036
252b5132
RH		 7037 switch (c)
7038 {
12b55ccc
L		 7039 case 'n':
7040 optimize_align_code = 0;
7041 break;
7042
a38cf1db
AM		 7043 case 'q':
7044 quiet_warnings = 1;
252b5132
RH		 7045 break;
7046
7047#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7048 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7049 should be emitted or not. FIXME: Not implemented. */
7050 case 'Q':
252b5132
RH		 7051 break;
7052
7053 /* -V: SVR4 argument to print version ID. */
7054 case 'V':
7055 print_version_id ();
7056 break;
7057
a38cf1db
AM		 7058 /* -k: Ignore for FreeBSD compatibility. */
7059 case 'k':
252b5132 7060 break;
4cc782b5
ILT		 7061
7062 case 's':
7063 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7064 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7065 break;
99ad8390
NC		 7066#endif
7067#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 7068 case OPTION_64:
7069 {
7070 const char **list, **l;
7071
3e73aa7c
JH		 7072 list = bfd_target_list ();
7073 for (l = list; *l != NULL; l++)
8620418b 7074 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7075 || strcmp (*l, "coff-x86-64") == 0
7076 || strcmp (*l, "pe-x86-64") == 0
7077 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7078 {
7079 default_arch = "x86_64";
7080 break;
7081 }
3e73aa7c 7082 if (*l == NULL)
6e0b89ee 7083 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7084 free (list);
7085 }
7086 break;
7087#endif
252b5132 7088
6e0b89ee
AM		 7089 case OPTION_32:
7090 default_arch = "i386";
7091 break;
7092
b3b91714
AM		 7093 case OPTION_DIVIDE:
7094#ifdef SVR4_COMMENT_CHARS
7095 {
7096 char *n, *t;
7097 const char *s;
7098
7099 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7100 t = n;
7101 for (s = i386_comment_chars; *s != '\0'; s++)
7102 if (*s != '/')
7103 *t++ = *s;
7104 *t = '\0';
7105 i386_comment_chars = n;
7106 }
7107#endif
7108 break;
7109
9103f4f4
L		 7110 case OPTION_MARCH:
7111 if (*arg == '.')
7112 as_fatal (_("Invalid -march= option: `%s'"), arg);
7113 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7114 {
7115 if (strcmp (arg, cpu_arch [i].name) == 0)
7116 {
ccc9c027 7117 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 7118 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 7119 if (!cpu_arch_tune_set)
7120 {
7121 cpu_arch_tune = cpu_arch_isa;
7122 cpu_arch_tune_flags = cpu_arch_isa_flags;
7123 }
9103f4f4
L		 7124 break;
7125 }
7126 }
7127 if (i >= ARRAY_SIZE (cpu_arch))
7128 as_fatal (_("Invalid -march= option: `%s'"), arg);
7129 break;
7130
7131 case OPTION_MTUNE:
7132 if (*arg == '.')
7133 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7134 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7135 {
7136 if (strcmp (arg, cpu_arch [i].name) == 0)
7137 {
ccc9c027 7138 cpu_arch_tune_set = 1;
9103f4f4
L		 7139 cpu_arch_tune = cpu_arch [i].type;
7140 cpu_arch_tune_flags = cpu_arch[i].flags;
7141 break;
7142 }
7143 }
7144 if (i >= ARRAY_SIZE (cpu_arch))
7145 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7146 break;
7147
252b5132
RH		 7148 default:
7149 return 0;
7150 }
7151 return 1;
7152}
7153
7154void
7155md_show_usage (stream)
7156 FILE *stream;
7157{
4cc782b5
ILT		 7158#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7159 fprintf (stream, _("\
a38cf1db
AM		 7160 -Q ignored\n\
7161 -V print assembler version number\n\
b3b91714
AM		 7162 -k ignored\n"));
7163#endif
7164 fprintf (stream, _("\
12b55ccc 7165 -n Do not optimize code alignment\n\
b3b91714
AM		 7166 -q quieten some warnings\n"));
7167#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7168 fprintf (stream, _("\
a38cf1db 7169 -s ignored\n"));
b3b91714 7170#endif
751d281c
L		 7171#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7172 fprintf (stream, _("\
7173 --32/--64 generate 32bit/64bit code\n"));
7174#endif
b3b91714
AM		 7175#ifdef SVR4_COMMENT_CHARS
7176 fprintf (stream, _("\
7177 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7178#else
7179 fprintf (stream, _("\
b3b91714 7180 --divide ignored\n"));
4cc782b5 7181#endif
9103f4f4
L		 7182 fprintf (stream, _("\
7183 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7184 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 7185 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 7186
252b5132
RH		 7187}
7188
3e73aa7c 7189#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 7190 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 7191
7192/* Pick the target format to use. */
7193
47926f60 7194const char *
e3bb37b5 7195i386_target_format (void)
252b5132 7196{
3e73aa7c 7197 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7198 {
7199 set_code_flag (CODE_64BIT);
c6fb90c8 7200 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7201 {
7202 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7203 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7204 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7205 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7206 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7207 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7208 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7209 cpu_arch_isa_flags.bitfield.cpummx= 1;
7210 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7211 cpu_arch_isa_flags.bitfield.cpusse = 1;
7212 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7213 }
c6fb90c8 7214 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7215 {
7216 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7217 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7218 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7219 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7220 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7221 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7222 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7223 cpu_arch_tune_flags.bitfield.cpummx= 1;
7224 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7225 cpu_arch_tune_flags.bitfield.cpusse = 1;
7226 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7227 }
9103f4f4 7228 }
3e73aa7c 7229 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7230 {
7231 set_code_flag (CODE_32BIT);
c6fb90c8 7232 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7233 {
7234 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7235 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7236 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7237 }
c6fb90c8 7238 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7239 {
7240 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7241 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7242 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7243 }
9103f4f4 7244 }
3e73aa7c
JH		 7245 else
7246 as_fatal (_("Unknown architecture"));
252b5132
RH		 7247 switch (OUTPUT_FLAVOR)
7248 {
872ce6ff
L		 7249#ifdef TE_PEP
7250 case bfd_target_coff_flavour:
7251 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7252 break;
7253#endif
4c63da97
AM		 7254#ifdef OBJ_MAYBE_AOUT
7255 case bfd_target_aout_flavour:
47926f60 7256 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7257#endif
7258#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7259 case bfd_target_coff_flavour:
7260 return "coff-i386";
4c63da97 7261#endif
3e73aa7c 7262#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7263 case bfd_target_elf_flavour:
3e73aa7c 7264 {
e5cb08ac 7265 if (flag_code == CODE_64BIT)
4fa24527
JB		 7266 {
7267 object_64bit = 1;
7268 use_rela_relocations = 1;
7269 }
9d7cbccd 7270 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7271 }
4c63da97 7272#endif
252b5132
RH		 7273 default:
7274 abort ();
7275 return NULL;
7276 }
7277}
7278
47926f60 7279#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 7280
7281#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 7282void
7283i386_elf_emit_arch_note (void)
a847613f 7284{
718ddfc0 7285 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 7286 {
7287 char *p;
7288 asection *seg = now_seg;
7289 subsegT subseg = now_subseg;
7290 Elf_Internal_Note i_note;
7291 Elf_External_Note e_note;
7292 asection *note_secp;
7293 int len;
7294
7295 /* Create the .note section. */
7296 note_secp = subseg_new (".note", 0);
7297 bfd_set_section_flags (stdoutput,
7298 note_secp,
7299 SEC_HAS_CONTENTS | SEC_READONLY);
7300
7301 /* Process the arch string. */
7302 len = strlen (cpu_arch_name);
7303
7304 i_note.namesz = len + 1;
7305 i_note.descsz = 0;
7306 i_note.type = NT_ARCH;
7307 p = frag_more (sizeof (e_note.namesz));
7308 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7309 p = frag_more (sizeof (e_note.descsz));
7310 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7311 p = frag_more (sizeof (e_note.type));
7312 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7313 p = frag_more (len + 1);
7314 strcpy (p, cpu_arch_name);
7315
7316 frag_align (2, 0, 0);
7317
7318 subseg_set (seg, subseg);
7319 }
7320}
7321#endif
252b5132 7322\f
252b5132
RH		 7323symbolS *
7324md_undefined_symbol (name)
7325 char *name;
7326{
18dc2407
ILT		 7327 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7328 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7329 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7330 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 7331 {
7332 if (!GOT_symbol)
7333 {
7334 if (symbol_find (name))
7335 as_bad (_("GOT already in symbol table"));
7336 GOT_symbol = symbol_new (name, undefined_section,
7337 (valueT) 0, &zero_address_frag);
7338 };
7339 return GOT_symbol;
7340 }
252b5132
RH		 7341 return 0;
7342}
7343
7344/* Round up a section size to the appropriate boundary. */
47926f60 7345
252b5132
RH		 7346valueT
7347md_section_align (segment, size)
ab9da554 7348 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7349 valueT size;
7350{
4c63da97
AM		 7351#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7352 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7353 {
7354 /* For a.out, force the section size to be aligned. If we don't do
7355 this, BFD will align it for us, but it will not write out the
7356 final bytes of the section. This may be a bug in BFD, but it is
7357 easier to fix it here since that is how the other a.out targets
7358 work. */
7359 int align;
7360
7361 align = bfd_get_section_alignment (stdoutput, segment);
7362 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7363 }
252b5132
RH		 7364#endif
7365
7366 return size;
7367}
7368
7369/* On the i386, PC-relative offsets are relative to the start of the
7370 next instruction. That is, the address of the offset, plus its
7371 size, since the offset is always the last part of the insn. */
7372
7373long
e3bb37b5 7374md_pcrel_from (fixS *fixP)
252b5132
RH		 7375{
7376 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7377}
7378
7379#ifndef I386COFF
7380
7381static void
e3bb37b5 7382s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 7383{
29b0f896 7384 int temp;
252b5132 7385
8a75718c
JB		 7386#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7387 if (IS_ELF)
7388 obj_elf_section_change_hook ();
7389#endif
252b5132
RH		 7390 temp = get_absolute_expression ();
7391 subseg_set (bss_section, (subsegT) temp);
7392 demand_empty_rest_of_line ();
7393}
7394
7395#endif
7396
252b5132 7397void
e3bb37b5 7398i386_validate_fix (fixS *fixp)
252b5132
RH		 7399{
7400 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7401 {
23df1078
JH		 7402 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7403 {
4fa24527 7404 if (!object_64bit)
23df1078
JH		 7405 abort ();
7406 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7407 }
7408 else
7409 {
4fa24527 7410 if (!object_64bit)
d6ab8113
JB		 7411 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7412 else
7413 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 7414 }
252b5132
RH		 7415 fixp->fx_subsy = 0;
7416 }
7417}
7418
252b5132
RH		 7419arelent *
7420tc_gen_reloc (section, fixp)
ab9da554 7421 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 7422 fixS *fixp;
7423{
7424 arelent *rel;
7425 bfd_reloc_code_real_type code;
7426
7427 switch (fixp->fx_r_type)
7428 {
3e73aa7c
JH		 7429 case BFD_RELOC_X86_64_PLT32:
7430 case BFD_RELOC_X86_64_GOT32:
7431 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 7432 case BFD_RELOC_386_PLT32:
7433 case BFD_RELOC_386_GOT32:
7434 case BFD_RELOC_386_GOTOFF:
7435 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 7436 case BFD_RELOC_386_TLS_GD:
7437 case BFD_RELOC_386_TLS_LDM:
7438 case BFD_RELOC_386_TLS_LDO_32:
7439 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7440 case BFD_RELOC_386_TLS_IE:
7441 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 7442 case BFD_RELOC_386_TLS_LE_32:
7443 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 7444 case BFD_RELOC_386_TLS_GOTDESC:
7445 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 7446 case BFD_RELOC_X86_64_TLSGD:
7447 case BFD_RELOC_X86_64_TLSLD:
7448 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7449 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 7450 case BFD_RELOC_X86_64_GOTTPOFF:
7451 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 7452 case BFD_RELOC_X86_64_TPOFF64:
7453 case BFD_RELOC_X86_64_GOTOFF64:
7454 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 7455 case BFD_RELOC_X86_64_GOT64:
7456 case BFD_RELOC_X86_64_GOTPCREL64:
7457 case BFD_RELOC_X86_64_GOTPC64:
7458 case BFD_RELOC_X86_64_GOTPLT64:
7459 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 7460 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7461 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 7462 case BFD_RELOC_RVA:
7463 case BFD_RELOC_VTABLE_ENTRY:
7464 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 7465#ifdef TE_PE
7466 case BFD_RELOC_32_SECREL:
7467#endif
252b5132
RH		 7468 code = fixp->fx_r_type;
7469 break;
dbbaec26
L		 7470 case BFD_RELOC_X86_64_32S:
7471 if (!fixp->fx_pcrel)
7472 {
7473 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7474 code = fixp->fx_r_type;
7475 break;
7476 }
252b5132 7477 default:
93382f6d 7478 if (fixp->fx_pcrel)
252b5132 7479 {
93382f6d
AM		 7480 switch (fixp->fx_size)
7481 {
7482 default:
b091f402
AM		 7483 as_bad_where (fixp->fx_file, fixp->fx_line,
7484 _("can not do %d byte pc-relative relocation"),
7485 fixp->fx_size);
93382f6d
AM		 7486 code = BFD_RELOC_32_PCREL;
7487 break;
7488 case 1: code = BFD_RELOC_8_PCREL; break;
7489 case 2: code = BFD_RELOC_16_PCREL; break;
7490 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 7491#ifdef BFD64
7492 case 8: code = BFD_RELOC_64_PCREL; break;
7493#endif
93382f6d
AM		 7494 }
7495 }
7496 else
7497 {
7498 switch (fixp->fx_size)
7499 {
7500 default:
b091f402
AM		 7501 as_bad_where (fixp->fx_file, fixp->fx_line,
7502 _("can not do %d byte relocation"),
7503 fixp->fx_size);
93382f6d
AM		 7504 code = BFD_RELOC_32;
7505 break;
7506 case 1: code = BFD_RELOC_8; break;
7507 case 2: code = BFD_RELOC_16; break;
7508 case 4: code = BFD_RELOC_32; break;
937149dd 7509#ifdef BFD64
3e73aa7c 7510 case 8: code = BFD_RELOC_64; break;
937149dd 7511#endif
93382f6d 7512 }
252b5132
RH		 7513 }
7514 break;
7515 }
252b5132 7516
d182319b
JB		 7517 if ((code == BFD_RELOC_32
7518 || code == BFD_RELOC_32_PCREL
7519 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7520 && GOT_symbol
7521 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7522 {
4fa24527 7523 if (!object_64bit)
d6ab8113
JB		 7524 code = BFD_RELOC_386_GOTPC;
7525 else
7526 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7527 }
7b81dfbb
AJ		 7528 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7529 && GOT_symbol
7530 && fixp->fx_addsy == GOT_symbol)
7531 {
7532 code = BFD_RELOC_X86_64_GOTPC64;
7533 }
252b5132
RH		 7534
7535 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7536 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7537 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7538
7539 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7540
3e73aa7c
JH		 7541 if (!use_rela_relocations)
7542 {
7543 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7544 vtable entry to be used in the relocation's section offset. */
7545 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7546 rel->address = fixp->fx_offset;
252b5132 7547
c6682705 7548 rel->addend = 0;
3e73aa7c
JH		 7549 }
7550 /* Use the rela in 64bit mode. */
252b5132 7551 else
3e73aa7c 7552 {
062cd5e7
AS		 7553 if (!fixp->fx_pcrel)
7554 rel->addend = fixp->fx_offset;
7555 else
7556 switch (code)
7557 {
7558 case BFD_RELOC_X86_64_PLT32:
7559 case BFD_RELOC_X86_64_GOT32:
7560 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7561 case BFD_RELOC_X86_64_TLSGD:
7562 case BFD_RELOC_X86_64_TLSLD:
7563 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7564 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7565 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7566 rel->addend = fixp->fx_offset - fixp->fx_size;
7567 break;
7568 default:
7569 rel->addend = (section->vma
7570 - fixp->fx_size
7571 + fixp->fx_addnumber
7572 + md_pcrel_from (fixp));
7573 break;
7574 }
3e73aa7c
JH		 7575 }
7576
252b5132
RH		 7577 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7578 if (rel->howto == NULL)
7579 {
7580 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7581 _("cannot represent relocation type %s"),
252b5132
RH		 7582 bfd_get_reloc_code_name (code));
7583 /* Set howto to a garbage value so that we can keep going. */
7584 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7585 assert (rel->howto != NULL);
7586 }
7587
7588 return rel;
7589}
7590
64a0c779
DN		 7591\f
7592/* Parse operands using Intel syntax. This implements a recursive descent
7593 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7594 Programmer's Guide.
7595
7596 FIXME: We do not recognize the full operand grammar defined in the MASM
7597 documentation. In particular, all the structure/union and
7598 high-level macro operands are missing.
7599
7600 Uppercase words are terminals, lower case words are non-terminals.
7601 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7602 bars '|' denote choices. Most grammar productions are implemented in
7603 functions called 'intel_<production>'.
7604
7605 Initial production is 'expr'.
7606
9306ca4a 7607 addOp + | -
64a0c779
DN		 7608
7609 alpha [a-zA-Z]
7610
9306ca4a
JB		 7611 binOp & | AND | \| | OR | ^ | XOR
7612
64a0c779
DN		 7613 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7614
7615 constant digits [[ radixOverride ]]
7616
9306ca4a 7617 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7618
7619 digits decdigit
b77a7acd
AJ		 7620 | digits decdigit
7621 | digits hexdigit
64a0c779
DN		 7622
7623 decdigit [0-9]
7624
9306ca4a
JB		 7625 e04 e04 addOp e05
7626 | e05
7627
7628 e05 e05 binOp e06
b77a7acd 7629 | e06
64a0c779
DN		 7630
7631 e06 e06 mulOp e09
b77a7acd 7632 | e09
64a0c779
DN		 7633
7634 e09 OFFSET e10
a724f0f4
JB		 7635 | SHORT e10
7636 | + e10
7637 | - e10
9306ca4a
JB		 7638 | ~ e10
7639 | NOT e10
64a0c779
DN		 7640 | e09 PTR e10
7641 | e09 : e10
7642 | e10
7643
7644 e10 e10 [ expr ]
b77a7acd 7645 | e11
64a0c779
DN		 7646
7647 e11 ( expr )
b77a7acd 7648 | [ expr ]
64a0c779
DN		 7649 | constant
7650 | dataType
7651 | id
7652 | $
7653 | register
7654
a724f0f4 7655 => expr expr cmpOp e04
9306ca4a 7656 | e04
64a0c779
DN		 7657
7658 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7659 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7660
7661 hexdigit a | b | c | d | e | f
b77a7acd 7662 | A | B | C | D | E | F
64a0c779
DN		 7663
7664 id alpha
b77a7acd 7665 | id alpha
64a0c779
DN		 7666 | id decdigit
7667
9306ca4a 7668 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7669
7670 quote " | '
7671
7672 register specialRegister
b77a7acd 7673 | gpRegister
64a0c779
DN		 7674 | byteRegister
7675
7676 segmentRegister CS | DS | ES | FS | GS | SS
7677
9306ca4a 7678 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 7679 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 7680 | TR3 | TR4 | TR5 | TR6 | TR7
7681
64a0c779
DN		 7682 We simplify the grammar in obvious places (e.g., register parsing is
7683 done by calling parse_register) and eliminate immediate left recursion
7684 to implement a recursive-descent parser.
7685
a724f0f4
JB		 7686 expr e04 expr'
7687
7688 expr' cmpOp e04 expr'
7689 | Empty
9306ca4a
JB		 7690
7691 e04 e05 e04'
7692
7693 e04' addOp e05 e04'
7694 | Empty
64a0c779
DN		 7695
7696 e05 e06 e05'
7697
9306ca4a 7698 e05' binOp e06 e05'
b77a7acd 7699 | Empty
64a0c779
DN		 7700
7701 e06 e09 e06'
7702
7703 e06' mulOp e09 e06'
b77a7acd 7704 | Empty
64a0c779
DN		 7705
7706 e09 OFFSET e10 e09'
a724f0f4
JB		 7707 | SHORT e10'
7708 | + e10'
7709 | - e10'
7710 | ~ e10'
7711 | NOT e10'
b77a7acd 7712 | e10 e09'
64a0c779
DN		 7713
7714 e09' PTR e10 e09'
b77a7acd 7715 | : e10 e09'
64a0c779
DN		 7716 | Empty
7717
7718 e10 e11 e10'
7719
7720 e10' [ expr ] e10'
b77a7acd 7721 | Empty
64a0c779
DN		 7722
7723 e11 ( expr )
b77a7acd 7724 | [ expr ]
64a0c779
DN		 7725 | BYTE
7726 | WORD
7727 | DWORD
9306ca4a 7728 | FWORD
64a0c779 7729 | QWORD
9306ca4a
JB		 7730 | TBYTE
7731 | OWORD
7732 | XMMWORD
64a0c779
DN		 7733 | .
7734 | $
7735 | register
7736 | id
7737 | constant */
7738
7739/* Parsing structure for the intel syntax parser. Used to implement the
7740 semantic actions for the operand grammar. */
7741struct intel_parser_s
7742 {
7743 char *op_string; /* The string being parsed. */
7744 int got_a_float; /* Whether the operand is a float. */
4a1805b1 7745 int op_modifier; /* Operand modifier. */
64a0c779 7746 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 7747 int in_offset; /* >=1 if parsing operand of offset. */
7748 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 7749 const reg_entry *reg; /* Last register reference found. */
7750 char *disp; /* Displacement string being built. */
a724f0f4 7751 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 7752 };
7753
7754static struct intel_parser_s intel_parser;
7755
7756/* Token structure for parsing intel syntax. */
7757struct intel_token
7758 {
7759 int code; /* Token code. */
7760 const reg_entry *reg; /* Register entry for register tokens. */
7761 char *str; /* String representation. */
7762 };
7763
7764static struct intel_token cur_token, prev_token;
7765
50705ef4
AM		 7766/* Token codes for the intel parser. Since T_SHORT is already used
7767 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 7768#define T_NIL -1
7769#define T_CONST 1
7770#define T_REG 2
7771#define T_BYTE 3
7772#define T_WORD 4
9306ca4a
JB		 7773#define T_DWORD 5
7774#define T_FWORD 6
7775#define T_QWORD 7
7776#define T_TBYTE 8
7777#define T_XMMWORD 9
50705ef4 7778#undef T_SHORT
9306ca4a
JB		 7779#define T_SHORT 10
7780#define T_OFFSET 11
7781#define T_PTR 12
7782#define T_ID 13
7783#define T_SHL 14
7784#define T_SHR 15
64a0c779
DN		 7785
7786/* Prototypes for intel parser functions. */
e3bb37b5
L		 7787static int intel_match_token (int);
7788static void intel_putback_token (void);
7789static void intel_get_token (void);
7790static int intel_expr (void);
7791static int intel_e04 (void);
7792static int intel_e05 (void);
7793static int intel_e06 (void);
7794static int intel_e09 (void);
7795static int intel_e10 (void);
7796static int intel_e11 (void);
64a0c779 7797
64a0c779 7798static int
e3bb37b5 7799i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 7800{
7801 int ret;
7802 char *p;
7803
a724f0f4
JB		 7804 p = intel_parser.op_string = xstrdup (operand_string);
7805 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7806
7807 for (;;)
64a0c779 7808 {
a724f0f4
JB		 7809 /* Initialize token holders. */
7810 cur_token.code = prev_token.code = T_NIL;
7811 cur_token.reg = prev_token.reg = NULL;
7812 cur_token.str = prev_token.str = NULL;
7813
7814 /* Initialize parser structure. */
7815 intel_parser.got_a_float = got_a_float;
7816 intel_parser.op_modifier = 0;
7817 intel_parser.is_mem = 0;
7818 intel_parser.in_offset = 0;
7819 intel_parser.in_bracket = 0;
7820 intel_parser.reg = NULL;
7821 intel_parser.disp[0] = '\0';
7822 intel_parser.next_operand = NULL;
7823
7824 /* Read the first token and start the parser. */
7825 intel_get_token ();
7826 ret = intel_expr ();
7827
7828 if (!ret)
7829 break;
7830
9306ca4a
JB		 7831 if (cur_token.code != T_NIL)
7832 {
7833 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7834 current_templates->start->name, cur_token.str);
7835 ret = 0;
7836 }
64a0c779
DN		 7837 /* If we found a memory reference, hand it over to i386_displacement
7838 to fill in the rest of the operand fields. */
9306ca4a 7839 else if (intel_parser.is_mem)
64a0c779
DN		 7840 {
7841 if ((i.mem_operands == 1
40fb9820 7842 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 7843 || i.mem_operands == 2)
7844 {
7845 as_bad (_("too many memory references for '%s'"),
7846 current_templates->start->name);
7847 ret = 0;
7848 }
7849 else
7850 {
7851 char *s = intel_parser.disp;
7852 i.mem_operands++;
7853
a724f0f4
JB		 7854 if (!quiet_warnings && intel_parser.is_mem < 0)
7855 /* See the comments in intel_bracket_expr. */
7856 as_warn (_("Treating `%s' as memory reference"), operand_string);
7857
64a0c779
DN		 7858 /* Add the displacement expression. */
7859 if (*s != '\0')
a4622f40
AM		 7860 ret = i386_displacement (s, s + strlen (s));
7861 if (ret)
a724f0f4
JB		 7862 {
7863 /* Swap base and index in 16-bit memory operands like
7864 [si+bx]. Since i386_index_check is also used in AT&T
7865 mode we have to do that here. */
7866 if (i.base_reg
7867 && i.index_reg
40fb9820
L		 7868 && i.base_reg->reg_type.bitfield.reg16
7869 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 7870 && i.base_reg->reg_num >= 6
7871 && i.index_reg->reg_num < 6)
7872 {
7873 const reg_entry *base = i.index_reg;
7874
7875 i.index_reg = i.base_reg;
7876 i.base_reg = base;
7877 }
7878 ret = i386_index_check (operand_string);
7879 }
64a0c779
DN		 7880 }
7881 }
7882
7883 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 7884 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 7885 || intel_parser.reg == NULL)
7886 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 7887
7888 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 7889 ret = 0;
a724f0f4
JB		 7890 if (!ret || !intel_parser.next_operand)
7891 break;
7892 intel_parser.op_string = intel_parser.next_operand;
7893 this_operand = i.operands++;
64a0c779
DN		 7894 }
7895
7896 free (p);
7897 free (intel_parser.disp);
7898
7899 return ret;
7900}
7901
a724f0f4
JB		 7902#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7903
7904/* expr e04 expr'
7905
7906 expr' cmpOp e04 expr'
7907 | Empty */
64a0c779 7908static int
e3bb37b5 7909intel_expr (void)
64a0c779 7910{
a724f0f4
JB		 7911 /* XXX Implement the comparison operators. */
7912 return intel_e04 ();
9306ca4a
JB		 7913}
7914
a724f0f4 7915/* e04 e05 e04'
9306ca4a 7916
a724f0f4 7917 e04' addOp e05 e04'
9306ca4a
JB		 7918 | Empty */
7919static int
e3bb37b5 7920intel_e04 (void)
9306ca4a 7921{
a724f0f4 7922 int nregs = -1;
9306ca4a 7923
a724f0f4 7924 for (;;)
9306ca4a 7925 {
a724f0f4
JB		 7926 if (!intel_e05())
7927 return 0;
9306ca4a 7928
a724f0f4
JB		 7929 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7930 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 7931
a724f0f4
JB		 7932 if (cur_token.code == '+')
7933 nregs = -1;
7934 else if (cur_token.code == '-')
7935 nregs = NUM_ADDRESS_REGS;
7936 else
7937 return 1;
64a0c779 7938
a724f0f4
JB		 7939 strcat (intel_parser.disp, cur_token.str);
7940 intel_match_token (cur_token.code);
7941 }
64a0c779
DN		 7942}
7943
64a0c779
DN		 7944/* e05 e06 e05'
7945
9306ca4a 7946 e05' binOp e06 e05'
64a0c779
DN		 7947 | Empty */
7948static int
e3bb37b5 7949intel_e05 (void)
64a0c779 7950{
a724f0f4 7951 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7952
a724f0f4 7953 for (;;)
64a0c779 7954 {
a724f0f4
JB		 7955 if (!intel_e06())
7956 return 0;
7957
4eed87de
AM		 7958 if (cur_token.code == '&'
7959 || cur_token.code == '|'
7960 || cur_token.code == '^')
a724f0f4
JB		 7961 {
7962 char str[2];
7963
7964 str[0] = cur_token.code;
7965 str[1] = 0;
7966 strcat (intel_parser.disp, str);
7967 }
7968 else
7969 break;
9306ca4a 7970
64a0c779
DN		 7971 intel_match_token (cur_token.code);
7972
a724f0f4
JB		 7973 if (nregs < 0)
7974 nregs = ~nregs;
64a0c779 7975 }
a724f0f4
JB		 7976 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7977 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7978 return 1;
4a1805b1 7979}
64a0c779
DN		 7980
7981/* e06 e09 e06'
7982
7983 e06' mulOp e09 e06'
b77a7acd 7984 | Empty */
64a0c779 7985static int
e3bb37b5 7986intel_e06 (void)
64a0c779 7987{
a724f0f4 7988 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7989
a724f0f4 7990 for (;;)
64a0c779 7991 {
a724f0f4
JB		 7992 if (!intel_e09())
7993 return 0;
9306ca4a 7994
4eed87de
AM		 7995 if (cur_token.code == '*'
7996 || cur_token.code == '/'
7997 || cur_token.code == '%')
a724f0f4
JB		 7998 {
7999 char str[2];
9306ca4a 8000
a724f0f4
JB		 8001 str[0] = cur_token.code;
8002 str[1] = 0;
8003 strcat (intel_parser.disp, str);
8004 }
8005 else if (cur_token.code == T_SHL)
8006 strcat (intel_parser.disp, "<<");
8007 else if (cur_token.code == T_SHR)
8008 strcat (intel_parser.disp, ">>");
8009 else
8010 break;
9306ca4a 8011
64e74474 8012 intel_match_token (cur_token.code);
64a0c779 8013
a724f0f4
JB		 8014 if (nregs < 0)
8015 nregs = ~nregs;
64a0c779 8016 }
a724f0f4
JB		 8017 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8018 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8019 return 1;
64a0c779
DN		 8020}
8021
a724f0f4
JB		 8022/* e09 OFFSET e09
8023 | SHORT e09
8024 | + e09
8025 | - e09
8026 | ~ e09
8027 | NOT e09
9306ca4a
JB		 8028 | e10 e09'
8029
64a0c779 8030 e09' PTR e10 e09'
b77a7acd 8031 | : e10 e09'
64a0c779
DN		 8032 | Empty */
8033static int
e3bb37b5 8034intel_e09 (void)
64a0c779 8035{
a724f0f4
JB		 8036 int nregs = ~NUM_ADDRESS_REGS;
8037 int in_offset = 0;
8038
8039 for (;;)
64a0c779 8040 {
a724f0f4
JB		 8041 /* Don't consume constants here. */
8042 if (cur_token.code == '+' || cur_token.code == '-')
8043 {
8044 /* Need to look one token ahead - if the next token
8045 is a constant, the current token is its sign. */
8046 int next_code;
8047
8048 intel_match_token (cur_token.code);
8049 next_code = cur_token.code;
8050 intel_putback_token ();
8051 if (next_code == T_CONST)
8052 break;
8053 }
8054
8055 /* e09 OFFSET e09 */
8056 if (cur_token.code == T_OFFSET)
8057 {
8058 if (!in_offset++)
8059 ++intel_parser.in_offset;
8060 }
8061
8062 /* e09 SHORT e09 */
8063 else if (cur_token.code == T_SHORT)
8064 intel_parser.op_modifier |= 1 << T_SHORT;
8065
8066 /* e09 + e09 */
8067 else if (cur_token.code == '+')
8068 strcat (intel_parser.disp, "+");
8069
8070 /* e09 - e09
8071 | ~ e09
8072 | NOT e09 */
8073 else if (cur_token.code == '-' || cur_token.code == '~')
8074 {
8075 char str[2];
64a0c779 8076
a724f0f4
JB		 8077 if (nregs < 0)
8078 nregs = ~nregs;
8079 str[0] = cur_token.code;
8080 str[1] = 0;
8081 strcat (intel_parser.disp, str);
8082 }
8083
8084 /* e09 e10 e09' */
8085 else
8086 break;
8087
8088 intel_match_token (cur_token.code);
64a0c779
DN		 8089 }
8090
a724f0f4 8091 for (;;)
9306ca4a 8092 {
a724f0f4
JB		 8093 if (!intel_e10 ())
8094 return 0;
9306ca4a 8095
a724f0f4
JB		 8096 /* e09' PTR e10 e09' */
8097 if (cur_token.code == T_PTR)
8098 {
8099 char suffix;
9306ca4a 8100
a724f0f4
JB		 8101 if (prev_token.code == T_BYTE)
8102 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 8103
a724f0f4
JB		 8104 else if (prev_token.code == T_WORD)
8105 {
8106 if (current_templates->start->name[0] == 'l'
8107 && current_templates->start->name[2] == 's'
8108 && current_templates->start->name[3] == 0)
8109 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8110 else if (intel_parser.got_a_float == 2) /* "fi..." */
8111 suffix = SHORT_MNEM_SUFFIX;
8112 else
8113 suffix = WORD_MNEM_SUFFIX;
8114 }
64a0c779 8115
a724f0f4
JB		 8116 else if (prev_token.code == T_DWORD)
8117 {
8118 if (current_templates->start->name[0] == 'l'
8119 && current_templates->start->name[2] == 's'
8120 && current_templates->start->name[3] == 0)
8121 suffix = WORD_MNEM_SUFFIX;
8122 else if (flag_code == CODE_16BIT
40fb9820
L		 8123 && (current_templates->start->opcode_modifier.jump
8124 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 8125 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8126 else if (intel_parser.got_a_float == 1) /* "f..." */
8127 suffix = SHORT_MNEM_SUFFIX;
8128 else
8129 suffix = LONG_MNEM_SUFFIX;
8130 }
9306ca4a 8131
a724f0f4
JB		 8132 else if (prev_token.code == T_FWORD)
8133 {
8134 if (current_templates->start->name[0] == 'l'
8135 && current_templates->start->name[2] == 's'
8136 && current_templates->start->name[3] == 0)
8137 suffix = LONG_MNEM_SUFFIX;
8138 else if (!intel_parser.got_a_float)
8139 {
8140 if (flag_code == CODE_16BIT)
8141 add_prefix (DATA_PREFIX_OPCODE);
8142 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8143 }
8144 else
8145 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8146 }
64a0c779 8147
a724f0f4
JB		 8148 else if (prev_token.code == T_QWORD)
8149 {
8150 if (intel_parser.got_a_float == 1) /* "f..." */
8151 suffix = LONG_MNEM_SUFFIX;
8152 else
8153 suffix = QWORD_MNEM_SUFFIX;
8154 }
64a0c779 8155
a724f0f4
JB		 8156 else if (prev_token.code == T_TBYTE)
8157 {
8158 if (intel_parser.got_a_float == 1)
8159 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8160 else
8161 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8162 }
9306ca4a 8163
a724f0f4 8164 else if (prev_token.code == T_XMMWORD)
9306ca4a 8165 {
a724f0f4
JB		 8166 /* XXX ignored for now, but accepted since gcc uses it */
8167 suffix = 0;
9306ca4a 8168 }
64a0c779 8169
f16b83df 8170 else
a724f0f4
JB		 8171 {
8172 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8173 return 0;
8174 }
8175
435acd52
JB		 8176 /* Operands for jump/call using 'ptr' notation denote absolute
8177 addresses. */
40fb9820
L		 8178 if (current_templates->start->opcode_modifier.jump
8179 || current_templates->start->opcode_modifier.jumpdword)
8180 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8181
a724f0f4
JB		 8182 if (current_templates->start->base_opcode == 0x8d /* lea */)
8183 ;
8184 else if (!i.suffix)
8185 i.suffix = suffix;
8186 else if (i.suffix != suffix)
8187 {
8188 as_bad (_("Conflicting operand modifiers"));
8189 return 0;
8190 }
64a0c779 8191
9306ca4a
JB		 8192 }
8193
a724f0f4
JB		 8194 /* e09' : e10 e09' */
8195 else if (cur_token.code == ':')
9306ca4a 8196 {
a724f0f4
JB		 8197 if (prev_token.code != T_REG)
8198 {
8199 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8200 segment/group identifier (which we don't have), using comma
8201 as the operand separator there is even less consistent, since
8202 there all branches only have a single operand. */
8203 if (this_operand != 0
8204 || intel_parser.in_offset
8205 || intel_parser.in_bracket
40fb9820
L		 8206 || (!current_templates->start->opcode_modifier.jump
8207 && !current_templates->start->opcode_modifier.jumpdword
8208 && !current_templates->start->opcode_modifier.jumpintersegment
8209 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 8210 return intel_match_token (T_NIL);
8211 /* Remember the start of the 2nd operand and terminate 1st
8212 operand here.
8213 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8214 another expression), but it gets at least the simplest case
8215 (a plain number or symbol on the left side) right. */
8216 intel_parser.next_operand = intel_parser.op_string;
8217 *--intel_parser.op_string = '\0';
8218 return intel_match_token (':');
8219 }
9306ca4a 8220 }
64a0c779 8221
a724f0f4 8222 /* e09' Empty */
64a0c779 8223 else
a724f0f4 8224 break;
64a0c779 8225
a724f0f4
JB		 8226 intel_match_token (cur_token.code);
8227
8228 }
8229
8230 if (in_offset)
8231 {
8232 --intel_parser.in_offset;
8233 if (nregs < 0)
8234 nregs = ~nregs;
8235 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 8236 {
a724f0f4 8237 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 8238 return 0;
8239 }
a724f0f4
JB		 8240 intel_parser.op_modifier |= 1 << T_OFFSET;
8241 }
9306ca4a 8242
a724f0f4
JB		 8243 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8244 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8245 return 1;
8246}
64a0c779 8247
a724f0f4 8248static int
e3bb37b5 8249intel_bracket_expr (void)
a724f0f4
JB		 8250{
8251 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8252 const char *start = intel_parser.op_string;
8253 int len;
8254
8255 if (i.op[this_operand].regs)
8256 return intel_match_token (T_NIL);
8257
8258 intel_match_token ('[');
8259
8260 /* Mark as a memory operand only if it's not already known to be an
8261 offset expression. If it's an offset expression, we need to keep
8262 the brace in. */
8263 if (!intel_parser.in_offset)
8264 {
8265 ++intel_parser.in_bracket;
435acd52
JB		 8266
8267 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 8268 if (current_templates->start->opcode_modifier.jump
8269 || current_templates->start->opcode_modifier.jumpdword)
8270 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8271
a724f0f4
JB		 8272 /* Unfortunately gas always diverged from MASM in a respect that can't
8273 be easily fixed without risking to break code sequences likely to be
8274 encountered (the testsuite even check for this): MASM doesn't consider
8275 an expression inside brackets unconditionally as a memory reference.
8276 When that is e.g. a constant, an offset expression, or the sum of the
8277 two, this is still taken as a constant load. gas, however, always
8278 treated these as memory references. As a compromise, we'll try to make
8279 offset expressions inside brackets work the MASM way (since that's
8280 less likely to be found in real world code), but make constants alone
8281 continue to work the traditional gas way. In either case, issue a
8282 warning. */
8283 intel_parser.op_modifier &= ~was_offset;
64a0c779 8284 }
a724f0f4 8285 else
64e74474 8286 strcat (intel_parser.disp, "[");
a724f0f4
JB		 8287
8288 /* Add a '+' to the displacement string if necessary. */
8289 if (*intel_parser.disp != '\0'
8290 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8291 strcat (intel_parser.disp, "+");
64a0c779 8292
a724f0f4
JB		 8293 if (intel_expr ()
8294 && (len = intel_parser.op_string - start - 1,
8295 intel_match_token (']')))
64a0c779 8296 {
a724f0f4
JB		 8297 /* Preserve brackets when the operand is an offset expression. */
8298 if (intel_parser.in_offset)
8299 strcat (intel_parser.disp, "]");
8300 else
8301 {
8302 --intel_parser.in_bracket;
8303 if (i.base_reg || i.index_reg)
8304 intel_parser.is_mem = 1;
8305 if (!intel_parser.is_mem)
8306 {
8307 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8308 /* Defer the warning until all of the operand was parsed. */
8309 intel_parser.is_mem = -1;
8310 else if (!quiet_warnings)
4eed87de
AM		 8311 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8312 len, start, len, start);
a724f0f4
JB		 8313 }
8314 }
8315 intel_parser.op_modifier |= was_offset;
64a0c779 8316
a724f0f4 8317 return 1;
64a0c779 8318 }
a724f0f4 8319 return 0;
64a0c779
DN		 8320}
8321
8322/* e10 e11 e10'
8323
8324 e10' [ expr ] e10'
b77a7acd 8325 | Empty */
64a0c779 8326static int
e3bb37b5 8327intel_e10 (void)
64a0c779 8328{
a724f0f4
JB		 8329 if (!intel_e11 ())
8330 return 0;
64a0c779 8331
a724f0f4 8332 while (cur_token.code == '[')
64a0c779 8333 {
a724f0f4 8334 if (!intel_bracket_expr ())
21d6c4af 8335 return 0;
64a0c779
DN		 8336 }
8337
a724f0f4 8338 return 1;
64a0c779
DN		 8339}
8340
64a0c779 8341/* e11 ( expr )
b77a7acd 8342 | [ expr ]
64a0c779
DN		 8343 | BYTE
8344 | WORD
8345 | DWORD
9306ca4a 8346 | FWORD
64a0c779 8347 | QWORD
9306ca4a
JB		 8348 | TBYTE
8349 | OWORD
8350 | XMMWORD
4a1805b1 8351 | $
64a0c779
DN		 8352 | .
8353 | register
8354 | id
8355 | constant */
8356static int
e3bb37b5 8357intel_e11 (void)
64a0c779 8358{
a724f0f4 8359 switch (cur_token.code)
64a0c779 8360 {
a724f0f4
JB		 8361 /* e11 ( expr ) */
8362 case '(':
64a0c779
DN		 8363 intel_match_token ('(');
8364 strcat (intel_parser.disp, "(");
8365
8366 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 8367 {
8368 strcat (intel_parser.disp, ")");
8369 return 1;
8370 }
a724f0f4 8371 return 0;
4a1805b1 8372
a724f0f4
JB		 8373 /* e11 [ expr ] */
8374 case '[':
a724f0f4 8375 return intel_bracket_expr ();
64a0c779 8376
a724f0f4
JB		 8377 /* e11 $
8378 | . */
8379 case '.':
64a0c779
DN		 8380 strcat (intel_parser.disp, cur_token.str);
8381 intel_match_token (cur_token.code);
21d6c4af
DN		 8382
8383 /* Mark as a memory operand only if it's not already known to be an
8384 offset expression. */
a724f0f4 8385 if (!intel_parser.in_offset)
21d6c4af 8386 intel_parser.is_mem = 1;
64a0c779
DN		 8387
8388 return 1;
64a0c779 8389
a724f0f4
JB		 8390 /* e11 register */
8391 case T_REG:
8392 {
8393 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 8394
a724f0f4 8395 intel_match_token (T_REG);
64a0c779 8396
a724f0f4
JB		 8397 /* Check for segment change. */
8398 if (cur_token.code == ':')
8399 {
40fb9820
L		 8400 if (!reg->reg_type.bitfield.sreg2
8401 && !reg->reg_type.bitfield.sreg3)
a724f0f4 8402 {
4eed87de
AM		 8403 as_bad (_("`%s' is not a valid segment register"),
8404 reg->reg_name);
a724f0f4
JB		 8405 return 0;
8406 }
8407 else if (i.seg[i.mem_operands])
8408 as_warn (_("Extra segment override ignored"));
8409 else
8410 {
8411 if (!intel_parser.in_offset)
8412 intel_parser.is_mem = 1;
8413 switch (reg->reg_num)
8414 {
8415 case 0:
8416 i.seg[i.mem_operands] = &es;
8417 break;
8418 case 1:
8419 i.seg[i.mem_operands] = &cs;
8420 break;
8421 case 2:
8422 i.seg[i.mem_operands] = &ss;
8423 break;
8424 case 3:
8425 i.seg[i.mem_operands] = &ds;
8426 break;
8427 case 4:
8428 i.seg[i.mem_operands] = &fs;
8429 break;
8430 case 5:
8431 i.seg[i.mem_operands] = &gs;
8432 break;
8433 }
8434 }
8435 }
64a0c779 8436
a724f0f4
JB		 8437 /* Not a segment register. Check for register scaling. */
8438 else if (cur_token.code == '*')
8439 {
8440 if (!intel_parser.in_bracket)
8441 {
8442 as_bad (_("Register scaling only allowed in memory operands"));
8443 return 0;
8444 }
64a0c779 8445
40fb9820 8446 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 8447 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8448 else if (i.index_reg)
8449 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 8450
a724f0f4
JB		 8451 /* What follows must be a valid scale. */
8452 intel_match_token ('*');
8453 i.index_reg = reg;
40fb9820 8454 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 8455
a724f0f4
JB		 8456 /* Set the scale after setting the register (otherwise,
8457 i386_scale will complain) */
8458 if (cur_token.code == '+' || cur_token.code == '-')
8459 {
8460 char *str, sign = cur_token.code;
8461 intel_match_token (cur_token.code);
8462 if (cur_token.code != T_CONST)
8463 {
8464 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8465 cur_token.str);
8466 return 0;
8467 }
8468 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8469 strcpy (str + 1, cur_token.str);
8470 *str = sign;
8471 if (!i386_scale (str))
8472 return 0;
8473 free (str);
8474 }
8475 else if (!i386_scale (cur_token.str))
64a0c779 8476 return 0;
a724f0f4
JB		 8477 intel_match_token (cur_token.code);
8478 }
64a0c779 8479
a724f0f4
JB		 8480 /* No scaling. If this is a memory operand, the register is either a
8481 base register (first occurrence) or an index register (second
8482 occurrence). */
7b0441f6 8483 else if (intel_parser.in_bracket)
a724f0f4 8484 {
64a0c779 8485
a724f0f4
JB		 8486 if (!i.base_reg)
8487 i.base_reg = reg;
8488 else if (!i.index_reg)
8489 i.index_reg = reg;
8490 else
8491 {
8492 as_bad (_("Too many register references in memory operand"));
8493 return 0;
8494 }
64a0c779 8495
40fb9820 8496 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8497 }
4a1805b1 8498
4d1bb795
JB		 8499 /* It's neither base nor index. */
8500 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8501 {
40fb9820
L		 8502 i386_operand_type temp = reg->reg_type;
8503 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8504 i.types[this_operand] = operand_type_or (i.types[this_operand],
8505 temp);
a724f0f4
JB		 8506 i.op[this_operand].regs = reg;
8507 i.reg_operands++;
8508 }
8509 else
8510 {
8511 as_bad (_("Invalid use of register"));
8512 return 0;
8513 }
64a0c779 8514
a724f0f4
JB		 8515 /* Since registers are not part of the displacement string (except
8516 when we're parsing offset operands), we may need to remove any
8517 preceding '+' from the displacement string. */
8518 if (*intel_parser.disp != '\0'
8519 && !intel_parser.in_offset)
8520 {
8521 char *s = intel_parser.disp;
8522 s += strlen (s) - 1;
8523 if (*s == '+')
8524 *s = '\0';
8525 }
4a1805b1 8526
a724f0f4
JB		 8527 return 1;
8528 }
8529
8530 /* e11 BYTE
8531 | WORD
8532 | DWORD
8533 | FWORD
8534 | QWORD
8535 | TBYTE
8536 | OWORD
8537 | XMMWORD */
8538 case T_BYTE:
8539 case T_WORD:
8540 case T_DWORD:
8541 case T_FWORD:
8542 case T_QWORD:
8543 case T_TBYTE:
8544 case T_XMMWORD:
8545 intel_match_token (cur_token.code);
64a0c779 8546
a724f0f4
JB		 8547 if (cur_token.code == T_PTR)
8548 return 1;
8549
8550 /* It must have been an identifier. */
8551 intel_putback_token ();
8552 cur_token.code = T_ID;
8553 /* FALLTHRU */
8554
8555 /* e11 id
8556 | constant */
8557 case T_ID:
8558 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8559 {
8560 symbolS *symbolP;
8561
a724f0f4
JB		 8562 /* The identifier represents a memory reference only if it's not
8563 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8564 symbolP = symbol_find(cur_token.str);
8565 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8566 intel_parser.is_mem = 1;
8567 }
a724f0f4 8568 /* FALLTHRU */
64a0c779 8569
a724f0f4
JB		 8570 case T_CONST:
8571 case '-':
8572 case '+':
8573 {
8574 char *save_str, sign = 0;
64a0c779 8575
a724f0f4
JB		 8576 /* Allow constants that start with `+' or `-'. */
8577 if (cur_token.code == '-' || cur_token.code == '+')
8578 {
8579 sign = cur_token.code;
8580 intel_match_token (cur_token.code);
8581 if (cur_token.code != T_CONST)
8582 {
8583 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8584 cur_token.str);
8585 return 0;
8586 }
8587 }
64a0c779 8588
a724f0f4
JB		 8589 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8590 strcpy (save_str + !!sign, cur_token.str);
8591 if (sign)
8592 *save_str = sign;
64a0c779 8593
a724f0f4
JB		 8594 /* Get the next token to check for register scaling. */
8595 intel_match_token (cur_token.code);
64a0c779 8596
4eed87de
AM		 8597 /* Check if this constant is a scaling factor for an
8598 index register. */
a724f0f4
JB		 8599 if (cur_token.code == '*')
8600 {
8601 if (intel_match_token ('*') && cur_token.code == T_REG)
8602 {
8603 const reg_entry *reg = cur_token.reg;
8604
8605 if (!intel_parser.in_bracket)
8606 {
4eed87de
AM		 8607 as_bad (_("Register scaling only allowed "
8608 "in memory operands"));
a724f0f4
JB		 8609 return 0;
8610 }
8611
4eed87de
AM		 8612 /* Disallow things like [1*si].
8613 sp and esp are invalid as index. */
40fb9820 8614 if (reg->reg_type.bitfield.reg16)
4eed87de 8615 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8616 else if (i.index_reg)
4eed87de 8617 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8618
8619 /* The constant is followed by `* reg', so it must be
8620 a valid scale. */
8621 i.index_reg = reg;
40fb9820 8622 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8623
8624 /* Set the scale after setting the register (otherwise,
8625 i386_scale will complain) */
8626 if (!i386_scale (save_str))
64a0c779 8627 return 0;
a724f0f4
JB		 8628 intel_match_token (T_REG);
8629
8630 /* Since registers are not part of the displacement
8631 string, we may need to remove any preceding '+' from
8632 the displacement string. */
8633 if (*intel_parser.disp != '\0')
8634 {
8635 char *s = intel_parser.disp;
8636 s += strlen (s) - 1;
8637 if (*s == '+')
8638 *s = '\0';
8639 }
8640
8641 free (save_str);
8642
8643 return 1;
8644 }
64a0c779 8645
a724f0f4
JB		 8646 /* The constant was not used for register scaling. Since we have
8647 already consumed the token following `*' we now need to put it
8648 back in the stream. */
64a0c779 8649 intel_putback_token ();
a724f0f4 8650 }
64a0c779 8651
a724f0f4
JB		 8652 /* Add the constant to the displacement string. */
8653 strcat (intel_parser.disp, save_str);
8654 free (save_str);
64a0c779 8655
a724f0f4
JB		 8656 return 1;
8657 }
64a0c779
DN		 8658 }
8659
64a0c779
DN		 8660 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8661 return 0;
8662}
8663
64a0c779
DN		 8664/* Match the given token against cur_token. If they match, read the next
8665 token from the operand string. */
8666static int
e3bb37b5 8667intel_match_token (int code)
64a0c779
DN		 8668{
8669 if (cur_token.code == code)
8670 {
8671 intel_get_token ();
8672 return 1;
8673 }
8674 else
8675 {
0477af35 8676 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 8677 return 0;
8678 }
8679}
8680
64a0c779
DN		 8681/* Read a new token from intel_parser.op_string and store it in cur_token. */
8682static void
e3bb37b5 8683intel_get_token (void)
64a0c779
DN		 8684{
8685 char *end_op;
8686 const reg_entry *reg;
8687 struct intel_token new_token;
8688
8689 new_token.code = T_NIL;
8690 new_token.reg = NULL;
8691 new_token.str = NULL;
8692
4a1805b1 8693 /* Free the memory allocated to the previous token and move
64a0c779
DN		 8694 cur_token to prev_token. */
8695 if (prev_token.str)
8696 free (prev_token.str);
8697
8698 prev_token = cur_token;
8699
8700 /* Skip whitespace. */
8701 while (is_space_char (*intel_parser.op_string))
8702 intel_parser.op_string++;
8703
8704 /* Return an empty token if we find nothing else on the line. */
8705 if (*intel_parser.op_string == '\0')
8706 {
8707 cur_token = new_token;
8708 return;
8709 }
8710
8711 /* The new token cannot be larger than the remainder of the operand
8712 string. */
a724f0f4 8713 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 8714 new_token.str[0] = '\0';
8715
8716 if (strchr ("0123456789", *intel_parser.op_string))
8717 {
8718 char *p = new_token.str;
8719 char *q = intel_parser.op_string;
8720 new_token.code = T_CONST;
8721
8722 /* Allow any kind of identifier char to encompass floating point and
8723 hexadecimal numbers. */
8724 while (is_identifier_char (*q))
8725 *p++ = *q++;
8726 *p = '\0';
8727
8728 /* Recognize special symbol names [0-9][bf]. */
8729 if (strlen (intel_parser.op_string) == 2
4a1805b1 8730 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 8731 || intel_parser.op_string[1] == 'f'))
8732 new_token.code = T_ID;
8733 }
8734
4d1bb795 8735 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 8736 {
4d1bb795
JB		 8737 size_t len = end_op - intel_parser.op_string;
8738
64a0c779
DN		 8739 new_token.code = T_REG;
8740 new_token.reg = reg;
8741
4d1bb795
JB		 8742 memcpy (new_token.str, intel_parser.op_string, len);
8743 new_token.str[len] = '\0';
64a0c779
DN		 8744 }
8745
8746 else if (is_identifier_char (*intel_parser.op_string))
8747 {
8748 char *p = new_token.str;
8749 char *q = intel_parser.op_string;
8750
8751 /* A '.' or '$' followed by an identifier char is an identifier.
8752 Otherwise, it's operator '.' followed by an expression. */
8753 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8754 {
9306ca4a
JB		 8755 new_token.code = '.';
8756 new_token.str[0] = '.';
64a0c779
DN		 8757 new_token.str[1] = '\0';
8758 }
8759 else
8760 {
8761 while (is_identifier_char (*q) || *q == '@')
8762 *p++ = *q++;
8763 *p = '\0';
8764
9306ca4a
JB		 8765 if (strcasecmp (new_token.str, "NOT") == 0)
8766 new_token.code = '~';
8767
8768 else if (strcasecmp (new_token.str, "MOD") == 0)
8769 new_token.code = '%';
8770
8771 else if (strcasecmp (new_token.str, "AND") == 0)
8772 new_token.code = '&';
8773
8774 else if (strcasecmp (new_token.str, "OR") == 0)
8775 new_token.code = '|';
8776
8777 else if (strcasecmp (new_token.str, "XOR") == 0)
8778 new_token.code = '^';
8779
8780 else if (strcasecmp (new_token.str, "SHL") == 0)
8781 new_token.code = T_SHL;
8782
8783 else if (strcasecmp (new_token.str, "SHR") == 0)
8784 new_token.code = T_SHR;
8785
8786 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 8787 new_token.code = T_BYTE;
8788
8789 else if (strcasecmp (new_token.str, "WORD") == 0)
8790 new_token.code = T_WORD;
8791
8792 else if (strcasecmp (new_token.str, "DWORD") == 0)
8793 new_token.code = T_DWORD;
8794
9306ca4a
JB		 8795 else if (strcasecmp (new_token.str, "FWORD") == 0)
8796 new_token.code = T_FWORD;
8797
64a0c779
DN		 8798 else if (strcasecmp (new_token.str, "QWORD") == 0)
8799 new_token.code = T_QWORD;
8800
9306ca4a
JB		 8801 else if (strcasecmp (new_token.str, "TBYTE") == 0
8802 /* XXX remove (gcc still uses it) */
8803 || strcasecmp (new_token.str, "XWORD") == 0)
8804 new_token.code = T_TBYTE;
8805
8806 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8807 || strcasecmp (new_token.str, "OWORD") == 0)
8808 new_token.code = T_XMMWORD;
64a0c779
DN		 8809
8810 else if (strcasecmp (new_token.str, "PTR") == 0)
8811 new_token.code = T_PTR;
8812
8813 else if (strcasecmp (new_token.str, "SHORT") == 0)
8814 new_token.code = T_SHORT;
8815
8816 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8817 {
8818 new_token.code = T_OFFSET;
8819
8820 /* ??? This is not mentioned in the MASM grammar but gcc
8821 makes use of it with -mintel-syntax. OFFSET may be
8822 followed by FLAT: */
8823 if (strncasecmp (q, " FLAT:", 6) == 0)
8824 strcat (new_token.str, " FLAT:");
8825 }
8826
8827 /* ??? This is not mentioned in the MASM grammar. */
8828 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 8829 {
8830 new_token.code = T_OFFSET;
8831 if (*q == ':')
8832 strcat (new_token.str, ":");
8833 else
8834 as_bad (_("`:' expected"));
8835 }
64a0c779
DN		 8836
8837 else
8838 new_token.code = T_ID;
8839 }
8840 }
8841
9306ca4a
JB		 8842 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8843 {
8844 new_token.code = *intel_parser.op_string;
8845 new_token.str[0] = *intel_parser.op_string;
8846 new_token.str[1] = '\0';
8847 }
8848
8849 else if (strchr ("<>", *intel_parser.op_string)
8850 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8851 {
8852 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8853 new_token.str[0] = *intel_parser.op_string;
8854 new_token.str[1] = *intel_parser.op_string;
8855 new_token.str[2] = '\0';
8856 }
8857
64a0c779 8858 else
0477af35 8859 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 8860
8861 intel_parser.op_string += strlen (new_token.str);
8862 cur_token = new_token;
8863}
8864
64a0c779
DN		 8865/* Put cur_token back into the token stream and make cur_token point to
8866 prev_token. */
8867static void
e3bb37b5 8868intel_putback_token (void)
64a0c779 8869{
a724f0f4
JB		 8870 if (cur_token.code != T_NIL)
8871 {
8872 intel_parser.op_string -= strlen (cur_token.str);
8873 free (cur_token.str);
8874 }
64a0c779 8875 cur_token = prev_token;
4a1805b1 8876
64a0c779
DN		 8877 /* Forget prev_token. */
8878 prev_token.code = T_NIL;
8879 prev_token.reg = NULL;
8880 prev_token.str = NULL;
8881}
54cfded0 8882
a4447b93 8883int
1df69f4f 8884tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 8885{
8886 unsigned int regnum;
8887 unsigned int regnames_count;
089dfecd 8888 static const char *const regnames_32[] =
54cfded0 8889 {
a4447b93
RH		 8890 "eax", "ecx", "edx", "ebx",
8891 "esp", "ebp", "esi", "edi",
089dfecd
JB		 8892 "eip", "eflags", NULL,
8893 "st0", "st1", "st2", "st3",
8894 "st4", "st5", "st6", "st7",
8895 NULL, NULL,
8896 "xmm0", "xmm1", "xmm2", "xmm3",
8897 "xmm4", "xmm5", "xmm6", "xmm7",
8898 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8899 "mm4", "mm5", "mm6", "mm7",
8900 "fcw", "fsw", "mxcsr",
8901 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8902 "tr", "ldtr"
54cfded0 8903 };
089dfecd 8904 static const char *const regnames_64[] =
54cfded0 8905 {
089dfecd
JB		 8906 "rax", "rdx", "rcx", "rbx",
8907 "rsi", "rdi", "rbp", "rsp",
8908 "r8", "r9", "r10", "r11",
54cfded0 8909 "r12", "r13", "r14", "r15",
089dfecd
JB		 8910 "rip",
8911 "xmm0", "xmm1", "xmm2", "xmm3",
8912 "xmm4", "xmm5", "xmm6", "xmm7",
8913 "xmm8", "xmm9", "xmm10", "xmm11",
8914 "xmm12", "xmm13", "xmm14", "xmm15",
8915 "st0", "st1", "st2", "st3",
8916 "st4", "st5", "st6", "st7",
8917 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8918 "mm4", "mm5", "mm6", "mm7",
8919 "rflags",
8920 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8921 "fs.base", "gs.base", NULL, NULL,
8922 "tr", "ldtr",
8923 "mxcsr", "fcw", "fsw"
54cfded0 8924 };
089dfecd 8925 const char *const *regnames;
54cfded0
AM		 8926
8927 if (flag_code == CODE_64BIT)
8928 {
8929 regnames = regnames_64;
0cea6190 8930 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 8931 }
8932 else
8933 {
8934 regnames = regnames_32;
0cea6190 8935 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 8936 }
8937
8938 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 8939 if (regnames[regnum] != NULL
8940 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 8941 return regnum;
8942
54cfded0
AM		 8943 return -1;
8944}
8945
8946void
8947tc_x86_frame_initial_instructions (void)
8948{
a4447b93
RH		 8949 static unsigned int sp_regno;
8950
8951 if (!sp_regno)
8952 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8953 ? "rsp" : "esp");
8954
8955 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8956 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8957}
d2b2c203
DJ		 8958
8959int
8960i386_elf_section_type (const char *str, size_t len)
8961{
8962 if (flag_code == CODE_64BIT
8963 && len == sizeof ("unwind") - 1
8964 && strncmp (str, "unwind", 6) == 0)
8965 return SHT_X86_64_UNWIND;
8966
8967 return -1;
8968}
bb41ade5
AM		 8969
8970#ifdef TE_PE
8971void
8972tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8973{
8974 expressionS expr;
8975
8976 expr.X_op = O_secrel;
8977 expr.X_add_symbol = symbol;
8978 expr.X_add_number = 0;
8979 emit_expr (&expr, size);
8980}
8981#endif
3b22753a
L		 8982
8983#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8984/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8985
8986int
8987x86_64_section_letter (int letter, char **ptr_msg)
8988{
8989 if (flag_code == CODE_64BIT)
8990 {
8991 if (letter == 'l')
8992 return SHF_X86_64_LARGE;
8993
8994 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8995 }
3b22753a 8996 else
64e74474 8997 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8998 return -1;
8999}
9000
9001int
9002x86_64_section_word (char *str, size_t len)
9003{
8620418b 9004 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9005 return SHF_X86_64_LARGE;
9006
9007 return -1;
9008}
9009
9010static void
9011handle_large_common (int small ATTRIBUTE_UNUSED)
9012{
9013 if (flag_code != CODE_64BIT)
9014 {
9015 s_comm_internal (0, elf_common_parse);
9016 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9017 }
9018 else
9019 {
9020 static segT lbss_section;
9021 asection *saved_com_section_ptr = elf_com_section_ptr;
9022 asection *saved_bss_section = bss_section;
9023
9024 if (lbss_section == NULL)
9025 {
9026 flagword applicable;
9027 segT seg = now_seg;
9028 subsegT subseg = now_subseg;
9029
9030 /* The .lbss section is for local .largecomm symbols. */
9031 lbss_section = subseg_new (".lbss", 0);
9032 applicable = bfd_applicable_section_flags (stdoutput);
9033 bfd_set_section_flags (stdoutput, lbss_section,
9034 applicable & SEC_ALLOC);
9035 seg_info (lbss_section)->bss = 1;
9036
9037 subseg_set (seg, subseg);
9038 }
9039
9040 elf_com_section_ptr = &_bfd_elf_large_com_section;
9041 bss_section = lbss_section;
9042
9043 s_comm_internal (0, elf_common_parse);
9044
9045 elf_com_section_ptr = saved_com_section_ptr;
9046 bss_section = saved_bss_section;
9047 }
9048}
9049#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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