projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* dwarf_reader.cc (Sized_dwarf_line_info::read_header_prolog,
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5dd15031 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
84/* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86#define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88#define END_OF_INSN '\0'
89
90/*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97typedef struct
98{
99 const template *start;
100 const template *end;
101}
102templates;
103
104/* 386 operand encoding bytes: see 386 book for details of this. */
105typedef struct
106{
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110}
111modrm_byte;
112
113/* x86-64 extension prefix. */
114typedef int rex_byte;
115
116/* The SSE5 instructions have a two bit instruction modifier (OC) that
117 is stored in two separate bytes in the instruction. Pick apart OC
118 into the 2 separate bits for instruction. */
119#define DREX_OC0(x) (((x) & 1) != 0)
120#define DREX_OC1(x) (((x) & 2) != 0)
121
122#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
123#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
124
125/* OC mappings */
126#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
127#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
128#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
129#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
130
131#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
132#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
133
134/* Information needed to create the DREX byte in SSE5 instructions. */
135typedef struct
136{
137 unsigned int reg; /* register */
138 unsigned int rex; /* REX flags */
139 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
140 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
141} drex_byte;
142
143/* 386 opcode byte to code indirect addressing. */
144typedef struct
145{
146 unsigned base;
147 unsigned index;
148 unsigned scale;
149}
150sib_byte;
151
152enum processor_type
153{
154 PROCESSOR_UNKNOWN,
155 PROCESSOR_I386,
156 PROCESSOR_I486,
157 PROCESSOR_PENTIUM,
158 PROCESSOR_PENTIUMPRO,
159 PROCESSOR_PENTIUM4,
160 PROCESSOR_NOCONA,
161 PROCESSOR_CORE,
162 PROCESSOR_CORE2,
163 PROCESSOR_K6,
164 PROCESSOR_ATHLON,
165 PROCESSOR_K8,
166 PROCESSOR_GENERIC32,
167 PROCESSOR_GENERIC64,
168 PROCESSOR_AMDFAM10
169};
170
171/* x86 arch names, types and features */
172typedef struct
173{
174 const char *name; /* arch name */
175 enum processor_type type; /* arch type */
176 i386_cpu_flags flags; /* cpu feature flags */
177}
178arch_entry;
179
e3bb37b5
L		 180static void set_code_flag (int);
181static void set_16bit_gcc_code_flag (int);
182static void set_intel_syntax (int);
1efbbeb4 183static void set_intel_mnemonic (int);
db51cc60 184static void set_allow_index_reg (int);
e3bb37b5 185static void set_cpu_arch (int);
6482c264 186#ifdef TE_PE
e3bb37b5 187static void pe_directive_secrel (int);
6482c264 188#endif
e3bb37b5
L		 189static void signed_cons (int);
190static char *output_invalid (int c);
a7619375 191static int i386_att_operand (char *);
e3bb37b5
L		 192static int i386_intel_operand (char *, int);
193static const reg_entry *parse_register (char *, char **);
194static char *parse_insn (char *, char *);
195static char *parse_operands (char *, const char *);
196static void swap_operands (void);
4d456e3d 197static void swap_2_operands (int, int);
e3bb37b5
L		 198static void optimize_imm (void);
199static void optimize_disp (void);
200static int match_template (void);
201static int check_string (void);
202static int process_suffix (void);
203static int check_byte_reg (void);
204static int check_long_reg (void);
205static int check_qword_reg (void);
206static int check_word_reg (void);
207static int finalize_imm (void);
85f10a01 208static void process_drex (void);
e3bb37b5
L		 209static int process_operands (void);
210static const seg_entry *build_modrm_byte (void);
211static void output_insn (void);
212static void output_imm (fragS *, offsetT);
213static void output_disp (fragS *, offsetT);
29b0f896 214#ifndef I386COFF
e3bb37b5 215static void s_bss (int);
252b5132 216#endif
17d4e2a2
L		 217#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
218static void handle_large_common (int small ATTRIBUTE_UNUSED);
219#endif
252b5132 220
a847613f 221static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 222
252b5132 223/* 'md_assemble ()' gathers together information and puts it into a
47926f60 224 i386_insn. */
252b5132 225
520dc8e8
AM		 226union i386_op
227 {
228 expressionS *disps;
229 expressionS *imms;
230 const reg_entry *regs;
231 };
232
252b5132
RH		 233struct _i386_insn
234 {
47926f60 235 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 236 template tm;
237
7d5e4556
L		 238 /* SUFFIX holds the instruction size suffix for byte, word, dword
239 or qword, if given. */
252b5132
RH		 240 char suffix;
241
47926f60 242 /* OPERANDS gives the number of given operands. */
252b5132
RH		 243 unsigned int operands;
244
245 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
246 of given register, displacement, memory operands and immediate
47926f60 247 operands. */
252b5132
RH		 248 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
249
250 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 251 use OP[i] for the corresponding operand. */
40fb9820 252 i386_operand_type types[MAX_OPERANDS];
252b5132 253
520dc8e8
AM		 254 /* Displacement expression, immediate expression, or register for each
255 operand. */
256 union i386_op op[MAX_OPERANDS];
252b5132 257
3e73aa7c
JH		 258 /* Flags for operands. */
259 unsigned int flags[MAX_OPERANDS];
260#define Operand_PCrel 1
261
252b5132 262 /* Relocation type for operand */
f86103b7 263 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 264
252b5132
RH		 265 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
266 the base index byte below. */
267 const reg_entry *base_reg;
268 const reg_entry *index_reg;
269 unsigned int log2_scale_factor;
270
271 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 272 explicit segment overrides are given. */
ce8a8b2f 273 const seg_entry *seg[2];
252b5132
RH		 274
275 /* PREFIX holds all the given prefix opcodes (usually null).
276 PREFIXES is the number of prefix opcodes. */
277 unsigned int prefixes;
278 unsigned char prefix[MAX_PREFIXES];
279
280 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 281 addressing modes of this insn are encoded. DREX is the byte
282 added by the SSE5 instructions. */
252b5132
RH		 283
284 modrm_byte rm;
3e73aa7c 285 rex_byte rex;
252b5132 286 sib_byte sib;
85f10a01 287 drex_byte drex;
252b5132
RH		 288 };
289
290typedef struct _i386_insn i386_insn;
291
292/* List of chars besides those in app.c:symbol_chars that can start an
293 operand. Used to prevent the scrubber eating vital white-space. */
32137342 294const char extra_symbol_chars[] = "*%-(["
252b5132 295#ifdef LEX_AT
32137342
NC		 296 "@"
297#endif
298#ifdef LEX_QM
299 "?"
252b5132 300#endif
32137342 301 ;
252b5132 302
29b0f896
AM		 303#if (defined (TE_I386AIX) \
304 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 305 && !defined (TE_GNU) \
29b0f896 306 && !defined (TE_LINUX) \
32137342 307 && !defined (TE_NETWARE) \
29b0f896
AM		 308 && !defined (TE_FreeBSD) \
309 && !defined (TE_NetBSD)))
252b5132 310/* This array holds the chars that always start a comment. If the
b3b91714
AM		 311 pre-processor is disabled, these aren't very useful. The option
312 --divide will remove '/' from this list. */
313const char *i386_comment_chars = "#/";
314#define SVR4_COMMENT_CHARS 1
252b5132 315#define PREFIX_SEPARATOR '\\'
252b5132 316
b3b91714
AM		 317#else
318const char *i386_comment_chars = "#";
319#define PREFIX_SEPARATOR '/'
320#endif
321
252b5132
RH		 322/* This array holds the chars that only start a comment at the beginning of
323 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 324 .line and .file directives will appear in the pre-processed output.
325 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 326 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 327 #NO_APP at the beginning of its output.
328 Also note that comments started like this one will always work if
252b5132 329 '/' isn't otherwise defined. */
b3b91714 330const char line_comment_chars[] = "#/";
252b5132 331
63a0b638 332const char line_separator_chars[] = ";";
252b5132 333
ce8a8b2f
AM		 334/* Chars that can be used to separate mant from exp in floating point
335 nums. */
252b5132
RH		 336const char EXP_CHARS[] = "eE";
337
ce8a8b2f
AM		 338/* Chars that mean this number is a floating point constant
339 As in 0f12.456
340 or 0d1.2345e12. */
252b5132
RH		 341const char FLT_CHARS[] = "fFdDxX";
342
ce8a8b2f 343/* Tables for lexical analysis. */
252b5132
RH		 344static char mnemonic_chars[256];
345static char register_chars[256];
346static char operand_chars[256];
347static char identifier_chars[256];
348static char digit_chars[256];
349
ce8a8b2f 350/* Lexical macros. */
252b5132
RH		 351#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
352#define is_operand_char(x) (operand_chars[(unsigned char) x])
353#define is_register_char(x) (register_chars[(unsigned char) x])
354#define is_space_char(x) ((x) == ' ')
355#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
356#define is_digit_char(x) (digit_chars[(unsigned char) x])
357
0234cb7c 358/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 359static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
360
361/* md_assemble() always leaves the strings it's passed unaltered. To
362 effect this we maintain a stack of saved characters that we've smashed
363 with '\0's (indicating end of strings for various sub-fields of the
47926f60 364 assembler instruction). */
252b5132 365static char save_stack[32];
ce8a8b2f 366static char *save_stack_p;
252b5132
RH		 367#define END_STRING_AND_SAVE(s) \
368 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
369#define RESTORE_END_STRING(s) \
370 do { *(s) = *--save_stack_p; } while (0)
371
47926f60 372/* The instruction we're assembling. */
252b5132
RH		 373static i386_insn i;
374
375/* Possible templates for current insn. */
376static const templates *current_templates;
377
31b2323c
L		 378/* Per instruction expressionS buffers: max displacements & immediates. */
379static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
380static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 381
47926f60
KH		 382/* Current operand we are working on. */
383static int this_operand;
252b5132 384
3e73aa7c
JH		 385/* We support four different modes. FLAG_CODE variable is used to distinguish
386 these. */
387
388enum flag_code {
389 CODE_32BIT,
390 CODE_16BIT,
391 CODE_64BIT };
392
393static enum flag_code flag_code;
4fa24527 394static unsigned int object_64bit;
3e73aa7c
JH		 395static int use_rela_relocations = 0;
396
397/* The names used to print error messages. */
b77a7acd 398static const char *flag_code_names[] =
3e73aa7c
JH		 399 {
400 "32",
401 "16",
402 "64"
403 };
252b5132 404
47926f60
KH		 405/* 1 for intel syntax,
406 0 if att syntax. */
407static int intel_syntax = 0;
252b5132 408
1efbbeb4
L		 409/* 1 for intel mnemonic,
410 0 if att mnemonic. */
411static int intel_mnemonic = !SYSV386_COMPAT;
412
5209009a 413/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 414static int old_gcc = OLDGCC_COMPAT;
415
a60de03c
JB		 416/* 1 if pseudo registers are permitted. */
417static int allow_pseudo_reg = 0;
418
47926f60
KH		 419/* 1 if register prefix % not required. */
420static int allow_naked_reg = 0;
252b5132 421
ba104c83 422/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 423static int allow_index_reg = 0;
424
2ca3ace5
L		 425/* Register prefix used for error message. */
426static const char *register_prefix = "%";
427
47926f60
KH		 428/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
429 leave, push, and pop instructions so that gcc has the same stack
430 frame as in 32 bit mode. */
431static char stackop_size = '\0';
eecb386c 432
12b55ccc
L		 433/* Non-zero to optimize code alignment. */
434int optimize_align_code = 1;
435
47926f60
KH		 436/* Non-zero to quieten some warnings. */
437static int quiet_warnings = 0;
a38cf1db 438
47926f60
KH		 439/* CPU name. */
440static const char *cpu_arch_name = NULL;
6305a203 441static char *cpu_sub_arch_name = NULL;
a38cf1db 442
47926f60 443/* CPU feature flags. */
40fb9820
L		 444static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
445
ccc9c027
L		 446/* If we have selected a cpu we are generating instructions for. */
447static int cpu_arch_tune_set = 0;
448
9103f4f4
L		 449/* Cpu we are generating instructions for. */
450static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
451
452/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 453static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 454
ccc9c027
L		 455/* CPU instruction set architecture used. */
456static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
457
9103f4f4 458/* CPU feature flags of instruction set architecture used. */
40fb9820 459static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 460
fddf5b5b
AM		 461/* If set, conditional jumps are not automatically promoted to handle
462 larger than a byte offset. */
463static unsigned int no_cond_jump_promotion = 0;
464
29b0f896 465/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 466static symbolS *GOT_symbol;
29b0f896 467
a4447b93
RH		 468/* The dwarf2 return column, adjusted for 32 or 64 bit. */
469unsigned int x86_dwarf2_return_column;
470
471/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
472int x86_cie_data_alignment;
473
252b5132 474/* Interface to relax_segment.
fddf5b5b
AM		 475 There are 3 major relax states for 386 jump insns because the
476 different types of jumps add different sizes to frags when we're
477 figuring out what sort of jump to choose to reach a given label. */
252b5132 478
47926f60 479/* Types. */
93c2a809
AM		 480#define UNCOND_JUMP 0
481#define COND_JUMP 1
482#define COND_JUMP86 2
fddf5b5b 483
47926f60 484/* Sizes. */
252b5132
RH		 485#define CODE16 1
486#define SMALL 0
29b0f896 487#define SMALL16 (SMALL | CODE16)
252b5132 488#define BIG 2
29b0f896 489#define BIG16 (BIG | CODE16)
252b5132
RH		 490
491#ifndef INLINE
492#ifdef __GNUC__
493#define INLINE __inline__
494#else
495#define INLINE
496#endif
497#endif
498
fddf5b5b
AM		 499#define ENCODE_RELAX_STATE(type, size) \
500 ((relax_substateT) (((type) << 2) | (size)))
501#define TYPE_FROM_RELAX_STATE(s) \
502 ((s) >> 2)
503#define DISP_SIZE_FROM_RELAX_STATE(s) \
504 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 505
506/* This table is used by relax_frag to promote short jumps to long
507 ones where necessary. SMALL (short) jumps may be promoted to BIG
508 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
509 don't allow a short jump in a 32 bit code segment to be promoted to
510 a 16 bit offset jump because it's slower (requires data size
511 prefix), and doesn't work, unless the destination is in the bottom
512 64k of the code segment (The top 16 bits of eip are zeroed). */
513
514const relax_typeS md_relax_table[] =
515{
24eab124
AM		 516 /* The fields are:
517 1) most positive reach of this state,
518 2) most negative reach of this state,
93c2a809 519 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 520 4) which index into the table to try if we can't fit into this one. */
252b5132 521
fddf5b5b 522 /* UNCOND_JUMP states. */
93c2a809
AM		 523 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
524 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
525 /* dword jmp adds 4 bytes to frag:
526 0 extra opcode bytes, 4 displacement bytes. */
252b5132 527 {0, 0, 4, 0},
93c2a809
AM		 528 /* word jmp adds 2 byte2 to frag:
529 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 530 {0, 0, 2, 0},
531
93c2a809
AM		 532 /* COND_JUMP states. */
533 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
534 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
535 /* dword conditionals adds 5 bytes to frag:
536 1 extra opcode byte, 4 displacement bytes. */
537 {0, 0, 5, 0},
fddf5b5b 538 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 539 1 extra opcode byte, 2 displacement bytes. */
540 {0, 0, 3, 0},
541
542 /* COND_JUMP86 states. */
543 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
544 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
545 /* dword conditionals adds 5 bytes to frag:
546 1 extra opcode byte, 4 displacement bytes. */
547 {0, 0, 5, 0},
548 /* word conditionals add 4 bytes to frag:
549 1 displacement byte and a 3 byte long branch insn. */
550 {0, 0, 4, 0}
252b5132
RH		 551};
552
9103f4f4
L		 553static const arch_entry cpu_arch[] =
554{
6305a203
L		 555 { "generic32", PROCESSOR_GENERIC32,
556 CPU_GENERIC32_FLAGS },
557 { "generic64", PROCESSOR_GENERIC64,
558 CPU_GENERIC64_FLAGS },
559 { "i8086", PROCESSOR_UNKNOWN,
560 CPU_NONE_FLAGS },
561 { "i186", PROCESSOR_UNKNOWN,
562 CPU_I186_FLAGS },
563 { "i286", PROCESSOR_UNKNOWN,
564 CPU_I286_FLAGS },
565 { "i386", PROCESSOR_I386,
566 CPU_I386_FLAGS },
567 { "i486", PROCESSOR_I486,
568 CPU_I486_FLAGS },
569 { "i586", PROCESSOR_PENTIUM,
570 CPU_I586_FLAGS },
571 { "i686", PROCESSOR_PENTIUMPRO,
572 CPU_I686_FLAGS },
573 { "pentium", PROCESSOR_PENTIUM,
574 CPU_I586_FLAGS },
575 { "pentiumpro", PROCESSOR_PENTIUMPRO,
576 CPU_I686_FLAGS },
577 { "pentiumii", PROCESSOR_PENTIUMPRO,
578 CPU_P2_FLAGS },
579 { "pentiumiii",PROCESSOR_PENTIUMPRO,
580 CPU_P3_FLAGS },
581 { "pentium4", PROCESSOR_PENTIUM4,
582 CPU_P4_FLAGS },
583 { "prescott", PROCESSOR_NOCONA,
584 CPU_CORE_FLAGS },
585 { "nocona", PROCESSOR_NOCONA,
586 CPU_NOCONA_FLAGS },
587 { "yonah", PROCESSOR_CORE,
588 CPU_CORE_FLAGS },
589 { "core", PROCESSOR_CORE,
590 CPU_CORE_FLAGS },
591 { "merom", PROCESSOR_CORE2,
592 CPU_CORE2_FLAGS },
593 { "core2", PROCESSOR_CORE2,
594 CPU_CORE2_FLAGS },
595 { "k6", PROCESSOR_K6,
596 CPU_K6_FLAGS },
597 { "k6_2", PROCESSOR_K6,
598 CPU_K6_2_FLAGS },
599 { "athlon", PROCESSOR_ATHLON,
600 CPU_ATHLON_FLAGS },
601 { "sledgehammer", PROCESSOR_K8,
602 CPU_K8_FLAGS },
603 { "opteron", PROCESSOR_K8,
604 CPU_K8_FLAGS },
605 { "k8", PROCESSOR_K8,
606 CPU_K8_FLAGS },
607 { "amdfam10", PROCESSOR_AMDFAM10,
608 CPU_AMDFAM10_FLAGS },
609 { ".mmx", PROCESSOR_UNKNOWN,
610 CPU_MMX_FLAGS },
611 { ".sse", PROCESSOR_UNKNOWN,
612 CPU_SSE_FLAGS },
613 { ".sse2", PROCESSOR_UNKNOWN,
614 CPU_SSE2_FLAGS },
615 { ".sse3", PROCESSOR_UNKNOWN,
616 CPU_SSE3_FLAGS },
617 { ".ssse3", PROCESSOR_UNKNOWN,
618 CPU_SSSE3_FLAGS },
619 { ".sse4.1", PROCESSOR_UNKNOWN,
620 CPU_SSE4_1_FLAGS },
621 { ".sse4.2", PROCESSOR_UNKNOWN,
622 CPU_SSE4_2_FLAGS },
623 { ".sse4", PROCESSOR_UNKNOWN,
624 CPU_SSE4_2_FLAGS },
625 { ".vmx", PROCESSOR_UNKNOWN,
626 CPU_VMX_FLAGS },
627 { ".smx", PROCESSOR_UNKNOWN,
628 CPU_SMX_FLAGS },
f03fe4c1
L		 629 { ".xsave", PROCESSOR_UNKNOWN,
630 CPU_XSAVE_FLAGS },
6305a203
L		 631 { ".3dnow", PROCESSOR_UNKNOWN,
632 CPU_3DNOW_FLAGS },
633 { ".3dnowa", PROCESSOR_UNKNOWN,
634 CPU_3DNOWA_FLAGS },
635 { ".padlock", PROCESSOR_UNKNOWN,
636 CPU_PADLOCK_FLAGS },
637 { ".pacifica", PROCESSOR_UNKNOWN,
638 CPU_SVME_FLAGS },
639 { ".svme", PROCESSOR_UNKNOWN,
640 CPU_SVME_FLAGS },
641 { ".sse4a", PROCESSOR_UNKNOWN,
642 CPU_SSE4A_FLAGS },
643 { ".abm", PROCESSOR_UNKNOWN,
644 CPU_ABM_FLAGS },
645 { ".sse5", PROCESSOR_UNKNOWN,
646 CPU_SSE5_FLAGS },
e413e4e9
AM		 647};
648
29b0f896
AM		 649const pseudo_typeS md_pseudo_table[] =
650{
651#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
652 {"align", s_align_bytes, 0},
653#else
654 {"align", s_align_ptwo, 0},
655#endif
656 {"arch", set_cpu_arch, 0},
657#ifndef I386COFF
658 {"bss", s_bss, 0},
659#endif
660 {"ffloat", float_cons, 'f'},
661 {"dfloat", float_cons, 'd'},
662 {"tfloat", float_cons, 'x'},
663 {"value", cons, 2},
d182319b 664 {"slong", signed_cons, 4},
29b0f896
AM		 665 {"noopt", s_ignore, 0},
666 {"optim", s_ignore, 0},
667 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
668 {"code16", set_code_flag, CODE_16BIT},
669 {"code32", set_code_flag, CODE_32BIT},
670 {"code64", set_code_flag, CODE_64BIT},
671 {"intel_syntax", set_intel_syntax, 1},
672 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 673 {"intel_mnemonic", set_intel_mnemonic, 1},
674 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 675 {"allow_index_reg", set_allow_index_reg, 1},
676 {"disallow_index_reg", set_allow_index_reg, 0},
3b22753a
L		 677#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
678 {"largecomm", handle_large_common, 0},
07a53e5c 679#else
e3bb37b5 680 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 681 {"loc", dwarf2_directive_loc, 0},
682 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 683#endif
6482c264
NC		 684#ifdef TE_PE
685 {"secrel32", pe_directive_secrel, 0},
686#endif
29b0f896
AM		 687 {0, 0, 0}
688};
689
690/* For interface with expression (). */
691extern char *input_line_pointer;
692
693/* Hash table for instruction mnemonic lookup. */
694static struct hash_control *op_hash;
695
696/* Hash table for register lookup. */
697static struct hash_control *reg_hash;
698\f
252b5132 699void
e3bb37b5 700i386_align_code (fragS *fragP, int count)
252b5132 701{
ce8a8b2f
AM		 702 /* Various efficient no-op patterns for aligning code labels.
703 Note: Don't try to assemble the instructions in the comments.
704 0L and 0w are not legal. */
252b5132
RH		 705 static const char f32_1[] =
706 {0x90}; /* nop */
707 static const char f32_2[] =
ccc9c027 708 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 709 static const char f32_3[] =
710 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
711 static const char f32_4[] =
712 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
713 static const char f32_5[] =
714 {0x90, /* nop */
715 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
716 static const char f32_6[] =
717 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
718 static const char f32_7[] =
719 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
720 static const char f32_8[] =
721 {0x90, /* nop */
722 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
723 static const char f32_9[] =
724 {0x89,0xf6, /* movl %esi,%esi */
725 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
726 static const char f32_10[] =
727 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
728 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
729 static const char f32_11[] =
730 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
731 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
732 static const char f32_12[] =
733 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
734 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
735 static const char f32_13[] =
736 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
737 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
738 static const char f32_14[] =
739 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
740 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 741 static const char f16_3[] =
742 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 743 static const char f16_4[] =
744 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
745 static const char f16_5[] =
746 {0x90, /* nop */
747 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
748 static const char f16_6[] =
749 {0x89,0xf6, /* mov %si,%si */
750 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
751 static const char f16_7[] =
752 {0x8d,0x74,0x00, /* lea 0(%si),%si */
753 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
754 static const char f16_8[] =
755 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
756 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 757 static const char jump_31[] =
758 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
759 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
760 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
761 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 762 static const char *const f32_patt[] = {
763 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 764 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 765 };
766 static const char *const f16_patt[] = {
76bc74dc 767 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 768 };
ccc9c027
L		 769 /* nopl (%[re]ax) */
770 static const char alt_3[] =
771 {0x0f,0x1f,0x00};
772 /* nopl 0(%[re]ax) */
773 static const char alt_4[] =
774 {0x0f,0x1f,0x40,0x00};
775 /* nopl 0(%[re]ax,%[re]ax,1) */
776 static const char alt_5[] =
777 {0x0f,0x1f,0x44,0x00,0x00};
778 /* nopw 0(%[re]ax,%[re]ax,1) */
779 static const char alt_6[] =
780 {0x66,0x0f,0x1f,0x44,0x00,0x00};
781 /* nopl 0L(%[re]ax) */
782 static const char alt_7[] =
783 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
784 /* nopl 0L(%[re]ax,%[re]ax,1) */
785 static const char alt_8[] =
786 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
787 /* nopw 0L(%[re]ax,%[re]ax,1) */
788 static const char alt_9[] =
789 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
790 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
791 static const char alt_10[] =
792 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
793 /* data16
794 nopw %cs:0L(%[re]ax,%[re]ax,1) */
795 static const char alt_long_11[] =
796 {0x66,
797 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
798 /* data16
799 data16
800 nopw %cs:0L(%[re]ax,%[re]ax,1) */
801 static const char alt_long_12[] =
802 {0x66,
803 0x66,
804 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
805 /* data16
806 data16
807 data16
808 nopw %cs:0L(%[re]ax,%[re]ax,1) */
809 static const char alt_long_13[] =
810 {0x66,
811 0x66,
812 0x66,
813 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
814 /* data16
815 data16
816 data16
817 data16
818 nopw %cs:0L(%[re]ax,%[re]ax,1) */
819 static const char alt_long_14[] =
820 {0x66,
821 0x66,
822 0x66,
823 0x66,
824 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
825 /* data16
826 data16
827 data16
828 data16
829 data16
830 nopw %cs:0L(%[re]ax,%[re]ax,1) */
831 static const char alt_long_15[] =
832 {0x66,
833 0x66,
834 0x66,
835 0x66,
836 0x66,
837 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
838 /* nopl 0(%[re]ax,%[re]ax,1)
839 nopw 0(%[re]ax,%[re]ax,1) */
840 static const char alt_short_11[] =
841 {0x0f,0x1f,0x44,0x00,0x00,
842 0x66,0x0f,0x1f,0x44,0x00,0x00};
843 /* nopw 0(%[re]ax,%[re]ax,1)
844 nopw 0(%[re]ax,%[re]ax,1) */
845 static const char alt_short_12[] =
846 {0x66,0x0f,0x1f,0x44,0x00,0x00,
847 0x66,0x0f,0x1f,0x44,0x00,0x00};
848 /* nopw 0(%[re]ax,%[re]ax,1)
849 nopl 0L(%[re]ax) */
850 static const char alt_short_13[] =
851 {0x66,0x0f,0x1f,0x44,0x00,0x00,
852 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
853 /* nopl 0L(%[re]ax)
854 nopl 0L(%[re]ax) */
855 static const char alt_short_14[] =
856 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
857 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
858 /* nopl 0L(%[re]ax)
859 nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_short_15[] =
861 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
862 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 static const char *const alt_short_patt[] = {
864 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
865 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
866 alt_short_14, alt_short_15
867 };
868 static const char *const alt_long_patt[] = {
869 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
870 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
871 alt_long_14, alt_long_15
872 };
252b5132 873
76bc74dc
L		 874 /* Only align for at least a positive non-zero boundary. */
875 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 876 return;
3e73aa7c 877
ccc9c027
L		 878 /* We need to decide which NOP sequence to use for 32bit and
879 64bit. When -mtune= is used:
4eed87de 880
76bc74dc
L		 881 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
882 PROCESSOR_GENERIC32, f32_patt will be used.
883 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
884 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
885 alt_long_patt will be used.
886 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
887 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 888
76bc74dc
L		 889 When -mtune= isn't used, alt_long_patt will be used if
890 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
891 be used.
ccc9c027
L		 892
893 When -march= or .arch is used, we can't use anything beyond
894 cpu_arch_isa_flags. */
895
896 if (flag_code == CODE_16BIT)
897 {
ccc9c027 898 if (count > 8)
33fef721 899 {
76bc74dc
L		 900 memcpy (fragP->fr_literal + fragP->fr_fix,
901 jump_31, count);
902 /* Adjust jump offset. */
903 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 904 }
76bc74dc
L		 905 else
906 memcpy (fragP->fr_literal + fragP->fr_fix,
907 f16_patt[count - 1], count);
252b5132 908 }
33fef721 909 else
ccc9c027
L		 910 {
911 const char *const *patt = NULL;
912
913 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
914 {
915 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
916 switch (cpu_arch_tune)
917 {
918 case PROCESSOR_UNKNOWN:
919 /* We use cpu_arch_isa_flags to check if we SHOULD
920 optimize for Cpu686. */
40fb9820 921 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 922 patt = alt_long_patt;
ccc9c027
L		 923 else
924 patt = f32_patt;
925 break;
ccc9c027
L		 926 case PROCESSOR_PENTIUMPRO:
927 case PROCESSOR_PENTIUM4:
928 case PROCESSOR_NOCONA:
ef05d495 929 case PROCESSOR_CORE:
76bc74dc
L		 930 case PROCESSOR_CORE2:
931 case PROCESSOR_GENERIC64:
932 patt = alt_long_patt;
933 break;
ccc9c027
L		 934 case PROCESSOR_K6:
935 case PROCESSOR_ATHLON:
936 case PROCESSOR_K8:
4eed87de 937 case PROCESSOR_AMDFAM10:
ccc9c027
L		 938 patt = alt_short_patt;
939 break;
76bc74dc 940 case PROCESSOR_I386:
ccc9c027
L		 941 case PROCESSOR_I486:
942 case PROCESSOR_PENTIUM:
943 case PROCESSOR_GENERIC32:
944 patt = f32_patt;
945 break;
4eed87de 946 }
ccc9c027
L		 947 }
948 else
949 {
950 switch (cpu_arch_tune)
951 {
952 case PROCESSOR_UNKNOWN:
953 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
954 PROCESSOR_UNKNOWN. */
955 abort ();
956 break;
957
76bc74dc 958 case PROCESSOR_I386:
ccc9c027
L		 959 case PROCESSOR_I486:
960 case PROCESSOR_PENTIUM:
ccc9c027
L		 961 case PROCESSOR_K6:
962 case PROCESSOR_ATHLON:
963 case PROCESSOR_K8:
4eed87de 964 case PROCESSOR_AMDFAM10:
ccc9c027
L		 965 case PROCESSOR_GENERIC32:
966 /* We use cpu_arch_isa_flags to check if we CAN optimize
967 for Cpu686. */
40fb9820 968 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 969 patt = alt_short_patt;
970 else
971 patt = f32_patt;
972 break;
76bc74dc
L		 973 case PROCESSOR_PENTIUMPRO:
974 case PROCESSOR_PENTIUM4:
975 case PROCESSOR_NOCONA:
976 case PROCESSOR_CORE:
ef05d495 977 case PROCESSOR_CORE2:
40fb9820 978 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 979 patt = alt_long_patt;
980 else
981 patt = f32_patt;
982 break;
983 case PROCESSOR_GENERIC64:
76bc74dc 984 patt = alt_long_patt;
ccc9c027 985 break;
4eed87de 986 }
ccc9c027
L		 987 }
988
76bc74dc
L		 989 if (patt == f32_patt)
990 {
991 /* If the padding is less than 15 bytes, we use the normal
992 ones. Otherwise, we use a jump instruction and adjust
993 its offset. */
994 if (count < 15)
995 memcpy (fragP->fr_literal + fragP->fr_fix,
996 patt[count - 1], count);
997 else
998 {
999 memcpy (fragP->fr_literal + fragP->fr_fix,
1000 jump_31, count);
1001 /* Adjust jump offset. */
1002 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1003 }
1004 }
1005 else
1006 {
1007 /* Maximum length of an instruction is 15 byte. If the
1008 padding is greater than 15 bytes and we don't use jump,
1009 we have to break it into smaller pieces. */
1010 int padding = count;
1011 while (padding > 15)
1012 {
1013 padding -= 15;
1014 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1015 patt [14], 15);
1016 }
1017
1018 if (padding)
1019 memcpy (fragP->fr_literal + fragP->fr_fix,
1020 patt [padding - 1], padding);
1021 }
ccc9c027 1022 }
33fef721 1023 fragP->fr_var = count;
252b5132
RH		 1024}
1025
c6fb90c8 1026static INLINE int
0dfbf9d7 1027operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1028{
0dfbf9d7 1029 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1030 {
1031 case 3:
0dfbf9d7 1032 if (x->array[2])
c6fb90c8
L		 1033 return 0;
1034 case 2:
0dfbf9d7 1035 if (x->array[1])
c6fb90c8
L		 1036 return 0;
1037 case 1:
0dfbf9d7 1038 return !x->array[0];
c6fb90c8
L		 1039 default:
1040 abort ();
1041 }
40fb9820
L		 1042}
1043
c6fb90c8 1044static INLINE void
0dfbf9d7 1045operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1046{
0dfbf9d7 1047 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1048 {
1049 case 3:
0dfbf9d7 1050 x->array[2] = v;
c6fb90c8 1051 case 2:
0dfbf9d7 1052 x->array[1] = v;
c6fb90c8 1053 case 1:
0dfbf9d7 1054 x->array[0] = v;
c6fb90c8
L		 1055 break;
1056 default:
1057 abort ();
1058 }
1059}
40fb9820 1060
c6fb90c8 1061static INLINE int
0dfbf9d7
L		 1062operand_type_equal (const union i386_operand_type *x,
1063 const union i386_operand_type *y)
c6fb90c8 1064{
0dfbf9d7 1065 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1066 {
1067 case 3:
0dfbf9d7 1068 if (x->array[2] != y->array[2])
c6fb90c8
L		 1069 return 0;
1070 case 2:
0dfbf9d7 1071 if (x->array[1] != y->array[1])
c6fb90c8
L		 1072 return 0;
1073 case 1:
0dfbf9d7 1074 return x->array[0] == y->array[0];
c6fb90c8
L		 1075 break;
1076 default:
1077 abort ();
1078 }
1079}
40fb9820 1080
0dfbf9d7
L		 1081static INLINE int
1082cpu_flags_all_zero (const union i386_cpu_flags *x)
1083{
1084 switch (ARRAY_SIZE(x->array))
1085 {
1086 case 3:
1087 if (x->array[2])
1088 return 0;
1089 case 2:
1090 if (x->array[1])
1091 return 0;
1092 case 1:
1093 return !x->array[0];
1094 default:
1095 abort ();
1096 }
1097}
1098
1099static INLINE void
1100cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1101{
1102 switch (ARRAY_SIZE(x->array))
1103 {
1104 case 3:
1105 x->array[2] = v;
1106 case 2:
1107 x->array[1] = v;
1108 case 1:
1109 x->array[0] = v;
1110 break;
1111 default:
1112 abort ();
1113 }
1114}
1115
1116static INLINE int
1117cpu_flags_equal (const union i386_cpu_flags *x,
1118 const union i386_cpu_flags *y)
1119{
1120 switch (ARRAY_SIZE(x->array))
1121 {
1122 case 3:
1123 if (x->array[2] != y->array[2])
1124 return 0;
1125 case 2:
1126 if (x->array[1] != y->array[1])
1127 return 0;
1128 case 1:
1129 return x->array[0] == y->array[0];
1130 break;
1131 default:
1132 abort ();
1133 }
1134}
c6fb90c8
L		 1135
1136static INLINE int
1137cpu_flags_check_cpu64 (i386_cpu_flags f)
1138{
1139 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1140 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1141}
1142
c6fb90c8
L		 1143static INLINE i386_cpu_flags
1144cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1145{
c6fb90c8
L		 1146 switch (ARRAY_SIZE (x.array))
1147 {
1148 case 3:
1149 x.array [2] &= y.array [2];
1150 case 2:
1151 x.array [1] &= y.array [1];
1152 case 1:
1153 x.array [0] &= y.array [0];
1154 break;
1155 default:
1156 abort ();
1157 }
1158 return x;
1159}
40fb9820 1160
c6fb90c8
L		 1161static INLINE i386_cpu_flags
1162cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1163{
c6fb90c8 1164 switch (ARRAY_SIZE (x.array))
40fb9820 1165 {
c6fb90c8
L		 1166 case 3:
1167 x.array [2] |= y.array [2];
1168 case 2:
1169 x.array [1] |= y.array [1];
1170 case 1:
1171 x.array [0] |= y.array [0];
40fb9820
L		 1172 break;
1173 default:
1174 abort ();
1175 }
40fb9820
L		 1176 return x;
1177}
1178
3629bb00
L		 1179/* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1180 1 if compatible with arch, 0 if there is no match. */
1181
40fb9820
L		 1182static int
1183cpu_flags_match (i386_cpu_flags x)
1184{
3629bb00 1185 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
40fb9820
L		 1186
1187 x.bitfield.cpu64 = 0;
1188 x.bitfield.cpuno64 = 0;
1189
0dfbf9d7 1190 if (cpu_flags_all_zero (&x))
3629bb00
L		 1191 overlap |= 1;
1192 else
1193 {
1194 i386_cpu_flags cpu = cpu_arch_flags;
1195
1196 cpu.bitfield.cpu64 = 0;
1197 cpu.bitfield.cpuno64 = 0;
1198 cpu = cpu_flags_and (x, cpu);
0dfbf9d7 1199 overlap |= cpu_flags_all_zero (&cpu) ? 0 : 1;
3629bb00
L		 1200 }
1201 return overlap;
40fb9820
L		 1202}
1203
c6fb90c8
L		 1204static INLINE i386_operand_type
1205operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1206{
c6fb90c8
L		 1207 switch (ARRAY_SIZE (x.array))
1208 {
1209 case 3:
1210 x.array [2] &= y.array [2];
1211 case 2:
1212 x.array [1] &= y.array [1];
1213 case 1:
1214 x.array [0] &= y.array [0];
1215 break;
1216 default:
1217 abort ();
1218 }
1219 return x;
40fb9820
L		 1220}
1221
c6fb90c8
L		 1222static INLINE i386_operand_type
1223operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1224{
c6fb90c8 1225 switch (ARRAY_SIZE (x.array))
40fb9820 1226 {
c6fb90c8
L		 1227 case 3:
1228 x.array [2] |= y.array [2];
1229 case 2:
1230 x.array [1] |= y.array [1];
1231 case 1:
1232 x.array [0] |= y.array [0];
40fb9820
L		 1233 break;
1234 default:
1235 abort ();
1236 }
c6fb90c8
L		 1237 return x;
1238}
40fb9820 1239
c6fb90c8
L		 1240static INLINE i386_operand_type
1241operand_type_xor (i386_operand_type x, i386_operand_type y)
1242{
1243 switch (ARRAY_SIZE (x.array))
1244 {
1245 case 3:
1246 x.array [2] ^= y.array [2];
1247 case 2:
1248 x.array [1] ^= y.array [1];
1249 case 1:
1250 x.array [0] ^= y.array [0];
1251 break;
1252 default:
1253 abort ();
1254 }
40fb9820
L		 1255 return x;
1256}
1257
1258static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1259static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1260static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1261static const i386_operand_type inoutportreg
1262 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1263static const i386_operand_type reg16_inoutportreg
1264 = OPERAND_TYPE_REG16_INOUTPORTREG;
1265static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1266static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1267static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1268static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1269static const i386_operand_type anydisp
1270 = OPERAND_TYPE_ANYDISP;
40fb9820
L		 1271static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1272static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1273static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1274static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1275static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1276static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1277static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1278static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1279static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1280static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1281
1282enum operand_type
1283{
1284 reg,
40fb9820
L		 1285 imm,
1286 disp,
1287 anymem
1288};
1289
c6fb90c8 1290static INLINE int
40fb9820
L		 1291operand_type_check (i386_operand_type t, enum operand_type c)
1292{
1293 switch (c)
1294 {
1295 case reg:
1296 return (t.bitfield.reg8
1297 || t.bitfield.reg16
1298 || t.bitfield.reg32
1299 || t.bitfield.reg64);
1300
40fb9820
L		 1301 case imm:
1302 return (t.bitfield.imm8
1303 || t.bitfield.imm8s
1304 || t.bitfield.imm16
1305 || t.bitfield.imm32
1306 || t.bitfield.imm32s
1307 || t.bitfield.imm64);
1308
1309 case disp:
1310 return (t.bitfield.disp8
1311 || t.bitfield.disp16
1312 || t.bitfield.disp32
1313 || t.bitfield.disp32s
1314 || t.bitfield.disp64);
1315
1316 case anymem:
1317 return (t.bitfield.disp8
1318 || t.bitfield.disp16
1319 || t.bitfield.disp32
1320 || t.bitfield.disp32s
1321 || t.bitfield.disp64
1322 || t.bitfield.baseindex);
1323
1324 default:
1325 abort ();
1326 }
1327}
1328
5c07affc
L		 1329/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1330 operand J for instruction template T. */
1331
1332static INLINE int
1333match_reg_size (const template *t, unsigned int j)
1334{
1335 return !((i.types[j].bitfield.byte
1336 && !t->operand_types[j].bitfield.byte)
1337 || (i.types[j].bitfield.word
1338 && !t->operand_types[j].bitfield.word)
1339 || (i.types[j].bitfield.dword
1340 && !t->operand_types[j].bitfield.dword)
1341 || (i.types[j].bitfield.qword
1342 && !t->operand_types[j].bitfield.qword));
1343}
1344
1345/* Return 1 if there is no conflict in any size on operand J for
1346 instruction template T. */
1347
1348static INLINE int
1349match_mem_size (const template *t, unsigned int j)
1350{
1351 return (match_reg_size (t, j)
1352 && !((i.types[j].bitfield.unspecified
1353 && !t->operand_types[j].bitfield.unspecified)
1354 || (i.types[j].bitfield.fword
1355 && !t->operand_types[j].bitfield.fword)
1356 || (i.types[j].bitfield.tbyte
1357 && !t->operand_types[j].bitfield.tbyte)
1358 || (i.types[j].bitfield.xmmword
1359 && !t->operand_types[j].bitfield.xmmword)));
1360}
1361
1362/* Return 1 if there is no size conflict on any operands for
1363 instruction template T. */
1364
1365static INLINE int
1366operand_size_match (const template *t)
1367{
1368 unsigned int j;
1369 int match = 1;
1370
1371 /* Don't check jump instructions. */
1372 if (t->opcode_modifier.jump
1373 || t->opcode_modifier.jumpbyte
1374 || t->opcode_modifier.jumpdword
1375 || t->opcode_modifier.jumpintersegment)
1376 return match;
1377
1378 /* Check memory and accumulator operand size. */
1379 for (j = 0; j < i.operands; j++)
1380 {
1381 if (t->operand_types[j].bitfield.anysize)
1382 continue;
1383
1384 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1385 {
1386 match = 0;
1387 break;
1388 }
1389
1390 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1391 {
1392 match = 0;
1393 break;
1394 }
1395 }
1396
1397 if (match
1398 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1399 return match;
1400
1401 /* Check reverse. */
1402 assert (i.operands == 2);
1403
1404 match = 1;
1405 for (j = 0; j < 2; j++)
1406 {
1407 if (t->operand_types[j].bitfield.acc
1408 && !match_reg_size (t, j ? 0 : 1))
1409 {
1410 match = 0;
1411 break;
1412 }
1413
1414 if (i.types[j].bitfield.mem
1415 && !match_mem_size (t, j ? 0 : 1))
1416 {
1417 match = 0;
1418 break;
1419 }
1420 }
1421
1422 return match;
1423}
1424
c6fb90c8 1425static INLINE int
40fb9820
L		 1426operand_type_match (i386_operand_type overlap,
1427 i386_operand_type given)
1428{
1429 i386_operand_type temp = overlap;
1430
1431 temp.bitfield.jumpabsolute = 0;
7d5e4556 1432 temp.bitfield.unspecified = 0;
5c07affc
L		 1433 temp.bitfield.byte = 0;
1434 temp.bitfield.word = 0;
1435 temp.bitfield.dword = 0;
1436 temp.bitfield.fword = 0;
1437 temp.bitfield.qword = 0;
1438 temp.bitfield.tbyte = 0;
1439 temp.bitfield.xmmword = 0;
0dfbf9d7 1440 if (operand_type_all_zero (&temp))
40fb9820
L		 1441 return 0;
1442
1443 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1444 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1445}
1446
7d5e4556 1447/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1448 unless the expected operand type register overlap is null.
1449 Note that Acc in a template matches every size of reg. */
1450
c6fb90c8 1451static INLINE int
40fb9820
L		 1452operand_type_register_match (i386_operand_type m0,
1453 i386_operand_type g0,
1454 i386_operand_type t0,
1455 i386_operand_type m1,
1456 i386_operand_type g1,
1457 i386_operand_type t1)
1458{
1459 if (!operand_type_check (g0, reg))
1460 return 1;
1461
1462 if (!operand_type_check (g1, reg))
1463 return 1;
1464
1465 if (g0.bitfield.reg8 == g1.bitfield.reg8
1466 && g0.bitfield.reg16 == g1.bitfield.reg16
1467 && g0.bitfield.reg32 == g1.bitfield.reg32
1468 && g0.bitfield.reg64 == g1.bitfield.reg64)
1469 return 1;
1470
1471 if (m0.bitfield.acc)
1472 {
1473 t0.bitfield.reg8 = 1;
1474 t0.bitfield.reg16 = 1;
1475 t0.bitfield.reg32 = 1;
1476 t0.bitfield.reg64 = 1;
1477 }
1478
1479 if (m1.bitfield.acc)
1480 {
1481 t1.bitfield.reg8 = 1;
1482 t1.bitfield.reg16 = 1;
1483 t1.bitfield.reg32 = 1;
1484 t1.bitfield.reg64 = 1;
1485 }
1486
1487 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1488 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1489 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1490 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1491}
1492
252b5132 1493static INLINE unsigned int
40fb9820 1494mode_from_disp_size (i386_operand_type t)
252b5132 1495{
40fb9820
L		 1496 if (t.bitfield.disp8)
1497 return 1;
1498 else if (t.bitfield.disp16
1499 || t.bitfield.disp32
1500 || t.bitfield.disp32s)
1501 return 2;
1502 else
1503 return 0;
252b5132
RH		 1504}
1505
1506static INLINE int
e3bb37b5 1507fits_in_signed_byte (offsetT num)
252b5132
RH		 1508{
1509 return (num >= -128) && (num <= 127);
47926f60 1510}
252b5132
RH		 1511
1512static INLINE int
e3bb37b5 1513fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1514{
1515 return (num & 0xff) == num;
47926f60 1516}
252b5132
RH		 1517
1518static INLINE int
e3bb37b5 1519fits_in_unsigned_word (offsetT num)
252b5132
RH		 1520{
1521 return (num & 0xffff) == num;
47926f60 1522}
252b5132
RH		 1523
1524static INLINE int
e3bb37b5 1525fits_in_signed_word (offsetT num)
252b5132
RH		 1526{
1527 return (-32768 <= num) && (num <= 32767);
47926f60 1528}
2a962e6d 1529
3e73aa7c 1530static INLINE int
e3bb37b5 1531fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1532{
1533#ifndef BFD64
1534 return 1;
1535#else
1536 return (!(((offsetT) -1 << 31) & num)
1537 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1538#endif
1539} /* fits_in_signed_long() */
2a962e6d 1540
3e73aa7c 1541static INLINE int
e3bb37b5 1542fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1543{
1544#ifndef BFD64
1545 return 1;
1546#else
1547 return (num & (((offsetT) 2 << 31) - 1)) == num;
1548#endif
1549} /* fits_in_unsigned_long() */
252b5132 1550
40fb9820 1551static i386_operand_type
e3bb37b5 1552smallest_imm_type (offsetT num)
252b5132 1553{
40fb9820
L		 1554 i386_operand_type t;
1555
0dfbf9d7 1556 operand_type_set (&t, 0);
40fb9820
L		 1557 t.bitfield.imm64 = 1;
1558
1559 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1560 {
1561 /* This code is disabled on the 486 because all the Imm1 forms
1562 in the opcode table are slower on the i486. They're the
1563 versions with the implicitly specified single-position
1564 displacement, which has another syntax if you really want to
1565 use that form. */
40fb9820
L		 1566 t.bitfield.imm1 = 1;
1567 t.bitfield.imm8 = 1;
1568 t.bitfield.imm8s = 1;
1569 t.bitfield.imm16 = 1;
1570 t.bitfield.imm32 = 1;
1571 t.bitfield.imm32s = 1;
1572 }
1573 else if (fits_in_signed_byte (num))
1574 {
1575 t.bitfield.imm8 = 1;
1576 t.bitfield.imm8s = 1;
1577 t.bitfield.imm16 = 1;
1578 t.bitfield.imm32 = 1;
1579 t.bitfield.imm32s = 1;
1580 }
1581 else if (fits_in_unsigned_byte (num))
1582 {
1583 t.bitfield.imm8 = 1;
1584 t.bitfield.imm16 = 1;
1585 t.bitfield.imm32 = 1;
1586 t.bitfield.imm32s = 1;
1587 }
1588 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1589 {
1590 t.bitfield.imm16 = 1;
1591 t.bitfield.imm32 = 1;
1592 t.bitfield.imm32s = 1;
1593 }
1594 else if (fits_in_signed_long (num))
1595 {
1596 t.bitfield.imm32 = 1;
1597 t.bitfield.imm32s = 1;
1598 }
1599 else if (fits_in_unsigned_long (num))
1600 t.bitfield.imm32 = 1;
1601
1602 return t;
47926f60 1603}
252b5132 1604
847f7ad4 1605static offsetT
e3bb37b5 1606offset_in_range (offsetT val, int size)
847f7ad4 1607{
508866be 1608 addressT mask;
ba2adb93 1609
847f7ad4
AM		 1610 switch (size)
1611 {
508866be
L		 1612 case 1: mask = ((addressT) 1 << 8) - 1; break;
1613 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1614 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1615#ifdef BFD64
1616 case 8: mask = ((addressT) 2 << 63) - 1; break;
1617#endif
47926f60 1618 default: abort ();
847f7ad4
AM		 1619 }
1620
ba2adb93 1621 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1622 if (!use_rela_relocations)
1623 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1624 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1625
47926f60 1626 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1627 {
1628 char buf1[40], buf2[40];
1629
1630 sprint_value (buf1, val);
1631 sprint_value (buf2, val & mask);
1632 as_warn (_("%s shortened to %s"), buf1, buf2);
1633 }
1634 return val & mask;
1635}
1636
252b5132
RH		 1637/* Returns 0 if attempting to add a prefix where one from the same
1638 class already exists, 1 if non rep/repne added, 2 if rep/repne
1639 added. */
1640static int
e3bb37b5 1641add_prefix (unsigned int prefix)
252b5132
RH		 1642{
1643 int ret = 1;
b1905489 1644 unsigned int q;
252b5132 1645
29b0f896
AM		 1646 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1647 && flag_code == CODE_64BIT)
b1905489 1648 {
161a04f6
L		 1649 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1650 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1651 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1652 ret = 0;
1653 q = REX_PREFIX;
1654 }
3e73aa7c 1655 else
b1905489
JB		 1656 {
1657 switch (prefix)
1658 {
1659 default:
1660 abort ();
1661
1662 case CS_PREFIX_OPCODE:
1663 case DS_PREFIX_OPCODE:
1664 case ES_PREFIX_OPCODE:
1665 case FS_PREFIX_OPCODE:
1666 case GS_PREFIX_OPCODE:
1667 case SS_PREFIX_OPCODE:
1668 q = SEG_PREFIX;
1669 break;
1670
1671 case REPNE_PREFIX_OPCODE:
1672 case REPE_PREFIX_OPCODE:
1673 ret = 2;
1674 /* fall thru */
1675 case LOCK_PREFIX_OPCODE:
1676 q = LOCKREP_PREFIX;
1677 break;
1678
1679 case FWAIT_OPCODE:
1680 q = WAIT_PREFIX;
1681 break;
1682
1683 case ADDR_PREFIX_OPCODE:
1684 q = ADDR_PREFIX;
1685 break;
1686
1687 case DATA_PREFIX_OPCODE:
1688 q = DATA_PREFIX;
1689 break;
1690 }
1691 if (i.prefix[q] != 0)
1692 ret = 0;
1693 }
252b5132 1694
b1905489 1695 if (ret)
252b5132 1696 {
b1905489
JB		 1697 if (!i.prefix[q])
1698 ++i.prefixes;
1699 i.prefix[q] |= prefix;
252b5132 1700 }
b1905489
JB		 1701 else
1702 as_bad (_("same type of prefix used twice"));
252b5132 1703
252b5132
RH		 1704 return ret;
1705}
1706
1707static void
e3bb37b5 1708set_code_flag (int value)
eecb386c 1709{
3e73aa7c 1710 flag_code = value;
40fb9820
L		 1711 if (flag_code == CODE_64BIT)
1712 {
1713 cpu_arch_flags.bitfield.cpu64 = 1;
1714 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1715 }
1716 else
1717 {
1718 cpu_arch_flags.bitfield.cpu64 = 0;
1719 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1720 }
1721 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1722 {
1723 as_bad (_("64bit mode not supported on this CPU."));
1724 }
40fb9820 1725 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1726 {
1727 as_bad (_("32bit mode not supported on this CPU."));
1728 }
eecb386c
AM		 1729 stackop_size = '\0';
1730}
1731
1732static void
e3bb37b5 1733set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1734{
3e73aa7c 1735 flag_code = new_code_flag;
40fb9820
L		 1736 if (flag_code != CODE_16BIT)
1737 abort ();
1738 cpu_arch_flags.bitfield.cpu64 = 0;
1739 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1740 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1741}
1742
1743static void
e3bb37b5 1744set_intel_syntax (int syntax_flag)
252b5132
RH		 1745{
1746 /* Find out if register prefixing is specified. */
1747 int ask_naked_reg = 0;
1748
1749 SKIP_WHITESPACE ();
29b0f896 1750 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1751 {
1752 char *string = input_line_pointer;
1753 int e = get_symbol_end ();
1754
47926f60 1755 if (strcmp (string, "prefix") == 0)
252b5132 1756 ask_naked_reg = 1;
47926f60 1757 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1758 ask_naked_reg = -1;
1759 else
d0b47220 1760 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1761 *input_line_pointer = e;
1762 }
1763 demand_empty_rest_of_line ();
c3332e24 1764
252b5132
RH		 1765 intel_syntax = syntax_flag;
1766
1767 if (ask_naked_reg == 0)
f86103b7
AM		 1768 allow_naked_reg = (intel_syntax
1769 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1770 else
1771 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1772
e4a3b5a4 1773 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1774 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1775 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1776}
1777
1efbbeb4
L		 1778static void
1779set_intel_mnemonic (int mnemonic_flag)
1780{
e1d4d893 1781 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1782}
1783
db51cc60
L		 1784static void
1785set_allow_index_reg (int flag)
1786{
1787 allow_index_reg = flag;
1788}
1789
e413e4e9 1790static void
e3bb37b5 1791set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1792{
47926f60 1793 SKIP_WHITESPACE ();
e413e4e9 1794
29b0f896 1795 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1796 {
1797 char *string = input_line_pointer;
1798 int e = get_symbol_end ();
9103f4f4 1799 unsigned int i;
40fb9820 1800 i386_cpu_flags flags;
e413e4e9 1801
9103f4f4 1802 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1803 {
1804 if (strcmp (string, cpu_arch[i].name) == 0)
1805 {
5c6af06e
JB		 1806 if (*string != '.')
1807 {
1808 cpu_arch_name = cpu_arch[i].name;
1809 cpu_sub_arch_name = NULL;
40fb9820
L		 1810 cpu_arch_flags = cpu_arch[i].flags;
1811 if (flag_code == CODE_64BIT)
1812 {
1813 cpu_arch_flags.bitfield.cpu64 = 1;
1814 cpu_arch_flags.bitfield.cpuno64 = 0;
1815 }
1816 else
1817 {
1818 cpu_arch_flags.bitfield.cpu64 = 0;
1819 cpu_arch_flags.bitfield.cpuno64 = 1;
1820 }
ccc9c027 1821 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1822 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1823 if (!cpu_arch_tune_set)
1824 {
1825 cpu_arch_tune = cpu_arch_isa;
1826 cpu_arch_tune_flags = cpu_arch_isa_flags;
1827 }
5c6af06e
JB		 1828 break;
1829 }
40fb9820 1830
c6fb90c8
L		 1831 flags = cpu_flags_or (cpu_arch_flags,
1832 cpu_arch[i].flags);
0dfbf9d7 1833 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 1834 {
6305a203
L		 1835 if (cpu_sub_arch_name)
1836 {
1837 char *name = cpu_sub_arch_name;
1838 cpu_sub_arch_name = concat (name,
1839 cpu_arch[i].name,
1bf57e9f 1840 (const char *) NULL);
6305a203
L		 1841 free (name);
1842 }
1843 else
1844 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 1845 cpu_arch_flags = flags;
5c6af06e
JB		 1846 }
1847 *input_line_pointer = e;
1848 demand_empty_rest_of_line ();
1849 return;
e413e4e9
AM		 1850 }
1851 }
9103f4f4 1852 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1853 as_bad (_("no such architecture: `%s'"), string);
1854
1855 *input_line_pointer = e;
1856 }
1857 else
1858 as_bad (_("missing cpu architecture"));
1859
fddf5b5b
AM		 1860 no_cond_jump_promotion = 0;
1861 if (*input_line_pointer == ','
29b0f896 1862 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1863 {
1864 char *string = ++input_line_pointer;
1865 int e = get_symbol_end ();
1866
1867 if (strcmp (string, "nojumps") == 0)
1868 no_cond_jump_promotion = 1;
1869 else if (strcmp (string, "jumps") == 0)
1870 ;
1871 else
1872 as_bad (_("no such architecture modifier: `%s'"), string);
1873
1874 *input_line_pointer = e;
1875 }
1876
e413e4e9
AM		 1877 demand_empty_rest_of_line ();
1878}
1879
b9d79e03
JH		 1880unsigned long
1881i386_mach ()
1882{
1883 if (!strcmp (default_arch, "x86_64"))
1884 return bfd_mach_x86_64;
1885 else if (!strcmp (default_arch, "i386"))
1886 return bfd_mach_i386_i386;
1887 else
1888 as_fatal (_("Unknown architecture"));
1889}
b9d79e03 1890\f
252b5132
RH		 1891void
1892md_begin ()
1893{
1894 const char *hash_err;
1895
47926f60 1896 /* Initialize op_hash hash table. */
252b5132
RH		 1897 op_hash = hash_new ();
1898
1899 {
29b0f896
AM		 1900 const template *optab;
1901 templates *core_optab;
252b5132 1902
47926f60
KH		 1903 /* Setup for loop. */
1904 optab = i386_optab;
252b5132
RH		 1905 core_optab = (templates *) xmalloc (sizeof (templates));
1906 core_optab->start = optab;
1907
1908 while (1)
1909 {
1910 ++optab;
1911 if (optab->name == NULL
1912 || strcmp (optab->name, (optab - 1)->name) != 0)
1913 {
1914 /* different name --> ship out current template list;
47926f60 1915 add to hash table; & begin anew. */
252b5132
RH		 1916 core_optab->end = optab;
1917 hash_err = hash_insert (op_hash,
1918 (optab - 1)->name,
1919 (PTR) core_optab);
1920 if (hash_err)
1921 {
252b5132
RH		 1922 as_fatal (_("Internal Error: Can't hash %s: %s"),
1923 (optab - 1)->name,
1924 hash_err);
1925 }
1926 if (optab->name == NULL)
1927 break;
1928 core_optab = (templates *) xmalloc (sizeof (templates));
1929 core_optab->start = optab;
1930 }
1931 }
1932 }
1933
47926f60 1934 /* Initialize reg_hash hash table. */
252b5132
RH		 1935 reg_hash = hash_new ();
1936 {
29b0f896 1937 const reg_entry *regtab;
c3fe08fa 1938 unsigned int regtab_size = i386_regtab_size;
252b5132 1939
c3fe08fa 1940 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1941 {
1942 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1943 if (hash_err)
3e73aa7c
JH		 1944 as_fatal (_("Internal Error: Can't hash %s: %s"),
1945 regtab->reg_name,
1946 hash_err);
252b5132
RH		 1947 }
1948 }
1949
47926f60 1950 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1951 {
29b0f896
AM		 1952 int c;
1953 char *p;
252b5132
RH		 1954
1955 for (c = 0; c < 256; c++)
1956 {
3882b010 1957 if (ISDIGIT (c))
252b5132
RH		 1958 {
1959 digit_chars[c] = c;
1960 mnemonic_chars[c] = c;
1961 register_chars[c] = c;
1962 operand_chars[c] = c;
1963 }
3882b010 1964 else if (ISLOWER (c))
252b5132
RH		 1965 {
1966 mnemonic_chars[c] = c;
1967 register_chars[c] = c;
1968 operand_chars[c] = c;
1969 }
3882b010 1970 else if (ISUPPER (c))
252b5132 1971 {
3882b010 1972 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1973 register_chars[c] = mnemonic_chars[c];
1974 operand_chars[c] = c;
1975 }
1976
3882b010 1977 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1978 identifier_chars[c] = c;
1979 else if (c >= 128)
1980 {
1981 identifier_chars[c] = c;
1982 operand_chars[c] = c;
1983 }
1984 }
1985
1986#ifdef LEX_AT
1987 identifier_chars['@'] = '@';
32137342
NC		 1988#endif
1989#ifdef LEX_QM
1990 identifier_chars['?'] = '?';
1991 operand_chars['?'] = '?';
252b5132 1992#endif
252b5132 1993 digit_chars['-'] = '-';
791fe849 1994 mnemonic_chars['-'] = '-';
0003779b 1995 mnemonic_chars['.'] = '.';
252b5132
RH		 1996 identifier_chars['_'] = '_';
1997 identifier_chars['.'] = '.';
1998
1999 for (p = operand_special_chars; *p != '\0'; p++)
2000 operand_chars[(unsigned char) *p] = *p;
2001 }
2002
2003#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2004 if (IS_ELF)
252b5132
RH		 2005 {
2006 record_alignment (text_section, 2);
2007 record_alignment (data_section, 2);
2008 record_alignment (bss_section, 2);
2009 }
2010#endif
a4447b93
RH		 2011
2012 if (flag_code == CODE_64BIT)
2013 {
2014 x86_dwarf2_return_column = 16;
2015 x86_cie_data_alignment = -8;
2016 }
2017 else
2018 {
2019 x86_dwarf2_return_column = 8;
2020 x86_cie_data_alignment = -4;
2021 }
252b5132
RH		 2022}
2023
2024void
e3bb37b5 2025i386_print_statistics (FILE *file)
252b5132
RH		 2026{
2027 hash_print_statistics (file, "i386 opcode", op_hash);
2028 hash_print_statistics (file, "i386 register", reg_hash);
2029}
2030\f
252b5132
RH		 2031#ifdef DEBUG386
2032
ce8a8b2f 2033/* Debugging routines for md_assemble. */
e3bb37b5 2034static void pte (template *);
40fb9820 2035static void pt (i386_operand_type);
e3bb37b5
L		 2036static void pe (expressionS *);
2037static void ps (symbolS *);
252b5132
RH		 2038
2039static void
e3bb37b5 2040pi (char *line, i386_insn *x)
252b5132 2041{
09f131f2 2042 unsigned int i;
252b5132
RH		 2043
2044 fprintf (stdout, "%s: template ", line);
2045 pte (&x->tm);
09f131f2
JH		 2046 fprintf (stdout, " address: base %s index %s scale %x\n",
2047 x->base_reg ? x->base_reg->reg_name : "none",
2048 x->index_reg ? x->index_reg->reg_name : "none",
2049 x->log2_scale_factor);
2050 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2051 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2052 fprintf (stdout, " sib: base %x index %x scale %x\n",
2053 x->sib.base, x->sib.index, x->sib.scale);
2054 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2055 (x->rex & REX_W) != 0,
2056 (x->rex & REX_R) != 0,
2057 (x->rex & REX_X) != 0,
2058 (x->rex & REX_B) != 0);
85f10a01
MM		 2059 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2060 x->drex.reg, x->drex.rex);
252b5132
RH		 2061 for (i = 0; i < x->operands; i++)
2062 {
2063 fprintf (stdout, " #%d: ", i + 1);
2064 pt (x->types[i]);
2065 fprintf (stdout, "\n");
40fb9820
L		 2066 if (x->types[i].bitfield.reg8
2067 || x->types[i].bitfield.reg16
2068 || x->types[i].bitfield.reg32
2069 || x->types[i].bitfield.reg64
2070 || x->types[i].bitfield.regmmx
2071 || x->types[i].bitfield.regxmm
2072 || x->types[i].bitfield.sreg2
2073 || x->types[i].bitfield.sreg3
2074 || x->types[i].bitfield.control
2075 || x->types[i].bitfield.debug
2076 || x->types[i].bitfield.test)
520dc8e8 2077 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2078 if (operand_type_check (x->types[i], imm))
520dc8e8 2079 pe (x->op[i].imms);
40fb9820 2080 if (operand_type_check (x->types[i], disp))
520dc8e8 2081 pe (x->op[i].disps);
252b5132
RH		 2082 }
2083}
2084
2085static void
e3bb37b5 2086pte (template *t)
252b5132 2087{
09f131f2 2088 unsigned int i;
252b5132 2089 fprintf (stdout, " %d operands ", t->operands);
47926f60 2090 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2091 if (t->extension_opcode != None)
2092 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2093 if (t->opcode_modifier.d)
252b5132 2094 fprintf (stdout, "D");
40fb9820 2095 if (t->opcode_modifier.w)
252b5132
RH		 2096 fprintf (stdout, "W");
2097 fprintf (stdout, "\n");
2098 for (i = 0; i < t->operands; i++)
2099 {
2100 fprintf (stdout, " #%d type ", i + 1);
2101 pt (t->operand_types[i]);
2102 fprintf (stdout, "\n");
2103 }
2104}
2105
2106static void
e3bb37b5 2107pe (expressionS *e)
252b5132 2108{
24eab124 2109 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2110 fprintf (stdout, " add_number %ld (%lx)\n",
2111 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2112 if (e->X_add_symbol)
2113 {
2114 fprintf (stdout, " add_symbol ");
2115 ps (e->X_add_symbol);
2116 fprintf (stdout, "\n");
2117 }
2118 if (e->X_op_symbol)
2119 {
2120 fprintf (stdout, " op_symbol ");
2121 ps (e->X_op_symbol);
2122 fprintf (stdout, "\n");
2123 }
2124}
2125
2126static void
e3bb37b5 2127ps (symbolS *s)
252b5132
RH		 2128{
2129 fprintf (stdout, "%s type %s%s",
2130 S_GET_NAME (s),
2131 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2132 segment_name (S_GET_SEGMENT (s)));
2133}
2134
7b81dfbb 2135static struct type_name
252b5132 2136 {
40fb9820
L		 2137 i386_operand_type mask;
2138 const char *name;
252b5132 2139 }
7b81dfbb 2140const type_names[] =
252b5132 2141{
40fb9820
L		 2142 { OPERAND_TYPE_REG8, "r8" },
2143 { OPERAND_TYPE_REG16, "r16" },
2144 { OPERAND_TYPE_REG32, "r32" },
2145 { OPERAND_TYPE_REG64, "r64" },
2146 { OPERAND_TYPE_IMM8, "i8" },
2147 { OPERAND_TYPE_IMM8, "i8s" },
2148 { OPERAND_TYPE_IMM16, "i16" },
2149 { OPERAND_TYPE_IMM32, "i32" },
2150 { OPERAND_TYPE_IMM32S, "i32s" },
2151 { OPERAND_TYPE_IMM64, "i64" },
2152 { OPERAND_TYPE_IMM1, "i1" },
2153 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2154 { OPERAND_TYPE_DISP8, "d8" },
2155 { OPERAND_TYPE_DISP16, "d16" },
2156 { OPERAND_TYPE_DISP32, "d32" },
2157 { OPERAND_TYPE_DISP32S, "d32s" },
2158 { OPERAND_TYPE_DISP64, "d64" },
2159 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2160 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2161 { OPERAND_TYPE_CONTROL, "control reg" },
2162 { OPERAND_TYPE_TEST, "test reg" },
2163 { OPERAND_TYPE_DEBUG, "debug reg" },
2164 { OPERAND_TYPE_FLOATREG, "FReg" },
2165 { OPERAND_TYPE_FLOATACC, "FAcc" },
2166 { OPERAND_TYPE_SREG2, "SReg2" },
2167 { OPERAND_TYPE_SREG3, "SReg3" },
2168 { OPERAND_TYPE_ACC, "Acc" },
2169 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2170 { OPERAND_TYPE_REGMMX, "rMMX" },
2171 { OPERAND_TYPE_REGXMM, "rXMM" },
2172 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2173};
2174
2175static void
40fb9820 2176pt (i386_operand_type t)
252b5132 2177{
40fb9820 2178 unsigned int j;
c6fb90c8 2179 i386_operand_type a;
252b5132 2180
40fb9820 2181 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2182 {
2183 a = operand_type_and (t, type_names[j].mask);
2184 if (!UINTS_ALL_ZERO (a))
2185 fprintf (stdout, "%s, ", type_names[j].name);
2186 }
252b5132
RH		 2187 fflush (stdout);
2188}
2189
2190#endif /* DEBUG386 */
2191\f
252b5132 2192static bfd_reloc_code_real_type
3956db08 2193reloc (unsigned int size,
64e74474
AM		 2194 int pcrel,
2195 int sign,
2196 bfd_reloc_code_real_type other)
252b5132 2197{
47926f60 2198 if (other != NO_RELOC)
3956db08
JB		 2199 {
2200 reloc_howto_type *reloc;
2201
2202 if (size == 8)
2203 switch (other)
2204 {
64e74474
AM		 2205 case BFD_RELOC_X86_64_GOT32:
2206 return BFD_RELOC_X86_64_GOT64;
2207 break;
2208 case BFD_RELOC_X86_64_PLTOFF64:
2209 return BFD_RELOC_X86_64_PLTOFF64;
2210 break;
2211 case BFD_RELOC_X86_64_GOTPC32:
2212 other = BFD_RELOC_X86_64_GOTPC64;
2213 break;
2214 case BFD_RELOC_X86_64_GOTPCREL:
2215 other = BFD_RELOC_X86_64_GOTPCREL64;
2216 break;
2217 case BFD_RELOC_X86_64_TPOFF32:
2218 other = BFD_RELOC_X86_64_TPOFF64;
2219 break;
2220 case BFD_RELOC_X86_64_DTPOFF32:
2221 other = BFD_RELOC_X86_64_DTPOFF64;
2222 break;
2223 default:
2224 break;
3956db08 2225 }
e05278af
JB		 2226
2227 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2228 if (size == 4 && flag_code != CODE_64BIT)
2229 sign = -1;
2230
3956db08
JB		 2231 reloc = bfd_reloc_type_lookup (stdoutput, other);
2232 if (!reloc)
2233 as_bad (_("unknown relocation (%u)"), other);
2234 else if (size != bfd_get_reloc_size (reloc))
2235 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2236 bfd_get_reloc_size (reloc),
2237 size);
2238 else if (pcrel && !reloc->pc_relative)
2239 as_bad (_("non-pc-relative relocation for pc-relative field"));
2240 else if ((reloc->complain_on_overflow == complain_overflow_signed
2241 && !sign)
2242 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2243 && sign > 0))
3956db08
JB		 2244 as_bad (_("relocated field and relocation type differ in signedness"));
2245 else
2246 return other;
2247 return NO_RELOC;
2248 }
252b5132
RH		 2249
2250 if (pcrel)
2251 {
3e73aa7c 2252 if (!sign)
3956db08 2253 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2254 switch (size)
2255 {
2256 case 1: return BFD_RELOC_8_PCREL;
2257 case 2: return BFD_RELOC_16_PCREL;
2258 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2259 case 8: return BFD_RELOC_64_PCREL;
252b5132 2260 }
3956db08 2261 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2262 }
2263 else
2264 {
3956db08 2265 if (sign > 0)
e5cb08ac 2266 switch (size)
3e73aa7c
JH		 2267 {
2268 case 4: return BFD_RELOC_X86_64_32S;
2269 }
2270 else
2271 switch (size)
2272 {
2273 case 1: return BFD_RELOC_8;
2274 case 2: return BFD_RELOC_16;
2275 case 4: return BFD_RELOC_32;
2276 case 8: return BFD_RELOC_64;
2277 }
3956db08
JB		 2278 as_bad (_("cannot do %s %u byte relocation"),
2279 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2280 }
2281
bfb32b52 2282 abort ();
252b5132
RH		 2283 return BFD_RELOC_NONE;
2284}
2285
47926f60
KH		 2286/* Here we decide which fixups can be adjusted to make them relative to
2287 the beginning of the section instead of the symbol. Basically we need
2288 to make sure that the dynamic relocations are done correctly, so in
2289 some cases we force the original symbol to be used. */
2290
252b5132 2291int
e3bb37b5 2292tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2293{
6d249963 2294#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2295 if (!IS_ELF)
31312f95
AM		 2296 return 1;
2297
a161fe53
AM		 2298 /* Don't adjust pc-relative references to merge sections in 64-bit
2299 mode. */
2300 if (use_rela_relocations
2301 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2302 && fixP->fx_pcrel)
252b5132 2303 return 0;
31312f95 2304
8d01d9a9
AJ		 2305 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2306 and changed later by validate_fix. */
2307 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2308 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2309 return 0;
2310
ce8a8b2f 2311 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2312 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2313 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2314 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2315 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2316 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2317 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2318 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2319 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2320 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2321 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2322 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2323 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2324 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2325 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2326 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2327 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2328 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2329 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2330 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2331 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2332 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2333 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2334 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2335 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2336 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2337 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2338 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2339 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2340 return 0;
31312f95 2341#endif
252b5132
RH		 2342 return 1;
2343}
252b5132 2344
b4cac588 2345static int
e3bb37b5 2346intel_float_operand (const char *mnemonic)
252b5132 2347{
9306ca4a
JB		 2348 /* Note that the value returned is meaningful only for opcodes with (memory)
2349 operands, hence the code here is free to improperly handle opcodes that
2350 have no operands (for better performance and smaller code). */
2351
2352 if (mnemonic[0] != 'f')
2353 return 0; /* non-math */
2354
2355 switch (mnemonic[1])
2356 {
2357 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2358 the fs segment override prefix not currently handled because no
2359 call path can make opcodes without operands get here */
2360 case 'i':
2361 return 2 /* integer op */;
2362 case 'l':
2363 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2364 return 3; /* fldcw/fldenv */
2365 break;
2366 case 'n':
2367 if (mnemonic[2] != 'o' /* fnop */)
2368 return 3; /* non-waiting control op */
2369 break;
2370 case 'r':
2371 if (mnemonic[2] == 's')
2372 return 3; /* frstor/frstpm */
2373 break;
2374 case 's':
2375 if (mnemonic[2] == 'a')
2376 return 3; /* fsave */
2377 if (mnemonic[2] == 't')
2378 {
2379 switch (mnemonic[3])
2380 {
2381 case 'c': /* fstcw */
2382 case 'd': /* fstdw */
2383 case 'e': /* fstenv */
2384 case 's': /* fsts[gw] */
2385 return 3;
2386 }
2387 }
2388 break;
2389 case 'x':
2390 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2391 return 0; /* fxsave/fxrstor are not really math ops */
2392 break;
2393 }
252b5132 2394
9306ca4a 2395 return 1;
252b5132
RH		 2396}
2397
65da13b5
L		 2398static void
2399process_immext (void)
2400{
2401 expressionS *exp;
2402
2403 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2404 {
1fed0ba1
L		 2405 /* SSE3 Instructions have the fixed operands with an opcode
2406 suffix which is coded in the same place as an 8-bit immediate
2407 field would be. Here we check those operands and remove them
2408 afterwards. */
65da13b5
L		 2409 unsigned int x;
2410
2411 for (x = 0; x < i.operands; x++)
2412 if (i.op[x].regs->reg_num != x)
2413 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2414 register_prefix, i.op[x].regs->reg_name, x + 1,
2415 i.tm.name);
2416
2417 i.operands = 0;
65da13b5
L		 2418 }
2419
2420 /* These AMD 3DNow! and SSE2 Instructions have an opcode suffix
2421 which is coded in the same place as an 8-bit immediate field
2422 would be. Here we fake an 8-bit immediate operand from the
2423 opcode suffix stored in tm.extension_opcode.
2424
2425 SSE5 also uses this encoding, for some of its 3 argument
2426 instructions. */
2427
2428 assert (i.imm_operands == 0
2429 && (i.operands <= 2
2430 || (i.tm.cpu_flags.bitfield.cpusse5
2431 && i.operands <= 3)));
2432
2433 exp = &im_expressions[i.imm_operands++];
2434 i.op[i.operands].imms = exp;
2435 i.types[i.operands] = imm8;
2436 i.operands++;
2437 exp->X_op = O_constant;
2438 exp->X_add_number = i.tm.extension_opcode;
2439 i.tm.extension_opcode = None;
2440}
2441
252b5132
RH		 2442/* This is the guts of the machine-dependent assembler. LINE points to a
2443 machine dependent instruction. This function is supposed to emit
2444 the frags/bytes it assembles to. */
2445
2446void
65da13b5 2447md_assemble (char *line)
252b5132 2448{
40fb9820 2449 unsigned int j;
252b5132
RH		 2450 char mnemonic[MAX_MNEM_SIZE];
2451
47926f60 2452 /* Initialize globals. */
252b5132
RH		 2453 memset (&i, '\0', sizeof (i));
2454 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2455 i.reloc[j] = NO_RELOC;
252b5132
RH		 2456 memset (disp_expressions, '\0', sizeof (disp_expressions));
2457 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2458 save_stack_p = save_stack;
252b5132
RH		 2459
2460 /* First parse an instruction mnemonic & call i386_operand for the operands.
2461 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2462 start of a (possibly prefixed) mnemonic. */
252b5132 2463
29b0f896
AM		 2464 line = parse_insn (line, mnemonic);
2465 if (line == NULL)
2466 return;
252b5132 2467
29b0f896
AM		 2468 line = parse_operands (line, mnemonic);
2469 if (line == NULL)
2470 return;
252b5132 2471
29b0f896
AM		 2472 /* Now we've parsed the mnemonic into a set of templates, and have the
2473 operands at hand. */
2474
2475 /* All intel opcodes have reversed operands except for "bound" and
2476 "enter". We also don't reverse intersegment "jmp" and "call"
2477 instructions with 2 immediate operands so that the immediate segment
050dfa73 2478 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2479 if (intel_syntax
2480 && i.operands > 1
29b0f896 2481 && (strcmp (mnemonic, "bound") != 0)
30123838 2482 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2483 && !(operand_type_check (i.types[0], imm)
2484 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2485 swap_operands ();
2486
ec56d5c0
JB		 2487 /* The order of the immediates should be reversed
2488 for 2 immediates extrq and insertq instructions */
2489 if (i.imm_operands == 2
2490 && (strcmp (mnemonic, "extrq") == 0
2491 || strcmp (mnemonic, "insertq") == 0))
2492 swap_2_operands (0, 1);
2493
29b0f896
AM		 2494 if (i.imm_operands)
2495 optimize_imm ();
2496
b300c311
L		 2497 /* Don't optimize displacement for movabs since it only takes 64bit
2498 displacement. */
2499 if (i.disp_operands
2500 && (flag_code != CODE_64BIT
2501 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2502 optimize_disp ();
2503
2504 /* Next, we find a template that matches the given insn,
2505 making sure the overlap of the given operands types is consistent
2506 with the template operand types. */
252b5132 2507
29b0f896
AM		 2508 if (!match_template ())
2509 return;
252b5132 2510
321fd21e
L		 2511 /* Zap movzx and movsx suffix. The suffix has been set from
2512 "word ptr" or "byte ptr" on the source operand in Intel syntax
2513 or extracted from mnemonic in AT&T syntax. But we'll use
2514 the destination register to choose the suffix for encoding. */
2515 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2516 {
321fd21e
L		 2517 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2518 there is no suffix, the default will be byte extension. */
2519 if (i.reg_operands != 2
2520 && !i.suffix
2521 && intel_syntax)
2522 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2523
2524 i.suffix = 0;
cd61ebfe 2525 }
24eab124 2526
40fb9820 2527 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2528 if (!add_prefix (FWAIT_OPCODE))
2529 return;
252b5132 2530
29b0f896 2531 /* Check string instruction segment overrides. */
40fb9820 2532 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2533 {
2534 if (!check_string ())
5dd0794d 2535 return;
29b0f896 2536 }
5dd0794d 2537
29b0f896
AM		 2538 if (!process_suffix ())
2539 return;
e413e4e9 2540
29b0f896
AM		 2541 /* Make still unresolved immediate matches conform to size of immediate
2542 given in i.suffix. */
2543 if (!finalize_imm ())
2544 return;
252b5132 2545
40fb9820 2546 if (i.types[0].bitfield.imm1)
29b0f896 2547 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2548
40fb9820 2549 for (j = 0; j < 3; j++)
c6fb90c8
L		 2550 if (i.types[j].bitfield.inoutportreg
2551 || i.types[j].bitfield.shiftcount
2552 || i.types[j].bitfield.acc
2553 || i.types[j].bitfield.floatacc)
40fb9820
L		 2554 i.reg_operands--;
2555
2556 if (i.tm.opcode_modifier.immext)
65da13b5 2557 process_immext ();
252b5132 2558
29b0f896
AM		 2559 /* For insns with operands there are more diddles to do to the opcode. */
2560 if (i.operands)
2561 {
2562 if (!process_operands ())
2563 return;
2564 }
40fb9820 2565 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2566 {
2567 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2568 as_warn (_("translating to `%sp'"), i.tm.name);
2569 }
252b5132 2570
29b0f896
AM		 2571 /* Handle conversion of 'int $3' --> special int3 insn. */
2572 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2573 {
2574 i.tm.base_opcode = INT3_OPCODE;
2575 i.imm_operands = 0;
2576 }
252b5132 2577
40fb9820
L		 2578 if ((i.tm.opcode_modifier.jump
2579 || i.tm.opcode_modifier.jumpbyte
2580 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2581 && i.op[0].disps->X_op == O_constant)
2582 {
2583 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2584 the absolute address given by the constant. Since ix86 jumps and
2585 calls are pc relative, we need to generate a reloc. */
2586 i.op[0].disps->X_add_symbol = &abs_symbol;
2587 i.op[0].disps->X_op = O_symbol;
2588 }
252b5132 2589
40fb9820 2590 if (i.tm.opcode_modifier.rex64)
161a04f6 2591 i.rex |= REX_W;
252b5132 2592
29b0f896
AM		 2593 /* For 8 bit registers we need an empty rex prefix. Also if the
2594 instruction already has a prefix, we need to convert old
2595 registers to new ones. */
773f551c 2596
40fb9820 2597 if ((i.types[0].bitfield.reg8
29b0f896 2598 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2599 || (i.types[1].bitfield.reg8
29b0f896 2600 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2601 || ((i.types[0].bitfield.reg8
2602 || i.types[1].bitfield.reg8)
29b0f896
AM		 2603 && i.rex != 0))
2604 {
2605 int x;
726c5dcd 2606
29b0f896
AM		 2607 i.rex |= REX_OPCODE;
2608 for (x = 0; x < 2; x++)
2609 {
2610 /* Look for 8 bit operand that uses old registers. */
40fb9820 2611 if (i.types[x].bitfield.reg8
29b0f896 2612 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2613 {
29b0f896
AM		 2614 /* In case it is "hi" register, give up. */
2615 if (i.op[x].regs->reg_num > 3)
a540244d 2616 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2617 "instruction requiring REX prefix."),
a540244d 2618 register_prefix, i.op[x].regs->reg_name);
773f551c 2619
29b0f896
AM		 2620 /* Otherwise it is equivalent to the extended register.
2621 Since the encoding doesn't change this is merely
2622 cosmetic cleanup for debug output. */
2623
2624 i.op[x].regs = i.op[x].regs + 8;
773f551c 2625 }
29b0f896
AM		 2626 }
2627 }
773f551c 2628
85f10a01
MM		 2629 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2630 REX prefix. */
2631 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2632 {
2633 i.drex.rex = i.rex;
2634 i.rex = 0;
2635 }
2636 else if (i.rex != 0)
29b0f896
AM		 2637 add_prefix (REX_OPCODE | i.rex);
2638
2639 /* We are ready to output the insn. */
2640 output_insn ();
2641}
2642
2643static char *
e3bb37b5 2644parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2645{
2646 char *l = line;
2647 char *token_start = l;
2648 char *mnem_p;
5c6af06e
JB		 2649 int supported;
2650 const template *t;
29b0f896
AM		 2651
2652 /* Non-zero if we found a prefix only acceptable with string insns. */
2653 const char *expecting_string_instruction = NULL;
45288df1 2654
29b0f896
AM		 2655 while (1)
2656 {
2657 mnem_p = mnemonic;
2658 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2659 {
2660 mnem_p++;
2661 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2662 {
29b0f896
AM		 2663 as_bad (_("no such instruction: `%s'"), token_start);
2664 return NULL;
2665 }
2666 l++;
2667 }
2668 if (!is_space_char (*l)
2669 && *l != END_OF_INSN
e44823cf
JB		 2670 && (intel_syntax
2671 || (*l != PREFIX_SEPARATOR
2672 && *l != ',')))
29b0f896
AM		 2673 {
2674 as_bad (_("invalid character %s in mnemonic"),
2675 output_invalid (*l));
2676 return NULL;
2677 }
2678 if (token_start == l)
2679 {
e44823cf 2680 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2681 as_bad (_("expecting prefix; got nothing"));
2682 else
2683 as_bad (_("expecting mnemonic; got nothing"));
2684 return NULL;
2685 }
45288df1 2686
29b0f896
AM		 2687 /* Look up instruction (or prefix) via hash table. */
2688 current_templates = hash_find (op_hash, mnemonic);
47926f60 2689
29b0f896
AM		 2690 if (*l != END_OF_INSN
2691 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2692 && current_templates
40fb9820 2693 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2694 {
c6fb90c8 2695 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2696 {
2697 as_bad ((flag_code != CODE_64BIT
2698 ? _("`%s' is only supported in 64-bit mode")
2699 : _("`%s' is not supported in 64-bit mode")),
2700 current_templates->start->name);
2701 return NULL;
2702 }
29b0f896
AM		 2703 /* If we are in 16-bit mode, do not allow addr16 or data16.
2704 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2705 if ((current_templates->start->opcode_modifier.size16
2706 || current_templates->start->opcode_modifier.size32)
29b0f896 2707 && flag_code != CODE_64BIT
40fb9820 2708 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2709 ^ (flag_code == CODE_16BIT)))
2710 {
2711 as_bad (_("redundant %s prefix"),
2712 current_templates->start->name);
2713 return NULL;
45288df1 2714 }
29b0f896
AM		 2715 /* Add prefix, checking for repeated prefixes. */
2716 switch (add_prefix (current_templates->start->base_opcode))
2717 {
2718 case 0:
2719 return NULL;
2720 case 2:
2721 expecting_string_instruction = current_templates->start->name;
2722 break;
2723 }
2724 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2725 token_start = ++l;
2726 }
2727 else
2728 break;
2729 }
45288df1 2730
29b0f896
AM		 2731 if (!current_templates)
2732 {
2733 /* See if we can get a match by trimming off a suffix. */
2734 switch (mnem_p[-1])
2735 {
2736 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2737 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2738 i.suffix = SHORT_MNEM_SUFFIX;
2739 else
29b0f896
AM		 2740 case BYTE_MNEM_SUFFIX:
2741 case QWORD_MNEM_SUFFIX:
2742 i.suffix = mnem_p[-1];
2743 mnem_p[-1] = '\0';
2744 current_templates = hash_find (op_hash, mnemonic);
2745 break;
2746 case SHORT_MNEM_SUFFIX:
2747 case LONG_MNEM_SUFFIX:
2748 if (!intel_syntax)
2749 {
2750 i.suffix = mnem_p[-1];
2751 mnem_p[-1] = '\0';
2752 current_templates = hash_find (op_hash, mnemonic);
2753 }
2754 break;
252b5132 2755
29b0f896
AM		 2756 /* Intel Syntax. */
2757 case 'd':
2758 if (intel_syntax)
2759 {
9306ca4a 2760 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2761 i.suffix = SHORT_MNEM_SUFFIX;
2762 else
2763 i.suffix = LONG_MNEM_SUFFIX;
2764 mnem_p[-1] = '\0';
2765 current_templates = hash_find (op_hash, mnemonic);
2766 }
2767 break;
2768 }
2769 if (!current_templates)
2770 {
2771 as_bad (_("no such instruction: `%s'"), token_start);
2772 return NULL;
2773 }
2774 }
252b5132 2775
40fb9820
L		 2776 if (current_templates->start->opcode_modifier.jump
2777 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2778 {
2779 /* Check for a branch hint. We allow ",pt" and ",pn" for
2780 predict taken and predict not taken respectively.
2781 I'm not sure that branch hints actually do anything on loop
2782 and jcxz insns (JumpByte) for current Pentium4 chips. They
2783 may work in the future and it doesn't hurt to accept them
2784 now. */
2785 if (l[0] == ',' && l[1] == 'p')
2786 {
2787 if (l[2] == 't')
2788 {
2789 if (!add_prefix (DS_PREFIX_OPCODE))
2790 return NULL;
2791 l += 3;
2792 }
2793 else if (l[2] == 'n')
2794 {
2795 if (!add_prefix (CS_PREFIX_OPCODE))
2796 return NULL;
2797 l += 3;
2798 }
2799 }
2800 }
2801 /* Any other comma loses. */
2802 if (*l == ',')
2803 {
2804 as_bad (_("invalid character %s in mnemonic"),
2805 output_invalid (*l));
2806 return NULL;
2807 }
252b5132 2808
29b0f896 2809 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2810 supported = 0;
2811 for (t = current_templates->start; t < current_templates->end; ++t)
2812 {
3629bb00
L		 2813 supported |= cpu_flags_match (t->cpu_flags);
2814 if (supported == 3)
2815 goto skip;
5c6af06e 2816 }
3629bb00 2817
5c6af06e
JB		 2818 if (!(supported & 2))
2819 {
2820 as_bad (flag_code == CODE_64BIT
2821 ? _("`%s' is not supported in 64-bit mode")
2822 : _("`%s' is only supported in 64-bit mode"),
2823 current_templates->start->name);
2824 return NULL;
2825 }
2826 if (!(supported & 1))
29b0f896 2827 {
3629bb00
L		 2828 as_bad (_("`%s' is not supported on `%s%s'"),
2829 current_templates->start->name, cpu_arch_name,
2830 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2831 return NULL;
29b0f896 2832 }
3629bb00
L		 2833
2834skip:
2835 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 2836 && (flag_code != CODE_16BIT))
29b0f896
AM		 2837 {
2838 as_warn (_("use .code16 to ensure correct addressing mode"));
2839 }
252b5132 2840
29b0f896 2841 /* Check for rep/repne without a string instruction. */
f41bbced 2842 if (expecting_string_instruction)
29b0f896 2843 {
f41bbced
JB		 2844 static templates override;
2845
2846 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2847 if (t->opcode_modifier.isstring)
f41bbced
JB		 2848 break;
2849 if (t >= current_templates->end)
2850 {
2851 as_bad (_("expecting string instruction after `%s'"),
64e74474 2852 expecting_string_instruction);
f41bbced
JB		 2853 return NULL;
2854 }
2855 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2856 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2857 break;
2858 override.end = t;
2859 current_templates = &override;
29b0f896 2860 }
252b5132 2861
29b0f896
AM		 2862 return l;
2863}
252b5132 2864
29b0f896 2865static char *
e3bb37b5 2866parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2867{
2868 char *token_start;
3138f287 2869
29b0f896
AM		 2870 /* 1 if operand is pending after ','. */
2871 unsigned int expecting_operand = 0;
252b5132 2872
29b0f896
AM		 2873 /* Non-zero if operand parens not balanced. */
2874 unsigned int paren_not_balanced;
2875
2876 while (*l != END_OF_INSN)
2877 {
2878 /* Skip optional white space before operand. */
2879 if (is_space_char (*l))
2880 ++l;
2881 if (!is_operand_char (*l) && *l != END_OF_INSN)
2882 {
2883 as_bad (_("invalid character %s before operand %d"),
2884 output_invalid (*l),
2885 i.operands + 1);
2886 return NULL;
2887 }
2888 token_start = l; /* after white space */
2889 paren_not_balanced = 0;
2890 while (paren_not_balanced || *l != ',')
2891 {
2892 if (*l == END_OF_INSN)
2893 {
2894 if (paren_not_balanced)
2895 {
2896 if (!intel_syntax)
2897 as_bad (_("unbalanced parenthesis in operand %d."),
2898 i.operands + 1);
2899 else
2900 as_bad (_("unbalanced brackets in operand %d."),
2901 i.operands + 1);
2902 return NULL;
2903 }
2904 else
2905 break; /* we are done */
2906 }
2907 else if (!is_operand_char (*l) && !is_space_char (*l))
2908 {
2909 as_bad (_("invalid character %s in operand %d"),
2910 output_invalid (*l),
2911 i.operands + 1);
2912 return NULL;
2913 }
2914 if (!intel_syntax)
2915 {
2916 if (*l == '(')
2917 ++paren_not_balanced;
2918 if (*l == ')')
2919 --paren_not_balanced;
2920 }
2921 else
2922 {
2923 if (*l == '[')
2924 ++paren_not_balanced;
2925 if (*l == ']')
2926 --paren_not_balanced;
2927 }
2928 l++;
2929 }
2930 if (l != token_start)
2931 { /* Yes, we've read in another operand. */
2932 unsigned int operand_ok;
2933 this_operand = i.operands++;
7d5e4556 2934 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 2935 if (i.operands > MAX_OPERANDS)
2936 {
2937 as_bad (_("spurious operands; (%d operands/instruction max)"),
2938 MAX_OPERANDS);
2939 return NULL;
2940 }
2941 /* Now parse operand adding info to 'i' as we go along. */
2942 END_STRING_AND_SAVE (l);
2943
2944 if (intel_syntax)
2945 operand_ok =
2946 i386_intel_operand (token_start,
2947 intel_float_operand (mnemonic));
2948 else
a7619375 2949 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 2950
2951 RESTORE_END_STRING (l);
2952 if (!operand_ok)
2953 return NULL;
2954 }
2955 else
2956 {
2957 if (expecting_operand)
2958 {
2959 expecting_operand_after_comma:
2960 as_bad (_("expecting operand after ','; got nothing"));
2961 return NULL;
2962 }
2963 if (*l == ',')
2964 {
2965 as_bad (_("expecting operand before ','; got nothing"));
2966 return NULL;
2967 }
2968 }
7f3f1ea2 2969
29b0f896
AM		 2970 /* Now *l must be either ',' or END_OF_INSN. */
2971 if (*l == ',')
2972 {
2973 if (*++l == END_OF_INSN)
2974 {
2975 /* Just skip it, if it's \n complain. */
2976 goto expecting_operand_after_comma;
2977 }
2978 expecting_operand = 1;
2979 }
2980 }
2981 return l;
2982}
7f3f1ea2 2983
050dfa73 2984static void
4d456e3d 2985swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2986{
2987 union i386_op temp_op;
40fb9820 2988 i386_operand_type temp_type;
050dfa73 2989 enum bfd_reloc_code_real temp_reloc;
4eed87de 2990
050dfa73
MM		 2991 temp_type = i.types[xchg2];
2992 i.types[xchg2] = i.types[xchg1];
2993 i.types[xchg1] = temp_type;
2994 temp_op = i.op[xchg2];
2995 i.op[xchg2] = i.op[xchg1];
2996 i.op[xchg1] = temp_op;
2997 temp_reloc = i.reloc[xchg2];
2998 i.reloc[xchg2] = i.reloc[xchg1];
2999 i.reloc[xchg1] = temp_reloc;
3000}
3001
29b0f896 3002static void
e3bb37b5 3003swap_operands (void)
29b0f896 3004{
b7c61d9a 3005 switch (i.operands)
050dfa73 3006 {
b7c61d9a 3007 case 4:
4d456e3d 3008 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3009 case 3:
3010 case 2:
4d456e3d 3011 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3012 break;
3013 default:
3014 abort ();
29b0f896 3015 }
29b0f896
AM		 3016
3017 if (i.mem_operands == 2)
3018 {
3019 const seg_entry *temp_seg;
3020 temp_seg = i.seg[0];
3021 i.seg[0] = i.seg[1];
3022 i.seg[1] = temp_seg;
3023 }
3024}
252b5132 3025
29b0f896
AM		 3026/* Try to ensure constant immediates are represented in the smallest
3027 opcode possible. */
3028static void
e3bb37b5 3029optimize_imm (void)
29b0f896
AM		 3030{
3031 char guess_suffix = 0;
3032 int op;
252b5132 3033
29b0f896
AM		 3034 if (i.suffix)
3035 guess_suffix = i.suffix;
3036 else if (i.reg_operands)
3037 {
3038 /* Figure out a suffix from the last register operand specified.
3039 We can't do this properly yet, ie. excluding InOutPortReg,
3040 but the following works for instructions with immediates.
3041 In any case, we can't set i.suffix yet. */
3042 for (op = i.operands; --op >= 0;)
40fb9820
L		 3043 if (i.types[op].bitfield.reg8)
3044 {
3045 guess_suffix = BYTE_MNEM_SUFFIX;
3046 break;
3047 }
3048 else if (i.types[op].bitfield.reg16)
252b5132 3049 {
40fb9820
L		 3050 guess_suffix = WORD_MNEM_SUFFIX;
3051 break;
3052 }
3053 else if (i.types[op].bitfield.reg32)
3054 {
3055 guess_suffix = LONG_MNEM_SUFFIX;
3056 break;
3057 }
3058 else if (i.types[op].bitfield.reg64)
3059 {
3060 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3061 break;
252b5132 3062 }
29b0f896
AM		 3063 }
3064 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3065 guess_suffix = WORD_MNEM_SUFFIX;
3066
3067 for (op = i.operands; --op >= 0;)
40fb9820 3068 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3069 {
3070 switch (i.op[op].imms->X_op)
252b5132 3071 {
29b0f896
AM		 3072 case O_constant:
3073 /* If a suffix is given, this operand may be shortened. */
3074 switch (guess_suffix)
252b5132 3075 {
29b0f896 3076 case LONG_MNEM_SUFFIX:
40fb9820
L		 3077 i.types[op].bitfield.imm32 = 1;
3078 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3079 break;
3080 case WORD_MNEM_SUFFIX:
40fb9820
L		 3081 i.types[op].bitfield.imm16 = 1;
3082 i.types[op].bitfield.imm32 = 1;
3083 i.types[op].bitfield.imm32s = 1;
3084 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3085 break;
3086 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3087 i.types[op].bitfield.imm8 = 1;
3088 i.types[op].bitfield.imm8s = 1;
3089 i.types[op].bitfield.imm16 = 1;
3090 i.types[op].bitfield.imm32 = 1;
3091 i.types[op].bitfield.imm32s = 1;
3092 i.types[op].bitfield.imm64 = 1;
29b0f896 3093 break;
252b5132 3094 }
252b5132 3095
29b0f896
AM		 3096 /* If this operand is at most 16 bits, convert it
3097 to a signed 16 bit number before trying to see
3098 whether it will fit in an even smaller size.
3099 This allows a 16-bit operand such as $0xffe0 to
3100 be recognised as within Imm8S range. */
40fb9820 3101 if ((i.types[op].bitfield.imm16)
29b0f896 3102 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3103 {
29b0f896
AM		 3104 i.op[op].imms->X_add_number =
3105 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3106 }
40fb9820 3107 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3108 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3109 == 0))
3110 {
3111 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3112 ^ ((offsetT) 1 << 31))
3113 - ((offsetT) 1 << 31));
3114 }
40fb9820 3115 i.types[op]
c6fb90c8
L		 3116 = operand_type_or (i.types[op],
3117 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3118
29b0f896
AM		 3119 /* We must avoid matching of Imm32 templates when 64bit
3120 only immediate is available. */
3121 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3122 i.types[op].bitfield.imm32 = 0;
29b0f896 3123 break;
252b5132 3124
29b0f896
AM		 3125 case O_absent:
3126 case O_register:
3127 abort ();
3128
3129 /* Symbols and expressions. */
3130 default:
9cd96992
JB		 3131 /* Convert symbolic operand to proper sizes for matching, but don't
3132 prevent matching a set of insns that only supports sizes other
3133 than those matching the insn suffix. */
3134 {
40fb9820 3135 i386_operand_type mask, allowed;
9cd96992
JB		 3136 const template *t;
3137
0dfbf9d7
L		 3138 operand_type_set (&mask, 0);
3139 operand_type_set (&allowed, 0);
40fb9820 3140
4eed87de
AM		 3141 for (t = current_templates->start;
3142 t < current_templates->end;
3143 ++t)
c6fb90c8
L		 3144 allowed = operand_type_or (allowed,
3145 t->operand_types[op]);
9cd96992
JB		 3146 switch (guess_suffix)
3147 {
3148 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3149 mask.bitfield.imm64 = 1;
3150 mask.bitfield.imm32s = 1;
9cd96992
JB		 3151 break;
3152 case LONG_MNEM_SUFFIX:
40fb9820 3153 mask.bitfield.imm32 = 1;
9cd96992
JB		 3154 break;
3155 case WORD_MNEM_SUFFIX:
40fb9820 3156 mask.bitfield.imm16 = 1;
9cd96992
JB		 3157 break;
3158 case BYTE_MNEM_SUFFIX:
40fb9820 3159 mask.bitfield.imm8 = 1;
9cd96992
JB		 3160 break;
3161 default:
9cd96992
JB		 3162 break;
3163 }
c6fb90c8 3164 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3165 if (!operand_type_all_zero (&allowed))
c6fb90c8 3166 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3167 }
29b0f896 3168 break;
252b5132 3169 }
29b0f896
AM		 3170 }
3171}
47926f60 3172
29b0f896
AM		 3173/* Try to use the smallest displacement type too. */
3174static void
e3bb37b5 3175optimize_disp (void)
29b0f896
AM		 3176{
3177 int op;
3e73aa7c 3178
29b0f896 3179 for (op = i.operands; --op >= 0;)
40fb9820 3180 if (operand_type_check (i.types[op], disp))
252b5132 3181 {
b300c311 3182 if (i.op[op].disps->X_op == O_constant)
252b5132 3183 {
b300c311 3184 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3185
40fb9820 3186 if (i.types[op].bitfield.disp16
b300c311
L		 3187 && (disp & ~(offsetT) 0xffff) == 0)
3188 {
3189 /* If this operand is at most 16 bits, convert
3190 to a signed 16 bit number and don't use 64bit
3191 displacement. */
3192 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3193 i.types[op].bitfield.disp64 = 0;
b300c311 3194 }
40fb9820 3195 if (i.types[op].bitfield.disp32
b300c311
L		 3196 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3197 {
3198 /* If this operand is at most 32 bits, convert
3199 to a signed 32 bit number and don't use 64bit
3200 displacement. */
3201 disp &= (((offsetT) 2 << 31) - 1);
3202 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3203 i.types[op].bitfield.disp64 = 0;
b300c311 3204 }
40fb9820 3205 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3206 {
40fb9820
L		 3207 i.types[op].bitfield.disp8 = 0;
3208 i.types[op].bitfield.disp16 = 0;
3209 i.types[op].bitfield.disp32 = 0;
3210 i.types[op].bitfield.disp32s = 0;
3211 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3212 i.op[op].disps = 0;
3213 i.disp_operands--;
3214 }
3215 else if (flag_code == CODE_64BIT)
3216 {
3217 if (fits_in_signed_long (disp))
28a9d8f5 3218 {
40fb9820
L		 3219 i.types[op].bitfield.disp64 = 0;
3220 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3221 }
b300c311 3222 if (fits_in_unsigned_long (disp))
40fb9820 3223 i.types[op].bitfield.disp32 = 1;
b300c311 3224 }
40fb9820
L		 3225 if ((i.types[op].bitfield.disp32
3226 || i.types[op].bitfield.disp32s
3227 || i.types[op].bitfield.disp16)
b300c311 3228 && fits_in_signed_byte (disp))
40fb9820 3229 i.types[op].bitfield.disp8 = 1;
252b5132 3230 }
67a4f2b7
AO		 3231 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3232 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3233 {
3234 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3235 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3236 i.types[op].bitfield.disp8 = 0;
3237 i.types[op].bitfield.disp16 = 0;
3238 i.types[op].bitfield.disp32 = 0;
3239 i.types[op].bitfield.disp32s = 0;
3240 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3241 }
3242 else
b300c311 3243 /* We only support 64bit displacement on constants. */
40fb9820 3244 i.types[op].bitfield.disp64 = 0;
252b5132 3245 }
29b0f896
AM		 3246}
3247
3248static int
e3bb37b5 3249match_template (void)
29b0f896
AM		 3250{
3251 /* Points to template once we've found it. */
3252 const template *t;
40fb9820 3253 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 3254 unsigned int found_reverse_match;
40fb9820
L		 3255 i386_opcode_modifier suffix_check;
3256 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3257 int addr_prefix_disp;
a5c311ca 3258 unsigned int j;
3629bb00 3259 unsigned int found_cpu_match;
45664ddb 3260 unsigned int check_register;
29b0f896 3261
f48ff2ae
L		 3262#if MAX_OPERANDS != 4
3263# error "MAX_OPERANDS must be 4."
3264#endif
3265
29b0f896 3266 found_reverse_match = 0;
539e75ad 3267 addr_prefix_disp = -1;
40fb9820
L		 3268
3269 memset (&suffix_check, 0, sizeof (suffix_check));
3270 if (i.suffix == BYTE_MNEM_SUFFIX)
3271 suffix_check.no_bsuf = 1;
3272 else if (i.suffix == WORD_MNEM_SUFFIX)
3273 suffix_check.no_wsuf = 1;
3274 else if (i.suffix == SHORT_MNEM_SUFFIX)
3275 suffix_check.no_ssuf = 1;
3276 else if (i.suffix == LONG_MNEM_SUFFIX)
3277 suffix_check.no_lsuf = 1;
3278 else if (i.suffix == QWORD_MNEM_SUFFIX)
3279 suffix_check.no_qsuf = 1;
3280 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3281 suffix_check.no_ldsuf = 1;
29b0f896 3282
45aa61fe 3283 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3284 {
539e75ad
L		 3285 addr_prefix_disp = -1;
3286
29b0f896
AM		 3287 /* Must have right number of operands. */
3288 if (i.operands != t->operands)
3289 continue;
3290
50aecf8c
L		 3291 /* Check processor support. */
3292 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
3293 if (!found_cpu_match)
3294 continue;
3295
e1d4d893
L		 3296 /* Check old gcc support. */
3297 if (!old_gcc && t->opcode_modifier.oldgcc)
3298 continue;
3299
3300 /* Check AT&T mnemonic. */
3301 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3302 continue;
3303
5c07affc
L		 3304 /* Check AT&T syntax Intel syntax. */
3305 if ((intel_syntax && t->opcode_modifier.attsyntax)
3306 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3307 continue;
3308
20592a94 3309 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3310 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3311 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3312 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3313 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3314 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3315 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3316 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3317 continue;
3318
5c07affc 3319 if (!operand_size_match (t))
7d5e4556 3320 continue;
539e75ad 3321
5c07affc
L		 3322 for (j = 0; j < MAX_OPERANDS; j++)
3323 operand_types[j] = t->operand_types[j];
3324
45aa61fe
AM		 3325 /* In general, don't allow 64-bit operands in 32-bit mode. */
3326 if (i.suffix == QWORD_MNEM_SUFFIX
3327 && flag_code != CODE_64BIT
3328 && (intel_syntax
40fb9820 3329 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3330 && !intel_float_operand (t->name))
3331 : intel_float_operand (t->name) != 2)
40fb9820
L		 3332 && ((!operand_types[0].bitfield.regmmx
3333 && !operand_types[0].bitfield.regxmm)
3334 || (!operand_types[t->operands > 1].bitfield.regmmx
3335 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 3336 && (t->base_opcode != 0x0fc7
3337 || t->extension_opcode != 1 /* cmpxchg8b */))
3338 continue;
3339
192dc9c6
JB		 3340 /* In general, don't allow 32-bit operands on pre-386. */
3341 else if (i.suffix == LONG_MNEM_SUFFIX
3342 && !cpu_arch_flags.bitfield.cpui386
3343 && (intel_syntax
3344 ? (!t->opcode_modifier.ignoresize
3345 && !intel_float_operand (t->name))
3346 : intel_float_operand (t->name) != 2)
3347 && ((!operand_types[0].bitfield.regmmx
3348 && !operand_types[0].bitfield.regxmm)
3349 || (!operand_types[t->operands > 1].bitfield.regmmx
3350 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3351 continue;
3352
29b0f896 3353 /* Do not verify operands when there are none. */
50aecf8c 3354 else
29b0f896 3355 {
c6fb90c8 3356 if (!t->operands)
2dbab7d5
L		 3357 /* We've found a match; break out of loop. */
3358 break;
29b0f896 3359 }
252b5132 3360
539e75ad
L		 3361 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3362 into Disp32/Disp16/Disp32 operand. */
3363 if (i.prefix[ADDR_PREFIX] != 0)
3364 {
40fb9820 3365 /* There should be only one Disp operand. */
539e75ad
L		 3366 switch (flag_code)
3367 {
3368 case CODE_16BIT:
40fb9820
L		 3369 for (j = 0; j < MAX_OPERANDS; j++)
3370 {
3371 if (operand_types[j].bitfield.disp16)
3372 {
3373 addr_prefix_disp = j;
3374 operand_types[j].bitfield.disp32 = 1;
3375 operand_types[j].bitfield.disp16 = 0;
3376 break;
3377 }
3378 }
539e75ad
L		 3379 break;
3380 case CODE_32BIT:
40fb9820
L		 3381 for (j = 0; j < MAX_OPERANDS; j++)
3382 {
3383 if (operand_types[j].bitfield.disp32)
3384 {
3385 addr_prefix_disp = j;
3386 operand_types[j].bitfield.disp32 = 0;
3387 operand_types[j].bitfield.disp16 = 1;
3388 break;
3389 }
3390 }
539e75ad
L		 3391 break;
3392 case CODE_64BIT:
40fb9820
L		 3393 for (j = 0; j < MAX_OPERANDS; j++)
3394 {
3395 if (operand_types[j].bitfield.disp64)
3396 {
3397 addr_prefix_disp = j;
3398 operand_types[j].bitfield.disp64 = 0;
3399 operand_types[j].bitfield.disp32 = 1;
3400 break;
3401 }
3402 }
539e75ad
L		 3403 break;
3404 }
539e75ad
L		 3405 }
3406
45664ddb
L		 3407 /* We check register size only if size of operands can be
3408 encoded the canonical way. */
3409 check_register = t->opcode_modifier.w;
c6fb90c8 3410 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3411 switch (t->operands)
3412 {
3413 case 1:
40fb9820 3414 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3415 continue;
3416 break;
3417 case 2:
8b38ad71
L		 3418 /* xchg %eax, %eax is a special case. It is an aliase for nop
3419 only in 32bit mode and we can use opcode 0x90. In 64bit
3420 mode, we can't use 0x90 for xchg %eax, %eax since it should
3421 zero-extend %eax to %rax. */
3422 if (flag_code == CODE_64BIT
3423 && t->base_opcode == 0x90
0dfbf9d7
L		 3424 && operand_type_equal (&i.types [0], &acc32)
3425 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3426 continue;
29b0f896 3427 case 3:
f48ff2ae 3428 case 4:
c6fb90c8 3429 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3430 if (!operand_type_match (overlap0, i.types[0])
3431 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3432 || (check_register
3433 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3434 operand_types[0],
3435 overlap1, i.types[1],
3436 operand_types[1])))
29b0f896
AM		 3437 {
3438 /* Check if other direction is valid ... */
40fb9820 3439 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3440 continue;
3441
3442 /* Try reversing direction of operands. */
c6fb90c8
L		 3443 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3444 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3445 if (!operand_type_match (overlap0, i.types[0])
3446 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3447 || (check_register
3448 && !operand_type_register_match (overlap0,
3449 i.types[0],
3450 operand_types[1],
3451 overlap1,
3452 i.types[1],
3453 operand_types[0])))
29b0f896
AM		 3454 {
3455 /* Does not match either direction. */
3456 continue;
3457 }
3458 /* found_reverse_match holds which of D or FloatDR
3459 we've found. */
40fb9820 3460 if (t->opcode_modifier.d)
8a2ed489 3461 found_reverse_match = Opcode_D;
40fb9820 3462 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3463 found_reverse_match = Opcode_FloatD;
3464 else
3465 found_reverse_match = 0;
40fb9820 3466 if (t->opcode_modifier.floatr)
8a2ed489 3467 found_reverse_match |= Opcode_FloatR;
29b0f896 3468 }
f48ff2ae 3469 else
29b0f896 3470 {
f48ff2ae 3471 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3472 switch (t->operands)
3473 {
3474 case 4:
c6fb90c8
L		 3475 overlap3 = operand_type_and (i.types[3],
3476 operand_types[3]);
d1cbb4db 3477 case 3:
c6fb90c8
L		 3478 overlap2 = operand_type_and (i.types[2],
3479 operand_types[2]);
d1cbb4db
L		 3480 break;
3481 }
29b0f896 3482
f48ff2ae
L		 3483 switch (t->operands)
3484 {
3485 case 4:
40fb9820 3486 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3487 || (check_register
3488 && !operand_type_register_match (overlap2,
3489 i.types[2],
3490 operand_types[2],
3491 overlap3,
3492 i.types[3],
3493 operand_types[3])))
f48ff2ae
L		 3494 continue;
3495 case 3:
3496 /* Here we make use of the fact that there are no
3497 reverse match 3 operand instructions, and all 3
3498 operand instructions only need to be checked for
3499 register consistency between operands 2 and 3. */
40fb9820 3500 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3501 || (check_register
3502 && !operand_type_register_match (overlap1,
3503 i.types[1],
3504 operand_types[1],
3505 overlap2,
3506 i.types[2],
3507 operand_types[2])))
f48ff2ae
L		 3508 continue;
3509 break;
3510 }
29b0f896 3511 }
f48ff2ae 3512 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3513 slip through to break. */
3514 }
3629bb00 3515 if (!found_cpu_match)
29b0f896
AM		 3516 {
3517 found_reverse_match = 0;
3518 continue;
3519 }
3520 /* We've found a match; break out of loop. */
3521 break;
3522 }
3523
3524 if (t == current_templates->end)
3525 {
3526 /* We found no match. */
3527 as_bad (_("suffix or operands invalid for `%s'"),
3528 current_templates->start->name);
3529 return 0;
3530 }
252b5132 3531
29b0f896
AM		 3532 if (!quiet_warnings)
3533 {
3534 if (!intel_syntax
40fb9820
L		 3535 && (i.types[0].bitfield.jumpabsolute
3536 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3537 {
3538 as_warn (_("indirect %s without `*'"), t->name);
3539 }
3540
40fb9820
L		 3541 if (t->opcode_modifier.isprefix
3542 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3543 {
3544 /* Warn them that a data or address size prefix doesn't
3545 affect assembly of the next line of code. */
3546 as_warn (_("stand-alone `%s' prefix"), t->name);
3547 }
3548 }
3549
3550 /* Copy the template we found. */
3551 i.tm = *t;
539e75ad
L		 3552
3553 if (addr_prefix_disp != -1)
3554 i.tm.operand_types[addr_prefix_disp]
3555 = operand_types[addr_prefix_disp];
3556
29b0f896
AM		 3557 if (found_reverse_match)
3558 {
3559 /* If we found a reverse match we must alter the opcode
3560 direction bit. found_reverse_match holds bits to change
3561 (different for int & float insns). */
3562
3563 i.tm.base_opcode ^= found_reverse_match;
3564
539e75ad
L		 3565 i.tm.operand_types[0] = operand_types[1];
3566 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3567 }
3568
3569 return 1;
3570}
3571
3572static int
e3bb37b5 3573check_string (void)
29b0f896 3574{
40fb9820
L		 3575 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3576 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3577 {
3578 if (i.seg[0] != NULL && i.seg[0] != &es)
3579 {
3580 as_bad (_("`%s' operand %d must use `%%es' segment"),
3581 i.tm.name,
3582 mem_op + 1);
3583 return 0;
3584 }
3585 /* There's only ever one segment override allowed per instruction.
3586 This instruction possibly has a legal segment override on the
3587 second operand, so copy the segment to where non-string
3588 instructions store it, allowing common code. */
3589 i.seg[0] = i.seg[1];
3590 }
40fb9820 3591 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3592 {
3593 if (i.seg[1] != NULL && i.seg[1] != &es)
3594 {
3595 as_bad (_("`%s' operand %d must use `%%es' segment"),
3596 i.tm.name,
3597 mem_op + 2);
3598 return 0;
3599 }
3600 }
3601 return 1;
3602}
3603
3604static int
543613e9 3605process_suffix (void)
29b0f896
AM		 3606{
3607 /* If matched instruction specifies an explicit instruction mnemonic
3608 suffix, use it. */
40fb9820
L		 3609 if (i.tm.opcode_modifier.size16)
3610 i.suffix = WORD_MNEM_SUFFIX;
3611 else if (i.tm.opcode_modifier.size32)
3612 i.suffix = LONG_MNEM_SUFFIX;
3613 else if (i.tm.opcode_modifier.size64)
3614 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3615 else if (i.reg_operands)
3616 {
3617 /* If there's no instruction mnemonic suffix we try to invent one
3618 based on register operands. */
3619 if (!i.suffix)
3620 {
3621 /* We take i.suffix from the last register operand specified,
3622 Destination register type is more significant than source
381d071f
L		 3623 register type. crc32 in SSE4.2 prefers source register
3624 type. */
3625 if (i.tm.base_opcode == 0xf20f38f1)
3626 {
40fb9820
L		 3627 if (i.types[0].bitfield.reg16)
3628 i.suffix = WORD_MNEM_SUFFIX;
3629 else if (i.types[0].bitfield.reg32)
3630 i.suffix = LONG_MNEM_SUFFIX;
3631 else if (i.types[0].bitfield.reg64)
3632 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3633 }
9344ff29 3634 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3635 {
40fb9820 3636 if (i.types[0].bitfield.reg8)
20592a94
L		 3637 i.suffix = BYTE_MNEM_SUFFIX;
3638 }
381d071f
L		 3639
3640 if (!i.suffix)
3641 {
3642 int op;
3643
20592a94
L		 3644 if (i.tm.base_opcode == 0xf20f38f1
3645 || i.tm.base_opcode == 0xf20f38f0)
3646 {
3647 /* We have to know the operand size for crc32. */
3648 as_bad (_("ambiguous memory operand size for `%s`"),
3649 i.tm.name);
3650 return 0;
3651 }
3652
381d071f 3653 for (op = i.operands; --op >= 0;)
40fb9820 3654 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3655 {
40fb9820
L		 3656 if (i.types[op].bitfield.reg8)
3657 {
3658 i.suffix = BYTE_MNEM_SUFFIX;
3659 break;
3660 }
3661 else if (i.types[op].bitfield.reg16)
3662 {
3663 i.suffix = WORD_MNEM_SUFFIX;
3664 break;
3665 }
3666 else if (i.types[op].bitfield.reg32)
3667 {
3668 i.suffix = LONG_MNEM_SUFFIX;
3669 break;
3670 }
3671 else if (i.types[op].bitfield.reg64)
3672 {
3673 i.suffix = QWORD_MNEM_SUFFIX;
3674 break;
3675 }
381d071f
L		 3676 }
3677 }
29b0f896
AM		 3678 }
3679 else if (i.suffix == BYTE_MNEM_SUFFIX)
3680 {
3681 if (!check_byte_reg ())
3682 return 0;
3683 }
3684 else if (i.suffix == LONG_MNEM_SUFFIX)
3685 {
3686 if (!check_long_reg ())
3687 return 0;
3688 }
3689 else if (i.suffix == QWORD_MNEM_SUFFIX)
3690 {
955e1e6a
L		 3691 if (intel_syntax
3692 && i.tm.opcode_modifier.ignoresize
3693 && i.tm.opcode_modifier.no_qsuf)
3694 i.suffix = 0;
3695 else if (!check_qword_reg ())
29b0f896
AM		 3696 return 0;
3697 }
3698 else if (i.suffix == WORD_MNEM_SUFFIX)
3699 {
3700 if (!check_word_reg ())
3701 return 0;
3702 }
582d5edd
L		 3703 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3704 {
3705 /* Skip if the instruction has x suffix. match_template
3706 should check if it is a valid suffix. */
3707 }
40fb9820 3708 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3709 /* Do nothing if the instruction is going to ignore the prefix. */
3710 ;
3711 else
3712 abort ();
3713 }
40fb9820 3714 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3715 && !i.suffix
3716 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3717 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3718 {
3719 i.suffix = stackop_size;
3720 }
9306ca4a
JB		 3721 else if (intel_syntax
3722 && !i.suffix
40fb9820
L		 3723 && (i.tm.operand_types[0].bitfield.jumpabsolute
3724 || i.tm.opcode_modifier.jumpbyte
3725 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3726 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3727 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3728 {
3729 switch (flag_code)
3730 {
3731 case CODE_64BIT:
40fb9820 3732 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3733 {
3734 i.suffix = QWORD_MNEM_SUFFIX;
3735 break;
3736 }
3737 case CODE_32BIT:
40fb9820 3738 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3739 i.suffix = LONG_MNEM_SUFFIX;
3740 break;
3741 case CODE_16BIT:
40fb9820 3742 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3743 i.suffix = WORD_MNEM_SUFFIX;
3744 break;
3745 }
3746 }
252b5132 3747
9306ca4a 3748 if (!i.suffix)
29b0f896 3749 {
9306ca4a
JB		 3750 if (!intel_syntax)
3751 {
40fb9820 3752 if (i.tm.opcode_modifier.w)
9306ca4a 3753 {
4eed87de
AM		 3754 as_bad (_("no instruction mnemonic suffix given and "
3755 "no register operands; can't size instruction"));
9306ca4a
JB		 3756 return 0;
3757 }
3758 }
3759 else
3760 {
40fb9820
L		 3761 unsigned int suffixes;
3762
3763 suffixes = !i.tm.opcode_modifier.no_bsuf;
3764 if (!i.tm.opcode_modifier.no_wsuf)
3765 suffixes |= 1 << 1;
3766 if (!i.tm.opcode_modifier.no_lsuf)
3767 suffixes |= 1 << 2;
fc4adea1 3768 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 3769 suffixes |= 1 << 3;
3770 if (!i.tm.opcode_modifier.no_ssuf)
3771 suffixes |= 1 << 4;
3772 if (!i.tm.opcode_modifier.no_qsuf)
3773 suffixes |= 1 << 5;
3774
3775 /* There are more than suffix matches. */
3776 if (i.tm.opcode_modifier.w
9306ca4a 3777 || ((suffixes & (suffixes - 1))
40fb9820
L		 3778 && !i.tm.opcode_modifier.defaultsize
3779 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3780 {
3781 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3782 return 0;
3783 }
3784 }
29b0f896 3785 }
252b5132 3786
9306ca4a
JB		 3787 /* Change the opcode based on the operand size given by i.suffix;
3788 We don't need to change things for byte insns. */
3789
582d5edd
L		 3790 if (i.suffix
3791 && i.suffix != BYTE_MNEM_SUFFIX
3792 && i.suffix != XMMWORD_MNEM_SUFFIX)
29b0f896
AM		 3793 {
3794 /* It's not a byte, select word/dword operation. */
40fb9820 3795 if (i.tm.opcode_modifier.w)
29b0f896 3796 {
40fb9820 3797 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3798 i.tm.base_opcode |= 8;
3799 else
3800 i.tm.base_opcode |= 1;
3801 }
0f3f3d8b 3802
29b0f896
AM		 3803 /* Now select between word & dword operations via the operand
3804 size prefix, except for instructions that will ignore this
3805 prefix anyway. */
ca61edf2 3806 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 3807 {
ca61edf2
L		 3808 /* The address size override prefix changes the size of the
3809 first operand. */
40fb9820
L		 3810 if ((flag_code == CODE_32BIT
3811 && i.op->regs[0].reg_type.bitfield.reg16)
3812 || (flag_code != CODE_32BIT
3813 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3814 if (!add_prefix (ADDR_PREFIX_OPCODE))
3815 return 0;
3816 }
3817 else if (i.suffix != QWORD_MNEM_SUFFIX
3818 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3819 && !i.tm.opcode_modifier.ignoresize
3820 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3821 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3822 || (flag_code == CODE_64BIT
40fb9820 3823 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3824 {
3825 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3826
40fb9820 3827 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3828 prefix = ADDR_PREFIX_OPCODE;
252b5132 3829
29b0f896
AM		 3830 if (!add_prefix (prefix))
3831 return 0;
24eab124 3832 }
252b5132 3833
29b0f896
AM		 3834 /* Set mode64 for an operand. */
3835 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3836 && flag_code == CODE_64BIT
40fb9820 3837 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3838 {
3839 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3840 need rex64. cmpxchg8b is also a special case. */
3841 if (! (i.operands == 2
3842 && i.tm.base_opcode == 0x90
3843 && i.tm.extension_opcode == None
0dfbf9d7
L		 3844 && operand_type_equal (&i.types [0], &acc64)
3845 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 3846 && ! (i.operands == 1
3847 && i.tm.base_opcode == 0xfc7
3848 && i.tm.extension_opcode == 1
40fb9820
L		 3849 && !operand_type_check (i.types [0], reg)
3850 && operand_type_check (i.types [0], anymem)))
f6bee062 3851 i.rex |= REX_W;
46e883c5 3852 }
3e73aa7c 3853
29b0f896
AM		 3854 /* Size floating point instruction. */
3855 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3856 if (i.tm.opcode_modifier.floatmf)
543613e9 3857 i.tm.base_opcode ^= 4;
29b0f896 3858 }
7ecd2f8b 3859
29b0f896
AM		 3860 return 1;
3861}
3e73aa7c 3862
29b0f896 3863static int
543613e9 3864check_byte_reg (void)
29b0f896
AM		 3865{
3866 int op;
543613e9 3867
29b0f896
AM		 3868 for (op = i.operands; --op >= 0;)
3869 {
3870 /* If this is an eight bit register, it's OK. If it's the 16 or
3871 32 bit version of an eight bit register, we will just use the
3872 low portion, and that's OK too. */
40fb9820 3873 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3874 continue;
3875
ca61edf2
L		 3876 /* Don't generate this warning if not needed. */
3877 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 3878 continue;
3879
9344ff29
L		 3880 /* crc32 doesn't generate this warning. */
3881 if (i.tm.base_opcode == 0xf20f38f0)
3882 continue;
3883
40fb9820
L		 3884 if ((i.types[op].bitfield.reg16
3885 || i.types[op].bitfield.reg32
3886 || i.types[op].bitfield.reg64)
3887 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3888 {
3889 /* Prohibit these changes in the 64bit mode, since the
3890 lowering is more complicated. */
3891 if (flag_code == CODE_64BIT
40fb9820 3892 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3893 {
2ca3ace5
L		 3894 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3895 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3896 i.suffix);
3897 return 0;
3898 }
3899#if REGISTER_WARNINGS
3900 if (!quiet_warnings
40fb9820 3901 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3902 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3903 register_prefix,
40fb9820 3904 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3905 ? REGNAM_AL - REGNAM_AX
3906 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3907 register_prefix,
29b0f896
AM		 3908 i.op[op].regs->reg_name,
3909 i.suffix);
3910#endif
3911 continue;
3912 }
3913 /* Any other register is bad. */
40fb9820
L		 3914 if (i.types[op].bitfield.reg16
3915 || i.types[op].bitfield.reg32
3916 || i.types[op].bitfield.reg64
3917 || i.types[op].bitfield.regmmx
3918 || i.types[op].bitfield.regxmm
3919 || i.types[op].bitfield.sreg2
3920 || i.types[op].bitfield.sreg3
3921 || i.types[op].bitfield.control
3922 || i.types[op].bitfield.debug
3923 || i.types[op].bitfield.test
3924 || i.types[op].bitfield.floatreg
3925 || i.types[op].bitfield.floatacc)
29b0f896 3926 {
a540244d
L		 3927 as_bad (_("`%s%s' not allowed with `%s%c'"),
3928 register_prefix,
29b0f896
AM		 3929 i.op[op].regs->reg_name,
3930 i.tm.name,
3931 i.suffix);
3932 return 0;
3933 }
3934 }
3935 return 1;
3936}
3937
3938static int
e3bb37b5 3939check_long_reg (void)
29b0f896
AM		 3940{
3941 int op;
3942
3943 for (op = i.operands; --op >= 0;)
3944 /* Reject eight bit registers, except where the template requires
3945 them. (eg. movzb) */
40fb9820
L		 3946 if (i.types[op].bitfield.reg8
3947 && (i.tm.operand_types[op].bitfield.reg16
3948 || i.tm.operand_types[op].bitfield.reg32
3949 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3950 {
a540244d
L		 3951 as_bad (_("`%s%s' not allowed with `%s%c'"),
3952 register_prefix,
29b0f896
AM		 3953 i.op[op].regs->reg_name,
3954 i.tm.name,
3955 i.suffix);
3956 return 0;
3957 }
3958 /* Warn if the e prefix on a general reg is missing. */
3959 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3960 && i.types[op].bitfield.reg16
3961 && (i.tm.operand_types[op].bitfield.reg32
3962 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3963 {
3964 /* Prohibit these changes in the 64bit mode, since the
3965 lowering is more complicated. */
3966 if (flag_code == CODE_64BIT)
252b5132 3967 {
2ca3ace5
L		 3968 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3969 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3970 i.suffix);
3971 return 0;
252b5132 3972 }
29b0f896
AM		 3973#if REGISTER_WARNINGS
3974 else
a540244d
L		 3975 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3976 register_prefix,
29b0f896 3977 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3978 register_prefix,
29b0f896
AM		 3979 i.op[op].regs->reg_name,
3980 i.suffix);
3981#endif
252b5132 3982 }
29b0f896 3983 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3984 else if (i.types[op].bitfield.reg64
3985 && (i.tm.operand_types[op].bitfield.reg32
3986 || i.tm.operand_types[op].bitfield.acc))
252b5132 3987 {
34828aad 3988 if (intel_syntax
ca61edf2 3989 && i.tm.opcode_modifier.toqword
40fb9820 3990 && !i.types[0].bitfield.regxmm)
34828aad 3991 {
ca61edf2 3992 /* Convert to QWORD. We want REX byte. */
34828aad
L		 3993 i.suffix = QWORD_MNEM_SUFFIX;
3994 }
3995 else
3996 {
3997 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3998 register_prefix, i.op[op].regs->reg_name,
3999 i.suffix);
4000 return 0;
4001 }
29b0f896
AM		 4002 }
4003 return 1;
4004}
252b5132 4005
29b0f896 4006static int
e3bb37b5 4007check_qword_reg (void)
29b0f896
AM		 4008{
4009 int op;
252b5132 4010
29b0f896
AM		 4011 for (op = i.operands; --op >= 0; )
4012 /* Reject eight bit registers, except where the template requires
4013 them. (eg. movzb) */
40fb9820
L		 4014 if (i.types[op].bitfield.reg8
4015 && (i.tm.operand_types[op].bitfield.reg16
4016 || i.tm.operand_types[op].bitfield.reg32
4017 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4018 {
a540244d
L		 4019 as_bad (_("`%s%s' not allowed with `%s%c'"),
4020 register_prefix,
29b0f896
AM		 4021 i.op[op].regs->reg_name,
4022 i.tm.name,
4023 i.suffix);
4024 return 0;
4025 }
4026 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4027 else if ((i.types[op].bitfield.reg16
4028 || i.types[op].bitfield.reg32)
4029 && (i.tm.operand_types[op].bitfield.reg32
4030 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4031 {
4032 /* Prohibit these changes in the 64bit mode, since the
4033 lowering is more complicated. */
34828aad 4034 if (intel_syntax
ca61edf2 4035 && i.tm.opcode_modifier.todword
40fb9820 4036 && !i.types[0].bitfield.regxmm)
34828aad 4037 {
ca61edf2 4038 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4039 i.suffix = LONG_MNEM_SUFFIX;
4040 }
4041 else
4042 {
4043 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4044 register_prefix, i.op[op].regs->reg_name,
4045 i.suffix);
4046 return 0;
4047 }
252b5132 4048 }
29b0f896
AM		 4049 return 1;
4050}
252b5132 4051
29b0f896 4052static int
e3bb37b5 4053check_word_reg (void)
29b0f896
AM		 4054{
4055 int op;
4056 for (op = i.operands; --op >= 0;)
4057 /* Reject eight bit registers, except where the template requires
4058 them. (eg. movzb) */
40fb9820
L		 4059 if (i.types[op].bitfield.reg8
4060 && (i.tm.operand_types[op].bitfield.reg16
4061 || i.tm.operand_types[op].bitfield.reg32
4062 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4063 {
a540244d
L		 4064 as_bad (_("`%s%s' not allowed with `%s%c'"),
4065 register_prefix,
29b0f896
AM		 4066 i.op[op].regs->reg_name,
4067 i.tm.name,
4068 i.suffix);
4069 return 0;
4070 }
4071 /* Warn if the e prefix on a general reg is present. */
4072 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4073 && i.types[op].bitfield.reg32
4074 && (i.tm.operand_types[op].bitfield.reg16
4075 || i.tm.operand_types[op].bitfield.acc))
252b5132 4076 {
29b0f896
AM		 4077 /* Prohibit these changes in the 64bit mode, since the
4078 lowering is more complicated. */
4079 if (flag_code == CODE_64BIT)
252b5132 4080 {
2ca3ace5
L		 4081 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4082 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4083 i.suffix);
4084 return 0;
252b5132 4085 }
29b0f896
AM		 4086 else
4087#if REGISTER_WARNINGS
a540244d
L		 4088 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4089 register_prefix,
29b0f896 4090 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4091 register_prefix,
29b0f896
AM		 4092 i.op[op].regs->reg_name,
4093 i.suffix);
4094#endif
4095 }
4096 return 1;
4097}
252b5132 4098
29b0f896 4099static int
40fb9820 4100update_imm (unsigned int j)
29b0f896 4101{
40fb9820
L		 4102 i386_operand_type overlap;
4103
c6fb90c8 4104 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 4105 if ((overlap.bitfield.imm8
4106 || overlap.bitfield.imm8s
4107 || overlap.bitfield.imm16
4108 || overlap.bitfield.imm32
4109 || overlap.bitfield.imm32s
4110 || overlap.bitfield.imm64)
0dfbf9d7
L		 4111 && !operand_type_equal (&overlap, &imm8)
4112 && !operand_type_equal (&overlap, &imm8s)
4113 && !operand_type_equal (&overlap, &imm16)
4114 && !operand_type_equal (&overlap, &imm32)
4115 && !operand_type_equal (&overlap, &imm32s)
4116 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4117 {
4118 if (i.suffix)
4119 {
40fb9820
L		 4120 i386_operand_type temp;
4121
0dfbf9d7 4122 operand_type_set (&temp, 0);
40fb9820
L		 4123 if (i.suffix == BYTE_MNEM_SUFFIX)
4124 {
4125 temp.bitfield.imm8 = overlap.bitfield.imm8;
4126 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4127 }
4128 else if (i.suffix == WORD_MNEM_SUFFIX)
4129 temp.bitfield.imm16 = overlap.bitfield.imm16;
4130 else if (i.suffix == QWORD_MNEM_SUFFIX)
4131 {
4132 temp.bitfield.imm64 = overlap.bitfield.imm64;
4133 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4134 }
4135 else
4136 temp.bitfield.imm32 = overlap.bitfield.imm32;
4137 overlap = temp;
29b0f896 4138 }
0dfbf9d7
L		 4139 else if (operand_type_equal (&overlap, &imm16_32_32s)
4140 || operand_type_equal (&overlap, &imm16_32)
4141 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4142 {
40fb9820 4143 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4144 overlap = imm16;
40fb9820 4145 else
65da13b5 4146 overlap = imm32s;
29b0f896 4147 }
0dfbf9d7
L		 4148 if (!operand_type_equal (&overlap, &imm8)
4149 && !operand_type_equal (&overlap, &imm8s)
4150 && !operand_type_equal (&overlap, &imm16)
4151 && !operand_type_equal (&overlap, &imm32)
4152 && !operand_type_equal (&overlap, &imm32s)
4153 && !operand_type_equal (&overlap, &imm64))
29b0f896 4154 {
4eed87de
AM		 4155 as_bad (_("no instruction mnemonic suffix given; "
4156 "can't determine immediate size"));
29b0f896
AM		 4157 return 0;
4158 }
4159 }
40fb9820 4160 i.types[j] = overlap;
29b0f896 4161
40fb9820
L		 4162 return 1;
4163}
4164
4165static int
4166finalize_imm (void)
4167{
4168 unsigned int j;
29b0f896 4169
40fb9820
L		 4170 for (j = 0; j < 2; j++)
4171 if (update_imm (j) == 0)
4172 return 0;
4173
c6fb90c8 4174 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 4175 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 4176
4177 return 1;
4178}
4179
85f10a01
MM		 4180static void
4181process_drex (void)
4182{
5dd15031
JJ		 4183 i.drex.modrm_reg = 0;
4184 i.drex.modrm_regmem = 0;
85f10a01
MM		 4185
4186 /* SSE5 4 operand instructions must have the destination the same as
4187 one of the inputs. Figure out the destination register and cache
4188 it away in the drex field, and remember which fields to use for
4189 the modrm byte. */
4190 if (i.tm.opcode_modifier.drex
4191 && i.tm.opcode_modifier.drexv
4192 && i.operands == 4)
4193 {
4194 i.tm.extension_opcode = None;
4195
4196 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4197 if (i.types[0].bitfield.regxmm != 0
4198 && i.types[1].bitfield.regxmm != 0
4199 && i.types[2].bitfield.regxmm != 0
4200 && i.types[3].bitfield.regxmm != 0
4201 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4202 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4203 {
4204 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4205 operand_type_set (&i.types[0], 0);
4206 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4207 i.reg_operands -= 2;
4208
4209 /* There are two different ways to encode a 4 operand
4210 instruction with all registers that uses OC1 set to
4211 0 or 1. Favor setting OC1 to 0 since this mimics the
4212 actions of other SSE5 assemblers. Use modrm encoding 2
4213 for register/register. Include the high order bit that
4214 is normally stored in the REX byte in the register
4215 field. */
4216 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4217 i.drex.modrm_reg = 2;
4218 i.drex.modrm_regmem = 1;
4219 i.drex.reg = (i.op[3].regs->reg_num
4220 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4221 }
4222
4223 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4224 else if (i.types[0].bitfield.regxmm != 0
4225 && i.types[1].bitfield.regxmm != 0
4226 && (i.types[2].bitfield.regxmm
4227 || operand_type_check (i.types[2], anymem))
4228 && i.types[3].bitfield.regxmm != 0
4229 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4230 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4231 {
4232 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4233 operand_type_set (&i.types[0], 0);
4234 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4235 i.reg_operands -= 2;
4236
4237 /* Specify the modrm encoding for memory addressing. Include
4238 the high order bit that is normally stored in the REX byte
4239 in the register field. */
4240 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4241 i.drex.modrm_reg = 1;
4242 i.drex.modrm_regmem = 2;
4243 i.drex.reg = (i.op[3].regs->reg_num
4244 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4245 }
4246
4247 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4248 else if (i.types[0].bitfield.regxmm != 0
4249 && operand_type_check (i.types[1], anymem) != 0
4250 && i.types[2].bitfield.regxmm != 0
4251 && i.types[3].bitfield.regxmm != 0
4252 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4253 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4254 {
4255 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4256 operand_type_set (&i.types[0], 0);
4257 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4258 i.reg_operands -= 2;
4259
4260 /* Specify the modrm encoding for memory addressing. Include
4261 the high order bit that is normally stored in the REX byte
4262 in the register field. */
4263 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4264 i.drex.modrm_reg = 2;
4265 i.drex.modrm_regmem = 1;
4266 i.drex.reg = (i.op[3].regs->reg_num
4267 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4268 }
4269
4270 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4271 else if (i.types[0].bitfield.regxmm != 0
4272 && i.types[1].bitfield.regxmm != 0
4273 && i.types[2].bitfield.regxmm != 0
4274 && i.types[3].bitfield.regxmm != 0
4275 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4276 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4277 {
4278 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4279 operand_type_set (&i.types[2], 0);
4280 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4281 i.reg_operands -= 2;
4282
4283 /* There are two different ways to encode a 4 operand
4284 instruction with all registers that uses OC1 set to
4285 0 or 1. Favor setting OC1 to 0 since this mimics the
4286 actions of other SSE5 assemblers. Use modrm encoding
4287 2 for register/register. Include the high order bit that
4288 is normally stored in the REX byte in the register
4289 field. */
4290 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4291 i.drex.modrm_reg = 1;
4292 i.drex.modrm_regmem = 0;
4293
4294 /* Remember the register, including the upper bits */
4295 i.drex.reg = (i.op[3].regs->reg_num
4296 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4297 }
4298
4299 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4300 else if (i.types[0].bitfield.regxmm != 0
4301 && (i.types[1].bitfield.regxmm
4302 || operand_type_check (i.types[1], anymem))
4303 && i.types[2].bitfield.regxmm != 0
4304 && i.types[3].bitfield.regxmm != 0
4305 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4306 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4307 {
4308 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4309 operand_type_set (&i.types[2], 0);
4310 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4311 i.reg_operands -= 2;
4312
4313 /* Specify the modrm encoding and remember the register
4314 including the bits normally stored in the REX byte. */
4315 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4316 i.drex.modrm_reg = 0;
4317 i.drex.modrm_regmem = 1;
4318 i.drex.reg = (i.op[3].regs->reg_num
4319 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4320 }
4321
4322 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4323 else if (operand_type_check (i.types[0], anymem) != 0
4324 && i.types[1].bitfield.regxmm != 0
4325 && i.types[2].bitfield.regxmm != 0
4326 && i.types[3].bitfield.regxmm != 0
4327 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4328 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4329 {
4330 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4331 operand_type_set (&i.types[2], 0);
4332 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4333 i.reg_operands -= 2;
4334
4335 /* Specify the modrm encoding and remember the register
4336 including the bits normally stored in the REX byte. */
4337 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4338 i.drex.modrm_reg = 1;
4339 i.drex.modrm_regmem = 0;
4340 i.drex.reg = (i.op[3].regs->reg_num
4341 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4342 }
4343
4344 else
4345 as_bad (_("Incorrect operands for the '%s' instruction"),
4346 i.tm.name);
4347 }
4348
4349 /* SSE5 instructions with the DREX byte where the only memory operand
4350 is in the 2nd argument, and the first and last xmm register must
4351 match, and is encoded in the DREX byte. */
4352 else if (i.tm.opcode_modifier.drex
4353 && !i.tm.opcode_modifier.drexv
4354 && i.operands == 4)
4355 {
4356 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4357 if (i.types[0].bitfield.regxmm != 0
4358 && (i.types[1].bitfield.regxmm
4359 || operand_type_check(i.types[1], anymem))
4360 && i.types[2].bitfield.regxmm != 0
4361 && i.types[3].bitfield.regxmm != 0
4362 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4363 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4364 {
4365 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4366 operand_type_set (&i.types[0], 0);
4367 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4368 i.reg_operands -= 2;
4369
4370 /* Specify the modrm encoding and remember the register
4371 including the high bit normally stored in the REX
4372 byte. */
4373 i.drex.modrm_reg = 2;
4374 i.drex.modrm_regmem = 1;
4375 i.drex.reg = (i.op[3].regs->reg_num
4376 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4377 }
4378
4379 else
4380 as_bad (_("Incorrect operands for the '%s' instruction"),
4381 i.tm.name);
4382 }
4383
4384 /* SSE5 3 operand instructions that the result is a register, being
4385 either operand can be a memory operand, using OC0 to note which
4386 one is the memory. */
4387 else if (i.tm.opcode_modifier.drex
4388 && i.tm.opcode_modifier.drexv
4389 && i.operands == 3)
4390 {
4391 i.tm.extension_opcode = None;
4392
4393 /* Case 1: 3 operand insn, src1 = register. */
4394 if (i.types[0].bitfield.regxmm != 0
4395 && i.types[1].bitfield.regxmm != 0
4396 && i.types[2].bitfield.regxmm != 0)
4397 {
4398 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4399 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4400 i.reg_operands--;
4401
4402 /* Specify the modrm encoding and remember the register
4403 including the high bit normally stored in the REX byte. */
4404 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4405 i.drex.modrm_reg = 1;
4406 i.drex.modrm_regmem = 0;
4407 i.drex.reg = (i.op[2].regs->reg_num
4408 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4409 }
4410
4411 /* Case 2: 3 operand insn, src1 = memory. */
4412 else if (operand_type_check (i.types[0], anymem) != 0
4413 && i.types[1].bitfield.regxmm != 0
4414 && i.types[2].bitfield.regxmm != 0)
4415 {
4416 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4417 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4418 i.reg_operands--;
4419
4420 /* Specify the modrm encoding and remember the register
4421 including the high bit normally stored in the REX
4422 byte. */
4423 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4424 i.drex.modrm_reg = 1;
4425 i.drex.modrm_regmem = 0;
4426 i.drex.reg = (i.op[2].regs->reg_num
4427 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4428 }
4429
4430 /* Case 3: 3 operand insn, src2 = memory. */
4431 else if (i.types[0].bitfield.regxmm != 0
4432 && operand_type_check (i.types[1], anymem) != 0
4433 && i.types[2].bitfield.regxmm != 0)
4434 {
4435 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4436 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4437 i.reg_operands--;
4438
4439 /* Specify the modrm encoding and remember the register
4440 including the high bit normally stored in the REX byte. */
4441 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4442 i.drex.modrm_reg = 0;
4443 i.drex.modrm_regmem = 1;
4444 i.drex.reg = (i.op[2].regs->reg_num
4445 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4446 }
4447
4448 else
4449 as_bad (_("Incorrect operands for the '%s' instruction"),
4450 i.tm.name);
4451 }
4452
4453 /* SSE5 4 operand instructions that are the comparison instructions
4454 where the first operand is the immediate value of the comparison
4455 to be done. */
4456 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4457 {
4458 /* Case 1: 4 operand insn, src1 = reg/memory. */
4459 if (operand_type_check (i.types[0], imm) != 0
4460 && (i.types[1].bitfield.regxmm
4461 || operand_type_check (i.types[1], anymem))
4462 && i.types[2].bitfield.regxmm != 0
4463 && i.types[3].bitfield.regxmm != 0)
4464 {
4465 /* clear the arguments that are stored in drex */
0dfbf9d7 4466 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4467 i.reg_operands--;
4468
4469 /* Specify the modrm encoding and remember the register
4470 including the high bit normally stored in the REX byte. */
4471 i.drex.modrm_reg = 2;
4472 i.drex.modrm_regmem = 1;
4473 i.drex.reg = (i.op[3].regs->reg_num
4474 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4475 }
4476
4477 /* Case 2: 3 operand insn with ImmExt that places the
4478 opcode_extension as an immediate argument. This is used for
4479 all of the varients of comparison that supplies the appropriate
4480 value as part of the instruction. */
4481 else if ((i.types[0].bitfield.regxmm
4482 || operand_type_check (i.types[0], anymem))
4483 && i.types[1].bitfield.regxmm != 0
4484 && i.types[2].bitfield.regxmm != 0
4485 && operand_type_check (i.types[3], imm) != 0)
4486 {
4487 /* clear the arguments that are stored in drex */
0dfbf9d7 4488 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4489 i.reg_operands--;
4490
4491 /* Specify the modrm encoding and remember the register
4492 including the high bit normally stored in the REX byte. */
4493 i.drex.modrm_reg = 1;
4494 i.drex.modrm_regmem = 0;
4495 i.drex.reg = (i.op[2].regs->reg_num
4496 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4497 }
4498
4499 else
4500 as_bad (_("Incorrect operands for the '%s' instruction"),
4501 i.tm.name);
4502 }
4503
4504 else if (i.tm.opcode_modifier.drex
4505 || i.tm.opcode_modifier.drexv
4506 || i.tm.opcode_modifier.drexc)
4507 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4508}
4509
29b0f896 4510static int
e3bb37b5 4511process_operands (void)
29b0f896
AM		 4512{
4513 /* Default segment register this instruction will use for memory
4514 accesses. 0 means unknown. This is only for optimizing out
4515 unnecessary segment overrides. */
4516 const seg_entry *default_seg = 0;
4517
85f10a01
MM		 4518 /* Handle all of the DREX munging that SSE5 needs. */
4519 if (i.tm.opcode_modifier.drex
4520 || i.tm.opcode_modifier.drexv
4521 || i.tm.opcode_modifier.drexc)
4522 process_drex ();
4523
e2ec9d29 4524 if (i.tm.opcode_modifier.firstxmm0)
29b0f896 4525 {
9fcfb3d7
L		 4526 unsigned int j;
4527
e2ec9d29 4528 /* The first operand is implicit and must be xmm0. */
0dfbf9d7
L		 4529 assert (i.reg_operands
4530 && operand_type_equal (&i.types[0], &regxmm));
e2ec9d29
L		 4531 if (i.op[0].regs->reg_num != 0)
4532 {
4533 if (intel_syntax)
4534 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4535 i.tm.name, register_prefix);
4536 else
4537 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4538 i.tm.name, register_prefix);
4539 return 0;
4540 }
9fcfb3d7
L		 4541
4542 for (j = 1; j < i.operands; j++)
4543 {
4544 i.op[j - 1] = i.op[j];
4545 i.types[j - 1] = i.types[j];
4546
4547 /* We need to adjust fields in i.tm since they are used by
4548 build_modrm_byte. */
4549 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4550 }
4551
e2ec9d29
L		 4552 i.operands--;
4553 i.reg_operands--;
e2ec9d29
L		 4554 i.tm.operands--;
4555 }
4556 else if (i.tm.opcode_modifier.regkludge)
4557 {
4558 /* The imul $imm, %reg instruction is converted into
4559 imul $imm, %reg, %reg, and the clr %reg instruction
4560 is converted into xor %reg, %reg. */
4561
4562 unsigned int first_reg_op;
4563
4564 if (operand_type_check (i.types[0], reg))
4565 first_reg_op = 0;
4566 else
4567 first_reg_op = 1;
4568 /* Pretend we saw the extra register operand. */
4569 assert (i.reg_operands == 1
4570 && i.op[first_reg_op + 1].regs == 0);
4571 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4572 i.types[first_reg_op + 1] = i.types[first_reg_op];
4573 i.operands++;
4574 i.reg_operands++;
29b0f896
AM		 4575 }
4576
40fb9820 4577 if (i.tm.opcode_modifier.shortform)
29b0f896 4578 {
40fb9820
L		 4579 if (i.types[0].bitfield.sreg2
4580 || i.types[0].bitfield.sreg3)
29b0f896 4581 {
4eed87de
AM		 4582 if (i.tm.base_opcode == POP_SEG_SHORT
4583 && i.op[0].regs->reg_num == 1)
29b0f896 4584 {
4eed87de
AM		 4585 as_bad (_("you can't `pop %%cs'"));
4586 return 0;
29b0f896 4587 }
4eed87de
AM		 4588 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4589 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4590 i.rex |= REX_B;
4eed87de
AM		 4591 }
4592 else
4593 {
85f10a01
MM		 4594 /* The register or float register operand is in operand
4595 0 or 1. */
40fb9820
L		 4596 unsigned int op;
4597
4598 if (i.types[0].bitfield.floatreg
4599 || operand_type_check (i.types[0], reg))
4600 op = 0;
4601 else
4602 op = 1;
4eed87de
AM		 4603 /* Register goes in low 3 bits of opcode. */
4604 i.tm.base_opcode |= i.op[op].regs->reg_num;
4605 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4606 i.rex |= REX_B;
40fb9820 4607 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4608 {
4eed87de
AM		 4609 /* Warn about some common errors, but press on regardless.
4610 The first case can be generated by gcc (<= 2.8.1). */
4611 if (i.operands == 2)
4612 {
4613 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4614 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4615 register_prefix, i.op[1].regs->reg_name,
4616 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4617 }
4618 else
4619 {
4620 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4621 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4622 register_prefix, i.op[0].regs->reg_name);
4eed87de 4623 }
29b0f896
AM		 4624 }
4625 }
4626 }
40fb9820 4627 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4628 {
4629 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4630 must be put into the modrm byte). Now, we make the modrm and
4631 index base bytes based on all the info we've collected. */
29b0f896
AM		 4632
4633 default_seg = build_modrm_byte ();
4634 }
8a2ed489 4635 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4636 {
4637 default_seg = &ds;
4638 }
40fb9820 4639 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4640 {
4641 /* For the string instructions that allow a segment override
4642 on one of their operands, the default segment is ds. */
4643 default_seg = &ds;
4644 }
4645
75178d9d
L		 4646 if (i.tm.base_opcode == 0x8d /* lea */
4647 && i.seg[0]
4648 && !quiet_warnings)
30123838 4649 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4650
4651 /* If a segment was explicitly specified, and the specified segment
4652 is not the default, use an opcode prefix to select it. If we
4653 never figured out what the default segment is, then default_seg
4654 will be zero at this point, and the specified segment prefix will
4655 always be used. */
29b0f896
AM		 4656 if ((i.seg[0]) && (i.seg[0] != default_seg))
4657 {
4658 if (!add_prefix (i.seg[0]->seg_prefix))
4659 return 0;
4660 }
4661 return 1;
4662}
4663
4664static const seg_entry *
e3bb37b5 4665build_modrm_byte (void)
29b0f896
AM		 4666{
4667 const seg_entry *default_seg = 0;
4668
85f10a01
MM		 4669 /* SSE5 4 operand instructions are encoded in such a way that one of
4670 the inputs must match the destination register. Process_drex hides
4671 the 3rd argument in the drex field, so that by the time we get
4672 here, it looks to GAS as if this is a 2 operand instruction. */
4673 if ((i.tm.opcode_modifier.drex
4674 || i.tm.opcode_modifier.drexv
b5016f89 4675 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4676 && i.reg_operands == 2)
4677 {
4678 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4679 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4680
4681 i.rm.reg = reg->reg_num;
4682 i.rm.regmem = regmem->reg_num;
4683 i.rm.mode = 3;
4684 if ((reg->reg_flags & RegRex) != 0)
4685 i.rex |= REX_R;
4686 if ((regmem->reg_flags & RegRex) != 0)
4687 i.rex |= REX_B;
4688 }
4689
29b0f896
AM		 4690 /* i.reg_operands MUST be the number of real register operands;
4691 implicit registers do not count. */
85f10a01 4692 else if (i.reg_operands == 2)
29b0f896
AM		 4693 {
4694 unsigned int source, dest;
cab737b9
L		 4695
4696 switch (i.operands)
4697 {
4698 case 2:
4699 source = 0;
4700 break;
4701 case 3:
c81128dc
L		 4702 /* When there are 3 operands, one of them may be immediate,
4703 which may be the first or the last operand. Otherwise,
4704 the first operand must be shift count register (cl). */
4705 assert (i.imm_operands == 1
4706 || (i.imm_operands == 0
40fb9820
L		 4707 && i.types[0].bitfield.shiftcount));
4708 if (operand_type_check (i.types[0], imm)
4709 || i.types[0].bitfield.shiftcount)
4710 source = 1;
4711 else
4712 source = 0;
cab737b9
L		 4713 break;
4714 case 4:
368d64cc
L		 4715 /* When there are 4 operands, the first two must be 8bit
4716 immediate operands. The source operand will be the 3rd
4717 one. */
cab737b9 4718 assert (i.imm_operands == 2
368d64cc
L		 4719 && i.types[0].bitfield.imm8
4720 && i.types[1].bitfield.imm8);
cab737b9
L		 4721 source = 2;
4722 break;
4723 default:
4724 abort ();
4725 }
4726
29b0f896
AM		 4727 dest = source + 1;
4728
4729 i.rm.mode = 3;
4730 /* One of the register operands will be encoded in the i.tm.reg
4731 field, the other in the combined i.tm.mode and i.tm.regmem
4732 fields. If no form of this instruction supports a memory
4733 destination operand, then we assume the source operand may
4734 sometimes be a memory operand and so we need to store the
4735 destination in the i.rm.reg field. */
40fb9820
L		 4736 if (!i.tm.operand_types[dest].bitfield.regmem
4737 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4738 {
4739 i.rm.reg = i.op[dest].regs->reg_num;
4740 i.rm.regmem = i.op[source].regs->reg_num;
4741 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4742 i.rex |= REX_R;
29b0f896 4743 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4744 i.rex |= REX_B;
29b0f896
AM		 4745 }
4746 else
4747 {
4748 i.rm.reg = i.op[source].regs->reg_num;
4749 i.rm.regmem = i.op[dest].regs->reg_num;
4750 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4751 i.rex |= REX_B;
29b0f896 4752 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4753 i.rex |= REX_R;
29b0f896 4754 }
161a04f6 4755 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4756 {
40fb9820
L		 4757 if (!i.types[0].bitfield.control
4758 && !i.types[1].bitfield.control)
c4a530c5 4759 abort ();
161a04f6 4760 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4761 add_prefix (LOCK_PREFIX_OPCODE);
4762 }
29b0f896
AM		 4763 }
4764 else
4765 { /* If it's not 2 reg operands... */
4766 if (i.mem_operands)
4767 {
4768 unsigned int fake_zero_displacement = 0;
99018f42 4769 unsigned int op;
4eed87de 4770
85f10a01
MM		 4771 /* This has been precalculated for SSE5 instructions
4772 that have a DREX field earlier in process_drex. */
b5016f89
L		 4773 if (i.tm.opcode_modifier.drex
4774 || i.tm.opcode_modifier.drexv
4775 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4776 op = i.drex.modrm_regmem;
4777 else
4778 {
c0209578
L		 4779 for (op = 0; op < i.operands; op++)
4780 if (operand_type_check (i.types[op], anymem))
4781 break;
4782 assert (op < i.operands);
85f10a01 4783 }
29b0f896
AM		 4784
4785 default_seg = &ds;
4786
4787 if (i.base_reg == 0)
4788 {
4789 i.rm.mode = 0;
4790 if (!i.disp_operands)
4791 fake_zero_displacement = 1;
4792 if (i.index_reg == 0)
4793 {
4794 /* Operand is just <disp> */
20f0a1fc 4795 if (flag_code == CODE_64BIT)
29b0f896
AM		 4796 {
4797 /* 64bit mode overwrites the 32bit absolute
4798 addressing by RIP relative addressing and
4799 absolute addressing is encoded by one of the
4800 redundant SIB forms. */
4801 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4802 i.sib.base = NO_BASE_REGISTER;
4803 i.sib.index = NO_INDEX_REGISTER;
fc225355 4804 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4805 ? disp32s : disp32);
20f0a1fc 4806 }
fc225355
L		 4807 else if ((flag_code == CODE_16BIT)
4808 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4809 {
4810 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4811 i.types[op] = disp16;
20f0a1fc
NC		 4812 }
4813 else
4814 {
4815 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4816 i.types[op] = disp32;
29b0f896
AM		 4817 }
4818 }
4819 else /* !i.base_reg && i.index_reg */
4820 {
db51cc60
L		 4821 if (i.index_reg->reg_num == RegEiz
4822 || i.index_reg->reg_num == RegRiz)
4823 i.sib.index = NO_INDEX_REGISTER;
4824 else
4825 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4826 i.sib.base = NO_BASE_REGISTER;
4827 i.sib.scale = i.log2_scale_factor;
4828 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4829 i.types[op].bitfield.disp8 = 0;
4830 i.types[op].bitfield.disp16 = 0;
4831 i.types[op].bitfield.disp64 = 0;
29b0f896 4832 if (flag_code != CODE_64BIT)
40fb9820
L		 4833 {
4834 /* Must be 32 bit */
4835 i.types[op].bitfield.disp32 = 1;
4836 i.types[op].bitfield.disp32s = 0;
4837 }
29b0f896 4838 else
40fb9820
L		 4839 {
4840 i.types[op].bitfield.disp32 = 0;
4841 i.types[op].bitfield.disp32s = 1;
4842 }
29b0f896 4843 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4844 i.rex |= REX_X;
29b0f896
AM		 4845 }
4846 }
4847 /* RIP addressing for 64bit mode. */
9a04903e
JB		 4848 else if (i.base_reg->reg_num == RegRip ||
4849 i.base_reg->reg_num == RegEip)
29b0f896
AM		 4850 {
4851 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4852 i.types[op].bitfield.disp8 = 0;
4853 i.types[op].bitfield.disp16 = 0;
4854 i.types[op].bitfield.disp32 = 0;
4855 i.types[op].bitfield.disp32s = 1;
4856 i.types[op].bitfield.disp64 = 0;
71903a11 4857 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4858 if (! i.disp_operands)
4859 fake_zero_displacement = 1;
29b0f896 4860 }
40fb9820 4861 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4862 {
4863 switch (i.base_reg->reg_num)
4864 {
4865 case 3: /* (%bx) */
4866 if (i.index_reg == 0)
4867 i.rm.regmem = 7;
4868 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4869 i.rm.regmem = i.index_reg->reg_num - 6;
4870 break;
4871 case 5: /* (%bp) */
4872 default_seg = &ss;
4873 if (i.index_reg == 0)
4874 {
4875 i.rm.regmem = 6;
40fb9820 4876 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4877 {
4878 /* fake (%bp) into 0(%bp) */
40fb9820 4879 i.types[op].bitfield.disp8 = 1;
252b5132 4880 fake_zero_displacement = 1;
29b0f896
AM		 4881 }
4882 }
4883 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4884 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4885 break;
4886 default: /* (%si) -> 4 or (%di) -> 5 */
4887 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4888 }
4889 i.rm.mode = mode_from_disp_size (i.types[op]);
4890 }
4891 else /* i.base_reg and 32/64 bit mode */
4892 {
4893 if (flag_code == CODE_64BIT
40fb9820
L		 4894 && operand_type_check (i.types[op], disp))
4895 {
4896 i386_operand_type temp;
0dfbf9d7 4897 operand_type_set (&temp, 0);
40fb9820
L		 4898 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4899 i.types[op] = temp;
4900 if (i.prefix[ADDR_PREFIX] == 0)
4901 i.types[op].bitfield.disp32s = 1;
4902 else
4903 i.types[op].bitfield.disp32 = 1;
4904 }
20f0a1fc 4905
29b0f896
AM		 4906 i.rm.regmem = i.base_reg->reg_num;
4907 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4908 i.rex |= REX_B;
29b0f896
AM		 4909 i.sib.base = i.base_reg->reg_num;
4910 /* x86-64 ignores REX prefix bit here to avoid decoder
4911 complications. */
4912 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4913 {
4914 default_seg = &ss;
4915 if (i.disp_operands == 0)
4916 {
4917 fake_zero_displacement = 1;
40fb9820 4918 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4919 }
4920 }
4921 else if (i.base_reg->reg_num == ESP_REG_NUM)
4922 {
4923 default_seg = &ss;
4924 }
4925 i.sib.scale = i.log2_scale_factor;
4926 if (i.index_reg == 0)
4927 {
4928 /* <disp>(%esp) becomes two byte modrm with no index
4929 register. We've already stored the code for esp
4930 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4931 Any base register besides %esp will not use the
4932 extra modrm byte. */
4933 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 4934 }
4935 else
4936 {
db51cc60
L		 4937 if (i.index_reg->reg_num == RegEiz
4938 || i.index_reg->reg_num == RegRiz)
4939 i.sib.index = NO_INDEX_REGISTER;
4940 else
4941 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4942 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4943 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4944 i.rex |= REX_X;
29b0f896 4945 }
67a4f2b7
AO		 4946
4947 if (i.disp_operands
4948 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4949 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4950 i.rm.mode = 0;
4951 else
4952 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4953 }
252b5132 4954
29b0f896
AM		 4955 if (fake_zero_displacement)
4956 {
4957 /* Fakes a zero displacement assuming that i.types[op]
4958 holds the correct displacement size. */
4959 expressionS *exp;
4960
4961 assert (i.op[op].disps == 0);
4962 exp = &disp_expressions[i.disp_operands++];
4963 i.op[op].disps = exp;
4964 exp->X_op = O_constant;
4965 exp->X_add_number = 0;
4966 exp->X_add_symbol = (symbolS *) 0;
4967 exp->X_op_symbol = (symbolS *) 0;
4968 }
4969 }
252b5132 4970
29b0f896
AM		 4971 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4972 (if any) based on i.tm.extension_opcode. Again, we must be
4973 careful to make sure that segment/control/debug/test/MMX
4974 registers are coded into the i.rm.reg field. */
4975 if (i.reg_operands)
4976 {
99018f42
L		 4977 unsigned int op;
4978
85f10a01
MM		 4979 /* This has been precalculated for SSE5 instructions
4980 that have a DREX field earlier in process_drex. */
b5016f89
L		 4981 if (i.tm.opcode_modifier.drex
4982 || i.tm.opcode_modifier.drexv
4983 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4984 {
4985 op = i.drex.modrm_reg;
4986 i.rm.reg = i.op[op].regs->reg_num;
4987 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4988 i.rex |= REX_R;
4989 }
4990 else
4991 {
c0209578
L		 4992 for (op = 0; op < i.operands; op++)
4993 if (i.types[op].bitfield.reg8
4994 || i.types[op].bitfield.reg16
4995 || i.types[op].bitfield.reg32
4996 || i.types[op].bitfield.reg64
4997 || i.types[op].bitfield.regmmx
4998 || i.types[op].bitfield.regxmm
4999 || i.types[op].bitfield.sreg2
5000 || i.types[op].bitfield.sreg3
5001 || i.types[op].bitfield.control
5002 || i.types[op].bitfield.debug
5003 || i.types[op].bitfield.test)
5004 break;
5005
5006 assert (op < i.operands);
99018f42 5007
85f10a01
MM		 5008 /* If there is an extension opcode to put here, the
5009 register number must be put into the regmem field. */
c0209578
L		 5010 if (i.tm.extension_opcode != None)
5011 {
5012 i.rm.regmem = i.op[op].regs->reg_num;
5013 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5014 i.rex |= REX_B;
5015 }
5016 else
5017 {
5018 i.rm.reg = i.op[op].regs->reg_num;
5019 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5020 i.rex |= REX_R;
5021 }
85f10a01 5022 }
252b5132 5023
29b0f896
AM		 5024 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5025 must set it to 3 to indicate this is a register operand
5026 in the regmem field. */
5027 if (!i.mem_operands)
5028 i.rm.mode = 3;
5029 }
252b5132 5030
29b0f896 5031 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 5032 if (i.tm.extension_opcode != None
5033 && !(i.tm.opcode_modifier.drex
5034 || i.tm.opcode_modifier.drexv
5035 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 5036 i.rm.reg = i.tm.extension_opcode;
5037 }
5038 return default_seg;
5039}
252b5132 5040
29b0f896 5041static void
e3bb37b5 5042output_branch (void)
29b0f896
AM		 5043{
5044 char *p;
5045 int code16;
5046 int prefix;
5047 relax_substateT subtype;
5048 symbolS *sym;
5049 offsetT off;
5050
5051 code16 = 0;
5052 if (flag_code == CODE_16BIT)
5053 code16 = CODE16;
5054
5055 prefix = 0;
5056 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5057 {
29b0f896
AM		 5058 prefix = 1;
5059 i.prefixes -= 1;
5060 code16 ^= CODE16;
252b5132 5061 }
29b0f896
AM		 5062 /* Pentium4 branch hints. */
5063 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5064 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5065 {
29b0f896
AM		 5066 prefix++;
5067 i.prefixes--;
5068 }
5069 if (i.prefix[REX_PREFIX] != 0)
5070 {
5071 prefix++;
5072 i.prefixes--;
2f66722d
AM		 5073 }
5074
29b0f896
AM		 5075 if (i.prefixes != 0 && !intel_syntax)
5076 as_warn (_("skipping prefixes on this instruction"));
5077
5078 /* It's always a symbol; End frag & setup for relax.
5079 Make sure there is enough room in this frag for the largest
5080 instruction we may generate in md_convert_frag. This is 2
5081 bytes for the opcode and room for the prefix and largest
5082 displacement. */
5083 frag_grow (prefix + 2 + 4);
5084 /* Prefix and 1 opcode byte go in fr_fix. */
5085 p = frag_more (prefix + 1);
5086 if (i.prefix[DATA_PREFIX] != 0)
5087 *p++ = DATA_PREFIX_OPCODE;
5088 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5089 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5090 *p++ = i.prefix[SEG_PREFIX];
5091 if (i.prefix[REX_PREFIX] != 0)
5092 *p++ = i.prefix[REX_PREFIX];
5093 *p = i.tm.base_opcode;
5094
5095 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5096 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5097 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5098 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5099 else
5100 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5101 subtype |= code16;
3e73aa7c 5102
29b0f896
AM		 5103 sym = i.op[0].disps->X_add_symbol;
5104 off = i.op[0].disps->X_add_number;
3e73aa7c 5105
29b0f896
AM		 5106 if (i.op[0].disps->X_op != O_constant
5107 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5108 {
29b0f896
AM		 5109 /* Handle complex expressions. */
5110 sym = make_expr_symbol (i.op[0].disps);
5111 off = 0;
5112 }
3e73aa7c 5113
29b0f896
AM		 5114 /* 1 possible extra opcode + 4 byte displacement go in var part.
5115 Pass reloc in fr_var. */
5116 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5117}
3e73aa7c 5118
29b0f896 5119static void
e3bb37b5 5120output_jump (void)
29b0f896
AM		 5121{
5122 char *p;
5123 int size;
3e02c1cc 5124 fixS *fixP;
29b0f896 5125
40fb9820 5126 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5127 {
5128 /* This is a loop or jecxz type instruction. */
5129 size = 1;
5130 if (i.prefix[ADDR_PREFIX] != 0)
5131 {
5132 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5133 i.prefixes -= 1;
5134 }
5135 /* Pentium4 branch hints. */
5136 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5137 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5138 {
5139 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5140 i.prefixes--;
3e73aa7c
JH		 5141 }
5142 }
29b0f896
AM		 5143 else
5144 {
5145 int code16;
3e73aa7c 5146
29b0f896
AM		 5147 code16 = 0;
5148 if (flag_code == CODE_16BIT)
5149 code16 = CODE16;
3e73aa7c 5150
29b0f896
AM		 5151 if (i.prefix[DATA_PREFIX] != 0)
5152 {
5153 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5154 i.prefixes -= 1;
5155 code16 ^= CODE16;
5156 }
252b5132 5157
29b0f896
AM		 5158 size = 4;
5159 if (code16)
5160 size = 2;
5161 }
9fcc94b6 5162
29b0f896
AM		 5163 if (i.prefix[REX_PREFIX] != 0)
5164 {
5165 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5166 i.prefixes -= 1;
5167 }
252b5132 5168
29b0f896
AM		 5169 if (i.prefixes != 0 && !intel_syntax)
5170 as_warn (_("skipping prefixes on this instruction"));
e0890092 5171
29b0f896
AM		 5172 p = frag_more (1 + size);
5173 *p++ = i.tm.base_opcode;
e0890092 5174
3e02c1cc
AM		 5175 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5176 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5177
5178 /* All jumps handled here are signed, but don't use a signed limit
5179 check for 32 and 16 bit jumps as we want to allow wrap around at
5180 4G and 64k respectively. */
5181 if (size == 1)
5182 fixP->fx_signed = 1;
29b0f896 5183}
e0890092 5184
29b0f896 5185static void
e3bb37b5 5186output_interseg_jump (void)
29b0f896
AM		 5187{
5188 char *p;
5189 int size;
5190 int prefix;
5191 int code16;
252b5132 5192
29b0f896
AM		 5193 code16 = 0;
5194 if (flag_code == CODE_16BIT)
5195 code16 = CODE16;
a217f122 5196
29b0f896
AM		 5197 prefix = 0;
5198 if (i.prefix[DATA_PREFIX] != 0)
5199 {
5200 prefix = 1;
5201 i.prefixes -= 1;
5202 code16 ^= CODE16;
5203 }
5204 if (i.prefix[REX_PREFIX] != 0)
5205 {
5206 prefix++;
5207 i.prefixes -= 1;
5208 }
252b5132 5209
29b0f896
AM		 5210 size = 4;
5211 if (code16)
5212 size = 2;
252b5132 5213
29b0f896
AM		 5214 if (i.prefixes != 0 && !intel_syntax)
5215 as_warn (_("skipping prefixes on this instruction"));
252b5132 5216
29b0f896
AM		 5217 /* 1 opcode; 2 segment; offset */
5218 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5219
29b0f896
AM		 5220 if (i.prefix[DATA_PREFIX] != 0)
5221 *p++ = DATA_PREFIX_OPCODE;
252b5132 5222
29b0f896
AM		 5223 if (i.prefix[REX_PREFIX] != 0)
5224 *p++ = i.prefix[REX_PREFIX];
252b5132 5225
29b0f896
AM		 5226 *p++ = i.tm.base_opcode;
5227 if (i.op[1].imms->X_op == O_constant)
5228 {
5229 offsetT n = i.op[1].imms->X_add_number;
252b5132 5230
29b0f896
AM		 5231 if (size == 2
5232 && !fits_in_unsigned_word (n)
5233 && !fits_in_signed_word (n))
5234 {
5235 as_bad (_("16-bit jump out of range"));
5236 return;
5237 }
5238 md_number_to_chars (p, n, size);
5239 }
5240 else
5241 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5242 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5243 if (i.op[0].imms->X_op != O_constant)
5244 as_bad (_("can't handle non absolute segment in `%s'"),
5245 i.tm.name);
5246 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5247}
a217f122 5248
29b0f896 5249static void
e3bb37b5 5250output_insn (void)
29b0f896 5251{
2bbd9c25
JJ		 5252 fragS *insn_start_frag;
5253 offsetT insn_start_off;
5254
29b0f896
AM		 5255 /* Tie dwarf2 debug info to the address at the start of the insn.
5256 We can't do this after the insn has been output as the current
5257 frag may have been closed off. eg. by frag_var. */
5258 dwarf2_emit_insn (0);
5259
2bbd9c25
JJ		 5260 insn_start_frag = frag_now;
5261 insn_start_off = frag_now_fix ();
5262
29b0f896 5263 /* Output jumps. */
40fb9820 5264 if (i.tm.opcode_modifier.jump)
29b0f896 5265 output_branch ();
40fb9820
L		 5266 else if (i.tm.opcode_modifier.jumpbyte
5267 || i.tm.opcode_modifier.jumpdword)
29b0f896 5268 output_jump ();
40fb9820 5269 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5270 output_interseg_jump ();
5271 else
5272 {
5273 /* Output normal instructions here. */
5274 char *p;
5275 unsigned char *q;
47465058 5276 unsigned int j;
331d2d0d 5277 unsigned int prefix;
4dffcebc
L		 5278
5279 switch (i.tm.opcode_length)
bc4bd9ab 5280 {
4dffcebc 5281 case 3:
331d2d0d
L		 5282 if (i.tm.base_opcode & 0xff000000)
5283 {
5284 prefix = (i.tm.base_opcode >> 24) & 0xff;
5285 goto check_prefix;
5286 }
4dffcebc
L		 5287 break;
5288 case 2:
5289 if ((i.tm.base_opcode & 0xff0000) != 0)
bc4bd9ab 5290 {
4dffcebc
L		 5291 prefix = (i.tm.base_opcode >> 16) & 0xff;
5292 if (i.tm.cpu_flags.bitfield.cpupadlock)
5293 {
5294check_prefix:
5295 if (prefix != REPE_PREFIX_OPCODE
5296 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5297 add_prefix (prefix);
5298 }
5299 else
bc4bd9ab
MK		 5300 add_prefix (prefix);
5301 }
4dffcebc
L		 5302 break;
5303 case 1:
5304 break;
5305 default:
5306 abort ();
0f10071e 5307 }
252b5132 5308
29b0f896 5309 /* The prefix bytes. */
47465058
L		 5310 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5311 if (*q)
5312 FRAG_APPEND_1_CHAR (*q);
252b5132 5313
29b0f896 5314 /* Now the opcode; be careful about word order here! */
4dffcebc 5315 if (i.tm.opcode_length == 1)
29b0f896
AM		 5316 {
5317 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5318 }
5319 else
5320 {
4dffcebc 5321 switch (i.tm.opcode_length)
331d2d0d 5322 {
4dffcebc 5323 case 3:
331d2d0d
L		 5324 p = frag_more (3);
5325 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5326 break;
5327 case 2:
5328 p = frag_more (2);
5329 break;
5330 default:
5331 abort ();
5332 break;
331d2d0d 5333 }
0f10071e 5334
29b0f896
AM		 5335 /* Put out high byte first: can't use md_number_to_chars! */
5336 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5337 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5338
5339 /* On SSE5, encode the OC1 bit in the DREX field if this
5340 encoding has multiple formats. */
5341 if (i.tm.opcode_modifier.drex
5342 && i.tm.opcode_modifier.drexv
5343 && DREX_OC1 (i.tm.extension_opcode))
5344 *p |= DREX_OC1_MASK;
29b0f896 5345 }
3e73aa7c 5346
29b0f896 5347 /* Now the modrm byte and sib byte (if present). */
40fb9820 5348 if (i.tm.opcode_modifier.modrm)
29b0f896 5349 {
4a3523fa
L		 5350 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5351 | i.rm.reg << 3
5352 | i.rm.mode << 6));
29b0f896
AM		 5353 /* If i.rm.regmem == ESP (4)
5354 && i.rm.mode != (Register mode)
5355 && not 16 bit
5356 ==> need second modrm byte. */
5357 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5358 && i.rm.mode != 3
40fb9820 5359 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5360 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5361 | i.sib.index << 3
5362 | i.sib.scale << 6));
29b0f896 5363 }
3e73aa7c 5364
85f10a01
MM		 5365 /* Write the DREX byte if needed. */
5366 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5367 {
5368 p = frag_more (1);
5369 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5370
5371 /* Encode the OC0 bit if this encoding has multiple
5372 formats. */
5373 if ((i.tm.opcode_modifier.drex
5374 || i.tm.opcode_modifier.drexv)
5375 && DREX_OC0 (i.tm.extension_opcode))
5376 *p |= DREX_OC0_MASK;
5377 }
5378
29b0f896 5379 if (i.disp_operands)
2bbd9c25 5380 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5381
29b0f896 5382 if (i.imm_operands)
2bbd9c25 5383 output_imm (insn_start_frag, insn_start_off);
29b0f896 5384 }
252b5132 5385
29b0f896
AM		 5386#ifdef DEBUG386
5387 if (flag_debug)
5388 {
7b81dfbb 5389 pi ("" /*line*/, &i);
29b0f896
AM		 5390 }
5391#endif /* DEBUG386 */
5392}
252b5132 5393
e205caa7
L		 5394/* Return the size of the displacement operand N. */
5395
5396static int
5397disp_size (unsigned int n)
5398{
5399 int size = 4;
40fb9820
L		 5400 if (i.types[n].bitfield.disp64)
5401 size = 8;
5402 else if (i.types[n].bitfield.disp8)
5403 size = 1;
5404 else if (i.types[n].bitfield.disp16)
5405 size = 2;
e205caa7
L		 5406 return size;
5407}
5408
5409/* Return the size of the immediate operand N. */
5410
5411static int
5412imm_size (unsigned int n)
5413{
5414 int size = 4;
40fb9820
L		 5415 if (i.types[n].bitfield.imm64)
5416 size = 8;
5417 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5418 size = 1;
5419 else if (i.types[n].bitfield.imm16)
5420 size = 2;
e205caa7
L		 5421 return size;
5422}
5423
29b0f896 5424static void
64e74474 5425output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5426{
5427 char *p;
5428 unsigned int n;
252b5132 5429
29b0f896
AM		 5430 for (n = 0; n < i.operands; n++)
5431 {
40fb9820 5432 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5433 {
5434 if (i.op[n].disps->X_op == O_constant)
5435 {
e205caa7 5436 int size = disp_size (n);
29b0f896 5437 offsetT val;
252b5132 5438
29b0f896
AM		 5439 val = offset_in_range (i.op[n].disps->X_add_number,
5440 size);
5441 p = frag_more (size);
5442 md_number_to_chars (p, val, size);
5443 }
5444 else
5445 {
f86103b7 5446 enum bfd_reloc_code_real reloc_type;
e205caa7 5447 int size = disp_size (n);
40fb9820 5448 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5449 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5450
e205caa7 5451 /* We can't have 8 bit displacement here. */
40fb9820 5452 assert (!i.types[n].bitfield.disp8);
e205caa7 5453
29b0f896
AM		 5454 /* The PC relative address is computed relative
5455 to the instruction boundary, so in case immediate
5456 fields follows, we need to adjust the value. */
5457 if (pcrel && i.imm_operands)
5458 {
29b0f896 5459 unsigned int n1;
e205caa7 5460 int sz = 0;
252b5132 5461
29b0f896 5462 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5463 if (operand_type_check (i.types[n1], imm))
252b5132 5464 {
e205caa7
L		 5465 /* Only one immediate is allowed for PC
5466 relative address. */
5467 assert (sz == 0);
5468 sz = imm_size (n1);
5469 i.op[n].disps->X_add_number -= sz;
252b5132 5470 }
29b0f896 5471 /* We should find the immediate. */
e205caa7 5472 assert (sz != 0);
29b0f896 5473 }
520dc8e8 5474
29b0f896 5475 p = frag_more (size);
2bbd9c25 5476 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5477 if (GOT_symbol
2bbd9c25 5478 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5479 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5480 || reloc_type == BFD_RELOC_X86_64_32S
5481 || (reloc_type == BFD_RELOC_64
5482 && object_64bit))
d6ab8113
JB		 5483 && (i.op[n].disps->X_op == O_symbol
5484 || (i.op[n].disps->X_op == O_add
5485 && ((symbol_get_value_expression
5486 (i.op[n].disps->X_op_symbol)->X_op)
5487 == O_subtract))))
5488 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5489 {
5490 offsetT add;
5491
5492 if (insn_start_frag == frag_now)
5493 add = (p - frag_now->fr_literal) - insn_start_off;
5494 else
5495 {
5496 fragS *fr;
5497
5498 add = insn_start_frag->fr_fix - insn_start_off;
5499 for (fr = insn_start_frag->fr_next;
5500 fr && fr != frag_now; fr = fr->fr_next)
5501 add += fr->fr_fix;
5502 add += p - frag_now->fr_literal;
5503 }
5504
4fa24527 5505 if (!object_64bit)
7b81dfbb
AJ		 5506 {
5507 reloc_type = BFD_RELOC_386_GOTPC;
5508 i.op[n].imms->X_add_number += add;
5509 }
5510 else if (reloc_type == BFD_RELOC_64)
5511 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5512 else
7b81dfbb
AJ		 5513 /* Don't do the adjustment for x86-64, as there
5514 the pcrel addressing is relative to the _next_
5515 insn, and that is taken care of in other code. */
d6ab8113 5516 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5517 }
062cd5e7 5518 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5519 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5520 }
5521 }
5522 }
5523}
252b5132 5524
29b0f896 5525static void
64e74474 5526output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5527{
5528 char *p;
5529 unsigned int n;
252b5132 5530
29b0f896
AM		 5531 for (n = 0; n < i.operands; n++)
5532 {
40fb9820 5533 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5534 {
5535 if (i.op[n].imms->X_op == O_constant)
5536 {
e205caa7 5537 int size = imm_size (n);
29b0f896 5538 offsetT val;
b4cac588 5539
29b0f896
AM		 5540 val = offset_in_range (i.op[n].imms->X_add_number,
5541 size);
5542 p = frag_more (size);
5543 md_number_to_chars (p, val, size);
5544 }
5545 else
5546 {
5547 /* Not absolute_section.
5548 Need a 32-bit fixup (don't support 8bit
5549 non-absolute imms). Try to support other
5550 sizes ... */
f86103b7 5551 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5552 int size = imm_size (n);
5553 int sign;
29b0f896 5554
40fb9820 5555 if (i.types[n].bitfield.imm32s
a7d61044 5556 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5557 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5558 sign = 1;
e205caa7
L		 5559 else
5560 sign = 0;
520dc8e8 5561
29b0f896
AM		 5562 p = frag_more (size);
5563 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5564
2bbd9c25
JJ		 5565 /* This is tough to explain. We end up with this one if we
5566 * have operands that look like
5567 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5568 * obtain the absolute address of the GOT, and it is strongly
5569 * preferable from a performance point of view to avoid using
5570 * a runtime relocation for this. The actual sequence of
5571 * instructions often look something like:
5572 *
5573 * call .L66
5574 * .L66:
5575 * popl %ebx
5576 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5577 *
5578 * The call and pop essentially return the absolute address
5579 * of the label .L66 and store it in %ebx. The linker itself
5580 * will ultimately change the first operand of the addl so
5581 * that %ebx points to the GOT, but to keep things simple, the
5582 * .o file must have this operand set so that it generates not
5583 * the absolute address of .L66, but the absolute address of
5584 * itself. This allows the linker itself simply treat a GOTPC
5585 * relocation as asking for a pcrel offset to the GOT to be
5586 * added in, and the addend of the relocation is stored in the
5587 * operand field for the instruction itself.
5588 *
5589 * Our job here is to fix the operand so that it would add
5590 * the correct offset so that %ebx would point to itself. The
5591 * thing that is tricky is that .-.L66 will point to the
5592 * beginning of the instruction, so we need to further modify
5593 * the operand so that it will point to itself. There are
5594 * other cases where you have something like:
5595 *
5596 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5597 *
5598 * and here no correction would be required. Internally in
5599 * the assembler we treat operands of this form as not being
5600 * pcrel since the '.' is explicitly mentioned, and I wonder
5601 * whether it would simplify matters to do it this way. Who
5602 * knows. In earlier versions of the PIC patches, the
5603 * pcrel_adjust field was used to store the correction, but
5604 * since the expression is not pcrel, I felt it would be
5605 * confusing to do it this way. */
5606
d6ab8113 5607 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5608 || reloc_type == BFD_RELOC_X86_64_32S
5609 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5610 && GOT_symbol
5611 && GOT_symbol == i.op[n].imms->X_add_symbol
5612 && (i.op[n].imms->X_op == O_symbol
5613 || (i.op[n].imms->X_op == O_add
5614 && ((symbol_get_value_expression
5615 (i.op[n].imms->X_op_symbol)->X_op)
5616 == O_subtract))))
5617 {
2bbd9c25
JJ		 5618 offsetT add;
5619
5620 if (insn_start_frag == frag_now)
5621 add = (p - frag_now->fr_literal) - insn_start_off;
5622 else
5623 {
5624 fragS *fr;
5625
5626 add = insn_start_frag->fr_fix - insn_start_off;
5627 for (fr = insn_start_frag->fr_next;
5628 fr && fr != frag_now; fr = fr->fr_next)
5629 add += fr->fr_fix;
5630 add += p - frag_now->fr_literal;
5631 }
5632
4fa24527 5633 if (!object_64bit)
d6ab8113 5634 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5635 else if (size == 4)
d6ab8113 5636 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5637 else if (size == 8)
5638 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5639 i.op[n].imms->X_add_number += add;
29b0f896 5640 }
29b0f896
AM		 5641 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5642 i.op[n].imms, 0, reloc_type);
5643 }
5644 }
5645 }
252b5132
RH		 5646}
5647\f
d182319b
JB		 5648/* x86_cons_fix_new is called via the expression parsing code when a
5649 reloc is needed. We use this hook to get the correct .got reloc. */
5650static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5651static int cons_sign = -1;
5652
5653void
e3bb37b5 5654x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5655 expressionS *exp)
d182319b
JB		 5656{
5657 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5658
5659 got_reloc = NO_RELOC;
5660
5661#ifdef TE_PE
5662 if (exp->X_op == O_secrel)
5663 {
5664 exp->X_op = O_symbol;
5665 r = BFD_RELOC_32_SECREL;
5666 }
5667#endif
5668
5669 fix_new_exp (frag, off, len, exp, 0, r);
5670}
5671
718ddfc0
JB		 5672#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5673# define lex_got(reloc, adjust, types) NULL
5674#else
f3c180ae
AM		 5675/* Parse operands of the form
5676 <symbol>@GOTOFF+<nnn>
5677 and similar .plt or .got references.
5678
5679 If we find one, set up the correct relocation in RELOC and copy the
5680 input string, minus the `@GOTOFF' into a malloc'd buffer for
5681 parsing by the calling routine. Return this buffer, and if ADJUST
5682 is non-null set it to the length of the string we removed from the
5683 input line. Otherwise return NULL. */
5684static char *
3956db08 5685lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5686 int *adjust,
40fb9820 5687 i386_operand_type *types)
f3c180ae 5688{
7b81dfbb
AJ		 5689 /* Some of the relocations depend on the size of what field is to
5690 be relocated. But in our callers i386_immediate and i386_displacement
5691 we don't yet know the operand size (this will be set by insn
5692 matching). Hence we record the word32 relocation here,
5693 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5694 static const struct {
5695 const char *str;
4fa24527 5696 const enum bfd_reloc_code_real rel[2];
40fb9820 5697 const i386_operand_type types64;
f3c180ae 5698 } gotrel[] = {
4eed87de
AM		 5699 { "PLTOFF", { 0,
5700 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5701 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5702 { "PLT", { BFD_RELOC_386_PLT32,
5703 BFD_RELOC_X86_64_PLT32 },
40fb9820 5704 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5705 { "GOTPLT", { 0,
5706 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5707 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5708 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5709 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5710 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5711 { "GOTPCREL", { 0,
5712 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5713 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5714 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5715 BFD_RELOC_X86_64_TLSGD },
40fb9820 5716 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5717 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5718 0 },
40fb9820 5719 OPERAND_TYPE_NONE },
4eed87de
AM		 5720 { "TLSLD", { 0,
5721 BFD_RELOC_X86_64_TLSLD },
40fb9820 5722 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5723 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5724 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5725 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5726 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5727 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5728 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5729 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5730 0 },
40fb9820 5731 OPERAND_TYPE_NONE },
4eed87de
AM		 5732 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5733 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5734
5735 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5736 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5737 0 },
40fb9820 5738 OPERAND_TYPE_NONE },
4eed87de
AM		 5739 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5740 0 },
40fb9820 5741 OPERAND_TYPE_NONE },
4eed87de
AM		 5742 { "GOT", { BFD_RELOC_386_GOT32,
5743 BFD_RELOC_X86_64_GOT32 },
40fb9820 5744 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5745 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5746 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5747 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5748 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5749 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5750 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5751 };
5752 char *cp;
5753 unsigned int j;
5754
718ddfc0
JB		 5755 if (!IS_ELF)
5756 return NULL;
5757
f3c180ae 5758 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5759 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5760 return NULL;
5761
47465058 5762 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 5763 {
5764 int len;
5765
5766 len = strlen (gotrel[j].str);
28f81592 5767 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5768 {
4fa24527 5769 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5770 {
28f81592
AM		 5771 int first, second;
5772 char *tmpbuf, *past_reloc;
f3c180ae 5773
4fa24527 5774 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5775 if (adjust)
5776 *adjust = len;
f3c180ae 5777
3956db08
JB		 5778 if (types)
5779 {
5780 if (flag_code != CODE_64BIT)
40fb9820
L		 5781 {
5782 types->bitfield.imm32 = 1;
5783 types->bitfield.disp32 = 1;
5784 }
3956db08
JB		 5785 else
5786 *types = gotrel[j].types64;
5787 }
5788
f3c180ae
AM		 5789 if (GOT_symbol == NULL)
5790 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5791
28f81592 5792 /* The length of the first part of our input line. */
f3c180ae 5793 first = cp - input_line_pointer;
28f81592
AM		 5794
5795 /* The second part goes from after the reloc token until
67c11a9b 5796 (and including) an end_of_line char or comma. */
28f81592 5797 past_reloc = cp + 1 + len;
67c11a9b
AM		 5798 cp = past_reloc;
5799 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5800 ++cp;
5801 second = cp + 1 - past_reloc;
28f81592
AM		 5802
5803 /* Allocate and copy string. The trailing NUL shouldn't
5804 be necessary, but be safe. */
5805 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5806 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5807 if (second != 0 && *past_reloc != ' ')
5808 /* Replace the relocation token with ' ', so that
5809 errors like foo@GOTOFF1 will be detected. */
5810 tmpbuf[first++] = ' ';
5811 memcpy (tmpbuf + first, past_reloc, second);
5812 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5813 return tmpbuf;
5814 }
5815
4fa24527
JB		 5816 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5817 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5818 return NULL;
5819 }
5820 }
5821
5822 /* Might be a symbol version string. Don't as_bad here. */
5823 return NULL;
5824}
5825
f3c180ae 5826void
e3bb37b5 5827x86_cons (expressionS *exp, int size)
f3c180ae 5828{
4fa24527 5829 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5830 {
5831 /* Handle @GOTOFF and the like in an expression. */
5832 char *save;
5833 char *gotfree_input_line;
5834 int adjust;
5835
5836 save = input_line_pointer;
3956db08 5837 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5838 if (gotfree_input_line)
5839 input_line_pointer = gotfree_input_line;
5840
5841 expression (exp);
5842
5843 if (gotfree_input_line)
5844 {
5845 /* expression () has merrily parsed up to the end of line,
5846 or a comma - in the wrong buffer. Transfer how far
5847 input_line_pointer has moved to the right buffer. */
5848 input_line_pointer = (save
5849 + (input_line_pointer - gotfree_input_line)
5850 + adjust);
5851 free (gotfree_input_line);
3992d3b7
AM		 5852 if (exp->X_op == O_constant
5853 || exp->X_op == O_absent
5854 || exp->X_op == O_illegal
5855 || exp->X_op == O_register
5856 || exp->X_op == O_big)
5857 {
5858 char c = *input_line_pointer;
5859 *input_line_pointer = 0;
5860 as_bad (_("missing or invalid expression `%s'"), save);
5861 *input_line_pointer = c;
5862 }
f3c180ae
AM		 5863 }
5864 }
5865 else
5866 expression (exp);
5867}
5868#endif
5869
d182319b 5870static void signed_cons (int size)
6482c264 5871{
d182319b
JB		 5872 if (flag_code == CODE_64BIT)
5873 cons_sign = 1;
5874 cons (size);
5875 cons_sign = -1;
6482c264
NC		 5876}
5877
d182319b 5878#ifdef TE_PE
6482c264
NC		 5879static void
5880pe_directive_secrel (dummy)
5881 int dummy ATTRIBUTE_UNUSED;
5882{
5883 expressionS exp;
5884
5885 do
5886 {
5887 expression (&exp);
5888 if (exp.X_op == O_symbol)
5889 exp.X_op = O_secrel;
5890
5891 emit_expr (&exp, 4);
5892 }
5893 while (*input_line_pointer++ == ',');
5894
5895 input_line_pointer--;
5896 demand_empty_rest_of_line ();
5897}
6482c264
NC		 5898#endif
5899
252b5132 5900static int
70e41ade 5901i386_immediate (char *imm_start)
252b5132
RH		 5902{
5903 char *save_input_line_pointer;
f3c180ae 5904 char *gotfree_input_line;
252b5132 5905 segT exp_seg = 0;
47926f60 5906 expressionS *exp;
40fb9820
L		 5907 i386_operand_type types;
5908
0dfbf9d7 5909 operand_type_set (&types, ~0);
252b5132
RH		 5910
5911 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5912 {
31b2323c
L		 5913 as_bad (_("at most %d immediate operands are allowed"),
5914 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5915 return 0;
5916 }
5917
5918 exp = &im_expressions[i.imm_operands++];
520dc8e8 5919 i.op[this_operand].imms = exp;
252b5132
RH		 5920
5921 if (is_space_char (*imm_start))
5922 ++imm_start;
5923
5924 save_input_line_pointer = input_line_pointer;
5925 input_line_pointer = imm_start;
5926
3956db08 5927 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5928 if (gotfree_input_line)
5929 input_line_pointer = gotfree_input_line;
252b5132
RH		 5930
5931 exp_seg = expression (exp);
5932
83183c0c 5933 SKIP_WHITESPACE ();
252b5132 5934 if (*input_line_pointer)
f3c180ae 5935 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5936
5937 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5938 if (gotfree_input_line)
5939 free (gotfree_input_line);
252b5132 5940
3992d3b7
AM		 5941 if (exp->X_op == O_absent
5942 || exp->X_op == O_illegal
5943 || exp->X_op == O_big
5944 || (gotfree_input_line
5945 && (exp->X_op == O_constant
5946 || exp->X_op == O_register)))
252b5132 5947 {
3992d3b7 5948 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5949 imm_start);
3992d3b7 5950 return 0;
252b5132 5951 }
3e73aa7c 5952 else if (exp->X_op == O_constant)
252b5132 5953 {
47926f60 5954 /* Size it properly later. */
40fb9820 5955 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5956 /* If BFD64, sign extend val. */
4eed87de
AM		 5957 if (!use_rela_relocations
5958 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5959 exp->X_add_number
5960 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5961 }
4c63da97 5962#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5963 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5964 && exp_seg != absolute_section
47926f60 5965 && exp_seg != text_section
24eab124
AM		 5966 && exp_seg != data_section
5967 && exp_seg != bss_section
5968 && exp_seg != undefined_section
f86103b7 5969 && !bfd_is_com_section (exp_seg))
252b5132 5970 {
d0b47220 5971 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5972 return 0;
5973 }
5974#endif
bb8f5920
L		 5975 else if (!intel_syntax && exp->X_op == O_register)
5976 {
5977 as_bad (_("illegal immediate register operand %s"), imm_start);
5978 return 0;
5979 }
252b5132
RH		 5980 else
5981 {
5982 /* This is an address. The size of the address will be
24eab124 5983 determined later, depending on destination register,
3e73aa7c 5984 suffix, or the default for the section. */
40fb9820
L		 5985 i.types[this_operand].bitfield.imm8 = 1;
5986 i.types[this_operand].bitfield.imm16 = 1;
5987 i.types[this_operand].bitfield.imm32 = 1;
5988 i.types[this_operand].bitfield.imm32s = 1;
5989 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 5990 i.types[this_operand] = operand_type_and (i.types[this_operand],
5991 types);
252b5132
RH		 5992 }
5993
5994 return 1;
5995}
5996
551c1ca1 5997static char *
e3bb37b5 5998i386_scale (char *scale)
252b5132 5999{
551c1ca1
AM		 6000 offsetT val;
6001 char *save = input_line_pointer;
252b5132 6002
551c1ca1
AM		 6003 input_line_pointer = scale;
6004 val = get_absolute_expression ();
6005
6006 switch (val)
252b5132 6007 {
551c1ca1 6008 case 1:
252b5132
RH		 6009 i.log2_scale_factor = 0;
6010 break;
551c1ca1 6011 case 2:
252b5132
RH		 6012 i.log2_scale_factor = 1;
6013 break;
551c1ca1 6014 case 4:
252b5132
RH		 6015 i.log2_scale_factor = 2;
6016 break;
551c1ca1 6017 case 8:
252b5132
RH		 6018 i.log2_scale_factor = 3;
6019 break;
6020 default:
a724f0f4
JB		 6021 {
6022 char sep = *input_line_pointer;
6023
6024 *input_line_pointer = '\0';
6025 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6026 scale);
6027 *input_line_pointer = sep;
6028 input_line_pointer = save;
6029 return NULL;
6030 }
252b5132 6031 }
29b0f896 6032 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6033 {
6034 as_warn (_("scale factor of %d without an index register"),
24eab124 6035 1 << i.log2_scale_factor);
252b5132 6036 i.log2_scale_factor = 0;
252b5132 6037 }
551c1ca1
AM		 6038 scale = input_line_pointer;
6039 input_line_pointer = save;
6040 return scale;
252b5132
RH		 6041}
6042
252b5132 6043static int
e3bb37b5 6044i386_displacement (char *disp_start, char *disp_end)
252b5132 6045{
29b0f896 6046 expressionS *exp;
252b5132
RH		 6047 segT exp_seg = 0;
6048 char *save_input_line_pointer;
f3c180ae 6049 char *gotfree_input_line;
40fb9820
L		 6050 int override;
6051 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6052 int ret;
252b5132 6053
31b2323c
L		 6054 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6055 {
6056 as_bad (_("at most %d displacement operands are allowed"),
6057 MAX_MEMORY_OPERANDS);
6058 return 0;
6059 }
6060
0dfbf9d7 6061 operand_type_set (&bigdisp, 0);
40fb9820
L		 6062 if ((i.types[this_operand].bitfield.jumpabsolute)
6063 || (!current_templates->start->opcode_modifier.jump
6064 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6065 {
40fb9820 6066 bigdisp.bitfield.disp32 = 1;
e05278af 6067 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6068 if (flag_code == CODE_64BIT)
6069 {
6070 if (!override)
6071 {
6072 bigdisp.bitfield.disp32s = 1;
6073 bigdisp.bitfield.disp64 = 1;
6074 }
6075 }
6076 else if ((flag_code == CODE_16BIT) ^ override)
6077 {
6078 bigdisp.bitfield.disp32 = 0;
6079 bigdisp.bitfield.disp16 = 1;
6080 }
e05278af
JB		 6081 }
6082 else
6083 {
6084 /* For PC-relative branches, the width of the displacement
6085 is dependent upon data size, not address size. */
e05278af 6086 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6087 if (flag_code == CODE_64BIT)
6088 {
6089 if (override || i.suffix == WORD_MNEM_SUFFIX)
6090 bigdisp.bitfield.disp16 = 1;
6091 else
6092 {
6093 bigdisp.bitfield.disp32 = 1;
6094 bigdisp.bitfield.disp32s = 1;
6095 }
6096 }
6097 else
e05278af
JB		 6098 {
6099 if (!override)
6100 override = (i.suffix == (flag_code != CODE_16BIT
6101 ? WORD_MNEM_SUFFIX
6102 : LONG_MNEM_SUFFIX));
40fb9820
L		 6103 bigdisp.bitfield.disp32 = 1;
6104 if ((flag_code == CODE_16BIT) ^ override)
6105 {
6106 bigdisp.bitfield.disp32 = 0;
6107 bigdisp.bitfield.disp16 = 1;
6108 }
e05278af 6109 }
e05278af 6110 }
c6fb90c8
L		 6111 i.types[this_operand] = operand_type_or (i.types[this_operand],
6112 bigdisp);
252b5132
RH		 6113
6114 exp = &disp_expressions[i.disp_operands];
520dc8e8 6115 i.op[this_operand].disps = exp;
252b5132
RH		 6116 i.disp_operands++;
6117 save_input_line_pointer = input_line_pointer;
6118 input_line_pointer = disp_start;
6119 END_STRING_AND_SAVE (disp_end);
6120
6121#ifndef GCC_ASM_O_HACK
6122#define GCC_ASM_O_HACK 0
6123#endif
6124#if GCC_ASM_O_HACK
6125 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6126 if (i.types[this_operand].bitfield.baseIndex
24eab124 6127 && displacement_string_end[-1] == '+')
252b5132
RH		 6128 {
6129 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6130 constraint within gcc asm statements.
6131 For instance:
6132
6133 #define _set_tssldt_desc(n,addr,limit,type) \
6134 __asm__ __volatile__ ( \
6135 "movw %w2,%0\n\t" \
6136 "movw %w1,2+%0\n\t" \
6137 "rorl $16,%1\n\t" \
6138 "movb %b1,4+%0\n\t" \
6139 "movb %4,5+%0\n\t" \
6140 "movb $0,6+%0\n\t" \
6141 "movb %h1,7+%0\n\t" \
6142 "rorl $16,%1" \
6143 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6144
6145 This works great except that the output assembler ends
6146 up looking a bit weird if it turns out that there is
6147 no offset. You end up producing code that looks like:
6148
6149 #APP
6150 movw $235,(%eax)
6151 movw %dx,2+(%eax)
6152 rorl $16,%edx
6153 movb %dl,4+(%eax)
6154 movb $137,5+(%eax)
6155 movb $0,6+(%eax)
6156 movb %dh,7+(%eax)
6157 rorl $16,%edx
6158 #NO_APP
6159
47926f60 6160 So here we provide the missing zero. */
24eab124
AM		 6161
6162 *displacement_string_end = '0';
252b5132
RH		 6163 }
6164#endif
3956db08 6165 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6166 if (gotfree_input_line)
6167 input_line_pointer = gotfree_input_line;
252b5132 6168
24eab124 6169 exp_seg = expression (exp);
252b5132 6170
636c26b0
AM		 6171 SKIP_WHITESPACE ();
6172 if (*input_line_pointer)
6173 as_bad (_("junk `%s' after expression"), input_line_pointer);
6174#if GCC_ASM_O_HACK
6175 RESTORE_END_STRING (disp_end + 1);
6176#endif
636c26b0 6177 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 6178 if (gotfree_input_line)
6179 free (gotfree_input_line);
3992d3b7 6180 ret = 1;
636c26b0 6181
24eab124
AM		 6182 /* We do this to make sure that the section symbol is in
6183 the symbol table. We will ultimately change the relocation
47926f60 6184 to be relative to the beginning of the section. */
1ae12ab7 6185 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6186 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6187 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6188 {
636c26b0 6189 if (exp->X_op != O_symbol)
3992d3b7 6190 goto inv_disp;
636c26b0 6191
e5cb08ac 6192 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6193 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6194 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6195 exp->X_op = O_subtract;
6196 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6197 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6198 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6199 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6200 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6201 else
29b0f896 6202 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6203 }
252b5132 6204
3992d3b7
AM		 6205 else if (exp->X_op == O_absent
6206 || exp->X_op == O_illegal
6207 || exp->X_op == O_big
6208 || (gotfree_input_line
6209 && (exp->X_op == O_constant
6210 || exp->X_op == O_register)))
2daf4fd8 6211 {
3992d3b7
AM		 6212 inv_disp:
6213 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6214 disp_start);
3992d3b7 6215 ret = 0;
2daf4fd8
AM		 6216 }
6217
4c63da97 6218#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6219 else if (exp->X_op != O_constant
6220 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6221 && exp_seg != absolute_section
6222 && exp_seg != text_section
6223 && exp_seg != data_section
6224 && exp_seg != bss_section
6225 && exp_seg != undefined_section
6226 && !bfd_is_com_section (exp_seg))
24eab124 6227 {
d0b47220 6228 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6229 ret = 0;
24eab124 6230 }
252b5132 6231#endif
3956db08 6232
3992d3b7
AM		 6233 RESTORE_END_STRING (disp_end);
6234
40fb9820
L		 6235 /* Check if this is a displacement only operand. */
6236 bigdisp = i.types[this_operand];
6237 bigdisp.bitfield.disp8 = 0;
6238 bigdisp.bitfield.disp16 = 0;
6239 bigdisp.bitfield.disp32 = 0;
6240 bigdisp.bitfield.disp32s = 0;
6241 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6242 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6243 i.types[this_operand] = operand_type_and (i.types[this_operand],
6244 types);
3956db08 6245
3992d3b7 6246 return ret;
252b5132
RH		 6247}
6248
eecb386c 6249/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6250 Return 1 on success, 0 on a failure. */
6251
252b5132 6252static int
e3bb37b5 6253i386_index_check (const char *operand_string)
252b5132 6254{
3e73aa7c 6255 int ok;
24eab124 6256#if INFER_ADDR_PREFIX
eecb386c
AM		 6257 int fudged = 0;
6258
24eab124
AM		 6259 tryprefix:
6260#endif
3e73aa7c 6261 ok = 1;
75178d9d 6262 if (flag_code == CODE_64BIT)
64e74474 6263 {
64e74474 6264 if ((i.base_reg
40fb9820
L		 6265 && ((i.prefix[ADDR_PREFIX] == 0
6266 && !i.base_reg->reg_type.bitfield.reg64)
6267 || (i.prefix[ADDR_PREFIX]
6268 && !i.base_reg->reg_type.bitfield.reg32))
6269 && (i.index_reg
9a04903e
JB		 6270 || i.base_reg->reg_num !=
6271 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6272 || (i.index_reg
40fb9820
L		 6273 && (!i.index_reg->reg_type.bitfield.baseindex
6274 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6275 && i.index_reg->reg_num != RegRiz
6276 && !i.index_reg->reg_type.bitfield.reg64
6277 )
40fb9820 6278 || (i.prefix[ADDR_PREFIX]
db51cc60 6279 && i.index_reg->reg_num != RegEiz
40fb9820 6280 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6281 ok = 0;
3e73aa7c
JH		 6282 }
6283 else
6284 {
6285 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6286 {
6287 /* 16bit checks. */
6288 if ((i.base_reg
40fb9820
L		 6289 && (!i.base_reg->reg_type.bitfield.reg16
6290 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6291 || (i.index_reg
40fb9820
L		 6292 && (!i.index_reg->reg_type.bitfield.reg16
6293 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6294 || !(i.base_reg
6295 && i.base_reg->reg_num < 6
6296 && i.index_reg->reg_num >= 6
6297 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6298 ok = 0;
6299 }
6300 else
e5cb08ac 6301 {
3e73aa7c
JH		 6302 /* 32bit checks. */
6303 if ((i.base_reg
40fb9820 6304 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6305 || (i.index_reg
db51cc60
L		 6306 && ((!i.index_reg->reg_type.bitfield.reg32
6307 && i.index_reg->reg_num != RegEiz)
40fb9820 6308 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6309 ok = 0;
3e73aa7c
JH		 6310 }
6311 }
6312 if (!ok)
24eab124
AM		 6313 {
6314#if INFER_ADDR_PREFIX
20f0a1fc 6315 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6316 {
6317 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6318 i.prefixes += 1;
b23bac36
AM		 6319 /* Change the size of any displacement too. At most one of
6320 Disp16 or Disp32 is set.
6321 FIXME. There doesn't seem to be any real need for separate
6322 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6323 Removing them would probably clean up the code quite a lot. */
4eed87de 6324 if (flag_code != CODE_64BIT
40fb9820
L		 6325 && (i.types[this_operand].bitfield.disp16
6326 || i.types[this_operand].bitfield.disp32))
6327 i.types[this_operand]
c6fb90c8 6328 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6329 fudged = 1;
24eab124
AM		 6330 goto tryprefix;
6331 }
eecb386c
AM		 6332 if (fudged)
6333 as_bad (_("`%s' is not a valid base/index expression"),
6334 operand_string);
6335 else
c388dee8 6336#endif
eecb386c
AM		 6337 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6338 operand_string,
3e73aa7c 6339 flag_code_names[flag_code]);
24eab124 6340 }
20f0a1fc 6341 return ok;
24eab124 6342}
252b5132 6343
252b5132 6344/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6345 on error. */
252b5132 6346
252b5132 6347static int
a7619375 6348i386_att_operand (char *operand_string)
252b5132 6349{
af6bdddf
AM		 6350 const reg_entry *r;
6351 char *end_op;
24eab124 6352 char *op_string = operand_string;
252b5132 6353
24eab124 6354 if (is_space_char (*op_string))
252b5132
RH		 6355 ++op_string;
6356
24eab124 6357 /* We check for an absolute prefix (differentiating,
47926f60 6358 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6359 if (*op_string == ABSOLUTE_PREFIX)
6360 {
6361 ++op_string;
6362 if (is_space_char (*op_string))
6363 ++op_string;
40fb9820 6364 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6365 }
252b5132 6366
47926f60 6367 /* Check if operand is a register. */
4d1bb795 6368 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6369 {
40fb9820
L		 6370 i386_operand_type temp;
6371
24eab124
AM		 6372 /* Check for a segment override by searching for ':' after a
6373 segment register. */
6374 op_string = end_op;
6375 if (is_space_char (*op_string))
6376 ++op_string;
40fb9820
L		 6377 if (*op_string == ':'
6378 && (r->reg_type.bitfield.sreg2
6379 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6380 {
6381 switch (r->reg_num)
6382 {
6383 case 0:
6384 i.seg[i.mem_operands] = &es;
6385 break;
6386 case 1:
6387 i.seg[i.mem_operands] = &cs;
6388 break;
6389 case 2:
6390 i.seg[i.mem_operands] = &ss;
6391 break;
6392 case 3:
6393 i.seg[i.mem_operands] = &ds;
6394 break;
6395 case 4:
6396 i.seg[i.mem_operands] = &fs;
6397 break;
6398 case 5:
6399 i.seg[i.mem_operands] = &gs;
6400 break;
6401 }
252b5132 6402
24eab124 6403 /* Skip the ':' and whitespace. */
252b5132
RH		 6404 ++op_string;
6405 if (is_space_char (*op_string))
24eab124 6406 ++op_string;
252b5132 6407
24eab124
AM		 6408 if (!is_digit_char (*op_string)
6409 && !is_identifier_char (*op_string)
6410 && *op_string != '('
6411 && *op_string != ABSOLUTE_PREFIX)
6412 {
6413 as_bad (_("bad memory operand `%s'"), op_string);
6414 return 0;
6415 }
47926f60 6416 /* Handle case of %es:*foo. */
24eab124
AM		 6417 if (*op_string == ABSOLUTE_PREFIX)
6418 {
6419 ++op_string;
6420 if (is_space_char (*op_string))
6421 ++op_string;
40fb9820 6422 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6423 }
6424 goto do_memory_reference;
6425 }
6426 if (*op_string)
6427 {
d0b47220 6428 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6429 return 0;
6430 }
40fb9820
L		 6431 temp = r->reg_type;
6432 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6433 i.types[this_operand] = operand_type_or (i.types[this_operand],
6434 temp);
7d5e4556 6435 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6436 i.op[this_operand].regs = r;
24eab124
AM		 6437 i.reg_operands++;
6438 }
af6bdddf
AM		 6439 else if (*op_string == REGISTER_PREFIX)
6440 {
6441 as_bad (_("bad register name `%s'"), op_string);
6442 return 0;
6443 }
24eab124 6444 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6445 {
24eab124 6446 ++op_string;
40fb9820 6447 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6448 {
d0b47220 6449 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6450 return 0;
6451 }
6452 if (!i386_immediate (op_string))
6453 return 0;
6454 }
6455 else if (is_digit_char (*op_string)
6456 || is_identifier_char (*op_string)
e5cb08ac 6457 || *op_string == '(')
24eab124 6458 {
47926f60 6459 /* This is a memory reference of some sort. */
af6bdddf 6460 char *base_string;
252b5132 6461
47926f60 6462 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6463 char *displacement_string_start;
6464 char *displacement_string_end;
252b5132 6465
24eab124 6466 do_memory_reference:
24eab124 6467 if ((i.mem_operands == 1
40fb9820 6468 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6469 || i.mem_operands == 2)
6470 {
6471 as_bad (_("too many memory references for `%s'"),
6472 current_templates->start->name);
6473 return 0;
6474 }
252b5132 6475
24eab124
AM		 6476 /* Check for base index form. We detect the base index form by
6477 looking for an ')' at the end of the operand, searching
6478 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6479 after the '('. */
af6bdddf 6480 base_string = op_string + strlen (op_string);
c3332e24 6481
af6bdddf
AM		 6482 --base_string;
6483 if (is_space_char (*base_string))
6484 --base_string;
252b5132 6485
47926f60 6486 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6487 displacement_string_start = op_string;
6488 displacement_string_end = base_string + 1;
252b5132 6489
24eab124
AM		 6490 if (*base_string == ')')
6491 {
af6bdddf 6492 char *temp_string;
24eab124
AM		 6493 unsigned int parens_balanced = 1;
6494 /* We've already checked that the number of left & right ()'s are
47926f60 6495 equal, so this loop will not be infinite. */
24eab124
AM		 6496 do
6497 {
6498 base_string--;
6499 if (*base_string == ')')
6500 parens_balanced++;
6501 if (*base_string == '(')
6502 parens_balanced--;
6503 }
6504 while (parens_balanced);
c3332e24 6505
af6bdddf 6506 temp_string = base_string;
c3332e24 6507
24eab124 6508 /* Skip past '(' and whitespace. */
252b5132
RH		 6509 ++base_string;
6510 if (is_space_char (*base_string))
24eab124 6511 ++base_string;
252b5132 6512
af6bdddf 6513 if (*base_string == ','
4eed87de
AM		 6514 || ((i.base_reg = parse_register (base_string, &end_op))
6515 != NULL))
252b5132 6516 {
af6bdddf 6517 displacement_string_end = temp_string;
252b5132 6518
40fb9820 6519 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6520
af6bdddf 6521 if (i.base_reg)
24eab124 6522 {
24eab124
AM		 6523 base_string = end_op;
6524 if (is_space_char (*base_string))
6525 ++base_string;
af6bdddf
AM		 6526 }
6527
6528 /* There may be an index reg or scale factor here. */
6529 if (*base_string == ',')
6530 {
6531 ++base_string;
6532 if (is_space_char (*base_string))
6533 ++base_string;
6534
4eed87de
AM		 6535 if ((i.index_reg = parse_register (base_string, &end_op))
6536 != NULL)
24eab124 6537 {
af6bdddf 6538 base_string = end_op;
24eab124
AM		 6539 if (is_space_char (*base_string))
6540 ++base_string;
af6bdddf
AM		 6541 if (*base_string == ',')
6542 {
6543 ++base_string;
6544 if (is_space_char (*base_string))
6545 ++base_string;
6546 }
e5cb08ac 6547 else if (*base_string != ')')
af6bdddf 6548 {
4eed87de
AM		 6549 as_bad (_("expecting `,' or `)' "
6550 "after index register in `%s'"),
af6bdddf
AM		 6551 operand_string);
6552 return 0;
6553 }
24eab124 6554 }
af6bdddf 6555 else if (*base_string == REGISTER_PREFIX)
24eab124 6556 {
af6bdddf 6557 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6558 return 0;
6559 }
252b5132 6560
47926f60 6561 /* Check for scale factor. */
551c1ca1 6562 if (*base_string != ')')
af6bdddf 6563 {
551c1ca1
AM		 6564 char *end_scale = i386_scale (base_string);
6565
6566 if (!end_scale)
af6bdddf 6567 return 0;
24eab124 6568
551c1ca1 6569 base_string = end_scale;
af6bdddf
AM		 6570 if (is_space_char (*base_string))
6571 ++base_string;
6572 if (*base_string != ')')
6573 {
4eed87de
AM		 6574 as_bad (_("expecting `)' "
6575 "after scale factor in `%s'"),
af6bdddf
AM		 6576 operand_string);
6577 return 0;
6578 }
6579 }
6580 else if (!i.index_reg)
24eab124 6581 {
4eed87de
AM		 6582 as_bad (_("expecting index register or scale factor "
6583 "after `,'; got '%c'"),
af6bdddf 6584 *base_string);
24eab124
AM		 6585 return 0;
6586 }
6587 }
af6bdddf 6588 else if (*base_string != ')')
24eab124 6589 {
4eed87de
AM		 6590 as_bad (_("expecting `,' or `)' "
6591 "after base register in `%s'"),
af6bdddf 6592 operand_string);
24eab124
AM		 6593 return 0;
6594 }
c3332e24 6595 }
af6bdddf 6596 else if (*base_string == REGISTER_PREFIX)
c3332e24 6597 {
af6bdddf 6598 as_bad (_("bad register name `%s'"), base_string);
24eab124 6599 return 0;
c3332e24 6600 }
24eab124
AM		 6601 }
6602
6603 /* If there's an expression beginning the operand, parse it,
6604 assuming displacement_string_start and
6605 displacement_string_end are meaningful. */
6606 if (displacement_string_start != displacement_string_end)
6607 {
6608 if (!i386_displacement (displacement_string_start,
6609 displacement_string_end))
6610 return 0;
6611 }
6612
6613 /* Special case for (%dx) while doing input/output op. */
6614 if (i.base_reg
0dfbf9d7
L		 6615 && operand_type_equal (&i.base_reg->reg_type,
6616 &reg16_inoutportreg)
24eab124
AM		 6617 && i.index_reg == 0
6618 && i.log2_scale_factor == 0
6619 && i.seg[i.mem_operands] == 0
40fb9820 6620 && !operand_type_check (i.types[this_operand], disp))
24eab124 6621 {
65da13b5 6622 i.types[this_operand] = inoutportreg;
24eab124
AM		 6623 return 1;
6624 }
6625
eecb386c
AM		 6626 if (i386_index_check (operand_string) == 0)
6627 return 0;
5c07affc 6628 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 6629 i.mem_operands++;
6630 }
6631 else
ce8a8b2f
AM		 6632 {
6633 /* It's not a memory operand; argh! */
24eab124
AM		 6634 as_bad (_("invalid char %s beginning operand %d `%s'"),
6635 output_invalid (*op_string),
6636 this_operand + 1,
6637 op_string);
6638 return 0;
6639 }
47926f60 6640 return 1; /* Normal return. */
252b5132
RH		 6641}
6642\f
ee7fcc42
AM		 6643/* md_estimate_size_before_relax()
6644
6645 Called just before relax() for rs_machine_dependent frags. The x86
6646 assembler uses these frags to handle variable size jump
6647 instructions.
6648
6649 Any symbol that is now undefined will not become defined.
6650 Return the correct fr_subtype in the frag.
6651 Return the initial "guess for variable size of frag" to caller.
6652 The guess is actually the growth beyond the fixed part. Whatever
6653 we do to grow the fixed or variable part contributes to our
6654 returned value. */
6655
252b5132
RH		 6656int
6657md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6658 fragS *fragP;
6659 segT segment;
252b5132 6660{
252b5132 6661 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6662 check for un-relaxable symbols. On an ELF system, we can't relax
6663 an externally visible symbol, because it may be overridden by a
6664 shared library. */
6665 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6666#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6667 || (IS_ELF
31312f95
AM		 6668 && (S_IS_EXTERNAL (fragP->fr_symbol)
6669 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 6670#endif
6671 )
252b5132 6672 {
b98ef147
AM		 6673 /* Symbol is undefined in this segment, or we need to keep a
6674 reloc so that weak symbols can be overridden. */
6675 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 6676 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 6677 unsigned char *opcode;
6678 int old_fr_fix;
f6af82bd 6679
ee7fcc42
AM		 6680 if (fragP->fr_var != NO_RELOC)
6681 reloc_type = fragP->fr_var;
b98ef147 6682 else if (size == 2)
f6af82bd
AM		 6683 reloc_type = BFD_RELOC_16_PCREL;
6684 else
6685 reloc_type = BFD_RELOC_32_PCREL;
252b5132 6686
ee7fcc42
AM		 6687 old_fr_fix = fragP->fr_fix;
6688 opcode = (unsigned char *) fragP->fr_opcode;
6689
fddf5b5b 6690 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 6691 {
fddf5b5b
AM		 6692 case UNCOND_JUMP:
6693 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 6694 opcode[0] = 0xe9;
252b5132 6695 fragP->fr_fix += size;
062cd5e7
AS		 6696 fix_new (fragP, old_fr_fix, size,
6697 fragP->fr_symbol,
6698 fragP->fr_offset, 1,
6699 reloc_type);
252b5132
RH		 6700 break;
6701
fddf5b5b 6702 case COND_JUMP86:
412167cb
AM		 6703 if (size == 2
6704 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 6705 {
6706 /* Negate the condition, and branch past an
6707 unconditional jump. */
6708 opcode[0] ^= 1;
6709 opcode[1] = 3;
6710 /* Insert an unconditional jump. */
6711 opcode[2] = 0xe9;
6712 /* We added two extra opcode bytes, and have a two byte
6713 offset. */
6714 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 6715 fix_new (fragP, old_fr_fix + 2, 2,
6716 fragP->fr_symbol,
6717 fragP->fr_offset, 1,
6718 reloc_type);
fddf5b5b
AM		 6719 break;
6720 }
6721 /* Fall through. */
6722
6723 case COND_JUMP:
412167cb
AM		 6724 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6725 {
3e02c1cc
AM		 6726 fixS *fixP;
6727
412167cb 6728 fragP->fr_fix += 1;
3e02c1cc
AM		 6729 fixP = fix_new (fragP, old_fr_fix, 1,
6730 fragP->fr_symbol,
6731 fragP->fr_offset, 1,
6732 BFD_RELOC_8_PCREL);
6733 fixP->fx_signed = 1;
412167cb
AM		 6734 break;
6735 }
93c2a809 6736
24eab124 6737 /* This changes the byte-displacement jump 0x7N
fddf5b5b 6738 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 6739 opcode[1] = opcode[0] + 0x10;
f6af82bd 6740 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 6741 /* We've added an opcode byte. */
6742 fragP->fr_fix += 1 + size;
062cd5e7
AS		 6743 fix_new (fragP, old_fr_fix + 1, size,
6744 fragP->fr_symbol,
6745 fragP->fr_offset, 1,
6746 reloc_type);
252b5132 6747 break;
fddf5b5b
AM		 6748
6749 default:
6750 BAD_CASE (fragP->fr_subtype);
6751 break;
252b5132
RH		 6752 }
6753 frag_wane (fragP);
ee7fcc42 6754 return fragP->fr_fix - old_fr_fix;
252b5132 6755 }
93c2a809 6756
93c2a809
AM		 6757 /* Guess size depending on current relax state. Initially the relax
6758 state will correspond to a short jump and we return 1, because
6759 the variable part of the frag (the branch offset) is one byte
6760 long. However, we can relax a section more than once and in that
6761 case we must either set fr_subtype back to the unrelaxed state,
6762 or return the value for the appropriate branch. */
6763 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 6764}
6765
47926f60
KH		 6766/* Called after relax() is finished.
6767
6768 In: Address of frag.
6769 fr_type == rs_machine_dependent.
6770 fr_subtype is what the address relaxed to.
6771
6772 Out: Any fixSs and constants are set up.
6773 Caller will turn frag into a ".space 0". */
6774
252b5132
RH		 6775void
6776md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 6777 bfd *abfd ATTRIBUTE_UNUSED;
6778 segT sec ATTRIBUTE_UNUSED;
29b0f896 6779 fragS *fragP;
252b5132 6780{
29b0f896 6781 unsigned char *opcode;
252b5132 6782 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6783 offsetT target_address;
6784 offsetT opcode_address;
252b5132 6785 unsigned int extension = 0;
847f7ad4 6786 offsetT displacement_from_opcode_start;
252b5132
RH		 6787
6788 opcode = (unsigned char *) fragP->fr_opcode;
6789
47926f60 6790 /* Address we want to reach in file space. */
252b5132 6791 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6792
47926f60 6793 /* Address opcode resides at in file space. */
252b5132
RH		 6794 opcode_address = fragP->fr_address + fragP->fr_fix;
6795
47926f60 6796 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6797 displacement_from_opcode_start = target_address - opcode_address;
6798
fddf5b5b 6799 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6800 {
47926f60
KH		 6801 /* Don't have to change opcode. */
6802 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6803 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6804 }
6805 else
6806 {
6807 if (no_cond_jump_promotion
6808 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6809 as_warn_where (fragP->fr_file, fragP->fr_line,
6810 _("long jump required"));
252b5132 6811
fddf5b5b
AM		 6812 switch (fragP->fr_subtype)
6813 {
6814 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6815 extension = 4; /* 1 opcode + 4 displacement */
6816 opcode[0] = 0xe9;
6817 where_to_put_displacement = &opcode[1];
6818 break;
252b5132 6819
fddf5b5b
AM		 6820 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6821 extension = 2; /* 1 opcode + 2 displacement */
6822 opcode[0] = 0xe9;
6823 where_to_put_displacement = &opcode[1];
6824 break;
252b5132 6825
fddf5b5b
AM		 6826 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6827 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6828 extension = 5; /* 2 opcode + 4 displacement */
6829 opcode[1] = opcode[0] + 0x10;
6830 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6831 where_to_put_displacement = &opcode[2];
6832 break;
252b5132 6833
fddf5b5b
AM		 6834 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6835 extension = 3; /* 2 opcode + 2 displacement */
6836 opcode[1] = opcode[0] + 0x10;
6837 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6838 where_to_put_displacement = &opcode[2];
6839 break;
252b5132 6840
fddf5b5b
AM		 6841 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6842 extension = 4;
6843 opcode[0] ^= 1;
6844 opcode[1] = 3;
6845 opcode[2] = 0xe9;
6846 where_to_put_displacement = &opcode[3];
6847 break;
6848
6849 default:
6850 BAD_CASE (fragP->fr_subtype);
6851 break;
6852 }
252b5132 6853 }
fddf5b5b 6854
7b81dfbb
AJ		 6855 /* If size if less then four we are sure that the operand fits,
6856 but if it's 4, then it could be that the displacement is larger
6857 then -/+ 2GB. */
6858 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6859 && object_64bit
6860 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6861 + ((addressT) 1 << 31))
6862 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6863 {
6864 as_bad_where (fragP->fr_file, fragP->fr_line,
6865 _("jump target out of range"));
6866 /* Make us emit 0. */
6867 displacement_from_opcode_start = extension;
6868 }
47926f60 6869 /* Now put displacement after opcode. */
252b5132
RH		 6870 md_number_to_chars ((char *) where_to_put_displacement,
6871 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6872 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6873 fragP->fr_fix += extension;
6874}
6875\f
252b5132
RH		 6876/* Apply a fixup (fixS) to segment data, once it has been determined
6877 by our caller that we have all the info we need to fix it up.
6878
6879 On the 386, immediates, displacements, and data pointers are all in
6880 the same (little-endian) format, so we don't need to care about which
6881 we are handling. */
6882
94f592af 6883void
55cf6793 6884md_apply_fix (fixP, valP, seg)
47926f60
KH		 6885 /* The fix we're to put in. */
6886 fixS *fixP;
47926f60 6887 /* Pointer to the value of the bits. */
c6682705 6888 valueT *valP;
47926f60
KH		 6889 /* Segment fix is from. */
6890 segT seg ATTRIBUTE_UNUSED;
252b5132 6891{
94f592af 6892 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6893 valueT value = *valP;
252b5132 6894
f86103b7 6895#if !defined (TE_Mach)
93382f6d
AM		 6896 if (fixP->fx_pcrel)
6897 {
6898 switch (fixP->fx_r_type)
6899 {
5865bb77
ILT		 6900 default:
6901 break;
6902
d6ab8113
JB		 6903 case BFD_RELOC_64:
6904 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6905 break;
93382f6d 6906 case BFD_RELOC_32:
ae8887b5 6907 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6908 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6909 break;
6910 case BFD_RELOC_16:
6911 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6912 break;
6913 case BFD_RELOC_8:
6914 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6915 break;
6916 }
6917 }
252b5132 6918
a161fe53 6919 if (fixP->fx_addsy != NULL
31312f95 6920 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6921 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6922 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6923 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6924 && !use_rela_relocations)
252b5132 6925 {
31312f95
AM		 6926 /* This is a hack. There should be a better way to handle this.
6927 This covers for the fact that bfd_install_relocation will
6928 subtract the current location (for partial_inplace, PC relative
6929 relocations); see more below. */
252b5132 6930#ifndef OBJ_AOUT
718ddfc0 6931 if (IS_ELF
252b5132
RH		 6932#ifdef TE_PE
6933 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6934#endif
6935 )
6936 value += fixP->fx_where + fixP->fx_frag->fr_address;
6937#endif
6938#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6939 if (IS_ELF)
252b5132 6940 {
6539b54b 6941 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6942
6539b54b 6943 if ((sym_seg == seg
2f66722d 6944 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6945 && sym_seg != absolute_section))
ae6063d4 6946 && !generic_force_reloc (fixP))
2f66722d
AM		 6947 {
6948 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6949 bfd_install_relocation subtracts them out again. I think
6950 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6951 it. FIXME. */
6952 value += fixP->fx_where + fixP->fx_frag->fr_address;
6953 }
252b5132
RH		 6954 }
6955#endif
6956#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6957 /* For some reason, the PE format does not store a
6958 section address offset for a PC relative symbol. */
6959 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6960 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6961 value += md_pcrel_from (fixP);
6962#endif
6963 }
6964
6965 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6966 and we must not disappoint it. */
252b5132 6967#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6968 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6969 switch (fixP->fx_r_type)
6970 {
6971 case BFD_RELOC_386_PLT32:
3e73aa7c 6972 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6973 /* Make the jump instruction point to the address of the operand. At
6974 runtime we merely add the offset to the actual PLT entry. */
6975 value = -4;
6976 break;
31312f95 6977
13ae64f3
JJ		 6978 case BFD_RELOC_386_TLS_GD:
6979 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6980 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6981 case BFD_RELOC_386_TLS_IE:
6982 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6983 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6984 case BFD_RELOC_X86_64_TLSGD:
6985 case BFD_RELOC_X86_64_TLSLD:
6986 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6987 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6988 value = 0; /* Fully resolved at runtime. No addend. */
6989 /* Fallthrough */
6990 case BFD_RELOC_386_TLS_LE:
6991 case BFD_RELOC_386_TLS_LDO_32:
6992 case BFD_RELOC_386_TLS_LE_32:
6993 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6994 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6995 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6996 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6997 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6998 break;
6999
67a4f2b7
AO		 7000 case BFD_RELOC_386_TLS_DESC_CALL:
7001 case BFD_RELOC_X86_64_TLSDESC_CALL:
7002 value = 0; /* Fully resolved at runtime. No addend. */
7003 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7004 fixP->fx_done = 0;
7005 return;
7006
00f7efb6
JJ		 7007 case BFD_RELOC_386_GOT32:
7008 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7009 value = 0; /* Fully resolved at runtime. No addend. */
7010 break;
47926f60
KH		 7011
7012 case BFD_RELOC_VTABLE_INHERIT:
7013 case BFD_RELOC_VTABLE_ENTRY:
7014 fixP->fx_done = 0;
94f592af 7015 return;
47926f60
KH		 7016
7017 default:
7018 break;
7019 }
7020#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7021 *valP = value;
f86103b7 7022#endif /* !defined (TE_Mach) */
3e73aa7c 7023
3e73aa7c 7024 /* Are we finished with this relocation now? */
c6682705 7025 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 7026 fixP->fx_done = 1;
7027 else if (use_rela_relocations)
7028 {
7029 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7030 /* Remember value for tc_gen_reloc. */
7031 fixP->fx_addnumber = value;
3e73aa7c
JH		 7032 value = 0;
7033 }
f86103b7 7034
94f592af 7035 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7036}
252b5132 7037\f
252b5132 7038char *
499ac353 7039md_atof (int type, char *litP, int *sizeP)
252b5132 7040{
499ac353
NC		 7041 /* This outputs the LITTLENUMs in REVERSE order;
7042 in accord with the bigendian 386. */
7043 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7044}
7045\f
2d545b82 7046static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7047
252b5132 7048static char *
e3bb37b5 7049output_invalid (int c)
252b5132 7050{
3882b010 7051 if (ISPRINT (c))
f9f21a03
L		 7052 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7053 "'%c'", c);
252b5132 7054 else
f9f21a03 7055 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7056 "(0x%x)", (unsigned char) c);
252b5132
RH		 7057 return output_invalid_buf;
7058}
7059
af6bdddf 7060/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7061
7062static const reg_entry *
4d1bb795 7063parse_real_register (char *reg_string, char **end_op)
252b5132 7064{
af6bdddf
AM		 7065 char *s = reg_string;
7066 char *p;
252b5132
RH		 7067 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7068 const reg_entry *r;
7069
7070 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7071 if (*s == REGISTER_PREFIX)
7072 ++s;
7073
7074 if (is_space_char (*s))
7075 ++s;
7076
7077 p = reg_name_given;
af6bdddf 7078 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7079 {
7080 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7081 return (const reg_entry *) NULL;
7082 s++;
252b5132
RH		 7083 }
7084
6588847e
DN		 7085 /* For naked regs, make sure that we are not dealing with an identifier.
7086 This prevents confusing an identifier like `eax_var' with register
7087 `eax'. */
7088 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7089 return (const reg_entry *) NULL;
7090
af6bdddf 7091 *end_op = s;
252b5132
RH		 7092
7093 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7094
5f47d35b 7095 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7096 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7097 {
5f47d35b
AM		 7098 if (is_space_char (*s))
7099 ++s;
7100 if (*s == '(')
7101 {
af6bdddf 7102 ++s;
5f47d35b
AM		 7103 if (is_space_char (*s))
7104 ++s;
7105 if (*s >= '0' && *s <= '7')
7106 {
db557034 7107 int fpr = *s - '0';
af6bdddf 7108 ++s;
5f47d35b
AM		 7109 if (is_space_char (*s))
7110 ++s;
7111 if (*s == ')')
7112 {
7113 *end_op = s + 1;
db557034
AM		 7114 r = hash_find (reg_hash, "st(0)");
7115 know (r);
7116 return r + fpr;
5f47d35b 7117 }
5f47d35b 7118 }
47926f60 7119 /* We have "%st(" then garbage. */
5f47d35b
AM		 7120 return (const reg_entry *) NULL;
7121 }
7122 }
7123
a60de03c
JB		 7124 if (r == NULL || allow_pseudo_reg)
7125 return r;
7126
0dfbf9d7 7127 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7128 return (const reg_entry *) NULL;
7129
192dc9c6
JB		 7130 if ((r->reg_type.bitfield.reg32
7131 || r->reg_type.bitfield.sreg3
7132 || r->reg_type.bitfield.control
7133 || r->reg_type.bitfield.debug
7134 || r->reg_type.bitfield.test)
7135 && !cpu_arch_flags.bitfield.cpui386)
7136 return (const reg_entry *) NULL;
7137
7138 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7139 return (const reg_entry *) NULL;
7140
7141 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7142 return (const reg_entry *) NULL;
7143
db51cc60 7144 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7145 if (!allow_index_reg
db51cc60
L		 7146 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7147 return (const reg_entry *) NULL;
7148
a60de03c
JB		 7149 if (((r->reg_flags & (RegRex64 | RegRex))
7150 || r->reg_type.bitfield.reg64)
40fb9820 7151 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7152 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7153 && flag_code != CODE_64BIT)
20f0a1fc 7154 return (const reg_entry *) NULL;
1ae00879 7155
b7240065
JB		 7156 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7157 return (const reg_entry *) NULL;
7158
252b5132
RH		 7159 return r;
7160}
4d1bb795
JB		 7161
7162/* REG_STRING starts *before* REGISTER_PREFIX. */
7163
7164static const reg_entry *
7165parse_register (char *reg_string, char **end_op)
7166{
7167 const reg_entry *r;
7168
7169 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7170 r = parse_real_register (reg_string, end_op);
7171 else
7172 r = NULL;
7173 if (!r)
7174 {
7175 char *save = input_line_pointer;
7176 char c;
7177 symbolS *symbolP;
7178
7179 input_line_pointer = reg_string;
7180 c = get_symbol_end ();
7181 symbolP = symbol_find (reg_string);
7182 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7183 {
7184 const expressionS *e = symbol_get_value_expression (symbolP);
7185
7186 know (e->X_op == O_register);
4eed87de 7187 know (e->X_add_number >= 0
c3fe08fa 7188 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7189 r = i386_regtab + e->X_add_number;
7190 *end_op = input_line_pointer;
7191 }
7192 *input_line_pointer = c;
7193 input_line_pointer = save;
7194 }
7195 return r;
7196}
7197
7198int
7199i386_parse_name (char *name, expressionS *e, char *nextcharP)
7200{
7201 const reg_entry *r;
7202 char *end = input_line_pointer;
7203
7204 *end = *nextcharP;
7205 r = parse_register (name, &input_line_pointer);
7206 if (r && end <= input_line_pointer)
7207 {
7208 *nextcharP = *input_line_pointer;
7209 *input_line_pointer = 0;
7210 e->X_op = O_register;
7211 e->X_add_number = r - i386_regtab;
7212 return 1;
7213 }
7214 input_line_pointer = end;
7215 *end = 0;
7216 return 0;
7217}
7218
7219void
7220md_operand (expressionS *e)
7221{
7222 if (*input_line_pointer == REGISTER_PREFIX)
7223 {
7224 char *end;
7225 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7226
7227 if (r)
7228 {
7229 e->X_op = O_register;
7230 e->X_add_number = r - i386_regtab;
7231 input_line_pointer = end;
7232 }
7233 }
7234}
7235
252b5132 7236\f
4cc782b5 7237#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7238const char *md_shortopts = "kVQ:sqn";
252b5132 7239#else
12b55ccc 7240const char *md_shortopts = "qn";
252b5132 7241#endif
6e0b89ee 7242
3e73aa7c 7243#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7244#define OPTION_64 (OPTION_MD_BASE + 1)
7245#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7246#define OPTION_MARCH (OPTION_MD_BASE + 3)
7247#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7248#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7249#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7250#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7251#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7252#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
b3b91714 7253
99ad8390
NC		 7254struct option md_longopts[] =
7255{
3e73aa7c 7256 {"32", no_argument, NULL, OPTION_32},
99ad8390 7257#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7258 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7259#endif
b3b91714 7260 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7261 {"march", required_argument, NULL, OPTION_MARCH},
7262 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7263 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7264 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7265 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7266 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7267 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
252b5132
RH		 7268 {NULL, no_argument, NULL, 0}
7269};
7270size_t md_longopts_size = sizeof (md_longopts);
7271
7272int
9103f4f4 7273md_parse_option (int c, char *arg)
252b5132 7274{
9103f4f4 7275 unsigned int i;
6305a203 7276 char *arch, *next;
9103f4f4 7277
252b5132
RH		 7278 switch (c)
7279 {
12b55ccc
L		 7280 case 'n':
7281 optimize_align_code = 0;
7282 break;
7283
a38cf1db
AM		 7284 case 'q':
7285 quiet_warnings = 1;
252b5132
RH		 7286 break;
7287
7288#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7289 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7290 should be emitted or not. FIXME: Not implemented. */
7291 case 'Q':
252b5132
RH		 7292 break;
7293
7294 /* -V: SVR4 argument to print version ID. */
7295 case 'V':
7296 print_version_id ();
7297 break;
7298
a38cf1db
AM		 7299 /* -k: Ignore for FreeBSD compatibility. */
7300 case 'k':
252b5132 7301 break;
4cc782b5
ILT		 7302
7303 case 's':
7304 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7305 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7306 break;
99ad8390
NC		 7307#endif
7308#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 7309 case OPTION_64:
7310 {
7311 const char **list, **l;
7312
3e73aa7c
JH		 7313 list = bfd_target_list ();
7314 for (l = list; *l != NULL; l++)
8620418b 7315 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7316 || strcmp (*l, "coff-x86-64") == 0
7317 || strcmp (*l, "pe-x86-64") == 0
7318 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7319 {
7320 default_arch = "x86_64";
7321 break;
7322 }
3e73aa7c 7323 if (*l == NULL)
6e0b89ee 7324 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7325 free (list);
7326 }
7327 break;
7328#endif
252b5132 7329
6e0b89ee
AM		 7330 case OPTION_32:
7331 default_arch = "i386";
7332 break;
7333
b3b91714
AM		 7334 case OPTION_DIVIDE:
7335#ifdef SVR4_COMMENT_CHARS
7336 {
7337 char *n, *t;
7338 const char *s;
7339
7340 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7341 t = n;
7342 for (s = i386_comment_chars; *s != '\0'; s++)
7343 if (*s != '/')
7344 *t++ = *s;
7345 *t = '\0';
7346 i386_comment_chars = n;
7347 }
7348#endif
7349 break;
7350
9103f4f4 7351 case OPTION_MARCH:
6305a203
L		 7352 arch = xstrdup (arg);
7353 do
9103f4f4 7354 {
6305a203
L		 7355 if (*arch == '.')
7356 as_fatal (_("Invalid -march= option: `%s'"), arg);
7357 next = strchr (arch, '+');
7358 if (next)
7359 *next++ = '\0';
7360 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 7361 {
6305a203 7362 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 7363 {
6305a203
L		 7364 /* Processor. */
7365 cpu_arch_name = cpu_arch[i].name;
7366 cpu_sub_arch_name = NULL;
7367 cpu_arch_flags = cpu_arch[i].flags;
7368 cpu_arch_isa = cpu_arch[i].type;
7369 cpu_arch_isa_flags = cpu_arch[i].flags;
7370 if (!cpu_arch_tune_set)
7371 {
7372 cpu_arch_tune = cpu_arch_isa;
7373 cpu_arch_tune_flags = cpu_arch_isa_flags;
7374 }
7375 break;
7376 }
7377 else if (*cpu_arch [i].name == '.'
7378 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7379 {
7380 /* ISA entension. */
7381 i386_cpu_flags flags;
7382 flags = cpu_flags_or (cpu_arch_flags,
7383 cpu_arch[i].flags);
0dfbf9d7 7384 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 7385 {
7386 if (cpu_sub_arch_name)
7387 {
7388 char *name = cpu_sub_arch_name;
7389 cpu_sub_arch_name = concat (name,
7390 cpu_arch[i].name,
1bf57e9f 7391 (const char *) NULL);
6305a203
L		 7392 free (name);
7393 }
7394 else
7395 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7396 cpu_arch_flags = flags;
7397 }
7398 break;
ccc9c027 7399 }
9103f4f4 7400 }
6305a203
L		 7401
7402 if (i >= ARRAY_SIZE (cpu_arch))
7403 as_fatal (_("Invalid -march= option: `%s'"), arg);
7404
7405 arch = next;
9103f4f4 7406 }
6305a203 7407 while (next != NULL );
9103f4f4
L		 7408 break;
7409
7410 case OPTION_MTUNE:
7411 if (*arg == '.')
7412 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7413 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7414 {
7415 if (strcmp (arg, cpu_arch [i].name) == 0)
7416 {
ccc9c027 7417 cpu_arch_tune_set = 1;
9103f4f4
L		 7418 cpu_arch_tune = cpu_arch [i].type;
7419 cpu_arch_tune_flags = cpu_arch[i].flags;
7420 break;
7421 }
7422 }
7423 if (i >= ARRAY_SIZE (cpu_arch))
7424 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7425 break;
7426
1efbbeb4
L		 7427 case OPTION_MMNEMONIC:
7428 if (strcasecmp (arg, "att") == 0)
7429 intel_mnemonic = 0;
7430 else if (strcasecmp (arg, "intel") == 0)
7431 intel_mnemonic = 1;
7432 else
7433 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7434 break;
7435
7436 case OPTION_MSYNTAX:
7437 if (strcasecmp (arg, "att") == 0)
7438 intel_syntax = 0;
7439 else if (strcasecmp (arg, "intel") == 0)
7440 intel_syntax = 1;
7441 else
7442 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7443 break;
7444
7445 case OPTION_MINDEX_REG:
7446 allow_index_reg = 1;
7447 break;
7448
7449 case OPTION_MNAKED_REG:
7450 allow_naked_reg = 1;
7451 break;
7452
7453 case OPTION_MOLD_GCC:
7454 old_gcc = 1;
1efbbeb4
L		 7455 break;
7456
252b5132
RH		 7457 default:
7458 return 0;
7459 }
7460 return 1;
7461}
7462
7463void
7464md_show_usage (stream)
7465 FILE *stream;
7466{
4cc782b5
ILT		 7467#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7468 fprintf (stream, _("\
a38cf1db
AM		 7469 -Q ignored\n\
7470 -V print assembler version number\n\
b3b91714
AM		 7471 -k ignored\n"));
7472#endif
7473 fprintf (stream, _("\
12b55ccc 7474 -n Do not optimize code alignment\n\
b3b91714
AM		 7475 -q quieten some warnings\n"));
7476#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7477 fprintf (stream, _("\
a38cf1db 7478 -s ignored\n"));
b3b91714 7479#endif
751d281c
L		 7480#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7481 fprintf (stream, _("\
7482 --32/--64 generate 32bit/64bit code\n"));
7483#endif
b3b91714
AM		 7484#ifdef SVR4_COMMENT_CHARS
7485 fprintf (stream, _("\
7486 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7487#else
7488 fprintf (stream, _("\
b3b91714 7489 --divide ignored\n"));
4cc782b5 7490#endif
9103f4f4 7491 fprintf (stream, _("\
6305a203
L		 7492 -march=CPU[,+EXTENSION...]\n\
7493 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 7494 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7495 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7496 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7497 generic32, generic64\n\
599121aa
L		 7498 EXTENSION is combination of:\n\
7499 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
f03fe4c1
L		 7500 vmx, smx, xsave, 3dnow, 3dnowa, sse4a, sse5, svme,\n\
7501 abm, padlock\n"));
6305a203 7502 fprintf (stream, _("\
2cb4f3d5
L		 7503 -mtune=CPU optimize for CPU, CPU is one of:\n\
7504 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7505 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7506 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7507 generic32, generic64\n"));
ba104c83
L		 7508 fprintf (stream, _("\
7509 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7510 fprintf (stream, _("\
7511 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7512 fprintf (stream, _("\
7513 -mindex-reg support pseudo index registers\n"));
7514 fprintf (stream, _("\
7515 -mnaked-reg don't require `%%' prefix for registers\n"));
7516 fprintf (stream, _("\
7517 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 7518}
7519
3e73aa7c 7520#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 7521 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 7522
7523/* Pick the target format to use. */
7524
47926f60 7525const char *
e3bb37b5 7526i386_target_format (void)
252b5132 7527{
3e73aa7c 7528 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7529 {
7530 set_code_flag (CODE_64BIT);
0dfbf9d7 7531 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 7532 {
7533 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7534 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7535 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7536 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7537 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7538 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7539 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7540 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 7541 cpu_arch_isa_flags.bitfield.cpusse = 1;
7542 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7543 }
0dfbf9d7 7544 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 7545 {
7546 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7547 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7548 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7549 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7550 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7551 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7552 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7553 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 7554 cpu_arch_tune_flags.bitfield.cpusse = 1;
7555 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7556 }
9103f4f4 7557 }
3e73aa7c 7558 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7559 {
7560 set_code_flag (CODE_32BIT);
0dfbf9d7 7561 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 7562 {
7563 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7564 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7565 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7566 }
0dfbf9d7 7567 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 7568 {
7569 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7570 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7571 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7572 }
9103f4f4 7573 }
3e73aa7c
JH		 7574 else
7575 as_fatal (_("Unknown architecture"));
252b5132
RH		 7576 switch (OUTPUT_FLAVOR)
7577 {
872ce6ff
L		 7578#ifdef TE_PEP
7579 case bfd_target_coff_flavour:
7580 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7581 break;
7582#endif
4c63da97
AM		 7583#ifdef OBJ_MAYBE_AOUT
7584 case bfd_target_aout_flavour:
47926f60 7585 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7586#endif
7587#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7588 case bfd_target_coff_flavour:
7589 return "coff-i386";
4c63da97 7590#endif
3e73aa7c 7591#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7592 case bfd_target_elf_flavour:
3e73aa7c 7593 {
e5cb08ac 7594 if (flag_code == CODE_64BIT)
4fa24527
JB		 7595 {
7596 object_64bit = 1;
7597 use_rela_relocations = 1;
7598 }
9d7cbccd 7599 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7600 }
4c63da97 7601#endif
252b5132
RH		 7602 default:
7603 abort ();
7604 return NULL;
7605 }
7606}
7607
47926f60 7608#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 7609
7610#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 7611void
7612i386_elf_emit_arch_note (void)
a847613f 7613{
718ddfc0 7614 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 7615 {
7616 char *p;
7617 asection *seg = now_seg;
7618 subsegT subseg = now_subseg;
7619 Elf_Internal_Note i_note;
7620 Elf_External_Note e_note;
7621 asection *note_secp;
7622 int len;
7623
7624 /* Create the .note section. */
7625 note_secp = subseg_new (".note", 0);
7626 bfd_set_section_flags (stdoutput,
7627 note_secp,
7628 SEC_HAS_CONTENTS | SEC_READONLY);
7629
7630 /* Process the arch string. */
7631 len = strlen (cpu_arch_name);
7632
7633 i_note.namesz = len + 1;
7634 i_note.descsz = 0;
7635 i_note.type = NT_ARCH;
7636 p = frag_more (sizeof (e_note.namesz));
7637 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7638 p = frag_more (sizeof (e_note.descsz));
7639 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7640 p = frag_more (sizeof (e_note.type));
7641 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7642 p = frag_more (len + 1);
7643 strcpy (p, cpu_arch_name);
7644
7645 frag_align (2, 0, 0);
7646
7647 subseg_set (seg, subseg);
7648 }
7649}
7650#endif
252b5132 7651\f
252b5132
RH		 7652symbolS *
7653md_undefined_symbol (name)
7654 char *name;
7655{
18dc2407
ILT		 7656 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7657 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7658 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7659 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 7660 {
7661 if (!GOT_symbol)
7662 {
7663 if (symbol_find (name))
7664 as_bad (_("GOT already in symbol table"));
7665 GOT_symbol = symbol_new (name, undefined_section,
7666 (valueT) 0, &zero_address_frag);
7667 };
7668 return GOT_symbol;
7669 }
252b5132
RH		 7670 return 0;
7671}
7672
7673/* Round up a section size to the appropriate boundary. */
47926f60 7674
252b5132
RH		 7675valueT
7676md_section_align (segment, size)
ab9da554 7677 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7678 valueT size;
7679{
4c63da97
AM		 7680#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7681 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7682 {
7683 /* For a.out, force the section size to be aligned. If we don't do
7684 this, BFD will align it for us, but it will not write out the
7685 final bytes of the section. This may be a bug in BFD, but it is
7686 easier to fix it here since that is how the other a.out targets
7687 work. */
7688 int align;
7689
7690 align = bfd_get_section_alignment (stdoutput, segment);
7691 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7692 }
252b5132
RH		 7693#endif
7694
7695 return size;
7696}
7697
7698/* On the i386, PC-relative offsets are relative to the start of the
7699 next instruction. That is, the address of the offset, plus its
7700 size, since the offset is always the last part of the insn. */
7701
7702long
e3bb37b5 7703md_pcrel_from (fixS *fixP)
252b5132
RH		 7704{
7705 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7706}
7707
7708#ifndef I386COFF
7709
7710static void
e3bb37b5 7711s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 7712{
29b0f896 7713 int temp;
252b5132 7714
8a75718c
JB		 7715#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7716 if (IS_ELF)
7717 obj_elf_section_change_hook ();
7718#endif
252b5132
RH		 7719 temp = get_absolute_expression ();
7720 subseg_set (bss_section, (subsegT) temp);
7721 demand_empty_rest_of_line ();
7722}
7723
7724#endif
7725
252b5132 7726void
e3bb37b5 7727i386_validate_fix (fixS *fixp)
252b5132
RH		 7728{
7729 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7730 {
23df1078
JH		 7731 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7732 {
4fa24527 7733 if (!object_64bit)
23df1078
JH		 7734 abort ();
7735 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7736 }
7737 else
7738 {
4fa24527 7739 if (!object_64bit)
d6ab8113
JB		 7740 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7741 else
7742 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 7743 }
252b5132
RH		 7744 fixp->fx_subsy = 0;
7745 }
7746}
7747
252b5132
RH		 7748arelent *
7749tc_gen_reloc (section, fixp)
ab9da554 7750 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 7751 fixS *fixp;
7752{
7753 arelent *rel;
7754 bfd_reloc_code_real_type code;
7755
7756 switch (fixp->fx_r_type)
7757 {
3e73aa7c
JH		 7758 case BFD_RELOC_X86_64_PLT32:
7759 case BFD_RELOC_X86_64_GOT32:
7760 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 7761 case BFD_RELOC_386_PLT32:
7762 case BFD_RELOC_386_GOT32:
7763 case BFD_RELOC_386_GOTOFF:
7764 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 7765 case BFD_RELOC_386_TLS_GD:
7766 case BFD_RELOC_386_TLS_LDM:
7767 case BFD_RELOC_386_TLS_LDO_32:
7768 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7769 case BFD_RELOC_386_TLS_IE:
7770 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 7771 case BFD_RELOC_386_TLS_LE_32:
7772 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 7773 case BFD_RELOC_386_TLS_GOTDESC:
7774 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 7775 case BFD_RELOC_X86_64_TLSGD:
7776 case BFD_RELOC_X86_64_TLSLD:
7777 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7778 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 7779 case BFD_RELOC_X86_64_GOTTPOFF:
7780 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 7781 case BFD_RELOC_X86_64_TPOFF64:
7782 case BFD_RELOC_X86_64_GOTOFF64:
7783 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 7784 case BFD_RELOC_X86_64_GOT64:
7785 case BFD_RELOC_X86_64_GOTPCREL64:
7786 case BFD_RELOC_X86_64_GOTPC64:
7787 case BFD_RELOC_X86_64_GOTPLT64:
7788 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 7789 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7790 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 7791 case BFD_RELOC_RVA:
7792 case BFD_RELOC_VTABLE_ENTRY:
7793 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 7794#ifdef TE_PE
7795 case BFD_RELOC_32_SECREL:
7796#endif
252b5132
RH		 7797 code = fixp->fx_r_type;
7798 break;
dbbaec26
L		 7799 case BFD_RELOC_X86_64_32S:
7800 if (!fixp->fx_pcrel)
7801 {
7802 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7803 code = fixp->fx_r_type;
7804 break;
7805 }
252b5132 7806 default:
93382f6d 7807 if (fixp->fx_pcrel)
252b5132 7808 {
93382f6d
AM		 7809 switch (fixp->fx_size)
7810 {
7811 default:
b091f402
AM		 7812 as_bad_where (fixp->fx_file, fixp->fx_line,
7813 _("can not do %d byte pc-relative relocation"),
7814 fixp->fx_size);
93382f6d
AM		 7815 code = BFD_RELOC_32_PCREL;
7816 break;
7817 case 1: code = BFD_RELOC_8_PCREL; break;
7818 case 2: code = BFD_RELOC_16_PCREL; break;
7819 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 7820#ifdef BFD64
7821 case 8: code = BFD_RELOC_64_PCREL; break;
7822#endif
93382f6d
AM		 7823 }
7824 }
7825 else
7826 {
7827 switch (fixp->fx_size)
7828 {
7829 default:
b091f402
AM		 7830 as_bad_where (fixp->fx_file, fixp->fx_line,
7831 _("can not do %d byte relocation"),
7832 fixp->fx_size);
93382f6d
AM		 7833 code = BFD_RELOC_32;
7834 break;
7835 case 1: code = BFD_RELOC_8; break;
7836 case 2: code = BFD_RELOC_16; break;
7837 case 4: code = BFD_RELOC_32; break;
937149dd 7838#ifdef BFD64
3e73aa7c 7839 case 8: code = BFD_RELOC_64; break;
937149dd 7840#endif
93382f6d 7841 }
252b5132
RH		 7842 }
7843 break;
7844 }
252b5132 7845
d182319b
JB		 7846 if ((code == BFD_RELOC_32
7847 || code == BFD_RELOC_32_PCREL
7848 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7849 && GOT_symbol
7850 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7851 {
4fa24527 7852 if (!object_64bit)
d6ab8113
JB		 7853 code = BFD_RELOC_386_GOTPC;
7854 else
7855 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7856 }
7b81dfbb
AJ		 7857 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7858 && GOT_symbol
7859 && fixp->fx_addsy == GOT_symbol)
7860 {
7861 code = BFD_RELOC_X86_64_GOTPC64;
7862 }
252b5132
RH		 7863
7864 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7865 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7866 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7867
7868 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7869
3e73aa7c
JH		 7870 if (!use_rela_relocations)
7871 {
7872 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7873 vtable entry to be used in the relocation's section offset. */
7874 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7875 rel->address = fixp->fx_offset;
252b5132 7876
c6682705 7877 rel->addend = 0;
3e73aa7c
JH		 7878 }
7879 /* Use the rela in 64bit mode. */
252b5132 7880 else
3e73aa7c 7881 {
062cd5e7
AS		 7882 if (!fixp->fx_pcrel)
7883 rel->addend = fixp->fx_offset;
7884 else
7885 switch (code)
7886 {
7887 case BFD_RELOC_X86_64_PLT32:
7888 case BFD_RELOC_X86_64_GOT32:
7889 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7890 case BFD_RELOC_X86_64_TLSGD:
7891 case BFD_RELOC_X86_64_TLSLD:
7892 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7893 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7894 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7895 rel->addend = fixp->fx_offset - fixp->fx_size;
7896 break;
7897 default:
7898 rel->addend = (section->vma
7899 - fixp->fx_size
7900 + fixp->fx_addnumber
7901 + md_pcrel_from (fixp));
7902 break;
7903 }
3e73aa7c
JH		 7904 }
7905
252b5132
RH		 7906 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7907 if (rel->howto == NULL)
7908 {
7909 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7910 _("cannot represent relocation type %s"),
252b5132
RH		 7911 bfd_get_reloc_code_name (code));
7912 /* Set howto to a garbage value so that we can keep going. */
7913 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7914 assert (rel->howto != NULL);
7915 }
7916
7917 return rel;
7918}
7919
64a0c779
DN		 7920\f
7921/* Parse operands using Intel syntax. This implements a recursive descent
7922 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7923 Programmer's Guide.
7924
7925 FIXME: We do not recognize the full operand grammar defined in the MASM
7926 documentation. In particular, all the structure/union and
7927 high-level macro operands are missing.
7928
7929 Uppercase words are terminals, lower case words are non-terminals.
7930 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7931 bars '|' denote choices. Most grammar productions are implemented in
7932 functions called 'intel_<production>'.
7933
7934 Initial production is 'expr'.
7935
9306ca4a 7936 addOp + | -
64a0c779
DN		 7937
7938 alpha [a-zA-Z]
7939
9306ca4a
JB		 7940 binOp & | AND | \| | OR | ^ | XOR
7941
64a0c779
DN		 7942 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7943
7944 constant digits [[ radixOverride ]]
7945
9306ca4a 7946 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7947
7948 digits decdigit
b77a7acd
AJ		 7949 | digits decdigit
7950 | digits hexdigit
64a0c779
DN		 7951
7952 decdigit [0-9]
7953
9306ca4a
JB		 7954 e04 e04 addOp e05
7955 | e05
7956
7957 e05 e05 binOp e06
b77a7acd 7958 | e06
64a0c779
DN		 7959
7960 e06 e06 mulOp e09
b77a7acd 7961 | e09
64a0c779
DN		 7962
7963 e09 OFFSET e10
a724f0f4
JB		 7964 | SHORT e10
7965 | + e10
7966 | - e10
9306ca4a
JB		 7967 | ~ e10
7968 | NOT e10
64a0c779
DN		 7969 | e09 PTR e10
7970 | e09 : e10
7971 | e10
7972
7973 e10 e10 [ expr ]
b77a7acd 7974 | e11
64a0c779
DN		 7975
7976 e11 ( expr )
b77a7acd 7977 | [ expr ]
64a0c779
DN		 7978 | constant
7979 | dataType
7980 | id
7981 | $
7982 | register
7983
a724f0f4 7984 => expr expr cmpOp e04
9306ca4a 7985 | e04
64a0c779
DN		 7986
7987 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7988 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7989
7990 hexdigit a | b | c | d | e | f
b77a7acd 7991 | A | B | C | D | E | F
64a0c779
DN		 7992
7993 id alpha
b77a7acd 7994 | id alpha
64a0c779
DN		 7995 | id decdigit
7996
9306ca4a 7997 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7998
7999 quote " | '
8000
8001 register specialRegister
b77a7acd 8002 | gpRegister
64a0c779
DN		 8003 | byteRegister
8004
8005 segmentRegister CS | DS | ES | FS | GS | SS
8006
9306ca4a 8007 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 8008 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 8009 | TR3 | TR4 | TR5 | TR6 | TR7
8010
64a0c779
DN		 8011 We simplify the grammar in obvious places (e.g., register parsing is
8012 done by calling parse_register) and eliminate immediate left recursion
8013 to implement a recursive-descent parser.
8014
a724f0f4
JB		 8015 expr e04 expr'
8016
8017 expr' cmpOp e04 expr'
8018 | Empty
9306ca4a
JB		 8019
8020 e04 e05 e04'
8021
8022 e04' addOp e05 e04'
8023 | Empty
64a0c779
DN		 8024
8025 e05 e06 e05'
8026
9306ca4a 8027 e05' binOp e06 e05'
b77a7acd 8028 | Empty
64a0c779
DN		 8029
8030 e06 e09 e06'
8031
8032 e06' mulOp e09 e06'
b77a7acd 8033 | Empty
64a0c779
DN		 8034
8035 e09 OFFSET e10 e09'
a724f0f4
JB		 8036 | SHORT e10'
8037 | + e10'
8038 | - e10'
8039 | ~ e10'
8040 | NOT e10'
b77a7acd 8041 | e10 e09'
64a0c779
DN		 8042
8043 e09' PTR e10 e09'
b77a7acd 8044 | : e10 e09'
64a0c779
DN		 8045 | Empty
8046
8047 e10 e11 e10'
8048
8049 e10' [ expr ] e10'
b77a7acd 8050 | Empty
64a0c779
DN		 8051
8052 e11 ( expr )
b77a7acd 8053 | [ expr ]
64a0c779
DN		 8054 | BYTE
8055 | WORD
8056 | DWORD
9306ca4a 8057 | FWORD
64a0c779 8058 | QWORD
9306ca4a
JB		 8059 | TBYTE
8060 | OWORD
8061 | XMMWORD
64a0c779
DN		 8062 | .
8063 | $
8064 | register
8065 | id
8066 | constant */
8067
8068/* Parsing structure for the intel syntax parser. Used to implement the
8069 semantic actions for the operand grammar. */
8070struct intel_parser_s
8071 {
8072 char *op_string; /* The string being parsed. */
8073 int got_a_float; /* Whether the operand is a float. */
4a1805b1 8074 int op_modifier; /* Operand modifier. */
64a0c779 8075 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 8076 int in_offset; /* >=1 if parsing operand of offset. */
8077 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 8078 const reg_entry *reg; /* Last register reference found. */
8079 char *disp; /* Displacement string being built. */
a724f0f4 8080 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 8081 };
8082
8083static struct intel_parser_s intel_parser;
8084
8085/* Token structure for parsing intel syntax. */
8086struct intel_token
8087 {
8088 int code; /* Token code. */
8089 const reg_entry *reg; /* Register entry for register tokens. */
8090 char *str; /* String representation. */
8091 };
8092
8093static struct intel_token cur_token, prev_token;
8094
50705ef4
AM		 8095/* Token codes for the intel parser. Since T_SHORT is already used
8096 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 8097#define T_NIL -1
8098#define T_CONST 1
8099#define T_REG 2
8100#define T_BYTE 3
8101#define T_WORD 4
9306ca4a
JB		 8102#define T_DWORD 5
8103#define T_FWORD 6
8104#define T_QWORD 7
8105#define T_TBYTE 8
8106#define T_XMMWORD 9
50705ef4 8107#undef T_SHORT
9306ca4a
JB		 8108#define T_SHORT 10
8109#define T_OFFSET 11
8110#define T_PTR 12
8111#define T_ID 13
8112#define T_SHL 14
8113#define T_SHR 15
64a0c779
DN		 8114
8115/* Prototypes for intel parser functions. */
e3bb37b5
L		 8116static int intel_match_token (int);
8117static void intel_putback_token (void);
8118static void intel_get_token (void);
8119static int intel_expr (void);
8120static int intel_e04 (void);
8121static int intel_e05 (void);
8122static int intel_e06 (void);
8123static int intel_e09 (void);
8124static int intel_e10 (void);
8125static int intel_e11 (void);
64a0c779 8126
64a0c779 8127static int
e3bb37b5 8128i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 8129{
8130 int ret;
8131 char *p;
8132
a724f0f4
JB		 8133 p = intel_parser.op_string = xstrdup (operand_string);
8134 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8135
8136 for (;;)
64a0c779 8137 {
a724f0f4
JB		 8138 /* Initialize token holders. */
8139 cur_token.code = prev_token.code = T_NIL;
8140 cur_token.reg = prev_token.reg = NULL;
8141 cur_token.str = prev_token.str = NULL;
8142
8143 /* Initialize parser structure. */
8144 intel_parser.got_a_float = got_a_float;
8145 intel_parser.op_modifier = 0;
8146 intel_parser.is_mem = 0;
8147 intel_parser.in_offset = 0;
8148 intel_parser.in_bracket = 0;
8149 intel_parser.reg = NULL;
8150 intel_parser.disp[0] = '\0';
8151 intel_parser.next_operand = NULL;
8152
8153 /* Read the first token and start the parser. */
8154 intel_get_token ();
8155 ret = intel_expr ();
8156
8157 if (!ret)
8158 break;
8159
9306ca4a
JB		 8160 if (cur_token.code != T_NIL)
8161 {
8162 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8163 current_templates->start->name, cur_token.str);
8164 ret = 0;
8165 }
64a0c779
DN		 8166 /* If we found a memory reference, hand it over to i386_displacement
8167 to fill in the rest of the operand fields. */
9306ca4a 8168 else if (intel_parser.is_mem)
64a0c779
DN		 8169 {
8170 if ((i.mem_operands == 1
40fb9820 8171 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 8172 || i.mem_operands == 2)
8173 {
8174 as_bad (_("too many memory references for '%s'"),
8175 current_templates->start->name);
8176 ret = 0;
8177 }
8178 else
8179 {
8180 char *s = intel_parser.disp;
5c07affc 8181 i.types[this_operand].bitfield.mem = 1;
64a0c779
DN		 8182 i.mem_operands++;
8183
a724f0f4
JB		 8184 if (!quiet_warnings && intel_parser.is_mem < 0)
8185 /* See the comments in intel_bracket_expr. */
8186 as_warn (_("Treating `%s' as memory reference"), operand_string);
8187
64a0c779
DN		 8188 /* Add the displacement expression. */
8189 if (*s != '\0')
a4622f40
AM		 8190 ret = i386_displacement (s, s + strlen (s));
8191 if (ret)
a724f0f4
JB		 8192 {
8193 /* Swap base and index in 16-bit memory operands like
8194 [si+bx]. Since i386_index_check is also used in AT&T
8195 mode we have to do that here. */
8196 if (i.base_reg
8197 && i.index_reg
40fb9820
L		 8198 && i.base_reg->reg_type.bitfield.reg16
8199 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 8200 && i.base_reg->reg_num >= 6
8201 && i.index_reg->reg_num < 6)
8202 {
8203 const reg_entry *base = i.index_reg;
8204
8205 i.index_reg = i.base_reg;
8206 i.base_reg = base;
8207 }
8208 ret = i386_index_check (operand_string);
8209 }
64a0c779
DN		 8210 }
8211 }
8212
8213 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 8214 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779 8215 || intel_parser.reg == NULL)
b7240065
JB		 8216 {
8217 if (i.mem_operands < 2 && i.seg[i.mem_operands])
8218 {
8219 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8220 as_warn (_("Segment override ignored"));
8221 i.seg[i.mem_operands] = NULL;
8222 }
8223 ret = i386_immediate (intel_parser.disp);
8224 }
a724f0f4
JB		 8225
8226 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 8227 ret = 0;
a724f0f4
JB		 8228 if (!ret || !intel_parser.next_operand)
8229 break;
8230 intel_parser.op_string = intel_parser.next_operand;
8231 this_operand = i.operands++;
7d5e4556 8232 i.types[this_operand].bitfield.unspecified = 1;
64a0c779
DN		 8233 }
8234
8235 free (p);
8236 free (intel_parser.disp);
8237
8238 return ret;
8239}
8240
a724f0f4
JB		 8241#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8242
8243/* expr e04 expr'
8244
8245 expr' cmpOp e04 expr'
8246 | Empty */
64a0c779 8247static int
e3bb37b5 8248intel_expr (void)
64a0c779 8249{
a724f0f4
JB		 8250 /* XXX Implement the comparison operators. */
8251 return intel_e04 ();
9306ca4a
JB		 8252}
8253
a724f0f4 8254/* e04 e05 e04'
9306ca4a 8255
a724f0f4 8256 e04' addOp e05 e04'
9306ca4a
JB		 8257 | Empty */
8258static int
e3bb37b5 8259intel_e04 (void)
9306ca4a 8260{
a724f0f4 8261 int nregs = -1;
9306ca4a 8262
a724f0f4 8263 for (;;)
9306ca4a 8264 {
a724f0f4
JB		 8265 if (!intel_e05())
8266 return 0;
9306ca4a 8267
a724f0f4
JB		 8268 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8269 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 8270
a724f0f4
JB		 8271 if (cur_token.code == '+')
8272 nregs = -1;
8273 else if (cur_token.code == '-')
8274 nregs = NUM_ADDRESS_REGS;
8275 else
8276 return 1;
64a0c779 8277
a724f0f4
JB		 8278 strcat (intel_parser.disp, cur_token.str);
8279 intel_match_token (cur_token.code);
8280 }
64a0c779
DN		 8281}
8282
64a0c779
DN		 8283/* e05 e06 e05'
8284
9306ca4a 8285 e05' binOp e06 e05'
64a0c779
DN		 8286 | Empty */
8287static int
e3bb37b5 8288intel_e05 (void)
64a0c779 8289{
a724f0f4 8290 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8291
a724f0f4 8292 for (;;)
64a0c779 8293 {
a724f0f4
JB		 8294 if (!intel_e06())
8295 return 0;
8296
4eed87de
AM		 8297 if (cur_token.code == '&'
8298 || cur_token.code == '|'
8299 || cur_token.code == '^')
a724f0f4
JB		 8300 {
8301 char str[2];
8302
8303 str[0] = cur_token.code;
8304 str[1] = 0;
8305 strcat (intel_parser.disp, str);
8306 }
8307 else
8308 break;
9306ca4a 8309
64a0c779
DN		 8310 intel_match_token (cur_token.code);
8311
a724f0f4
JB		 8312 if (nregs < 0)
8313 nregs = ~nregs;
64a0c779 8314 }
a724f0f4
JB		 8315 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8316 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8317 return 1;
4a1805b1 8318}
64a0c779
DN		 8319
8320/* e06 e09 e06'
8321
8322 e06' mulOp e09 e06'
b77a7acd 8323 | Empty */
64a0c779 8324static int
e3bb37b5 8325intel_e06 (void)
64a0c779 8326{
a724f0f4 8327 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8328
a724f0f4 8329 for (;;)
64a0c779 8330 {
a724f0f4
JB		 8331 if (!intel_e09())
8332 return 0;
9306ca4a 8333
4eed87de
AM		 8334 if (cur_token.code == '*'
8335 || cur_token.code == '/'
8336 || cur_token.code == '%')
a724f0f4
JB		 8337 {
8338 char str[2];
9306ca4a 8339
a724f0f4
JB		 8340 str[0] = cur_token.code;
8341 str[1] = 0;
8342 strcat (intel_parser.disp, str);
8343 }
8344 else if (cur_token.code == T_SHL)
8345 strcat (intel_parser.disp, "<<");
8346 else if (cur_token.code == T_SHR)
8347 strcat (intel_parser.disp, ">>");
8348 else
8349 break;
9306ca4a 8350
64e74474 8351 intel_match_token (cur_token.code);
64a0c779 8352
a724f0f4
JB		 8353 if (nregs < 0)
8354 nregs = ~nregs;
64a0c779 8355 }
a724f0f4
JB		 8356 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8357 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8358 return 1;
64a0c779
DN		 8359}
8360
a724f0f4
JB		 8361/* e09 OFFSET e09
8362 | SHORT e09
8363 | + e09
8364 | - e09
8365 | ~ e09
8366 | NOT e09
9306ca4a
JB		 8367 | e10 e09'
8368
64a0c779 8369 e09' PTR e10 e09'
b77a7acd 8370 | : e10 e09'
64a0c779
DN		 8371 | Empty */
8372static int
e3bb37b5 8373intel_e09 (void)
64a0c779 8374{
a724f0f4
JB		 8375 int nregs = ~NUM_ADDRESS_REGS;
8376 int in_offset = 0;
8377
8378 for (;;)
64a0c779 8379 {
a724f0f4
JB		 8380 /* Don't consume constants here. */
8381 if (cur_token.code == '+' || cur_token.code == '-')
8382 {
8383 /* Need to look one token ahead - if the next token
8384 is a constant, the current token is its sign. */
8385 int next_code;
8386
8387 intel_match_token (cur_token.code);
8388 next_code = cur_token.code;
8389 intel_putback_token ();
8390 if (next_code == T_CONST)
8391 break;
8392 }
8393
8394 /* e09 OFFSET e09 */
8395 if (cur_token.code == T_OFFSET)
8396 {
8397 if (!in_offset++)
8398 ++intel_parser.in_offset;
8399 }
8400
8401 /* e09 SHORT e09 */
8402 else if (cur_token.code == T_SHORT)
8403 intel_parser.op_modifier |= 1 << T_SHORT;
8404
8405 /* e09 + e09 */
8406 else if (cur_token.code == '+')
8407 strcat (intel_parser.disp, "+");
8408
8409 /* e09 - e09
8410 | ~ e09
8411 | NOT e09 */
8412 else if (cur_token.code == '-' || cur_token.code == '~')
8413 {
8414 char str[2];
64a0c779 8415
a724f0f4
JB		 8416 if (nregs < 0)
8417 nregs = ~nregs;
8418 str[0] = cur_token.code;
8419 str[1] = 0;
8420 strcat (intel_parser.disp, str);
8421 }
8422
8423 /* e09 e10 e09' */
8424 else
8425 break;
8426
8427 intel_match_token (cur_token.code);
64a0c779
DN		 8428 }
8429
a724f0f4 8430 for (;;)
9306ca4a 8431 {
a724f0f4
JB		 8432 if (!intel_e10 ())
8433 return 0;
9306ca4a 8434
a724f0f4
JB		 8435 /* e09' PTR e10 e09' */
8436 if (cur_token.code == T_PTR)
8437 {
8438 char suffix;
9306ca4a 8439
a724f0f4 8440 if (prev_token.code == T_BYTE)
7d5e4556
L		 8441 {
8442 suffix = BYTE_MNEM_SUFFIX;
8443 i.types[this_operand].bitfield.byte = 1;
8444 }
9306ca4a 8445
a724f0f4
JB		 8446 else if (prev_token.code == T_WORD)
8447 {
34b772a6
JB		 8448 if ((current_templates->start->name[0] == 'l'
8449 && current_templates->start->name[2] == 's'
8450 && current_templates->start->name[3] == 0)
8451 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 8452 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8453 else if (intel_parser.got_a_float == 2) /* "fi..." */
8454 suffix = SHORT_MNEM_SUFFIX;
8455 else
8456 suffix = WORD_MNEM_SUFFIX;
7d5e4556 8457 i.types[this_operand].bitfield.word = 1;
a724f0f4 8458 }
64a0c779 8459
a724f0f4
JB		 8460 else if (prev_token.code == T_DWORD)
8461 {
34b772a6
JB		 8462 if ((current_templates->start->name[0] == 'l'
8463 && current_templates->start->name[2] == 's'
8464 && current_templates->start->name[3] == 0)
8465 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 8466 suffix = WORD_MNEM_SUFFIX;
8467 else if (flag_code == CODE_16BIT
40fb9820
L		 8468 && (current_templates->start->opcode_modifier.jump
8469 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 8470 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8471 else if (intel_parser.got_a_float == 1) /* "f..." */
8472 suffix = SHORT_MNEM_SUFFIX;
8473 else
8474 suffix = LONG_MNEM_SUFFIX;
7d5e4556 8475 i.types[this_operand].bitfield.dword = 1;
a724f0f4 8476 }
9306ca4a 8477
a724f0f4
JB		 8478 else if (prev_token.code == T_FWORD)
8479 {
8480 if (current_templates->start->name[0] == 'l'
8481 && current_templates->start->name[2] == 's'
8482 && current_templates->start->name[3] == 0)
8483 suffix = LONG_MNEM_SUFFIX;
8484 else if (!intel_parser.got_a_float)
8485 {
8486 if (flag_code == CODE_16BIT)
8487 add_prefix (DATA_PREFIX_OPCODE);
8488 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8489 }
8490 else
8491 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7d5e4556 8492 i.types[this_operand].bitfield.fword = 1;
a724f0f4 8493 }
64a0c779 8494
a724f0f4
JB		 8495 else if (prev_token.code == T_QWORD)
8496 {
34b772a6
JB		 8497 if (current_templates->start->base_opcode == 0x62 /* bound */
8498 || intel_parser.got_a_float == 1) /* "f..." */
a724f0f4
JB		 8499 suffix = LONG_MNEM_SUFFIX;
8500 else
34b772a6 8501 suffix = QWORD_MNEM_SUFFIX;
7d5e4556 8502 i.types[this_operand].bitfield.qword = 1;
a724f0f4 8503 }
64a0c779 8504
a724f0f4
JB		 8505 else if (prev_token.code == T_TBYTE)
8506 {
8507 if (intel_parser.got_a_float == 1)
8508 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8509 else
8510 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8511 }
9306ca4a 8512
a724f0f4 8513 else if (prev_token.code == T_XMMWORD)
9306ca4a 8514 {
582d5edd 8515 suffix = XMMWORD_MNEM_SUFFIX;
7d5e4556 8516 i.types[this_operand].bitfield.xmmword = 1;
9306ca4a 8517 }
64a0c779 8518
f16b83df 8519 else
a724f0f4
JB		 8520 {
8521 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8522 return 0;
8523 }
8524
7d5e4556
L		 8525 i.types[this_operand].bitfield.unspecified = 0;
8526
435acd52
JB		 8527 /* Operands for jump/call using 'ptr' notation denote absolute
8528 addresses. */
40fb9820
L		 8529 if (current_templates->start->opcode_modifier.jump
8530 || current_templates->start->opcode_modifier.jumpdword)
8531 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8532
a724f0f4
JB		 8533 if (current_templates->start->base_opcode == 0x8d /* lea */)
8534 ;
8535 else if (!i.suffix)
8536 i.suffix = suffix;
8537 else if (i.suffix != suffix)
8538 {
8539 as_bad (_("Conflicting operand modifiers"));
8540 return 0;
8541 }
64a0c779 8542
9306ca4a
JB		 8543 }
8544
a724f0f4
JB		 8545 /* e09' : e10 e09' */
8546 else if (cur_token.code == ':')
9306ca4a 8547 {
a724f0f4
JB		 8548 if (prev_token.code != T_REG)
8549 {
8550 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8551 segment/group identifier (which we don't have), using comma
8552 as the operand separator there is even less consistent, since
8553 there all branches only have a single operand. */
8554 if (this_operand != 0
8555 || intel_parser.in_offset
8556 || intel_parser.in_bracket
40fb9820
L		 8557 || (!current_templates->start->opcode_modifier.jump
8558 && !current_templates->start->opcode_modifier.jumpdword
8559 && !current_templates->start->opcode_modifier.jumpintersegment
8560 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 8561 return intel_match_token (T_NIL);
8562 /* Remember the start of the 2nd operand and terminate 1st
8563 operand here.
8564 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8565 another expression), but it gets at least the simplest case
8566 (a plain number or symbol on the left side) right. */
8567 intel_parser.next_operand = intel_parser.op_string;
8568 *--intel_parser.op_string = '\0';
8569 return intel_match_token (':');
8570 }
9306ca4a 8571 }
64a0c779 8572
a724f0f4 8573 /* e09' Empty */
64a0c779 8574 else
a724f0f4 8575 break;
64a0c779 8576
a724f0f4
JB		 8577 intel_match_token (cur_token.code);
8578
8579 }
8580
8581 if (in_offset)
8582 {
8583 --intel_parser.in_offset;
8584 if (nregs < 0)
8585 nregs = ~nregs;
8586 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 8587 {
a724f0f4 8588 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 8589 return 0;
8590 }
a724f0f4
JB		 8591 intel_parser.op_modifier |= 1 << T_OFFSET;
8592 }
9306ca4a 8593
a724f0f4
JB		 8594 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8595 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8596 return 1;
8597}
64a0c779 8598
a724f0f4 8599static int
e3bb37b5 8600intel_bracket_expr (void)
a724f0f4
JB		 8601{
8602 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8603 const char *start = intel_parser.op_string;
8604 int len;
8605
8606 if (i.op[this_operand].regs)
8607 return intel_match_token (T_NIL);
8608
8609 intel_match_token ('[');
8610
8611 /* Mark as a memory operand only if it's not already known to be an
8612 offset expression. If it's an offset expression, we need to keep
8613 the brace in. */
8614 if (!intel_parser.in_offset)
8615 {
8616 ++intel_parser.in_bracket;
435acd52
JB		 8617
8618 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 8619 if (current_templates->start->opcode_modifier.jump
8620 || current_templates->start->opcode_modifier.jumpdword)
8621 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8622
a724f0f4
JB		 8623 /* Unfortunately gas always diverged from MASM in a respect that can't
8624 be easily fixed without risking to break code sequences likely to be
8625 encountered (the testsuite even check for this): MASM doesn't consider
8626 an expression inside brackets unconditionally as a memory reference.
8627 When that is e.g. a constant, an offset expression, or the sum of the
8628 two, this is still taken as a constant load. gas, however, always
8629 treated these as memory references. As a compromise, we'll try to make
8630 offset expressions inside brackets work the MASM way (since that's
8631 less likely to be found in real world code), but make constants alone
8632 continue to work the traditional gas way. In either case, issue a
8633 warning. */
8634 intel_parser.op_modifier &= ~was_offset;
64a0c779 8635 }
a724f0f4 8636 else
64e74474 8637 strcat (intel_parser.disp, "[");
a724f0f4
JB		 8638
8639 /* Add a '+' to the displacement string if necessary. */
8640 if (*intel_parser.disp != '\0'
8641 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8642 strcat (intel_parser.disp, "+");
64a0c779 8643
a724f0f4
JB		 8644 if (intel_expr ()
8645 && (len = intel_parser.op_string - start - 1,
8646 intel_match_token (']')))
64a0c779 8647 {
a724f0f4
JB		 8648 /* Preserve brackets when the operand is an offset expression. */
8649 if (intel_parser.in_offset)
8650 strcat (intel_parser.disp, "]");
8651 else
8652 {
8653 --intel_parser.in_bracket;
8654 if (i.base_reg || i.index_reg)
8655 intel_parser.is_mem = 1;
8656 if (!intel_parser.is_mem)
8657 {
8658 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8659 /* Defer the warning until all of the operand was parsed. */
8660 intel_parser.is_mem = -1;
8661 else if (!quiet_warnings)
4eed87de
AM		 8662 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8663 len, start, len, start);
a724f0f4
JB		 8664 }
8665 }
8666 intel_parser.op_modifier |= was_offset;
64a0c779 8667
a724f0f4 8668 return 1;
64a0c779 8669 }
a724f0f4 8670 return 0;
64a0c779
DN		 8671}
8672
8673/* e10 e11 e10'
8674
8675 e10' [ expr ] e10'
b77a7acd 8676 | Empty */
64a0c779 8677static int
e3bb37b5 8678intel_e10 (void)
64a0c779 8679{
a724f0f4
JB		 8680 if (!intel_e11 ())
8681 return 0;
64a0c779 8682
a724f0f4 8683 while (cur_token.code == '[')
64a0c779 8684 {
a724f0f4 8685 if (!intel_bracket_expr ())
21d6c4af 8686 return 0;
64a0c779
DN		 8687 }
8688
a724f0f4 8689 return 1;
64a0c779
DN		 8690}
8691
64a0c779 8692/* e11 ( expr )
b77a7acd 8693 | [ expr ]
64a0c779
DN		 8694 | BYTE
8695 | WORD
8696 | DWORD
9306ca4a 8697 | FWORD
64a0c779 8698 | QWORD
9306ca4a
JB		 8699 | TBYTE
8700 | OWORD
8701 | XMMWORD
4a1805b1 8702 | $
64a0c779
DN		 8703 | .
8704 | register
8705 | id
8706 | constant */
8707static int
e3bb37b5 8708intel_e11 (void)
64a0c779 8709{
a724f0f4 8710 switch (cur_token.code)
64a0c779 8711 {
a724f0f4
JB		 8712 /* e11 ( expr ) */
8713 case '(':
64a0c779
DN		 8714 intel_match_token ('(');
8715 strcat (intel_parser.disp, "(");
8716
8717 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 8718 {
8719 strcat (intel_parser.disp, ")");
8720 return 1;
8721 }
a724f0f4 8722 return 0;
4a1805b1 8723
a724f0f4
JB		 8724 /* e11 [ expr ] */
8725 case '[':
a724f0f4 8726 return intel_bracket_expr ();
64a0c779 8727
a724f0f4
JB		 8728 /* e11 $
8729 | . */
8730 case '.':
64a0c779
DN		 8731 strcat (intel_parser.disp, cur_token.str);
8732 intel_match_token (cur_token.code);
21d6c4af
DN		 8733
8734 /* Mark as a memory operand only if it's not already known to be an
8735 offset expression. */
a724f0f4 8736 if (!intel_parser.in_offset)
21d6c4af 8737 intel_parser.is_mem = 1;
64a0c779
DN		 8738
8739 return 1;
64a0c779 8740
a724f0f4
JB		 8741 /* e11 register */
8742 case T_REG:
8743 {
8744 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 8745
a724f0f4 8746 intel_match_token (T_REG);
64a0c779 8747
a724f0f4
JB		 8748 /* Check for segment change. */
8749 if (cur_token.code == ':')
8750 {
40fb9820
L		 8751 if (!reg->reg_type.bitfield.sreg2
8752 && !reg->reg_type.bitfield.sreg3)
a724f0f4 8753 {
4eed87de
AM		 8754 as_bad (_("`%s' is not a valid segment register"),
8755 reg->reg_name);
a724f0f4
JB		 8756 return 0;
8757 }
b7240065
JB		 8758 else if (i.mem_operands >= 2)
8759 as_warn (_("Segment override ignored"));
a724f0f4
JB		 8760 else if (i.seg[i.mem_operands])
8761 as_warn (_("Extra segment override ignored"));
8762 else
8763 {
8764 if (!intel_parser.in_offset)
8765 intel_parser.is_mem = 1;
8766 switch (reg->reg_num)
8767 {
8768 case 0:
8769 i.seg[i.mem_operands] = &es;
8770 break;
8771 case 1:
8772 i.seg[i.mem_operands] = &cs;
8773 break;
8774 case 2:
8775 i.seg[i.mem_operands] = &ss;
8776 break;
8777 case 3:
8778 i.seg[i.mem_operands] = &ds;
8779 break;
8780 case 4:
8781 i.seg[i.mem_operands] = &fs;
8782 break;
8783 case 5:
8784 i.seg[i.mem_operands] = &gs;
8785 break;
8786 }
8787 }
8788 }
64a0c779 8789
b7240065
JB		 8790 else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
8791 {
8792 as_bad (_("cannot use `FLAT' here"));
8793 return 0;
8794 }
8795
a724f0f4
JB		 8796 /* Not a segment register. Check for register scaling. */
8797 else if (cur_token.code == '*')
8798 {
8799 if (!intel_parser.in_bracket)
8800 {
8801 as_bad (_("Register scaling only allowed in memory operands"));
8802 return 0;
8803 }
64a0c779 8804
40fb9820 8805 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 8806 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8807 else if (i.index_reg)
8808 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 8809
a724f0f4
JB		 8810 /* What follows must be a valid scale. */
8811 intel_match_token ('*');
8812 i.index_reg = reg;
40fb9820 8813 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 8814
a724f0f4
JB		 8815 /* Set the scale after setting the register (otherwise,
8816 i386_scale will complain) */
8817 if (cur_token.code == '+' || cur_token.code == '-')
8818 {
8819 char *str, sign = cur_token.code;
8820 intel_match_token (cur_token.code);
8821 if (cur_token.code != T_CONST)
8822 {
8823 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8824 cur_token.str);
8825 return 0;
8826 }
8827 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8828 strcpy (str + 1, cur_token.str);
8829 *str = sign;
8830 if (!i386_scale (str))
8831 return 0;
8832 free (str);
8833 }
8834 else if (!i386_scale (cur_token.str))
64a0c779 8835 return 0;
a724f0f4
JB		 8836 intel_match_token (cur_token.code);
8837 }
64a0c779 8838
a724f0f4
JB		 8839 /* No scaling. If this is a memory operand, the register is either a
8840 base register (first occurrence) or an index register (second
8841 occurrence). */
7b0441f6 8842 else if (intel_parser.in_bracket)
a724f0f4 8843 {
64a0c779 8844
a724f0f4
JB		 8845 if (!i.base_reg)
8846 i.base_reg = reg;
8847 else if (!i.index_reg)
8848 i.index_reg = reg;
8849 else
8850 {
8851 as_bad (_("Too many register references in memory operand"));
8852 return 0;
8853 }
64a0c779 8854
40fb9820 8855 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8856 }
4a1805b1 8857
4d1bb795
JB		 8858 /* It's neither base nor index. */
8859 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8860 {
40fb9820
L		 8861 i386_operand_type temp = reg->reg_type;
8862 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8863 i.types[this_operand] = operand_type_or (i.types[this_operand],
8864 temp);
7d5e4556 8865 i.types[this_operand].bitfield.unspecified = 0;
a724f0f4
JB		 8866 i.op[this_operand].regs = reg;
8867 i.reg_operands++;
8868 }
8869 else
8870 {
8871 as_bad (_("Invalid use of register"));
8872 return 0;
8873 }
64a0c779 8874
a724f0f4
JB		 8875 /* Since registers are not part of the displacement string (except
8876 when we're parsing offset operands), we may need to remove any
8877 preceding '+' from the displacement string. */
8878 if (*intel_parser.disp != '\0'
8879 && !intel_parser.in_offset)
8880 {
8881 char *s = intel_parser.disp;
8882 s += strlen (s) - 1;
8883 if (*s == '+')
8884 *s = '\0';
8885 }
4a1805b1 8886
a724f0f4
JB		 8887 return 1;
8888 }
8889
8890 /* e11 BYTE
8891 | WORD
8892 | DWORD
8893 | FWORD
8894 | QWORD
8895 | TBYTE
8896 | OWORD
8897 | XMMWORD */
8898 case T_BYTE:
8899 case T_WORD:
8900 case T_DWORD:
8901 case T_FWORD:
8902 case T_QWORD:
8903 case T_TBYTE:
8904 case T_XMMWORD:
8905 intel_match_token (cur_token.code);
64a0c779 8906
a724f0f4
JB		 8907 if (cur_token.code == T_PTR)
8908 return 1;
8909
8910 /* It must have been an identifier. */
8911 intel_putback_token ();
8912 cur_token.code = T_ID;
8913 /* FALLTHRU */
8914
8915 /* e11 id
8916 | constant */
8917 case T_ID:
8918 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8919 {
8920 symbolS *symbolP;
8921
a724f0f4
JB		 8922 /* The identifier represents a memory reference only if it's not
8923 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8924 symbolP = symbol_find(cur_token.str);
8925 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8926 intel_parser.is_mem = 1;
8927 }
a724f0f4 8928 /* FALLTHRU */
64a0c779 8929
a724f0f4
JB		 8930 case T_CONST:
8931 case '-':
8932 case '+':
8933 {
8934 char *save_str, sign = 0;
64a0c779 8935
a724f0f4
JB		 8936 /* Allow constants that start with `+' or `-'. */
8937 if (cur_token.code == '-' || cur_token.code == '+')
8938 {
8939 sign = cur_token.code;
8940 intel_match_token (cur_token.code);
8941 if (cur_token.code != T_CONST)
8942 {
8943 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8944 cur_token.str);
8945 return 0;
8946 }
8947 }
64a0c779 8948
a724f0f4
JB		 8949 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8950 strcpy (save_str + !!sign, cur_token.str);
8951 if (sign)
8952 *save_str = sign;
64a0c779 8953
a724f0f4
JB		 8954 /* Get the next token to check for register scaling. */
8955 intel_match_token (cur_token.code);
64a0c779 8956
4eed87de
AM		 8957 /* Check if this constant is a scaling factor for an
8958 index register. */
a724f0f4
JB		 8959 if (cur_token.code == '*')
8960 {
8961 if (intel_match_token ('*') && cur_token.code == T_REG)
8962 {
8963 const reg_entry *reg = cur_token.reg;
8964
8965 if (!intel_parser.in_bracket)
8966 {
4eed87de
AM		 8967 as_bad (_("Register scaling only allowed "
8968 "in memory operands"));
a724f0f4
JB		 8969 return 0;
8970 }
8971
4eed87de
AM		 8972 /* Disallow things like [1*si].
8973 sp and esp are invalid as index. */
40fb9820 8974 if (reg->reg_type.bitfield.reg16)
4eed87de 8975 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8976 else if (i.index_reg)
4eed87de 8977 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8978
8979 /* The constant is followed by `* reg', so it must be
8980 a valid scale. */
8981 i.index_reg = reg;
40fb9820 8982 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8983
8984 /* Set the scale after setting the register (otherwise,
8985 i386_scale will complain) */
8986 if (!i386_scale (save_str))
64a0c779 8987 return 0;
a724f0f4
JB		 8988 intel_match_token (T_REG);
8989
8990 /* Since registers are not part of the displacement
8991 string, we may need to remove any preceding '+' from
8992 the displacement string. */
8993 if (*intel_parser.disp != '\0')
8994 {
8995 char *s = intel_parser.disp;
8996 s += strlen (s) - 1;
8997 if (*s == '+')
8998 *s = '\0';
8999 }
9000
9001 free (save_str);
9002
9003 return 1;
9004 }
64a0c779 9005
a724f0f4
JB		 9006 /* The constant was not used for register scaling. Since we have
9007 already consumed the token following `*' we now need to put it
9008 back in the stream. */
64a0c779 9009 intel_putback_token ();
a724f0f4 9010 }
64a0c779 9011
a724f0f4
JB		 9012 /* Add the constant to the displacement string. */
9013 strcat (intel_parser.disp, save_str);
9014 free (save_str);
64a0c779 9015
a724f0f4
JB		 9016 return 1;
9017 }
64a0c779
DN		 9018 }
9019
64a0c779
DN		 9020 as_bad (_("Unrecognized token '%s'"), cur_token.str);
9021 return 0;
9022}
9023
64a0c779
DN		 9024/* Match the given token against cur_token. If they match, read the next
9025 token from the operand string. */
9026static int
e3bb37b5 9027intel_match_token (int code)
64a0c779
DN		 9028{
9029 if (cur_token.code == code)
9030 {
9031 intel_get_token ();
9032 return 1;
9033 }
9034 else
9035 {
0477af35 9036 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 9037 return 0;
9038 }
9039}
9040
64a0c779
DN		 9041/* Read a new token from intel_parser.op_string and store it in cur_token. */
9042static void
e3bb37b5 9043intel_get_token (void)
64a0c779
DN		 9044{
9045 char *end_op;
9046 const reg_entry *reg;
9047 struct intel_token new_token;
9048
9049 new_token.code = T_NIL;
9050 new_token.reg = NULL;
9051 new_token.str = NULL;
9052
4a1805b1 9053 /* Free the memory allocated to the previous token and move
64a0c779
DN		 9054 cur_token to prev_token. */
9055 if (prev_token.str)
9056 free (prev_token.str);
9057
9058 prev_token = cur_token;
9059
9060 /* Skip whitespace. */
9061 while (is_space_char (*intel_parser.op_string))
9062 intel_parser.op_string++;
9063
9064 /* Return an empty token if we find nothing else on the line. */
9065 if (*intel_parser.op_string == '\0')
9066 {
9067 cur_token = new_token;
9068 return;
9069 }
9070
9071 /* The new token cannot be larger than the remainder of the operand
9072 string. */
a724f0f4 9073 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 9074 new_token.str[0] = '\0';
9075
9076 if (strchr ("0123456789", *intel_parser.op_string))
9077 {
9078 char *p = new_token.str;
9079 char *q = intel_parser.op_string;
9080 new_token.code = T_CONST;
9081
9082 /* Allow any kind of identifier char to encompass floating point and
9083 hexadecimal numbers. */
9084 while (is_identifier_char (*q))
9085 *p++ = *q++;
9086 *p = '\0';
9087
9088 /* Recognize special symbol names [0-9][bf]. */
9089 if (strlen (intel_parser.op_string) == 2
4a1805b1 9090 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 9091 || intel_parser.op_string[1] == 'f'))
9092 new_token.code = T_ID;
9093 }
9094
4d1bb795 9095 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 9096 {
4d1bb795
JB		 9097 size_t len = end_op - intel_parser.op_string;
9098
64a0c779
DN		 9099 new_token.code = T_REG;
9100 new_token.reg = reg;
9101
4d1bb795
JB		 9102 memcpy (new_token.str, intel_parser.op_string, len);
9103 new_token.str[len] = '\0';
64a0c779
DN		 9104 }
9105
9106 else if (is_identifier_char (*intel_parser.op_string))
9107 {
9108 char *p = new_token.str;
9109 char *q = intel_parser.op_string;
9110
9111 /* A '.' or '$' followed by an identifier char is an identifier.
9112 Otherwise, it's operator '.' followed by an expression. */
9113 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9114 {
9306ca4a
JB		 9115 new_token.code = '.';
9116 new_token.str[0] = '.';
64a0c779
DN		 9117 new_token.str[1] = '\0';
9118 }
9119 else
9120 {
9121 while (is_identifier_char (*q) || *q == '@')
9122 *p++ = *q++;
9123 *p = '\0';
9124
9306ca4a
JB		 9125 if (strcasecmp (new_token.str, "NOT") == 0)
9126 new_token.code = '~';
9127
9128 else if (strcasecmp (new_token.str, "MOD") == 0)
9129 new_token.code = '%';
9130
9131 else if (strcasecmp (new_token.str, "AND") == 0)
9132 new_token.code = '&';
9133
9134 else if (strcasecmp (new_token.str, "OR") == 0)
9135 new_token.code = '|';
9136
9137 else if (strcasecmp (new_token.str, "XOR") == 0)
9138 new_token.code = '^';
9139
9140 else if (strcasecmp (new_token.str, "SHL") == 0)
9141 new_token.code = T_SHL;
9142
9143 else if (strcasecmp (new_token.str, "SHR") == 0)
9144 new_token.code = T_SHR;
9145
9146 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 9147 new_token.code = T_BYTE;
9148
9149 else if (strcasecmp (new_token.str, "WORD") == 0)
9150 new_token.code = T_WORD;
9151
9152 else if (strcasecmp (new_token.str, "DWORD") == 0)
9153 new_token.code = T_DWORD;
9154
9306ca4a
JB		 9155 else if (strcasecmp (new_token.str, "FWORD") == 0)
9156 new_token.code = T_FWORD;
9157
64a0c779
DN		 9158 else if (strcasecmp (new_token.str, "QWORD") == 0)
9159 new_token.code = T_QWORD;
9160
9306ca4a
JB		 9161 else if (strcasecmp (new_token.str, "TBYTE") == 0
9162 /* XXX remove (gcc still uses it) */
9163 || strcasecmp (new_token.str, "XWORD") == 0)
9164 new_token.code = T_TBYTE;
9165
9166 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9167 || strcasecmp (new_token.str, "OWORD") == 0)
9168 new_token.code = T_XMMWORD;
64a0c779
DN		 9169
9170 else if (strcasecmp (new_token.str, "PTR") == 0)
9171 new_token.code = T_PTR;
9172
9173 else if (strcasecmp (new_token.str, "SHORT") == 0)
9174 new_token.code = T_SHORT;
9175
9176 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9177 {
9178 new_token.code = T_OFFSET;
9179
9180 /* ??? This is not mentioned in the MASM grammar but gcc
9181 makes use of it with -mintel-syntax. OFFSET may be
9182 followed by FLAT: */
9183 if (strncasecmp (q, " FLAT:", 6) == 0)
9184 strcat (new_token.str, " FLAT:");
9185 }
9186
64a0c779
DN		 9187 else
9188 new_token.code = T_ID;
9189 }
9190 }
9191
9306ca4a
JB		 9192 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9193 {
9194 new_token.code = *intel_parser.op_string;
9195 new_token.str[0] = *intel_parser.op_string;
9196 new_token.str[1] = '\0';
9197 }
9198
9199 else if (strchr ("<>", *intel_parser.op_string)
9200 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9201 {
9202 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9203 new_token.str[0] = *intel_parser.op_string;
9204 new_token.str[1] = *intel_parser.op_string;
9205 new_token.str[2] = '\0';
9206 }
9207
64a0c779 9208 else
0477af35 9209 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 9210
9211 intel_parser.op_string += strlen (new_token.str);
9212 cur_token = new_token;
9213}
9214
64a0c779
DN		 9215/* Put cur_token back into the token stream and make cur_token point to
9216 prev_token. */
9217static void
e3bb37b5 9218intel_putback_token (void)
64a0c779 9219{
a724f0f4
JB		 9220 if (cur_token.code != T_NIL)
9221 {
9222 intel_parser.op_string -= strlen (cur_token.str);
9223 free (cur_token.str);
9224 }
64a0c779 9225 cur_token = prev_token;
4a1805b1 9226
64a0c779
DN		 9227 /* Forget prev_token. */
9228 prev_token.code = T_NIL;
9229 prev_token.reg = NULL;
9230 prev_token.str = NULL;
9231}
54cfded0 9232
a60de03c
JB		 9233void
9234tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9235{
a60de03c
JB		 9236 int saved_naked_reg;
9237 char saved_register_dot;
54cfded0 9238
a60de03c
JB		 9239 saved_naked_reg = allow_naked_reg;
9240 allow_naked_reg = 1;
9241 saved_register_dot = register_chars['.'];
9242 register_chars['.'] = '.';
9243 allow_pseudo_reg = 1;
9244 expression_and_evaluate (exp);
9245 allow_pseudo_reg = 0;
9246 register_chars['.'] = saved_register_dot;
9247 allow_naked_reg = saved_naked_reg;
9248
9249 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 9250 {
a60de03c
JB		 9251 if ((addressT) exp->X_add_number < i386_regtab_size)
9252 {
9253 exp->X_op = O_constant;
9254 exp->X_add_number = i386_regtab[exp->X_add_number]
9255 .dw2_regnum[flag_code >> 1];
9256 }
9257 else
9258 exp->X_op = O_illegal;
54cfded0 9259 }
54cfded0
AM		 9260}
9261
9262void
9263tc_x86_frame_initial_instructions (void)
9264{
a60de03c
JB		 9265 static unsigned int sp_regno[2];
9266
9267 if (!sp_regno[flag_code >> 1])
9268 {
9269 char *saved_input = input_line_pointer;
9270 char sp[][4] = {"esp", "rsp"};
9271 expressionS exp;
a4447b93 9272
a60de03c
JB		 9273 input_line_pointer = sp[flag_code >> 1];
9274 tc_x86_parse_to_dw2regnum (&exp);
9275 assert (exp.X_op == O_constant);
9276 sp_regno[flag_code >> 1] = exp.X_add_number;
9277 input_line_pointer = saved_input;
9278 }
a4447b93 9279
a60de03c 9280 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 9281 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9282}
d2b2c203
DJ		 9283
9284int
9285i386_elf_section_type (const char *str, size_t len)
9286{
9287 if (flag_code == CODE_64BIT
9288 && len == sizeof ("unwind") - 1
9289 && strncmp (str, "unwind", 6) == 0)
9290 return SHT_X86_64_UNWIND;
9291
9292 return -1;
9293}
bb41ade5
AM		 9294
9295#ifdef TE_PE
9296void
9297tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9298{
9299 expressionS expr;
9300
9301 expr.X_op = O_secrel;
9302 expr.X_add_symbol = symbol;
9303 expr.X_add_number = 0;
9304 emit_expr (&expr, size);
9305}
9306#endif
3b22753a
L		 9307
9308#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9309/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9310
9311int
9312x86_64_section_letter (int letter, char **ptr_msg)
9313{
9314 if (flag_code == CODE_64BIT)
9315 {
9316 if (letter == 'l')
9317 return SHF_X86_64_LARGE;
9318
9319 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9320 }
3b22753a 9321 else
64e74474 9322 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9323 return -1;
9324}
9325
9326int
9327x86_64_section_word (char *str, size_t len)
9328{
8620418b 9329 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9330 return SHF_X86_64_LARGE;
9331
9332 return -1;
9333}
9334
9335static void
9336handle_large_common (int small ATTRIBUTE_UNUSED)
9337{
9338 if (flag_code != CODE_64BIT)
9339 {
9340 s_comm_internal (0, elf_common_parse);
9341 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9342 }
9343 else
9344 {
9345 static segT lbss_section;
9346 asection *saved_com_section_ptr = elf_com_section_ptr;
9347 asection *saved_bss_section = bss_section;
9348
9349 if (lbss_section == NULL)
9350 {
9351 flagword applicable;
9352 segT seg = now_seg;
9353 subsegT subseg = now_subseg;
9354
9355 /* The .lbss section is for local .largecomm symbols. */
9356 lbss_section = subseg_new (".lbss", 0);
9357 applicable = bfd_applicable_section_flags (stdoutput);
9358 bfd_set_section_flags (stdoutput, lbss_section,
9359 applicable & SEC_ALLOC);
9360 seg_info (lbss_section)->bss = 1;
9361
9362 subseg_set (seg, subseg);
9363 }
9364
9365 elf_com_section_ptr = &_bfd_elf_large_com_section;
9366 bss_section = lbss_section;
9367
9368 s_comm_internal (0, elf_common_parse);
9369
9370 elf_com_section_ptr = saved_com_section_ptr;
9371 bss_section = saved_bss_section;
9372 }
9373}
9374#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
This page took 1.19023 seconds and 4 git commands to generate.