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Remove documention of dead "target vxworks"
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
4b95cf5c 2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
22109423 136 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 137}
138arch_entry;
139
78f12dd3 140static void update_code_flag (int, int);
e3bb37b5
L		 141static void set_code_flag (int);
142static void set_16bit_gcc_code_flag (int);
143static void set_intel_syntax (int);
1efbbeb4 144static void set_intel_mnemonic (int);
db51cc60 145static void set_allow_index_reg (int);
7bab8ab5 146static void set_check (int);
e3bb37b5 147static void set_cpu_arch (int);
6482c264 148#ifdef TE_PE
e3bb37b5 149static void pe_directive_secrel (int);
6482c264 150#endif
e3bb37b5
L		 151static void signed_cons (int);
152static char *output_invalid (int c);
ee86248c
JB		 153static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
154 const char *);
155static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
156 const char *);
a7619375 157static int i386_att_operand (char *);
e3bb37b5 158static int i386_intel_operand (char *, int);
ee86248c
JB		 159static int i386_intel_simplify (expressionS *);
160static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 161static const reg_entry *parse_register (char *, char **);
162static char *parse_insn (char *, char *);
163static char *parse_operands (char *, const char *);
164static void swap_operands (void);
4d456e3d 165static void swap_2_operands (int, int);
e3bb37b5
L		 166static void optimize_imm (void);
167static void optimize_disp (void);
d3ce72d0 168static const insn_template *match_template (void);
e3bb37b5
L		 169static int check_string (void);
170static int process_suffix (void);
171static int check_byte_reg (void);
172static int check_long_reg (void);
173static int check_qword_reg (void);
174static int check_word_reg (void);
175static int finalize_imm (void);
176static int process_operands (void);
177static const seg_entry *build_modrm_byte (void);
178static void output_insn (void);
179static void output_imm (fragS *, offsetT);
180static void output_disp (fragS *, offsetT);
29b0f896 181#ifndef I386COFF
e3bb37b5 182static void s_bss (int);
252b5132 183#endif
17d4e2a2
L		 184#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185static void handle_large_common (int small ATTRIBUTE_UNUSED);
186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
43234a1e
L		 190/* This struct describes rounding control and SAE in the instruction. */
191struct RC_Operation
192{
193 enum rc_type
194 {
195 rne = 0,
196 rd,
197 ru,
198 rz,
199 saeonly
200 } type;
201 int operand;
202};
203
204static struct RC_Operation rc_op;
205
206/* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209struct Mask_Operation
210{
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
214 int operand;
215};
216
217static struct Mask_Operation mask_op;
218
219/* The struct describes broadcasting, applied to OPERAND. FACTOR is
220 broadcast factor. */
221struct Broadcast_Operation
222{
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
224 int type;
225
226 /* Index of broadcasted operand. */
227 int operand;
228};
229
230static struct Broadcast_Operation broadcast_op;
231
c0f3af97
L		 232/* VEX prefix. */
233typedef struct
234{
43234a1e
L		 235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
c0f3af97
L		 237 unsigned int length;
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
240} vex_prefix;
241
252b5132 242/* 'md_assemble ()' gathers together information and puts it into a
47926f60 243 i386_insn. */
252b5132 244
520dc8e8
AM		 245union i386_op
246 {
247 expressionS *disps;
248 expressionS *imms;
249 const reg_entry *regs;
250 };
251
a65babc9
L		 252enum i386_error
253 {
86e026a4 254 operand_size_mismatch,
a65babc9
L		 255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
259 bad_imm4,
260 old_gcc_only,
261 unsupported_with_intel_mnemonic,
262 unsupported_syntax,
6c30d220
L		 263 unsupported,
264 invalid_vsib_address,
7bab8ab5 265 invalid_vector_register_set,
43234a1e
L		 266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
269 broadcast_needed,
270 unsupported_masking,
271 mask_not_on_destination,
272 no_default_mask,
273 unsupported_rc_sae,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
276 try_vector_disp8
a65babc9
L		 277 };
278
252b5132
RH		 279struct _i386_insn
280 {
47926f60 281 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 282 insn_template tm;
252b5132 283
7d5e4556
L		 284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
252b5132
RH		 286 char suffix;
287
47926f60 288 /* OPERANDS gives the number of given operands. */
252b5132
RH		 289 unsigned int operands;
290
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
47926f60 293 operands. */
252b5132
RH		 294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
295
296 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 297 use OP[i] for the corresponding operand. */
40fb9820 298 i386_operand_type types[MAX_OPERANDS];
252b5132 299
520dc8e8
AM		 300 /* Displacement expression, immediate expression, or register for each
301 operand. */
302 union i386_op op[MAX_OPERANDS];
252b5132 303
3e73aa7c
JH		 304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306#define Operand_PCrel 1
307
252b5132 308 /* Relocation type for operand */
f86103b7 309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 310
252b5132
RH		 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
316
317 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 318 explicit segment overrides are given. */
ce8a8b2f 319 const seg_entry *seg[2];
252b5132
RH		 320
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
325
326 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 327 addressing modes of this insn are encoded. */
252b5132 328 modrm_byte rm;
3e73aa7c 329 rex_byte rex;
43234a1e 330 rex_byte vrex;
252b5132 331 sib_byte sib;
c0f3af97 332 vex_prefix vex;
b6169b20 333
43234a1e
L		 334 /* Masking attributes. */
335 struct Mask_Operation *mask;
336
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
339
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
342
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
345
b6169b20 346 /* Swap operand in encoding. */
4473e004 347 unsigned int swap_operand;
891edac4 348
a501d77e
L		 349 /* Prefer 8bit or 32bit displacement in encoding. */
350 enum
351 {
352 disp_encoding_default = 0,
353 disp_encoding_8bit,
354 disp_encoding_32bit
355 } disp_encoding;
f8a5c266 356
d5de92cf
L		 357 /* REP prefix. */
358 const char *rep_prefix;
359
165de32a
L		 360 /* HLE prefix. */
361 const char *hle_prefix;
42164a71 362
7e8b059b
L		 363 /* Have BND prefix. */
364 const char *bnd_prefix;
365
43234a1e
L		 366 /* Need VREX to support upper 16 registers. */
367 int need_vrex;
368
891edac4 369 /* Error message. */
a65babc9 370 enum i386_error error;
252b5132
RH		 371 };
372
373typedef struct _i386_insn i386_insn;
374
43234a1e
L		 375/* Link RC type with corresponding string, that'll be looked for in
376 asm. */
377struct RC_name
378{
379 enum rc_type type;
380 const char *name;
381 unsigned int len;
382};
383
384static const struct RC_name RC_NamesTable[] =
385{
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
391};
392
252b5132
RH		 393/* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 395const char extra_symbol_chars[] = "*%-([{"
252b5132 396#ifdef LEX_AT
32137342
NC		 397 "@"
398#endif
399#ifdef LEX_QM
400 "?"
252b5132 401#endif
32137342 402 ;
252b5132 403
29b0f896
AM		 404#if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 406 && !defined (TE_GNU) \
29b0f896 407 && !defined (TE_LINUX) \
8d63c93e
RM		 408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
29b0f896 410 && !defined (TE_FreeBSD) \
5b806d27 411 && !defined (TE_DragonFly) \
29b0f896 412 && !defined (TE_NetBSD)))
252b5132 413/* This array holds the chars that always start a comment. If the
b3b91714
AM		 414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416const char *i386_comment_chars = "#/";
417#define SVR4_COMMENT_CHARS 1
252b5132 418#define PREFIX_SEPARATOR '\\'
252b5132 419
b3b91714
AM		 420#else
421const char *i386_comment_chars = "#";
422#define PREFIX_SEPARATOR '/'
423#endif
424
252b5132
RH		 425/* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 429 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
252b5132 432 '/' isn't otherwise defined. */
b3b91714 433const char line_comment_chars[] = "#/";
252b5132 434
63a0b638 435const char line_separator_chars[] = ";";
252b5132 436
ce8a8b2f
AM		 437/* Chars that can be used to separate mant from exp in floating point
438 nums. */
252b5132
RH		 439const char EXP_CHARS[] = "eE";
440
ce8a8b2f
AM		 441/* Chars that mean this number is a floating point constant
442 As in 0f12.456
443 or 0d1.2345e12. */
252b5132
RH		 444const char FLT_CHARS[] = "fFdDxX";
445
ce8a8b2f 446/* Tables for lexical analysis. */
252b5132
RH		 447static char mnemonic_chars[256];
448static char register_chars[256];
449static char operand_chars[256];
450static char identifier_chars[256];
451static char digit_chars[256];
452
ce8a8b2f 453/* Lexical macros. */
252b5132
RH		 454#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455#define is_operand_char(x) (operand_chars[(unsigned char) x])
456#define is_register_char(x) (register_chars[(unsigned char) x])
457#define is_space_char(x) ((x) == ' ')
458#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459#define is_digit_char(x) (digit_chars[(unsigned char) x])
460
0234cb7c 461/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 462static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
463
464/* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
47926f60 467 assembler instruction). */
252b5132 468static char save_stack[32];
ce8a8b2f 469static char *save_stack_p;
252b5132
RH		 470#define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472#define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
474
47926f60 475/* The instruction we're assembling. */
252b5132
RH		 476static i386_insn i;
477
478/* Possible templates for current insn. */
479static const templates *current_templates;
480
31b2323c
L		 481/* Per instruction expressionS buffers: max displacements & immediates. */
482static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 484
47926f60 485/* Current operand we are working on. */
ee86248c 486static int this_operand = -1;
252b5132 487
3e73aa7c
JH		 488/* We support four different modes. FLAG_CODE variable is used to distinguish
489 these. */
490
491enum flag_code {
492 CODE_32BIT,
493 CODE_16BIT,
494 CODE_64BIT };
495
496static enum flag_code flag_code;
4fa24527 497static unsigned int object_64bit;
862be3fb 498static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 499static int use_rela_relocations = 0;
500
7af8ed2d
NC		 501#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
504
351f65ca
L		 505/* The ELF ABI to use. */
506enum x86_elf_abi
507{
508 I386_ABI,
7f56bc95
L		 509 X86_64_ABI,
510 X86_64_X32_ABI
351f65ca
L		 511};
512
513static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 514#endif
351f65ca 515
167ad85b
TG		 516#if defined (TE_PE) || defined (TE_PEP)
517/* Use big object file format. */
518static int use_big_obj = 0;
519#endif
520
47926f60
KH		 521/* 1 for intel syntax,
522 0 if att syntax. */
523static int intel_syntax = 0;
252b5132 524
1efbbeb4
L		 525/* 1 for intel mnemonic,
526 0 if att mnemonic. */
527static int intel_mnemonic = !SYSV386_COMPAT;
528
5209009a 529/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 530static int old_gcc = OLDGCC_COMPAT;
531
a60de03c
JB		 532/* 1 if pseudo registers are permitted. */
533static int allow_pseudo_reg = 0;
534
47926f60
KH		 535/* 1 if register prefix % not required. */
536static int allow_naked_reg = 0;
252b5132 537
7e8b059b
L		 538/* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
540 explicitly. */
541static int add_bnd_prefix = 0;
542
ba104c83 543/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 544static int allow_index_reg = 0;
545
d022bddd
IT		 546/* 1 if the assembler should ignore LOCK prefix, even if it was
547 specified explicitly. */
548static int omit_lock_prefix = 0;
549
7bab8ab5 550static enum check_kind
daf50ae7 551 {
7bab8ab5
JB		 552 check_none = 0,
553 check_warning,
554 check_error
daf50ae7 555 }
7bab8ab5 556sse_check, operand_check = check_warning;
daf50ae7 557
2ca3ace5
L		 558/* Register prefix used for error message. */
559static const char *register_prefix = "%";
560
47926f60
KH		 561/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
562 leave, push, and pop instructions so that gcc has the same stack
563 frame as in 32 bit mode. */
564static char stackop_size = '\0';
eecb386c 565
12b55ccc
L		 566/* Non-zero to optimize code alignment. */
567int optimize_align_code = 1;
568
47926f60
KH		 569/* Non-zero to quieten some warnings. */
570static int quiet_warnings = 0;
a38cf1db 571
47926f60
KH		 572/* CPU name. */
573static const char *cpu_arch_name = NULL;
6305a203 574static char *cpu_sub_arch_name = NULL;
a38cf1db 575
47926f60 576/* CPU feature flags. */
40fb9820
L		 577static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
578
ccc9c027
L		 579/* If we have selected a cpu we are generating instructions for. */
580static int cpu_arch_tune_set = 0;
581
9103f4f4 582/* Cpu we are generating instructions for. */
fbf3f584 583enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 584
585/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 586static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 587
ccc9c027 588/* CPU instruction set architecture used. */
fbf3f584 589enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 590
9103f4f4 591/* CPU feature flags of instruction set architecture used. */
fbf3f584 592i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 593
fddf5b5b
AM		 594/* If set, conditional jumps are not automatically promoted to handle
595 larger than a byte offset. */
596static unsigned int no_cond_jump_promotion = 0;
597
c0f3af97
L		 598/* Encode SSE instructions with VEX prefix. */
599static unsigned int sse2avx;
600
539f890d
L		 601/* Encode scalar AVX instructions with specific vector length. */
602static enum
603 {
604 vex128 = 0,
605 vex256
606 } avxscalar;
607
43234a1e
L		 608/* Encode scalar EVEX LIG instructions with specific vector length. */
609static enum
610 {
611 evexl128 = 0,
612 evexl256,
613 evexl512
614 } evexlig;
615
616/* Encode EVEX WIG instructions with specific evex.w. */
617static enum
618 {
619 evexw0 = 0,
620 evexw1
621 } evexwig;
622
29b0f896 623/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 624static symbolS *GOT_symbol;
29b0f896 625
a4447b93
RH		 626/* The dwarf2 return column, adjusted for 32 or 64 bit. */
627unsigned int x86_dwarf2_return_column;
628
629/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
630int x86_cie_data_alignment;
631
252b5132 632/* Interface to relax_segment.
fddf5b5b
AM		 633 There are 3 major relax states for 386 jump insns because the
634 different types of jumps add different sizes to frags when we're
635 figuring out what sort of jump to choose to reach a given label. */
252b5132 636
47926f60 637/* Types. */
93c2a809
AM		 638#define UNCOND_JUMP 0
639#define COND_JUMP 1
640#define COND_JUMP86 2
fddf5b5b 641
47926f60 642/* Sizes. */
252b5132
RH		 643#define CODE16 1
644#define SMALL 0
29b0f896 645#define SMALL16 (SMALL | CODE16)
252b5132 646#define BIG 2
29b0f896 647#define BIG16 (BIG | CODE16)
252b5132
RH		 648
649#ifndef INLINE
650#ifdef __GNUC__
651#define INLINE __inline__
652#else
653#define INLINE
654#endif
655#endif
656
fddf5b5b
AM		 657#define ENCODE_RELAX_STATE(type, size) \
658 ((relax_substateT) (((type) << 2) | (size)))
659#define TYPE_FROM_RELAX_STATE(s) \
660 ((s) >> 2)
661#define DISP_SIZE_FROM_RELAX_STATE(s) \
662 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 663
664/* This table is used by relax_frag to promote short jumps to long
665 ones where necessary. SMALL (short) jumps may be promoted to BIG
666 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
667 don't allow a short jump in a 32 bit code segment to be promoted to
668 a 16 bit offset jump because it's slower (requires data size
669 prefix), and doesn't work, unless the destination is in the bottom
670 64k of the code segment (The top 16 bits of eip are zeroed). */
671
672const relax_typeS md_relax_table[] =
673{
24eab124
AM		 674 /* The fields are:
675 1) most positive reach of this state,
676 2) most negative reach of this state,
93c2a809 677 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 678 4) which index into the table to try if we can't fit into this one. */
252b5132 679
fddf5b5b 680 /* UNCOND_JUMP states. */
93c2a809
AM		 681 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
682 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
683 /* dword jmp adds 4 bytes to frag:
684 0 extra opcode bytes, 4 displacement bytes. */
252b5132 685 {0, 0, 4, 0},
93c2a809
AM		 686 /* word jmp adds 2 byte2 to frag:
687 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 688 {0, 0, 2, 0},
689
93c2a809
AM		 690 /* COND_JUMP states. */
691 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
692 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
693 /* dword conditionals adds 5 bytes to frag:
694 1 extra opcode byte, 4 displacement bytes. */
695 {0, 0, 5, 0},
fddf5b5b 696 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 697 1 extra opcode byte, 2 displacement bytes. */
698 {0, 0, 3, 0},
699
700 /* COND_JUMP86 states. */
701 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
702 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
703 /* dword conditionals adds 5 bytes to frag:
704 1 extra opcode byte, 4 displacement bytes. */
705 {0, 0, 5, 0},
706 /* word conditionals add 4 bytes to frag:
707 1 displacement byte and a 3 byte long branch insn. */
708 {0, 0, 4, 0}
252b5132
RH		 709};
710
9103f4f4
L		 711static const arch_entry cpu_arch[] =
712{
89507696
JB		 713 /* Do not replace the first two entries - i386_target_format()
714 relies on them being there in this order. */
8a2c8fef 715 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 716 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 717 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 718 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 719 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 720 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 721 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 722 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 723 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 724 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 725 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 726 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 727 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 728 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 729 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 730 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 732 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 734 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 736 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 738 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 740 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 741 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 742 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 743 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 744 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 745 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 746 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 747 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 748 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 750 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 752 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 753 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 754 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 756 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 758 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 759 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
760 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 762 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 764 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 766 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 768 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 770 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 772 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 773 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 774 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 775 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 776 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 777 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 778 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 779 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
780 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 781 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
782 CPU_BDVER4_FLAGS, 0, 0 },
7b458c12
L		 783 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
784 CPU_BTVER1_FLAGS, 0, 0 },
785 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
786 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 787 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 788 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 789 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 790 CPU_287_FLAGS, 0, 0 },
8a2c8fef 791 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 792 CPU_387_FLAGS, 0, 0 },
8a2c8fef 793 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 794 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 795 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 796 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 797 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 798 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 799 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 800 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 801 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 802 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 803 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 804 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 805 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 806 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 807 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 808 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 809 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 810 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 811 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 812 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 813 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 814 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 815 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 816 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 817 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
818 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 819 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
820 CPU_AVX512F_FLAGS, 0, 0 },
821 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
822 CPU_AVX512CD_FLAGS, 0, 0 },
823 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
824 CPU_AVX512ER_FLAGS, 0, 0 },
825 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
826 CPU_AVX512PF_FLAGS, 0, 0 },
8a2c8fef 827 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 828 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 829 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 830 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 831 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
832 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 833 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 834 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 835 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 836 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 837 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 838 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 839 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 840 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 841 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 842 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 843 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 844 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 845 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 846 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 847 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 848 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 849 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 850 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 851 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
852 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 854 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 856 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 857 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 858 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 860 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 862 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 863 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
864 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 865 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 866 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 867 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
868 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 869 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
870 CPU_HLE_FLAGS, 0, 0 },
871 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
872 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 873 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
874 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 876 CPU_CLFLUSH_FLAGS, 0, 0 },
877 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
878 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 880 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 882 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 884 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 885 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 886 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 887 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 888 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 889 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 890 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 891 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 892 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 894 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 895 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 896 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 897 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
898 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 899 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
900 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 901 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
902 CPU_ADX_FLAGS, 0, 0 },
903 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
904 CPU_RDSEED_FLAGS, 0, 0 },
905 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
906 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 907 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
908 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 909 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
910 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 911 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
912 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 913 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
914 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
915 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
916 CPU_XSAVEC_FLAGS, 0, 0 },
917 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
918 CPU_XSAVES_FLAGS, 0, 0 },
dcf893b5
IT		 919 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
920 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 921 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
922 CPU_SE1_FLAGS, 0, 0 },
90a915bf
IT		 923 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
924 CPU_AVX512DQ_FLAGS, 0, 0 },
1ba585e8
IT		 925 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
926 CPU_AVX512BW_FLAGS, 0, 0 },
b28d1bda
IT		 927 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
928 CPU_AVX512VL_FLAGS, 0, 0 },
e413e4e9
AM		 929};
930
704209c0 931#ifdef I386COFF
a6c24e68
NC		 932/* Like s_lcomm_internal in gas/read.c but the alignment string
933 is allowed to be optional. */
934
935static symbolS *
936pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
937{
938 addressT align = 0;
939
940 SKIP_WHITESPACE ();
941
7ab9ffdd 942 if (needs_align
a6c24e68
NC		 943 && *input_line_pointer == ',')
944 {
945 align = parse_align (needs_align - 1);
7ab9ffdd 946
a6c24e68
NC		 947 if (align == (addressT) -1)
948 return NULL;
949 }
950 else
951 {
952 if (size >= 8)
953 align = 3;
954 else if (size >= 4)
955 align = 2;
956 else if (size >= 2)
957 align = 1;
958 else
959 align = 0;
960 }
961
962 bss_alloc (symbolP, size, align);
963 return symbolP;
964}
965
704209c0 966static void
a6c24e68
NC		 967pe_lcomm (int needs_align)
968{
969 s_comm_internal (needs_align * 2, pe_lcomm_internal);
970}
704209c0 971#endif
a6c24e68 972
29b0f896
AM		 973const pseudo_typeS md_pseudo_table[] =
974{
975#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
976 {"align", s_align_bytes, 0},
977#else
978 {"align", s_align_ptwo, 0},
979#endif
980 {"arch", set_cpu_arch, 0},
981#ifndef I386COFF
982 {"bss", s_bss, 0},
a6c24e68
NC		 983#else
984 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 985#endif
986 {"ffloat", float_cons, 'f'},
987 {"dfloat", float_cons, 'd'},
988 {"tfloat", float_cons, 'x'},
989 {"value", cons, 2},
d182319b 990 {"slong", signed_cons, 4},
29b0f896
AM		 991 {"noopt", s_ignore, 0},
992 {"optim", s_ignore, 0},
993 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
994 {"code16", set_code_flag, CODE_16BIT},
995 {"code32", set_code_flag, CODE_32BIT},
996 {"code64", set_code_flag, CODE_64BIT},
997 {"intel_syntax", set_intel_syntax, 1},
998 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 999 {"intel_mnemonic", set_intel_mnemonic, 1},
1000 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1001 {"allow_index_reg", set_allow_index_reg, 1},
1002 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1003 {"sse_check", set_check, 0},
1004 {"operand_check", set_check, 1},
3b22753a
L		 1005#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1006 {"largecomm", handle_large_common, 0},
07a53e5c 1007#else
e3bb37b5 1008 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1009 {"loc", dwarf2_directive_loc, 0},
1010 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1011#endif
6482c264
NC		 1012#ifdef TE_PE
1013 {"secrel32", pe_directive_secrel, 0},
1014#endif
29b0f896
AM		 1015 {0, 0, 0}
1016};
1017
1018/* For interface with expression (). */
1019extern char *input_line_pointer;
1020
1021/* Hash table for instruction mnemonic lookup. */
1022static struct hash_control *op_hash;
1023
1024/* Hash table for register lookup. */
1025static struct hash_control *reg_hash;
1026\f
252b5132 1027void
e3bb37b5 1028i386_align_code (fragS *fragP, int count)
252b5132 1029{
ce8a8b2f
AM		 1030 /* Various efficient no-op patterns for aligning code labels.
1031 Note: Don't try to assemble the instructions in the comments.
1032 0L and 0w are not legal. */
252b5132
RH		 1033 static const char f32_1[] =
1034 {0x90}; /* nop */
1035 static const char f32_2[] =
ccc9c027 1036 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1037 static const char f32_3[] =
1038 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1039 static const char f32_4[] =
1040 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1041 static const char f32_5[] =
1042 {0x90, /* nop */
1043 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1044 static const char f32_6[] =
1045 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1046 static const char f32_7[] =
1047 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1048 static const char f32_8[] =
1049 {0x90, /* nop */
1050 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1051 static const char f32_9[] =
1052 {0x89,0xf6, /* movl %esi,%esi */
1053 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1054 static const char f32_10[] =
1055 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1056 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1057 static const char f32_11[] =
1058 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1059 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1060 static const char f32_12[] =
1061 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1062 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1063 static const char f32_13[] =
1064 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1065 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1066 static const char f32_14[] =
1067 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1068 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1069 static const char f16_3[] =
1070 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1071 static const char f16_4[] =
1072 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1073 static const char f16_5[] =
1074 {0x90, /* nop */
1075 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1076 static const char f16_6[] =
1077 {0x89,0xf6, /* mov %si,%si */
1078 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1079 static const char f16_7[] =
1080 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1081 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1082 static const char f16_8[] =
1083 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1084 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1085 static const char jump_31[] =
1086 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1087 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1088 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1089 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1090 static const char *const f32_patt[] = {
1091 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1092 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1093 };
1094 static const char *const f16_patt[] = {
76bc74dc 1095 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1096 };
ccc9c027
L		 1097 /* nopl (%[re]ax) */
1098 static const char alt_3[] =
1099 {0x0f,0x1f,0x00};
1100 /* nopl 0(%[re]ax) */
1101 static const char alt_4[] =
1102 {0x0f,0x1f,0x40,0x00};
1103 /* nopl 0(%[re]ax,%[re]ax,1) */
1104 static const char alt_5[] =
1105 {0x0f,0x1f,0x44,0x00,0x00};
1106 /* nopw 0(%[re]ax,%[re]ax,1) */
1107 static const char alt_6[] =
1108 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1109 /* nopl 0L(%[re]ax) */
1110 static const char alt_7[] =
1111 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1112 /* nopl 0L(%[re]ax,%[re]ax,1) */
1113 static const char alt_8[] =
1114 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1115 /* nopw 0L(%[re]ax,%[re]ax,1) */
1116 static const char alt_9[] =
1117 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1118 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1119 static const char alt_10[] =
1120 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1121 /* data16
1122 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1123 static const char alt_long_11[] =
1124 {0x66,
1125 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1126 /* data16
1127 data16
1128 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1129 static const char alt_long_12[] =
1130 {0x66,
1131 0x66,
1132 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1133 /* data16
1134 data16
1135 data16
1136 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_long_13[] =
1138 {0x66,
1139 0x66,
1140 0x66,
1141 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1142 /* data16
1143 data16
1144 data16
1145 data16
1146 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1147 static const char alt_long_14[] =
1148 {0x66,
1149 0x66,
1150 0x66,
1151 0x66,
1152 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1153 /* data16
1154 data16
1155 data16
1156 data16
1157 data16
1158 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1159 static const char alt_long_15[] =
1160 {0x66,
1161 0x66,
1162 0x66,
1163 0x66,
1164 0x66,
1165 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1166 /* nopl 0(%[re]ax,%[re]ax,1)
1167 nopw 0(%[re]ax,%[re]ax,1) */
1168 static const char alt_short_11[] =
1169 {0x0f,0x1f,0x44,0x00,0x00,
1170 0x66,0x0f,0x1f,0x44,0x00,0x00};
1171 /* nopw 0(%[re]ax,%[re]ax,1)
1172 nopw 0(%[re]ax,%[re]ax,1) */
1173 static const char alt_short_12[] =
1174 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1175 0x66,0x0f,0x1f,0x44,0x00,0x00};
1176 /* nopw 0(%[re]ax,%[re]ax,1)
1177 nopl 0L(%[re]ax) */
1178 static const char alt_short_13[] =
1179 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1180 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1181 /* nopl 0L(%[re]ax)
1182 nopl 0L(%[re]ax) */
1183 static const char alt_short_14[] =
1184 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1185 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1186 /* nopl 0L(%[re]ax)
1187 nopl 0L(%[re]ax,%[re]ax,1) */
1188 static const char alt_short_15[] =
1189 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1190 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1191 static const char *const alt_short_patt[] = {
1192 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1193 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1194 alt_short_14, alt_short_15
1195 };
1196 static const char *const alt_long_patt[] = {
1197 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1198 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1199 alt_long_14, alt_long_15
1200 };
252b5132 1201
76bc74dc
L		 1202 /* Only align for at least a positive non-zero boundary. */
1203 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1204 return;
3e73aa7c 1205
ccc9c027
L		 1206 /* We need to decide which NOP sequence to use for 32bit and
1207 64bit. When -mtune= is used:
4eed87de 1208
76bc74dc
L		 1209 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1210 PROCESSOR_GENERIC32, f32_patt will be used.
1211 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1212 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1213 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1214 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1215 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1216 will be used.
ccc9c027 1217
76bc74dc 1218 When -mtune= isn't used, alt_long_patt will be used if
22109423 1219 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1220 be used.
ccc9c027
L		 1221
1222 When -march= or .arch is used, we can't use anything beyond
1223 cpu_arch_isa_flags. */
1224
1225 if (flag_code == CODE_16BIT)
1226 {
ccc9c027 1227 if (count > 8)
33fef721 1228 {
76bc74dc
L		 1229 memcpy (fragP->fr_literal + fragP->fr_fix,
1230 jump_31, count);
1231 /* Adjust jump offset. */
1232 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1233 }
76bc74dc
L		 1234 else
1235 memcpy (fragP->fr_literal + fragP->fr_fix,
1236 f16_patt[count - 1], count);
252b5132 1237 }
33fef721 1238 else
ccc9c027
L		 1239 {
1240 const char *const *patt = NULL;
1241
fbf3f584 1242 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1243 {
1244 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1245 switch (cpu_arch_tune)
1246 {
1247 case PROCESSOR_UNKNOWN:
1248 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1249 optimize with nops. */
1250 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1251 patt = alt_long_patt;
ccc9c027
L		 1252 else
1253 patt = f32_patt;
1254 break;
ccc9c027
L		 1255 case PROCESSOR_PENTIUM4:
1256 case PROCESSOR_NOCONA:
ef05d495 1257 case PROCESSOR_CORE:
76bc74dc 1258 case PROCESSOR_CORE2:
bd5295b2 1259 case PROCESSOR_COREI7:
3632d14b 1260 case PROCESSOR_L1OM:
7a9068fe 1261 case PROCESSOR_K1OM:
76bc74dc
L		 1262 case PROCESSOR_GENERIC64:
1263 patt = alt_long_patt;
1264 break;
ccc9c027
L		 1265 case PROCESSOR_K6:
1266 case PROCESSOR_ATHLON:
1267 case PROCESSOR_K8:
4eed87de 1268 case PROCESSOR_AMDFAM10:
8aedb9fe 1269 case PROCESSOR_BD:
7b458c12 1270 case PROCESSOR_BT:
ccc9c027
L		 1271 patt = alt_short_patt;
1272 break;
76bc74dc 1273 case PROCESSOR_I386:
ccc9c027
L		 1274 case PROCESSOR_I486:
1275 case PROCESSOR_PENTIUM:
2dde1948 1276 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1277 case PROCESSOR_GENERIC32:
1278 patt = f32_patt;
1279 break;
4eed87de 1280 }
ccc9c027
L		 1281 }
1282 else
1283 {
fbf3f584 1284 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1285 {
1286 case PROCESSOR_UNKNOWN:
e6a14101 1287 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1288 PROCESSOR_UNKNOWN. */
1289 abort ();
1290 break;
1291
76bc74dc 1292 case PROCESSOR_I386:
ccc9c027
L		 1293 case PROCESSOR_I486:
1294 case PROCESSOR_PENTIUM:
ccc9c027
L		 1295 case PROCESSOR_K6:
1296 case PROCESSOR_ATHLON:
1297 case PROCESSOR_K8:
4eed87de 1298 case PROCESSOR_AMDFAM10:
8aedb9fe 1299 case PROCESSOR_BD:
7b458c12 1300 case PROCESSOR_BT:
ccc9c027
L		 1301 case PROCESSOR_GENERIC32:
1302 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1303 with nops. */
1304 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1305 patt = alt_short_patt;
1306 else
1307 patt = f32_patt;
1308 break;
76bc74dc
L		 1309 case PROCESSOR_PENTIUMPRO:
1310 case PROCESSOR_PENTIUM4:
1311 case PROCESSOR_NOCONA:
1312 case PROCESSOR_CORE:
ef05d495 1313 case PROCESSOR_CORE2:
bd5295b2 1314 case PROCESSOR_COREI7:
3632d14b 1315 case PROCESSOR_L1OM:
7a9068fe 1316 case PROCESSOR_K1OM:
22109423 1317 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1318 patt = alt_long_patt;
1319 else
1320 patt = f32_patt;
1321 break;
1322 case PROCESSOR_GENERIC64:
76bc74dc 1323 patt = alt_long_patt;
ccc9c027 1324 break;
4eed87de 1325 }
ccc9c027
L		 1326 }
1327
76bc74dc
L		 1328 if (patt == f32_patt)
1329 {
1330 /* If the padding is less than 15 bytes, we use the normal
1331 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1332 its offset. */
1333 int limit;
76ba9986 1334
711eedef
L		 1335 /* For 64bit, the limit is 3 bytes. */
1336 if (flag_code == CODE_64BIT
1337 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1338 limit = 3;
1339 else
1340 limit = 15;
1341 if (count < limit)
76bc74dc
L		 1342 memcpy (fragP->fr_literal + fragP->fr_fix,
1343 patt[count - 1], count);
1344 else
1345 {
1346 memcpy (fragP->fr_literal + fragP->fr_fix,
1347 jump_31, count);
1348 /* Adjust jump offset. */
1349 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1350 }
1351 }
1352 else
1353 {
1354 /* Maximum length of an instruction is 15 byte. If the
1355 padding is greater than 15 bytes and we don't use jump,
1356 we have to break it into smaller pieces. */
1357 int padding = count;
1358 while (padding > 15)
1359 {
1360 padding -= 15;
1361 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1362 patt [14], 15);
1363 }
1364
1365 if (padding)
1366 memcpy (fragP->fr_literal + fragP->fr_fix,
1367 patt [padding - 1], padding);
1368 }
ccc9c027 1369 }
33fef721 1370 fragP->fr_var = count;
252b5132
RH		 1371}
1372
c6fb90c8 1373static INLINE int
0dfbf9d7 1374operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1375{
0dfbf9d7 1376 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1377 {
1378 case 3:
0dfbf9d7 1379 if (x->array[2])
c6fb90c8
L		 1380 return 0;
1381 case 2:
0dfbf9d7 1382 if (x->array[1])
c6fb90c8
L		 1383 return 0;
1384 case 1:
0dfbf9d7 1385 return !x->array[0];
c6fb90c8
L		 1386 default:
1387 abort ();
1388 }
40fb9820
L		 1389}
1390
c6fb90c8 1391static INLINE void
0dfbf9d7 1392operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1393{
0dfbf9d7 1394 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1395 {
1396 case 3:
0dfbf9d7 1397 x->array[2] = v;
c6fb90c8 1398 case 2:
0dfbf9d7 1399 x->array[1] = v;
c6fb90c8 1400 case 1:
0dfbf9d7 1401 x->array[0] = v;
c6fb90c8
L		 1402 break;
1403 default:
1404 abort ();
1405 }
1406}
40fb9820 1407
c6fb90c8 1408static INLINE int
0dfbf9d7
L		 1409operand_type_equal (const union i386_operand_type *x,
1410 const union i386_operand_type *y)
c6fb90c8 1411{
0dfbf9d7 1412 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1413 {
1414 case 3:
0dfbf9d7 1415 if (x->array[2] != y->array[2])
c6fb90c8
L		 1416 return 0;
1417 case 2:
0dfbf9d7 1418 if (x->array[1] != y->array[1])
c6fb90c8
L		 1419 return 0;
1420 case 1:
0dfbf9d7 1421 return x->array[0] == y->array[0];
c6fb90c8
L		 1422 break;
1423 default:
1424 abort ();
1425 }
1426}
40fb9820 1427
0dfbf9d7
L		 1428static INLINE int
1429cpu_flags_all_zero (const union i386_cpu_flags *x)
1430{
1431 switch (ARRAY_SIZE(x->array))
1432 {
1433 case 3:
1434 if (x->array[2])
1435 return 0;
1436 case 2:
1437 if (x->array[1])
1438 return 0;
1439 case 1:
1440 return !x->array[0];
1441 default:
1442 abort ();
1443 }
1444}
1445
1446static INLINE void
1447cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1448{
1449 switch (ARRAY_SIZE(x->array))
1450 {
1451 case 3:
1452 x->array[2] = v;
1453 case 2:
1454 x->array[1] = v;
1455 case 1:
1456 x->array[0] = v;
1457 break;
1458 default:
1459 abort ();
1460 }
1461}
1462
1463static INLINE int
1464cpu_flags_equal (const union i386_cpu_flags *x,
1465 const union i386_cpu_flags *y)
1466{
1467 switch (ARRAY_SIZE(x->array))
1468 {
1469 case 3:
1470 if (x->array[2] != y->array[2])
1471 return 0;
1472 case 2:
1473 if (x->array[1] != y->array[1])
1474 return 0;
1475 case 1:
1476 return x->array[0] == y->array[0];
1477 break;
1478 default:
1479 abort ();
1480 }
1481}
c6fb90c8
L		 1482
1483static INLINE int
1484cpu_flags_check_cpu64 (i386_cpu_flags f)
1485{
1486 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1487 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1488}
1489
c6fb90c8
L		 1490static INLINE i386_cpu_flags
1491cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1492{
c6fb90c8
L		 1493 switch (ARRAY_SIZE (x.array))
1494 {
1495 case 3:
1496 x.array [2] &= y.array [2];
1497 case 2:
1498 x.array [1] &= y.array [1];
1499 case 1:
1500 x.array [0] &= y.array [0];
1501 break;
1502 default:
1503 abort ();
1504 }
1505 return x;
1506}
40fb9820 1507
c6fb90c8
L		 1508static INLINE i386_cpu_flags
1509cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1510{
c6fb90c8 1511 switch (ARRAY_SIZE (x.array))
40fb9820 1512 {
c6fb90c8
L		 1513 case 3:
1514 x.array [2] |= y.array [2];
1515 case 2:
1516 x.array [1] |= y.array [1];
1517 case 1:
1518 x.array [0] |= y.array [0];
40fb9820
L		 1519 break;
1520 default:
1521 abort ();
1522 }
40fb9820
L		 1523 return x;
1524}
1525
309d3373
JB		 1526static INLINE i386_cpu_flags
1527cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1528{
1529 switch (ARRAY_SIZE (x.array))
1530 {
1531 case 3:
1532 x.array [2] &= ~y.array [2];
1533 case 2:
1534 x.array [1] &= ~y.array [1];
1535 case 1:
1536 x.array [0] &= ~y.array [0];
1537 break;
1538 default:
1539 abort ();
1540 }
1541 return x;
1542}
1543
c0f3af97
L		 1544#define CPU_FLAGS_ARCH_MATCH 0x1
1545#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1546#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1547#define CPU_FLAGS_PCLMUL_MATCH 0x8
1548#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1549
a5ff0eb2 1550#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1551 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1552 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1553#define CPU_FLAGS_PERFECT_MATCH \
1554 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1555
1556/* Return CPU flags match bits. */
3629bb00 1557
40fb9820 1558static int
d3ce72d0 1559cpu_flags_match (const insn_template *t)
40fb9820 1560{
c0f3af97
L		 1561 i386_cpu_flags x = t->cpu_flags;
1562 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1563
1564 x.bitfield.cpu64 = 0;
1565 x.bitfield.cpuno64 = 0;
1566
0dfbf9d7 1567 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1568 {
1569 /* This instruction is available on all archs. */
1570 match |= CPU_FLAGS_32BIT_MATCH;
1571 }
3629bb00
L		 1572 else
1573 {
c0f3af97 1574 /* This instruction is available only on some archs. */
3629bb00
L		 1575 i386_cpu_flags cpu = cpu_arch_flags;
1576
1577 cpu.bitfield.cpu64 = 0;
1578 cpu.bitfield.cpuno64 = 0;
1579 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1580 if (!cpu_flags_all_zero (&cpu))
1581 {
a5ff0eb2
L		 1582 if (x.bitfield.cpuavx)
1583 {
ce2f5b3c 1584 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1585 if (cpu.bitfield.cpuavx)
1586 {
1587 /* Check SSE2AVX. */
1588 if (!t->opcode_modifier.sse2avx|| sse2avx)
1589 {
1590 match |= (CPU_FLAGS_ARCH_MATCH
1591 | CPU_FLAGS_AVX_MATCH);
1592 /* Check AES. */
1593 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1594 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1595 /* Check PCLMUL. */
1596 if (!x.bitfield.cpupclmul
1597 || cpu.bitfield.cpupclmul)
1598 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1599 }
1600 }
1601 else
1602 match |= CPU_FLAGS_ARCH_MATCH;
1603 }
1604 else
c0f3af97
L		 1605 match |= CPU_FLAGS_32BIT_MATCH;
1606 }
3629bb00 1607 }
c0f3af97 1608 return match;
40fb9820
L		 1609}
1610
c6fb90c8
L		 1611static INLINE i386_operand_type
1612operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1613{
c6fb90c8
L		 1614 switch (ARRAY_SIZE (x.array))
1615 {
1616 case 3:
1617 x.array [2] &= y.array [2];
1618 case 2:
1619 x.array [1] &= y.array [1];
1620 case 1:
1621 x.array [0] &= y.array [0];
1622 break;
1623 default:
1624 abort ();
1625 }
1626 return x;
40fb9820
L		 1627}
1628
c6fb90c8
L		 1629static INLINE i386_operand_type
1630operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1631{
c6fb90c8 1632 switch (ARRAY_SIZE (x.array))
40fb9820 1633 {
c6fb90c8
L		 1634 case 3:
1635 x.array [2] |= y.array [2];
1636 case 2:
1637 x.array [1] |= y.array [1];
1638 case 1:
1639 x.array [0] |= y.array [0];
40fb9820
L		 1640 break;
1641 default:
1642 abort ();
1643 }
c6fb90c8
L		 1644 return x;
1645}
40fb9820 1646
c6fb90c8
L		 1647static INLINE i386_operand_type
1648operand_type_xor (i386_operand_type x, i386_operand_type y)
1649{
1650 switch (ARRAY_SIZE (x.array))
1651 {
1652 case 3:
1653 x.array [2] ^= y.array [2];
1654 case 2:
1655 x.array [1] ^= y.array [1];
1656 case 1:
1657 x.array [0] ^= y.array [0];
1658 break;
1659 default:
1660 abort ();
1661 }
40fb9820
L		 1662 return x;
1663}
1664
1665static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1666static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1667static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1668static const i386_operand_type inoutportreg
1669 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1670static const i386_operand_type reg16_inoutportreg
1671 = OPERAND_TYPE_REG16_INOUTPORTREG;
1672static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1673static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1674static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1675static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1676static const i386_operand_type anydisp
1677 = OPERAND_TYPE_ANYDISP;
40fb9820 1678static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1679static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1680static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1681static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1682static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1683static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1684static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1685static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1686static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1687static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1688static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1689static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1690static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1691static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1692
1693enum operand_type
1694{
1695 reg,
40fb9820
L		 1696 imm,
1697 disp,
1698 anymem
1699};
1700
c6fb90c8 1701static INLINE int
40fb9820
L		 1702operand_type_check (i386_operand_type t, enum operand_type c)
1703{
1704 switch (c)
1705 {
1706 case reg:
1707 return (t.bitfield.reg8
1708 || t.bitfield.reg16
1709 || t.bitfield.reg32
1710 || t.bitfield.reg64);
1711
40fb9820
L		 1712 case imm:
1713 return (t.bitfield.imm8
1714 || t.bitfield.imm8s
1715 || t.bitfield.imm16
1716 || t.bitfield.imm32
1717 || t.bitfield.imm32s
1718 || t.bitfield.imm64);
1719
1720 case disp:
1721 return (t.bitfield.disp8
1722 || t.bitfield.disp16
1723 || t.bitfield.disp32
1724 || t.bitfield.disp32s
1725 || t.bitfield.disp64);
1726
1727 case anymem:
1728 return (t.bitfield.disp8
1729 || t.bitfield.disp16
1730 || t.bitfield.disp32
1731 || t.bitfield.disp32s
1732 || t.bitfield.disp64
1733 || t.bitfield.baseindex);
1734
1735 default:
1736 abort ();
1737 }
2cfe26b6
AM		 1738
1739 return 0;
40fb9820
L		 1740}
1741
5c07affc
L		 1742/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1743 operand J for instruction template T. */
1744
1745static INLINE int
d3ce72d0 1746match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1747{
1748 return !((i.types[j].bitfield.byte
1749 && !t->operand_types[j].bitfield.byte)
1750 || (i.types[j].bitfield.word
1751 && !t->operand_types[j].bitfield.word)
1752 || (i.types[j].bitfield.dword
1753 && !t->operand_types[j].bitfield.dword)
1754 || (i.types[j].bitfield.qword
1755 && !t->operand_types[j].bitfield.qword));
1756}
1757
1758/* Return 1 if there is no conflict in any size on operand J for
1759 instruction template T. */
1760
1761static INLINE int
d3ce72d0 1762match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1763{
1764 return (match_reg_size (t, j)
1765 && !((i.types[j].bitfield.unspecified
1766 && !t->operand_types[j].bitfield.unspecified)
1767 || (i.types[j].bitfield.fword
1768 && !t->operand_types[j].bitfield.fword)
1769 || (i.types[j].bitfield.tbyte
1770 && !t->operand_types[j].bitfield.tbyte)
1771 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1772 && !t->operand_types[j].bitfield.xmmword)
1773 || (i.types[j].bitfield.ymmword
43234a1e
L		 1774 && !t->operand_types[j].bitfield.ymmword)
1775 || (i.types[j].bitfield.zmmword
1776 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1777}
1778
1779/* Return 1 if there is no size conflict on any operands for
1780 instruction template T. */
1781
1782static INLINE int
d3ce72d0 1783operand_size_match (const insn_template *t)
5c07affc
L		 1784{
1785 unsigned int j;
1786 int match = 1;
1787
1788 /* Don't check jump instructions. */
1789 if (t->opcode_modifier.jump
1790 || t->opcode_modifier.jumpbyte
1791 || t->opcode_modifier.jumpdword
1792 || t->opcode_modifier.jumpintersegment)
1793 return match;
1794
1795 /* Check memory and accumulator operand size. */
1796 for (j = 0; j < i.operands; j++)
1797 {
1798 if (t->operand_types[j].bitfield.anysize)
1799 continue;
1800
1801 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1802 {
1803 match = 0;
1804 break;
1805 }
1806
1807 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1808 {
1809 match = 0;
1810 break;
1811 }
1812 }
1813
891edac4 1814 if (match)
5c07affc 1815 return match;
891edac4
L		 1816 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1817 {
1818mismatch:
86e026a4 1819 i.error = operand_size_mismatch;
891edac4
L		 1820 return 0;
1821 }
5c07affc
L		 1822
1823 /* Check reverse. */
9c2799c2 1824 gas_assert (i.operands == 2);
5c07affc
L		 1825
1826 match = 1;
1827 for (j = 0; j < 2; j++)
1828 {
1829 if (t->operand_types[j].bitfield.acc
1830 && !match_reg_size (t, j ? 0 : 1))
891edac4 1831 goto mismatch;
5c07affc
L		 1832
1833 if (i.types[j].bitfield.mem
1834 && !match_mem_size (t, j ? 0 : 1))
891edac4 1835 goto mismatch;
5c07affc
L		 1836 }
1837
1838 return match;
1839}
1840
c6fb90c8 1841static INLINE int
40fb9820
L		 1842operand_type_match (i386_operand_type overlap,
1843 i386_operand_type given)
1844{
1845 i386_operand_type temp = overlap;
1846
1847 temp.bitfield.jumpabsolute = 0;
7d5e4556 1848 temp.bitfield.unspecified = 0;
5c07affc
L		 1849 temp.bitfield.byte = 0;
1850 temp.bitfield.word = 0;
1851 temp.bitfield.dword = 0;
1852 temp.bitfield.fword = 0;
1853 temp.bitfield.qword = 0;
1854 temp.bitfield.tbyte = 0;
1855 temp.bitfield.xmmword = 0;
c0f3af97 1856 temp.bitfield.ymmword = 0;
43234a1e 1857 temp.bitfield.zmmword = 0;
0dfbf9d7 1858 if (operand_type_all_zero (&temp))
891edac4 1859 goto mismatch;
40fb9820 1860
891edac4
L		 1861 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1862 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1863 return 1;
1864
1865mismatch:
a65babc9 1866 i.error = operand_type_mismatch;
891edac4 1867 return 0;
40fb9820
L		 1868}
1869
7d5e4556 1870/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1871 unless the expected operand type register overlap is null.
1872 Note that Acc in a template matches every size of reg. */
1873
c6fb90c8 1874static INLINE int
40fb9820
L		 1875operand_type_register_match (i386_operand_type m0,
1876 i386_operand_type g0,
1877 i386_operand_type t0,
1878 i386_operand_type m1,
1879 i386_operand_type g1,
1880 i386_operand_type t1)
1881{
1882 if (!operand_type_check (g0, reg))
1883 return 1;
1884
1885 if (!operand_type_check (g1, reg))
1886 return 1;
1887
1888 if (g0.bitfield.reg8 == g1.bitfield.reg8
1889 && g0.bitfield.reg16 == g1.bitfield.reg16
1890 && g0.bitfield.reg32 == g1.bitfield.reg32
1891 && g0.bitfield.reg64 == g1.bitfield.reg64)
1892 return 1;
1893
1894 if (m0.bitfield.acc)
1895 {
1896 t0.bitfield.reg8 = 1;
1897 t0.bitfield.reg16 = 1;
1898 t0.bitfield.reg32 = 1;
1899 t0.bitfield.reg64 = 1;
1900 }
1901
1902 if (m1.bitfield.acc)
1903 {
1904 t1.bitfield.reg8 = 1;
1905 t1.bitfield.reg16 = 1;
1906 t1.bitfield.reg32 = 1;
1907 t1.bitfield.reg64 = 1;
1908 }
1909
891edac4
L		 1910 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1911 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1912 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1913 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1914 return 1;
1915
a65babc9 1916 i.error = register_type_mismatch;
891edac4
L		 1917
1918 return 0;
40fb9820
L		 1919}
1920
4c692bc7
JB		 1921static INLINE unsigned int
1922register_number (const reg_entry *r)
1923{
1924 unsigned int nr = r->reg_num;
1925
1926 if (r->reg_flags & RegRex)
1927 nr += 8;
1928
1929 return nr;
1930}
1931
252b5132 1932static INLINE unsigned int
40fb9820 1933mode_from_disp_size (i386_operand_type t)
252b5132 1934{
43234a1e 1935 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1936 return 1;
1937 else if (t.bitfield.disp16
1938 || t.bitfield.disp32
1939 || t.bitfield.disp32s)
1940 return 2;
1941 else
1942 return 0;
252b5132
RH		 1943}
1944
1945static INLINE int
e3bb37b5 1946fits_in_signed_byte (offsetT num)
252b5132
RH		 1947{
1948 return (num >= -128) && (num <= 127);
47926f60 1949}
252b5132
RH		 1950
1951static INLINE int
e3bb37b5 1952fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1953{
1954 return (num & 0xff) == num;
47926f60 1955}
252b5132
RH		 1956
1957static INLINE int
e3bb37b5 1958fits_in_unsigned_word (offsetT num)
252b5132
RH		 1959{
1960 return (num & 0xffff) == num;
47926f60 1961}
252b5132
RH		 1962
1963static INLINE int
e3bb37b5 1964fits_in_signed_word (offsetT num)
252b5132
RH		 1965{
1966 return (-32768 <= num) && (num <= 32767);
47926f60 1967}
2a962e6d 1968
3e73aa7c 1969static INLINE int
e3bb37b5 1970fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1971{
1972#ifndef BFD64
1973 return 1;
1974#else
1975 return (!(((offsetT) -1 << 31) & num)
1976 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1977#endif
1978} /* fits_in_signed_long() */
2a962e6d 1979
3e73aa7c 1980static INLINE int
e3bb37b5 1981fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1982{
1983#ifndef BFD64
1984 return 1;
1985#else
1986 return (num & (((offsetT) 2 << 31) - 1)) == num;
1987#endif
1988} /* fits_in_unsigned_long() */
252b5132 1989
43234a1e
L		 1990static INLINE int
1991fits_in_vec_disp8 (offsetT num)
1992{
1993 int shift = i.memshift;
1994 unsigned int mask;
1995
1996 if (shift == -1)
1997 abort ();
1998
1999 mask = (1 << shift) - 1;
2000
2001 /* Return 0 if NUM isn't properly aligned. */
2002 if ((num & mask))
2003 return 0;
2004
2005 /* Check if NUM will fit in 8bit after shift. */
2006 return fits_in_signed_byte (num >> shift);
2007}
2008
a683cc34
SP		 2009static INLINE int
2010fits_in_imm4 (offsetT num)
2011{
2012 return (num & 0xf) == num;
2013}
2014
40fb9820 2015static i386_operand_type
e3bb37b5 2016smallest_imm_type (offsetT num)
252b5132 2017{
40fb9820 2018 i386_operand_type t;
7ab9ffdd 2019
0dfbf9d7 2020 operand_type_set (&t, 0);
40fb9820
L		 2021 t.bitfield.imm64 = 1;
2022
2023 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2024 {
2025 /* This code is disabled on the 486 because all the Imm1 forms
2026 in the opcode table are slower on the i486. They're the
2027 versions with the implicitly specified single-position
2028 displacement, which has another syntax if you really want to
2029 use that form. */
40fb9820
L		 2030 t.bitfield.imm1 = 1;
2031 t.bitfield.imm8 = 1;
2032 t.bitfield.imm8s = 1;
2033 t.bitfield.imm16 = 1;
2034 t.bitfield.imm32 = 1;
2035 t.bitfield.imm32s = 1;
2036 }
2037 else if (fits_in_signed_byte (num))
2038 {
2039 t.bitfield.imm8 = 1;
2040 t.bitfield.imm8s = 1;
2041 t.bitfield.imm16 = 1;
2042 t.bitfield.imm32 = 1;
2043 t.bitfield.imm32s = 1;
2044 }
2045 else if (fits_in_unsigned_byte (num))
2046 {
2047 t.bitfield.imm8 = 1;
2048 t.bitfield.imm16 = 1;
2049 t.bitfield.imm32 = 1;
2050 t.bitfield.imm32s = 1;
2051 }
2052 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2053 {
2054 t.bitfield.imm16 = 1;
2055 t.bitfield.imm32 = 1;
2056 t.bitfield.imm32s = 1;
2057 }
2058 else if (fits_in_signed_long (num))
2059 {
2060 t.bitfield.imm32 = 1;
2061 t.bitfield.imm32s = 1;
2062 }
2063 else if (fits_in_unsigned_long (num))
2064 t.bitfield.imm32 = 1;
2065
2066 return t;
47926f60 2067}
252b5132 2068
847f7ad4 2069static offsetT
e3bb37b5 2070offset_in_range (offsetT val, int size)
847f7ad4 2071{
508866be 2072 addressT mask;
ba2adb93 2073
847f7ad4
AM		 2074 switch (size)
2075 {
508866be
L		 2076 case 1: mask = ((addressT) 1 << 8) - 1; break;
2077 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2078 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2079#ifdef BFD64
2080 case 8: mask = ((addressT) 2 << 63) - 1; break;
2081#endif
47926f60 2082 default: abort ();
847f7ad4
AM		 2083 }
2084
9de868bf
L		 2085#ifdef BFD64
2086 /* If BFD64, sign extend val for 32bit address mode. */
2087 if (flag_code != CODE_64BIT
2088 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2089 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2090 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2091#endif
ba2adb93 2092
47926f60 2093 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2094 {
2095 char buf1[40], buf2[40];
2096
2097 sprint_value (buf1, val);
2098 sprint_value (buf2, val & mask);
2099 as_warn (_("%s shortened to %s"), buf1, buf2);
2100 }
2101 return val & mask;
2102}
2103
c32fa91d
L		 2104enum PREFIX_GROUP
2105{
2106 PREFIX_EXIST = 0,
2107 PREFIX_LOCK,
2108 PREFIX_REP,
2109 PREFIX_OTHER
2110};
2111
2112/* Returns
2113 a. PREFIX_EXIST if attempting to add a prefix where one from the
2114 same class already exists.
2115 b. PREFIX_LOCK if lock prefix is added.
2116 c. PREFIX_REP if rep/repne prefix is added.
2117 d. PREFIX_OTHER if other prefix is added.
2118 */
2119
2120static enum PREFIX_GROUP
e3bb37b5 2121add_prefix (unsigned int prefix)
252b5132 2122{
c32fa91d 2123 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2124 unsigned int q;
252b5132 2125
29b0f896
AM		 2126 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2127 && flag_code == CODE_64BIT)
b1905489 2128 {
161a04f6
L		 2129 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2130 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2131 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2132 ret = PREFIX_EXIST;
b1905489
JB		 2133 q = REX_PREFIX;
2134 }
3e73aa7c 2135 else
b1905489
JB		 2136 {
2137 switch (prefix)
2138 {
2139 default:
2140 abort ();
2141
2142 case CS_PREFIX_OPCODE:
2143 case DS_PREFIX_OPCODE:
2144 case ES_PREFIX_OPCODE:
2145 case FS_PREFIX_OPCODE:
2146 case GS_PREFIX_OPCODE:
2147 case SS_PREFIX_OPCODE:
2148 q = SEG_PREFIX;
2149 break;
2150
2151 case REPNE_PREFIX_OPCODE:
2152 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2153 q = REP_PREFIX;
2154 ret = PREFIX_REP;
2155 break;
2156
b1905489 2157 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2158 q = LOCK_PREFIX;
2159 ret = PREFIX_LOCK;
b1905489
JB		 2160 break;
2161
2162 case FWAIT_OPCODE:
2163 q = WAIT_PREFIX;
2164 break;
2165
2166 case ADDR_PREFIX_OPCODE:
2167 q = ADDR_PREFIX;
2168 break;
2169
2170 case DATA_PREFIX_OPCODE:
2171 q = DATA_PREFIX;
2172 break;
2173 }
2174 if (i.prefix[q] != 0)
c32fa91d 2175 ret = PREFIX_EXIST;
b1905489 2176 }
252b5132 2177
b1905489 2178 if (ret)
252b5132 2179 {
b1905489
JB		 2180 if (!i.prefix[q])
2181 ++i.prefixes;
2182 i.prefix[q] |= prefix;
252b5132 2183 }
b1905489
JB		 2184 else
2185 as_bad (_("same type of prefix used twice"));
252b5132 2186
252b5132
RH		 2187 return ret;
2188}
2189
2190static void
78f12dd3 2191update_code_flag (int value, int check)
eecb386c 2192{
78f12dd3
L		 2193 PRINTF_LIKE ((*as_error));
2194
1e9cc1c2 2195 flag_code = (enum flag_code) value;
40fb9820
L		 2196 if (flag_code == CODE_64BIT)
2197 {
2198 cpu_arch_flags.bitfield.cpu64 = 1;
2199 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2200 }
2201 else
2202 {
2203 cpu_arch_flags.bitfield.cpu64 = 0;
2204 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2205 }
2206 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2207 {
78f12dd3
L		 2208 if (check)
2209 as_error = as_fatal;
2210 else
2211 as_error = as_bad;
2212 (*as_error) (_("64bit mode not supported on `%s'."),
2213 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2214 }
40fb9820 2215 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2216 {
78f12dd3
L		 2217 if (check)
2218 as_error = as_fatal;
2219 else
2220 as_error = as_bad;
2221 (*as_error) (_("32bit mode not supported on `%s'."),
2222 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2223 }
eecb386c
AM		 2224 stackop_size = '\0';
2225}
2226
78f12dd3
L		 2227static void
2228set_code_flag (int value)
2229{
2230 update_code_flag (value, 0);
2231}
2232
eecb386c 2233static void
e3bb37b5 2234set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2235{
1e9cc1c2 2236 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2237 if (flag_code != CODE_16BIT)
2238 abort ();
2239 cpu_arch_flags.bitfield.cpu64 = 0;
2240 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2241 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2242}
2243
2244static void
e3bb37b5 2245set_intel_syntax (int syntax_flag)
252b5132
RH		 2246{
2247 /* Find out if register prefixing is specified. */
2248 int ask_naked_reg = 0;
2249
2250 SKIP_WHITESPACE ();
29b0f896 2251 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2252 {
2253 char *string = input_line_pointer;
2254 int e = get_symbol_end ();
2255
47926f60 2256 if (strcmp (string, "prefix") == 0)
252b5132 2257 ask_naked_reg = 1;
47926f60 2258 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2259 ask_naked_reg = -1;
2260 else
d0b47220 2261 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2262 *input_line_pointer = e;
2263 }
2264 demand_empty_rest_of_line ();
c3332e24 2265
252b5132
RH		 2266 intel_syntax = syntax_flag;
2267
2268 if (ask_naked_reg == 0)
f86103b7
AM		 2269 allow_naked_reg = (intel_syntax
2270 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2271 else
2272 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2273
ee86248c 2274 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2275
e4a3b5a4 2276 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2277 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2278 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2279}
2280
1efbbeb4
L		 2281static void
2282set_intel_mnemonic (int mnemonic_flag)
2283{
e1d4d893 2284 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2285}
2286
db51cc60
L		 2287static void
2288set_allow_index_reg (int flag)
2289{
2290 allow_index_reg = flag;
2291}
2292
cb19c032 2293static void
7bab8ab5 2294set_check (int what)
cb19c032 2295{
7bab8ab5
JB		 2296 enum check_kind *kind;
2297 const char *str;
2298
2299 if (what)
2300 {
2301 kind = &operand_check;
2302 str = "operand";
2303 }
2304 else
2305 {
2306 kind = &sse_check;
2307 str = "sse";
2308 }
2309
cb19c032
L		 2310 SKIP_WHITESPACE ();
2311
2312 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2313 {
2314 char *string = input_line_pointer;
2315 int e = get_symbol_end ();
2316
2317 if (strcmp (string, "none") == 0)
7bab8ab5 2318 *kind = check_none;
cb19c032 2319 else if (strcmp (string, "warning") == 0)
7bab8ab5 2320 *kind = check_warning;
cb19c032 2321 else if (strcmp (string, "error") == 0)
7bab8ab5 2322 *kind = check_error;
cb19c032 2323 else
7bab8ab5 2324 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2325 *input_line_pointer = e;
2326 }
2327 else
7bab8ab5 2328 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2329
2330 demand_empty_rest_of_line ();
2331}
2332
8a9036a4
L		 2333static void
2334check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2335 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2336{
2337#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2338 static const char *arch;
2339
2340 /* Intel LIOM is only supported on ELF. */
2341 if (!IS_ELF)
2342 return;
2343
2344 if (!arch)
2345 {
2346 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2347 use default_arch. */
2348 arch = cpu_arch_name;
2349 if (!arch)
2350 arch = default_arch;
2351 }
2352
3632d14b 2353 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2354 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2355 || new_flag.bitfield.cpul1om)
8a9036a4 2356 return;
76ba9986 2357
7a9068fe
L		 2358 /* If we are targeting Intel K1OM, we must enable it. */
2359 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2360 || new_flag.bitfield.cpuk1om)
2361 return;
2362
8a9036a4
L		 2363 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2364#endif
2365}
2366
e413e4e9 2367static void
e3bb37b5 2368set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2369{
47926f60 2370 SKIP_WHITESPACE ();
e413e4e9 2371
29b0f896 2372 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2373 {
2374 char *string = input_line_pointer;
2375 int e = get_symbol_end ();
91d6fa6a 2376 unsigned int j;
40fb9820 2377 i386_cpu_flags flags;
e413e4e9 2378
91d6fa6a 2379 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2380 {
91d6fa6a 2381 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2382 {
91d6fa6a 2383 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2384
5c6af06e
JB		 2385 if (*string != '.')
2386 {
91d6fa6a 2387 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2388 cpu_sub_arch_name = NULL;
91d6fa6a 2389 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2390 if (flag_code == CODE_64BIT)
2391 {
2392 cpu_arch_flags.bitfield.cpu64 = 1;
2393 cpu_arch_flags.bitfield.cpuno64 = 0;
2394 }
2395 else
2396 {
2397 cpu_arch_flags.bitfield.cpu64 = 0;
2398 cpu_arch_flags.bitfield.cpuno64 = 1;
2399 }
91d6fa6a
NC		 2400 cpu_arch_isa = cpu_arch[j].type;
2401 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2402 if (!cpu_arch_tune_set)
2403 {
2404 cpu_arch_tune = cpu_arch_isa;
2405 cpu_arch_tune_flags = cpu_arch_isa_flags;
2406 }
5c6af06e
JB		 2407 break;
2408 }
40fb9820 2409
22109423 2410 if (!cpu_arch[j].negated)
309d3373 2411 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2412 cpu_arch[j].flags);
309d3373
JB		 2413 else
2414 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2415 cpu_arch[j].flags);
0dfbf9d7 2416 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2417 {
6305a203
L		 2418 if (cpu_sub_arch_name)
2419 {
2420 char *name = cpu_sub_arch_name;
2421 cpu_sub_arch_name = concat (name,
91d6fa6a 2422 cpu_arch[j].name,
1bf57e9f 2423 (const char *) NULL);
6305a203
L		 2424 free (name);
2425 }
2426 else
91d6fa6a 2427 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2428 cpu_arch_flags = flags;
a586129e 2429 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2430 }
2431 *input_line_pointer = e;
2432 demand_empty_rest_of_line ();
2433 return;
e413e4e9
AM		 2434 }
2435 }
91d6fa6a 2436 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2437 as_bad (_("no such architecture: `%s'"), string);
2438
2439 *input_line_pointer = e;
2440 }
2441 else
2442 as_bad (_("missing cpu architecture"));
2443
fddf5b5b
AM		 2444 no_cond_jump_promotion = 0;
2445 if (*input_line_pointer == ','
29b0f896 2446 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2447 {
2448 char *string = ++input_line_pointer;
2449 int e = get_symbol_end ();
2450
2451 if (strcmp (string, "nojumps") == 0)
2452 no_cond_jump_promotion = 1;
2453 else if (strcmp (string, "jumps") == 0)
2454 ;
2455 else
2456 as_bad (_("no such architecture modifier: `%s'"), string);
2457
2458 *input_line_pointer = e;
2459 }
2460
e413e4e9
AM		 2461 demand_empty_rest_of_line ();
2462}
2463
8a9036a4
L		 2464enum bfd_architecture
2465i386_arch (void)
2466{
3632d14b 2467 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2468 {
2469 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2470 || flag_code != CODE_64BIT)
2471 as_fatal (_("Intel L1OM is 64bit ELF only"));
2472 return bfd_arch_l1om;
2473 }
7a9068fe
L		 2474 else if (cpu_arch_isa == PROCESSOR_K1OM)
2475 {
2476 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2477 || flag_code != CODE_64BIT)
2478 as_fatal (_("Intel K1OM is 64bit ELF only"));
2479 return bfd_arch_k1om;
2480 }
8a9036a4
L		 2481 else
2482 return bfd_arch_i386;
2483}
2484
b9d79e03 2485unsigned long
7016a5d5 2486i386_mach (void)
b9d79e03 2487{
351f65ca 2488 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2489 {
3632d14b 2490 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2491 {
351f65ca
L		 2492 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2493 || default_arch[6] != '\0')
8a9036a4
L		 2494 as_fatal (_("Intel L1OM is 64bit ELF only"));
2495 return bfd_mach_l1om;
2496 }
7a9068fe
L		 2497 else if (cpu_arch_isa == PROCESSOR_K1OM)
2498 {
2499 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2500 || default_arch[6] != '\0')
2501 as_fatal (_("Intel K1OM is 64bit ELF only"));
2502 return bfd_mach_k1om;
2503 }
351f65ca 2504 else if (default_arch[6] == '\0')
8a9036a4 2505 return bfd_mach_x86_64;
351f65ca
L		 2506 else
2507 return bfd_mach_x64_32;
8a9036a4 2508 }
b9d79e03
JH		 2509 else if (!strcmp (default_arch, "i386"))
2510 return bfd_mach_i386_i386;
2511 else
2b5d6a91 2512 as_fatal (_("unknown architecture"));
b9d79e03 2513}
b9d79e03 2514\f
252b5132 2515void
7016a5d5 2516md_begin (void)
252b5132
RH		 2517{
2518 const char *hash_err;
2519
47926f60 2520 /* Initialize op_hash hash table. */
252b5132
RH		 2521 op_hash = hash_new ();
2522
2523 {
d3ce72d0 2524 const insn_template *optab;
29b0f896 2525 templates *core_optab;
252b5132 2526
47926f60
KH		 2527 /* Setup for loop. */
2528 optab = i386_optab;
252b5132
RH		 2529 core_optab = (templates *) xmalloc (sizeof (templates));
2530 core_optab->start = optab;
2531
2532 while (1)
2533 {
2534 ++optab;
2535 if (optab->name == NULL
2536 || strcmp (optab->name, (optab - 1)->name) != 0)
2537 {
2538 /* different name --> ship out current template list;
47926f60 2539 add to hash table; & begin anew. */
252b5132
RH		 2540 core_optab->end = optab;
2541 hash_err = hash_insert (op_hash,
2542 (optab - 1)->name,
5a49b8ac 2543 (void *) core_optab);
252b5132
RH		 2544 if (hash_err)
2545 {
b37df7c4 2546 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2547 (optab - 1)->name,
2548 hash_err);
2549 }
2550 if (optab->name == NULL)
2551 break;
2552 core_optab = (templates *) xmalloc (sizeof (templates));
2553 core_optab->start = optab;
2554 }
2555 }
2556 }
2557
47926f60 2558 /* Initialize reg_hash hash table. */
252b5132
RH		 2559 reg_hash = hash_new ();
2560 {
29b0f896 2561 const reg_entry *regtab;
c3fe08fa 2562 unsigned int regtab_size = i386_regtab_size;
252b5132 2563
c3fe08fa 2564 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2565 {
5a49b8ac 2566 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2567 if (hash_err)
b37df7c4 2568 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2569 regtab->reg_name,
2570 hash_err);
252b5132
RH		 2571 }
2572 }
2573
47926f60 2574 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2575 {
29b0f896
AM		 2576 int c;
2577 char *p;
252b5132
RH		 2578
2579 for (c = 0; c < 256; c++)
2580 {
3882b010 2581 if (ISDIGIT (c))
252b5132
RH		 2582 {
2583 digit_chars[c] = c;
2584 mnemonic_chars[c] = c;
2585 register_chars[c] = c;
2586 operand_chars[c] = c;
2587 }
3882b010 2588 else if (ISLOWER (c))
252b5132
RH		 2589 {
2590 mnemonic_chars[c] = c;
2591 register_chars[c] = c;
2592 operand_chars[c] = c;
2593 }
3882b010 2594 else if (ISUPPER (c))
252b5132 2595 {
3882b010 2596 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2597 register_chars[c] = mnemonic_chars[c];
2598 operand_chars[c] = c;
2599 }
43234a1e
L		 2600 else if (c == '{' || c == '}')
2601 operand_chars[c] = c;
252b5132 2602
3882b010 2603 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2604 identifier_chars[c] = c;
2605 else if (c >= 128)
2606 {
2607 identifier_chars[c] = c;
2608 operand_chars[c] = c;
2609 }
2610 }
2611
2612#ifdef LEX_AT
2613 identifier_chars['@'] = '@';
32137342
NC		 2614#endif
2615#ifdef LEX_QM
2616 identifier_chars['?'] = '?';
2617 operand_chars['?'] = '?';
252b5132 2618#endif
252b5132 2619 digit_chars['-'] = '-';
c0f3af97 2620 mnemonic_chars['_'] = '_';
791fe849 2621 mnemonic_chars['-'] = '-';
0003779b 2622 mnemonic_chars['.'] = '.';
252b5132
RH		 2623 identifier_chars['_'] = '_';
2624 identifier_chars['.'] = '.';
2625
2626 for (p = operand_special_chars; *p != '\0'; p++)
2627 operand_chars[(unsigned char) *p] = *p;
2628 }
2629
a4447b93
RH		 2630 if (flag_code == CODE_64BIT)
2631 {
ca19b261
KT		 2632#if defined (OBJ_COFF) && defined (TE_PE)
2633 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2634 ? 32 : 16);
2635#else
a4447b93 2636 x86_dwarf2_return_column = 16;
ca19b261 2637#endif
61ff971f 2638 x86_cie_data_alignment = -8;
a4447b93
RH		 2639 }
2640 else
2641 {
2642 x86_dwarf2_return_column = 8;
2643 x86_cie_data_alignment = -4;
2644 }
252b5132
RH		 2645}
2646
2647void
e3bb37b5 2648i386_print_statistics (FILE *file)
252b5132
RH		 2649{
2650 hash_print_statistics (file, "i386 opcode", op_hash);
2651 hash_print_statistics (file, "i386 register", reg_hash);
2652}
2653\f
252b5132
RH		 2654#ifdef DEBUG386
2655
ce8a8b2f 2656/* Debugging routines for md_assemble. */
d3ce72d0 2657static void pte (insn_template *);
40fb9820 2658static void pt (i386_operand_type);
e3bb37b5
L		 2659static void pe (expressionS *);
2660static void ps (symbolS *);
252b5132
RH		 2661
2662static void
e3bb37b5 2663pi (char *line, i386_insn *x)
252b5132 2664{
09137c09 2665 unsigned int j;
252b5132
RH		 2666
2667 fprintf (stdout, "%s: template ", line);
2668 pte (&x->tm);
09f131f2
JH		 2669 fprintf (stdout, " address: base %s index %s scale %x\n",
2670 x->base_reg ? x->base_reg->reg_name : "none",
2671 x->index_reg ? x->index_reg->reg_name : "none",
2672 x->log2_scale_factor);
2673 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2674 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2675 fprintf (stdout, " sib: base %x index %x scale %x\n",
2676 x->sib.base, x->sib.index, x->sib.scale);
2677 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2678 (x->rex & REX_W) != 0,
2679 (x->rex & REX_R) != 0,
2680 (x->rex & REX_X) != 0,
2681 (x->rex & REX_B) != 0);
09137c09 2682 for (j = 0; j < x->operands; j++)
252b5132 2683 {
09137c09
SP		 2684 fprintf (stdout, " #%d: ", j + 1);
2685 pt (x->types[j]);
252b5132 2686 fprintf (stdout, "\n");
09137c09
SP		 2687 if (x->types[j].bitfield.reg8
2688 || x->types[j].bitfield.reg16
2689 || x->types[j].bitfield.reg32
2690 || x->types[j].bitfield.reg64
2691 || x->types[j].bitfield.regmmx
2692 || x->types[j].bitfield.regxmm
2693 || x->types[j].bitfield.regymm
43234a1e 2694 || x->types[j].bitfield.regzmm
09137c09
SP		 2695 || x->types[j].bitfield.sreg2
2696 || x->types[j].bitfield.sreg3
2697 || x->types[j].bitfield.control
2698 || x->types[j].bitfield.debug
2699 || x->types[j].bitfield.test)
2700 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2701 if (operand_type_check (x->types[j], imm))
2702 pe (x->op[j].imms);
2703 if (operand_type_check (x->types[j], disp))
2704 pe (x->op[j].disps);
252b5132
RH		 2705 }
2706}
2707
2708static void
d3ce72d0 2709pte (insn_template *t)
252b5132 2710{
09137c09 2711 unsigned int j;
252b5132 2712 fprintf (stdout, " %d operands ", t->operands);
47926f60 2713 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2714 if (t->extension_opcode != None)
2715 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2716 if (t->opcode_modifier.d)
252b5132 2717 fprintf (stdout, "D");
40fb9820 2718 if (t->opcode_modifier.w)
252b5132
RH		 2719 fprintf (stdout, "W");
2720 fprintf (stdout, "\n");
09137c09 2721 for (j = 0; j < t->operands; j++)
252b5132 2722 {
09137c09
SP		 2723 fprintf (stdout, " #%d type ", j + 1);
2724 pt (t->operand_types[j]);
252b5132
RH		 2725 fprintf (stdout, "\n");
2726 }
2727}
2728
2729static void
e3bb37b5 2730pe (expressionS *e)
252b5132 2731{
24eab124 2732 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2733 fprintf (stdout, " add_number %ld (%lx)\n",
2734 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2735 if (e->X_add_symbol)
2736 {
2737 fprintf (stdout, " add_symbol ");
2738 ps (e->X_add_symbol);
2739 fprintf (stdout, "\n");
2740 }
2741 if (e->X_op_symbol)
2742 {
2743 fprintf (stdout, " op_symbol ");
2744 ps (e->X_op_symbol);
2745 fprintf (stdout, "\n");
2746 }
2747}
2748
2749static void
e3bb37b5 2750ps (symbolS *s)
252b5132
RH		 2751{
2752 fprintf (stdout, "%s type %s%s",
2753 S_GET_NAME (s),
2754 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2755 segment_name (S_GET_SEGMENT (s)));
2756}
2757
7b81dfbb 2758static struct type_name
252b5132 2759 {
40fb9820
L		 2760 i386_operand_type mask;
2761 const char *name;
252b5132 2762 }
7b81dfbb 2763const type_names[] =
252b5132 2764{
40fb9820
L		 2765 { OPERAND_TYPE_REG8, "r8" },
2766 { OPERAND_TYPE_REG16, "r16" },
2767 { OPERAND_TYPE_REG32, "r32" },
2768 { OPERAND_TYPE_REG64, "r64" },
2769 { OPERAND_TYPE_IMM8, "i8" },
2770 { OPERAND_TYPE_IMM8, "i8s" },
2771 { OPERAND_TYPE_IMM16, "i16" },
2772 { OPERAND_TYPE_IMM32, "i32" },
2773 { OPERAND_TYPE_IMM32S, "i32s" },
2774 { OPERAND_TYPE_IMM64, "i64" },
2775 { OPERAND_TYPE_IMM1, "i1" },
2776 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2777 { OPERAND_TYPE_DISP8, "d8" },
2778 { OPERAND_TYPE_DISP16, "d16" },
2779 { OPERAND_TYPE_DISP32, "d32" },
2780 { OPERAND_TYPE_DISP32S, "d32s" },
2781 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2782 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2783 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2784 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2785 { OPERAND_TYPE_CONTROL, "control reg" },
2786 { OPERAND_TYPE_TEST, "test reg" },
2787 { OPERAND_TYPE_DEBUG, "debug reg" },
2788 { OPERAND_TYPE_FLOATREG, "FReg" },
2789 { OPERAND_TYPE_FLOATACC, "FAcc" },
2790 { OPERAND_TYPE_SREG2, "SReg2" },
2791 { OPERAND_TYPE_SREG3, "SReg3" },
2792 { OPERAND_TYPE_ACC, "Acc" },
2793 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2794 { OPERAND_TYPE_REGMMX, "rMMX" },
2795 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2796 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2797 { OPERAND_TYPE_REGZMM, "rZMM" },
2798 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2799 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2800};
2801
2802static void
40fb9820 2803pt (i386_operand_type t)
252b5132 2804{
40fb9820 2805 unsigned int j;
c6fb90c8 2806 i386_operand_type a;
252b5132 2807
40fb9820 2808 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2809 {
2810 a = operand_type_and (t, type_names[j].mask);
0349dc08 2811 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2812 fprintf (stdout, "%s, ", type_names[j].name);
2813 }
252b5132
RH		 2814 fflush (stdout);
2815}
2816
2817#endif /* DEBUG386 */
2818\f
252b5132 2819static bfd_reloc_code_real_type
3956db08 2820reloc (unsigned int size,
64e74474
AM		 2821 int pcrel,
2822 int sign,
c3320543 2823 int bnd_prefix,
64e74474 2824 bfd_reloc_code_real_type other)
252b5132 2825{
47926f60 2826 if (other != NO_RELOC)
3956db08 2827 {
91d6fa6a 2828 reloc_howto_type *rel;
3956db08
JB		 2829
2830 if (size == 8)
2831 switch (other)
2832 {
64e74474
AM		 2833 case BFD_RELOC_X86_64_GOT32:
2834 return BFD_RELOC_X86_64_GOT64;
2835 break;
2836 case BFD_RELOC_X86_64_PLTOFF64:
2837 return BFD_RELOC_X86_64_PLTOFF64;
2838 break;
2839 case BFD_RELOC_X86_64_GOTPC32:
2840 other = BFD_RELOC_X86_64_GOTPC64;
2841 break;
2842 case BFD_RELOC_X86_64_GOTPCREL:
2843 other = BFD_RELOC_X86_64_GOTPCREL64;
2844 break;
2845 case BFD_RELOC_X86_64_TPOFF32:
2846 other = BFD_RELOC_X86_64_TPOFF64;
2847 break;
2848 case BFD_RELOC_X86_64_DTPOFF32:
2849 other = BFD_RELOC_X86_64_DTPOFF64;
2850 break;
2851 default:
2852 break;
3956db08 2853 }
e05278af 2854
8ce3d284 2855#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2856 if (other == BFD_RELOC_SIZE32)
2857 {
2858 if (size == 8)
1ab668bf 2859 other = BFD_RELOC_SIZE64;
8fd4256d 2860 if (pcrel)
1ab668bf
AM		 2861 {
2862 as_bad (_("there are no pc-relative size relocations"));
2863 return NO_RELOC;
2864 }
8fd4256d 2865 }
8ce3d284 2866#endif
8fd4256d 2867
e05278af 2868 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2869 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2870 sign = -1;
2871
91d6fa6a
NC		 2872 rel = bfd_reloc_type_lookup (stdoutput, other);
2873 if (!rel)
3956db08 2874 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2875 else if (size != bfd_get_reloc_size (rel))
3956db08 2876 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2877 bfd_get_reloc_size (rel),
3956db08 2878 size);
91d6fa6a 2879 else if (pcrel && !rel->pc_relative)
3956db08 2880 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2881 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2882 && !sign)
91d6fa6a 2883 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2884 && sign > 0))
3956db08
JB		 2885 as_bad (_("relocated field and relocation type differ in signedness"));
2886 else
2887 return other;
2888 return NO_RELOC;
2889 }
252b5132
RH		 2890
2891 if (pcrel)
2892 {
3e73aa7c 2893 if (!sign)
3956db08 2894 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2895 switch (size)
2896 {
2897 case 1: return BFD_RELOC_8_PCREL;
2898 case 2: return BFD_RELOC_16_PCREL;
c3320543
L		 2899 case 4: return (bnd_prefix && object_64bit
2900 ? BFD_RELOC_X86_64_PC32_BND
2901 : BFD_RELOC_32_PCREL);
d6ab8113 2902 case 8: return BFD_RELOC_64_PCREL;
252b5132 2903 }
3956db08 2904 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2905 }
2906 else
2907 {
3956db08 2908 if (sign > 0)
e5cb08ac 2909 switch (size)
3e73aa7c
JH		 2910 {
2911 case 4: return BFD_RELOC_X86_64_32S;
2912 }
2913 else
2914 switch (size)
2915 {
2916 case 1: return BFD_RELOC_8;
2917 case 2: return BFD_RELOC_16;
2918 case 4: return BFD_RELOC_32;
2919 case 8: return BFD_RELOC_64;
2920 }
3956db08
JB		 2921 as_bad (_("cannot do %s %u byte relocation"),
2922 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2923 }
2924
0cc9e1d3 2925 return NO_RELOC;
252b5132
RH		 2926}
2927
47926f60
KH		 2928/* Here we decide which fixups can be adjusted to make them relative to
2929 the beginning of the section instead of the symbol. Basically we need
2930 to make sure that the dynamic relocations are done correctly, so in
2931 some cases we force the original symbol to be used. */
2932
252b5132 2933int
e3bb37b5 2934tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2935{
6d249963 2936#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2937 if (!IS_ELF)
31312f95
AM		 2938 return 1;
2939
a161fe53
AM		 2940 /* Don't adjust pc-relative references to merge sections in 64-bit
2941 mode. */
2942 if (use_rela_relocations
2943 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2944 && fixP->fx_pcrel)
252b5132 2945 return 0;
31312f95 2946
8d01d9a9
AJ		 2947 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2948 and changed later by validate_fix. */
2949 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2950 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2951 return 0;
2952
8fd4256d
L		 2953 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2954 for size relocations. */
2955 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2956 || fixP->fx_r_type == BFD_RELOC_SIZE64
2957 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2958 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2959 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2960 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2961 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2962 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2963 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2964 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2965 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2966 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2967 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2968 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2969 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2970 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2971 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2972 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2973 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2974 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2975 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2976 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2977 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2978 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2979 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2980 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2981 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2982 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2983 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2984 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2985 return 0;
31312f95 2986#endif
252b5132
RH		 2987 return 1;
2988}
252b5132 2989
b4cac588 2990static int
e3bb37b5 2991intel_float_operand (const char *mnemonic)
252b5132 2992{
9306ca4a
JB		 2993 /* Note that the value returned is meaningful only for opcodes with (memory)
2994 operands, hence the code here is free to improperly handle opcodes that
2995 have no operands (for better performance and smaller code). */
2996
2997 if (mnemonic[0] != 'f')
2998 return 0; /* non-math */
2999
3000 switch (mnemonic[1])
3001 {
3002 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3003 the fs segment override prefix not currently handled because no
3004 call path can make opcodes without operands get here */
3005 case 'i':
3006 return 2 /* integer op */;
3007 case 'l':
3008 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3009 return 3; /* fldcw/fldenv */
3010 break;
3011 case 'n':
3012 if (mnemonic[2] != 'o' /* fnop */)
3013 return 3; /* non-waiting control op */
3014 break;
3015 case 'r':
3016 if (mnemonic[2] == 's')
3017 return 3; /* frstor/frstpm */
3018 break;
3019 case 's':
3020 if (mnemonic[2] == 'a')
3021 return 3; /* fsave */
3022 if (mnemonic[2] == 't')
3023 {
3024 switch (mnemonic[3])
3025 {
3026 case 'c': /* fstcw */
3027 case 'd': /* fstdw */
3028 case 'e': /* fstenv */
3029 case 's': /* fsts[gw] */
3030 return 3;
3031 }
3032 }
3033 break;
3034 case 'x':
3035 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3036 return 0; /* fxsave/fxrstor are not really math ops */
3037 break;
3038 }
252b5132 3039
9306ca4a 3040 return 1;
252b5132
RH		 3041}
3042
c0f3af97
L		 3043/* Build the VEX prefix. */
3044
3045static void
d3ce72d0 3046build_vex_prefix (const insn_template *t)
c0f3af97
L		 3047{
3048 unsigned int register_specifier;
3049 unsigned int implied_prefix;
3050 unsigned int vector_length;
3051
3052 /* Check register specifier. */
3053 if (i.vex.register_specifier)
43234a1e
L		 3054 {
3055 register_specifier =
3056 ~register_number (i.vex.register_specifier) & 0xf;
3057 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3058 }
c0f3af97
L		 3059 else
3060 register_specifier = 0xf;
3061
fa99fab2
L		 3062 /* Use 2-byte VEX prefix by swappping destination and source
3063 operand. */
3064 if (!i.swap_operand
3065 && i.operands == i.reg_operands
7f399153 3066 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3067 && i.tm.opcode_modifier.s
3068 && i.rex == REX_B)
3069 {
3070 unsigned int xchg = i.operands - 1;
3071 union i386_op temp_op;
3072 i386_operand_type temp_type;
3073
3074 temp_type = i.types[xchg];
3075 i.types[xchg] = i.types[0];
3076 i.types[0] = temp_type;
3077 temp_op = i.op[xchg];
3078 i.op[xchg] = i.op[0];
3079 i.op[0] = temp_op;
3080
9c2799c2 3081 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3082
3083 i.rex = REX_R;
3084 xchg = i.rm.regmem;
3085 i.rm.regmem = i.rm.reg;
3086 i.rm.reg = xchg;
3087
3088 /* Use the next insn. */
3089 i.tm = t[1];
3090 }
3091
539f890d
L		 3092 if (i.tm.opcode_modifier.vex == VEXScalar)
3093 vector_length = avxscalar;
3094 else
3095 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3096
3097 switch ((i.tm.base_opcode >> 8) & 0xff)
3098 {
3099 case 0:
3100 implied_prefix = 0;
3101 break;
3102 case DATA_PREFIX_OPCODE:
3103 implied_prefix = 1;
3104 break;
3105 case REPE_PREFIX_OPCODE:
3106 implied_prefix = 2;
3107 break;
3108 case REPNE_PREFIX_OPCODE:
3109 implied_prefix = 3;
3110 break;
3111 default:
3112 abort ();
3113 }
3114
3115 /* Use 2-byte VEX prefix if possible. */
7f399153 3116 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3117 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3118 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3119 {
3120 /* 2-byte VEX prefix. */
3121 unsigned int r;
3122
3123 i.vex.length = 2;
3124 i.vex.bytes[0] = 0xc5;
3125
3126 /* Check the REX.R bit. */
3127 r = (i.rex & REX_R) ? 0 : 1;
3128 i.vex.bytes[1] = (r << 7
3129 | register_specifier << 3
3130 | vector_length << 2
3131 | implied_prefix);
3132 }
3133 else
3134 {
3135 /* 3-byte VEX prefix. */
3136 unsigned int m, w;
3137
f88c9eb0 3138 i.vex.length = 3;
f88c9eb0 3139
7f399153 3140 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3141 {
7f399153
L		 3142 case VEX0F:
3143 m = 0x1;
80de6e00 3144 i.vex.bytes[0] = 0xc4;
7f399153
L		 3145 break;
3146 case VEX0F38:
3147 m = 0x2;
80de6e00 3148 i.vex.bytes[0] = 0xc4;
7f399153
L		 3149 break;
3150 case VEX0F3A:
3151 m = 0x3;
80de6e00 3152 i.vex.bytes[0] = 0xc4;
7f399153
L		 3153 break;
3154 case XOP08:
5dd85c99
SP		 3155 m = 0x8;
3156 i.vex.bytes[0] = 0x8f;
7f399153
L		 3157 break;
3158 case XOP09:
f88c9eb0
SP		 3159 m = 0x9;
3160 i.vex.bytes[0] = 0x8f;
7f399153
L		 3161 break;
3162 case XOP0A:
f88c9eb0
SP		 3163 m = 0xa;
3164 i.vex.bytes[0] = 0x8f;
7f399153
L		 3165 break;
3166 default:
3167 abort ();
f88c9eb0 3168 }
c0f3af97 3169
c0f3af97
L		 3170 /* The high 3 bits of the second VEX byte are 1's compliment
3171 of RXB bits from REX. */
3172 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3173
3174 /* Check the REX.W bit. */
3175 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3176 if (i.tm.opcode_modifier.vexw == VEXW1)
3177 w = 1;
c0f3af97
L		 3178
3179 i.vex.bytes[2] = (w << 7
3180 | register_specifier << 3
3181 | vector_length << 2
3182 | implied_prefix);
3183 }
3184}
3185
43234a1e
L		 3186/* Build the EVEX prefix. */
3187
3188static void
3189build_evex_prefix (void)
3190{
3191 unsigned int register_specifier;
3192 unsigned int implied_prefix;
3193 unsigned int m, w;
3194 rex_byte vrex_used = 0;
3195
3196 /* Check register specifier. */
3197 if (i.vex.register_specifier)
3198 {
3199 gas_assert ((i.vrex & REX_X) == 0);
3200
3201 register_specifier = i.vex.register_specifier->reg_num;
3202 if ((i.vex.register_specifier->reg_flags & RegRex))
3203 register_specifier += 8;
3204 /* The upper 16 registers are encoded in the fourth byte of the
3205 EVEX prefix. */
3206 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3207 i.vex.bytes[3] = 0x8;
3208 register_specifier = ~register_specifier & 0xf;
3209 }
3210 else
3211 {
3212 register_specifier = 0xf;
3213
3214 /* Encode upper 16 vector index register in the fourth byte of
3215 the EVEX prefix. */
3216 if (!(i.vrex & REX_X))
3217 i.vex.bytes[3] = 0x8;
3218 else
3219 vrex_used |= REX_X;
3220 }
3221
3222 switch ((i.tm.base_opcode >> 8) & 0xff)
3223 {
3224 case 0:
3225 implied_prefix = 0;
3226 break;
3227 case DATA_PREFIX_OPCODE:
3228 implied_prefix = 1;
3229 break;
3230 case REPE_PREFIX_OPCODE:
3231 implied_prefix = 2;
3232 break;
3233 case REPNE_PREFIX_OPCODE:
3234 implied_prefix = 3;
3235 break;
3236 default:
3237 abort ();
3238 }
3239
3240 /* 4 byte EVEX prefix. */
3241 i.vex.length = 4;
3242 i.vex.bytes[0] = 0x62;
3243
3244 /* mmmm bits. */
3245 switch (i.tm.opcode_modifier.vexopcode)
3246 {
3247 case VEX0F:
3248 m = 1;
3249 break;
3250 case VEX0F38:
3251 m = 2;
3252 break;
3253 case VEX0F3A:
3254 m = 3;
3255 break;
3256 default:
3257 abort ();
3258 break;
3259 }
3260
3261 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3262 bits from REX. */
3263 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3264
3265 /* The fifth bit of the second EVEX byte is 1's compliment of the
3266 REX_R bit in VREX. */
3267 if (!(i.vrex & REX_R))
3268 i.vex.bytes[1] |= 0x10;
3269 else
3270 vrex_used |= REX_R;
3271
3272 if ((i.reg_operands + i.imm_operands) == i.operands)
3273 {
3274 /* When all operands are registers, the REX_X bit in REX is not
3275 used. We reuse it to encode the upper 16 registers, which is
3276 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3277 as 1's compliment. */
3278 if ((i.vrex & REX_B))
3279 {
3280 vrex_used |= REX_B;
3281 i.vex.bytes[1] &= ~0x40;
3282 }
3283 }
3284
3285 /* EVEX instructions shouldn't need the REX prefix. */
3286 i.vrex &= ~vrex_used;
3287 gas_assert (i.vrex == 0);
3288
3289 /* Check the REX.W bit. */
3290 w = (i.rex & REX_W) ? 1 : 0;
3291 if (i.tm.opcode_modifier.vexw)
3292 {
3293 if (i.tm.opcode_modifier.vexw == VEXW1)
3294 w = 1;
3295 }
3296 /* If w is not set it means we are dealing with WIG instruction. */
3297 else if (!w)
3298 {
3299 if (evexwig == evexw1)
3300 w = 1;
3301 }
3302
3303 /* Encode the U bit. */
3304 implied_prefix |= 0x4;
3305
3306 /* The third byte of the EVEX prefix. */
3307 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3308
3309 /* The fourth byte of the EVEX prefix. */
3310 /* The zeroing-masking bit. */
3311 if (i.mask && i.mask->zeroing)
3312 i.vex.bytes[3] |= 0x80;
3313
3314 /* Don't always set the broadcast bit if there is no RC. */
3315 if (!i.rounding)
3316 {
3317 /* Encode the vector length. */
3318 unsigned int vec_length;
3319
3320 switch (i.tm.opcode_modifier.evex)
3321 {
3322 case EVEXLIG: /* LL' is ignored */
3323 vec_length = evexlig << 5;
3324 break;
3325 case EVEX128:
3326 vec_length = 0 << 5;
3327 break;
3328 case EVEX256:
3329 vec_length = 1 << 5;
3330 break;
3331 case EVEX512:
3332 vec_length = 2 << 5;
3333 break;
3334 default:
3335 abort ();
3336 break;
3337 }
3338 i.vex.bytes[3] |= vec_length;
3339 /* Encode the broadcast bit. */
3340 if (i.broadcast)
3341 i.vex.bytes[3] |= 0x10;
3342 }
3343 else
3344 {
3345 if (i.rounding->type != saeonly)
3346 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3347 else
3348 i.vex.bytes[3] |= 0x10;
3349 }
3350
3351 if (i.mask && i.mask->mask)
3352 i.vex.bytes[3] |= i.mask->mask->reg_num;
3353}
3354
65da13b5
L		 3355static void
3356process_immext (void)
3357{
3358 expressionS *exp;
3359
4c692bc7
JB		 3360 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3361 && i.operands > 0)
65da13b5 3362 {
4c692bc7
JB		 3363 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3364 with an opcode suffix which is coded in the same place as an
3365 8-bit immediate field would be.
3366 Here we check those operands and remove them afterwards. */
65da13b5
L		 3367 unsigned int x;
3368
3369 for (x = 0; x < i.operands; x++)
4c692bc7 3370 if (register_number (i.op[x].regs) != x)
65da13b5 3371 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3372 register_prefix, i.op[x].regs->reg_name, x + 1,
3373 i.tm.name);
3374
3375 i.operands = 0;
65da13b5
L		 3376 }
3377
c0f3af97 3378 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3379 which is coded in the same place as an 8-bit immediate field
3380 would be. Here we fake an 8-bit immediate operand from the
3381 opcode suffix stored in tm.extension_opcode.
3382
c1e679ec 3383 AVX instructions also use this encoding, for some of
c0f3af97 3384 3 argument instructions. */
65da13b5 3385
43234a1e 3386 gas_assert (i.imm_operands <= 1
7ab9ffdd 3387 && (i.operands <= 2
43234a1e
L		 3388 || ((i.tm.opcode_modifier.vex
3389 || i.tm.opcode_modifier.evex)
7ab9ffdd 3390 && i.operands <= 4)));
65da13b5
L		 3391
3392 exp = &im_expressions[i.imm_operands++];
3393 i.op[i.operands].imms = exp;
3394 i.types[i.operands] = imm8;
3395 i.operands++;
3396 exp->X_op = O_constant;
3397 exp->X_add_number = i.tm.extension_opcode;
3398 i.tm.extension_opcode = None;
3399}
3400
42164a71
L		 3401
3402static int
3403check_hle (void)
3404{
3405 switch (i.tm.opcode_modifier.hleprefixok)
3406 {
3407 default:
3408 abort ();
82c2def5 3409 case HLEPrefixNone:
165de32a
L		 3410 as_bad (_("invalid instruction `%s' after `%s'"),
3411 i.tm.name, i.hle_prefix);
42164a71 3412 return 0;
82c2def5 3413 case HLEPrefixLock:
42164a71
L		 3414 if (i.prefix[LOCK_PREFIX])
3415 return 1;
165de32a 3416 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3417 return 0;
82c2def5 3418 case HLEPrefixAny:
42164a71 3419 return 1;
82c2def5 3420 case HLEPrefixRelease:
42164a71
L		 3421 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3422 {
3423 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3424 i.tm.name);
3425 return 0;
3426 }
3427 if (i.mem_operands == 0
3428 || !operand_type_check (i.types[i.operands - 1], anymem))
3429 {
3430 as_bad (_("memory destination needed for instruction `%s'"
3431 " after `xrelease'"), i.tm.name);
3432 return 0;
3433 }
3434 return 1;
3435 }
3436}
3437
252b5132
RH		 3438/* This is the guts of the machine-dependent assembler. LINE points to a
3439 machine dependent instruction. This function is supposed to emit
3440 the frags/bytes it assembles to. */
3441
3442void
65da13b5 3443md_assemble (char *line)
252b5132 3444{
40fb9820 3445 unsigned int j;
252b5132 3446 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3447 const insn_template *t;
252b5132 3448
47926f60 3449 /* Initialize globals. */
252b5132
RH		 3450 memset (&i, '\0', sizeof (i));
3451 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3452 i.reloc[j] = NO_RELOC;
252b5132
RH		 3453 memset (disp_expressions, '\0', sizeof (disp_expressions));
3454 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3455 save_stack_p = save_stack;
252b5132
RH		 3456
3457 /* First parse an instruction mnemonic & call i386_operand for the operands.
3458 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3459 start of a (possibly prefixed) mnemonic. */
252b5132 3460
29b0f896
AM		 3461 line = parse_insn (line, mnemonic);
3462 if (line == NULL)
3463 return;
252b5132 3464
29b0f896 3465 line = parse_operands (line, mnemonic);
ee86248c 3466 this_operand = -1;
29b0f896
AM		 3467 if (line == NULL)
3468 return;
252b5132 3469
29b0f896
AM		 3470 /* Now we've parsed the mnemonic into a set of templates, and have the
3471 operands at hand. */
3472
3473 /* All intel opcodes have reversed operands except for "bound" and
3474 "enter". We also don't reverse intersegment "jmp" and "call"
3475 instructions with 2 immediate operands so that the immediate segment
050dfa73 3476 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3477 if (intel_syntax
3478 && i.operands > 1
29b0f896 3479 && (strcmp (mnemonic, "bound") != 0)
30123838 3480 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3481 && !(operand_type_check (i.types[0], imm)
3482 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3483 swap_operands ();
3484
ec56d5c0
JB		 3485 /* The order of the immediates should be reversed
3486 for 2 immediates extrq and insertq instructions */
3487 if (i.imm_operands == 2
3488 && (strcmp (mnemonic, "extrq") == 0
3489 || strcmp (mnemonic, "insertq") == 0))
3490 swap_2_operands (0, 1);
3491
29b0f896
AM		 3492 if (i.imm_operands)
3493 optimize_imm ();
3494
b300c311
L		 3495 /* Don't optimize displacement for movabs since it only takes 64bit
3496 displacement. */
3497 if (i.disp_operands
a501d77e 3498 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3499 && (flag_code != CODE_64BIT
3500 || strcmp (mnemonic, "movabs") != 0))
3501 optimize_disp ();
29b0f896
AM		 3502
3503 /* Next, we find a template that matches the given insn,
3504 making sure the overlap of the given operands types is consistent
3505 with the template operand types. */
252b5132 3506
fa99fab2 3507 if (!(t = match_template ()))
29b0f896 3508 return;
252b5132 3509
7bab8ab5 3510 if (sse_check != check_none
81f8a913 3511 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3512 && (i.tm.cpu_flags.bitfield.cpusse
3513 || i.tm.cpu_flags.bitfield.cpusse2
3514 || i.tm.cpu_flags.bitfield.cpusse3
3515 || i.tm.cpu_flags.bitfield.cpussse3
3516 || i.tm.cpu_flags.bitfield.cpusse4_1
3517 || i.tm.cpu_flags.bitfield.cpusse4_2))
3518 {
7bab8ab5 3519 (sse_check == check_warning
daf50ae7
L		 3520 ? as_warn
3521 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3522 }
3523
321fd21e
L		 3524 /* Zap movzx and movsx suffix. The suffix has been set from
3525 "word ptr" or "byte ptr" on the source operand in Intel syntax
3526 or extracted from mnemonic in AT&T syntax. But we'll use
3527 the destination register to choose the suffix for encoding. */
3528 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3529 {
321fd21e
L		 3530 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3531 there is no suffix, the default will be byte extension. */
3532 if (i.reg_operands != 2
3533 && !i.suffix
7ab9ffdd 3534 && intel_syntax)
321fd21e
L		 3535 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3536
3537 i.suffix = 0;
cd61ebfe 3538 }
24eab124 3539
40fb9820 3540 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3541 if (!add_prefix (FWAIT_OPCODE))
3542 return;
252b5132 3543
d5de92cf
L		 3544 /* Check if REP prefix is OK. */
3545 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3546 {
3547 as_bad (_("invalid instruction `%s' after `%s'"),
3548 i.tm.name, i.rep_prefix);
3549 return;
3550 }
3551
c1ba0266
L		 3552 /* Check for lock without a lockable instruction. Destination operand
3553 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3554 if (i.prefix[LOCK_PREFIX]
3555 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3556 || i.mem_operands == 0
3557 || (i.tm.base_opcode != 0x86
3558 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3559 {
3560 as_bad (_("expecting lockable instruction after `lock'"));
3561 return;
3562 }
3563
42164a71 3564 /* Check if HLE prefix is OK. */
165de32a 3565 if (i.hle_prefix && !check_hle ())
42164a71
L		 3566 return;
3567
7e8b059b
L		 3568 /* Check BND prefix. */
3569 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3570 as_bad (_("expecting valid branch instruction after `bnd'"));
3571
3572 if (i.tm.cpu_flags.bitfield.cpumpx
3573 && flag_code == CODE_64BIT
3574 && i.prefix[ADDR_PREFIX])
3575 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3576
3577 /* Insert BND prefix. */
3578 if (add_bnd_prefix
3579 && i.tm.opcode_modifier.bndprefixok
3580 && !i.prefix[BND_PREFIX])
3581 add_prefix (BND_PREFIX_OPCODE);
3582
29b0f896 3583 /* Check string instruction segment overrides. */
40fb9820 3584 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3585 {
3586 if (!check_string ())
5dd0794d 3587 return;
fc0763e6 3588 i.disp_operands = 0;
29b0f896 3589 }
5dd0794d 3590
29b0f896
AM		 3591 if (!process_suffix ())
3592 return;
e413e4e9 3593
bc0844ae
L		 3594 /* Update operand types. */
3595 for (j = 0; j < i.operands; j++)
3596 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3597
29b0f896
AM		 3598 /* Make still unresolved immediate matches conform to size of immediate
3599 given in i.suffix. */
3600 if (!finalize_imm ())
3601 return;
252b5132 3602
40fb9820 3603 if (i.types[0].bitfield.imm1)
29b0f896 3604 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3605
9afe6eb8
L		 3606 /* We only need to check those implicit registers for instructions
3607 with 3 operands or less. */
3608 if (i.operands <= 3)
3609 for (j = 0; j < i.operands; j++)
3610 if (i.types[j].bitfield.inoutportreg
3611 || i.types[j].bitfield.shiftcount
3612 || i.types[j].bitfield.acc
3613 || i.types[j].bitfield.floatacc)
3614 i.reg_operands--;
40fb9820 3615
c0f3af97
L		 3616 /* ImmExt should be processed after SSE2AVX. */
3617 if (!i.tm.opcode_modifier.sse2avx
3618 && i.tm.opcode_modifier.immext)
65da13b5 3619 process_immext ();
252b5132 3620
29b0f896
AM		 3621 /* For insns with operands there are more diddles to do to the opcode. */
3622 if (i.operands)
3623 {
3624 if (!process_operands ())
3625 return;
3626 }
40fb9820 3627 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3628 {
3629 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3630 as_warn (_("translating to `%sp'"), i.tm.name);
3631 }
252b5132 3632
c0f3af97 3633 if (i.tm.opcode_modifier.vex)
fa99fab2 3634 build_vex_prefix (t);
c0f3af97 3635
43234a1e
L		 3636 if (i.tm.opcode_modifier.evex)
3637 build_evex_prefix ();
3638
5dd85c99
SP		 3639 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3640 instructions may define INT_OPCODE as well, so avoid this corner
3641 case for those instructions that use MODRM. */
3642 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3643 && !i.tm.opcode_modifier.modrm
3644 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3645 {
3646 i.tm.base_opcode = INT3_OPCODE;
3647 i.imm_operands = 0;
3648 }
252b5132 3649
40fb9820
L		 3650 if ((i.tm.opcode_modifier.jump
3651 || i.tm.opcode_modifier.jumpbyte
3652 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3653 && i.op[0].disps->X_op == O_constant)
3654 {
3655 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3656 the absolute address given by the constant. Since ix86 jumps and
3657 calls are pc relative, we need to generate a reloc. */
3658 i.op[0].disps->X_add_symbol = &abs_symbol;
3659 i.op[0].disps->X_op = O_symbol;
3660 }
252b5132 3661
40fb9820 3662 if (i.tm.opcode_modifier.rex64)
161a04f6 3663 i.rex |= REX_W;
252b5132 3664
29b0f896
AM		 3665 /* For 8 bit registers we need an empty rex prefix. Also if the
3666 instruction already has a prefix, we need to convert old
3667 registers to new ones. */
773f551c 3668
40fb9820 3669 if ((i.types[0].bitfield.reg8
29b0f896 3670 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3671 || (i.types[1].bitfield.reg8
29b0f896 3672 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3673 || ((i.types[0].bitfield.reg8
3674 || i.types[1].bitfield.reg8)
29b0f896
AM		 3675 && i.rex != 0))
3676 {
3677 int x;
726c5dcd 3678
29b0f896
AM		 3679 i.rex |= REX_OPCODE;
3680 for (x = 0; x < 2; x++)
3681 {
3682 /* Look for 8 bit operand that uses old registers. */
40fb9820 3683 if (i.types[x].bitfield.reg8
29b0f896 3684 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3685 {
29b0f896
AM		 3686 /* In case it is "hi" register, give up. */
3687 if (i.op[x].regs->reg_num > 3)
a540244d 3688 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3689 "instruction requiring REX prefix."),
a540244d 3690 register_prefix, i.op[x].regs->reg_name);
773f551c 3691
29b0f896
AM		 3692 /* Otherwise it is equivalent to the extended register.
3693 Since the encoding doesn't change this is merely
3694 cosmetic cleanup for debug output. */
3695
3696 i.op[x].regs = i.op[x].regs + 8;
773f551c 3697 }
29b0f896
AM		 3698 }
3699 }
773f551c 3700
7ab9ffdd 3701 if (i.rex != 0)
29b0f896
AM		 3702 add_prefix (REX_OPCODE | i.rex);
3703
3704 /* We are ready to output the insn. */
3705 output_insn ();
3706}
3707
3708static char *
e3bb37b5 3709parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3710{
3711 char *l = line;
3712 char *token_start = l;
3713 char *mnem_p;
5c6af06e 3714 int supported;
d3ce72d0 3715 const insn_template *t;
b6169b20 3716 char *dot_p = NULL;
29b0f896 3717
29b0f896
AM		 3718 while (1)
3719 {
3720 mnem_p = mnemonic;
3721 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3722 {
b6169b20
L		 3723 if (*mnem_p == '.')
3724 dot_p = mnem_p;
29b0f896
AM		 3725 mnem_p++;
3726 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3727 {
29b0f896
AM		 3728 as_bad (_("no such instruction: `%s'"), token_start);
3729 return NULL;
3730 }
3731 l++;
3732 }
3733 if (!is_space_char (*l)
3734 && *l != END_OF_INSN
e44823cf
JB		 3735 && (intel_syntax
3736 || (*l != PREFIX_SEPARATOR
3737 && *l != ',')))
29b0f896
AM		 3738 {
3739 as_bad (_("invalid character %s in mnemonic"),
3740 output_invalid (*l));
3741 return NULL;
3742 }
3743 if (token_start == l)
3744 {
e44823cf 3745 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3746 as_bad (_("expecting prefix; got nothing"));
3747 else
3748 as_bad (_("expecting mnemonic; got nothing"));
3749 return NULL;
3750 }
45288df1 3751
29b0f896 3752 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3753 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3754
29b0f896
AM		 3755 if (*l != END_OF_INSN
3756 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3757 && current_templates
40fb9820 3758 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3759 {
c6fb90c8 3760 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3761 {
3762 as_bad ((flag_code != CODE_64BIT
3763 ? _("`%s' is only supported in 64-bit mode")
3764 : _("`%s' is not supported in 64-bit mode")),
3765 current_templates->start->name);
3766 return NULL;
3767 }
29b0f896
AM		 3768 /* If we are in 16-bit mode, do not allow addr16 or data16.
3769 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3770 if ((current_templates->start->opcode_modifier.size16
3771 || current_templates->start->opcode_modifier.size32)
29b0f896 3772 && flag_code != CODE_64BIT
40fb9820 3773 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3774 ^ (flag_code == CODE_16BIT)))
3775 {
3776 as_bad (_("redundant %s prefix"),
3777 current_templates->start->name);
3778 return NULL;
45288df1 3779 }
29b0f896
AM		 3780 /* Add prefix, checking for repeated prefixes. */
3781 switch (add_prefix (current_templates->start->base_opcode))
3782 {
c32fa91d 3783 case PREFIX_EXIST:
29b0f896 3784 return NULL;
c32fa91d 3785 case PREFIX_REP:
42164a71 3786 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3787 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3788 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3789 i.bnd_prefix = current_templates->start->name;
42164a71 3790 else
d5de92cf 3791 i.rep_prefix = current_templates->start->name;
29b0f896 3792 break;
c32fa91d
L		 3793 default:
3794 break;
29b0f896
AM		 3795 }
3796 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3797 token_start = ++l;
3798 }
3799 else
3800 break;
3801 }
45288df1 3802
30a55f88 3803 if (!current_templates)
b6169b20 3804 {
f8a5c266
L		 3805 /* Check if we should swap operand or force 32bit displacement in
3806 encoding. */
30a55f88
L		 3807 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3808 i.swap_operand = 1;
8d63c93e 3809 else if (mnem_p - 3 == dot_p
a501d77e
L		 3810 && dot_p[1] == 'd'
3811 && dot_p[2] == '8')
3812 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3813 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3814 && dot_p[1] == 'd'
3815 && dot_p[2] == '3'
3816 && dot_p[3] == '2')
a501d77e 3817 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3818 else
3819 goto check_suffix;
3820 mnem_p = dot_p;
3821 *dot_p = '\0';
d3ce72d0 3822 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3823 }
3824
29b0f896
AM		 3825 if (!current_templates)
3826 {
b6169b20 3827check_suffix:
29b0f896
AM		 3828 /* See if we can get a match by trimming off a suffix. */
3829 switch (mnem_p[-1])
3830 {
3831 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3832 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3833 i.suffix = SHORT_MNEM_SUFFIX;
3834 else
29b0f896
AM		 3835 case BYTE_MNEM_SUFFIX:
3836 case QWORD_MNEM_SUFFIX:
3837 i.suffix = mnem_p[-1];
3838 mnem_p[-1] = '\0';
d3ce72d0
NC		 3839 current_templates = (const templates *) hash_find (op_hash,
3840 mnemonic);
29b0f896
AM		 3841 break;
3842 case SHORT_MNEM_SUFFIX:
3843 case LONG_MNEM_SUFFIX:
3844 if (!intel_syntax)
3845 {
3846 i.suffix = mnem_p[-1];
3847 mnem_p[-1] = '\0';
d3ce72d0
NC		 3848 current_templates = (const templates *) hash_find (op_hash,
3849 mnemonic);
29b0f896
AM		 3850 }
3851 break;
252b5132 3852
29b0f896
AM		 3853 /* Intel Syntax. */
3854 case 'd':
3855 if (intel_syntax)
3856 {
9306ca4a 3857 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3858 i.suffix = SHORT_MNEM_SUFFIX;
3859 else
3860 i.suffix = LONG_MNEM_SUFFIX;
3861 mnem_p[-1] = '\0';
d3ce72d0
NC		 3862 current_templates = (const templates *) hash_find (op_hash,
3863 mnemonic);
29b0f896
AM		 3864 }
3865 break;
3866 }
3867 if (!current_templates)
3868 {
3869 as_bad (_("no such instruction: `%s'"), token_start);
3870 return NULL;
3871 }
3872 }
252b5132 3873
40fb9820
L		 3874 if (current_templates->start->opcode_modifier.jump
3875 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3876 {
3877 /* Check for a branch hint. We allow ",pt" and ",pn" for
3878 predict taken and predict not taken respectively.
3879 I'm not sure that branch hints actually do anything on loop
3880 and jcxz insns (JumpByte) for current Pentium4 chips. They
3881 may work in the future and it doesn't hurt to accept them
3882 now. */
3883 if (l[0] == ',' && l[1] == 'p')
3884 {
3885 if (l[2] == 't')
3886 {
3887 if (!add_prefix (DS_PREFIX_OPCODE))
3888 return NULL;
3889 l += 3;
3890 }
3891 else if (l[2] == 'n')
3892 {
3893 if (!add_prefix (CS_PREFIX_OPCODE))
3894 return NULL;
3895 l += 3;
3896 }
3897 }
3898 }
3899 /* Any other comma loses. */
3900 if (*l == ',')
3901 {
3902 as_bad (_("invalid character %s in mnemonic"),
3903 output_invalid (*l));
3904 return NULL;
3905 }
252b5132 3906
29b0f896 3907 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3908 supported = 0;
3909 for (t = current_templates->start; t < current_templates->end; ++t)
3910 {
c0f3af97
L		 3911 supported |= cpu_flags_match (t);
3912 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3913 goto skip;
5c6af06e 3914 }
3629bb00 3915
c0f3af97 3916 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3917 {
3918 as_bad (flag_code == CODE_64BIT
3919 ? _("`%s' is not supported in 64-bit mode")
3920 : _("`%s' is only supported in 64-bit mode"),
3921 current_templates->start->name);
3922 return NULL;
3923 }
c0f3af97 3924 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3925 {
3629bb00 3926 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3927 current_templates->start->name,
41aacd83 3928 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3929 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3930 return NULL;
29b0f896 3931 }
3629bb00
L		 3932
3933skip:
3934 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3935 && (flag_code != CODE_16BIT))
29b0f896
AM		 3936 {
3937 as_warn (_("use .code16 to ensure correct addressing mode"));
3938 }
252b5132 3939
29b0f896
AM		 3940 return l;
3941}
252b5132 3942
29b0f896 3943static char *
e3bb37b5 3944parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3945{
3946 char *token_start;
3138f287 3947
29b0f896
AM		 3948 /* 1 if operand is pending after ','. */
3949 unsigned int expecting_operand = 0;
252b5132 3950
29b0f896
AM		 3951 /* Non-zero if operand parens not balanced. */
3952 unsigned int paren_not_balanced;
3953
3954 while (*l != END_OF_INSN)
3955 {
3956 /* Skip optional white space before operand. */
3957 if (is_space_char (*l))
3958 ++l;
3959 if (!is_operand_char (*l) && *l != END_OF_INSN)
3960 {
3961 as_bad (_("invalid character %s before operand %d"),
3962 output_invalid (*l),
3963 i.operands + 1);
3964 return NULL;
3965 }
3966 token_start = l; /* after white space */
3967 paren_not_balanced = 0;
3968 while (paren_not_balanced || *l != ',')
3969 {
3970 if (*l == END_OF_INSN)
3971 {
3972 if (paren_not_balanced)
3973 {
3974 if (!intel_syntax)
3975 as_bad (_("unbalanced parenthesis in operand %d."),
3976 i.operands + 1);
3977 else
3978 as_bad (_("unbalanced brackets in operand %d."),
3979 i.operands + 1);
3980 return NULL;
3981 }
3982 else
3983 break; /* we are done */
3984 }
3985 else if (!is_operand_char (*l) && !is_space_char (*l))
3986 {
3987 as_bad (_("invalid character %s in operand %d"),
3988 output_invalid (*l),
3989 i.operands + 1);
3990 return NULL;
3991 }
3992 if (!intel_syntax)
3993 {
3994 if (*l == '(')
3995 ++paren_not_balanced;
3996 if (*l == ')')
3997 --paren_not_balanced;
3998 }
3999 else
4000 {
4001 if (*l == '[')
4002 ++paren_not_balanced;
4003 if (*l == ']')
4004 --paren_not_balanced;
4005 }
4006 l++;
4007 }
4008 if (l != token_start)
4009 { /* Yes, we've read in another operand. */
4010 unsigned int operand_ok;
4011 this_operand = i.operands++;
7d5e4556 4012 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4013 if (i.operands > MAX_OPERANDS)
4014 {
4015 as_bad (_("spurious operands; (%d operands/instruction max)"),
4016 MAX_OPERANDS);
4017 return NULL;
4018 }
4019 /* Now parse operand adding info to 'i' as we go along. */
4020 END_STRING_AND_SAVE (l);
4021
4022 if (intel_syntax)
4023 operand_ok =
4024 i386_intel_operand (token_start,
4025 intel_float_operand (mnemonic));
4026 else
a7619375 4027 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4028
4029 RESTORE_END_STRING (l);
4030 if (!operand_ok)
4031 return NULL;
4032 }
4033 else
4034 {
4035 if (expecting_operand)
4036 {
4037 expecting_operand_after_comma:
4038 as_bad (_("expecting operand after ','; got nothing"));
4039 return NULL;
4040 }
4041 if (*l == ',')
4042 {
4043 as_bad (_("expecting operand before ','; got nothing"));
4044 return NULL;
4045 }
4046 }
7f3f1ea2 4047
29b0f896
AM		 4048 /* Now *l must be either ',' or END_OF_INSN. */
4049 if (*l == ',')
4050 {
4051 if (*++l == END_OF_INSN)
4052 {
4053 /* Just skip it, if it's \n complain. */
4054 goto expecting_operand_after_comma;
4055 }
4056 expecting_operand = 1;
4057 }
4058 }
4059 return l;
4060}
7f3f1ea2 4061
050dfa73 4062static void
4d456e3d 4063swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4064{
4065 union i386_op temp_op;
40fb9820 4066 i386_operand_type temp_type;
050dfa73 4067 enum bfd_reloc_code_real temp_reloc;
4eed87de 4068
050dfa73
MM		 4069 temp_type = i.types[xchg2];
4070 i.types[xchg2] = i.types[xchg1];
4071 i.types[xchg1] = temp_type;
4072 temp_op = i.op[xchg2];
4073 i.op[xchg2] = i.op[xchg1];
4074 i.op[xchg1] = temp_op;
4075 temp_reloc = i.reloc[xchg2];
4076 i.reloc[xchg2] = i.reloc[xchg1];
4077 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4078
4079 if (i.mask)
4080 {
4081 if (i.mask->operand == xchg1)
4082 i.mask->operand = xchg2;
4083 else if (i.mask->operand == xchg2)
4084 i.mask->operand = xchg1;
4085 }
4086 if (i.broadcast)
4087 {
4088 if (i.broadcast->operand == xchg1)
4089 i.broadcast->operand = xchg2;
4090 else if (i.broadcast->operand == xchg2)
4091 i.broadcast->operand = xchg1;
4092 }
4093 if (i.rounding)
4094 {
4095 if (i.rounding->operand == xchg1)
4096 i.rounding->operand = xchg2;
4097 else if (i.rounding->operand == xchg2)
4098 i.rounding->operand = xchg1;
4099 }
050dfa73
MM		 4100}
4101
29b0f896 4102static void
e3bb37b5 4103swap_operands (void)
29b0f896 4104{
b7c61d9a 4105 switch (i.operands)
050dfa73 4106 {
c0f3af97 4107 case 5:
b7c61d9a 4108 case 4:
4d456e3d 4109 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4110 case 3:
4111 case 2:
4d456e3d 4112 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4113 break;
4114 default:
4115 abort ();
29b0f896 4116 }
29b0f896
AM		 4117
4118 if (i.mem_operands == 2)
4119 {
4120 const seg_entry *temp_seg;
4121 temp_seg = i.seg[0];
4122 i.seg[0] = i.seg[1];
4123 i.seg[1] = temp_seg;
4124 }
4125}
252b5132 4126
29b0f896
AM		 4127/* Try to ensure constant immediates are represented in the smallest
4128 opcode possible. */
4129static void
e3bb37b5 4130optimize_imm (void)
29b0f896
AM		 4131{
4132 char guess_suffix = 0;
4133 int op;
252b5132 4134
29b0f896
AM		 4135 if (i.suffix)
4136 guess_suffix = i.suffix;
4137 else if (i.reg_operands)
4138 {
4139 /* Figure out a suffix from the last register operand specified.
4140 We can't do this properly yet, ie. excluding InOutPortReg,
4141 but the following works for instructions with immediates.
4142 In any case, we can't set i.suffix yet. */
4143 for (op = i.operands; --op >= 0;)
40fb9820 4144 if (i.types[op].bitfield.reg8)
7ab9ffdd 4145 {
40fb9820
L		 4146 guess_suffix = BYTE_MNEM_SUFFIX;
4147 break;
4148 }
4149 else if (i.types[op].bitfield.reg16)
252b5132 4150 {
40fb9820
L		 4151 guess_suffix = WORD_MNEM_SUFFIX;
4152 break;
4153 }
4154 else if (i.types[op].bitfield.reg32)
4155 {
4156 guess_suffix = LONG_MNEM_SUFFIX;
4157 break;
4158 }
4159 else if (i.types[op].bitfield.reg64)
4160 {
4161 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4162 break;
252b5132 4163 }
29b0f896
AM		 4164 }
4165 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4166 guess_suffix = WORD_MNEM_SUFFIX;
4167
4168 for (op = i.operands; --op >= 0;)
40fb9820 4169 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4170 {
4171 switch (i.op[op].imms->X_op)
252b5132 4172 {
29b0f896
AM		 4173 case O_constant:
4174 /* If a suffix is given, this operand may be shortened. */
4175 switch (guess_suffix)
252b5132 4176 {
29b0f896 4177 case LONG_MNEM_SUFFIX:
40fb9820
L		 4178 i.types[op].bitfield.imm32 = 1;
4179 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4180 break;
4181 case WORD_MNEM_SUFFIX:
40fb9820
L		 4182 i.types[op].bitfield.imm16 = 1;
4183 i.types[op].bitfield.imm32 = 1;
4184 i.types[op].bitfield.imm32s = 1;
4185 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4186 break;
4187 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4188 i.types[op].bitfield.imm8 = 1;
4189 i.types[op].bitfield.imm8s = 1;
4190 i.types[op].bitfield.imm16 = 1;
4191 i.types[op].bitfield.imm32 = 1;
4192 i.types[op].bitfield.imm32s = 1;
4193 i.types[op].bitfield.imm64 = 1;
29b0f896 4194 break;
252b5132 4195 }
252b5132 4196
29b0f896
AM		 4197 /* If this operand is at most 16 bits, convert it
4198 to a signed 16 bit number before trying to see
4199 whether it will fit in an even smaller size.
4200 This allows a 16-bit operand such as $0xffe0 to
4201 be recognised as within Imm8S range. */
40fb9820 4202 if ((i.types[op].bitfield.imm16)
29b0f896 4203 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4204 {
29b0f896
AM		 4205 i.op[op].imms->X_add_number =
4206 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4207 }
40fb9820 4208 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4209 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4210 == 0))
4211 {
4212 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4213 ^ ((offsetT) 1 << 31))
4214 - ((offsetT) 1 << 31));
4215 }
40fb9820 4216 i.types[op]
c6fb90c8
L		 4217 = operand_type_or (i.types[op],
4218 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4219
29b0f896
AM		 4220 /* We must avoid matching of Imm32 templates when 64bit
4221 only immediate is available. */
4222 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4223 i.types[op].bitfield.imm32 = 0;
29b0f896 4224 break;
252b5132 4225
29b0f896
AM		 4226 case O_absent:
4227 case O_register:
4228 abort ();
4229
4230 /* Symbols and expressions. */
4231 default:
9cd96992
JB		 4232 /* Convert symbolic operand to proper sizes for matching, but don't
4233 prevent matching a set of insns that only supports sizes other
4234 than those matching the insn suffix. */
4235 {
40fb9820 4236 i386_operand_type mask, allowed;
d3ce72d0 4237 const insn_template *t;
9cd96992 4238
0dfbf9d7
L		 4239 operand_type_set (&mask, 0);
4240 operand_type_set (&allowed, 0);
40fb9820 4241
4eed87de
AM		 4242 for (t = current_templates->start;
4243 t < current_templates->end;
4244 ++t)
c6fb90c8
L		 4245 allowed = operand_type_or (allowed,
4246 t->operand_types[op]);
9cd96992
JB		 4247 switch (guess_suffix)
4248 {
4249 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4250 mask.bitfield.imm64 = 1;
4251 mask.bitfield.imm32s = 1;
9cd96992
JB		 4252 break;
4253 case LONG_MNEM_SUFFIX:
40fb9820 4254 mask.bitfield.imm32 = 1;
9cd96992
JB		 4255 break;
4256 case WORD_MNEM_SUFFIX:
40fb9820 4257 mask.bitfield.imm16 = 1;
9cd96992
JB		 4258 break;
4259 case BYTE_MNEM_SUFFIX:
40fb9820 4260 mask.bitfield.imm8 = 1;
9cd96992
JB		 4261 break;
4262 default:
9cd96992
JB		 4263 break;
4264 }
c6fb90c8 4265 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4266 if (!operand_type_all_zero (&allowed))
c6fb90c8 4267 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4268 }
29b0f896 4269 break;
252b5132 4270 }
29b0f896
AM		 4271 }
4272}
47926f60 4273
29b0f896
AM		 4274/* Try to use the smallest displacement type too. */
4275static void
e3bb37b5 4276optimize_disp (void)
29b0f896
AM		 4277{
4278 int op;
3e73aa7c 4279
29b0f896 4280 for (op = i.operands; --op >= 0;)
40fb9820 4281 if (operand_type_check (i.types[op], disp))
252b5132 4282 {
b300c311 4283 if (i.op[op].disps->X_op == O_constant)
252b5132 4284 {
91d6fa6a 4285 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4286
40fb9820 4287 if (i.types[op].bitfield.disp16
91d6fa6a 4288 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4289 {
4290 /* If this operand is at most 16 bits, convert
4291 to a signed 16 bit number and don't use 64bit
4292 displacement. */
91d6fa6a 4293 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4294 i.types[op].bitfield.disp64 = 0;
b300c311 4295 }
40fb9820 4296 if (i.types[op].bitfield.disp32
91d6fa6a 4297 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4298 {
4299 /* If this operand is at most 32 bits, convert
4300 to a signed 32 bit number and don't use 64bit
4301 displacement. */
91d6fa6a
NC		 4302 op_disp &= (((offsetT) 2 << 31) - 1);
4303 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4304 i.types[op].bitfield.disp64 = 0;
b300c311 4305 }
91d6fa6a 4306 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4307 {
40fb9820
L		 4308 i.types[op].bitfield.disp8 = 0;
4309 i.types[op].bitfield.disp16 = 0;
4310 i.types[op].bitfield.disp32 = 0;
4311 i.types[op].bitfield.disp32s = 0;
4312 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4313 i.op[op].disps = 0;
4314 i.disp_operands--;
4315 }
4316 else if (flag_code == CODE_64BIT)
4317 {
91d6fa6a 4318 if (fits_in_signed_long (op_disp))
28a9d8f5 4319 {
40fb9820
L		 4320 i.types[op].bitfield.disp64 = 0;
4321 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4322 }
0e1147d9 4323 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4324 && fits_in_unsigned_long (op_disp))
40fb9820 4325 i.types[op].bitfield.disp32 = 1;
b300c311 4326 }
40fb9820
L		 4327 if ((i.types[op].bitfield.disp32
4328 || i.types[op].bitfield.disp32s
4329 || i.types[op].bitfield.disp16)
91d6fa6a 4330 && fits_in_signed_byte (op_disp))
40fb9820 4331 i.types[op].bitfield.disp8 = 1;
252b5132 4332 }
67a4f2b7
AO		 4333 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4334 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4335 {
4336 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4337 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4338 i.types[op].bitfield.disp8 = 0;
4339 i.types[op].bitfield.disp16 = 0;
4340 i.types[op].bitfield.disp32 = 0;
4341 i.types[op].bitfield.disp32s = 0;
4342 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4343 }
4344 else
b300c311 4345 /* We only support 64bit displacement on constants. */
40fb9820 4346 i.types[op].bitfield.disp64 = 0;
252b5132 4347 }
29b0f896
AM		 4348}
4349
6c30d220
L		 4350/* Check if operands are valid for the instruction. */
4351
4352static int
4353check_VecOperands (const insn_template *t)
4354{
43234a1e
L		 4355 unsigned int op;
4356
6c30d220
L		 4357 /* Without VSIB byte, we can't have a vector register for index. */
4358 if (!t->opcode_modifier.vecsib
4359 && i.index_reg
4360 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4361 || i.index_reg->reg_type.bitfield.regymm
4362 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4363 {
4364 i.error = unsupported_vector_index_register;
4365 return 1;
4366 }
4367
ad8ecc81
MZ		 4368 /* Check if default mask is allowed. */
4369 if (t->opcode_modifier.nodefmask
4370 && (!i.mask || i.mask->mask->reg_num == 0))
4371 {
4372 i.error = no_default_mask;
4373 return 1;
4374 }
4375
7bab8ab5
JB		 4376 /* For VSIB byte, we need a vector register for index, and all vector
4377 registers must be distinct. */
4378 if (t->opcode_modifier.vecsib)
4379 {
4380 if (!i.index_reg
6c30d220
L		 4381 || !((t->opcode_modifier.vecsib == VecSIB128
4382 && i.index_reg->reg_type.bitfield.regxmm)
4383 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4384 && i.index_reg->reg_type.bitfield.regymm)
4385 || (t->opcode_modifier.vecsib == VecSIB512
4386 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4387 {
4388 i.error = invalid_vsib_address;
4389 return 1;
4390 }
4391
43234a1e
L		 4392 gas_assert (i.reg_operands == 2 || i.mask);
4393 if (i.reg_operands == 2 && !i.mask)
4394 {
4395 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4396 || i.types[0].bitfield.regymm);
43234a1e 4397 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4398 || i.types[2].bitfield.regymm);
43234a1e
L		 4399 if (operand_check == check_none)
4400 return 0;
4401 if (register_number (i.op[0].regs)
4402 != register_number (i.index_reg)
4403 && register_number (i.op[2].regs)
4404 != register_number (i.index_reg)
4405 && register_number (i.op[0].regs)
4406 != register_number (i.op[2].regs))
4407 return 0;
4408 if (operand_check == check_error)
4409 {
4410 i.error = invalid_vector_register_set;
4411 return 1;
4412 }
4413 as_warn (_("mask, index, and destination registers should be distinct"));
4414 }
8444f82a
MZ		 4415 else if (i.reg_operands == 1 && i.mask)
4416 {
4417 if ((i.types[1].bitfield.regymm
4418 || i.types[1].bitfield.regzmm)
4419 && (register_number (i.op[1].regs)
4420 == register_number (i.index_reg)))
4421 {
4422 if (operand_check == check_error)
4423 {
4424 i.error = invalid_vector_register_set;
4425 return 1;
4426 }
4427 if (operand_check != check_none)
4428 as_warn (_("index and destination registers should be distinct"));
4429 }
4430 }
43234a1e 4431 }
7bab8ab5 4432
43234a1e
L		 4433 /* Check if broadcast is supported by the instruction and is applied
4434 to the memory operand. */
4435 if (i.broadcast)
4436 {
4437 int broadcasted_opnd_size;
4438
4439 /* Check if specified broadcast is supported in this instruction,
4440 and it's applied to memory operand of DWORD or QWORD type,
4441 depending on VecESize. */
4442 if (i.broadcast->type != t->opcode_modifier.broadcast
4443 || !i.types[i.broadcast->operand].bitfield.mem
4444 || (t->opcode_modifier.vecesize == 0
4445 && !i.types[i.broadcast->operand].bitfield.dword
4446 && !i.types[i.broadcast->operand].bitfield.unspecified)
4447 || (t->opcode_modifier.vecesize == 1
4448 && !i.types[i.broadcast->operand].bitfield.qword
4449 && !i.types[i.broadcast->operand].bitfield.unspecified))
4450 goto bad_broadcast;
4451
4452 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4453 if (i.broadcast->type == BROADCAST_1TO16)
4454 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4455 else if (i.broadcast->type == BROADCAST_1TO8)
4456 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4457 else if (i.broadcast->type == BROADCAST_1TO4)
4458 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4459 else if (i.broadcast->type == BROADCAST_1TO2)
4460 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4461 else
4462 goto bad_broadcast;
4463
4464 if ((broadcasted_opnd_size == 256
4465 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4466 || (broadcasted_opnd_size == 512
4467 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4468 {
4469 bad_broadcast:
4470 i.error = unsupported_broadcast;
4471 return 1;
4472 }
4473 }
4474 /* If broadcast is supported in this instruction, we need to check if
4475 operand of one-element size isn't specified without broadcast. */
4476 else if (t->opcode_modifier.broadcast && i.mem_operands)
4477 {
4478 /* Find memory operand. */
4479 for (op = 0; op < i.operands; op++)
4480 if (operand_type_check (i.types[op], anymem))
4481 break;
4482 gas_assert (op < i.operands);
4483 /* Check size of the memory operand. */
4484 if ((t->opcode_modifier.vecesize == 0
4485 && i.types[op].bitfield.dword)
4486 || (t->opcode_modifier.vecesize == 1
4487 && i.types[op].bitfield.qword))
4488 {
4489 i.error = broadcast_needed;
4490 return 1;
4491 }
4492 }
4493
4494 /* Check if requested masking is supported. */
4495 if (i.mask
4496 && (!t->opcode_modifier.masking
4497 || (i.mask->zeroing
4498 && t->opcode_modifier.masking == MERGING_MASKING)))
4499 {
4500 i.error = unsupported_masking;
4501 return 1;
4502 }
4503
4504 /* Check if masking is applied to dest operand. */
4505 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4506 {
4507 i.error = mask_not_on_destination;
4508 return 1;
4509 }
4510
43234a1e
L		 4511 /* Check RC/SAE. */
4512 if (i.rounding)
4513 {
4514 if ((i.rounding->type != saeonly
4515 && !t->opcode_modifier.staticrounding)
4516 || (i.rounding->type == saeonly
4517 && (t->opcode_modifier.staticrounding
4518 || !t->opcode_modifier.sae)))
4519 {
4520 i.error = unsupported_rc_sae;
4521 return 1;
4522 }
4523 /* If the instruction has several immediate operands and one of
4524 them is rounding, the rounding operand should be the last
4525 immediate operand. */
4526 if (i.imm_operands > 1
4527 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4528 {
43234a1e 4529 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4530 return 1;
4531 }
6c30d220
L		 4532 }
4533
43234a1e
L		 4534 /* Check vector Disp8 operand. */
4535 if (t->opcode_modifier.disp8memshift)
4536 {
4537 if (i.broadcast)
4538 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4539 else
4540 i.memshift = t->opcode_modifier.disp8memshift;
4541
4542 for (op = 0; op < i.operands; op++)
4543 if (operand_type_check (i.types[op], disp)
4544 && i.op[op].disps->X_op == O_constant)
4545 {
4546 offsetT value = i.op[op].disps->X_add_number;
4547 int vec_disp8_ok = fits_in_vec_disp8 (value);
4548 if (t->operand_types [op].bitfield.vec_disp8)
4549 {
4550 if (vec_disp8_ok)
4551 i.types[op].bitfield.vec_disp8 = 1;
4552 else
4553 {
4554 /* Vector insn can only have Vec_Disp8/Disp32 in
4555 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4556 mode. */
4557 i.types[op].bitfield.disp8 = 0;
4558 if (flag_code != CODE_16BIT)
4559 i.types[op].bitfield.disp16 = 0;
4560 }
4561 }
4562 else if (flag_code != CODE_16BIT)
4563 {
4564 /* One form of this instruction supports vector Disp8.
4565 Try vector Disp8 if we need to use Disp32. */
4566 if (vec_disp8_ok && !fits_in_signed_byte (value))
4567 {
4568 i.error = try_vector_disp8;
4569 return 1;
4570 }
4571 }
4572 }
4573 }
4574 else
4575 i.memshift = -1;
4576
6c30d220
L		 4577 return 0;
4578}
4579
43f3e2ee 4580/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4581 operand types. */
4582
4583static int
4584VEX_check_operands (const insn_template *t)
4585{
43234a1e
L		 4586 /* VREX is only valid with EVEX prefix. */
4587 if (i.need_vrex && !t->opcode_modifier.evex)
4588 {
4589 i.error = invalid_register_operand;
4590 return 1;
4591 }
4592
a683cc34
SP		 4593 if (!t->opcode_modifier.vex)
4594 return 0;
4595
4596 /* Only check VEX_Imm4, which must be the first operand. */
4597 if (t->operand_types[0].bitfield.vec_imm4)
4598 {
4599 if (i.op[0].imms->X_op != O_constant
4600 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4601 {
a65babc9 4602 i.error = bad_imm4;
891edac4
L		 4603 return 1;
4604 }
a683cc34
SP		 4605
4606 /* Turn off Imm8 so that update_imm won't complain. */
4607 i.types[0] = vec_imm4;
4608 }
4609
4610 return 0;
4611}
4612
d3ce72d0 4613static const insn_template *
e3bb37b5 4614match_template (void)
29b0f896
AM		 4615{
4616 /* Points to template once we've found it. */
d3ce72d0 4617 const insn_template *t;
40fb9820 4618 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4619 i386_operand_type overlap4;
29b0f896 4620 unsigned int found_reverse_match;
40fb9820
L		 4621 i386_opcode_modifier suffix_check;
4622 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4623 int addr_prefix_disp;
a5c311ca 4624 unsigned int j;
3629bb00 4625 unsigned int found_cpu_match;
45664ddb 4626 unsigned int check_register;
5614d22c 4627 enum i386_error specific_error = 0;
29b0f896 4628
c0f3af97
L		 4629#if MAX_OPERANDS != 5
4630# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4631#endif
4632
29b0f896 4633 found_reverse_match = 0;
539e75ad 4634 addr_prefix_disp = -1;
40fb9820
L		 4635
4636 memset (&suffix_check, 0, sizeof (suffix_check));
4637 if (i.suffix == BYTE_MNEM_SUFFIX)
4638 suffix_check.no_bsuf = 1;
4639 else if (i.suffix == WORD_MNEM_SUFFIX)
4640 suffix_check.no_wsuf = 1;
4641 else if (i.suffix == SHORT_MNEM_SUFFIX)
4642 suffix_check.no_ssuf = 1;
4643 else if (i.suffix == LONG_MNEM_SUFFIX)
4644 suffix_check.no_lsuf = 1;
4645 else if (i.suffix == QWORD_MNEM_SUFFIX)
4646 suffix_check.no_qsuf = 1;
4647 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4648 suffix_check.no_ldsuf = 1;
29b0f896 4649
01559ecc
L		 4650 /* Must have right number of operands. */
4651 i.error = number_of_operands_mismatch;
4652
45aa61fe 4653 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4654 {
539e75ad
L		 4655 addr_prefix_disp = -1;
4656
29b0f896
AM		 4657 if (i.operands != t->operands)
4658 continue;
4659
50aecf8c 4660 /* Check processor support. */
a65babc9 4661 i.error = unsupported;
c0f3af97
L		 4662 found_cpu_match = (cpu_flags_match (t)
4663 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4664 if (!found_cpu_match)
4665 continue;
4666
e1d4d893 4667 /* Check old gcc support. */
a65babc9 4668 i.error = old_gcc_only;
e1d4d893
L		 4669 if (!old_gcc && t->opcode_modifier.oldgcc)
4670 continue;
4671
4672 /* Check AT&T mnemonic. */
a65babc9 4673 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4674 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4675 continue;
4676
891edac4 4677 /* Check AT&T/Intel syntax. */
a65babc9 4678 i.error = unsupported_syntax;
5c07affc
L		 4679 if ((intel_syntax && t->opcode_modifier.attsyntax)
4680 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4681 continue;
4682
20592a94 4683 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4684 i.error = invalid_instruction_suffix;
567e4e96
L		 4685 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4686 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4687 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4688 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4689 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4690 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4691 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4692 continue;
4693
5c07affc 4694 if (!operand_size_match (t))
7d5e4556 4695 continue;
539e75ad 4696
5c07affc
L		 4697 for (j = 0; j < MAX_OPERANDS; j++)
4698 operand_types[j] = t->operand_types[j];
4699
45aa61fe
AM		 4700 /* In general, don't allow 64-bit operands in 32-bit mode. */
4701 if (i.suffix == QWORD_MNEM_SUFFIX
4702 && flag_code != CODE_64BIT
4703 && (intel_syntax
40fb9820 4704 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4705 && !intel_float_operand (t->name))
4706 : intel_float_operand (t->name) != 2)
40fb9820 4707 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4708 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4709 && !operand_types[0].bitfield.regymm
4710 && !operand_types[0].bitfield.regzmm)
40fb9820 4711 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4712 && operand_types[t->operands > 1].bitfield.regxmm
4713 && operand_types[t->operands > 1].bitfield.regymm
4714 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4715 && (t->base_opcode != 0x0fc7
4716 || t->extension_opcode != 1 /* cmpxchg8b */))
4717 continue;
4718
192dc9c6
JB		 4719 /* In general, don't allow 32-bit operands on pre-386. */
4720 else if (i.suffix == LONG_MNEM_SUFFIX
4721 && !cpu_arch_flags.bitfield.cpui386
4722 && (intel_syntax
4723 ? (!t->opcode_modifier.ignoresize
4724 && !intel_float_operand (t->name))
4725 : intel_float_operand (t->name) != 2)
4726 && ((!operand_types[0].bitfield.regmmx
4727 && !operand_types[0].bitfield.regxmm)
4728 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4729 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4730 continue;
4731
29b0f896 4732 /* Do not verify operands when there are none. */
50aecf8c 4733 else
29b0f896 4734 {
c6fb90c8 4735 if (!t->operands)
2dbab7d5
L		 4736 /* We've found a match; break out of loop. */
4737 break;
29b0f896 4738 }
252b5132 4739
539e75ad
L		 4740 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4741 into Disp32/Disp16/Disp32 operand. */
4742 if (i.prefix[ADDR_PREFIX] != 0)
4743 {
40fb9820 4744 /* There should be only one Disp operand. */
539e75ad
L		 4745 switch (flag_code)
4746 {
4747 case CODE_16BIT:
40fb9820
L		 4748 for (j = 0; j < MAX_OPERANDS; j++)
4749 {
4750 if (operand_types[j].bitfield.disp16)
4751 {
4752 addr_prefix_disp = j;
4753 operand_types[j].bitfield.disp32 = 1;
4754 operand_types[j].bitfield.disp16 = 0;
4755 break;
4756 }
4757 }
539e75ad
L		 4758 break;
4759 case CODE_32BIT:
40fb9820
L		 4760 for (j = 0; j < MAX_OPERANDS; j++)
4761 {
4762 if (operand_types[j].bitfield.disp32)
4763 {
4764 addr_prefix_disp = j;
4765 operand_types[j].bitfield.disp32 = 0;
4766 operand_types[j].bitfield.disp16 = 1;
4767 break;
4768 }
4769 }
539e75ad
L		 4770 break;
4771 case CODE_64BIT:
40fb9820
L		 4772 for (j = 0; j < MAX_OPERANDS; j++)
4773 {
4774 if (operand_types[j].bitfield.disp64)
4775 {
4776 addr_prefix_disp = j;
4777 operand_types[j].bitfield.disp64 = 0;
4778 operand_types[j].bitfield.disp32 = 1;
4779 break;
4780 }
4781 }
539e75ad
L		 4782 break;
4783 }
539e75ad
L		 4784 }
4785
56ffb741
L		 4786 /* We check register size if needed. */
4787 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4788 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4789 switch (t->operands)
4790 {
4791 case 1:
40fb9820 4792 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4793 continue;
4794 break;
4795 case 2:
8b38ad71
L		 4796 /* xchg %eax, %eax is a special case. It is an aliase for nop
4797 only in 32bit mode and we can use opcode 0x90. In 64bit
4798 mode, we can't use 0x90 for xchg %eax, %eax since it should
4799 zero-extend %eax to %rax. */
4800 if (flag_code == CODE_64BIT
4801 && t->base_opcode == 0x90
0dfbf9d7
L		 4802 && operand_type_equal (&i.types [0], &acc32)
4803 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4804 continue;
b6169b20
L		 4805 if (i.swap_operand)
4806 {
4807 /* If we swap operand in encoding, we either match
4808 the next one or reverse direction of operands. */
4809 if (t->opcode_modifier.s)
4810 continue;
4811 else if (t->opcode_modifier.d)
4812 goto check_reverse;
4813 }
4814
29b0f896 4815 case 3:
fa99fab2
L		 4816 /* If we swap operand in encoding, we match the next one. */
4817 if (i.swap_operand && t->opcode_modifier.s)
4818 continue;
f48ff2ae 4819 case 4:
c0f3af97 4820 case 5:
c6fb90c8 4821 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4822 if (!operand_type_match (overlap0, i.types[0])
4823 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4824 || (check_register
4825 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4826 operand_types[0],
4827 overlap1, i.types[1],
4828 operand_types[1])))
29b0f896
AM		 4829 {
4830 /* Check if other direction is valid ... */
40fb9820 4831 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4832 continue;
4833
b6169b20 4834check_reverse:
29b0f896 4835 /* Try reversing direction of operands. */
c6fb90c8
L		 4836 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4837 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4838 if (!operand_type_match (overlap0, i.types[0])
4839 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4840 || (check_register
4841 && !operand_type_register_match (overlap0,
4842 i.types[0],
4843 operand_types[1],
4844 overlap1,
4845 i.types[1],
4846 operand_types[0])))
29b0f896
AM		 4847 {
4848 /* Does not match either direction. */
4849 continue;
4850 }
4851 /* found_reverse_match holds which of D or FloatDR
4852 we've found. */
40fb9820 4853 if (t->opcode_modifier.d)
8a2ed489 4854 found_reverse_match = Opcode_D;
40fb9820 4855 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4856 found_reverse_match = Opcode_FloatD;
4857 else
4858 found_reverse_match = 0;
40fb9820 4859 if (t->opcode_modifier.floatr)
8a2ed489 4860 found_reverse_match |= Opcode_FloatR;
29b0f896 4861 }
f48ff2ae 4862 else
29b0f896 4863 {
f48ff2ae 4864 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4865 switch (t->operands)
4866 {
c0f3af97
L		 4867 case 5:
4868 overlap4 = operand_type_and (i.types[4],
4869 operand_types[4]);
d1cbb4db 4870 case 4:
c6fb90c8
L		 4871 overlap3 = operand_type_and (i.types[3],
4872 operand_types[3]);
d1cbb4db 4873 case 3:
c6fb90c8
L		 4874 overlap2 = operand_type_and (i.types[2],
4875 operand_types[2]);
d1cbb4db
L		 4876 break;
4877 }
29b0f896 4878
f48ff2ae
L		 4879 switch (t->operands)
4880 {
c0f3af97
L		 4881 case 5:
4882 if (!operand_type_match (overlap4, i.types[4])
4883 || !operand_type_register_match (overlap3,
4884 i.types[3],
4885 operand_types[3],
4886 overlap4,
4887 i.types[4],
4888 operand_types[4]))
4889 continue;
f48ff2ae 4890 case 4:
40fb9820 4891 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4892 || (check_register
4893 && !operand_type_register_match (overlap2,
4894 i.types[2],
4895 operand_types[2],
4896 overlap3,
4897 i.types[3],
4898 operand_types[3])))
f48ff2ae
L		 4899 continue;
4900 case 3:
4901 /* Here we make use of the fact that there are no
4902 reverse match 3 operand instructions, and all 3
4903 operand instructions only need to be checked for
4904 register consistency between operands 2 and 3. */
40fb9820 4905 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4906 || (check_register
4907 && !operand_type_register_match (overlap1,
4908 i.types[1],
4909 operand_types[1],
4910 overlap2,
4911 i.types[2],
4912 operand_types[2])))
f48ff2ae
L		 4913 continue;
4914 break;
4915 }
29b0f896 4916 }
f48ff2ae 4917 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4918 slip through to break. */
4919 }
3629bb00 4920 if (!found_cpu_match)
29b0f896
AM		 4921 {
4922 found_reverse_match = 0;
4923 continue;
4924 }
c0f3af97 4925
5614d22c
JB		 4926 /* Check if vector and VEX operands are valid. */
4927 if (check_VecOperands (t) || VEX_check_operands (t))
4928 {
4929 specific_error = i.error;
4930 continue;
4931 }
a683cc34 4932
29b0f896
AM		 4933 /* We've found a match; break out of loop. */
4934 break;
4935 }
4936
4937 if (t == current_templates->end)
4938 {
4939 /* We found no match. */
a65babc9 4940 const char *err_msg;
5614d22c 4941 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4942 {
4943 default:
4944 abort ();
86e026a4 4945 case operand_size_mismatch:
a65babc9
L		 4946 err_msg = _("operand size mismatch");
4947 break;
4948 case operand_type_mismatch:
4949 err_msg = _("operand type mismatch");
4950 break;
4951 case register_type_mismatch:
4952 err_msg = _("register type mismatch");
4953 break;
4954 case number_of_operands_mismatch:
4955 err_msg = _("number of operands mismatch");
4956 break;
4957 case invalid_instruction_suffix:
4958 err_msg = _("invalid instruction suffix");
4959 break;
4960 case bad_imm4:
4a2608e3 4961 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4962 break;
4963 case old_gcc_only:
4964 err_msg = _("only supported with old gcc");
4965 break;
4966 case unsupported_with_intel_mnemonic:
4967 err_msg = _("unsupported with Intel mnemonic");
4968 break;
4969 case unsupported_syntax:
4970 err_msg = _("unsupported syntax");
4971 break;
4972 case unsupported:
35262a23 4973 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4974 current_templates->start->name);
4975 return NULL;
6c30d220
L		 4976 case invalid_vsib_address:
4977 err_msg = _("invalid VSIB address");
4978 break;
7bab8ab5
JB		 4979 case invalid_vector_register_set:
4980 err_msg = _("mask, index, and destination registers must be distinct");
4981 break;
6c30d220
L		 4982 case unsupported_vector_index_register:
4983 err_msg = _("unsupported vector index register");
4984 break;
43234a1e
L		 4985 case unsupported_broadcast:
4986 err_msg = _("unsupported broadcast");
4987 break;
4988 case broadcast_not_on_src_operand:
4989 err_msg = _("broadcast not on source memory operand");
4990 break;
4991 case broadcast_needed:
4992 err_msg = _("broadcast is needed for operand of such type");
4993 break;
4994 case unsupported_masking:
4995 err_msg = _("unsupported masking");
4996 break;
4997 case mask_not_on_destination:
4998 err_msg = _("mask not on destination operand");
4999 break;
5000 case no_default_mask:
5001 err_msg = _("default mask isn't allowed");
5002 break;
5003 case unsupported_rc_sae:
5004 err_msg = _("unsupported static rounding/sae");
5005 break;
5006 case rc_sae_operand_not_last_imm:
5007 if (intel_syntax)
5008 err_msg = _("RC/SAE operand must precede immediate operands");
5009 else
5010 err_msg = _("RC/SAE operand must follow immediate operands");
5011 break;
5012 case invalid_register_operand:
5013 err_msg = _("invalid register operand");
5014 break;
a65babc9
L		 5015 }
5016 as_bad (_("%s for `%s'"), err_msg,
891edac4 5017 current_templates->start->name);
fa99fab2 5018 return NULL;
29b0f896 5019 }
252b5132 5020
29b0f896
AM		 5021 if (!quiet_warnings)
5022 {
5023 if (!intel_syntax
40fb9820
L		 5024 && (i.types[0].bitfield.jumpabsolute
5025 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5026 {
5027 as_warn (_("indirect %s without `*'"), t->name);
5028 }
5029
40fb9820
L		 5030 if (t->opcode_modifier.isprefix
5031 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5032 {
5033 /* Warn them that a data or address size prefix doesn't
5034 affect assembly of the next line of code. */
5035 as_warn (_("stand-alone `%s' prefix"), t->name);
5036 }
5037 }
5038
5039 /* Copy the template we found. */
5040 i.tm = *t;
539e75ad
L		 5041
5042 if (addr_prefix_disp != -1)
5043 i.tm.operand_types[addr_prefix_disp]
5044 = operand_types[addr_prefix_disp];
5045
29b0f896
AM		 5046 if (found_reverse_match)
5047 {
5048 /* If we found a reverse match we must alter the opcode
5049 direction bit. found_reverse_match holds bits to change
5050 (different for int & float insns). */
5051
5052 i.tm.base_opcode ^= found_reverse_match;
5053
539e75ad
L		 5054 i.tm.operand_types[0] = operand_types[1];
5055 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5056 }
5057
fa99fab2 5058 return t;
29b0f896
AM		 5059}
5060
5061static int
e3bb37b5 5062check_string (void)
29b0f896 5063{
40fb9820
L		 5064 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5065 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5066 {
5067 if (i.seg[0] != NULL && i.seg[0] != &es)
5068 {
a87af027 5069 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5070 i.tm.name,
a87af027
JB		 5071 mem_op + 1,
5072 register_prefix);
29b0f896
AM		 5073 return 0;
5074 }
5075 /* There's only ever one segment override allowed per instruction.
5076 This instruction possibly has a legal segment override on the
5077 second operand, so copy the segment to where non-string
5078 instructions store it, allowing common code. */
5079 i.seg[0] = i.seg[1];
5080 }
40fb9820 5081 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5082 {
5083 if (i.seg[1] != NULL && i.seg[1] != &es)
5084 {
a87af027 5085 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5086 i.tm.name,
a87af027
JB		 5087 mem_op + 2,
5088 register_prefix);
29b0f896
AM		 5089 return 0;
5090 }
5091 }
5092 return 1;
5093}
5094
5095static int
543613e9 5096process_suffix (void)
29b0f896
AM		 5097{
5098 /* If matched instruction specifies an explicit instruction mnemonic
5099 suffix, use it. */
40fb9820
L		 5100 if (i.tm.opcode_modifier.size16)
5101 i.suffix = WORD_MNEM_SUFFIX;
5102 else if (i.tm.opcode_modifier.size32)
5103 i.suffix = LONG_MNEM_SUFFIX;
5104 else if (i.tm.opcode_modifier.size64)
5105 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5106 else if (i.reg_operands)
5107 {
5108 /* If there's no instruction mnemonic suffix we try to invent one
5109 based on register operands. */
5110 if (!i.suffix)
5111 {
5112 /* We take i.suffix from the last register operand specified,
5113 Destination register type is more significant than source
381d071f
L		 5114 register type. crc32 in SSE4.2 prefers source register
5115 type. */
5116 if (i.tm.base_opcode == 0xf20f38f1)
5117 {
40fb9820
L		 5118 if (i.types[0].bitfield.reg16)
5119 i.suffix = WORD_MNEM_SUFFIX;
5120 else if (i.types[0].bitfield.reg32)
5121 i.suffix = LONG_MNEM_SUFFIX;
5122 else if (i.types[0].bitfield.reg64)
5123 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5124 }
9344ff29 5125 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5126 {
40fb9820 5127 if (i.types[0].bitfield.reg8)
20592a94
L		 5128 i.suffix = BYTE_MNEM_SUFFIX;
5129 }
381d071f
L		 5130
5131 if (!i.suffix)
5132 {
5133 int op;
5134
20592a94
L		 5135 if (i.tm.base_opcode == 0xf20f38f1
5136 || i.tm.base_opcode == 0xf20f38f0)
5137 {
5138 /* We have to know the operand size for crc32. */
5139 as_bad (_("ambiguous memory operand size for `%s`"),
5140 i.tm.name);
5141 return 0;
5142 }
5143
381d071f 5144 for (op = i.operands; --op >= 0;)
40fb9820 5145 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5146 {
40fb9820
L		 5147 if (i.types[op].bitfield.reg8)
5148 {
5149 i.suffix = BYTE_MNEM_SUFFIX;
5150 break;
5151 }
5152 else if (i.types[op].bitfield.reg16)
5153 {
5154 i.suffix = WORD_MNEM_SUFFIX;
5155 break;
5156 }
5157 else if (i.types[op].bitfield.reg32)
5158 {
5159 i.suffix = LONG_MNEM_SUFFIX;
5160 break;
5161 }
5162 else if (i.types[op].bitfield.reg64)
5163 {
5164 i.suffix = QWORD_MNEM_SUFFIX;
5165 break;
5166 }
381d071f
L		 5167 }
5168 }
29b0f896
AM		 5169 }
5170 else if (i.suffix == BYTE_MNEM_SUFFIX)
5171 {
2eb952a4
L		 5172 if (intel_syntax
5173 && i.tm.opcode_modifier.ignoresize
5174 && i.tm.opcode_modifier.no_bsuf)
5175 i.suffix = 0;
5176 else if (!check_byte_reg ())
29b0f896
AM		 5177 return 0;
5178 }
5179 else if (i.suffix == LONG_MNEM_SUFFIX)
5180 {
2eb952a4
L		 5181 if (intel_syntax
5182 && i.tm.opcode_modifier.ignoresize
5183 && i.tm.opcode_modifier.no_lsuf)
5184 i.suffix = 0;
5185 else if (!check_long_reg ())
29b0f896
AM		 5186 return 0;
5187 }
5188 else if (i.suffix == QWORD_MNEM_SUFFIX)
5189 {
955e1e6a
L		 5190 if (intel_syntax
5191 && i.tm.opcode_modifier.ignoresize
5192 && i.tm.opcode_modifier.no_qsuf)
5193 i.suffix = 0;
5194 else if (!check_qword_reg ())
29b0f896
AM		 5195 return 0;
5196 }
5197 else if (i.suffix == WORD_MNEM_SUFFIX)
5198 {
2eb952a4
L		 5199 if (intel_syntax
5200 && i.tm.opcode_modifier.ignoresize
5201 && i.tm.opcode_modifier.no_wsuf)
5202 i.suffix = 0;
5203 else if (!check_word_reg ())
29b0f896
AM		 5204 return 0;
5205 }
c0f3af97 5206 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5207 || i.suffix == YMMWORD_MNEM_SUFFIX
5208 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5209 {
43234a1e 5210 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5211 should check if it is a valid suffix. */
5212 }
40fb9820 5213 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5214 /* Do nothing if the instruction is going to ignore the prefix. */
5215 ;
5216 else
5217 abort ();
5218 }
40fb9820 5219 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5220 && !i.suffix
5221 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5222 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5223 {
5224 i.suffix = stackop_size;
5225 }
9306ca4a
JB		 5226 else if (intel_syntax
5227 && !i.suffix
40fb9820
L		 5228 && (i.tm.operand_types[0].bitfield.jumpabsolute
5229 || i.tm.opcode_modifier.jumpbyte
5230 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5231 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5232 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5233 {
5234 switch (flag_code)
5235 {
5236 case CODE_64BIT:
40fb9820 5237 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5238 {
5239 i.suffix = QWORD_MNEM_SUFFIX;
5240 break;
5241 }
5242 case CODE_32BIT:
40fb9820 5243 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5244 i.suffix = LONG_MNEM_SUFFIX;
5245 break;
5246 case CODE_16BIT:
40fb9820 5247 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5248 i.suffix = WORD_MNEM_SUFFIX;
5249 break;
5250 }
5251 }
252b5132 5252
9306ca4a 5253 if (!i.suffix)
29b0f896 5254 {
9306ca4a
JB		 5255 if (!intel_syntax)
5256 {
40fb9820 5257 if (i.tm.opcode_modifier.w)
9306ca4a 5258 {
4eed87de
AM		 5259 as_bad (_("no instruction mnemonic suffix given and "
5260 "no register operands; can't size instruction"));
9306ca4a
JB		 5261 return 0;
5262 }
5263 }
5264 else
5265 {
40fb9820 5266 unsigned int suffixes;
7ab9ffdd 5267
40fb9820
L		 5268 suffixes = !i.tm.opcode_modifier.no_bsuf;
5269 if (!i.tm.opcode_modifier.no_wsuf)
5270 suffixes |= 1 << 1;
5271 if (!i.tm.opcode_modifier.no_lsuf)
5272 suffixes |= 1 << 2;
fc4adea1 5273 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5274 suffixes |= 1 << 3;
5275 if (!i.tm.opcode_modifier.no_ssuf)
5276 suffixes |= 1 << 4;
5277 if (!i.tm.opcode_modifier.no_qsuf)
5278 suffixes |= 1 << 5;
5279
5280 /* There are more than suffix matches. */
5281 if (i.tm.opcode_modifier.w
9306ca4a 5282 || ((suffixes & (suffixes - 1))
40fb9820
L		 5283 && !i.tm.opcode_modifier.defaultsize
5284 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5285 {
5286 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5287 return 0;
5288 }
5289 }
29b0f896 5290 }
252b5132 5291
9306ca4a
JB		 5292 /* Change the opcode based on the operand size given by i.suffix;
5293 We don't need to change things for byte insns. */
5294
582d5edd
L		 5295 if (i.suffix
5296 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5297 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5298 && i.suffix != YMMWORD_MNEM_SUFFIX
5299 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5300 {
5301 /* It's not a byte, select word/dword operation. */
40fb9820 5302 if (i.tm.opcode_modifier.w)
29b0f896 5303 {
40fb9820 5304 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5305 i.tm.base_opcode |= 8;
5306 else
5307 i.tm.base_opcode |= 1;
5308 }
0f3f3d8b 5309
29b0f896
AM		 5310 /* Now select between word & dword operations via the operand
5311 size prefix, except for instructions that will ignore this
5312 prefix anyway. */
ca61edf2 5313 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5314 {
ca61edf2
L		 5315 /* The address size override prefix changes the size of the
5316 first operand. */
40fb9820
L		 5317 if ((flag_code == CODE_32BIT
5318 && i.op->regs[0].reg_type.bitfield.reg16)
5319 || (flag_code != CODE_32BIT
5320 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5321 if (!add_prefix (ADDR_PREFIX_OPCODE))
5322 return 0;
5323 }
5324 else if (i.suffix != QWORD_MNEM_SUFFIX
5325 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5326 && !i.tm.opcode_modifier.ignoresize
5327 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5328 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5329 || (flag_code == CODE_64BIT
40fb9820 5330 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5331 {
5332 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5333
40fb9820 5334 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5335 prefix = ADDR_PREFIX_OPCODE;
252b5132 5336
29b0f896
AM		 5337 if (!add_prefix (prefix))
5338 return 0;
24eab124 5339 }
252b5132 5340
29b0f896
AM		 5341 /* Set mode64 for an operand. */
5342 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5343 && flag_code == CODE_64BIT
40fb9820 5344 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5345 {
5346 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5347 need rex64. cmpxchg8b is also a special case. */
5348 if (! (i.operands == 2
5349 && i.tm.base_opcode == 0x90
5350 && i.tm.extension_opcode == None
0dfbf9d7
L		 5351 && operand_type_equal (&i.types [0], &acc64)
5352 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5353 && ! (i.operands == 1
5354 && i.tm.base_opcode == 0xfc7
5355 && i.tm.extension_opcode == 1
40fb9820
L		 5356 && !operand_type_check (i.types [0], reg)
5357 && operand_type_check (i.types [0], anymem)))
f6bee062 5358 i.rex |= REX_W;
46e883c5 5359 }
3e73aa7c 5360
29b0f896
AM		 5361 /* Size floating point instruction. */
5362 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5363 if (i.tm.opcode_modifier.floatmf)
543613e9 5364 i.tm.base_opcode ^= 4;
29b0f896 5365 }
7ecd2f8b 5366
29b0f896
AM		 5367 return 1;
5368}
3e73aa7c 5369
29b0f896 5370static int
543613e9 5371check_byte_reg (void)
29b0f896
AM		 5372{
5373 int op;
543613e9 5374
29b0f896
AM		 5375 for (op = i.operands; --op >= 0;)
5376 {
5377 /* If this is an eight bit register, it's OK. If it's the 16 or
5378 32 bit version of an eight bit register, we will just use the
5379 low portion, and that's OK too. */
40fb9820 5380 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5381 continue;
5382
5a819eb9
JB		 5383 /* I/O port address operands are OK too. */
5384 if (i.tm.operand_types[op].bitfield.inoutportreg)
5385 continue;
5386
9344ff29
L		 5387 /* crc32 doesn't generate this warning. */
5388 if (i.tm.base_opcode == 0xf20f38f0)
5389 continue;
5390
40fb9820
L		 5391 if ((i.types[op].bitfield.reg16
5392 || i.types[op].bitfield.reg32
5393 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5394 && i.op[op].regs->reg_num < 4
5395 /* Prohibit these changes in 64bit mode, since the lowering
5396 would be more complicated. */
5397 && flag_code != CODE_64BIT)
29b0f896 5398 {
29b0f896 5399#if REGISTER_WARNINGS
5a819eb9 5400 if (!quiet_warnings)
a540244d
L		 5401 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5402 register_prefix,
40fb9820 5403 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5404 ? REGNAM_AL - REGNAM_AX
5405 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5406 register_prefix,
29b0f896
AM		 5407 i.op[op].regs->reg_name,
5408 i.suffix);
5409#endif
5410 continue;
5411 }
5412 /* Any other register is bad. */
40fb9820
L		 5413 if (i.types[op].bitfield.reg16
5414 || i.types[op].bitfield.reg32
5415 || i.types[op].bitfield.reg64
5416 || i.types[op].bitfield.regmmx
5417 || i.types[op].bitfield.regxmm
c0f3af97 5418 || i.types[op].bitfield.regymm
43234a1e 5419 || i.types[op].bitfield.regzmm
40fb9820
L		 5420 || i.types[op].bitfield.sreg2
5421 || i.types[op].bitfield.sreg3
5422 || i.types[op].bitfield.control
5423 || i.types[op].bitfield.debug
5424 || i.types[op].bitfield.test
5425 || i.types[op].bitfield.floatreg
5426 || i.types[op].bitfield.floatacc)
29b0f896 5427 {
a540244d
L		 5428 as_bad (_("`%s%s' not allowed with `%s%c'"),
5429 register_prefix,
29b0f896
AM		 5430 i.op[op].regs->reg_name,
5431 i.tm.name,
5432 i.suffix);
5433 return 0;
5434 }
5435 }
5436 return 1;
5437}
5438
5439static int
e3bb37b5 5440check_long_reg (void)
29b0f896
AM		 5441{
5442 int op;
5443
5444 for (op = i.operands; --op >= 0;)
5445 /* Reject eight bit registers, except where the template requires
5446 them. (eg. movzb) */
40fb9820
L		 5447 if (i.types[op].bitfield.reg8
5448 && (i.tm.operand_types[op].bitfield.reg16
5449 || i.tm.operand_types[op].bitfield.reg32
5450 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5451 {
a540244d
L		 5452 as_bad (_("`%s%s' not allowed with `%s%c'"),
5453 register_prefix,
29b0f896
AM		 5454 i.op[op].regs->reg_name,
5455 i.tm.name,
5456 i.suffix);
5457 return 0;
5458 }
e4630f71 5459 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5460 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5461 && i.types[op].bitfield.reg16
5462 && (i.tm.operand_types[op].bitfield.reg32
5463 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5464 {
5465 /* Prohibit these changes in the 64bit mode, since the
5466 lowering is more complicated. */
5467 if (flag_code == CODE_64BIT)
252b5132 5468 {
2b5d6a91 5469 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5470 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5471 i.suffix);
5472 return 0;
252b5132 5473 }
29b0f896 5474#if REGISTER_WARNINGS
cecf1424
JB		 5475 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5476 register_prefix,
5477 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5478 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5479#endif
252b5132 5480 }
e4630f71 5481 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5482 else if (i.types[op].bitfield.reg64
5483 && (i.tm.operand_types[op].bitfield.reg32
5484 || i.tm.operand_types[op].bitfield.acc))
252b5132 5485 {
34828aad 5486 if (intel_syntax
ca61edf2 5487 && i.tm.opcode_modifier.toqword
40fb9820 5488 && !i.types[0].bitfield.regxmm)
34828aad 5489 {
ca61edf2 5490 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5491 i.suffix = QWORD_MNEM_SUFFIX;
5492 }
5493 else
5494 {
2b5d6a91 5495 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5496 register_prefix, i.op[op].regs->reg_name,
5497 i.suffix);
5498 return 0;
5499 }
29b0f896
AM		 5500 }
5501 return 1;
5502}
252b5132 5503
29b0f896 5504static int
e3bb37b5 5505check_qword_reg (void)
29b0f896
AM		 5506{
5507 int op;
252b5132 5508
29b0f896
AM		 5509 for (op = i.operands; --op >= 0; )
5510 /* Reject eight bit registers, except where the template requires
5511 them. (eg. movzb) */
40fb9820
L		 5512 if (i.types[op].bitfield.reg8
5513 && (i.tm.operand_types[op].bitfield.reg16
5514 || i.tm.operand_types[op].bitfield.reg32
5515 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5516 {
a540244d
L		 5517 as_bad (_("`%s%s' not allowed with `%s%c'"),
5518 register_prefix,
29b0f896
AM		 5519 i.op[op].regs->reg_name,
5520 i.tm.name,
5521 i.suffix);
5522 return 0;
5523 }
e4630f71 5524 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5525 else if ((i.types[op].bitfield.reg16
5526 || i.types[op].bitfield.reg32)
5527 && (i.tm.operand_types[op].bitfield.reg32
5528 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5529 {
5530 /* Prohibit these changes in the 64bit mode, since the
5531 lowering is more complicated. */
34828aad 5532 if (intel_syntax
ca61edf2 5533 && i.tm.opcode_modifier.todword
40fb9820 5534 && !i.types[0].bitfield.regxmm)
34828aad 5535 {
ca61edf2 5536 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5537 i.suffix = LONG_MNEM_SUFFIX;
5538 }
5539 else
5540 {
2b5d6a91 5541 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5542 register_prefix, i.op[op].regs->reg_name,
5543 i.suffix);
5544 return 0;
5545 }
252b5132 5546 }
29b0f896
AM		 5547 return 1;
5548}
252b5132 5549
29b0f896 5550static int
e3bb37b5 5551check_word_reg (void)
29b0f896
AM		 5552{
5553 int op;
5554 for (op = i.operands; --op >= 0;)
5555 /* Reject eight bit registers, except where the template requires
5556 them. (eg. movzb) */
40fb9820
L		 5557 if (i.types[op].bitfield.reg8
5558 && (i.tm.operand_types[op].bitfield.reg16
5559 || i.tm.operand_types[op].bitfield.reg32
5560 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5561 {
a540244d
L		 5562 as_bad (_("`%s%s' not allowed with `%s%c'"),
5563 register_prefix,
29b0f896
AM		 5564 i.op[op].regs->reg_name,
5565 i.tm.name,
5566 i.suffix);
5567 return 0;
5568 }
e4630f71 5569 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5570 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5571 && (i.types[op].bitfield.reg32
5572 || i.types[op].bitfield.reg64)
40fb9820
L		 5573 && (i.tm.operand_types[op].bitfield.reg16
5574 || i.tm.operand_types[op].bitfield.acc))
252b5132 5575 {
29b0f896
AM		 5576 /* Prohibit these changes in the 64bit mode, since the
5577 lowering is more complicated. */
5578 if (flag_code == CODE_64BIT)
252b5132 5579 {
2b5d6a91 5580 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5581 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5582 i.suffix);
5583 return 0;
252b5132 5584 }
29b0f896 5585#if REGISTER_WARNINGS
cecf1424
JB		 5586 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5587 register_prefix,
5588 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5589 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5590#endif
5591 }
5592 return 1;
5593}
252b5132 5594
29b0f896 5595static int
40fb9820 5596update_imm (unsigned int j)
29b0f896 5597{
bc0844ae 5598 i386_operand_type overlap = i.types[j];
40fb9820
L		 5599 if ((overlap.bitfield.imm8
5600 || overlap.bitfield.imm8s
5601 || overlap.bitfield.imm16
5602 || overlap.bitfield.imm32
5603 || overlap.bitfield.imm32s
5604 || overlap.bitfield.imm64)
0dfbf9d7
L		 5605 && !operand_type_equal (&overlap, &imm8)
5606 && !operand_type_equal (&overlap, &imm8s)
5607 && !operand_type_equal (&overlap, &imm16)
5608 && !operand_type_equal (&overlap, &imm32)
5609 && !operand_type_equal (&overlap, &imm32s)
5610 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5611 {
5612 if (i.suffix)
5613 {
40fb9820
L		 5614 i386_operand_type temp;
5615
0dfbf9d7 5616 operand_type_set (&temp, 0);
7ab9ffdd 5617 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5618 {
5619 temp.bitfield.imm8 = overlap.bitfield.imm8;
5620 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5621 }
5622 else if (i.suffix == WORD_MNEM_SUFFIX)
5623 temp.bitfield.imm16 = overlap.bitfield.imm16;
5624 else if (i.suffix == QWORD_MNEM_SUFFIX)
5625 {
5626 temp.bitfield.imm64 = overlap.bitfield.imm64;
5627 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5628 }
5629 else
5630 temp.bitfield.imm32 = overlap.bitfield.imm32;
5631 overlap = temp;
29b0f896 5632 }
0dfbf9d7
L		 5633 else if (operand_type_equal (&overlap, &imm16_32_32s)
5634 || operand_type_equal (&overlap, &imm16_32)
5635 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5636 {
40fb9820 5637 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5638 overlap = imm16;
40fb9820 5639 else
65da13b5 5640 overlap = imm32s;
29b0f896 5641 }
0dfbf9d7
L		 5642 if (!operand_type_equal (&overlap, &imm8)
5643 && !operand_type_equal (&overlap, &imm8s)
5644 && !operand_type_equal (&overlap, &imm16)
5645 && !operand_type_equal (&overlap, &imm32)
5646 && !operand_type_equal (&overlap, &imm32s)
5647 && !operand_type_equal (&overlap, &imm64))
29b0f896 5648 {
4eed87de
AM		 5649 as_bad (_("no instruction mnemonic suffix given; "
5650 "can't determine immediate size"));
29b0f896
AM		 5651 return 0;
5652 }
5653 }
40fb9820 5654 i.types[j] = overlap;
29b0f896 5655
40fb9820
L		 5656 return 1;
5657}
5658
5659static int
5660finalize_imm (void)
5661{
bc0844ae 5662 unsigned int j, n;
29b0f896 5663
bc0844ae
L		 5664 /* Update the first 2 immediate operands. */
5665 n = i.operands > 2 ? 2 : i.operands;
5666 if (n)
5667 {
5668 for (j = 0; j < n; j++)
5669 if (update_imm (j) == 0)
5670 return 0;
40fb9820 5671
bc0844ae
L		 5672 /* The 3rd operand can't be immediate operand. */
5673 gas_assert (operand_type_check (i.types[2], imm) == 0);
5674 }
29b0f896
AM		 5675
5676 return 1;
5677}
5678
c0f3af97
L		 5679static int
5680bad_implicit_operand (int xmm)
5681{
91d6fa6a
NC		 5682 const char *ireg = xmm ? "xmm0" : "ymm0";
5683
c0f3af97
L		 5684 if (intel_syntax)
5685 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5686 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5687 else
5688 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5689 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5690 return 0;
5691}
5692
29b0f896 5693static int
e3bb37b5 5694process_operands (void)
29b0f896
AM		 5695{
5696 /* Default segment register this instruction will use for memory
5697 accesses. 0 means unknown. This is only for optimizing out
5698 unnecessary segment overrides. */
5699 const seg_entry *default_seg = 0;
5700
2426c15f 5701 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5702 {
91d6fa6a
NC		 5703 unsigned int dupl = i.operands;
5704 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5705 unsigned int j;
5706
c0f3af97 5707 /* The destination must be an xmm register. */
9c2799c2 5708 gas_assert (i.reg_operands
91d6fa6a 5709 && MAX_OPERANDS > dupl
7ab9ffdd 5710 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5711
5712 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5713 {
c0f3af97 5714 /* The first operand is implicit and must be xmm0. */
9c2799c2 5715 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5716 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5717 return bad_implicit_operand (1);
5718
8cd7925b 5719 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5720 {
5721 /* Keep xmm0 for instructions with VEX prefix and 3
5722 sources. */
5723 goto duplicate;
5724 }
e2ec9d29 5725 else
c0f3af97
L		 5726 {
5727 /* We remove the first xmm0 and keep the number of
5728 operands unchanged, which in fact duplicates the
5729 destination. */
5730 for (j = 1; j < i.operands; j++)
5731 {
5732 i.op[j - 1] = i.op[j];
5733 i.types[j - 1] = i.types[j];
5734 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5735 }
5736 }
5737 }
5738 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5739 {
91d6fa6a 5740 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5741 && (i.tm.opcode_modifier.vexsources
5742 == VEX3SOURCES));
c0f3af97
L		 5743
5744 /* Add the implicit xmm0 for instructions with VEX prefix
5745 and 3 sources. */
5746 for (j = i.operands; j > 0; j--)
5747 {
5748 i.op[j] = i.op[j - 1];
5749 i.types[j] = i.types[j - 1];
5750 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5751 }
5752 i.op[0].regs
5753 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5754 i.types[0] = regxmm;
c0f3af97
L		 5755 i.tm.operand_types[0] = regxmm;
5756
5757 i.operands += 2;
5758 i.reg_operands += 2;
5759 i.tm.operands += 2;
5760
91d6fa6a 5761 dupl++;
c0f3af97 5762 dest++;
91d6fa6a
NC		 5763 i.op[dupl] = i.op[dest];
5764 i.types[dupl] = i.types[dest];
5765 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5766 }
c0f3af97
L		 5767 else
5768 {
5769duplicate:
5770 i.operands++;
5771 i.reg_operands++;
5772 i.tm.operands++;
5773
91d6fa6a
NC		 5774 i.op[dupl] = i.op[dest];
5775 i.types[dupl] = i.types[dest];
5776 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5777 }
5778
5779 if (i.tm.opcode_modifier.immext)
5780 process_immext ();
5781 }
5782 else if (i.tm.opcode_modifier.firstxmm0)
5783 {
5784 unsigned int j;
5785
43234a1e 5786 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5787 gas_assert (i.reg_operands
7ab9ffdd 5788 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5789 || operand_type_equal (&i.types[0], &regymm)
5790 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5791 if (register_number (i.op[0].regs) != 0)
c0f3af97 5792 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5793
5794 for (j = 1; j < i.operands; j++)
5795 {
5796 i.op[j - 1] = i.op[j];
5797 i.types[j - 1] = i.types[j];
5798
5799 /* We need to adjust fields in i.tm since they are used by
5800 build_modrm_byte. */
5801 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5802 }
5803
e2ec9d29
L		 5804 i.operands--;
5805 i.reg_operands--;
e2ec9d29
L		 5806 i.tm.operands--;
5807 }
5808 else if (i.tm.opcode_modifier.regkludge)
5809 {
5810 /* The imul $imm, %reg instruction is converted into
5811 imul $imm, %reg, %reg, and the clr %reg instruction
5812 is converted into xor %reg, %reg. */
5813
5814 unsigned int first_reg_op;
5815
5816 if (operand_type_check (i.types[0], reg))
5817 first_reg_op = 0;
5818 else
5819 first_reg_op = 1;
5820 /* Pretend we saw the extra register operand. */
9c2799c2 5821 gas_assert (i.reg_operands == 1
7ab9ffdd 5822 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5823 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5824 i.types[first_reg_op + 1] = i.types[first_reg_op];
5825 i.operands++;
5826 i.reg_operands++;
29b0f896
AM		 5827 }
5828
40fb9820 5829 if (i.tm.opcode_modifier.shortform)
29b0f896 5830 {
40fb9820
L		 5831 if (i.types[0].bitfield.sreg2
5832 || i.types[0].bitfield.sreg3)
29b0f896 5833 {
4eed87de
AM		 5834 if (i.tm.base_opcode == POP_SEG_SHORT
5835 && i.op[0].regs->reg_num == 1)
29b0f896 5836 {
a87af027 5837 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5838 return 0;
29b0f896 5839 }
4eed87de
AM		 5840 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5841 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5842 i.rex |= REX_B;
4eed87de
AM		 5843 }
5844 else
5845 {
7ab9ffdd 5846 /* The register or float register operand is in operand
85f10a01 5847 0 or 1. */
40fb9820 5848 unsigned int op;
7ab9ffdd
L		 5849
5850 if (i.types[0].bitfield.floatreg
5851 || operand_type_check (i.types[0], reg))
5852 op = 0;
5853 else
5854 op = 1;
4eed87de
AM		 5855 /* Register goes in low 3 bits of opcode. */
5856 i.tm.base_opcode |= i.op[op].regs->reg_num;
5857 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5858 i.rex |= REX_B;
40fb9820 5859 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5860 {
4eed87de
AM		 5861 /* Warn about some common errors, but press on regardless.
5862 The first case can be generated by gcc (<= 2.8.1). */
5863 if (i.operands == 2)
5864 {
5865 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5866 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5867 register_prefix, i.op[!intel_syntax].regs->reg_name,
5868 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5869 }
5870 else
5871 {
5872 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5873 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5874 register_prefix, i.op[0].regs->reg_name);
4eed87de 5875 }
29b0f896
AM		 5876 }
5877 }
5878 }
40fb9820 5879 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5880 {
5881 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5882 must be put into the modrm byte). Now, we make the modrm and
5883 index base bytes based on all the info we've collected. */
29b0f896
AM		 5884
5885 default_seg = build_modrm_byte ();
5886 }
8a2ed489 5887 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5888 {
5889 default_seg = &ds;
5890 }
40fb9820 5891 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5892 {
5893 /* For the string instructions that allow a segment override
5894 on one of their operands, the default segment is ds. */
5895 default_seg = &ds;
5896 }
5897
75178d9d
L		 5898 if (i.tm.base_opcode == 0x8d /* lea */
5899 && i.seg[0]
5900 && !quiet_warnings)
30123838 5901 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5902
5903 /* If a segment was explicitly specified, and the specified segment
5904 is not the default, use an opcode prefix to select it. If we
5905 never figured out what the default segment is, then default_seg
5906 will be zero at this point, and the specified segment prefix will
5907 always be used. */
29b0f896
AM		 5908 if ((i.seg[0]) && (i.seg[0] != default_seg))
5909 {
5910 if (!add_prefix (i.seg[0]->seg_prefix))
5911 return 0;
5912 }
5913 return 1;
5914}
5915
5916static const seg_entry *
e3bb37b5 5917build_modrm_byte (void)
29b0f896
AM		 5918{
5919 const seg_entry *default_seg = 0;
c0f3af97 5920 unsigned int source, dest;
8cd7925b 5921 int vex_3_sources;
c0f3af97
L		 5922
5923 /* The first operand of instructions with VEX prefix and 3 sources
5924 must be VEX_Imm4. */
8cd7925b 5925 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5926 if (vex_3_sources)
5927 {
91d6fa6a 5928 unsigned int nds, reg_slot;
4c2c6516 5929 expressionS *exp;
c0f3af97 5930
922d8de8 5931 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5932 && i.tm.opcode_modifier.immext)
5933 {
5934 dest = i.operands - 2;
5935 gas_assert (dest == 3);
5936 }
922d8de8 5937 else
a683cc34 5938 dest = i.operands - 1;
c0f3af97 5939 nds = dest - 1;
922d8de8 5940
a683cc34
SP		 5941 /* There are 2 kinds of instructions:
5942 1. 5 operands: 4 register operands or 3 register operands
5943 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5944 VexW0 or VexW1. The destination must be either XMM, YMM or
5945 ZMM register.
a683cc34
SP		 5946 2. 4 operands: 4 register operands or 3 register operands
5947 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5948 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5949 || (i.reg_operands == 3 && i.mem_operands == 1))
5950 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5951 && (i.tm.opcode_modifier.veximmext
5952 || (i.imm_operands == 1
5953 && i.types[0].bitfield.vec_imm4
5954 && (i.tm.opcode_modifier.vexw == VEXW0
5955 || i.tm.opcode_modifier.vexw == VEXW1)
5956 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5957 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5958 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5959
5960 if (i.imm_operands == 0)
5961 {
5962 /* When there is no immediate operand, generate an 8bit
5963 immediate operand to encode the first operand. */
5964 exp = &im_expressions[i.imm_operands++];
5965 i.op[i.operands].imms = exp;
5966 i.types[i.operands] = imm8;
5967 i.operands++;
5968 /* If VexW1 is set, the first operand is the source and
5969 the second operand is encoded in the immediate operand. */
5970 if (i.tm.opcode_modifier.vexw == VEXW1)
5971 {
5972 source = 0;
5973 reg_slot = 1;
5974 }
5975 else
5976 {
5977 source = 1;
5978 reg_slot = 0;
5979 }
5980
5981 /* FMA swaps REG and NDS. */
5982 if (i.tm.cpu_flags.bitfield.cpufma)
5983 {
5984 unsigned int tmp;
5985 tmp = reg_slot;
5986 reg_slot = nds;
5987 nds = tmp;
5988 }
5989
24981e7b
L		 5990 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5991 &regxmm)
a683cc34 5992 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 5993 &regymm)
5994 || operand_type_equal (&i.tm.operand_types[reg_slot],
5995 &regzmm));
a683cc34 5996 exp->X_op = O_constant;
4c692bc7 5997 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 5998 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
5999 }
922d8de8 6000 else
a683cc34
SP		 6001 {
6002 unsigned int imm_slot;
6003
6004 if (i.tm.opcode_modifier.vexw == VEXW0)
6005 {
6006 /* If VexW0 is set, the third operand is the source and
6007 the second operand is encoded in the immediate
6008 operand. */
6009 source = 2;
6010 reg_slot = 1;
6011 }
6012 else
6013 {
6014 /* VexW1 is set, the second operand is the source and
6015 the third operand is encoded in the immediate
6016 operand. */
6017 source = 1;
6018 reg_slot = 2;
6019 }
6020
6021 if (i.tm.opcode_modifier.immext)
6022 {
6023 /* When ImmExt is set, the immdiate byte is the last
6024 operand. */
6025 imm_slot = i.operands - 1;
6026 source--;
6027 reg_slot--;
6028 }
6029 else
6030 {
6031 imm_slot = 0;
6032
6033 /* Turn on Imm8 so that output_imm will generate it. */
6034 i.types[imm_slot].bitfield.imm8 = 1;
6035 }
6036
24981e7b
L		 6037 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6038 &regxmm)
6039 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6040 &regymm)
6041 || operand_type_equal (&i.tm.operand_types[reg_slot],
6042 &regzmm));
a683cc34 6043 i.op[imm_slot].imms->X_add_number
4c692bc7 6044 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6045 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6046 }
6047
6048 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6049 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6050 &regymm)
6051 || operand_type_equal (&i.tm.operand_types[nds],
6052 &regzmm));
dae39acc 6053 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6054 }
6055 else
6056 source = dest = 0;
29b0f896
AM		 6057
6058 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6059 implicit registers do not count. If there are 3 register
6060 operands, it must be a instruction with VexNDS. For a
6061 instruction with VexNDD, the destination register is encoded
6062 in VEX prefix. If there are 4 register operands, it must be
6063 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6064 if (i.mem_operands == 0
6065 && ((i.reg_operands == 2
2426c15f 6066 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6067 || (i.reg_operands == 3
2426c15f 6068 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6069 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6070 {
cab737b9
L		 6071 switch (i.operands)
6072 {
6073 case 2:
6074 source = 0;
6075 break;
6076 case 3:
c81128dc
L		 6077 /* When there are 3 operands, one of them may be immediate,
6078 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6079 the first operand must be shift count register (cl) or it
6080 is an instruction with VexNDS. */
9c2799c2 6081 gas_assert (i.imm_operands == 1
7ab9ffdd 6082 || (i.imm_operands == 0
2426c15f 6083 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6084 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6085 if (operand_type_check (i.types[0], imm)
6086 || i.types[0].bitfield.shiftcount)
6087 source = 1;
6088 else
6089 source = 0;
cab737b9
L		 6090 break;
6091 case 4:
368d64cc
L		 6092 /* When there are 4 operands, the first two must be 8bit
6093 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6094 one.
6095
6096 For instructions with VexNDS, if the first operand
6097 an imm8, the source operand is the 2nd one. If the last
6098 operand is imm8, the source operand is the first one. */
9c2799c2 6099 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6100 && i.types[0].bitfield.imm8
6101 && i.types[1].bitfield.imm8)
2426c15f 6102 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6103 && i.imm_operands == 1
6104 && (i.types[0].bitfield.imm8
43234a1e
L		 6105 || i.types[i.operands - 1].bitfield.imm8
6106 || i.rounding)));
9f2670f2
L		 6107 if (i.imm_operands == 2)
6108 source = 2;
6109 else
c0f3af97
L		 6110 {
6111 if (i.types[0].bitfield.imm8)
6112 source = 1;
6113 else
6114 source = 0;
6115 }
c0f3af97
L		 6116 break;
6117 case 5:
43234a1e
L		 6118 if (i.tm.opcode_modifier.evex)
6119 {
6120 /* For EVEX instructions, when there are 5 operands, the
6121 first one must be immediate operand. If the second one
6122 is immediate operand, the source operand is the 3th
6123 one. If the last one is immediate operand, the source
6124 operand is the 2nd one. */
6125 gas_assert (i.imm_operands == 2
6126 && i.tm.opcode_modifier.sae
6127 && operand_type_check (i.types[0], imm));
6128 if (operand_type_check (i.types[1], imm))
6129 source = 2;
6130 else if (operand_type_check (i.types[4], imm))
6131 source = 1;
6132 else
6133 abort ();
6134 }
cab737b9
L		 6135 break;
6136 default:
6137 abort ();
6138 }
6139
c0f3af97
L		 6140 if (!vex_3_sources)
6141 {
6142 dest = source + 1;
6143
43234a1e
L		 6144 /* RC/SAE operand could be between DEST and SRC. That happens
6145 when one operand is GPR and the other one is XMM/YMM/ZMM
6146 register. */
6147 if (i.rounding && i.rounding->operand == (int) dest)
6148 dest++;
6149
2426c15f 6150 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6151 {
43234a1e
L		 6152 /* For instructions with VexNDS, the register-only source
6153 operand must be 32/64bit integer, XMM, YMM or ZMM
6154 register. It is encoded in VEX prefix. We need to
6155 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6156
6157 i386_operand_type op;
6158 unsigned int vvvv;
6159
6160 /* Check register-only source operand when two source
6161 operands are swapped. */
6162 if (!i.tm.operand_types[source].bitfield.baseindex
6163 && i.tm.operand_types[dest].bitfield.baseindex)
6164 {
6165 vvvv = source;
6166 source = dest;
6167 }
6168 else
6169 vvvv = dest;
6170
6171 op = i.tm.operand_types[vvvv];
fa99fab2 6172 op.bitfield.regmem = 0;
c0f3af97 6173 if ((dest + 1) >= i.operands
ac4eb736
AM		 6174 || (!op.bitfield.reg32
6175 && op.bitfield.reg64
f12dc422 6176 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6177 && !operand_type_equal (&op, &regymm)
6178 && !operand_type_equal (&op, &regzmm)
6179 && !operand_type_equal (&op, &regmask)))
c0f3af97 6180 abort ();
f12dc422 6181 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6182 dest++;
6183 }
6184 }
29b0f896
AM		 6185
6186 i.rm.mode = 3;
6187 /* One of the register operands will be encoded in the i.tm.reg
6188 field, the other in the combined i.tm.mode and i.tm.regmem
6189 fields. If no form of this instruction supports a memory
6190 destination operand, then we assume the source operand may
6191 sometimes be a memory operand and so we need to store the
6192 destination in the i.rm.reg field. */
40fb9820
L		 6193 if (!i.tm.operand_types[dest].bitfield.regmem
6194 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6195 {
6196 i.rm.reg = i.op[dest].regs->reg_num;
6197 i.rm.regmem = i.op[source].regs->reg_num;
6198 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6199 i.rex |= REX_R;
43234a1e
L		 6200 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6201 i.vrex |= REX_R;
29b0f896 6202 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6203 i.rex |= REX_B;
43234a1e
L		 6204 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6205 i.vrex |= REX_B;
29b0f896
AM		 6206 }
6207 else
6208 {
6209 i.rm.reg = i.op[source].regs->reg_num;
6210 i.rm.regmem = i.op[dest].regs->reg_num;
6211 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6212 i.rex |= REX_B;
43234a1e
L		 6213 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6214 i.vrex |= REX_B;
29b0f896 6215 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6216 i.rex |= REX_R;
43234a1e
L		 6217 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6218 i.vrex |= REX_R;
29b0f896 6219 }
161a04f6 6220 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6221 {
40fb9820
L		 6222 if (!i.types[0].bitfield.control
6223 && !i.types[1].bitfield.control)
c4a530c5 6224 abort ();
161a04f6 6225 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6226 add_prefix (LOCK_PREFIX_OPCODE);
6227 }
29b0f896
AM		 6228 }
6229 else
6230 { /* If it's not 2 reg operands... */
c0f3af97
L		 6231 unsigned int mem;
6232
29b0f896
AM		 6233 if (i.mem_operands)
6234 {
6235 unsigned int fake_zero_displacement = 0;
99018f42 6236 unsigned int op;
4eed87de 6237
7ab9ffdd
L		 6238 for (op = 0; op < i.operands; op++)
6239 if (operand_type_check (i.types[op], anymem))
6240 break;
7ab9ffdd 6241 gas_assert (op < i.operands);
29b0f896 6242
6c30d220
L		 6243 if (i.tm.opcode_modifier.vecsib)
6244 {
6245 if (i.index_reg->reg_num == RegEiz
6246 || i.index_reg->reg_num == RegRiz)
6247 abort ();
6248
6249 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6250 if (!i.base_reg)
6251 {
6252 i.sib.base = NO_BASE_REGISTER;
6253 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6254 /* No Vec_Disp8 if there is no base. */
6255 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6256 i.types[op].bitfield.disp8 = 0;
6257 i.types[op].bitfield.disp16 = 0;
6258 i.types[op].bitfield.disp64 = 0;
6259 if (flag_code != CODE_64BIT)
6260 {
6261 /* Must be 32 bit */
6262 i.types[op].bitfield.disp32 = 1;
6263 i.types[op].bitfield.disp32s = 0;
6264 }
6265 else
6266 {
6267 i.types[op].bitfield.disp32 = 0;
6268 i.types[op].bitfield.disp32s = 1;
6269 }
6270 }
6271 i.sib.index = i.index_reg->reg_num;
6272 if ((i.index_reg->reg_flags & RegRex) != 0)
6273 i.rex |= REX_X;
43234a1e
L		 6274 if ((i.index_reg->reg_flags & RegVRex) != 0)
6275 i.vrex |= REX_X;
6c30d220
L		 6276 }
6277
29b0f896
AM		 6278 default_seg = &ds;
6279
6280 if (i.base_reg == 0)
6281 {
6282 i.rm.mode = 0;
6283 if (!i.disp_operands)
6c30d220
L		 6284 {
6285 fake_zero_displacement = 1;
6286 /* Instructions with VSIB byte need 32bit displacement
6287 if there is no base register. */
6288 if (i.tm.opcode_modifier.vecsib)
6289 i.types[op].bitfield.disp32 = 1;
6290 }
29b0f896
AM		 6291 if (i.index_reg == 0)
6292 {
6c30d220 6293 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6294 /* Operand is just <disp> */
20f0a1fc 6295 if (flag_code == CODE_64BIT)
29b0f896
AM		 6296 {
6297 /* 64bit mode overwrites the 32bit absolute
6298 addressing by RIP relative addressing and
6299 absolute addressing is encoded by one of the
6300 redundant SIB forms. */
6301 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6302 i.sib.base = NO_BASE_REGISTER;
6303 i.sib.index = NO_INDEX_REGISTER;
fc225355 6304 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6305 ? disp32s : disp32);
20f0a1fc 6306 }
fc225355
L		 6307 else if ((flag_code == CODE_16BIT)
6308 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6309 {
6310 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6311 i.types[op] = disp16;
20f0a1fc
NC		 6312 }
6313 else
6314 {
6315 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6316 i.types[op] = disp32;
29b0f896
AM		 6317 }
6318 }
6c30d220 6319 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6320 {
6c30d220 6321 /* !i.base_reg && i.index_reg */
db51cc60
L		 6322 if (i.index_reg->reg_num == RegEiz
6323 || i.index_reg->reg_num == RegRiz)
6324 i.sib.index = NO_INDEX_REGISTER;
6325 else
6326 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6327 i.sib.base = NO_BASE_REGISTER;
6328 i.sib.scale = i.log2_scale_factor;
6329 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6330 /* No Vec_Disp8 if there is no base. */
6331 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6332 i.types[op].bitfield.disp8 = 0;
6333 i.types[op].bitfield.disp16 = 0;
6334 i.types[op].bitfield.disp64 = 0;
29b0f896 6335 if (flag_code != CODE_64BIT)
40fb9820
L		 6336 {
6337 /* Must be 32 bit */
6338 i.types[op].bitfield.disp32 = 1;
6339 i.types[op].bitfield.disp32s = 0;
6340 }
29b0f896 6341 else
40fb9820
L		 6342 {
6343 i.types[op].bitfield.disp32 = 0;
6344 i.types[op].bitfield.disp32s = 1;
6345 }
29b0f896 6346 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6347 i.rex |= REX_X;
29b0f896
AM		 6348 }
6349 }
6350 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6351 else if (i.base_reg->reg_num == RegRip ||
6352 i.base_reg->reg_num == RegEip)
29b0f896 6353 {
6c30d220 6354 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6355 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6356 i.types[op].bitfield.disp8 = 0;
6357 i.types[op].bitfield.disp16 = 0;
6358 i.types[op].bitfield.disp32 = 0;
6359 i.types[op].bitfield.disp32s = 1;
6360 i.types[op].bitfield.disp64 = 0;
43234a1e 6361 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6362 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6363 if (! i.disp_operands)
6364 fake_zero_displacement = 1;
29b0f896 6365 }
40fb9820 6366 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6367 {
6c30d220 6368 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6369 switch (i.base_reg->reg_num)
6370 {
6371 case 3: /* (%bx) */
6372 if (i.index_reg == 0)
6373 i.rm.regmem = 7;
6374 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6375 i.rm.regmem = i.index_reg->reg_num - 6;
6376 break;
6377 case 5: /* (%bp) */
6378 default_seg = &ss;
6379 if (i.index_reg == 0)
6380 {
6381 i.rm.regmem = 6;
40fb9820 6382 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6383 {
6384 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6385 if (i.tm.operand_types[op].bitfield.vec_disp8)
6386 i.types[op].bitfield.vec_disp8 = 1;
6387 else
6388 i.types[op].bitfield.disp8 = 1;
252b5132 6389 fake_zero_displacement = 1;
29b0f896
AM		 6390 }
6391 }
6392 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6393 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6394 break;
6395 default: /* (%si) -> 4 or (%di) -> 5 */
6396 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6397 }
6398 i.rm.mode = mode_from_disp_size (i.types[op]);
6399 }
6400 else /* i.base_reg and 32/64 bit mode */
6401 {
6402 if (flag_code == CODE_64BIT
40fb9820
L		 6403 && operand_type_check (i.types[op], disp))
6404 {
6405 i386_operand_type temp;
0dfbf9d7 6406 operand_type_set (&temp, 0);
40fb9820 6407 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6408 temp.bitfield.vec_disp8
6409 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6410 i.types[op] = temp;
6411 if (i.prefix[ADDR_PREFIX] == 0)
6412 i.types[op].bitfield.disp32s = 1;
6413 else
6414 i.types[op].bitfield.disp32 = 1;
6415 }
20f0a1fc 6416
6c30d220
L		 6417 if (!i.tm.opcode_modifier.vecsib)
6418 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6419 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6420 i.rex |= REX_B;
29b0f896
AM		 6421 i.sib.base = i.base_reg->reg_num;
6422 /* x86-64 ignores REX prefix bit here to avoid decoder
6423 complications. */
848930b2
JB		 6424 if (!(i.base_reg->reg_flags & RegRex)
6425 && (i.base_reg->reg_num == EBP_REG_NUM
6426 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6427 default_seg = &ss;
848930b2 6428 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6429 {
848930b2 6430 fake_zero_displacement = 1;
43234a1e
L		 6431 if (i.tm.operand_types [op].bitfield.vec_disp8)
6432 i.types[op].bitfield.vec_disp8 = 1;
6433 else
6434 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6435 }
6436 i.sib.scale = i.log2_scale_factor;
6437 if (i.index_reg == 0)
6438 {
6c30d220 6439 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6440 /* <disp>(%esp) becomes two byte modrm with no index
6441 register. We've already stored the code for esp
6442 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6443 Any base register besides %esp will not use the
6444 extra modrm byte. */
6445 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6446 }
6c30d220 6447 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6448 {
db51cc60
L		 6449 if (i.index_reg->reg_num == RegEiz
6450 || i.index_reg->reg_num == RegRiz)
6451 i.sib.index = NO_INDEX_REGISTER;
6452 else
6453 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6454 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6455 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6456 i.rex |= REX_X;
29b0f896 6457 }
67a4f2b7
AO		 6458
6459 if (i.disp_operands
6460 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6461 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6462 i.rm.mode = 0;
6463 else
a501d77e
L		 6464 {
6465 if (!fake_zero_displacement
6466 && !i.disp_operands
6467 && i.disp_encoding)
6468 {
6469 fake_zero_displacement = 1;
6470 if (i.disp_encoding == disp_encoding_8bit)
6471 i.types[op].bitfield.disp8 = 1;
6472 else
6473 i.types[op].bitfield.disp32 = 1;
6474 }
6475 i.rm.mode = mode_from_disp_size (i.types[op]);
6476 }
29b0f896 6477 }
252b5132 6478
29b0f896
AM		 6479 if (fake_zero_displacement)
6480 {
6481 /* Fakes a zero displacement assuming that i.types[op]
6482 holds the correct displacement size. */
6483 expressionS *exp;
6484
9c2799c2 6485 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6486 exp = &disp_expressions[i.disp_operands++];
6487 i.op[op].disps = exp;
6488 exp->X_op = O_constant;
6489 exp->X_add_number = 0;
6490 exp->X_add_symbol = (symbolS *) 0;
6491 exp->X_op_symbol = (symbolS *) 0;
6492 }
c0f3af97
L		 6493
6494 mem = op;
29b0f896 6495 }
c0f3af97
L		 6496 else
6497 mem = ~0;
252b5132 6498
8c43a48b 6499 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6500 {
6501 if (operand_type_check (i.types[0], imm))
6502 i.vex.register_specifier = NULL;
6503 else
6504 {
6505 /* VEX.vvvv encodes one of the sources when the first
6506 operand is not an immediate. */
1ef99a7b 6507 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6508 i.vex.register_specifier = i.op[0].regs;
6509 else
6510 i.vex.register_specifier = i.op[1].regs;
6511 }
6512
6513 /* Destination is a XMM register encoded in the ModRM.reg
6514 and VEX.R bit. */
6515 i.rm.reg = i.op[2].regs->reg_num;
6516 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6517 i.rex |= REX_R;
6518
6519 /* ModRM.rm and VEX.B encodes the other source. */
6520 if (!i.mem_operands)
6521 {
6522 i.rm.mode = 3;
6523
1ef99a7b 6524 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6525 i.rm.regmem = i.op[1].regs->reg_num;
6526 else
6527 i.rm.regmem = i.op[0].regs->reg_num;
6528
6529 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6530 i.rex |= REX_B;
6531 }
6532 }
2426c15f 6533 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6534 {
6535 i.vex.register_specifier = i.op[2].regs;
6536 if (!i.mem_operands)
6537 {
6538 i.rm.mode = 3;
6539 i.rm.regmem = i.op[1].regs->reg_num;
6540 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6541 i.rex |= REX_B;
6542 }
6543 }
29b0f896
AM		 6544 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6545 (if any) based on i.tm.extension_opcode. Again, we must be
6546 careful to make sure that segment/control/debug/test/MMX
6547 registers are coded into the i.rm.reg field. */
f88c9eb0 6548 else if (i.reg_operands)
29b0f896 6549 {
99018f42 6550 unsigned int op;
7ab9ffdd
L		 6551 unsigned int vex_reg = ~0;
6552
6553 for (op = 0; op < i.operands; op++)
6554 if (i.types[op].bitfield.reg8
6555 || i.types[op].bitfield.reg16
6556 || i.types[op].bitfield.reg32
6557 || i.types[op].bitfield.reg64
6558 || i.types[op].bitfield.regmmx
6559 || i.types[op].bitfield.regxmm
6560 || i.types[op].bitfield.regymm
7e8b059b 6561 || i.types[op].bitfield.regbnd
43234a1e
L		 6562 || i.types[op].bitfield.regzmm
6563 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6564 || i.types[op].bitfield.sreg2
6565 || i.types[op].bitfield.sreg3
6566 || i.types[op].bitfield.control
6567 || i.types[op].bitfield.debug
6568 || i.types[op].bitfield.test)
6569 break;
c0209578 6570
7ab9ffdd
L		 6571 if (vex_3_sources)
6572 op = dest;
2426c15f 6573 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6574 {
6575 /* For instructions with VexNDS, the register-only
6576 source operand is encoded in VEX prefix. */
6577 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6578
7ab9ffdd 6579 if (op > mem)
c0f3af97 6580 {
7ab9ffdd
L		 6581 vex_reg = op++;
6582 gas_assert (op < i.operands);
c0f3af97
L		 6583 }
6584 else
c0f3af97 6585 {
f12dc422
L		 6586 /* Check register-only source operand when two source
6587 operands are swapped. */
6588 if (!i.tm.operand_types[op].bitfield.baseindex
6589 && i.tm.operand_types[op + 1].bitfield.baseindex)
6590 {
6591 vex_reg = op;
6592 op += 2;
6593 gas_assert (mem == (vex_reg + 1)
6594 && op < i.operands);
6595 }
6596 else
6597 {
6598 vex_reg = op + 1;
6599 gas_assert (vex_reg < i.operands);
6600 }
c0f3af97 6601 }
7ab9ffdd 6602 }
2426c15f 6603 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6604 {
f12dc422 6605 /* For instructions with VexNDD, the register destination
7ab9ffdd 6606 is encoded in VEX prefix. */
f12dc422
L		 6607 if (i.mem_operands == 0)
6608 {
6609 /* There is no memory operand. */
6610 gas_assert ((op + 2) == i.operands);
6611 vex_reg = op + 1;
6612 }
6613 else
8d63c93e 6614 {
f12dc422
L		 6615 /* There are only 2 operands. */
6616 gas_assert (op < 2 && i.operands == 2);
6617 vex_reg = 1;
6618 }
7ab9ffdd
L		 6619 }
6620 else
6621 gas_assert (op < i.operands);
99018f42 6622
7ab9ffdd
L		 6623 if (vex_reg != (unsigned int) ~0)
6624 {
f12dc422 6625 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6626
f12dc422
L		 6627 if (type->bitfield.reg32 != 1
6628 && type->bitfield.reg64 != 1
6629 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6630 && !operand_type_equal (type, &regymm)
6631 && !operand_type_equal (type, &regzmm)
6632 && !operand_type_equal (type, &regmask))
7ab9ffdd 6633 abort ();
f88c9eb0 6634
7ab9ffdd
L		 6635 i.vex.register_specifier = i.op[vex_reg].regs;
6636 }
6637
1b9f0c97
L		 6638 /* Don't set OP operand twice. */
6639 if (vex_reg != op)
7ab9ffdd 6640 {
1b9f0c97
L		 6641 /* If there is an extension opcode to put here, the
6642 register number must be put into the regmem field. */
6643 if (i.tm.extension_opcode != None)
6644 {
6645 i.rm.regmem = i.op[op].regs->reg_num;
6646 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6647 i.rex |= REX_B;
43234a1e
L		 6648 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6649 i.vrex |= REX_B;
1b9f0c97
L		 6650 }
6651 else
6652 {
6653 i.rm.reg = i.op[op].regs->reg_num;
6654 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6655 i.rex |= REX_R;
43234a1e
L		 6656 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6657 i.vrex |= REX_R;
1b9f0c97 6658 }
7ab9ffdd 6659 }
252b5132 6660
29b0f896
AM		 6661 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6662 must set it to 3 to indicate this is a register operand
6663 in the regmem field. */
6664 if (!i.mem_operands)
6665 i.rm.mode = 3;
6666 }
252b5132 6667
29b0f896 6668 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6669 if (i.tm.extension_opcode != None)
29b0f896
AM		 6670 i.rm.reg = i.tm.extension_opcode;
6671 }
6672 return default_seg;
6673}
252b5132 6674
29b0f896 6675static void
e3bb37b5 6676output_branch (void)
29b0f896
AM		 6677{
6678 char *p;
f8a5c266 6679 int size;
29b0f896
AM		 6680 int code16;
6681 int prefix;
6682 relax_substateT subtype;
6683 symbolS *sym;
6684 offsetT off;
6685
f8a5c266 6686 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6687 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6688
6689 prefix = 0;
6690 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6691 {
29b0f896
AM		 6692 prefix = 1;
6693 i.prefixes -= 1;
6694 code16 ^= CODE16;
252b5132 6695 }
29b0f896
AM		 6696 /* Pentium4 branch hints. */
6697 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6698 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6699 {
29b0f896
AM		 6700 prefix++;
6701 i.prefixes--;
6702 }
6703 if (i.prefix[REX_PREFIX] != 0)
6704 {
6705 prefix++;
6706 i.prefixes--;
2f66722d
AM		 6707 }
6708
7e8b059b
L		 6709 /* BND prefixed jump. */
6710 if (i.prefix[BND_PREFIX] != 0)
6711 {
6712 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6713 i.prefixes -= 1;
6714 }
6715
29b0f896
AM		 6716 if (i.prefixes != 0 && !intel_syntax)
6717 as_warn (_("skipping prefixes on this instruction"));
6718
6719 /* It's always a symbol; End frag & setup for relax.
6720 Make sure there is enough room in this frag for the largest
6721 instruction we may generate in md_convert_frag. This is 2
6722 bytes for the opcode and room for the prefix and largest
6723 displacement. */
6724 frag_grow (prefix + 2 + 4);
6725 /* Prefix and 1 opcode byte go in fr_fix. */
6726 p = frag_more (prefix + 1);
6727 if (i.prefix[DATA_PREFIX] != 0)
6728 *p++ = DATA_PREFIX_OPCODE;
6729 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6730 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6731 *p++ = i.prefix[SEG_PREFIX];
6732 if (i.prefix[REX_PREFIX] != 0)
6733 *p++ = i.prefix[REX_PREFIX];
6734 *p = i.tm.base_opcode;
6735
6736 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6737 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6738 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6739 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6740 else
f8a5c266 6741 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6742 subtype |= code16;
3e73aa7c 6743
29b0f896
AM		 6744 sym = i.op[0].disps->X_add_symbol;
6745 off = i.op[0].disps->X_add_number;
3e73aa7c 6746
29b0f896
AM		 6747 if (i.op[0].disps->X_op != O_constant
6748 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6749 {
29b0f896
AM		 6750 /* Handle complex expressions. */
6751 sym = make_expr_symbol (i.op[0].disps);
6752 off = 0;
6753 }
3e73aa7c 6754
29b0f896
AM		 6755 /* 1 possible extra opcode + 4 byte displacement go in var part.
6756 Pass reloc in fr_var. */
c3320543
L		 6757 frag_var (rs_machine_dependent, 5,
6758 ((!object_64bit
6759 || i.reloc[0] != NO_RELOC
6760 || (i.bnd_prefix == NULL && !add_bnd_prefix))
6761 ? i.reloc[0]
6762 : BFD_RELOC_X86_64_PC32_BND),
6763 subtype, sym, off, p);
29b0f896 6764}
3e73aa7c 6765
29b0f896 6766static void
e3bb37b5 6767output_jump (void)
29b0f896
AM		 6768{
6769 char *p;
6770 int size;
3e02c1cc 6771 fixS *fixP;
29b0f896 6772
40fb9820 6773 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6774 {
6775 /* This is a loop or jecxz type instruction. */
6776 size = 1;
6777 if (i.prefix[ADDR_PREFIX] != 0)
6778 {
6779 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6780 i.prefixes -= 1;
6781 }
6782 /* Pentium4 branch hints. */
6783 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6784 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6785 {
6786 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6787 i.prefixes--;
3e73aa7c
JH		 6788 }
6789 }
29b0f896
AM		 6790 else
6791 {
6792 int code16;
3e73aa7c 6793
29b0f896
AM		 6794 code16 = 0;
6795 if (flag_code == CODE_16BIT)
6796 code16 = CODE16;
3e73aa7c 6797
29b0f896
AM		 6798 if (i.prefix[DATA_PREFIX] != 0)
6799 {
6800 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6801 i.prefixes -= 1;
6802 code16 ^= CODE16;
6803 }
252b5132 6804
29b0f896
AM		 6805 size = 4;
6806 if (code16)
6807 size = 2;
6808 }
9fcc94b6 6809
29b0f896
AM		 6810 if (i.prefix[REX_PREFIX] != 0)
6811 {
6812 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6813 i.prefixes -= 1;
6814 }
252b5132 6815
7e8b059b
L		 6816 /* BND prefixed jump. */
6817 if (i.prefix[BND_PREFIX] != 0)
6818 {
6819 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6820 i.prefixes -= 1;
6821 }
6822
29b0f896
AM		 6823 if (i.prefixes != 0 && !intel_syntax)
6824 as_warn (_("skipping prefixes on this instruction"));
e0890092 6825
42164a71
L		 6826 p = frag_more (i.tm.opcode_length + size);
6827 switch (i.tm.opcode_length)
6828 {
6829 case 2:
6830 *p++ = i.tm.base_opcode >> 8;
6831 case 1:
6832 *p++ = i.tm.base_opcode;
6833 break;
6834 default:
6835 abort ();
6836 }
e0890092 6837
3e02c1cc 6838 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543
L		 6839 i.op[0].disps, 1, reloc (size, 1, 1,
6840 (i.bnd_prefix != NULL
6841 || add_bnd_prefix),
6842 i.reloc[0]));
3e02c1cc
AM		 6843
6844 /* All jumps handled here are signed, but don't use a signed limit
6845 check for 32 and 16 bit jumps as we want to allow wrap around at
6846 4G and 64k respectively. */
6847 if (size == 1)
6848 fixP->fx_signed = 1;
29b0f896 6849}
e0890092 6850
29b0f896 6851static void
e3bb37b5 6852output_interseg_jump (void)
29b0f896
AM		 6853{
6854 char *p;
6855 int size;
6856 int prefix;
6857 int code16;
252b5132 6858
29b0f896
AM		 6859 code16 = 0;
6860 if (flag_code == CODE_16BIT)
6861 code16 = CODE16;
a217f122 6862
29b0f896
AM		 6863 prefix = 0;
6864 if (i.prefix[DATA_PREFIX] != 0)
6865 {
6866 prefix = 1;
6867 i.prefixes -= 1;
6868 code16 ^= CODE16;
6869 }
6870 if (i.prefix[REX_PREFIX] != 0)
6871 {
6872 prefix++;
6873 i.prefixes -= 1;
6874 }
252b5132 6875
29b0f896
AM		 6876 size = 4;
6877 if (code16)
6878 size = 2;
252b5132 6879
29b0f896
AM		 6880 if (i.prefixes != 0 && !intel_syntax)
6881 as_warn (_("skipping prefixes on this instruction"));
252b5132 6882
29b0f896
AM		 6883 /* 1 opcode; 2 segment; offset */
6884 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6885
29b0f896
AM		 6886 if (i.prefix[DATA_PREFIX] != 0)
6887 *p++ = DATA_PREFIX_OPCODE;
252b5132 6888
29b0f896
AM		 6889 if (i.prefix[REX_PREFIX] != 0)
6890 *p++ = i.prefix[REX_PREFIX];
252b5132 6891
29b0f896
AM		 6892 *p++ = i.tm.base_opcode;
6893 if (i.op[1].imms->X_op == O_constant)
6894 {
6895 offsetT n = i.op[1].imms->X_add_number;
252b5132 6896
29b0f896
AM		 6897 if (size == 2
6898 && !fits_in_unsigned_word (n)
6899 && !fits_in_signed_word (n))
6900 {
6901 as_bad (_("16-bit jump out of range"));
6902 return;
6903 }
6904 md_number_to_chars (p, n, size);
6905 }
6906 else
6907 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543 6908 i.op[1].imms, 0, reloc (size, 0, 0, 0, i.reloc[1]));
29b0f896
AM		 6909 if (i.op[0].imms->X_op != O_constant)
6910 as_bad (_("can't handle non absolute segment in `%s'"),
6911 i.tm.name);
6912 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6913}
a217f122 6914
29b0f896 6915static void
e3bb37b5 6916output_insn (void)
29b0f896 6917{
2bbd9c25
JJ		 6918 fragS *insn_start_frag;
6919 offsetT insn_start_off;
6920
29b0f896
AM		 6921 /* Tie dwarf2 debug info to the address at the start of the insn.
6922 We can't do this after the insn has been output as the current
6923 frag may have been closed off. eg. by frag_var. */
6924 dwarf2_emit_insn (0);
6925
2bbd9c25
JJ		 6926 insn_start_frag = frag_now;
6927 insn_start_off = frag_now_fix ();
6928
29b0f896 6929 /* Output jumps. */
40fb9820 6930 if (i.tm.opcode_modifier.jump)
29b0f896 6931 output_branch ();
40fb9820
L		 6932 else if (i.tm.opcode_modifier.jumpbyte
6933 || i.tm.opcode_modifier.jumpdword)
29b0f896 6934 output_jump ();
40fb9820 6935 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6936 output_interseg_jump ();
6937 else
6938 {
6939 /* Output normal instructions here. */
6940 char *p;
6941 unsigned char *q;
47465058 6942 unsigned int j;
331d2d0d 6943 unsigned int prefix;
4dffcebc 6944
d022bddd
IT		 6945 /* Some processors fail on LOCK prefix. This options makes
6946 assembler ignore LOCK prefix and serves as a workaround. */
6947 if (omit_lock_prefix)
6948 {
6949 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6950 return;
6951 i.prefix[LOCK_PREFIX] = 0;
6952 }
6953
43234a1e
L		 6954 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6955 don't need the explicit prefix. */
6956 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6957 {
c0f3af97 6958 switch (i.tm.opcode_length)
bc4bd9ab 6959 {
c0f3af97
L		 6960 case 3:
6961 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6962 {
c0f3af97
L		 6963 prefix = (i.tm.base_opcode >> 24) & 0xff;
6964 goto check_prefix;
6965 }
6966 break;
6967 case 2:
6968 if ((i.tm.base_opcode & 0xff0000) != 0)
6969 {
6970 prefix = (i.tm.base_opcode >> 16) & 0xff;
6971 if (i.tm.cpu_flags.bitfield.cpupadlock)
6972 {
4dffcebc 6973check_prefix:
c0f3af97 6974 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6975 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6976 != REPE_PREFIX_OPCODE))
6977 add_prefix (prefix);
6978 }
6979 else
4dffcebc
L		 6980 add_prefix (prefix);
6981 }
c0f3af97
L		 6982 break;
6983 case 1:
6984 break;
6985 default:
6986 abort ();
bc4bd9ab 6987 }
c0f3af97
L		 6988
6989 /* The prefix bytes. */
6990 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6991 if (*q)
6992 FRAG_APPEND_1_CHAR (*q);
0f10071e 6993 }
ae5c1c7b 6994 else
c0f3af97
L		 6995 {
6996 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6997 if (*q)
6998 switch (j)
6999 {
7000 case REX_PREFIX:
7001 /* REX byte is encoded in VEX prefix. */
7002 break;
7003 case SEG_PREFIX:
7004 case ADDR_PREFIX:
7005 FRAG_APPEND_1_CHAR (*q);
7006 break;
7007 default:
7008 /* There should be no other prefixes for instructions
7009 with VEX prefix. */
7010 abort ();
7011 }
7012
43234a1e
L		 7013 /* For EVEX instructions i.vrex should become 0 after
7014 build_evex_prefix. For VEX instructions upper 16 registers
7015 aren't available, so VREX should be 0. */
7016 if (i.vrex)
7017 abort ();
c0f3af97
L		 7018 /* Now the VEX prefix. */
7019 p = frag_more (i.vex.length);
7020 for (j = 0; j < i.vex.length; j++)
7021 p[j] = i.vex.bytes[j];
7022 }
252b5132 7023
29b0f896 7024 /* Now the opcode; be careful about word order here! */
4dffcebc 7025 if (i.tm.opcode_length == 1)
29b0f896
AM		 7026 {
7027 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7028 }
7029 else
7030 {
4dffcebc 7031 switch (i.tm.opcode_length)
331d2d0d 7032 {
43234a1e
L		 7033 case 4:
7034 p = frag_more (4);
7035 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7036 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7037 break;
4dffcebc 7038 case 3:
331d2d0d
L		 7039 p = frag_more (3);
7040 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7041 break;
7042 case 2:
7043 p = frag_more (2);
7044 break;
7045 default:
7046 abort ();
7047 break;
331d2d0d 7048 }
0f10071e 7049
29b0f896
AM		 7050 /* Put out high byte first: can't use md_number_to_chars! */
7051 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7052 *p = i.tm.base_opcode & 0xff;
7053 }
3e73aa7c 7054
29b0f896 7055 /* Now the modrm byte and sib byte (if present). */
40fb9820 7056 if (i.tm.opcode_modifier.modrm)
29b0f896 7057 {
4a3523fa
L		 7058 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7059 | i.rm.reg << 3
7060 | i.rm.mode << 6));
29b0f896
AM		 7061 /* If i.rm.regmem == ESP (4)
7062 && i.rm.mode != (Register mode)
7063 && not 16 bit
7064 ==> need second modrm byte. */
7065 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7066 && i.rm.mode != 3
40fb9820 7067 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7068 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7069 | i.sib.index << 3
7070 | i.sib.scale << 6));
29b0f896 7071 }
3e73aa7c 7072
29b0f896 7073 if (i.disp_operands)
2bbd9c25 7074 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7075
29b0f896 7076 if (i.imm_operands)
2bbd9c25 7077 output_imm (insn_start_frag, insn_start_off);
29b0f896 7078 }
252b5132 7079
29b0f896
AM		 7080#ifdef DEBUG386
7081 if (flag_debug)
7082 {
7b81dfbb 7083 pi ("" /*line*/, &i);
29b0f896
AM		 7084 }
7085#endif /* DEBUG386 */
7086}
252b5132 7087
e205caa7
L		 7088/* Return the size of the displacement operand N. */
7089
7090static int
7091disp_size (unsigned int n)
7092{
7093 int size = 4;
43234a1e
L		 7094
7095 /* Vec_Disp8 has to be 8bit. */
7096 if (i.types[n].bitfield.vec_disp8)
7097 size = 1;
7098 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7099 size = 8;
7100 else if (i.types[n].bitfield.disp8)
7101 size = 1;
7102 else if (i.types[n].bitfield.disp16)
7103 size = 2;
e205caa7
L		 7104 return size;
7105}
7106
7107/* Return the size of the immediate operand N. */
7108
7109static int
7110imm_size (unsigned int n)
7111{
7112 int size = 4;
40fb9820
L		 7113 if (i.types[n].bitfield.imm64)
7114 size = 8;
7115 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7116 size = 1;
7117 else if (i.types[n].bitfield.imm16)
7118 size = 2;
e205caa7
L		 7119 return size;
7120}
7121
29b0f896 7122static void
64e74474 7123output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7124{
7125 char *p;
7126 unsigned int n;
252b5132 7127
29b0f896
AM		 7128 for (n = 0; n < i.operands; n++)
7129 {
43234a1e
L		 7130 if (i.types[n].bitfield.vec_disp8
7131 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7132 {
7133 if (i.op[n].disps->X_op == O_constant)
7134 {
e205caa7 7135 int size = disp_size (n);
43234a1e 7136 offsetT val = i.op[n].disps->X_add_number;
252b5132 7137
43234a1e
L		 7138 if (i.types[n].bitfield.vec_disp8)
7139 val >>= i.memshift;
7140 val = offset_in_range (val, size);
29b0f896
AM		 7141 p = frag_more (size);
7142 md_number_to_chars (p, val, size);
7143 }
7144 else
7145 {
f86103b7 7146 enum bfd_reloc_code_real reloc_type;
e205caa7 7147 int size = disp_size (n);
40fb9820 7148 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7149 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7150
e205caa7 7151 /* We can't have 8 bit displacement here. */
9c2799c2 7152 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7153
29b0f896
AM		 7154 /* The PC relative address is computed relative
7155 to the instruction boundary, so in case immediate
7156 fields follows, we need to adjust the value. */
7157 if (pcrel && i.imm_operands)
7158 {
29b0f896 7159 unsigned int n1;
e205caa7 7160 int sz = 0;
252b5132 7161
29b0f896 7162 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7163 if (operand_type_check (i.types[n1], imm))
252b5132 7164 {
e205caa7
L		 7165 /* Only one immediate is allowed for PC
7166 relative address. */
9c2799c2 7167 gas_assert (sz == 0);
e205caa7
L		 7168 sz = imm_size (n1);
7169 i.op[n].disps->X_add_number -= sz;
252b5132 7170 }
29b0f896 7171 /* We should find the immediate. */
9c2799c2 7172 gas_assert (sz != 0);
29b0f896 7173 }
520dc8e8 7174
29b0f896 7175 p = frag_more (size);
c3320543
L		 7176 reloc_type = reloc (size, pcrel, sign,
7177 (i.bnd_prefix != NULL
7178 || add_bnd_prefix),
7179 i.reloc[n]);
d6ab8113 7180 if (GOT_symbol
2bbd9c25 7181 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7182 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7183 || reloc_type == BFD_RELOC_X86_64_32S
7184 || (reloc_type == BFD_RELOC_64
7185 && object_64bit))
d6ab8113
JB		 7186 && (i.op[n].disps->X_op == O_symbol
7187 || (i.op[n].disps->X_op == O_add
7188 && ((symbol_get_value_expression
7189 (i.op[n].disps->X_op_symbol)->X_op)
7190 == O_subtract))))
7191 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7192 {
7193 offsetT add;
7194
7195 if (insn_start_frag == frag_now)
7196 add = (p - frag_now->fr_literal) - insn_start_off;
7197 else
7198 {
7199 fragS *fr;
7200
7201 add = insn_start_frag->fr_fix - insn_start_off;
7202 for (fr = insn_start_frag->fr_next;
7203 fr && fr != frag_now; fr = fr->fr_next)
7204 add += fr->fr_fix;
7205 add += p - frag_now->fr_literal;
7206 }
7207
4fa24527 7208 if (!object_64bit)
7b81dfbb
AJ		 7209 {
7210 reloc_type = BFD_RELOC_386_GOTPC;
7211 i.op[n].imms->X_add_number += add;
7212 }
7213 else if (reloc_type == BFD_RELOC_64)
7214 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7215 else
7b81dfbb
AJ		 7216 /* Don't do the adjustment for x86-64, as there
7217 the pcrel addressing is relative to the _next_
7218 insn, and that is taken care of in other code. */
d6ab8113 7219 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7220 }
062cd5e7 7221 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7222 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7223 }
7224 }
7225 }
7226}
252b5132 7227
29b0f896 7228static void
64e74474 7229output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7230{
7231 char *p;
7232 unsigned int n;
252b5132 7233
29b0f896
AM		 7234 for (n = 0; n < i.operands; n++)
7235 {
43234a1e
L		 7236 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7237 if (i.rounding && (int) n == i.rounding->operand)
7238 continue;
7239
40fb9820 7240 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7241 {
7242 if (i.op[n].imms->X_op == O_constant)
7243 {
e205caa7 7244 int size = imm_size (n);
29b0f896 7245 offsetT val;
b4cac588 7246
29b0f896
AM		 7247 val = offset_in_range (i.op[n].imms->X_add_number,
7248 size);
7249 p = frag_more (size);
7250 md_number_to_chars (p, val, size);
7251 }
7252 else
7253 {
7254 /* Not absolute_section.
7255 Need a 32-bit fixup (don't support 8bit
7256 non-absolute imms). Try to support other
7257 sizes ... */
f86103b7 7258 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7259 int size = imm_size (n);
7260 int sign;
29b0f896 7261
40fb9820 7262 if (i.types[n].bitfield.imm32s
a7d61044 7263 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7264 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7265 sign = 1;
e205caa7
L		 7266 else
7267 sign = 0;
520dc8e8 7268
29b0f896 7269 p = frag_more (size);
c3320543 7270 reloc_type = reloc (size, 0, sign, 0, i.reloc[n]);
f86103b7 7271
2bbd9c25
JJ		 7272 /* This is tough to explain. We end up with this one if we
7273 * have operands that look like
7274 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7275 * obtain the absolute address of the GOT, and it is strongly
7276 * preferable from a performance point of view to avoid using
7277 * a runtime relocation for this. The actual sequence of
7278 * instructions often look something like:
7279 *
7280 * call .L66
7281 * .L66:
7282 * popl %ebx
7283 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7284 *
7285 * The call and pop essentially return the absolute address
7286 * of the label .L66 and store it in %ebx. The linker itself
7287 * will ultimately change the first operand of the addl so
7288 * that %ebx points to the GOT, but to keep things simple, the
7289 * .o file must have this operand set so that it generates not
7290 * the absolute address of .L66, but the absolute address of
7291 * itself. This allows the linker itself simply treat a GOTPC
7292 * relocation as asking for a pcrel offset to the GOT to be
7293 * added in, and the addend of the relocation is stored in the
7294 * operand field for the instruction itself.
7295 *
7296 * Our job here is to fix the operand so that it would add
7297 * the correct offset so that %ebx would point to itself. The
7298 * thing that is tricky is that .-.L66 will point to the
7299 * beginning of the instruction, so we need to further modify
7300 * the operand so that it will point to itself. There are
7301 * other cases where you have something like:
7302 *
7303 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7304 *
7305 * and here no correction would be required. Internally in
7306 * the assembler we treat operands of this form as not being
7307 * pcrel since the '.' is explicitly mentioned, and I wonder
7308 * whether it would simplify matters to do it this way. Who
7309 * knows. In earlier versions of the PIC patches, the
7310 * pcrel_adjust field was used to store the correction, but
7311 * since the expression is not pcrel, I felt it would be
7312 * confusing to do it this way. */
7313
d6ab8113 7314 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7315 || reloc_type == BFD_RELOC_X86_64_32S
7316 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7317 && GOT_symbol
7318 && GOT_symbol == i.op[n].imms->X_add_symbol
7319 && (i.op[n].imms->X_op == O_symbol
7320 || (i.op[n].imms->X_op == O_add
7321 && ((symbol_get_value_expression
7322 (i.op[n].imms->X_op_symbol)->X_op)
7323 == O_subtract))))
7324 {
2bbd9c25
JJ		 7325 offsetT add;
7326
7327 if (insn_start_frag == frag_now)
7328 add = (p - frag_now->fr_literal) - insn_start_off;
7329 else
7330 {
7331 fragS *fr;
7332
7333 add = insn_start_frag->fr_fix - insn_start_off;
7334 for (fr = insn_start_frag->fr_next;
7335 fr && fr != frag_now; fr = fr->fr_next)
7336 add += fr->fr_fix;
7337 add += p - frag_now->fr_literal;
7338 }
7339
4fa24527 7340 if (!object_64bit)
d6ab8113 7341 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7342 else if (size == 4)
d6ab8113 7343 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7344 else if (size == 8)
7345 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7346 i.op[n].imms->X_add_number += add;
29b0f896 7347 }
29b0f896
AM		 7348 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7349 i.op[n].imms, 0, reloc_type);
7350 }
7351 }
7352 }
252b5132
RH		 7353}
7354\f
d182319b
JB		 7355/* x86_cons_fix_new is called via the expression parsing code when a
7356 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7357static int cons_sign = -1;
7358
7359void
e3bb37b5 7360x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7361 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7362{
62ebcb5c 7363 r = reloc (len, 0, cons_sign, 0, r);
d182319b
JB		 7364
7365#ifdef TE_PE
7366 if (exp->X_op == O_secrel)
7367 {
7368 exp->X_op = O_symbol;
7369 r = BFD_RELOC_32_SECREL;
7370 }
7371#endif
7372
7373 fix_new_exp (frag, off, len, exp, 0, r);
7374}
7375
357d1bd8
L		 7376/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7377 purpose of the `.dc.a' internal pseudo-op. */
7378
7379int
7380x86_address_bytes (void)
7381{
7382 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7383 return 4;
7384 return stdoutput->arch_info->bits_per_address / 8;
7385}
7386
d382c579
TG		 7387#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7388 || defined (LEX_AT)
c06ec724 7389# define lex_got(reloc, adjust, types, bnd_prefix) NULL
718ddfc0 7390#else
f3c180ae
AM		 7391/* Parse operands of the form
7392 <symbol>@GOTOFF+<nnn>
7393 and similar .plt or .got references.
7394
7395 If we find one, set up the correct relocation in RELOC and copy the
7396 input string, minus the `@GOTOFF' into a malloc'd buffer for
7397 parsing by the calling routine. Return this buffer, and if ADJUST
7398 is non-null set it to the length of the string we removed from the
7399 input line. Otherwise return NULL. */
7400static char *
91d6fa6a 7401lex_got (enum bfd_reloc_code_real *rel,
64e74474 7402 int *adjust,
c3320543
L		 7403 i386_operand_type *types,
7404 int bnd_prefix)
f3c180ae 7405{
7b81dfbb
AJ		 7406 /* Some of the relocations depend on the size of what field is to
7407 be relocated. But in our callers i386_immediate and i386_displacement
7408 we don't yet know the operand size (this will be set by insn
7409 matching). Hence we record the word32 relocation here,
7410 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7411 static const struct {
7412 const char *str;
cff8d58a 7413 int len;
4fa24527 7414 const enum bfd_reloc_code_real rel[2];
40fb9820 7415 const i386_operand_type types64;
f3c180ae 7416 } gotrel[] = {
8ce3d284 7417#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7418 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7419 BFD_RELOC_SIZE32 },
7420 OPERAND_TYPE_IMM32_64 },
8ce3d284 7421#endif
cff8d58a
L		 7422 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7423 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7424 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7425 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7426 BFD_RELOC_X86_64_PLT32 },
40fb9820 7427 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7428 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7429 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7430 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7431 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7432 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7433 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7434 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7435 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7436 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7437 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7438 BFD_RELOC_X86_64_TLSGD },
40fb9820 7439 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7440 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7441 _dummy_first_bfd_reloc_code_real },
40fb9820 7442 OPERAND_TYPE_NONE },
cff8d58a
L		 7443 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7444 BFD_RELOC_X86_64_TLSLD },
40fb9820 7445 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7446 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7447 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7448 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7449 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7450 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7451 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7452 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7453 _dummy_first_bfd_reloc_code_real },
40fb9820 7454 OPERAND_TYPE_NONE },
cff8d58a
L		 7455 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7456 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7457 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7458 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7459 _dummy_first_bfd_reloc_code_real },
40fb9820 7460 OPERAND_TYPE_NONE },
cff8d58a
L		 7461 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7462 _dummy_first_bfd_reloc_code_real },
40fb9820 7463 OPERAND_TYPE_NONE },
cff8d58a
L		 7464 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7465 BFD_RELOC_X86_64_GOT32 },
40fb9820 7466 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7467 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7468 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7469 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7470 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7471 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7472 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7473 };
7474 char *cp;
7475 unsigned int j;
7476
d382c579 7477#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7478 if (!IS_ELF)
7479 return NULL;
d382c579 7480#endif
718ddfc0 7481
f3c180ae 7482 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7483 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7484 return NULL;
7485
47465058 7486 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7487 {
cff8d58a 7488 int len = gotrel[j].len;
28f81592 7489 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7490 {
4fa24527 7491 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7492 {
28f81592
AM		 7493 int first, second;
7494 char *tmpbuf, *past_reloc;
f3c180ae 7495
91d6fa6a 7496 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7497
3956db08
JB		 7498 if (types)
7499 {
7500 if (flag_code != CODE_64BIT)
40fb9820
L		 7501 {
7502 types->bitfield.imm32 = 1;
7503 types->bitfield.disp32 = 1;
7504 }
3956db08
JB		 7505 else
7506 *types = gotrel[j].types64;
7507 }
7508
8fd4256d 7509 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7510 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7511
28f81592 7512 /* The length of the first part of our input line. */
f3c180ae 7513 first = cp - input_line_pointer;
28f81592
AM		 7514
7515 /* The second part goes from after the reloc token until
67c11a9b 7516 (and including) an end_of_line char or comma. */
28f81592 7517 past_reloc = cp + 1 + len;
67c11a9b
AM		 7518 cp = past_reloc;
7519 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7520 ++cp;
7521 second = cp + 1 - past_reloc;
28f81592
AM		 7522
7523 /* Allocate and copy string. The trailing NUL shouldn't
7524 be necessary, but be safe. */
1e9cc1c2 7525 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7526 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7527 if (second != 0 && *past_reloc != ' ')
7528 /* Replace the relocation token with ' ', so that
7529 errors like foo@GOTOFF1 will be detected. */
7530 tmpbuf[first++] = ' ';
af89796a
L		 7531 else
7532 /* Increment length by 1 if the relocation token is
7533 removed. */
7534 len++;
7535 if (adjust)
7536 *adjust = len;
0787a12d
AM		 7537 memcpy (tmpbuf + first, past_reloc, second);
7538 tmpbuf[first + second] = '\0';
c3320543
L		 7539 if (bnd_prefix && *rel == BFD_RELOC_X86_64_PLT32)
7540 *rel = BFD_RELOC_X86_64_PLT32_BND;
f3c180ae
AM		 7541 return tmpbuf;
7542 }
7543
4fa24527
JB		 7544 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7545 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7546 return NULL;
7547 }
7548 }
7549
7550 /* Might be a symbol version string. Don't as_bad here. */
7551 return NULL;
7552}
4e4f7c87 7553#endif
f3c180ae 7554
a988325c
NC		 7555#ifdef TE_PE
7556#ifdef lex_got
7557#undef lex_got
7558#endif
7559/* Parse operands of the form
7560 <symbol>@SECREL32+<nnn>
7561
7562 If we find one, set up the correct relocation in RELOC and copy the
7563 input string, minus the `@SECREL32' into a malloc'd buffer for
7564 parsing by the calling routine. Return this buffer, and if ADJUST
7565 is non-null set it to the length of the string we removed from the
34bca508
L		 7566 input line. Otherwise return NULL.
7567
a988325c
NC		 7568 This function is copied from the ELF version above adjusted for PE targets. */
7569
7570static char *
7571lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7572 int *adjust ATTRIBUTE_UNUSED,
c06ec724
L		 7573 i386_operand_type *types,
7574 int bnd_prefix ATTRIBUTE_UNUSED)
a988325c
NC		 7575{
7576 static const struct
7577 {
7578 const char *str;
7579 int len;
7580 const enum bfd_reloc_code_real rel[2];
7581 const i386_operand_type types64;
7582 }
7583 gotrel[] =
7584 {
7585 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7586 BFD_RELOC_32_SECREL },
7587 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7588 };
7589
7590 char *cp;
7591 unsigned j;
7592
7593 for (cp = input_line_pointer; *cp != '@'; cp++)
7594 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7595 return NULL;
7596
7597 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7598 {
7599 int len = gotrel[j].len;
7600
7601 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7602 {
7603 if (gotrel[j].rel[object_64bit] != 0)
7604 {
7605 int first, second;
7606 char *tmpbuf, *past_reloc;
7607
7608 *rel = gotrel[j].rel[object_64bit];
7609 if (adjust)
7610 *adjust = len;
7611
7612 if (types)
7613 {
7614 if (flag_code != CODE_64BIT)
7615 {
7616 types->bitfield.imm32 = 1;
7617 types->bitfield.disp32 = 1;
7618 }
7619 else
7620 *types = gotrel[j].types64;
7621 }
7622
7623 /* The length of the first part of our input line. */
7624 first = cp - input_line_pointer;
7625
7626 /* The second part goes from after the reloc token until
7627 (and including) an end_of_line char or comma. */
7628 past_reloc = cp + 1 + len;
7629 cp = past_reloc;
7630 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7631 ++cp;
7632 second = cp + 1 - past_reloc;
7633
7634 /* Allocate and copy string. The trailing NUL shouldn't
7635 be necessary, but be safe. */
7636 tmpbuf = (char *) xmalloc (first + second + 2);
7637 memcpy (tmpbuf, input_line_pointer, first);
7638 if (second != 0 && *past_reloc != ' ')
7639 /* Replace the relocation token with ' ', so that
7640 errors like foo@SECLREL321 will be detected. */
7641 tmpbuf[first++] = ' ';
7642 memcpy (tmpbuf + first, past_reloc, second);
7643 tmpbuf[first + second] = '\0';
7644 return tmpbuf;
7645 }
7646
7647 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7648 gotrel[j].str, 1 << (5 + object_64bit));
7649 return NULL;
7650 }
7651 }
7652
7653 /* Might be a symbol version string. Don't as_bad here. */
7654 return NULL;
7655}
7656
7657#endif /* TE_PE */
7658
62ebcb5c 7659bfd_reloc_code_real_type
e3bb37b5 7660x86_cons (expressionS *exp, int size)
f3c180ae 7661{
62ebcb5c
AM		 7662 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7663
ee86248c
JB		 7664 intel_syntax = -intel_syntax;
7665
3c7b9c2c 7666 exp->X_md = 0;
4fa24527 7667 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7668 {
7669 /* Handle @GOTOFF and the like in an expression. */
7670 char *save;
7671 char *gotfree_input_line;
4a57f2cf 7672 int adjust = 0;
f3c180ae
AM		 7673
7674 save = input_line_pointer;
c3320543 7675 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL, 0);
f3c180ae
AM		 7676 if (gotfree_input_line)
7677 input_line_pointer = gotfree_input_line;
7678
7679 expression (exp);
7680
7681 if (gotfree_input_line)
7682 {
7683 /* expression () has merrily parsed up to the end of line,
7684 or a comma - in the wrong buffer. Transfer how far
7685 input_line_pointer has moved to the right buffer. */
7686 input_line_pointer = (save
7687 + (input_line_pointer - gotfree_input_line)
7688 + adjust);
7689 free (gotfree_input_line);
3992d3b7
AM		 7690 if (exp->X_op == O_constant
7691 || exp->X_op == O_absent
7692 || exp->X_op == O_illegal
0398aac5 7693 || exp->X_op == O_register
3992d3b7
AM		 7694 || exp->X_op == O_big)
7695 {
7696 char c = *input_line_pointer;
7697 *input_line_pointer = 0;
7698 as_bad (_("missing or invalid expression `%s'"), save);
7699 *input_line_pointer = c;
7700 }
f3c180ae
AM		 7701 }
7702 }
7703 else
7704 expression (exp);
ee86248c
JB		 7705
7706 intel_syntax = -intel_syntax;
7707
7708 if (intel_syntax)
7709 i386_intel_simplify (exp);
62ebcb5c
AM		 7710
7711 return got_reloc;
f3c180ae 7712}
f3c180ae 7713
9f32dd5b
L		 7714static void
7715signed_cons (int size)
6482c264 7716{
d182319b
JB		 7717 if (flag_code == CODE_64BIT)
7718 cons_sign = 1;
7719 cons (size);
7720 cons_sign = -1;
6482c264
NC		 7721}
7722
d182319b 7723#ifdef TE_PE
6482c264 7724static void
7016a5d5 7725pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7726{
7727 expressionS exp;
7728
7729 do
7730 {
7731 expression (&exp);
7732 if (exp.X_op == O_symbol)
7733 exp.X_op = O_secrel;
7734
7735 emit_expr (&exp, 4);
7736 }
7737 while (*input_line_pointer++ == ',');
7738
7739 input_line_pointer--;
7740 demand_empty_rest_of_line ();
7741}
6482c264
NC		 7742#endif
7743
43234a1e
L		 7744/* Handle Vector operations. */
7745
7746static char *
7747check_VecOperations (char *op_string, char *op_end)
7748{
7749 const reg_entry *mask;
7750 const char *saved;
7751 char *end_op;
7752
7753 while (*op_string
7754 && (op_end == NULL || op_string < op_end))
7755 {
7756 saved = op_string;
7757 if (*op_string == '{')
7758 {
7759 op_string++;
7760
7761 /* Check broadcasts. */
7762 if (strncmp (op_string, "1to", 3) == 0)
7763 {
7764 int bcst_type;
7765
7766 if (i.broadcast)
7767 goto duplicated_vec_op;
7768
7769 op_string += 3;
7770 if (*op_string == '8')
7771 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7772 else if (*op_string == '4')
7773 bcst_type = BROADCAST_1TO4;
7774 else if (*op_string == '2')
7775 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7776 else if (*op_string == '1'
7777 && *(op_string+1) == '6')
7778 {
7779 bcst_type = BROADCAST_1TO16;
7780 op_string++;
7781 }
7782 else
7783 {
7784 as_bad (_("Unsupported broadcast: `%s'"), saved);
7785 return NULL;
7786 }
7787 op_string++;
7788
7789 broadcast_op.type = bcst_type;
7790 broadcast_op.operand = this_operand;
7791 i.broadcast = &broadcast_op;
7792 }
7793 /* Check masking operation. */
7794 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7795 {
7796 /* k0 can't be used for write mask. */
7797 if (mask->reg_num == 0)
7798 {
7799 as_bad (_("`%s' can't be used for write mask"),
7800 op_string);
7801 return NULL;
7802 }
7803
7804 if (!i.mask)
7805 {
7806 mask_op.mask = mask;
7807 mask_op.zeroing = 0;
7808 mask_op.operand = this_operand;
7809 i.mask = &mask_op;
7810 }
7811 else
7812 {
7813 if (i.mask->mask)
7814 goto duplicated_vec_op;
7815
7816 i.mask->mask = mask;
7817
7818 /* Only "{z}" is allowed here. No need to check
7819 zeroing mask explicitly. */
7820 if (i.mask->operand != this_operand)
7821 {
7822 as_bad (_("invalid write mask `%s'"), saved);
7823 return NULL;
7824 }
7825 }
7826
7827 op_string = end_op;
7828 }
7829 /* Check zeroing-flag for masking operation. */
7830 else if (*op_string == 'z')
7831 {
7832 if (!i.mask)
7833 {
7834 mask_op.mask = NULL;
7835 mask_op.zeroing = 1;
7836 mask_op.operand = this_operand;
7837 i.mask = &mask_op;
7838 }
7839 else
7840 {
7841 if (i.mask->zeroing)
7842 {
7843 duplicated_vec_op:
7844 as_bad (_("duplicated `%s'"), saved);
7845 return NULL;
7846 }
7847
7848 i.mask->zeroing = 1;
7849
7850 /* Only "{%k}" is allowed here. No need to check mask
7851 register explicitly. */
7852 if (i.mask->operand != this_operand)
7853 {
7854 as_bad (_("invalid zeroing-masking `%s'"),
7855 saved);
7856 return NULL;
7857 }
7858 }
7859
7860 op_string++;
7861 }
7862 else
7863 goto unknown_vec_op;
7864
7865 if (*op_string != '}')
7866 {
7867 as_bad (_("missing `}' in `%s'"), saved);
7868 return NULL;
7869 }
7870 op_string++;
7871 continue;
7872 }
7873 unknown_vec_op:
7874 /* We don't know this one. */
7875 as_bad (_("unknown vector operation: `%s'"), saved);
7876 return NULL;
7877 }
7878
7879 return op_string;
7880}
7881
252b5132 7882static int
70e41ade 7883i386_immediate (char *imm_start)
252b5132
RH		 7884{
7885 char *save_input_line_pointer;
f3c180ae 7886 char *gotfree_input_line;
252b5132 7887 segT exp_seg = 0;
47926f60 7888 expressionS *exp;
40fb9820
L		 7889 i386_operand_type types;
7890
0dfbf9d7 7891 operand_type_set (&types, ~0);
252b5132
RH		 7892
7893 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7894 {
31b2323c
L		 7895 as_bad (_("at most %d immediate operands are allowed"),
7896 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7897 return 0;
7898 }
7899
7900 exp = &im_expressions[i.imm_operands++];
520dc8e8 7901 i.op[this_operand].imms = exp;
252b5132
RH		 7902
7903 if (is_space_char (*imm_start))
7904 ++imm_start;
7905
7906 save_input_line_pointer = input_line_pointer;
7907 input_line_pointer = imm_start;
7908
c3320543
L		 7909 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
7910 (i.bnd_prefix != NULL
7911 || add_bnd_prefix));
f3c180ae
AM		 7912 if (gotfree_input_line)
7913 input_line_pointer = gotfree_input_line;
252b5132
RH		 7914
7915 exp_seg = expression (exp);
7916
83183c0c 7917 SKIP_WHITESPACE ();
43234a1e
L		 7918
7919 /* Handle vector operations. */
7920 if (*input_line_pointer == '{')
7921 {
7922 input_line_pointer = check_VecOperations (input_line_pointer,
7923 NULL);
7924 if (input_line_pointer == NULL)
7925 return 0;
7926 }
7927
252b5132 7928 if (*input_line_pointer)
f3c180ae 7929 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7930
7931 input_line_pointer = save_input_line_pointer;
f3c180ae 7932 if (gotfree_input_line)
ee86248c
JB		 7933 {
7934 free (gotfree_input_line);
7935
7936 if (exp->X_op == O_constant || exp->X_op == O_register)
7937 exp->X_op = O_illegal;
7938 }
7939
7940 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7941}
252b5132 7942
ee86248c
JB		 7943static int
7944i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7945 i386_operand_type types, const char *imm_start)
7946{
7947 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7948 {
313c53d1
L		 7949 if (imm_start)
7950 as_bad (_("missing or invalid immediate expression `%s'"),
7951 imm_start);
3992d3b7 7952 return 0;
252b5132 7953 }
3e73aa7c 7954 else if (exp->X_op == O_constant)
252b5132 7955 {
47926f60 7956 /* Size it properly later. */
40fb9820 7957 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7958 /* If not 64bit, sign extend val. */
7959 if (flag_code != CODE_64BIT
4eed87de
AM		 7960 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7961 exp->X_add_number
7962 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7963 }
4c63da97 7964#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7965 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7966 && exp_seg != absolute_section
47926f60 7967 && exp_seg != text_section
24eab124
AM		 7968 && exp_seg != data_section
7969 && exp_seg != bss_section
7970 && exp_seg != undefined_section
f86103b7 7971 && !bfd_is_com_section (exp_seg))
252b5132 7972 {
d0b47220 7973 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7974 return 0;
7975 }
7976#endif
bb8f5920
L		 7977 else if (!intel_syntax && exp->X_op == O_register)
7978 {
313c53d1
L		 7979 if (imm_start)
7980 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7981 return 0;
7982 }
252b5132
RH		 7983 else
7984 {
7985 /* This is an address. The size of the address will be
24eab124 7986 determined later, depending on destination register,
3e73aa7c 7987 suffix, or the default for the section. */
40fb9820
L		 7988 i.types[this_operand].bitfield.imm8 = 1;
7989 i.types[this_operand].bitfield.imm16 = 1;
7990 i.types[this_operand].bitfield.imm32 = 1;
7991 i.types[this_operand].bitfield.imm32s = 1;
7992 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7993 i.types[this_operand] = operand_type_and (i.types[this_operand],
7994 types);
252b5132
RH		 7995 }
7996
7997 return 1;
7998}
7999
551c1ca1 8000static char *
e3bb37b5 8001i386_scale (char *scale)
252b5132 8002{
551c1ca1
AM		 8003 offsetT val;
8004 char *save = input_line_pointer;
252b5132 8005
551c1ca1
AM		 8006 input_line_pointer = scale;
8007 val = get_absolute_expression ();
8008
8009 switch (val)
252b5132 8010 {
551c1ca1 8011 case 1:
252b5132
RH		 8012 i.log2_scale_factor = 0;
8013 break;
551c1ca1 8014 case 2:
252b5132
RH		 8015 i.log2_scale_factor = 1;
8016 break;
551c1ca1 8017 case 4:
252b5132
RH		 8018 i.log2_scale_factor = 2;
8019 break;
551c1ca1 8020 case 8:
252b5132
RH		 8021 i.log2_scale_factor = 3;
8022 break;
8023 default:
a724f0f4
JB		 8024 {
8025 char sep = *input_line_pointer;
8026
8027 *input_line_pointer = '\0';
8028 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8029 scale);
8030 *input_line_pointer = sep;
8031 input_line_pointer = save;
8032 return NULL;
8033 }
252b5132 8034 }
29b0f896 8035 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8036 {
8037 as_warn (_("scale factor of %d without an index register"),
24eab124 8038 1 << i.log2_scale_factor);
252b5132 8039 i.log2_scale_factor = 0;
252b5132 8040 }
551c1ca1
AM		 8041 scale = input_line_pointer;
8042 input_line_pointer = save;
8043 return scale;
252b5132
RH		 8044}
8045
252b5132 8046static int
e3bb37b5 8047i386_displacement (char *disp_start, char *disp_end)
252b5132 8048{
29b0f896 8049 expressionS *exp;
252b5132
RH		 8050 segT exp_seg = 0;
8051 char *save_input_line_pointer;
f3c180ae 8052 char *gotfree_input_line;
40fb9820
L		 8053 int override;
8054 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8055 int ret;
252b5132 8056
31b2323c
L		 8057 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8058 {
8059 as_bad (_("at most %d displacement operands are allowed"),
8060 MAX_MEMORY_OPERANDS);
8061 return 0;
8062 }
8063
0dfbf9d7 8064 operand_type_set (&bigdisp, 0);
40fb9820
L		 8065 if ((i.types[this_operand].bitfield.jumpabsolute)
8066 || (!current_templates->start->opcode_modifier.jump
8067 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8068 {
40fb9820 8069 bigdisp.bitfield.disp32 = 1;
e05278af 8070 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8071 if (flag_code == CODE_64BIT)
8072 {
8073 if (!override)
8074 {
8075 bigdisp.bitfield.disp32s = 1;
8076 bigdisp.bitfield.disp64 = 1;
8077 }
8078 }
8079 else if ((flag_code == CODE_16BIT) ^ override)
8080 {
8081 bigdisp.bitfield.disp32 = 0;
8082 bigdisp.bitfield.disp16 = 1;
8083 }
e05278af
JB		 8084 }
8085 else
8086 {
8087 /* For PC-relative branches, the width of the displacement
8088 is dependent upon data size, not address size. */
e05278af 8089 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8090 if (flag_code == CODE_64BIT)
8091 {
8092 if (override || i.suffix == WORD_MNEM_SUFFIX)
8093 bigdisp.bitfield.disp16 = 1;
8094 else
8095 {
8096 bigdisp.bitfield.disp32 = 1;
8097 bigdisp.bitfield.disp32s = 1;
8098 }
8099 }
8100 else
e05278af
JB		 8101 {
8102 if (!override)
8103 override = (i.suffix == (flag_code != CODE_16BIT
8104 ? WORD_MNEM_SUFFIX
8105 : LONG_MNEM_SUFFIX));
40fb9820
L		 8106 bigdisp.bitfield.disp32 = 1;
8107 if ((flag_code == CODE_16BIT) ^ override)
8108 {
8109 bigdisp.bitfield.disp32 = 0;
8110 bigdisp.bitfield.disp16 = 1;
8111 }
e05278af 8112 }
e05278af 8113 }
c6fb90c8
L		 8114 i.types[this_operand] = operand_type_or (i.types[this_operand],
8115 bigdisp);
252b5132
RH		 8116
8117 exp = &disp_expressions[i.disp_operands];
520dc8e8 8118 i.op[this_operand].disps = exp;
252b5132
RH		 8119 i.disp_operands++;
8120 save_input_line_pointer = input_line_pointer;
8121 input_line_pointer = disp_start;
8122 END_STRING_AND_SAVE (disp_end);
8123
8124#ifndef GCC_ASM_O_HACK
8125#define GCC_ASM_O_HACK 0
8126#endif
8127#if GCC_ASM_O_HACK
8128 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8129 if (i.types[this_operand].bitfield.baseIndex
24eab124 8130 && displacement_string_end[-1] == '+')
252b5132
RH		 8131 {
8132 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8133 constraint within gcc asm statements.
8134 For instance:
8135
8136 #define _set_tssldt_desc(n,addr,limit,type) \
8137 __asm__ __volatile__ ( \
8138 "movw %w2,%0\n\t" \
8139 "movw %w1,2+%0\n\t" \
8140 "rorl $16,%1\n\t" \
8141 "movb %b1,4+%0\n\t" \
8142 "movb %4,5+%0\n\t" \
8143 "movb $0,6+%0\n\t" \
8144 "movb %h1,7+%0\n\t" \
8145 "rorl $16,%1" \
8146 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8147
8148 This works great except that the output assembler ends
8149 up looking a bit weird if it turns out that there is
8150 no offset. You end up producing code that looks like:
8151
8152 #APP
8153 movw $235,(%eax)
8154 movw %dx,2+(%eax)
8155 rorl $16,%edx
8156 movb %dl,4+(%eax)
8157 movb $137,5+(%eax)
8158 movb $0,6+(%eax)
8159 movb %dh,7+(%eax)
8160 rorl $16,%edx
8161 #NO_APP
8162
47926f60 8163 So here we provide the missing zero. */
24eab124
AM		 8164
8165 *displacement_string_end = '0';
252b5132
RH		 8166 }
8167#endif
c3320543
L		 8168 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
8169 (i.bnd_prefix != NULL
8170 || add_bnd_prefix));
f3c180ae
AM		 8171 if (gotfree_input_line)
8172 input_line_pointer = gotfree_input_line;
252b5132 8173
24eab124 8174 exp_seg = expression (exp);
252b5132 8175
636c26b0
AM		 8176 SKIP_WHITESPACE ();
8177 if (*input_line_pointer)
8178 as_bad (_("junk `%s' after expression"), input_line_pointer);
8179#if GCC_ASM_O_HACK
8180 RESTORE_END_STRING (disp_end + 1);
8181#endif
636c26b0 8182 input_line_pointer = save_input_line_pointer;
636c26b0 8183 if (gotfree_input_line)
ee86248c
JB		 8184 {
8185 free (gotfree_input_line);
8186
8187 if (exp->X_op == O_constant || exp->X_op == O_register)
8188 exp->X_op = O_illegal;
8189 }
8190
8191 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8192
8193 RESTORE_END_STRING (disp_end);
8194
8195 return ret;
8196}
8197
8198static int
8199i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8200 i386_operand_type types, const char *disp_start)
8201{
8202 i386_operand_type bigdisp;
8203 int ret = 1;
636c26b0 8204
24eab124
AM		 8205 /* We do this to make sure that the section symbol is in
8206 the symbol table. We will ultimately change the relocation
47926f60 8207 to be relative to the beginning of the section. */
1ae12ab7 8208 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8209 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8210 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8211 {
636c26b0 8212 if (exp->X_op != O_symbol)
3992d3b7 8213 goto inv_disp;
636c26b0 8214
e5cb08ac 8215 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8216 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8217 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8218 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8219 exp->X_op = O_subtract;
8220 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8221 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8222 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8223 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8224 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8225 else
29b0f896 8226 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8227 }
252b5132 8228
3992d3b7
AM		 8229 else if (exp->X_op == O_absent
8230 || exp->X_op == O_illegal
ee86248c 8231 || exp->X_op == O_big)
2daf4fd8 8232 {
3992d3b7
AM		 8233 inv_disp:
8234 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8235 disp_start);
3992d3b7 8236 ret = 0;
2daf4fd8
AM		 8237 }
8238
0e1147d9
L		 8239 else if (flag_code == CODE_64BIT
8240 && !i.prefix[ADDR_PREFIX]
8241 && exp->X_op == O_constant)
8242 {
8243 /* Since displacement is signed extended to 64bit, don't allow
8244 disp32 and turn off disp32s if they are out of range. */
8245 i.types[this_operand].bitfield.disp32 = 0;
8246 if (!fits_in_signed_long (exp->X_add_number))
8247 {
8248 i.types[this_operand].bitfield.disp32s = 0;
8249 if (i.types[this_operand].bitfield.baseindex)
8250 {
8251 as_bad (_("0x%lx out range of signed 32bit displacement"),
8252 (long) exp->X_add_number);
8253 ret = 0;
8254 }
8255 }
8256 }
8257
4c63da97 8258#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8259 else if (exp->X_op != O_constant
8260 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8261 && exp_seg != absolute_section
8262 && exp_seg != text_section
8263 && exp_seg != data_section
8264 && exp_seg != bss_section
8265 && exp_seg != undefined_section
8266 && !bfd_is_com_section (exp_seg))
24eab124 8267 {
d0b47220 8268 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8269 ret = 0;
24eab124 8270 }
252b5132 8271#endif
3956db08 8272
40fb9820
L		 8273 /* Check if this is a displacement only operand. */
8274 bigdisp = i.types[this_operand];
8275 bigdisp.bitfield.disp8 = 0;
8276 bigdisp.bitfield.disp16 = 0;
8277 bigdisp.bitfield.disp32 = 0;
8278 bigdisp.bitfield.disp32s = 0;
8279 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8280 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8281 i.types[this_operand] = operand_type_and (i.types[this_operand],
8282 types);
3956db08 8283
3992d3b7 8284 return ret;
252b5132
RH		 8285}
8286
eecb386c 8287/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8288 Return 1 on success, 0 on a failure. */
8289
252b5132 8290static int
e3bb37b5 8291i386_index_check (const char *operand_string)
252b5132 8292{
fc0763e6 8293 const char *kind = "base/index";
be05d201
L		 8294 enum flag_code addr_mode;
8295
8296 if (i.prefix[ADDR_PREFIX])
8297 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8298 else
8299 {
8300 addr_mode = flag_code;
8301
24eab124 8302#if INFER_ADDR_PREFIX
be05d201
L		 8303 if (i.mem_operands == 0)
8304 {
8305 /* Infer address prefix from the first memory operand. */
8306 const reg_entry *addr_reg = i.base_reg;
8307
8308 if (addr_reg == NULL)
8309 addr_reg = i.index_reg;
eecb386c 8310
be05d201
L		 8311 if (addr_reg)
8312 {
8313 if (addr_reg->reg_num == RegEip
8314 || addr_reg->reg_num == RegEiz
8315 || addr_reg->reg_type.bitfield.reg32)
8316 addr_mode = CODE_32BIT;
8317 else if (flag_code != CODE_64BIT
8318 && addr_reg->reg_type.bitfield.reg16)
8319 addr_mode = CODE_16BIT;
8320
8321 if (addr_mode != flag_code)
8322 {
8323 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8324 i.prefixes += 1;
8325 /* Change the size of any displacement too. At most one
8326 of Disp16 or Disp32 is set.
8327 FIXME. There doesn't seem to be any real need for
8328 separate Disp16 and Disp32 flags. The same goes for
8329 Imm16 and Imm32. Removing them would probably clean
8330 up the code quite a lot. */
8331 if (flag_code != CODE_64BIT
8332 && (i.types[this_operand].bitfield.disp16
8333 || i.types[this_operand].bitfield.disp32))
8334 i.types[this_operand]
8335 = operand_type_xor (i.types[this_operand], disp16_32);
8336 }
8337 }
8338 }
24eab124 8339#endif
be05d201
L		 8340 }
8341
fc0763e6
JB		 8342 if (current_templates->start->opcode_modifier.isstring
8343 && !current_templates->start->opcode_modifier.immext
8344 && (current_templates->end[-1].opcode_modifier.isstring
8345 || i.mem_operands))
8346 {
8347 /* Memory operands of string insns are special in that they only allow
8348 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8349 const reg_entry *expected_reg;
8350 static const char *di_si[][2] =
8351 {
8352 { "esi", "edi" },
8353 { "si", "di" },
8354 { "rsi", "rdi" }
8355 };
8356 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8357
8358 kind = "string address";
8359
8360 if (current_templates->start->opcode_modifier.w)
8361 {
8362 i386_operand_type type = current_templates->end[-1].operand_types[0];
8363
8364 if (!type.bitfield.baseindex
8365 || ((!i.mem_operands != !intel_syntax)
8366 && current_templates->end[-1].operand_types[1]
8367 .bitfield.baseindex))
8368 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8369 expected_reg = hash_find (reg_hash,
8370 di_si[addr_mode][type.bitfield.esseg]);
8371
fc0763e6
JB		 8372 }
8373 else
be05d201 8374 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8375
be05d201
L		 8376 if (i.base_reg != expected_reg
8377 || i.index_reg
fc0763e6 8378 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8379 {
be05d201
L		 8380 /* The second memory operand must have the same size as
8381 the first one. */
8382 if (i.mem_operands
8383 && i.base_reg
8384 && !((addr_mode == CODE_64BIT
8385 && i.base_reg->reg_type.bitfield.reg64)
8386 || (addr_mode == CODE_32BIT
8387 ? i.base_reg->reg_type.bitfield.reg32
8388 : i.base_reg->reg_type.bitfield.reg16)))
8389 goto bad_address;
8390
fc0763e6
JB		 8391 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8392 operand_string,
8393 intel_syntax ? '[' : '(',
8394 register_prefix,
be05d201 8395 expected_reg->reg_name,
fc0763e6 8396 intel_syntax ? ']' : ')');
be05d201 8397 return 1;
fc0763e6 8398 }
be05d201
L		 8399 else
8400 return 1;
8401
8402bad_address:
8403 as_bad (_("`%s' is not a valid %s expression"),
8404 operand_string, kind);
8405 return 0;
3e73aa7c
JH		 8406 }
8407 else
8408 {
be05d201
L		 8409 if (addr_mode != CODE_16BIT)
8410 {
8411 /* 32-bit/64-bit checks. */
8412 if ((i.base_reg
8413 && (addr_mode == CODE_64BIT
8414 ? !i.base_reg->reg_type.bitfield.reg64
8415 : !i.base_reg->reg_type.bitfield.reg32)
8416 && (i.index_reg
8417 || (i.base_reg->reg_num
8418 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8419 || (i.index_reg
8420 && !i.index_reg->reg_type.bitfield.regxmm
8421 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8422 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8423 && ((addr_mode == CODE_64BIT
8424 ? !(i.index_reg->reg_type.bitfield.reg64
8425 || i.index_reg->reg_num == RegRiz)
8426 : !(i.index_reg->reg_type.bitfield.reg32
8427 || i.index_reg->reg_num == RegEiz))
8428 || !i.index_reg->reg_type.bitfield.baseindex)))
8429 goto bad_address;
8430 }
8431 else
3e73aa7c 8432 {
be05d201 8433 /* 16-bit checks. */
3e73aa7c 8434 if ((i.base_reg
40fb9820
L		 8435 && (!i.base_reg->reg_type.bitfield.reg16
8436 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8437 || (i.index_reg
40fb9820
L		 8438 && (!i.index_reg->reg_type.bitfield.reg16
8439 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8440 || !(i.base_reg
8441 && i.base_reg->reg_num < 6
8442 && i.index_reg->reg_num >= 6
8443 && i.log2_scale_factor == 0))))
be05d201 8444 goto bad_address;
3e73aa7c
JH		 8445 }
8446 }
be05d201 8447 return 1;
24eab124 8448}
252b5132 8449
43234a1e
L		 8450/* Handle vector immediates. */
8451
8452static int
8453RC_SAE_immediate (const char *imm_start)
8454{
8455 unsigned int match_found, j;
8456 const char *pstr = imm_start;
8457 expressionS *exp;
8458
8459 if (*pstr != '{')
8460 return 0;
8461
8462 pstr++;
8463 match_found = 0;
8464 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8465 {
8466 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8467 {
8468 if (!i.rounding)
8469 {
8470 rc_op.type = RC_NamesTable[j].type;
8471 rc_op.operand = this_operand;
8472 i.rounding = &rc_op;
8473 }
8474 else
8475 {
8476 as_bad (_("duplicated `%s'"), imm_start);
8477 return 0;
8478 }
8479 pstr += RC_NamesTable[j].len;
8480 match_found = 1;
8481 break;
8482 }
8483 }
8484 if (!match_found)
8485 return 0;
8486
8487 if (*pstr++ != '}')
8488 {
8489 as_bad (_("Missing '}': '%s'"), imm_start);
8490 return 0;
8491 }
8492 /* RC/SAE immediate string should contain nothing more. */;
8493 if (*pstr != 0)
8494 {
8495 as_bad (_("Junk after '}': '%s'"), imm_start);
8496 return 0;
8497 }
8498
8499 exp = &im_expressions[i.imm_operands++];
8500 i.op[this_operand].imms = exp;
8501
8502 exp->X_op = O_constant;
8503 exp->X_add_number = 0;
8504 exp->X_add_symbol = (symbolS *) 0;
8505 exp->X_op_symbol = (symbolS *) 0;
8506
8507 i.types[this_operand].bitfield.imm8 = 1;
8508 return 1;
8509}
8510
fc0763e6 8511/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8512 on error. */
252b5132 8513
252b5132 8514static int
a7619375 8515i386_att_operand (char *operand_string)
252b5132 8516{
af6bdddf
AM		 8517 const reg_entry *r;
8518 char *end_op;
24eab124 8519 char *op_string = operand_string;
252b5132 8520
24eab124 8521 if (is_space_char (*op_string))
252b5132
RH		 8522 ++op_string;
8523
24eab124 8524 /* We check for an absolute prefix (differentiating,
47926f60 8525 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8526 if (*op_string == ABSOLUTE_PREFIX)
8527 {
8528 ++op_string;
8529 if (is_space_char (*op_string))
8530 ++op_string;
40fb9820 8531 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8532 }
252b5132 8533
47926f60 8534 /* Check if operand is a register. */
4d1bb795 8535 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8536 {
40fb9820
L		 8537 i386_operand_type temp;
8538
24eab124
AM		 8539 /* Check for a segment override by searching for ':' after a
8540 segment register. */
8541 op_string = end_op;
8542 if (is_space_char (*op_string))
8543 ++op_string;
40fb9820
L		 8544 if (*op_string == ':'
8545 && (r->reg_type.bitfield.sreg2
8546 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8547 {
8548 switch (r->reg_num)
8549 {
8550 case 0:
8551 i.seg[i.mem_operands] = &es;
8552 break;
8553 case 1:
8554 i.seg[i.mem_operands] = &cs;
8555 break;
8556 case 2:
8557 i.seg[i.mem_operands] = &ss;
8558 break;
8559 case 3:
8560 i.seg[i.mem_operands] = &ds;
8561 break;
8562 case 4:
8563 i.seg[i.mem_operands] = &fs;
8564 break;
8565 case 5:
8566 i.seg[i.mem_operands] = &gs;
8567 break;
8568 }
252b5132 8569
24eab124 8570 /* Skip the ':' and whitespace. */
252b5132
RH		 8571 ++op_string;
8572 if (is_space_char (*op_string))
24eab124 8573 ++op_string;
252b5132 8574
24eab124
AM		 8575 if (!is_digit_char (*op_string)
8576 && !is_identifier_char (*op_string)
8577 && *op_string != '('
8578 && *op_string != ABSOLUTE_PREFIX)
8579 {
8580 as_bad (_("bad memory operand `%s'"), op_string);
8581 return 0;
8582 }
47926f60 8583 /* Handle case of %es:*foo. */
24eab124
AM		 8584 if (*op_string == ABSOLUTE_PREFIX)
8585 {
8586 ++op_string;
8587 if (is_space_char (*op_string))
8588 ++op_string;
40fb9820 8589 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8590 }
8591 goto do_memory_reference;
8592 }
43234a1e
L		 8593
8594 /* Handle vector operations. */
8595 if (*op_string == '{')
8596 {
8597 op_string = check_VecOperations (op_string, NULL);
8598 if (op_string == NULL)
8599 return 0;
8600 }
8601
24eab124
AM		 8602 if (*op_string)
8603 {
d0b47220 8604 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8605 return 0;
8606 }
40fb9820
L		 8607 temp = r->reg_type;
8608 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8609 i.types[this_operand] = operand_type_or (i.types[this_operand],
8610 temp);
7d5e4556 8611 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8612 i.op[this_operand].regs = r;
24eab124
AM		 8613 i.reg_operands++;
8614 }
af6bdddf
AM		 8615 else if (*op_string == REGISTER_PREFIX)
8616 {
8617 as_bad (_("bad register name `%s'"), op_string);
8618 return 0;
8619 }
24eab124 8620 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8621 {
24eab124 8622 ++op_string;
40fb9820 8623 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8624 {
d0b47220 8625 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8626 return 0;
8627 }
8628 if (!i386_immediate (op_string))
8629 return 0;
8630 }
43234a1e
L		 8631 else if (RC_SAE_immediate (operand_string))
8632 {
8633 /* If it is a RC or SAE immediate, do nothing. */
8634 ;
8635 }
24eab124
AM		 8636 else if (is_digit_char (*op_string)
8637 || is_identifier_char (*op_string)
e5cb08ac 8638 || *op_string == '(')
24eab124 8639 {
47926f60 8640 /* This is a memory reference of some sort. */
af6bdddf 8641 char *base_string;
252b5132 8642
47926f60 8643 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8644 char *displacement_string_start;
8645 char *displacement_string_end;
43234a1e 8646 char *vop_start;
252b5132 8647
24eab124 8648 do_memory_reference:
24eab124 8649 if ((i.mem_operands == 1
40fb9820 8650 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8651 || i.mem_operands == 2)
8652 {
8653 as_bad (_("too many memory references for `%s'"),
8654 current_templates->start->name);
8655 return 0;
8656 }
252b5132 8657
24eab124
AM		 8658 /* Check for base index form. We detect the base index form by
8659 looking for an ')' at the end of the operand, searching
8660 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8661 after the '('. */
af6bdddf 8662 base_string = op_string + strlen (op_string);
c3332e24 8663
43234a1e
L		 8664 /* Handle vector operations. */
8665 vop_start = strchr (op_string, '{');
8666 if (vop_start && vop_start < base_string)
8667 {
8668 if (check_VecOperations (vop_start, base_string) == NULL)
8669 return 0;
8670 base_string = vop_start;
8671 }
8672
af6bdddf
AM		 8673 --base_string;
8674 if (is_space_char (*base_string))
8675 --base_string;
252b5132 8676
47926f60 8677 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8678 displacement_string_start = op_string;
8679 displacement_string_end = base_string + 1;
252b5132 8680
24eab124
AM		 8681 if (*base_string == ')')
8682 {
af6bdddf 8683 char *temp_string;
24eab124
AM		 8684 unsigned int parens_balanced = 1;
8685 /* We've already checked that the number of left & right ()'s are
47926f60 8686 equal, so this loop will not be infinite. */
24eab124
AM		 8687 do
8688 {
8689 base_string--;
8690 if (*base_string == ')')
8691 parens_balanced++;
8692 if (*base_string == '(')
8693 parens_balanced--;
8694 }
8695 while (parens_balanced);
c3332e24 8696
af6bdddf 8697 temp_string = base_string;
c3332e24 8698
24eab124 8699 /* Skip past '(' and whitespace. */
252b5132
RH		 8700 ++base_string;
8701 if (is_space_char (*base_string))
24eab124 8702 ++base_string;
252b5132 8703
af6bdddf 8704 if (*base_string == ','
4eed87de
AM		 8705 || ((i.base_reg = parse_register (base_string, &end_op))
8706 != NULL))
252b5132 8707 {
af6bdddf 8708 displacement_string_end = temp_string;
252b5132 8709
40fb9820 8710 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8711
af6bdddf 8712 if (i.base_reg)
24eab124 8713 {
24eab124
AM		 8714 base_string = end_op;
8715 if (is_space_char (*base_string))
8716 ++base_string;
af6bdddf
AM		 8717 }
8718
8719 /* There may be an index reg or scale factor here. */
8720 if (*base_string == ',')
8721 {
8722 ++base_string;
8723 if (is_space_char (*base_string))
8724 ++base_string;
8725
4eed87de
AM		 8726 if ((i.index_reg = parse_register (base_string, &end_op))
8727 != NULL)
24eab124 8728 {
af6bdddf 8729 base_string = end_op;
24eab124
AM		 8730 if (is_space_char (*base_string))
8731 ++base_string;
af6bdddf
AM		 8732 if (*base_string == ',')
8733 {
8734 ++base_string;
8735 if (is_space_char (*base_string))
8736 ++base_string;
8737 }
e5cb08ac 8738 else if (*base_string != ')')
af6bdddf 8739 {
4eed87de
AM		 8740 as_bad (_("expecting `,' or `)' "
8741 "after index register in `%s'"),
af6bdddf
AM		 8742 operand_string);
8743 return 0;
8744 }
24eab124 8745 }
af6bdddf 8746 else if (*base_string == REGISTER_PREFIX)
24eab124 8747 {
f76bf5e0
L		 8748 end_op = strchr (base_string, ',');
8749 if (end_op)
8750 *end_op = '\0';
af6bdddf 8751 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8752 return 0;
8753 }
252b5132 8754
47926f60 8755 /* Check for scale factor. */
551c1ca1 8756 if (*base_string != ')')
af6bdddf 8757 {
551c1ca1
AM		 8758 char *end_scale = i386_scale (base_string);
8759
8760 if (!end_scale)
af6bdddf 8761 return 0;
24eab124 8762
551c1ca1 8763 base_string = end_scale;
af6bdddf
AM		 8764 if (is_space_char (*base_string))
8765 ++base_string;
8766 if (*base_string != ')')
8767 {
4eed87de
AM		 8768 as_bad (_("expecting `)' "
8769 "after scale factor in `%s'"),
af6bdddf
AM		 8770 operand_string);
8771 return 0;
8772 }
8773 }
8774 else if (!i.index_reg)
24eab124 8775 {
4eed87de
AM		 8776 as_bad (_("expecting index register or scale factor "
8777 "after `,'; got '%c'"),
af6bdddf 8778 *base_string);
24eab124
AM		 8779 return 0;
8780 }
8781 }
af6bdddf 8782 else if (*base_string != ')')
24eab124 8783 {
4eed87de
AM		 8784 as_bad (_("expecting `,' or `)' "
8785 "after base register in `%s'"),
af6bdddf 8786 operand_string);
24eab124
AM		 8787 return 0;
8788 }
c3332e24 8789 }
af6bdddf 8790 else if (*base_string == REGISTER_PREFIX)
c3332e24 8791 {
f76bf5e0
L		 8792 end_op = strchr (base_string, ',');
8793 if (end_op)
8794 *end_op = '\0';
af6bdddf 8795 as_bad (_("bad register name `%s'"), base_string);
24eab124 8796 return 0;
c3332e24 8797 }
24eab124
AM		 8798 }
8799
8800 /* If there's an expression beginning the operand, parse it,
8801 assuming displacement_string_start and
8802 displacement_string_end are meaningful. */
8803 if (displacement_string_start != displacement_string_end)
8804 {
8805 if (!i386_displacement (displacement_string_start,
8806 displacement_string_end))
8807 return 0;
8808 }
8809
8810 /* Special case for (%dx) while doing input/output op. */
8811 if (i.base_reg
0dfbf9d7
L		 8812 && operand_type_equal (&i.base_reg->reg_type,
8813 &reg16_inoutportreg)
24eab124
AM		 8814 && i.index_reg == 0
8815 && i.log2_scale_factor == 0
8816 && i.seg[i.mem_operands] == 0
40fb9820 8817 && !operand_type_check (i.types[this_operand], disp))
24eab124 8818 {
65da13b5 8819 i.types[this_operand] = inoutportreg;
24eab124
AM		 8820 return 1;
8821 }
8822
eecb386c
AM		 8823 if (i386_index_check (operand_string) == 0)
8824 return 0;
5c07affc 8825 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8826 i.mem_operands++;
8827 }
8828 else
ce8a8b2f
AM		 8829 {
8830 /* It's not a memory operand; argh! */
24eab124
AM		 8831 as_bad (_("invalid char %s beginning operand %d `%s'"),
8832 output_invalid (*op_string),
8833 this_operand + 1,
8834 op_string);
8835 return 0;
8836 }
47926f60 8837 return 1; /* Normal return. */
252b5132
RH		 8838}
8839\f
fa94de6b
RM		 8840/* Calculate the maximum variable size (i.e., excluding fr_fix)
8841 that an rs_machine_dependent frag may reach. */
8842
8843unsigned int
8844i386_frag_max_var (fragS *frag)
8845{
8846 /* The only relaxable frags are for jumps.
8847 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8848 gas_assert (frag->fr_type == rs_machine_dependent);
8849 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8850}
8851
ee7fcc42
AM		 8852/* md_estimate_size_before_relax()
8853
8854 Called just before relax() for rs_machine_dependent frags. The x86
8855 assembler uses these frags to handle variable size jump
8856 instructions.
8857
8858 Any symbol that is now undefined will not become defined.
8859 Return the correct fr_subtype in the frag.
8860 Return the initial "guess for variable size of frag" to caller.
8861 The guess is actually the growth beyond the fixed part. Whatever
8862 we do to grow the fixed or variable part contributes to our
8863 returned value. */
8864
252b5132 8865int
7016a5d5 8866md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8867{
252b5132 8868 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8869 check for un-relaxable symbols. On an ELF system, we can't relax
8870 an externally visible symbol, because it may be overridden by a
8871 shared library. */
8872 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8873#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8874 || (IS_ELF
31312f95 8875 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 8876 || S_IS_WEAK (fragP->fr_symbol)
8877 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8878 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 8879#endif
8880#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8881 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8882 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8883#endif
8884 )
252b5132 8885 {
b98ef147
AM		 8886 /* Symbol is undefined in this segment, or we need to keep a
8887 reloc so that weak symbols can be overridden. */
8888 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8889 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8890 unsigned char *opcode;
8891 int old_fr_fix;
f6af82bd 8892
ee7fcc42 8893 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8894 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8895 else if (size == 2)
f6af82bd
AM		 8896 reloc_type = BFD_RELOC_16_PCREL;
8897 else
8898 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8899
ee7fcc42
AM		 8900 old_fr_fix = fragP->fr_fix;
8901 opcode = (unsigned char *) fragP->fr_opcode;
8902
fddf5b5b 8903 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8904 {
fddf5b5b
AM		 8905 case UNCOND_JUMP:
8906 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8907 opcode[0] = 0xe9;
252b5132 8908 fragP->fr_fix += size;
062cd5e7
AS		 8909 fix_new (fragP, old_fr_fix, size,
8910 fragP->fr_symbol,
8911 fragP->fr_offset, 1,
8912 reloc_type);
252b5132
RH		 8913 break;
8914
fddf5b5b 8915 case COND_JUMP86:
412167cb
AM		 8916 if (size == 2
8917 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8918 {
8919 /* Negate the condition, and branch past an
8920 unconditional jump. */
8921 opcode[0] ^= 1;
8922 opcode[1] = 3;
8923 /* Insert an unconditional jump. */
8924 opcode[2] = 0xe9;
8925 /* We added two extra opcode bytes, and have a two byte
8926 offset. */
8927 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8928 fix_new (fragP, old_fr_fix + 2, 2,
8929 fragP->fr_symbol,
8930 fragP->fr_offset, 1,
8931 reloc_type);
fddf5b5b
AM		 8932 break;
8933 }
8934 /* Fall through. */
8935
8936 case COND_JUMP:
412167cb
AM		 8937 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8938 {
3e02c1cc
AM		 8939 fixS *fixP;
8940
412167cb 8941 fragP->fr_fix += 1;
3e02c1cc
AM		 8942 fixP = fix_new (fragP, old_fr_fix, 1,
8943 fragP->fr_symbol,
8944 fragP->fr_offset, 1,
8945 BFD_RELOC_8_PCREL);
8946 fixP->fx_signed = 1;
412167cb
AM		 8947 break;
8948 }
93c2a809 8949
24eab124 8950 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8951 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8952 opcode[1] = opcode[0] + 0x10;
f6af82bd 8953 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8954 /* We've added an opcode byte. */
8955 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8956 fix_new (fragP, old_fr_fix + 1, size,
8957 fragP->fr_symbol,
8958 fragP->fr_offset, 1,
8959 reloc_type);
252b5132 8960 break;
fddf5b5b
AM		 8961
8962 default:
8963 BAD_CASE (fragP->fr_subtype);
8964 break;
252b5132
RH		 8965 }
8966 frag_wane (fragP);
ee7fcc42 8967 return fragP->fr_fix - old_fr_fix;
252b5132 8968 }
93c2a809 8969
93c2a809
AM		 8970 /* Guess size depending on current relax state. Initially the relax
8971 state will correspond to a short jump and we return 1, because
8972 the variable part of the frag (the branch offset) is one byte
8973 long. However, we can relax a section more than once and in that
8974 case we must either set fr_subtype back to the unrelaxed state,
8975 or return the value for the appropriate branch. */
8976 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8977}
8978
47926f60
KH		 8979/* Called after relax() is finished.
8980
8981 In: Address of frag.
8982 fr_type == rs_machine_dependent.
8983 fr_subtype is what the address relaxed to.
8984
8985 Out: Any fixSs and constants are set up.
8986 Caller will turn frag into a ".space 0". */
8987
252b5132 8988void
7016a5d5
TG		 8989md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8990 fragS *fragP)
252b5132 8991{
29b0f896 8992 unsigned char *opcode;
252b5132 8993 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 8994 offsetT target_address;
8995 offsetT opcode_address;
252b5132 8996 unsigned int extension = 0;
847f7ad4 8997 offsetT displacement_from_opcode_start;
252b5132
RH		 8998
8999 opcode = (unsigned char *) fragP->fr_opcode;
9000
47926f60 9001 /* Address we want to reach in file space. */
252b5132 9002 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9003
47926f60 9004 /* Address opcode resides at in file space. */
252b5132
RH		 9005 opcode_address = fragP->fr_address + fragP->fr_fix;
9006
47926f60 9007 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9008 displacement_from_opcode_start = target_address - opcode_address;
9009
fddf5b5b 9010 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9011 {
47926f60
KH		 9012 /* Don't have to change opcode. */
9013 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9014 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9015 }
9016 else
9017 {
9018 if (no_cond_jump_promotion
9019 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9020 as_warn_where (fragP->fr_file, fragP->fr_line,
9021 _("long jump required"));
252b5132 9022
fddf5b5b
AM		 9023 switch (fragP->fr_subtype)
9024 {
9025 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9026 extension = 4; /* 1 opcode + 4 displacement */
9027 opcode[0] = 0xe9;
9028 where_to_put_displacement = &opcode[1];
9029 break;
252b5132 9030
fddf5b5b
AM		 9031 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9032 extension = 2; /* 1 opcode + 2 displacement */
9033 opcode[0] = 0xe9;
9034 where_to_put_displacement = &opcode[1];
9035 break;
252b5132 9036
fddf5b5b
AM		 9037 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9038 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9039 extension = 5; /* 2 opcode + 4 displacement */
9040 opcode[1] = opcode[0] + 0x10;
9041 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9042 where_to_put_displacement = &opcode[2];
9043 break;
252b5132 9044
fddf5b5b
AM		 9045 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9046 extension = 3; /* 2 opcode + 2 displacement */
9047 opcode[1] = opcode[0] + 0x10;
9048 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9049 where_to_put_displacement = &opcode[2];
9050 break;
252b5132 9051
fddf5b5b
AM		 9052 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9053 extension = 4;
9054 opcode[0] ^= 1;
9055 opcode[1] = 3;
9056 opcode[2] = 0xe9;
9057 where_to_put_displacement = &opcode[3];
9058 break;
9059
9060 default:
9061 BAD_CASE (fragP->fr_subtype);
9062 break;
9063 }
252b5132 9064 }
fddf5b5b 9065
7b81dfbb
AJ		 9066 /* If size if less then four we are sure that the operand fits,
9067 but if it's 4, then it could be that the displacement is larger
9068 then -/+ 2GB. */
9069 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9070 && object_64bit
9071 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9072 + ((addressT) 1 << 31))
9073 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9074 {
9075 as_bad_where (fragP->fr_file, fragP->fr_line,
9076 _("jump target out of range"));
9077 /* Make us emit 0. */
9078 displacement_from_opcode_start = extension;
9079 }
47926f60 9080 /* Now put displacement after opcode. */
252b5132
RH		 9081 md_number_to_chars ((char *) where_to_put_displacement,
9082 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9083 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9084 fragP->fr_fix += extension;
9085}
9086\f
7016a5d5 9087/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9088 by our caller that we have all the info we need to fix it up.
9089
7016a5d5
TG		 9090 Parameter valP is the pointer to the value of the bits.
9091
252b5132
RH		 9092 On the 386, immediates, displacements, and data pointers are all in
9093 the same (little-endian) format, so we don't need to care about which
9094 we are handling. */
9095
94f592af 9096void
7016a5d5 9097md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9098{
94f592af 9099 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9100 valueT value = *valP;
252b5132 9101
f86103b7 9102#if !defined (TE_Mach)
93382f6d
AM		 9103 if (fixP->fx_pcrel)
9104 {
9105 switch (fixP->fx_r_type)
9106 {
5865bb77
ILT		 9107 default:
9108 break;
9109
d6ab8113
JB		 9110 case BFD_RELOC_64:
9111 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9112 break;
93382f6d 9113 case BFD_RELOC_32:
ae8887b5 9114 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9115 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9116 break;
9117 case BFD_RELOC_16:
9118 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9119 break;
9120 case BFD_RELOC_8:
9121 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9122 break;
9123 }
9124 }
252b5132 9125
a161fe53 9126 if (fixP->fx_addsy != NULL
31312f95 9127 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9128 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9129 || fixP->fx_r_type == BFD_RELOC_16_PCREL
c3320543
L		 9130 || fixP->fx_r_type == BFD_RELOC_8_PCREL
9131 || fixP->fx_r_type == BFD_RELOC_X86_64_PC32_BND)
31312f95 9132 && !use_rela_relocations)
252b5132 9133 {
31312f95
AM		 9134 /* This is a hack. There should be a better way to handle this.
9135 This covers for the fact that bfd_install_relocation will
9136 subtract the current location (for partial_inplace, PC relative
9137 relocations); see more below. */
252b5132 9138#ifndef OBJ_AOUT
718ddfc0 9139 if (IS_ELF
252b5132
RH		 9140#ifdef TE_PE
9141 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9142#endif
9143 )
9144 value += fixP->fx_where + fixP->fx_frag->fr_address;
9145#endif
9146#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9147 if (IS_ELF)
252b5132 9148 {
6539b54b 9149 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9150
6539b54b 9151 if ((sym_seg == seg
2f66722d 9152 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9153 && sym_seg != absolute_section))
af65af87 9154 && !generic_force_reloc (fixP))
2f66722d
AM		 9155 {
9156 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9157 bfd_install_relocation subtracts them out again. I think
9158 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9159 it. FIXME. */
9160 value += fixP->fx_where + fixP->fx_frag->fr_address;
9161 }
252b5132
RH		 9162 }
9163#endif
9164#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9165 /* For some reason, the PE format does not store a
9166 section address offset for a PC relative symbol. */
9167 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9168 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9169 value += md_pcrel_from (fixP);
9170#endif
9171 }
fbeb56a4 9172#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9173 if (fixP->fx_addsy != NULL
9174 && S_IS_WEAK (fixP->fx_addsy)
9175 /* PR 16858: Do not modify weak function references. */
9176 && ! fixP->fx_pcrel)
fbeb56a4 9177 {
296a8689
NC		 9178#if !defined (TE_PEP)
9179 /* For x86 PE weak function symbols are neither PC-relative
9180 nor do they set S_IS_FUNCTION. So the only reliable way
9181 to detect them is to check the flags of their containing
9182 section. */
9183 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9184 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9185 ;
9186 else
9187#endif
fbeb56a4
DK		 9188 value -= S_GET_VALUE (fixP->fx_addsy);
9189 }
9190#endif
252b5132
RH		 9191
9192 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9193 and we must not disappoint it. */
252b5132 9194#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9195 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9196 switch (fixP->fx_r_type)
9197 {
9198 case BFD_RELOC_386_PLT32:
3e73aa7c 9199 case BFD_RELOC_X86_64_PLT32:
c3320543 9200 case BFD_RELOC_X86_64_PLT32_BND:
47926f60
KH		 9201 /* Make the jump instruction point to the address of the operand. At
9202 runtime we merely add the offset to the actual PLT entry. */
9203 value = -4;
9204 break;
31312f95 9205
13ae64f3
JJ		 9206 case BFD_RELOC_386_TLS_GD:
9207 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9208 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9209 case BFD_RELOC_386_TLS_IE:
9210 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9211 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9212 case BFD_RELOC_X86_64_TLSGD:
9213 case BFD_RELOC_X86_64_TLSLD:
9214 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9215 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9216 value = 0; /* Fully resolved at runtime. No addend. */
9217 /* Fallthrough */
9218 case BFD_RELOC_386_TLS_LE:
9219 case BFD_RELOC_386_TLS_LDO_32:
9220 case BFD_RELOC_386_TLS_LE_32:
9221 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9222 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9223 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9224 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9225 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9226 break;
9227
67a4f2b7
AO		 9228 case BFD_RELOC_386_TLS_DESC_CALL:
9229 case BFD_RELOC_X86_64_TLSDESC_CALL:
9230 value = 0; /* Fully resolved at runtime. No addend. */
9231 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9232 fixP->fx_done = 0;
9233 return;
9234
00f7efb6
JJ		 9235 case BFD_RELOC_386_GOT32:
9236 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9237 value = 0; /* Fully resolved at runtime. No addend. */
9238 break;
47926f60
KH		 9239
9240 case BFD_RELOC_VTABLE_INHERIT:
9241 case BFD_RELOC_VTABLE_ENTRY:
9242 fixP->fx_done = 0;
94f592af 9243 return;
47926f60
KH		 9244
9245 default:
9246 break;
9247 }
9248#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9249 *valP = value;
f86103b7 9250#endif /* !defined (TE_Mach) */
3e73aa7c 9251
3e73aa7c 9252 /* Are we finished with this relocation now? */
c6682705 9253 if (fixP->fx_addsy == NULL)
3e73aa7c 9254 fixP->fx_done = 1;
fbeb56a4
DK		 9255#if defined (OBJ_COFF) && defined (TE_PE)
9256 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9257 {
9258 fixP->fx_done = 0;
9259 /* Remember value for tc_gen_reloc. */
9260 fixP->fx_addnumber = value;
9261 /* Clear out the frag for now. */
9262 value = 0;
9263 }
9264#endif
3e73aa7c
JH		 9265 else if (use_rela_relocations)
9266 {
9267 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9268 /* Remember value for tc_gen_reloc. */
9269 fixP->fx_addnumber = value;
3e73aa7c
JH		 9270 value = 0;
9271 }
f86103b7 9272
94f592af 9273 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9274}
252b5132 9275\f
252b5132 9276char *
499ac353 9277md_atof (int type, char *litP, int *sizeP)
252b5132 9278{
499ac353
NC		 9279 /* This outputs the LITTLENUMs in REVERSE order;
9280 in accord with the bigendian 386. */
9281 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9282}
9283\f
2d545b82 9284static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9285
252b5132 9286static char *
e3bb37b5 9287output_invalid (int c)
252b5132 9288{
3882b010 9289 if (ISPRINT (c))
f9f21a03
L		 9290 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9291 "'%c'", c);
252b5132 9292 else
f9f21a03 9293 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9294 "(0x%x)", (unsigned char) c);
252b5132
RH		 9295 return output_invalid_buf;
9296}
9297
af6bdddf 9298/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9299
9300static const reg_entry *
4d1bb795 9301parse_real_register (char *reg_string, char **end_op)
252b5132 9302{
af6bdddf
AM		 9303 char *s = reg_string;
9304 char *p;
252b5132
RH		 9305 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9306 const reg_entry *r;
9307
9308 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9309 if (*s == REGISTER_PREFIX)
9310 ++s;
9311
9312 if (is_space_char (*s))
9313 ++s;
9314
9315 p = reg_name_given;
af6bdddf 9316 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9317 {
9318 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9319 return (const reg_entry *) NULL;
9320 s++;
252b5132
RH		 9321 }
9322
6588847e
DN		 9323 /* For naked regs, make sure that we are not dealing with an identifier.
9324 This prevents confusing an identifier like `eax_var' with register
9325 `eax'. */
9326 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9327 return (const reg_entry *) NULL;
9328
af6bdddf 9329 *end_op = s;
252b5132
RH		 9330
9331 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9332
5f47d35b 9333 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9334 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9335 {
5f47d35b
AM		 9336 if (is_space_char (*s))
9337 ++s;
9338 if (*s == '(')
9339 {
af6bdddf 9340 ++s;
5f47d35b
AM		 9341 if (is_space_char (*s))
9342 ++s;
9343 if (*s >= '0' && *s <= '7')
9344 {
db557034 9345 int fpr = *s - '0';
af6bdddf 9346 ++s;
5f47d35b
AM		 9347 if (is_space_char (*s))
9348 ++s;
9349 if (*s == ')')
9350 {
9351 *end_op = s + 1;
1e9cc1c2 9352 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9353 know (r);
9354 return r + fpr;
5f47d35b 9355 }
5f47d35b 9356 }
47926f60 9357 /* We have "%st(" then garbage. */
5f47d35b
AM		 9358 return (const reg_entry *) NULL;
9359 }
9360 }
9361
a60de03c
JB		 9362 if (r == NULL || allow_pseudo_reg)
9363 return r;
9364
0dfbf9d7 9365 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9366 return (const reg_entry *) NULL;
9367
192dc9c6
JB		 9368 if ((r->reg_type.bitfield.reg32
9369 || r->reg_type.bitfield.sreg3
9370 || r->reg_type.bitfield.control
9371 || r->reg_type.bitfield.debug
9372 || r->reg_type.bitfield.test)
9373 && !cpu_arch_flags.bitfield.cpui386)
9374 return (const reg_entry *) NULL;
9375
309d3373
JB		 9376 if (r->reg_type.bitfield.floatreg
9377 && !cpu_arch_flags.bitfield.cpu8087
9378 && !cpu_arch_flags.bitfield.cpu287
9379 && !cpu_arch_flags.bitfield.cpu387)
9380 return (const reg_entry *) NULL;
9381
192dc9c6
JB		 9382 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9383 return (const reg_entry *) NULL;
9384
9385 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9386 return (const reg_entry *) NULL;
9387
40f12533
L		 9388 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9389 return (const reg_entry *) NULL;
9390
43234a1e
L		 9391 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9392 && !cpu_arch_flags.bitfield.cpuavx512f)
9393 return (const reg_entry *) NULL;
9394
db51cc60 9395 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9396 if (!allow_index_reg
db51cc60
L		 9397 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9398 return (const reg_entry *) NULL;
9399
43234a1e
L		 9400 /* Upper 16 vector register is only available with VREX in 64bit
9401 mode. */
9402 if ((r->reg_flags & RegVRex))
9403 {
9404 if (!cpu_arch_flags.bitfield.cpuvrex
9405 || flag_code != CODE_64BIT)
9406 return (const reg_entry *) NULL;
9407
9408 i.need_vrex = 1;
9409 }
9410
a60de03c
JB		 9411 if (((r->reg_flags & (RegRex64 | RegRex))
9412 || r->reg_type.bitfield.reg64)
40fb9820 9413 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9414 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9415 && flag_code != CODE_64BIT)
20f0a1fc 9416 return (const reg_entry *) NULL;
1ae00879 9417
b7240065
JB		 9418 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9419 return (const reg_entry *) NULL;
9420
252b5132
RH		 9421 return r;
9422}
4d1bb795
JB		 9423
9424/* REG_STRING starts *before* REGISTER_PREFIX. */
9425
9426static const reg_entry *
9427parse_register (char *reg_string, char **end_op)
9428{
9429 const reg_entry *r;
9430
9431 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9432 r = parse_real_register (reg_string, end_op);
9433 else
9434 r = NULL;
9435 if (!r)
9436 {
9437 char *save = input_line_pointer;
9438 char c;
9439 symbolS *symbolP;
9440
9441 input_line_pointer = reg_string;
9442 c = get_symbol_end ();
9443 symbolP = symbol_find (reg_string);
9444 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9445 {
9446 const expressionS *e = symbol_get_value_expression (symbolP);
9447
0398aac5 9448 know (e->X_op == O_register);
4eed87de 9449 know (e->X_add_number >= 0
c3fe08fa 9450 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9451 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9452 if ((r->reg_flags & RegVRex))
9453 i.need_vrex = 1;
4d1bb795
JB		 9454 *end_op = input_line_pointer;
9455 }
9456 *input_line_pointer = c;
9457 input_line_pointer = save;
9458 }
9459 return r;
9460}
9461
9462int
9463i386_parse_name (char *name, expressionS *e, char *nextcharP)
9464{
9465 const reg_entry *r;
9466 char *end = input_line_pointer;
9467
9468 *end = *nextcharP;
9469 r = parse_register (name, &input_line_pointer);
9470 if (r && end <= input_line_pointer)
9471 {
9472 *nextcharP = *input_line_pointer;
9473 *input_line_pointer = 0;
9474 e->X_op = O_register;
9475 e->X_add_number = r - i386_regtab;
9476 return 1;
9477 }
9478 input_line_pointer = end;
9479 *end = 0;
ee86248c 9480 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9481}
9482
9483void
9484md_operand (expressionS *e)
9485{
ee86248c
JB		 9486 char *end;
9487 const reg_entry *r;
4d1bb795 9488
ee86248c
JB		 9489 switch (*input_line_pointer)
9490 {
9491 case REGISTER_PREFIX:
9492 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9493 if (r)
9494 {
9495 e->X_op = O_register;
9496 e->X_add_number = r - i386_regtab;
9497 input_line_pointer = end;
9498 }
ee86248c
JB		 9499 break;
9500
9501 case '[':
9c2799c2 9502 gas_assert (intel_syntax);
ee86248c
JB		 9503 end = input_line_pointer++;
9504 expression (e);
9505 if (*input_line_pointer == ']')
9506 {
9507 ++input_line_pointer;
9508 e->X_op_symbol = make_expr_symbol (e);
9509 e->X_add_symbol = NULL;
9510 e->X_add_number = 0;
9511 e->X_op = O_index;
9512 }
9513 else
9514 {
9515 e->X_op = O_absent;
9516 input_line_pointer = end;
9517 }
9518 break;
4d1bb795
JB		 9519 }
9520}
9521
252b5132 9522\f
4cc782b5 9523#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9524const char *md_shortopts = "kVQ:sqn";
252b5132 9525#else
12b55ccc 9526const char *md_shortopts = "qn";
252b5132 9527#endif
6e0b89ee 9528
3e73aa7c 9529#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9530#define OPTION_64 (OPTION_MD_BASE + 1)
9531#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9532#define OPTION_MARCH (OPTION_MD_BASE + 3)
9533#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9534#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9535#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9536#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9537#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9538#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9539#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9540#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9541#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9542#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9543#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9544#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9545#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9546#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9547#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
a5094208 9548#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
b3b91714 9549
99ad8390
NC		 9550struct option md_longopts[] =
9551{
3e73aa7c 9552 {"32", no_argument, NULL, OPTION_32},
321098a5 9553#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9554 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9555 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9556#endif
9557#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9558 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 9559#endif
b3b91714 9560 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9561 {"march", required_argument, NULL, OPTION_MARCH},
9562 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9563 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9564 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9565 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9566 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9567 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9568 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9569 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9570 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9571 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9572 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9573 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9574 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9575# if defined (TE_PE) || defined (TE_PEP)
9576 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9577#endif
a5094208 9578 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
252b5132
RH		 9579 {NULL, no_argument, NULL, 0}
9580};
9581size_t md_longopts_size = sizeof (md_longopts);
9582
9583int
9103f4f4 9584md_parse_option (int c, char *arg)
252b5132 9585{
91d6fa6a 9586 unsigned int j;
6305a203 9587 char *arch, *next;
9103f4f4 9588
252b5132
RH		 9589 switch (c)
9590 {
12b55ccc
L		 9591 case 'n':
9592 optimize_align_code = 0;
9593 break;
9594
a38cf1db
AM		 9595 case 'q':
9596 quiet_warnings = 1;
252b5132
RH		 9597 break;
9598
9599#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9600 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9601 should be emitted or not. FIXME: Not implemented. */
9602 case 'Q':
252b5132
RH		 9603 break;
9604
9605 /* -V: SVR4 argument to print version ID. */
9606 case 'V':
9607 print_version_id ();
9608 break;
9609
a38cf1db
AM		 9610 /* -k: Ignore for FreeBSD compatibility. */
9611 case 'k':
252b5132 9612 break;
4cc782b5
ILT		 9613
9614 case 's':
9615 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9616 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9617 break;
99ad8390 9618#endif
321098a5 9619#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9620 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9621 case OPTION_64:
9622 {
9623 const char **list, **l;
9624
3e73aa7c
JH		 9625 list = bfd_target_list ();
9626 for (l = list; *l != NULL; l++)
8620418b 9627 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9628 || strcmp (*l, "coff-x86-64") == 0
9629 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9630 || strcmp (*l, "pei-x86-64") == 0
9631 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9632 {
9633 default_arch = "x86_64";
9634 break;
9635 }
3e73aa7c 9636 if (*l == NULL)
2b5d6a91 9637 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9638 free (list);
9639 }
9640 break;
9641#endif
252b5132 9642
351f65ca 9643#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9644 case OPTION_X32:
351f65ca
L		 9645 if (IS_ELF)
9646 {
9647 const char **list, **l;
9648
9649 list = bfd_target_list ();
9650 for (l = list; *l != NULL; l++)
9651 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9652 {
9653 default_arch = "x86_64:32";
9654 break;
9655 }
9656 if (*l == NULL)
2b5d6a91 9657 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9658 free (list);
9659 }
9660 else
9661 as_fatal (_("32bit x86_64 is only supported for ELF"));
9662 break;
9663#endif
9664
6e0b89ee
AM		 9665 case OPTION_32:
9666 default_arch = "i386";
9667 break;
9668
b3b91714
AM		 9669 case OPTION_DIVIDE:
9670#ifdef SVR4_COMMENT_CHARS
9671 {
9672 char *n, *t;
9673 const char *s;
9674
9675 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9676 t = n;
9677 for (s = i386_comment_chars; *s != '\0'; s++)
9678 if (*s != '/')
9679 *t++ = *s;
9680 *t = '\0';
9681 i386_comment_chars = n;
9682 }
9683#endif
9684 break;
9685
9103f4f4 9686 case OPTION_MARCH:
6305a203
L		 9687 arch = xstrdup (arg);
9688 do
9103f4f4 9689 {
6305a203 9690 if (*arch == '.')
2b5d6a91 9691 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9692 next = strchr (arch, '+');
9693 if (next)
9694 *next++ = '\0';
91d6fa6a 9695 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9696 {
91d6fa6a 9697 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9698 {
6305a203 9699 /* Processor. */
1ded5609
JB		 9700 if (! cpu_arch[j].flags.bitfield.cpui386)
9701 continue;
9702
91d6fa6a 9703 cpu_arch_name = cpu_arch[j].name;
6305a203 9704 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9705 cpu_arch_flags = cpu_arch[j].flags;
9706 cpu_arch_isa = cpu_arch[j].type;
9707 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9708 if (!cpu_arch_tune_set)
9709 {
9710 cpu_arch_tune = cpu_arch_isa;
9711 cpu_arch_tune_flags = cpu_arch_isa_flags;
9712 }
9713 break;
9714 }
91d6fa6a
NC		 9715 else if (*cpu_arch [j].name == '.'
9716 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9717 {
9718 /* ISA entension. */
9719 i386_cpu_flags flags;
309d3373 9720
49021df2 9721 if (!cpu_arch[j].negated)
309d3373 9722 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9723 cpu_arch[j].flags);
309d3373
JB		 9724 else
9725 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9726 cpu_arch[j].flags);
0dfbf9d7 9727 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9728 {
9729 if (cpu_sub_arch_name)
9730 {
9731 char *name = cpu_sub_arch_name;
9732 cpu_sub_arch_name = concat (name,
91d6fa6a 9733 cpu_arch[j].name,
1bf57e9f 9734 (const char *) NULL);
6305a203
L		 9735 free (name);
9736 }
9737 else
91d6fa6a 9738 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9739 cpu_arch_flags = flags;
a586129e 9740 cpu_arch_isa_flags = flags;
6305a203
L		 9741 }
9742 break;
ccc9c027 9743 }
9103f4f4 9744 }
6305a203 9745
91d6fa6a 9746 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9747 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9748
9749 arch = next;
9103f4f4 9750 }
6305a203 9751 while (next != NULL );
9103f4f4
L		 9752 break;
9753
9754 case OPTION_MTUNE:
9755 if (*arg == '.')
2b5d6a91 9756 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9757 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9758 {
91d6fa6a 9759 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9760 {
ccc9c027 9761 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9762 cpu_arch_tune = cpu_arch [j].type;
9763 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9764 break;
9765 }
9766 }
91d6fa6a 9767 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9768 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9769 break;
9770
1efbbeb4
L		 9771 case OPTION_MMNEMONIC:
9772 if (strcasecmp (arg, "att") == 0)
9773 intel_mnemonic = 0;
9774 else if (strcasecmp (arg, "intel") == 0)
9775 intel_mnemonic = 1;
9776 else
2b5d6a91 9777 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9778 break;
9779
9780 case OPTION_MSYNTAX:
9781 if (strcasecmp (arg, "att") == 0)
9782 intel_syntax = 0;
9783 else if (strcasecmp (arg, "intel") == 0)
9784 intel_syntax = 1;
9785 else
2b5d6a91 9786 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9787 break;
9788
9789 case OPTION_MINDEX_REG:
9790 allow_index_reg = 1;
9791 break;
9792
9793 case OPTION_MNAKED_REG:
9794 allow_naked_reg = 1;
9795 break;
9796
9797 case OPTION_MOLD_GCC:
9798 old_gcc = 1;
1efbbeb4
L		 9799 break;
9800
c0f3af97
L		 9801 case OPTION_MSSE2AVX:
9802 sse2avx = 1;
9803 break;
9804
daf50ae7
L		 9805 case OPTION_MSSE_CHECK:
9806 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9807 sse_check = check_error;
daf50ae7 9808 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9809 sse_check = check_warning;
daf50ae7 9810 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9811 sse_check = check_none;
daf50ae7 9812 else
2b5d6a91 9813 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9814 break;
9815
7bab8ab5
JB		 9816 case OPTION_MOPERAND_CHECK:
9817 if (strcasecmp (arg, "error") == 0)
9818 operand_check = check_error;
9819 else if (strcasecmp (arg, "warning") == 0)
9820 operand_check = check_warning;
9821 else if (strcasecmp (arg, "none") == 0)
9822 operand_check = check_none;
9823 else
9824 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9825 break;
9826
539f890d
L		 9827 case OPTION_MAVXSCALAR:
9828 if (strcasecmp (arg, "128") == 0)
9829 avxscalar = vex128;
9830 else if (strcasecmp (arg, "256") == 0)
9831 avxscalar = vex256;
9832 else
2b5d6a91 9833 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9834 break;
9835
7e8b059b
L		 9836 case OPTION_MADD_BND_PREFIX:
9837 add_bnd_prefix = 1;
9838 break;
9839
43234a1e
L		 9840 case OPTION_MEVEXLIG:
9841 if (strcmp (arg, "128") == 0)
9842 evexlig = evexl128;
9843 else if (strcmp (arg, "256") == 0)
9844 evexlig = evexl256;
9845 else if (strcmp (arg, "512") == 0)
9846 evexlig = evexl512;
9847 else
9848 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9849 break;
9850
9851 case OPTION_MEVEXWIG:
9852 if (strcmp (arg, "0") == 0)
9853 evexwig = evexw0;
9854 else if (strcmp (arg, "1") == 0)
9855 evexwig = evexw1;
9856 else
9857 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9858 break;
9859
167ad85b
TG		 9860# if defined (TE_PE) || defined (TE_PEP)
9861 case OPTION_MBIG_OBJ:
9862 use_big_obj = 1;
9863 break;
9864#endif
9865
a5094208 9866 case OPTION_OMIT_LOCK_PREFIX:
d022bddd
IT		 9867 if (strcasecmp (arg, "yes") == 0)
9868 omit_lock_prefix = 1;
9869 else if (strcasecmp (arg, "no") == 0)
9870 omit_lock_prefix = 0;
9871 else
9872 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9873 break;
9874
252b5132
RH		 9875 default:
9876 return 0;
9877 }
9878 return 1;
9879}
9880
8a2c8fef
L		 9881#define MESSAGE_TEMPLATE \
9882" "
9883
9884static void
1ded5609 9885show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9886{
9887 static char message[] = MESSAGE_TEMPLATE;
9888 char *start = message + 27;
9889 char *p;
9890 int size = sizeof (MESSAGE_TEMPLATE);
9891 int left;
9892 const char *name;
9893 int len;
9894 unsigned int j;
9895
9896 p = start;
9897 left = size - (start - message);
9898 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9899 {
9900 /* Should it be skipped? */
9901 if (cpu_arch [j].skip)
9902 continue;
9903
9904 name = cpu_arch [j].name;
9905 len = cpu_arch [j].len;
9906 if (*name == '.')
9907 {
9908 /* It is an extension. Skip if we aren't asked to show it. */
9909 if (ext)
9910 {
9911 name++;
9912 len--;
9913 }
9914 else
9915 continue;
9916 }
9917 else if (ext)
9918 {
9919 /* It is an processor. Skip if we show only extension. */
9920 continue;
9921 }
1ded5609
JB		 9922 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9923 {
9924 /* It is an impossible processor - skip. */
9925 continue;
9926 }
8a2c8fef
L		 9927
9928 /* Reserve 2 spaces for ", " or ",\0" */
9929 left -= len + 2;
9930
9931 /* Check if there is any room. */
9932 if (left >= 0)
9933 {
9934 if (p != start)
9935 {
9936 *p++ = ',';
9937 *p++ = ' ';
9938 }
9939 p = mempcpy (p, name, len);
9940 }
9941 else
9942 {
9943 /* Output the current message now and start a new one. */
9944 *p++ = ',';
9945 *p = '\0';
9946 fprintf (stream, "%s\n", message);
9947 p = start;
9948 left = size - (start - message) - len - 2;
8d63c93e 9949
8a2c8fef
L		 9950 gas_assert (left >= 0);
9951
9952 p = mempcpy (p, name, len);
9953 }
9954 }
9955
9956 *p = '\0';
9957 fprintf (stream, "%s\n", message);
9958}
9959
252b5132 9960void
8a2c8fef 9961md_show_usage (FILE *stream)
252b5132 9962{
4cc782b5
ILT		 9963#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9964 fprintf (stream, _("\
a38cf1db
AM		 9965 -Q ignored\n\
9966 -V print assembler version number\n\
b3b91714
AM		 9967 -k ignored\n"));
9968#endif
9969 fprintf (stream, _("\
12b55ccc 9970 -n Do not optimize code alignment\n\
b3b91714
AM		 9971 -q quieten some warnings\n"));
9972#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9973 fprintf (stream, _("\
a38cf1db 9974 -s ignored\n"));
b3b91714 9975#endif
321098a5
L		 9976#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9977 || defined (TE_PE) || defined (TE_PEP))
751d281c 9978 fprintf (stream, _("\
570561f7 9979 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 9980#endif
b3b91714
AM		 9981#ifdef SVR4_COMMENT_CHARS
9982 fprintf (stream, _("\
9983 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 9984#else
9985 fprintf (stream, _("\
b3b91714 9986 --divide ignored\n"));
4cc782b5 9987#endif
9103f4f4 9988 fprintf (stream, _("\
6305a203 9989 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 9990 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 9991 show_arch (stream, 0, 1);
8a2c8fef
L		 9992 fprintf (stream, _("\
9993 EXTENSION is combination of:\n"));
1ded5609 9994 show_arch (stream, 1, 0);
6305a203 9995 fprintf (stream, _("\
8a2c8fef 9996 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 9997 show_arch (stream, 0, 0);
ba104c83 9998 fprintf (stream, _("\
c0f3af97
L		 9999 -msse2avx encode SSE instructions with VEX prefix\n"));
10000 fprintf (stream, _("\
daf50ae7
L		 10001 -msse-check=[none|error|warning]\n\
10002 check SSE instructions\n"));
10003 fprintf (stream, _("\
7bab8ab5
JB		 10004 -moperand-check=[none|error|warning]\n\
10005 check operand combinations for validity\n"));
10006 fprintf (stream, _("\
539f890d
L		 10007 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10008 length\n"));
10009 fprintf (stream, _("\
43234a1e
L		 10010 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10011 length\n"));
10012 fprintf (stream, _("\
10013 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10014 for EVEX.W bit ignored instructions\n"));
10015 fprintf (stream, _("\
ba104c83
L		 10016 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10017 fprintf (stream, _("\
10018 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10019 fprintf (stream, _("\
10020 -mindex-reg support pseudo index registers\n"));
10021 fprintf (stream, _("\
10022 -mnaked-reg don't require `%%' prefix for registers\n"));
10023 fprintf (stream, _("\
10024 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10025 fprintf (stream, _("\
10026 -madd-bnd-prefix add BND prefix for all valid branches\n"));
167ad85b
TG		 10027# if defined (TE_PE) || defined (TE_PEP)
10028 fprintf (stream, _("\
10029 -mbig-obj generate big object files\n"));
10030#endif
d022bddd
IT		 10031 fprintf (stream, _("\
10032 -momit-lock-prefix=[no|yes]\n\
10033 strip all lock prefixes\n"));
252b5132
RH		 10034}
10035
3e73aa7c 10036#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10037 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10038 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10039
10040/* Pick the target format to use. */
10041
47926f60 10042const char *
e3bb37b5 10043i386_target_format (void)
252b5132 10044{
351f65ca
L		 10045 if (!strncmp (default_arch, "x86_64", 6))
10046 {
10047 update_code_flag (CODE_64BIT, 1);
10048 if (default_arch[6] == '\0')
7f56bc95 10049 x86_elf_abi = X86_64_ABI;
351f65ca 10050 else
7f56bc95 10051 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10052 }
3e73aa7c 10053 else if (!strcmp (default_arch, "i386"))
78f12dd3 10054 update_code_flag (CODE_32BIT, 1);
3e73aa7c 10055 else
2b5d6a91 10056 as_fatal (_("unknown architecture"));
89507696
JB		 10057
10058 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10059 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10060 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10061 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10062
252b5132
RH		 10063 switch (OUTPUT_FLAVOR)
10064 {
9384f2ff 10065#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10066 case bfd_target_aout_flavour:
47926f60 10067 return AOUT_TARGET_FORMAT;
4c63da97 10068#endif
9384f2ff
AM		 10069#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10070# if defined (TE_PE) || defined (TE_PEP)
10071 case bfd_target_coff_flavour:
167ad85b
TG		 10072 if (flag_code == CODE_64BIT)
10073 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10074 else
10075 return "pe-i386";
9384f2ff 10076# elif defined (TE_GO32)
0561d57c
JK		 10077 case bfd_target_coff_flavour:
10078 return "coff-go32";
9384f2ff 10079# else
252b5132
RH		 10080 case bfd_target_coff_flavour:
10081 return "coff-i386";
9384f2ff 10082# endif
4c63da97 10083#endif
3e73aa7c 10084#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10085 case bfd_target_elf_flavour:
3e73aa7c 10086 {
351f65ca
L		 10087 const char *format;
10088
10089 switch (x86_elf_abi)
4fa24527 10090 {
351f65ca
L		 10091 default:
10092 format = ELF_TARGET_FORMAT;
10093 break;
7f56bc95 10094 case X86_64_ABI:
351f65ca 10095 use_rela_relocations = 1;
4fa24527 10096 object_64bit = 1;
351f65ca
L		 10097 format = ELF_TARGET_FORMAT64;
10098 break;
7f56bc95 10099 case X86_64_X32_ABI:
4fa24527 10100 use_rela_relocations = 1;
351f65ca 10101 object_64bit = 1;
862be3fb 10102 disallow_64bit_reloc = 1;
351f65ca
L		 10103 format = ELF_TARGET_FORMAT32;
10104 break;
4fa24527 10105 }
3632d14b 10106 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10107 {
7f56bc95 10108 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10109 as_fatal (_("Intel L1OM is 64bit only"));
10110 return ELF_TARGET_L1OM_FORMAT;
10111 }
7a9068fe
L		 10112 if (cpu_arch_isa == PROCESSOR_K1OM)
10113 {
10114 if (x86_elf_abi != X86_64_ABI)
10115 as_fatal (_("Intel K1OM is 64bit only"));
10116 return ELF_TARGET_K1OM_FORMAT;
10117 }
8a9036a4 10118 else
351f65ca 10119 return format;
3e73aa7c 10120 }
e57f8c65
TG		 10121#endif
10122#if defined (OBJ_MACH_O)
10123 case bfd_target_mach_o_flavour:
d382c579
TG		 10124 if (flag_code == CODE_64BIT)
10125 {
10126 use_rela_relocations = 1;
10127 object_64bit = 1;
10128 return "mach-o-x86-64";
10129 }
10130 else
10131 return "mach-o-i386";
4c63da97 10132#endif
252b5132
RH		 10133 default:
10134 abort ();
10135 return NULL;
10136 }
10137}
10138
47926f60 10139#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 10140
10141#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 10142void
10143i386_elf_emit_arch_note (void)
a847613f 10144{
718ddfc0 10145 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 10146 {
10147 char *p;
10148 asection *seg = now_seg;
10149 subsegT subseg = now_subseg;
10150 Elf_Internal_Note i_note;
10151 Elf_External_Note e_note;
10152 asection *note_secp;
10153 int len;
10154
10155 /* Create the .note section. */
10156 note_secp = subseg_new (".note", 0);
10157 bfd_set_section_flags (stdoutput,
10158 note_secp,
10159 SEC_HAS_CONTENTS | SEC_READONLY);
10160
10161 /* Process the arch string. */
10162 len = strlen (cpu_arch_name);
10163
10164 i_note.namesz = len + 1;
10165 i_note.descsz = 0;
10166 i_note.type = NT_ARCH;
10167 p = frag_more (sizeof (e_note.namesz));
10168 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10169 p = frag_more (sizeof (e_note.descsz));
10170 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10171 p = frag_more (sizeof (e_note.type));
10172 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10173 p = frag_more (len + 1);
10174 strcpy (p, cpu_arch_name);
10175
10176 frag_align (2, 0, 0);
10177
10178 subseg_set (seg, subseg);
10179 }
10180}
10181#endif
252b5132 10182\f
252b5132 10183symbolS *
7016a5d5 10184md_undefined_symbol (char *name)
252b5132 10185{
18dc2407
ILT		 10186 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10187 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10188 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10189 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10190 {
10191 if (!GOT_symbol)
10192 {
10193 if (symbol_find (name))
10194 as_bad (_("GOT already in symbol table"));
10195 GOT_symbol = symbol_new (name, undefined_section,
10196 (valueT) 0, &zero_address_frag);
10197 };
10198 return GOT_symbol;
10199 }
252b5132
RH		 10200 return 0;
10201}
10202
10203/* Round up a section size to the appropriate boundary. */
47926f60 10204
252b5132 10205valueT
7016a5d5 10206md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10207{
4c63da97
AM		 10208#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10209 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10210 {
10211 /* For a.out, force the section size to be aligned. If we don't do
10212 this, BFD will align it for us, but it will not write out the
10213 final bytes of the section. This may be a bug in BFD, but it is
10214 easier to fix it here since that is how the other a.out targets
10215 work. */
10216 int align;
10217
10218 align = bfd_get_section_alignment (stdoutput, segment);
10219 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10220 }
252b5132
RH		 10221#endif
10222
10223 return size;
10224}
10225
10226/* On the i386, PC-relative offsets are relative to the start of the
10227 next instruction. That is, the address of the offset, plus its
10228 size, since the offset is always the last part of the insn. */
10229
10230long
e3bb37b5 10231md_pcrel_from (fixS *fixP)
252b5132
RH		 10232{
10233 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10234}
10235
10236#ifndef I386COFF
10237
10238static void
e3bb37b5 10239s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10240{
29b0f896 10241 int temp;
252b5132 10242
8a75718c
JB		 10243#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10244 if (IS_ELF)
10245 obj_elf_section_change_hook ();
10246#endif
252b5132
RH		 10247 temp = get_absolute_expression ();
10248 subseg_set (bss_section, (subsegT) temp);
10249 demand_empty_rest_of_line ();
10250}
10251
10252#endif
10253
252b5132 10254void
e3bb37b5 10255i386_validate_fix (fixS *fixp)
252b5132
RH		 10256{
10257 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10258 {
23df1078
JH		 10259 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10260 {
4fa24527 10261 if (!object_64bit)
23df1078
JH		 10262 abort ();
10263 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10264 }
10265 else
10266 {
4fa24527 10267 if (!object_64bit)
d6ab8113
JB		 10268 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10269 else
10270 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10271 }
252b5132
RH		 10272 fixp->fx_subsy = 0;
10273 }
10274}
10275
252b5132 10276arelent *
7016a5d5 10277tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10278{
10279 arelent *rel;
10280 bfd_reloc_code_real_type code;
10281
10282 switch (fixp->fx_r_type)
10283 {
8ce3d284 10284#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10285 case BFD_RELOC_SIZE32:
10286 case BFD_RELOC_SIZE64:
10287 if (S_IS_DEFINED (fixp->fx_addsy)
10288 && !S_IS_EXTERNAL (fixp->fx_addsy))
10289 {
10290 /* Resolve size relocation against local symbol to size of
10291 the symbol plus addend. */
10292 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10293 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10294 && !fits_in_unsigned_long (value))
10295 as_bad_where (fixp->fx_file, fixp->fx_line,
10296 _("symbol size computation overflow"));
10297 fixp->fx_addsy = NULL;
10298 fixp->fx_subsy = NULL;
10299 md_apply_fix (fixp, (valueT *) &value, NULL);
10300 return NULL;
10301 }
8ce3d284 10302#endif
8fd4256d 10303
3e73aa7c 10304 case BFD_RELOC_X86_64_PLT32:
c3320543 10305 case BFD_RELOC_X86_64_PLT32_BND:
3e73aa7c
JH		 10306 case BFD_RELOC_X86_64_GOT32:
10307 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10308 case BFD_RELOC_386_PLT32:
10309 case BFD_RELOC_386_GOT32:
10310 case BFD_RELOC_386_GOTOFF:
10311 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10312 case BFD_RELOC_386_TLS_GD:
10313 case BFD_RELOC_386_TLS_LDM:
10314 case BFD_RELOC_386_TLS_LDO_32:
10315 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10316 case BFD_RELOC_386_TLS_IE:
10317 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10318 case BFD_RELOC_386_TLS_LE_32:
10319 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10320 case BFD_RELOC_386_TLS_GOTDESC:
10321 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10322 case BFD_RELOC_X86_64_TLSGD:
10323 case BFD_RELOC_X86_64_TLSLD:
10324 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10325 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10326 case BFD_RELOC_X86_64_GOTTPOFF:
10327 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10328 case BFD_RELOC_X86_64_TPOFF64:
10329 case BFD_RELOC_X86_64_GOTOFF64:
10330 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10331 case BFD_RELOC_X86_64_GOT64:
10332 case BFD_RELOC_X86_64_GOTPCREL64:
10333 case BFD_RELOC_X86_64_GOTPC64:
10334 case BFD_RELOC_X86_64_GOTPLT64:
10335 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10336 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10337 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10338 case BFD_RELOC_RVA:
10339 case BFD_RELOC_VTABLE_ENTRY:
10340 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10341#ifdef TE_PE
10342 case BFD_RELOC_32_SECREL:
10343#endif
252b5132
RH		 10344 code = fixp->fx_r_type;
10345 break;
dbbaec26
L		 10346 case BFD_RELOC_X86_64_32S:
10347 if (!fixp->fx_pcrel)
10348 {
10349 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10350 code = fixp->fx_r_type;
10351 break;
10352 }
252b5132 10353 default:
93382f6d 10354 if (fixp->fx_pcrel)
252b5132 10355 {
93382f6d
AM		 10356 switch (fixp->fx_size)
10357 {
10358 default:
b091f402
AM		 10359 as_bad_where (fixp->fx_file, fixp->fx_line,
10360 _("can not do %d byte pc-relative relocation"),
10361 fixp->fx_size);
93382f6d
AM		 10362 code = BFD_RELOC_32_PCREL;
10363 break;
10364 case 1: code = BFD_RELOC_8_PCREL; break;
10365 case 2: code = BFD_RELOC_16_PCREL; break;
c3320543
L		 10366 case 4:
10367 code = (fixp->fx_r_type == BFD_RELOC_X86_64_PC32_BND
10368 ? fixp-> fx_r_type : BFD_RELOC_32_PCREL);
10369 break;
d6ab8113
JB		 10370#ifdef BFD64
10371 case 8: code = BFD_RELOC_64_PCREL; break;
10372#endif
93382f6d
AM		 10373 }
10374 }
10375 else
10376 {
10377 switch (fixp->fx_size)
10378 {
10379 default:
b091f402
AM		 10380 as_bad_where (fixp->fx_file, fixp->fx_line,
10381 _("can not do %d byte relocation"),
10382 fixp->fx_size);
93382f6d
AM		 10383 code = BFD_RELOC_32;
10384 break;
10385 case 1: code = BFD_RELOC_8; break;
10386 case 2: code = BFD_RELOC_16; break;
10387 case 4: code = BFD_RELOC_32; break;
937149dd 10388#ifdef BFD64
3e73aa7c 10389 case 8: code = BFD_RELOC_64; break;
937149dd 10390#endif
93382f6d 10391 }
252b5132
RH		 10392 }
10393 break;
10394 }
252b5132 10395
d182319b
JB		 10396 if ((code == BFD_RELOC_32
10397 || code == BFD_RELOC_32_PCREL
10398 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10399 && GOT_symbol
10400 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10401 {
4fa24527 10402 if (!object_64bit)
d6ab8113
JB		 10403 code = BFD_RELOC_386_GOTPC;
10404 else
10405 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10406 }
7b81dfbb
AJ		 10407 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10408 && GOT_symbol
10409 && fixp->fx_addsy == GOT_symbol)
10410 {
10411 code = BFD_RELOC_X86_64_GOTPC64;
10412 }
252b5132
RH		 10413
10414 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10415 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10416 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10417
10418 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10419
3e73aa7c
JH		 10420 if (!use_rela_relocations)
10421 {
10422 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10423 vtable entry to be used in the relocation's section offset. */
10424 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10425 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10426#if defined (OBJ_COFF) && defined (TE_PE)
10427 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10428 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10429 else
10430#endif
c6682705 10431 rel->addend = 0;
3e73aa7c
JH		 10432 }
10433 /* Use the rela in 64bit mode. */
252b5132 10434 else
3e73aa7c 10435 {
862be3fb
L		 10436 if (disallow_64bit_reloc)
10437 switch (code)
10438 {
862be3fb
L		 10439 case BFD_RELOC_X86_64_DTPOFF64:
10440 case BFD_RELOC_X86_64_TPOFF64:
10441 case BFD_RELOC_64_PCREL:
10442 case BFD_RELOC_X86_64_GOTOFF64:
10443 case BFD_RELOC_X86_64_GOT64:
10444 case BFD_RELOC_X86_64_GOTPCREL64:
10445 case BFD_RELOC_X86_64_GOTPC64:
10446 case BFD_RELOC_X86_64_GOTPLT64:
10447 case BFD_RELOC_X86_64_PLTOFF64:
10448 as_bad_where (fixp->fx_file, fixp->fx_line,
10449 _("cannot represent relocation type %s in x32 mode"),
10450 bfd_get_reloc_code_name (code));
10451 break;
10452 default:
10453 break;
10454 }
10455
062cd5e7
AS		 10456 if (!fixp->fx_pcrel)
10457 rel->addend = fixp->fx_offset;
10458 else
10459 switch (code)
10460 {
10461 case BFD_RELOC_X86_64_PLT32:
c3320543 10462 case BFD_RELOC_X86_64_PLT32_BND:
062cd5e7
AS		 10463 case BFD_RELOC_X86_64_GOT32:
10464 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10465 case BFD_RELOC_X86_64_TLSGD:
10466 case BFD_RELOC_X86_64_TLSLD:
10467 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10468 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10469 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10470 rel->addend = fixp->fx_offset - fixp->fx_size;
10471 break;
10472 default:
10473 rel->addend = (section->vma
10474 - fixp->fx_size
10475 + fixp->fx_addnumber
10476 + md_pcrel_from (fixp));
10477 break;
10478 }
3e73aa7c
JH		 10479 }
10480
252b5132
RH		 10481 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10482 if (rel->howto == NULL)
10483 {
10484 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10485 _("cannot represent relocation type %s"),
252b5132
RH		 10486 bfd_get_reloc_code_name (code));
10487 /* Set howto to a garbage value so that we can keep going. */
10488 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10489 gas_assert (rel->howto != NULL);
252b5132
RH		 10490 }
10491
10492 return rel;
10493}
10494
ee86248c 10495#include "tc-i386-intel.c"
54cfded0 10496
a60de03c
JB		 10497void
10498tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10499{
a60de03c
JB		 10500 int saved_naked_reg;
10501 char saved_register_dot;
54cfded0 10502
a60de03c
JB		 10503 saved_naked_reg = allow_naked_reg;
10504 allow_naked_reg = 1;
10505 saved_register_dot = register_chars['.'];
10506 register_chars['.'] = '.';
10507 allow_pseudo_reg = 1;
10508 expression_and_evaluate (exp);
10509 allow_pseudo_reg = 0;
10510 register_chars['.'] = saved_register_dot;
10511 allow_naked_reg = saved_naked_reg;
10512
e96d56a1 10513 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10514 {
a60de03c
JB		 10515 if ((addressT) exp->X_add_number < i386_regtab_size)
10516 {
10517 exp->X_op = O_constant;
10518 exp->X_add_number = i386_regtab[exp->X_add_number]
10519 .dw2_regnum[flag_code >> 1];
10520 }
10521 else
10522 exp->X_op = O_illegal;
54cfded0 10523 }
54cfded0
AM		 10524}
10525
10526void
10527tc_x86_frame_initial_instructions (void)
10528{
a60de03c
JB		 10529 static unsigned int sp_regno[2];
10530
10531 if (!sp_regno[flag_code >> 1])
10532 {
10533 char *saved_input = input_line_pointer;
10534 char sp[][4] = {"esp", "rsp"};
10535 expressionS exp;
a4447b93 10536
a60de03c
JB		 10537 input_line_pointer = sp[flag_code >> 1];
10538 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10539 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10540 sp_regno[flag_code >> 1] = exp.X_add_number;
10541 input_line_pointer = saved_input;
10542 }
a4447b93 10543
61ff971f
L		 10544 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10545 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10546}
d2b2c203 10547
d7921315
L		 10548int
10549x86_dwarf2_addr_size (void)
10550{
10551#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10552 if (x86_elf_abi == X86_64_X32_ABI)
10553 return 4;
10554#endif
10555 return bfd_arch_bits_per_address (stdoutput) / 8;
10556}
10557
d2b2c203
DJ		 10558int
10559i386_elf_section_type (const char *str, size_t len)
10560{
10561 if (flag_code == CODE_64BIT
10562 && len == sizeof ("unwind") - 1
10563 && strncmp (str, "unwind", 6) == 0)
10564 return SHT_X86_64_UNWIND;
10565
10566 return -1;
10567}
bb41ade5 10568
ad5fec3b
EB		 10569#ifdef TE_SOLARIS
10570void
10571i386_solaris_fix_up_eh_frame (segT sec)
10572{
10573 if (flag_code == CODE_64BIT)
10574 elf_section_type (sec) = SHT_X86_64_UNWIND;
10575}
10576#endif
10577
bb41ade5
AM		 10578#ifdef TE_PE
10579void
10580tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10581{
91d6fa6a 10582 expressionS exp;
bb41ade5 10583
91d6fa6a
NC		 10584 exp.X_op = O_secrel;
10585 exp.X_add_symbol = symbol;
10586 exp.X_add_number = 0;
10587 emit_expr (&exp, size);
bb41ade5
AM		 10588}
10589#endif
3b22753a
L		 10590
10591#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10592/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10593
01e1a5bc 10594bfd_vma
3b22753a
L		 10595x86_64_section_letter (int letter, char **ptr_msg)
10596{
10597 if (flag_code == CODE_64BIT)
10598 {
10599 if (letter == 'l')
10600 return SHF_X86_64_LARGE;
10601
8f3bae45 10602 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10603 }
3b22753a 10604 else
8f3bae45 10605 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10606 return -1;
10607}
10608
01e1a5bc 10609bfd_vma
3b22753a
L		 10610x86_64_section_word (char *str, size_t len)
10611{
8620418b 10612 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10613 return SHF_X86_64_LARGE;
10614
10615 return -1;
10616}
10617
10618static void
10619handle_large_common (int small ATTRIBUTE_UNUSED)
10620{
10621 if (flag_code != CODE_64BIT)
10622 {
10623 s_comm_internal (0, elf_common_parse);
10624 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10625 }
10626 else
10627 {
10628 static segT lbss_section;
10629 asection *saved_com_section_ptr = elf_com_section_ptr;
10630 asection *saved_bss_section = bss_section;
10631
10632 if (lbss_section == NULL)
10633 {
10634 flagword applicable;
10635 segT seg = now_seg;
10636 subsegT subseg = now_subseg;
10637
10638 /* The .lbss section is for local .largecomm symbols. */
10639 lbss_section = subseg_new (".lbss", 0);
10640 applicable = bfd_applicable_section_flags (stdoutput);
10641 bfd_set_section_flags (stdoutput, lbss_section,
10642 applicable & SEC_ALLOC);
10643 seg_info (lbss_section)->bss = 1;
10644
10645 subseg_set (seg, subseg);
10646 }
10647
10648 elf_com_section_ptr = &_bfd_elf_large_com_section;
10649 bss_section = lbss_section;
10650
10651 s_comm_internal (0, elf_common_parse);
10652
10653 elf_com_section_ptr = saved_com_section_ptr;
10654 bss_section = saved_bss_section;
10655 }
10656}
10657#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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