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* alphanbsd-tdep.c: Include "target.h".
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5dd15031 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 84#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 85/* Intel Syntax. Use a non-ascii letter since since it never appears
86 in instructions. */
87#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
89#define END_OF_INSN '\0'
90
91/*
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
96 END.
97 */
98typedef struct
99{
100 const template *start;
101 const template *end;
102}
103templates;
104
105/* 386 operand encoding bytes: see 386 book for details of this. */
106typedef struct
107{
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
111}
112modrm_byte;
113
114/* x86-64 extension prefix. */
115typedef int rex_byte;
116
117/* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120#define DREX_OC0(x) (((x) & 1) != 0)
121#define DREX_OC1(x) (((x) & 2) != 0)
122
123#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
125
126/* OC mappings */
127#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
131
132#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
134
135/* Information needed to create the DREX byte in SSE5 instructions. */
136typedef struct
137{
138 unsigned int reg; /* register */
139 unsigned int rex; /* REX flags */
140 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
142} drex_byte;
143
144/* 386 opcode byte to code indirect addressing. */
145typedef struct
146{
147 unsigned base;
148 unsigned index;
149 unsigned scale;
150}
151sib_byte;
152
153enum processor_type
154{
155 PROCESSOR_UNKNOWN,
156 PROCESSOR_I386,
157 PROCESSOR_I486,
158 PROCESSOR_PENTIUM,
159 PROCESSOR_PENTIUMPRO,
160 PROCESSOR_PENTIUM4,
161 PROCESSOR_NOCONA,
162 PROCESSOR_CORE,
163 PROCESSOR_CORE2,
164 PROCESSOR_K6,
165 PROCESSOR_ATHLON,
166 PROCESSOR_K8,
167 PROCESSOR_GENERIC32,
168 PROCESSOR_GENERIC64,
169 PROCESSOR_AMDFAM10
170};
171
172/* x86 arch names, types and features */
173typedef struct
174{
175 const char *name; /* arch name */
176 enum processor_type type; /* arch type */
177 i386_cpu_flags flags; /* cpu feature flags */
178}
179arch_entry;
180
e3bb37b5
L		 181static void set_code_flag (int);
182static void set_16bit_gcc_code_flag (int);
183static void set_intel_syntax (int);
1efbbeb4 184static void set_intel_mnemonic (int);
db51cc60 185static void set_allow_index_reg (int);
e3bb37b5 186static void set_cpu_arch (int);
6482c264 187#ifdef TE_PE
e3bb37b5 188static void pe_directive_secrel (int);
6482c264 189#endif
e3bb37b5
L		 190static void signed_cons (int);
191static char *output_invalid (int c);
a7619375 192static int i386_att_operand (char *);
e3bb37b5
L		 193static int i386_intel_operand (char *, int);
194static const reg_entry *parse_register (char *, char **);
195static char *parse_insn (char *, char *);
196static char *parse_operands (char *, const char *);
197static void swap_operands (void);
4d456e3d 198static void swap_2_operands (int, int);
e3bb37b5
L		 199static void optimize_imm (void);
200static void optimize_disp (void);
201static int match_template (void);
202static int check_string (void);
203static int process_suffix (void);
204static int check_byte_reg (void);
205static int check_long_reg (void);
206static int check_qword_reg (void);
207static int check_word_reg (void);
208static int finalize_imm (void);
85f10a01 209static void process_drex (void);
e3bb37b5
L		 210static int process_operands (void);
211static const seg_entry *build_modrm_byte (void);
212static void output_insn (void);
213static void output_imm (fragS *, offsetT);
214static void output_disp (fragS *, offsetT);
29b0f896 215#ifndef I386COFF
e3bb37b5 216static void s_bss (int);
252b5132 217#endif
17d4e2a2
L		 218#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
219static void handle_large_common (int small ATTRIBUTE_UNUSED);
220#endif
252b5132 221
a847613f 222static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 223
c0f3af97
L		 224/* VEX prefix. */
225typedef struct
226{
227 /* VEX prefix is either 2 byte or 3 byte. */
228 unsigned char bytes[3];
229 unsigned int length;
230 /* Destination or source register specifier. */
231 const reg_entry *register_specifier;
232} vex_prefix;
233
252b5132 234/* 'md_assemble ()' gathers together information and puts it into a
47926f60 235 i386_insn. */
252b5132 236
520dc8e8
AM		 237union i386_op
238 {
239 expressionS *disps;
240 expressionS *imms;
241 const reg_entry *regs;
242 };
243
252b5132
RH		 244struct _i386_insn
245 {
47926f60 246 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 247 template tm;
248
7d5e4556
L		 249 /* SUFFIX holds the instruction size suffix for byte, word, dword
250 or qword, if given. */
252b5132
RH		 251 char suffix;
252
47926f60 253 /* OPERANDS gives the number of given operands. */
252b5132
RH		 254 unsigned int operands;
255
256 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
257 of given register, displacement, memory operands and immediate
47926f60 258 operands. */
252b5132
RH		 259 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
260
261 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 262 use OP[i] for the corresponding operand. */
40fb9820 263 i386_operand_type types[MAX_OPERANDS];
252b5132 264
520dc8e8
AM		 265 /* Displacement expression, immediate expression, or register for each
266 operand. */
267 union i386_op op[MAX_OPERANDS];
252b5132 268
3e73aa7c
JH		 269 /* Flags for operands. */
270 unsigned int flags[MAX_OPERANDS];
271#define Operand_PCrel 1
272
252b5132 273 /* Relocation type for operand */
f86103b7 274 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 275
252b5132
RH		 276 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
277 the base index byte below. */
278 const reg_entry *base_reg;
279 const reg_entry *index_reg;
280 unsigned int log2_scale_factor;
281
282 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 283 explicit segment overrides are given. */
ce8a8b2f 284 const seg_entry *seg[2];
252b5132
RH		 285
286 /* PREFIX holds all the given prefix opcodes (usually null).
287 PREFIXES is the number of prefix opcodes. */
288 unsigned int prefixes;
289 unsigned char prefix[MAX_PREFIXES];
290
291 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 292 addressing modes of this insn are encoded. DREX is the byte
293 added by the SSE5 instructions. */
252b5132
RH		 294
295 modrm_byte rm;
3e73aa7c 296 rex_byte rex;
252b5132 297 sib_byte sib;
85f10a01 298 drex_byte drex;
c0f3af97 299 vex_prefix vex;
252b5132
RH		 300 };
301
302typedef struct _i386_insn i386_insn;
303
304/* List of chars besides those in app.c:symbol_chars that can start an
305 operand. Used to prevent the scrubber eating vital white-space. */
32137342 306const char extra_symbol_chars[] = "*%-(["
252b5132 307#ifdef LEX_AT
32137342
NC		 308 "@"
309#endif
310#ifdef LEX_QM
311 "?"
252b5132 312#endif
32137342 313 ;
252b5132 314
29b0f896
AM		 315#if (defined (TE_I386AIX) \
316 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 317 && !defined (TE_GNU) \
29b0f896 318 && !defined (TE_LINUX) \
32137342 319 && !defined (TE_NETWARE) \
29b0f896
AM		 320 && !defined (TE_FreeBSD) \
321 && !defined (TE_NetBSD)))
252b5132 322/* This array holds the chars that always start a comment. If the
b3b91714
AM		 323 pre-processor is disabled, these aren't very useful. The option
324 --divide will remove '/' from this list. */
325const char *i386_comment_chars = "#/";
326#define SVR4_COMMENT_CHARS 1
252b5132 327#define PREFIX_SEPARATOR '\\'
252b5132 328
b3b91714
AM		 329#else
330const char *i386_comment_chars = "#";
331#define PREFIX_SEPARATOR '/'
332#endif
333
252b5132
RH		 334/* This array holds the chars that only start a comment at the beginning of
335 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 336 .line and .file directives will appear in the pre-processed output.
337 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 338 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 339 #NO_APP at the beginning of its output.
340 Also note that comments started like this one will always work if
252b5132 341 '/' isn't otherwise defined. */
b3b91714 342const char line_comment_chars[] = "#/";
252b5132 343
63a0b638 344const char line_separator_chars[] = ";";
252b5132 345
ce8a8b2f
AM		 346/* Chars that can be used to separate mant from exp in floating point
347 nums. */
252b5132
RH		 348const char EXP_CHARS[] = "eE";
349
ce8a8b2f
AM		 350/* Chars that mean this number is a floating point constant
351 As in 0f12.456
352 or 0d1.2345e12. */
252b5132
RH		 353const char FLT_CHARS[] = "fFdDxX";
354
ce8a8b2f 355/* Tables for lexical analysis. */
252b5132
RH		 356static char mnemonic_chars[256];
357static char register_chars[256];
358static char operand_chars[256];
359static char identifier_chars[256];
360static char digit_chars[256];
361
ce8a8b2f 362/* Lexical macros. */
252b5132
RH		 363#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
364#define is_operand_char(x) (operand_chars[(unsigned char) x])
365#define is_register_char(x) (register_chars[(unsigned char) x])
366#define is_space_char(x) ((x) == ' ')
367#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
368#define is_digit_char(x) (digit_chars[(unsigned char) x])
369
0234cb7c 370/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 371static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
372
373/* md_assemble() always leaves the strings it's passed unaltered. To
374 effect this we maintain a stack of saved characters that we've smashed
375 with '\0's (indicating end of strings for various sub-fields of the
47926f60 376 assembler instruction). */
252b5132 377static char save_stack[32];
ce8a8b2f 378static char *save_stack_p;
252b5132
RH		 379#define END_STRING_AND_SAVE(s) \
380 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
381#define RESTORE_END_STRING(s) \
382 do { *(s) = *--save_stack_p; } while (0)
383
47926f60 384/* The instruction we're assembling. */
252b5132
RH		 385static i386_insn i;
386
387/* Possible templates for current insn. */
388static const templates *current_templates;
389
31b2323c
L		 390/* Per instruction expressionS buffers: max displacements & immediates. */
391static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
392static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 393
47926f60
KH		 394/* Current operand we are working on. */
395static int this_operand;
252b5132 396
3e73aa7c
JH		 397/* We support four different modes. FLAG_CODE variable is used to distinguish
398 these. */
399
400enum flag_code {
401 CODE_32BIT,
402 CODE_16BIT,
403 CODE_64BIT };
404
405static enum flag_code flag_code;
4fa24527 406static unsigned int object_64bit;
3e73aa7c
JH		 407static int use_rela_relocations = 0;
408
409/* The names used to print error messages. */
b77a7acd 410static const char *flag_code_names[] =
3e73aa7c
JH		 411 {
412 "32",
413 "16",
414 "64"
415 };
252b5132 416
47926f60
KH		 417/* 1 for intel syntax,
418 0 if att syntax. */
419static int intel_syntax = 0;
252b5132 420
1efbbeb4
L		 421/* 1 for intel mnemonic,
422 0 if att mnemonic. */
423static int intel_mnemonic = !SYSV386_COMPAT;
424
5209009a 425/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 426static int old_gcc = OLDGCC_COMPAT;
427
a60de03c
JB		 428/* 1 if pseudo registers are permitted. */
429static int allow_pseudo_reg = 0;
430
47926f60
KH		 431/* 1 if register prefix % not required. */
432static int allow_naked_reg = 0;
252b5132 433
ba104c83 434/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 435static int allow_index_reg = 0;
436
2ca3ace5
L		 437/* Register prefix used for error message. */
438static const char *register_prefix = "%";
439
47926f60
KH		 440/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
441 leave, push, and pop instructions so that gcc has the same stack
442 frame as in 32 bit mode. */
443static char stackop_size = '\0';
eecb386c 444
12b55ccc
L		 445/* Non-zero to optimize code alignment. */
446int optimize_align_code = 1;
447
47926f60
KH		 448/* Non-zero to quieten some warnings. */
449static int quiet_warnings = 0;
a38cf1db 450
47926f60
KH		 451/* CPU name. */
452static const char *cpu_arch_name = NULL;
6305a203 453static char *cpu_sub_arch_name = NULL;
a38cf1db 454
47926f60 455/* CPU feature flags. */
40fb9820
L		 456static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
457
ccc9c027
L		 458/* If we have selected a cpu we are generating instructions for. */
459static int cpu_arch_tune_set = 0;
460
9103f4f4
L		 461/* Cpu we are generating instructions for. */
462static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
463
464/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 465static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 466
ccc9c027
L		 467/* CPU instruction set architecture used. */
468static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
469
9103f4f4 470/* CPU feature flags of instruction set architecture used. */
40fb9820 471static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 472
fddf5b5b
AM		 473/* If set, conditional jumps are not automatically promoted to handle
474 larger than a byte offset. */
475static unsigned int no_cond_jump_promotion = 0;
476
c0f3af97
L		 477/* Encode SSE instructions with VEX prefix. */
478static unsigned int sse2avx;
479
29b0f896 480/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 481static symbolS *GOT_symbol;
29b0f896 482
a4447b93
RH		 483/* The dwarf2 return column, adjusted for 32 or 64 bit. */
484unsigned int x86_dwarf2_return_column;
485
486/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
487int x86_cie_data_alignment;
488
252b5132 489/* Interface to relax_segment.
fddf5b5b
AM		 490 There are 3 major relax states for 386 jump insns because the
491 different types of jumps add different sizes to frags when we're
492 figuring out what sort of jump to choose to reach a given label. */
252b5132 493
47926f60 494/* Types. */
93c2a809
AM		 495#define UNCOND_JUMP 0
496#define COND_JUMP 1
497#define COND_JUMP86 2
fddf5b5b 498
47926f60 499/* Sizes. */
252b5132
RH		 500#define CODE16 1
501#define SMALL 0
29b0f896 502#define SMALL16 (SMALL | CODE16)
252b5132 503#define BIG 2
29b0f896 504#define BIG16 (BIG | CODE16)
252b5132
RH		 505
506#ifndef INLINE
507#ifdef __GNUC__
508#define INLINE __inline__
509#else
510#define INLINE
511#endif
512#endif
513
fddf5b5b
AM		 514#define ENCODE_RELAX_STATE(type, size) \
515 ((relax_substateT) (((type) << 2) | (size)))
516#define TYPE_FROM_RELAX_STATE(s) \
517 ((s) >> 2)
518#define DISP_SIZE_FROM_RELAX_STATE(s) \
519 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 520
521/* This table is used by relax_frag to promote short jumps to long
522 ones where necessary. SMALL (short) jumps may be promoted to BIG
523 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
524 don't allow a short jump in a 32 bit code segment to be promoted to
525 a 16 bit offset jump because it's slower (requires data size
526 prefix), and doesn't work, unless the destination is in the bottom
527 64k of the code segment (The top 16 bits of eip are zeroed). */
528
529const relax_typeS md_relax_table[] =
530{
24eab124
AM		 531 /* The fields are:
532 1) most positive reach of this state,
533 2) most negative reach of this state,
93c2a809 534 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 535 4) which index into the table to try if we can't fit into this one. */
252b5132 536
fddf5b5b 537 /* UNCOND_JUMP states. */
93c2a809
AM		 538 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
539 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
540 /* dword jmp adds 4 bytes to frag:
541 0 extra opcode bytes, 4 displacement bytes. */
252b5132 542 {0, 0, 4, 0},
93c2a809
AM		 543 /* word jmp adds 2 byte2 to frag:
544 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 545 {0, 0, 2, 0},
546
93c2a809
AM		 547 /* COND_JUMP states. */
548 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
549 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
550 /* dword conditionals adds 5 bytes to frag:
551 1 extra opcode byte, 4 displacement bytes. */
552 {0, 0, 5, 0},
fddf5b5b 553 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 554 1 extra opcode byte, 2 displacement bytes. */
555 {0, 0, 3, 0},
556
557 /* COND_JUMP86 states. */
558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
559 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
560 /* dword conditionals adds 5 bytes to frag:
561 1 extra opcode byte, 4 displacement bytes. */
562 {0, 0, 5, 0},
563 /* word conditionals add 4 bytes to frag:
564 1 displacement byte and a 3 byte long branch insn. */
565 {0, 0, 4, 0}
252b5132
RH		 566};
567
9103f4f4
L		 568static const arch_entry cpu_arch[] =
569{
6305a203
L		 570 { "generic32", PROCESSOR_GENERIC32,
571 CPU_GENERIC32_FLAGS },
572 { "generic64", PROCESSOR_GENERIC64,
573 CPU_GENERIC64_FLAGS },
574 { "i8086", PROCESSOR_UNKNOWN,
575 CPU_NONE_FLAGS },
576 { "i186", PROCESSOR_UNKNOWN,
577 CPU_I186_FLAGS },
578 { "i286", PROCESSOR_UNKNOWN,
579 CPU_I286_FLAGS },
580 { "i386", PROCESSOR_I386,
581 CPU_I386_FLAGS },
582 { "i486", PROCESSOR_I486,
583 CPU_I486_FLAGS },
584 { "i586", PROCESSOR_PENTIUM,
585 CPU_I586_FLAGS },
586 { "i686", PROCESSOR_PENTIUMPRO,
587 CPU_I686_FLAGS },
588 { "pentium", PROCESSOR_PENTIUM,
589 CPU_I586_FLAGS },
590 { "pentiumpro", PROCESSOR_PENTIUMPRO,
591 CPU_I686_FLAGS },
592 { "pentiumii", PROCESSOR_PENTIUMPRO,
593 CPU_P2_FLAGS },
594 { "pentiumiii",PROCESSOR_PENTIUMPRO,
595 CPU_P3_FLAGS },
596 { "pentium4", PROCESSOR_PENTIUM4,
597 CPU_P4_FLAGS },
598 { "prescott", PROCESSOR_NOCONA,
599 CPU_CORE_FLAGS },
600 { "nocona", PROCESSOR_NOCONA,
601 CPU_NOCONA_FLAGS },
602 { "yonah", PROCESSOR_CORE,
603 CPU_CORE_FLAGS },
604 { "core", PROCESSOR_CORE,
605 CPU_CORE_FLAGS },
606 { "merom", PROCESSOR_CORE2,
607 CPU_CORE2_FLAGS },
608 { "core2", PROCESSOR_CORE2,
609 CPU_CORE2_FLAGS },
610 { "k6", PROCESSOR_K6,
611 CPU_K6_FLAGS },
612 { "k6_2", PROCESSOR_K6,
613 CPU_K6_2_FLAGS },
614 { "athlon", PROCESSOR_ATHLON,
615 CPU_ATHLON_FLAGS },
616 { "sledgehammer", PROCESSOR_K8,
617 CPU_K8_FLAGS },
618 { "opteron", PROCESSOR_K8,
619 CPU_K8_FLAGS },
620 { "k8", PROCESSOR_K8,
621 CPU_K8_FLAGS },
622 { "amdfam10", PROCESSOR_AMDFAM10,
623 CPU_AMDFAM10_FLAGS },
624 { ".mmx", PROCESSOR_UNKNOWN,
625 CPU_MMX_FLAGS },
626 { ".sse", PROCESSOR_UNKNOWN,
627 CPU_SSE_FLAGS },
628 { ".sse2", PROCESSOR_UNKNOWN,
629 CPU_SSE2_FLAGS },
630 { ".sse3", PROCESSOR_UNKNOWN,
631 CPU_SSE3_FLAGS },
632 { ".ssse3", PROCESSOR_UNKNOWN,
633 CPU_SSSE3_FLAGS },
634 { ".sse4.1", PROCESSOR_UNKNOWN,
635 CPU_SSE4_1_FLAGS },
636 { ".sse4.2", PROCESSOR_UNKNOWN,
637 CPU_SSE4_2_FLAGS },
638 { ".sse4", PROCESSOR_UNKNOWN,
639 CPU_SSE4_2_FLAGS },
c0f3af97
L		 640 { ".avx", PROCESSOR_UNKNOWN,
641 CPU_AVX_FLAGS },
6305a203
L		 642 { ".vmx", PROCESSOR_UNKNOWN,
643 CPU_VMX_FLAGS },
644 { ".smx", PROCESSOR_UNKNOWN,
645 CPU_SMX_FLAGS },
f03fe4c1
L		 646 { ".xsave", PROCESSOR_UNKNOWN,
647 CPU_XSAVE_FLAGS },
c0f3af97
L		 648 { ".aes", PROCESSOR_UNKNOWN,
649 CPU_AES_FLAGS },
594ab6a3
L		 650 { ".pclmul", PROCESSOR_UNKNOWN,
651 CPU_PCLMUL_FLAGS },
c0f3af97 652 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 653 CPU_PCLMUL_FLAGS },
c0f3af97
L		 654 { ".fma", PROCESSOR_UNKNOWN,
655 CPU_FMA_FLAGS },
6305a203
L		 656 { ".3dnow", PROCESSOR_UNKNOWN,
657 CPU_3DNOW_FLAGS },
658 { ".3dnowa", PROCESSOR_UNKNOWN,
659 CPU_3DNOWA_FLAGS },
660 { ".padlock", PROCESSOR_UNKNOWN,
661 CPU_PADLOCK_FLAGS },
662 { ".pacifica", PROCESSOR_UNKNOWN,
663 CPU_SVME_FLAGS },
664 { ".svme", PROCESSOR_UNKNOWN,
665 CPU_SVME_FLAGS },
666 { ".sse4a", PROCESSOR_UNKNOWN,
667 CPU_SSE4A_FLAGS },
668 { ".abm", PROCESSOR_UNKNOWN,
669 CPU_ABM_FLAGS },
670 { ".sse5", PROCESSOR_UNKNOWN,
671 CPU_SSE5_FLAGS },
e413e4e9
AM		 672};
673
29b0f896
AM		 674const pseudo_typeS md_pseudo_table[] =
675{
676#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
677 {"align", s_align_bytes, 0},
678#else
679 {"align", s_align_ptwo, 0},
680#endif
681 {"arch", set_cpu_arch, 0},
682#ifndef I386COFF
683 {"bss", s_bss, 0},
684#endif
685 {"ffloat", float_cons, 'f'},
686 {"dfloat", float_cons, 'd'},
687 {"tfloat", float_cons, 'x'},
688 {"value", cons, 2},
d182319b 689 {"slong", signed_cons, 4},
29b0f896
AM		 690 {"noopt", s_ignore, 0},
691 {"optim", s_ignore, 0},
692 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
693 {"code16", set_code_flag, CODE_16BIT},
694 {"code32", set_code_flag, CODE_32BIT},
695 {"code64", set_code_flag, CODE_64BIT},
696 {"intel_syntax", set_intel_syntax, 1},
697 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 698 {"intel_mnemonic", set_intel_mnemonic, 1},
699 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 700 {"allow_index_reg", set_allow_index_reg, 1},
701 {"disallow_index_reg", set_allow_index_reg, 0},
3b22753a
L		 702#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
703 {"largecomm", handle_large_common, 0},
07a53e5c 704#else
e3bb37b5 705 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 706 {"loc", dwarf2_directive_loc, 0},
707 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 708#endif
6482c264
NC		 709#ifdef TE_PE
710 {"secrel32", pe_directive_secrel, 0},
711#endif
29b0f896
AM		 712 {0, 0, 0}
713};
714
715/* For interface with expression (). */
716extern char *input_line_pointer;
717
718/* Hash table for instruction mnemonic lookup. */
719static struct hash_control *op_hash;
720
721/* Hash table for register lookup. */
722static struct hash_control *reg_hash;
723\f
252b5132 724void
e3bb37b5 725i386_align_code (fragS *fragP, int count)
252b5132 726{
ce8a8b2f
AM		 727 /* Various efficient no-op patterns for aligning code labels.
728 Note: Don't try to assemble the instructions in the comments.
729 0L and 0w are not legal. */
252b5132
RH		 730 static const char f32_1[] =
731 {0x90}; /* nop */
732 static const char f32_2[] =
ccc9c027 733 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 734 static const char f32_3[] =
735 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
736 static const char f32_4[] =
737 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
738 static const char f32_5[] =
739 {0x90, /* nop */
740 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
741 static const char f32_6[] =
742 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
743 static const char f32_7[] =
744 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
745 static const char f32_8[] =
746 {0x90, /* nop */
747 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
748 static const char f32_9[] =
749 {0x89,0xf6, /* movl %esi,%esi */
750 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
751 static const char f32_10[] =
752 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
753 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
754 static const char f32_11[] =
755 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
756 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
757 static const char f32_12[] =
758 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
759 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
760 static const char f32_13[] =
761 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
762 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
763 static const char f32_14[] =
764 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
765 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 766 static const char f16_3[] =
767 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 768 static const char f16_4[] =
769 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
770 static const char f16_5[] =
771 {0x90, /* nop */
772 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
773 static const char f16_6[] =
774 {0x89,0xf6, /* mov %si,%si */
775 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
776 static const char f16_7[] =
777 {0x8d,0x74,0x00, /* lea 0(%si),%si */
778 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
779 static const char f16_8[] =
780 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
781 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 782 static const char jump_31[] =
783 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
784 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
785 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
786 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 787 static const char *const f32_patt[] = {
788 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 789 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 790 };
791 static const char *const f16_patt[] = {
76bc74dc 792 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 793 };
ccc9c027
L		 794 /* nopl (%[re]ax) */
795 static const char alt_3[] =
796 {0x0f,0x1f,0x00};
797 /* nopl 0(%[re]ax) */
798 static const char alt_4[] =
799 {0x0f,0x1f,0x40,0x00};
800 /* nopl 0(%[re]ax,%[re]ax,1) */
801 static const char alt_5[] =
802 {0x0f,0x1f,0x44,0x00,0x00};
803 /* nopw 0(%[re]ax,%[re]ax,1) */
804 static const char alt_6[] =
805 {0x66,0x0f,0x1f,0x44,0x00,0x00};
806 /* nopl 0L(%[re]ax) */
807 static const char alt_7[] =
808 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
809 /* nopl 0L(%[re]ax,%[re]ax,1) */
810 static const char alt_8[] =
811 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
812 /* nopw 0L(%[re]ax,%[re]ax,1) */
813 static const char alt_9[] =
814 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
815 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
816 static const char alt_10[] =
817 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
818 /* data16
819 nopw %cs:0L(%[re]ax,%[re]ax,1) */
820 static const char alt_long_11[] =
821 {0x66,
822 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
823 /* data16
824 data16
825 nopw %cs:0L(%[re]ax,%[re]ax,1) */
826 static const char alt_long_12[] =
827 {0x66,
828 0x66,
829 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
830 /* data16
831 data16
832 data16
833 nopw %cs:0L(%[re]ax,%[re]ax,1) */
834 static const char alt_long_13[] =
835 {0x66,
836 0x66,
837 0x66,
838 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
839 /* data16
840 data16
841 data16
842 data16
843 nopw %cs:0L(%[re]ax,%[re]ax,1) */
844 static const char alt_long_14[] =
845 {0x66,
846 0x66,
847 0x66,
848 0x66,
849 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
850 /* data16
851 data16
852 data16
853 data16
854 data16
855 nopw %cs:0L(%[re]ax,%[re]ax,1) */
856 static const char alt_long_15[] =
857 {0x66,
858 0x66,
859 0x66,
860 0x66,
861 0x66,
862 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 /* nopl 0(%[re]ax,%[re]ax,1)
864 nopw 0(%[re]ax,%[re]ax,1) */
865 static const char alt_short_11[] =
866 {0x0f,0x1f,0x44,0x00,0x00,
867 0x66,0x0f,0x1f,0x44,0x00,0x00};
868 /* nopw 0(%[re]ax,%[re]ax,1)
869 nopw 0(%[re]ax,%[re]ax,1) */
870 static const char alt_short_12[] =
871 {0x66,0x0f,0x1f,0x44,0x00,0x00,
872 0x66,0x0f,0x1f,0x44,0x00,0x00};
873 /* nopw 0(%[re]ax,%[re]ax,1)
874 nopl 0L(%[re]ax) */
875 static const char alt_short_13[] =
876 {0x66,0x0f,0x1f,0x44,0x00,0x00,
877 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
878 /* nopl 0L(%[re]ax)
879 nopl 0L(%[re]ax) */
880 static const char alt_short_14[] =
881 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
882 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
883 /* nopl 0L(%[re]ax)
884 nopl 0L(%[re]ax,%[re]ax,1) */
885 static const char alt_short_15[] =
886 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
887 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
888 static const char *const alt_short_patt[] = {
889 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
890 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
891 alt_short_14, alt_short_15
892 };
893 static const char *const alt_long_patt[] = {
894 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
895 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
896 alt_long_14, alt_long_15
897 };
252b5132 898
76bc74dc
L		 899 /* Only align for at least a positive non-zero boundary. */
900 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 901 return;
3e73aa7c 902
ccc9c027
L		 903 /* We need to decide which NOP sequence to use for 32bit and
904 64bit. When -mtune= is used:
4eed87de 905
76bc74dc
L		 906 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
907 PROCESSOR_GENERIC32, f32_patt will be used.
908 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
909 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
910 alt_long_patt will be used.
911 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
912 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 913
76bc74dc
L		 914 When -mtune= isn't used, alt_long_patt will be used if
915 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
916 be used.
ccc9c027
L		 917
918 When -march= or .arch is used, we can't use anything beyond
919 cpu_arch_isa_flags. */
920
921 if (flag_code == CODE_16BIT)
922 {
ccc9c027 923 if (count > 8)
33fef721 924 {
76bc74dc
L		 925 memcpy (fragP->fr_literal + fragP->fr_fix,
926 jump_31, count);
927 /* Adjust jump offset. */
928 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 929 }
76bc74dc
L		 930 else
931 memcpy (fragP->fr_literal + fragP->fr_fix,
932 f16_patt[count - 1], count);
252b5132 933 }
33fef721 934 else
ccc9c027
L		 935 {
936 const char *const *patt = NULL;
937
938 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
939 {
940 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
941 switch (cpu_arch_tune)
942 {
943 case PROCESSOR_UNKNOWN:
944 /* We use cpu_arch_isa_flags to check if we SHOULD
945 optimize for Cpu686. */
40fb9820 946 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 947 patt = alt_long_patt;
ccc9c027
L		 948 else
949 patt = f32_patt;
950 break;
ccc9c027
L		 951 case PROCESSOR_PENTIUMPRO:
952 case PROCESSOR_PENTIUM4:
953 case PROCESSOR_NOCONA:
ef05d495 954 case PROCESSOR_CORE:
76bc74dc
L		 955 case PROCESSOR_CORE2:
956 case PROCESSOR_GENERIC64:
957 patt = alt_long_patt;
958 break;
ccc9c027
L		 959 case PROCESSOR_K6:
960 case PROCESSOR_ATHLON:
961 case PROCESSOR_K8:
4eed87de 962 case PROCESSOR_AMDFAM10:
ccc9c027
L		 963 patt = alt_short_patt;
964 break;
76bc74dc 965 case PROCESSOR_I386:
ccc9c027
L		 966 case PROCESSOR_I486:
967 case PROCESSOR_PENTIUM:
968 case PROCESSOR_GENERIC32:
969 patt = f32_patt;
970 break;
4eed87de 971 }
ccc9c027
L		 972 }
973 else
974 {
975 switch (cpu_arch_tune)
976 {
977 case PROCESSOR_UNKNOWN:
978 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
979 PROCESSOR_UNKNOWN. */
980 abort ();
981 break;
982
76bc74dc 983 case PROCESSOR_I386:
ccc9c027
L		 984 case PROCESSOR_I486:
985 case PROCESSOR_PENTIUM:
ccc9c027
L		 986 case PROCESSOR_K6:
987 case PROCESSOR_ATHLON:
988 case PROCESSOR_K8:
4eed87de 989 case PROCESSOR_AMDFAM10:
ccc9c027
L		 990 case PROCESSOR_GENERIC32:
991 /* We use cpu_arch_isa_flags to check if we CAN optimize
992 for Cpu686. */
40fb9820 993 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 994 patt = alt_short_patt;
995 else
996 patt = f32_patt;
997 break;
76bc74dc
L		 998 case PROCESSOR_PENTIUMPRO:
999 case PROCESSOR_PENTIUM4:
1000 case PROCESSOR_NOCONA:
1001 case PROCESSOR_CORE:
ef05d495 1002 case PROCESSOR_CORE2:
40fb9820 1003 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 1004 patt = alt_long_patt;
1005 else
1006 patt = f32_patt;
1007 break;
1008 case PROCESSOR_GENERIC64:
76bc74dc 1009 patt = alt_long_patt;
ccc9c027 1010 break;
4eed87de 1011 }
ccc9c027
L		 1012 }
1013
76bc74dc
L		 1014 if (patt == f32_patt)
1015 {
1016 /* If the padding is less than 15 bytes, we use the normal
1017 ones. Otherwise, we use a jump instruction and adjust
1018 its offset. */
1019 if (count < 15)
1020 memcpy (fragP->fr_literal + fragP->fr_fix,
1021 patt[count - 1], count);
1022 else
1023 {
1024 memcpy (fragP->fr_literal + fragP->fr_fix,
1025 jump_31, count);
1026 /* Adjust jump offset. */
1027 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1028 }
1029 }
1030 else
1031 {
1032 /* Maximum length of an instruction is 15 byte. If the
1033 padding is greater than 15 bytes and we don't use jump,
1034 we have to break it into smaller pieces. */
1035 int padding = count;
1036 while (padding > 15)
1037 {
1038 padding -= 15;
1039 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1040 patt [14], 15);
1041 }
1042
1043 if (padding)
1044 memcpy (fragP->fr_literal + fragP->fr_fix,
1045 patt [padding - 1], padding);
1046 }
ccc9c027 1047 }
33fef721 1048 fragP->fr_var = count;
252b5132
RH		 1049}
1050
c6fb90c8 1051static INLINE int
0dfbf9d7 1052operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1053{
0dfbf9d7 1054 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1055 {
1056 case 3:
0dfbf9d7 1057 if (x->array[2])
c6fb90c8
L		 1058 return 0;
1059 case 2:
0dfbf9d7 1060 if (x->array[1])
c6fb90c8
L		 1061 return 0;
1062 case 1:
0dfbf9d7 1063 return !x->array[0];
c6fb90c8
L		 1064 default:
1065 abort ();
1066 }
40fb9820
L		 1067}
1068
c6fb90c8 1069static INLINE void
0dfbf9d7 1070operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1071{
0dfbf9d7 1072 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1073 {
1074 case 3:
0dfbf9d7 1075 x->array[2] = v;
c6fb90c8 1076 case 2:
0dfbf9d7 1077 x->array[1] = v;
c6fb90c8 1078 case 1:
0dfbf9d7 1079 x->array[0] = v;
c6fb90c8
L		 1080 break;
1081 default:
1082 abort ();
1083 }
1084}
40fb9820 1085
c6fb90c8 1086static INLINE int
0dfbf9d7
L		 1087operand_type_equal (const union i386_operand_type *x,
1088 const union i386_operand_type *y)
c6fb90c8 1089{
0dfbf9d7 1090 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1091 {
1092 case 3:
0dfbf9d7 1093 if (x->array[2] != y->array[2])
c6fb90c8
L		 1094 return 0;
1095 case 2:
0dfbf9d7 1096 if (x->array[1] != y->array[1])
c6fb90c8
L		 1097 return 0;
1098 case 1:
0dfbf9d7 1099 return x->array[0] == y->array[0];
c6fb90c8
L		 1100 break;
1101 default:
1102 abort ();
1103 }
1104}
40fb9820 1105
0dfbf9d7
L		 1106static INLINE int
1107cpu_flags_all_zero (const union i386_cpu_flags *x)
1108{
1109 switch (ARRAY_SIZE(x->array))
1110 {
1111 case 3:
1112 if (x->array[2])
1113 return 0;
1114 case 2:
1115 if (x->array[1])
1116 return 0;
1117 case 1:
1118 return !x->array[0];
1119 default:
1120 abort ();
1121 }
1122}
1123
1124static INLINE void
1125cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1126{
1127 switch (ARRAY_SIZE(x->array))
1128 {
1129 case 3:
1130 x->array[2] = v;
1131 case 2:
1132 x->array[1] = v;
1133 case 1:
1134 x->array[0] = v;
1135 break;
1136 default:
1137 abort ();
1138 }
1139}
1140
1141static INLINE int
1142cpu_flags_equal (const union i386_cpu_flags *x,
1143 const union i386_cpu_flags *y)
1144{
1145 switch (ARRAY_SIZE(x->array))
1146 {
1147 case 3:
1148 if (x->array[2] != y->array[2])
1149 return 0;
1150 case 2:
1151 if (x->array[1] != y->array[1])
1152 return 0;
1153 case 1:
1154 return x->array[0] == y->array[0];
1155 break;
1156 default:
1157 abort ();
1158 }
1159}
c6fb90c8
L		 1160
1161static INLINE int
1162cpu_flags_check_cpu64 (i386_cpu_flags f)
1163{
1164 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1165 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1166}
1167
c6fb90c8
L		 1168static INLINE i386_cpu_flags
1169cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1170{
c6fb90c8
L		 1171 switch (ARRAY_SIZE (x.array))
1172 {
1173 case 3:
1174 x.array [2] &= y.array [2];
1175 case 2:
1176 x.array [1] &= y.array [1];
1177 case 1:
1178 x.array [0] &= y.array [0];
1179 break;
1180 default:
1181 abort ();
1182 }
1183 return x;
1184}
40fb9820 1185
c6fb90c8
L		 1186static INLINE i386_cpu_flags
1187cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1188{
c6fb90c8 1189 switch (ARRAY_SIZE (x.array))
40fb9820 1190 {
c6fb90c8
L		 1191 case 3:
1192 x.array [2] |= y.array [2];
1193 case 2:
1194 x.array [1] |= y.array [1];
1195 case 1:
1196 x.array [0] |= y.array [0];
40fb9820
L		 1197 break;
1198 default:
1199 abort ();
1200 }
40fb9820
L		 1201 return x;
1202}
1203
c0f3af97
L		 1204#define CPU_FLAGS_ARCH_MATCH 0x1
1205#define CPU_FLAGS_64BIT_MATCH 0x2
1206
1207#define CPU_FLAGS_32BIT_MATCH CPU_FLAGS_ARCH_MATCH
1208#define CPU_FLAGS_PERFECT_MATCH \
1209 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1210
1211/* Return CPU flags match bits. */
3629bb00 1212
40fb9820 1213static int
c0f3af97 1214cpu_flags_match (const template *t)
40fb9820 1215{
c0f3af97
L		 1216 i386_cpu_flags x = t->cpu_flags;
1217 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1218
1219 x.bitfield.cpu64 = 0;
1220 x.bitfield.cpuno64 = 0;
1221
0dfbf9d7 1222 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1223 {
1224 /* This instruction is available on all archs. */
1225 match |= CPU_FLAGS_32BIT_MATCH;
1226 }
3629bb00
L		 1227 else
1228 {
c0f3af97 1229 /* This instruction is available only on some archs. */
3629bb00
L		 1230 i386_cpu_flags cpu = cpu_arch_flags;
1231
1232 cpu.bitfield.cpu64 = 0;
1233 cpu.bitfield.cpuno64 = 0;
1234 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1235 if (!cpu_flags_all_zero (&cpu))
1236 {
1237 /* Check SSE2AVX */
1238 if (!t->opcode_modifier.sse2avx || sse2avx)
1239 match |= CPU_FLAGS_32BIT_MATCH;
1240 }
3629bb00 1241 }
c0f3af97 1242 return match;
40fb9820
L		 1243}
1244
c6fb90c8
L		 1245static INLINE i386_operand_type
1246operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1247{
c6fb90c8
L		 1248 switch (ARRAY_SIZE (x.array))
1249 {
1250 case 3:
1251 x.array [2] &= y.array [2];
1252 case 2:
1253 x.array [1] &= y.array [1];
1254 case 1:
1255 x.array [0] &= y.array [0];
1256 break;
1257 default:
1258 abort ();
1259 }
1260 return x;
40fb9820
L		 1261}
1262
c6fb90c8
L		 1263static INLINE i386_operand_type
1264operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1265{
c6fb90c8 1266 switch (ARRAY_SIZE (x.array))
40fb9820 1267 {
c6fb90c8
L		 1268 case 3:
1269 x.array [2] |= y.array [2];
1270 case 2:
1271 x.array [1] |= y.array [1];
1272 case 1:
1273 x.array [0] |= y.array [0];
40fb9820
L		 1274 break;
1275 default:
1276 abort ();
1277 }
c6fb90c8
L		 1278 return x;
1279}
40fb9820 1280
c6fb90c8
L		 1281static INLINE i386_operand_type
1282operand_type_xor (i386_operand_type x, i386_operand_type y)
1283{
1284 switch (ARRAY_SIZE (x.array))
1285 {
1286 case 3:
1287 x.array [2] ^= y.array [2];
1288 case 2:
1289 x.array [1] ^= y.array [1];
1290 case 1:
1291 x.array [0] ^= y.array [0];
1292 break;
1293 default:
1294 abort ();
1295 }
40fb9820
L		 1296 return x;
1297}
1298
1299static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1300static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1301static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1302static const i386_operand_type inoutportreg
1303 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1304static const i386_operand_type reg16_inoutportreg
1305 = OPERAND_TYPE_REG16_INOUTPORTREG;
1306static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1307static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1308static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1309static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1310static const i386_operand_type anydisp
1311 = OPERAND_TYPE_ANYDISP;
40fb9820 1312static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1313static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1314static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1315static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1316static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1317static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1318static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1319static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1320static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1321static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1322static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
c0f3af97 1323static const i386_operand_type vex_imm4 = OPERAND_TYPE_VEX_IMM4;
40fb9820
L		 1324
1325enum operand_type
1326{
1327 reg,
40fb9820
L		 1328 imm,
1329 disp,
1330 anymem
1331};
1332
c6fb90c8 1333static INLINE int
40fb9820
L		 1334operand_type_check (i386_operand_type t, enum operand_type c)
1335{
1336 switch (c)
1337 {
1338 case reg:
1339 return (t.bitfield.reg8
1340 || t.bitfield.reg16
1341 || t.bitfield.reg32
1342 || t.bitfield.reg64);
1343
40fb9820
L		 1344 case imm:
1345 return (t.bitfield.imm8
1346 || t.bitfield.imm8s
1347 || t.bitfield.imm16
1348 || t.bitfield.imm32
1349 || t.bitfield.imm32s
1350 || t.bitfield.imm64);
1351
1352 case disp:
1353 return (t.bitfield.disp8
1354 || t.bitfield.disp16
1355 || t.bitfield.disp32
1356 || t.bitfield.disp32s
1357 || t.bitfield.disp64);
1358
1359 case anymem:
1360 return (t.bitfield.disp8
1361 || t.bitfield.disp16
1362 || t.bitfield.disp32
1363 || t.bitfield.disp32s
1364 || t.bitfield.disp64
1365 || t.bitfield.baseindex);
1366
1367 default:
1368 abort ();
1369 }
1370}
1371
5c07affc
L		 1372/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1373 operand J for instruction template T. */
1374
1375static INLINE int
1376match_reg_size (const template *t, unsigned int j)
1377{
1378 return !((i.types[j].bitfield.byte
1379 && !t->operand_types[j].bitfield.byte)
1380 || (i.types[j].bitfield.word
1381 && !t->operand_types[j].bitfield.word)
1382 || (i.types[j].bitfield.dword
1383 && !t->operand_types[j].bitfield.dword)
1384 || (i.types[j].bitfield.qword
1385 && !t->operand_types[j].bitfield.qword));
1386}
1387
1388/* Return 1 if there is no conflict in any size on operand J for
1389 instruction template T. */
1390
1391static INLINE int
1392match_mem_size (const template *t, unsigned int j)
1393{
1394 return (match_reg_size (t, j)
1395 && !((i.types[j].bitfield.unspecified
1396 && !t->operand_types[j].bitfield.unspecified)
1397 || (i.types[j].bitfield.fword
1398 && !t->operand_types[j].bitfield.fword)
1399 || (i.types[j].bitfield.tbyte
1400 && !t->operand_types[j].bitfield.tbyte)
1401 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1402 && !t->operand_types[j].bitfield.xmmword)
1403 || (i.types[j].bitfield.ymmword
1404 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1405}
1406
1407/* Return 1 if there is no size conflict on any operands for
1408 instruction template T. */
1409
1410static INLINE int
1411operand_size_match (const template *t)
1412{
1413 unsigned int j;
1414 int match = 1;
1415
1416 /* Don't check jump instructions. */
1417 if (t->opcode_modifier.jump
1418 || t->opcode_modifier.jumpbyte
1419 || t->opcode_modifier.jumpdword
1420 || t->opcode_modifier.jumpintersegment)
1421 return match;
1422
1423 /* Check memory and accumulator operand size. */
1424 for (j = 0; j < i.operands; j++)
1425 {
1426 if (t->operand_types[j].bitfield.anysize)
1427 continue;
1428
1429 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1430 {
1431 match = 0;
1432 break;
1433 }
1434
1435 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1436 {
1437 match = 0;
1438 break;
1439 }
1440 }
1441
1442 if (match
1443 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1444 return match;
1445
1446 /* Check reverse. */
1447 assert (i.operands == 2);
1448
1449 match = 1;
1450 for (j = 0; j < 2; j++)
1451 {
1452 if (t->operand_types[j].bitfield.acc
1453 && !match_reg_size (t, j ? 0 : 1))
1454 {
1455 match = 0;
1456 break;
1457 }
1458
1459 if (i.types[j].bitfield.mem
1460 && !match_mem_size (t, j ? 0 : 1))
1461 {
1462 match = 0;
1463 break;
1464 }
1465 }
1466
1467 return match;
1468}
1469
c6fb90c8 1470static INLINE int
40fb9820
L		 1471operand_type_match (i386_operand_type overlap,
1472 i386_operand_type given)
1473{
1474 i386_operand_type temp = overlap;
1475
1476 temp.bitfield.jumpabsolute = 0;
7d5e4556 1477 temp.bitfield.unspecified = 0;
5c07affc
L		 1478 temp.bitfield.byte = 0;
1479 temp.bitfield.word = 0;
1480 temp.bitfield.dword = 0;
1481 temp.bitfield.fword = 0;
1482 temp.bitfield.qword = 0;
1483 temp.bitfield.tbyte = 0;
1484 temp.bitfield.xmmword = 0;
c0f3af97 1485 temp.bitfield.ymmword = 0;
0dfbf9d7 1486 if (operand_type_all_zero (&temp))
40fb9820
L		 1487 return 0;
1488
1489 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1490 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1491}
1492
7d5e4556 1493/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1494 unless the expected operand type register overlap is null.
1495 Note that Acc in a template matches every size of reg. */
1496
c6fb90c8 1497static INLINE int
40fb9820
L		 1498operand_type_register_match (i386_operand_type m0,
1499 i386_operand_type g0,
1500 i386_operand_type t0,
1501 i386_operand_type m1,
1502 i386_operand_type g1,
1503 i386_operand_type t1)
1504{
1505 if (!operand_type_check (g0, reg))
1506 return 1;
1507
1508 if (!operand_type_check (g1, reg))
1509 return 1;
1510
1511 if (g0.bitfield.reg8 == g1.bitfield.reg8
1512 && g0.bitfield.reg16 == g1.bitfield.reg16
1513 && g0.bitfield.reg32 == g1.bitfield.reg32
1514 && g0.bitfield.reg64 == g1.bitfield.reg64)
1515 return 1;
1516
1517 if (m0.bitfield.acc)
1518 {
1519 t0.bitfield.reg8 = 1;
1520 t0.bitfield.reg16 = 1;
1521 t0.bitfield.reg32 = 1;
1522 t0.bitfield.reg64 = 1;
1523 }
1524
1525 if (m1.bitfield.acc)
1526 {
1527 t1.bitfield.reg8 = 1;
1528 t1.bitfield.reg16 = 1;
1529 t1.bitfield.reg32 = 1;
1530 t1.bitfield.reg64 = 1;
1531 }
1532
1533 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1534 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1535 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1536 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1537}
1538
252b5132 1539static INLINE unsigned int
40fb9820 1540mode_from_disp_size (i386_operand_type t)
252b5132 1541{
40fb9820
L		 1542 if (t.bitfield.disp8)
1543 return 1;
1544 else if (t.bitfield.disp16
1545 || t.bitfield.disp32
1546 || t.bitfield.disp32s)
1547 return 2;
1548 else
1549 return 0;
252b5132
RH		 1550}
1551
1552static INLINE int
e3bb37b5 1553fits_in_signed_byte (offsetT num)
252b5132
RH		 1554{
1555 return (num >= -128) && (num <= 127);
47926f60 1556}
252b5132
RH		 1557
1558static INLINE int
e3bb37b5 1559fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1560{
1561 return (num & 0xff) == num;
47926f60 1562}
252b5132
RH		 1563
1564static INLINE int
e3bb37b5 1565fits_in_unsigned_word (offsetT num)
252b5132
RH		 1566{
1567 return (num & 0xffff) == num;
47926f60 1568}
252b5132
RH		 1569
1570static INLINE int
e3bb37b5 1571fits_in_signed_word (offsetT num)
252b5132
RH		 1572{
1573 return (-32768 <= num) && (num <= 32767);
47926f60 1574}
2a962e6d 1575
3e73aa7c 1576static INLINE int
e3bb37b5 1577fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1578{
1579#ifndef BFD64
1580 return 1;
1581#else
1582 return (!(((offsetT) -1 << 31) & num)
1583 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1584#endif
1585} /* fits_in_signed_long() */
2a962e6d 1586
3e73aa7c 1587static INLINE int
e3bb37b5 1588fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1589{
1590#ifndef BFD64
1591 return 1;
1592#else
1593 return (num & (((offsetT) 2 << 31) - 1)) == num;
1594#endif
1595} /* fits_in_unsigned_long() */
252b5132 1596
c0f3af97
L		 1597static INLINE int
1598fits_in_imm4 (offsetT num)
1599{
1600 return (num & 0xf) == num;
1601}
1602
40fb9820 1603static i386_operand_type
e3bb37b5 1604smallest_imm_type (offsetT num)
252b5132 1605{
40fb9820
L		 1606 i386_operand_type t;
1607
0dfbf9d7 1608 operand_type_set (&t, 0);
40fb9820
L		 1609 t.bitfield.imm64 = 1;
1610
1611 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1612 {
1613 /* This code is disabled on the 486 because all the Imm1 forms
1614 in the opcode table are slower on the i486. They're the
1615 versions with the implicitly specified single-position
1616 displacement, which has another syntax if you really want to
1617 use that form. */
40fb9820
L		 1618 t.bitfield.imm1 = 1;
1619 t.bitfield.imm8 = 1;
1620 t.bitfield.imm8s = 1;
1621 t.bitfield.imm16 = 1;
1622 t.bitfield.imm32 = 1;
1623 t.bitfield.imm32s = 1;
1624 }
1625 else if (fits_in_signed_byte (num))
1626 {
1627 t.bitfield.imm8 = 1;
1628 t.bitfield.imm8s = 1;
1629 t.bitfield.imm16 = 1;
1630 t.bitfield.imm32 = 1;
1631 t.bitfield.imm32s = 1;
1632 }
1633 else if (fits_in_unsigned_byte (num))
1634 {
1635 t.bitfield.imm8 = 1;
1636 t.bitfield.imm16 = 1;
1637 t.bitfield.imm32 = 1;
1638 t.bitfield.imm32s = 1;
1639 }
1640 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1641 {
1642 t.bitfield.imm16 = 1;
1643 t.bitfield.imm32 = 1;
1644 t.bitfield.imm32s = 1;
1645 }
1646 else if (fits_in_signed_long (num))
1647 {
1648 t.bitfield.imm32 = 1;
1649 t.bitfield.imm32s = 1;
1650 }
1651 else if (fits_in_unsigned_long (num))
1652 t.bitfield.imm32 = 1;
1653
1654 return t;
47926f60 1655}
252b5132 1656
847f7ad4 1657static offsetT
e3bb37b5 1658offset_in_range (offsetT val, int size)
847f7ad4 1659{
508866be 1660 addressT mask;
ba2adb93 1661
847f7ad4
AM		 1662 switch (size)
1663 {
508866be
L		 1664 case 1: mask = ((addressT) 1 << 8) - 1; break;
1665 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1666 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1667#ifdef BFD64
1668 case 8: mask = ((addressT) 2 << 63) - 1; break;
1669#endif
47926f60 1670 default: abort ();
847f7ad4
AM		 1671 }
1672
ba2adb93 1673 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1674 if (!use_rela_relocations)
1675 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1676 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1677
47926f60 1678 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1679 {
1680 char buf1[40], buf2[40];
1681
1682 sprint_value (buf1, val);
1683 sprint_value (buf2, val & mask);
1684 as_warn (_("%s shortened to %s"), buf1, buf2);
1685 }
1686 return val & mask;
1687}
1688
252b5132
RH		 1689/* Returns 0 if attempting to add a prefix where one from the same
1690 class already exists, 1 if non rep/repne added, 2 if rep/repne
1691 added. */
1692static int
e3bb37b5 1693add_prefix (unsigned int prefix)
252b5132
RH		 1694{
1695 int ret = 1;
b1905489 1696 unsigned int q;
252b5132 1697
29b0f896
AM		 1698 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1699 && flag_code == CODE_64BIT)
b1905489 1700 {
161a04f6
L		 1701 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1702 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1703 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1704 ret = 0;
1705 q = REX_PREFIX;
1706 }
3e73aa7c 1707 else
b1905489
JB		 1708 {
1709 switch (prefix)
1710 {
1711 default:
1712 abort ();
1713
1714 case CS_PREFIX_OPCODE:
1715 case DS_PREFIX_OPCODE:
1716 case ES_PREFIX_OPCODE:
1717 case FS_PREFIX_OPCODE:
1718 case GS_PREFIX_OPCODE:
1719 case SS_PREFIX_OPCODE:
1720 q = SEG_PREFIX;
1721 break;
1722
1723 case REPNE_PREFIX_OPCODE:
1724 case REPE_PREFIX_OPCODE:
1725 ret = 2;
1726 /* fall thru */
1727 case LOCK_PREFIX_OPCODE:
1728 q = LOCKREP_PREFIX;
1729 break;
1730
1731 case FWAIT_OPCODE:
1732 q = WAIT_PREFIX;
1733 break;
1734
1735 case ADDR_PREFIX_OPCODE:
1736 q = ADDR_PREFIX;
1737 break;
1738
1739 case DATA_PREFIX_OPCODE:
1740 q = DATA_PREFIX;
1741 break;
1742 }
1743 if (i.prefix[q] != 0)
1744 ret = 0;
1745 }
252b5132 1746
b1905489 1747 if (ret)
252b5132 1748 {
b1905489
JB		 1749 if (!i.prefix[q])
1750 ++i.prefixes;
1751 i.prefix[q] |= prefix;
252b5132 1752 }
b1905489
JB		 1753 else
1754 as_bad (_("same type of prefix used twice"));
252b5132 1755
252b5132
RH		 1756 return ret;
1757}
1758
1759static void
e3bb37b5 1760set_code_flag (int value)
eecb386c 1761{
3e73aa7c 1762 flag_code = value;
40fb9820
L		 1763 if (flag_code == CODE_64BIT)
1764 {
1765 cpu_arch_flags.bitfield.cpu64 = 1;
1766 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1767 }
1768 else
1769 {
1770 cpu_arch_flags.bitfield.cpu64 = 0;
1771 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1772 }
1773 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1774 {
1775 as_bad (_("64bit mode not supported on this CPU."));
1776 }
40fb9820 1777 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1778 {
1779 as_bad (_("32bit mode not supported on this CPU."));
1780 }
eecb386c
AM		 1781 stackop_size = '\0';
1782}
1783
1784static void
e3bb37b5 1785set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1786{
3e73aa7c 1787 flag_code = new_code_flag;
40fb9820
L		 1788 if (flag_code != CODE_16BIT)
1789 abort ();
1790 cpu_arch_flags.bitfield.cpu64 = 0;
1791 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1792 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1793}
1794
1795static void
e3bb37b5 1796set_intel_syntax (int syntax_flag)
252b5132
RH		 1797{
1798 /* Find out if register prefixing is specified. */
1799 int ask_naked_reg = 0;
1800
1801 SKIP_WHITESPACE ();
29b0f896 1802 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1803 {
1804 char *string = input_line_pointer;
1805 int e = get_symbol_end ();
1806
47926f60 1807 if (strcmp (string, "prefix") == 0)
252b5132 1808 ask_naked_reg = 1;
47926f60 1809 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1810 ask_naked_reg = -1;
1811 else
d0b47220 1812 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1813 *input_line_pointer = e;
1814 }
1815 demand_empty_rest_of_line ();
c3332e24 1816
252b5132
RH		 1817 intel_syntax = syntax_flag;
1818
1819 if (ask_naked_reg == 0)
f86103b7
AM		 1820 allow_naked_reg = (intel_syntax
1821 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1822 else
1823 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1824
e4a3b5a4 1825 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1826 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1827 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1828}
1829
1efbbeb4
L		 1830static void
1831set_intel_mnemonic (int mnemonic_flag)
1832{
e1d4d893 1833 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1834}
1835
db51cc60
L		 1836static void
1837set_allow_index_reg (int flag)
1838{
1839 allow_index_reg = flag;
1840}
1841
e413e4e9 1842static void
e3bb37b5 1843set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1844{
47926f60 1845 SKIP_WHITESPACE ();
e413e4e9 1846
29b0f896 1847 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1848 {
1849 char *string = input_line_pointer;
1850 int e = get_symbol_end ();
9103f4f4 1851 unsigned int i;
40fb9820 1852 i386_cpu_flags flags;
e413e4e9 1853
9103f4f4 1854 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1855 {
1856 if (strcmp (string, cpu_arch[i].name) == 0)
1857 {
5c6af06e
JB		 1858 if (*string != '.')
1859 {
1860 cpu_arch_name = cpu_arch[i].name;
1861 cpu_sub_arch_name = NULL;
40fb9820
L		 1862 cpu_arch_flags = cpu_arch[i].flags;
1863 if (flag_code == CODE_64BIT)
1864 {
1865 cpu_arch_flags.bitfield.cpu64 = 1;
1866 cpu_arch_flags.bitfield.cpuno64 = 0;
1867 }
1868 else
1869 {
1870 cpu_arch_flags.bitfield.cpu64 = 0;
1871 cpu_arch_flags.bitfield.cpuno64 = 1;
1872 }
ccc9c027 1873 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1874 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1875 if (!cpu_arch_tune_set)
1876 {
1877 cpu_arch_tune = cpu_arch_isa;
1878 cpu_arch_tune_flags = cpu_arch_isa_flags;
1879 }
5c6af06e
JB		 1880 break;
1881 }
40fb9820 1882
c6fb90c8
L		 1883 flags = cpu_flags_or (cpu_arch_flags,
1884 cpu_arch[i].flags);
0dfbf9d7 1885 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 1886 {
6305a203
L		 1887 if (cpu_sub_arch_name)
1888 {
1889 char *name = cpu_sub_arch_name;
1890 cpu_sub_arch_name = concat (name,
1891 cpu_arch[i].name,
1bf57e9f 1892 (const char *) NULL);
6305a203
L		 1893 free (name);
1894 }
1895 else
1896 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 1897 cpu_arch_flags = flags;
5c6af06e
JB		 1898 }
1899 *input_line_pointer = e;
1900 demand_empty_rest_of_line ();
1901 return;
e413e4e9
AM		 1902 }
1903 }
9103f4f4 1904 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1905 as_bad (_("no such architecture: `%s'"), string);
1906
1907 *input_line_pointer = e;
1908 }
1909 else
1910 as_bad (_("missing cpu architecture"));
1911
fddf5b5b
AM		 1912 no_cond_jump_promotion = 0;
1913 if (*input_line_pointer == ','
29b0f896 1914 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1915 {
1916 char *string = ++input_line_pointer;
1917 int e = get_symbol_end ();
1918
1919 if (strcmp (string, "nojumps") == 0)
1920 no_cond_jump_promotion = 1;
1921 else if (strcmp (string, "jumps") == 0)
1922 ;
1923 else
1924 as_bad (_("no such architecture modifier: `%s'"), string);
1925
1926 *input_line_pointer = e;
1927 }
1928
e413e4e9
AM		 1929 demand_empty_rest_of_line ();
1930}
1931
b9d79e03
JH		 1932unsigned long
1933i386_mach ()
1934{
1935 if (!strcmp (default_arch, "x86_64"))
1936 return bfd_mach_x86_64;
1937 else if (!strcmp (default_arch, "i386"))
1938 return bfd_mach_i386_i386;
1939 else
1940 as_fatal (_("Unknown architecture"));
1941}
b9d79e03 1942\f
252b5132
RH		 1943void
1944md_begin ()
1945{
1946 const char *hash_err;
1947
47926f60 1948 /* Initialize op_hash hash table. */
252b5132
RH		 1949 op_hash = hash_new ();
1950
1951 {
29b0f896
AM		 1952 const template *optab;
1953 templates *core_optab;
252b5132 1954
47926f60
KH		 1955 /* Setup for loop. */
1956 optab = i386_optab;
252b5132
RH		 1957 core_optab = (templates *) xmalloc (sizeof (templates));
1958 core_optab->start = optab;
1959
1960 while (1)
1961 {
1962 ++optab;
1963 if (optab->name == NULL
1964 || strcmp (optab->name, (optab - 1)->name) != 0)
1965 {
1966 /* different name --> ship out current template list;
47926f60 1967 add to hash table; & begin anew. */
252b5132
RH		 1968 core_optab->end = optab;
1969 hash_err = hash_insert (op_hash,
1970 (optab - 1)->name,
1971 (PTR) core_optab);
1972 if (hash_err)
1973 {
252b5132
RH		 1974 as_fatal (_("Internal Error: Can't hash %s: %s"),
1975 (optab - 1)->name,
1976 hash_err);
1977 }
1978 if (optab->name == NULL)
1979 break;
1980 core_optab = (templates *) xmalloc (sizeof (templates));
1981 core_optab->start = optab;
1982 }
1983 }
1984 }
1985
47926f60 1986 /* Initialize reg_hash hash table. */
252b5132
RH		 1987 reg_hash = hash_new ();
1988 {
29b0f896 1989 const reg_entry *regtab;
c3fe08fa 1990 unsigned int regtab_size = i386_regtab_size;
252b5132 1991
c3fe08fa 1992 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1993 {
1994 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1995 if (hash_err)
3e73aa7c
JH		 1996 as_fatal (_("Internal Error: Can't hash %s: %s"),
1997 regtab->reg_name,
1998 hash_err);
252b5132
RH		 1999 }
2000 }
2001
47926f60 2002 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2003 {
29b0f896
AM		 2004 int c;
2005 char *p;
252b5132
RH		 2006
2007 for (c = 0; c < 256; c++)
2008 {
3882b010 2009 if (ISDIGIT (c))
252b5132
RH		 2010 {
2011 digit_chars[c] = c;
2012 mnemonic_chars[c] = c;
2013 register_chars[c] = c;
2014 operand_chars[c] = c;
2015 }
3882b010 2016 else if (ISLOWER (c))
252b5132
RH		 2017 {
2018 mnemonic_chars[c] = c;
2019 register_chars[c] = c;
2020 operand_chars[c] = c;
2021 }
3882b010 2022 else if (ISUPPER (c))
252b5132 2023 {
3882b010 2024 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2025 register_chars[c] = mnemonic_chars[c];
2026 operand_chars[c] = c;
2027 }
2028
3882b010 2029 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2030 identifier_chars[c] = c;
2031 else if (c >= 128)
2032 {
2033 identifier_chars[c] = c;
2034 operand_chars[c] = c;
2035 }
2036 }
2037
2038#ifdef LEX_AT
2039 identifier_chars['@'] = '@';
32137342
NC		 2040#endif
2041#ifdef LEX_QM
2042 identifier_chars['?'] = '?';
2043 operand_chars['?'] = '?';
252b5132 2044#endif
252b5132 2045 digit_chars['-'] = '-';
c0f3af97 2046 mnemonic_chars['_'] = '_';
791fe849 2047 mnemonic_chars['-'] = '-';
0003779b 2048 mnemonic_chars['.'] = '.';
252b5132
RH		 2049 identifier_chars['_'] = '_';
2050 identifier_chars['.'] = '.';
2051
2052 for (p = operand_special_chars; *p != '\0'; p++)
2053 operand_chars[(unsigned char) *p] = *p;
2054 }
2055
2056#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2057 if (IS_ELF)
252b5132
RH		 2058 {
2059 record_alignment (text_section, 2);
2060 record_alignment (data_section, 2);
2061 record_alignment (bss_section, 2);
2062 }
2063#endif
a4447b93
RH		 2064
2065 if (flag_code == CODE_64BIT)
2066 {
2067 x86_dwarf2_return_column = 16;
2068 x86_cie_data_alignment = -8;
2069 }
2070 else
2071 {
2072 x86_dwarf2_return_column = 8;
2073 x86_cie_data_alignment = -4;
2074 }
252b5132
RH		 2075}
2076
2077void
e3bb37b5 2078i386_print_statistics (FILE *file)
252b5132
RH		 2079{
2080 hash_print_statistics (file, "i386 opcode", op_hash);
2081 hash_print_statistics (file, "i386 register", reg_hash);
2082}
2083\f
252b5132
RH		 2084#ifdef DEBUG386
2085
ce8a8b2f 2086/* Debugging routines for md_assemble. */
e3bb37b5 2087static void pte (template *);
40fb9820 2088static void pt (i386_operand_type);
e3bb37b5
L		 2089static void pe (expressionS *);
2090static void ps (symbolS *);
252b5132
RH		 2091
2092static void
e3bb37b5 2093pi (char *line, i386_insn *x)
252b5132 2094{
09f131f2 2095 unsigned int i;
252b5132
RH		 2096
2097 fprintf (stdout, "%s: template ", line);
2098 pte (&x->tm);
09f131f2
JH		 2099 fprintf (stdout, " address: base %s index %s scale %x\n",
2100 x->base_reg ? x->base_reg->reg_name : "none",
2101 x->index_reg ? x->index_reg->reg_name : "none",
2102 x->log2_scale_factor);
2103 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2104 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2105 fprintf (stdout, " sib: base %x index %x scale %x\n",
2106 x->sib.base, x->sib.index, x->sib.scale);
2107 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2108 (x->rex & REX_W) != 0,
2109 (x->rex & REX_R) != 0,
2110 (x->rex & REX_X) != 0,
2111 (x->rex & REX_B) != 0);
85f10a01
MM		 2112 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2113 x->drex.reg, x->drex.rex);
252b5132
RH		 2114 for (i = 0; i < x->operands; i++)
2115 {
2116 fprintf (stdout, " #%d: ", i + 1);
2117 pt (x->types[i]);
2118 fprintf (stdout, "\n");
40fb9820
L		 2119 if (x->types[i].bitfield.reg8
2120 || x->types[i].bitfield.reg16
2121 || x->types[i].bitfield.reg32
2122 || x->types[i].bitfield.reg64
2123 || x->types[i].bitfield.regmmx
2124 || x->types[i].bitfield.regxmm
c0f3af97 2125 || x->types[i].bitfield.regymm
40fb9820
L		 2126 || x->types[i].bitfield.sreg2
2127 || x->types[i].bitfield.sreg3
2128 || x->types[i].bitfield.control
2129 || x->types[i].bitfield.debug
2130 || x->types[i].bitfield.test)
520dc8e8 2131 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2132 if (operand_type_check (x->types[i], imm))
520dc8e8 2133 pe (x->op[i].imms);
40fb9820 2134 if (operand_type_check (x->types[i], disp))
520dc8e8 2135 pe (x->op[i].disps);
252b5132
RH		 2136 }
2137}
2138
2139static void
e3bb37b5 2140pte (template *t)
252b5132 2141{
09f131f2 2142 unsigned int i;
252b5132 2143 fprintf (stdout, " %d operands ", t->operands);
47926f60 2144 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2145 if (t->extension_opcode != None)
2146 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2147 if (t->opcode_modifier.d)
252b5132 2148 fprintf (stdout, "D");
40fb9820 2149 if (t->opcode_modifier.w)
252b5132
RH		 2150 fprintf (stdout, "W");
2151 fprintf (stdout, "\n");
2152 for (i = 0; i < t->operands; i++)
2153 {
2154 fprintf (stdout, " #%d type ", i + 1);
2155 pt (t->operand_types[i]);
2156 fprintf (stdout, "\n");
2157 }
2158}
2159
2160static void
e3bb37b5 2161pe (expressionS *e)
252b5132 2162{
24eab124 2163 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2164 fprintf (stdout, " add_number %ld (%lx)\n",
2165 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2166 if (e->X_add_symbol)
2167 {
2168 fprintf (stdout, " add_symbol ");
2169 ps (e->X_add_symbol);
2170 fprintf (stdout, "\n");
2171 }
2172 if (e->X_op_symbol)
2173 {
2174 fprintf (stdout, " op_symbol ");
2175 ps (e->X_op_symbol);
2176 fprintf (stdout, "\n");
2177 }
2178}
2179
2180static void
e3bb37b5 2181ps (symbolS *s)
252b5132
RH		 2182{
2183 fprintf (stdout, "%s type %s%s",
2184 S_GET_NAME (s),
2185 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2186 segment_name (S_GET_SEGMENT (s)));
2187}
2188
7b81dfbb 2189static struct type_name
252b5132 2190 {
40fb9820
L		 2191 i386_operand_type mask;
2192 const char *name;
252b5132 2193 }
7b81dfbb 2194const type_names[] =
252b5132 2195{
40fb9820
L		 2196 { OPERAND_TYPE_REG8, "r8" },
2197 { OPERAND_TYPE_REG16, "r16" },
2198 { OPERAND_TYPE_REG32, "r32" },
2199 { OPERAND_TYPE_REG64, "r64" },
2200 { OPERAND_TYPE_IMM8, "i8" },
2201 { OPERAND_TYPE_IMM8, "i8s" },
2202 { OPERAND_TYPE_IMM16, "i16" },
2203 { OPERAND_TYPE_IMM32, "i32" },
2204 { OPERAND_TYPE_IMM32S, "i32s" },
2205 { OPERAND_TYPE_IMM64, "i64" },
2206 { OPERAND_TYPE_IMM1, "i1" },
2207 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2208 { OPERAND_TYPE_DISP8, "d8" },
2209 { OPERAND_TYPE_DISP16, "d16" },
2210 { OPERAND_TYPE_DISP32, "d32" },
2211 { OPERAND_TYPE_DISP32S, "d32s" },
2212 { OPERAND_TYPE_DISP64, "d64" },
2213 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2214 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2215 { OPERAND_TYPE_CONTROL, "control reg" },
2216 { OPERAND_TYPE_TEST, "test reg" },
2217 { OPERAND_TYPE_DEBUG, "debug reg" },
2218 { OPERAND_TYPE_FLOATREG, "FReg" },
2219 { OPERAND_TYPE_FLOATACC, "FAcc" },
2220 { OPERAND_TYPE_SREG2, "SReg2" },
2221 { OPERAND_TYPE_SREG3, "SReg3" },
2222 { OPERAND_TYPE_ACC, "Acc" },
2223 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2224 { OPERAND_TYPE_REGMMX, "rMMX" },
2225 { OPERAND_TYPE_REGXMM, "rXMM" },
2226 { OPERAND_TYPE_ESSEG, "es" },
c0f3af97 2227 { OPERAND_TYPE_VEX_IMM4, "VEX i4" },
252b5132
RH		 2228};
2229
2230static void
40fb9820 2231pt (i386_operand_type t)
252b5132 2232{
40fb9820 2233 unsigned int j;
c6fb90c8 2234 i386_operand_type a;
252b5132 2235
40fb9820 2236 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2237 {
2238 a = operand_type_and (t, type_names[j].mask);
2239 if (!UINTS_ALL_ZERO (a))
2240 fprintf (stdout, "%s, ", type_names[j].name);
2241 }
252b5132
RH		 2242 fflush (stdout);
2243}
2244
2245#endif /* DEBUG386 */
2246\f
252b5132 2247static bfd_reloc_code_real_type
3956db08 2248reloc (unsigned int size,
64e74474
AM		 2249 int pcrel,
2250 int sign,
2251 bfd_reloc_code_real_type other)
252b5132 2252{
47926f60 2253 if (other != NO_RELOC)
3956db08
JB		 2254 {
2255 reloc_howto_type *reloc;
2256
2257 if (size == 8)
2258 switch (other)
2259 {
64e74474
AM		 2260 case BFD_RELOC_X86_64_GOT32:
2261 return BFD_RELOC_X86_64_GOT64;
2262 break;
2263 case BFD_RELOC_X86_64_PLTOFF64:
2264 return BFD_RELOC_X86_64_PLTOFF64;
2265 break;
2266 case BFD_RELOC_X86_64_GOTPC32:
2267 other = BFD_RELOC_X86_64_GOTPC64;
2268 break;
2269 case BFD_RELOC_X86_64_GOTPCREL:
2270 other = BFD_RELOC_X86_64_GOTPCREL64;
2271 break;
2272 case BFD_RELOC_X86_64_TPOFF32:
2273 other = BFD_RELOC_X86_64_TPOFF64;
2274 break;
2275 case BFD_RELOC_X86_64_DTPOFF32:
2276 other = BFD_RELOC_X86_64_DTPOFF64;
2277 break;
2278 default:
2279 break;
3956db08 2280 }
e05278af
JB		 2281
2282 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2283 if (size == 4 && flag_code != CODE_64BIT)
2284 sign = -1;
2285
3956db08
JB		 2286 reloc = bfd_reloc_type_lookup (stdoutput, other);
2287 if (!reloc)
2288 as_bad (_("unknown relocation (%u)"), other);
2289 else if (size != bfd_get_reloc_size (reloc))
2290 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2291 bfd_get_reloc_size (reloc),
2292 size);
2293 else if (pcrel && !reloc->pc_relative)
2294 as_bad (_("non-pc-relative relocation for pc-relative field"));
2295 else if ((reloc->complain_on_overflow == complain_overflow_signed
2296 && !sign)
2297 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2298 && sign > 0))
3956db08
JB		 2299 as_bad (_("relocated field and relocation type differ in signedness"));
2300 else
2301 return other;
2302 return NO_RELOC;
2303 }
252b5132
RH		 2304
2305 if (pcrel)
2306 {
3e73aa7c 2307 if (!sign)
3956db08 2308 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2309 switch (size)
2310 {
2311 case 1: return BFD_RELOC_8_PCREL;
2312 case 2: return BFD_RELOC_16_PCREL;
2313 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2314 case 8: return BFD_RELOC_64_PCREL;
252b5132 2315 }
3956db08 2316 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2317 }
2318 else
2319 {
3956db08 2320 if (sign > 0)
e5cb08ac 2321 switch (size)
3e73aa7c
JH		 2322 {
2323 case 4: return BFD_RELOC_X86_64_32S;
2324 }
2325 else
2326 switch (size)
2327 {
2328 case 1: return BFD_RELOC_8;
2329 case 2: return BFD_RELOC_16;
2330 case 4: return BFD_RELOC_32;
2331 case 8: return BFD_RELOC_64;
2332 }
3956db08
JB		 2333 as_bad (_("cannot do %s %u byte relocation"),
2334 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2335 }
2336
bfb32b52 2337 abort ();
252b5132
RH		 2338 return BFD_RELOC_NONE;
2339}
2340
47926f60
KH		 2341/* Here we decide which fixups can be adjusted to make them relative to
2342 the beginning of the section instead of the symbol. Basically we need
2343 to make sure that the dynamic relocations are done correctly, so in
2344 some cases we force the original symbol to be used. */
2345
252b5132 2346int
e3bb37b5 2347tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2348{
6d249963 2349#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2350 if (!IS_ELF)
31312f95
AM		 2351 return 1;
2352
a161fe53
AM		 2353 /* Don't adjust pc-relative references to merge sections in 64-bit
2354 mode. */
2355 if (use_rela_relocations
2356 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2357 && fixP->fx_pcrel)
252b5132 2358 return 0;
31312f95 2359
8d01d9a9
AJ		 2360 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2361 and changed later by validate_fix. */
2362 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2363 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2364 return 0;
2365
ce8a8b2f 2366 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2367 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2368 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2369 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2370 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2371 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2372 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2373 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2374 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2375 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2376 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2377 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2378 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2379 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2380 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2381 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2382 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2383 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2384 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2385 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2386 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2387 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2388 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2389 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2390 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2391 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2392 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2393 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2394 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2395 return 0;
31312f95 2396#endif
252b5132
RH		 2397 return 1;
2398}
252b5132 2399
b4cac588 2400static int
e3bb37b5 2401intel_float_operand (const char *mnemonic)
252b5132 2402{
9306ca4a
JB		 2403 /* Note that the value returned is meaningful only for opcodes with (memory)
2404 operands, hence the code here is free to improperly handle opcodes that
2405 have no operands (for better performance and smaller code). */
2406
2407 if (mnemonic[0] != 'f')
2408 return 0; /* non-math */
2409
2410 switch (mnemonic[1])
2411 {
2412 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2413 the fs segment override prefix not currently handled because no
2414 call path can make opcodes without operands get here */
2415 case 'i':
2416 return 2 /* integer op */;
2417 case 'l':
2418 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2419 return 3; /* fldcw/fldenv */
2420 break;
2421 case 'n':
2422 if (mnemonic[2] != 'o' /* fnop */)
2423 return 3; /* non-waiting control op */
2424 break;
2425 case 'r':
2426 if (mnemonic[2] == 's')
2427 return 3; /* frstor/frstpm */
2428 break;
2429 case 's':
2430 if (mnemonic[2] == 'a')
2431 return 3; /* fsave */
2432 if (mnemonic[2] == 't')
2433 {
2434 switch (mnemonic[3])
2435 {
2436 case 'c': /* fstcw */
2437 case 'd': /* fstdw */
2438 case 'e': /* fstenv */
2439 case 's': /* fsts[gw] */
2440 return 3;
2441 }
2442 }
2443 break;
2444 case 'x':
2445 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2446 return 0; /* fxsave/fxrstor are not really math ops */
2447 break;
2448 }
252b5132 2449
9306ca4a 2450 return 1;
252b5132
RH		 2451}
2452
c0f3af97
L		 2453/* Build the VEX prefix. */
2454
2455static void
2456build_vex_prefix (void)
2457{
2458 unsigned int register_specifier;
2459 unsigned int implied_prefix;
2460 unsigned int vector_length;
2461
2462 /* Check register specifier. */
2463 if (i.vex.register_specifier)
2464 {
2465 register_specifier = i.vex.register_specifier->reg_num;
2466 if ((i.vex.register_specifier->reg_flags & RegRex))
2467 register_specifier += 8;
2468 register_specifier = ~register_specifier & 0xf;
2469 }
2470 else
2471 register_specifier = 0xf;
2472
2473 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2474
2475 switch ((i.tm.base_opcode >> 8) & 0xff)
2476 {
2477 case 0:
2478 implied_prefix = 0;
2479 break;
2480 case DATA_PREFIX_OPCODE:
2481 implied_prefix = 1;
2482 break;
2483 case REPE_PREFIX_OPCODE:
2484 implied_prefix = 2;
2485 break;
2486 case REPNE_PREFIX_OPCODE:
2487 implied_prefix = 3;
2488 break;
2489 default:
2490 abort ();
2491 }
2492
2493 /* Use 2-byte VEX prefix if possible. */
2494 if (i.tm.opcode_modifier.vex0f
2495 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2496 {
2497 /* 2-byte VEX prefix. */
2498 unsigned int r;
2499
2500 i.vex.length = 2;
2501 i.vex.bytes[0] = 0xc5;
2502
2503 /* Check the REX.R bit. */
2504 r = (i.rex & REX_R) ? 0 : 1;
2505 i.vex.bytes[1] = (r << 7
2506 | register_specifier << 3
2507 | vector_length << 2
2508 | implied_prefix);
2509 }
2510 else
2511 {
2512 /* 3-byte VEX prefix. */
2513 unsigned int m, w;
2514
2515 if (i.tm.opcode_modifier.vex0f)
2516 m = 0x1;
2517 else if (i.tm.opcode_modifier.vex0f38)
2518 m = 0x2;
2519 else if (i.tm.opcode_modifier.vex0f3a)
2520 m = 0x3;
2521 else
2522 abort ();
2523
2524 i.vex.length = 3;
2525 i.vex.bytes[0] = 0xc4;
2526
2527 /* The high 3 bits of the second VEX byte are 1's compliment
2528 of RXB bits from REX. */
2529 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2530
2531 /* Check the REX.W bit. */
2532 w = (i.rex & REX_W) ? 1 : 0;
2533 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2534 {
2535 if (w)
2536 abort ();
2537
2538 if (i.tm.opcode_modifier.vexw1)
2539 w = 1;
2540 }
2541
2542 i.vex.bytes[2] = (w << 7
2543 | register_specifier << 3
2544 | vector_length << 2
2545 | implied_prefix);
2546 }
2547}
2548
65da13b5
L		 2549static void
2550process_immext (void)
2551{
2552 expressionS *exp;
2553
2554 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2555 {
1fed0ba1
L		 2556 /* SSE3 Instructions have the fixed operands with an opcode
2557 suffix which is coded in the same place as an 8-bit immediate
2558 field would be. Here we check those operands and remove them
2559 afterwards. */
65da13b5
L		 2560 unsigned int x;
2561
2562 for (x = 0; x < i.operands; x++)
2563 if (i.op[x].regs->reg_num != x)
2564 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2565 register_prefix, i.op[x].regs->reg_name, x + 1,
2566 i.tm.name);
2567
2568 i.operands = 0;
65da13b5
L		 2569 }
2570
c0f3af97 2571 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2572 which is coded in the same place as an 8-bit immediate field
2573 would be. Here we fake an 8-bit immediate operand from the
2574 opcode suffix stored in tm.extension_opcode.
2575
c0f3af97
L		 2576 SSE5 and AVX instructions also use this encoding, for some of
2577 3 argument instructions. */
65da13b5
L		 2578
2579 assert (i.imm_operands == 0
2580 && (i.operands <= 2
2581 || (i.tm.cpu_flags.bitfield.cpusse5
c0f3af97
L		 2582 && i.operands <= 3)
2583 || (i.tm.opcode_modifier.vex
2584 && i.operands <= 4)));
65da13b5
L		 2585
2586 exp = &im_expressions[i.imm_operands++];
2587 i.op[i.operands].imms = exp;
2588 i.types[i.operands] = imm8;
2589 i.operands++;
2590 exp->X_op = O_constant;
2591 exp->X_add_number = i.tm.extension_opcode;
2592 i.tm.extension_opcode = None;
2593}
2594
252b5132
RH		 2595/* This is the guts of the machine-dependent assembler. LINE points to a
2596 machine dependent instruction. This function is supposed to emit
2597 the frags/bytes it assembles to. */
2598
2599void
65da13b5 2600md_assemble (char *line)
252b5132 2601{
40fb9820 2602 unsigned int j;
252b5132
RH		 2603 char mnemonic[MAX_MNEM_SIZE];
2604
47926f60 2605 /* Initialize globals. */
252b5132
RH		 2606 memset (&i, '\0', sizeof (i));
2607 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2608 i.reloc[j] = NO_RELOC;
252b5132
RH		 2609 memset (disp_expressions, '\0', sizeof (disp_expressions));
2610 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2611 save_stack_p = save_stack;
252b5132
RH		 2612
2613 /* First parse an instruction mnemonic & call i386_operand for the operands.
2614 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2615 start of a (possibly prefixed) mnemonic. */
252b5132 2616
29b0f896
AM		 2617 line = parse_insn (line, mnemonic);
2618 if (line == NULL)
2619 return;
252b5132 2620
29b0f896
AM		 2621 line = parse_operands (line, mnemonic);
2622 if (line == NULL)
2623 return;
252b5132 2624
29b0f896
AM		 2625 /* Now we've parsed the mnemonic into a set of templates, and have the
2626 operands at hand. */
2627
2628 /* All intel opcodes have reversed operands except for "bound" and
2629 "enter". We also don't reverse intersegment "jmp" and "call"
2630 instructions with 2 immediate operands so that the immediate segment
050dfa73 2631 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2632 if (intel_syntax
2633 && i.operands > 1
29b0f896 2634 && (strcmp (mnemonic, "bound") != 0)
30123838 2635 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2636 && !(operand_type_check (i.types[0], imm)
2637 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2638 swap_operands ();
2639
ec56d5c0
JB		 2640 /* The order of the immediates should be reversed
2641 for 2 immediates extrq and insertq instructions */
2642 if (i.imm_operands == 2
2643 && (strcmp (mnemonic, "extrq") == 0
2644 || strcmp (mnemonic, "insertq") == 0))
2645 swap_2_operands (0, 1);
2646
29b0f896
AM		 2647 if (i.imm_operands)
2648 optimize_imm ();
2649
b300c311
L		 2650 /* Don't optimize displacement for movabs since it only takes 64bit
2651 displacement. */
2652 if (i.disp_operands
2653 && (flag_code != CODE_64BIT
2654 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2655 optimize_disp ();
2656
2657 /* Next, we find a template that matches the given insn,
2658 making sure the overlap of the given operands types is consistent
2659 with the template operand types. */
252b5132 2660
29b0f896
AM		 2661 if (!match_template ())
2662 return;
252b5132 2663
321fd21e
L		 2664 /* Zap movzx and movsx suffix. The suffix has been set from
2665 "word ptr" or "byte ptr" on the source operand in Intel syntax
2666 or extracted from mnemonic in AT&T syntax. But we'll use
2667 the destination register to choose the suffix for encoding. */
2668 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2669 {
321fd21e
L		 2670 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2671 there is no suffix, the default will be byte extension. */
2672 if (i.reg_operands != 2
2673 && !i.suffix
2674 && intel_syntax)
2675 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2676
2677 i.suffix = 0;
cd61ebfe 2678 }
24eab124 2679
40fb9820 2680 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2681 if (!add_prefix (FWAIT_OPCODE))
2682 return;
252b5132 2683
29b0f896 2684 /* Check string instruction segment overrides. */
40fb9820 2685 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2686 {
2687 if (!check_string ())
5dd0794d 2688 return;
29b0f896 2689 }
5dd0794d 2690
29b0f896
AM		 2691 if (!process_suffix ())
2692 return;
e413e4e9 2693
29b0f896
AM		 2694 /* Make still unresolved immediate matches conform to size of immediate
2695 given in i.suffix. */
2696 if (!finalize_imm ())
2697 return;
252b5132 2698
40fb9820 2699 if (i.types[0].bitfield.imm1)
29b0f896 2700 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2701
40fb9820 2702 for (j = 0; j < 3; j++)
c6fb90c8
L		 2703 if (i.types[j].bitfield.inoutportreg
2704 || i.types[j].bitfield.shiftcount
2705 || i.types[j].bitfield.acc
2706 || i.types[j].bitfield.floatacc)
40fb9820
L		 2707 i.reg_operands--;
2708
c0f3af97
L		 2709 /* ImmExt should be processed after SSE2AVX. */
2710 if (!i.tm.opcode_modifier.sse2avx
2711 && i.tm.opcode_modifier.immext)
65da13b5 2712 process_immext ();
252b5132 2713
29b0f896
AM		 2714 /* For insns with operands there are more diddles to do to the opcode. */
2715 if (i.operands)
2716 {
2717 if (!process_operands ())
2718 return;
2719 }
40fb9820 2720 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2721 {
2722 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2723 as_warn (_("translating to `%sp'"), i.tm.name);
2724 }
252b5132 2725
c0f3af97
L		 2726 if (i.tm.opcode_modifier.vex)
2727 build_vex_prefix ();
2728
29b0f896
AM		 2729 /* Handle conversion of 'int $3' --> special int3 insn. */
2730 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2731 {
2732 i.tm.base_opcode = INT3_OPCODE;
2733 i.imm_operands = 0;
2734 }
252b5132 2735
40fb9820
L		 2736 if ((i.tm.opcode_modifier.jump
2737 || i.tm.opcode_modifier.jumpbyte
2738 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2739 && i.op[0].disps->X_op == O_constant)
2740 {
2741 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2742 the absolute address given by the constant. Since ix86 jumps and
2743 calls are pc relative, we need to generate a reloc. */
2744 i.op[0].disps->X_add_symbol = &abs_symbol;
2745 i.op[0].disps->X_op = O_symbol;
2746 }
252b5132 2747
40fb9820 2748 if (i.tm.opcode_modifier.rex64)
161a04f6 2749 i.rex |= REX_W;
252b5132 2750
29b0f896
AM		 2751 /* For 8 bit registers we need an empty rex prefix. Also if the
2752 instruction already has a prefix, we need to convert old
2753 registers to new ones. */
773f551c 2754
40fb9820 2755 if ((i.types[0].bitfield.reg8
29b0f896 2756 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2757 || (i.types[1].bitfield.reg8
29b0f896 2758 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2759 || ((i.types[0].bitfield.reg8
2760 || i.types[1].bitfield.reg8)
29b0f896
AM		 2761 && i.rex != 0))
2762 {
2763 int x;
726c5dcd 2764
29b0f896
AM		 2765 i.rex |= REX_OPCODE;
2766 for (x = 0; x < 2; x++)
2767 {
2768 /* Look for 8 bit operand that uses old registers. */
40fb9820 2769 if (i.types[x].bitfield.reg8
29b0f896 2770 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2771 {
29b0f896
AM		 2772 /* In case it is "hi" register, give up. */
2773 if (i.op[x].regs->reg_num > 3)
a540244d 2774 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2775 "instruction requiring REX prefix."),
a540244d 2776 register_prefix, i.op[x].regs->reg_name);
773f551c 2777
29b0f896
AM		 2778 /* Otherwise it is equivalent to the extended register.
2779 Since the encoding doesn't change this is merely
2780 cosmetic cleanup for debug output. */
2781
2782 i.op[x].regs = i.op[x].regs + 8;
773f551c 2783 }
29b0f896
AM		 2784 }
2785 }
773f551c 2786
85f10a01
MM		 2787 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2788 REX prefix. */
2789 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2790 {
2791 i.drex.rex = i.rex;
2792 i.rex = 0;
2793 }
2794 else if (i.rex != 0)
29b0f896
AM		 2795 add_prefix (REX_OPCODE | i.rex);
2796
2797 /* We are ready to output the insn. */
2798 output_insn ();
2799}
2800
2801static char *
e3bb37b5 2802parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2803{
2804 char *l = line;
2805 char *token_start = l;
2806 char *mnem_p;
5c6af06e
JB		 2807 int supported;
2808 const template *t;
29b0f896
AM		 2809
2810 /* Non-zero if we found a prefix only acceptable with string insns. */
2811 const char *expecting_string_instruction = NULL;
45288df1 2812
29b0f896
AM		 2813 while (1)
2814 {
2815 mnem_p = mnemonic;
2816 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2817 {
2818 mnem_p++;
2819 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2820 {
29b0f896
AM		 2821 as_bad (_("no such instruction: `%s'"), token_start);
2822 return NULL;
2823 }
2824 l++;
2825 }
2826 if (!is_space_char (*l)
2827 && *l != END_OF_INSN
e44823cf
JB		 2828 && (intel_syntax
2829 || (*l != PREFIX_SEPARATOR
2830 && *l != ',')))
29b0f896
AM		 2831 {
2832 as_bad (_("invalid character %s in mnemonic"),
2833 output_invalid (*l));
2834 return NULL;
2835 }
2836 if (token_start == l)
2837 {
e44823cf 2838 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2839 as_bad (_("expecting prefix; got nothing"));
2840 else
2841 as_bad (_("expecting mnemonic; got nothing"));
2842 return NULL;
2843 }
45288df1 2844
29b0f896
AM		 2845 /* Look up instruction (or prefix) via hash table. */
2846 current_templates = hash_find (op_hash, mnemonic);
47926f60 2847
29b0f896
AM		 2848 if (*l != END_OF_INSN
2849 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2850 && current_templates
40fb9820 2851 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2852 {
c6fb90c8 2853 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2854 {
2855 as_bad ((flag_code != CODE_64BIT
2856 ? _("`%s' is only supported in 64-bit mode")
2857 : _("`%s' is not supported in 64-bit mode")),
2858 current_templates->start->name);
2859 return NULL;
2860 }
29b0f896
AM		 2861 /* If we are in 16-bit mode, do not allow addr16 or data16.
2862 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2863 if ((current_templates->start->opcode_modifier.size16
2864 || current_templates->start->opcode_modifier.size32)
29b0f896 2865 && flag_code != CODE_64BIT
40fb9820 2866 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2867 ^ (flag_code == CODE_16BIT)))
2868 {
2869 as_bad (_("redundant %s prefix"),
2870 current_templates->start->name);
2871 return NULL;
45288df1 2872 }
29b0f896
AM		 2873 /* Add prefix, checking for repeated prefixes. */
2874 switch (add_prefix (current_templates->start->base_opcode))
2875 {
2876 case 0:
2877 return NULL;
2878 case 2:
2879 expecting_string_instruction = current_templates->start->name;
2880 break;
2881 }
2882 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2883 token_start = ++l;
2884 }
2885 else
2886 break;
2887 }
45288df1 2888
29b0f896
AM		 2889 if (!current_templates)
2890 {
2891 /* See if we can get a match by trimming off a suffix. */
2892 switch (mnem_p[-1])
2893 {
2894 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2895 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2896 i.suffix = SHORT_MNEM_SUFFIX;
2897 else
29b0f896
AM		 2898 case BYTE_MNEM_SUFFIX:
2899 case QWORD_MNEM_SUFFIX:
2900 i.suffix = mnem_p[-1];
2901 mnem_p[-1] = '\0';
2902 current_templates = hash_find (op_hash, mnemonic);
2903 break;
2904 case SHORT_MNEM_SUFFIX:
2905 case LONG_MNEM_SUFFIX:
2906 if (!intel_syntax)
2907 {
2908 i.suffix = mnem_p[-1];
2909 mnem_p[-1] = '\0';
2910 current_templates = hash_find (op_hash, mnemonic);
2911 }
2912 break;
252b5132 2913
29b0f896
AM		 2914 /* Intel Syntax. */
2915 case 'd':
2916 if (intel_syntax)
2917 {
9306ca4a 2918 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2919 i.suffix = SHORT_MNEM_SUFFIX;
2920 else
2921 i.suffix = LONG_MNEM_SUFFIX;
2922 mnem_p[-1] = '\0';
2923 current_templates = hash_find (op_hash, mnemonic);
2924 }
2925 break;
2926 }
2927 if (!current_templates)
2928 {
2929 as_bad (_("no such instruction: `%s'"), token_start);
2930 return NULL;
2931 }
2932 }
252b5132 2933
40fb9820
L		 2934 if (current_templates->start->opcode_modifier.jump
2935 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2936 {
2937 /* Check for a branch hint. We allow ",pt" and ",pn" for
2938 predict taken and predict not taken respectively.
2939 I'm not sure that branch hints actually do anything on loop
2940 and jcxz insns (JumpByte) for current Pentium4 chips. They
2941 may work in the future and it doesn't hurt to accept them
2942 now. */
2943 if (l[0] == ',' && l[1] == 'p')
2944 {
2945 if (l[2] == 't')
2946 {
2947 if (!add_prefix (DS_PREFIX_OPCODE))
2948 return NULL;
2949 l += 3;
2950 }
2951 else if (l[2] == 'n')
2952 {
2953 if (!add_prefix (CS_PREFIX_OPCODE))
2954 return NULL;
2955 l += 3;
2956 }
2957 }
2958 }
2959 /* Any other comma loses. */
2960 if (*l == ',')
2961 {
2962 as_bad (_("invalid character %s in mnemonic"),
2963 output_invalid (*l));
2964 return NULL;
2965 }
252b5132 2966
29b0f896 2967 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2968 supported = 0;
2969 for (t = current_templates->start; t < current_templates->end; ++t)
2970 {
c0f3af97
L		 2971 supported |= cpu_flags_match (t);
2972 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 2973 goto skip;
5c6af06e 2974 }
3629bb00 2975
c0f3af97 2976 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 2977 {
2978 as_bad (flag_code == CODE_64BIT
2979 ? _("`%s' is not supported in 64-bit mode")
2980 : _("`%s' is only supported in 64-bit mode"),
2981 current_templates->start->name);
2982 return NULL;
2983 }
c0f3af97 2984 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 2985 {
3629bb00
L		 2986 as_bad (_("`%s' is not supported on `%s%s'"),
2987 current_templates->start->name, cpu_arch_name,
2988 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2989 return NULL;
29b0f896 2990 }
3629bb00
L		 2991
2992skip:
2993 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 2994 && (flag_code != CODE_16BIT))
29b0f896
AM		 2995 {
2996 as_warn (_("use .code16 to ensure correct addressing mode"));
2997 }
252b5132 2998
29b0f896 2999 /* Check for rep/repne without a string instruction. */
f41bbced 3000 if (expecting_string_instruction)
29b0f896 3001 {
f41bbced
JB		 3002 static templates override;
3003
3004 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3005 if (t->opcode_modifier.isstring)
f41bbced
JB		 3006 break;
3007 if (t >= current_templates->end)
3008 {
3009 as_bad (_("expecting string instruction after `%s'"),
64e74474 3010 expecting_string_instruction);
f41bbced
JB		 3011 return NULL;
3012 }
3013 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3014 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3015 break;
3016 override.end = t;
3017 current_templates = &override;
29b0f896 3018 }
252b5132 3019
29b0f896
AM		 3020 return l;
3021}
252b5132 3022
29b0f896 3023static char *
e3bb37b5 3024parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3025{
3026 char *token_start;
3138f287 3027
29b0f896
AM		 3028 /* 1 if operand is pending after ','. */
3029 unsigned int expecting_operand = 0;
252b5132 3030
29b0f896
AM		 3031 /* Non-zero if operand parens not balanced. */
3032 unsigned int paren_not_balanced;
3033
3034 while (*l != END_OF_INSN)
3035 {
3036 /* Skip optional white space before operand. */
3037 if (is_space_char (*l))
3038 ++l;
3039 if (!is_operand_char (*l) && *l != END_OF_INSN)
3040 {
3041 as_bad (_("invalid character %s before operand %d"),
3042 output_invalid (*l),
3043 i.operands + 1);
3044 return NULL;
3045 }
3046 token_start = l; /* after white space */
3047 paren_not_balanced = 0;
3048 while (paren_not_balanced || *l != ',')
3049 {
3050 if (*l == END_OF_INSN)
3051 {
3052 if (paren_not_balanced)
3053 {
3054 if (!intel_syntax)
3055 as_bad (_("unbalanced parenthesis in operand %d."),
3056 i.operands + 1);
3057 else
3058 as_bad (_("unbalanced brackets in operand %d."),
3059 i.operands + 1);
3060 return NULL;
3061 }
3062 else
3063 break; /* we are done */
3064 }
3065 else if (!is_operand_char (*l) && !is_space_char (*l))
3066 {
3067 as_bad (_("invalid character %s in operand %d"),
3068 output_invalid (*l),
3069 i.operands + 1);
3070 return NULL;
3071 }
3072 if (!intel_syntax)
3073 {
3074 if (*l == '(')
3075 ++paren_not_balanced;
3076 if (*l == ')')
3077 --paren_not_balanced;
3078 }
3079 else
3080 {
3081 if (*l == '[')
3082 ++paren_not_balanced;
3083 if (*l == ']')
3084 --paren_not_balanced;
3085 }
3086 l++;
3087 }
3088 if (l != token_start)
3089 { /* Yes, we've read in another operand. */
3090 unsigned int operand_ok;
3091 this_operand = i.operands++;
7d5e4556 3092 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3093 if (i.operands > MAX_OPERANDS)
3094 {
3095 as_bad (_("spurious operands; (%d operands/instruction max)"),
3096 MAX_OPERANDS);
3097 return NULL;
3098 }
3099 /* Now parse operand adding info to 'i' as we go along. */
3100 END_STRING_AND_SAVE (l);
3101
3102 if (intel_syntax)
3103 operand_ok =
3104 i386_intel_operand (token_start,
3105 intel_float_operand (mnemonic));
3106 else
a7619375 3107 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3108
3109 RESTORE_END_STRING (l);
3110 if (!operand_ok)
3111 return NULL;
3112 }
3113 else
3114 {
3115 if (expecting_operand)
3116 {
3117 expecting_operand_after_comma:
3118 as_bad (_("expecting operand after ','; got nothing"));
3119 return NULL;
3120 }
3121 if (*l == ',')
3122 {
3123 as_bad (_("expecting operand before ','; got nothing"));
3124 return NULL;
3125 }
3126 }
7f3f1ea2 3127
29b0f896
AM		 3128 /* Now *l must be either ',' or END_OF_INSN. */
3129 if (*l == ',')
3130 {
3131 if (*++l == END_OF_INSN)
3132 {
3133 /* Just skip it, if it's \n complain. */
3134 goto expecting_operand_after_comma;
3135 }
3136 expecting_operand = 1;
3137 }
3138 }
3139 return l;
3140}
7f3f1ea2 3141
050dfa73 3142static void
4d456e3d 3143swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3144{
3145 union i386_op temp_op;
40fb9820 3146 i386_operand_type temp_type;
050dfa73 3147 enum bfd_reloc_code_real temp_reloc;
4eed87de 3148
050dfa73
MM		 3149 temp_type = i.types[xchg2];
3150 i.types[xchg2] = i.types[xchg1];
3151 i.types[xchg1] = temp_type;
3152 temp_op = i.op[xchg2];
3153 i.op[xchg2] = i.op[xchg1];
3154 i.op[xchg1] = temp_op;
3155 temp_reloc = i.reloc[xchg2];
3156 i.reloc[xchg2] = i.reloc[xchg1];
3157 i.reloc[xchg1] = temp_reloc;
3158}
3159
29b0f896 3160static void
e3bb37b5 3161swap_operands (void)
29b0f896 3162{
b7c61d9a 3163 switch (i.operands)
050dfa73 3164 {
c0f3af97 3165 case 5:
b7c61d9a 3166 case 4:
4d456e3d 3167 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3168 case 3:
3169 case 2:
4d456e3d 3170 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3171 break;
3172 default:
3173 abort ();
29b0f896 3174 }
29b0f896
AM		 3175
3176 if (i.mem_operands == 2)
3177 {
3178 const seg_entry *temp_seg;
3179 temp_seg = i.seg[0];
3180 i.seg[0] = i.seg[1];
3181 i.seg[1] = temp_seg;
3182 }
3183}
252b5132 3184
29b0f896
AM		 3185/* Try to ensure constant immediates are represented in the smallest
3186 opcode possible. */
3187static void
e3bb37b5 3188optimize_imm (void)
29b0f896
AM		 3189{
3190 char guess_suffix = 0;
3191 int op;
252b5132 3192
29b0f896
AM		 3193 if (i.suffix)
3194 guess_suffix = i.suffix;
3195 else if (i.reg_operands)
3196 {
3197 /* Figure out a suffix from the last register operand specified.
3198 We can't do this properly yet, ie. excluding InOutPortReg,
3199 but the following works for instructions with immediates.
3200 In any case, we can't set i.suffix yet. */
3201 for (op = i.operands; --op >= 0;)
40fb9820
L		 3202 if (i.types[op].bitfield.reg8)
3203 {
3204 guess_suffix = BYTE_MNEM_SUFFIX;
3205 break;
3206 }
3207 else if (i.types[op].bitfield.reg16)
252b5132 3208 {
40fb9820
L		 3209 guess_suffix = WORD_MNEM_SUFFIX;
3210 break;
3211 }
3212 else if (i.types[op].bitfield.reg32)
3213 {
3214 guess_suffix = LONG_MNEM_SUFFIX;
3215 break;
3216 }
3217 else if (i.types[op].bitfield.reg64)
3218 {
3219 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3220 break;
252b5132 3221 }
29b0f896
AM		 3222 }
3223 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3224 guess_suffix = WORD_MNEM_SUFFIX;
3225
3226 for (op = i.operands; --op >= 0;)
40fb9820 3227 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3228 {
3229 switch (i.op[op].imms->X_op)
252b5132 3230 {
29b0f896
AM		 3231 case O_constant:
3232 /* If a suffix is given, this operand may be shortened. */
3233 switch (guess_suffix)
252b5132 3234 {
29b0f896 3235 case LONG_MNEM_SUFFIX:
40fb9820
L		 3236 i.types[op].bitfield.imm32 = 1;
3237 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3238 break;
3239 case WORD_MNEM_SUFFIX:
40fb9820
L		 3240 i.types[op].bitfield.imm16 = 1;
3241 i.types[op].bitfield.imm32 = 1;
3242 i.types[op].bitfield.imm32s = 1;
3243 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3244 break;
3245 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3246 i.types[op].bitfield.imm8 = 1;
3247 i.types[op].bitfield.imm8s = 1;
3248 i.types[op].bitfield.imm16 = 1;
3249 i.types[op].bitfield.imm32 = 1;
3250 i.types[op].bitfield.imm32s = 1;
3251 i.types[op].bitfield.imm64 = 1;
29b0f896 3252 break;
252b5132 3253 }
252b5132 3254
29b0f896
AM		 3255 /* If this operand is at most 16 bits, convert it
3256 to a signed 16 bit number before trying to see
3257 whether it will fit in an even smaller size.
3258 This allows a 16-bit operand such as $0xffe0 to
3259 be recognised as within Imm8S range. */
40fb9820 3260 if ((i.types[op].bitfield.imm16)
29b0f896 3261 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3262 {
29b0f896
AM		 3263 i.op[op].imms->X_add_number =
3264 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3265 }
40fb9820 3266 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3267 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3268 == 0))
3269 {
3270 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3271 ^ ((offsetT) 1 << 31))
3272 - ((offsetT) 1 << 31));
3273 }
40fb9820 3274 i.types[op]
c6fb90c8
L		 3275 = operand_type_or (i.types[op],
3276 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3277
29b0f896
AM		 3278 /* We must avoid matching of Imm32 templates when 64bit
3279 only immediate is available. */
3280 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3281 i.types[op].bitfield.imm32 = 0;
29b0f896 3282 break;
252b5132 3283
29b0f896
AM		 3284 case O_absent:
3285 case O_register:
3286 abort ();
3287
3288 /* Symbols and expressions. */
3289 default:
9cd96992
JB		 3290 /* Convert symbolic operand to proper sizes for matching, but don't
3291 prevent matching a set of insns that only supports sizes other
3292 than those matching the insn suffix. */
3293 {
40fb9820 3294 i386_operand_type mask, allowed;
9cd96992
JB		 3295 const template *t;
3296
0dfbf9d7
L		 3297 operand_type_set (&mask, 0);
3298 operand_type_set (&allowed, 0);
40fb9820 3299
4eed87de
AM		 3300 for (t = current_templates->start;
3301 t < current_templates->end;
3302 ++t)
c6fb90c8
L		 3303 allowed = operand_type_or (allowed,
3304 t->operand_types[op]);
9cd96992
JB		 3305 switch (guess_suffix)
3306 {
3307 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3308 mask.bitfield.imm64 = 1;
3309 mask.bitfield.imm32s = 1;
9cd96992
JB		 3310 break;
3311 case LONG_MNEM_SUFFIX:
40fb9820 3312 mask.bitfield.imm32 = 1;
9cd96992
JB		 3313 break;
3314 case WORD_MNEM_SUFFIX:
40fb9820 3315 mask.bitfield.imm16 = 1;
9cd96992
JB		 3316 break;
3317 case BYTE_MNEM_SUFFIX:
40fb9820 3318 mask.bitfield.imm8 = 1;
9cd96992
JB		 3319 break;
3320 default:
9cd96992
JB		 3321 break;
3322 }
c6fb90c8 3323 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3324 if (!operand_type_all_zero (&allowed))
c6fb90c8 3325 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3326 }
29b0f896 3327 break;
252b5132 3328 }
29b0f896
AM		 3329 }
3330}
47926f60 3331
29b0f896
AM		 3332/* Try to use the smallest displacement type too. */
3333static void
e3bb37b5 3334optimize_disp (void)
29b0f896
AM		 3335{
3336 int op;
3e73aa7c 3337
29b0f896 3338 for (op = i.operands; --op >= 0;)
40fb9820 3339 if (operand_type_check (i.types[op], disp))
252b5132 3340 {
b300c311 3341 if (i.op[op].disps->X_op == O_constant)
252b5132 3342 {
b300c311 3343 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3344
40fb9820 3345 if (i.types[op].bitfield.disp16
b300c311
L		 3346 && (disp & ~(offsetT) 0xffff) == 0)
3347 {
3348 /* If this operand is at most 16 bits, convert
3349 to a signed 16 bit number and don't use 64bit
3350 displacement. */
3351 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3352 i.types[op].bitfield.disp64 = 0;
b300c311 3353 }
40fb9820 3354 if (i.types[op].bitfield.disp32
b300c311
L		 3355 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3356 {
3357 /* If this operand is at most 32 bits, convert
3358 to a signed 32 bit number and don't use 64bit
3359 displacement. */
3360 disp &= (((offsetT) 2 << 31) - 1);
3361 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3362 i.types[op].bitfield.disp64 = 0;
b300c311 3363 }
40fb9820 3364 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3365 {
40fb9820
L		 3366 i.types[op].bitfield.disp8 = 0;
3367 i.types[op].bitfield.disp16 = 0;
3368 i.types[op].bitfield.disp32 = 0;
3369 i.types[op].bitfield.disp32s = 0;
3370 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3371 i.op[op].disps = 0;
3372 i.disp_operands--;
3373 }
3374 else if (flag_code == CODE_64BIT)
3375 {
3376 if (fits_in_signed_long (disp))
28a9d8f5 3377 {
40fb9820
L		 3378 i.types[op].bitfield.disp64 = 0;
3379 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3380 }
b300c311 3381 if (fits_in_unsigned_long (disp))
40fb9820 3382 i.types[op].bitfield.disp32 = 1;
b300c311 3383 }
40fb9820
L		 3384 if ((i.types[op].bitfield.disp32
3385 || i.types[op].bitfield.disp32s
3386 || i.types[op].bitfield.disp16)
b300c311 3387 && fits_in_signed_byte (disp))
40fb9820 3388 i.types[op].bitfield.disp8 = 1;
252b5132 3389 }
67a4f2b7
AO		 3390 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3391 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3392 {
3393 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3394 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3395 i.types[op].bitfield.disp8 = 0;
3396 i.types[op].bitfield.disp16 = 0;
3397 i.types[op].bitfield.disp32 = 0;
3398 i.types[op].bitfield.disp32s = 0;
3399 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3400 }
3401 else
b300c311 3402 /* We only support 64bit displacement on constants. */
40fb9820 3403 i.types[op].bitfield.disp64 = 0;
252b5132 3404 }
29b0f896
AM		 3405}
3406
c0f3af97
L		 3407/* Check if operands are valid for the instrucrtion. Update VEX
3408 operand types. */
3409
3410static int
3411VEX_check_operands (const template *t)
3412{
3413 if (!t->opcode_modifier.vex)
3414 return 0;
3415
3416 /* Only check VEX_Imm4, which must be the first operand. */
3417 if (t->operand_types[0].bitfield.vex_imm4)
3418 {
3419 if (i.op[0].imms->X_op != O_constant
3420 || !fits_in_imm4 (i.op[0].imms->X_add_number))
3421 return 1;
3422
3423 /* Turn off Imm8 so that update_imm won't complain. */
3424 i.types[0] = vex_imm4;
3425 }
3426
3427 return 0;
3428}
3429
29b0f896 3430static int
e3bb37b5 3431match_template (void)
29b0f896
AM		 3432{
3433 /* Points to template once we've found it. */
3434 const template *t;
40fb9820 3435 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3436 i386_operand_type overlap4;
29b0f896 3437 unsigned int found_reverse_match;
40fb9820
L		 3438 i386_opcode_modifier suffix_check;
3439 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3440 int addr_prefix_disp;
a5c311ca 3441 unsigned int j;
3629bb00 3442 unsigned int found_cpu_match;
45664ddb 3443 unsigned int check_register;
29b0f896 3444
c0f3af97
L		 3445#if MAX_OPERANDS != 5
3446# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3447#endif
3448
29b0f896 3449 found_reverse_match = 0;
539e75ad 3450 addr_prefix_disp = -1;
40fb9820
L		 3451
3452 memset (&suffix_check, 0, sizeof (suffix_check));
3453 if (i.suffix == BYTE_MNEM_SUFFIX)
3454 suffix_check.no_bsuf = 1;
3455 else if (i.suffix == WORD_MNEM_SUFFIX)
3456 suffix_check.no_wsuf = 1;
3457 else if (i.suffix == SHORT_MNEM_SUFFIX)
3458 suffix_check.no_ssuf = 1;
3459 else if (i.suffix == LONG_MNEM_SUFFIX)
3460 suffix_check.no_lsuf = 1;
3461 else if (i.suffix == QWORD_MNEM_SUFFIX)
3462 suffix_check.no_qsuf = 1;
3463 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3464 suffix_check.no_ldsuf = 1;
29b0f896 3465
45aa61fe 3466 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3467 {
539e75ad
L		 3468 addr_prefix_disp = -1;
3469
29b0f896
AM		 3470 /* Must have right number of operands. */
3471 if (i.operands != t->operands)
3472 continue;
3473
50aecf8c 3474 /* Check processor support. */
c0f3af97
L		 3475 found_cpu_match = (cpu_flags_match (t)
3476 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3477 if (!found_cpu_match)
3478 continue;
3479
e1d4d893
L		 3480 /* Check old gcc support. */
3481 if (!old_gcc && t->opcode_modifier.oldgcc)
3482 continue;
3483
3484 /* Check AT&T mnemonic. */
3485 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3486 continue;
3487
5c07affc
L		 3488 /* Check AT&T syntax Intel syntax. */
3489 if ((intel_syntax && t->opcode_modifier.attsyntax)
3490 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3491 continue;
3492
20592a94 3493 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3494 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3495 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3496 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3497 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3498 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3499 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3500 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3501 continue;
3502
5c07affc 3503 if (!operand_size_match (t))
7d5e4556 3504 continue;
539e75ad 3505
5c07affc
L		 3506 for (j = 0; j < MAX_OPERANDS; j++)
3507 operand_types[j] = t->operand_types[j];
3508
45aa61fe
AM		 3509 /* In general, don't allow 64-bit operands in 32-bit mode. */
3510 if (i.suffix == QWORD_MNEM_SUFFIX
3511 && flag_code != CODE_64BIT
3512 && (intel_syntax
40fb9820 3513 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3514 && !intel_float_operand (t->name))
3515 : intel_float_operand (t->name) != 2)
40fb9820 3516 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3517 && !operand_types[0].bitfield.regxmm
3518 && !operand_types[0].bitfield.regymm)
40fb9820 3519 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3520 && !!operand_types[t->operands > 1].bitfield.regxmm
3521 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3522 && (t->base_opcode != 0x0fc7
3523 || t->extension_opcode != 1 /* cmpxchg8b */))
3524 continue;
3525
192dc9c6
JB		 3526 /* In general, don't allow 32-bit operands on pre-386. */
3527 else if (i.suffix == LONG_MNEM_SUFFIX
3528 && !cpu_arch_flags.bitfield.cpui386
3529 && (intel_syntax
3530 ? (!t->opcode_modifier.ignoresize
3531 && !intel_float_operand (t->name))
3532 : intel_float_operand (t->name) != 2)
3533 && ((!operand_types[0].bitfield.regmmx
3534 && !operand_types[0].bitfield.regxmm)
3535 || (!operand_types[t->operands > 1].bitfield.regmmx
3536 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3537 continue;
3538
29b0f896 3539 /* Do not verify operands when there are none. */
50aecf8c 3540 else
29b0f896 3541 {
c6fb90c8 3542 if (!t->operands)
2dbab7d5
L		 3543 /* We've found a match; break out of loop. */
3544 break;
29b0f896 3545 }
252b5132 3546
539e75ad
L		 3547 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3548 into Disp32/Disp16/Disp32 operand. */
3549 if (i.prefix[ADDR_PREFIX] != 0)
3550 {
40fb9820 3551 /* There should be only one Disp operand. */
539e75ad
L		 3552 switch (flag_code)
3553 {
3554 case CODE_16BIT:
40fb9820
L		 3555 for (j = 0; j < MAX_OPERANDS; j++)
3556 {
3557 if (operand_types[j].bitfield.disp16)
3558 {
3559 addr_prefix_disp = j;
3560 operand_types[j].bitfield.disp32 = 1;
3561 operand_types[j].bitfield.disp16 = 0;
3562 break;
3563 }
3564 }
539e75ad
L		 3565 break;
3566 case CODE_32BIT:
40fb9820
L		 3567 for (j = 0; j < MAX_OPERANDS; j++)
3568 {
3569 if (operand_types[j].bitfield.disp32)
3570 {
3571 addr_prefix_disp = j;
3572 operand_types[j].bitfield.disp32 = 0;
3573 operand_types[j].bitfield.disp16 = 1;
3574 break;
3575 }
3576 }
539e75ad
L		 3577 break;
3578 case CODE_64BIT:
40fb9820
L		 3579 for (j = 0; j < MAX_OPERANDS; j++)
3580 {
3581 if (operand_types[j].bitfield.disp64)
3582 {
3583 addr_prefix_disp = j;
3584 operand_types[j].bitfield.disp64 = 0;
3585 operand_types[j].bitfield.disp32 = 1;
3586 break;
3587 }
3588 }
539e75ad
L		 3589 break;
3590 }
539e75ad
L		 3591 }
3592
45664ddb
L		 3593 /* We check register size only if size of operands can be
3594 encoded the canonical way. */
3595 check_register = t->opcode_modifier.w;
c6fb90c8 3596 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3597 switch (t->operands)
3598 {
3599 case 1:
40fb9820 3600 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3601 continue;
3602 break;
3603 case 2:
8b38ad71
L		 3604 /* xchg %eax, %eax is a special case. It is an aliase for nop
3605 only in 32bit mode and we can use opcode 0x90. In 64bit
3606 mode, we can't use 0x90 for xchg %eax, %eax since it should
3607 zero-extend %eax to %rax. */
3608 if (flag_code == CODE_64BIT
3609 && t->base_opcode == 0x90
0dfbf9d7
L		 3610 && operand_type_equal (&i.types [0], &acc32)
3611 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3612 continue;
29b0f896 3613 case 3:
f48ff2ae 3614 case 4:
c0f3af97 3615 case 5:
c6fb90c8 3616 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3617 if (!operand_type_match (overlap0, i.types[0])
3618 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3619 || (check_register
3620 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3621 operand_types[0],
3622 overlap1, i.types[1],
3623 operand_types[1])))
29b0f896
AM		 3624 {
3625 /* Check if other direction is valid ... */
40fb9820 3626 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3627 continue;
3628
3629 /* Try reversing direction of operands. */
c6fb90c8
L		 3630 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3631 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3632 if (!operand_type_match (overlap0, i.types[0])
3633 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3634 || (check_register
3635 && !operand_type_register_match (overlap0,
3636 i.types[0],
3637 operand_types[1],
3638 overlap1,
3639 i.types[1],
3640 operand_types[0])))
29b0f896
AM		 3641 {
3642 /* Does not match either direction. */
3643 continue;
3644 }
3645 /* found_reverse_match holds which of D or FloatDR
3646 we've found. */
40fb9820 3647 if (t->opcode_modifier.d)
8a2ed489 3648 found_reverse_match = Opcode_D;
40fb9820 3649 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3650 found_reverse_match = Opcode_FloatD;
3651 else
3652 found_reverse_match = 0;
40fb9820 3653 if (t->opcode_modifier.floatr)
8a2ed489 3654 found_reverse_match |= Opcode_FloatR;
29b0f896 3655 }
f48ff2ae 3656 else
29b0f896 3657 {
f48ff2ae 3658 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3659 switch (t->operands)
3660 {
c0f3af97
L		 3661 case 5:
3662 overlap4 = operand_type_and (i.types[4],
3663 operand_types[4]);
d1cbb4db 3664 case 4:
c6fb90c8
L		 3665 overlap3 = operand_type_and (i.types[3],
3666 operand_types[3]);
d1cbb4db 3667 case 3:
c6fb90c8
L		 3668 overlap2 = operand_type_and (i.types[2],
3669 operand_types[2]);
d1cbb4db
L		 3670 break;
3671 }
29b0f896 3672
f48ff2ae
L		 3673 switch (t->operands)
3674 {
c0f3af97
L		 3675 case 5:
3676 if (!operand_type_match (overlap4, i.types[4])
3677 || !operand_type_register_match (overlap3,
3678 i.types[3],
3679 operand_types[3],
3680 overlap4,
3681 i.types[4],
3682 operand_types[4]))
3683 continue;
f48ff2ae 3684 case 4:
40fb9820 3685 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3686 || (check_register
3687 && !operand_type_register_match (overlap2,
3688 i.types[2],
3689 operand_types[2],
3690 overlap3,
3691 i.types[3],
3692 operand_types[3])))
f48ff2ae
L		 3693 continue;
3694 case 3:
3695 /* Here we make use of the fact that there are no
3696 reverse match 3 operand instructions, and all 3
3697 operand instructions only need to be checked for
3698 register consistency between operands 2 and 3. */
40fb9820 3699 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3700 || (check_register
3701 && !operand_type_register_match (overlap1,
3702 i.types[1],
3703 operand_types[1],
3704 overlap2,
3705 i.types[2],
3706 operand_types[2])))
f48ff2ae
L		 3707 continue;
3708 break;
3709 }
29b0f896 3710 }
f48ff2ae 3711 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3712 slip through to break. */
3713 }
3629bb00 3714 if (!found_cpu_match)
29b0f896
AM		 3715 {
3716 found_reverse_match = 0;
3717 continue;
3718 }
c0f3af97
L		 3719
3720 /* Check if VEX operands are valid. */
3721 if (VEX_check_operands (t))
3722 continue;
3723
29b0f896
AM		 3724 /* We've found a match; break out of loop. */
3725 break;
3726 }
3727
3728 if (t == current_templates->end)
3729 {
3730 /* We found no match. */
3731 as_bad (_("suffix or operands invalid for `%s'"),
3732 current_templates->start->name);
3733 return 0;
3734 }
252b5132 3735
29b0f896
AM		 3736 if (!quiet_warnings)
3737 {
3738 if (!intel_syntax
40fb9820
L		 3739 && (i.types[0].bitfield.jumpabsolute
3740 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3741 {
3742 as_warn (_("indirect %s without `*'"), t->name);
3743 }
3744
40fb9820
L		 3745 if (t->opcode_modifier.isprefix
3746 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3747 {
3748 /* Warn them that a data or address size prefix doesn't
3749 affect assembly of the next line of code. */
3750 as_warn (_("stand-alone `%s' prefix"), t->name);
3751 }
3752 }
3753
3754 /* Copy the template we found. */
3755 i.tm = *t;
539e75ad
L		 3756
3757 if (addr_prefix_disp != -1)
3758 i.tm.operand_types[addr_prefix_disp]
3759 = operand_types[addr_prefix_disp];
3760
29b0f896
AM		 3761 if (found_reverse_match)
3762 {
3763 /* If we found a reverse match we must alter the opcode
3764 direction bit. found_reverse_match holds bits to change
3765 (different for int & float insns). */
3766
3767 i.tm.base_opcode ^= found_reverse_match;
3768
539e75ad
L		 3769 i.tm.operand_types[0] = operand_types[1];
3770 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3771 }
3772
3773 return 1;
3774}
3775
3776static int
e3bb37b5 3777check_string (void)
29b0f896 3778{
40fb9820
L		 3779 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3780 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3781 {
3782 if (i.seg[0] != NULL && i.seg[0] != &es)
3783 {
3784 as_bad (_("`%s' operand %d must use `%%es' segment"),
3785 i.tm.name,
3786 mem_op + 1);
3787 return 0;
3788 }
3789 /* There's only ever one segment override allowed per instruction.
3790 This instruction possibly has a legal segment override on the
3791 second operand, so copy the segment to where non-string
3792 instructions store it, allowing common code. */
3793 i.seg[0] = i.seg[1];
3794 }
40fb9820 3795 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3796 {
3797 if (i.seg[1] != NULL && i.seg[1] != &es)
3798 {
3799 as_bad (_("`%s' operand %d must use `%%es' segment"),
3800 i.tm.name,
3801 mem_op + 2);
3802 return 0;
3803 }
3804 }
3805 return 1;
3806}
3807
3808static int
543613e9 3809process_suffix (void)
29b0f896
AM		 3810{
3811 /* If matched instruction specifies an explicit instruction mnemonic
3812 suffix, use it. */
40fb9820
L		 3813 if (i.tm.opcode_modifier.size16)
3814 i.suffix = WORD_MNEM_SUFFIX;
3815 else if (i.tm.opcode_modifier.size32)
3816 i.suffix = LONG_MNEM_SUFFIX;
3817 else if (i.tm.opcode_modifier.size64)
3818 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3819 else if (i.reg_operands)
3820 {
3821 /* If there's no instruction mnemonic suffix we try to invent one
3822 based on register operands. */
3823 if (!i.suffix)
3824 {
3825 /* We take i.suffix from the last register operand specified,
3826 Destination register type is more significant than source
381d071f
L		 3827 register type. crc32 in SSE4.2 prefers source register
3828 type. */
3829 if (i.tm.base_opcode == 0xf20f38f1)
3830 {
40fb9820
L		 3831 if (i.types[0].bitfield.reg16)
3832 i.suffix = WORD_MNEM_SUFFIX;
3833 else if (i.types[0].bitfield.reg32)
3834 i.suffix = LONG_MNEM_SUFFIX;
3835 else if (i.types[0].bitfield.reg64)
3836 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3837 }
9344ff29 3838 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3839 {
40fb9820 3840 if (i.types[0].bitfield.reg8)
20592a94
L		 3841 i.suffix = BYTE_MNEM_SUFFIX;
3842 }
381d071f
L		 3843
3844 if (!i.suffix)
3845 {
3846 int op;
3847
20592a94
L		 3848 if (i.tm.base_opcode == 0xf20f38f1
3849 || i.tm.base_opcode == 0xf20f38f0)
3850 {
3851 /* We have to know the operand size for crc32. */
3852 as_bad (_("ambiguous memory operand size for `%s`"),
3853 i.tm.name);
3854 return 0;
3855 }
3856
381d071f 3857 for (op = i.operands; --op >= 0;)
40fb9820 3858 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3859 {
40fb9820
L		 3860 if (i.types[op].bitfield.reg8)
3861 {
3862 i.suffix = BYTE_MNEM_SUFFIX;
3863 break;
3864 }
3865 else if (i.types[op].bitfield.reg16)
3866 {
3867 i.suffix = WORD_MNEM_SUFFIX;
3868 break;
3869 }
3870 else if (i.types[op].bitfield.reg32)
3871 {
3872 i.suffix = LONG_MNEM_SUFFIX;
3873 break;
3874 }
3875 else if (i.types[op].bitfield.reg64)
3876 {
3877 i.suffix = QWORD_MNEM_SUFFIX;
3878 break;
3879 }
381d071f
L		 3880 }
3881 }
29b0f896
AM		 3882 }
3883 else if (i.suffix == BYTE_MNEM_SUFFIX)
3884 {
3885 if (!check_byte_reg ())
3886 return 0;
3887 }
3888 else if (i.suffix == LONG_MNEM_SUFFIX)
3889 {
3890 if (!check_long_reg ())
3891 return 0;
3892 }
3893 else if (i.suffix == QWORD_MNEM_SUFFIX)
3894 {
955e1e6a
L		 3895 if (intel_syntax
3896 && i.tm.opcode_modifier.ignoresize
3897 && i.tm.opcode_modifier.no_qsuf)
3898 i.suffix = 0;
3899 else if (!check_qword_reg ())
29b0f896
AM		 3900 return 0;
3901 }
3902 else if (i.suffix == WORD_MNEM_SUFFIX)
3903 {
3904 if (!check_word_reg ())
3905 return 0;
3906 }
c0f3af97
L		 3907 else if (i.suffix == XMMWORD_MNEM_SUFFIX
3908 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 3909 {
c0f3af97 3910 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 3911 should check if it is a valid suffix. */
3912 }
40fb9820 3913 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3914 /* Do nothing if the instruction is going to ignore the prefix. */
3915 ;
3916 else
3917 abort ();
3918 }
40fb9820 3919 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3920 && !i.suffix
3921 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3922 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3923 {
3924 i.suffix = stackop_size;
3925 }
9306ca4a
JB		 3926 else if (intel_syntax
3927 && !i.suffix
40fb9820
L		 3928 && (i.tm.operand_types[0].bitfield.jumpabsolute
3929 || i.tm.opcode_modifier.jumpbyte
3930 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3931 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3932 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3933 {
3934 switch (flag_code)
3935 {
3936 case CODE_64BIT:
40fb9820 3937 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3938 {
3939 i.suffix = QWORD_MNEM_SUFFIX;
3940 break;
3941 }
3942 case CODE_32BIT:
40fb9820 3943 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3944 i.suffix = LONG_MNEM_SUFFIX;
3945 break;
3946 case CODE_16BIT:
40fb9820 3947 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3948 i.suffix = WORD_MNEM_SUFFIX;
3949 break;
3950 }
3951 }
252b5132 3952
9306ca4a 3953 if (!i.suffix)
29b0f896 3954 {
9306ca4a
JB		 3955 if (!intel_syntax)
3956 {
40fb9820 3957 if (i.tm.opcode_modifier.w)
9306ca4a 3958 {
4eed87de
AM		 3959 as_bad (_("no instruction mnemonic suffix given and "
3960 "no register operands; can't size instruction"));
9306ca4a
JB		 3961 return 0;
3962 }
3963 }
3964 else
3965 {
40fb9820
L		 3966 unsigned int suffixes;
3967
3968 suffixes = !i.tm.opcode_modifier.no_bsuf;
3969 if (!i.tm.opcode_modifier.no_wsuf)
3970 suffixes |= 1 << 1;
3971 if (!i.tm.opcode_modifier.no_lsuf)
3972 suffixes |= 1 << 2;
fc4adea1 3973 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 3974 suffixes |= 1 << 3;
3975 if (!i.tm.opcode_modifier.no_ssuf)
3976 suffixes |= 1 << 4;
3977 if (!i.tm.opcode_modifier.no_qsuf)
3978 suffixes |= 1 << 5;
3979
3980 /* There are more than suffix matches. */
3981 if (i.tm.opcode_modifier.w
9306ca4a 3982 || ((suffixes & (suffixes - 1))
40fb9820
L		 3983 && !i.tm.opcode_modifier.defaultsize
3984 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3985 {
3986 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3987 return 0;
3988 }
3989 }
29b0f896 3990 }
252b5132 3991
9306ca4a
JB		 3992 /* Change the opcode based on the operand size given by i.suffix;
3993 We don't need to change things for byte insns. */
3994
582d5edd
L		 3995 if (i.suffix
3996 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 3997 && i.suffix != XMMWORD_MNEM_SUFFIX
3998 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 3999 {
4000 /* It's not a byte, select word/dword operation. */
40fb9820 4001 if (i.tm.opcode_modifier.w)
29b0f896 4002 {
40fb9820 4003 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4004 i.tm.base_opcode |= 8;
4005 else
4006 i.tm.base_opcode |= 1;
4007 }
0f3f3d8b 4008
29b0f896
AM		 4009 /* Now select between word & dword operations via the operand
4010 size prefix, except for instructions that will ignore this
4011 prefix anyway. */
ca61edf2 4012 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4013 {
ca61edf2
L		 4014 /* The address size override prefix changes the size of the
4015 first operand. */
40fb9820
L		 4016 if ((flag_code == CODE_32BIT
4017 && i.op->regs[0].reg_type.bitfield.reg16)
4018 || (flag_code != CODE_32BIT
4019 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4020 if (!add_prefix (ADDR_PREFIX_OPCODE))
4021 return 0;
4022 }
4023 else if (i.suffix != QWORD_MNEM_SUFFIX
4024 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4025 && !i.tm.opcode_modifier.ignoresize
4026 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4027 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4028 || (flag_code == CODE_64BIT
40fb9820 4029 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4030 {
4031 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4032
40fb9820 4033 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4034 prefix = ADDR_PREFIX_OPCODE;
252b5132 4035
29b0f896
AM		 4036 if (!add_prefix (prefix))
4037 return 0;
24eab124 4038 }
252b5132 4039
29b0f896
AM		 4040 /* Set mode64 for an operand. */
4041 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4042 && flag_code == CODE_64BIT
40fb9820 4043 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4044 {
4045 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4046 need rex64. cmpxchg8b is also a special case. */
4047 if (! (i.operands == 2
4048 && i.tm.base_opcode == 0x90
4049 && i.tm.extension_opcode == None
0dfbf9d7
L		 4050 && operand_type_equal (&i.types [0], &acc64)
4051 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4052 && ! (i.operands == 1
4053 && i.tm.base_opcode == 0xfc7
4054 && i.tm.extension_opcode == 1
40fb9820
L		 4055 && !operand_type_check (i.types [0], reg)
4056 && operand_type_check (i.types [0], anymem)))
f6bee062 4057 i.rex |= REX_W;
46e883c5 4058 }
3e73aa7c 4059
29b0f896
AM		 4060 /* Size floating point instruction. */
4061 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4062 if (i.tm.opcode_modifier.floatmf)
543613e9 4063 i.tm.base_opcode ^= 4;
29b0f896 4064 }
7ecd2f8b 4065
29b0f896
AM		 4066 return 1;
4067}
3e73aa7c 4068
29b0f896 4069static int
543613e9 4070check_byte_reg (void)
29b0f896
AM		 4071{
4072 int op;
543613e9 4073
29b0f896
AM		 4074 for (op = i.operands; --op >= 0;)
4075 {
4076 /* If this is an eight bit register, it's OK. If it's the 16 or
4077 32 bit version of an eight bit register, we will just use the
4078 low portion, and that's OK too. */
40fb9820 4079 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4080 continue;
4081
ca61edf2
L		 4082 /* Don't generate this warning if not needed. */
4083 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4084 continue;
4085
9344ff29
L		 4086 /* crc32 doesn't generate this warning. */
4087 if (i.tm.base_opcode == 0xf20f38f0)
4088 continue;
4089
40fb9820
L		 4090 if ((i.types[op].bitfield.reg16
4091 || i.types[op].bitfield.reg32
4092 || i.types[op].bitfield.reg64)
4093 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4094 {
4095 /* Prohibit these changes in the 64bit mode, since the
4096 lowering is more complicated. */
4097 if (flag_code == CODE_64BIT
40fb9820 4098 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4099 {
2ca3ace5
L		 4100 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4101 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4102 i.suffix);
4103 return 0;
4104 }
4105#if REGISTER_WARNINGS
4106 if (!quiet_warnings
40fb9820 4107 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4108 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4109 register_prefix,
40fb9820 4110 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4111 ? REGNAM_AL - REGNAM_AX
4112 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4113 register_prefix,
29b0f896
AM		 4114 i.op[op].regs->reg_name,
4115 i.suffix);
4116#endif
4117 continue;
4118 }
4119 /* Any other register is bad. */
40fb9820
L		 4120 if (i.types[op].bitfield.reg16
4121 || i.types[op].bitfield.reg32
4122 || i.types[op].bitfield.reg64
4123 || i.types[op].bitfield.regmmx
4124 || i.types[op].bitfield.regxmm
c0f3af97 4125 || i.types[op].bitfield.regymm
40fb9820
L		 4126 || i.types[op].bitfield.sreg2
4127 || i.types[op].bitfield.sreg3
4128 || i.types[op].bitfield.control
4129 || i.types[op].bitfield.debug
4130 || i.types[op].bitfield.test
4131 || i.types[op].bitfield.floatreg
4132 || i.types[op].bitfield.floatacc)
29b0f896 4133 {
a540244d
L		 4134 as_bad (_("`%s%s' not allowed with `%s%c'"),
4135 register_prefix,
29b0f896
AM		 4136 i.op[op].regs->reg_name,
4137 i.tm.name,
4138 i.suffix);
4139 return 0;
4140 }
4141 }
4142 return 1;
4143}
4144
4145static int
e3bb37b5 4146check_long_reg (void)
29b0f896
AM		 4147{
4148 int op;
4149
4150 for (op = i.operands; --op >= 0;)
4151 /* Reject eight bit registers, except where the template requires
4152 them. (eg. movzb) */
40fb9820
L		 4153 if (i.types[op].bitfield.reg8
4154 && (i.tm.operand_types[op].bitfield.reg16
4155 || i.tm.operand_types[op].bitfield.reg32
4156 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4157 {
a540244d
L		 4158 as_bad (_("`%s%s' not allowed with `%s%c'"),
4159 register_prefix,
29b0f896
AM		 4160 i.op[op].regs->reg_name,
4161 i.tm.name,
4162 i.suffix);
4163 return 0;
4164 }
4165 /* Warn if the e prefix on a general reg is missing. */
4166 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4167 && i.types[op].bitfield.reg16
4168 && (i.tm.operand_types[op].bitfield.reg32
4169 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4170 {
4171 /* Prohibit these changes in the 64bit mode, since the
4172 lowering is more complicated. */
4173 if (flag_code == CODE_64BIT)
252b5132 4174 {
2ca3ace5
L		 4175 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4176 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4177 i.suffix);
4178 return 0;
252b5132 4179 }
29b0f896
AM		 4180#if REGISTER_WARNINGS
4181 else
a540244d
L		 4182 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4183 register_prefix,
29b0f896 4184 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4185 register_prefix,
29b0f896
AM		 4186 i.op[op].regs->reg_name,
4187 i.suffix);
4188#endif
252b5132 4189 }
29b0f896 4190 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4191 else if (i.types[op].bitfield.reg64
4192 && (i.tm.operand_types[op].bitfield.reg32
4193 || i.tm.operand_types[op].bitfield.acc))
252b5132 4194 {
34828aad 4195 if (intel_syntax
ca61edf2 4196 && i.tm.opcode_modifier.toqword
40fb9820 4197 && !i.types[0].bitfield.regxmm)
34828aad 4198 {
ca61edf2 4199 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4200 i.suffix = QWORD_MNEM_SUFFIX;
4201 }
4202 else
4203 {
4204 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4205 register_prefix, i.op[op].regs->reg_name,
4206 i.suffix);
4207 return 0;
4208 }
29b0f896
AM		 4209 }
4210 return 1;
4211}
252b5132 4212
29b0f896 4213static int
e3bb37b5 4214check_qword_reg (void)
29b0f896
AM		 4215{
4216 int op;
252b5132 4217
29b0f896
AM		 4218 for (op = i.operands; --op >= 0; )
4219 /* Reject eight bit registers, except where the template requires
4220 them. (eg. movzb) */
40fb9820
L		 4221 if (i.types[op].bitfield.reg8
4222 && (i.tm.operand_types[op].bitfield.reg16
4223 || i.tm.operand_types[op].bitfield.reg32
4224 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4225 {
a540244d
L		 4226 as_bad (_("`%s%s' not allowed with `%s%c'"),
4227 register_prefix,
29b0f896
AM		 4228 i.op[op].regs->reg_name,
4229 i.tm.name,
4230 i.suffix);
4231 return 0;
4232 }
4233 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4234 else if ((i.types[op].bitfield.reg16
4235 || i.types[op].bitfield.reg32)
4236 && (i.tm.operand_types[op].bitfield.reg32
4237 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4238 {
4239 /* Prohibit these changes in the 64bit mode, since the
4240 lowering is more complicated. */
34828aad 4241 if (intel_syntax
ca61edf2 4242 && i.tm.opcode_modifier.todword
40fb9820 4243 && !i.types[0].bitfield.regxmm)
34828aad 4244 {
ca61edf2 4245 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4246 i.suffix = LONG_MNEM_SUFFIX;
4247 }
4248 else
4249 {
4250 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4251 register_prefix, i.op[op].regs->reg_name,
4252 i.suffix);
4253 return 0;
4254 }
252b5132 4255 }
29b0f896
AM		 4256 return 1;
4257}
252b5132 4258
29b0f896 4259static int
e3bb37b5 4260check_word_reg (void)
29b0f896
AM		 4261{
4262 int op;
4263 for (op = i.operands; --op >= 0;)
4264 /* Reject eight bit registers, except where the template requires
4265 them. (eg. movzb) */
40fb9820
L		 4266 if (i.types[op].bitfield.reg8
4267 && (i.tm.operand_types[op].bitfield.reg16
4268 || i.tm.operand_types[op].bitfield.reg32
4269 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4270 {
a540244d
L		 4271 as_bad (_("`%s%s' not allowed with `%s%c'"),
4272 register_prefix,
29b0f896
AM		 4273 i.op[op].regs->reg_name,
4274 i.tm.name,
4275 i.suffix);
4276 return 0;
4277 }
4278 /* Warn if the e prefix on a general reg is present. */
4279 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4280 && i.types[op].bitfield.reg32
4281 && (i.tm.operand_types[op].bitfield.reg16
4282 || i.tm.operand_types[op].bitfield.acc))
252b5132 4283 {
29b0f896
AM		 4284 /* Prohibit these changes in the 64bit mode, since the
4285 lowering is more complicated. */
4286 if (flag_code == CODE_64BIT)
252b5132 4287 {
2ca3ace5
L		 4288 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4289 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4290 i.suffix);
4291 return 0;
252b5132 4292 }
29b0f896
AM		 4293 else
4294#if REGISTER_WARNINGS
a540244d
L		 4295 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4296 register_prefix,
29b0f896 4297 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4298 register_prefix,
29b0f896
AM		 4299 i.op[op].regs->reg_name,
4300 i.suffix);
4301#endif
4302 }
4303 return 1;
4304}
252b5132 4305
29b0f896 4306static int
40fb9820 4307update_imm (unsigned int j)
29b0f896 4308{
40fb9820
L		 4309 i386_operand_type overlap;
4310
c6fb90c8 4311 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 4312 if ((overlap.bitfield.imm8
4313 || overlap.bitfield.imm8s
4314 || overlap.bitfield.imm16
4315 || overlap.bitfield.imm32
4316 || overlap.bitfield.imm32s
4317 || overlap.bitfield.imm64)
0dfbf9d7
L		 4318 && !operand_type_equal (&overlap, &imm8)
4319 && !operand_type_equal (&overlap, &imm8s)
4320 && !operand_type_equal (&overlap, &imm16)
4321 && !operand_type_equal (&overlap, &imm32)
4322 && !operand_type_equal (&overlap, &imm32s)
4323 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4324 {
4325 if (i.suffix)
4326 {
40fb9820
L		 4327 i386_operand_type temp;
4328
0dfbf9d7 4329 operand_type_set (&temp, 0);
40fb9820
L		 4330 if (i.suffix == BYTE_MNEM_SUFFIX)
4331 {
4332 temp.bitfield.imm8 = overlap.bitfield.imm8;
4333 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4334 }
4335 else if (i.suffix == WORD_MNEM_SUFFIX)
4336 temp.bitfield.imm16 = overlap.bitfield.imm16;
4337 else if (i.suffix == QWORD_MNEM_SUFFIX)
4338 {
4339 temp.bitfield.imm64 = overlap.bitfield.imm64;
4340 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4341 }
4342 else
4343 temp.bitfield.imm32 = overlap.bitfield.imm32;
4344 overlap = temp;
29b0f896 4345 }
0dfbf9d7
L		 4346 else if (operand_type_equal (&overlap, &imm16_32_32s)
4347 || operand_type_equal (&overlap, &imm16_32)
4348 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4349 {
40fb9820 4350 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4351 overlap = imm16;
40fb9820 4352 else
65da13b5 4353 overlap = imm32s;
29b0f896 4354 }
0dfbf9d7
L		 4355 if (!operand_type_equal (&overlap, &imm8)
4356 && !operand_type_equal (&overlap, &imm8s)
4357 && !operand_type_equal (&overlap, &imm16)
4358 && !operand_type_equal (&overlap, &imm32)
4359 && !operand_type_equal (&overlap, &imm32s)
4360 && !operand_type_equal (&overlap, &imm64))
29b0f896 4361 {
4eed87de
AM		 4362 as_bad (_("no instruction mnemonic suffix given; "
4363 "can't determine immediate size"));
29b0f896
AM		 4364 return 0;
4365 }
4366 }
40fb9820 4367 i.types[j] = overlap;
29b0f896 4368
40fb9820
L		 4369 return 1;
4370}
4371
4372static int
4373finalize_imm (void)
4374{
4375 unsigned int j;
29b0f896 4376
40fb9820
L		 4377 for (j = 0; j < 2; j++)
4378 if (update_imm (j) == 0)
4379 return 0;
4380
c6fb90c8 4381 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 4382 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 4383
4384 return 1;
4385}
4386
85f10a01
MM		 4387static void
4388process_drex (void)
4389{
5dd15031
JJ		 4390 i.drex.modrm_reg = 0;
4391 i.drex.modrm_regmem = 0;
85f10a01
MM		 4392
4393 /* SSE5 4 operand instructions must have the destination the same as
4394 one of the inputs. Figure out the destination register and cache
4395 it away in the drex field, and remember which fields to use for
4396 the modrm byte. */
4397 if (i.tm.opcode_modifier.drex
4398 && i.tm.opcode_modifier.drexv
4399 && i.operands == 4)
4400 {
4401 i.tm.extension_opcode = None;
4402
4403 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4404 if (i.types[0].bitfield.regxmm != 0
4405 && i.types[1].bitfield.regxmm != 0
4406 && i.types[2].bitfield.regxmm != 0
4407 && i.types[3].bitfield.regxmm != 0
4408 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4409 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4410 {
4411 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4412 operand_type_set (&i.types[0], 0);
4413 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4414 i.reg_operands -= 2;
4415
4416 /* There are two different ways to encode a 4 operand
4417 instruction with all registers that uses OC1 set to
4418 0 or 1. Favor setting OC1 to 0 since this mimics the
4419 actions of other SSE5 assemblers. Use modrm encoding 2
4420 for register/register. Include the high order bit that
4421 is normally stored in the REX byte in the register
4422 field. */
4423 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4424 i.drex.modrm_reg = 2;
4425 i.drex.modrm_regmem = 1;
4426 i.drex.reg = (i.op[3].regs->reg_num
4427 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4428 }
4429
4430 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4431 else if (i.types[0].bitfield.regxmm != 0
4432 && i.types[1].bitfield.regxmm != 0
4433 && (i.types[2].bitfield.regxmm
4434 || operand_type_check (i.types[2], anymem))
4435 && i.types[3].bitfield.regxmm != 0
4436 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4437 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4438 {
4439 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4440 operand_type_set (&i.types[0], 0);
4441 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4442 i.reg_operands -= 2;
4443
4444 /* Specify the modrm encoding for memory addressing. Include
4445 the high order bit that is normally stored in the REX byte
4446 in the register field. */
4447 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4448 i.drex.modrm_reg = 1;
4449 i.drex.modrm_regmem = 2;
4450 i.drex.reg = (i.op[3].regs->reg_num
4451 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4452 }
4453
4454 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4455 else if (i.types[0].bitfield.regxmm != 0
4456 && operand_type_check (i.types[1], anymem) != 0
4457 && i.types[2].bitfield.regxmm != 0
4458 && i.types[3].bitfield.regxmm != 0
4459 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4460 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4461 {
4462 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4463 operand_type_set (&i.types[0], 0);
4464 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4465 i.reg_operands -= 2;
4466
4467 /* Specify the modrm encoding for memory addressing. Include
4468 the high order bit that is normally stored in the REX byte
4469 in the register field. */
4470 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4471 i.drex.modrm_reg = 2;
4472 i.drex.modrm_regmem = 1;
4473 i.drex.reg = (i.op[3].regs->reg_num
4474 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4475 }
4476
4477 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4478 else if (i.types[0].bitfield.regxmm != 0
4479 && i.types[1].bitfield.regxmm != 0
4480 && i.types[2].bitfield.regxmm != 0
4481 && i.types[3].bitfield.regxmm != 0
4482 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4483 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4484 {
4485 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4486 operand_type_set (&i.types[2], 0);
4487 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4488 i.reg_operands -= 2;
4489
4490 /* There are two different ways to encode a 4 operand
4491 instruction with all registers that uses OC1 set to
4492 0 or 1. Favor setting OC1 to 0 since this mimics the
4493 actions of other SSE5 assemblers. Use modrm encoding
4494 2 for register/register. Include the high order bit that
4495 is normally stored in the REX byte in the register
4496 field. */
4497 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4498 i.drex.modrm_reg = 1;
4499 i.drex.modrm_regmem = 0;
4500
4501 /* Remember the register, including the upper bits */
4502 i.drex.reg = (i.op[3].regs->reg_num
4503 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4504 }
4505
4506 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4507 else if (i.types[0].bitfield.regxmm != 0
4508 && (i.types[1].bitfield.regxmm
4509 || operand_type_check (i.types[1], anymem))
4510 && i.types[2].bitfield.regxmm != 0
4511 && i.types[3].bitfield.regxmm != 0
4512 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4513 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4514 {
4515 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4516 operand_type_set (&i.types[2], 0);
4517 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4518 i.reg_operands -= 2;
4519
4520 /* Specify the modrm encoding and remember the register
4521 including the bits normally stored in the REX byte. */
4522 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4523 i.drex.modrm_reg = 0;
4524 i.drex.modrm_regmem = 1;
4525 i.drex.reg = (i.op[3].regs->reg_num
4526 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4527 }
4528
4529 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4530 else if (operand_type_check (i.types[0], anymem) != 0
4531 && i.types[1].bitfield.regxmm != 0
4532 && i.types[2].bitfield.regxmm != 0
4533 && i.types[3].bitfield.regxmm != 0
4534 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4535 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4536 {
4537 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4538 operand_type_set (&i.types[2], 0);
4539 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4540 i.reg_operands -= 2;
4541
4542 /* Specify the modrm encoding and remember the register
4543 including the bits normally stored in the REX byte. */
4544 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4545 i.drex.modrm_reg = 1;
4546 i.drex.modrm_regmem = 0;
4547 i.drex.reg = (i.op[3].regs->reg_num
4548 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4549 }
4550
4551 else
4552 as_bad (_("Incorrect operands for the '%s' instruction"),
4553 i.tm.name);
4554 }
4555
4556 /* SSE5 instructions with the DREX byte where the only memory operand
4557 is in the 2nd argument, and the first and last xmm register must
4558 match, and is encoded in the DREX byte. */
4559 else if (i.tm.opcode_modifier.drex
4560 && !i.tm.opcode_modifier.drexv
4561 && i.operands == 4)
4562 {
4563 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4564 if (i.types[0].bitfield.regxmm != 0
4565 && (i.types[1].bitfield.regxmm
4566 || operand_type_check(i.types[1], anymem))
4567 && i.types[2].bitfield.regxmm != 0
4568 && i.types[3].bitfield.regxmm != 0
4569 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4570 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4571 {
4572 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4573 operand_type_set (&i.types[0], 0);
4574 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4575 i.reg_operands -= 2;
4576
4577 /* Specify the modrm encoding and remember the register
4578 including the high bit normally stored in the REX
4579 byte. */
4580 i.drex.modrm_reg = 2;
4581 i.drex.modrm_regmem = 1;
4582 i.drex.reg = (i.op[3].regs->reg_num
4583 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4584 }
4585
4586 else
4587 as_bad (_("Incorrect operands for the '%s' instruction"),
4588 i.tm.name);
4589 }
4590
4591 /* SSE5 3 operand instructions that the result is a register, being
4592 either operand can be a memory operand, using OC0 to note which
4593 one is the memory. */
4594 else if (i.tm.opcode_modifier.drex
4595 && i.tm.opcode_modifier.drexv
4596 && i.operands == 3)
4597 {
4598 i.tm.extension_opcode = None;
4599
4600 /* Case 1: 3 operand insn, src1 = register. */
4601 if (i.types[0].bitfield.regxmm != 0
4602 && i.types[1].bitfield.regxmm != 0
4603 && i.types[2].bitfield.regxmm != 0)
4604 {
4605 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4606 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4607 i.reg_operands--;
4608
4609 /* Specify the modrm encoding and remember the register
4610 including the high bit normally stored in the REX byte. */
4611 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4612 i.drex.modrm_reg = 1;
4613 i.drex.modrm_regmem = 0;
4614 i.drex.reg = (i.op[2].regs->reg_num
4615 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4616 }
4617
4618 /* Case 2: 3 operand insn, src1 = memory. */
4619 else if (operand_type_check (i.types[0], anymem) != 0
4620 && i.types[1].bitfield.regxmm != 0
4621 && i.types[2].bitfield.regxmm != 0)
4622 {
4623 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4624 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4625 i.reg_operands--;
4626
4627 /* Specify the modrm encoding and remember the register
4628 including the high bit normally stored in the REX
4629 byte. */
4630 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4631 i.drex.modrm_reg = 1;
4632 i.drex.modrm_regmem = 0;
4633 i.drex.reg = (i.op[2].regs->reg_num
4634 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4635 }
4636
4637 /* Case 3: 3 operand insn, src2 = memory. */
4638 else if (i.types[0].bitfield.regxmm != 0
4639 && operand_type_check (i.types[1], anymem) != 0
4640 && i.types[2].bitfield.regxmm != 0)
4641 {
4642 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4643 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4644 i.reg_operands--;
4645
4646 /* Specify the modrm encoding and remember the register
4647 including the high bit normally stored in the REX byte. */
4648 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4649 i.drex.modrm_reg = 0;
4650 i.drex.modrm_regmem = 1;
4651 i.drex.reg = (i.op[2].regs->reg_num
4652 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4653 }
4654
4655 else
4656 as_bad (_("Incorrect operands for the '%s' instruction"),
4657 i.tm.name);
4658 }
4659
4660 /* SSE5 4 operand instructions that are the comparison instructions
4661 where the first operand is the immediate value of the comparison
4662 to be done. */
4663 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4664 {
4665 /* Case 1: 4 operand insn, src1 = reg/memory. */
4666 if (operand_type_check (i.types[0], imm) != 0
4667 && (i.types[1].bitfield.regxmm
4668 || operand_type_check (i.types[1], anymem))
4669 && i.types[2].bitfield.regxmm != 0
4670 && i.types[3].bitfield.regxmm != 0)
4671 {
4672 /* clear the arguments that are stored in drex */
0dfbf9d7 4673 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4674 i.reg_operands--;
4675
4676 /* Specify the modrm encoding and remember the register
4677 including the high bit normally stored in the REX byte. */
4678 i.drex.modrm_reg = 2;
4679 i.drex.modrm_regmem = 1;
4680 i.drex.reg = (i.op[3].regs->reg_num
4681 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4682 }
4683
4684 /* Case 2: 3 operand insn with ImmExt that places the
4685 opcode_extension as an immediate argument. This is used for
4686 all of the varients of comparison that supplies the appropriate
4687 value as part of the instruction. */
4688 else if ((i.types[0].bitfield.regxmm
4689 || operand_type_check (i.types[0], anymem))
4690 && i.types[1].bitfield.regxmm != 0
4691 && i.types[2].bitfield.regxmm != 0
4692 && operand_type_check (i.types[3], imm) != 0)
4693 {
4694 /* clear the arguments that are stored in drex */
0dfbf9d7 4695 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4696 i.reg_operands--;
4697
4698 /* Specify the modrm encoding and remember the register
4699 including the high bit normally stored in the REX byte. */
4700 i.drex.modrm_reg = 1;
4701 i.drex.modrm_regmem = 0;
4702 i.drex.reg = (i.op[2].regs->reg_num
4703 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4704 }
4705
4706 else
4707 as_bad (_("Incorrect operands for the '%s' instruction"),
4708 i.tm.name);
4709 }
4710
4711 else if (i.tm.opcode_modifier.drex
4712 || i.tm.opcode_modifier.drexv
4713 || i.tm.opcode_modifier.drexc)
4714 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4715}
4716
c0f3af97
L		 4717static int
4718bad_implicit_operand (int xmm)
4719{
4720 const char *reg = xmm ? "xmm0" : "ymm0";
4721 if (intel_syntax)
4722 as_bad (_("the last operand of `%s' must be `%s%s'"),
4723 i.tm.name, register_prefix, reg);
4724 else
4725 as_bad (_("the first operand of `%s' must be `%s%s'"),
4726 i.tm.name, register_prefix, reg);
4727 return 0;
4728}
4729
29b0f896 4730static int
e3bb37b5 4731process_operands (void)
29b0f896
AM		 4732{
4733 /* Default segment register this instruction will use for memory
4734 accesses. 0 means unknown. This is only for optimizing out
4735 unnecessary segment overrides. */
4736 const seg_entry *default_seg = 0;
4737
85f10a01
MM		 4738 /* Handle all of the DREX munging that SSE5 needs. */
4739 if (i.tm.opcode_modifier.drex
4740 || i.tm.opcode_modifier.drexv
4741 || i.tm.opcode_modifier.drexc)
4742 process_drex ();
4743
c0f3af97
L		 4744 if (i.tm.opcode_modifier.sse2avx
4745 && (i.tm.opcode_modifier.vexnds
4746 || i.tm.opcode_modifier.vexndd))
29b0f896 4747 {
c0f3af97
L		 4748 unsigned int dup = i.operands;
4749 unsigned int dest = dup - 1;
9fcfb3d7
L		 4750 unsigned int j;
4751
c0f3af97 4752 /* The destination must be an xmm register. */
0dfbf9d7 4753 assert (i.reg_operands
c0f3af97
L		 4754 && MAX_OPERANDS > dup
4755 && operand_type_equal (&i.types[dest], &regxmm));
4756
4757 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4758 {
c0f3af97
L		 4759 /* The first operand is implicit and must be xmm0. */
4760 assert (operand_type_equal (&i.types[0], &regxmm));
4761 if (i.op[0].regs->reg_num != 0)
4762 return bad_implicit_operand (1);
4763
4764 if (i.tm.opcode_modifier.vex3sources)
4765 {
4766 /* Keep xmm0 for instructions with VEX prefix and 3
4767 sources. */
4768 goto duplicate;
4769 }
e2ec9d29 4770 else
c0f3af97
L		 4771 {
4772 /* We remove the first xmm0 and keep the number of
4773 operands unchanged, which in fact duplicates the
4774 destination. */
4775 for (j = 1; j < i.operands; j++)
4776 {
4777 i.op[j - 1] = i.op[j];
4778 i.types[j - 1] = i.types[j];
4779 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4780 }
4781 }
4782 }
4783 else if (i.tm.opcode_modifier.implicit1stxmm0)
4784 {
4785 assert ((MAX_OPERANDS - 1) > dup
4786 && i.tm.opcode_modifier.vex3sources);
4787
4788 /* Add the implicit xmm0 for instructions with VEX prefix
4789 and 3 sources. */
4790 for (j = i.operands; j > 0; j--)
4791 {
4792 i.op[j] = i.op[j - 1];
4793 i.types[j] = i.types[j - 1];
4794 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4795 }
4796 i.op[0].regs
4797 = (const reg_entry *) hash_find (reg_hash, "xmm0");
4798 i.types[0] = regxmm;
4799 i.tm.operand_types[0] = regxmm;
4800
4801 i.operands += 2;
4802 i.reg_operands += 2;
4803 i.tm.operands += 2;
4804
4805 dup++;
4806 dest++;
4807 i.op[dup] = i.op[dest];
4808 i.types[dup] = i.types[dest];
4809 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4810 }
c0f3af97
L		 4811 else
4812 {
4813duplicate:
4814 i.operands++;
4815 i.reg_operands++;
4816 i.tm.operands++;
4817
4818 i.op[dup] = i.op[dest];
4819 i.types[dup] = i.types[dest];
4820 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4821 }
4822
4823 if (i.tm.opcode_modifier.immext)
4824 process_immext ();
4825 }
4826 else if (i.tm.opcode_modifier.firstxmm0)
4827 {
4828 unsigned int j;
4829
4830 /* The first operand is implicit and must be xmm0/ymm0. */
4831 assert (i.reg_operands
4832 && (operand_type_equal (&i.types[0], &regxmm)
4833 || operand_type_equal (&i.types[0], &regymm)));
4834 if (i.op[0].regs->reg_num != 0)
4835 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4836
4837 for (j = 1; j < i.operands; j++)
4838 {
4839 i.op[j - 1] = i.op[j];
4840 i.types[j - 1] = i.types[j];
4841
4842 /* We need to adjust fields in i.tm since they are used by
4843 build_modrm_byte. */
4844 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4845 }
4846
e2ec9d29
L		 4847 i.operands--;
4848 i.reg_operands--;
e2ec9d29
L		 4849 i.tm.operands--;
4850 }
4851 else if (i.tm.opcode_modifier.regkludge)
4852 {
4853 /* The imul $imm, %reg instruction is converted into
4854 imul $imm, %reg, %reg, and the clr %reg instruction
4855 is converted into xor %reg, %reg. */
4856
4857 unsigned int first_reg_op;
4858
4859 if (operand_type_check (i.types[0], reg))
4860 first_reg_op = 0;
4861 else
4862 first_reg_op = 1;
4863 /* Pretend we saw the extra register operand. */
4864 assert (i.reg_operands == 1
4865 && i.op[first_reg_op + 1].regs == 0);
4866 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4867 i.types[first_reg_op + 1] = i.types[first_reg_op];
4868 i.operands++;
4869 i.reg_operands++;
29b0f896
AM		 4870 }
4871
40fb9820 4872 if (i.tm.opcode_modifier.shortform)
29b0f896 4873 {
40fb9820
L		 4874 if (i.types[0].bitfield.sreg2
4875 || i.types[0].bitfield.sreg3)
29b0f896 4876 {
4eed87de
AM		 4877 if (i.tm.base_opcode == POP_SEG_SHORT
4878 && i.op[0].regs->reg_num == 1)
29b0f896 4879 {
4eed87de
AM		 4880 as_bad (_("you can't `pop %%cs'"));
4881 return 0;
29b0f896 4882 }
4eed87de
AM		 4883 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4884 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4885 i.rex |= REX_B;
4eed87de
AM		 4886 }
4887 else
4888 {
85f10a01
MM		 4889 /* The register or float register operand is in operand
4890 0 or 1. */
40fb9820
L		 4891 unsigned int op;
4892
4893 if (i.types[0].bitfield.floatreg
4894 || operand_type_check (i.types[0], reg))
4895 op = 0;
4896 else
4897 op = 1;
4eed87de
AM		 4898 /* Register goes in low 3 bits of opcode. */
4899 i.tm.base_opcode |= i.op[op].regs->reg_num;
4900 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4901 i.rex |= REX_B;
40fb9820 4902 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4903 {
4eed87de
AM		 4904 /* Warn about some common errors, but press on regardless.
4905 The first case can be generated by gcc (<= 2.8.1). */
4906 if (i.operands == 2)
4907 {
4908 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4909 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4910 register_prefix, i.op[1].regs->reg_name,
4911 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4912 }
4913 else
4914 {
4915 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4916 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4917 register_prefix, i.op[0].regs->reg_name);
4eed87de 4918 }
29b0f896
AM		 4919 }
4920 }
4921 }
40fb9820 4922 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4923 {
4924 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4925 must be put into the modrm byte). Now, we make the modrm and
4926 index base bytes based on all the info we've collected. */
29b0f896
AM		 4927
4928 default_seg = build_modrm_byte ();
4929 }
8a2ed489 4930 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4931 {
4932 default_seg = &ds;
4933 }
40fb9820 4934 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4935 {
4936 /* For the string instructions that allow a segment override
4937 on one of their operands, the default segment is ds. */
4938 default_seg = &ds;
4939 }
4940
75178d9d
L		 4941 if (i.tm.base_opcode == 0x8d /* lea */
4942 && i.seg[0]
4943 && !quiet_warnings)
30123838 4944 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4945
4946 /* If a segment was explicitly specified, and the specified segment
4947 is not the default, use an opcode prefix to select it. If we
4948 never figured out what the default segment is, then default_seg
4949 will be zero at this point, and the specified segment prefix will
4950 always be used. */
29b0f896
AM		 4951 if ((i.seg[0]) && (i.seg[0] != default_seg))
4952 {
4953 if (!add_prefix (i.seg[0]->seg_prefix))
4954 return 0;
4955 }
4956 return 1;
4957}
4958
4959static const seg_entry *
e3bb37b5 4960build_modrm_byte (void)
29b0f896
AM		 4961{
4962 const seg_entry *default_seg = 0;
c0f3af97
L		 4963 unsigned int source, dest;
4964 int vex_3_sources;
4965
4966 /* The first operand of instructions with VEX prefix and 3 sources
4967 must be VEX_Imm4. */
4968 vex_3_sources = i.tm.opcode_modifier.vex3sources;
4969 if (vex_3_sources)
4970 {
4971 unsigned int nds, reg;
4972
4973 if (i.tm.opcode_modifier.veximmext
4974 && i.tm.opcode_modifier.immext)
4975 {
4976 dest = i.operands - 2;
4977 assert (dest == 3);
4978 }
4979 else
4980 dest = i.operands - 1;
4981 nds = dest - 1;
4982
4983 /* There are 2 kinds of instructions:
4984 1. 5 operands: one immediate operand and 4 register
4985 operands or 3 register operands plus 1 memory operand.
4986 It must have VexNDS and VexW0 or VexW1. The destination
4987 must be either XMM or YMM register.
4988 2. 4 operands: 4 register operands or 3 register operands
4989 plus 1 memory operand. It must have VexNDS and VexImmExt. */
4990 if (!((i.reg_operands == 4
4991 || (i.reg_operands == 3 && i.mem_operands == 1))
4992 && i.tm.opcode_modifier.vexnds
4993 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
4994 || operand_type_equal (&i.tm.operand_types[dest], &regymm))
4995 && (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
4996 || operand_type_equal (&i.tm.operand_types[nds], &regymm))
4997 && ((dest == 4
4998 && i.imm_operands == 1
4999 && i.types[0].bitfield.vex_imm4
5000 && (i.tm.opcode_modifier.vexw0
5001 || i.tm.opcode_modifier.vexw1))
5002 || (dest == 3
5003 && (i.imm_operands == 0
5004 || (i.imm_operands == 1
5005 && i.tm.opcode_modifier.immext))
5006 && i.tm.opcode_modifier.veximmext))))
5007 abort ();
5008
5009 i.vex.register_specifier = i.op[nds].regs;
5010
5011 if (i.imm_operands == 0)
5012 {
5013 /* When there is no immediate operand, generate an 8bit
5014 immediate operand to encode the first operand. */
5015 expressionS *exp = &im_expressions[i.imm_operands++];
5016 i.op[i.operands].imms = exp;
5017 i.types[i.operands] = imm8;
5018 i.operands++;
5019 /* If VexW1 is set, the first operand is the source and
5020 the second operand is encoded in the immediate operand. */
5021 if (i.tm.opcode_modifier.vexw1)
5022 {
5023 source = 0;
5024 reg = 1;
5025 }
5026 else
5027 {
5028 source = 1;
5029 reg = 0;
5030 }
5031 assert (operand_type_equal (&i.tm.operand_types[reg], &regxmm)
5032 || operand_type_equal (&i.tm.operand_types[reg],
5033 &regymm));
5034 exp->X_op = O_constant;
5035 exp->X_add_number
5036 = ((i.op[reg].regs->reg_num
5037 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
5038 }
5039 else
5040 {
5041 unsigned int imm;
5042
5043 if (i.tm.opcode_modifier.vexw0)
5044 {
5045 /* If VexW0 is set, the third operand is the source and
5046 the second operand is encoded in the immediate
5047 operand. */
5048 source = 2;
5049 reg = 1;
5050 }
5051 else
5052 {
5053 /* VexW1 is set, the second operand is the source and
5054 the third operand is encoded in the immediate
5055 operand. */
5056 source = 1;
5057 reg = 2;
5058 }
5059
5060 if (i.tm.opcode_modifier.immext)
5061 {
5062 /* When ImmExt is set, the immdiate byte is the last
5063 operand. */
5064 imm = i.operands - 1;
5065 source--;
5066 reg--;
5067 }
5068 else
5069 {
5070 imm = 0;
5071
5072 /* Turn on Imm8 so that output_imm will generate it. */
5073 i.types[imm].bitfield.imm8 = 1;
5074 }
5075
5076 assert (operand_type_equal (&i.tm.operand_types[reg], &regxmm)
5077 || operand_type_equal (&i.tm.operand_types[reg],
5078 &regymm));
5079 i.op[imm].imms->X_add_number
5080 |= ((i.op[reg].regs->reg_num
5081 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
5082 }
5083 }
5084 else
5085 source = dest = 0;
29b0f896 5086
85f10a01
MM		 5087 /* SSE5 4 operand instructions are encoded in such a way that one of
5088 the inputs must match the destination register. Process_drex hides
5089 the 3rd argument in the drex field, so that by the time we get
5090 here, it looks to GAS as if this is a 2 operand instruction. */
5091 if ((i.tm.opcode_modifier.drex
5092 || i.tm.opcode_modifier.drexv
b5016f89 5093 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5094 && i.reg_operands == 2)
5095 {
5096 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
5097 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
5098
5099 i.rm.reg = reg->reg_num;
5100 i.rm.regmem = regmem->reg_num;
5101 i.rm.mode = 3;
5102 if ((reg->reg_flags & RegRex) != 0)
5103 i.rex |= REX_R;
5104 if ((regmem->reg_flags & RegRex) != 0)
5105 i.rex |= REX_B;
5106 }
5107
29b0f896 5108 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5109 implicit registers do not count. If there are 3 register
5110 operands, it must be a instruction with VexNDS. For a
5111 instruction with VexNDD, the destination register is encoded
5112 in VEX prefix. If there are 4 register operands, it must be
5113 a instruction with VEX prefix and 3 sources. */
5114 else if (i.mem_operands == 0
5115 && ((i.reg_operands == 2
5116 && !i.tm.opcode_modifier.vexndd)
5117 || (i.reg_operands == 3
5118 && i.tm.opcode_modifier.vexnds)
5119 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5120 {
cab737b9
L		 5121 switch (i.operands)
5122 {
5123 case 2:
5124 source = 0;
5125 break;
5126 case 3:
c81128dc
L		 5127 /* When there are 3 operands, one of them may be immediate,
5128 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5129 the first operand must be shift count register (cl) or it
5130 is an instruction with VexNDS. */
c81128dc
L		 5131 assert (i.imm_operands == 1
5132 || (i.imm_operands == 0
c0f3af97
L		 5133 && (i.tm.opcode_modifier.vexnds
5134 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5135 if (operand_type_check (i.types[0], imm)
5136 || i.types[0].bitfield.shiftcount)
5137 source = 1;
5138 else
5139 source = 0;
cab737b9
L		 5140 break;
5141 case 4:
368d64cc
L		 5142 /* When there are 4 operands, the first two must be 8bit
5143 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5144 one.
5145
5146 For instructions with VexNDS, if the first operand
5147 an imm8, the source operand is the 2nd one. If the last
5148 operand is imm8, the source operand is the first one. */
5149 assert ((i.imm_operands == 2
5150 && i.types[0].bitfield.imm8
5151 && i.types[1].bitfield.imm8)
5152 || (i.tm.opcode_modifier.vexnds
5153 && i.imm_operands == 1
5154 && (i.types[0].bitfield.imm8
5155 || i.types[i.operands - 1].bitfield.imm8)));
5156 if (i.tm.opcode_modifier.vexnds)
5157 {
5158 if (i.types[0].bitfield.imm8)
5159 source = 1;
5160 else
5161 source = 0;
5162 }
5163 else
5164 source = 2;
5165 break;
5166 case 5:
cab737b9
L		 5167 break;
5168 default:
5169 abort ();
5170 }
5171
c0f3af97
L		 5172 if (!vex_3_sources)
5173 {
5174 dest = source + 1;
5175
5176 if (i.tm.opcode_modifier.vexnds)
5177 {
5178 /* For instructions with VexNDS, the register-only
5179 source operand must be XMM or YMM register. It is
5180 encoded in VEX prefix. */
5181 if ((dest + 1) >= i.operands
5182 || (!operand_type_equal (&i.tm.operand_types[dest],
5183 &regxmm)
5184 && !operand_type_equal (&i.tm.operand_types[dest],
5185 &regymm)))
5186 abort ();
5187 i.vex.register_specifier = i.op[dest].regs;
5188 dest++;
5189 }
5190 }
29b0f896
AM		 5191
5192 i.rm.mode = 3;
5193 /* One of the register operands will be encoded in the i.tm.reg
5194 field, the other in the combined i.tm.mode and i.tm.regmem
5195 fields. If no form of this instruction supports a memory
5196 destination operand, then we assume the source operand may
5197 sometimes be a memory operand and so we need to store the
5198 destination in the i.rm.reg field. */
40fb9820
L		 5199 if (!i.tm.operand_types[dest].bitfield.regmem
5200 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5201 {
5202 i.rm.reg = i.op[dest].regs->reg_num;
5203 i.rm.regmem = i.op[source].regs->reg_num;
5204 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5205 i.rex |= REX_R;
29b0f896 5206 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5207 i.rex |= REX_B;
29b0f896
AM		 5208 }
5209 else
5210 {
5211 i.rm.reg = i.op[source].regs->reg_num;
5212 i.rm.regmem = i.op[dest].regs->reg_num;
5213 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5214 i.rex |= REX_B;
29b0f896 5215 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5216 i.rex |= REX_R;
29b0f896 5217 }
161a04f6 5218 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5219 {
40fb9820
L		 5220 if (!i.types[0].bitfield.control
5221 && !i.types[1].bitfield.control)
c4a530c5 5222 abort ();
161a04f6 5223 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5224 add_prefix (LOCK_PREFIX_OPCODE);
5225 }
29b0f896
AM		 5226 }
5227 else
5228 { /* If it's not 2 reg operands... */
c0f3af97
L		 5229 unsigned int mem;
5230
29b0f896
AM		 5231 if (i.mem_operands)
5232 {
5233 unsigned int fake_zero_displacement = 0;
99018f42 5234 unsigned int op;
4eed87de 5235
85f10a01
MM		 5236 /* This has been precalculated for SSE5 instructions
5237 that have a DREX field earlier in process_drex. */
b5016f89
L		 5238 if (i.tm.opcode_modifier.drex
5239 || i.tm.opcode_modifier.drexv
5240 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5241 op = i.drex.modrm_regmem;
5242 else
5243 {
c0209578
L		 5244 for (op = 0; op < i.operands; op++)
5245 if (operand_type_check (i.types[op], anymem))
5246 break;
5247 assert (op < i.operands);
85f10a01 5248 }
29b0f896
AM		 5249
5250 default_seg = &ds;
5251
5252 if (i.base_reg == 0)
5253 {
5254 i.rm.mode = 0;
5255 if (!i.disp_operands)
5256 fake_zero_displacement = 1;
5257 if (i.index_reg == 0)
5258 {
5259 /* Operand is just <disp> */
20f0a1fc 5260 if (flag_code == CODE_64BIT)
29b0f896
AM		 5261 {
5262 /* 64bit mode overwrites the 32bit absolute
5263 addressing by RIP relative addressing and
5264 absolute addressing is encoded by one of the
5265 redundant SIB forms. */
5266 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5267 i.sib.base = NO_BASE_REGISTER;
5268 i.sib.index = NO_INDEX_REGISTER;
fc225355 5269 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5270 ? disp32s : disp32);
20f0a1fc 5271 }
fc225355
L		 5272 else if ((flag_code == CODE_16BIT)
5273 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5274 {
5275 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5276 i.types[op] = disp16;
20f0a1fc
NC		 5277 }
5278 else
5279 {
5280 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5281 i.types[op] = disp32;
29b0f896
AM		 5282 }
5283 }
5284 else /* !i.base_reg && i.index_reg */
5285 {
db51cc60
L		 5286 if (i.index_reg->reg_num == RegEiz
5287 || i.index_reg->reg_num == RegRiz)
5288 i.sib.index = NO_INDEX_REGISTER;
5289 else
5290 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5291 i.sib.base = NO_BASE_REGISTER;
5292 i.sib.scale = i.log2_scale_factor;
5293 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5294 i.types[op].bitfield.disp8 = 0;
5295 i.types[op].bitfield.disp16 = 0;
5296 i.types[op].bitfield.disp64 = 0;
29b0f896 5297 if (flag_code != CODE_64BIT)
40fb9820
L		 5298 {
5299 /* Must be 32 bit */
5300 i.types[op].bitfield.disp32 = 1;
5301 i.types[op].bitfield.disp32s = 0;
5302 }
29b0f896 5303 else
40fb9820
L		 5304 {
5305 i.types[op].bitfield.disp32 = 0;
5306 i.types[op].bitfield.disp32s = 1;
5307 }
29b0f896 5308 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5309 i.rex |= REX_X;
29b0f896
AM		 5310 }
5311 }
5312 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5313 else if (i.base_reg->reg_num == RegRip ||
5314 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5315 {
5316 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5317 i.types[op].bitfield.disp8 = 0;
5318 i.types[op].bitfield.disp16 = 0;
5319 i.types[op].bitfield.disp32 = 0;
5320 i.types[op].bitfield.disp32s = 1;
5321 i.types[op].bitfield.disp64 = 0;
71903a11 5322 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5323 if (! i.disp_operands)
5324 fake_zero_displacement = 1;
29b0f896 5325 }
40fb9820 5326 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5327 {
5328 switch (i.base_reg->reg_num)
5329 {
5330 case 3: /* (%bx) */
5331 if (i.index_reg == 0)
5332 i.rm.regmem = 7;
5333 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5334 i.rm.regmem = i.index_reg->reg_num - 6;
5335 break;
5336 case 5: /* (%bp) */
5337 default_seg = &ss;
5338 if (i.index_reg == 0)
5339 {
5340 i.rm.regmem = 6;
40fb9820 5341 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5342 {
5343 /* fake (%bp) into 0(%bp) */
40fb9820 5344 i.types[op].bitfield.disp8 = 1;
252b5132 5345 fake_zero_displacement = 1;
29b0f896
AM		 5346 }
5347 }
5348 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5349 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5350 break;
5351 default: /* (%si) -> 4 or (%di) -> 5 */
5352 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5353 }
5354 i.rm.mode = mode_from_disp_size (i.types[op]);
5355 }
5356 else /* i.base_reg and 32/64 bit mode */
5357 {
5358 if (flag_code == CODE_64BIT
40fb9820
L		 5359 && operand_type_check (i.types[op], disp))
5360 {
5361 i386_operand_type temp;
0dfbf9d7 5362 operand_type_set (&temp, 0);
40fb9820
L		 5363 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5364 i.types[op] = temp;
5365 if (i.prefix[ADDR_PREFIX] == 0)
5366 i.types[op].bitfield.disp32s = 1;
5367 else
5368 i.types[op].bitfield.disp32 = 1;
5369 }
20f0a1fc 5370
29b0f896
AM		 5371 i.rm.regmem = i.base_reg->reg_num;
5372 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5373 i.rex |= REX_B;
29b0f896
AM		 5374 i.sib.base = i.base_reg->reg_num;
5375 /* x86-64 ignores REX prefix bit here to avoid decoder
5376 complications. */
5377 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5378 {
5379 default_seg = &ss;
5380 if (i.disp_operands == 0)
5381 {
5382 fake_zero_displacement = 1;
40fb9820 5383 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5384 }
5385 }
5386 else if (i.base_reg->reg_num == ESP_REG_NUM)
5387 {
5388 default_seg = &ss;
5389 }
5390 i.sib.scale = i.log2_scale_factor;
5391 if (i.index_reg == 0)
5392 {
5393 /* <disp>(%esp) becomes two byte modrm with no index
5394 register. We've already stored the code for esp
5395 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5396 Any base register besides %esp will not use the
5397 extra modrm byte. */
5398 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5399 }
5400 else
5401 {
db51cc60
L		 5402 if (i.index_reg->reg_num == RegEiz
5403 || i.index_reg->reg_num == RegRiz)
5404 i.sib.index = NO_INDEX_REGISTER;
5405 else
5406 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5407 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5408 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5409 i.rex |= REX_X;
29b0f896 5410 }
67a4f2b7
AO		 5411
5412 if (i.disp_operands
5413 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5414 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5415 i.rm.mode = 0;
5416 else
5417 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5418 }
252b5132 5419
29b0f896
AM		 5420 if (fake_zero_displacement)
5421 {
5422 /* Fakes a zero displacement assuming that i.types[op]
5423 holds the correct displacement size. */
5424 expressionS *exp;
5425
5426 assert (i.op[op].disps == 0);
5427 exp = &disp_expressions[i.disp_operands++];
5428 i.op[op].disps = exp;
5429 exp->X_op = O_constant;
5430 exp->X_add_number = 0;
5431 exp->X_add_symbol = (symbolS *) 0;
5432 exp->X_op_symbol = (symbolS *) 0;
5433 }
c0f3af97
L		 5434
5435 mem = op;
29b0f896 5436 }
c0f3af97
L		 5437 else
5438 mem = ~0;
252b5132 5439
29b0f896
AM		 5440 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5441 (if any) based on i.tm.extension_opcode. Again, we must be
5442 careful to make sure that segment/control/debug/test/MMX
5443 registers are coded into the i.rm.reg field. */
5444 if (i.reg_operands)
5445 {
99018f42
L		 5446 unsigned int op;
5447
85f10a01
MM		 5448 /* This has been precalculated for SSE5 instructions
5449 that have a DREX field earlier in process_drex. */
b5016f89
L		 5450 if (i.tm.opcode_modifier.drex
5451 || i.tm.opcode_modifier.drexv
5452 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5453 {
5454 op = i.drex.modrm_reg;
5455 i.rm.reg = i.op[op].regs->reg_num;
5456 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5457 i.rex |= REX_R;
5458 }
5459 else
5460 {
c0f3af97
L		 5461 unsigned int vex_reg = ~0;
5462
c0209578
L		 5463 for (op = 0; op < i.operands; op++)
5464 if (i.types[op].bitfield.reg8
5465 || i.types[op].bitfield.reg16
5466 || i.types[op].bitfield.reg32
5467 || i.types[op].bitfield.reg64
5468 || i.types[op].bitfield.regmmx
5469 || i.types[op].bitfield.regxmm
c0f3af97 5470 || i.types[op].bitfield.regymm
c0209578
L		 5471 || i.types[op].bitfield.sreg2
5472 || i.types[op].bitfield.sreg3
5473 || i.types[op].bitfield.control
5474 || i.types[op].bitfield.debug
5475 || i.types[op].bitfield.test)
5476 break;
5477
c0f3af97
L		 5478 if (vex_3_sources)
5479 op = dest;
5480 else if (i.tm.opcode_modifier.vexnds)
5481 {
5482 /* For instructions with VexNDS, the register-only
5483 source operand is encoded in VEX prefix. */
5484 assert (mem != (unsigned int) ~0);
5485
5486 if (op > mem)
5487 {
5488 vex_reg = op++;
5489 assert (op < i.operands);
5490 }
5491 else
5492 {
5493 vex_reg = op + 1;
5494 assert (vex_reg < i.operands);
5495 }
5496 }
5497 else if (i.tm.opcode_modifier.vexndd)
5498 {
5499 /* For instructions with VexNDD, there should be
5500 no memory operand and the register destination
5501 is encoded in VEX prefix. */
5502 assert (i.mem_operands == 0
5503 && (op + 2) == i.operands);
5504 vex_reg = op + 1;
5505 }
5506 else
5507 assert (op < i.operands);
5508
5509 if (vex_reg != (unsigned int) ~0)
5510 {
5511 assert (i.reg_operands == 2);
5512
5513 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5514 & regxmm)
5515 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5516 &regymm))
5517 abort ();
5518 i.vex.register_specifier = i.op[vex_reg].regs;
5519 }
99018f42 5520
85f10a01
MM		 5521 /* If there is an extension opcode to put here, the
5522 register number must be put into the regmem field. */
c0209578
L		 5523 if (i.tm.extension_opcode != None)
5524 {
5525 i.rm.regmem = i.op[op].regs->reg_num;
5526 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5527 i.rex |= REX_B;
5528 }
5529 else
5530 {
5531 i.rm.reg = i.op[op].regs->reg_num;
5532 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5533 i.rex |= REX_R;
5534 }
85f10a01 5535 }
252b5132 5536
29b0f896
AM		 5537 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5538 must set it to 3 to indicate this is a register operand
5539 in the regmem field. */
5540 if (!i.mem_operands)
5541 i.rm.mode = 3;
5542 }
252b5132 5543
29b0f896 5544 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 5545 if (i.tm.extension_opcode != None
5546 && !(i.tm.opcode_modifier.drex
5547 || i.tm.opcode_modifier.drexv
5548 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 5549 i.rm.reg = i.tm.extension_opcode;
5550 }
5551 return default_seg;
5552}
252b5132 5553
29b0f896 5554static void
e3bb37b5 5555output_branch (void)
29b0f896
AM		 5556{
5557 char *p;
5558 int code16;
5559 int prefix;
5560 relax_substateT subtype;
5561 symbolS *sym;
5562 offsetT off;
5563
5564 code16 = 0;
5565 if (flag_code == CODE_16BIT)
5566 code16 = CODE16;
5567
5568 prefix = 0;
5569 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5570 {
29b0f896
AM		 5571 prefix = 1;
5572 i.prefixes -= 1;
5573 code16 ^= CODE16;
252b5132 5574 }
29b0f896
AM		 5575 /* Pentium4 branch hints. */
5576 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5577 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5578 {
29b0f896
AM		 5579 prefix++;
5580 i.prefixes--;
5581 }
5582 if (i.prefix[REX_PREFIX] != 0)
5583 {
5584 prefix++;
5585 i.prefixes--;
2f66722d
AM		 5586 }
5587
29b0f896
AM		 5588 if (i.prefixes != 0 && !intel_syntax)
5589 as_warn (_("skipping prefixes on this instruction"));
5590
5591 /* It's always a symbol; End frag & setup for relax.
5592 Make sure there is enough room in this frag for the largest
5593 instruction we may generate in md_convert_frag. This is 2
5594 bytes for the opcode and room for the prefix and largest
5595 displacement. */
5596 frag_grow (prefix + 2 + 4);
5597 /* Prefix and 1 opcode byte go in fr_fix. */
5598 p = frag_more (prefix + 1);
5599 if (i.prefix[DATA_PREFIX] != 0)
5600 *p++ = DATA_PREFIX_OPCODE;
5601 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5602 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5603 *p++ = i.prefix[SEG_PREFIX];
5604 if (i.prefix[REX_PREFIX] != 0)
5605 *p++ = i.prefix[REX_PREFIX];
5606 *p = i.tm.base_opcode;
5607
5608 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5609 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5610 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5611 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5612 else
5613 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5614 subtype |= code16;
3e73aa7c 5615
29b0f896
AM		 5616 sym = i.op[0].disps->X_add_symbol;
5617 off = i.op[0].disps->X_add_number;
3e73aa7c 5618
29b0f896
AM		 5619 if (i.op[0].disps->X_op != O_constant
5620 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5621 {
29b0f896
AM		 5622 /* Handle complex expressions. */
5623 sym = make_expr_symbol (i.op[0].disps);
5624 off = 0;
5625 }
3e73aa7c 5626
29b0f896
AM		 5627 /* 1 possible extra opcode + 4 byte displacement go in var part.
5628 Pass reloc in fr_var. */
5629 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5630}
3e73aa7c 5631
29b0f896 5632static void
e3bb37b5 5633output_jump (void)
29b0f896
AM		 5634{
5635 char *p;
5636 int size;
3e02c1cc 5637 fixS *fixP;
29b0f896 5638
40fb9820 5639 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5640 {
5641 /* This is a loop or jecxz type instruction. */
5642 size = 1;
5643 if (i.prefix[ADDR_PREFIX] != 0)
5644 {
5645 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5646 i.prefixes -= 1;
5647 }
5648 /* Pentium4 branch hints. */
5649 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5650 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5651 {
5652 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5653 i.prefixes--;
3e73aa7c
JH		 5654 }
5655 }
29b0f896
AM		 5656 else
5657 {
5658 int code16;
3e73aa7c 5659
29b0f896
AM		 5660 code16 = 0;
5661 if (flag_code == CODE_16BIT)
5662 code16 = CODE16;
3e73aa7c 5663
29b0f896
AM		 5664 if (i.prefix[DATA_PREFIX] != 0)
5665 {
5666 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5667 i.prefixes -= 1;
5668 code16 ^= CODE16;
5669 }
252b5132 5670
29b0f896
AM		 5671 size = 4;
5672 if (code16)
5673 size = 2;
5674 }
9fcc94b6 5675
29b0f896
AM		 5676 if (i.prefix[REX_PREFIX] != 0)
5677 {
5678 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5679 i.prefixes -= 1;
5680 }
252b5132 5681
29b0f896
AM		 5682 if (i.prefixes != 0 && !intel_syntax)
5683 as_warn (_("skipping prefixes on this instruction"));
e0890092 5684
29b0f896
AM		 5685 p = frag_more (1 + size);
5686 *p++ = i.tm.base_opcode;
e0890092 5687
3e02c1cc
AM		 5688 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5689 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5690
5691 /* All jumps handled here are signed, but don't use a signed limit
5692 check for 32 and 16 bit jumps as we want to allow wrap around at
5693 4G and 64k respectively. */
5694 if (size == 1)
5695 fixP->fx_signed = 1;
29b0f896 5696}
e0890092 5697
29b0f896 5698static void
e3bb37b5 5699output_interseg_jump (void)
29b0f896
AM		 5700{
5701 char *p;
5702 int size;
5703 int prefix;
5704 int code16;
252b5132 5705
29b0f896
AM		 5706 code16 = 0;
5707 if (flag_code == CODE_16BIT)
5708 code16 = CODE16;
a217f122 5709
29b0f896
AM		 5710 prefix = 0;
5711 if (i.prefix[DATA_PREFIX] != 0)
5712 {
5713 prefix = 1;
5714 i.prefixes -= 1;
5715 code16 ^= CODE16;
5716 }
5717 if (i.prefix[REX_PREFIX] != 0)
5718 {
5719 prefix++;
5720 i.prefixes -= 1;
5721 }
252b5132 5722
29b0f896
AM		 5723 size = 4;
5724 if (code16)
5725 size = 2;
252b5132 5726
29b0f896
AM		 5727 if (i.prefixes != 0 && !intel_syntax)
5728 as_warn (_("skipping prefixes on this instruction"));
252b5132 5729
29b0f896
AM		 5730 /* 1 opcode; 2 segment; offset */
5731 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5732
29b0f896
AM		 5733 if (i.prefix[DATA_PREFIX] != 0)
5734 *p++ = DATA_PREFIX_OPCODE;
252b5132 5735
29b0f896
AM		 5736 if (i.prefix[REX_PREFIX] != 0)
5737 *p++ = i.prefix[REX_PREFIX];
252b5132 5738
29b0f896
AM		 5739 *p++ = i.tm.base_opcode;
5740 if (i.op[1].imms->X_op == O_constant)
5741 {
5742 offsetT n = i.op[1].imms->X_add_number;
252b5132 5743
29b0f896
AM		 5744 if (size == 2
5745 && !fits_in_unsigned_word (n)
5746 && !fits_in_signed_word (n))
5747 {
5748 as_bad (_("16-bit jump out of range"));
5749 return;
5750 }
5751 md_number_to_chars (p, n, size);
5752 }
5753 else
5754 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5755 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5756 if (i.op[0].imms->X_op != O_constant)
5757 as_bad (_("can't handle non absolute segment in `%s'"),
5758 i.tm.name);
5759 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5760}
a217f122 5761
29b0f896 5762static void
e3bb37b5 5763output_insn (void)
29b0f896 5764{
2bbd9c25
JJ		 5765 fragS *insn_start_frag;
5766 offsetT insn_start_off;
5767
29b0f896
AM		 5768 /* Tie dwarf2 debug info to the address at the start of the insn.
5769 We can't do this after the insn has been output as the current
5770 frag may have been closed off. eg. by frag_var. */
5771 dwarf2_emit_insn (0);
5772
2bbd9c25
JJ		 5773 insn_start_frag = frag_now;
5774 insn_start_off = frag_now_fix ();
5775
29b0f896 5776 /* Output jumps. */
40fb9820 5777 if (i.tm.opcode_modifier.jump)
29b0f896 5778 output_branch ();
40fb9820
L		 5779 else if (i.tm.opcode_modifier.jumpbyte
5780 || i.tm.opcode_modifier.jumpdword)
29b0f896 5781 output_jump ();
40fb9820 5782 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5783 output_interseg_jump ();
5784 else
5785 {
5786 /* Output normal instructions here. */
5787 char *p;
5788 unsigned char *q;
47465058 5789 unsigned int j;
331d2d0d 5790 unsigned int prefix;
4dffcebc 5791
c0f3af97
L		 5792 /* Since the VEX prefix contains the implicit prefix, we don't
5793 need the explicit prefix. */
5794 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5795 {
c0f3af97 5796 switch (i.tm.opcode_length)
bc4bd9ab 5797 {
c0f3af97
L		 5798 case 3:
5799 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5800 {
c0f3af97
L		 5801 prefix = (i.tm.base_opcode >> 24) & 0xff;
5802 goto check_prefix;
5803 }
5804 break;
5805 case 2:
5806 if ((i.tm.base_opcode & 0xff0000) != 0)
5807 {
5808 prefix = (i.tm.base_opcode >> 16) & 0xff;
5809 if (i.tm.cpu_flags.bitfield.cpupadlock)
5810 {
4dffcebc 5811check_prefix:
c0f3af97
L		 5812 if (prefix != REPE_PREFIX_OPCODE
5813 || (i.prefix[LOCKREP_PREFIX]
5814 != REPE_PREFIX_OPCODE))
5815 add_prefix (prefix);
5816 }
5817 else
4dffcebc
L		 5818 add_prefix (prefix);
5819 }
c0f3af97
L		 5820 break;
5821 case 1:
5822 break;
5823 default:
5824 abort ();
bc4bd9ab 5825 }
c0f3af97
L		 5826
5827 /* The prefix bytes. */
5828 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5829 if (*q)
5830 FRAG_APPEND_1_CHAR (*q);
0f10071e 5831 }
252b5132 5832
c0f3af97
L		 5833 if (i.tm.opcode_modifier.vex)
5834 {
5835 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5836 if (*q)
5837 switch (j)
5838 {
5839 case REX_PREFIX:
5840 /* REX byte is encoded in VEX prefix. */
5841 break;
5842 case SEG_PREFIX:
5843 case ADDR_PREFIX:
5844 FRAG_APPEND_1_CHAR (*q);
5845 break;
5846 default:
5847 /* There should be no other prefixes for instructions
5848 with VEX prefix. */
5849 abort ();
5850 }
5851
5852 /* Now the VEX prefix. */
5853 p = frag_more (i.vex.length);
5854 for (j = 0; j < i.vex.length; j++)
5855 p[j] = i.vex.bytes[j];
5856 }
252b5132 5857
29b0f896 5858 /* Now the opcode; be careful about word order here! */
4dffcebc 5859 if (i.tm.opcode_length == 1)
29b0f896
AM		 5860 {
5861 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5862 }
5863 else
5864 {
4dffcebc 5865 switch (i.tm.opcode_length)
331d2d0d 5866 {
4dffcebc 5867 case 3:
331d2d0d
L		 5868 p = frag_more (3);
5869 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5870 break;
5871 case 2:
5872 p = frag_more (2);
5873 break;
5874 default:
5875 abort ();
5876 break;
331d2d0d 5877 }
0f10071e 5878
29b0f896
AM		 5879 /* Put out high byte first: can't use md_number_to_chars! */
5880 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5881 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5882
5883 /* On SSE5, encode the OC1 bit in the DREX field if this
5884 encoding has multiple formats. */
5885 if (i.tm.opcode_modifier.drex
5886 && i.tm.opcode_modifier.drexv
5887 && DREX_OC1 (i.tm.extension_opcode))
5888 *p |= DREX_OC1_MASK;
29b0f896 5889 }
3e73aa7c 5890
29b0f896 5891 /* Now the modrm byte and sib byte (if present). */
40fb9820 5892 if (i.tm.opcode_modifier.modrm)
29b0f896 5893 {
4a3523fa
L		 5894 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5895 | i.rm.reg << 3
5896 | i.rm.mode << 6));
29b0f896
AM		 5897 /* If i.rm.regmem == ESP (4)
5898 && i.rm.mode != (Register mode)
5899 && not 16 bit
5900 ==> need second modrm byte. */
5901 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5902 && i.rm.mode != 3
40fb9820 5903 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5904 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5905 | i.sib.index << 3
5906 | i.sib.scale << 6));
29b0f896 5907 }
3e73aa7c 5908
85f10a01
MM		 5909 /* Write the DREX byte if needed. */
5910 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5911 {
5912 p = frag_more (1);
5913 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5914
5915 /* Encode the OC0 bit if this encoding has multiple
5916 formats. */
5917 if ((i.tm.opcode_modifier.drex
5918 || i.tm.opcode_modifier.drexv)
5919 && DREX_OC0 (i.tm.extension_opcode))
5920 *p |= DREX_OC0_MASK;
5921 }
5922
29b0f896 5923 if (i.disp_operands)
2bbd9c25 5924 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5925
29b0f896 5926 if (i.imm_operands)
2bbd9c25 5927 output_imm (insn_start_frag, insn_start_off);
29b0f896 5928 }
252b5132 5929
29b0f896
AM		 5930#ifdef DEBUG386
5931 if (flag_debug)
5932 {
7b81dfbb 5933 pi ("" /*line*/, &i);
29b0f896
AM		 5934 }
5935#endif /* DEBUG386 */
5936}
252b5132 5937
e205caa7
L		 5938/* Return the size of the displacement operand N. */
5939
5940static int
5941disp_size (unsigned int n)
5942{
5943 int size = 4;
40fb9820
L		 5944 if (i.types[n].bitfield.disp64)
5945 size = 8;
5946 else if (i.types[n].bitfield.disp8)
5947 size = 1;
5948 else if (i.types[n].bitfield.disp16)
5949 size = 2;
e205caa7
L		 5950 return size;
5951}
5952
5953/* Return the size of the immediate operand N. */
5954
5955static int
5956imm_size (unsigned int n)
5957{
5958 int size = 4;
40fb9820
L		 5959 if (i.types[n].bitfield.imm64)
5960 size = 8;
5961 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5962 size = 1;
5963 else if (i.types[n].bitfield.imm16)
5964 size = 2;
e205caa7
L		 5965 return size;
5966}
5967
29b0f896 5968static void
64e74474 5969output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5970{
5971 char *p;
5972 unsigned int n;
252b5132 5973
29b0f896
AM		 5974 for (n = 0; n < i.operands; n++)
5975 {
40fb9820 5976 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5977 {
5978 if (i.op[n].disps->X_op == O_constant)
5979 {
e205caa7 5980 int size = disp_size (n);
29b0f896 5981 offsetT val;
252b5132 5982
29b0f896
AM		 5983 val = offset_in_range (i.op[n].disps->X_add_number,
5984 size);
5985 p = frag_more (size);
5986 md_number_to_chars (p, val, size);
5987 }
5988 else
5989 {
f86103b7 5990 enum bfd_reloc_code_real reloc_type;
e205caa7 5991 int size = disp_size (n);
40fb9820 5992 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5993 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5994
e205caa7 5995 /* We can't have 8 bit displacement here. */
40fb9820 5996 assert (!i.types[n].bitfield.disp8);
e205caa7 5997
29b0f896
AM		 5998 /* The PC relative address is computed relative
5999 to the instruction boundary, so in case immediate
6000 fields follows, we need to adjust the value. */
6001 if (pcrel && i.imm_operands)
6002 {
29b0f896 6003 unsigned int n1;
e205caa7 6004 int sz = 0;
252b5132 6005
29b0f896 6006 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6007 if (operand_type_check (i.types[n1], imm))
252b5132 6008 {
e205caa7
L		 6009 /* Only one immediate is allowed for PC
6010 relative address. */
6011 assert (sz == 0);
6012 sz = imm_size (n1);
6013 i.op[n].disps->X_add_number -= sz;
252b5132 6014 }
29b0f896 6015 /* We should find the immediate. */
e205caa7 6016 assert (sz != 0);
29b0f896 6017 }
520dc8e8 6018
29b0f896 6019 p = frag_more (size);
2bbd9c25 6020 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6021 if (GOT_symbol
2bbd9c25 6022 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6023 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6024 || reloc_type == BFD_RELOC_X86_64_32S
6025 || (reloc_type == BFD_RELOC_64
6026 && object_64bit))
d6ab8113
JB		 6027 && (i.op[n].disps->X_op == O_symbol
6028 || (i.op[n].disps->X_op == O_add
6029 && ((symbol_get_value_expression
6030 (i.op[n].disps->X_op_symbol)->X_op)
6031 == O_subtract))))
6032 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6033 {
6034 offsetT add;
6035
6036 if (insn_start_frag == frag_now)
6037 add = (p - frag_now->fr_literal) - insn_start_off;
6038 else
6039 {
6040 fragS *fr;
6041
6042 add = insn_start_frag->fr_fix - insn_start_off;
6043 for (fr = insn_start_frag->fr_next;
6044 fr && fr != frag_now; fr = fr->fr_next)
6045 add += fr->fr_fix;
6046 add += p - frag_now->fr_literal;
6047 }
6048
4fa24527 6049 if (!object_64bit)
7b81dfbb
AJ		 6050 {
6051 reloc_type = BFD_RELOC_386_GOTPC;
6052 i.op[n].imms->X_add_number += add;
6053 }
6054 else if (reloc_type == BFD_RELOC_64)
6055 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6056 else
7b81dfbb
AJ		 6057 /* Don't do the adjustment for x86-64, as there
6058 the pcrel addressing is relative to the _next_
6059 insn, and that is taken care of in other code. */
d6ab8113 6060 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6061 }
062cd5e7 6062 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6063 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6064 }
6065 }
6066 }
6067}
252b5132 6068
29b0f896 6069static void
64e74474 6070output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6071{
6072 char *p;
6073 unsigned int n;
252b5132 6074
29b0f896
AM		 6075 for (n = 0; n < i.operands; n++)
6076 {
40fb9820 6077 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6078 {
6079 if (i.op[n].imms->X_op == O_constant)
6080 {
e205caa7 6081 int size = imm_size (n);
29b0f896 6082 offsetT val;
b4cac588 6083
29b0f896
AM		 6084 val = offset_in_range (i.op[n].imms->X_add_number,
6085 size);
6086 p = frag_more (size);
6087 md_number_to_chars (p, val, size);
6088 }
6089 else
6090 {
6091 /* Not absolute_section.
6092 Need a 32-bit fixup (don't support 8bit
6093 non-absolute imms). Try to support other
6094 sizes ... */
f86103b7 6095 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6096 int size = imm_size (n);
6097 int sign;
29b0f896 6098
40fb9820 6099 if (i.types[n].bitfield.imm32s
a7d61044 6100 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6101 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6102 sign = 1;
e205caa7
L		 6103 else
6104 sign = 0;
520dc8e8 6105
29b0f896
AM		 6106 p = frag_more (size);
6107 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6108
2bbd9c25
JJ		 6109 /* This is tough to explain. We end up with this one if we
6110 * have operands that look like
6111 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6112 * obtain the absolute address of the GOT, and it is strongly
6113 * preferable from a performance point of view to avoid using
6114 * a runtime relocation for this. The actual sequence of
6115 * instructions often look something like:
6116 *
6117 * call .L66
6118 * .L66:
6119 * popl %ebx
6120 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6121 *
6122 * The call and pop essentially return the absolute address
6123 * of the label .L66 and store it in %ebx. The linker itself
6124 * will ultimately change the first operand of the addl so
6125 * that %ebx points to the GOT, but to keep things simple, the
6126 * .o file must have this operand set so that it generates not
6127 * the absolute address of .L66, but the absolute address of
6128 * itself. This allows the linker itself simply treat a GOTPC
6129 * relocation as asking for a pcrel offset to the GOT to be
6130 * added in, and the addend of the relocation is stored in the
6131 * operand field for the instruction itself.
6132 *
6133 * Our job here is to fix the operand so that it would add
6134 * the correct offset so that %ebx would point to itself. The
6135 * thing that is tricky is that .-.L66 will point to the
6136 * beginning of the instruction, so we need to further modify
6137 * the operand so that it will point to itself. There are
6138 * other cases where you have something like:
6139 *
6140 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6141 *
6142 * and here no correction would be required. Internally in
6143 * the assembler we treat operands of this form as not being
6144 * pcrel since the '.' is explicitly mentioned, and I wonder
6145 * whether it would simplify matters to do it this way. Who
6146 * knows. In earlier versions of the PIC patches, the
6147 * pcrel_adjust field was used to store the correction, but
6148 * since the expression is not pcrel, I felt it would be
6149 * confusing to do it this way. */
6150
d6ab8113 6151 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6152 || reloc_type == BFD_RELOC_X86_64_32S
6153 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6154 && GOT_symbol
6155 && GOT_symbol == i.op[n].imms->X_add_symbol
6156 && (i.op[n].imms->X_op == O_symbol
6157 || (i.op[n].imms->X_op == O_add
6158 && ((symbol_get_value_expression
6159 (i.op[n].imms->X_op_symbol)->X_op)
6160 == O_subtract))))
6161 {
2bbd9c25
JJ		 6162 offsetT add;
6163
6164 if (insn_start_frag == frag_now)
6165 add = (p - frag_now->fr_literal) - insn_start_off;
6166 else
6167 {
6168 fragS *fr;
6169
6170 add = insn_start_frag->fr_fix - insn_start_off;
6171 for (fr = insn_start_frag->fr_next;
6172 fr && fr != frag_now; fr = fr->fr_next)
6173 add += fr->fr_fix;
6174 add += p - frag_now->fr_literal;
6175 }
6176
4fa24527 6177 if (!object_64bit)
d6ab8113 6178 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6179 else if (size == 4)
d6ab8113 6180 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6181 else if (size == 8)
6182 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6183 i.op[n].imms->X_add_number += add;
29b0f896 6184 }
29b0f896
AM		 6185 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6186 i.op[n].imms, 0, reloc_type);
6187 }
6188 }
6189 }
252b5132
RH		 6190}
6191\f
d182319b
JB		 6192/* x86_cons_fix_new is called via the expression parsing code when a
6193 reloc is needed. We use this hook to get the correct .got reloc. */
6194static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6195static int cons_sign = -1;
6196
6197void
e3bb37b5 6198x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6199 expressionS *exp)
d182319b
JB		 6200{
6201 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6202
6203 got_reloc = NO_RELOC;
6204
6205#ifdef TE_PE
6206 if (exp->X_op == O_secrel)
6207 {
6208 exp->X_op = O_symbol;
6209 r = BFD_RELOC_32_SECREL;
6210 }
6211#endif
6212
6213 fix_new_exp (frag, off, len, exp, 0, r);
6214}
6215
718ddfc0
JB		 6216#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6217# define lex_got(reloc, adjust, types) NULL
6218#else
f3c180ae
AM		 6219/* Parse operands of the form
6220 <symbol>@GOTOFF+<nnn>
6221 and similar .plt or .got references.
6222
6223 If we find one, set up the correct relocation in RELOC and copy the
6224 input string, minus the `@GOTOFF' into a malloc'd buffer for
6225 parsing by the calling routine. Return this buffer, and if ADJUST
6226 is non-null set it to the length of the string we removed from the
6227 input line. Otherwise return NULL. */
6228static char *
3956db08 6229lex_got (enum bfd_reloc_code_real *reloc,
64e74474 6230 int *adjust,
40fb9820 6231 i386_operand_type *types)
f3c180ae 6232{
7b81dfbb
AJ		 6233 /* Some of the relocations depend on the size of what field is to
6234 be relocated. But in our callers i386_immediate and i386_displacement
6235 we don't yet know the operand size (this will be set by insn
6236 matching). Hence we record the word32 relocation here,
6237 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6238 static const struct {
6239 const char *str;
4fa24527 6240 const enum bfd_reloc_code_real rel[2];
40fb9820 6241 const i386_operand_type types64;
f3c180ae 6242 } gotrel[] = {
4eed87de
AM		 6243 { "PLTOFF", { 0,
6244 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6245 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6246 { "PLT", { BFD_RELOC_386_PLT32,
6247 BFD_RELOC_X86_64_PLT32 },
40fb9820 6248 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6249 { "GOTPLT", { 0,
6250 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6251 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6252 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6253 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6254 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6255 { "GOTPCREL", { 0,
6256 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6257 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6258 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6259 BFD_RELOC_X86_64_TLSGD },
40fb9820 6260 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6261 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
6262 0 },
40fb9820 6263 OPERAND_TYPE_NONE },
4eed87de
AM		 6264 { "TLSLD", { 0,
6265 BFD_RELOC_X86_64_TLSLD },
40fb9820 6266 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6267 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6268 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6269 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6270 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6271 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6272 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6273 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
6274 0 },
40fb9820 6275 OPERAND_TYPE_NONE },
4eed87de
AM		 6276 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6277 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 6278
6279 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6280 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
6281 0 },
40fb9820 6282 OPERAND_TYPE_NONE },
4eed87de
AM		 6283 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
6284 0 },
40fb9820 6285 OPERAND_TYPE_NONE },
4eed87de
AM		 6286 { "GOT", { BFD_RELOC_386_GOT32,
6287 BFD_RELOC_X86_64_GOT32 },
40fb9820 6288 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6289 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6290 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6291 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6292 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6293 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6294 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6295 };
6296 char *cp;
6297 unsigned int j;
6298
718ddfc0
JB		 6299 if (!IS_ELF)
6300 return NULL;
6301
f3c180ae 6302 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6303 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6304 return NULL;
6305
47465058 6306 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6307 {
6308 int len;
6309
6310 len = strlen (gotrel[j].str);
28f81592 6311 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6312 {
4fa24527 6313 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6314 {
28f81592
AM		 6315 int first, second;
6316 char *tmpbuf, *past_reloc;
f3c180ae 6317
4fa24527 6318 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 6319 if (adjust)
6320 *adjust = len;
f3c180ae 6321
3956db08
JB		 6322 if (types)
6323 {
6324 if (flag_code != CODE_64BIT)
40fb9820
L		 6325 {
6326 types->bitfield.imm32 = 1;
6327 types->bitfield.disp32 = 1;
6328 }
3956db08
JB		 6329 else
6330 *types = gotrel[j].types64;
6331 }
6332
f3c180ae
AM		 6333 if (GOT_symbol == NULL)
6334 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6335
28f81592 6336 /* The length of the first part of our input line. */
f3c180ae 6337 first = cp - input_line_pointer;
28f81592
AM		 6338
6339 /* The second part goes from after the reloc token until
67c11a9b 6340 (and including) an end_of_line char or comma. */
28f81592 6341 past_reloc = cp + 1 + len;
67c11a9b
AM		 6342 cp = past_reloc;
6343 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6344 ++cp;
6345 second = cp + 1 - past_reloc;
28f81592
AM		 6346
6347 /* Allocate and copy string. The trailing NUL shouldn't
6348 be necessary, but be safe. */
6349 tmpbuf = xmalloc (first + second + 2);
f3c180ae 6350 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6351 if (second != 0 && *past_reloc != ' ')
6352 /* Replace the relocation token with ' ', so that
6353 errors like foo@GOTOFF1 will be detected. */
6354 tmpbuf[first++] = ' ';
6355 memcpy (tmpbuf + first, past_reloc, second);
6356 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6357 return tmpbuf;
6358 }
6359
4fa24527
JB		 6360 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6361 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6362 return NULL;
6363 }
6364 }
6365
6366 /* Might be a symbol version string. Don't as_bad here. */
6367 return NULL;
6368}
6369
f3c180ae 6370void
e3bb37b5 6371x86_cons (expressionS *exp, int size)
f3c180ae 6372{
4fa24527 6373 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6374 {
6375 /* Handle @GOTOFF and the like in an expression. */
6376 char *save;
6377 char *gotfree_input_line;
6378 int adjust;
6379
6380 save = input_line_pointer;
3956db08 6381 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6382 if (gotfree_input_line)
6383 input_line_pointer = gotfree_input_line;
6384
6385 expression (exp);
6386
6387 if (gotfree_input_line)
6388 {
6389 /* expression () has merrily parsed up to the end of line,
6390 or a comma - in the wrong buffer. Transfer how far
6391 input_line_pointer has moved to the right buffer. */
6392 input_line_pointer = (save
6393 + (input_line_pointer - gotfree_input_line)
6394 + adjust);
6395 free (gotfree_input_line);
3992d3b7
AM		 6396 if (exp->X_op == O_constant
6397 || exp->X_op == O_absent
6398 || exp->X_op == O_illegal
6399 || exp->X_op == O_register
6400 || exp->X_op == O_big)
6401 {
6402 char c = *input_line_pointer;
6403 *input_line_pointer = 0;
6404 as_bad (_("missing or invalid expression `%s'"), save);
6405 *input_line_pointer = c;
6406 }
f3c180ae
AM		 6407 }
6408 }
6409 else
6410 expression (exp);
6411}
6412#endif
6413
d182319b 6414static void signed_cons (int size)
6482c264 6415{
d182319b
JB		 6416 if (flag_code == CODE_64BIT)
6417 cons_sign = 1;
6418 cons (size);
6419 cons_sign = -1;
6482c264
NC		 6420}
6421
d182319b 6422#ifdef TE_PE
6482c264
NC		 6423static void
6424pe_directive_secrel (dummy)
6425 int dummy ATTRIBUTE_UNUSED;
6426{
6427 expressionS exp;
6428
6429 do
6430 {
6431 expression (&exp);
6432 if (exp.X_op == O_symbol)
6433 exp.X_op = O_secrel;
6434
6435 emit_expr (&exp, 4);
6436 }
6437 while (*input_line_pointer++ == ',');
6438
6439 input_line_pointer--;
6440 demand_empty_rest_of_line ();
6441}
6482c264
NC		 6442#endif
6443
252b5132 6444static int
70e41ade 6445i386_immediate (char *imm_start)
252b5132
RH		 6446{
6447 char *save_input_line_pointer;
f3c180ae 6448 char *gotfree_input_line;
252b5132 6449 segT exp_seg = 0;
47926f60 6450 expressionS *exp;
40fb9820
L		 6451 i386_operand_type types;
6452
0dfbf9d7 6453 operand_type_set (&types, ~0);
252b5132
RH		 6454
6455 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6456 {
31b2323c
L		 6457 as_bad (_("at most %d immediate operands are allowed"),
6458 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6459 return 0;
6460 }
6461
6462 exp = &im_expressions[i.imm_operands++];
520dc8e8 6463 i.op[this_operand].imms = exp;
252b5132
RH		 6464
6465 if (is_space_char (*imm_start))
6466 ++imm_start;
6467
6468 save_input_line_pointer = input_line_pointer;
6469 input_line_pointer = imm_start;
6470
3956db08 6471 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6472 if (gotfree_input_line)
6473 input_line_pointer = gotfree_input_line;
252b5132
RH		 6474
6475 exp_seg = expression (exp);
6476
83183c0c 6477 SKIP_WHITESPACE ();
252b5132 6478 if (*input_line_pointer)
f3c180ae 6479 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6480
6481 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 6482 if (gotfree_input_line)
6483 free (gotfree_input_line);
252b5132 6484
3992d3b7
AM		 6485 if (exp->X_op == O_absent
6486 || exp->X_op == O_illegal
6487 || exp->X_op == O_big
6488 || (gotfree_input_line
6489 && (exp->X_op == O_constant
6490 || exp->X_op == O_register)))
252b5132 6491 {
3992d3b7 6492 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 6493 imm_start);
3992d3b7 6494 return 0;
252b5132 6495 }
3e73aa7c 6496 else if (exp->X_op == O_constant)
252b5132 6497 {
47926f60 6498 /* Size it properly later. */
40fb9820 6499 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6500 /* If BFD64, sign extend val. */
4eed87de
AM		 6501 if (!use_rela_relocations
6502 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6503 exp->X_add_number
6504 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6505 }
4c63da97 6506#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6507 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6508 && exp_seg != absolute_section
47926f60 6509 && exp_seg != text_section
24eab124
AM		 6510 && exp_seg != data_section
6511 && exp_seg != bss_section
6512 && exp_seg != undefined_section
f86103b7 6513 && !bfd_is_com_section (exp_seg))
252b5132 6514 {
d0b47220 6515 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6516 return 0;
6517 }
6518#endif
bb8f5920
L		 6519 else if (!intel_syntax && exp->X_op == O_register)
6520 {
6521 as_bad (_("illegal immediate register operand %s"), imm_start);
6522 return 0;
6523 }
252b5132
RH		 6524 else
6525 {
6526 /* This is an address. The size of the address will be
24eab124 6527 determined later, depending on destination register,
3e73aa7c 6528 suffix, or the default for the section. */
40fb9820
L		 6529 i.types[this_operand].bitfield.imm8 = 1;
6530 i.types[this_operand].bitfield.imm16 = 1;
6531 i.types[this_operand].bitfield.imm32 = 1;
6532 i.types[this_operand].bitfield.imm32s = 1;
6533 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6534 i.types[this_operand] = operand_type_and (i.types[this_operand],
6535 types);
252b5132
RH		 6536 }
6537
6538 return 1;
6539}
6540
551c1ca1 6541static char *
e3bb37b5 6542i386_scale (char *scale)
252b5132 6543{
551c1ca1
AM		 6544 offsetT val;
6545 char *save = input_line_pointer;
252b5132 6546
551c1ca1
AM		 6547 input_line_pointer = scale;
6548 val = get_absolute_expression ();
6549
6550 switch (val)
252b5132 6551 {
551c1ca1 6552 case 1:
252b5132
RH		 6553 i.log2_scale_factor = 0;
6554 break;
551c1ca1 6555 case 2:
252b5132
RH		 6556 i.log2_scale_factor = 1;
6557 break;
551c1ca1 6558 case 4:
252b5132
RH		 6559 i.log2_scale_factor = 2;
6560 break;
551c1ca1 6561 case 8:
252b5132
RH		 6562 i.log2_scale_factor = 3;
6563 break;
6564 default:
a724f0f4
JB		 6565 {
6566 char sep = *input_line_pointer;
6567
6568 *input_line_pointer = '\0';
6569 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6570 scale);
6571 *input_line_pointer = sep;
6572 input_line_pointer = save;
6573 return NULL;
6574 }
252b5132 6575 }
29b0f896 6576 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6577 {
6578 as_warn (_("scale factor of %d without an index register"),
24eab124 6579 1 << i.log2_scale_factor);
252b5132 6580 i.log2_scale_factor = 0;
252b5132 6581 }
551c1ca1
AM		 6582 scale = input_line_pointer;
6583 input_line_pointer = save;
6584 return scale;
252b5132
RH		 6585}
6586
252b5132 6587static int
e3bb37b5 6588i386_displacement (char *disp_start, char *disp_end)
252b5132 6589{
29b0f896 6590 expressionS *exp;
252b5132
RH		 6591 segT exp_seg = 0;
6592 char *save_input_line_pointer;
f3c180ae 6593 char *gotfree_input_line;
40fb9820
L		 6594 int override;
6595 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6596 int ret;
252b5132 6597
31b2323c
L		 6598 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6599 {
6600 as_bad (_("at most %d displacement operands are allowed"),
6601 MAX_MEMORY_OPERANDS);
6602 return 0;
6603 }
6604
0dfbf9d7 6605 operand_type_set (&bigdisp, 0);
40fb9820
L		 6606 if ((i.types[this_operand].bitfield.jumpabsolute)
6607 || (!current_templates->start->opcode_modifier.jump
6608 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6609 {
40fb9820 6610 bigdisp.bitfield.disp32 = 1;
e05278af 6611 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6612 if (flag_code == CODE_64BIT)
6613 {
6614 if (!override)
6615 {
6616 bigdisp.bitfield.disp32s = 1;
6617 bigdisp.bitfield.disp64 = 1;
6618 }
6619 }
6620 else if ((flag_code == CODE_16BIT) ^ override)
6621 {
6622 bigdisp.bitfield.disp32 = 0;
6623 bigdisp.bitfield.disp16 = 1;
6624 }
e05278af
JB		 6625 }
6626 else
6627 {
6628 /* For PC-relative branches, the width of the displacement
6629 is dependent upon data size, not address size. */
e05278af 6630 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6631 if (flag_code == CODE_64BIT)
6632 {
6633 if (override || i.suffix == WORD_MNEM_SUFFIX)
6634 bigdisp.bitfield.disp16 = 1;
6635 else
6636 {
6637 bigdisp.bitfield.disp32 = 1;
6638 bigdisp.bitfield.disp32s = 1;
6639 }
6640 }
6641 else
e05278af
JB		 6642 {
6643 if (!override)
6644 override = (i.suffix == (flag_code != CODE_16BIT
6645 ? WORD_MNEM_SUFFIX
6646 : LONG_MNEM_SUFFIX));
40fb9820
L		 6647 bigdisp.bitfield.disp32 = 1;
6648 if ((flag_code == CODE_16BIT) ^ override)
6649 {
6650 bigdisp.bitfield.disp32 = 0;
6651 bigdisp.bitfield.disp16 = 1;
6652 }
e05278af 6653 }
e05278af 6654 }
c6fb90c8
L		 6655 i.types[this_operand] = operand_type_or (i.types[this_operand],
6656 bigdisp);
252b5132
RH		 6657
6658 exp = &disp_expressions[i.disp_operands];
520dc8e8 6659 i.op[this_operand].disps = exp;
252b5132
RH		 6660 i.disp_operands++;
6661 save_input_line_pointer = input_line_pointer;
6662 input_line_pointer = disp_start;
6663 END_STRING_AND_SAVE (disp_end);
6664
6665#ifndef GCC_ASM_O_HACK
6666#define GCC_ASM_O_HACK 0
6667#endif
6668#if GCC_ASM_O_HACK
6669 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6670 if (i.types[this_operand].bitfield.baseIndex
24eab124 6671 && displacement_string_end[-1] == '+')
252b5132
RH		 6672 {
6673 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6674 constraint within gcc asm statements.
6675 For instance:
6676
6677 #define _set_tssldt_desc(n,addr,limit,type) \
6678 __asm__ __volatile__ ( \
6679 "movw %w2,%0\n\t" \
6680 "movw %w1,2+%0\n\t" \
6681 "rorl $16,%1\n\t" \
6682 "movb %b1,4+%0\n\t" \
6683 "movb %4,5+%0\n\t" \
6684 "movb $0,6+%0\n\t" \
6685 "movb %h1,7+%0\n\t" \
6686 "rorl $16,%1" \
6687 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6688
6689 This works great except that the output assembler ends
6690 up looking a bit weird if it turns out that there is
6691 no offset. You end up producing code that looks like:
6692
6693 #APP
6694 movw $235,(%eax)
6695 movw %dx,2+(%eax)
6696 rorl $16,%edx
6697 movb %dl,4+(%eax)
6698 movb $137,5+(%eax)
6699 movb $0,6+(%eax)
6700 movb %dh,7+(%eax)
6701 rorl $16,%edx
6702 #NO_APP
6703
47926f60 6704 So here we provide the missing zero. */
24eab124
AM		 6705
6706 *displacement_string_end = '0';
252b5132
RH		 6707 }
6708#endif
3956db08 6709 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6710 if (gotfree_input_line)
6711 input_line_pointer = gotfree_input_line;
252b5132 6712
24eab124 6713 exp_seg = expression (exp);
252b5132 6714
636c26b0
AM		 6715 SKIP_WHITESPACE ();
6716 if (*input_line_pointer)
6717 as_bad (_("junk `%s' after expression"), input_line_pointer);
6718#if GCC_ASM_O_HACK
6719 RESTORE_END_STRING (disp_end + 1);
6720#endif
636c26b0 6721 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 6722 if (gotfree_input_line)
6723 free (gotfree_input_line);
3992d3b7 6724 ret = 1;
636c26b0 6725
24eab124
AM		 6726 /* We do this to make sure that the section symbol is in
6727 the symbol table. We will ultimately change the relocation
47926f60 6728 to be relative to the beginning of the section. */
1ae12ab7 6729 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6730 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6731 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6732 {
636c26b0 6733 if (exp->X_op != O_symbol)
3992d3b7 6734 goto inv_disp;
636c26b0 6735
e5cb08ac 6736 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6737 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6738 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6739 exp->X_op = O_subtract;
6740 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6741 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6742 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6743 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6744 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6745 else
29b0f896 6746 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6747 }
252b5132 6748
3992d3b7
AM		 6749 else if (exp->X_op == O_absent
6750 || exp->X_op == O_illegal
6751 || exp->X_op == O_big
6752 || (gotfree_input_line
6753 && (exp->X_op == O_constant
6754 || exp->X_op == O_register)))
2daf4fd8 6755 {
3992d3b7
AM		 6756 inv_disp:
6757 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6758 disp_start);
3992d3b7 6759 ret = 0;
2daf4fd8
AM		 6760 }
6761
4c63da97 6762#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6763 else if (exp->X_op != O_constant
6764 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6765 && exp_seg != absolute_section
6766 && exp_seg != text_section
6767 && exp_seg != data_section
6768 && exp_seg != bss_section
6769 && exp_seg != undefined_section
6770 && !bfd_is_com_section (exp_seg))
24eab124 6771 {
d0b47220 6772 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6773 ret = 0;
24eab124 6774 }
252b5132 6775#endif
3956db08 6776
3992d3b7
AM		 6777 RESTORE_END_STRING (disp_end);
6778
40fb9820
L		 6779 /* Check if this is a displacement only operand. */
6780 bigdisp = i.types[this_operand];
6781 bigdisp.bitfield.disp8 = 0;
6782 bigdisp.bitfield.disp16 = 0;
6783 bigdisp.bitfield.disp32 = 0;
6784 bigdisp.bitfield.disp32s = 0;
6785 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6786 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6787 i.types[this_operand] = operand_type_and (i.types[this_operand],
6788 types);
3956db08 6789
3992d3b7 6790 return ret;
252b5132
RH		 6791}
6792
eecb386c 6793/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6794 Return 1 on success, 0 on a failure. */
6795
252b5132 6796static int
e3bb37b5 6797i386_index_check (const char *operand_string)
252b5132 6798{
3e73aa7c 6799 int ok;
24eab124 6800#if INFER_ADDR_PREFIX
eecb386c
AM		 6801 int fudged = 0;
6802
24eab124
AM		 6803 tryprefix:
6804#endif
3e73aa7c 6805 ok = 1;
75178d9d 6806 if (flag_code == CODE_64BIT)
64e74474 6807 {
64e74474 6808 if ((i.base_reg
40fb9820
L		 6809 && ((i.prefix[ADDR_PREFIX] == 0
6810 && !i.base_reg->reg_type.bitfield.reg64)
6811 || (i.prefix[ADDR_PREFIX]
6812 && !i.base_reg->reg_type.bitfield.reg32))
6813 && (i.index_reg
9a04903e
JB		 6814 || i.base_reg->reg_num !=
6815 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6816 || (i.index_reg
40fb9820
L		 6817 && (!i.index_reg->reg_type.bitfield.baseindex
6818 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6819 && i.index_reg->reg_num != RegRiz
6820 && !i.index_reg->reg_type.bitfield.reg64
6821 )
40fb9820 6822 || (i.prefix[ADDR_PREFIX]
db51cc60 6823 && i.index_reg->reg_num != RegEiz
40fb9820 6824 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6825 ok = 0;
3e73aa7c
JH		 6826 }
6827 else
6828 {
6829 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6830 {
6831 /* 16bit checks. */
6832 if ((i.base_reg
40fb9820
L		 6833 && (!i.base_reg->reg_type.bitfield.reg16
6834 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6835 || (i.index_reg
40fb9820
L		 6836 && (!i.index_reg->reg_type.bitfield.reg16
6837 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6838 || !(i.base_reg
6839 && i.base_reg->reg_num < 6
6840 && i.index_reg->reg_num >= 6
6841 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6842 ok = 0;
6843 }
6844 else
e5cb08ac 6845 {
3e73aa7c
JH		 6846 /* 32bit checks. */
6847 if ((i.base_reg
40fb9820 6848 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6849 || (i.index_reg
db51cc60
L		 6850 && ((!i.index_reg->reg_type.bitfield.reg32
6851 && i.index_reg->reg_num != RegEiz)
40fb9820 6852 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6853 ok = 0;
3e73aa7c
JH		 6854 }
6855 }
6856 if (!ok)
24eab124
AM		 6857 {
6858#if INFER_ADDR_PREFIX
20f0a1fc 6859 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6860 {
6861 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6862 i.prefixes += 1;
b23bac36
AM		 6863 /* Change the size of any displacement too. At most one of
6864 Disp16 or Disp32 is set.
6865 FIXME. There doesn't seem to be any real need for separate
6866 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6867 Removing them would probably clean up the code quite a lot. */
4eed87de 6868 if (flag_code != CODE_64BIT
40fb9820
L		 6869 && (i.types[this_operand].bitfield.disp16
6870 || i.types[this_operand].bitfield.disp32))
6871 i.types[this_operand]
c6fb90c8 6872 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6873 fudged = 1;
24eab124
AM		 6874 goto tryprefix;
6875 }
eecb386c
AM		 6876 if (fudged)
6877 as_bad (_("`%s' is not a valid base/index expression"),
6878 operand_string);
6879 else
c388dee8 6880#endif
eecb386c
AM		 6881 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6882 operand_string,
3e73aa7c 6883 flag_code_names[flag_code]);
24eab124 6884 }
20f0a1fc 6885 return ok;
24eab124 6886}
252b5132 6887
252b5132 6888/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6889 on error. */
252b5132 6890
252b5132 6891static int
a7619375 6892i386_att_operand (char *operand_string)
252b5132 6893{
af6bdddf
AM		 6894 const reg_entry *r;
6895 char *end_op;
24eab124 6896 char *op_string = operand_string;
252b5132 6897
24eab124 6898 if (is_space_char (*op_string))
252b5132
RH		 6899 ++op_string;
6900
24eab124 6901 /* We check for an absolute prefix (differentiating,
47926f60 6902 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6903 if (*op_string == ABSOLUTE_PREFIX)
6904 {
6905 ++op_string;
6906 if (is_space_char (*op_string))
6907 ++op_string;
40fb9820 6908 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6909 }
252b5132 6910
47926f60 6911 /* Check if operand is a register. */
4d1bb795 6912 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6913 {
40fb9820
L		 6914 i386_operand_type temp;
6915
24eab124
AM		 6916 /* Check for a segment override by searching for ':' after a
6917 segment register. */
6918 op_string = end_op;
6919 if (is_space_char (*op_string))
6920 ++op_string;
40fb9820
L		 6921 if (*op_string == ':'
6922 && (r->reg_type.bitfield.sreg2
6923 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6924 {
6925 switch (r->reg_num)
6926 {
6927 case 0:
6928 i.seg[i.mem_operands] = &es;
6929 break;
6930 case 1:
6931 i.seg[i.mem_operands] = &cs;
6932 break;
6933 case 2:
6934 i.seg[i.mem_operands] = &ss;
6935 break;
6936 case 3:
6937 i.seg[i.mem_operands] = &ds;
6938 break;
6939 case 4:
6940 i.seg[i.mem_operands] = &fs;
6941 break;
6942 case 5:
6943 i.seg[i.mem_operands] = &gs;
6944 break;
6945 }
252b5132 6946
24eab124 6947 /* Skip the ':' and whitespace. */
252b5132
RH		 6948 ++op_string;
6949 if (is_space_char (*op_string))
24eab124 6950 ++op_string;
252b5132 6951
24eab124
AM		 6952 if (!is_digit_char (*op_string)
6953 && !is_identifier_char (*op_string)
6954 && *op_string != '('
6955 && *op_string != ABSOLUTE_PREFIX)
6956 {
6957 as_bad (_("bad memory operand `%s'"), op_string);
6958 return 0;
6959 }
47926f60 6960 /* Handle case of %es:*foo. */
24eab124
AM		 6961 if (*op_string == ABSOLUTE_PREFIX)
6962 {
6963 ++op_string;
6964 if (is_space_char (*op_string))
6965 ++op_string;
40fb9820 6966 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6967 }
6968 goto do_memory_reference;
6969 }
6970 if (*op_string)
6971 {
d0b47220 6972 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6973 return 0;
6974 }
40fb9820
L		 6975 temp = r->reg_type;
6976 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6977 i.types[this_operand] = operand_type_or (i.types[this_operand],
6978 temp);
7d5e4556 6979 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6980 i.op[this_operand].regs = r;
24eab124
AM		 6981 i.reg_operands++;
6982 }
af6bdddf
AM		 6983 else if (*op_string == REGISTER_PREFIX)
6984 {
6985 as_bad (_("bad register name `%s'"), op_string);
6986 return 0;
6987 }
24eab124 6988 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6989 {
24eab124 6990 ++op_string;
40fb9820 6991 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6992 {
d0b47220 6993 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6994 return 0;
6995 }
6996 if (!i386_immediate (op_string))
6997 return 0;
6998 }
6999 else if (is_digit_char (*op_string)
7000 || is_identifier_char (*op_string)
e5cb08ac 7001 || *op_string == '(')
24eab124 7002 {
47926f60 7003 /* This is a memory reference of some sort. */
af6bdddf 7004 char *base_string;
252b5132 7005
47926f60 7006 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7007 char *displacement_string_start;
7008 char *displacement_string_end;
252b5132 7009
24eab124 7010 do_memory_reference:
24eab124 7011 if ((i.mem_operands == 1
40fb9820 7012 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7013 || i.mem_operands == 2)
7014 {
7015 as_bad (_("too many memory references for `%s'"),
7016 current_templates->start->name);
7017 return 0;
7018 }
252b5132 7019
24eab124
AM		 7020 /* Check for base index form. We detect the base index form by
7021 looking for an ')' at the end of the operand, searching
7022 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7023 after the '('. */
af6bdddf 7024 base_string = op_string + strlen (op_string);
c3332e24 7025
af6bdddf
AM		 7026 --base_string;
7027 if (is_space_char (*base_string))
7028 --base_string;
252b5132 7029
47926f60 7030 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7031 displacement_string_start = op_string;
7032 displacement_string_end = base_string + 1;
252b5132 7033
24eab124
AM		 7034 if (*base_string == ')')
7035 {
af6bdddf 7036 char *temp_string;
24eab124
AM		 7037 unsigned int parens_balanced = 1;
7038 /* We've already checked that the number of left & right ()'s are
47926f60 7039 equal, so this loop will not be infinite. */
24eab124
AM		 7040 do
7041 {
7042 base_string--;
7043 if (*base_string == ')')
7044 parens_balanced++;
7045 if (*base_string == '(')
7046 parens_balanced--;
7047 }
7048 while (parens_balanced);
c3332e24 7049
af6bdddf 7050 temp_string = base_string;
c3332e24 7051
24eab124 7052 /* Skip past '(' and whitespace. */
252b5132
RH		 7053 ++base_string;
7054 if (is_space_char (*base_string))
24eab124 7055 ++base_string;
252b5132 7056
af6bdddf 7057 if (*base_string == ','
4eed87de
AM		 7058 || ((i.base_reg = parse_register (base_string, &end_op))
7059 != NULL))
252b5132 7060 {
af6bdddf 7061 displacement_string_end = temp_string;
252b5132 7062
40fb9820 7063 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7064
af6bdddf 7065 if (i.base_reg)
24eab124 7066 {
24eab124
AM		 7067 base_string = end_op;
7068 if (is_space_char (*base_string))
7069 ++base_string;
af6bdddf
AM		 7070 }
7071
7072 /* There may be an index reg or scale factor here. */
7073 if (*base_string == ',')
7074 {
7075 ++base_string;
7076 if (is_space_char (*base_string))
7077 ++base_string;
7078
4eed87de
AM		 7079 if ((i.index_reg = parse_register (base_string, &end_op))
7080 != NULL)
24eab124 7081 {
af6bdddf 7082 base_string = end_op;
24eab124
AM		 7083 if (is_space_char (*base_string))
7084 ++base_string;
af6bdddf
AM		 7085 if (*base_string == ',')
7086 {
7087 ++base_string;
7088 if (is_space_char (*base_string))
7089 ++base_string;
7090 }
e5cb08ac 7091 else if (*base_string != ')')
af6bdddf 7092 {
4eed87de
AM		 7093 as_bad (_("expecting `,' or `)' "
7094 "after index register in `%s'"),
af6bdddf
AM		 7095 operand_string);
7096 return 0;
7097 }
24eab124 7098 }
af6bdddf 7099 else if (*base_string == REGISTER_PREFIX)
24eab124 7100 {
af6bdddf 7101 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7102 return 0;
7103 }
252b5132 7104
47926f60 7105 /* Check for scale factor. */
551c1ca1 7106 if (*base_string != ')')
af6bdddf 7107 {
551c1ca1
AM		 7108 char *end_scale = i386_scale (base_string);
7109
7110 if (!end_scale)
af6bdddf 7111 return 0;
24eab124 7112
551c1ca1 7113 base_string = end_scale;
af6bdddf
AM		 7114 if (is_space_char (*base_string))
7115 ++base_string;
7116 if (*base_string != ')')
7117 {
4eed87de
AM		 7118 as_bad (_("expecting `)' "
7119 "after scale factor in `%s'"),
af6bdddf
AM		 7120 operand_string);
7121 return 0;
7122 }
7123 }
7124 else if (!i.index_reg)
24eab124 7125 {
4eed87de
AM		 7126 as_bad (_("expecting index register or scale factor "
7127 "after `,'; got '%c'"),
af6bdddf 7128 *base_string);
24eab124
AM		 7129 return 0;
7130 }
7131 }
af6bdddf 7132 else if (*base_string != ')')
24eab124 7133 {
4eed87de
AM		 7134 as_bad (_("expecting `,' or `)' "
7135 "after base register in `%s'"),
af6bdddf 7136 operand_string);
24eab124
AM		 7137 return 0;
7138 }
c3332e24 7139 }
af6bdddf 7140 else if (*base_string == REGISTER_PREFIX)
c3332e24 7141 {
af6bdddf 7142 as_bad (_("bad register name `%s'"), base_string);
24eab124 7143 return 0;
c3332e24 7144 }
24eab124
AM		 7145 }
7146
7147 /* If there's an expression beginning the operand, parse it,
7148 assuming displacement_string_start and
7149 displacement_string_end are meaningful. */
7150 if (displacement_string_start != displacement_string_end)
7151 {
7152 if (!i386_displacement (displacement_string_start,
7153 displacement_string_end))
7154 return 0;
7155 }
7156
7157 /* Special case for (%dx) while doing input/output op. */
7158 if (i.base_reg
0dfbf9d7
L		 7159 && operand_type_equal (&i.base_reg->reg_type,
7160 &reg16_inoutportreg)
24eab124
AM		 7161 && i.index_reg == 0
7162 && i.log2_scale_factor == 0
7163 && i.seg[i.mem_operands] == 0
40fb9820 7164 && !operand_type_check (i.types[this_operand], disp))
24eab124 7165 {
65da13b5 7166 i.types[this_operand] = inoutportreg;
24eab124
AM		 7167 return 1;
7168 }
7169
eecb386c
AM		 7170 if (i386_index_check (operand_string) == 0)
7171 return 0;
5c07affc 7172 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7173 i.mem_operands++;
7174 }
7175 else
ce8a8b2f
AM		 7176 {
7177 /* It's not a memory operand; argh! */
24eab124
AM		 7178 as_bad (_("invalid char %s beginning operand %d `%s'"),
7179 output_invalid (*op_string),
7180 this_operand + 1,
7181 op_string);
7182 return 0;
7183 }
47926f60 7184 return 1; /* Normal return. */
252b5132
RH		 7185}
7186\f
ee7fcc42
AM		 7187/* md_estimate_size_before_relax()
7188
7189 Called just before relax() for rs_machine_dependent frags. The x86
7190 assembler uses these frags to handle variable size jump
7191 instructions.
7192
7193 Any symbol that is now undefined will not become defined.
7194 Return the correct fr_subtype in the frag.
7195 Return the initial "guess for variable size of frag" to caller.
7196 The guess is actually the growth beyond the fixed part. Whatever
7197 we do to grow the fixed or variable part contributes to our
7198 returned value. */
7199
252b5132
RH		 7200int
7201md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7202 fragS *fragP;
7203 segT segment;
252b5132 7204{
252b5132 7205 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7206 check for un-relaxable symbols. On an ELF system, we can't relax
7207 an externally visible symbol, because it may be overridden by a
7208 shared library. */
7209 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7210#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7211 || (IS_ELF
31312f95
AM		 7212 && (S_IS_EXTERNAL (fragP->fr_symbol)
7213 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 7214#endif
7215 )
252b5132 7216 {
b98ef147
AM		 7217 /* Symbol is undefined in this segment, or we need to keep a
7218 reloc so that weak symbols can be overridden. */
7219 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7220 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7221 unsigned char *opcode;
7222 int old_fr_fix;
f6af82bd 7223
ee7fcc42
AM		 7224 if (fragP->fr_var != NO_RELOC)
7225 reloc_type = fragP->fr_var;
b98ef147 7226 else if (size == 2)
f6af82bd
AM		 7227 reloc_type = BFD_RELOC_16_PCREL;
7228 else
7229 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7230
ee7fcc42
AM		 7231 old_fr_fix = fragP->fr_fix;
7232 opcode = (unsigned char *) fragP->fr_opcode;
7233
fddf5b5b 7234 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7235 {
fddf5b5b
AM		 7236 case UNCOND_JUMP:
7237 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7238 opcode[0] = 0xe9;
252b5132 7239 fragP->fr_fix += size;
062cd5e7
AS		 7240 fix_new (fragP, old_fr_fix, size,
7241 fragP->fr_symbol,
7242 fragP->fr_offset, 1,
7243 reloc_type);
252b5132
RH		 7244 break;
7245
fddf5b5b 7246 case COND_JUMP86:
412167cb
AM		 7247 if (size == 2
7248 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7249 {
7250 /* Negate the condition, and branch past an
7251 unconditional jump. */
7252 opcode[0] ^= 1;
7253 opcode[1] = 3;
7254 /* Insert an unconditional jump. */
7255 opcode[2] = 0xe9;
7256 /* We added two extra opcode bytes, and have a two byte
7257 offset. */
7258 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7259 fix_new (fragP, old_fr_fix + 2, 2,
7260 fragP->fr_symbol,
7261 fragP->fr_offset, 1,
7262 reloc_type);
fddf5b5b
AM		 7263 break;
7264 }
7265 /* Fall through. */
7266
7267 case COND_JUMP:
412167cb
AM		 7268 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7269 {
3e02c1cc
AM		 7270 fixS *fixP;
7271
412167cb 7272 fragP->fr_fix += 1;
3e02c1cc
AM		 7273 fixP = fix_new (fragP, old_fr_fix, 1,
7274 fragP->fr_symbol,
7275 fragP->fr_offset, 1,
7276 BFD_RELOC_8_PCREL);
7277 fixP->fx_signed = 1;
412167cb
AM		 7278 break;
7279 }
93c2a809 7280
24eab124 7281 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7282 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7283 opcode[1] = opcode[0] + 0x10;
f6af82bd 7284 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7285 /* We've added an opcode byte. */
7286 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7287 fix_new (fragP, old_fr_fix + 1, size,
7288 fragP->fr_symbol,
7289 fragP->fr_offset, 1,
7290 reloc_type);
252b5132 7291 break;
fddf5b5b
AM		 7292
7293 default:
7294 BAD_CASE (fragP->fr_subtype);
7295 break;
252b5132
RH		 7296 }
7297 frag_wane (fragP);
ee7fcc42 7298 return fragP->fr_fix - old_fr_fix;
252b5132 7299 }
93c2a809 7300
93c2a809
AM		 7301 /* Guess size depending on current relax state. Initially the relax
7302 state will correspond to a short jump and we return 1, because
7303 the variable part of the frag (the branch offset) is one byte
7304 long. However, we can relax a section more than once and in that
7305 case we must either set fr_subtype back to the unrelaxed state,
7306 or return the value for the appropriate branch. */
7307 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7308}
7309
47926f60
KH		 7310/* Called after relax() is finished.
7311
7312 In: Address of frag.
7313 fr_type == rs_machine_dependent.
7314 fr_subtype is what the address relaxed to.
7315
7316 Out: Any fixSs and constants are set up.
7317 Caller will turn frag into a ".space 0". */
7318
252b5132
RH		 7319void
7320md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7321 bfd *abfd ATTRIBUTE_UNUSED;
7322 segT sec ATTRIBUTE_UNUSED;
29b0f896 7323 fragS *fragP;
252b5132 7324{
29b0f896 7325 unsigned char *opcode;
252b5132 7326 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7327 offsetT target_address;
7328 offsetT opcode_address;
252b5132 7329 unsigned int extension = 0;
847f7ad4 7330 offsetT displacement_from_opcode_start;
252b5132
RH		 7331
7332 opcode = (unsigned char *) fragP->fr_opcode;
7333
47926f60 7334 /* Address we want to reach in file space. */
252b5132 7335 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7336
47926f60 7337 /* Address opcode resides at in file space. */
252b5132
RH		 7338 opcode_address = fragP->fr_address + fragP->fr_fix;
7339
47926f60 7340 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7341 displacement_from_opcode_start = target_address - opcode_address;
7342
fddf5b5b 7343 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7344 {
47926f60
KH		 7345 /* Don't have to change opcode. */
7346 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7347 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7348 }
7349 else
7350 {
7351 if (no_cond_jump_promotion
7352 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7353 as_warn_where (fragP->fr_file, fragP->fr_line,
7354 _("long jump required"));
252b5132 7355
fddf5b5b
AM		 7356 switch (fragP->fr_subtype)
7357 {
7358 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7359 extension = 4; /* 1 opcode + 4 displacement */
7360 opcode[0] = 0xe9;
7361 where_to_put_displacement = &opcode[1];
7362 break;
252b5132 7363
fddf5b5b
AM		 7364 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7365 extension = 2; /* 1 opcode + 2 displacement */
7366 opcode[0] = 0xe9;
7367 where_to_put_displacement = &opcode[1];
7368 break;
252b5132 7369
fddf5b5b
AM		 7370 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7371 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7372 extension = 5; /* 2 opcode + 4 displacement */
7373 opcode[1] = opcode[0] + 0x10;
7374 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7375 where_to_put_displacement = &opcode[2];
7376 break;
252b5132 7377
fddf5b5b
AM		 7378 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7379 extension = 3; /* 2 opcode + 2 displacement */
7380 opcode[1] = opcode[0] + 0x10;
7381 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7382 where_to_put_displacement = &opcode[2];
7383 break;
252b5132 7384
fddf5b5b
AM		 7385 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7386 extension = 4;
7387 opcode[0] ^= 1;
7388 opcode[1] = 3;
7389 opcode[2] = 0xe9;
7390 where_to_put_displacement = &opcode[3];
7391 break;
7392
7393 default:
7394 BAD_CASE (fragP->fr_subtype);
7395 break;
7396 }
252b5132 7397 }
fddf5b5b 7398
7b81dfbb
AJ		 7399 /* If size if less then four we are sure that the operand fits,
7400 but if it's 4, then it could be that the displacement is larger
7401 then -/+ 2GB. */
7402 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7403 && object_64bit
7404 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7405 + ((addressT) 1 << 31))
7406 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7407 {
7408 as_bad_where (fragP->fr_file, fragP->fr_line,
7409 _("jump target out of range"));
7410 /* Make us emit 0. */
7411 displacement_from_opcode_start = extension;
7412 }
47926f60 7413 /* Now put displacement after opcode. */
252b5132
RH		 7414 md_number_to_chars ((char *) where_to_put_displacement,
7415 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7416 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7417 fragP->fr_fix += extension;
7418}
7419\f
252b5132
RH		 7420/* Apply a fixup (fixS) to segment data, once it has been determined
7421 by our caller that we have all the info we need to fix it up.
7422
7423 On the 386, immediates, displacements, and data pointers are all in
7424 the same (little-endian) format, so we don't need to care about which
7425 we are handling. */
7426
94f592af 7427void
55cf6793 7428md_apply_fix (fixP, valP, seg)
47926f60
KH		 7429 /* The fix we're to put in. */
7430 fixS *fixP;
47926f60 7431 /* Pointer to the value of the bits. */
c6682705 7432 valueT *valP;
47926f60
KH		 7433 /* Segment fix is from. */
7434 segT seg ATTRIBUTE_UNUSED;
252b5132 7435{
94f592af 7436 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7437 valueT value = *valP;
252b5132 7438
f86103b7 7439#if !defined (TE_Mach)
93382f6d
AM		 7440 if (fixP->fx_pcrel)
7441 {
7442 switch (fixP->fx_r_type)
7443 {
5865bb77
ILT		 7444 default:
7445 break;
7446
d6ab8113
JB		 7447 case BFD_RELOC_64:
7448 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7449 break;
93382f6d 7450 case BFD_RELOC_32:
ae8887b5 7451 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7452 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7453 break;
7454 case BFD_RELOC_16:
7455 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7456 break;
7457 case BFD_RELOC_8:
7458 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7459 break;
7460 }
7461 }
252b5132 7462
a161fe53 7463 if (fixP->fx_addsy != NULL
31312f95 7464 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7465 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7466 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7467 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7468 && !use_rela_relocations)
252b5132 7469 {
31312f95
AM		 7470 /* This is a hack. There should be a better way to handle this.
7471 This covers for the fact that bfd_install_relocation will
7472 subtract the current location (for partial_inplace, PC relative
7473 relocations); see more below. */
252b5132 7474#ifndef OBJ_AOUT
718ddfc0 7475 if (IS_ELF
252b5132
RH		 7476#ifdef TE_PE
7477 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7478#endif
7479 )
7480 value += fixP->fx_where + fixP->fx_frag->fr_address;
7481#endif
7482#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7483 if (IS_ELF)
252b5132 7484 {
6539b54b 7485 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7486
6539b54b 7487 if ((sym_seg == seg
2f66722d 7488 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7489 && sym_seg != absolute_section))
ae6063d4 7490 && !generic_force_reloc (fixP))
2f66722d
AM		 7491 {
7492 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7493 bfd_install_relocation subtracts them out again. I think
7494 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7495 it. FIXME. */
7496 value += fixP->fx_where + fixP->fx_frag->fr_address;
7497 }
252b5132
RH		 7498 }
7499#endif
7500#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7501 /* For some reason, the PE format does not store a
7502 section address offset for a PC relative symbol. */
7503 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7504 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7505 value += md_pcrel_from (fixP);
7506#endif
7507 }
7508
7509 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7510 and we must not disappoint it. */
252b5132 7511#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7512 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7513 switch (fixP->fx_r_type)
7514 {
7515 case BFD_RELOC_386_PLT32:
3e73aa7c 7516 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7517 /* Make the jump instruction point to the address of the operand. At
7518 runtime we merely add the offset to the actual PLT entry. */
7519 value = -4;
7520 break;
31312f95 7521
13ae64f3
JJ		 7522 case BFD_RELOC_386_TLS_GD:
7523 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7524 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7525 case BFD_RELOC_386_TLS_IE:
7526 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7527 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7528 case BFD_RELOC_X86_64_TLSGD:
7529 case BFD_RELOC_X86_64_TLSLD:
7530 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7531 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7532 value = 0; /* Fully resolved at runtime. No addend. */
7533 /* Fallthrough */
7534 case BFD_RELOC_386_TLS_LE:
7535 case BFD_RELOC_386_TLS_LDO_32:
7536 case BFD_RELOC_386_TLS_LE_32:
7537 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7538 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7539 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7540 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7541 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7542 break;
7543
67a4f2b7
AO		 7544 case BFD_RELOC_386_TLS_DESC_CALL:
7545 case BFD_RELOC_X86_64_TLSDESC_CALL:
7546 value = 0; /* Fully resolved at runtime. No addend. */
7547 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7548 fixP->fx_done = 0;
7549 return;
7550
00f7efb6
JJ		 7551 case BFD_RELOC_386_GOT32:
7552 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7553 value = 0; /* Fully resolved at runtime. No addend. */
7554 break;
47926f60
KH		 7555
7556 case BFD_RELOC_VTABLE_INHERIT:
7557 case BFD_RELOC_VTABLE_ENTRY:
7558 fixP->fx_done = 0;
94f592af 7559 return;
47926f60
KH		 7560
7561 default:
7562 break;
7563 }
7564#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7565 *valP = value;
f86103b7 7566#endif /* !defined (TE_Mach) */
3e73aa7c 7567
3e73aa7c 7568 /* Are we finished with this relocation now? */
c6682705 7569 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 7570 fixP->fx_done = 1;
7571 else if (use_rela_relocations)
7572 {
7573 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7574 /* Remember value for tc_gen_reloc. */
7575 fixP->fx_addnumber = value;
3e73aa7c
JH		 7576 value = 0;
7577 }
f86103b7 7578
94f592af 7579 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7580}
252b5132 7581\f
252b5132 7582char *
499ac353 7583md_atof (int type, char *litP, int *sizeP)
252b5132 7584{
499ac353
NC		 7585 /* This outputs the LITTLENUMs in REVERSE order;
7586 in accord with the bigendian 386. */
7587 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7588}
7589\f
2d545b82 7590static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7591
252b5132 7592static char *
e3bb37b5 7593output_invalid (int c)
252b5132 7594{
3882b010 7595 if (ISPRINT (c))
f9f21a03
L		 7596 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7597 "'%c'", c);
252b5132 7598 else
f9f21a03 7599 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7600 "(0x%x)", (unsigned char) c);
252b5132
RH		 7601 return output_invalid_buf;
7602}
7603
af6bdddf 7604/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7605
7606static const reg_entry *
4d1bb795 7607parse_real_register (char *reg_string, char **end_op)
252b5132 7608{
af6bdddf
AM		 7609 char *s = reg_string;
7610 char *p;
252b5132
RH		 7611 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7612 const reg_entry *r;
7613
7614 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7615 if (*s == REGISTER_PREFIX)
7616 ++s;
7617
7618 if (is_space_char (*s))
7619 ++s;
7620
7621 p = reg_name_given;
af6bdddf 7622 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7623 {
7624 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7625 return (const reg_entry *) NULL;
7626 s++;
252b5132
RH		 7627 }
7628
6588847e
DN		 7629 /* For naked regs, make sure that we are not dealing with an identifier.
7630 This prevents confusing an identifier like `eax_var' with register
7631 `eax'. */
7632 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7633 return (const reg_entry *) NULL;
7634
af6bdddf 7635 *end_op = s;
252b5132
RH		 7636
7637 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7638
5f47d35b 7639 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7640 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7641 {
5f47d35b
AM		 7642 if (is_space_char (*s))
7643 ++s;
7644 if (*s == '(')
7645 {
af6bdddf 7646 ++s;
5f47d35b
AM		 7647 if (is_space_char (*s))
7648 ++s;
7649 if (*s >= '0' && *s <= '7')
7650 {
db557034 7651 int fpr = *s - '0';
af6bdddf 7652 ++s;
5f47d35b
AM		 7653 if (is_space_char (*s))
7654 ++s;
7655 if (*s == ')')
7656 {
7657 *end_op = s + 1;
db557034
AM		 7658 r = hash_find (reg_hash, "st(0)");
7659 know (r);
7660 return r + fpr;
5f47d35b 7661 }
5f47d35b 7662 }
47926f60 7663 /* We have "%st(" then garbage. */
5f47d35b
AM		 7664 return (const reg_entry *) NULL;
7665 }
7666 }
7667
a60de03c
JB		 7668 if (r == NULL || allow_pseudo_reg)
7669 return r;
7670
0dfbf9d7 7671 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7672 return (const reg_entry *) NULL;
7673
192dc9c6
JB		 7674 if ((r->reg_type.bitfield.reg32
7675 || r->reg_type.bitfield.sreg3
7676 || r->reg_type.bitfield.control
7677 || r->reg_type.bitfield.debug
7678 || r->reg_type.bitfield.test)
7679 && !cpu_arch_flags.bitfield.cpui386)
7680 return (const reg_entry *) NULL;
7681
7682 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7683 return (const reg_entry *) NULL;
7684
7685 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7686 return (const reg_entry *) NULL;
7687
db51cc60 7688 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7689 if (!allow_index_reg
db51cc60
L		 7690 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7691 return (const reg_entry *) NULL;
7692
a60de03c
JB		 7693 if (((r->reg_flags & (RegRex64 | RegRex))
7694 || r->reg_type.bitfield.reg64)
40fb9820 7695 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7696 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7697 && flag_code != CODE_64BIT)
20f0a1fc 7698 return (const reg_entry *) NULL;
1ae00879 7699
b7240065
JB		 7700 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7701 return (const reg_entry *) NULL;
7702
252b5132
RH		 7703 return r;
7704}
4d1bb795
JB		 7705
7706/* REG_STRING starts *before* REGISTER_PREFIX. */
7707
7708static const reg_entry *
7709parse_register (char *reg_string, char **end_op)
7710{
7711 const reg_entry *r;
7712
7713 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7714 r = parse_real_register (reg_string, end_op);
7715 else
7716 r = NULL;
7717 if (!r)
7718 {
7719 char *save = input_line_pointer;
7720 char c;
7721 symbolS *symbolP;
7722
7723 input_line_pointer = reg_string;
7724 c = get_symbol_end ();
7725 symbolP = symbol_find (reg_string);
7726 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7727 {
7728 const expressionS *e = symbol_get_value_expression (symbolP);
7729
7730 know (e->X_op == O_register);
4eed87de 7731 know (e->X_add_number >= 0
c3fe08fa 7732 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7733 r = i386_regtab + e->X_add_number;
7734 *end_op = input_line_pointer;
7735 }
7736 *input_line_pointer = c;
7737 input_line_pointer = save;
7738 }
7739 return r;
7740}
7741
7742int
7743i386_parse_name (char *name, expressionS *e, char *nextcharP)
7744{
7745 const reg_entry *r;
7746 char *end = input_line_pointer;
7747
7748 *end = *nextcharP;
7749 r = parse_register (name, &input_line_pointer);
7750 if (r && end <= input_line_pointer)
7751 {
7752 *nextcharP = *input_line_pointer;
7753 *input_line_pointer = 0;
7754 e->X_op = O_register;
7755 e->X_add_number = r - i386_regtab;
7756 return 1;
7757 }
7758 input_line_pointer = end;
7759 *end = 0;
7760 return 0;
7761}
7762
7763void
7764md_operand (expressionS *e)
7765{
7766 if (*input_line_pointer == REGISTER_PREFIX)
7767 {
7768 char *end;
7769 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7770
7771 if (r)
7772 {
7773 e->X_op = O_register;
7774 e->X_add_number = r - i386_regtab;
7775 input_line_pointer = end;
7776 }
7777 }
7778}
7779
252b5132 7780\f
4cc782b5 7781#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7782const char *md_shortopts = "kVQ:sqn";
252b5132 7783#else
12b55ccc 7784const char *md_shortopts = "qn";
252b5132 7785#endif
6e0b89ee 7786
3e73aa7c 7787#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7788#define OPTION_64 (OPTION_MD_BASE + 1)
7789#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7790#define OPTION_MARCH (OPTION_MD_BASE + 3)
7791#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7792#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7793#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7794#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7795#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7796#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7797#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
b3b91714 7798
99ad8390
NC		 7799struct option md_longopts[] =
7800{
3e73aa7c 7801 {"32", no_argument, NULL, OPTION_32},
99ad8390 7802#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7803 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7804#endif
b3b91714 7805 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7806 {"march", required_argument, NULL, OPTION_MARCH},
7807 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7808 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7809 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7810 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7811 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7812 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7813 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
252b5132
RH		 7814 {NULL, no_argument, NULL, 0}
7815};
7816size_t md_longopts_size = sizeof (md_longopts);
7817
7818int
9103f4f4 7819md_parse_option (int c, char *arg)
252b5132 7820{
9103f4f4 7821 unsigned int i;
6305a203 7822 char *arch, *next;
9103f4f4 7823
252b5132
RH		 7824 switch (c)
7825 {
12b55ccc
L		 7826 case 'n':
7827 optimize_align_code = 0;
7828 break;
7829
a38cf1db
AM		 7830 case 'q':
7831 quiet_warnings = 1;
252b5132
RH		 7832 break;
7833
7834#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7835 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7836 should be emitted or not. FIXME: Not implemented. */
7837 case 'Q':
252b5132
RH		 7838 break;
7839
7840 /* -V: SVR4 argument to print version ID. */
7841 case 'V':
7842 print_version_id ();
7843 break;
7844
a38cf1db
AM		 7845 /* -k: Ignore for FreeBSD compatibility. */
7846 case 'k':
252b5132 7847 break;
4cc782b5
ILT		 7848
7849 case 's':
7850 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7851 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7852 break;
99ad8390
NC		 7853#endif
7854#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 7855 case OPTION_64:
7856 {
7857 const char **list, **l;
7858
3e73aa7c
JH		 7859 list = bfd_target_list ();
7860 for (l = list; *l != NULL; l++)
8620418b 7861 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7862 || strcmp (*l, "coff-x86-64") == 0
7863 || strcmp (*l, "pe-x86-64") == 0
7864 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7865 {
7866 default_arch = "x86_64";
7867 break;
7868 }
3e73aa7c 7869 if (*l == NULL)
6e0b89ee 7870 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7871 free (list);
7872 }
7873 break;
7874#endif
252b5132 7875
6e0b89ee
AM		 7876 case OPTION_32:
7877 default_arch = "i386";
7878 break;
7879
b3b91714
AM		 7880 case OPTION_DIVIDE:
7881#ifdef SVR4_COMMENT_CHARS
7882 {
7883 char *n, *t;
7884 const char *s;
7885
7886 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7887 t = n;
7888 for (s = i386_comment_chars; *s != '\0'; s++)
7889 if (*s != '/')
7890 *t++ = *s;
7891 *t = '\0';
7892 i386_comment_chars = n;
7893 }
7894#endif
7895 break;
7896
9103f4f4 7897 case OPTION_MARCH:
6305a203
L		 7898 arch = xstrdup (arg);
7899 do
9103f4f4 7900 {
6305a203
L		 7901 if (*arch == '.')
7902 as_fatal (_("Invalid -march= option: `%s'"), arg);
7903 next = strchr (arch, '+');
7904 if (next)
7905 *next++ = '\0';
7906 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 7907 {
6305a203 7908 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 7909 {
6305a203
L		 7910 /* Processor. */
7911 cpu_arch_name = cpu_arch[i].name;
7912 cpu_sub_arch_name = NULL;
7913 cpu_arch_flags = cpu_arch[i].flags;
7914 cpu_arch_isa = cpu_arch[i].type;
7915 cpu_arch_isa_flags = cpu_arch[i].flags;
7916 if (!cpu_arch_tune_set)
7917 {
7918 cpu_arch_tune = cpu_arch_isa;
7919 cpu_arch_tune_flags = cpu_arch_isa_flags;
7920 }
7921 break;
7922 }
7923 else if (*cpu_arch [i].name == '.'
7924 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7925 {
7926 /* ISA entension. */
7927 i386_cpu_flags flags;
7928 flags = cpu_flags_or (cpu_arch_flags,
7929 cpu_arch[i].flags);
0dfbf9d7 7930 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 7931 {
7932 if (cpu_sub_arch_name)
7933 {
7934 char *name = cpu_sub_arch_name;
7935 cpu_sub_arch_name = concat (name,
7936 cpu_arch[i].name,
1bf57e9f 7937 (const char *) NULL);
6305a203
L		 7938 free (name);
7939 }
7940 else
7941 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7942 cpu_arch_flags = flags;
7943 }
7944 break;
ccc9c027 7945 }
9103f4f4 7946 }
6305a203
L		 7947
7948 if (i >= ARRAY_SIZE (cpu_arch))
7949 as_fatal (_("Invalid -march= option: `%s'"), arg);
7950
7951 arch = next;
9103f4f4 7952 }
6305a203 7953 while (next != NULL );
9103f4f4
L		 7954 break;
7955
7956 case OPTION_MTUNE:
7957 if (*arg == '.')
7958 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7959 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7960 {
7961 if (strcmp (arg, cpu_arch [i].name) == 0)
7962 {
ccc9c027 7963 cpu_arch_tune_set = 1;
9103f4f4
L		 7964 cpu_arch_tune = cpu_arch [i].type;
7965 cpu_arch_tune_flags = cpu_arch[i].flags;
7966 break;
7967 }
7968 }
7969 if (i >= ARRAY_SIZE (cpu_arch))
7970 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7971 break;
7972
1efbbeb4
L		 7973 case OPTION_MMNEMONIC:
7974 if (strcasecmp (arg, "att") == 0)
7975 intel_mnemonic = 0;
7976 else if (strcasecmp (arg, "intel") == 0)
7977 intel_mnemonic = 1;
7978 else
7979 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7980 break;
7981
7982 case OPTION_MSYNTAX:
7983 if (strcasecmp (arg, "att") == 0)
7984 intel_syntax = 0;
7985 else if (strcasecmp (arg, "intel") == 0)
7986 intel_syntax = 1;
7987 else
7988 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7989 break;
7990
7991 case OPTION_MINDEX_REG:
7992 allow_index_reg = 1;
7993 break;
7994
7995 case OPTION_MNAKED_REG:
7996 allow_naked_reg = 1;
7997 break;
7998
7999 case OPTION_MOLD_GCC:
8000 old_gcc = 1;
1efbbeb4
L		 8001 break;
8002
c0f3af97
L		 8003 case OPTION_MSSE2AVX:
8004 sse2avx = 1;
8005 break;
8006
252b5132
RH		 8007 default:
8008 return 0;
8009 }
8010 return 1;
8011}
8012
8013void
8014md_show_usage (stream)
8015 FILE *stream;
8016{
4cc782b5
ILT		 8017#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8018 fprintf (stream, _("\
a38cf1db
AM		 8019 -Q ignored\n\
8020 -V print assembler version number\n\
b3b91714
AM		 8021 -k ignored\n"));
8022#endif
8023 fprintf (stream, _("\
12b55ccc 8024 -n Do not optimize code alignment\n\
b3b91714
AM		 8025 -q quieten some warnings\n"));
8026#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8027 fprintf (stream, _("\
a38cf1db 8028 -s ignored\n"));
b3b91714 8029#endif
751d281c
L		 8030#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8031 fprintf (stream, _("\
8032 --32/--64 generate 32bit/64bit code\n"));
8033#endif
b3b91714
AM		 8034#ifdef SVR4_COMMENT_CHARS
8035 fprintf (stream, _("\
8036 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8037#else
8038 fprintf (stream, _("\
b3b91714 8039 --divide ignored\n"));
4cc782b5 8040#endif
9103f4f4 8041 fprintf (stream, _("\
6305a203
L		 8042 -march=CPU[,+EXTENSION...]\n\
8043 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 8044 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8045 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8046 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8047 generic32, generic64\n\
599121aa
L		 8048 EXTENSION is combination of:\n\
8049 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
594ab6a3 8050 avx, vmx, smx, xsave, aes, pclmul, fma, 3dnow,\n\
c0f3af97 8051 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
6305a203 8052 fprintf (stream, _("\
2cb4f3d5
L		 8053 -mtune=CPU optimize for CPU, CPU is one of:\n\
8054 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8055 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8056 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8057 generic32, generic64\n"));
ba104c83 8058 fprintf (stream, _("\
c0f3af97
L		 8059 -msse2avx encode SSE instructions with VEX prefix\n"));
8060 fprintf (stream, _("\
ba104c83
L		 8061 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8062 fprintf (stream, _("\
8063 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8064 fprintf (stream, _("\
8065 -mindex-reg support pseudo index registers\n"));
8066 fprintf (stream, _("\
8067 -mnaked-reg don't require `%%' prefix for registers\n"));
8068 fprintf (stream, _("\
8069 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8070}
8071
3e73aa7c 8072#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 8073 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 8074
8075/* Pick the target format to use. */
8076
47926f60 8077const char *
e3bb37b5 8078i386_target_format (void)
252b5132 8079{
3e73aa7c 8080 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8081 {
8082 set_code_flag (CODE_64BIT);
0dfbf9d7 8083 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8084 {
8085 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8086 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8087 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8088 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8089 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8090 cpu_arch_isa_flags.bitfield.cpui686 = 1;
8091 cpu_arch_isa_flags.bitfield.cpup4 = 1;
8092 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8093 cpu_arch_isa_flags.bitfield.cpusse = 1;
8094 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
8095 }
0dfbf9d7 8096 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8097 {
8098 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8099 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8100 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8101 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8102 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8103 cpu_arch_tune_flags.bitfield.cpui686 = 1;
8104 cpu_arch_tune_flags.bitfield.cpup4 = 1;
8105 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8106 cpu_arch_tune_flags.bitfield.cpusse = 1;
8107 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8108 }
9103f4f4 8109 }
3e73aa7c 8110 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8111 {
8112 set_code_flag (CODE_32BIT);
0dfbf9d7 8113 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8114 {
8115 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8116 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8117 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8118 }
0dfbf9d7 8119 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8120 {
8121 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8122 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8123 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8124 }
9103f4f4 8125 }
3e73aa7c
JH		 8126 else
8127 as_fatal (_("Unknown architecture"));
252b5132
RH		 8128 switch (OUTPUT_FLAVOR)
8129 {
872ce6ff
L		 8130#ifdef TE_PEP
8131 case bfd_target_coff_flavour:
8132 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
8133 break;
8134#endif
4c63da97
AM		 8135#ifdef OBJ_MAYBE_AOUT
8136 case bfd_target_aout_flavour:
47926f60 8137 return AOUT_TARGET_FORMAT;
4c63da97
AM		 8138#endif
8139#ifdef OBJ_MAYBE_COFF
252b5132
RH		 8140 case bfd_target_coff_flavour:
8141 return "coff-i386";
4c63da97 8142#endif
3e73aa7c 8143#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8144 case bfd_target_elf_flavour:
3e73aa7c 8145 {
e5cb08ac 8146 if (flag_code == CODE_64BIT)
4fa24527
JB		 8147 {
8148 object_64bit = 1;
8149 use_rela_relocations = 1;
8150 }
9d7cbccd 8151 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 8152 }
4c63da97 8153#endif
252b5132
RH		 8154 default:
8155 abort ();
8156 return NULL;
8157 }
8158}
8159
47926f60 8160#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8161
8162#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8163void
8164i386_elf_emit_arch_note (void)
a847613f 8165{
718ddfc0 8166 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8167 {
8168 char *p;
8169 asection *seg = now_seg;
8170 subsegT subseg = now_subseg;
8171 Elf_Internal_Note i_note;
8172 Elf_External_Note e_note;
8173 asection *note_secp;
8174 int len;
8175
8176 /* Create the .note section. */
8177 note_secp = subseg_new (".note", 0);
8178 bfd_set_section_flags (stdoutput,
8179 note_secp,
8180 SEC_HAS_CONTENTS | SEC_READONLY);
8181
8182 /* Process the arch string. */
8183 len = strlen (cpu_arch_name);
8184
8185 i_note.namesz = len + 1;
8186 i_note.descsz = 0;
8187 i_note.type = NT_ARCH;
8188 p = frag_more (sizeof (e_note.namesz));
8189 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8190 p = frag_more (sizeof (e_note.descsz));
8191 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8192 p = frag_more (sizeof (e_note.type));
8193 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8194 p = frag_more (len + 1);
8195 strcpy (p, cpu_arch_name);
8196
8197 frag_align (2, 0, 0);
8198
8199 subseg_set (seg, subseg);
8200 }
8201}
8202#endif
252b5132 8203\f
252b5132
RH		 8204symbolS *
8205md_undefined_symbol (name)
8206 char *name;
8207{
18dc2407
ILT		 8208 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8209 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8210 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8211 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8212 {
8213 if (!GOT_symbol)
8214 {
8215 if (symbol_find (name))
8216 as_bad (_("GOT already in symbol table"));
8217 GOT_symbol = symbol_new (name, undefined_section,
8218 (valueT) 0, &zero_address_frag);
8219 };
8220 return GOT_symbol;
8221 }
252b5132
RH		 8222 return 0;
8223}
8224
8225/* Round up a section size to the appropriate boundary. */
47926f60 8226
252b5132
RH		 8227valueT
8228md_section_align (segment, size)
ab9da554 8229 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8230 valueT size;
8231{
4c63da97
AM		 8232#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8233 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8234 {
8235 /* For a.out, force the section size to be aligned. If we don't do
8236 this, BFD will align it for us, but it will not write out the
8237 final bytes of the section. This may be a bug in BFD, but it is
8238 easier to fix it here since that is how the other a.out targets
8239 work. */
8240 int align;
8241
8242 align = bfd_get_section_alignment (stdoutput, segment);
8243 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8244 }
252b5132
RH		 8245#endif
8246
8247 return size;
8248}
8249
8250/* On the i386, PC-relative offsets are relative to the start of the
8251 next instruction. That is, the address of the offset, plus its
8252 size, since the offset is always the last part of the insn. */
8253
8254long
e3bb37b5 8255md_pcrel_from (fixS *fixP)
252b5132
RH		 8256{
8257 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8258}
8259
8260#ifndef I386COFF
8261
8262static void
e3bb37b5 8263s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8264{
29b0f896 8265 int temp;
252b5132 8266
8a75718c
JB		 8267#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8268 if (IS_ELF)
8269 obj_elf_section_change_hook ();
8270#endif
252b5132
RH		 8271 temp = get_absolute_expression ();
8272 subseg_set (bss_section, (subsegT) temp);
8273 demand_empty_rest_of_line ();
8274}
8275
8276#endif
8277
252b5132 8278void
e3bb37b5 8279i386_validate_fix (fixS *fixp)
252b5132
RH		 8280{
8281 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8282 {
23df1078
JH		 8283 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8284 {
4fa24527 8285 if (!object_64bit)
23df1078
JH		 8286 abort ();
8287 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8288 }
8289 else
8290 {
4fa24527 8291 if (!object_64bit)
d6ab8113
JB		 8292 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8293 else
8294 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8295 }
252b5132
RH		 8296 fixp->fx_subsy = 0;
8297 }
8298}
8299
252b5132
RH		 8300arelent *
8301tc_gen_reloc (section, fixp)
ab9da554 8302 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8303 fixS *fixp;
8304{
8305 arelent *rel;
8306 bfd_reloc_code_real_type code;
8307
8308 switch (fixp->fx_r_type)
8309 {
3e73aa7c
JH		 8310 case BFD_RELOC_X86_64_PLT32:
8311 case BFD_RELOC_X86_64_GOT32:
8312 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8313 case BFD_RELOC_386_PLT32:
8314 case BFD_RELOC_386_GOT32:
8315 case BFD_RELOC_386_GOTOFF:
8316 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8317 case BFD_RELOC_386_TLS_GD:
8318 case BFD_RELOC_386_TLS_LDM:
8319 case BFD_RELOC_386_TLS_LDO_32:
8320 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8321 case BFD_RELOC_386_TLS_IE:
8322 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8323 case BFD_RELOC_386_TLS_LE_32:
8324 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8325 case BFD_RELOC_386_TLS_GOTDESC:
8326 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8327 case BFD_RELOC_X86_64_TLSGD:
8328 case BFD_RELOC_X86_64_TLSLD:
8329 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8330 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8331 case BFD_RELOC_X86_64_GOTTPOFF:
8332 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8333 case BFD_RELOC_X86_64_TPOFF64:
8334 case BFD_RELOC_X86_64_GOTOFF64:
8335 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8336 case BFD_RELOC_X86_64_GOT64:
8337 case BFD_RELOC_X86_64_GOTPCREL64:
8338 case BFD_RELOC_X86_64_GOTPC64:
8339 case BFD_RELOC_X86_64_GOTPLT64:
8340 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8341 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8342 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8343 case BFD_RELOC_RVA:
8344 case BFD_RELOC_VTABLE_ENTRY:
8345 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8346#ifdef TE_PE
8347 case BFD_RELOC_32_SECREL:
8348#endif
252b5132
RH		 8349 code = fixp->fx_r_type;
8350 break;
dbbaec26
L		 8351 case BFD_RELOC_X86_64_32S:
8352 if (!fixp->fx_pcrel)
8353 {
8354 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8355 code = fixp->fx_r_type;
8356 break;
8357 }
252b5132 8358 default:
93382f6d 8359 if (fixp->fx_pcrel)
252b5132 8360 {
93382f6d
AM		 8361 switch (fixp->fx_size)
8362 {
8363 default:
b091f402
AM		 8364 as_bad_where (fixp->fx_file, fixp->fx_line,
8365 _("can not do %d byte pc-relative relocation"),
8366 fixp->fx_size);
93382f6d
AM		 8367 code = BFD_RELOC_32_PCREL;
8368 break;
8369 case 1: code = BFD_RELOC_8_PCREL; break;
8370 case 2: code = BFD_RELOC_16_PCREL; break;
8371 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8372#ifdef BFD64
8373 case 8: code = BFD_RELOC_64_PCREL; break;
8374#endif
93382f6d
AM		 8375 }
8376 }
8377 else
8378 {
8379 switch (fixp->fx_size)
8380 {
8381 default:
b091f402
AM		 8382 as_bad_where (fixp->fx_file, fixp->fx_line,
8383 _("can not do %d byte relocation"),
8384 fixp->fx_size);
93382f6d
AM		 8385 code = BFD_RELOC_32;
8386 break;
8387 case 1: code = BFD_RELOC_8; break;
8388 case 2: code = BFD_RELOC_16; break;
8389 case 4: code = BFD_RELOC_32; break;
937149dd 8390#ifdef BFD64
3e73aa7c 8391 case 8: code = BFD_RELOC_64; break;
937149dd 8392#endif
93382f6d 8393 }
252b5132
RH		 8394 }
8395 break;
8396 }
252b5132 8397
d182319b
JB		 8398 if ((code == BFD_RELOC_32
8399 || code == BFD_RELOC_32_PCREL
8400 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8401 && GOT_symbol
8402 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8403 {
4fa24527 8404 if (!object_64bit)
d6ab8113
JB		 8405 code = BFD_RELOC_386_GOTPC;
8406 else
8407 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8408 }
7b81dfbb
AJ		 8409 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8410 && GOT_symbol
8411 && fixp->fx_addsy == GOT_symbol)
8412 {
8413 code = BFD_RELOC_X86_64_GOTPC64;
8414 }
252b5132
RH		 8415
8416 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8417 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8418 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8419
8420 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8421
3e73aa7c
JH		 8422 if (!use_rela_relocations)
8423 {
8424 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8425 vtable entry to be used in the relocation's section offset. */
8426 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8427 rel->address = fixp->fx_offset;
252b5132 8428
c6682705 8429 rel->addend = 0;
3e73aa7c
JH		 8430 }
8431 /* Use the rela in 64bit mode. */
252b5132 8432 else
3e73aa7c 8433 {
062cd5e7
AS		 8434 if (!fixp->fx_pcrel)
8435 rel->addend = fixp->fx_offset;
8436 else
8437 switch (code)
8438 {
8439 case BFD_RELOC_X86_64_PLT32:
8440 case BFD_RELOC_X86_64_GOT32:
8441 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8442 case BFD_RELOC_X86_64_TLSGD:
8443 case BFD_RELOC_X86_64_TLSLD:
8444 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8445 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8446 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8447 rel->addend = fixp->fx_offset - fixp->fx_size;
8448 break;
8449 default:
8450 rel->addend = (section->vma
8451 - fixp->fx_size
8452 + fixp->fx_addnumber
8453 + md_pcrel_from (fixp));
8454 break;
8455 }
3e73aa7c
JH		 8456 }
8457
252b5132
RH		 8458 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8459 if (rel->howto == NULL)
8460 {
8461 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8462 _("cannot represent relocation type %s"),
252b5132
RH		 8463 bfd_get_reloc_code_name (code));
8464 /* Set howto to a garbage value so that we can keep going. */
8465 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
8466 assert (rel->howto != NULL);
8467 }
8468
8469 return rel;
8470}
8471
64a0c779
DN		 8472\f
8473/* Parse operands using Intel syntax. This implements a recursive descent
8474 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8475 Programmer's Guide.
8476
8477 FIXME: We do not recognize the full operand grammar defined in the MASM
8478 documentation. In particular, all the structure/union and
8479 high-level macro operands are missing.
8480
8481 Uppercase words are terminals, lower case words are non-terminals.
8482 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8483 bars '|' denote choices. Most grammar productions are implemented in
8484 functions called 'intel_<production>'.
8485
8486 Initial production is 'expr'.
8487
9306ca4a 8488 addOp + | -
64a0c779
DN		 8489
8490 alpha [a-zA-Z]
8491
9306ca4a
JB		 8492 binOp & | AND | \| | OR | ^ | XOR
8493
64a0c779
DN		 8494 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8495
8496 constant digits [[ radixOverride ]]
8497
c0f3af97 8498 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
64a0c779
DN		 8499
8500 digits decdigit
b77a7acd
AJ		 8501 | digits decdigit
8502 | digits hexdigit
64a0c779
DN		 8503
8504 decdigit [0-9]
8505
9306ca4a
JB		 8506 e04 e04 addOp e05
8507 | e05
8508
8509 e05 e05 binOp e06
b77a7acd 8510 | e06
64a0c779
DN		 8511
8512 e06 e06 mulOp e09
b77a7acd 8513 | e09
64a0c779
DN		 8514
8515 e09 OFFSET e10
a724f0f4
JB		 8516 | SHORT e10
8517 | + e10
8518 | - e10
9306ca4a
JB		 8519 | ~ e10
8520 | NOT e10
64a0c779
DN		 8521 | e09 PTR e10
8522 | e09 : e10
8523 | e10
8524
8525 e10 e10 [ expr ]
b77a7acd 8526 | e11
64a0c779
DN		 8527
8528 e11 ( expr )
b77a7acd 8529 | [ expr ]
64a0c779
DN		 8530 | constant
8531 | dataType
8532 | id
8533 | $
8534 | register
8535
a724f0f4 8536 => expr expr cmpOp e04
9306ca4a 8537 | e04
64a0c779
DN		 8538
8539 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 8540 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 8541
8542 hexdigit a | b | c | d | e | f
b77a7acd 8543 | A | B | C | D | E | F
64a0c779
DN		 8544
8545 id alpha
b77a7acd 8546 | id alpha
64a0c779
DN		 8547 | id decdigit
8548
9306ca4a 8549 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 8550
8551 quote " | '
8552
8553 register specialRegister
b77a7acd 8554 | gpRegister
64a0c779
DN		 8555 | byteRegister
8556
8557 segmentRegister CS | DS | ES | FS | GS | SS
8558
9306ca4a 8559 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 8560 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 8561 | TR3 | TR4 | TR5 | TR6 | TR7
8562
64a0c779
DN		 8563 We simplify the grammar in obvious places (e.g., register parsing is
8564 done by calling parse_register) and eliminate immediate left recursion
8565 to implement a recursive-descent parser.
8566
a724f0f4
JB		 8567 expr e04 expr'
8568
8569 expr' cmpOp e04 expr'
8570 | Empty
9306ca4a
JB		 8571
8572 e04 e05 e04'
8573
8574 e04' addOp e05 e04'
8575 | Empty
64a0c779
DN		 8576
8577 e05 e06 e05'
8578
9306ca4a 8579 e05' binOp e06 e05'
b77a7acd 8580 | Empty
64a0c779
DN		 8581
8582 e06 e09 e06'
8583
8584 e06' mulOp e09 e06'
b77a7acd 8585 | Empty
64a0c779
DN		 8586
8587 e09 OFFSET e10 e09'
a724f0f4
JB		 8588 | SHORT e10'
8589 | + e10'
8590 | - e10'
8591 | ~ e10'
8592 | NOT e10'
b77a7acd 8593 | e10 e09'
64a0c779
DN		 8594
8595 e09' PTR e10 e09'
b77a7acd 8596 | : e10 e09'
64a0c779
DN		 8597 | Empty
8598
8599 e10 e11 e10'
8600
8601 e10' [ expr ] e10'
b77a7acd 8602 | Empty
64a0c779
DN		 8603
8604 e11 ( expr )
b77a7acd 8605 | [ expr ]
64a0c779
DN		 8606 | BYTE
8607 | WORD
8608 | DWORD
9306ca4a 8609 | FWORD
64a0c779 8610 | QWORD
9306ca4a
JB		 8611 | TBYTE
8612 | OWORD
8613 | XMMWORD
c0f3af97 8614 | YMMWORD
64a0c779
DN		 8615 | .
8616 | $
8617 | register
8618 | id
8619 | constant */
8620
8621/* Parsing structure for the intel syntax parser. Used to implement the
8622 semantic actions for the operand grammar. */
8623struct intel_parser_s
8624 {
8625 char *op_string; /* The string being parsed. */
8626 int got_a_float; /* Whether the operand is a float. */
4a1805b1 8627 int op_modifier; /* Operand modifier. */
64a0c779 8628 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 8629 int in_offset; /* >=1 if parsing operand of offset. */
8630 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 8631 const reg_entry *reg; /* Last register reference found. */
8632 char *disp; /* Displacement string being built. */
a724f0f4 8633 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 8634 };
8635
8636static struct intel_parser_s intel_parser;
8637
8638/* Token structure for parsing intel syntax. */
8639struct intel_token
8640 {
8641 int code; /* Token code. */
8642 const reg_entry *reg; /* Register entry for register tokens. */
8643 char *str; /* String representation. */
8644 };
8645
8646static struct intel_token cur_token, prev_token;
8647
50705ef4
AM		 8648/* Token codes for the intel parser. Since T_SHORT is already used
8649 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 8650#define T_NIL -1
8651#define T_CONST 1
8652#define T_REG 2
8653#define T_BYTE 3
8654#define T_WORD 4
9306ca4a
JB		 8655#define T_DWORD 5
8656#define T_FWORD 6
8657#define T_QWORD 7
8658#define T_TBYTE 8
8659#define T_XMMWORD 9
50705ef4 8660#undef T_SHORT
9306ca4a
JB		 8661#define T_SHORT 10
8662#define T_OFFSET 11
8663#define T_PTR 12
8664#define T_ID 13
8665#define T_SHL 14
8666#define T_SHR 15
c0f3af97 8667#define T_YMMWORD 16
64a0c779
DN		 8668
8669/* Prototypes for intel parser functions. */
e3bb37b5
L		 8670static int intel_match_token (int);
8671static void intel_putback_token (void);
8672static void intel_get_token (void);
8673static int intel_expr (void);
8674static int intel_e04 (void);
8675static int intel_e05 (void);
8676static int intel_e06 (void);
8677static int intel_e09 (void);
8678static int intel_e10 (void);
8679static int intel_e11 (void);
64a0c779 8680
64a0c779 8681static int
e3bb37b5 8682i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 8683{
8684 int ret;
8685 char *p;
8686
a724f0f4
JB		 8687 p = intel_parser.op_string = xstrdup (operand_string);
8688 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8689
8690 for (;;)
64a0c779 8691 {
a724f0f4
JB		 8692 /* Initialize token holders. */
8693 cur_token.code = prev_token.code = T_NIL;
8694 cur_token.reg = prev_token.reg = NULL;
8695 cur_token.str = prev_token.str = NULL;
8696
8697 /* Initialize parser structure. */
8698 intel_parser.got_a_float = got_a_float;
8699 intel_parser.op_modifier = 0;
8700 intel_parser.is_mem = 0;
8701 intel_parser.in_offset = 0;
8702 intel_parser.in_bracket = 0;
8703 intel_parser.reg = NULL;
8704 intel_parser.disp[0] = '\0';
8705 intel_parser.next_operand = NULL;
8706
8707 /* Read the first token and start the parser. */
8708 intel_get_token ();
8709 ret = intel_expr ();
8710
8711 if (!ret)
8712 break;
8713
9306ca4a
JB		 8714 if (cur_token.code != T_NIL)
8715 {
8716 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8717 current_templates->start->name, cur_token.str);
8718 ret = 0;
8719 }
64a0c779
DN		 8720 /* If we found a memory reference, hand it over to i386_displacement
8721 to fill in the rest of the operand fields. */
9306ca4a 8722 else if (intel_parser.is_mem)
64a0c779
DN		 8723 {
8724 if ((i.mem_operands == 1
40fb9820 8725 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 8726 || i.mem_operands == 2)
8727 {
8728 as_bad (_("too many memory references for '%s'"),
8729 current_templates->start->name);
8730 ret = 0;
8731 }
8732 else
8733 {
8734 char *s = intel_parser.disp;
5c07affc 8735 i.types[this_operand].bitfield.mem = 1;
64a0c779
DN		 8736 i.mem_operands++;
8737
a724f0f4
JB		 8738 if (!quiet_warnings && intel_parser.is_mem < 0)
8739 /* See the comments in intel_bracket_expr. */
8740 as_warn (_("Treating `%s' as memory reference"), operand_string);
8741
64a0c779
DN		 8742 /* Add the displacement expression. */
8743 if (*s != '\0')
a4622f40
AM		 8744 ret = i386_displacement (s, s + strlen (s));
8745 if (ret)
a724f0f4
JB		 8746 {
8747 /* Swap base and index in 16-bit memory operands like
8748 [si+bx]. Since i386_index_check is also used in AT&T
8749 mode we have to do that here. */
8750 if (i.base_reg
8751 && i.index_reg
40fb9820
L		 8752 && i.base_reg->reg_type.bitfield.reg16
8753 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 8754 && i.base_reg->reg_num >= 6
8755 && i.index_reg->reg_num < 6)
8756 {
8757 const reg_entry *base = i.index_reg;
8758
8759 i.index_reg = i.base_reg;
8760 i.base_reg = base;
8761 }
8762 ret = i386_index_check (operand_string);
8763 }
64a0c779
DN		 8764 }
8765 }
8766
8767 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 8768 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779 8769 || intel_parser.reg == NULL)
b7240065
JB		 8770 {
8771 if (i.mem_operands < 2 && i.seg[i.mem_operands])
8772 {
8773 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8774 as_warn (_("Segment override ignored"));
8775 i.seg[i.mem_operands] = NULL;
8776 }
8777 ret = i386_immediate (intel_parser.disp);
8778 }
a724f0f4
JB		 8779
8780 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 8781 ret = 0;
a724f0f4
JB		 8782 if (!ret || !intel_parser.next_operand)
8783 break;
8784 intel_parser.op_string = intel_parser.next_operand;
8785 this_operand = i.operands++;
7d5e4556 8786 i.types[this_operand].bitfield.unspecified = 1;
64a0c779
DN		 8787 }
8788
8789 free (p);
8790 free (intel_parser.disp);
8791
8792 return ret;
8793}
8794
a724f0f4
JB		 8795#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8796
8797/* expr e04 expr'
8798
8799 expr' cmpOp e04 expr'
8800 | Empty */
64a0c779 8801static int
e3bb37b5 8802intel_expr (void)
64a0c779 8803{
a724f0f4
JB		 8804 /* XXX Implement the comparison operators. */
8805 return intel_e04 ();
9306ca4a
JB		 8806}
8807
a724f0f4 8808/* e04 e05 e04'
9306ca4a 8809
a724f0f4 8810 e04' addOp e05 e04'
9306ca4a
JB		 8811 | Empty */
8812static int
e3bb37b5 8813intel_e04 (void)
9306ca4a 8814{
a724f0f4 8815 int nregs = -1;
9306ca4a 8816
a724f0f4 8817 for (;;)
9306ca4a 8818 {
a724f0f4
JB		 8819 if (!intel_e05())
8820 return 0;
9306ca4a 8821
a724f0f4
JB		 8822 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8823 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 8824
a724f0f4
JB		 8825 if (cur_token.code == '+')
8826 nregs = -1;
8827 else if (cur_token.code == '-')
8828 nregs = NUM_ADDRESS_REGS;
8829 else
8830 return 1;
64a0c779 8831
a724f0f4
JB		 8832 strcat (intel_parser.disp, cur_token.str);
8833 intel_match_token (cur_token.code);
8834 }
64a0c779
DN		 8835}
8836
64a0c779
DN		 8837/* e05 e06 e05'
8838
9306ca4a 8839 e05' binOp e06 e05'
64a0c779
DN		 8840 | Empty */
8841static int
e3bb37b5 8842intel_e05 (void)
64a0c779 8843{
a724f0f4 8844 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8845
a724f0f4 8846 for (;;)
64a0c779 8847 {
a724f0f4
JB		 8848 if (!intel_e06())
8849 return 0;
8850
4eed87de
AM		 8851 if (cur_token.code == '&'
8852 || cur_token.code == '|'
8853 || cur_token.code == '^')
a724f0f4
JB		 8854 {
8855 char str[2];
8856
8857 str[0] = cur_token.code;
8858 str[1] = 0;
8859 strcat (intel_parser.disp, str);
8860 }
8861 else
8862 break;
9306ca4a 8863
64a0c779
DN		 8864 intel_match_token (cur_token.code);
8865
a724f0f4
JB		 8866 if (nregs < 0)
8867 nregs = ~nregs;
64a0c779 8868 }
a724f0f4
JB		 8869 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8870 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8871 return 1;
4a1805b1 8872}
64a0c779
DN		 8873
8874/* e06 e09 e06'
8875
8876 e06' mulOp e09 e06'
b77a7acd 8877 | Empty */
64a0c779 8878static int
e3bb37b5 8879intel_e06 (void)
64a0c779 8880{
a724f0f4 8881 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8882
a724f0f4 8883 for (;;)
64a0c779 8884 {
a724f0f4
JB		 8885 if (!intel_e09())
8886 return 0;
9306ca4a 8887
4eed87de
AM		 8888 if (cur_token.code == '*'
8889 || cur_token.code == '/'
8890 || cur_token.code == '%')
a724f0f4
JB		 8891 {
8892 char str[2];
9306ca4a 8893
a724f0f4
JB		 8894 str[0] = cur_token.code;
8895 str[1] = 0;
8896 strcat (intel_parser.disp, str);
8897 }
8898 else if (cur_token.code == T_SHL)
8899 strcat (intel_parser.disp, "<<");
8900 else if (cur_token.code == T_SHR)
8901 strcat (intel_parser.disp, ">>");
8902 else
8903 break;
9306ca4a 8904
64e74474 8905 intel_match_token (cur_token.code);
64a0c779 8906
a724f0f4
JB		 8907 if (nregs < 0)
8908 nregs = ~nregs;
64a0c779 8909 }
a724f0f4
JB		 8910 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8911 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8912 return 1;
64a0c779
DN		 8913}
8914
a724f0f4
JB		 8915/* e09 OFFSET e09
8916 | SHORT e09
8917 | + e09
8918 | - e09
8919 | ~ e09
8920 | NOT e09
9306ca4a
JB		 8921 | e10 e09'
8922
64a0c779 8923 e09' PTR e10 e09'
b77a7acd 8924 | : e10 e09'
64a0c779
DN		 8925 | Empty */
8926static int
e3bb37b5 8927intel_e09 (void)
64a0c779 8928{
a724f0f4
JB		 8929 int nregs = ~NUM_ADDRESS_REGS;
8930 int in_offset = 0;
8931
8932 for (;;)
64a0c779 8933 {
a724f0f4
JB		 8934 /* Don't consume constants here. */
8935 if (cur_token.code == '+' || cur_token.code == '-')
8936 {
8937 /* Need to look one token ahead - if the next token
8938 is a constant, the current token is its sign. */
8939 int next_code;
8940
8941 intel_match_token (cur_token.code);
8942 next_code = cur_token.code;
8943 intel_putback_token ();
8944 if (next_code == T_CONST)
8945 break;
8946 }
8947
8948 /* e09 OFFSET e09 */
8949 if (cur_token.code == T_OFFSET)
8950 {
8951 if (!in_offset++)
8952 ++intel_parser.in_offset;
8953 }
8954
8955 /* e09 SHORT e09 */
8956 else if (cur_token.code == T_SHORT)
8957 intel_parser.op_modifier |= 1 << T_SHORT;
8958
8959 /* e09 + e09 */
8960 else if (cur_token.code == '+')
8961 strcat (intel_parser.disp, "+");
8962
8963 /* e09 - e09
8964 | ~ e09
8965 | NOT e09 */
8966 else if (cur_token.code == '-' || cur_token.code == '~')
8967 {
8968 char str[2];
64a0c779 8969
a724f0f4
JB		 8970 if (nregs < 0)
8971 nregs = ~nregs;
8972 str[0] = cur_token.code;
8973 str[1] = 0;
8974 strcat (intel_parser.disp, str);
8975 }
8976
8977 /* e09 e10 e09' */
8978 else
8979 break;
8980
8981 intel_match_token (cur_token.code);
64a0c779
DN		 8982 }
8983
a724f0f4 8984 for (;;)
9306ca4a 8985 {
a724f0f4
JB		 8986 if (!intel_e10 ())
8987 return 0;
9306ca4a 8988
a724f0f4
JB		 8989 /* e09' PTR e10 e09' */
8990 if (cur_token.code == T_PTR)
8991 {
8992 char suffix;
9306ca4a 8993
a724f0f4 8994 if (prev_token.code == T_BYTE)
7d5e4556
L		 8995 {
8996 suffix = BYTE_MNEM_SUFFIX;
8997 i.types[this_operand].bitfield.byte = 1;
8998 }
9306ca4a 8999
a724f0f4
JB		 9000 else if (prev_token.code == T_WORD)
9001 {
34b772a6
JB		 9002 if ((current_templates->start->name[0] == 'l'
9003 && current_templates->start->name[2] == 's'
9004 && current_templates->start->name[3] == 0)
9005 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9006 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9007 else if (intel_parser.got_a_float == 2) /* "fi..." */
9008 suffix = SHORT_MNEM_SUFFIX;
9009 else
9010 suffix = WORD_MNEM_SUFFIX;
7d5e4556 9011 i.types[this_operand].bitfield.word = 1;
a724f0f4 9012 }
64a0c779 9013
a724f0f4
JB		 9014 else if (prev_token.code == T_DWORD)
9015 {
34b772a6
JB		 9016 if ((current_templates->start->name[0] == 'l'
9017 && current_templates->start->name[2] == 's'
9018 && current_templates->start->name[3] == 0)
9019 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9020 suffix = WORD_MNEM_SUFFIX;
9021 else if (flag_code == CODE_16BIT
40fb9820
L		 9022 && (current_templates->start->opcode_modifier.jump
9023 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 9024 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9025 else if (intel_parser.got_a_float == 1) /* "f..." */
9026 suffix = SHORT_MNEM_SUFFIX;
9027 else
9028 suffix = LONG_MNEM_SUFFIX;
7d5e4556 9029 i.types[this_operand].bitfield.dword = 1;
a724f0f4 9030 }
9306ca4a 9031
a724f0f4
JB		 9032 else if (prev_token.code == T_FWORD)
9033 {
9034 if (current_templates->start->name[0] == 'l'
9035 && current_templates->start->name[2] == 's'
9036 && current_templates->start->name[3] == 0)
9037 suffix = LONG_MNEM_SUFFIX;
9038 else if (!intel_parser.got_a_float)
9039 {
9040 if (flag_code == CODE_16BIT)
9041 add_prefix (DATA_PREFIX_OPCODE);
9042 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9043 }
9044 else
9045 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7d5e4556 9046 i.types[this_operand].bitfield.fword = 1;
a724f0f4 9047 }
64a0c779 9048
a724f0f4
JB		 9049 else if (prev_token.code == T_QWORD)
9050 {
34b772a6
JB		 9051 if (current_templates->start->base_opcode == 0x62 /* bound */
9052 || intel_parser.got_a_float == 1) /* "f..." */
a724f0f4
JB		 9053 suffix = LONG_MNEM_SUFFIX;
9054 else
34b772a6 9055 suffix = QWORD_MNEM_SUFFIX;
7d5e4556 9056 i.types[this_operand].bitfield.qword = 1;
a724f0f4 9057 }
64a0c779 9058
a724f0f4
JB		 9059 else if (prev_token.code == T_TBYTE)
9060 {
9061 if (intel_parser.got_a_float == 1)
9062 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9063 else
9064 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9065 }
9306ca4a 9066
a724f0f4 9067 else if (prev_token.code == T_XMMWORD)
9306ca4a 9068 {
582d5edd 9069 suffix = XMMWORD_MNEM_SUFFIX;
7d5e4556 9070 i.types[this_operand].bitfield.xmmword = 1;
9306ca4a 9071 }
64a0c779 9072
c0f3af97
L		 9073 else if (prev_token.code == T_YMMWORD)
9074 {
9075 suffix = YMMWORD_MNEM_SUFFIX;
9076 i.types[this_operand].bitfield.ymmword = 1;
9077 }
9078
f16b83df 9079 else
a724f0f4
JB		 9080 {
9081 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
9082 return 0;
9083 }
9084
7d5e4556
L		 9085 i.types[this_operand].bitfield.unspecified = 0;
9086
435acd52
JB		 9087 /* Operands for jump/call using 'ptr' notation denote absolute
9088 addresses. */
40fb9820
L		 9089 if (current_templates->start->opcode_modifier.jump
9090 || current_templates->start->opcode_modifier.jumpdword)
9091 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9092
a724f0f4
JB		 9093 if (current_templates->start->base_opcode == 0x8d /* lea */)
9094 ;
9095 else if (!i.suffix)
9096 i.suffix = suffix;
9097 else if (i.suffix != suffix)
9098 {
9099 as_bad (_("Conflicting operand modifiers"));
9100 return 0;
9101 }
64a0c779 9102
9306ca4a
JB		 9103 }
9104
a724f0f4
JB		 9105 /* e09' : e10 e09' */
9106 else if (cur_token.code == ':')
9306ca4a 9107 {
a724f0f4
JB		 9108 if (prev_token.code != T_REG)
9109 {
9110 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9111 segment/group identifier (which we don't have), using comma
9112 as the operand separator there is even less consistent, since
9113 there all branches only have a single operand. */
9114 if (this_operand != 0
9115 || intel_parser.in_offset
9116 || intel_parser.in_bracket
40fb9820
L		 9117 || (!current_templates->start->opcode_modifier.jump
9118 && !current_templates->start->opcode_modifier.jumpdword
9119 && !current_templates->start->opcode_modifier.jumpintersegment
9120 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 9121 return intel_match_token (T_NIL);
9122 /* Remember the start of the 2nd operand and terminate 1st
9123 operand here.
9124 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9125 another expression), but it gets at least the simplest case
9126 (a plain number or symbol on the left side) right. */
9127 intel_parser.next_operand = intel_parser.op_string;
9128 *--intel_parser.op_string = '\0';
9129 return intel_match_token (':');
9130 }
9306ca4a 9131 }
64a0c779 9132
a724f0f4 9133 /* e09' Empty */
64a0c779 9134 else
a724f0f4 9135 break;
64a0c779 9136
a724f0f4
JB		 9137 intel_match_token (cur_token.code);
9138
9139 }
9140
9141 if (in_offset)
9142 {
9143 --intel_parser.in_offset;
9144 if (nregs < 0)
9145 nregs = ~nregs;
9146 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 9147 {
a724f0f4 9148 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 9149 return 0;
9150 }
a724f0f4
JB		 9151 intel_parser.op_modifier |= 1 << T_OFFSET;
9152 }
9306ca4a 9153
a724f0f4
JB		 9154 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9155 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
9156 return 1;
9157}
64a0c779 9158
a724f0f4 9159static int
e3bb37b5 9160intel_bracket_expr (void)
a724f0f4
JB		 9161{
9162 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
9163 const char *start = intel_parser.op_string;
9164 int len;
9165
9166 if (i.op[this_operand].regs)
9167 return intel_match_token (T_NIL);
9168
9169 intel_match_token ('[');
9170
9171 /* Mark as a memory operand only if it's not already known to be an
9172 offset expression. If it's an offset expression, we need to keep
9173 the brace in. */
9174 if (!intel_parser.in_offset)
9175 {
9176 ++intel_parser.in_bracket;
435acd52
JB		 9177
9178 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 9179 if (current_templates->start->opcode_modifier.jump
9180 || current_templates->start->opcode_modifier.jumpdword)
9181 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9182
a724f0f4
JB		 9183 /* Unfortunately gas always diverged from MASM in a respect that can't
9184 be easily fixed without risking to break code sequences likely to be
9185 encountered (the testsuite even check for this): MASM doesn't consider
9186 an expression inside brackets unconditionally as a memory reference.
9187 When that is e.g. a constant, an offset expression, or the sum of the
9188 two, this is still taken as a constant load. gas, however, always
9189 treated these as memory references. As a compromise, we'll try to make
9190 offset expressions inside brackets work the MASM way (since that's
9191 less likely to be found in real world code), but make constants alone
9192 continue to work the traditional gas way. In either case, issue a
9193 warning. */
9194 intel_parser.op_modifier &= ~was_offset;
64a0c779 9195 }
a724f0f4 9196 else
64e74474 9197 strcat (intel_parser.disp, "[");
a724f0f4
JB		 9198
9199 /* Add a '+' to the displacement string if necessary. */
9200 if (*intel_parser.disp != '\0'
9201 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
9202 strcat (intel_parser.disp, "+");
64a0c779 9203
a724f0f4
JB		 9204 if (intel_expr ()
9205 && (len = intel_parser.op_string - start - 1,
9206 intel_match_token (']')))
64a0c779 9207 {
a724f0f4
JB		 9208 /* Preserve brackets when the operand is an offset expression. */
9209 if (intel_parser.in_offset)
9210 strcat (intel_parser.disp, "]");
9211 else
9212 {
9213 --intel_parser.in_bracket;
9214 if (i.base_reg || i.index_reg)
9215 intel_parser.is_mem = 1;
9216 if (!intel_parser.is_mem)
9217 {
9218 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
9219 /* Defer the warning until all of the operand was parsed. */
9220 intel_parser.is_mem = -1;
9221 else if (!quiet_warnings)
4eed87de
AM		 9222 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9223 len, start, len, start);
a724f0f4
JB		 9224 }
9225 }
9226 intel_parser.op_modifier |= was_offset;
64a0c779 9227
a724f0f4 9228 return 1;
64a0c779 9229 }
a724f0f4 9230 return 0;
64a0c779
DN		 9231}
9232
9233/* e10 e11 e10'
9234
9235 e10' [ expr ] e10'
b77a7acd 9236 | Empty */
64a0c779 9237static int
e3bb37b5 9238intel_e10 (void)
64a0c779 9239{
a724f0f4
JB		 9240 if (!intel_e11 ())
9241 return 0;
64a0c779 9242
a724f0f4 9243 while (cur_token.code == '[')
64a0c779 9244 {
a724f0f4 9245 if (!intel_bracket_expr ())
21d6c4af 9246 return 0;
64a0c779
DN		 9247 }
9248
a724f0f4 9249 return 1;
64a0c779
DN		 9250}
9251
64a0c779 9252/* e11 ( expr )
b77a7acd 9253 | [ expr ]
64a0c779
DN		 9254 | BYTE
9255 | WORD
9256 | DWORD
9306ca4a 9257 | FWORD
64a0c779 9258 | QWORD
9306ca4a
JB		 9259 | TBYTE
9260 | OWORD
9261 | XMMWORD
c0f3af97 9262 | YMMWORD
4a1805b1 9263 | $
64a0c779
DN		 9264 | .
9265 | register
9266 | id
9267 | constant */
9268static int
e3bb37b5 9269intel_e11 (void)
64a0c779 9270{
a724f0f4 9271 switch (cur_token.code)
64a0c779 9272 {
a724f0f4
JB		 9273 /* e11 ( expr ) */
9274 case '(':
64a0c779
DN		 9275 intel_match_token ('(');
9276 strcat (intel_parser.disp, "(");
9277
9278 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 9279 {
9280 strcat (intel_parser.disp, ")");
9281 return 1;
9282 }
a724f0f4 9283 return 0;
4a1805b1 9284
a724f0f4
JB		 9285 /* e11 [ expr ] */
9286 case '[':
a724f0f4 9287 return intel_bracket_expr ();
64a0c779 9288
a724f0f4
JB		 9289 /* e11 $
9290 | . */
9291 case '.':
64a0c779
DN		 9292 strcat (intel_parser.disp, cur_token.str);
9293 intel_match_token (cur_token.code);
21d6c4af
DN		 9294
9295 /* Mark as a memory operand only if it's not already known to be an
9296 offset expression. */
a724f0f4 9297 if (!intel_parser.in_offset)
21d6c4af 9298 intel_parser.is_mem = 1;
64a0c779
DN		 9299
9300 return 1;
64a0c779 9301
a724f0f4
JB		 9302 /* e11 register */
9303 case T_REG:
9304 {
9305 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 9306
a724f0f4 9307 intel_match_token (T_REG);
64a0c779 9308
a724f0f4
JB		 9309 /* Check for segment change. */
9310 if (cur_token.code == ':')
9311 {
40fb9820
L		 9312 if (!reg->reg_type.bitfield.sreg2
9313 && !reg->reg_type.bitfield.sreg3)
a724f0f4 9314 {
4eed87de
AM		 9315 as_bad (_("`%s' is not a valid segment register"),
9316 reg->reg_name);
a724f0f4
JB		 9317 return 0;
9318 }
b7240065
JB		 9319 else if (i.mem_operands >= 2)
9320 as_warn (_("Segment override ignored"));
a724f0f4
JB		 9321 else if (i.seg[i.mem_operands])
9322 as_warn (_("Extra segment override ignored"));
9323 else
9324 {
9325 if (!intel_parser.in_offset)
9326 intel_parser.is_mem = 1;
9327 switch (reg->reg_num)
9328 {
9329 case 0:
9330 i.seg[i.mem_operands] = &es;
9331 break;
9332 case 1:
9333 i.seg[i.mem_operands] = &cs;
9334 break;
9335 case 2:
9336 i.seg[i.mem_operands] = &ss;
9337 break;
9338 case 3:
9339 i.seg[i.mem_operands] = &ds;
9340 break;
9341 case 4:
9342 i.seg[i.mem_operands] = &fs;
9343 break;
9344 case 5:
9345 i.seg[i.mem_operands] = &gs;
9346 break;
9347 }
9348 }
9349 }
64a0c779 9350
b7240065
JB		 9351 else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
9352 {
9353 as_bad (_("cannot use `FLAT' here"));
9354 return 0;
9355 }
9356
a724f0f4
JB		 9357 /* Not a segment register. Check for register scaling. */
9358 else if (cur_token.code == '*')
9359 {
9360 if (!intel_parser.in_bracket)
9361 {
9362 as_bad (_("Register scaling only allowed in memory operands"));
9363 return 0;
9364 }
64a0c779 9365
40fb9820 9366 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 9367 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
9368 else if (i.index_reg)
9369 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 9370
a724f0f4
JB		 9371 /* What follows must be a valid scale. */
9372 intel_match_token ('*');
9373 i.index_reg = reg;
40fb9820 9374 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 9375
a724f0f4
JB		 9376 /* Set the scale after setting the register (otherwise,
9377 i386_scale will complain) */
9378 if (cur_token.code == '+' || cur_token.code == '-')
9379 {
9380 char *str, sign = cur_token.code;
9381 intel_match_token (cur_token.code);
9382 if (cur_token.code != T_CONST)
9383 {
9384 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9385 cur_token.str);
9386 return 0;
9387 }
9388 str = (char *) xmalloc (strlen (cur_token.str) + 2);
9389 strcpy (str + 1, cur_token.str);
9390 *str = sign;
9391 if (!i386_scale (str))
9392 return 0;
9393 free (str);
9394 }
9395 else if (!i386_scale (cur_token.str))
64a0c779 9396 return 0;
a724f0f4
JB		 9397 intel_match_token (cur_token.code);
9398 }
64a0c779 9399
a724f0f4
JB		 9400 /* No scaling. If this is a memory operand, the register is either a
9401 base register (first occurrence) or an index register (second
9402 occurrence). */
7b0441f6 9403 else if (intel_parser.in_bracket)
a724f0f4 9404 {
64a0c779 9405
a724f0f4
JB		 9406 if (!i.base_reg)
9407 i.base_reg = reg;
9408 else if (!i.index_reg)
9409 i.index_reg = reg;
9410 else
9411 {
9412 as_bad (_("Too many register references in memory operand"));
9413 return 0;
9414 }
64a0c779 9415
40fb9820 9416 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 9417 }
4a1805b1 9418
4d1bb795
JB		 9419 /* It's neither base nor index. */
9420 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 9421 {
40fb9820
L		 9422 i386_operand_type temp = reg->reg_type;
9423 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9424 i.types[this_operand] = operand_type_or (i.types[this_operand],
9425 temp);
7d5e4556 9426 i.types[this_operand].bitfield.unspecified = 0;
a724f0f4
JB		 9427 i.op[this_operand].regs = reg;
9428 i.reg_operands++;
9429 }
9430 else
9431 {
9432 as_bad (_("Invalid use of register"));
9433 return 0;
9434 }
64a0c779 9435
a724f0f4
JB		 9436 /* Since registers are not part of the displacement string (except
9437 when we're parsing offset operands), we may need to remove any
9438 preceding '+' from the displacement string. */
9439 if (*intel_parser.disp != '\0'
9440 && !intel_parser.in_offset)
9441 {
9442 char *s = intel_parser.disp;
9443 s += strlen (s) - 1;
9444 if (*s == '+')
9445 *s = '\0';
9446 }
4a1805b1 9447
a724f0f4
JB		 9448 return 1;
9449 }
9450
9451 /* e11 BYTE
9452 | WORD
9453 | DWORD
9454 | FWORD
9455 | QWORD
9456 | TBYTE
9457 | OWORD
c0f3af97
L		 9458 | XMMWORD
9459 | YMMWORD */
a724f0f4
JB		 9460 case T_BYTE:
9461 case T_WORD:
9462 case T_DWORD:
9463 case T_FWORD:
9464 case T_QWORD:
9465 case T_TBYTE:
9466 case T_XMMWORD:
c0f3af97 9467 case T_YMMWORD:
a724f0f4 9468 intel_match_token (cur_token.code);
64a0c779 9469
a724f0f4
JB		 9470 if (cur_token.code == T_PTR)
9471 return 1;
9472
9473 /* It must have been an identifier. */
9474 intel_putback_token ();
9475 cur_token.code = T_ID;
9476 /* FALLTHRU */
9477
9478 /* e11 id
9479 | constant */
9480 case T_ID:
9481 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 9482 {
9483 symbolS *symbolP;
9484
a724f0f4
JB		 9485 /* The identifier represents a memory reference only if it's not
9486 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 9487 symbolP = symbol_find(cur_token.str);
9488 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
9489 intel_parser.is_mem = 1;
9490 }
a724f0f4 9491 /* FALLTHRU */
64a0c779 9492
a724f0f4
JB		 9493 case T_CONST:
9494 case '-':
9495 case '+':
9496 {
9497 char *save_str, sign = 0;
64a0c779 9498
a724f0f4
JB		 9499 /* Allow constants that start with `+' or `-'. */
9500 if (cur_token.code == '-' || cur_token.code == '+')
9501 {
9502 sign = cur_token.code;
9503 intel_match_token (cur_token.code);
9504 if (cur_token.code != T_CONST)
9505 {
9506 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9507 cur_token.str);
9508 return 0;
9509 }
9510 }
64a0c779 9511
a724f0f4
JB		 9512 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
9513 strcpy (save_str + !!sign, cur_token.str);
9514 if (sign)
9515 *save_str = sign;
64a0c779 9516
a724f0f4
JB		 9517 /* Get the next token to check for register scaling. */
9518 intel_match_token (cur_token.code);
64a0c779 9519
4eed87de
AM		 9520 /* Check if this constant is a scaling factor for an
9521 index register. */
a724f0f4
JB		 9522 if (cur_token.code == '*')
9523 {
9524 if (intel_match_token ('*') && cur_token.code == T_REG)
9525 {
9526 const reg_entry *reg = cur_token.reg;
9527
9528 if (!intel_parser.in_bracket)
9529 {
4eed87de
AM		 9530 as_bad (_("Register scaling only allowed "
9531 "in memory operands"));
a724f0f4
JB		 9532 return 0;
9533 }
9534
4eed87de
AM		 9535 /* Disallow things like [1*si].
9536 sp and esp are invalid as index. */
40fb9820 9537 if (reg->reg_type.bitfield.reg16)
4eed87de 9538 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 9539 else if (i.index_reg)
4eed87de 9540 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 9541
9542 /* The constant is followed by `* reg', so it must be
9543 a valid scale. */
9544 i.index_reg = reg;
40fb9820 9545 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 9546
9547 /* Set the scale after setting the register (otherwise,
9548 i386_scale will complain) */
9549 if (!i386_scale (save_str))
64a0c779 9550 return 0;
a724f0f4
JB		 9551 intel_match_token (T_REG);
9552
9553 /* Since registers are not part of the displacement
9554 string, we may need to remove any preceding '+' from
9555 the displacement string. */
9556 if (*intel_parser.disp != '\0')
9557 {
9558 char *s = intel_parser.disp;
9559 s += strlen (s) - 1;
9560 if (*s == '+')
9561 *s = '\0';
9562 }
9563
9564 free (save_str);
9565
9566 return 1;
9567 }
64a0c779 9568
a724f0f4
JB		 9569 /* The constant was not used for register scaling. Since we have
9570 already consumed the token following `*' we now need to put it
9571 back in the stream. */
64a0c779 9572 intel_putback_token ();
a724f0f4 9573 }
64a0c779 9574
a724f0f4
JB		 9575 /* Add the constant to the displacement string. */
9576 strcat (intel_parser.disp, save_str);
9577 free (save_str);
64a0c779 9578
a724f0f4
JB		 9579 return 1;
9580 }
64a0c779
DN		 9581 }
9582
64a0c779
DN		 9583 as_bad (_("Unrecognized token '%s'"), cur_token.str);
9584 return 0;
9585}
9586
64a0c779
DN		 9587/* Match the given token against cur_token. If they match, read the next
9588 token from the operand string. */
9589static int
e3bb37b5 9590intel_match_token (int code)
64a0c779
DN		 9591{
9592 if (cur_token.code == code)
9593 {
9594 intel_get_token ();
9595 return 1;
9596 }
9597 else
9598 {
0477af35 9599 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 9600 return 0;
9601 }
9602}
9603
64a0c779
DN		 9604/* Read a new token from intel_parser.op_string and store it in cur_token. */
9605static void
e3bb37b5 9606intel_get_token (void)
64a0c779
DN		 9607{
9608 char *end_op;
9609 const reg_entry *reg;
9610 struct intel_token new_token;
9611
9612 new_token.code = T_NIL;
9613 new_token.reg = NULL;
9614 new_token.str = NULL;
9615
4a1805b1 9616 /* Free the memory allocated to the previous token and move
64a0c779
DN		 9617 cur_token to prev_token. */
9618 if (prev_token.str)
9619 free (prev_token.str);
9620
9621 prev_token = cur_token;
9622
9623 /* Skip whitespace. */
9624 while (is_space_char (*intel_parser.op_string))
9625 intel_parser.op_string++;
9626
9627 /* Return an empty token if we find nothing else on the line. */
9628 if (*intel_parser.op_string == '\0')
9629 {
9630 cur_token = new_token;
9631 return;
9632 }
9633
9634 /* The new token cannot be larger than the remainder of the operand
9635 string. */
a724f0f4 9636 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 9637 new_token.str[0] = '\0';
9638
9639 if (strchr ("0123456789", *intel_parser.op_string))
9640 {
9641 char *p = new_token.str;
9642 char *q = intel_parser.op_string;
9643 new_token.code = T_CONST;
9644
9645 /* Allow any kind of identifier char to encompass floating point and
9646 hexadecimal numbers. */
9647 while (is_identifier_char (*q))
9648 *p++ = *q++;
9649 *p = '\0';
9650
9651 /* Recognize special symbol names [0-9][bf]. */
9652 if (strlen (intel_parser.op_string) == 2
4a1805b1 9653 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 9654 || intel_parser.op_string[1] == 'f'))
9655 new_token.code = T_ID;
9656 }
9657
4d1bb795 9658 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 9659 {
4d1bb795
JB		 9660 size_t len = end_op - intel_parser.op_string;
9661
64a0c779
DN		 9662 new_token.code = T_REG;
9663 new_token.reg = reg;
9664
4d1bb795
JB		 9665 memcpy (new_token.str, intel_parser.op_string, len);
9666 new_token.str[len] = '\0';
64a0c779
DN		 9667 }
9668
9669 else if (is_identifier_char (*intel_parser.op_string))
9670 {
9671 char *p = new_token.str;
9672 char *q = intel_parser.op_string;
9673
9674 /* A '.' or '$' followed by an identifier char is an identifier.
9675 Otherwise, it's operator '.' followed by an expression. */
9676 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9677 {
9306ca4a
JB		 9678 new_token.code = '.';
9679 new_token.str[0] = '.';
64a0c779
DN		 9680 new_token.str[1] = '\0';
9681 }
9682 else
9683 {
9684 while (is_identifier_char (*q) || *q == '@')
9685 *p++ = *q++;
9686 *p = '\0';
9687
9306ca4a
JB		 9688 if (strcasecmp (new_token.str, "NOT") == 0)
9689 new_token.code = '~';
9690
9691 else if (strcasecmp (new_token.str, "MOD") == 0)
9692 new_token.code = '%';
9693
9694 else if (strcasecmp (new_token.str, "AND") == 0)
9695 new_token.code = '&';
9696
9697 else if (strcasecmp (new_token.str, "OR") == 0)
9698 new_token.code = '|';
9699
9700 else if (strcasecmp (new_token.str, "XOR") == 0)
9701 new_token.code = '^';
9702
9703 else if (strcasecmp (new_token.str, "SHL") == 0)
9704 new_token.code = T_SHL;
9705
9706 else if (strcasecmp (new_token.str, "SHR") == 0)
9707 new_token.code = T_SHR;
9708
9709 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 9710 new_token.code = T_BYTE;
9711
9712 else if (strcasecmp (new_token.str, "WORD") == 0)
9713 new_token.code = T_WORD;
9714
9715 else if (strcasecmp (new_token.str, "DWORD") == 0)
9716 new_token.code = T_DWORD;
9717
9306ca4a
JB		 9718 else if (strcasecmp (new_token.str, "FWORD") == 0)
9719 new_token.code = T_FWORD;
9720
64a0c779
DN		 9721 else if (strcasecmp (new_token.str, "QWORD") == 0)
9722 new_token.code = T_QWORD;
9723
9306ca4a
JB		 9724 else if (strcasecmp (new_token.str, "TBYTE") == 0
9725 /* XXX remove (gcc still uses it) */
9726 || strcasecmp (new_token.str, "XWORD") == 0)
9727 new_token.code = T_TBYTE;
9728
9729 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9730 || strcasecmp (new_token.str, "OWORD") == 0)
9731 new_token.code = T_XMMWORD;
64a0c779 9732
c0f3af97
L		 9733 else if (strcasecmp (new_token.str, "YMMWORD") == 0)
9734 new_token.code = T_YMMWORD;
9735
64a0c779
DN		 9736 else if (strcasecmp (new_token.str, "PTR") == 0)
9737 new_token.code = T_PTR;
9738
9739 else if (strcasecmp (new_token.str, "SHORT") == 0)
9740 new_token.code = T_SHORT;
9741
9742 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9743 {
9744 new_token.code = T_OFFSET;
9745
9746 /* ??? This is not mentioned in the MASM grammar but gcc
9747 makes use of it with -mintel-syntax. OFFSET may be
9748 followed by FLAT: */
9749 if (strncasecmp (q, " FLAT:", 6) == 0)
9750 strcat (new_token.str, " FLAT:");
9751 }
9752
64a0c779
DN		 9753 else
9754 new_token.code = T_ID;
9755 }
9756 }
9757
9306ca4a
JB		 9758 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9759 {
9760 new_token.code = *intel_parser.op_string;
9761 new_token.str[0] = *intel_parser.op_string;
9762 new_token.str[1] = '\0';
9763 }
9764
9765 else if (strchr ("<>", *intel_parser.op_string)
9766 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9767 {
9768 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9769 new_token.str[0] = *intel_parser.op_string;
9770 new_token.str[1] = *intel_parser.op_string;
9771 new_token.str[2] = '\0';
9772 }
9773
64a0c779 9774 else
0477af35 9775 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 9776
9777 intel_parser.op_string += strlen (new_token.str);
9778 cur_token = new_token;
9779}
9780
64a0c779
DN		 9781/* Put cur_token back into the token stream and make cur_token point to
9782 prev_token. */
9783static void
e3bb37b5 9784intel_putback_token (void)
64a0c779 9785{
a724f0f4
JB		 9786 if (cur_token.code != T_NIL)
9787 {
9788 intel_parser.op_string -= strlen (cur_token.str);
9789 free (cur_token.str);
9790 }
64a0c779 9791 cur_token = prev_token;
4a1805b1 9792
64a0c779
DN		 9793 /* Forget prev_token. */
9794 prev_token.code = T_NIL;
9795 prev_token.reg = NULL;
9796 prev_token.str = NULL;
9797}
54cfded0 9798
a60de03c
JB		 9799void
9800tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9801{
a60de03c
JB		 9802 int saved_naked_reg;
9803 char saved_register_dot;
54cfded0 9804
a60de03c
JB		 9805 saved_naked_reg = allow_naked_reg;
9806 allow_naked_reg = 1;
9807 saved_register_dot = register_chars['.'];
9808 register_chars['.'] = '.';
9809 allow_pseudo_reg = 1;
9810 expression_and_evaluate (exp);
9811 allow_pseudo_reg = 0;
9812 register_chars['.'] = saved_register_dot;
9813 allow_naked_reg = saved_naked_reg;
9814
9815 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 9816 {
a60de03c
JB		 9817 if ((addressT) exp->X_add_number < i386_regtab_size)
9818 {
9819 exp->X_op = O_constant;
9820 exp->X_add_number = i386_regtab[exp->X_add_number]
9821 .dw2_regnum[flag_code >> 1];
9822 }
9823 else
9824 exp->X_op = O_illegal;
54cfded0 9825 }
54cfded0
AM		 9826}
9827
9828void
9829tc_x86_frame_initial_instructions (void)
9830{
a60de03c
JB		 9831 static unsigned int sp_regno[2];
9832
9833 if (!sp_regno[flag_code >> 1])
9834 {
9835 char *saved_input = input_line_pointer;
9836 char sp[][4] = {"esp", "rsp"};
9837 expressionS exp;
a4447b93 9838
a60de03c
JB		 9839 input_line_pointer = sp[flag_code >> 1];
9840 tc_x86_parse_to_dw2regnum (&exp);
9841 assert (exp.X_op == O_constant);
9842 sp_regno[flag_code >> 1] = exp.X_add_number;
9843 input_line_pointer = saved_input;
9844 }
a4447b93 9845
a60de03c 9846 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 9847 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9848}
d2b2c203
DJ		 9849
9850int
9851i386_elf_section_type (const char *str, size_t len)
9852{
9853 if (flag_code == CODE_64BIT
9854 && len == sizeof ("unwind") - 1
9855 && strncmp (str, "unwind", 6) == 0)
9856 return SHT_X86_64_UNWIND;
9857
9858 return -1;
9859}
bb41ade5
AM		 9860
9861#ifdef TE_PE
9862void
9863tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9864{
9865 expressionS expr;
9866
9867 expr.X_op = O_secrel;
9868 expr.X_add_symbol = symbol;
9869 expr.X_add_number = 0;
9870 emit_expr (&expr, size);
9871}
9872#endif
3b22753a
L		 9873
9874#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9875/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9876
9877int
9878x86_64_section_letter (int letter, char **ptr_msg)
9879{
9880 if (flag_code == CODE_64BIT)
9881 {
9882 if (letter == 'l')
9883 return SHF_X86_64_LARGE;
9884
9885 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9886 }
3b22753a 9887 else
64e74474 9888 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9889 return -1;
9890}
9891
9892int
9893x86_64_section_word (char *str, size_t len)
9894{
8620418b 9895 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9896 return SHF_X86_64_LARGE;
9897
9898 return -1;
9899}
9900
9901static void
9902handle_large_common (int small ATTRIBUTE_UNUSED)
9903{
9904 if (flag_code != CODE_64BIT)
9905 {
9906 s_comm_internal (0, elf_common_parse);
9907 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9908 }
9909 else
9910 {
9911 static segT lbss_section;
9912 asection *saved_com_section_ptr = elf_com_section_ptr;
9913 asection *saved_bss_section = bss_section;
9914
9915 if (lbss_section == NULL)
9916 {
9917 flagword applicable;
9918 segT seg = now_seg;
9919 subsegT subseg = now_subseg;
9920
9921 /* The .lbss section is for local .largecomm symbols. */
9922 lbss_section = subseg_new (".lbss", 0);
9923 applicable = bfd_applicable_section_flags (stdoutput);
9924 bfd_set_section_flags (stdoutput, lbss_section,
9925 applicable & SEC_ALLOC);
9926 seg_info (lbss_section)->bss = 1;
9927
9928 subseg_set (seg, subseg);
9929 }
9930
9931 elf_com_section_ptr = &_bfd_elf_large_com_section;
9932 bss_section = lbss_section;
9933
9934 s_comm_internal (0, elf_common_parse);
9935
9936 elf_com_section_ptr = saved_com_section_ptr;
9937 bss_section = saved_bss_section;
9938 }
9939}
9940#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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