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Don't link FreeBSD tests with -ldl.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
4b95cf5c 2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
22109423 136 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 137}
138arch_entry;
139
78f12dd3 140static void update_code_flag (int, int);
e3bb37b5
L		 141static void set_code_flag (int);
142static void set_16bit_gcc_code_flag (int);
143static void set_intel_syntax (int);
1efbbeb4 144static void set_intel_mnemonic (int);
db51cc60 145static void set_allow_index_reg (int);
7bab8ab5 146static void set_check (int);
e3bb37b5 147static void set_cpu_arch (int);
6482c264 148#ifdef TE_PE
e3bb37b5 149static void pe_directive_secrel (int);
6482c264 150#endif
e3bb37b5
L		 151static void signed_cons (int);
152static char *output_invalid (int c);
ee86248c
JB		 153static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
154 const char *);
155static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
156 const char *);
a7619375 157static int i386_att_operand (char *);
e3bb37b5 158static int i386_intel_operand (char *, int);
ee86248c
JB		 159static int i386_intel_simplify (expressionS *);
160static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 161static const reg_entry *parse_register (char *, char **);
162static char *parse_insn (char *, char *);
163static char *parse_operands (char *, const char *);
164static void swap_operands (void);
4d456e3d 165static void swap_2_operands (int, int);
e3bb37b5
L		 166static void optimize_imm (void);
167static void optimize_disp (void);
d3ce72d0 168static const insn_template *match_template (void);
e3bb37b5
L		 169static int check_string (void);
170static int process_suffix (void);
171static int check_byte_reg (void);
172static int check_long_reg (void);
173static int check_qword_reg (void);
174static int check_word_reg (void);
175static int finalize_imm (void);
176static int process_operands (void);
177static const seg_entry *build_modrm_byte (void);
178static void output_insn (void);
179static void output_imm (fragS *, offsetT);
180static void output_disp (fragS *, offsetT);
29b0f896 181#ifndef I386COFF
e3bb37b5 182static void s_bss (int);
252b5132 183#endif
17d4e2a2
L		 184#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185static void handle_large_common (int small ATTRIBUTE_UNUSED);
186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
43234a1e
L		 190/* This struct describes rounding control and SAE in the instruction. */
191struct RC_Operation
192{
193 enum rc_type
194 {
195 rne = 0,
196 rd,
197 ru,
198 rz,
199 saeonly
200 } type;
201 int operand;
202};
203
204static struct RC_Operation rc_op;
205
206/* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209struct Mask_Operation
210{
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
214 int operand;
215};
216
217static struct Mask_Operation mask_op;
218
219/* The struct describes broadcasting, applied to OPERAND. FACTOR is
220 broadcast factor. */
221struct Broadcast_Operation
222{
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
224 int type;
225
226 /* Index of broadcasted operand. */
227 int operand;
228};
229
230static struct Broadcast_Operation broadcast_op;
231
c0f3af97
L		 232/* VEX prefix. */
233typedef struct
234{
43234a1e
L		 235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
c0f3af97
L		 237 unsigned int length;
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
240} vex_prefix;
241
252b5132 242/* 'md_assemble ()' gathers together information and puts it into a
47926f60 243 i386_insn. */
252b5132 244
520dc8e8
AM		 245union i386_op
246 {
247 expressionS *disps;
248 expressionS *imms;
249 const reg_entry *regs;
250 };
251
a65babc9
L		 252enum i386_error
253 {
86e026a4 254 operand_size_mismatch,
a65babc9
L		 255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
259 bad_imm4,
260 old_gcc_only,
261 unsupported_with_intel_mnemonic,
262 unsupported_syntax,
6c30d220
L		 263 unsupported,
264 invalid_vsib_address,
7bab8ab5 265 invalid_vector_register_set,
43234a1e
L		 266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
269 broadcast_needed,
270 unsupported_masking,
271 mask_not_on_destination,
272 no_default_mask,
273 unsupported_rc_sae,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
276 try_vector_disp8
a65babc9
L		 277 };
278
252b5132
RH		 279struct _i386_insn
280 {
47926f60 281 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 282 insn_template tm;
252b5132 283
7d5e4556
L		 284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
252b5132
RH		 286 char suffix;
287
47926f60 288 /* OPERANDS gives the number of given operands. */
252b5132
RH		 289 unsigned int operands;
290
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
47926f60 293 operands. */
252b5132
RH		 294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
295
296 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 297 use OP[i] for the corresponding operand. */
40fb9820 298 i386_operand_type types[MAX_OPERANDS];
252b5132 299
520dc8e8
AM		 300 /* Displacement expression, immediate expression, or register for each
301 operand. */
302 union i386_op op[MAX_OPERANDS];
252b5132 303
3e73aa7c
JH		 304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306#define Operand_PCrel 1
307
252b5132 308 /* Relocation type for operand */
f86103b7 309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 310
252b5132
RH		 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
316
317 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 318 explicit segment overrides are given. */
ce8a8b2f 319 const seg_entry *seg[2];
252b5132
RH		 320
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
325
326 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 327 addressing modes of this insn are encoded. */
252b5132 328 modrm_byte rm;
3e73aa7c 329 rex_byte rex;
43234a1e 330 rex_byte vrex;
252b5132 331 sib_byte sib;
c0f3af97 332 vex_prefix vex;
b6169b20 333
43234a1e
L		 334 /* Masking attributes. */
335 struct Mask_Operation *mask;
336
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
339
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
342
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
345
b6169b20 346 /* Swap operand in encoding. */
4473e004 347 unsigned int swap_operand;
891edac4 348
a501d77e
L		 349 /* Prefer 8bit or 32bit displacement in encoding. */
350 enum
351 {
352 disp_encoding_default = 0,
353 disp_encoding_8bit,
354 disp_encoding_32bit
355 } disp_encoding;
f8a5c266 356
d5de92cf
L		 357 /* REP prefix. */
358 const char *rep_prefix;
359
165de32a
L		 360 /* HLE prefix. */
361 const char *hle_prefix;
42164a71 362
7e8b059b
L		 363 /* Have BND prefix. */
364 const char *bnd_prefix;
365
43234a1e
L		 366 /* Need VREX to support upper 16 registers. */
367 int need_vrex;
368
891edac4 369 /* Error message. */
a65babc9 370 enum i386_error error;
252b5132
RH		 371 };
372
373typedef struct _i386_insn i386_insn;
374
43234a1e
L		 375/* Link RC type with corresponding string, that'll be looked for in
376 asm. */
377struct RC_name
378{
379 enum rc_type type;
380 const char *name;
381 unsigned int len;
382};
383
384static const struct RC_name RC_NamesTable[] =
385{
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
391};
392
252b5132
RH		 393/* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 395const char extra_symbol_chars[] = "*%-([{"
252b5132 396#ifdef LEX_AT
32137342
NC		 397 "@"
398#endif
399#ifdef LEX_QM
400 "?"
252b5132 401#endif
32137342 402 ;
252b5132 403
29b0f896
AM		 404#if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 406 && !defined (TE_GNU) \
29b0f896 407 && !defined (TE_LINUX) \
8d63c93e
RM		 408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
29b0f896 410 && !defined (TE_FreeBSD) \
5b806d27 411 && !defined (TE_DragonFly) \
29b0f896 412 && !defined (TE_NetBSD)))
252b5132 413/* This array holds the chars that always start a comment. If the
b3b91714
AM		 414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416const char *i386_comment_chars = "#/";
417#define SVR4_COMMENT_CHARS 1
252b5132 418#define PREFIX_SEPARATOR '\\'
252b5132 419
b3b91714
AM		 420#else
421const char *i386_comment_chars = "#";
422#define PREFIX_SEPARATOR '/'
423#endif
424
252b5132
RH		 425/* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 429 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
252b5132 432 '/' isn't otherwise defined. */
b3b91714 433const char line_comment_chars[] = "#/";
252b5132 434
63a0b638 435const char line_separator_chars[] = ";";
252b5132 436
ce8a8b2f
AM		 437/* Chars that can be used to separate mant from exp in floating point
438 nums. */
252b5132
RH		 439const char EXP_CHARS[] = "eE";
440
ce8a8b2f
AM		 441/* Chars that mean this number is a floating point constant
442 As in 0f12.456
443 or 0d1.2345e12. */
252b5132
RH		 444const char FLT_CHARS[] = "fFdDxX";
445
ce8a8b2f 446/* Tables for lexical analysis. */
252b5132
RH		 447static char mnemonic_chars[256];
448static char register_chars[256];
449static char operand_chars[256];
450static char identifier_chars[256];
451static char digit_chars[256];
452
ce8a8b2f 453/* Lexical macros. */
252b5132
RH		 454#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455#define is_operand_char(x) (operand_chars[(unsigned char) x])
456#define is_register_char(x) (register_chars[(unsigned char) x])
457#define is_space_char(x) ((x) == ' ')
458#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459#define is_digit_char(x) (digit_chars[(unsigned char) x])
460
0234cb7c 461/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 462static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
463
464/* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
47926f60 467 assembler instruction). */
252b5132 468static char save_stack[32];
ce8a8b2f 469static char *save_stack_p;
252b5132
RH		 470#define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472#define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
474
47926f60 475/* The instruction we're assembling. */
252b5132
RH		 476static i386_insn i;
477
478/* Possible templates for current insn. */
479static const templates *current_templates;
480
31b2323c
L		 481/* Per instruction expressionS buffers: max displacements & immediates. */
482static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 484
47926f60 485/* Current operand we are working on. */
ee86248c 486static int this_operand = -1;
252b5132 487
3e73aa7c
JH		 488/* We support four different modes. FLAG_CODE variable is used to distinguish
489 these. */
490
491enum flag_code {
492 CODE_32BIT,
493 CODE_16BIT,
494 CODE_64BIT };
495
496static enum flag_code flag_code;
4fa24527 497static unsigned int object_64bit;
862be3fb 498static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 499static int use_rela_relocations = 0;
500
7af8ed2d
NC		 501#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
504
351f65ca
L		 505/* The ELF ABI to use. */
506enum x86_elf_abi
507{
508 I386_ABI,
7f56bc95
L		 509 X86_64_ABI,
510 X86_64_X32_ABI
351f65ca
L		 511};
512
513static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 514#endif
351f65ca 515
167ad85b
TG		 516#if defined (TE_PE) || defined (TE_PEP)
517/* Use big object file format. */
518static int use_big_obj = 0;
519#endif
520
47926f60
KH		 521/* 1 for intel syntax,
522 0 if att syntax. */
523static int intel_syntax = 0;
252b5132 524
1efbbeb4
L		 525/* 1 for intel mnemonic,
526 0 if att mnemonic. */
527static int intel_mnemonic = !SYSV386_COMPAT;
528
5209009a 529/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 530static int old_gcc = OLDGCC_COMPAT;
531
a60de03c
JB		 532/* 1 if pseudo registers are permitted. */
533static int allow_pseudo_reg = 0;
534
47926f60
KH		 535/* 1 if register prefix % not required. */
536static int allow_naked_reg = 0;
252b5132 537
7e8b059b
L		 538/* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
540 explicitly. */
541static int add_bnd_prefix = 0;
542
ba104c83 543/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 544static int allow_index_reg = 0;
545
7bab8ab5 546static enum check_kind
daf50ae7 547 {
7bab8ab5
JB		 548 check_none = 0,
549 check_warning,
550 check_error
daf50ae7 551 }
7bab8ab5 552sse_check, operand_check = check_warning;
daf50ae7 553
2ca3ace5
L		 554/* Register prefix used for error message. */
555static const char *register_prefix = "%";
556
47926f60
KH		 557/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
558 leave, push, and pop instructions so that gcc has the same stack
559 frame as in 32 bit mode. */
560static char stackop_size = '\0';
eecb386c 561
12b55ccc
L		 562/* Non-zero to optimize code alignment. */
563int optimize_align_code = 1;
564
47926f60
KH		 565/* Non-zero to quieten some warnings. */
566static int quiet_warnings = 0;
a38cf1db 567
47926f60
KH		 568/* CPU name. */
569static const char *cpu_arch_name = NULL;
6305a203 570static char *cpu_sub_arch_name = NULL;
a38cf1db 571
47926f60 572/* CPU feature flags. */
40fb9820
L		 573static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
574
ccc9c027
L		 575/* If we have selected a cpu we are generating instructions for. */
576static int cpu_arch_tune_set = 0;
577
9103f4f4 578/* Cpu we are generating instructions for. */
fbf3f584 579enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 580
581/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 582static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 583
ccc9c027 584/* CPU instruction set architecture used. */
fbf3f584 585enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 586
9103f4f4 587/* CPU feature flags of instruction set architecture used. */
fbf3f584 588i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 589
fddf5b5b
AM		 590/* If set, conditional jumps are not automatically promoted to handle
591 larger than a byte offset. */
592static unsigned int no_cond_jump_promotion = 0;
593
c0f3af97
L		 594/* Encode SSE instructions with VEX prefix. */
595static unsigned int sse2avx;
596
539f890d
L		 597/* Encode scalar AVX instructions with specific vector length. */
598static enum
599 {
600 vex128 = 0,
601 vex256
602 } avxscalar;
603
43234a1e
L		 604/* Encode scalar EVEX LIG instructions with specific vector length. */
605static enum
606 {
607 evexl128 = 0,
608 evexl256,
609 evexl512
610 } evexlig;
611
612/* Encode EVEX WIG instructions with specific evex.w. */
613static enum
614 {
615 evexw0 = 0,
616 evexw1
617 } evexwig;
618
29b0f896 619/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 620static symbolS *GOT_symbol;
29b0f896 621
a4447b93
RH		 622/* The dwarf2 return column, adjusted for 32 or 64 bit. */
623unsigned int x86_dwarf2_return_column;
624
625/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
626int x86_cie_data_alignment;
627
252b5132 628/* Interface to relax_segment.
fddf5b5b
AM		 629 There are 3 major relax states for 386 jump insns because the
630 different types of jumps add different sizes to frags when we're
631 figuring out what sort of jump to choose to reach a given label. */
252b5132 632
47926f60 633/* Types. */
93c2a809
AM		 634#define UNCOND_JUMP 0
635#define COND_JUMP 1
636#define COND_JUMP86 2
fddf5b5b 637
47926f60 638/* Sizes. */
252b5132
RH		 639#define CODE16 1
640#define SMALL 0
29b0f896 641#define SMALL16 (SMALL | CODE16)
252b5132 642#define BIG 2
29b0f896 643#define BIG16 (BIG | CODE16)
252b5132
RH		 644
645#ifndef INLINE
646#ifdef __GNUC__
647#define INLINE __inline__
648#else
649#define INLINE
650#endif
651#endif
652
fddf5b5b
AM		 653#define ENCODE_RELAX_STATE(type, size) \
654 ((relax_substateT) (((type) << 2) | (size)))
655#define TYPE_FROM_RELAX_STATE(s) \
656 ((s) >> 2)
657#define DISP_SIZE_FROM_RELAX_STATE(s) \
658 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 659
660/* This table is used by relax_frag to promote short jumps to long
661 ones where necessary. SMALL (short) jumps may be promoted to BIG
662 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
663 don't allow a short jump in a 32 bit code segment to be promoted to
664 a 16 bit offset jump because it's slower (requires data size
665 prefix), and doesn't work, unless the destination is in the bottom
666 64k of the code segment (The top 16 bits of eip are zeroed). */
667
668const relax_typeS md_relax_table[] =
669{
24eab124
AM		 670 /* The fields are:
671 1) most positive reach of this state,
672 2) most negative reach of this state,
93c2a809 673 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 674 4) which index into the table to try if we can't fit into this one. */
252b5132 675
fddf5b5b 676 /* UNCOND_JUMP states. */
93c2a809
AM		 677 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
678 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
679 /* dword jmp adds 4 bytes to frag:
680 0 extra opcode bytes, 4 displacement bytes. */
252b5132 681 {0, 0, 4, 0},
93c2a809
AM		 682 /* word jmp adds 2 byte2 to frag:
683 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 684 {0, 0, 2, 0},
685
93c2a809
AM		 686 /* COND_JUMP states. */
687 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
688 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
689 /* dword conditionals adds 5 bytes to frag:
690 1 extra opcode byte, 4 displacement bytes. */
691 {0, 0, 5, 0},
fddf5b5b 692 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 693 1 extra opcode byte, 2 displacement bytes. */
694 {0, 0, 3, 0},
695
696 /* COND_JUMP86 states. */
697 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
698 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
699 /* dword conditionals adds 5 bytes to frag:
700 1 extra opcode byte, 4 displacement bytes. */
701 {0, 0, 5, 0},
702 /* word conditionals add 4 bytes to frag:
703 1 displacement byte and a 3 byte long branch insn. */
704 {0, 0, 4, 0}
252b5132
RH		 705};
706
9103f4f4
L		 707static const arch_entry cpu_arch[] =
708{
89507696
JB		 709 /* Do not replace the first two entries - i386_target_format()
710 relies on them being there in this order. */
8a2c8fef 711 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 712 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 713 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 714 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 715 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 716 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 717 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 718 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 719 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 720 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 721 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 722 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 723 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 724 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 725 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 726 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 727 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 728 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 729 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 730 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 732 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 734 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 736 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 738 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 740 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 741 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 742 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 743 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 744 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 745 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 746 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 747 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 748 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 750 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 752 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 753 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 754 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 755 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
756 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 758 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 760 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 762 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 764 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 766 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 768 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 770 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 771 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 772 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 773 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 774 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 775 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
776 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 777 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
778 CPU_BDVER4_FLAGS, 0, 0 },
7b458c12
L		 779 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
780 CPU_BTVER1_FLAGS, 0, 0 },
781 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
782 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 783 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 784 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 785 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 786 CPU_287_FLAGS, 0, 0 },
8a2c8fef 787 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 788 CPU_387_FLAGS, 0, 0 },
8a2c8fef 789 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 790 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 791 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 792 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 793 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 794 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 795 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 796 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 797 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 798 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 799 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 800 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 801 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 802 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 803 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 804 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 805 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 806 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 807 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 808 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 809 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 810 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 811 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 812 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 813 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
814 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 815 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
816 CPU_AVX512F_FLAGS, 0, 0 },
817 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
818 CPU_AVX512CD_FLAGS, 0, 0 },
819 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
820 CPU_AVX512ER_FLAGS, 0, 0 },
821 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
822 CPU_AVX512PF_FLAGS, 0, 0 },
8a2c8fef 823 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 824 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 825 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 826 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 827 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
828 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 829 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 830 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 831 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 832 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 833 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 834 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 835 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 836 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 837 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 838 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 839 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 840 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 841 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 842 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 843 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 844 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 845 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 846 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 847 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
848 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 849 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 850 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 852 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 854 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 856 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 857 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 858 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 859 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
860 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 862 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 863 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
864 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 865 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
866 CPU_HLE_FLAGS, 0, 0 },
867 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
868 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 869 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
870 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 871 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 872 CPU_CLFLUSH_FLAGS, 0, 0 },
873 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
874 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 876 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 877 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 878 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 880 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 882 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 884 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 885 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 886 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 887 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 888 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 889 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 890 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 891 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 892 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 893 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
894 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 895 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
896 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 897 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
898 CPU_ADX_FLAGS, 0, 0 },
899 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
900 CPU_RDSEED_FLAGS, 0, 0 },
901 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
902 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 903 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
904 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 905 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
906 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 907 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
908 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 909 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
910 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
911 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
912 CPU_XSAVEC_FLAGS, 0, 0 },
913 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
914 CPU_XSAVES_FLAGS, 0, 0 },
dcf893b5
IT		 915 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
916 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 917 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
918 CPU_SE1_FLAGS, 0, 0 },
e413e4e9
AM		 919};
920
704209c0 921#ifdef I386COFF
a6c24e68
NC		 922/* Like s_lcomm_internal in gas/read.c but the alignment string
923 is allowed to be optional. */
924
925static symbolS *
926pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
927{
928 addressT align = 0;
929
930 SKIP_WHITESPACE ();
931
7ab9ffdd 932 if (needs_align
a6c24e68
NC		 933 && *input_line_pointer == ',')
934 {
935 align = parse_align (needs_align - 1);
7ab9ffdd 936
a6c24e68
NC		 937 if (align == (addressT) -1)
938 return NULL;
939 }
940 else
941 {
942 if (size >= 8)
943 align = 3;
944 else if (size >= 4)
945 align = 2;
946 else if (size >= 2)
947 align = 1;
948 else
949 align = 0;
950 }
951
952 bss_alloc (symbolP, size, align);
953 return symbolP;
954}
955
704209c0 956static void
a6c24e68
NC		 957pe_lcomm (int needs_align)
958{
959 s_comm_internal (needs_align * 2, pe_lcomm_internal);
960}
704209c0 961#endif
a6c24e68 962
29b0f896
AM		 963const pseudo_typeS md_pseudo_table[] =
964{
965#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
966 {"align", s_align_bytes, 0},
967#else
968 {"align", s_align_ptwo, 0},
969#endif
970 {"arch", set_cpu_arch, 0},
971#ifndef I386COFF
972 {"bss", s_bss, 0},
a6c24e68
NC		 973#else
974 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 975#endif
976 {"ffloat", float_cons, 'f'},
977 {"dfloat", float_cons, 'd'},
978 {"tfloat", float_cons, 'x'},
979 {"value", cons, 2},
d182319b 980 {"slong", signed_cons, 4},
29b0f896
AM		 981 {"noopt", s_ignore, 0},
982 {"optim", s_ignore, 0},
983 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
984 {"code16", set_code_flag, CODE_16BIT},
985 {"code32", set_code_flag, CODE_32BIT},
986 {"code64", set_code_flag, CODE_64BIT},
987 {"intel_syntax", set_intel_syntax, 1},
988 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 989 {"intel_mnemonic", set_intel_mnemonic, 1},
990 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 991 {"allow_index_reg", set_allow_index_reg, 1},
992 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 993 {"sse_check", set_check, 0},
994 {"operand_check", set_check, 1},
3b22753a
L		 995#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
996 {"largecomm", handle_large_common, 0},
07a53e5c 997#else
e3bb37b5 998 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 999 {"loc", dwarf2_directive_loc, 0},
1000 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1001#endif
6482c264
NC		 1002#ifdef TE_PE
1003 {"secrel32", pe_directive_secrel, 0},
1004#endif
29b0f896
AM		 1005 {0, 0, 0}
1006};
1007
1008/* For interface with expression (). */
1009extern char *input_line_pointer;
1010
1011/* Hash table for instruction mnemonic lookup. */
1012static struct hash_control *op_hash;
1013
1014/* Hash table for register lookup. */
1015static struct hash_control *reg_hash;
1016\f
252b5132 1017void
e3bb37b5 1018i386_align_code (fragS *fragP, int count)
252b5132 1019{
ce8a8b2f
AM		 1020 /* Various efficient no-op patterns for aligning code labels.
1021 Note: Don't try to assemble the instructions in the comments.
1022 0L and 0w are not legal. */
252b5132
RH		 1023 static const char f32_1[] =
1024 {0x90}; /* nop */
1025 static const char f32_2[] =
ccc9c027 1026 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1027 static const char f32_3[] =
1028 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1029 static const char f32_4[] =
1030 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1031 static const char f32_5[] =
1032 {0x90, /* nop */
1033 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1034 static const char f32_6[] =
1035 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1036 static const char f32_7[] =
1037 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1038 static const char f32_8[] =
1039 {0x90, /* nop */
1040 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1041 static const char f32_9[] =
1042 {0x89,0xf6, /* movl %esi,%esi */
1043 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1044 static const char f32_10[] =
1045 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1046 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1047 static const char f32_11[] =
1048 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1049 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1050 static const char f32_12[] =
1051 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1052 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1053 static const char f32_13[] =
1054 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1055 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1056 static const char f32_14[] =
1057 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1058 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1059 static const char f16_3[] =
1060 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1061 static const char f16_4[] =
1062 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1063 static const char f16_5[] =
1064 {0x90, /* nop */
1065 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1066 static const char f16_6[] =
1067 {0x89,0xf6, /* mov %si,%si */
1068 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1069 static const char f16_7[] =
1070 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1071 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1072 static const char f16_8[] =
1073 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1074 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1075 static const char jump_31[] =
1076 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1077 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1078 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1079 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1080 static const char *const f32_patt[] = {
1081 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1082 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1083 };
1084 static const char *const f16_patt[] = {
76bc74dc 1085 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1086 };
ccc9c027
L		 1087 /* nopl (%[re]ax) */
1088 static const char alt_3[] =
1089 {0x0f,0x1f,0x00};
1090 /* nopl 0(%[re]ax) */
1091 static const char alt_4[] =
1092 {0x0f,0x1f,0x40,0x00};
1093 /* nopl 0(%[re]ax,%[re]ax,1) */
1094 static const char alt_5[] =
1095 {0x0f,0x1f,0x44,0x00,0x00};
1096 /* nopw 0(%[re]ax,%[re]ax,1) */
1097 static const char alt_6[] =
1098 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1099 /* nopl 0L(%[re]ax) */
1100 static const char alt_7[] =
1101 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1102 /* nopl 0L(%[re]ax,%[re]ax,1) */
1103 static const char alt_8[] =
1104 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1105 /* nopw 0L(%[re]ax,%[re]ax,1) */
1106 static const char alt_9[] =
1107 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1108 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1109 static const char alt_10[] =
1110 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1111 /* data16
1112 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1113 static const char alt_long_11[] =
1114 {0x66,
1115 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1116 /* data16
1117 data16
1118 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1119 static const char alt_long_12[] =
1120 {0x66,
1121 0x66,
1122 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1123 /* data16
1124 data16
1125 data16
1126 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1127 static const char alt_long_13[] =
1128 {0x66,
1129 0x66,
1130 0x66,
1131 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1132 /* data16
1133 data16
1134 data16
1135 data16
1136 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_long_14[] =
1138 {0x66,
1139 0x66,
1140 0x66,
1141 0x66,
1142 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1143 /* data16
1144 data16
1145 data16
1146 data16
1147 data16
1148 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1149 static const char alt_long_15[] =
1150 {0x66,
1151 0x66,
1152 0x66,
1153 0x66,
1154 0x66,
1155 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1156 /* nopl 0(%[re]ax,%[re]ax,1)
1157 nopw 0(%[re]ax,%[re]ax,1) */
1158 static const char alt_short_11[] =
1159 {0x0f,0x1f,0x44,0x00,0x00,
1160 0x66,0x0f,0x1f,0x44,0x00,0x00};
1161 /* nopw 0(%[re]ax,%[re]ax,1)
1162 nopw 0(%[re]ax,%[re]ax,1) */
1163 static const char alt_short_12[] =
1164 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1165 0x66,0x0f,0x1f,0x44,0x00,0x00};
1166 /* nopw 0(%[re]ax,%[re]ax,1)
1167 nopl 0L(%[re]ax) */
1168 static const char alt_short_13[] =
1169 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1170 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1171 /* nopl 0L(%[re]ax)
1172 nopl 0L(%[re]ax) */
1173 static const char alt_short_14[] =
1174 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1175 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1176 /* nopl 0L(%[re]ax)
1177 nopl 0L(%[re]ax,%[re]ax,1) */
1178 static const char alt_short_15[] =
1179 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1180 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1181 static const char *const alt_short_patt[] = {
1182 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1183 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1184 alt_short_14, alt_short_15
1185 };
1186 static const char *const alt_long_patt[] = {
1187 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1188 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1189 alt_long_14, alt_long_15
1190 };
252b5132 1191
76bc74dc
L		 1192 /* Only align for at least a positive non-zero boundary. */
1193 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1194 return;
3e73aa7c 1195
ccc9c027
L		 1196 /* We need to decide which NOP sequence to use for 32bit and
1197 64bit. When -mtune= is used:
4eed87de 1198
76bc74dc
L		 1199 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1200 PROCESSOR_GENERIC32, f32_patt will be used.
1201 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1202 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1203 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1204 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1205 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1206 will be used.
ccc9c027 1207
76bc74dc 1208 When -mtune= isn't used, alt_long_patt will be used if
22109423 1209 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1210 be used.
ccc9c027
L		 1211
1212 When -march= or .arch is used, we can't use anything beyond
1213 cpu_arch_isa_flags. */
1214
1215 if (flag_code == CODE_16BIT)
1216 {
ccc9c027 1217 if (count > 8)
33fef721 1218 {
76bc74dc
L		 1219 memcpy (fragP->fr_literal + fragP->fr_fix,
1220 jump_31, count);
1221 /* Adjust jump offset. */
1222 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1223 }
76bc74dc
L		 1224 else
1225 memcpy (fragP->fr_literal + fragP->fr_fix,
1226 f16_patt[count - 1], count);
252b5132 1227 }
33fef721 1228 else
ccc9c027
L		 1229 {
1230 const char *const *patt = NULL;
1231
fbf3f584 1232 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1233 {
1234 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1235 switch (cpu_arch_tune)
1236 {
1237 case PROCESSOR_UNKNOWN:
1238 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1239 optimize with nops. */
1240 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1241 patt = alt_long_patt;
ccc9c027
L		 1242 else
1243 patt = f32_patt;
1244 break;
ccc9c027
L		 1245 case PROCESSOR_PENTIUM4:
1246 case PROCESSOR_NOCONA:
ef05d495 1247 case PROCESSOR_CORE:
76bc74dc 1248 case PROCESSOR_CORE2:
bd5295b2 1249 case PROCESSOR_COREI7:
3632d14b 1250 case PROCESSOR_L1OM:
7a9068fe 1251 case PROCESSOR_K1OM:
76bc74dc
L		 1252 case PROCESSOR_GENERIC64:
1253 patt = alt_long_patt;
1254 break;
ccc9c027
L		 1255 case PROCESSOR_K6:
1256 case PROCESSOR_ATHLON:
1257 case PROCESSOR_K8:
4eed87de 1258 case PROCESSOR_AMDFAM10:
8aedb9fe 1259 case PROCESSOR_BD:
7b458c12 1260 case PROCESSOR_BT:
ccc9c027
L		 1261 patt = alt_short_patt;
1262 break;
76bc74dc 1263 case PROCESSOR_I386:
ccc9c027
L		 1264 case PROCESSOR_I486:
1265 case PROCESSOR_PENTIUM:
2dde1948 1266 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1267 case PROCESSOR_GENERIC32:
1268 patt = f32_patt;
1269 break;
4eed87de 1270 }
ccc9c027
L		 1271 }
1272 else
1273 {
fbf3f584 1274 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1275 {
1276 case PROCESSOR_UNKNOWN:
e6a14101 1277 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1278 PROCESSOR_UNKNOWN. */
1279 abort ();
1280 break;
1281
76bc74dc 1282 case PROCESSOR_I386:
ccc9c027
L		 1283 case PROCESSOR_I486:
1284 case PROCESSOR_PENTIUM:
ccc9c027
L		 1285 case PROCESSOR_K6:
1286 case PROCESSOR_ATHLON:
1287 case PROCESSOR_K8:
4eed87de 1288 case PROCESSOR_AMDFAM10:
8aedb9fe 1289 case PROCESSOR_BD:
7b458c12 1290 case PROCESSOR_BT:
ccc9c027
L		 1291 case PROCESSOR_GENERIC32:
1292 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1293 with nops. */
1294 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1295 patt = alt_short_patt;
1296 else
1297 patt = f32_patt;
1298 break;
76bc74dc
L		 1299 case PROCESSOR_PENTIUMPRO:
1300 case PROCESSOR_PENTIUM4:
1301 case PROCESSOR_NOCONA:
1302 case PROCESSOR_CORE:
ef05d495 1303 case PROCESSOR_CORE2:
bd5295b2 1304 case PROCESSOR_COREI7:
3632d14b 1305 case PROCESSOR_L1OM:
7a9068fe 1306 case PROCESSOR_K1OM:
22109423 1307 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1308 patt = alt_long_patt;
1309 else
1310 patt = f32_patt;
1311 break;
1312 case PROCESSOR_GENERIC64:
76bc74dc 1313 patt = alt_long_patt;
ccc9c027 1314 break;
4eed87de 1315 }
ccc9c027
L		 1316 }
1317
76bc74dc
L		 1318 if (patt == f32_patt)
1319 {
1320 /* If the padding is less than 15 bytes, we use the normal
1321 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1322 its offset. */
1323 int limit;
76ba9986 1324
711eedef
L		 1325 /* For 64bit, the limit is 3 bytes. */
1326 if (flag_code == CODE_64BIT
1327 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1328 limit = 3;
1329 else
1330 limit = 15;
1331 if (count < limit)
76bc74dc
L		 1332 memcpy (fragP->fr_literal + fragP->fr_fix,
1333 patt[count - 1], count);
1334 else
1335 {
1336 memcpy (fragP->fr_literal + fragP->fr_fix,
1337 jump_31, count);
1338 /* Adjust jump offset. */
1339 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1340 }
1341 }
1342 else
1343 {
1344 /* Maximum length of an instruction is 15 byte. If the
1345 padding is greater than 15 bytes and we don't use jump,
1346 we have to break it into smaller pieces. */
1347 int padding = count;
1348 while (padding > 15)
1349 {
1350 padding -= 15;
1351 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1352 patt [14], 15);
1353 }
1354
1355 if (padding)
1356 memcpy (fragP->fr_literal + fragP->fr_fix,
1357 patt [padding - 1], padding);
1358 }
ccc9c027 1359 }
33fef721 1360 fragP->fr_var = count;
252b5132
RH		 1361}
1362
c6fb90c8 1363static INLINE int
0dfbf9d7 1364operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1365{
0dfbf9d7 1366 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1367 {
1368 case 3:
0dfbf9d7 1369 if (x->array[2])
c6fb90c8
L		 1370 return 0;
1371 case 2:
0dfbf9d7 1372 if (x->array[1])
c6fb90c8
L		 1373 return 0;
1374 case 1:
0dfbf9d7 1375 return !x->array[0];
c6fb90c8
L		 1376 default:
1377 abort ();
1378 }
40fb9820
L		 1379}
1380
c6fb90c8 1381static INLINE void
0dfbf9d7 1382operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1383{
0dfbf9d7 1384 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1385 {
1386 case 3:
0dfbf9d7 1387 x->array[2] = v;
c6fb90c8 1388 case 2:
0dfbf9d7 1389 x->array[1] = v;
c6fb90c8 1390 case 1:
0dfbf9d7 1391 x->array[0] = v;
c6fb90c8
L		 1392 break;
1393 default:
1394 abort ();
1395 }
1396}
40fb9820 1397
c6fb90c8 1398static INLINE int
0dfbf9d7
L		 1399operand_type_equal (const union i386_operand_type *x,
1400 const union i386_operand_type *y)
c6fb90c8 1401{
0dfbf9d7 1402 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1403 {
1404 case 3:
0dfbf9d7 1405 if (x->array[2] != y->array[2])
c6fb90c8
L		 1406 return 0;
1407 case 2:
0dfbf9d7 1408 if (x->array[1] != y->array[1])
c6fb90c8
L		 1409 return 0;
1410 case 1:
0dfbf9d7 1411 return x->array[0] == y->array[0];
c6fb90c8
L		 1412 break;
1413 default:
1414 abort ();
1415 }
1416}
40fb9820 1417
0dfbf9d7
L		 1418static INLINE int
1419cpu_flags_all_zero (const union i386_cpu_flags *x)
1420{
1421 switch (ARRAY_SIZE(x->array))
1422 {
1423 case 3:
1424 if (x->array[2])
1425 return 0;
1426 case 2:
1427 if (x->array[1])
1428 return 0;
1429 case 1:
1430 return !x->array[0];
1431 default:
1432 abort ();
1433 }
1434}
1435
1436static INLINE void
1437cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1438{
1439 switch (ARRAY_SIZE(x->array))
1440 {
1441 case 3:
1442 x->array[2] = v;
1443 case 2:
1444 x->array[1] = v;
1445 case 1:
1446 x->array[0] = v;
1447 break;
1448 default:
1449 abort ();
1450 }
1451}
1452
1453static INLINE int
1454cpu_flags_equal (const union i386_cpu_flags *x,
1455 const union i386_cpu_flags *y)
1456{
1457 switch (ARRAY_SIZE(x->array))
1458 {
1459 case 3:
1460 if (x->array[2] != y->array[2])
1461 return 0;
1462 case 2:
1463 if (x->array[1] != y->array[1])
1464 return 0;
1465 case 1:
1466 return x->array[0] == y->array[0];
1467 break;
1468 default:
1469 abort ();
1470 }
1471}
c6fb90c8
L		 1472
1473static INLINE int
1474cpu_flags_check_cpu64 (i386_cpu_flags f)
1475{
1476 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1477 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1478}
1479
c6fb90c8
L		 1480static INLINE i386_cpu_flags
1481cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1482{
c6fb90c8
L		 1483 switch (ARRAY_SIZE (x.array))
1484 {
1485 case 3:
1486 x.array [2] &= y.array [2];
1487 case 2:
1488 x.array [1] &= y.array [1];
1489 case 1:
1490 x.array [0] &= y.array [0];
1491 break;
1492 default:
1493 abort ();
1494 }
1495 return x;
1496}
40fb9820 1497
c6fb90c8
L		 1498static INLINE i386_cpu_flags
1499cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1500{
c6fb90c8 1501 switch (ARRAY_SIZE (x.array))
40fb9820 1502 {
c6fb90c8
L		 1503 case 3:
1504 x.array [2] |= y.array [2];
1505 case 2:
1506 x.array [1] |= y.array [1];
1507 case 1:
1508 x.array [0] |= y.array [0];
40fb9820
L		 1509 break;
1510 default:
1511 abort ();
1512 }
40fb9820
L		 1513 return x;
1514}
1515
309d3373
JB		 1516static INLINE i386_cpu_flags
1517cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1518{
1519 switch (ARRAY_SIZE (x.array))
1520 {
1521 case 3:
1522 x.array [2] &= ~y.array [2];
1523 case 2:
1524 x.array [1] &= ~y.array [1];
1525 case 1:
1526 x.array [0] &= ~y.array [0];
1527 break;
1528 default:
1529 abort ();
1530 }
1531 return x;
1532}
1533
c0f3af97
L		 1534#define CPU_FLAGS_ARCH_MATCH 0x1
1535#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1536#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1537#define CPU_FLAGS_PCLMUL_MATCH 0x8
1538#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1539
a5ff0eb2 1540#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1541 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1542 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1543#define CPU_FLAGS_PERFECT_MATCH \
1544 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1545
1546/* Return CPU flags match bits. */
3629bb00 1547
40fb9820 1548static int
d3ce72d0 1549cpu_flags_match (const insn_template *t)
40fb9820 1550{
c0f3af97
L		 1551 i386_cpu_flags x = t->cpu_flags;
1552 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1553
1554 x.bitfield.cpu64 = 0;
1555 x.bitfield.cpuno64 = 0;
1556
0dfbf9d7 1557 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1558 {
1559 /* This instruction is available on all archs. */
1560 match |= CPU_FLAGS_32BIT_MATCH;
1561 }
3629bb00
L		 1562 else
1563 {
c0f3af97 1564 /* This instruction is available only on some archs. */
3629bb00
L		 1565 i386_cpu_flags cpu = cpu_arch_flags;
1566
1567 cpu.bitfield.cpu64 = 0;
1568 cpu.bitfield.cpuno64 = 0;
1569 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1570 if (!cpu_flags_all_zero (&cpu))
1571 {
a5ff0eb2
L		 1572 if (x.bitfield.cpuavx)
1573 {
ce2f5b3c 1574 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1575 if (cpu.bitfield.cpuavx)
1576 {
1577 /* Check SSE2AVX. */
1578 if (!t->opcode_modifier.sse2avx|| sse2avx)
1579 {
1580 match |= (CPU_FLAGS_ARCH_MATCH
1581 | CPU_FLAGS_AVX_MATCH);
1582 /* Check AES. */
1583 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1584 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1585 /* Check PCLMUL. */
1586 if (!x.bitfield.cpupclmul
1587 || cpu.bitfield.cpupclmul)
1588 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1589 }
1590 }
1591 else
1592 match |= CPU_FLAGS_ARCH_MATCH;
1593 }
1594 else
c0f3af97
L		 1595 match |= CPU_FLAGS_32BIT_MATCH;
1596 }
3629bb00 1597 }
c0f3af97 1598 return match;
40fb9820
L		 1599}
1600
c6fb90c8
L		 1601static INLINE i386_operand_type
1602operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1603{
c6fb90c8
L		 1604 switch (ARRAY_SIZE (x.array))
1605 {
1606 case 3:
1607 x.array [2] &= y.array [2];
1608 case 2:
1609 x.array [1] &= y.array [1];
1610 case 1:
1611 x.array [0] &= y.array [0];
1612 break;
1613 default:
1614 abort ();
1615 }
1616 return x;
40fb9820
L		 1617}
1618
c6fb90c8
L		 1619static INLINE i386_operand_type
1620operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1621{
c6fb90c8 1622 switch (ARRAY_SIZE (x.array))
40fb9820 1623 {
c6fb90c8
L		 1624 case 3:
1625 x.array [2] |= y.array [2];
1626 case 2:
1627 x.array [1] |= y.array [1];
1628 case 1:
1629 x.array [0] |= y.array [0];
40fb9820
L		 1630 break;
1631 default:
1632 abort ();
1633 }
c6fb90c8
L		 1634 return x;
1635}
40fb9820 1636
c6fb90c8
L		 1637static INLINE i386_operand_type
1638operand_type_xor (i386_operand_type x, i386_operand_type y)
1639{
1640 switch (ARRAY_SIZE (x.array))
1641 {
1642 case 3:
1643 x.array [2] ^= y.array [2];
1644 case 2:
1645 x.array [1] ^= y.array [1];
1646 case 1:
1647 x.array [0] ^= y.array [0];
1648 break;
1649 default:
1650 abort ();
1651 }
40fb9820
L		 1652 return x;
1653}
1654
1655static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1656static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1657static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1658static const i386_operand_type inoutportreg
1659 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1660static const i386_operand_type reg16_inoutportreg
1661 = OPERAND_TYPE_REG16_INOUTPORTREG;
1662static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1663static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1664static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1665static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1666static const i386_operand_type anydisp
1667 = OPERAND_TYPE_ANYDISP;
40fb9820 1668static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1669static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1670static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1671static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1672static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1673static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1674static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1675static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1676static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1677static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1678static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1679static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1680static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1681static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1682
1683enum operand_type
1684{
1685 reg,
40fb9820
L		 1686 imm,
1687 disp,
1688 anymem
1689};
1690
c6fb90c8 1691static INLINE int
40fb9820
L		 1692operand_type_check (i386_operand_type t, enum operand_type c)
1693{
1694 switch (c)
1695 {
1696 case reg:
1697 return (t.bitfield.reg8
1698 || t.bitfield.reg16
1699 || t.bitfield.reg32
1700 || t.bitfield.reg64);
1701
40fb9820
L		 1702 case imm:
1703 return (t.bitfield.imm8
1704 || t.bitfield.imm8s
1705 || t.bitfield.imm16
1706 || t.bitfield.imm32
1707 || t.bitfield.imm32s
1708 || t.bitfield.imm64);
1709
1710 case disp:
1711 return (t.bitfield.disp8
1712 || t.bitfield.disp16
1713 || t.bitfield.disp32
1714 || t.bitfield.disp32s
1715 || t.bitfield.disp64);
1716
1717 case anymem:
1718 return (t.bitfield.disp8
1719 || t.bitfield.disp16
1720 || t.bitfield.disp32
1721 || t.bitfield.disp32s
1722 || t.bitfield.disp64
1723 || t.bitfield.baseindex);
1724
1725 default:
1726 abort ();
1727 }
2cfe26b6
AM		 1728
1729 return 0;
40fb9820
L		 1730}
1731
5c07affc
L		 1732/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1733 operand J for instruction template T. */
1734
1735static INLINE int
d3ce72d0 1736match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1737{
1738 return !((i.types[j].bitfield.byte
1739 && !t->operand_types[j].bitfield.byte)
1740 || (i.types[j].bitfield.word
1741 && !t->operand_types[j].bitfield.word)
1742 || (i.types[j].bitfield.dword
1743 && !t->operand_types[j].bitfield.dword)
1744 || (i.types[j].bitfield.qword
1745 && !t->operand_types[j].bitfield.qword));
1746}
1747
1748/* Return 1 if there is no conflict in any size on operand J for
1749 instruction template T. */
1750
1751static INLINE int
d3ce72d0 1752match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1753{
1754 return (match_reg_size (t, j)
1755 && !((i.types[j].bitfield.unspecified
1756 && !t->operand_types[j].bitfield.unspecified)
1757 || (i.types[j].bitfield.fword
1758 && !t->operand_types[j].bitfield.fword)
1759 || (i.types[j].bitfield.tbyte
1760 && !t->operand_types[j].bitfield.tbyte)
1761 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1762 && !t->operand_types[j].bitfield.xmmword)
1763 || (i.types[j].bitfield.ymmword
43234a1e
L		 1764 && !t->operand_types[j].bitfield.ymmword)
1765 || (i.types[j].bitfield.zmmword
1766 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1767}
1768
1769/* Return 1 if there is no size conflict on any operands for
1770 instruction template T. */
1771
1772static INLINE int
d3ce72d0 1773operand_size_match (const insn_template *t)
5c07affc
L		 1774{
1775 unsigned int j;
1776 int match = 1;
1777
1778 /* Don't check jump instructions. */
1779 if (t->opcode_modifier.jump
1780 || t->opcode_modifier.jumpbyte
1781 || t->opcode_modifier.jumpdword
1782 || t->opcode_modifier.jumpintersegment)
1783 return match;
1784
1785 /* Check memory and accumulator operand size. */
1786 for (j = 0; j < i.operands; j++)
1787 {
1788 if (t->operand_types[j].bitfield.anysize)
1789 continue;
1790
1791 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1792 {
1793 match = 0;
1794 break;
1795 }
1796
1797 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1798 {
1799 match = 0;
1800 break;
1801 }
1802 }
1803
891edac4 1804 if (match)
5c07affc 1805 return match;
891edac4
L		 1806 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1807 {
1808mismatch:
86e026a4 1809 i.error = operand_size_mismatch;
891edac4
L		 1810 return 0;
1811 }
5c07affc
L		 1812
1813 /* Check reverse. */
9c2799c2 1814 gas_assert (i.operands == 2);
5c07affc
L		 1815
1816 match = 1;
1817 for (j = 0; j < 2; j++)
1818 {
1819 if (t->operand_types[j].bitfield.acc
1820 && !match_reg_size (t, j ? 0 : 1))
891edac4 1821 goto mismatch;
5c07affc
L		 1822
1823 if (i.types[j].bitfield.mem
1824 && !match_mem_size (t, j ? 0 : 1))
891edac4 1825 goto mismatch;
5c07affc
L		 1826 }
1827
1828 return match;
1829}
1830
c6fb90c8 1831static INLINE int
40fb9820
L		 1832operand_type_match (i386_operand_type overlap,
1833 i386_operand_type given)
1834{
1835 i386_operand_type temp = overlap;
1836
1837 temp.bitfield.jumpabsolute = 0;
7d5e4556 1838 temp.bitfield.unspecified = 0;
5c07affc
L		 1839 temp.bitfield.byte = 0;
1840 temp.bitfield.word = 0;
1841 temp.bitfield.dword = 0;
1842 temp.bitfield.fword = 0;
1843 temp.bitfield.qword = 0;
1844 temp.bitfield.tbyte = 0;
1845 temp.bitfield.xmmword = 0;
c0f3af97 1846 temp.bitfield.ymmword = 0;
43234a1e 1847 temp.bitfield.zmmword = 0;
0dfbf9d7 1848 if (operand_type_all_zero (&temp))
891edac4 1849 goto mismatch;
40fb9820 1850
891edac4
L		 1851 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1852 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1853 return 1;
1854
1855mismatch:
a65babc9 1856 i.error = operand_type_mismatch;
891edac4 1857 return 0;
40fb9820
L		 1858}
1859
7d5e4556 1860/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1861 unless the expected operand type register overlap is null.
1862 Note that Acc in a template matches every size of reg. */
1863
c6fb90c8 1864static INLINE int
40fb9820
L		 1865operand_type_register_match (i386_operand_type m0,
1866 i386_operand_type g0,
1867 i386_operand_type t0,
1868 i386_operand_type m1,
1869 i386_operand_type g1,
1870 i386_operand_type t1)
1871{
1872 if (!operand_type_check (g0, reg))
1873 return 1;
1874
1875 if (!operand_type_check (g1, reg))
1876 return 1;
1877
1878 if (g0.bitfield.reg8 == g1.bitfield.reg8
1879 && g0.bitfield.reg16 == g1.bitfield.reg16
1880 && g0.bitfield.reg32 == g1.bitfield.reg32
1881 && g0.bitfield.reg64 == g1.bitfield.reg64)
1882 return 1;
1883
1884 if (m0.bitfield.acc)
1885 {
1886 t0.bitfield.reg8 = 1;
1887 t0.bitfield.reg16 = 1;
1888 t0.bitfield.reg32 = 1;
1889 t0.bitfield.reg64 = 1;
1890 }
1891
1892 if (m1.bitfield.acc)
1893 {
1894 t1.bitfield.reg8 = 1;
1895 t1.bitfield.reg16 = 1;
1896 t1.bitfield.reg32 = 1;
1897 t1.bitfield.reg64 = 1;
1898 }
1899
891edac4
L		 1900 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1901 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1902 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1903 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1904 return 1;
1905
a65babc9 1906 i.error = register_type_mismatch;
891edac4
L		 1907
1908 return 0;
40fb9820
L		 1909}
1910
4c692bc7
JB		 1911static INLINE unsigned int
1912register_number (const reg_entry *r)
1913{
1914 unsigned int nr = r->reg_num;
1915
1916 if (r->reg_flags & RegRex)
1917 nr += 8;
1918
1919 return nr;
1920}
1921
252b5132 1922static INLINE unsigned int
40fb9820 1923mode_from_disp_size (i386_operand_type t)
252b5132 1924{
43234a1e 1925 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1926 return 1;
1927 else if (t.bitfield.disp16
1928 || t.bitfield.disp32
1929 || t.bitfield.disp32s)
1930 return 2;
1931 else
1932 return 0;
252b5132
RH		 1933}
1934
1935static INLINE int
e3bb37b5 1936fits_in_signed_byte (offsetT num)
252b5132
RH		 1937{
1938 return (num >= -128) && (num <= 127);
47926f60 1939}
252b5132
RH		 1940
1941static INLINE int
e3bb37b5 1942fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1943{
1944 return (num & 0xff) == num;
47926f60 1945}
252b5132
RH		 1946
1947static INLINE int
e3bb37b5 1948fits_in_unsigned_word (offsetT num)
252b5132
RH		 1949{
1950 return (num & 0xffff) == num;
47926f60 1951}
252b5132
RH		 1952
1953static INLINE int
e3bb37b5 1954fits_in_signed_word (offsetT num)
252b5132
RH		 1955{
1956 return (-32768 <= num) && (num <= 32767);
47926f60 1957}
2a962e6d 1958
3e73aa7c 1959static INLINE int
e3bb37b5 1960fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1961{
1962#ifndef BFD64
1963 return 1;
1964#else
1965 return (!(((offsetT) -1 << 31) & num)
1966 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1967#endif
1968} /* fits_in_signed_long() */
2a962e6d 1969
3e73aa7c 1970static INLINE int
e3bb37b5 1971fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1972{
1973#ifndef BFD64
1974 return 1;
1975#else
1976 return (num & (((offsetT) 2 << 31) - 1)) == num;
1977#endif
1978} /* fits_in_unsigned_long() */
252b5132 1979
43234a1e
L		 1980static INLINE int
1981fits_in_vec_disp8 (offsetT num)
1982{
1983 int shift = i.memshift;
1984 unsigned int mask;
1985
1986 if (shift == -1)
1987 abort ();
1988
1989 mask = (1 << shift) - 1;
1990
1991 /* Return 0 if NUM isn't properly aligned. */
1992 if ((num & mask))
1993 return 0;
1994
1995 /* Check if NUM will fit in 8bit after shift. */
1996 return fits_in_signed_byte (num >> shift);
1997}
1998
a683cc34
SP		 1999static INLINE int
2000fits_in_imm4 (offsetT num)
2001{
2002 return (num & 0xf) == num;
2003}
2004
40fb9820 2005static i386_operand_type
e3bb37b5 2006smallest_imm_type (offsetT num)
252b5132 2007{
40fb9820 2008 i386_operand_type t;
7ab9ffdd 2009
0dfbf9d7 2010 operand_type_set (&t, 0);
40fb9820
L		 2011 t.bitfield.imm64 = 1;
2012
2013 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2014 {
2015 /* This code is disabled on the 486 because all the Imm1 forms
2016 in the opcode table are slower on the i486. They're the
2017 versions with the implicitly specified single-position
2018 displacement, which has another syntax if you really want to
2019 use that form. */
40fb9820
L		 2020 t.bitfield.imm1 = 1;
2021 t.bitfield.imm8 = 1;
2022 t.bitfield.imm8s = 1;
2023 t.bitfield.imm16 = 1;
2024 t.bitfield.imm32 = 1;
2025 t.bitfield.imm32s = 1;
2026 }
2027 else if (fits_in_signed_byte (num))
2028 {
2029 t.bitfield.imm8 = 1;
2030 t.bitfield.imm8s = 1;
2031 t.bitfield.imm16 = 1;
2032 t.bitfield.imm32 = 1;
2033 t.bitfield.imm32s = 1;
2034 }
2035 else if (fits_in_unsigned_byte (num))
2036 {
2037 t.bitfield.imm8 = 1;
2038 t.bitfield.imm16 = 1;
2039 t.bitfield.imm32 = 1;
2040 t.bitfield.imm32s = 1;
2041 }
2042 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2043 {
2044 t.bitfield.imm16 = 1;
2045 t.bitfield.imm32 = 1;
2046 t.bitfield.imm32s = 1;
2047 }
2048 else if (fits_in_signed_long (num))
2049 {
2050 t.bitfield.imm32 = 1;
2051 t.bitfield.imm32s = 1;
2052 }
2053 else if (fits_in_unsigned_long (num))
2054 t.bitfield.imm32 = 1;
2055
2056 return t;
47926f60 2057}
252b5132 2058
847f7ad4 2059static offsetT
e3bb37b5 2060offset_in_range (offsetT val, int size)
847f7ad4 2061{
508866be 2062 addressT mask;
ba2adb93 2063
847f7ad4
AM		 2064 switch (size)
2065 {
508866be
L		 2066 case 1: mask = ((addressT) 1 << 8) - 1; break;
2067 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2068 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2069#ifdef BFD64
2070 case 8: mask = ((addressT) 2 << 63) - 1; break;
2071#endif
47926f60 2072 default: abort ();
847f7ad4
AM		 2073 }
2074
9de868bf
L		 2075#ifdef BFD64
2076 /* If BFD64, sign extend val for 32bit address mode. */
2077 if (flag_code != CODE_64BIT
2078 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2079 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2080 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2081#endif
ba2adb93 2082
47926f60 2083 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2084 {
2085 char buf1[40], buf2[40];
2086
2087 sprint_value (buf1, val);
2088 sprint_value (buf2, val & mask);
2089 as_warn (_("%s shortened to %s"), buf1, buf2);
2090 }
2091 return val & mask;
2092}
2093
c32fa91d
L		 2094enum PREFIX_GROUP
2095{
2096 PREFIX_EXIST = 0,
2097 PREFIX_LOCK,
2098 PREFIX_REP,
2099 PREFIX_OTHER
2100};
2101
2102/* Returns
2103 a. PREFIX_EXIST if attempting to add a prefix where one from the
2104 same class already exists.
2105 b. PREFIX_LOCK if lock prefix is added.
2106 c. PREFIX_REP if rep/repne prefix is added.
2107 d. PREFIX_OTHER if other prefix is added.
2108 */
2109
2110static enum PREFIX_GROUP
e3bb37b5 2111add_prefix (unsigned int prefix)
252b5132 2112{
c32fa91d 2113 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2114 unsigned int q;
252b5132 2115
29b0f896
AM		 2116 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2117 && flag_code == CODE_64BIT)
b1905489 2118 {
161a04f6
L		 2119 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2120 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2121 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2122 ret = PREFIX_EXIST;
b1905489
JB		 2123 q = REX_PREFIX;
2124 }
3e73aa7c 2125 else
b1905489
JB		 2126 {
2127 switch (prefix)
2128 {
2129 default:
2130 abort ();
2131
2132 case CS_PREFIX_OPCODE:
2133 case DS_PREFIX_OPCODE:
2134 case ES_PREFIX_OPCODE:
2135 case FS_PREFIX_OPCODE:
2136 case GS_PREFIX_OPCODE:
2137 case SS_PREFIX_OPCODE:
2138 q = SEG_PREFIX;
2139 break;
2140
2141 case REPNE_PREFIX_OPCODE:
2142 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2143 q = REP_PREFIX;
2144 ret = PREFIX_REP;
2145 break;
2146
b1905489 2147 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2148 q = LOCK_PREFIX;
2149 ret = PREFIX_LOCK;
b1905489
JB		 2150 break;
2151
2152 case FWAIT_OPCODE:
2153 q = WAIT_PREFIX;
2154 break;
2155
2156 case ADDR_PREFIX_OPCODE:
2157 q = ADDR_PREFIX;
2158 break;
2159
2160 case DATA_PREFIX_OPCODE:
2161 q = DATA_PREFIX;
2162 break;
2163 }
2164 if (i.prefix[q] != 0)
c32fa91d 2165 ret = PREFIX_EXIST;
b1905489 2166 }
252b5132 2167
b1905489 2168 if (ret)
252b5132 2169 {
b1905489
JB		 2170 if (!i.prefix[q])
2171 ++i.prefixes;
2172 i.prefix[q] |= prefix;
252b5132 2173 }
b1905489
JB		 2174 else
2175 as_bad (_("same type of prefix used twice"));
252b5132 2176
252b5132
RH		 2177 return ret;
2178}
2179
2180static void
78f12dd3 2181update_code_flag (int value, int check)
eecb386c 2182{
78f12dd3
L		 2183 PRINTF_LIKE ((*as_error));
2184
1e9cc1c2 2185 flag_code = (enum flag_code) value;
40fb9820
L		 2186 if (flag_code == CODE_64BIT)
2187 {
2188 cpu_arch_flags.bitfield.cpu64 = 1;
2189 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2190 }
2191 else
2192 {
2193 cpu_arch_flags.bitfield.cpu64 = 0;
2194 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2195 }
2196 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2197 {
78f12dd3
L		 2198 if (check)
2199 as_error = as_fatal;
2200 else
2201 as_error = as_bad;
2202 (*as_error) (_("64bit mode not supported on `%s'."),
2203 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2204 }
40fb9820 2205 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2206 {
78f12dd3
L		 2207 if (check)
2208 as_error = as_fatal;
2209 else
2210 as_error = as_bad;
2211 (*as_error) (_("32bit mode not supported on `%s'."),
2212 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2213 }
eecb386c
AM		 2214 stackop_size = '\0';
2215}
2216
78f12dd3
L		 2217static void
2218set_code_flag (int value)
2219{
2220 update_code_flag (value, 0);
2221}
2222
eecb386c 2223static void
e3bb37b5 2224set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2225{
1e9cc1c2 2226 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2227 if (flag_code != CODE_16BIT)
2228 abort ();
2229 cpu_arch_flags.bitfield.cpu64 = 0;
2230 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2231 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2232}
2233
2234static void
e3bb37b5 2235set_intel_syntax (int syntax_flag)
252b5132
RH		 2236{
2237 /* Find out if register prefixing is specified. */
2238 int ask_naked_reg = 0;
2239
2240 SKIP_WHITESPACE ();
29b0f896 2241 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2242 {
2243 char *string = input_line_pointer;
2244 int e = get_symbol_end ();
2245
47926f60 2246 if (strcmp (string, "prefix") == 0)
252b5132 2247 ask_naked_reg = 1;
47926f60 2248 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2249 ask_naked_reg = -1;
2250 else
d0b47220 2251 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2252 *input_line_pointer = e;
2253 }
2254 demand_empty_rest_of_line ();
c3332e24 2255
252b5132
RH		 2256 intel_syntax = syntax_flag;
2257
2258 if (ask_naked_reg == 0)
f86103b7
AM		 2259 allow_naked_reg = (intel_syntax
2260 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2261 else
2262 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2263
ee86248c 2264 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2265
e4a3b5a4 2266 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2267 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2268 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2269}
2270
1efbbeb4
L		 2271static void
2272set_intel_mnemonic (int mnemonic_flag)
2273{
e1d4d893 2274 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2275}
2276
db51cc60
L		 2277static void
2278set_allow_index_reg (int flag)
2279{
2280 allow_index_reg = flag;
2281}
2282
cb19c032 2283static void
7bab8ab5 2284set_check (int what)
cb19c032 2285{
7bab8ab5
JB		 2286 enum check_kind *kind;
2287 const char *str;
2288
2289 if (what)
2290 {
2291 kind = &operand_check;
2292 str = "operand";
2293 }
2294 else
2295 {
2296 kind = &sse_check;
2297 str = "sse";
2298 }
2299
cb19c032
L		 2300 SKIP_WHITESPACE ();
2301
2302 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2303 {
2304 char *string = input_line_pointer;
2305 int e = get_symbol_end ();
2306
2307 if (strcmp (string, "none") == 0)
7bab8ab5 2308 *kind = check_none;
cb19c032 2309 else if (strcmp (string, "warning") == 0)
7bab8ab5 2310 *kind = check_warning;
cb19c032 2311 else if (strcmp (string, "error") == 0)
7bab8ab5 2312 *kind = check_error;
cb19c032 2313 else
7bab8ab5 2314 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2315 *input_line_pointer = e;
2316 }
2317 else
7bab8ab5 2318 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2319
2320 demand_empty_rest_of_line ();
2321}
2322
8a9036a4
L		 2323static void
2324check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2325 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2326{
2327#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2328 static const char *arch;
2329
2330 /* Intel LIOM is only supported on ELF. */
2331 if (!IS_ELF)
2332 return;
2333
2334 if (!arch)
2335 {
2336 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2337 use default_arch. */
2338 arch = cpu_arch_name;
2339 if (!arch)
2340 arch = default_arch;
2341 }
2342
3632d14b 2343 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2344 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2345 || new_flag.bitfield.cpul1om)
8a9036a4 2346 return;
76ba9986 2347
7a9068fe
L		 2348 /* If we are targeting Intel K1OM, we must enable it. */
2349 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2350 || new_flag.bitfield.cpuk1om)
2351 return;
2352
8a9036a4
L		 2353 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2354#endif
2355}
2356
e413e4e9 2357static void
e3bb37b5 2358set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2359{
47926f60 2360 SKIP_WHITESPACE ();
e413e4e9 2361
29b0f896 2362 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2363 {
2364 char *string = input_line_pointer;
2365 int e = get_symbol_end ();
91d6fa6a 2366 unsigned int j;
40fb9820 2367 i386_cpu_flags flags;
e413e4e9 2368
91d6fa6a 2369 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2370 {
91d6fa6a 2371 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2372 {
91d6fa6a 2373 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2374
5c6af06e
JB		 2375 if (*string != '.')
2376 {
91d6fa6a 2377 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2378 cpu_sub_arch_name = NULL;
91d6fa6a 2379 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2380 if (flag_code == CODE_64BIT)
2381 {
2382 cpu_arch_flags.bitfield.cpu64 = 1;
2383 cpu_arch_flags.bitfield.cpuno64 = 0;
2384 }
2385 else
2386 {
2387 cpu_arch_flags.bitfield.cpu64 = 0;
2388 cpu_arch_flags.bitfield.cpuno64 = 1;
2389 }
91d6fa6a
NC		 2390 cpu_arch_isa = cpu_arch[j].type;
2391 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2392 if (!cpu_arch_tune_set)
2393 {
2394 cpu_arch_tune = cpu_arch_isa;
2395 cpu_arch_tune_flags = cpu_arch_isa_flags;
2396 }
5c6af06e
JB		 2397 break;
2398 }
40fb9820 2399
22109423 2400 if (!cpu_arch[j].negated)
309d3373 2401 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2402 cpu_arch[j].flags);
309d3373
JB		 2403 else
2404 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2405 cpu_arch[j].flags);
0dfbf9d7 2406 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2407 {
6305a203
L		 2408 if (cpu_sub_arch_name)
2409 {
2410 char *name = cpu_sub_arch_name;
2411 cpu_sub_arch_name = concat (name,
91d6fa6a 2412 cpu_arch[j].name,
1bf57e9f 2413 (const char *) NULL);
6305a203
L		 2414 free (name);
2415 }
2416 else
91d6fa6a 2417 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2418 cpu_arch_flags = flags;
a586129e 2419 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2420 }
2421 *input_line_pointer = e;
2422 demand_empty_rest_of_line ();
2423 return;
e413e4e9
AM		 2424 }
2425 }
91d6fa6a 2426 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2427 as_bad (_("no such architecture: `%s'"), string);
2428
2429 *input_line_pointer = e;
2430 }
2431 else
2432 as_bad (_("missing cpu architecture"));
2433
fddf5b5b
AM		 2434 no_cond_jump_promotion = 0;
2435 if (*input_line_pointer == ','
29b0f896 2436 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2437 {
2438 char *string = ++input_line_pointer;
2439 int e = get_symbol_end ();
2440
2441 if (strcmp (string, "nojumps") == 0)
2442 no_cond_jump_promotion = 1;
2443 else if (strcmp (string, "jumps") == 0)
2444 ;
2445 else
2446 as_bad (_("no such architecture modifier: `%s'"), string);
2447
2448 *input_line_pointer = e;
2449 }
2450
e413e4e9
AM		 2451 demand_empty_rest_of_line ();
2452}
2453
8a9036a4
L		 2454enum bfd_architecture
2455i386_arch (void)
2456{
3632d14b 2457 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2458 {
2459 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2460 || flag_code != CODE_64BIT)
2461 as_fatal (_("Intel L1OM is 64bit ELF only"));
2462 return bfd_arch_l1om;
2463 }
7a9068fe
L		 2464 else if (cpu_arch_isa == PROCESSOR_K1OM)
2465 {
2466 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2467 || flag_code != CODE_64BIT)
2468 as_fatal (_("Intel K1OM is 64bit ELF only"));
2469 return bfd_arch_k1om;
2470 }
8a9036a4
L		 2471 else
2472 return bfd_arch_i386;
2473}
2474
b9d79e03 2475unsigned long
7016a5d5 2476i386_mach (void)
b9d79e03 2477{
351f65ca 2478 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2479 {
3632d14b 2480 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2481 {
351f65ca
L		 2482 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2483 || default_arch[6] != '\0')
8a9036a4
L		 2484 as_fatal (_("Intel L1OM is 64bit ELF only"));
2485 return bfd_mach_l1om;
2486 }
7a9068fe
L		 2487 else if (cpu_arch_isa == PROCESSOR_K1OM)
2488 {
2489 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2490 || default_arch[6] != '\0')
2491 as_fatal (_("Intel K1OM is 64bit ELF only"));
2492 return bfd_mach_k1om;
2493 }
351f65ca 2494 else if (default_arch[6] == '\0')
8a9036a4 2495 return bfd_mach_x86_64;
351f65ca
L		 2496 else
2497 return bfd_mach_x64_32;
8a9036a4 2498 }
b9d79e03
JH		 2499 else if (!strcmp (default_arch, "i386"))
2500 return bfd_mach_i386_i386;
2501 else
2b5d6a91 2502 as_fatal (_("unknown architecture"));
b9d79e03 2503}
b9d79e03 2504\f
252b5132 2505void
7016a5d5 2506md_begin (void)
252b5132
RH		 2507{
2508 const char *hash_err;
2509
47926f60 2510 /* Initialize op_hash hash table. */
252b5132
RH		 2511 op_hash = hash_new ();
2512
2513 {
d3ce72d0 2514 const insn_template *optab;
29b0f896 2515 templates *core_optab;
252b5132 2516
47926f60
KH		 2517 /* Setup for loop. */
2518 optab = i386_optab;
252b5132
RH		 2519 core_optab = (templates *) xmalloc (sizeof (templates));
2520 core_optab->start = optab;
2521
2522 while (1)
2523 {
2524 ++optab;
2525 if (optab->name == NULL
2526 || strcmp (optab->name, (optab - 1)->name) != 0)
2527 {
2528 /* different name --> ship out current template list;
47926f60 2529 add to hash table; & begin anew. */
252b5132
RH		 2530 core_optab->end = optab;
2531 hash_err = hash_insert (op_hash,
2532 (optab - 1)->name,
5a49b8ac 2533 (void *) core_optab);
252b5132
RH		 2534 if (hash_err)
2535 {
b37df7c4 2536 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2537 (optab - 1)->name,
2538 hash_err);
2539 }
2540 if (optab->name == NULL)
2541 break;
2542 core_optab = (templates *) xmalloc (sizeof (templates));
2543 core_optab->start = optab;
2544 }
2545 }
2546 }
2547
47926f60 2548 /* Initialize reg_hash hash table. */
252b5132
RH		 2549 reg_hash = hash_new ();
2550 {
29b0f896 2551 const reg_entry *regtab;
c3fe08fa 2552 unsigned int regtab_size = i386_regtab_size;
252b5132 2553
c3fe08fa 2554 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2555 {
5a49b8ac 2556 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2557 if (hash_err)
b37df7c4 2558 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2559 regtab->reg_name,
2560 hash_err);
252b5132
RH		 2561 }
2562 }
2563
47926f60 2564 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2565 {
29b0f896
AM		 2566 int c;
2567 char *p;
252b5132
RH		 2568
2569 for (c = 0; c < 256; c++)
2570 {
3882b010 2571 if (ISDIGIT (c))
252b5132
RH		 2572 {
2573 digit_chars[c] = c;
2574 mnemonic_chars[c] = c;
2575 register_chars[c] = c;
2576 operand_chars[c] = c;
2577 }
3882b010 2578 else if (ISLOWER (c))
252b5132
RH		 2579 {
2580 mnemonic_chars[c] = c;
2581 register_chars[c] = c;
2582 operand_chars[c] = c;
2583 }
3882b010 2584 else if (ISUPPER (c))
252b5132 2585 {
3882b010 2586 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2587 register_chars[c] = mnemonic_chars[c];
2588 operand_chars[c] = c;
2589 }
43234a1e
L		 2590 else if (c == '{' || c == '}')
2591 operand_chars[c] = c;
252b5132 2592
3882b010 2593 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2594 identifier_chars[c] = c;
2595 else if (c >= 128)
2596 {
2597 identifier_chars[c] = c;
2598 operand_chars[c] = c;
2599 }
2600 }
2601
2602#ifdef LEX_AT
2603 identifier_chars['@'] = '@';
32137342
NC		 2604#endif
2605#ifdef LEX_QM
2606 identifier_chars['?'] = '?';
2607 operand_chars['?'] = '?';
252b5132 2608#endif
252b5132 2609 digit_chars['-'] = '-';
c0f3af97 2610 mnemonic_chars['_'] = '_';
791fe849 2611 mnemonic_chars['-'] = '-';
0003779b 2612 mnemonic_chars['.'] = '.';
252b5132
RH		 2613 identifier_chars['_'] = '_';
2614 identifier_chars['.'] = '.';
2615
2616 for (p = operand_special_chars; *p != '\0'; p++)
2617 operand_chars[(unsigned char) *p] = *p;
2618 }
2619
a4447b93
RH		 2620 if (flag_code == CODE_64BIT)
2621 {
ca19b261
KT		 2622#if defined (OBJ_COFF) && defined (TE_PE)
2623 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2624 ? 32 : 16);
2625#else
a4447b93 2626 x86_dwarf2_return_column = 16;
ca19b261 2627#endif
61ff971f 2628 x86_cie_data_alignment = -8;
a4447b93
RH		 2629 }
2630 else
2631 {
2632 x86_dwarf2_return_column = 8;
2633 x86_cie_data_alignment = -4;
2634 }
252b5132
RH		 2635}
2636
2637void
e3bb37b5 2638i386_print_statistics (FILE *file)
252b5132
RH		 2639{
2640 hash_print_statistics (file, "i386 opcode", op_hash);
2641 hash_print_statistics (file, "i386 register", reg_hash);
2642}
2643\f
252b5132
RH		 2644#ifdef DEBUG386
2645
ce8a8b2f 2646/* Debugging routines for md_assemble. */
d3ce72d0 2647static void pte (insn_template *);
40fb9820 2648static void pt (i386_operand_type);
e3bb37b5
L		 2649static void pe (expressionS *);
2650static void ps (symbolS *);
252b5132
RH		 2651
2652static void
e3bb37b5 2653pi (char *line, i386_insn *x)
252b5132 2654{
09137c09 2655 unsigned int j;
252b5132
RH		 2656
2657 fprintf (stdout, "%s: template ", line);
2658 pte (&x->tm);
09f131f2
JH		 2659 fprintf (stdout, " address: base %s index %s scale %x\n",
2660 x->base_reg ? x->base_reg->reg_name : "none",
2661 x->index_reg ? x->index_reg->reg_name : "none",
2662 x->log2_scale_factor);
2663 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2664 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2665 fprintf (stdout, " sib: base %x index %x scale %x\n",
2666 x->sib.base, x->sib.index, x->sib.scale);
2667 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2668 (x->rex & REX_W) != 0,
2669 (x->rex & REX_R) != 0,
2670 (x->rex & REX_X) != 0,
2671 (x->rex & REX_B) != 0);
09137c09 2672 for (j = 0; j < x->operands; j++)
252b5132 2673 {
09137c09
SP		 2674 fprintf (stdout, " #%d: ", j + 1);
2675 pt (x->types[j]);
252b5132 2676 fprintf (stdout, "\n");
09137c09
SP		 2677 if (x->types[j].bitfield.reg8
2678 || x->types[j].bitfield.reg16
2679 || x->types[j].bitfield.reg32
2680 || x->types[j].bitfield.reg64
2681 || x->types[j].bitfield.regmmx
2682 || x->types[j].bitfield.regxmm
2683 || x->types[j].bitfield.regymm
43234a1e 2684 || x->types[j].bitfield.regzmm
09137c09
SP		 2685 || x->types[j].bitfield.sreg2
2686 || x->types[j].bitfield.sreg3
2687 || x->types[j].bitfield.control
2688 || x->types[j].bitfield.debug
2689 || x->types[j].bitfield.test)
2690 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2691 if (operand_type_check (x->types[j], imm))
2692 pe (x->op[j].imms);
2693 if (operand_type_check (x->types[j], disp))
2694 pe (x->op[j].disps);
252b5132
RH		 2695 }
2696}
2697
2698static void
d3ce72d0 2699pte (insn_template *t)
252b5132 2700{
09137c09 2701 unsigned int j;
252b5132 2702 fprintf (stdout, " %d operands ", t->operands);
47926f60 2703 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2704 if (t->extension_opcode != None)
2705 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2706 if (t->opcode_modifier.d)
252b5132 2707 fprintf (stdout, "D");
40fb9820 2708 if (t->opcode_modifier.w)
252b5132
RH		 2709 fprintf (stdout, "W");
2710 fprintf (stdout, "\n");
09137c09 2711 for (j = 0; j < t->operands; j++)
252b5132 2712 {
09137c09
SP		 2713 fprintf (stdout, " #%d type ", j + 1);
2714 pt (t->operand_types[j]);
252b5132
RH		 2715 fprintf (stdout, "\n");
2716 }
2717}
2718
2719static void
e3bb37b5 2720pe (expressionS *e)
252b5132 2721{
24eab124 2722 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2723 fprintf (stdout, " add_number %ld (%lx)\n",
2724 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2725 if (e->X_add_symbol)
2726 {
2727 fprintf (stdout, " add_symbol ");
2728 ps (e->X_add_symbol);
2729 fprintf (stdout, "\n");
2730 }
2731 if (e->X_op_symbol)
2732 {
2733 fprintf (stdout, " op_symbol ");
2734 ps (e->X_op_symbol);
2735 fprintf (stdout, "\n");
2736 }
2737}
2738
2739static void
e3bb37b5 2740ps (symbolS *s)
252b5132
RH		 2741{
2742 fprintf (stdout, "%s type %s%s",
2743 S_GET_NAME (s),
2744 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2745 segment_name (S_GET_SEGMENT (s)));
2746}
2747
7b81dfbb 2748static struct type_name
252b5132 2749 {
40fb9820
L		 2750 i386_operand_type mask;
2751 const char *name;
252b5132 2752 }
7b81dfbb 2753const type_names[] =
252b5132 2754{
40fb9820
L		 2755 { OPERAND_TYPE_REG8, "r8" },
2756 { OPERAND_TYPE_REG16, "r16" },
2757 { OPERAND_TYPE_REG32, "r32" },
2758 { OPERAND_TYPE_REG64, "r64" },
2759 { OPERAND_TYPE_IMM8, "i8" },
2760 { OPERAND_TYPE_IMM8, "i8s" },
2761 { OPERAND_TYPE_IMM16, "i16" },
2762 { OPERAND_TYPE_IMM32, "i32" },
2763 { OPERAND_TYPE_IMM32S, "i32s" },
2764 { OPERAND_TYPE_IMM64, "i64" },
2765 { OPERAND_TYPE_IMM1, "i1" },
2766 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2767 { OPERAND_TYPE_DISP8, "d8" },
2768 { OPERAND_TYPE_DISP16, "d16" },
2769 { OPERAND_TYPE_DISP32, "d32" },
2770 { OPERAND_TYPE_DISP32S, "d32s" },
2771 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2772 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2773 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2774 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2775 { OPERAND_TYPE_CONTROL, "control reg" },
2776 { OPERAND_TYPE_TEST, "test reg" },
2777 { OPERAND_TYPE_DEBUG, "debug reg" },
2778 { OPERAND_TYPE_FLOATREG, "FReg" },
2779 { OPERAND_TYPE_FLOATACC, "FAcc" },
2780 { OPERAND_TYPE_SREG2, "SReg2" },
2781 { OPERAND_TYPE_SREG3, "SReg3" },
2782 { OPERAND_TYPE_ACC, "Acc" },
2783 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2784 { OPERAND_TYPE_REGMMX, "rMMX" },
2785 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2786 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2787 { OPERAND_TYPE_REGZMM, "rZMM" },
2788 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2789 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2790};
2791
2792static void
40fb9820 2793pt (i386_operand_type t)
252b5132 2794{
40fb9820 2795 unsigned int j;
c6fb90c8 2796 i386_operand_type a;
252b5132 2797
40fb9820 2798 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2799 {
2800 a = operand_type_and (t, type_names[j].mask);
0349dc08 2801 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2802 fprintf (stdout, "%s, ", type_names[j].name);
2803 }
252b5132
RH		 2804 fflush (stdout);
2805}
2806
2807#endif /* DEBUG386 */
2808\f
252b5132 2809static bfd_reloc_code_real_type
3956db08 2810reloc (unsigned int size,
64e74474
AM		 2811 int pcrel,
2812 int sign,
c3320543 2813 int bnd_prefix,
64e74474 2814 bfd_reloc_code_real_type other)
252b5132 2815{
47926f60 2816 if (other != NO_RELOC)
3956db08 2817 {
91d6fa6a 2818 reloc_howto_type *rel;
3956db08
JB		 2819
2820 if (size == 8)
2821 switch (other)
2822 {
64e74474
AM		 2823 case BFD_RELOC_X86_64_GOT32:
2824 return BFD_RELOC_X86_64_GOT64;
2825 break;
2826 case BFD_RELOC_X86_64_PLTOFF64:
2827 return BFD_RELOC_X86_64_PLTOFF64;
2828 break;
2829 case BFD_RELOC_X86_64_GOTPC32:
2830 other = BFD_RELOC_X86_64_GOTPC64;
2831 break;
2832 case BFD_RELOC_X86_64_GOTPCREL:
2833 other = BFD_RELOC_X86_64_GOTPCREL64;
2834 break;
2835 case BFD_RELOC_X86_64_TPOFF32:
2836 other = BFD_RELOC_X86_64_TPOFF64;
2837 break;
2838 case BFD_RELOC_X86_64_DTPOFF32:
2839 other = BFD_RELOC_X86_64_DTPOFF64;
2840 break;
2841 default:
2842 break;
3956db08 2843 }
e05278af 2844
8ce3d284 2845#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2846 if (other == BFD_RELOC_SIZE32)
2847 {
2848 if (size == 8)
2849 return BFD_RELOC_SIZE64;
2850 if (pcrel)
2851 as_bad (_("there are no pc-relative size relocations"));
2852 }
8ce3d284 2853#endif
8fd4256d 2854
e05278af 2855 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2856 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2857 sign = -1;
2858
91d6fa6a
NC		 2859 rel = bfd_reloc_type_lookup (stdoutput, other);
2860 if (!rel)
3956db08 2861 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2862 else if (size != bfd_get_reloc_size (rel))
3956db08 2863 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2864 bfd_get_reloc_size (rel),
3956db08 2865 size);
91d6fa6a 2866 else if (pcrel && !rel->pc_relative)
3956db08 2867 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2868 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2869 && !sign)
91d6fa6a 2870 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2871 && sign > 0))
3956db08
JB		 2872 as_bad (_("relocated field and relocation type differ in signedness"));
2873 else
2874 return other;
2875 return NO_RELOC;
2876 }
252b5132
RH		 2877
2878 if (pcrel)
2879 {
3e73aa7c 2880 if (!sign)
3956db08 2881 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2882 switch (size)
2883 {
2884 case 1: return BFD_RELOC_8_PCREL;
2885 case 2: return BFD_RELOC_16_PCREL;
c3320543
L		 2886 case 4: return (bnd_prefix && object_64bit
2887 ? BFD_RELOC_X86_64_PC32_BND
2888 : BFD_RELOC_32_PCREL);
d6ab8113 2889 case 8: return BFD_RELOC_64_PCREL;
252b5132 2890 }
3956db08 2891 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2892 }
2893 else
2894 {
3956db08 2895 if (sign > 0)
e5cb08ac 2896 switch (size)
3e73aa7c
JH		 2897 {
2898 case 4: return BFD_RELOC_X86_64_32S;
2899 }
2900 else
2901 switch (size)
2902 {
2903 case 1: return BFD_RELOC_8;
2904 case 2: return BFD_RELOC_16;
2905 case 4: return BFD_RELOC_32;
2906 case 8: return BFD_RELOC_64;
2907 }
3956db08
JB		 2908 as_bad (_("cannot do %s %u byte relocation"),
2909 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2910 }
2911
0cc9e1d3 2912 return NO_RELOC;
252b5132
RH		 2913}
2914
47926f60
KH		 2915/* Here we decide which fixups can be adjusted to make them relative to
2916 the beginning of the section instead of the symbol. Basically we need
2917 to make sure that the dynamic relocations are done correctly, so in
2918 some cases we force the original symbol to be used. */
2919
252b5132 2920int
e3bb37b5 2921tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2922{
6d249963 2923#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2924 if (!IS_ELF)
31312f95
AM		 2925 return 1;
2926
a161fe53
AM		 2927 /* Don't adjust pc-relative references to merge sections in 64-bit
2928 mode. */
2929 if (use_rela_relocations
2930 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2931 && fixP->fx_pcrel)
252b5132 2932 return 0;
31312f95 2933
8d01d9a9
AJ		 2934 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2935 and changed later by validate_fix. */
2936 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2937 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2938 return 0;
2939
8fd4256d
L		 2940 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2941 for size relocations. */
2942 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2943 || fixP->fx_r_type == BFD_RELOC_SIZE64
2944 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2945 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2946 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2947 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2948 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2949 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2950 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2951 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2952 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2953 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2954 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2955 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2956 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2957 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2958 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2959 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2960 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2961 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2962 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2963 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2964 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2965 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2966 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2967 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2968 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2969 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2970 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2971 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2972 return 0;
31312f95 2973#endif
252b5132
RH		 2974 return 1;
2975}
252b5132 2976
b4cac588 2977static int
e3bb37b5 2978intel_float_operand (const char *mnemonic)
252b5132 2979{
9306ca4a
JB		 2980 /* Note that the value returned is meaningful only for opcodes with (memory)
2981 operands, hence the code here is free to improperly handle opcodes that
2982 have no operands (for better performance and smaller code). */
2983
2984 if (mnemonic[0] != 'f')
2985 return 0; /* non-math */
2986
2987 switch (mnemonic[1])
2988 {
2989 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2990 the fs segment override prefix not currently handled because no
2991 call path can make opcodes without operands get here */
2992 case 'i':
2993 return 2 /* integer op */;
2994 case 'l':
2995 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2996 return 3; /* fldcw/fldenv */
2997 break;
2998 case 'n':
2999 if (mnemonic[2] != 'o' /* fnop */)
3000 return 3; /* non-waiting control op */
3001 break;
3002 case 'r':
3003 if (mnemonic[2] == 's')
3004 return 3; /* frstor/frstpm */
3005 break;
3006 case 's':
3007 if (mnemonic[2] == 'a')
3008 return 3; /* fsave */
3009 if (mnemonic[2] == 't')
3010 {
3011 switch (mnemonic[3])
3012 {
3013 case 'c': /* fstcw */
3014 case 'd': /* fstdw */
3015 case 'e': /* fstenv */
3016 case 's': /* fsts[gw] */
3017 return 3;
3018 }
3019 }
3020 break;
3021 case 'x':
3022 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3023 return 0; /* fxsave/fxrstor are not really math ops */
3024 break;
3025 }
252b5132 3026
9306ca4a 3027 return 1;
252b5132
RH		 3028}
3029
c0f3af97
L		 3030/* Build the VEX prefix. */
3031
3032static void
d3ce72d0 3033build_vex_prefix (const insn_template *t)
c0f3af97
L		 3034{
3035 unsigned int register_specifier;
3036 unsigned int implied_prefix;
3037 unsigned int vector_length;
3038
3039 /* Check register specifier. */
3040 if (i.vex.register_specifier)
43234a1e
L		 3041 {
3042 register_specifier =
3043 ~register_number (i.vex.register_specifier) & 0xf;
3044 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3045 }
c0f3af97
L		 3046 else
3047 register_specifier = 0xf;
3048
fa99fab2
L		 3049 /* Use 2-byte VEX prefix by swappping destination and source
3050 operand. */
3051 if (!i.swap_operand
3052 && i.operands == i.reg_operands
7f399153 3053 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3054 && i.tm.opcode_modifier.s
3055 && i.rex == REX_B)
3056 {
3057 unsigned int xchg = i.operands - 1;
3058 union i386_op temp_op;
3059 i386_operand_type temp_type;
3060
3061 temp_type = i.types[xchg];
3062 i.types[xchg] = i.types[0];
3063 i.types[0] = temp_type;
3064 temp_op = i.op[xchg];
3065 i.op[xchg] = i.op[0];
3066 i.op[0] = temp_op;
3067
9c2799c2 3068 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3069
3070 i.rex = REX_R;
3071 xchg = i.rm.regmem;
3072 i.rm.regmem = i.rm.reg;
3073 i.rm.reg = xchg;
3074
3075 /* Use the next insn. */
3076 i.tm = t[1];
3077 }
3078
539f890d
L		 3079 if (i.tm.opcode_modifier.vex == VEXScalar)
3080 vector_length = avxscalar;
3081 else
3082 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3083
3084 switch ((i.tm.base_opcode >> 8) & 0xff)
3085 {
3086 case 0:
3087 implied_prefix = 0;
3088 break;
3089 case DATA_PREFIX_OPCODE:
3090 implied_prefix = 1;
3091 break;
3092 case REPE_PREFIX_OPCODE:
3093 implied_prefix = 2;
3094 break;
3095 case REPNE_PREFIX_OPCODE:
3096 implied_prefix = 3;
3097 break;
3098 default:
3099 abort ();
3100 }
3101
3102 /* Use 2-byte VEX prefix if possible. */
7f399153 3103 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3104 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3105 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3106 {
3107 /* 2-byte VEX prefix. */
3108 unsigned int r;
3109
3110 i.vex.length = 2;
3111 i.vex.bytes[0] = 0xc5;
3112
3113 /* Check the REX.R bit. */
3114 r = (i.rex & REX_R) ? 0 : 1;
3115 i.vex.bytes[1] = (r << 7
3116 | register_specifier << 3
3117 | vector_length << 2
3118 | implied_prefix);
3119 }
3120 else
3121 {
3122 /* 3-byte VEX prefix. */
3123 unsigned int m, w;
3124
f88c9eb0 3125 i.vex.length = 3;
f88c9eb0 3126
7f399153 3127 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3128 {
7f399153
L		 3129 case VEX0F:
3130 m = 0x1;
80de6e00 3131 i.vex.bytes[0] = 0xc4;
7f399153
L		 3132 break;
3133 case VEX0F38:
3134 m = 0x2;
80de6e00 3135 i.vex.bytes[0] = 0xc4;
7f399153
L		 3136 break;
3137 case VEX0F3A:
3138 m = 0x3;
80de6e00 3139 i.vex.bytes[0] = 0xc4;
7f399153
L		 3140 break;
3141 case XOP08:
5dd85c99
SP		 3142 m = 0x8;
3143 i.vex.bytes[0] = 0x8f;
7f399153
L		 3144 break;
3145 case XOP09:
f88c9eb0
SP		 3146 m = 0x9;
3147 i.vex.bytes[0] = 0x8f;
7f399153
L		 3148 break;
3149 case XOP0A:
f88c9eb0
SP		 3150 m = 0xa;
3151 i.vex.bytes[0] = 0x8f;
7f399153
L		 3152 break;
3153 default:
3154 abort ();
f88c9eb0 3155 }
c0f3af97 3156
c0f3af97
L		 3157 /* The high 3 bits of the second VEX byte are 1's compliment
3158 of RXB bits from REX. */
3159 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3160
3161 /* Check the REX.W bit. */
3162 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 3163 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 3164 {
3165 if (w)
3166 abort ();
3167
1ef99a7b 3168 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 3169 w = 1;
3170 }
3171
3172 i.vex.bytes[2] = (w << 7
3173 | register_specifier << 3
3174 | vector_length << 2
3175 | implied_prefix);
3176 }
3177}
3178
43234a1e
L		 3179/* Build the EVEX prefix. */
3180
3181static void
3182build_evex_prefix (void)
3183{
3184 unsigned int register_specifier;
3185 unsigned int implied_prefix;
3186 unsigned int m, w;
3187 rex_byte vrex_used = 0;
3188
3189 /* Check register specifier. */
3190 if (i.vex.register_specifier)
3191 {
3192 gas_assert ((i.vrex & REX_X) == 0);
3193
3194 register_specifier = i.vex.register_specifier->reg_num;
3195 if ((i.vex.register_specifier->reg_flags & RegRex))
3196 register_specifier += 8;
3197 /* The upper 16 registers are encoded in the fourth byte of the
3198 EVEX prefix. */
3199 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3200 i.vex.bytes[3] = 0x8;
3201 register_specifier = ~register_specifier & 0xf;
3202 }
3203 else
3204 {
3205 register_specifier = 0xf;
3206
3207 /* Encode upper 16 vector index register in the fourth byte of
3208 the EVEX prefix. */
3209 if (!(i.vrex & REX_X))
3210 i.vex.bytes[3] = 0x8;
3211 else
3212 vrex_used |= REX_X;
3213 }
3214
3215 switch ((i.tm.base_opcode >> 8) & 0xff)
3216 {
3217 case 0:
3218 implied_prefix = 0;
3219 break;
3220 case DATA_PREFIX_OPCODE:
3221 implied_prefix = 1;
3222 break;
3223 case REPE_PREFIX_OPCODE:
3224 implied_prefix = 2;
3225 break;
3226 case REPNE_PREFIX_OPCODE:
3227 implied_prefix = 3;
3228 break;
3229 default:
3230 abort ();
3231 }
3232
3233 /* 4 byte EVEX prefix. */
3234 i.vex.length = 4;
3235 i.vex.bytes[0] = 0x62;
3236
3237 /* mmmm bits. */
3238 switch (i.tm.opcode_modifier.vexopcode)
3239 {
3240 case VEX0F:
3241 m = 1;
3242 break;
3243 case VEX0F38:
3244 m = 2;
3245 break;
3246 case VEX0F3A:
3247 m = 3;
3248 break;
3249 default:
3250 abort ();
3251 break;
3252 }
3253
3254 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3255 bits from REX. */
3256 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3257
3258 /* The fifth bit of the second EVEX byte is 1's compliment of the
3259 REX_R bit in VREX. */
3260 if (!(i.vrex & REX_R))
3261 i.vex.bytes[1] |= 0x10;
3262 else
3263 vrex_used |= REX_R;
3264
3265 if ((i.reg_operands + i.imm_operands) == i.operands)
3266 {
3267 /* When all operands are registers, the REX_X bit in REX is not
3268 used. We reuse it to encode the upper 16 registers, which is
3269 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3270 as 1's compliment. */
3271 if ((i.vrex & REX_B))
3272 {
3273 vrex_used |= REX_B;
3274 i.vex.bytes[1] &= ~0x40;
3275 }
3276 }
3277
3278 /* EVEX instructions shouldn't need the REX prefix. */
3279 i.vrex &= ~vrex_used;
3280 gas_assert (i.vrex == 0);
3281
3282 /* Check the REX.W bit. */
3283 w = (i.rex & REX_W) ? 1 : 0;
3284 if (i.tm.opcode_modifier.vexw)
3285 {
3286 if (i.tm.opcode_modifier.vexw == VEXW1)
3287 w = 1;
3288 }
3289 /* If w is not set it means we are dealing with WIG instruction. */
3290 else if (!w)
3291 {
3292 if (evexwig == evexw1)
3293 w = 1;
3294 }
3295
3296 /* Encode the U bit. */
3297 implied_prefix |= 0x4;
3298
3299 /* The third byte of the EVEX prefix. */
3300 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3301
3302 /* The fourth byte of the EVEX prefix. */
3303 /* The zeroing-masking bit. */
3304 if (i.mask && i.mask->zeroing)
3305 i.vex.bytes[3] |= 0x80;
3306
3307 /* Don't always set the broadcast bit if there is no RC. */
3308 if (!i.rounding)
3309 {
3310 /* Encode the vector length. */
3311 unsigned int vec_length;
3312
3313 switch (i.tm.opcode_modifier.evex)
3314 {
3315 case EVEXLIG: /* LL' is ignored */
3316 vec_length = evexlig << 5;
3317 break;
3318 case EVEX128:
3319 vec_length = 0 << 5;
3320 break;
3321 case EVEX256:
3322 vec_length = 1 << 5;
3323 break;
3324 case EVEX512:
3325 vec_length = 2 << 5;
3326 break;
3327 default:
3328 abort ();
3329 break;
3330 }
3331 i.vex.bytes[3] |= vec_length;
3332 /* Encode the broadcast bit. */
3333 if (i.broadcast)
3334 i.vex.bytes[3] |= 0x10;
3335 }
3336 else
3337 {
3338 if (i.rounding->type != saeonly)
3339 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3340 else
3341 i.vex.bytes[3] |= 0x10;
3342 }
3343
3344 if (i.mask && i.mask->mask)
3345 i.vex.bytes[3] |= i.mask->mask->reg_num;
3346}
3347
65da13b5
L		 3348static void
3349process_immext (void)
3350{
3351 expressionS *exp;
3352
4c692bc7
JB		 3353 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3354 && i.operands > 0)
65da13b5 3355 {
4c692bc7
JB		 3356 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3357 with an opcode suffix which is coded in the same place as an
3358 8-bit immediate field would be.
3359 Here we check those operands and remove them afterwards. */
65da13b5
L		 3360 unsigned int x;
3361
3362 for (x = 0; x < i.operands; x++)
4c692bc7 3363 if (register_number (i.op[x].regs) != x)
65da13b5 3364 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3365 register_prefix, i.op[x].regs->reg_name, x + 1,
3366 i.tm.name);
3367
3368 i.operands = 0;
65da13b5
L		 3369 }
3370
c0f3af97 3371 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3372 which is coded in the same place as an 8-bit immediate field
3373 would be. Here we fake an 8-bit immediate operand from the
3374 opcode suffix stored in tm.extension_opcode.
3375
c1e679ec 3376 AVX instructions also use this encoding, for some of
c0f3af97 3377 3 argument instructions. */
65da13b5 3378
43234a1e 3379 gas_assert (i.imm_operands <= 1
7ab9ffdd 3380 && (i.operands <= 2
43234a1e
L		 3381 || ((i.tm.opcode_modifier.vex
3382 || i.tm.opcode_modifier.evex)
7ab9ffdd 3383 && i.operands <= 4)));
65da13b5
L		 3384
3385 exp = &im_expressions[i.imm_operands++];
3386 i.op[i.operands].imms = exp;
3387 i.types[i.operands] = imm8;
3388 i.operands++;
3389 exp->X_op = O_constant;
3390 exp->X_add_number = i.tm.extension_opcode;
3391 i.tm.extension_opcode = None;
3392}
3393
42164a71
L		 3394
3395static int
3396check_hle (void)
3397{
3398 switch (i.tm.opcode_modifier.hleprefixok)
3399 {
3400 default:
3401 abort ();
82c2def5 3402 case HLEPrefixNone:
165de32a
L		 3403 as_bad (_("invalid instruction `%s' after `%s'"),
3404 i.tm.name, i.hle_prefix);
42164a71 3405 return 0;
82c2def5 3406 case HLEPrefixLock:
42164a71
L		 3407 if (i.prefix[LOCK_PREFIX])
3408 return 1;
165de32a 3409 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3410 return 0;
82c2def5 3411 case HLEPrefixAny:
42164a71 3412 return 1;
82c2def5 3413 case HLEPrefixRelease:
42164a71
L		 3414 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3415 {
3416 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3417 i.tm.name);
3418 return 0;
3419 }
3420 if (i.mem_operands == 0
3421 || !operand_type_check (i.types[i.operands - 1], anymem))
3422 {
3423 as_bad (_("memory destination needed for instruction `%s'"
3424 " after `xrelease'"), i.tm.name);
3425 return 0;
3426 }
3427 return 1;
3428 }
3429}
3430
252b5132
RH		 3431/* This is the guts of the machine-dependent assembler. LINE points to a
3432 machine dependent instruction. This function is supposed to emit
3433 the frags/bytes it assembles to. */
3434
3435void
65da13b5 3436md_assemble (char *line)
252b5132 3437{
40fb9820 3438 unsigned int j;
252b5132 3439 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3440 const insn_template *t;
252b5132 3441
47926f60 3442 /* Initialize globals. */
252b5132
RH		 3443 memset (&i, '\0', sizeof (i));
3444 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3445 i.reloc[j] = NO_RELOC;
252b5132
RH		 3446 memset (disp_expressions, '\0', sizeof (disp_expressions));
3447 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3448 save_stack_p = save_stack;
252b5132
RH		 3449
3450 /* First parse an instruction mnemonic & call i386_operand for the operands.
3451 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3452 start of a (possibly prefixed) mnemonic. */
252b5132 3453
29b0f896
AM		 3454 line = parse_insn (line, mnemonic);
3455 if (line == NULL)
3456 return;
252b5132 3457
29b0f896 3458 line = parse_operands (line, mnemonic);
ee86248c 3459 this_operand = -1;
29b0f896
AM		 3460 if (line == NULL)
3461 return;
252b5132 3462
29b0f896
AM		 3463 /* Now we've parsed the mnemonic into a set of templates, and have the
3464 operands at hand. */
3465
3466 /* All intel opcodes have reversed operands except for "bound" and
3467 "enter". We also don't reverse intersegment "jmp" and "call"
3468 instructions with 2 immediate operands so that the immediate segment
050dfa73 3469 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3470 if (intel_syntax
3471 && i.operands > 1
29b0f896 3472 && (strcmp (mnemonic, "bound") != 0)
30123838 3473 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3474 && !(operand_type_check (i.types[0], imm)
3475 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3476 swap_operands ();
3477
ec56d5c0
JB		 3478 /* The order of the immediates should be reversed
3479 for 2 immediates extrq and insertq instructions */
3480 if (i.imm_operands == 2
3481 && (strcmp (mnemonic, "extrq") == 0
3482 || strcmp (mnemonic, "insertq") == 0))
3483 swap_2_operands (0, 1);
3484
29b0f896
AM		 3485 if (i.imm_operands)
3486 optimize_imm ();
3487
b300c311
L		 3488 /* Don't optimize displacement for movabs since it only takes 64bit
3489 displacement. */
3490 if (i.disp_operands
a501d77e 3491 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3492 && (flag_code != CODE_64BIT
3493 || strcmp (mnemonic, "movabs") != 0))
3494 optimize_disp ();
29b0f896
AM		 3495
3496 /* Next, we find a template that matches the given insn,
3497 making sure the overlap of the given operands types is consistent
3498 with the template operand types. */
252b5132 3499
fa99fab2 3500 if (!(t = match_template ()))
29b0f896 3501 return;
252b5132 3502
7bab8ab5 3503 if (sse_check != check_none
81f8a913 3504 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3505 && (i.tm.cpu_flags.bitfield.cpusse
3506 || i.tm.cpu_flags.bitfield.cpusse2
3507 || i.tm.cpu_flags.bitfield.cpusse3
3508 || i.tm.cpu_flags.bitfield.cpussse3
3509 || i.tm.cpu_flags.bitfield.cpusse4_1
3510 || i.tm.cpu_flags.bitfield.cpusse4_2))
3511 {
7bab8ab5 3512 (sse_check == check_warning
daf50ae7
L		 3513 ? as_warn
3514 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3515 }
3516
321fd21e
L		 3517 /* Zap movzx and movsx suffix. The suffix has been set from
3518 "word ptr" or "byte ptr" on the source operand in Intel syntax
3519 or extracted from mnemonic in AT&T syntax. But we'll use
3520 the destination register to choose the suffix for encoding. */
3521 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3522 {
321fd21e
L		 3523 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3524 there is no suffix, the default will be byte extension. */
3525 if (i.reg_operands != 2
3526 && !i.suffix
7ab9ffdd 3527 && intel_syntax)
321fd21e
L		 3528 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3529
3530 i.suffix = 0;
cd61ebfe 3531 }
24eab124 3532
40fb9820 3533 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3534 if (!add_prefix (FWAIT_OPCODE))
3535 return;
252b5132 3536
d5de92cf
L		 3537 /* Check if REP prefix is OK. */
3538 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3539 {
3540 as_bad (_("invalid instruction `%s' after `%s'"),
3541 i.tm.name, i.rep_prefix);
3542 return;
3543 }
3544
c1ba0266
L		 3545 /* Check for lock without a lockable instruction. Destination operand
3546 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3547 if (i.prefix[LOCK_PREFIX]
3548 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3549 || i.mem_operands == 0
3550 || (i.tm.base_opcode != 0x86
3551 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3552 {
3553 as_bad (_("expecting lockable instruction after `lock'"));
3554 return;
3555 }
3556
42164a71 3557 /* Check if HLE prefix is OK. */
165de32a 3558 if (i.hle_prefix && !check_hle ())
42164a71
L		 3559 return;
3560
7e8b059b
L		 3561 /* Check BND prefix. */
3562 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3563 as_bad (_("expecting valid branch instruction after `bnd'"));
3564
3565 if (i.tm.cpu_flags.bitfield.cpumpx
3566 && flag_code == CODE_64BIT
3567 && i.prefix[ADDR_PREFIX])
3568 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3569
3570 /* Insert BND prefix. */
3571 if (add_bnd_prefix
3572 && i.tm.opcode_modifier.bndprefixok
3573 && !i.prefix[BND_PREFIX])
3574 add_prefix (BND_PREFIX_OPCODE);
3575
29b0f896 3576 /* Check string instruction segment overrides. */
40fb9820 3577 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3578 {
3579 if (!check_string ())
5dd0794d 3580 return;
fc0763e6 3581 i.disp_operands = 0;
29b0f896 3582 }
5dd0794d 3583
29b0f896
AM		 3584 if (!process_suffix ())
3585 return;
e413e4e9 3586
bc0844ae
L		 3587 /* Update operand types. */
3588 for (j = 0; j < i.operands; j++)
3589 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3590
29b0f896
AM		 3591 /* Make still unresolved immediate matches conform to size of immediate
3592 given in i.suffix. */
3593 if (!finalize_imm ())
3594 return;
252b5132 3595
40fb9820 3596 if (i.types[0].bitfield.imm1)
29b0f896 3597 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3598
9afe6eb8
L		 3599 /* We only need to check those implicit registers for instructions
3600 with 3 operands or less. */
3601 if (i.operands <= 3)
3602 for (j = 0; j < i.operands; j++)
3603 if (i.types[j].bitfield.inoutportreg
3604 || i.types[j].bitfield.shiftcount
3605 || i.types[j].bitfield.acc
3606 || i.types[j].bitfield.floatacc)
3607 i.reg_operands--;
40fb9820 3608
c0f3af97
L		 3609 /* ImmExt should be processed after SSE2AVX. */
3610 if (!i.tm.opcode_modifier.sse2avx
3611 && i.tm.opcode_modifier.immext)
65da13b5 3612 process_immext ();
252b5132 3613
29b0f896
AM		 3614 /* For insns with operands there are more diddles to do to the opcode. */
3615 if (i.operands)
3616 {
3617 if (!process_operands ())
3618 return;
3619 }
40fb9820 3620 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3621 {
3622 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3623 as_warn (_("translating to `%sp'"), i.tm.name);
3624 }
252b5132 3625
c0f3af97 3626 if (i.tm.opcode_modifier.vex)
fa99fab2 3627 build_vex_prefix (t);
c0f3af97 3628
43234a1e
L		 3629 if (i.tm.opcode_modifier.evex)
3630 build_evex_prefix ();
3631
5dd85c99
SP		 3632 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3633 instructions may define INT_OPCODE as well, so avoid this corner
3634 case for those instructions that use MODRM. */
3635 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3636 && !i.tm.opcode_modifier.modrm
3637 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3638 {
3639 i.tm.base_opcode = INT3_OPCODE;
3640 i.imm_operands = 0;
3641 }
252b5132 3642
40fb9820
L		 3643 if ((i.tm.opcode_modifier.jump
3644 || i.tm.opcode_modifier.jumpbyte
3645 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3646 && i.op[0].disps->X_op == O_constant)
3647 {
3648 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3649 the absolute address given by the constant. Since ix86 jumps and
3650 calls are pc relative, we need to generate a reloc. */
3651 i.op[0].disps->X_add_symbol = &abs_symbol;
3652 i.op[0].disps->X_op = O_symbol;
3653 }
252b5132 3654
40fb9820 3655 if (i.tm.opcode_modifier.rex64)
161a04f6 3656 i.rex |= REX_W;
252b5132 3657
29b0f896
AM		 3658 /* For 8 bit registers we need an empty rex prefix. Also if the
3659 instruction already has a prefix, we need to convert old
3660 registers to new ones. */
773f551c 3661
40fb9820 3662 if ((i.types[0].bitfield.reg8
29b0f896 3663 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3664 || (i.types[1].bitfield.reg8
29b0f896 3665 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3666 || ((i.types[0].bitfield.reg8
3667 || i.types[1].bitfield.reg8)
29b0f896
AM		 3668 && i.rex != 0))
3669 {
3670 int x;
726c5dcd 3671
29b0f896
AM		 3672 i.rex |= REX_OPCODE;
3673 for (x = 0; x < 2; x++)
3674 {
3675 /* Look for 8 bit operand that uses old registers. */
40fb9820 3676 if (i.types[x].bitfield.reg8
29b0f896 3677 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3678 {
29b0f896
AM		 3679 /* In case it is "hi" register, give up. */
3680 if (i.op[x].regs->reg_num > 3)
a540244d 3681 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3682 "instruction requiring REX prefix."),
a540244d 3683 register_prefix, i.op[x].regs->reg_name);
773f551c 3684
29b0f896
AM		 3685 /* Otherwise it is equivalent to the extended register.
3686 Since the encoding doesn't change this is merely
3687 cosmetic cleanup for debug output. */
3688
3689 i.op[x].regs = i.op[x].regs + 8;
773f551c 3690 }
29b0f896
AM		 3691 }
3692 }
773f551c 3693
7ab9ffdd 3694 if (i.rex != 0)
29b0f896
AM		 3695 add_prefix (REX_OPCODE | i.rex);
3696
3697 /* We are ready to output the insn. */
3698 output_insn ();
3699}
3700
3701static char *
e3bb37b5 3702parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3703{
3704 char *l = line;
3705 char *token_start = l;
3706 char *mnem_p;
5c6af06e 3707 int supported;
d3ce72d0 3708 const insn_template *t;
b6169b20 3709 char *dot_p = NULL;
29b0f896 3710
29b0f896
AM		 3711 while (1)
3712 {
3713 mnem_p = mnemonic;
3714 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3715 {
b6169b20
L		 3716 if (*mnem_p == '.')
3717 dot_p = mnem_p;
29b0f896
AM		 3718 mnem_p++;
3719 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3720 {
29b0f896
AM		 3721 as_bad (_("no such instruction: `%s'"), token_start);
3722 return NULL;
3723 }
3724 l++;
3725 }
3726 if (!is_space_char (*l)
3727 && *l != END_OF_INSN
e44823cf
JB		 3728 && (intel_syntax
3729 || (*l != PREFIX_SEPARATOR
3730 && *l != ',')))
29b0f896
AM		 3731 {
3732 as_bad (_("invalid character %s in mnemonic"),
3733 output_invalid (*l));
3734 return NULL;
3735 }
3736 if (token_start == l)
3737 {
e44823cf 3738 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3739 as_bad (_("expecting prefix; got nothing"));
3740 else
3741 as_bad (_("expecting mnemonic; got nothing"));
3742 return NULL;
3743 }
45288df1 3744
29b0f896 3745 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3746 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3747
29b0f896
AM		 3748 if (*l != END_OF_INSN
3749 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3750 && current_templates
40fb9820 3751 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3752 {
c6fb90c8 3753 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3754 {
3755 as_bad ((flag_code != CODE_64BIT
3756 ? _("`%s' is only supported in 64-bit mode")
3757 : _("`%s' is not supported in 64-bit mode")),
3758 current_templates->start->name);
3759 return NULL;
3760 }
29b0f896
AM		 3761 /* If we are in 16-bit mode, do not allow addr16 or data16.
3762 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3763 if ((current_templates->start->opcode_modifier.size16
3764 || current_templates->start->opcode_modifier.size32)
29b0f896 3765 && flag_code != CODE_64BIT
40fb9820 3766 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3767 ^ (flag_code == CODE_16BIT)))
3768 {
3769 as_bad (_("redundant %s prefix"),
3770 current_templates->start->name);
3771 return NULL;
45288df1 3772 }
29b0f896
AM		 3773 /* Add prefix, checking for repeated prefixes. */
3774 switch (add_prefix (current_templates->start->base_opcode))
3775 {
c32fa91d 3776 case PREFIX_EXIST:
29b0f896 3777 return NULL;
c32fa91d 3778 case PREFIX_REP:
42164a71 3779 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3780 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3781 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3782 i.bnd_prefix = current_templates->start->name;
42164a71 3783 else
d5de92cf 3784 i.rep_prefix = current_templates->start->name;
29b0f896 3785 break;
c32fa91d
L		 3786 default:
3787 break;
29b0f896
AM		 3788 }
3789 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3790 token_start = ++l;
3791 }
3792 else
3793 break;
3794 }
45288df1 3795
30a55f88 3796 if (!current_templates)
b6169b20 3797 {
f8a5c266
L		 3798 /* Check if we should swap operand or force 32bit displacement in
3799 encoding. */
30a55f88
L		 3800 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3801 i.swap_operand = 1;
8d63c93e 3802 else if (mnem_p - 3 == dot_p
a501d77e
L		 3803 && dot_p[1] == 'd'
3804 && dot_p[2] == '8')
3805 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3806 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3807 && dot_p[1] == 'd'
3808 && dot_p[2] == '3'
3809 && dot_p[3] == '2')
a501d77e 3810 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3811 else
3812 goto check_suffix;
3813 mnem_p = dot_p;
3814 *dot_p = '\0';
d3ce72d0 3815 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3816 }
3817
29b0f896
AM		 3818 if (!current_templates)
3819 {
b6169b20 3820check_suffix:
29b0f896
AM		 3821 /* See if we can get a match by trimming off a suffix. */
3822 switch (mnem_p[-1])
3823 {
3824 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3825 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3826 i.suffix = SHORT_MNEM_SUFFIX;
3827 else
29b0f896
AM		 3828 case BYTE_MNEM_SUFFIX:
3829 case QWORD_MNEM_SUFFIX:
3830 i.suffix = mnem_p[-1];
3831 mnem_p[-1] = '\0';
d3ce72d0
NC		 3832 current_templates = (const templates *) hash_find (op_hash,
3833 mnemonic);
29b0f896
AM		 3834 break;
3835 case SHORT_MNEM_SUFFIX:
3836 case LONG_MNEM_SUFFIX:
3837 if (!intel_syntax)
3838 {
3839 i.suffix = mnem_p[-1];
3840 mnem_p[-1] = '\0';
d3ce72d0
NC		 3841 current_templates = (const templates *) hash_find (op_hash,
3842 mnemonic);
29b0f896
AM		 3843 }
3844 break;
252b5132 3845
29b0f896
AM		 3846 /* Intel Syntax. */
3847 case 'd':
3848 if (intel_syntax)
3849 {
9306ca4a 3850 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3851 i.suffix = SHORT_MNEM_SUFFIX;
3852 else
3853 i.suffix = LONG_MNEM_SUFFIX;
3854 mnem_p[-1] = '\0';
d3ce72d0
NC		 3855 current_templates = (const templates *) hash_find (op_hash,
3856 mnemonic);
29b0f896
AM		 3857 }
3858 break;
3859 }
3860 if (!current_templates)
3861 {
3862 as_bad (_("no such instruction: `%s'"), token_start);
3863 return NULL;
3864 }
3865 }
252b5132 3866
40fb9820
L		 3867 if (current_templates->start->opcode_modifier.jump
3868 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3869 {
3870 /* Check for a branch hint. We allow ",pt" and ",pn" for
3871 predict taken and predict not taken respectively.
3872 I'm not sure that branch hints actually do anything on loop
3873 and jcxz insns (JumpByte) for current Pentium4 chips. They
3874 may work in the future and it doesn't hurt to accept them
3875 now. */
3876 if (l[0] == ',' && l[1] == 'p')
3877 {
3878 if (l[2] == 't')
3879 {
3880 if (!add_prefix (DS_PREFIX_OPCODE))
3881 return NULL;
3882 l += 3;
3883 }
3884 else if (l[2] == 'n')
3885 {
3886 if (!add_prefix (CS_PREFIX_OPCODE))
3887 return NULL;
3888 l += 3;
3889 }
3890 }
3891 }
3892 /* Any other comma loses. */
3893 if (*l == ',')
3894 {
3895 as_bad (_("invalid character %s in mnemonic"),
3896 output_invalid (*l));
3897 return NULL;
3898 }
252b5132 3899
29b0f896 3900 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3901 supported = 0;
3902 for (t = current_templates->start; t < current_templates->end; ++t)
3903 {
c0f3af97
L		 3904 supported |= cpu_flags_match (t);
3905 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3906 goto skip;
5c6af06e 3907 }
3629bb00 3908
c0f3af97 3909 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3910 {
3911 as_bad (flag_code == CODE_64BIT
3912 ? _("`%s' is not supported in 64-bit mode")
3913 : _("`%s' is only supported in 64-bit mode"),
3914 current_templates->start->name);
3915 return NULL;
3916 }
c0f3af97 3917 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3918 {
3629bb00 3919 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3920 current_templates->start->name,
41aacd83 3921 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3922 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3923 return NULL;
29b0f896 3924 }
3629bb00
L		 3925
3926skip:
3927 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3928 && (flag_code != CODE_16BIT))
29b0f896
AM		 3929 {
3930 as_warn (_("use .code16 to ensure correct addressing mode"));
3931 }
252b5132 3932
29b0f896
AM		 3933 return l;
3934}
252b5132 3935
29b0f896 3936static char *
e3bb37b5 3937parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3938{
3939 char *token_start;
3138f287 3940
29b0f896
AM		 3941 /* 1 if operand is pending after ','. */
3942 unsigned int expecting_operand = 0;
252b5132 3943
29b0f896
AM		 3944 /* Non-zero if operand parens not balanced. */
3945 unsigned int paren_not_balanced;
3946
3947 while (*l != END_OF_INSN)
3948 {
3949 /* Skip optional white space before operand. */
3950 if (is_space_char (*l))
3951 ++l;
3952 if (!is_operand_char (*l) && *l != END_OF_INSN)
3953 {
3954 as_bad (_("invalid character %s before operand %d"),
3955 output_invalid (*l),
3956 i.operands + 1);
3957 return NULL;
3958 }
3959 token_start = l; /* after white space */
3960 paren_not_balanced = 0;
3961 while (paren_not_balanced || *l != ',')
3962 {
3963 if (*l == END_OF_INSN)
3964 {
3965 if (paren_not_balanced)
3966 {
3967 if (!intel_syntax)
3968 as_bad (_("unbalanced parenthesis in operand %d."),
3969 i.operands + 1);
3970 else
3971 as_bad (_("unbalanced brackets in operand %d."),
3972 i.operands + 1);
3973 return NULL;
3974 }
3975 else
3976 break; /* we are done */
3977 }
3978 else if (!is_operand_char (*l) && !is_space_char (*l))
3979 {
3980 as_bad (_("invalid character %s in operand %d"),
3981 output_invalid (*l),
3982 i.operands + 1);
3983 return NULL;
3984 }
3985 if (!intel_syntax)
3986 {
3987 if (*l == '(')
3988 ++paren_not_balanced;
3989 if (*l == ')')
3990 --paren_not_balanced;
3991 }
3992 else
3993 {
3994 if (*l == '[')
3995 ++paren_not_balanced;
3996 if (*l == ']')
3997 --paren_not_balanced;
3998 }
3999 l++;
4000 }
4001 if (l != token_start)
4002 { /* Yes, we've read in another operand. */
4003 unsigned int operand_ok;
4004 this_operand = i.operands++;
7d5e4556 4005 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4006 if (i.operands > MAX_OPERANDS)
4007 {
4008 as_bad (_("spurious operands; (%d operands/instruction max)"),
4009 MAX_OPERANDS);
4010 return NULL;
4011 }
4012 /* Now parse operand adding info to 'i' as we go along. */
4013 END_STRING_AND_SAVE (l);
4014
4015 if (intel_syntax)
4016 operand_ok =
4017 i386_intel_operand (token_start,
4018 intel_float_operand (mnemonic));
4019 else
a7619375 4020 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4021
4022 RESTORE_END_STRING (l);
4023 if (!operand_ok)
4024 return NULL;
4025 }
4026 else
4027 {
4028 if (expecting_operand)
4029 {
4030 expecting_operand_after_comma:
4031 as_bad (_("expecting operand after ','; got nothing"));
4032 return NULL;
4033 }
4034 if (*l == ',')
4035 {
4036 as_bad (_("expecting operand before ','; got nothing"));
4037 return NULL;
4038 }
4039 }
7f3f1ea2 4040
29b0f896
AM		 4041 /* Now *l must be either ',' or END_OF_INSN. */
4042 if (*l == ',')
4043 {
4044 if (*++l == END_OF_INSN)
4045 {
4046 /* Just skip it, if it's \n complain. */
4047 goto expecting_operand_after_comma;
4048 }
4049 expecting_operand = 1;
4050 }
4051 }
4052 return l;
4053}
7f3f1ea2 4054
050dfa73 4055static void
4d456e3d 4056swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4057{
4058 union i386_op temp_op;
40fb9820 4059 i386_operand_type temp_type;
050dfa73 4060 enum bfd_reloc_code_real temp_reloc;
4eed87de 4061
050dfa73
MM		 4062 temp_type = i.types[xchg2];
4063 i.types[xchg2] = i.types[xchg1];
4064 i.types[xchg1] = temp_type;
4065 temp_op = i.op[xchg2];
4066 i.op[xchg2] = i.op[xchg1];
4067 i.op[xchg1] = temp_op;
4068 temp_reloc = i.reloc[xchg2];
4069 i.reloc[xchg2] = i.reloc[xchg1];
4070 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4071
4072 if (i.mask)
4073 {
4074 if (i.mask->operand == xchg1)
4075 i.mask->operand = xchg2;
4076 else if (i.mask->operand == xchg2)
4077 i.mask->operand = xchg1;
4078 }
4079 if (i.broadcast)
4080 {
4081 if (i.broadcast->operand == xchg1)
4082 i.broadcast->operand = xchg2;
4083 else if (i.broadcast->operand == xchg2)
4084 i.broadcast->operand = xchg1;
4085 }
4086 if (i.rounding)
4087 {
4088 if (i.rounding->operand == xchg1)
4089 i.rounding->operand = xchg2;
4090 else if (i.rounding->operand == xchg2)
4091 i.rounding->operand = xchg1;
4092 }
050dfa73
MM		 4093}
4094
29b0f896 4095static void
e3bb37b5 4096swap_operands (void)
29b0f896 4097{
b7c61d9a 4098 switch (i.operands)
050dfa73 4099 {
c0f3af97 4100 case 5:
b7c61d9a 4101 case 4:
4d456e3d 4102 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4103 case 3:
4104 case 2:
4d456e3d 4105 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4106 break;
4107 default:
4108 abort ();
29b0f896 4109 }
29b0f896
AM		 4110
4111 if (i.mem_operands == 2)
4112 {
4113 const seg_entry *temp_seg;
4114 temp_seg = i.seg[0];
4115 i.seg[0] = i.seg[1];
4116 i.seg[1] = temp_seg;
4117 }
4118}
252b5132 4119
29b0f896
AM		 4120/* Try to ensure constant immediates are represented in the smallest
4121 opcode possible. */
4122static void
e3bb37b5 4123optimize_imm (void)
29b0f896
AM		 4124{
4125 char guess_suffix = 0;
4126 int op;
252b5132 4127
29b0f896
AM		 4128 if (i.suffix)
4129 guess_suffix = i.suffix;
4130 else if (i.reg_operands)
4131 {
4132 /* Figure out a suffix from the last register operand specified.
4133 We can't do this properly yet, ie. excluding InOutPortReg,
4134 but the following works for instructions with immediates.
4135 In any case, we can't set i.suffix yet. */
4136 for (op = i.operands; --op >= 0;)
40fb9820 4137 if (i.types[op].bitfield.reg8)
7ab9ffdd 4138 {
40fb9820
L		 4139 guess_suffix = BYTE_MNEM_SUFFIX;
4140 break;
4141 }
4142 else if (i.types[op].bitfield.reg16)
252b5132 4143 {
40fb9820
L		 4144 guess_suffix = WORD_MNEM_SUFFIX;
4145 break;
4146 }
4147 else if (i.types[op].bitfield.reg32)
4148 {
4149 guess_suffix = LONG_MNEM_SUFFIX;
4150 break;
4151 }
4152 else if (i.types[op].bitfield.reg64)
4153 {
4154 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4155 break;
252b5132 4156 }
29b0f896
AM		 4157 }
4158 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4159 guess_suffix = WORD_MNEM_SUFFIX;
4160
4161 for (op = i.operands; --op >= 0;)
40fb9820 4162 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4163 {
4164 switch (i.op[op].imms->X_op)
252b5132 4165 {
29b0f896
AM		 4166 case O_constant:
4167 /* If a suffix is given, this operand may be shortened. */
4168 switch (guess_suffix)
252b5132 4169 {
29b0f896 4170 case LONG_MNEM_SUFFIX:
40fb9820
L		 4171 i.types[op].bitfield.imm32 = 1;
4172 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4173 break;
4174 case WORD_MNEM_SUFFIX:
40fb9820
L		 4175 i.types[op].bitfield.imm16 = 1;
4176 i.types[op].bitfield.imm32 = 1;
4177 i.types[op].bitfield.imm32s = 1;
4178 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4179 break;
4180 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4181 i.types[op].bitfield.imm8 = 1;
4182 i.types[op].bitfield.imm8s = 1;
4183 i.types[op].bitfield.imm16 = 1;
4184 i.types[op].bitfield.imm32 = 1;
4185 i.types[op].bitfield.imm32s = 1;
4186 i.types[op].bitfield.imm64 = 1;
29b0f896 4187 break;
252b5132 4188 }
252b5132 4189
29b0f896
AM		 4190 /* If this operand is at most 16 bits, convert it
4191 to a signed 16 bit number before trying to see
4192 whether it will fit in an even smaller size.
4193 This allows a 16-bit operand such as $0xffe0 to
4194 be recognised as within Imm8S range. */
40fb9820 4195 if ((i.types[op].bitfield.imm16)
29b0f896 4196 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4197 {
29b0f896
AM		 4198 i.op[op].imms->X_add_number =
4199 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4200 }
40fb9820 4201 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4202 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4203 == 0))
4204 {
4205 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4206 ^ ((offsetT) 1 << 31))
4207 - ((offsetT) 1 << 31));
4208 }
40fb9820 4209 i.types[op]
c6fb90c8
L		 4210 = operand_type_or (i.types[op],
4211 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4212
29b0f896
AM		 4213 /* We must avoid matching of Imm32 templates when 64bit
4214 only immediate is available. */
4215 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4216 i.types[op].bitfield.imm32 = 0;
29b0f896 4217 break;
252b5132 4218
29b0f896
AM		 4219 case O_absent:
4220 case O_register:
4221 abort ();
4222
4223 /* Symbols and expressions. */
4224 default:
9cd96992
JB		 4225 /* Convert symbolic operand to proper sizes for matching, but don't
4226 prevent matching a set of insns that only supports sizes other
4227 than those matching the insn suffix. */
4228 {
40fb9820 4229 i386_operand_type mask, allowed;
d3ce72d0 4230 const insn_template *t;
9cd96992 4231
0dfbf9d7
L		 4232 operand_type_set (&mask, 0);
4233 operand_type_set (&allowed, 0);
40fb9820 4234
4eed87de
AM		 4235 for (t = current_templates->start;
4236 t < current_templates->end;
4237 ++t)
c6fb90c8
L		 4238 allowed = operand_type_or (allowed,
4239 t->operand_types[op]);
9cd96992
JB		 4240 switch (guess_suffix)
4241 {
4242 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4243 mask.bitfield.imm64 = 1;
4244 mask.bitfield.imm32s = 1;
9cd96992
JB		 4245 break;
4246 case LONG_MNEM_SUFFIX:
40fb9820 4247 mask.bitfield.imm32 = 1;
9cd96992
JB		 4248 break;
4249 case WORD_MNEM_SUFFIX:
40fb9820 4250 mask.bitfield.imm16 = 1;
9cd96992
JB		 4251 break;
4252 case BYTE_MNEM_SUFFIX:
40fb9820 4253 mask.bitfield.imm8 = 1;
9cd96992
JB		 4254 break;
4255 default:
9cd96992
JB		 4256 break;
4257 }
c6fb90c8 4258 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4259 if (!operand_type_all_zero (&allowed))
c6fb90c8 4260 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4261 }
29b0f896 4262 break;
252b5132 4263 }
29b0f896
AM		 4264 }
4265}
47926f60 4266
29b0f896
AM		 4267/* Try to use the smallest displacement type too. */
4268static void
e3bb37b5 4269optimize_disp (void)
29b0f896
AM		 4270{
4271 int op;
3e73aa7c 4272
29b0f896 4273 for (op = i.operands; --op >= 0;)
40fb9820 4274 if (operand_type_check (i.types[op], disp))
252b5132 4275 {
b300c311 4276 if (i.op[op].disps->X_op == O_constant)
252b5132 4277 {
91d6fa6a 4278 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4279
40fb9820 4280 if (i.types[op].bitfield.disp16
91d6fa6a 4281 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4282 {
4283 /* If this operand is at most 16 bits, convert
4284 to a signed 16 bit number and don't use 64bit
4285 displacement. */
91d6fa6a 4286 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4287 i.types[op].bitfield.disp64 = 0;
b300c311 4288 }
40fb9820 4289 if (i.types[op].bitfield.disp32
91d6fa6a 4290 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4291 {
4292 /* If this operand is at most 32 bits, convert
4293 to a signed 32 bit number and don't use 64bit
4294 displacement. */
91d6fa6a
NC		 4295 op_disp &= (((offsetT) 2 << 31) - 1);
4296 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4297 i.types[op].bitfield.disp64 = 0;
b300c311 4298 }
91d6fa6a 4299 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4300 {
40fb9820
L		 4301 i.types[op].bitfield.disp8 = 0;
4302 i.types[op].bitfield.disp16 = 0;
4303 i.types[op].bitfield.disp32 = 0;
4304 i.types[op].bitfield.disp32s = 0;
4305 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4306 i.op[op].disps = 0;
4307 i.disp_operands--;
4308 }
4309 else if (flag_code == CODE_64BIT)
4310 {
91d6fa6a 4311 if (fits_in_signed_long (op_disp))
28a9d8f5 4312 {
40fb9820
L		 4313 i.types[op].bitfield.disp64 = 0;
4314 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4315 }
0e1147d9 4316 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4317 && fits_in_unsigned_long (op_disp))
40fb9820 4318 i.types[op].bitfield.disp32 = 1;
b300c311 4319 }
40fb9820
L		 4320 if ((i.types[op].bitfield.disp32
4321 || i.types[op].bitfield.disp32s
4322 || i.types[op].bitfield.disp16)
91d6fa6a 4323 && fits_in_signed_byte (op_disp))
40fb9820 4324 i.types[op].bitfield.disp8 = 1;
252b5132 4325 }
67a4f2b7
AO		 4326 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4327 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4328 {
4329 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4330 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4331 i.types[op].bitfield.disp8 = 0;
4332 i.types[op].bitfield.disp16 = 0;
4333 i.types[op].bitfield.disp32 = 0;
4334 i.types[op].bitfield.disp32s = 0;
4335 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4336 }
4337 else
b300c311 4338 /* We only support 64bit displacement on constants. */
40fb9820 4339 i.types[op].bitfield.disp64 = 0;
252b5132 4340 }
29b0f896
AM		 4341}
4342
6c30d220
L		 4343/* Check if operands are valid for the instruction. */
4344
4345static int
4346check_VecOperands (const insn_template *t)
4347{
43234a1e
L		 4348 unsigned int op;
4349
6c30d220
L		 4350 /* Without VSIB byte, we can't have a vector register for index. */
4351 if (!t->opcode_modifier.vecsib
4352 && i.index_reg
4353 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4354 || i.index_reg->reg_type.bitfield.regymm
4355 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4356 {
4357 i.error = unsupported_vector_index_register;
4358 return 1;
4359 }
4360
ad8ecc81
MZ		 4361 /* Check if default mask is allowed. */
4362 if (t->opcode_modifier.nodefmask
4363 && (!i.mask || i.mask->mask->reg_num == 0))
4364 {
4365 i.error = no_default_mask;
4366 return 1;
4367 }
4368
7bab8ab5
JB		 4369 /* For VSIB byte, we need a vector register for index, and all vector
4370 registers must be distinct. */
4371 if (t->opcode_modifier.vecsib)
4372 {
4373 if (!i.index_reg
6c30d220
L		 4374 || !((t->opcode_modifier.vecsib == VecSIB128
4375 && i.index_reg->reg_type.bitfield.regxmm)
4376 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4377 && i.index_reg->reg_type.bitfield.regymm)
4378 || (t->opcode_modifier.vecsib == VecSIB512
4379 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4380 {
4381 i.error = invalid_vsib_address;
4382 return 1;
4383 }
4384
43234a1e
L		 4385 gas_assert (i.reg_operands == 2 || i.mask);
4386 if (i.reg_operands == 2 && !i.mask)
4387 {
4388 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4389 || i.types[0].bitfield.regymm);
43234a1e 4390 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4391 || i.types[2].bitfield.regymm);
43234a1e
L		 4392 if (operand_check == check_none)
4393 return 0;
4394 if (register_number (i.op[0].regs)
4395 != register_number (i.index_reg)
4396 && register_number (i.op[2].regs)
4397 != register_number (i.index_reg)
4398 && register_number (i.op[0].regs)
4399 != register_number (i.op[2].regs))
4400 return 0;
4401 if (operand_check == check_error)
4402 {
4403 i.error = invalid_vector_register_set;
4404 return 1;
4405 }
4406 as_warn (_("mask, index, and destination registers should be distinct"));
4407 }
8444f82a
MZ		 4408 else if (i.reg_operands == 1 && i.mask)
4409 {
4410 if ((i.types[1].bitfield.regymm
4411 || i.types[1].bitfield.regzmm)
4412 && (register_number (i.op[1].regs)
4413 == register_number (i.index_reg)))
4414 {
4415 if (operand_check == check_error)
4416 {
4417 i.error = invalid_vector_register_set;
4418 return 1;
4419 }
4420 if (operand_check != check_none)
4421 as_warn (_("index and destination registers should be distinct"));
4422 }
4423 }
43234a1e 4424 }
7bab8ab5 4425
43234a1e
L		 4426 /* Check if broadcast is supported by the instruction and is applied
4427 to the memory operand. */
4428 if (i.broadcast)
4429 {
4430 int broadcasted_opnd_size;
4431
4432 /* Check if specified broadcast is supported in this instruction,
4433 and it's applied to memory operand of DWORD or QWORD type,
4434 depending on VecESize. */
4435 if (i.broadcast->type != t->opcode_modifier.broadcast
4436 || !i.types[i.broadcast->operand].bitfield.mem
4437 || (t->opcode_modifier.vecesize == 0
4438 && !i.types[i.broadcast->operand].bitfield.dword
4439 && !i.types[i.broadcast->operand].bitfield.unspecified)
4440 || (t->opcode_modifier.vecesize == 1
4441 && !i.types[i.broadcast->operand].bitfield.qword
4442 && !i.types[i.broadcast->operand].bitfield.unspecified))
4443 goto bad_broadcast;
4444
4445 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4446 if (i.broadcast->type == BROADCAST_1TO16)
4447 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4448 else if (i.broadcast->type == BROADCAST_1TO8)
4449 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4450 else
4451 goto bad_broadcast;
4452
4453 if ((broadcasted_opnd_size == 256
4454 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4455 || (broadcasted_opnd_size == 512
4456 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4457 {
4458 bad_broadcast:
4459 i.error = unsupported_broadcast;
4460 return 1;
4461 }
4462 }
4463 /* If broadcast is supported in this instruction, we need to check if
4464 operand of one-element size isn't specified without broadcast. */
4465 else if (t->opcode_modifier.broadcast && i.mem_operands)
4466 {
4467 /* Find memory operand. */
4468 for (op = 0; op < i.operands; op++)
4469 if (operand_type_check (i.types[op], anymem))
4470 break;
4471 gas_assert (op < i.operands);
4472 /* Check size of the memory operand. */
4473 if ((t->opcode_modifier.vecesize == 0
4474 && i.types[op].bitfield.dword)
4475 || (t->opcode_modifier.vecesize == 1
4476 && i.types[op].bitfield.qword))
4477 {
4478 i.error = broadcast_needed;
4479 return 1;
4480 }
4481 }
4482
4483 /* Check if requested masking is supported. */
4484 if (i.mask
4485 && (!t->opcode_modifier.masking
4486 || (i.mask->zeroing
4487 && t->opcode_modifier.masking == MERGING_MASKING)))
4488 {
4489 i.error = unsupported_masking;
4490 return 1;
4491 }
4492
4493 /* Check if masking is applied to dest operand. */
4494 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4495 {
4496 i.error = mask_not_on_destination;
4497 return 1;
4498 }
4499
43234a1e
L		 4500 /* Check RC/SAE. */
4501 if (i.rounding)
4502 {
4503 if ((i.rounding->type != saeonly
4504 && !t->opcode_modifier.staticrounding)
4505 || (i.rounding->type == saeonly
4506 && (t->opcode_modifier.staticrounding
4507 || !t->opcode_modifier.sae)))
4508 {
4509 i.error = unsupported_rc_sae;
4510 return 1;
4511 }
4512 /* If the instruction has several immediate operands and one of
4513 them is rounding, the rounding operand should be the last
4514 immediate operand. */
4515 if (i.imm_operands > 1
4516 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4517 {
43234a1e 4518 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4519 return 1;
4520 }
6c30d220
L		 4521 }
4522
43234a1e
L		 4523 /* Check vector Disp8 operand. */
4524 if (t->opcode_modifier.disp8memshift)
4525 {
4526 if (i.broadcast)
4527 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4528 else
4529 i.memshift = t->opcode_modifier.disp8memshift;
4530
4531 for (op = 0; op < i.operands; op++)
4532 if (operand_type_check (i.types[op], disp)
4533 && i.op[op].disps->X_op == O_constant)
4534 {
4535 offsetT value = i.op[op].disps->X_add_number;
4536 int vec_disp8_ok = fits_in_vec_disp8 (value);
4537 if (t->operand_types [op].bitfield.vec_disp8)
4538 {
4539 if (vec_disp8_ok)
4540 i.types[op].bitfield.vec_disp8 = 1;
4541 else
4542 {
4543 /* Vector insn can only have Vec_Disp8/Disp32 in
4544 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4545 mode. */
4546 i.types[op].bitfield.disp8 = 0;
4547 if (flag_code != CODE_16BIT)
4548 i.types[op].bitfield.disp16 = 0;
4549 }
4550 }
4551 else if (flag_code != CODE_16BIT)
4552 {
4553 /* One form of this instruction supports vector Disp8.
4554 Try vector Disp8 if we need to use Disp32. */
4555 if (vec_disp8_ok && !fits_in_signed_byte (value))
4556 {
4557 i.error = try_vector_disp8;
4558 return 1;
4559 }
4560 }
4561 }
4562 }
4563 else
4564 i.memshift = -1;
4565
6c30d220
L		 4566 return 0;
4567}
4568
43f3e2ee 4569/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4570 operand types. */
4571
4572static int
4573VEX_check_operands (const insn_template *t)
4574{
43234a1e
L		 4575 /* VREX is only valid with EVEX prefix. */
4576 if (i.need_vrex && !t->opcode_modifier.evex)
4577 {
4578 i.error = invalid_register_operand;
4579 return 1;
4580 }
4581
a683cc34
SP		 4582 if (!t->opcode_modifier.vex)
4583 return 0;
4584
4585 /* Only check VEX_Imm4, which must be the first operand. */
4586 if (t->operand_types[0].bitfield.vec_imm4)
4587 {
4588 if (i.op[0].imms->X_op != O_constant
4589 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4590 {
a65babc9 4591 i.error = bad_imm4;
891edac4
L		 4592 return 1;
4593 }
a683cc34
SP		 4594
4595 /* Turn off Imm8 so that update_imm won't complain. */
4596 i.types[0] = vec_imm4;
4597 }
4598
4599 return 0;
4600}
4601
d3ce72d0 4602static const insn_template *
e3bb37b5 4603match_template (void)
29b0f896
AM		 4604{
4605 /* Points to template once we've found it. */
d3ce72d0 4606 const insn_template *t;
40fb9820 4607 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4608 i386_operand_type overlap4;
29b0f896 4609 unsigned int found_reverse_match;
40fb9820
L		 4610 i386_opcode_modifier suffix_check;
4611 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4612 int addr_prefix_disp;
a5c311ca 4613 unsigned int j;
3629bb00 4614 unsigned int found_cpu_match;
45664ddb 4615 unsigned int check_register;
5614d22c 4616 enum i386_error specific_error = 0;
29b0f896 4617
c0f3af97
L		 4618#if MAX_OPERANDS != 5
4619# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4620#endif
4621
29b0f896 4622 found_reverse_match = 0;
539e75ad 4623 addr_prefix_disp = -1;
40fb9820
L		 4624
4625 memset (&suffix_check, 0, sizeof (suffix_check));
4626 if (i.suffix == BYTE_MNEM_SUFFIX)
4627 suffix_check.no_bsuf = 1;
4628 else if (i.suffix == WORD_MNEM_SUFFIX)
4629 suffix_check.no_wsuf = 1;
4630 else if (i.suffix == SHORT_MNEM_SUFFIX)
4631 suffix_check.no_ssuf = 1;
4632 else if (i.suffix == LONG_MNEM_SUFFIX)
4633 suffix_check.no_lsuf = 1;
4634 else if (i.suffix == QWORD_MNEM_SUFFIX)
4635 suffix_check.no_qsuf = 1;
4636 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4637 suffix_check.no_ldsuf = 1;
29b0f896 4638
01559ecc
L		 4639 /* Must have right number of operands. */
4640 i.error = number_of_operands_mismatch;
4641
45aa61fe 4642 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4643 {
539e75ad
L		 4644 addr_prefix_disp = -1;
4645
29b0f896
AM		 4646 if (i.operands != t->operands)
4647 continue;
4648
50aecf8c 4649 /* Check processor support. */
a65babc9 4650 i.error = unsupported;
c0f3af97
L		 4651 found_cpu_match = (cpu_flags_match (t)
4652 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4653 if (!found_cpu_match)
4654 continue;
4655
e1d4d893 4656 /* Check old gcc support. */
a65babc9 4657 i.error = old_gcc_only;
e1d4d893
L		 4658 if (!old_gcc && t->opcode_modifier.oldgcc)
4659 continue;
4660
4661 /* Check AT&T mnemonic. */
a65babc9 4662 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4663 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4664 continue;
4665
891edac4 4666 /* Check AT&T/Intel syntax. */
a65babc9 4667 i.error = unsupported_syntax;
5c07affc
L		 4668 if ((intel_syntax && t->opcode_modifier.attsyntax)
4669 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4670 continue;
4671
20592a94 4672 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4673 i.error = invalid_instruction_suffix;
567e4e96
L		 4674 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4675 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4676 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4677 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4678 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4679 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4680 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4681 continue;
4682
5c07affc 4683 if (!operand_size_match (t))
7d5e4556 4684 continue;
539e75ad 4685
5c07affc
L		 4686 for (j = 0; j < MAX_OPERANDS; j++)
4687 operand_types[j] = t->operand_types[j];
4688
45aa61fe
AM		 4689 /* In general, don't allow 64-bit operands in 32-bit mode. */
4690 if (i.suffix == QWORD_MNEM_SUFFIX
4691 && flag_code != CODE_64BIT
4692 && (intel_syntax
40fb9820 4693 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4694 && !intel_float_operand (t->name))
4695 : intel_float_operand (t->name) != 2)
40fb9820 4696 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4697 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4698 && !operand_types[0].bitfield.regymm
4699 && !operand_types[0].bitfield.regzmm)
40fb9820 4700 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97 4701 && !!operand_types[t->operands > 1].bitfield.regxmm
43234a1e
L		 4702 && !!operand_types[t->operands > 1].bitfield.regymm
4703 && !!operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4704 && (t->base_opcode != 0x0fc7
4705 || t->extension_opcode != 1 /* cmpxchg8b */))
4706 continue;
4707
192dc9c6
JB		 4708 /* In general, don't allow 32-bit operands on pre-386. */
4709 else if (i.suffix == LONG_MNEM_SUFFIX
4710 && !cpu_arch_flags.bitfield.cpui386
4711 && (intel_syntax
4712 ? (!t->opcode_modifier.ignoresize
4713 && !intel_float_operand (t->name))
4714 : intel_float_operand (t->name) != 2)
4715 && ((!operand_types[0].bitfield.regmmx
4716 && !operand_types[0].bitfield.regxmm)
4717 || (!operand_types[t->operands > 1].bitfield.regmmx
4718 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4719 continue;
4720
29b0f896 4721 /* Do not verify operands when there are none. */
50aecf8c 4722 else
29b0f896 4723 {
c6fb90c8 4724 if (!t->operands)
2dbab7d5
L		 4725 /* We've found a match; break out of loop. */
4726 break;
29b0f896 4727 }
252b5132 4728
539e75ad
L		 4729 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4730 into Disp32/Disp16/Disp32 operand. */
4731 if (i.prefix[ADDR_PREFIX] != 0)
4732 {
40fb9820 4733 /* There should be only one Disp operand. */
539e75ad
L		 4734 switch (flag_code)
4735 {
4736 case CODE_16BIT:
40fb9820
L		 4737 for (j = 0; j < MAX_OPERANDS; j++)
4738 {
4739 if (operand_types[j].bitfield.disp16)
4740 {
4741 addr_prefix_disp = j;
4742 operand_types[j].bitfield.disp32 = 1;
4743 operand_types[j].bitfield.disp16 = 0;
4744 break;
4745 }
4746 }
539e75ad
L		 4747 break;
4748 case CODE_32BIT:
40fb9820
L		 4749 for (j = 0; j < MAX_OPERANDS; j++)
4750 {
4751 if (operand_types[j].bitfield.disp32)
4752 {
4753 addr_prefix_disp = j;
4754 operand_types[j].bitfield.disp32 = 0;
4755 operand_types[j].bitfield.disp16 = 1;
4756 break;
4757 }
4758 }
539e75ad
L		 4759 break;
4760 case CODE_64BIT:
40fb9820
L		 4761 for (j = 0; j < MAX_OPERANDS; j++)
4762 {
4763 if (operand_types[j].bitfield.disp64)
4764 {
4765 addr_prefix_disp = j;
4766 operand_types[j].bitfield.disp64 = 0;
4767 operand_types[j].bitfield.disp32 = 1;
4768 break;
4769 }
4770 }
539e75ad
L		 4771 break;
4772 }
539e75ad
L		 4773 }
4774
56ffb741
L		 4775 /* We check register size if needed. */
4776 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4777 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4778 switch (t->operands)
4779 {
4780 case 1:
40fb9820 4781 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4782 continue;
4783 break;
4784 case 2:
8b38ad71
L		 4785 /* xchg %eax, %eax is a special case. It is an aliase for nop
4786 only in 32bit mode and we can use opcode 0x90. In 64bit
4787 mode, we can't use 0x90 for xchg %eax, %eax since it should
4788 zero-extend %eax to %rax. */
4789 if (flag_code == CODE_64BIT
4790 && t->base_opcode == 0x90
0dfbf9d7
L		 4791 && operand_type_equal (&i.types [0], &acc32)
4792 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4793 continue;
b6169b20
L		 4794 if (i.swap_operand)
4795 {
4796 /* If we swap operand in encoding, we either match
4797 the next one or reverse direction of operands. */
4798 if (t->opcode_modifier.s)
4799 continue;
4800 else if (t->opcode_modifier.d)
4801 goto check_reverse;
4802 }
4803
29b0f896 4804 case 3:
fa99fab2
L		 4805 /* If we swap operand in encoding, we match the next one. */
4806 if (i.swap_operand && t->opcode_modifier.s)
4807 continue;
f48ff2ae 4808 case 4:
c0f3af97 4809 case 5:
c6fb90c8 4810 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4811 if (!operand_type_match (overlap0, i.types[0])
4812 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4813 || (check_register
4814 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4815 operand_types[0],
4816 overlap1, i.types[1],
4817 operand_types[1])))
29b0f896
AM		 4818 {
4819 /* Check if other direction is valid ... */
40fb9820 4820 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4821 continue;
4822
b6169b20 4823check_reverse:
29b0f896 4824 /* Try reversing direction of operands. */
c6fb90c8
L		 4825 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4826 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4827 if (!operand_type_match (overlap0, i.types[0])
4828 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4829 || (check_register
4830 && !operand_type_register_match (overlap0,
4831 i.types[0],
4832 operand_types[1],
4833 overlap1,
4834 i.types[1],
4835 operand_types[0])))
29b0f896
AM		 4836 {
4837 /* Does not match either direction. */
4838 continue;
4839 }
4840 /* found_reverse_match holds which of D or FloatDR
4841 we've found. */
40fb9820 4842 if (t->opcode_modifier.d)
8a2ed489 4843 found_reverse_match = Opcode_D;
40fb9820 4844 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4845 found_reverse_match = Opcode_FloatD;
4846 else
4847 found_reverse_match = 0;
40fb9820 4848 if (t->opcode_modifier.floatr)
8a2ed489 4849 found_reverse_match |= Opcode_FloatR;
29b0f896 4850 }
f48ff2ae 4851 else
29b0f896 4852 {
f48ff2ae 4853 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4854 switch (t->operands)
4855 {
c0f3af97
L		 4856 case 5:
4857 overlap4 = operand_type_and (i.types[4],
4858 operand_types[4]);
d1cbb4db 4859 case 4:
c6fb90c8
L		 4860 overlap3 = operand_type_and (i.types[3],
4861 operand_types[3]);
d1cbb4db 4862 case 3:
c6fb90c8
L		 4863 overlap2 = operand_type_and (i.types[2],
4864 operand_types[2]);
d1cbb4db
L		 4865 break;
4866 }
29b0f896 4867
f48ff2ae
L		 4868 switch (t->operands)
4869 {
c0f3af97
L		 4870 case 5:
4871 if (!operand_type_match (overlap4, i.types[4])
4872 || !operand_type_register_match (overlap3,
4873 i.types[3],
4874 operand_types[3],
4875 overlap4,
4876 i.types[4],
4877 operand_types[4]))
4878 continue;
f48ff2ae 4879 case 4:
40fb9820 4880 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4881 || (check_register
4882 && !operand_type_register_match (overlap2,
4883 i.types[2],
4884 operand_types[2],
4885 overlap3,
4886 i.types[3],
4887 operand_types[3])))
f48ff2ae
L		 4888 continue;
4889 case 3:
4890 /* Here we make use of the fact that there are no
4891 reverse match 3 operand instructions, and all 3
4892 operand instructions only need to be checked for
4893 register consistency between operands 2 and 3. */
40fb9820 4894 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4895 || (check_register
4896 && !operand_type_register_match (overlap1,
4897 i.types[1],
4898 operand_types[1],
4899 overlap2,
4900 i.types[2],
4901 operand_types[2])))
f48ff2ae
L		 4902 continue;
4903 break;
4904 }
29b0f896 4905 }
f48ff2ae 4906 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4907 slip through to break. */
4908 }
3629bb00 4909 if (!found_cpu_match)
29b0f896
AM		 4910 {
4911 found_reverse_match = 0;
4912 continue;
4913 }
c0f3af97 4914
5614d22c
JB		 4915 /* Check if vector and VEX operands are valid. */
4916 if (check_VecOperands (t) || VEX_check_operands (t))
4917 {
4918 specific_error = i.error;
4919 continue;
4920 }
a683cc34 4921
29b0f896
AM		 4922 /* We've found a match; break out of loop. */
4923 break;
4924 }
4925
4926 if (t == current_templates->end)
4927 {
4928 /* We found no match. */
a65babc9 4929 const char *err_msg;
5614d22c 4930 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4931 {
4932 default:
4933 abort ();
86e026a4 4934 case operand_size_mismatch:
a65babc9
L		 4935 err_msg = _("operand size mismatch");
4936 break;
4937 case operand_type_mismatch:
4938 err_msg = _("operand type mismatch");
4939 break;
4940 case register_type_mismatch:
4941 err_msg = _("register type mismatch");
4942 break;
4943 case number_of_operands_mismatch:
4944 err_msg = _("number of operands mismatch");
4945 break;
4946 case invalid_instruction_suffix:
4947 err_msg = _("invalid instruction suffix");
4948 break;
4949 case bad_imm4:
4a2608e3 4950 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4951 break;
4952 case old_gcc_only:
4953 err_msg = _("only supported with old gcc");
4954 break;
4955 case unsupported_with_intel_mnemonic:
4956 err_msg = _("unsupported with Intel mnemonic");
4957 break;
4958 case unsupported_syntax:
4959 err_msg = _("unsupported syntax");
4960 break;
4961 case unsupported:
35262a23 4962 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4963 current_templates->start->name);
4964 return NULL;
6c30d220
L		 4965 case invalid_vsib_address:
4966 err_msg = _("invalid VSIB address");
4967 break;
7bab8ab5
JB		 4968 case invalid_vector_register_set:
4969 err_msg = _("mask, index, and destination registers must be distinct");
4970 break;
6c30d220
L		 4971 case unsupported_vector_index_register:
4972 err_msg = _("unsupported vector index register");
4973 break;
43234a1e
L		 4974 case unsupported_broadcast:
4975 err_msg = _("unsupported broadcast");
4976 break;
4977 case broadcast_not_on_src_operand:
4978 err_msg = _("broadcast not on source memory operand");
4979 break;
4980 case broadcast_needed:
4981 err_msg = _("broadcast is needed for operand of such type");
4982 break;
4983 case unsupported_masking:
4984 err_msg = _("unsupported masking");
4985 break;
4986 case mask_not_on_destination:
4987 err_msg = _("mask not on destination operand");
4988 break;
4989 case no_default_mask:
4990 err_msg = _("default mask isn't allowed");
4991 break;
4992 case unsupported_rc_sae:
4993 err_msg = _("unsupported static rounding/sae");
4994 break;
4995 case rc_sae_operand_not_last_imm:
4996 if (intel_syntax)
4997 err_msg = _("RC/SAE operand must precede immediate operands");
4998 else
4999 err_msg = _("RC/SAE operand must follow immediate operands");
5000 break;
5001 case invalid_register_operand:
5002 err_msg = _("invalid register operand");
5003 break;
a65babc9
L		 5004 }
5005 as_bad (_("%s for `%s'"), err_msg,
891edac4 5006 current_templates->start->name);
fa99fab2 5007 return NULL;
29b0f896 5008 }
252b5132 5009
29b0f896
AM		 5010 if (!quiet_warnings)
5011 {
5012 if (!intel_syntax
40fb9820
L		 5013 && (i.types[0].bitfield.jumpabsolute
5014 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5015 {
5016 as_warn (_("indirect %s without `*'"), t->name);
5017 }
5018
40fb9820
L		 5019 if (t->opcode_modifier.isprefix
5020 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5021 {
5022 /* Warn them that a data or address size prefix doesn't
5023 affect assembly of the next line of code. */
5024 as_warn (_("stand-alone `%s' prefix"), t->name);
5025 }
5026 }
5027
5028 /* Copy the template we found. */
5029 i.tm = *t;
539e75ad
L		 5030
5031 if (addr_prefix_disp != -1)
5032 i.tm.operand_types[addr_prefix_disp]
5033 = operand_types[addr_prefix_disp];
5034
29b0f896
AM		 5035 if (found_reverse_match)
5036 {
5037 /* If we found a reverse match we must alter the opcode
5038 direction bit. found_reverse_match holds bits to change
5039 (different for int & float insns). */
5040
5041 i.tm.base_opcode ^= found_reverse_match;
5042
539e75ad
L		 5043 i.tm.operand_types[0] = operand_types[1];
5044 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5045 }
5046
fa99fab2 5047 return t;
29b0f896
AM		 5048}
5049
5050static int
e3bb37b5 5051check_string (void)
29b0f896 5052{
40fb9820
L		 5053 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5054 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5055 {
5056 if (i.seg[0] != NULL && i.seg[0] != &es)
5057 {
a87af027 5058 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5059 i.tm.name,
a87af027
JB		 5060 mem_op + 1,
5061 register_prefix);
29b0f896
AM		 5062 return 0;
5063 }
5064 /* There's only ever one segment override allowed per instruction.
5065 This instruction possibly has a legal segment override on the
5066 second operand, so copy the segment to where non-string
5067 instructions store it, allowing common code. */
5068 i.seg[0] = i.seg[1];
5069 }
40fb9820 5070 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5071 {
5072 if (i.seg[1] != NULL && i.seg[1] != &es)
5073 {
a87af027 5074 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5075 i.tm.name,
a87af027
JB		 5076 mem_op + 2,
5077 register_prefix);
29b0f896
AM		 5078 return 0;
5079 }
5080 }
5081 return 1;
5082}
5083
5084static int
543613e9 5085process_suffix (void)
29b0f896
AM		 5086{
5087 /* If matched instruction specifies an explicit instruction mnemonic
5088 suffix, use it. */
40fb9820
L		 5089 if (i.tm.opcode_modifier.size16)
5090 i.suffix = WORD_MNEM_SUFFIX;
5091 else if (i.tm.opcode_modifier.size32)
5092 i.suffix = LONG_MNEM_SUFFIX;
5093 else if (i.tm.opcode_modifier.size64)
5094 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5095 else if (i.reg_operands)
5096 {
5097 /* If there's no instruction mnemonic suffix we try to invent one
5098 based on register operands. */
5099 if (!i.suffix)
5100 {
5101 /* We take i.suffix from the last register operand specified,
5102 Destination register type is more significant than source
381d071f
L		 5103 register type. crc32 in SSE4.2 prefers source register
5104 type. */
5105 if (i.tm.base_opcode == 0xf20f38f1)
5106 {
40fb9820
L		 5107 if (i.types[0].bitfield.reg16)
5108 i.suffix = WORD_MNEM_SUFFIX;
5109 else if (i.types[0].bitfield.reg32)
5110 i.suffix = LONG_MNEM_SUFFIX;
5111 else if (i.types[0].bitfield.reg64)
5112 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5113 }
9344ff29 5114 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5115 {
40fb9820 5116 if (i.types[0].bitfield.reg8)
20592a94
L		 5117 i.suffix = BYTE_MNEM_SUFFIX;
5118 }
381d071f
L		 5119
5120 if (!i.suffix)
5121 {
5122 int op;
5123
20592a94
L		 5124 if (i.tm.base_opcode == 0xf20f38f1
5125 || i.tm.base_opcode == 0xf20f38f0)
5126 {
5127 /* We have to know the operand size for crc32. */
5128 as_bad (_("ambiguous memory operand size for `%s`"),
5129 i.tm.name);
5130 return 0;
5131 }
5132
381d071f 5133 for (op = i.operands; --op >= 0;)
40fb9820 5134 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5135 {
40fb9820
L		 5136 if (i.types[op].bitfield.reg8)
5137 {
5138 i.suffix = BYTE_MNEM_SUFFIX;
5139 break;
5140 }
5141 else if (i.types[op].bitfield.reg16)
5142 {
5143 i.suffix = WORD_MNEM_SUFFIX;
5144 break;
5145 }
5146 else if (i.types[op].bitfield.reg32)
5147 {
5148 i.suffix = LONG_MNEM_SUFFIX;
5149 break;
5150 }
5151 else if (i.types[op].bitfield.reg64)
5152 {
5153 i.suffix = QWORD_MNEM_SUFFIX;
5154 break;
5155 }
381d071f
L		 5156 }
5157 }
29b0f896
AM		 5158 }
5159 else if (i.suffix == BYTE_MNEM_SUFFIX)
5160 {
2eb952a4
L		 5161 if (intel_syntax
5162 && i.tm.opcode_modifier.ignoresize
5163 && i.tm.opcode_modifier.no_bsuf)
5164 i.suffix = 0;
5165 else if (!check_byte_reg ())
29b0f896
AM		 5166 return 0;
5167 }
5168 else if (i.suffix == LONG_MNEM_SUFFIX)
5169 {
2eb952a4
L		 5170 if (intel_syntax
5171 && i.tm.opcode_modifier.ignoresize
5172 && i.tm.opcode_modifier.no_lsuf)
5173 i.suffix = 0;
5174 else if (!check_long_reg ())
29b0f896
AM		 5175 return 0;
5176 }
5177 else if (i.suffix == QWORD_MNEM_SUFFIX)
5178 {
955e1e6a
L		 5179 if (intel_syntax
5180 && i.tm.opcode_modifier.ignoresize
5181 && i.tm.opcode_modifier.no_qsuf)
5182 i.suffix = 0;
5183 else if (!check_qword_reg ())
29b0f896
AM		 5184 return 0;
5185 }
5186 else if (i.suffix == WORD_MNEM_SUFFIX)
5187 {
2eb952a4
L		 5188 if (intel_syntax
5189 && i.tm.opcode_modifier.ignoresize
5190 && i.tm.opcode_modifier.no_wsuf)
5191 i.suffix = 0;
5192 else if (!check_word_reg ())
29b0f896
AM		 5193 return 0;
5194 }
c0f3af97 5195 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5196 || i.suffix == YMMWORD_MNEM_SUFFIX
5197 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5198 {
43234a1e 5199 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5200 should check if it is a valid suffix. */
5201 }
40fb9820 5202 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5203 /* Do nothing if the instruction is going to ignore the prefix. */
5204 ;
5205 else
5206 abort ();
5207 }
40fb9820 5208 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5209 && !i.suffix
5210 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5211 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5212 {
5213 i.suffix = stackop_size;
5214 }
9306ca4a
JB		 5215 else if (intel_syntax
5216 && !i.suffix
40fb9820
L		 5217 && (i.tm.operand_types[0].bitfield.jumpabsolute
5218 || i.tm.opcode_modifier.jumpbyte
5219 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5220 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5221 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5222 {
5223 switch (flag_code)
5224 {
5225 case CODE_64BIT:
40fb9820 5226 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5227 {
5228 i.suffix = QWORD_MNEM_SUFFIX;
5229 break;
5230 }
5231 case CODE_32BIT:
40fb9820 5232 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5233 i.suffix = LONG_MNEM_SUFFIX;
5234 break;
5235 case CODE_16BIT:
40fb9820 5236 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5237 i.suffix = WORD_MNEM_SUFFIX;
5238 break;
5239 }
5240 }
252b5132 5241
9306ca4a 5242 if (!i.suffix)
29b0f896 5243 {
9306ca4a
JB		 5244 if (!intel_syntax)
5245 {
40fb9820 5246 if (i.tm.opcode_modifier.w)
9306ca4a 5247 {
4eed87de
AM		 5248 as_bad (_("no instruction mnemonic suffix given and "
5249 "no register operands; can't size instruction"));
9306ca4a
JB		 5250 return 0;
5251 }
5252 }
5253 else
5254 {
40fb9820 5255 unsigned int suffixes;
7ab9ffdd 5256
40fb9820
L		 5257 suffixes = !i.tm.opcode_modifier.no_bsuf;
5258 if (!i.tm.opcode_modifier.no_wsuf)
5259 suffixes |= 1 << 1;
5260 if (!i.tm.opcode_modifier.no_lsuf)
5261 suffixes |= 1 << 2;
fc4adea1 5262 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5263 suffixes |= 1 << 3;
5264 if (!i.tm.opcode_modifier.no_ssuf)
5265 suffixes |= 1 << 4;
5266 if (!i.tm.opcode_modifier.no_qsuf)
5267 suffixes |= 1 << 5;
5268
5269 /* There are more than suffix matches. */
5270 if (i.tm.opcode_modifier.w
9306ca4a 5271 || ((suffixes & (suffixes - 1))
40fb9820
L		 5272 && !i.tm.opcode_modifier.defaultsize
5273 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5274 {
5275 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5276 return 0;
5277 }
5278 }
29b0f896 5279 }
252b5132 5280
9306ca4a
JB		 5281 /* Change the opcode based on the operand size given by i.suffix;
5282 We don't need to change things for byte insns. */
5283
582d5edd
L		 5284 if (i.suffix
5285 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5286 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5287 && i.suffix != YMMWORD_MNEM_SUFFIX
5288 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5289 {
5290 /* It's not a byte, select word/dword operation. */
40fb9820 5291 if (i.tm.opcode_modifier.w)
29b0f896 5292 {
40fb9820 5293 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5294 i.tm.base_opcode |= 8;
5295 else
5296 i.tm.base_opcode |= 1;
5297 }
0f3f3d8b 5298
29b0f896
AM		 5299 /* Now select between word & dword operations via the operand
5300 size prefix, except for instructions that will ignore this
5301 prefix anyway. */
ca61edf2 5302 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5303 {
ca61edf2
L		 5304 /* The address size override prefix changes the size of the
5305 first operand. */
40fb9820
L		 5306 if ((flag_code == CODE_32BIT
5307 && i.op->regs[0].reg_type.bitfield.reg16)
5308 || (flag_code != CODE_32BIT
5309 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5310 if (!add_prefix (ADDR_PREFIX_OPCODE))
5311 return 0;
5312 }
5313 else if (i.suffix != QWORD_MNEM_SUFFIX
5314 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5315 && !i.tm.opcode_modifier.ignoresize
5316 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5317 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5318 || (flag_code == CODE_64BIT
40fb9820 5319 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5320 {
5321 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5322
40fb9820 5323 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5324 prefix = ADDR_PREFIX_OPCODE;
252b5132 5325
29b0f896
AM		 5326 if (!add_prefix (prefix))
5327 return 0;
24eab124 5328 }
252b5132 5329
29b0f896
AM		 5330 /* Set mode64 for an operand. */
5331 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5332 && flag_code == CODE_64BIT
40fb9820 5333 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5334 {
5335 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5336 need rex64. cmpxchg8b is also a special case. */
5337 if (! (i.operands == 2
5338 && i.tm.base_opcode == 0x90
5339 && i.tm.extension_opcode == None
0dfbf9d7
L		 5340 && operand_type_equal (&i.types [0], &acc64)
5341 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5342 && ! (i.operands == 1
5343 && i.tm.base_opcode == 0xfc7
5344 && i.tm.extension_opcode == 1
40fb9820
L		 5345 && !operand_type_check (i.types [0], reg)
5346 && operand_type_check (i.types [0], anymem)))
f6bee062 5347 i.rex |= REX_W;
46e883c5 5348 }
3e73aa7c 5349
29b0f896
AM		 5350 /* Size floating point instruction. */
5351 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5352 if (i.tm.opcode_modifier.floatmf)
543613e9 5353 i.tm.base_opcode ^= 4;
29b0f896 5354 }
7ecd2f8b 5355
29b0f896
AM		 5356 return 1;
5357}
3e73aa7c 5358
29b0f896 5359static int
543613e9 5360check_byte_reg (void)
29b0f896
AM		 5361{
5362 int op;
543613e9 5363
29b0f896
AM		 5364 for (op = i.operands; --op >= 0;)
5365 {
5366 /* If this is an eight bit register, it's OK. If it's the 16 or
5367 32 bit version of an eight bit register, we will just use the
5368 low portion, and that's OK too. */
40fb9820 5369 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5370 continue;
5371
5a819eb9
JB		 5372 /* I/O port address operands are OK too. */
5373 if (i.tm.operand_types[op].bitfield.inoutportreg)
5374 continue;
5375
9344ff29
L		 5376 /* crc32 doesn't generate this warning. */
5377 if (i.tm.base_opcode == 0xf20f38f0)
5378 continue;
5379
40fb9820
L		 5380 if ((i.types[op].bitfield.reg16
5381 || i.types[op].bitfield.reg32
5382 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5383 && i.op[op].regs->reg_num < 4
5384 /* Prohibit these changes in 64bit mode, since the lowering
5385 would be more complicated. */
5386 && flag_code != CODE_64BIT)
29b0f896 5387 {
29b0f896 5388#if REGISTER_WARNINGS
5a819eb9 5389 if (!quiet_warnings)
a540244d
L		 5390 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5391 register_prefix,
40fb9820 5392 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5393 ? REGNAM_AL - REGNAM_AX
5394 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5395 register_prefix,
29b0f896
AM		 5396 i.op[op].regs->reg_name,
5397 i.suffix);
5398#endif
5399 continue;
5400 }
5401 /* Any other register is bad. */
40fb9820
L		 5402 if (i.types[op].bitfield.reg16
5403 || i.types[op].bitfield.reg32
5404 || i.types[op].bitfield.reg64
5405 || i.types[op].bitfield.regmmx
5406 || i.types[op].bitfield.regxmm
c0f3af97 5407 || i.types[op].bitfield.regymm
43234a1e 5408 || i.types[op].bitfield.regzmm
40fb9820
L		 5409 || i.types[op].bitfield.sreg2
5410 || i.types[op].bitfield.sreg3
5411 || i.types[op].bitfield.control
5412 || i.types[op].bitfield.debug
5413 || i.types[op].bitfield.test
5414 || i.types[op].bitfield.floatreg
5415 || i.types[op].bitfield.floatacc)
29b0f896 5416 {
a540244d
L		 5417 as_bad (_("`%s%s' not allowed with `%s%c'"),
5418 register_prefix,
29b0f896
AM		 5419 i.op[op].regs->reg_name,
5420 i.tm.name,
5421 i.suffix);
5422 return 0;
5423 }
5424 }
5425 return 1;
5426}
5427
5428static int
e3bb37b5 5429check_long_reg (void)
29b0f896
AM		 5430{
5431 int op;
5432
5433 for (op = i.operands; --op >= 0;)
5434 /* Reject eight bit registers, except where the template requires
5435 them. (eg. movzb) */
40fb9820
L		 5436 if (i.types[op].bitfield.reg8
5437 && (i.tm.operand_types[op].bitfield.reg16
5438 || i.tm.operand_types[op].bitfield.reg32
5439 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5440 {
a540244d
L		 5441 as_bad (_("`%s%s' not allowed with `%s%c'"),
5442 register_prefix,
29b0f896
AM		 5443 i.op[op].regs->reg_name,
5444 i.tm.name,
5445 i.suffix);
5446 return 0;
5447 }
e4630f71 5448 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5449 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5450 && i.types[op].bitfield.reg16
5451 && (i.tm.operand_types[op].bitfield.reg32
5452 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5453 {
5454 /* Prohibit these changes in the 64bit mode, since the
5455 lowering is more complicated. */
5456 if (flag_code == CODE_64BIT)
252b5132 5457 {
2b5d6a91 5458 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5459 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5460 i.suffix);
5461 return 0;
252b5132 5462 }
29b0f896 5463#if REGISTER_WARNINGS
cecf1424
JB		 5464 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5465 register_prefix,
5466 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5467 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5468#endif
252b5132 5469 }
e4630f71 5470 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5471 else if (i.types[op].bitfield.reg64
5472 && (i.tm.operand_types[op].bitfield.reg32
5473 || i.tm.operand_types[op].bitfield.acc))
252b5132 5474 {
34828aad 5475 if (intel_syntax
ca61edf2 5476 && i.tm.opcode_modifier.toqword
40fb9820 5477 && !i.types[0].bitfield.regxmm)
34828aad 5478 {
ca61edf2 5479 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5480 i.suffix = QWORD_MNEM_SUFFIX;
5481 }
5482 else
5483 {
2b5d6a91 5484 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5485 register_prefix, i.op[op].regs->reg_name,
5486 i.suffix);
5487 return 0;
5488 }
29b0f896
AM		 5489 }
5490 return 1;
5491}
252b5132 5492
29b0f896 5493static int
e3bb37b5 5494check_qword_reg (void)
29b0f896
AM		 5495{
5496 int op;
252b5132 5497
29b0f896
AM		 5498 for (op = i.operands; --op >= 0; )
5499 /* Reject eight bit registers, except where the template requires
5500 them. (eg. movzb) */
40fb9820
L		 5501 if (i.types[op].bitfield.reg8
5502 && (i.tm.operand_types[op].bitfield.reg16
5503 || i.tm.operand_types[op].bitfield.reg32
5504 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5505 {
a540244d
L		 5506 as_bad (_("`%s%s' not allowed with `%s%c'"),
5507 register_prefix,
29b0f896
AM		 5508 i.op[op].regs->reg_name,
5509 i.tm.name,
5510 i.suffix);
5511 return 0;
5512 }
e4630f71 5513 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5514 else if ((i.types[op].bitfield.reg16
5515 || i.types[op].bitfield.reg32)
5516 && (i.tm.operand_types[op].bitfield.reg32
5517 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5518 {
5519 /* Prohibit these changes in the 64bit mode, since the
5520 lowering is more complicated. */
34828aad 5521 if (intel_syntax
ca61edf2 5522 && i.tm.opcode_modifier.todword
40fb9820 5523 && !i.types[0].bitfield.regxmm)
34828aad 5524 {
ca61edf2 5525 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5526 i.suffix = LONG_MNEM_SUFFIX;
5527 }
5528 else
5529 {
2b5d6a91 5530 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5531 register_prefix, i.op[op].regs->reg_name,
5532 i.suffix);
5533 return 0;
5534 }
252b5132 5535 }
29b0f896
AM		 5536 return 1;
5537}
252b5132 5538
29b0f896 5539static int
e3bb37b5 5540check_word_reg (void)
29b0f896
AM		 5541{
5542 int op;
5543 for (op = i.operands; --op >= 0;)
5544 /* Reject eight bit registers, except where the template requires
5545 them. (eg. movzb) */
40fb9820
L		 5546 if (i.types[op].bitfield.reg8
5547 && (i.tm.operand_types[op].bitfield.reg16
5548 || i.tm.operand_types[op].bitfield.reg32
5549 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5550 {
a540244d
L		 5551 as_bad (_("`%s%s' not allowed with `%s%c'"),
5552 register_prefix,
29b0f896
AM		 5553 i.op[op].regs->reg_name,
5554 i.tm.name,
5555 i.suffix);
5556 return 0;
5557 }
e4630f71 5558 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5559 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5560 && (i.types[op].bitfield.reg32
5561 || i.types[op].bitfield.reg64)
40fb9820
L		 5562 && (i.tm.operand_types[op].bitfield.reg16
5563 || i.tm.operand_types[op].bitfield.acc))
252b5132 5564 {
29b0f896
AM		 5565 /* Prohibit these changes in the 64bit mode, since the
5566 lowering is more complicated. */
5567 if (flag_code == CODE_64BIT)
252b5132 5568 {
2b5d6a91 5569 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5570 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5571 i.suffix);
5572 return 0;
252b5132 5573 }
29b0f896 5574#if REGISTER_WARNINGS
cecf1424
JB		 5575 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5576 register_prefix,
5577 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5578 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5579#endif
5580 }
5581 return 1;
5582}
252b5132 5583
29b0f896 5584static int
40fb9820 5585update_imm (unsigned int j)
29b0f896 5586{
bc0844ae 5587 i386_operand_type overlap = i.types[j];
40fb9820
L		 5588 if ((overlap.bitfield.imm8
5589 || overlap.bitfield.imm8s
5590 || overlap.bitfield.imm16
5591 || overlap.bitfield.imm32
5592 || overlap.bitfield.imm32s
5593 || overlap.bitfield.imm64)
0dfbf9d7
L		 5594 && !operand_type_equal (&overlap, &imm8)
5595 && !operand_type_equal (&overlap, &imm8s)
5596 && !operand_type_equal (&overlap, &imm16)
5597 && !operand_type_equal (&overlap, &imm32)
5598 && !operand_type_equal (&overlap, &imm32s)
5599 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5600 {
5601 if (i.suffix)
5602 {
40fb9820
L		 5603 i386_operand_type temp;
5604
0dfbf9d7 5605 operand_type_set (&temp, 0);
7ab9ffdd 5606 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5607 {
5608 temp.bitfield.imm8 = overlap.bitfield.imm8;
5609 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5610 }
5611 else if (i.suffix == WORD_MNEM_SUFFIX)
5612 temp.bitfield.imm16 = overlap.bitfield.imm16;
5613 else if (i.suffix == QWORD_MNEM_SUFFIX)
5614 {
5615 temp.bitfield.imm64 = overlap.bitfield.imm64;
5616 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5617 }
5618 else
5619 temp.bitfield.imm32 = overlap.bitfield.imm32;
5620 overlap = temp;
29b0f896 5621 }
0dfbf9d7
L		 5622 else if (operand_type_equal (&overlap, &imm16_32_32s)
5623 || operand_type_equal (&overlap, &imm16_32)
5624 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5625 {
40fb9820 5626 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5627 overlap = imm16;
40fb9820 5628 else
65da13b5 5629 overlap = imm32s;
29b0f896 5630 }
0dfbf9d7
L		 5631 if (!operand_type_equal (&overlap, &imm8)
5632 && !operand_type_equal (&overlap, &imm8s)
5633 && !operand_type_equal (&overlap, &imm16)
5634 && !operand_type_equal (&overlap, &imm32)
5635 && !operand_type_equal (&overlap, &imm32s)
5636 && !operand_type_equal (&overlap, &imm64))
29b0f896 5637 {
4eed87de
AM		 5638 as_bad (_("no instruction mnemonic suffix given; "
5639 "can't determine immediate size"));
29b0f896
AM		 5640 return 0;
5641 }
5642 }
40fb9820 5643 i.types[j] = overlap;
29b0f896 5644
40fb9820
L		 5645 return 1;
5646}
5647
5648static int
5649finalize_imm (void)
5650{
bc0844ae 5651 unsigned int j, n;
29b0f896 5652
bc0844ae
L		 5653 /* Update the first 2 immediate operands. */
5654 n = i.operands > 2 ? 2 : i.operands;
5655 if (n)
5656 {
5657 for (j = 0; j < n; j++)
5658 if (update_imm (j) == 0)
5659 return 0;
40fb9820 5660
bc0844ae
L		 5661 /* The 3rd operand can't be immediate operand. */
5662 gas_assert (operand_type_check (i.types[2], imm) == 0);
5663 }
29b0f896
AM		 5664
5665 return 1;
5666}
5667
c0f3af97
L		 5668static int
5669bad_implicit_operand (int xmm)
5670{
91d6fa6a
NC		 5671 const char *ireg = xmm ? "xmm0" : "ymm0";
5672
c0f3af97
L		 5673 if (intel_syntax)
5674 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5675 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5676 else
5677 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5678 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5679 return 0;
5680}
5681
29b0f896 5682static int
e3bb37b5 5683process_operands (void)
29b0f896
AM		 5684{
5685 /* Default segment register this instruction will use for memory
5686 accesses. 0 means unknown. This is only for optimizing out
5687 unnecessary segment overrides. */
5688 const seg_entry *default_seg = 0;
5689
2426c15f 5690 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5691 {
91d6fa6a
NC		 5692 unsigned int dupl = i.operands;
5693 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5694 unsigned int j;
5695
c0f3af97 5696 /* The destination must be an xmm register. */
9c2799c2 5697 gas_assert (i.reg_operands
91d6fa6a 5698 && MAX_OPERANDS > dupl
7ab9ffdd 5699 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5700
5701 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5702 {
c0f3af97 5703 /* The first operand is implicit and must be xmm0. */
9c2799c2 5704 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5705 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5706 return bad_implicit_operand (1);
5707
8cd7925b 5708 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5709 {
5710 /* Keep xmm0 for instructions with VEX prefix and 3
5711 sources. */
5712 goto duplicate;
5713 }
e2ec9d29 5714 else
c0f3af97
L		 5715 {
5716 /* We remove the first xmm0 and keep the number of
5717 operands unchanged, which in fact duplicates the
5718 destination. */
5719 for (j = 1; j < i.operands; j++)
5720 {
5721 i.op[j - 1] = i.op[j];
5722 i.types[j - 1] = i.types[j];
5723 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5724 }
5725 }
5726 }
5727 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5728 {
91d6fa6a 5729 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5730 && (i.tm.opcode_modifier.vexsources
5731 == VEX3SOURCES));
c0f3af97
L		 5732
5733 /* Add the implicit xmm0 for instructions with VEX prefix
5734 and 3 sources. */
5735 for (j = i.operands; j > 0; j--)
5736 {
5737 i.op[j] = i.op[j - 1];
5738 i.types[j] = i.types[j - 1];
5739 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5740 }
5741 i.op[0].regs
5742 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5743 i.types[0] = regxmm;
c0f3af97
L		 5744 i.tm.operand_types[0] = regxmm;
5745
5746 i.operands += 2;
5747 i.reg_operands += 2;
5748 i.tm.operands += 2;
5749
91d6fa6a 5750 dupl++;
c0f3af97 5751 dest++;
91d6fa6a
NC		 5752 i.op[dupl] = i.op[dest];
5753 i.types[dupl] = i.types[dest];
5754 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5755 }
c0f3af97
L		 5756 else
5757 {
5758duplicate:
5759 i.operands++;
5760 i.reg_operands++;
5761 i.tm.operands++;
5762
91d6fa6a
NC		 5763 i.op[dupl] = i.op[dest];
5764 i.types[dupl] = i.types[dest];
5765 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5766 }
5767
5768 if (i.tm.opcode_modifier.immext)
5769 process_immext ();
5770 }
5771 else if (i.tm.opcode_modifier.firstxmm0)
5772 {
5773 unsigned int j;
5774
43234a1e 5775 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5776 gas_assert (i.reg_operands
7ab9ffdd 5777 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5778 || operand_type_equal (&i.types[0], &regymm)
5779 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5780 if (register_number (i.op[0].regs) != 0)
c0f3af97 5781 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5782
5783 for (j = 1; j < i.operands; j++)
5784 {
5785 i.op[j - 1] = i.op[j];
5786 i.types[j - 1] = i.types[j];
5787
5788 /* We need to adjust fields in i.tm since they are used by
5789 build_modrm_byte. */
5790 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5791 }
5792
e2ec9d29
L		 5793 i.operands--;
5794 i.reg_operands--;
e2ec9d29
L		 5795 i.tm.operands--;
5796 }
5797 else if (i.tm.opcode_modifier.regkludge)
5798 {
5799 /* The imul $imm, %reg instruction is converted into
5800 imul $imm, %reg, %reg, and the clr %reg instruction
5801 is converted into xor %reg, %reg. */
5802
5803 unsigned int first_reg_op;
5804
5805 if (operand_type_check (i.types[0], reg))
5806 first_reg_op = 0;
5807 else
5808 first_reg_op = 1;
5809 /* Pretend we saw the extra register operand. */
9c2799c2 5810 gas_assert (i.reg_operands == 1
7ab9ffdd 5811 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5812 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5813 i.types[first_reg_op + 1] = i.types[first_reg_op];
5814 i.operands++;
5815 i.reg_operands++;
29b0f896
AM		 5816 }
5817
40fb9820 5818 if (i.tm.opcode_modifier.shortform)
29b0f896 5819 {
40fb9820
L		 5820 if (i.types[0].bitfield.sreg2
5821 || i.types[0].bitfield.sreg3)
29b0f896 5822 {
4eed87de
AM		 5823 if (i.tm.base_opcode == POP_SEG_SHORT
5824 && i.op[0].regs->reg_num == 1)
29b0f896 5825 {
a87af027 5826 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5827 return 0;
29b0f896 5828 }
4eed87de
AM		 5829 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5830 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5831 i.rex |= REX_B;
4eed87de
AM		 5832 }
5833 else
5834 {
7ab9ffdd 5835 /* The register or float register operand is in operand
85f10a01 5836 0 or 1. */
40fb9820 5837 unsigned int op;
7ab9ffdd
L		 5838
5839 if (i.types[0].bitfield.floatreg
5840 || operand_type_check (i.types[0], reg))
5841 op = 0;
5842 else
5843 op = 1;
4eed87de
AM		 5844 /* Register goes in low 3 bits of opcode. */
5845 i.tm.base_opcode |= i.op[op].regs->reg_num;
5846 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5847 i.rex |= REX_B;
40fb9820 5848 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5849 {
4eed87de
AM		 5850 /* Warn about some common errors, but press on regardless.
5851 The first case can be generated by gcc (<= 2.8.1). */
5852 if (i.operands == 2)
5853 {
5854 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5855 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5856 register_prefix, i.op[!intel_syntax].regs->reg_name,
5857 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5858 }
5859 else
5860 {
5861 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5862 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5863 register_prefix, i.op[0].regs->reg_name);
4eed87de 5864 }
29b0f896
AM		 5865 }
5866 }
5867 }
40fb9820 5868 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5869 {
5870 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5871 must be put into the modrm byte). Now, we make the modrm and
5872 index base bytes based on all the info we've collected. */
29b0f896
AM		 5873
5874 default_seg = build_modrm_byte ();
5875 }
8a2ed489 5876 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5877 {
5878 default_seg = &ds;
5879 }
40fb9820 5880 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5881 {
5882 /* For the string instructions that allow a segment override
5883 on one of their operands, the default segment is ds. */
5884 default_seg = &ds;
5885 }
5886
75178d9d
L		 5887 if (i.tm.base_opcode == 0x8d /* lea */
5888 && i.seg[0]
5889 && !quiet_warnings)
30123838 5890 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5891
5892 /* If a segment was explicitly specified, and the specified segment
5893 is not the default, use an opcode prefix to select it. If we
5894 never figured out what the default segment is, then default_seg
5895 will be zero at this point, and the specified segment prefix will
5896 always be used. */
29b0f896
AM		 5897 if ((i.seg[0]) && (i.seg[0] != default_seg))
5898 {
5899 if (!add_prefix (i.seg[0]->seg_prefix))
5900 return 0;
5901 }
5902 return 1;
5903}
5904
5905static const seg_entry *
e3bb37b5 5906build_modrm_byte (void)
29b0f896
AM		 5907{
5908 const seg_entry *default_seg = 0;
c0f3af97 5909 unsigned int source, dest;
8cd7925b 5910 int vex_3_sources;
c0f3af97
L		 5911
5912 /* The first operand of instructions with VEX prefix and 3 sources
5913 must be VEX_Imm4. */
8cd7925b 5914 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5915 if (vex_3_sources)
5916 {
91d6fa6a 5917 unsigned int nds, reg_slot;
4c2c6516 5918 expressionS *exp;
c0f3af97 5919
922d8de8 5920 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5921 && i.tm.opcode_modifier.immext)
5922 {
5923 dest = i.operands - 2;
5924 gas_assert (dest == 3);
5925 }
922d8de8 5926 else
a683cc34 5927 dest = i.operands - 1;
c0f3af97 5928 nds = dest - 1;
922d8de8 5929
a683cc34
SP		 5930 /* There are 2 kinds of instructions:
5931 1. 5 operands: 4 register operands or 3 register operands
5932 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5933 VexW0 or VexW1. The destination must be either XMM, YMM or
5934 ZMM register.
a683cc34
SP		 5935 2. 4 operands: 4 register operands or 3 register operands
5936 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5937 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5938 || (i.reg_operands == 3 && i.mem_operands == 1))
5939 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5940 && (i.tm.opcode_modifier.veximmext
5941 || (i.imm_operands == 1
5942 && i.types[0].bitfield.vec_imm4
5943 && (i.tm.opcode_modifier.vexw == VEXW0
5944 || i.tm.opcode_modifier.vexw == VEXW1)
5945 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5946 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5947 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5948
5949 if (i.imm_operands == 0)
5950 {
5951 /* When there is no immediate operand, generate an 8bit
5952 immediate operand to encode the first operand. */
5953 exp = &im_expressions[i.imm_operands++];
5954 i.op[i.operands].imms = exp;
5955 i.types[i.operands] = imm8;
5956 i.operands++;
5957 /* If VexW1 is set, the first operand is the source and
5958 the second operand is encoded in the immediate operand. */
5959 if (i.tm.opcode_modifier.vexw == VEXW1)
5960 {
5961 source = 0;
5962 reg_slot = 1;
5963 }
5964 else
5965 {
5966 source = 1;
5967 reg_slot = 0;
5968 }
5969
5970 /* FMA swaps REG and NDS. */
5971 if (i.tm.cpu_flags.bitfield.cpufma)
5972 {
5973 unsigned int tmp;
5974 tmp = reg_slot;
5975 reg_slot = nds;
5976 nds = tmp;
5977 }
5978
24981e7b
L		 5979 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5980 &regxmm)
a683cc34 5981 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 5982 &regymm)
5983 || operand_type_equal (&i.tm.operand_types[reg_slot],
5984 &regzmm));
a683cc34 5985 exp->X_op = O_constant;
4c692bc7 5986 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 5987 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
5988 }
922d8de8 5989 else
a683cc34
SP		 5990 {
5991 unsigned int imm_slot;
5992
5993 if (i.tm.opcode_modifier.vexw == VEXW0)
5994 {
5995 /* If VexW0 is set, the third operand is the source and
5996 the second operand is encoded in the immediate
5997 operand. */
5998 source = 2;
5999 reg_slot = 1;
6000 }
6001 else
6002 {
6003 /* VexW1 is set, the second operand is the source and
6004 the third operand is encoded in the immediate
6005 operand. */
6006 source = 1;
6007 reg_slot = 2;
6008 }
6009
6010 if (i.tm.opcode_modifier.immext)
6011 {
6012 /* When ImmExt is set, the immdiate byte is the last
6013 operand. */
6014 imm_slot = i.operands - 1;
6015 source--;
6016 reg_slot--;
6017 }
6018 else
6019 {
6020 imm_slot = 0;
6021
6022 /* Turn on Imm8 so that output_imm will generate it. */
6023 i.types[imm_slot].bitfield.imm8 = 1;
6024 }
6025
24981e7b
L		 6026 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6027 &regxmm)
6028 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6029 &regymm)
6030 || operand_type_equal (&i.tm.operand_types[reg_slot],
6031 &regzmm));
a683cc34 6032 i.op[imm_slot].imms->X_add_number
4c692bc7 6033 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6034 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6035 }
6036
6037 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6038 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6039 &regymm)
6040 || operand_type_equal (&i.tm.operand_types[nds],
6041 &regzmm));
dae39acc 6042 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6043 }
6044 else
6045 source = dest = 0;
29b0f896
AM		 6046
6047 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6048 implicit registers do not count. If there are 3 register
6049 operands, it must be a instruction with VexNDS. For a
6050 instruction with VexNDD, the destination register is encoded
6051 in VEX prefix. If there are 4 register operands, it must be
6052 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6053 if (i.mem_operands == 0
6054 && ((i.reg_operands == 2
2426c15f 6055 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6056 || (i.reg_operands == 3
2426c15f 6057 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6058 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6059 {
cab737b9
L		 6060 switch (i.operands)
6061 {
6062 case 2:
6063 source = 0;
6064 break;
6065 case 3:
c81128dc
L		 6066 /* When there are 3 operands, one of them may be immediate,
6067 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6068 the first operand must be shift count register (cl) or it
6069 is an instruction with VexNDS. */
9c2799c2 6070 gas_assert (i.imm_operands == 1
7ab9ffdd 6071 || (i.imm_operands == 0
2426c15f 6072 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6073 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6074 if (operand_type_check (i.types[0], imm)
6075 || i.types[0].bitfield.shiftcount)
6076 source = 1;
6077 else
6078 source = 0;
cab737b9
L		 6079 break;
6080 case 4:
368d64cc
L		 6081 /* When there are 4 operands, the first two must be 8bit
6082 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6083 one.
6084
6085 For instructions with VexNDS, if the first operand
6086 an imm8, the source operand is the 2nd one. If the last
6087 operand is imm8, the source operand is the first one. */
9c2799c2 6088 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6089 && i.types[0].bitfield.imm8
6090 && i.types[1].bitfield.imm8)
2426c15f 6091 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6092 && i.imm_operands == 1
6093 && (i.types[0].bitfield.imm8
43234a1e
L		 6094 || i.types[i.operands - 1].bitfield.imm8
6095 || i.rounding)));
9f2670f2
L		 6096 if (i.imm_operands == 2)
6097 source = 2;
6098 else
c0f3af97
L		 6099 {
6100 if (i.types[0].bitfield.imm8)
6101 source = 1;
6102 else
6103 source = 0;
6104 }
c0f3af97
L		 6105 break;
6106 case 5:
43234a1e
L		 6107 if (i.tm.opcode_modifier.evex)
6108 {
6109 /* For EVEX instructions, when there are 5 operands, the
6110 first one must be immediate operand. If the second one
6111 is immediate operand, the source operand is the 3th
6112 one. If the last one is immediate operand, the source
6113 operand is the 2nd one. */
6114 gas_assert (i.imm_operands == 2
6115 && i.tm.opcode_modifier.sae
6116 && operand_type_check (i.types[0], imm));
6117 if (operand_type_check (i.types[1], imm))
6118 source = 2;
6119 else if (operand_type_check (i.types[4], imm))
6120 source = 1;
6121 else
6122 abort ();
6123 }
cab737b9
L		 6124 break;
6125 default:
6126 abort ();
6127 }
6128
c0f3af97
L		 6129 if (!vex_3_sources)
6130 {
6131 dest = source + 1;
6132
43234a1e
L		 6133 /* RC/SAE operand could be between DEST and SRC. That happens
6134 when one operand is GPR and the other one is XMM/YMM/ZMM
6135 register. */
6136 if (i.rounding && i.rounding->operand == (int) dest)
6137 dest++;
6138
2426c15f 6139 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6140 {
43234a1e
L		 6141 /* For instructions with VexNDS, the register-only source
6142 operand must be 32/64bit integer, XMM, YMM or ZMM
6143 register. It is encoded in VEX prefix. We need to
6144 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6145
6146 i386_operand_type op;
6147 unsigned int vvvv;
6148
6149 /* Check register-only source operand when two source
6150 operands are swapped. */
6151 if (!i.tm.operand_types[source].bitfield.baseindex
6152 && i.tm.operand_types[dest].bitfield.baseindex)
6153 {
6154 vvvv = source;
6155 source = dest;
6156 }
6157 else
6158 vvvv = dest;
6159
6160 op = i.tm.operand_types[vvvv];
fa99fab2 6161 op.bitfield.regmem = 0;
c0f3af97 6162 if ((dest + 1) >= i.operands
f12dc422
L		 6163 || (op.bitfield.reg32 != 1
6164 && !op.bitfield.reg64 != 1
6165 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6166 && !operand_type_equal (&op, &regymm)
6167 && !operand_type_equal (&op, &regzmm)
6168 && !operand_type_equal (&op, &regmask)))
c0f3af97 6169 abort ();
f12dc422 6170 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6171 dest++;
6172 }
6173 }
29b0f896
AM		 6174
6175 i.rm.mode = 3;
6176 /* One of the register operands will be encoded in the i.tm.reg
6177 field, the other in the combined i.tm.mode and i.tm.regmem
6178 fields. If no form of this instruction supports a memory
6179 destination operand, then we assume the source operand may
6180 sometimes be a memory operand and so we need to store the
6181 destination in the i.rm.reg field. */
40fb9820
L		 6182 if (!i.tm.operand_types[dest].bitfield.regmem
6183 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6184 {
6185 i.rm.reg = i.op[dest].regs->reg_num;
6186 i.rm.regmem = i.op[source].regs->reg_num;
6187 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6188 i.rex |= REX_R;
43234a1e
L		 6189 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6190 i.vrex |= REX_R;
29b0f896 6191 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6192 i.rex |= REX_B;
43234a1e
L		 6193 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6194 i.vrex |= REX_B;
29b0f896
AM		 6195 }
6196 else
6197 {
6198 i.rm.reg = i.op[source].regs->reg_num;
6199 i.rm.regmem = i.op[dest].regs->reg_num;
6200 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6201 i.rex |= REX_B;
43234a1e
L		 6202 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6203 i.vrex |= REX_B;
29b0f896 6204 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6205 i.rex |= REX_R;
43234a1e
L		 6206 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6207 i.vrex |= REX_R;
29b0f896 6208 }
161a04f6 6209 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6210 {
40fb9820
L		 6211 if (!i.types[0].bitfield.control
6212 && !i.types[1].bitfield.control)
c4a530c5 6213 abort ();
161a04f6 6214 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6215 add_prefix (LOCK_PREFIX_OPCODE);
6216 }
29b0f896
AM		 6217 }
6218 else
6219 { /* If it's not 2 reg operands... */
c0f3af97
L		 6220 unsigned int mem;
6221
29b0f896
AM		 6222 if (i.mem_operands)
6223 {
6224 unsigned int fake_zero_displacement = 0;
99018f42 6225 unsigned int op;
4eed87de 6226
7ab9ffdd
L		 6227 for (op = 0; op < i.operands; op++)
6228 if (operand_type_check (i.types[op], anymem))
6229 break;
7ab9ffdd 6230 gas_assert (op < i.operands);
29b0f896 6231
6c30d220
L		 6232 if (i.tm.opcode_modifier.vecsib)
6233 {
6234 if (i.index_reg->reg_num == RegEiz
6235 || i.index_reg->reg_num == RegRiz)
6236 abort ();
6237
6238 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6239 if (!i.base_reg)
6240 {
6241 i.sib.base = NO_BASE_REGISTER;
6242 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6243 /* No Vec_Disp8 if there is no base. */
6244 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6245 i.types[op].bitfield.disp8 = 0;
6246 i.types[op].bitfield.disp16 = 0;
6247 i.types[op].bitfield.disp64 = 0;
6248 if (flag_code != CODE_64BIT)
6249 {
6250 /* Must be 32 bit */
6251 i.types[op].bitfield.disp32 = 1;
6252 i.types[op].bitfield.disp32s = 0;
6253 }
6254 else
6255 {
6256 i.types[op].bitfield.disp32 = 0;
6257 i.types[op].bitfield.disp32s = 1;
6258 }
6259 }
6260 i.sib.index = i.index_reg->reg_num;
6261 if ((i.index_reg->reg_flags & RegRex) != 0)
6262 i.rex |= REX_X;
43234a1e
L		 6263 if ((i.index_reg->reg_flags & RegVRex) != 0)
6264 i.vrex |= REX_X;
6c30d220
L		 6265 }
6266
29b0f896
AM		 6267 default_seg = &ds;
6268
6269 if (i.base_reg == 0)
6270 {
6271 i.rm.mode = 0;
6272 if (!i.disp_operands)
6c30d220
L		 6273 {
6274 fake_zero_displacement = 1;
6275 /* Instructions with VSIB byte need 32bit displacement
6276 if there is no base register. */
6277 if (i.tm.opcode_modifier.vecsib)
6278 i.types[op].bitfield.disp32 = 1;
6279 }
29b0f896
AM		 6280 if (i.index_reg == 0)
6281 {
6c30d220 6282 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6283 /* Operand is just <disp> */
20f0a1fc 6284 if (flag_code == CODE_64BIT)
29b0f896
AM		 6285 {
6286 /* 64bit mode overwrites the 32bit absolute
6287 addressing by RIP relative addressing and
6288 absolute addressing is encoded by one of the
6289 redundant SIB forms. */
6290 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6291 i.sib.base = NO_BASE_REGISTER;
6292 i.sib.index = NO_INDEX_REGISTER;
fc225355 6293 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6294 ? disp32s : disp32);
20f0a1fc 6295 }
fc225355
L		 6296 else if ((flag_code == CODE_16BIT)
6297 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6298 {
6299 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6300 i.types[op] = disp16;
20f0a1fc
NC		 6301 }
6302 else
6303 {
6304 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6305 i.types[op] = disp32;
29b0f896
AM		 6306 }
6307 }
6c30d220 6308 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6309 {
6c30d220 6310 /* !i.base_reg && i.index_reg */
db51cc60
L		 6311 if (i.index_reg->reg_num == RegEiz
6312 || i.index_reg->reg_num == RegRiz)
6313 i.sib.index = NO_INDEX_REGISTER;
6314 else
6315 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6316 i.sib.base = NO_BASE_REGISTER;
6317 i.sib.scale = i.log2_scale_factor;
6318 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6319 /* No Vec_Disp8 if there is no base. */
6320 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6321 i.types[op].bitfield.disp8 = 0;
6322 i.types[op].bitfield.disp16 = 0;
6323 i.types[op].bitfield.disp64 = 0;
29b0f896 6324 if (flag_code != CODE_64BIT)
40fb9820
L		 6325 {
6326 /* Must be 32 bit */
6327 i.types[op].bitfield.disp32 = 1;
6328 i.types[op].bitfield.disp32s = 0;
6329 }
29b0f896 6330 else
40fb9820
L		 6331 {
6332 i.types[op].bitfield.disp32 = 0;
6333 i.types[op].bitfield.disp32s = 1;
6334 }
29b0f896 6335 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6336 i.rex |= REX_X;
29b0f896
AM		 6337 }
6338 }
6339 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6340 else if (i.base_reg->reg_num == RegRip ||
6341 i.base_reg->reg_num == RegEip)
29b0f896 6342 {
6c30d220 6343 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6344 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6345 i.types[op].bitfield.disp8 = 0;
6346 i.types[op].bitfield.disp16 = 0;
6347 i.types[op].bitfield.disp32 = 0;
6348 i.types[op].bitfield.disp32s = 1;
6349 i.types[op].bitfield.disp64 = 0;
43234a1e 6350 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6351 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6352 if (! i.disp_operands)
6353 fake_zero_displacement = 1;
29b0f896 6354 }
40fb9820 6355 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6356 {
6c30d220 6357 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6358 switch (i.base_reg->reg_num)
6359 {
6360 case 3: /* (%bx) */
6361 if (i.index_reg == 0)
6362 i.rm.regmem = 7;
6363 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6364 i.rm.regmem = i.index_reg->reg_num - 6;
6365 break;
6366 case 5: /* (%bp) */
6367 default_seg = &ss;
6368 if (i.index_reg == 0)
6369 {
6370 i.rm.regmem = 6;
40fb9820 6371 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6372 {
6373 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6374 if (i.tm.operand_types[op].bitfield.vec_disp8)
6375 i.types[op].bitfield.vec_disp8 = 1;
6376 else
6377 i.types[op].bitfield.disp8 = 1;
252b5132 6378 fake_zero_displacement = 1;
29b0f896
AM		 6379 }
6380 }
6381 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6382 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6383 break;
6384 default: /* (%si) -> 4 or (%di) -> 5 */
6385 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6386 }
6387 i.rm.mode = mode_from_disp_size (i.types[op]);
6388 }
6389 else /* i.base_reg and 32/64 bit mode */
6390 {
6391 if (flag_code == CODE_64BIT
40fb9820
L		 6392 && operand_type_check (i.types[op], disp))
6393 {
6394 i386_operand_type temp;
0dfbf9d7 6395 operand_type_set (&temp, 0);
40fb9820 6396 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6397 temp.bitfield.vec_disp8
6398 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6399 i.types[op] = temp;
6400 if (i.prefix[ADDR_PREFIX] == 0)
6401 i.types[op].bitfield.disp32s = 1;
6402 else
6403 i.types[op].bitfield.disp32 = 1;
6404 }
20f0a1fc 6405
6c30d220
L		 6406 if (!i.tm.opcode_modifier.vecsib)
6407 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6408 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6409 i.rex |= REX_B;
29b0f896
AM		 6410 i.sib.base = i.base_reg->reg_num;
6411 /* x86-64 ignores REX prefix bit here to avoid decoder
6412 complications. */
848930b2
JB		 6413 if (!(i.base_reg->reg_flags & RegRex)
6414 && (i.base_reg->reg_num == EBP_REG_NUM
6415 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6416 default_seg = &ss;
848930b2 6417 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6418 {
848930b2 6419 fake_zero_displacement = 1;
43234a1e
L		 6420 if (i.tm.operand_types [op].bitfield.vec_disp8)
6421 i.types[op].bitfield.vec_disp8 = 1;
6422 else
6423 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6424 }
6425 i.sib.scale = i.log2_scale_factor;
6426 if (i.index_reg == 0)
6427 {
6c30d220 6428 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6429 /* <disp>(%esp) becomes two byte modrm with no index
6430 register. We've already stored the code for esp
6431 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6432 Any base register besides %esp will not use the
6433 extra modrm byte. */
6434 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6435 }
6c30d220 6436 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6437 {
db51cc60
L		 6438 if (i.index_reg->reg_num == RegEiz
6439 || i.index_reg->reg_num == RegRiz)
6440 i.sib.index = NO_INDEX_REGISTER;
6441 else
6442 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6443 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6444 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6445 i.rex |= REX_X;
29b0f896 6446 }
67a4f2b7
AO		 6447
6448 if (i.disp_operands
6449 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6450 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6451 i.rm.mode = 0;
6452 else
a501d77e
L		 6453 {
6454 if (!fake_zero_displacement
6455 && !i.disp_operands
6456 && i.disp_encoding)
6457 {
6458 fake_zero_displacement = 1;
6459 if (i.disp_encoding == disp_encoding_8bit)
6460 i.types[op].bitfield.disp8 = 1;
6461 else
6462 i.types[op].bitfield.disp32 = 1;
6463 }
6464 i.rm.mode = mode_from_disp_size (i.types[op]);
6465 }
29b0f896 6466 }
252b5132 6467
29b0f896
AM		 6468 if (fake_zero_displacement)
6469 {
6470 /* Fakes a zero displacement assuming that i.types[op]
6471 holds the correct displacement size. */
6472 expressionS *exp;
6473
9c2799c2 6474 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6475 exp = &disp_expressions[i.disp_operands++];
6476 i.op[op].disps = exp;
6477 exp->X_op = O_constant;
6478 exp->X_add_number = 0;
6479 exp->X_add_symbol = (symbolS *) 0;
6480 exp->X_op_symbol = (symbolS *) 0;
6481 }
c0f3af97
L		 6482
6483 mem = op;
29b0f896 6484 }
c0f3af97
L		 6485 else
6486 mem = ~0;
252b5132 6487
8c43a48b 6488 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6489 {
6490 if (operand_type_check (i.types[0], imm))
6491 i.vex.register_specifier = NULL;
6492 else
6493 {
6494 /* VEX.vvvv encodes one of the sources when the first
6495 operand is not an immediate. */
1ef99a7b 6496 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6497 i.vex.register_specifier = i.op[0].regs;
6498 else
6499 i.vex.register_specifier = i.op[1].regs;
6500 }
6501
6502 /* Destination is a XMM register encoded in the ModRM.reg
6503 and VEX.R bit. */
6504 i.rm.reg = i.op[2].regs->reg_num;
6505 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6506 i.rex |= REX_R;
6507
6508 /* ModRM.rm and VEX.B encodes the other source. */
6509 if (!i.mem_operands)
6510 {
6511 i.rm.mode = 3;
6512
1ef99a7b 6513 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6514 i.rm.regmem = i.op[1].regs->reg_num;
6515 else
6516 i.rm.regmem = i.op[0].regs->reg_num;
6517
6518 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6519 i.rex |= REX_B;
6520 }
6521 }
2426c15f 6522 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6523 {
6524 i.vex.register_specifier = i.op[2].regs;
6525 if (!i.mem_operands)
6526 {
6527 i.rm.mode = 3;
6528 i.rm.regmem = i.op[1].regs->reg_num;
6529 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6530 i.rex |= REX_B;
6531 }
6532 }
29b0f896
AM		 6533 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6534 (if any) based on i.tm.extension_opcode. Again, we must be
6535 careful to make sure that segment/control/debug/test/MMX
6536 registers are coded into the i.rm.reg field. */
f88c9eb0 6537 else if (i.reg_operands)
29b0f896 6538 {
99018f42 6539 unsigned int op;
7ab9ffdd
L		 6540 unsigned int vex_reg = ~0;
6541
6542 for (op = 0; op < i.operands; op++)
6543 if (i.types[op].bitfield.reg8
6544 || i.types[op].bitfield.reg16
6545 || i.types[op].bitfield.reg32
6546 || i.types[op].bitfield.reg64
6547 || i.types[op].bitfield.regmmx
6548 || i.types[op].bitfield.regxmm
6549 || i.types[op].bitfield.regymm
7e8b059b 6550 || i.types[op].bitfield.regbnd
43234a1e
L		 6551 || i.types[op].bitfield.regzmm
6552 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6553 || i.types[op].bitfield.sreg2
6554 || i.types[op].bitfield.sreg3
6555 || i.types[op].bitfield.control
6556 || i.types[op].bitfield.debug
6557 || i.types[op].bitfield.test)
6558 break;
c0209578 6559
7ab9ffdd
L		 6560 if (vex_3_sources)
6561 op = dest;
2426c15f 6562 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6563 {
6564 /* For instructions with VexNDS, the register-only
6565 source operand is encoded in VEX prefix. */
6566 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6567
7ab9ffdd 6568 if (op > mem)
c0f3af97 6569 {
7ab9ffdd
L		 6570 vex_reg = op++;
6571 gas_assert (op < i.operands);
c0f3af97
L		 6572 }
6573 else
c0f3af97 6574 {
f12dc422
L		 6575 /* Check register-only source operand when two source
6576 operands are swapped. */
6577 if (!i.tm.operand_types[op].bitfield.baseindex
6578 && i.tm.operand_types[op + 1].bitfield.baseindex)
6579 {
6580 vex_reg = op;
6581 op += 2;
6582 gas_assert (mem == (vex_reg + 1)
6583 && op < i.operands);
6584 }
6585 else
6586 {
6587 vex_reg = op + 1;
6588 gas_assert (vex_reg < i.operands);
6589 }
c0f3af97 6590 }
7ab9ffdd 6591 }
2426c15f 6592 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6593 {
f12dc422 6594 /* For instructions with VexNDD, the register destination
7ab9ffdd 6595 is encoded in VEX prefix. */
f12dc422
L		 6596 if (i.mem_operands == 0)
6597 {
6598 /* There is no memory operand. */
6599 gas_assert ((op + 2) == i.operands);
6600 vex_reg = op + 1;
6601 }
6602 else
8d63c93e 6603 {
f12dc422
L		 6604 /* There are only 2 operands. */
6605 gas_assert (op < 2 && i.operands == 2);
6606 vex_reg = 1;
6607 }
7ab9ffdd
L		 6608 }
6609 else
6610 gas_assert (op < i.operands);
99018f42 6611
7ab9ffdd
L		 6612 if (vex_reg != (unsigned int) ~0)
6613 {
f12dc422 6614 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6615
f12dc422
L		 6616 if (type->bitfield.reg32 != 1
6617 && type->bitfield.reg64 != 1
6618 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6619 && !operand_type_equal (type, &regymm)
6620 && !operand_type_equal (type, &regzmm)
6621 && !operand_type_equal (type, &regmask))
7ab9ffdd 6622 abort ();
f88c9eb0 6623
7ab9ffdd
L		 6624 i.vex.register_specifier = i.op[vex_reg].regs;
6625 }
6626
1b9f0c97
L		 6627 /* Don't set OP operand twice. */
6628 if (vex_reg != op)
7ab9ffdd 6629 {
1b9f0c97
L		 6630 /* If there is an extension opcode to put here, the
6631 register number must be put into the regmem field. */
6632 if (i.tm.extension_opcode != None)
6633 {
6634 i.rm.regmem = i.op[op].regs->reg_num;
6635 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6636 i.rex |= REX_B;
43234a1e
L		 6637 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6638 i.vrex |= REX_B;
1b9f0c97
L		 6639 }
6640 else
6641 {
6642 i.rm.reg = i.op[op].regs->reg_num;
6643 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6644 i.rex |= REX_R;
43234a1e
L		 6645 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6646 i.vrex |= REX_R;
1b9f0c97 6647 }
7ab9ffdd 6648 }
252b5132 6649
29b0f896
AM		 6650 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6651 must set it to 3 to indicate this is a register operand
6652 in the regmem field. */
6653 if (!i.mem_operands)
6654 i.rm.mode = 3;
6655 }
252b5132 6656
29b0f896 6657 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6658 if (i.tm.extension_opcode != None)
29b0f896
AM		 6659 i.rm.reg = i.tm.extension_opcode;
6660 }
6661 return default_seg;
6662}
252b5132 6663
29b0f896 6664static void
e3bb37b5 6665output_branch (void)
29b0f896
AM		 6666{
6667 char *p;
f8a5c266 6668 int size;
29b0f896
AM		 6669 int code16;
6670 int prefix;
6671 relax_substateT subtype;
6672 symbolS *sym;
6673 offsetT off;
6674
f8a5c266 6675 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6676 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6677
6678 prefix = 0;
6679 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6680 {
29b0f896
AM		 6681 prefix = 1;
6682 i.prefixes -= 1;
6683 code16 ^= CODE16;
252b5132 6684 }
29b0f896
AM		 6685 /* Pentium4 branch hints. */
6686 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6687 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6688 {
29b0f896
AM		 6689 prefix++;
6690 i.prefixes--;
6691 }
6692 if (i.prefix[REX_PREFIX] != 0)
6693 {
6694 prefix++;
6695 i.prefixes--;
2f66722d
AM		 6696 }
6697
7e8b059b
L		 6698 /* BND prefixed jump. */
6699 if (i.prefix[BND_PREFIX] != 0)
6700 {
6701 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6702 i.prefixes -= 1;
6703 }
6704
29b0f896
AM		 6705 if (i.prefixes != 0 && !intel_syntax)
6706 as_warn (_("skipping prefixes on this instruction"));
6707
6708 /* It's always a symbol; End frag & setup for relax.
6709 Make sure there is enough room in this frag for the largest
6710 instruction we may generate in md_convert_frag. This is 2
6711 bytes for the opcode and room for the prefix and largest
6712 displacement. */
6713 frag_grow (prefix + 2 + 4);
6714 /* Prefix and 1 opcode byte go in fr_fix. */
6715 p = frag_more (prefix + 1);
6716 if (i.prefix[DATA_PREFIX] != 0)
6717 *p++ = DATA_PREFIX_OPCODE;
6718 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6719 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6720 *p++ = i.prefix[SEG_PREFIX];
6721 if (i.prefix[REX_PREFIX] != 0)
6722 *p++ = i.prefix[REX_PREFIX];
6723 *p = i.tm.base_opcode;
6724
6725 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6726 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6727 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6728 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6729 else
f8a5c266 6730 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6731 subtype |= code16;
3e73aa7c 6732
29b0f896
AM		 6733 sym = i.op[0].disps->X_add_symbol;
6734 off = i.op[0].disps->X_add_number;
3e73aa7c 6735
29b0f896
AM		 6736 if (i.op[0].disps->X_op != O_constant
6737 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6738 {
29b0f896
AM		 6739 /* Handle complex expressions. */
6740 sym = make_expr_symbol (i.op[0].disps);
6741 off = 0;
6742 }
3e73aa7c 6743
29b0f896
AM		 6744 /* 1 possible extra opcode + 4 byte displacement go in var part.
6745 Pass reloc in fr_var. */
c3320543
L		 6746 frag_var (rs_machine_dependent, 5,
6747 ((!object_64bit
6748 || i.reloc[0] != NO_RELOC
6749 || (i.bnd_prefix == NULL && !add_bnd_prefix))
6750 ? i.reloc[0]
6751 : BFD_RELOC_X86_64_PC32_BND),
6752 subtype, sym, off, p);
29b0f896 6753}
3e73aa7c 6754
29b0f896 6755static void
e3bb37b5 6756output_jump (void)
29b0f896
AM		 6757{
6758 char *p;
6759 int size;
3e02c1cc 6760 fixS *fixP;
29b0f896 6761
40fb9820 6762 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6763 {
6764 /* This is a loop or jecxz type instruction. */
6765 size = 1;
6766 if (i.prefix[ADDR_PREFIX] != 0)
6767 {
6768 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6769 i.prefixes -= 1;
6770 }
6771 /* Pentium4 branch hints. */
6772 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6773 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6774 {
6775 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6776 i.prefixes--;
3e73aa7c
JH		 6777 }
6778 }
29b0f896
AM		 6779 else
6780 {
6781 int code16;
3e73aa7c 6782
29b0f896
AM		 6783 code16 = 0;
6784 if (flag_code == CODE_16BIT)
6785 code16 = CODE16;
3e73aa7c 6786
29b0f896
AM		 6787 if (i.prefix[DATA_PREFIX] != 0)
6788 {
6789 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6790 i.prefixes -= 1;
6791 code16 ^= CODE16;
6792 }
252b5132 6793
29b0f896
AM		 6794 size = 4;
6795 if (code16)
6796 size = 2;
6797 }
9fcc94b6 6798
29b0f896
AM		 6799 if (i.prefix[REX_PREFIX] != 0)
6800 {
6801 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6802 i.prefixes -= 1;
6803 }
252b5132 6804
7e8b059b
L		 6805 /* BND prefixed jump. */
6806 if (i.prefix[BND_PREFIX] != 0)
6807 {
6808 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6809 i.prefixes -= 1;
6810 }
6811
29b0f896
AM		 6812 if (i.prefixes != 0 && !intel_syntax)
6813 as_warn (_("skipping prefixes on this instruction"));
e0890092 6814
42164a71
L		 6815 p = frag_more (i.tm.opcode_length + size);
6816 switch (i.tm.opcode_length)
6817 {
6818 case 2:
6819 *p++ = i.tm.base_opcode >> 8;
6820 case 1:
6821 *p++ = i.tm.base_opcode;
6822 break;
6823 default:
6824 abort ();
6825 }
e0890092 6826
3e02c1cc 6827 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543
L		 6828 i.op[0].disps, 1, reloc (size, 1, 1,
6829 (i.bnd_prefix != NULL
6830 || add_bnd_prefix),
6831 i.reloc[0]));
3e02c1cc
AM		 6832
6833 /* All jumps handled here are signed, but don't use a signed limit
6834 check for 32 and 16 bit jumps as we want to allow wrap around at
6835 4G and 64k respectively. */
6836 if (size == 1)
6837 fixP->fx_signed = 1;
29b0f896 6838}
e0890092 6839
29b0f896 6840static void
e3bb37b5 6841output_interseg_jump (void)
29b0f896
AM		 6842{
6843 char *p;
6844 int size;
6845 int prefix;
6846 int code16;
252b5132 6847
29b0f896
AM		 6848 code16 = 0;
6849 if (flag_code == CODE_16BIT)
6850 code16 = CODE16;
a217f122 6851
29b0f896
AM		 6852 prefix = 0;
6853 if (i.prefix[DATA_PREFIX] != 0)
6854 {
6855 prefix = 1;
6856 i.prefixes -= 1;
6857 code16 ^= CODE16;
6858 }
6859 if (i.prefix[REX_PREFIX] != 0)
6860 {
6861 prefix++;
6862 i.prefixes -= 1;
6863 }
252b5132 6864
29b0f896
AM		 6865 size = 4;
6866 if (code16)
6867 size = 2;
252b5132 6868
29b0f896
AM		 6869 if (i.prefixes != 0 && !intel_syntax)
6870 as_warn (_("skipping prefixes on this instruction"));
252b5132 6871
29b0f896
AM		 6872 /* 1 opcode; 2 segment; offset */
6873 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6874
29b0f896
AM		 6875 if (i.prefix[DATA_PREFIX] != 0)
6876 *p++ = DATA_PREFIX_OPCODE;
252b5132 6877
29b0f896
AM		 6878 if (i.prefix[REX_PREFIX] != 0)
6879 *p++ = i.prefix[REX_PREFIX];
252b5132 6880
29b0f896
AM		 6881 *p++ = i.tm.base_opcode;
6882 if (i.op[1].imms->X_op == O_constant)
6883 {
6884 offsetT n = i.op[1].imms->X_add_number;
252b5132 6885
29b0f896
AM		 6886 if (size == 2
6887 && !fits_in_unsigned_word (n)
6888 && !fits_in_signed_word (n))
6889 {
6890 as_bad (_("16-bit jump out of range"));
6891 return;
6892 }
6893 md_number_to_chars (p, n, size);
6894 }
6895 else
6896 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543 6897 i.op[1].imms, 0, reloc (size, 0, 0, 0, i.reloc[1]));
29b0f896
AM		 6898 if (i.op[0].imms->X_op != O_constant)
6899 as_bad (_("can't handle non absolute segment in `%s'"),
6900 i.tm.name);
6901 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6902}
a217f122 6903
29b0f896 6904static void
e3bb37b5 6905output_insn (void)
29b0f896 6906{
2bbd9c25
JJ		 6907 fragS *insn_start_frag;
6908 offsetT insn_start_off;
6909
29b0f896
AM		 6910 /* Tie dwarf2 debug info to the address at the start of the insn.
6911 We can't do this after the insn has been output as the current
6912 frag may have been closed off. eg. by frag_var. */
6913 dwarf2_emit_insn (0);
6914
2bbd9c25
JJ		 6915 insn_start_frag = frag_now;
6916 insn_start_off = frag_now_fix ();
6917
29b0f896 6918 /* Output jumps. */
40fb9820 6919 if (i.tm.opcode_modifier.jump)
29b0f896 6920 output_branch ();
40fb9820
L		 6921 else if (i.tm.opcode_modifier.jumpbyte
6922 || i.tm.opcode_modifier.jumpdword)
29b0f896 6923 output_jump ();
40fb9820 6924 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6925 output_interseg_jump ();
6926 else
6927 {
6928 /* Output normal instructions here. */
6929 char *p;
6930 unsigned char *q;
47465058 6931 unsigned int j;
331d2d0d 6932 unsigned int prefix;
4dffcebc 6933
43234a1e
L		 6934 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6935 don't need the explicit prefix. */
6936 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6937 {
c0f3af97 6938 switch (i.tm.opcode_length)
bc4bd9ab 6939 {
c0f3af97
L		 6940 case 3:
6941 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6942 {
c0f3af97
L		 6943 prefix = (i.tm.base_opcode >> 24) & 0xff;
6944 goto check_prefix;
6945 }
6946 break;
6947 case 2:
6948 if ((i.tm.base_opcode & 0xff0000) != 0)
6949 {
6950 prefix = (i.tm.base_opcode >> 16) & 0xff;
6951 if (i.tm.cpu_flags.bitfield.cpupadlock)
6952 {
4dffcebc 6953check_prefix:
c0f3af97 6954 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6955 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6956 != REPE_PREFIX_OPCODE))
6957 add_prefix (prefix);
6958 }
6959 else
4dffcebc
L		 6960 add_prefix (prefix);
6961 }
c0f3af97
L		 6962 break;
6963 case 1:
6964 break;
6965 default:
6966 abort ();
bc4bd9ab 6967 }
c0f3af97
L		 6968
6969 /* The prefix bytes. */
6970 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6971 if (*q)
6972 FRAG_APPEND_1_CHAR (*q);
0f10071e 6973 }
ae5c1c7b 6974 else
c0f3af97
L		 6975 {
6976 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6977 if (*q)
6978 switch (j)
6979 {
6980 case REX_PREFIX:
6981 /* REX byte is encoded in VEX prefix. */
6982 break;
6983 case SEG_PREFIX:
6984 case ADDR_PREFIX:
6985 FRAG_APPEND_1_CHAR (*q);
6986 break;
6987 default:
6988 /* There should be no other prefixes for instructions
6989 with VEX prefix. */
6990 abort ();
6991 }
6992
43234a1e
L		 6993 /* For EVEX instructions i.vrex should become 0 after
6994 build_evex_prefix. For VEX instructions upper 16 registers
6995 aren't available, so VREX should be 0. */
6996 if (i.vrex)
6997 abort ();
c0f3af97
L		 6998 /* Now the VEX prefix. */
6999 p = frag_more (i.vex.length);
7000 for (j = 0; j < i.vex.length; j++)
7001 p[j] = i.vex.bytes[j];
7002 }
252b5132 7003
29b0f896 7004 /* Now the opcode; be careful about word order here! */
4dffcebc 7005 if (i.tm.opcode_length == 1)
29b0f896
AM		 7006 {
7007 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7008 }
7009 else
7010 {
4dffcebc 7011 switch (i.tm.opcode_length)
331d2d0d 7012 {
43234a1e
L		 7013 case 4:
7014 p = frag_more (4);
7015 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7016 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7017 break;
4dffcebc 7018 case 3:
331d2d0d
L		 7019 p = frag_more (3);
7020 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7021 break;
7022 case 2:
7023 p = frag_more (2);
7024 break;
7025 default:
7026 abort ();
7027 break;
331d2d0d 7028 }
0f10071e 7029
29b0f896
AM		 7030 /* Put out high byte first: can't use md_number_to_chars! */
7031 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7032 *p = i.tm.base_opcode & 0xff;
7033 }
3e73aa7c 7034
29b0f896 7035 /* Now the modrm byte and sib byte (if present). */
40fb9820 7036 if (i.tm.opcode_modifier.modrm)
29b0f896 7037 {
4a3523fa
L		 7038 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7039 | i.rm.reg << 3
7040 | i.rm.mode << 6));
29b0f896
AM		 7041 /* If i.rm.regmem == ESP (4)
7042 && i.rm.mode != (Register mode)
7043 && not 16 bit
7044 ==> need second modrm byte. */
7045 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7046 && i.rm.mode != 3
40fb9820 7047 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7048 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7049 | i.sib.index << 3
7050 | i.sib.scale << 6));
29b0f896 7051 }
3e73aa7c 7052
29b0f896 7053 if (i.disp_operands)
2bbd9c25 7054 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7055
29b0f896 7056 if (i.imm_operands)
2bbd9c25 7057 output_imm (insn_start_frag, insn_start_off);
29b0f896 7058 }
252b5132 7059
29b0f896
AM		 7060#ifdef DEBUG386
7061 if (flag_debug)
7062 {
7b81dfbb 7063 pi ("" /*line*/, &i);
29b0f896
AM		 7064 }
7065#endif /* DEBUG386 */
7066}
252b5132 7067
e205caa7
L		 7068/* Return the size of the displacement operand N. */
7069
7070static int
7071disp_size (unsigned int n)
7072{
7073 int size = 4;
43234a1e
L		 7074
7075 /* Vec_Disp8 has to be 8bit. */
7076 if (i.types[n].bitfield.vec_disp8)
7077 size = 1;
7078 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7079 size = 8;
7080 else if (i.types[n].bitfield.disp8)
7081 size = 1;
7082 else if (i.types[n].bitfield.disp16)
7083 size = 2;
e205caa7
L		 7084 return size;
7085}
7086
7087/* Return the size of the immediate operand N. */
7088
7089static int
7090imm_size (unsigned int n)
7091{
7092 int size = 4;
40fb9820
L		 7093 if (i.types[n].bitfield.imm64)
7094 size = 8;
7095 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7096 size = 1;
7097 else if (i.types[n].bitfield.imm16)
7098 size = 2;
e205caa7
L		 7099 return size;
7100}
7101
29b0f896 7102static void
64e74474 7103output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7104{
7105 char *p;
7106 unsigned int n;
252b5132 7107
29b0f896
AM		 7108 for (n = 0; n < i.operands; n++)
7109 {
43234a1e
L		 7110 if (i.types[n].bitfield.vec_disp8
7111 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7112 {
7113 if (i.op[n].disps->X_op == O_constant)
7114 {
e205caa7 7115 int size = disp_size (n);
43234a1e 7116 offsetT val = i.op[n].disps->X_add_number;
252b5132 7117
43234a1e
L		 7118 if (i.types[n].bitfield.vec_disp8)
7119 val >>= i.memshift;
7120 val = offset_in_range (val, size);
29b0f896
AM		 7121 p = frag_more (size);
7122 md_number_to_chars (p, val, size);
7123 }
7124 else
7125 {
f86103b7 7126 enum bfd_reloc_code_real reloc_type;
e205caa7 7127 int size = disp_size (n);
40fb9820 7128 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7129 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7130
e205caa7 7131 /* We can't have 8 bit displacement here. */
9c2799c2 7132 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7133
29b0f896
AM		 7134 /* The PC relative address is computed relative
7135 to the instruction boundary, so in case immediate
7136 fields follows, we need to adjust the value. */
7137 if (pcrel && i.imm_operands)
7138 {
29b0f896 7139 unsigned int n1;
e205caa7 7140 int sz = 0;
252b5132 7141
29b0f896 7142 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7143 if (operand_type_check (i.types[n1], imm))
252b5132 7144 {
e205caa7
L		 7145 /* Only one immediate is allowed for PC
7146 relative address. */
9c2799c2 7147 gas_assert (sz == 0);
e205caa7
L		 7148 sz = imm_size (n1);
7149 i.op[n].disps->X_add_number -= sz;
252b5132 7150 }
29b0f896 7151 /* We should find the immediate. */
9c2799c2 7152 gas_assert (sz != 0);
29b0f896 7153 }
520dc8e8 7154
29b0f896 7155 p = frag_more (size);
c3320543
L		 7156 reloc_type = reloc (size, pcrel, sign,
7157 (i.bnd_prefix != NULL
7158 || add_bnd_prefix),
7159 i.reloc[n]);
d6ab8113 7160 if (GOT_symbol
2bbd9c25 7161 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7162 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7163 || reloc_type == BFD_RELOC_X86_64_32S
7164 || (reloc_type == BFD_RELOC_64
7165 && object_64bit))
d6ab8113
JB		 7166 && (i.op[n].disps->X_op == O_symbol
7167 || (i.op[n].disps->X_op == O_add
7168 && ((symbol_get_value_expression
7169 (i.op[n].disps->X_op_symbol)->X_op)
7170 == O_subtract))))
7171 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7172 {
7173 offsetT add;
7174
7175 if (insn_start_frag == frag_now)
7176 add = (p - frag_now->fr_literal) - insn_start_off;
7177 else
7178 {
7179 fragS *fr;
7180
7181 add = insn_start_frag->fr_fix - insn_start_off;
7182 for (fr = insn_start_frag->fr_next;
7183 fr && fr != frag_now; fr = fr->fr_next)
7184 add += fr->fr_fix;
7185 add += p - frag_now->fr_literal;
7186 }
7187
4fa24527 7188 if (!object_64bit)
7b81dfbb
AJ		 7189 {
7190 reloc_type = BFD_RELOC_386_GOTPC;
7191 i.op[n].imms->X_add_number += add;
7192 }
7193 else if (reloc_type == BFD_RELOC_64)
7194 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7195 else
7b81dfbb
AJ		 7196 /* Don't do the adjustment for x86-64, as there
7197 the pcrel addressing is relative to the _next_
7198 insn, and that is taken care of in other code. */
d6ab8113 7199 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7200 }
062cd5e7 7201 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7202 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7203 }
7204 }
7205 }
7206}
252b5132 7207
29b0f896 7208static void
64e74474 7209output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7210{
7211 char *p;
7212 unsigned int n;
252b5132 7213
29b0f896
AM		 7214 for (n = 0; n < i.operands; n++)
7215 {
43234a1e
L		 7216 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7217 if (i.rounding && (int) n == i.rounding->operand)
7218 continue;
7219
40fb9820 7220 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7221 {
7222 if (i.op[n].imms->X_op == O_constant)
7223 {
e205caa7 7224 int size = imm_size (n);
29b0f896 7225 offsetT val;
b4cac588 7226
29b0f896
AM		 7227 val = offset_in_range (i.op[n].imms->X_add_number,
7228 size);
7229 p = frag_more (size);
7230 md_number_to_chars (p, val, size);
7231 }
7232 else
7233 {
7234 /* Not absolute_section.
7235 Need a 32-bit fixup (don't support 8bit
7236 non-absolute imms). Try to support other
7237 sizes ... */
f86103b7 7238 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7239 int size = imm_size (n);
7240 int sign;
29b0f896 7241
40fb9820 7242 if (i.types[n].bitfield.imm32s
a7d61044 7243 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7244 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7245 sign = 1;
e205caa7
L		 7246 else
7247 sign = 0;
520dc8e8 7248
29b0f896 7249 p = frag_more (size);
c3320543 7250 reloc_type = reloc (size, 0, sign, 0, i.reloc[n]);
f86103b7 7251
2bbd9c25
JJ		 7252 /* This is tough to explain. We end up with this one if we
7253 * have operands that look like
7254 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7255 * obtain the absolute address of the GOT, and it is strongly
7256 * preferable from a performance point of view to avoid using
7257 * a runtime relocation for this. The actual sequence of
7258 * instructions often look something like:
7259 *
7260 * call .L66
7261 * .L66:
7262 * popl %ebx
7263 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7264 *
7265 * The call and pop essentially return the absolute address
7266 * of the label .L66 and store it in %ebx. The linker itself
7267 * will ultimately change the first operand of the addl so
7268 * that %ebx points to the GOT, but to keep things simple, the
7269 * .o file must have this operand set so that it generates not
7270 * the absolute address of .L66, but the absolute address of
7271 * itself. This allows the linker itself simply treat a GOTPC
7272 * relocation as asking for a pcrel offset to the GOT to be
7273 * added in, and the addend of the relocation is stored in the
7274 * operand field for the instruction itself.
7275 *
7276 * Our job here is to fix the operand so that it would add
7277 * the correct offset so that %ebx would point to itself. The
7278 * thing that is tricky is that .-.L66 will point to the
7279 * beginning of the instruction, so we need to further modify
7280 * the operand so that it will point to itself. There are
7281 * other cases where you have something like:
7282 *
7283 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7284 *
7285 * and here no correction would be required. Internally in
7286 * the assembler we treat operands of this form as not being
7287 * pcrel since the '.' is explicitly mentioned, and I wonder
7288 * whether it would simplify matters to do it this way. Who
7289 * knows. In earlier versions of the PIC patches, the
7290 * pcrel_adjust field was used to store the correction, but
7291 * since the expression is not pcrel, I felt it would be
7292 * confusing to do it this way. */
7293
d6ab8113 7294 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7295 || reloc_type == BFD_RELOC_X86_64_32S
7296 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7297 && GOT_symbol
7298 && GOT_symbol == i.op[n].imms->X_add_symbol
7299 && (i.op[n].imms->X_op == O_symbol
7300 || (i.op[n].imms->X_op == O_add
7301 && ((symbol_get_value_expression
7302 (i.op[n].imms->X_op_symbol)->X_op)
7303 == O_subtract))))
7304 {
2bbd9c25
JJ		 7305 offsetT add;
7306
7307 if (insn_start_frag == frag_now)
7308 add = (p - frag_now->fr_literal) - insn_start_off;
7309 else
7310 {
7311 fragS *fr;
7312
7313 add = insn_start_frag->fr_fix - insn_start_off;
7314 for (fr = insn_start_frag->fr_next;
7315 fr && fr != frag_now; fr = fr->fr_next)
7316 add += fr->fr_fix;
7317 add += p - frag_now->fr_literal;
7318 }
7319
4fa24527 7320 if (!object_64bit)
d6ab8113 7321 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7322 else if (size == 4)
d6ab8113 7323 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7324 else if (size == 8)
7325 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7326 i.op[n].imms->X_add_number += add;
29b0f896 7327 }
29b0f896
AM		 7328 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7329 i.op[n].imms, 0, reloc_type);
7330 }
7331 }
7332 }
252b5132
RH		 7333}
7334\f
d182319b
JB		 7335/* x86_cons_fix_new is called via the expression parsing code when a
7336 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7337static int cons_sign = -1;
7338
7339void
e3bb37b5 7340x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7341 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7342{
62ebcb5c 7343 r = reloc (len, 0, cons_sign, 0, r);
d182319b
JB		 7344
7345#ifdef TE_PE
7346 if (exp->X_op == O_secrel)
7347 {
7348 exp->X_op = O_symbol;
7349 r = BFD_RELOC_32_SECREL;
7350 }
7351#endif
7352
7353 fix_new_exp (frag, off, len, exp, 0, r);
7354}
7355
357d1bd8
L		 7356/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7357 purpose of the `.dc.a' internal pseudo-op. */
7358
7359int
7360x86_address_bytes (void)
7361{
7362 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7363 return 4;
7364 return stdoutput->arch_info->bits_per_address / 8;
7365}
7366
d382c579
TG		 7367#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7368 || defined (LEX_AT)
c06ec724 7369# define lex_got(reloc, adjust, types, bnd_prefix) NULL
718ddfc0 7370#else
f3c180ae
AM		 7371/* Parse operands of the form
7372 <symbol>@GOTOFF+<nnn>
7373 and similar .plt or .got references.
7374
7375 If we find one, set up the correct relocation in RELOC and copy the
7376 input string, minus the `@GOTOFF' into a malloc'd buffer for
7377 parsing by the calling routine. Return this buffer, and if ADJUST
7378 is non-null set it to the length of the string we removed from the
7379 input line. Otherwise return NULL. */
7380static char *
91d6fa6a 7381lex_got (enum bfd_reloc_code_real *rel,
64e74474 7382 int *adjust,
c3320543
L		 7383 i386_operand_type *types,
7384 int bnd_prefix)
f3c180ae 7385{
7b81dfbb
AJ		 7386 /* Some of the relocations depend on the size of what field is to
7387 be relocated. But in our callers i386_immediate and i386_displacement
7388 we don't yet know the operand size (this will be set by insn
7389 matching). Hence we record the word32 relocation here,
7390 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7391 static const struct {
7392 const char *str;
cff8d58a 7393 int len;
4fa24527 7394 const enum bfd_reloc_code_real rel[2];
40fb9820 7395 const i386_operand_type types64;
f3c180ae 7396 } gotrel[] = {
8ce3d284 7397#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7398 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7399 BFD_RELOC_SIZE32 },
7400 OPERAND_TYPE_IMM32_64 },
8ce3d284 7401#endif
cff8d58a
L		 7402 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7403 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7404 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7405 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7406 BFD_RELOC_X86_64_PLT32 },
40fb9820 7407 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7408 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7409 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7410 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7411 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7412 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7413 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7414 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7415 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7416 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7417 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7418 BFD_RELOC_X86_64_TLSGD },
40fb9820 7419 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7420 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7421 _dummy_first_bfd_reloc_code_real },
40fb9820 7422 OPERAND_TYPE_NONE },
cff8d58a
L		 7423 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7424 BFD_RELOC_X86_64_TLSLD },
40fb9820 7425 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7426 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7427 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7428 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7429 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7430 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7431 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7432 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7433 _dummy_first_bfd_reloc_code_real },
40fb9820 7434 OPERAND_TYPE_NONE },
cff8d58a
L		 7435 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7436 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7437 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7438 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7439 _dummy_first_bfd_reloc_code_real },
40fb9820 7440 OPERAND_TYPE_NONE },
cff8d58a
L		 7441 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7442 _dummy_first_bfd_reloc_code_real },
40fb9820 7443 OPERAND_TYPE_NONE },
cff8d58a
L		 7444 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7445 BFD_RELOC_X86_64_GOT32 },
40fb9820 7446 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7447 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7448 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7449 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7450 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7451 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7452 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7453 };
7454 char *cp;
7455 unsigned int j;
7456
d382c579 7457#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7458 if (!IS_ELF)
7459 return NULL;
d382c579 7460#endif
718ddfc0 7461
f3c180ae 7462 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7463 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7464 return NULL;
7465
47465058 7466 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7467 {
cff8d58a 7468 int len = gotrel[j].len;
28f81592 7469 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7470 {
4fa24527 7471 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7472 {
28f81592
AM		 7473 int first, second;
7474 char *tmpbuf, *past_reloc;
f3c180ae 7475
91d6fa6a 7476 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7477
3956db08
JB		 7478 if (types)
7479 {
7480 if (flag_code != CODE_64BIT)
40fb9820
L		 7481 {
7482 types->bitfield.imm32 = 1;
7483 types->bitfield.disp32 = 1;
7484 }
3956db08
JB		 7485 else
7486 *types = gotrel[j].types64;
7487 }
7488
8fd4256d 7489 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7490 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7491
28f81592 7492 /* The length of the first part of our input line. */
f3c180ae 7493 first = cp - input_line_pointer;
28f81592
AM		 7494
7495 /* The second part goes from after the reloc token until
67c11a9b 7496 (and including) an end_of_line char or comma. */
28f81592 7497 past_reloc = cp + 1 + len;
67c11a9b
AM		 7498 cp = past_reloc;
7499 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7500 ++cp;
7501 second = cp + 1 - past_reloc;
28f81592
AM		 7502
7503 /* Allocate and copy string. The trailing NUL shouldn't
7504 be necessary, but be safe. */
1e9cc1c2 7505 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7506 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7507 if (second != 0 && *past_reloc != ' ')
7508 /* Replace the relocation token with ' ', so that
7509 errors like foo@GOTOFF1 will be detected. */
7510 tmpbuf[first++] = ' ';
af89796a
L		 7511 else
7512 /* Increment length by 1 if the relocation token is
7513 removed. */
7514 len++;
7515 if (adjust)
7516 *adjust = len;
0787a12d
AM		 7517 memcpy (tmpbuf + first, past_reloc, second);
7518 tmpbuf[first + second] = '\0';
c3320543
L		 7519 if (bnd_prefix && *rel == BFD_RELOC_X86_64_PLT32)
7520 *rel = BFD_RELOC_X86_64_PLT32_BND;
f3c180ae
AM		 7521 return tmpbuf;
7522 }
7523
4fa24527
JB		 7524 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7525 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7526 return NULL;
7527 }
7528 }
7529
7530 /* Might be a symbol version string. Don't as_bad here. */
7531 return NULL;
7532}
4e4f7c87 7533#endif
f3c180ae 7534
a988325c
NC		 7535#ifdef TE_PE
7536#ifdef lex_got
7537#undef lex_got
7538#endif
7539/* Parse operands of the form
7540 <symbol>@SECREL32+<nnn>
7541
7542 If we find one, set up the correct relocation in RELOC and copy the
7543 input string, minus the `@SECREL32' into a malloc'd buffer for
7544 parsing by the calling routine. Return this buffer, and if ADJUST
7545 is non-null set it to the length of the string we removed from the
34bca508
L		 7546 input line. Otherwise return NULL.
7547
a988325c
NC		 7548 This function is copied from the ELF version above adjusted for PE targets. */
7549
7550static char *
7551lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7552 int *adjust ATTRIBUTE_UNUSED,
c06ec724
L		 7553 i386_operand_type *types,
7554 int bnd_prefix ATTRIBUTE_UNUSED)
a988325c
NC		 7555{
7556 static const struct
7557 {
7558 const char *str;
7559 int len;
7560 const enum bfd_reloc_code_real rel[2];
7561 const i386_operand_type types64;
7562 }
7563 gotrel[] =
7564 {
7565 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7566 BFD_RELOC_32_SECREL },
7567 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7568 };
7569
7570 char *cp;
7571 unsigned j;
7572
7573 for (cp = input_line_pointer; *cp != '@'; cp++)
7574 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7575 return NULL;
7576
7577 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7578 {
7579 int len = gotrel[j].len;
7580
7581 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7582 {
7583 if (gotrel[j].rel[object_64bit] != 0)
7584 {
7585 int first, second;
7586 char *tmpbuf, *past_reloc;
7587
7588 *rel = gotrel[j].rel[object_64bit];
7589 if (adjust)
7590 *adjust = len;
7591
7592 if (types)
7593 {
7594 if (flag_code != CODE_64BIT)
7595 {
7596 types->bitfield.imm32 = 1;
7597 types->bitfield.disp32 = 1;
7598 }
7599 else
7600 *types = gotrel[j].types64;
7601 }
7602
7603 /* The length of the first part of our input line. */
7604 first = cp - input_line_pointer;
7605
7606 /* The second part goes from after the reloc token until
7607 (and including) an end_of_line char or comma. */
7608 past_reloc = cp + 1 + len;
7609 cp = past_reloc;
7610 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7611 ++cp;
7612 second = cp + 1 - past_reloc;
7613
7614 /* Allocate and copy string. The trailing NUL shouldn't
7615 be necessary, but be safe. */
7616 tmpbuf = (char *) xmalloc (first + second + 2);
7617 memcpy (tmpbuf, input_line_pointer, first);
7618 if (second != 0 && *past_reloc != ' ')
7619 /* Replace the relocation token with ' ', so that
7620 errors like foo@SECLREL321 will be detected. */
7621 tmpbuf[first++] = ' ';
7622 memcpy (tmpbuf + first, past_reloc, second);
7623 tmpbuf[first + second] = '\0';
7624 return tmpbuf;
7625 }
7626
7627 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7628 gotrel[j].str, 1 << (5 + object_64bit));
7629 return NULL;
7630 }
7631 }
7632
7633 /* Might be a symbol version string. Don't as_bad here. */
7634 return NULL;
7635}
7636
7637#endif /* TE_PE */
7638
62ebcb5c 7639bfd_reloc_code_real_type
e3bb37b5 7640x86_cons (expressionS *exp, int size)
f3c180ae 7641{
62ebcb5c
AM		 7642 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7643
ee86248c
JB		 7644 intel_syntax = -intel_syntax;
7645
3c7b9c2c 7646 exp->X_md = 0;
4fa24527 7647 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7648 {
7649 /* Handle @GOTOFF and the like in an expression. */
7650 char *save;
7651 char *gotfree_input_line;
4a57f2cf 7652 int adjust = 0;
f3c180ae
AM		 7653
7654 save = input_line_pointer;
c3320543 7655 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL, 0);
f3c180ae
AM		 7656 if (gotfree_input_line)
7657 input_line_pointer = gotfree_input_line;
7658
7659 expression (exp);
7660
7661 if (gotfree_input_line)
7662 {
7663 /* expression () has merrily parsed up to the end of line,
7664 or a comma - in the wrong buffer. Transfer how far
7665 input_line_pointer has moved to the right buffer. */
7666 input_line_pointer = (save
7667 + (input_line_pointer - gotfree_input_line)
7668 + adjust);
7669 free (gotfree_input_line);
3992d3b7
AM		 7670 if (exp->X_op == O_constant
7671 || exp->X_op == O_absent
7672 || exp->X_op == O_illegal
0398aac5 7673 || exp->X_op == O_register
3992d3b7
AM		 7674 || exp->X_op == O_big)
7675 {
7676 char c = *input_line_pointer;
7677 *input_line_pointer = 0;
7678 as_bad (_("missing or invalid expression `%s'"), save);
7679 *input_line_pointer = c;
7680 }
f3c180ae
AM		 7681 }
7682 }
7683 else
7684 expression (exp);
ee86248c
JB		 7685
7686 intel_syntax = -intel_syntax;
7687
7688 if (intel_syntax)
7689 i386_intel_simplify (exp);
62ebcb5c
AM		 7690
7691 return got_reloc;
f3c180ae 7692}
f3c180ae 7693
9f32dd5b
L		 7694static void
7695signed_cons (int size)
6482c264 7696{
d182319b
JB		 7697 if (flag_code == CODE_64BIT)
7698 cons_sign = 1;
7699 cons (size);
7700 cons_sign = -1;
6482c264
NC		 7701}
7702
d182319b 7703#ifdef TE_PE
6482c264 7704static void
7016a5d5 7705pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7706{
7707 expressionS exp;
7708
7709 do
7710 {
7711 expression (&exp);
7712 if (exp.X_op == O_symbol)
7713 exp.X_op = O_secrel;
7714
7715 emit_expr (&exp, 4);
7716 }
7717 while (*input_line_pointer++ == ',');
7718
7719 input_line_pointer--;
7720 demand_empty_rest_of_line ();
7721}
6482c264
NC		 7722#endif
7723
43234a1e
L		 7724/* Handle Vector operations. */
7725
7726static char *
7727check_VecOperations (char *op_string, char *op_end)
7728{
7729 const reg_entry *mask;
7730 const char *saved;
7731 char *end_op;
7732
7733 while (*op_string
7734 && (op_end == NULL || op_string < op_end))
7735 {
7736 saved = op_string;
7737 if (*op_string == '{')
7738 {
7739 op_string++;
7740
7741 /* Check broadcasts. */
7742 if (strncmp (op_string, "1to", 3) == 0)
7743 {
7744 int bcst_type;
7745
7746 if (i.broadcast)
7747 goto duplicated_vec_op;
7748
7749 op_string += 3;
7750 if (*op_string == '8')
7751 bcst_type = BROADCAST_1TO8;
7752 else if (*op_string == '1'
7753 && *(op_string+1) == '6')
7754 {
7755 bcst_type = BROADCAST_1TO16;
7756 op_string++;
7757 }
7758 else
7759 {
7760 as_bad (_("Unsupported broadcast: `%s'"), saved);
7761 return NULL;
7762 }
7763 op_string++;
7764
7765 broadcast_op.type = bcst_type;
7766 broadcast_op.operand = this_operand;
7767 i.broadcast = &broadcast_op;
7768 }
7769 /* Check masking operation. */
7770 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7771 {
7772 /* k0 can't be used for write mask. */
7773 if (mask->reg_num == 0)
7774 {
7775 as_bad (_("`%s' can't be used for write mask"),
7776 op_string);
7777 return NULL;
7778 }
7779
7780 if (!i.mask)
7781 {
7782 mask_op.mask = mask;
7783 mask_op.zeroing = 0;
7784 mask_op.operand = this_operand;
7785 i.mask = &mask_op;
7786 }
7787 else
7788 {
7789 if (i.mask->mask)
7790 goto duplicated_vec_op;
7791
7792 i.mask->mask = mask;
7793
7794 /* Only "{z}" is allowed here. No need to check
7795 zeroing mask explicitly. */
7796 if (i.mask->operand != this_operand)
7797 {
7798 as_bad (_("invalid write mask `%s'"), saved);
7799 return NULL;
7800 }
7801 }
7802
7803 op_string = end_op;
7804 }
7805 /* Check zeroing-flag for masking operation. */
7806 else if (*op_string == 'z')
7807 {
7808 if (!i.mask)
7809 {
7810 mask_op.mask = NULL;
7811 mask_op.zeroing = 1;
7812 mask_op.operand = this_operand;
7813 i.mask = &mask_op;
7814 }
7815 else
7816 {
7817 if (i.mask->zeroing)
7818 {
7819 duplicated_vec_op:
7820 as_bad (_("duplicated `%s'"), saved);
7821 return NULL;
7822 }
7823
7824 i.mask->zeroing = 1;
7825
7826 /* Only "{%k}" is allowed here. No need to check mask
7827 register explicitly. */
7828 if (i.mask->operand != this_operand)
7829 {
7830 as_bad (_("invalid zeroing-masking `%s'"),
7831 saved);
7832 return NULL;
7833 }
7834 }
7835
7836 op_string++;
7837 }
7838 else
7839 goto unknown_vec_op;
7840
7841 if (*op_string != '}')
7842 {
7843 as_bad (_("missing `}' in `%s'"), saved);
7844 return NULL;
7845 }
7846 op_string++;
7847 continue;
7848 }
7849 unknown_vec_op:
7850 /* We don't know this one. */
7851 as_bad (_("unknown vector operation: `%s'"), saved);
7852 return NULL;
7853 }
7854
7855 return op_string;
7856}
7857
252b5132 7858static int
70e41ade 7859i386_immediate (char *imm_start)
252b5132
RH		 7860{
7861 char *save_input_line_pointer;
f3c180ae 7862 char *gotfree_input_line;
252b5132 7863 segT exp_seg = 0;
47926f60 7864 expressionS *exp;
40fb9820
L		 7865 i386_operand_type types;
7866
0dfbf9d7 7867 operand_type_set (&types, ~0);
252b5132
RH		 7868
7869 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7870 {
31b2323c
L		 7871 as_bad (_("at most %d immediate operands are allowed"),
7872 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7873 return 0;
7874 }
7875
7876 exp = &im_expressions[i.imm_operands++];
520dc8e8 7877 i.op[this_operand].imms = exp;
252b5132
RH		 7878
7879 if (is_space_char (*imm_start))
7880 ++imm_start;
7881
7882 save_input_line_pointer = input_line_pointer;
7883 input_line_pointer = imm_start;
7884
c3320543
L		 7885 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
7886 (i.bnd_prefix != NULL
7887 || add_bnd_prefix));
f3c180ae
AM		 7888 if (gotfree_input_line)
7889 input_line_pointer = gotfree_input_line;
252b5132
RH		 7890
7891 exp_seg = expression (exp);
7892
83183c0c 7893 SKIP_WHITESPACE ();
43234a1e
L		 7894
7895 /* Handle vector operations. */
7896 if (*input_line_pointer == '{')
7897 {
7898 input_line_pointer = check_VecOperations (input_line_pointer,
7899 NULL);
7900 if (input_line_pointer == NULL)
7901 return 0;
7902 }
7903
252b5132 7904 if (*input_line_pointer)
f3c180ae 7905 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7906
7907 input_line_pointer = save_input_line_pointer;
f3c180ae 7908 if (gotfree_input_line)
ee86248c
JB		 7909 {
7910 free (gotfree_input_line);
7911
7912 if (exp->X_op == O_constant || exp->X_op == O_register)
7913 exp->X_op = O_illegal;
7914 }
7915
7916 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7917}
252b5132 7918
ee86248c
JB		 7919static int
7920i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7921 i386_operand_type types, const char *imm_start)
7922{
7923 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7924 {
313c53d1
L		 7925 if (imm_start)
7926 as_bad (_("missing or invalid immediate expression `%s'"),
7927 imm_start);
3992d3b7 7928 return 0;
252b5132 7929 }
3e73aa7c 7930 else if (exp->X_op == O_constant)
252b5132 7931 {
47926f60 7932 /* Size it properly later. */
40fb9820 7933 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7934 /* If not 64bit, sign extend val. */
7935 if (flag_code != CODE_64BIT
4eed87de
AM		 7936 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7937 exp->X_add_number
7938 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7939 }
4c63da97 7940#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7941 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7942 && exp_seg != absolute_section
47926f60 7943 && exp_seg != text_section
24eab124
AM		 7944 && exp_seg != data_section
7945 && exp_seg != bss_section
7946 && exp_seg != undefined_section
f86103b7 7947 && !bfd_is_com_section (exp_seg))
252b5132 7948 {
d0b47220 7949 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7950 return 0;
7951 }
7952#endif
bb8f5920
L		 7953 else if (!intel_syntax && exp->X_op == O_register)
7954 {
313c53d1
L		 7955 if (imm_start)
7956 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7957 return 0;
7958 }
252b5132
RH		 7959 else
7960 {
7961 /* This is an address. The size of the address will be
24eab124 7962 determined later, depending on destination register,
3e73aa7c 7963 suffix, or the default for the section. */
40fb9820
L		 7964 i.types[this_operand].bitfield.imm8 = 1;
7965 i.types[this_operand].bitfield.imm16 = 1;
7966 i.types[this_operand].bitfield.imm32 = 1;
7967 i.types[this_operand].bitfield.imm32s = 1;
7968 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7969 i.types[this_operand] = operand_type_and (i.types[this_operand],
7970 types);
252b5132
RH		 7971 }
7972
7973 return 1;
7974}
7975
551c1ca1 7976static char *
e3bb37b5 7977i386_scale (char *scale)
252b5132 7978{
551c1ca1
AM		 7979 offsetT val;
7980 char *save = input_line_pointer;
252b5132 7981
551c1ca1
AM		 7982 input_line_pointer = scale;
7983 val = get_absolute_expression ();
7984
7985 switch (val)
252b5132 7986 {
551c1ca1 7987 case 1:
252b5132
RH		 7988 i.log2_scale_factor = 0;
7989 break;
551c1ca1 7990 case 2:
252b5132
RH		 7991 i.log2_scale_factor = 1;
7992 break;
551c1ca1 7993 case 4:
252b5132
RH		 7994 i.log2_scale_factor = 2;
7995 break;
551c1ca1 7996 case 8:
252b5132
RH		 7997 i.log2_scale_factor = 3;
7998 break;
7999 default:
a724f0f4
JB		 8000 {
8001 char sep = *input_line_pointer;
8002
8003 *input_line_pointer = '\0';
8004 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8005 scale);
8006 *input_line_pointer = sep;
8007 input_line_pointer = save;
8008 return NULL;
8009 }
252b5132 8010 }
29b0f896 8011 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8012 {
8013 as_warn (_("scale factor of %d without an index register"),
24eab124 8014 1 << i.log2_scale_factor);
252b5132 8015 i.log2_scale_factor = 0;
252b5132 8016 }
551c1ca1
AM		 8017 scale = input_line_pointer;
8018 input_line_pointer = save;
8019 return scale;
252b5132
RH		 8020}
8021
252b5132 8022static int
e3bb37b5 8023i386_displacement (char *disp_start, char *disp_end)
252b5132 8024{
29b0f896 8025 expressionS *exp;
252b5132
RH		 8026 segT exp_seg = 0;
8027 char *save_input_line_pointer;
f3c180ae 8028 char *gotfree_input_line;
40fb9820
L		 8029 int override;
8030 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8031 int ret;
252b5132 8032
31b2323c
L		 8033 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8034 {
8035 as_bad (_("at most %d displacement operands are allowed"),
8036 MAX_MEMORY_OPERANDS);
8037 return 0;
8038 }
8039
0dfbf9d7 8040 operand_type_set (&bigdisp, 0);
40fb9820
L		 8041 if ((i.types[this_operand].bitfield.jumpabsolute)
8042 || (!current_templates->start->opcode_modifier.jump
8043 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8044 {
40fb9820 8045 bigdisp.bitfield.disp32 = 1;
e05278af 8046 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8047 if (flag_code == CODE_64BIT)
8048 {
8049 if (!override)
8050 {
8051 bigdisp.bitfield.disp32s = 1;
8052 bigdisp.bitfield.disp64 = 1;
8053 }
8054 }
8055 else if ((flag_code == CODE_16BIT) ^ override)
8056 {
8057 bigdisp.bitfield.disp32 = 0;
8058 bigdisp.bitfield.disp16 = 1;
8059 }
e05278af
JB		 8060 }
8061 else
8062 {
8063 /* For PC-relative branches, the width of the displacement
8064 is dependent upon data size, not address size. */
e05278af 8065 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8066 if (flag_code == CODE_64BIT)
8067 {
8068 if (override || i.suffix == WORD_MNEM_SUFFIX)
8069 bigdisp.bitfield.disp16 = 1;
8070 else
8071 {
8072 bigdisp.bitfield.disp32 = 1;
8073 bigdisp.bitfield.disp32s = 1;
8074 }
8075 }
8076 else
e05278af
JB		 8077 {
8078 if (!override)
8079 override = (i.suffix == (flag_code != CODE_16BIT
8080 ? WORD_MNEM_SUFFIX
8081 : LONG_MNEM_SUFFIX));
40fb9820
L		 8082 bigdisp.bitfield.disp32 = 1;
8083 if ((flag_code == CODE_16BIT) ^ override)
8084 {
8085 bigdisp.bitfield.disp32 = 0;
8086 bigdisp.bitfield.disp16 = 1;
8087 }
e05278af 8088 }
e05278af 8089 }
c6fb90c8
L		 8090 i.types[this_operand] = operand_type_or (i.types[this_operand],
8091 bigdisp);
252b5132
RH		 8092
8093 exp = &disp_expressions[i.disp_operands];
520dc8e8 8094 i.op[this_operand].disps = exp;
252b5132
RH		 8095 i.disp_operands++;
8096 save_input_line_pointer = input_line_pointer;
8097 input_line_pointer = disp_start;
8098 END_STRING_AND_SAVE (disp_end);
8099
8100#ifndef GCC_ASM_O_HACK
8101#define GCC_ASM_O_HACK 0
8102#endif
8103#if GCC_ASM_O_HACK
8104 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8105 if (i.types[this_operand].bitfield.baseIndex
24eab124 8106 && displacement_string_end[-1] == '+')
252b5132
RH		 8107 {
8108 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8109 constraint within gcc asm statements.
8110 For instance:
8111
8112 #define _set_tssldt_desc(n,addr,limit,type) \
8113 __asm__ __volatile__ ( \
8114 "movw %w2,%0\n\t" \
8115 "movw %w1,2+%0\n\t" \
8116 "rorl $16,%1\n\t" \
8117 "movb %b1,4+%0\n\t" \
8118 "movb %4,5+%0\n\t" \
8119 "movb $0,6+%0\n\t" \
8120 "movb %h1,7+%0\n\t" \
8121 "rorl $16,%1" \
8122 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8123
8124 This works great except that the output assembler ends
8125 up looking a bit weird if it turns out that there is
8126 no offset. You end up producing code that looks like:
8127
8128 #APP
8129 movw $235,(%eax)
8130 movw %dx,2+(%eax)
8131 rorl $16,%edx
8132 movb %dl,4+(%eax)
8133 movb $137,5+(%eax)
8134 movb $0,6+(%eax)
8135 movb %dh,7+(%eax)
8136 rorl $16,%edx
8137 #NO_APP
8138
47926f60 8139 So here we provide the missing zero. */
24eab124
AM		 8140
8141 *displacement_string_end = '0';
252b5132
RH		 8142 }
8143#endif
c3320543
L		 8144 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
8145 (i.bnd_prefix != NULL
8146 || add_bnd_prefix));
f3c180ae
AM		 8147 if (gotfree_input_line)
8148 input_line_pointer = gotfree_input_line;
252b5132 8149
24eab124 8150 exp_seg = expression (exp);
252b5132 8151
636c26b0
AM		 8152 SKIP_WHITESPACE ();
8153 if (*input_line_pointer)
8154 as_bad (_("junk `%s' after expression"), input_line_pointer);
8155#if GCC_ASM_O_HACK
8156 RESTORE_END_STRING (disp_end + 1);
8157#endif
636c26b0 8158 input_line_pointer = save_input_line_pointer;
636c26b0 8159 if (gotfree_input_line)
ee86248c
JB		 8160 {
8161 free (gotfree_input_line);
8162
8163 if (exp->X_op == O_constant || exp->X_op == O_register)
8164 exp->X_op = O_illegal;
8165 }
8166
8167 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8168
8169 RESTORE_END_STRING (disp_end);
8170
8171 return ret;
8172}
8173
8174static int
8175i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8176 i386_operand_type types, const char *disp_start)
8177{
8178 i386_operand_type bigdisp;
8179 int ret = 1;
636c26b0 8180
24eab124
AM		 8181 /* We do this to make sure that the section symbol is in
8182 the symbol table. We will ultimately change the relocation
47926f60 8183 to be relative to the beginning of the section. */
1ae12ab7 8184 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8185 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8186 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8187 {
636c26b0 8188 if (exp->X_op != O_symbol)
3992d3b7 8189 goto inv_disp;
636c26b0 8190
e5cb08ac 8191 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8192 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8193 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8194 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8195 exp->X_op = O_subtract;
8196 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8197 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8198 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8199 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8200 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8201 else
29b0f896 8202 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8203 }
252b5132 8204
3992d3b7
AM		 8205 else if (exp->X_op == O_absent
8206 || exp->X_op == O_illegal
ee86248c 8207 || exp->X_op == O_big)
2daf4fd8 8208 {
3992d3b7
AM		 8209 inv_disp:
8210 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8211 disp_start);
3992d3b7 8212 ret = 0;
2daf4fd8
AM		 8213 }
8214
0e1147d9
L		 8215 else if (flag_code == CODE_64BIT
8216 && !i.prefix[ADDR_PREFIX]
8217 && exp->X_op == O_constant)
8218 {
8219 /* Since displacement is signed extended to 64bit, don't allow
8220 disp32 and turn off disp32s if they are out of range. */
8221 i.types[this_operand].bitfield.disp32 = 0;
8222 if (!fits_in_signed_long (exp->X_add_number))
8223 {
8224 i.types[this_operand].bitfield.disp32s = 0;
8225 if (i.types[this_operand].bitfield.baseindex)
8226 {
8227 as_bad (_("0x%lx out range of signed 32bit displacement"),
8228 (long) exp->X_add_number);
8229 ret = 0;
8230 }
8231 }
8232 }
8233
4c63da97 8234#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8235 else if (exp->X_op != O_constant
8236 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8237 && exp_seg != absolute_section
8238 && exp_seg != text_section
8239 && exp_seg != data_section
8240 && exp_seg != bss_section
8241 && exp_seg != undefined_section
8242 && !bfd_is_com_section (exp_seg))
24eab124 8243 {
d0b47220 8244 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8245 ret = 0;
24eab124 8246 }
252b5132 8247#endif
3956db08 8248
40fb9820
L		 8249 /* Check if this is a displacement only operand. */
8250 bigdisp = i.types[this_operand];
8251 bigdisp.bitfield.disp8 = 0;
8252 bigdisp.bitfield.disp16 = 0;
8253 bigdisp.bitfield.disp32 = 0;
8254 bigdisp.bitfield.disp32s = 0;
8255 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8256 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8257 i.types[this_operand] = operand_type_and (i.types[this_operand],
8258 types);
3956db08 8259
3992d3b7 8260 return ret;
252b5132
RH		 8261}
8262
eecb386c 8263/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8264 Return 1 on success, 0 on a failure. */
8265
252b5132 8266static int
e3bb37b5 8267i386_index_check (const char *operand_string)
252b5132 8268{
fc0763e6 8269 const char *kind = "base/index";
be05d201
L		 8270 enum flag_code addr_mode;
8271
8272 if (i.prefix[ADDR_PREFIX])
8273 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8274 else
8275 {
8276 addr_mode = flag_code;
8277
24eab124 8278#if INFER_ADDR_PREFIX
be05d201
L		 8279 if (i.mem_operands == 0)
8280 {
8281 /* Infer address prefix from the first memory operand. */
8282 const reg_entry *addr_reg = i.base_reg;
8283
8284 if (addr_reg == NULL)
8285 addr_reg = i.index_reg;
eecb386c 8286
be05d201
L		 8287 if (addr_reg)
8288 {
8289 if (addr_reg->reg_num == RegEip
8290 || addr_reg->reg_num == RegEiz
8291 || addr_reg->reg_type.bitfield.reg32)
8292 addr_mode = CODE_32BIT;
8293 else if (flag_code != CODE_64BIT
8294 && addr_reg->reg_type.bitfield.reg16)
8295 addr_mode = CODE_16BIT;
8296
8297 if (addr_mode != flag_code)
8298 {
8299 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8300 i.prefixes += 1;
8301 /* Change the size of any displacement too. At most one
8302 of Disp16 or Disp32 is set.
8303 FIXME. There doesn't seem to be any real need for
8304 separate Disp16 and Disp32 flags. The same goes for
8305 Imm16 and Imm32. Removing them would probably clean
8306 up the code quite a lot. */
8307 if (flag_code != CODE_64BIT
8308 && (i.types[this_operand].bitfield.disp16
8309 || i.types[this_operand].bitfield.disp32))
8310 i.types[this_operand]
8311 = operand_type_xor (i.types[this_operand], disp16_32);
8312 }
8313 }
8314 }
24eab124 8315#endif
be05d201
L		 8316 }
8317
fc0763e6
JB		 8318 if (current_templates->start->opcode_modifier.isstring
8319 && !current_templates->start->opcode_modifier.immext
8320 && (current_templates->end[-1].opcode_modifier.isstring
8321 || i.mem_operands))
8322 {
8323 /* Memory operands of string insns are special in that they only allow
8324 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8325 const reg_entry *expected_reg;
8326 static const char *di_si[][2] =
8327 {
8328 { "esi", "edi" },
8329 { "si", "di" },
8330 { "rsi", "rdi" }
8331 };
8332 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8333
8334 kind = "string address";
8335
8336 if (current_templates->start->opcode_modifier.w)
8337 {
8338 i386_operand_type type = current_templates->end[-1].operand_types[0];
8339
8340 if (!type.bitfield.baseindex
8341 || ((!i.mem_operands != !intel_syntax)
8342 && current_templates->end[-1].operand_types[1]
8343 .bitfield.baseindex))
8344 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8345 expected_reg = hash_find (reg_hash,
8346 di_si[addr_mode][type.bitfield.esseg]);
8347
fc0763e6
JB		 8348 }
8349 else
be05d201 8350 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8351
be05d201
L		 8352 if (i.base_reg != expected_reg
8353 || i.index_reg
fc0763e6 8354 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8355 {
be05d201
L		 8356 /* The second memory operand must have the same size as
8357 the first one. */
8358 if (i.mem_operands
8359 && i.base_reg
8360 && !((addr_mode == CODE_64BIT
8361 && i.base_reg->reg_type.bitfield.reg64)
8362 || (addr_mode == CODE_32BIT
8363 ? i.base_reg->reg_type.bitfield.reg32
8364 : i.base_reg->reg_type.bitfield.reg16)))
8365 goto bad_address;
8366
fc0763e6
JB		 8367 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8368 operand_string,
8369 intel_syntax ? '[' : '(',
8370 register_prefix,
be05d201 8371 expected_reg->reg_name,
fc0763e6 8372 intel_syntax ? ']' : ')');
be05d201 8373 return 1;
fc0763e6 8374 }
be05d201
L		 8375 else
8376 return 1;
8377
8378bad_address:
8379 as_bad (_("`%s' is not a valid %s expression"),
8380 operand_string, kind);
8381 return 0;
3e73aa7c
JH		 8382 }
8383 else
8384 {
be05d201
L		 8385 if (addr_mode != CODE_16BIT)
8386 {
8387 /* 32-bit/64-bit checks. */
8388 if ((i.base_reg
8389 && (addr_mode == CODE_64BIT
8390 ? !i.base_reg->reg_type.bitfield.reg64
8391 : !i.base_reg->reg_type.bitfield.reg32)
8392 && (i.index_reg
8393 || (i.base_reg->reg_num
8394 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8395 || (i.index_reg
8396 && !i.index_reg->reg_type.bitfield.regxmm
8397 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8398 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8399 && ((addr_mode == CODE_64BIT
8400 ? !(i.index_reg->reg_type.bitfield.reg64
8401 || i.index_reg->reg_num == RegRiz)
8402 : !(i.index_reg->reg_type.bitfield.reg32
8403 || i.index_reg->reg_num == RegEiz))
8404 || !i.index_reg->reg_type.bitfield.baseindex)))
8405 goto bad_address;
8406 }
8407 else
3e73aa7c 8408 {
be05d201 8409 /* 16-bit checks. */
3e73aa7c 8410 if ((i.base_reg
40fb9820
L		 8411 && (!i.base_reg->reg_type.bitfield.reg16
8412 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8413 || (i.index_reg
40fb9820
L		 8414 && (!i.index_reg->reg_type.bitfield.reg16
8415 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8416 || !(i.base_reg
8417 && i.base_reg->reg_num < 6
8418 && i.index_reg->reg_num >= 6
8419 && i.log2_scale_factor == 0))))
be05d201 8420 goto bad_address;
3e73aa7c
JH		 8421 }
8422 }
be05d201 8423 return 1;
24eab124 8424}
252b5132 8425
43234a1e
L		 8426/* Handle vector immediates. */
8427
8428static int
8429RC_SAE_immediate (const char *imm_start)
8430{
8431 unsigned int match_found, j;
8432 const char *pstr = imm_start;
8433 expressionS *exp;
8434
8435 if (*pstr != '{')
8436 return 0;
8437
8438 pstr++;
8439 match_found = 0;
8440 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8441 {
8442 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8443 {
8444 if (!i.rounding)
8445 {
8446 rc_op.type = RC_NamesTable[j].type;
8447 rc_op.operand = this_operand;
8448 i.rounding = &rc_op;
8449 }
8450 else
8451 {
8452 as_bad (_("duplicated `%s'"), imm_start);
8453 return 0;
8454 }
8455 pstr += RC_NamesTable[j].len;
8456 match_found = 1;
8457 break;
8458 }
8459 }
8460 if (!match_found)
8461 return 0;
8462
8463 if (*pstr++ != '}')
8464 {
8465 as_bad (_("Missing '}': '%s'"), imm_start);
8466 return 0;
8467 }
8468 /* RC/SAE immediate string should contain nothing more. */;
8469 if (*pstr != 0)
8470 {
8471 as_bad (_("Junk after '}': '%s'"), imm_start);
8472 return 0;
8473 }
8474
8475 exp = &im_expressions[i.imm_operands++];
8476 i.op[this_operand].imms = exp;
8477
8478 exp->X_op = O_constant;
8479 exp->X_add_number = 0;
8480 exp->X_add_symbol = (symbolS *) 0;
8481 exp->X_op_symbol = (symbolS *) 0;
8482
8483 i.types[this_operand].bitfield.imm8 = 1;
8484 return 1;
8485}
8486
fc0763e6 8487/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8488 on error. */
252b5132 8489
252b5132 8490static int
a7619375 8491i386_att_operand (char *operand_string)
252b5132 8492{
af6bdddf
AM		 8493 const reg_entry *r;
8494 char *end_op;
24eab124 8495 char *op_string = operand_string;
252b5132 8496
24eab124 8497 if (is_space_char (*op_string))
252b5132
RH		 8498 ++op_string;
8499
24eab124 8500 /* We check for an absolute prefix (differentiating,
47926f60 8501 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8502 if (*op_string == ABSOLUTE_PREFIX)
8503 {
8504 ++op_string;
8505 if (is_space_char (*op_string))
8506 ++op_string;
40fb9820 8507 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8508 }
252b5132 8509
47926f60 8510 /* Check if operand is a register. */
4d1bb795 8511 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8512 {
40fb9820
L		 8513 i386_operand_type temp;
8514
24eab124
AM		 8515 /* Check for a segment override by searching for ':' after a
8516 segment register. */
8517 op_string = end_op;
8518 if (is_space_char (*op_string))
8519 ++op_string;
40fb9820
L		 8520 if (*op_string == ':'
8521 && (r->reg_type.bitfield.sreg2
8522 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8523 {
8524 switch (r->reg_num)
8525 {
8526 case 0:
8527 i.seg[i.mem_operands] = &es;
8528 break;
8529 case 1:
8530 i.seg[i.mem_operands] = &cs;
8531 break;
8532 case 2:
8533 i.seg[i.mem_operands] = &ss;
8534 break;
8535 case 3:
8536 i.seg[i.mem_operands] = &ds;
8537 break;
8538 case 4:
8539 i.seg[i.mem_operands] = &fs;
8540 break;
8541 case 5:
8542 i.seg[i.mem_operands] = &gs;
8543 break;
8544 }
252b5132 8545
24eab124 8546 /* Skip the ':' and whitespace. */
252b5132
RH		 8547 ++op_string;
8548 if (is_space_char (*op_string))
24eab124 8549 ++op_string;
252b5132 8550
24eab124
AM		 8551 if (!is_digit_char (*op_string)
8552 && !is_identifier_char (*op_string)
8553 && *op_string != '('
8554 && *op_string != ABSOLUTE_PREFIX)
8555 {
8556 as_bad (_("bad memory operand `%s'"), op_string);
8557 return 0;
8558 }
47926f60 8559 /* Handle case of %es:*foo. */
24eab124
AM		 8560 if (*op_string == ABSOLUTE_PREFIX)
8561 {
8562 ++op_string;
8563 if (is_space_char (*op_string))
8564 ++op_string;
40fb9820 8565 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8566 }
8567 goto do_memory_reference;
8568 }
43234a1e
L		 8569
8570 /* Handle vector operations. */
8571 if (*op_string == '{')
8572 {
8573 op_string = check_VecOperations (op_string, NULL);
8574 if (op_string == NULL)
8575 return 0;
8576 }
8577
24eab124
AM		 8578 if (*op_string)
8579 {
d0b47220 8580 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8581 return 0;
8582 }
40fb9820
L		 8583 temp = r->reg_type;
8584 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8585 i.types[this_operand] = operand_type_or (i.types[this_operand],
8586 temp);
7d5e4556 8587 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8588 i.op[this_operand].regs = r;
24eab124
AM		 8589 i.reg_operands++;
8590 }
af6bdddf
AM		 8591 else if (*op_string == REGISTER_PREFIX)
8592 {
8593 as_bad (_("bad register name `%s'"), op_string);
8594 return 0;
8595 }
24eab124 8596 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8597 {
24eab124 8598 ++op_string;
40fb9820 8599 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8600 {
d0b47220 8601 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8602 return 0;
8603 }
8604 if (!i386_immediate (op_string))
8605 return 0;
8606 }
43234a1e
L		 8607 else if (RC_SAE_immediate (operand_string))
8608 {
8609 /* If it is a RC or SAE immediate, do nothing. */
8610 ;
8611 }
24eab124
AM		 8612 else if (is_digit_char (*op_string)
8613 || is_identifier_char (*op_string)
e5cb08ac 8614 || *op_string == '(')
24eab124 8615 {
47926f60 8616 /* This is a memory reference of some sort. */
af6bdddf 8617 char *base_string;
252b5132 8618
47926f60 8619 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8620 char *displacement_string_start;
8621 char *displacement_string_end;
43234a1e 8622 char *vop_start;
252b5132 8623
24eab124 8624 do_memory_reference:
24eab124 8625 if ((i.mem_operands == 1
40fb9820 8626 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8627 || i.mem_operands == 2)
8628 {
8629 as_bad (_("too many memory references for `%s'"),
8630 current_templates->start->name);
8631 return 0;
8632 }
252b5132 8633
24eab124
AM		 8634 /* Check for base index form. We detect the base index form by
8635 looking for an ')' at the end of the operand, searching
8636 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8637 after the '('. */
af6bdddf 8638 base_string = op_string + strlen (op_string);
c3332e24 8639
43234a1e
L		 8640 /* Handle vector operations. */
8641 vop_start = strchr (op_string, '{');
8642 if (vop_start && vop_start < base_string)
8643 {
8644 if (check_VecOperations (vop_start, base_string) == NULL)
8645 return 0;
8646 base_string = vop_start;
8647 }
8648
af6bdddf
AM		 8649 --base_string;
8650 if (is_space_char (*base_string))
8651 --base_string;
252b5132 8652
47926f60 8653 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8654 displacement_string_start = op_string;
8655 displacement_string_end = base_string + 1;
252b5132 8656
24eab124
AM		 8657 if (*base_string == ')')
8658 {
af6bdddf 8659 char *temp_string;
24eab124
AM		 8660 unsigned int parens_balanced = 1;
8661 /* We've already checked that the number of left & right ()'s are
47926f60 8662 equal, so this loop will not be infinite. */
24eab124
AM		 8663 do
8664 {
8665 base_string--;
8666 if (*base_string == ')')
8667 parens_balanced++;
8668 if (*base_string == '(')
8669 parens_balanced--;
8670 }
8671 while (parens_balanced);
c3332e24 8672
af6bdddf 8673 temp_string = base_string;
c3332e24 8674
24eab124 8675 /* Skip past '(' and whitespace. */
252b5132
RH		 8676 ++base_string;
8677 if (is_space_char (*base_string))
24eab124 8678 ++base_string;
252b5132 8679
af6bdddf 8680 if (*base_string == ','
4eed87de
AM		 8681 || ((i.base_reg = parse_register (base_string, &end_op))
8682 != NULL))
252b5132 8683 {
af6bdddf 8684 displacement_string_end = temp_string;
252b5132 8685
40fb9820 8686 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8687
af6bdddf 8688 if (i.base_reg)
24eab124 8689 {
24eab124
AM		 8690 base_string = end_op;
8691 if (is_space_char (*base_string))
8692 ++base_string;
af6bdddf
AM		 8693 }
8694
8695 /* There may be an index reg or scale factor here. */
8696 if (*base_string == ',')
8697 {
8698 ++base_string;
8699 if (is_space_char (*base_string))
8700 ++base_string;
8701
4eed87de
AM		 8702 if ((i.index_reg = parse_register (base_string, &end_op))
8703 != NULL)
24eab124 8704 {
af6bdddf 8705 base_string = end_op;
24eab124
AM		 8706 if (is_space_char (*base_string))
8707 ++base_string;
af6bdddf
AM		 8708 if (*base_string == ',')
8709 {
8710 ++base_string;
8711 if (is_space_char (*base_string))
8712 ++base_string;
8713 }
e5cb08ac 8714 else if (*base_string != ')')
af6bdddf 8715 {
4eed87de
AM		 8716 as_bad (_("expecting `,' or `)' "
8717 "after index register in `%s'"),
af6bdddf
AM		 8718 operand_string);
8719 return 0;
8720 }
24eab124 8721 }
af6bdddf 8722 else if (*base_string == REGISTER_PREFIX)
24eab124 8723 {
f76bf5e0
L		 8724 end_op = strchr (base_string, ',');
8725 if (end_op)
8726 *end_op = '\0';
af6bdddf 8727 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8728 return 0;
8729 }
252b5132 8730
47926f60 8731 /* Check for scale factor. */
551c1ca1 8732 if (*base_string != ')')
af6bdddf 8733 {
551c1ca1
AM		 8734 char *end_scale = i386_scale (base_string);
8735
8736 if (!end_scale)
af6bdddf 8737 return 0;
24eab124 8738
551c1ca1 8739 base_string = end_scale;
af6bdddf
AM		 8740 if (is_space_char (*base_string))
8741 ++base_string;
8742 if (*base_string != ')')
8743 {
4eed87de
AM		 8744 as_bad (_("expecting `)' "
8745 "after scale factor in `%s'"),
af6bdddf
AM		 8746 operand_string);
8747 return 0;
8748 }
8749 }
8750 else if (!i.index_reg)
24eab124 8751 {
4eed87de
AM		 8752 as_bad (_("expecting index register or scale factor "
8753 "after `,'; got '%c'"),
af6bdddf 8754 *base_string);
24eab124
AM		 8755 return 0;
8756 }
8757 }
af6bdddf 8758 else if (*base_string != ')')
24eab124 8759 {
4eed87de
AM		 8760 as_bad (_("expecting `,' or `)' "
8761 "after base register in `%s'"),
af6bdddf 8762 operand_string);
24eab124
AM		 8763 return 0;
8764 }
c3332e24 8765 }
af6bdddf 8766 else if (*base_string == REGISTER_PREFIX)
c3332e24 8767 {
f76bf5e0
L		 8768 end_op = strchr (base_string, ',');
8769 if (end_op)
8770 *end_op = '\0';
af6bdddf 8771 as_bad (_("bad register name `%s'"), base_string);
24eab124 8772 return 0;
c3332e24 8773 }
24eab124
AM		 8774 }
8775
8776 /* If there's an expression beginning the operand, parse it,
8777 assuming displacement_string_start and
8778 displacement_string_end are meaningful. */
8779 if (displacement_string_start != displacement_string_end)
8780 {
8781 if (!i386_displacement (displacement_string_start,
8782 displacement_string_end))
8783 return 0;
8784 }
8785
8786 /* Special case for (%dx) while doing input/output op. */
8787 if (i.base_reg
0dfbf9d7
L		 8788 && operand_type_equal (&i.base_reg->reg_type,
8789 &reg16_inoutportreg)
24eab124
AM		 8790 && i.index_reg == 0
8791 && i.log2_scale_factor == 0
8792 && i.seg[i.mem_operands] == 0
40fb9820 8793 && !operand_type_check (i.types[this_operand], disp))
24eab124 8794 {
65da13b5 8795 i.types[this_operand] = inoutportreg;
24eab124
AM		 8796 return 1;
8797 }
8798
eecb386c
AM		 8799 if (i386_index_check (operand_string) == 0)
8800 return 0;
5c07affc 8801 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8802 i.mem_operands++;
8803 }
8804 else
ce8a8b2f
AM		 8805 {
8806 /* It's not a memory operand; argh! */
24eab124
AM		 8807 as_bad (_("invalid char %s beginning operand %d `%s'"),
8808 output_invalid (*op_string),
8809 this_operand + 1,
8810 op_string);
8811 return 0;
8812 }
47926f60 8813 return 1; /* Normal return. */
252b5132
RH		 8814}
8815\f
fa94de6b
RM		 8816/* Calculate the maximum variable size (i.e., excluding fr_fix)
8817 that an rs_machine_dependent frag may reach. */
8818
8819unsigned int
8820i386_frag_max_var (fragS *frag)
8821{
8822 /* The only relaxable frags are for jumps.
8823 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8824 gas_assert (frag->fr_type == rs_machine_dependent);
8825 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8826}
8827
ee7fcc42
AM		 8828/* md_estimate_size_before_relax()
8829
8830 Called just before relax() for rs_machine_dependent frags. The x86
8831 assembler uses these frags to handle variable size jump
8832 instructions.
8833
8834 Any symbol that is now undefined will not become defined.
8835 Return the correct fr_subtype in the frag.
8836 Return the initial "guess for variable size of frag" to caller.
8837 The guess is actually the growth beyond the fixed part. Whatever
8838 we do to grow the fixed or variable part contributes to our
8839 returned value. */
8840
252b5132 8841int
7016a5d5 8842md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8843{
252b5132 8844 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8845 check for un-relaxable symbols. On an ELF system, we can't relax
8846 an externally visible symbol, because it may be overridden by a
8847 shared library. */
8848 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8849#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8850 || (IS_ELF
31312f95 8851 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 8852 || S_IS_WEAK (fragP->fr_symbol)
8853 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8854 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 8855#endif
8856#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8857 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8858 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8859#endif
8860 )
252b5132 8861 {
b98ef147
AM		 8862 /* Symbol is undefined in this segment, or we need to keep a
8863 reloc so that weak symbols can be overridden. */
8864 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8865 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8866 unsigned char *opcode;
8867 int old_fr_fix;
f6af82bd 8868
ee7fcc42 8869 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8870 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8871 else if (size == 2)
f6af82bd
AM		 8872 reloc_type = BFD_RELOC_16_PCREL;
8873 else
8874 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8875
ee7fcc42
AM		 8876 old_fr_fix = fragP->fr_fix;
8877 opcode = (unsigned char *) fragP->fr_opcode;
8878
fddf5b5b 8879 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8880 {
fddf5b5b
AM		 8881 case UNCOND_JUMP:
8882 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8883 opcode[0] = 0xe9;
252b5132 8884 fragP->fr_fix += size;
062cd5e7
AS		 8885 fix_new (fragP, old_fr_fix, size,
8886 fragP->fr_symbol,
8887 fragP->fr_offset, 1,
8888 reloc_type);
252b5132
RH		 8889 break;
8890
fddf5b5b 8891 case COND_JUMP86:
412167cb
AM		 8892 if (size == 2
8893 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8894 {
8895 /* Negate the condition, and branch past an
8896 unconditional jump. */
8897 opcode[0] ^= 1;
8898 opcode[1] = 3;
8899 /* Insert an unconditional jump. */
8900 opcode[2] = 0xe9;
8901 /* We added two extra opcode bytes, and have a two byte
8902 offset. */
8903 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8904 fix_new (fragP, old_fr_fix + 2, 2,
8905 fragP->fr_symbol,
8906 fragP->fr_offset, 1,
8907 reloc_type);
fddf5b5b
AM		 8908 break;
8909 }
8910 /* Fall through. */
8911
8912 case COND_JUMP:
412167cb
AM		 8913 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8914 {
3e02c1cc
AM		 8915 fixS *fixP;
8916
412167cb 8917 fragP->fr_fix += 1;
3e02c1cc
AM		 8918 fixP = fix_new (fragP, old_fr_fix, 1,
8919 fragP->fr_symbol,
8920 fragP->fr_offset, 1,
8921 BFD_RELOC_8_PCREL);
8922 fixP->fx_signed = 1;
412167cb
AM		 8923 break;
8924 }
93c2a809 8925
24eab124 8926 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8927 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8928 opcode[1] = opcode[0] + 0x10;
f6af82bd 8929 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8930 /* We've added an opcode byte. */
8931 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8932 fix_new (fragP, old_fr_fix + 1, size,
8933 fragP->fr_symbol,
8934 fragP->fr_offset, 1,
8935 reloc_type);
252b5132 8936 break;
fddf5b5b
AM		 8937
8938 default:
8939 BAD_CASE (fragP->fr_subtype);
8940 break;
252b5132
RH		 8941 }
8942 frag_wane (fragP);
ee7fcc42 8943 return fragP->fr_fix - old_fr_fix;
252b5132 8944 }
93c2a809 8945
93c2a809
AM		 8946 /* Guess size depending on current relax state. Initially the relax
8947 state will correspond to a short jump and we return 1, because
8948 the variable part of the frag (the branch offset) is one byte
8949 long. However, we can relax a section more than once and in that
8950 case we must either set fr_subtype back to the unrelaxed state,
8951 or return the value for the appropriate branch. */
8952 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8953}
8954
47926f60
KH		 8955/* Called after relax() is finished.
8956
8957 In: Address of frag.
8958 fr_type == rs_machine_dependent.
8959 fr_subtype is what the address relaxed to.
8960
8961 Out: Any fixSs and constants are set up.
8962 Caller will turn frag into a ".space 0". */
8963
252b5132 8964void
7016a5d5
TG		 8965md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8966 fragS *fragP)
252b5132 8967{
29b0f896 8968 unsigned char *opcode;
252b5132 8969 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 8970 offsetT target_address;
8971 offsetT opcode_address;
252b5132 8972 unsigned int extension = 0;
847f7ad4 8973 offsetT displacement_from_opcode_start;
252b5132
RH		 8974
8975 opcode = (unsigned char *) fragP->fr_opcode;
8976
47926f60 8977 /* Address we want to reach in file space. */
252b5132 8978 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 8979
47926f60 8980 /* Address opcode resides at in file space. */
252b5132
RH		 8981 opcode_address = fragP->fr_address + fragP->fr_fix;
8982
47926f60 8983 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 8984 displacement_from_opcode_start = target_address - opcode_address;
8985
fddf5b5b 8986 if ((fragP->fr_subtype & BIG) == 0)
252b5132 8987 {
47926f60
KH		 8988 /* Don't have to change opcode. */
8989 extension = 1; /* 1 opcode + 1 displacement */
252b5132 8990 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 8991 }
8992 else
8993 {
8994 if (no_cond_jump_promotion
8995 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 8996 as_warn_where (fragP->fr_file, fragP->fr_line,
8997 _("long jump required"));
252b5132 8998
fddf5b5b
AM		 8999 switch (fragP->fr_subtype)
9000 {
9001 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9002 extension = 4; /* 1 opcode + 4 displacement */
9003 opcode[0] = 0xe9;
9004 where_to_put_displacement = &opcode[1];
9005 break;
252b5132 9006
fddf5b5b
AM		 9007 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9008 extension = 2; /* 1 opcode + 2 displacement */
9009 opcode[0] = 0xe9;
9010 where_to_put_displacement = &opcode[1];
9011 break;
252b5132 9012
fddf5b5b
AM		 9013 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9014 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9015 extension = 5; /* 2 opcode + 4 displacement */
9016 opcode[1] = opcode[0] + 0x10;
9017 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9018 where_to_put_displacement = &opcode[2];
9019 break;
252b5132 9020
fddf5b5b
AM		 9021 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9022 extension = 3; /* 2 opcode + 2 displacement */
9023 opcode[1] = opcode[0] + 0x10;
9024 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9025 where_to_put_displacement = &opcode[2];
9026 break;
252b5132 9027
fddf5b5b
AM		 9028 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9029 extension = 4;
9030 opcode[0] ^= 1;
9031 opcode[1] = 3;
9032 opcode[2] = 0xe9;
9033 where_to_put_displacement = &opcode[3];
9034 break;
9035
9036 default:
9037 BAD_CASE (fragP->fr_subtype);
9038 break;
9039 }
252b5132 9040 }
fddf5b5b 9041
7b81dfbb
AJ		 9042 /* If size if less then four we are sure that the operand fits,
9043 but if it's 4, then it could be that the displacement is larger
9044 then -/+ 2GB. */
9045 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9046 && object_64bit
9047 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9048 + ((addressT) 1 << 31))
9049 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9050 {
9051 as_bad_where (fragP->fr_file, fragP->fr_line,
9052 _("jump target out of range"));
9053 /* Make us emit 0. */
9054 displacement_from_opcode_start = extension;
9055 }
47926f60 9056 /* Now put displacement after opcode. */
252b5132
RH		 9057 md_number_to_chars ((char *) where_to_put_displacement,
9058 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9059 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9060 fragP->fr_fix += extension;
9061}
9062\f
7016a5d5 9063/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9064 by our caller that we have all the info we need to fix it up.
9065
7016a5d5
TG		 9066 Parameter valP is the pointer to the value of the bits.
9067
252b5132
RH		 9068 On the 386, immediates, displacements, and data pointers are all in
9069 the same (little-endian) format, so we don't need to care about which
9070 we are handling. */
9071
94f592af 9072void
7016a5d5 9073md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9074{
94f592af 9075 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9076 valueT value = *valP;
252b5132 9077
f86103b7 9078#if !defined (TE_Mach)
93382f6d
AM		 9079 if (fixP->fx_pcrel)
9080 {
9081 switch (fixP->fx_r_type)
9082 {
5865bb77
ILT		 9083 default:
9084 break;
9085
d6ab8113
JB		 9086 case BFD_RELOC_64:
9087 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9088 break;
93382f6d 9089 case BFD_RELOC_32:
ae8887b5 9090 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9091 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9092 break;
9093 case BFD_RELOC_16:
9094 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9095 break;
9096 case BFD_RELOC_8:
9097 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9098 break;
9099 }
9100 }
252b5132 9101
a161fe53 9102 if (fixP->fx_addsy != NULL
31312f95 9103 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9104 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9105 || fixP->fx_r_type == BFD_RELOC_16_PCREL
c3320543
L		 9106 || fixP->fx_r_type == BFD_RELOC_8_PCREL
9107 || fixP->fx_r_type == BFD_RELOC_X86_64_PC32_BND)
31312f95 9108 && !use_rela_relocations)
252b5132 9109 {
31312f95
AM		 9110 /* This is a hack. There should be a better way to handle this.
9111 This covers for the fact that bfd_install_relocation will
9112 subtract the current location (for partial_inplace, PC relative
9113 relocations); see more below. */
252b5132 9114#ifndef OBJ_AOUT
718ddfc0 9115 if (IS_ELF
252b5132
RH		 9116#ifdef TE_PE
9117 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9118#endif
9119 )
9120 value += fixP->fx_where + fixP->fx_frag->fr_address;
9121#endif
9122#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9123 if (IS_ELF)
252b5132 9124 {
6539b54b 9125 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9126
6539b54b 9127 if ((sym_seg == seg
2f66722d 9128 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9129 && sym_seg != absolute_section))
af65af87 9130 && !generic_force_reloc (fixP))
2f66722d
AM		 9131 {
9132 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9133 bfd_install_relocation subtracts them out again. I think
9134 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9135 it. FIXME. */
9136 value += fixP->fx_where + fixP->fx_frag->fr_address;
9137 }
252b5132
RH		 9138 }
9139#endif
9140#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9141 /* For some reason, the PE format does not store a
9142 section address offset for a PC relative symbol. */
9143 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9144 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9145 value += md_pcrel_from (fixP);
9146#endif
9147 }
fbeb56a4 9148#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9149 if (fixP->fx_addsy != NULL
9150 && S_IS_WEAK (fixP->fx_addsy)
9151 /* PR 16858: Do not modify weak function references. */
9152 && ! fixP->fx_pcrel)
fbeb56a4
DK		 9153 {
9154 value -= S_GET_VALUE (fixP->fx_addsy);
9155 }
9156#endif
252b5132
RH		 9157
9158 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9159 and we must not disappoint it. */
252b5132 9160#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9161 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9162 switch (fixP->fx_r_type)
9163 {
9164 case BFD_RELOC_386_PLT32:
3e73aa7c 9165 case BFD_RELOC_X86_64_PLT32:
c3320543 9166 case BFD_RELOC_X86_64_PLT32_BND:
47926f60
KH		 9167 /* Make the jump instruction point to the address of the operand. At
9168 runtime we merely add the offset to the actual PLT entry. */
9169 value = -4;
9170 break;
31312f95 9171
13ae64f3
JJ		 9172 case BFD_RELOC_386_TLS_GD:
9173 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9174 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9175 case BFD_RELOC_386_TLS_IE:
9176 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9177 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9178 case BFD_RELOC_X86_64_TLSGD:
9179 case BFD_RELOC_X86_64_TLSLD:
9180 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9181 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9182 value = 0; /* Fully resolved at runtime. No addend. */
9183 /* Fallthrough */
9184 case BFD_RELOC_386_TLS_LE:
9185 case BFD_RELOC_386_TLS_LDO_32:
9186 case BFD_RELOC_386_TLS_LE_32:
9187 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9188 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9189 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9190 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9191 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9192 break;
9193
67a4f2b7
AO		 9194 case BFD_RELOC_386_TLS_DESC_CALL:
9195 case BFD_RELOC_X86_64_TLSDESC_CALL:
9196 value = 0; /* Fully resolved at runtime. No addend. */
9197 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9198 fixP->fx_done = 0;
9199 return;
9200
00f7efb6
JJ		 9201 case BFD_RELOC_386_GOT32:
9202 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9203 value = 0; /* Fully resolved at runtime. No addend. */
9204 break;
47926f60
KH		 9205
9206 case BFD_RELOC_VTABLE_INHERIT:
9207 case BFD_RELOC_VTABLE_ENTRY:
9208 fixP->fx_done = 0;
94f592af 9209 return;
47926f60
KH		 9210
9211 default:
9212 break;
9213 }
9214#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9215 *valP = value;
f86103b7 9216#endif /* !defined (TE_Mach) */
3e73aa7c 9217
3e73aa7c 9218 /* Are we finished with this relocation now? */
c6682705 9219 if (fixP->fx_addsy == NULL)
3e73aa7c 9220 fixP->fx_done = 1;
fbeb56a4
DK		 9221#if defined (OBJ_COFF) && defined (TE_PE)
9222 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9223 {
9224 fixP->fx_done = 0;
9225 /* Remember value for tc_gen_reloc. */
9226 fixP->fx_addnumber = value;
9227 /* Clear out the frag for now. */
9228 value = 0;
9229 }
9230#endif
3e73aa7c
JH		 9231 else if (use_rela_relocations)
9232 {
9233 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9234 /* Remember value for tc_gen_reloc. */
9235 fixP->fx_addnumber = value;
3e73aa7c
JH		 9236 value = 0;
9237 }
f86103b7 9238
94f592af 9239 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9240}
252b5132 9241\f
252b5132 9242char *
499ac353 9243md_atof (int type, char *litP, int *sizeP)
252b5132 9244{
499ac353
NC		 9245 /* This outputs the LITTLENUMs in REVERSE order;
9246 in accord with the bigendian 386. */
9247 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9248}
9249\f
2d545b82 9250static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9251
252b5132 9252static char *
e3bb37b5 9253output_invalid (int c)
252b5132 9254{
3882b010 9255 if (ISPRINT (c))
f9f21a03
L		 9256 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9257 "'%c'", c);
252b5132 9258 else
f9f21a03 9259 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9260 "(0x%x)", (unsigned char) c);
252b5132
RH		 9261 return output_invalid_buf;
9262}
9263
af6bdddf 9264/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9265
9266static const reg_entry *
4d1bb795 9267parse_real_register (char *reg_string, char **end_op)
252b5132 9268{
af6bdddf
AM		 9269 char *s = reg_string;
9270 char *p;
252b5132
RH		 9271 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9272 const reg_entry *r;
9273
9274 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9275 if (*s == REGISTER_PREFIX)
9276 ++s;
9277
9278 if (is_space_char (*s))
9279 ++s;
9280
9281 p = reg_name_given;
af6bdddf 9282 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9283 {
9284 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9285 return (const reg_entry *) NULL;
9286 s++;
252b5132
RH		 9287 }
9288
6588847e
DN		 9289 /* For naked regs, make sure that we are not dealing with an identifier.
9290 This prevents confusing an identifier like `eax_var' with register
9291 `eax'. */
9292 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9293 return (const reg_entry *) NULL;
9294
af6bdddf 9295 *end_op = s;
252b5132
RH		 9296
9297 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9298
5f47d35b 9299 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9300 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9301 {
5f47d35b
AM		 9302 if (is_space_char (*s))
9303 ++s;
9304 if (*s == '(')
9305 {
af6bdddf 9306 ++s;
5f47d35b
AM		 9307 if (is_space_char (*s))
9308 ++s;
9309 if (*s >= '0' && *s <= '7')
9310 {
db557034 9311 int fpr = *s - '0';
af6bdddf 9312 ++s;
5f47d35b
AM		 9313 if (is_space_char (*s))
9314 ++s;
9315 if (*s == ')')
9316 {
9317 *end_op = s + 1;
1e9cc1c2 9318 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9319 know (r);
9320 return r + fpr;
5f47d35b 9321 }
5f47d35b 9322 }
47926f60 9323 /* We have "%st(" then garbage. */
5f47d35b
AM		 9324 return (const reg_entry *) NULL;
9325 }
9326 }
9327
a60de03c
JB		 9328 if (r == NULL || allow_pseudo_reg)
9329 return r;
9330
0dfbf9d7 9331 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9332 return (const reg_entry *) NULL;
9333
192dc9c6
JB		 9334 if ((r->reg_type.bitfield.reg32
9335 || r->reg_type.bitfield.sreg3
9336 || r->reg_type.bitfield.control
9337 || r->reg_type.bitfield.debug
9338 || r->reg_type.bitfield.test)
9339 && !cpu_arch_flags.bitfield.cpui386)
9340 return (const reg_entry *) NULL;
9341
309d3373
JB		 9342 if (r->reg_type.bitfield.floatreg
9343 && !cpu_arch_flags.bitfield.cpu8087
9344 && !cpu_arch_flags.bitfield.cpu287
9345 && !cpu_arch_flags.bitfield.cpu387)
9346 return (const reg_entry *) NULL;
9347
192dc9c6
JB		 9348 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9349 return (const reg_entry *) NULL;
9350
9351 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9352 return (const reg_entry *) NULL;
9353
40f12533
L		 9354 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9355 return (const reg_entry *) NULL;
9356
43234a1e
L		 9357 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9358 && !cpu_arch_flags.bitfield.cpuavx512f)
9359 return (const reg_entry *) NULL;
9360
db51cc60 9361 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9362 if (!allow_index_reg
db51cc60
L		 9363 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9364 return (const reg_entry *) NULL;
9365
43234a1e
L		 9366 /* Upper 16 vector register is only available with VREX in 64bit
9367 mode. */
9368 if ((r->reg_flags & RegVRex))
9369 {
9370 if (!cpu_arch_flags.bitfield.cpuvrex
9371 || flag_code != CODE_64BIT)
9372 return (const reg_entry *) NULL;
9373
9374 i.need_vrex = 1;
9375 }
9376
a60de03c
JB		 9377 if (((r->reg_flags & (RegRex64 | RegRex))
9378 || r->reg_type.bitfield.reg64)
40fb9820 9379 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9380 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9381 && flag_code != CODE_64BIT)
20f0a1fc 9382 return (const reg_entry *) NULL;
1ae00879 9383
b7240065
JB		 9384 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9385 return (const reg_entry *) NULL;
9386
252b5132
RH		 9387 return r;
9388}
4d1bb795
JB		 9389
9390/* REG_STRING starts *before* REGISTER_PREFIX. */
9391
9392static const reg_entry *
9393parse_register (char *reg_string, char **end_op)
9394{
9395 const reg_entry *r;
9396
9397 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9398 r = parse_real_register (reg_string, end_op);
9399 else
9400 r = NULL;
9401 if (!r)
9402 {
9403 char *save = input_line_pointer;
9404 char c;
9405 symbolS *symbolP;
9406
9407 input_line_pointer = reg_string;
9408 c = get_symbol_end ();
9409 symbolP = symbol_find (reg_string);
9410 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9411 {
9412 const expressionS *e = symbol_get_value_expression (symbolP);
9413
0398aac5 9414 know (e->X_op == O_register);
4eed87de 9415 know (e->X_add_number >= 0
c3fe08fa 9416 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 9417 r = i386_regtab + e->X_add_number;
9418 *end_op = input_line_pointer;
9419 }
9420 *input_line_pointer = c;
9421 input_line_pointer = save;
9422 }
9423 return r;
9424}
9425
9426int
9427i386_parse_name (char *name, expressionS *e, char *nextcharP)
9428{
9429 const reg_entry *r;
9430 char *end = input_line_pointer;
9431
9432 *end = *nextcharP;
9433 r = parse_register (name, &input_line_pointer);
9434 if (r && end <= input_line_pointer)
9435 {
9436 *nextcharP = *input_line_pointer;
9437 *input_line_pointer = 0;
9438 e->X_op = O_register;
9439 e->X_add_number = r - i386_regtab;
9440 return 1;
9441 }
9442 input_line_pointer = end;
9443 *end = 0;
ee86248c 9444 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9445}
9446
9447void
9448md_operand (expressionS *e)
9449{
ee86248c
JB		 9450 char *end;
9451 const reg_entry *r;
4d1bb795 9452
ee86248c
JB		 9453 switch (*input_line_pointer)
9454 {
9455 case REGISTER_PREFIX:
9456 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9457 if (r)
9458 {
9459 e->X_op = O_register;
9460 e->X_add_number = r - i386_regtab;
9461 input_line_pointer = end;
9462 }
ee86248c
JB		 9463 break;
9464
9465 case '[':
9c2799c2 9466 gas_assert (intel_syntax);
ee86248c
JB		 9467 end = input_line_pointer++;
9468 expression (e);
9469 if (*input_line_pointer == ']')
9470 {
9471 ++input_line_pointer;
9472 e->X_op_symbol = make_expr_symbol (e);
9473 e->X_add_symbol = NULL;
9474 e->X_add_number = 0;
9475 e->X_op = O_index;
9476 }
9477 else
9478 {
9479 e->X_op = O_absent;
9480 input_line_pointer = end;
9481 }
9482 break;
4d1bb795
JB		 9483 }
9484}
9485
252b5132 9486\f
4cc782b5 9487#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9488const char *md_shortopts = "kVQ:sqn";
252b5132 9489#else
12b55ccc 9490const char *md_shortopts = "qn";
252b5132 9491#endif
6e0b89ee 9492
3e73aa7c 9493#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9494#define OPTION_64 (OPTION_MD_BASE + 1)
9495#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9496#define OPTION_MARCH (OPTION_MD_BASE + 3)
9497#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9498#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9499#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9500#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9501#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9502#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9503#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9504#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9505#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9506#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9507#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9508#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9509#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9510#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9511#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
b3b91714 9512
99ad8390
NC		 9513struct option md_longopts[] =
9514{
3e73aa7c 9515 {"32", no_argument, NULL, OPTION_32},
321098a5 9516#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9517 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9518 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9519#endif
9520#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9521 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 9522#endif
b3b91714 9523 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9524 {"march", required_argument, NULL, OPTION_MARCH},
9525 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9526 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9527 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9528 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9529 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9530 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9531 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9532 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9533 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9534 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9535 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9536 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9537 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9538# if defined (TE_PE) || defined (TE_PEP)
9539 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9540#endif
252b5132
RH		 9541 {NULL, no_argument, NULL, 0}
9542};
9543size_t md_longopts_size = sizeof (md_longopts);
9544
9545int
9103f4f4 9546md_parse_option (int c, char *arg)
252b5132 9547{
91d6fa6a 9548 unsigned int j;
6305a203 9549 char *arch, *next;
9103f4f4 9550
252b5132
RH		 9551 switch (c)
9552 {
12b55ccc
L		 9553 case 'n':
9554 optimize_align_code = 0;
9555 break;
9556
a38cf1db
AM		 9557 case 'q':
9558 quiet_warnings = 1;
252b5132
RH		 9559 break;
9560
9561#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9562 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9563 should be emitted or not. FIXME: Not implemented. */
9564 case 'Q':
252b5132
RH		 9565 break;
9566
9567 /* -V: SVR4 argument to print version ID. */
9568 case 'V':
9569 print_version_id ();
9570 break;
9571
a38cf1db
AM		 9572 /* -k: Ignore for FreeBSD compatibility. */
9573 case 'k':
252b5132 9574 break;
4cc782b5
ILT		 9575
9576 case 's':
9577 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9578 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9579 break;
99ad8390 9580#endif
321098a5 9581#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9582 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9583 case OPTION_64:
9584 {
9585 const char **list, **l;
9586
3e73aa7c
JH		 9587 list = bfd_target_list ();
9588 for (l = list; *l != NULL; l++)
8620418b 9589 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9590 || strcmp (*l, "coff-x86-64") == 0
9591 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9592 || strcmp (*l, "pei-x86-64") == 0
9593 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9594 {
9595 default_arch = "x86_64";
9596 break;
9597 }
3e73aa7c 9598 if (*l == NULL)
2b5d6a91 9599 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9600 free (list);
9601 }
9602 break;
9603#endif
252b5132 9604
351f65ca 9605#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9606 case OPTION_X32:
351f65ca
L		 9607 if (IS_ELF)
9608 {
9609 const char **list, **l;
9610
9611 list = bfd_target_list ();
9612 for (l = list; *l != NULL; l++)
9613 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9614 {
9615 default_arch = "x86_64:32";
9616 break;
9617 }
9618 if (*l == NULL)
2b5d6a91 9619 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9620 free (list);
9621 }
9622 else
9623 as_fatal (_("32bit x86_64 is only supported for ELF"));
9624 break;
9625#endif
9626
6e0b89ee
AM		 9627 case OPTION_32:
9628 default_arch = "i386";
9629 break;
9630
b3b91714
AM		 9631 case OPTION_DIVIDE:
9632#ifdef SVR4_COMMENT_CHARS
9633 {
9634 char *n, *t;
9635 const char *s;
9636
9637 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9638 t = n;
9639 for (s = i386_comment_chars; *s != '\0'; s++)
9640 if (*s != '/')
9641 *t++ = *s;
9642 *t = '\0';
9643 i386_comment_chars = n;
9644 }
9645#endif
9646 break;
9647
9103f4f4 9648 case OPTION_MARCH:
6305a203
L		 9649 arch = xstrdup (arg);
9650 do
9103f4f4 9651 {
6305a203 9652 if (*arch == '.')
2b5d6a91 9653 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9654 next = strchr (arch, '+');
9655 if (next)
9656 *next++ = '\0';
91d6fa6a 9657 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9658 {
91d6fa6a 9659 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9660 {
6305a203 9661 /* Processor. */
1ded5609
JB		 9662 if (! cpu_arch[j].flags.bitfield.cpui386)
9663 continue;
9664
91d6fa6a 9665 cpu_arch_name = cpu_arch[j].name;
6305a203 9666 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9667 cpu_arch_flags = cpu_arch[j].flags;
9668 cpu_arch_isa = cpu_arch[j].type;
9669 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9670 if (!cpu_arch_tune_set)
9671 {
9672 cpu_arch_tune = cpu_arch_isa;
9673 cpu_arch_tune_flags = cpu_arch_isa_flags;
9674 }
9675 break;
9676 }
91d6fa6a
NC		 9677 else if (*cpu_arch [j].name == '.'
9678 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9679 {
9680 /* ISA entension. */
9681 i386_cpu_flags flags;
309d3373 9682
49021df2 9683 if (!cpu_arch[j].negated)
309d3373 9684 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9685 cpu_arch[j].flags);
309d3373
JB		 9686 else
9687 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9688 cpu_arch[j].flags);
0dfbf9d7 9689 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9690 {
9691 if (cpu_sub_arch_name)
9692 {
9693 char *name = cpu_sub_arch_name;
9694 cpu_sub_arch_name = concat (name,
91d6fa6a 9695 cpu_arch[j].name,
1bf57e9f 9696 (const char *) NULL);
6305a203
L		 9697 free (name);
9698 }
9699 else
91d6fa6a 9700 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9701 cpu_arch_flags = flags;
a586129e 9702 cpu_arch_isa_flags = flags;
6305a203
L		 9703 }
9704 break;
ccc9c027 9705 }
9103f4f4 9706 }
6305a203 9707
91d6fa6a 9708 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9709 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9710
9711 arch = next;
9103f4f4 9712 }
6305a203 9713 while (next != NULL );
9103f4f4
L		 9714 break;
9715
9716 case OPTION_MTUNE:
9717 if (*arg == '.')
2b5d6a91 9718 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9719 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9720 {
91d6fa6a 9721 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9722 {
ccc9c027 9723 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9724 cpu_arch_tune = cpu_arch [j].type;
9725 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9726 break;
9727 }
9728 }
91d6fa6a 9729 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9730 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9731 break;
9732
1efbbeb4
L		 9733 case OPTION_MMNEMONIC:
9734 if (strcasecmp (arg, "att") == 0)
9735 intel_mnemonic = 0;
9736 else if (strcasecmp (arg, "intel") == 0)
9737 intel_mnemonic = 1;
9738 else
2b5d6a91 9739 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9740 break;
9741
9742 case OPTION_MSYNTAX:
9743 if (strcasecmp (arg, "att") == 0)
9744 intel_syntax = 0;
9745 else if (strcasecmp (arg, "intel") == 0)
9746 intel_syntax = 1;
9747 else
2b5d6a91 9748 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9749 break;
9750
9751 case OPTION_MINDEX_REG:
9752 allow_index_reg = 1;
9753 break;
9754
9755 case OPTION_MNAKED_REG:
9756 allow_naked_reg = 1;
9757 break;
9758
9759 case OPTION_MOLD_GCC:
9760 old_gcc = 1;
1efbbeb4
L		 9761 break;
9762
c0f3af97
L		 9763 case OPTION_MSSE2AVX:
9764 sse2avx = 1;
9765 break;
9766
daf50ae7
L		 9767 case OPTION_MSSE_CHECK:
9768 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9769 sse_check = check_error;
daf50ae7 9770 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9771 sse_check = check_warning;
daf50ae7 9772 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9773 sse_check = check_none;
daf50ae7 9774 else
2b5d6a91 9775 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9776 break;
9777
7bab8ab5
JB		 9778 case OPTION_MOPERAND_CHECK:
9779 if (strcasecmp (arg, "error") == 0)
9780 operand_check = check_error;
9781 else if (strcasecmp (arg, "warning") == 0)
9782 operand_check = check_warning;
9783 else if (strcasecmp (arg, "none") == 0)
9784 operand_check = check_none;
9785 else
9786 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9787 break;
9788
539f890d
L		 9789 case OPTION_MAVXSCALAR:
9790 if (strcasecmp (arg, "128") == 0)
9791 avxscalar = vex128;
9792 else if (strcasecmp (arg, "256") == 0)
9793 avxscalar = vex256;
9794 else
2b5d6a91 9795 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9796 break;
9797
7e8b059b
L		 9798 case OPTION_MADD_BND_PREFIX:
9799 add_bnd_prefix = 1;
9800 break;
9801
43234a1e
L		 9802 case OPTION_MEVEXLIG:
9803 if (strcmp (arg, "128") == 0)
9804 evexlig = evexl128;
9805 else if (strcmp (arg, "256") == 0)
9806 evexlig = evexl256;
9807 else if (strcmp (arg, "512") == 0)
9808 evexlig = evexl512;
9809 else
9810 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9811 break;
9812
9813 case OPTION_MEVEXWIG:
9814 if (strcmp (arg, "0") == 0)
9815 evexwig = evexw0;
9816 else if (strcmp (arg, "1") == 0)
9817 evexwig = evexw1;
9818 else
9819 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9820 break;
9821
167ad85b
TG		 9822# if defined (TE_PE) || defined (TE_PEP)
9823 case OPTION_MBIG_OBJ:
9824 use_big_obj = 1;
9825 break;
9826#endif
9827
252b5132
RH		 9828 default:
9829 return 0;
9830 }
9831 return 1;
9832}
9833
8a2c8fef
L		 9834#define MESSAGE_TEMPLATE \
9835" "
9836
9837static void
1ded5609 9838show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9839{
9840 static char message[] = MESSAGE_TEMPLATE;
9841 char *start = message + 27;
9842 char *p;
9843 int size = sizeof (MESSAGE_TEMPLATE);
9844 int left;
9845 const char *name;
9846 int len;
9847 unsigned int j;
9848
9849 p = start;
9850 left = size - (start - message);
9851 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9852 {
9853 /* Should it be skipped? */
9854 if (cpu_arch [j].skip)
9855 continue;
9856
9857 name = cpu_arch [j].name;
9858 len = cpu_arch [j].len;
9859 if (*name == '.')
9860 {
9861 /* It is an extension. Skip if we aren't asked to show it. */
9862 if (ext)
9863 {
9864 name++;
9865 len--;
9866 }
9867 else
9868 continue;
9869 }
9870 else if (ext)
9871 {
9872 /* It is an processor. Skip if we show only extension. */
9873 continue;
9874 }
1ded5609
JB		 9875 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9876 {
9877 /* It is an impossible processor - skip. */
9878 continue;
9879 }
8a2c8fef
L		 9880
9881 /* Reserve 2 spaces for ", " or ",\0" */
9882 left -= len + 2;
9883
9884 /* Check if there is any room. */
9885 if (left >= 0)
9886 {
9887 if (p != start)
9888 {
9889 *p++ = ',';
9890 *p++ = ' ';
9891 }
9892 p = mempcpy (p, name, len);
9893 }
9894 else
9895 {
9896 /* Output the current message now and start a new one. */
9897 *p++ = ',';
9898 *p = '\0';
9899 fprintf (stream, "%s\n", message);
9900 p = start;
9901 left = size - (start - message) - len - 2;
8d63c93e 9902
8a2c8fef
L		 9903 gas_assert (left >= 0);
9904
9905 p = mempcpy (p, name, len);
9906 }
9907 }
9908
9909 *p = '\0';
9910 fprintf (stream, "%s\n", message);
9911}
9912
252b5132 9913void
8a2c8fef 9914md_show_usage (FILE *stream)
252b5132 9915{
4cc782b5
ILT		 9916#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9917 fprintf (stream, _("\
a38cf1db
AM		 9918 -Q ignored\n\
9919 -V print assembler version number\n\
b3b91714
AM		 9920 -k ignored\n"));
9921#endif
9922 fprintf (stream, _("\
12b55ccc 9923 -n Do not optimize code alignment\n\
b3b91714
AM		 9924 -q quieten some warnings\n"));
9925#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9926 fprintf (stream, _("\
a38cf1db 9927 -s ignored\n"));
b3b91714 9928#endif
321098a5
L		 9929#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9930 || defined (TE_PE) || defined (TE_PEP))
751d281c 9931 fprintf (stream, _("\
570561f7 9932 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 9933#endif
b3b91714
AM		 9934#ifdef SVR4_COMMENT_CHARS
9935 fprintf (stream, _("\
9936 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 9937#else
9938 fprintf (stream, _("\
b3b91714 9939 --divide ignored\n"));
4cc782b5 9940#endif
9103f4f4 9941 fprintf (stream, _("\
6305a203 9942 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 9943 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 9944 show_arch (stream, 0, 1);
8a2c8fef
L		 9945 fprintf (stream, _("\
9946 EXTENSION is combination of:\n"));
1ded5609 9947 show_arch (stream, 1, 0);
6305a203 9948 fprintf (stream, _("\
8a2c8fef 9949 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 9950 show_arch (stream, 0, 0);
ba104c83 9951 fprintf (stream, _("\
c0f3af97
L		 9952 -msse2avx encode SSE instructions with VEX prefix\n"));
9953 fprintf (stream, _("\
daf50ae7
L		 9954 -msse-check=[none|error|warning]\n\
9955 check SSE instructions\n"));
9956 fprintf (stream, _("\
7bab8ab5
JB		 9957 -moperand-check=[none|error|warning]\n\
9958 check operand combinations for validity\n"));
9959 fprintf (stream, _("\
539f890d
L		 9960 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9961 length\n"));
9962 fprintf (stream, _("\
43234a1e
L		 9963 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9964 length\n"));
9965 fprintf (stream, _("\
9966 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9967 for EVEX.W bit ignored instructions\n"));
9968 fprintf (stream, _("\
ba104c83
L		 9969 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9970 fprintf (stream, _("\
9971 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9972 fprintf (stream, _("\
9973 -mindex-reg support pseudo index registers\n"));
9974 fprintf (stream, _("\
9975 -mnaked-reg don't require `%%' prefix for registers\n"));
9976 fprintf (stream, _("\
9977 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 9978 fprintf (stream, _("\
9979 -madd-bnd-prefix add BND prefix for all valid branches\n"));
167ad85b
TG		 9980# if defined (TE_PE) || defined (TE_PEP)
9981 fprintf (stream, _("\
9982 -mbig-obj generate big object files\n"));
9983#endif
252b5132
RH		 9984}
9985
3e73aa7c 9986#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 9987 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 9988 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 9989
9990/* Pick the target format to use. */
9991
47926f60 9992const char *
e3bb37b5 9993i386_target_format (void)
252b5132 9994{
351f65ca
L		 9995 if (!strncmp (default_arch, "x86_64", 6))
9996 {
9997 update_code_flag (CODE_64BIT, 1);
9998 if (default_arch[6] == '\0')
7f56bc95 9999 x86_elf_abi = X86_64_ABI;
351f65ca 10000 else
7f56bc95 10001 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10002 }
3e73aa7c 10003 else if (!strcmp (default_arch, "i386"))
78f12dd3 10004 update_code_flag (CODE_32BIT, 1);
3e73aa7c 10005 else
2b5d6a91 10006 as_fatal (_("unknown architecture"));
89507696
JB		 10007
10008 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10009 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10010 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10011 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10012
252b5132
RH		 10013 switch (OUTPUT_FLAVOR)
10014 {
9384f2ff 10015#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10016 case bfd_target_aout_flavour:
47926f60 10017 return AOUT_TARGET_FORMAT;
4c63da97 10018#endif
9384f2ff
AM		 10019#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10020# if defined (TE_PE) || defined (TE_PEP)
10021 case bfd_target_coff_flavour:
167ad85b
TG		 10022 if (flag_code == CODE_64BIT)
10023 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10024 else
10025 return "pe-i386";
9384f2ff 10026# elif defined (TE_GO32)
0561d57c
JK		 10027 case bfd_target_coff_flavour:
10028 return "coff-go32";
9384f2ff 10029# else
252b5132
RH		 10030 case bfd_target_coff_flavour:
10031 return "coff-i386";
9384f2ff 10032# endif
4c63da97 10033#endif
3e73aa7c 10034#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10035 case bfd_target_elf_flavour:
3e73aa7c 10036 {
351f65ca
L		 10037 const char *format;
10038
10039 switch (x86_elf_abi)
4fa24527 10040 {
351f65ca
L		 10041 default:
10042 format = ELF_TARGET_FORMAT;
10043 break;
7f56bc95 10044 case X86_64_ABI:
351f65ca 10045 use_rela_relocations = 1;
4fa24527 10046 object_64bit = 1;
351f65ca
L		 10047 format = ELF_TARGET_FORMAT64;
10048 break;
7f56bc95 10049 case X86_64_X32_ABI:
4fa24527 10050 use_rela_relocations = 1;
351f65ca 10051 object_64bit = 1;
862be3fb 10052 disallow_64bit_reloc = 1;
351f65ca
L		 10053 format = ELF_TARGET_FORMAT32;
10054 break;
4fa24527 10055 }
3632d14b 10056 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10057 {
7f56bc95 10058 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10059 as_fatal (_("Intel L1OM is 64bit only"));
10060 return ELF_TARGET_L1OM_FORMAT;
10061 }
7a9068fe
L		 10062 if (cpu_arch_isa == PROCESSOR_K1OM)
10063 {
10064 if (x86_elf_abi != X86_64_ABI)
10065 as_fatal (_("Intel K1OM is 64bit only"));
10066 return ELF_TARGET_K1OM_FORMAT;
10067 }
8a9036a4 10068 else
351f65ca 10069 return format;
3e73aa7c 10070 }
e57f8c65
TG		 10071#endif
10072#if defined (OBJ_MACH_O)
10073 case bfd_target_mach_o_flavour:
d382c579
TG		 10074 if (flag_code == CODE_64BIT)
10075 {
10076 use_rela_relocations = 1;
10077 object_64bit = 1;
10078 return "mach-o-x86-64";
10079 }
10080 else
10081 return "mach-o-i386";
4c63da97 10082#endif
252b5132
RH		 10083 default:
10084 abort ();
10085 return NULL;
10086 }
10087}
10088
47926f60 10089#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 10090
10091#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 10092void
10093i386_elf_emit_arch_note (void)
a847613f 10094{
718ddfc0 10095 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 10096 {
10097 char *p;
10098 asection *seg = now_seg;
10099 subsegT subseg = now_subseg;
10100 Elf_Internal_Note i_note;
10101 Elf_External_Note e_note;
10102 asection *note_secp;
10103 int len;
10104
10105 /* Create the .note section. */
10106 note_secp = subseg_new (".note", 0);
10107 bfd_set_section_flags (stdoutput,
10108 note_secp,
10109 SEC_HAS_CONTENTS | SEC_READONLY);
10110
10111 /* Process the arch string. */
10112 len = strlen (cpu_arch_name);
10113
10114 i_note.namesz = len + 1;
10115 i_note.descsz = 0;
10116 i_note.type = NT_ARCH;
10117 p = frag_more (sizeof (e_note.namesz));
10118 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10119 p = frag_more (sizeof (e_note.descsz));
10120 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10121 p = frag_more (sizeof (e_note.type));
10122 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10123 p = frag_more (len + 1);
10124 strcpy (p, cpu_arch_name);
10125
10126 frag_align (2, 0, 0);
10127
10128 subseg_set (seg, subseg);
10129 }
10130}
10131#endif
252b5132 10132\f
252b5132 10133symbolS *
7016a5d5 10134md_undefined_symbol (char *name)
252b5132 10135{
18dc2407
ILT		 10136 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10137 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10138 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10139 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10140 {
10141 if (!GOT_symbol)
10142 {
10143 if (symbol_find (name))
10144 as_bad (_("GOT already in symbol table"));
10145 GOT_symbol = symbol_new (name, undefined_section,
10146 (valueT) 0, &zero_address_frag);
10147 };
10148 return GOT_symbol;
10149 }
252b5132
RH		 10150 return 0;
10151}
10152
10153/* Round up a section size to the appropriate boundary. */
47926f60 10154
252b5132 10155valueT
7016a5d5 10156md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10157{
4c63da97
AM		 10158#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10159 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10160 {
10161 /* For a.out, force the section size to be aligned. If we don't do
10162 this, BFD will align it for us, but it will not write out the
10163 final bytes of the section. This may be a bug in BFD, but it is
10164 easier to fix it here since that is how the other a.out targets
10165 work. */
10166 int align;
10167
10168 align = bfd_get_section_alignment (stdoutput, segment);
10169 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10170 }
252b5132
RH		 10171#endif
10172
10173 return size;
10174}
10175
10176/* On the i386, PC-relative offsets are relative to the start of the
10177 next instruction. That is, the address of the offset, plus its
10178 size, since the offset is always the last part of the insn. */
10179
10180long
e3bb37b5 10181md_pcrel_from (fixS *fixP)
252b5132
RH		 10182{
10183 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10184}
10185
10186#ifndef I386COFF
10187
10188static void
e3bb37b5 10189s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10190{
29b0f896 10191 int temp;
252b5132 10192
8a75718c
JB		 10193#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10194 if (IS_ELF)
10195 obj_elf_section_change_hook ();
10196#endif
252b5132
RH		 10197 temp = get_absolute_expression ();
10198 subseg_set (bss_section, (subsegT) temp);
10199 demand_empty_rest_of_line ();
10200}
10201
10202#endif
10203
252b5132 10204void
e3bb37b5 10205i386_validate_fix (fixS *fixp)
252b5132
RH		 10206{
10207 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10208 {
23df1078
JH		 10209 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10210 {
4fa24527 10211 if (!object_64bit)
23df1078
JH		 10212 abort ();
10213 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10214 }
10215 else
10216 {
4fa24527 10217 if (!object_64bit)
d6ab8113
JB		 10218 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10219 else
10220 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10221 }
252b5132
RH		 10222 fixp->fx_subsy = 0;
10223 }
10224}
10225
252b5132 10226arelent *
7016a5d5 10227tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10228{
10229 arelent *rel;
10230 bfd_reloc_code_real_type code;
10231
10232 switch (fixp->fx_r_type)
10233 {
8ce3d284 10234#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10235 case BFD_RELOC_SIZE32:
10236 case BFD_RELOC_SIZE64:
10237 if (S_IS_DEFINED (fixp->fx_addsy)
10238 && !S_IS_EXTERNAL (fixp->fx_addsy))
10239 {
10240 /* Resolve size relocation against local symbol to size of
10241 the symbol plus addend. */
10242 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10243 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10244 && !fits_in_unsigned_long (value))
10245 as_bad_where (fixp->fx_file, fixp->fx_line,
10246 _("symbol size computation overflow"));
10247 fixp->fx_addsy = NULL;
10248 fixp->fx_subsy = NULL;
10249 md_apply_fix (fixp, (valueT *) &value, NULL);
10250 return NULL;
10251 }
8ce3d284 10252#endif
8fd4256d 10253
3e73aa7c 10254 case BFD_RELOC_X86_64_PLT32:
c3320543 10255 case BFD_RELOC_X86_64_PLT32_BND:
3e73aa7c
JH		 10256 case BFD_RELOC_X86_64_GOT32:
10257 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10258 case BFD_RELOC_386_PLT32:
10259 case BFD_RELOC_386_GOT32:
10260 case BFD_RELOC_386_GOTOFF:
10261 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10262 case BFD_RELOC_386_TLS_GD:
10263 case BFD_RELOC_386_TLS_LDM:
10264 case BFD_RELOC_386_TLS_LDO_32:
10265 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10266 case BFD_RELOC_386_TLS_IE:
10267 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10268 case BFD_RELOC_386_TLS_LE_32:
10269 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10270 case BFD_RELOC_386_TLS_GOTDESC:
10271 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10272 case BFD_RELOC_X86_64_TLSGD:
10273 case BFD_RELOC_X86_64_TLSLD:
10274 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10275 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10276 case BFD_RELOC_X86_64_GOTTPOFF:
10277 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10278 case BFD_RELOC_X86_64_TPOFF64:
10279 case BFD_RELOC_X86_64_GOTOFF64:
10280 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10281 case BFD_RELOC_X86_64_GOT64:
10282 case BFD_RELOC_X86_64_GOTPCREL64:
10283 case BFD_RELOC_X86_64_GOTPC64:
10284 case BFD_RELOC_X86_64_GOTPLT64:
10285 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10286 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10287 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10288 case BFD_RELOC_RVA:
10289 case BFD_RELOC_VTABLE_ENTRY:
10290 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10291#ifdef TE_PE
10292 case BFD_RELOC_32_SECREL:
10293#endif
252b5132
RH		 10294 code = fixp->fx_r_type;
10295 break;
dbbaec26
L		 10296 case BFD_RELOC_X86_64_32S:
10297 if (!fixp->fx_pcrel)
10298 {
10299 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10300 code = fixp->fx_r_type;
10301 break;
10302 }
252b5132 10303 default:
93382f6d 10304 if (fixp->fx_pcrel)
252b5132 10305 {
93382f6d
AM		 10306 switch (fixp->fx_size)
10307 {
10308 default:
b091f402
AM		 10309 as_bad_where (fixp->fx_file, fixp->fx_line,
10310 _("can not do %d byte pc-relative relocation"),
10311 fixp->fx_size);
93382f6d
AM		 10312 code = BFD_RELOC_32_PCREL;
10313 break;
10314 case 1: code = BFD_RELOC_8_PCREL; break;
10315 case 2: code = BFD_RELOC_16_PCREL; break;
c3320543
L		 10316 case 4:
10317 code = (fixp->fx_r_type == BFD_RELOC_X86_64_PC32_BND
10318 ? fixp-> fx_r_type : BFD_RELOC_32_PCREL);
10319 break;
d6ab8113
JB		 10320#ifdef BFD64
10321 case 8: code = BFD_RELOC_64_PCREL; break;
10322#endif
93382f6d
AM		 10323 }
10324 }
10325 else
10326 {
10327 switch (fixp->fx_size)
10328 {
10329 default:
b091f402
AM		 10330 as_bad_where (fixp->fx_file, fixp->fx_line,
10331 _("can not do %d byte relocation"),
10332 fixp->fx_size);
93382f6d
AM		 10333 code = BFD_RELOC_32;
10334 break;
10335 case 1: code = BFD_RELOC_8; break;
10336 case 2: code = BFD_RELOC_16; break;
10337 case 4: code = BFD_RELOC_32; break;
937149dd 10338#ifdef BFD64
3e73aa7c 10339 case 8: code = BFD_RELOC_64; break;
937149dd 10340#endif
93382f6d 10341 }
252b5132
RH		 10342 }
10343 break;
10344 }
252b5132 10345
d182319b
JB		 10346 if ((code == BFD_RELOC_32
10347 || code == BFD_RELOC_32_PCREL
10348 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10349 && GOT_symbol
10350 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10351 {
4fa24527 10352 if (!object_64bit)
d6ab8113
JB		 10353 code = BFD_RELOC_386_GOTPC;
10354 else
10355 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10356 }
7b81dfbb
AJ		 10357 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10358 && GOT_symbol
10359 && fixp->fx_addsy == GOT_symbol)
10360 {
10361 code = BFD_RELOC_X86_64_GOTPC64;
10362 }
252b5132
RH		 10363
10364 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10365 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10366 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10367
10368 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10369
3e73aa7c
JH		 10370 if (!use_rela_relocations)
10371 {
10372 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10373 vtable entry to be used in the relocation's section offset. */
10374 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10375 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10376#if defined (OBJ_COFF) && defined (TE_PE)
10377 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10378 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10379 else
10380#endif
c6682705 10381 rel->addend = 0;
3e73aa7c
JH		 10382 }
10383 /* Use the rela in 64bit mode. */
252b5132 10384 else
3e73aa7c 10385 {
862be3fb
L		 10386 if (disallow_64bit_reloc)
10387 switch (code)
10388 {
862be3fb
L		 10389 case BFD_RELOC_X86_64_DTPOFF64:
10390 case BFD_RELOC_X86_64_TPOFF64:
10391 case BFD_RELOC_64_PCREL:
10392 case BFD_RELOC_X86_64_GOTOFF64:
10393 case BFD_RELOC_X86_64_GOT64:
10394 case BFD_RELOC_X86_64_GOTPCREL64:
10395 case BFD_RELOC_X86_64_GOTPC64:
10396 case BFD_RELOC_X86_64_GOTPLT64:
10397 case BFD_RELOC_X86_64_PLTOFF64:
10398 as_bad_where (fixp->fx_file, fixp->fx_line,
10399 _("cannot represent relocation type %s in x32 mode"),
10400 bfd_get_reloc_code_name (code));
10401 break;
10402 default:
10403 break;
10404 }
10405
062cd5e7
AS		 10406 if (!fixp->fx_pcrel)
10407 rel->addend = fixp->fx_offset;
10408 else
10409 switch (code)
10410 {
10411 case BFD_RELOC_X86_64_PLT32:
c3320543 10412 case BFD_RELOC_X86_64_PLT32_BND:
062cd5e7
AS		 10413 case BFD_RELOC_X86_64_GOT32:
10414 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10415 case BFD_RELOC_X86_64_TLSGD:
10416 case BFD_RELOC_X86_64_TLSLD:
10417 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10418 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10419 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10420 rel->addend = fixp->fx_offset - fixp->fx_size;
10421 break;
10422 default:
10423 rel->addend = (section->vma
10424 - fixp->fx_size
10425 + fixp->fx_addnumber
10426 + md_pcrel_from (fixp));
10427 break;
10428 }
3e73aa7c
JH		 10429 }
10430
252b5132
RH		 10431 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10432 if (rel->howto == NULL)
10433 {
10434 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10435 _("cannot represent relocation type %s"),
252b5132
RH		 10436 bfd_get_reloc_code_name (code));
10437 /* Set howto to a garbage value so that we can keep going. */
10438 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10439 gas_assert (rel->howto != NULL);
252b5132
RH		 10440 }
10441
10442 return rel;
10443}
10444
ee86248c 10445#include "tc-i386-intel.c"
54cfded0 10446
a60de03c
JB		 10447void
10448tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10449{
a60de03c
JB		 10450 int saved_naked_reg;
10451 char saved_register_dot;
54cfded0 10452
a60de03c
JB		 10453 saved_naked_reg = allow_naked_reg;
10454 allow_naked_reg = 1;
10455 saved_register_dot = register_chars['.'];
10456 register_chars['.'] = '.';
10457 allow_pseudo_reg = 1;
10458 expression_and_evaluate (exp);
10459 allow_pseudo_reg = 0;
10460 register_chars['.'] = saved_register_dot;
10461 allow_naked_reg = saved_naked_reg;
10462
e96d56a1 10463 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10464 {
a60de03c
JB		 10465 if ((addressT) exp->X_add_number < i386_regtab_size)
10466 {
10467 exp->X_op = O_constant;
10468 exp->X_add_number = i386_regtab[exp->X_add_number]
10469 .dw2_regnum[flag_code >> 1];
10470 }
10471 else
10472 exp->X_op = O_illegal;
54cfded0 10473 }
54cfded0
AM		 10474}
10475
10476void
10477tc_x86_frame_initial_instructions (void)
10478{
a60de03c
JB		 10479 static unsigned int sp_regno[2];
10480
10481 if (!sp_regno[flag_code >> 1])
10482 {
10483 char *saved_input = input_line_pointer;
10484 char sp[][4] = {"esp", "rsp"};
10485 expressionS exp;
a4447b93 10486
a60de03c
JB		 10487 input_line_pointer = sp[flag_code >> 1];
10488 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10489 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10490 sp_regno[flag_code >> 1] = exp.X_add_number;
10491 input_line_pointer = saved_input;
10492 }
a4447b93 10493
61ff971f
L		 10494 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10495 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10496}
d2b2c203 10497
d7921315
L		 10498int
10499x86_dwarf2_addr_size (void)
10500{
10501#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10502 if (x86_elf_abi == X86_64_X32_ABI)
10503 return 4;
10504#endif
10505 return bfd_arch_bits_per_address (stdoutput) / 8;
10506}
10507
d2b2c203
DJ		 10508int
10509i386_elf_section_type (const char *str, size_t len)
10510{
10511 if (flag_code == CODE_64BIT
10512 && len == sizeof ("unwind") - 1
10513 && strncmp (str, "unwind", 6) == 0)
10514 return SHT_X86_64_UNWIND;
10515
10516 return -1;
10517}
bb41ade5 10518
ad5fec3b
EB		 10519#ifdef TE_SOLARIS
10520void
10521i386_solaris_fix_up_eh_frame (segT sec)
10522{
10523 if (flag_code == CODE_64BIT)
10524 elf_section_type (sec) = SHT_X86_64_UNWIND;
10525}
10526#endif
10527
bb41ade5
AM		 10528#ifdef TE_PE
10529void
10530tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10531{
91d6fa6a 10532 expressionS exp;
bb41ade5 10533
91d6fa6a
NC		 10534 exp.X_op = O_secrel;
10535 exp.X_add_symbol = symbol;
10536 exp.X_add_number = 0;
10537 emit_expr (&exp, size);
bb41ade5
AM		 10538}
10539#endif
3b22753a
L		 10540
10541#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10542/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10543
01e1a5bc 10544bfd_vma
3b22753a
L		 10545x86_64_section_letter (int letter, char **ptr_msg)
10546{
10547 if (flag_code == CODE_64BIT)
10548 {
10549 if (letter == 'l')
10550 return SHF_X86_64_LARGE;
10551
8f3bae45 10552 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10553 }
3b22753a 10554 else
8f3bae45 10555 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10556 return -1;
10557}
10558
01e1a5bc 10559bfd_vma
3b22753a
L		 10560x86_64_section_word (char *str, size_t len)
10561{
8620418b 10562 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10563 return SHF_X86_64_LARGE;
10564
10565 return -1;
10566}
10567
10568static void
10569handle_large_common (int small ATTRIBUTE_UNUSED)
10570{
10571 if (flag_code != CODE_64BIT)
10572 {
10573 s_comm_internal (0, elf_common_parse);
10574 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10575 }
10576 else
10577 {
10578 static segT lbss_section;
10579 asection *saved_com_section_ptr = elf_com_section_ptr;
10580 asection *saved_bss_section = bss_section;
10581
10582 if (lbss_section == NULL)
10583 {
10584 flagword applicable;
10585 segT seg = now_seg;
10586 subsegT subseg = now_subseg;
10587
10588 /* The .lbss section is for local .largecomm symbols. */
10589 lbss_section = subseg_new (".lbss", 0);
10590 applicable = bfd_applicable_section_flags (stdoutput);
10591 bfd_set_section_flags (stdoutput, lbss_section,
10592 applicable & SEC_ALLOC);
10593 seg_info (lbss_section)->bss = 1;
10594
10595 subseg_set (seg, subseg);
10596 }
10597
10598 elf_com_section_ptr = &_bfd_elf_large_com_section;
10599 bss_section = lbss_section;
10600
10601 s_comm_internal (0, elf_common_parse);
10602
10603 elf_com_section_ptr = saved_com_section_ptr;
10604 bss_section = saved_bss_section;
10605 }
10606}
10607#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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