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Use ctime_r and localtime_r for threadsafety
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
6aa385b9
JB		 12019-11-14 Jan Beulich <jbeulich@suse.com>
2
3 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
4 * i386-tbl.h: Re-generate.
5
0cfa3eb3
JB		 62019-11-14 Jan Beulich <jbeulich@suse.com>
7
8 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
9 JumpInterSegment, and JumpAbsolute entries.
10 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
11 JUMP_ABSOLUTE): Define.
12 (struct i386_opcode_modifier): Extend jump field to 3 bits.
13 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
14 fields.
15 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
16 JumpInterSegment): Define.
17 * i386-tbl.h: Re-generate.
18
6f2f06be
JB		 192019-11-14 Jan Beulich <jbeulich@suse.com>
20
21 * i386-gen.c (operand_type_init): Remove
22 OPERAND_TYPE_JUMPABSOLUTE entry.
23 (opcode_modifiers): Add JumpAbsolute entry.
24 (operand_types): Remove JumpAbsolute entry.
25 * i386-opc.h (JumpAbsolute): Move between enums.
26 (struct i386_opcode_modifier): Add jumpabsolute field.
27 (union i386_operand_type): Remove jumpabsolute field.
28 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
29 * i386-init.h, i386-tbl.h: Re-generate.
30
601e8564
JB		 312019-11-14 Jan Beulich <jbeulich@suse.com>
32
33 * i386-gen.c (opcode_modifiers): Add AnySize entry.
34 (operand_types): Remove AnySize entry.
35 * i386-opc.h (AnySize): Move between enums.
36 (struct i386_opcode_modifier): Add anysize field.
37 (OTUnused): Un-comment.
38 (union i386_operand_type): Remove anysize field.
39 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
40 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
41 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
42 AnySize.
43 * i386-tbl.h: Re-generate.
44
7722d40a
JW		 452019-11-12 Nelson Chu <nelson.chu@sifive.com>
46
47 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
48 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
49 use the floating point register (FPR).
50
ce760a76
MI		 512019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
52
53 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
54 cmode 1101.
55 (is_mve_encoding_conflict): Update cmode conflict checks for
56 MVE_VMVN_IMM.
57
51c8edf6
JB		 582019-11-12 Jan Beulich <jbeulich@suse.com>
59
60 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
61 entry.
62 (operand_types): Remove EsSeg entry.
63 (main): Replace stale use of OTMax.
64 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
65 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
66 (EsSeg): Delete.
67 (OTUnused): Comment out.
68 (union i386_operand_type): Remove esseg field.
69 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
70 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
71 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
72 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
73 * i386-init.h, i386-tbl.h: Re-generate.
74
474da251
JB		 752019-11-12 Jan Beulich <jbeulich@suse.com>
76
77 * i386-gen.c (operand_instances): Add RegB entry.
78 * i386-opc.h (enum operand_instance): Add RegB.
79 * i386-opc.tbl (RegC, RegD, RegB): Define.
80 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
81 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
82 monitorx, mwaitx): Drop ImmExt and convert encodings
83 accordingly.
84 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
85 (edx, rdx): Add Instance=RegD.
86 (ebx, rbx): Add Instance=RegB.
87 * i386-tbl.h: Re-generate.
88
75e5731b
JB		 892019-11-12 Jan Beulich <jbeulich@suse.com>
90
91 * i386-gen.c (operand_type_init): Adjust
92 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
93 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
94 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
95 (operand_instances): New.
96 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
97 (output_operand_type): New parameter "instance". Process it.
98 (process_i386_operand_type): New local variable "instance".
99 (main): Adjust static assertions.
100 * i386-opc.h (INSTANCE_WIDTH): Define.
101 (enum operand_instance): New.
102 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
103 (union i386_operand_type): Replace acc, inoutportreg, and
104 shiftcount by instance.
105 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
106 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
107 Add Instance=.
108 * i386-init.h, i386-tbl.h: Re-generate.
109
91802f3c
JB		 1102019-11-11 Jan Beulich <jbeulich@suse.com>
111
112 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
113 smaxp/sminp entries' "tied_operand" field to 2.
114
4f5fc85d
JB		 1152019-11-11 Jan Beulich <jbeulich@suse.com>
116
117 * aarch64-opc.c (operand_general_constraint_met_p): Replace
118 "index" local variable by that of the already existing "num".
119
dc2be329
L		 1202019-11-08 H.J. Lu <hongjiu.lu@intel.com>
121
122 PR gas/25167
123 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
124 * i386-tbl.h: Regenerated.
125
f74a6307
JB		 1262019-11-08 Jan Beulich <jbeulich@suse.com>
127
128 * i386-gen.c (operand_type_init): Add Class= to
129 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
130 OPERAND_TYPE_REGBND entry.
131 (operand_classes): Add RegMask and RegBND entries.
132 (operand_types): Drop RegMask and RegBND entry.
133 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
134 (RegMask, RegBND): Delete.
135 (union i386_operand_type): Remove regmask and regbnd fields.
136 * i386-opc.tbl (RegMask, RegBND): Define.
137 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
138 Class=RegBND.
139 * i386-init.h, i386-tbl.h: Re-generate.
140
3528c362
JB		 1412019-11-08 Jan Beulich <jbeulich@suse.com>
142
143 * i386-gen.c (operand_type_init): Add Class= to
144 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
145 OPERAND_TYPE_REGZMM entries.
146 (operand_classes): Add RegMMX and RegSIMD entries.
147 (operand_types): Drop RegMMX and RegSIMD entries.
148 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
149 (RegMMX, RegSIMD): Delete.
150 (union i386_operand_type): Remove regmmx and regsimd fields.
151 * i386-opc.tbl (RegMMX): Define.
152 (RegXMM, RegYMM, RegZMM): Add Class=.
153 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
154 Class=RegSIMD.
155 * i386-init.h, i386-tbl.h: Re-generate.
156
4a5c67ed
JB		 1572019-11-08 Jan Beulich <jbeulich@suse.com>
158
159 * i386-gen.c (operand_type_init): Add Class= to
160 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
161 entries.
162 (operand_classes): Add RegCR, RegDR, and RegTR entries.
163 (operand_types): Drop Control, Debug, and Test entries.
164 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
165 (Control, Debug, Test): Delete.
166 (union i386_operand_type): Remove control, debug, and test
167 fields.
168 * i386-opc.tbl (Control, Debug, Test): Define.
169 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
170 Class=RegDR, and Test by Class=RegTR.
171 * i386-init.h, i386-tbl.h: Re-generate.
172
00cee14f
JB		 1732019-11-08 Jan Beulich <jbeulich@suse.com>
174
175 * i386-gen.c (operand_type_init): Add Class= to
176 OPERAND_TYPE_SREG entry.
177 (operand_classes): Add SReg entry.
178 (operand_types): Drop SReg entry.
179 * i386-opc.h (enum operand_class): Add SReg.
180 (SReg): Delete.
181 (union i386_operand_type): Remove sreg field.
182 * i386-opc.tbl (SReg): Define.
183 * i386-reg.tbl: Replace SReg by Class=SReg.
184 * i386-init.h, i386-tbl.h: Re-generate.
185
bab6aec1
JB		 1862019-11-08 Jan Beulich <jbeulich@suse.com>
187
188 * i386-gen.c (operand_type_init): Add Class=. New
189 OPERAND_TYPE_ANYIMM entry.
190 (operand_classes): New.
191 (operand_types): Drop Reg entry.
192 (output_operand_type): New parameter "class". Process it.
193 (process_i386_operand_type): New local variable "class".
194 (main): Adjust static assertions.
195 * i386-opc.h (CLASS_WIDTH): Define.
196 (enum operand_class): New.
197 (Reg): Replace by Class. Adjust comment.
198 (union i386_operand_type): Replace reg by class.
199 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
200 Class=.
201 * i386-reg.tbl: Replace Reg by Class=Reg.
202 * i386-init.h: Re-generate.
203
1f4cd317
MM		 2042019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
205
206 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
207 (aarch64_opcode_table): Add data gathering hint mnemonic.
208 * opcodes/aarch64-dis-2.c: Account for new instruction.
209
616ce08e
MM		 2102019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
211
212 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
213
214
8382113f
MM		 2152019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
216
217 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
218 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
219 aarch64_feature_f64mm): New feature sets.
220 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
221 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
222 instructions.
223 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
224 macros.
225 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
226 (OP_SVE_QQQ): New qualifier.
227 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
228 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
229 the movprfx constraint.
230 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
231 (aarch64_opcode_table): Define new instructions smmla,
232 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
233 uzip{1/2}, trn{1/2}.
234 * aarch64-opc.c (operand_general_constraint_met_p): Handle
235 AARCH64_OPND_SVE_ADDR_RI_S4x32.
236 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
237 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
238 Account for new instructions.
239 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
240 S4x32 operand.
241 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
242
aab2c27d
MM		 2432019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2442019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
245
246 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
247 Armv8.6-A.
248 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
249 (neon_opcodes): Add bfloat SIMD instructions.
250 (print_insn_coprocessor): Add new control character %b to print
251 condition code without checking cp_num.
252 (print_insn_neon): Account for BFloat16 instructions that have no
253 special top-byte handling.
254
33593eaf
MM		 2552019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2562019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
257
258 * arm-dis.c (print_insn_coprocessor,
259 print_insn_generic_coprocessor): Create wrapper functions around
260 the implementation of the print_insn_coprocessor control codes.
261 (print_insn_coprocessor_1): Original print_insn_coprocessor
262 function that now takes which array to look at as an argument.
263 (print_insn_arm): Use both print_insn_coprocessor and
264 print_insn_generic_coprocessor.
265 (print_insn_thumb32): As above.
266
df678013
MM		 2672019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2682019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
269
270 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
271 in reglane special case.
272 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
273 aarch64_find_next_opcode): Account for new instructions.
274 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
275 in reglane special case.
276 * aarch64-opc.c (struct operand_qualifier_data): Add data for
277 new AARCH64_OPND_QLF_S_2H qualifier.
278 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
279 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
280 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
281 sets.
282 (BFLOAT_SVE, BFLOAT): New feature set macros.
283 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
284 instructions.
285 (aarch64_opcode_table): Define new instructions bfdot,
286 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
287 bfcvtn2, bfcvt.
288
8ae2d3d9
MM		 2892019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2902019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
291
292 * aarch64-tbl.h (ARMV8_6): New macro.
293
142861df
JB		 2942019-11-07 Jan Beulich <jbeulich@suse.com>
295
296 * i386-dis.c (prefix_table): Add mcommit.
297 (rm_table): Add rdpru.
298 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
299 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
300 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
301 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
302 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
303 * i386-opc.tbl (mcommit, rdpru): New.
304 * i386-init.h, i386-tbl.h: Re-generate.
305
081e283f
JB		 3062019-11-07 Jan Beulich <jbeulich@suse.com>
307
308 * i386-dis.c (OP_Mwait): Drop local variable "names", use
309 "names32" instead.
310 (OP_Monitor): Drop local variable "op1_names", re-purpose
311 "names" for it instead, and replace former "names" uses by
312 "names32" ones.
313
c050c89a
JB		 3142019-11-07 Jan Beulich <jbeulich@suse.com>
315
316 PR/gas 25167
317 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
318 operand-less forms.
319 * opcodes/i386-tbl.h: Re-generate.
320
7abb8d81
JB		 3212019-11-05 Jan Beulich <jbeulich@suse.com>
322
323 * i386-dis.c (OP_Mwaitx): Delete.
324 (prefix_table): Use OP_Mwait for mwaitx entry.
325 (OP_Mwait): Also handle mwaitx.
326
267b8516
JB		 3272019-11-05 Jan Beulich <jbeulich@suse.com>
328
329 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
330 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
331 (prefix_table): Add respective entries.
332 (rm_table): Link to those entries.
333
f8687e93
JB		 3342019-11-05 Jan Beulich <jbeulich@suse.com>
335
336 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
337 (REG_0F1C_P_0_MOD_0): ... this.
338 (REG_0F1E_MOD_3): Rename to ...
339 (REG_0F1E_P_1_MOD_3): ... this.
340 (RM_0F01_REG_5): Rename to ...
341 (RM_0F01_REG_5_MOD_3): ... this.
342 (RM_0F01_REG_7): Rename to ...
343 (RM_0F01_REG_7_MOD_3): ... this.
344 (RM_0F1E_MOD_3_REG_7): Rename to ...
345 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
346 (RM_0FAE_REG_6): Rename to ...
347 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
348 (RM_0FAE_REG_7): Rename to ...
349 (RM_0FAE_REG_7_MOD_3): ... this.
350 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
351 (PREFIX_0F01_REG_5_MOD_0): ... this.
352 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
353 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
354 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
355 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
356 (PREFIX_0FAE_REG_0): Rename to ...
357 (PREFIX_0FAE_REG_0_MOD_3): ... this.
358 (PREFIX_0FAE_REG_1): Rename to ...
359 (PREFIX_0FAE_REG_1_MOD_3): ... this.
360 (PREFIX_0FAE_REG_2): Rename to ...
361 (PREFIX_0FAE_REG_2_MOD_3): ... this.
362 (PREFIX_0FAE_REG_3): Rename to ...
363 (PREFIX_0FAE_REG_3_MOD_3): ... this.
364 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
365 (PREFIX_0FAE_REG_4_MOD_0): ... this.
366 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
367 (PREFIX_0FAE_REG_4_MOD_3): ... this.
368 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
369 (PREFIX_0FAE_REG_5_MOD_0): ... this.
370 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
371 (PREFIX_0FAE_REG_5_MOD_3): ... this.
372 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
373 (PREFIX_0FAE_REG_6_MOD_0): ... this.
374 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
375 (PREFIX_0FAE_REG_6_MOD_3): ... this.
376 (PREFIX_0FAE_REG_7): Rename to ...
377 (PREFIX_0FAE_REG_7_MOD_0): ... this.
378 (PREFIX_MOD_0_0FC3): Rename to ...
379 (PREFIX_0FC3_MOD_0): ... this.
380 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
381 (PREFIX_0FC7_REG_6_MOD_0): ... this.
382 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
383 (PREFIX_0FC7_REG_6_MOD_3): ... this.
384 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
385 (PREFIX_0FC7_REG_7_MOD_3): ... this.
386 (reg_table, prefix_table, mod_table, rm_table): Adjust
387 accordingly.
388
5103274f
NC		 3892019-11-04 Nick Clifton <nickc@redhat.com>
390
391 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
392 of a v850 system register. Move the v850_sreg_names array into
393 this function.
394 (get_v850_reg_name): Likewise for ordinary register names.
395 (get_v850_vreg_name): Likewise for vector register names.
396 (get_v850_cc_name): Likewise for condition codes.
397 * get_v850_float_cc_name): Likewise for floating point condition
398 codes.
399 (get_v850_cacheop_name): Likewise for cache-ops.
400 (get_v850_prefop_name): Likewise for pref-ops.
401 (disassemble): Use the new accessor functions.
402
1820262b
DB		 4032019-10-30 Delia Burduv <delia.burduv@arm.com>
404
405 * aarch64-opc.c (print_immediate_offset_address): Don't print the
406 immediate for the writeback form of ldraa/ldrab if it is 0.
407 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
408 * aarch64-opc-2.c: Regenerated.
409
3cc17af5
JB		 4102019-10-30 Jan Beulich <jbeulich@suse.com>
411
412 * i386-gen.c (operand_type_shorthands): Delete.
413 (operand_type_init): Expand previous shorthands.
414 (set_bitfield_from_shorthand): Rename back to ...
415 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
416 of operand_type_init[].
417 (set_bitfield): Adjust call to the above function.
418 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
419 RegXMM, RegYMM, RegZMM): Define.
420 * i386-reg.tbl: Expand prior shorthands.
421
a2cebd03
JB		 4222019-10-30 Jan Beulich <jbeulich@suse.com>
423
424 * i386-gen.c (output_i386_opcode): Change order of fields
425 emitted to output.
426 * i386-opc.h (struct insn_template): Move operands field.
427 Convert extension_opcode field to unsigned short.
428 * i386-tbl.h: Re-generate.
429
507916b8
JB		 4302019-10-30 Jan Beulich <jbeulich@suse.com>
431
432 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
433 of W.
434 * i386-opc.h (W): Extend comment.
435 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
436 general purpose variants not allowing for byte operands.
437 * i386-tbl.h: Re-generate.
438
efea62b4
NC		 4392019-10-29 Nick Clifton <nickc@redhat.com>
440
441 * tic30-dis.c (print_branch): Correct size of operand array.
442
9adb2591
NC		 4432019-10-29 Nick Clifton <nickc@redhat.com>
444
445 * d30v-dis.c (print_insn): Check that operand index is valid
446 before attempting to access the operands array.
447
993a00a9
NC		 4482019-10-29 Nick Clifton <nickc@redhat.com>
449
450 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
451 locating the bit to be tested.
452
66a66a17
NC		 4532019-10-29 Nick Clifton <nickc@redhat.com>
454
455 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
456 values.
457 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
458 (print_insn_s12z): Check for illegal size values.
459
1ee3542c
NC		 4602019-10-28 Nick Clifton <nickc@redhat.com>
461
462 * csky-dis.c (csky_chars_to_number): Check for a negative
463 count. Use an unsigned integer to construct the return value.
464
bbf9a0b5
NC		 4652019-10-28 Nick Clifton <nickc@redhat.com>
466
467 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
468 operand buffer. Set value to 15 not 13.
469 (get_register_operand): Use OPERAND_BUFFER_LEN.
470 (get_indirect_operand): Likewise.
471 (print_two_operand): Likewise.
472 (print_three_operand): Likewise.
473 (print_oar_insn): Likewise.
474
d1e304bc
NC		 4752019-10-28 Nick Clifton <nickc@redhat.com>
476
477 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
478 (bit_extract_simple): Likewise.
479 (bit_copy): Likewise.
480 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
481 index_offset array are not accessed.
482
dee33451
NC		 4832019-10-28 Nick Clifton <nickc@redhat.com>
484
485 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
486 operand.
487
27cee81d
NC		 4882019-10-25 Nick Clifton <nickc@redhat.com>
489
490 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
491 access to opcodes.op array element.
492
de6d8dc2
NC		 4932019-10-23 Nick Clifton <nickc@redhat.com>
494
495 * rx-dis.c (get_register_name): Fix spelling typo in error
496 message.
497 (get_condition_name, get_flag_name, get_double_register_name)
498 (get_double_register_high_name, get_double_register_low_name)
499 (get_double_control_register_name, get_double_condition_name)
500 (get_opsize_name, get_size_name): Likewise.
501
6207ed28
NC		 5022019-10-22 Nick Clifton <nickc@redhat.com>
503
504 * rx-dis.c (get_size_name): New function. Provides safe
505 access to name array.
506 (get_opsize_name): Likewise.
507 (print_insn_rx): Use the accessor functions.
508
12234dfd
NC		 5092019-10-16 Nick Clifton <nickc@redhat.com>
510
511 * rx-dis.c (get_register_name): New function. Provides safe
512 access to name array.
513 (get_condition_name, get_flag_name, get_double_register_name)
514 (get_double_register_high_name, get_double_register_low_name)
515 (get_double_control_register_name, get_double_condition_name):
516 Likewise.
517 (print_insn_rx): Use the accessor functions.
518
1d378749
NC		 5192019-10-09 Nick Clifton <nickc@redhat.com>
520
521 PR 25041
522 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
523 instructions.
524
d241b910
JB		 5252019-10-07 Jan Beulich <jbeulich@suse.com>
526
527 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
528 (cmpsd): Likewise. Move EsSeg to other operand.
529 * opcodes/i386-tbl.h: Re-generate.
530
f5c5b7c1
AM		 5312019-09-23 Alan Modra <amodra@gmail.com>
532
533 * m68k-dis.c: Include cpu-m68k.h
534
7beeaeb8
AM		 5352019-09-23 Alan Modra <amodra@gmail.com>
536
537 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
538 "elf/mips.h" earlier.
539
3f9aad11
JB		 5402018-09-20 Jan Beulich <jbeulich@suse.com>
541
542 PR gas/25012
543 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
544 with SReg operand.
545 * i386-tbl.h: Re-generate.
546
fd361982
AM		 5472019-09-18 Alan Modra <amodra@gmail.com>
548
549 * arc-ext.c: Update throughout for bfd section macro changes.
550
e0b2a78c
SM		 5512019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
552
553 * Makefile.in: Re-generate.
554 * configure: Re-generate.
555
7e9ad3a3
JW		 5562019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
557
558 * riscv-opc.c (riscv_opcodes): Change subset field
559 to insn_class field for all instructions.
560 (riscv_insn_types): Likewise.
561
bb695960
PB		 5622019-09-16 Phil Blundell <pb@pbcl.net>
563
564 * configure: Regenerated.
565
8063ab7e
MV		 5662019-09-10 Miod Vallat <miod@online.fr>
567
568 PR 24982
569 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
570
60391a25
PB		 5712019-09-09 Phil Blundell <pb@pbcl.net>
572
573 binutils 2.33 branch created.
574
f44b758d
NC		 5752019-09-03 Nick Clifton <nickc@redhat.com>
576
577 PR 24961
578 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
579 greater than zero before indexing via (bufcnt -1).
580
1e4b5e7d
NC		 5812019-09-03 Nick Clifton <nickc@redhat.com>
582
583 PR 24958
584 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
585 (MAX_SPEC_REG_NAME_LEN): Define.
586 (struct mmix_dis_info): Use defined constants for array lengths.
587 (get_reg_name): New function.
588 (get_sprec_reg_name): New function.
589 (print_insn_mmix): Use new functions.
590
c4a23bf8
SP		 5912019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
592
593 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
594 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
595 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
596
a051e2f3
KT		 5972019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
598
599 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
600 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
601 (aarch64_sys_reg_supported_p): Update checks for the above.
602
08132bdd
SP		 6032019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
604
605 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
606 cases MVE_SQRSHRL and MVE_UQRSHLL.
607 (print_insn_mve): Add case for specifier 'k' to check
608 specific bit of the instruction.
609
d88bdcb4
PA		 6102019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
611
612 PR 24854
613 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
614 encountering an unknown machine type.
615 (print_insn_arc): Handle arc_insn_length returning 0. In error
616 cases return -1 rather than calling abort.
617
bc750500
JB		 6182019-08-07 Jan Beulich <jbeulich@suse.com>
619
620 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
621 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
622 IgnoreSize.
623 * i386-tbl.h: Re-generate.
624
23d188c7
BW		 6252019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
626
627 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
628 instructions.
629
c0d6f62f
JW		 6302019-07-30 Mel Chen <mel.chen@sifive.com>
631
632 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
633 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
634
635 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
636 fscsr.
637
0f3f7167
CZ		 6382019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
639
640 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
641 and MPY class instructions.
642 (parse_option): Add nps400 option.
643 (print_arc_disassembler_options): Add nps400 info.
644
7e126ba3
CZ		 6452019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
646
647 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
648 (bspop): Likewise.
649 (modapp): Likewise.
650 * arc-opc.c (RAD_CHK): Add.
651 * arc-tbl.h: Regenerate.
652
a028026d
KT		 6532019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
654
655 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
656 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
657
ac79ff9e
NC		 6582019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
659
660 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
661 instructions as UNPREDICTABLE.
662
231097b0
JM		 6632019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
664
665 * bpf-desc.c: Regenerated.
666
1d942ae9
JB		 6672019-07-17 Jan Beulich <jbeulich@suse.com>
668
669 * i386-gen.c (static_assert): Define.
670 (main): Use it.
671 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
672 (Opcode_Modifier_Num): ... this.
673 (Mem): Delete.
674
dfd69174
JB		 6752019-07-16 Jan Beulich <jbeulich@suse.com>
676
677 * i386-gen.c (operand_types): Move RegMem ...
678 (opcode_modifiers): ... here.
679 * i386-opc.h (RegMem): Move to opcode modifer enum.
680 (union i386_operand_type): Move regmem field ...
681 (struct i386_opcode_modifier): ... here.
682 * i386-opc.tbl (RegMem): Define.
683 (mov, movq): Move RegMem on segment, control, debug, and test
684 register flavors.
685 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
686 to non-SSE2AVX flavor.
687 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
688 Move RegMem on register only flavors. Drop IgnoreSize from
689 legacy encoding flavors.
690 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
691 flavors.
692 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
693 register only flavors.
694 (vmovd): Move RegMem and drop IgnoreSize on register only
695 flavor. Change opcode and operand order to store form.
696 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
697
21df382b
JB		 6982019-07-16 Jan Beulich <jbeulich@suse.com>
699
700 * i386-gen.c (operand_type_init, operand_types): Replace SReg
701 entries.
702 * i386-opc.h (SReg2, SReg3): Replace by ...
703 (SReg): ... this.
704 (union i386_operand_type): Replace sreg fields.
705 * i386-opc.tbl (mov, ): Use SReg.
706 (push, pop): Likewies. Drop i386 and x86-64 specific segment
707 register flavors.
708 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
709 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
710
3719fd55
JM		 7112019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
712
713 * bpf-desc.c: Regenerate.
714 * bpf-opc.c: Likewise.
715 * bpf-opc.h: Likewise.
716
92434a14
JM		 7172019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
718
719 * bpf-desc.c: Regenerate.
720 * bpf-opc.c: Likewise.
721
43dd7626
HPN		 7222019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
723
724 * arm-dis.c (print_insn_coprocessor): Rename index to
725 index_operand.
726
98602811
JW		 7272019-07-05 Kito Cheng <kito.cheng@sifive.com>
728
729 * riscv-opc.c (riscv_insn_types): Add r4 type.
730
731 * riscv-opc.c (riscv_insn_types): Add b and j type.
732
733 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
734 format for sb type and correct s type.
735
01c1ee4a
RS		 7362019-07-02 Richard Sandiford <richard.sandiford@arm.com>
737
738 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
739 SVE FMOV alias of FCPY.
740
83adff69
RS		 7412019-07-02 Richard Sandiford <richard.sandiford@arm.com>
742
743 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
744 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
745
89418844
RS		 7462019-07-02 Richard Sandiford <richard.sandiford@arm.com>
747
748 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
749 registers in an instruction prefixed by MOVPRFX.
750
41be57ca
MM		 7512019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
752
753 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
754 sve_size_13 icode to account for variant behaviour of
755 pmull{t,b}.
756 * aarch64-dis-2.c: Regenerate.
757 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
758 sve_size_13 icode to account for variant behaviour of
759 pmull{t,b}.
760 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
761 (OP_SVE_VVV_Q_D): Add new qualifier.
762 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
763 (struct aarch64_opcode): Split pmull{t,b} into those requiring
764 AES and those not.
765
9d3bf266
JB		 7662019-07-01 Jan Beulich <jbeulich@suse.com>
767
768 * opcodes/i386-gen.c (operand_type_init): Remove
769 OPERAND_TYPE_VEC_IMM4 entry.
770 (operand_types): Remove Vec_Imm4.
771 * opcodes/i386-opc.h (Vec_Imm4): Delete.
772 (union i386_operand_type): Remove vec_imm4.
773 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
774 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
775
c3949f43
JB		 7762019-07-01 Jan Beulich <jbeulich@suse.com>
777
778 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
779 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
780 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
781 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
782 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
783 monitorx, mwaitx): Drop ImmExt from operand-less forms.
784 * i386-tbl.h: Re-generate.
785
5641ec01
JB		 7862019-07-01 Jan Beulich <jbeulich@suse.com>
787
788 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
789 register operands.
790 * i386-tbl.h: Re-generate.
791
79dec6b7
JB		 7922019-07-01 Jan Beulich <jbeulich@suse.com>
793
794 * i386-opc.tbl (C): New.
795 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
796 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
797 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
798 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
799 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
800 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
801 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
802 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
803 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
804 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
805 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
806 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
807 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
808 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
809 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
810 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
811 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
812 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
813 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
814 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
815 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
816 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
817 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
818 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
819 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
820 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
821 flavors.
822 * i386-tbl.h: Re-generate.
823
a0a1771e
JB		 8242019-07-01 Jan Beulich <jbeulich@suse.com>
825
826 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
827 register operands.
828 * i386-tbl.h: Re-generate.
829
cd546e7b
JB		 8302019-07-01 Jan Beulich <jbeulich@suse.com>
831
832 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
833 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
834 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
835 * i386-tbl.h: Re-generate.
836
e3bba3fc
JB		 8372019-07-01 Jan Beulich <jbeulich@suse.com>
838
839 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
840 Disp8MemShift from register only templates.
841 * i386-tbl.h: Re-generate.
842
36cc073e
JB		 8432019-07-01 Jan Beulich <jbeulich@suse.com>
844
845 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
846 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
847 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
848 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
849 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
850 EVEX_W_0F11_P_3_M_1): Delete.
851 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
852 EVEX_W_0F11_P_3): New.
853 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
854 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
855 MOD_EVEX_0F11_PREFIX_3 table entries.
856 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
857 PREFIX_EVEX_0F11 table entries.
858 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
859 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
860 EVEX_W_0F11_P_3_M_{0,1} table entries.
861
219920a7
JB		 8622019-07-01 Jan Beulich <jbeulich@suse.com>
863
864 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
865 Delete.
866
e395f487
L		 8672019-06-27 H.J. Lu <hongjiu.lu@intel.com>
868
869 PR binutils/24719
870 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
871 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
872 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
873 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
874 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
875 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
876 EVEX_LEN_0F38C7_R_6_P_2_W_1.
877 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
878 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
879 PREFIX_EVEX_0F38C6_REG_6 entries.
880 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
881 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
882 EVEX_W_0F38C7_R_6_P_2 entries.
883 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
884 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
885 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
886 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
887 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
888 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
889 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
890
2b7bcc87
JB		 8912019-06-27 Jan Beulich <jbeulich@suse.com>
892
893 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
894 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
895 VEX_LEN_0F2D_P_3): Delete.
896 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
897 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
898 (prefix_table): ... here.
899
c1dc7af5
JB		 9002019-06-27 Jan Beulich <jbeulich@suse.com>
901
902 * i386-dis.c (Iq): Delete.
903 (Id): New.
904 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
905 TBM insns.
906 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
907 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
908 (OP_E_memory): Also honor needindex when deciding whether an
909 address size prefix needs printing.
910 (OP_I): Remove handling of q_mode. Add handling of d_mode.
911
d7560e2d
JW		 9122019-06-26 Jim Wilson <jimw@sifive.com>
913
914 PR binutils/24739
915 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
916 Set info->display_endian to info->endian_code.
917
2c703856
JB		 9182019-06-25 Jan Beulich <jbeulich@suse.com>
919
920 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
921 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
922 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
923 OPERAND_TYPE_ACC64 entries.
924 * i386-init.h: Re-generate.
925
54fbadc0
JB		 9262019-06-25 Jan Beulich <jbeulich@suse.com>
927
928 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
929 Delete.
930 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
931 of dqa_mode.
932 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
933 entries here.
934 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
935 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
936
a280ab8e
JB		 9372019-06-25 Jan Beulich <jbeulich@suse.com>
938
939 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
940 variables.
941
e1a1babd
JB		 9422019-06-25 Jan Beulich <jbeulich@suse.com>
943
944 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
945 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
946 movnti.
d7560e2d 947 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 948 * i386-tbl.h: Re-generate.
949
b8364fa7
JB		 9502019-06-25 Jan Beulich <jbeulich@suse.com>
951
952 * i386-opc.tbl (and): Mark Imm8S form for optimization.
953 * i386-tbl.h: Re-generate.
954
ad692897
L		 9552019-06-21 H.J. Lu <hongjiu.lu@intel.com>
956
957 * i386-dis-evex.h: Break into ...
958 * i386-dis-evex-len.h: New file.
959 * i386-dis-evex-mod.h: Likewise.
960 * i386-dis-evex-prefix.h: Likewise.
961 * i386-dis-evex-reg.h: Likewise.
962 * i386-dis-evex-w.h: Likewise.
963 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
964 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
965 i386-dis-evex-mod.h.
966
f0a6222e
L		 9672019-06-19 H.J. Lu <hongjiu.lu@intel.com>
968
969 PR binutils/24700
970 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
971 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
972 EVEX_W_0F385B_P_2.
973 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
974 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
975 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
976 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
977 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
978 EVEX_LEN_0F385B_P_2_W_1.
979 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
980 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
981 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
982 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
983 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
984 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
985 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
986 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
987 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
988 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
989
6e1c90b7
L		 9902019-06-17 H.J. Lu <hongjiu.lu@intel.com>
991
992 PR binutils/24691
993 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
994 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
995 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
996 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
997 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
998 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
999 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1000 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1001 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1002 EVEX_LEN_0F3A43_P_2_W_1.
1003 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1004 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1005 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1006 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1007 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1008 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1009 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1010 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1011 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1012 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1013 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1014 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1015
bcc5a6eb
NC		 10162019-06-14 Nick Clifton <nickc@redhat.com>
1017
1018 * po/fr.po; Updated French translation.
1019
e4c4ac46
SH		 10202019-06-13 Stafford Horne <shorne@gmail.com>
1021
1022 * or1k-asm.c: Regenerated.
1023 * or1k-desc.c: Regenerated.
1024 * or1k-desc.h: Regenerated.
1025 * or1k-dis.c: Regenerated.
1026 * or1k-ibld.c: Regenerated.
1027 * or1k-opc.c: Regenerated.
1028 * or1k-opc.h: Regenerated.
1029 * or1k-opinst.c: Regenerated.
1030
a0e44ef5
PB		 10312019-06-12 Peter Bergner <bergner@linux.ibm.com>
1032
1033 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1034
12efd68d
L		 10352019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1036
1037 PR binutils/24633
1038 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1039 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1040 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1041 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1042 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1043 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1044 EVEX_LEN_0F3A1B_P_2_W_1.
1045 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1046 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1047 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1048 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1049 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1050 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1051 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1052 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1053
63c6fc6c
L		 10542019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1055
1056 PR binutils/24626
1057 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1058 EVEX.vvvv when disassembling VEX and EVEX instructions.
1059 (OP_VEX): Set vex.register_specifier to 0 after readding
1060 vex.register_specifier.
1061 (OP_Vex_2src_1): Likewise.
1062 (OP_Vex_2src_2): Likewise.
1063 (OP_LWP_E): Likewise.
1064 (OP_EX_Vex): Don't check vex.register_specifier.
1065 (OP_XMM_Vex): Likewise.
1066
9186c494
L		 10672019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1068 Lili Cui <lili.cui@intel.com>
1069
1070 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1071 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1072 instructions.
1073 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1074 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1075 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1076 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1077 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1078 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1079 * i386-init.h: Regenerated.
1080 * i386-tbl.h: Likewise.
1081
5d79adc4
L		 10822019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1083 Lili Cui <lili.cui@intel.com>
1084
1085 * doc/c-i386.texi: Document enqcmd.
1086 * testsuite/gas/i386/enqcmd-intel.d: New file.
1087 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1088 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1089 * testsuite/gas/i386/enqcmd.d: Likewise.
1090 * testsuite/gas/i386/enqcmd.s: Likewise.
1091 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1092 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1093 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1094 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1095 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1096 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1097 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1098 and x86-64-enqcmd.
1099
a9d96ab9
AH		 11002019-06-04 Alan Hayward <alan.hayward@arm.com>
1101
1102 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1103
4f6d070a
AM		 11042019-06-03 Alan Modra <amodra@gmail.com>
1105
1106 * ppc-dis.c (prefix_opcd_indices): Correct size.
1107
a2f4b66c
L		 11082019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1109
1110 PR gas/24625
1111 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1112 Disp8ShiftVL.
1113 * i386-tbl.h: Regenerated.
1114
405b5bd8
AM		 11152019-05-24 Alan Modra <amodra@gmail.com>
1116
1117 * po/POTFILES.in: Regenerate.
1118
8acf1435
PB		 11192019-05-24 Peter Bergner <bergner@linux.ibm.com>
1120 Alan Modra <amodra@gmail.com>
1121
1122 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1123 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1124 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1125 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1126 XTOP>): Define and add entries.
1127 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1128 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1129 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1130 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1131
dd7efa79
PB		 11322019-05-24 Peter Bergner <bergner@linux.ibm.com>
1133 Alan Modra <amodra@gmail.com>
1134
1135 * ppc-dis.c (ppc_opts): Add "future" entry.
1136 (PREFIX_OPCD_SEGS): Define.
1137 (prefix_opcd_indices): New array.
1138 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1139 (lookup_prefix): New function.
1140 (print_insn_powerpc): Handle 64-bit prefix instructions.
1141 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1142 (PMRR, POWERXX): Define.
1143 (prefix_opcodes): New instruction table.
1144 (prefix_num_opcodes): New constant.
1145
79472b45
JM		 11462019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1147
1148 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1149 * configure: Regenerated.
1150 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1151 and cpu/bpf.opc.
1152 (HFILES): Add bpf-desc.h and bpf-opc.h.
1153 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1154 bpf-ibld.c and bpf-opc.c.
1155 (BPF_DEPS): Define.
1156 * Makefile.in: Regenerated.
1157 * disassemble.c (ARCH_bpf): Define.
1158 (disassembler): Add case for bfd_arch_bpf.
1159 (disassemble_init_for_target): Likewise.
1160 (enum epbf_isa_attr): Define.
1161 * disassemble.h: extern print_insn_bpf.
1162 * bpf-asm.c: Generated.
1163 * bpf-opc.h: Likewise.
1164 * bpf-opc.c: Likewise.
1165 * bpf-ibld.c: Likewise.
1166 * bpf-dis.c: Likewise.
1167 * bpf-desc.h: Likewise.
1168 * bpf-desc.c: Likewise.
1169
ba6cd17f
SD		 11702019-05-21 Sudakshina Das <sudi.das@arm.com>
1171
1172 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1173 and VMSR with the new operands.
1174
e39c1607
SD		 11752019-05-21 Sudakshina Das <sudi.das@arm.com>
1176
1177 * arm-dis.c (enum mve_instructions): New enum
1178 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1179 and cneg.
1180 (mve_opcodes): New instructions as above.
1181 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1182 csneg and csel.
1183 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1184
23d00a41
SD		 11852019-05-21 Sudakshina Das <sudi.das@arm.com>
1186
1187 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1188 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1189 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1190 uqshl, urshrl and urshr.
1191 (is_mve_okay_in_it): Add new instructions to TRUE list.
1192 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1193 (print_insn_mve): Updated to accept new %j,
1194 %<bitfield>m and %<bitfield>n patterns.
1195
cd4797ee
FS		 11962019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1197
1198 * mips-opc.c (mips_builtin_opcodes): Change source register
1199 constraint for DAUI.
1200
999b073b
NC		 12012019-05-20 Nick Clifton <nickc@redhat.com>
1202
1203 * po/fr.po: Updated French translation.
1204
14b456f2
AV		 12052019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1206 Michael Collison <michael.collison@arm.com>
1207
1208 * arm-dis.c (thumb32_opcodes): Add new instructions.
1209 (enum mve_instructions): Likewise.
1210 (enum mve_undefined): Add new reasons.
1211 (is_mve_encoding_conflict): Handle new instructions.
1212 (is_mve_undefined): Likewise.
1213 (is_mve_unpredictable): Likewise.
1214 (print_mve_undefined): Likewise.
1215 (print_mve_size): Likewise.
1216
f49bb598
AV		 12172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1218 Michael Collison <michael.collison@arm.com>
1219
1220 * arm-dis.c (thumb32_opcodes): Add new instructions.
1221 (enum mve_instructions): Likewise.
1222 (is_mve_encoding_conflict): Handle new instructions.
1223 (is_mve_undefined): Likewise.
1224 (is_mve_unpredictable): Likewise.
1225 (print_mve_size): Likewise.
1226
56858bea
AV		 12272019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1228 Michael Collison <michael.collison@arm.com>
1229
1230 * arm-dis.c (thumb32_opcodes): Add new instructions.
1231 (enum mve_instructions): Likewise.
1232 (is_mve_encoding_conflict): Likewise.
1233 (is_mve_unpredictable): Likewise.
1234 (print_mve_size): Likewise.
1235
e523f101
AV		 12362019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1237 Michael Collison <michael.collison@arm.com>
1238
1239 * arm-dis.c (thumb32_opcodes): Add new instructions.
1240 (enum mve_instructions): Likewise.
1241 (is_mve_encoding_conflict): Handle new instructions.
1242 (is_mve_undefined): Likewise.
1243 (is_mve_unpredictable): Likewise.
1244 (print_mve_size): Likewise.
1245
66dcaa5d
AV		 12462019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1247 Michael Collison <michael.collison@arm.com>
1248
1249 * arm-dis.c (thumb32_opcodes): Add new instructions.
1250 (enum mve_instructions): Likewise.
1251 (is_mve_encoding_conflict): Handle new instructions.
1252 (is_mve_undefined): Likewise.
1253 (is_mve_unpredictable): Likewise.
1254 (print_mve_size): Likewise.
1255 (print_insn_mve): Likewise.
1256
d052b9b7
AV		 12572019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1258 Michael Collison <michael.collison@arm.com>
1259
1260 * arm-dis.c (thumb32_opcodes): Add new instructions.
1261 (print_insn_thumb32): Handle new instructions.
1262
ed63aa17
AV		 12632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1264 Michael Collison <michael.collison@arm.com>
1265
1266 * arm-dis.c (enum mve_instructions): Add new instructions.
1267 (enum mve_undefined): Add new reasons.
1268 (is_mve_encoding_conflict): Handle new instructions.
1269 (is_mve_undefined): Likewise.
1270 (is_mve_unpredictable): Likewise.
1271 (print_mve_undefined): Likewise.
1272 (print_mve_size): Likewise.
1273 (print_mve_shift_n): Likewise.
1274 (print_insn_mve): Likewise.
1275
897b9bbc
AV		 12762019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1277 Michael Collison <michael.collison@arm.com>
1278
1279 * arm-dis.c (enum mve_instructions): Add new instructions.
1280 (is_mve_encoding_conflict): Handle new instructions.
1281 (is_mve_unpredictable): Likewise.
1282 (print_mve_rotate): Likewise.
1283 (print_mve_size): Likewise.
1284 (print_insn_mve): Likewise.
1285
1c8f2df8
AV		 12862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1287 Michael Collison <michael.collison@arm.com>
1288
1289 * arm-dis.c (enum mve_instructions): Add new instructions.
1290 (is_mve_encoding_conflict): Handle new instructions.
1291 (is_mve_unpredictable): Likewise.
1292 (print_mve_size): Likewise.
1293 (print_insn_mve): Likewise.
1294
d3b63143
AV		 12952019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1296 Michael Collison <michael.collison@arm.com>
1297
1298 * arm-dis.c (enum mve_instructions): Add new instructions.
1299 (enum mve_undefined): Add new reasons.
1300 (is_mve_encoding_conflict): Handle new instructions.
1301 (is_mve_undefined): Likewise.
1302 (is_mve_unpredictable): Likewise.
1303 (print_mve_undefined): Likewise.
1304 (print_mve_size): Likewise.
1305 (print_insn_mve): Likewise.
1306
14925797
AV		 13072019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1308 Michael Collison <michael.collison@arm.com>
1309
1310 * arm-dis.c (enum mve_instructions): Add new instructions.
1311 (is_mve_encoding_conflict): Handle new instructions.
1312 (is_mve_undefined): Likewise.
1313 (is_mve_unpredictable): Likewise.
1314 (print_mve_size): Likewise.
1315 (print_insn_mve): Likewise.
1316
c507f10b
AV		 13172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1318 Michael Collison <michael.collison@arm.com>
1319
1320 * arm-dis.c (enum mve_instructions): Add new instructions.
1321 (enum mve_unpredictable): Add new reasons.
1322 (enum mve_undefined): Likewise.
1323 (is_mve_okay_in_it): Handle new isntructions.
1324 (is_mve_encoding_conflict): Likewise.
1325 (is_mve_undefined): Likewise.
1326 (is_mve_unpredictable): Likewise.
1327 (print_mve_vmov_index): Likewise.
1328 (print_simd_imm8): Likewise.
1329 (print_mve_undefined): Likewise.
1330 (print_mve_unpredictable): Likewise.
1331 (print_mve_size): Likewise.
1332 (print_insn_mve): Likewise.
1333
bf0b396d
AV		 13342019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1335 Michael Collison <michael.collison@arm.com>
1336
1337 * arm-dis.c (enum mve_instructions): Add new instructions.
1338 (enum mve_unpredictable): Add new reasons.
1339 (enum mve_undefined): Likewise.
1340 (is_mve_encoding_conflict): Handle new instructions.
1341 (is_mve_undefined): Likewise.
1342 (is_mve_unpredictable): Likewise.
1343 (print_mve_undefined): Likewise.
1344 (print_mve_unpredictable): Likewise.
1345 (print_mve_rounding_mode): Likewise.
1346 (print_mve_vcvt_size): Likewise.
1347 (print_mve_size): Likewise.
1348 (print_insn_mve): Likewise.
1349
ef1576a1
AV		 13502019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1351 Michael Collison <michael.collison@arm.com>
1352
1353 * arm-dis.c (enum mve_instructions): Add new instructions.
1354 (enum mve_unpredictable): Add new reasons.
1355 (enum mve_undefined): Likewise.
1356 (is_mve_undefined): Handle new instructions.
1357 (is_mve_unpredictable): Likewise.
1358 (print_mve_undefined): Likewise.
1359 (print_mve_unpredictable): Likewise.
1360 (print_mve_size): Likewise.
1361 (print_insn_mve): Likewise.
1362
aef6d006
AV		 13632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1364 Michael Collison <michael.collison@arm.com>
1365
1366 * arm-dis.c (enum mve_instructions): Add new instructions.
1367 (enum mve_undefined): Add new reasons.
1368 (insns): Add new instructions.
1369 (is_mve_encoding_conflict):
1370 (print_mve_vld_str_addr): New print function.
1371 (is_mve_undefined): Handle new instructions.
1372 (is_mve_unpredictable): Likewise.
1373 (print_mve_undefined): Likewise.
1374 (print_mve_size): Likewise.
1375 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1376 (print_insn_mve): Handle new operands.
1377
04d54ace
AV		 13782019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1379 Michael Collison <michael.collison@arm.com>
1380
1381 * arm-dis.c (enum mve_instructions): Add new instructions.
1382 (enum mve_unpredictable): Add new reasons.
1383 (is_mve_encoding_conflict): Handle new instructions.
1384 (is_mve_unpredictable): Likewise.
1385 (mve_opcodes): Add new instructions.
1386 (print_mve_unpredictable): Handle new reasons.
1387 (print_mve_register_blocks): New print function.
1388 (print_mve_size): Handle new instructions.
1389 (print_insn_mve): Likewise.
1390
9743db03
AV		 13912019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1392 Michael Collison <michael.collison@arm.com>
1393
1394 * arm-dis.c (enum mve_instructions): Add new instructions.
1395 (enum mve_unpredictable): Add new reasons.
1396 (enum mve_undefined): Likewise.
1397 (is_mve_encoding_conflict): Handle new instructions.
1398 (is_mve_undefined): Likewise.
1399 (is_mve_unpredictable): Likewise.
1400 (coprocessor_opcodes): Move NEON VDUP from here...
1401 (neon_opcodes): ... to here.
1402 (mve_opcodes): Add new instructions.
1403 (print_mve_undefined): Handle new reasons.
1404 (print_mve_unpredictable): Likewise.
1405 (print_mve_size): Handle new instructions.
1406 (print_insn_neon): Handle vdup.
1407 (print_insn_mve): Handle new operands.
1408
143275ea
AV		 14092019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1410 Michael Collison <michael.collison@arm.com>
1411
1412 * arm-dis.c (enum mve_instructions): Add new instructions.
1413 (enum mve_unpredictable): Add new values.
1414 (mve_opcodes): Add new instructions.
1415 (vec_condnames): New array with vector conditions.
1416 (mve_predicatenames): New array with predicate suffixes.
1417 (mve_vec_sizename): New array with vector sizes.
1418 (enum vpt_pred_state): New enum with vector predication states.
1419 (struct vpt_block): New struct type for vpt blocks.
1420 (vpt_block_state): Global struct to keep track of state.
1421 (mve_extract_pred_mask): New helper function.
1422 (num_instructions_vpt_block): Likewise.
1423 (mark_outside_vpt_block): Likewise.
1424 (mark_inside_vpt_block): Likewise.
1425 (invert_next_predicate_state): Likewise.
1426 (update_next_predicate_state): Likewise.
1427 (update_vpt_block_state): Likewise.
1428 (is_vpt_instruction): Likewise.
1429 (is_mve_encoding_conflict): Add entries for new instructions.
1430 (is_mve_unpredictable): Likewise.
1431 (print_mve_unpredictable): Handle new cases.
1432 (print_instruction_predicate): Likewise.
1433 (print_mve_size): New function.
1434 (print_vec_condition): New function.
1435 (print_insn_mve): Handle vpt blocks and new print operands.
1436
f08d8ce3
AV		 14372019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1438
1439 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1440 8, 14 and 15 for Armv8.1-M Mainline.
1441
73cd51e5
AV		 14422019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1443 Michael Collison <michael.collison@arm.com>
1444
1445 * arm-dis.c (enum mve_instructions): New enum.
1446 (enum mve_unpredictable): Likewise.
1447 (enum mve_undefined): Likewise.
1448 (struct mopcode32): New struct.
1449 (is_mve_okay_in_it): New function.
1450 (is_mve_architecture): Likewise.
1451 (arm_decode_field): Likewise.
1452 (arm_decode_field_multiple): Likewise.
1453 (is_mve_encoding_conflict): Likewise.
1454 (is_mve_undefined): Likewise.
1455 (is_mve_unpredictable): Likewise.
1456 (print_mve_undefined): Likewise.
1457 (print_mve_unpredictable): Likewise.
1458 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1459 (print_insn_mve): New function.
1460 (print_insn_thumb32): Handle MVE architecture.
1461 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1462
3076e594
NC		 14632019-05-10 Nick Clifton <nickc@redhat.com>
1464
1465 PR 24538
1466 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1467 end of the table prematurely.
1468
387e7624
FS		 14692019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1470
1471 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1472 macros for R6.
1473
0067be51
AM		 14742019-05-11 Alan Modra <amodra@gmail.com>
1475
1476 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1477 when -Mraw is in effect.
1478
42e6288f
MM		 14792019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1480
1481 * aarch64-dis-2.c: Regenerate.
1482 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1483 (OP_SVE_BBB): New variant set.
1484 (OP_SVE_DDDD): New variant set.
1485 (OP_SVE_HHH): New variant set.
1486 (OP_SVE_HHHU): New variant set.
1487 (OP_SVE_SSS): New variant set.
1488 (OP_SVE_SSSU): New variant set.
1489 (OP_SVE_SHH): New variant set.
1490 (OP_SVE_SBBU): New variant set.
1491 (OP_SVE_DSS): New variant set.
1492 (OP_SVE_DHHU): New variant set.
1493 (OP_SVE_VMV_HSD_BHS): New variant set.
1494 (OP_SVE_VVU_HSD_BHS): New variant set.
1495 (OP_SVE_VVVU_SD_BH): New variant set.
1496 (OP_SVE_VVVU_BHSD): New variant set.
1497 (OP_SVE_VVV_QHD_DBS): New variant set.
1498 (OP_SVE_VVV_HSD_BHS): New variant set.
1499 (OP_SVE_VVV_HSD_BHS2): New variant set.
1500 (OP_SVE_VVV_BHS_HSD): New variant set.
1501 (OP_SVE_VV_BHS_HSD): New variant set.
1502 (OP_SVE_VVV_SD): New variant set.
1503 (OP_SVE_VVU_BHS_HSD): New variant set.
1504 (OP_SVE_VZVV_SD): New variant set.
1505 (OP_SVE_VZVV_BH): New variant set.
1506 (OP_SVE_VZV_SD): New variant set.
1507 (aarch64_opcode_table): Add sve2 instructions.
1508
28ed815a
MM		 15092019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1510
1511 * aarch64-asm-2.c: Regenerated.
1512 * aarch64-dis-2.c: Regenerated.
1513 * aarch64-opc-2.c: Regenerated.
1514 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1515 for SVE_SHLIMM_UNPRED_22.
1516 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1517 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1518 operand.
1519
fd1dc4a0
MM		 15202019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1521
1522 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1523 sve_size_tsz_bhs iclass encode.
1524 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1525 sve_size_tsz_bhs iclass decode.
1526
31e36ab3
MM		 15272019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1528
1529 * aarch64-asm-2.c: Regenerated.
1530 * aarch64-dis-2.c: Regenerated.
1531 * aarch64-opc-2.c: Regenerated.
1532 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1533 for SVE_Zm4_11_INDEX.
1534 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1535 (fields): Handle SVE_i2h field.
1536 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1537 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1538
1be5f94f
MM		 15392019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1540
1541 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1542 sve_shift_tsz_bhsd iclass encode.
1543 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1544 sve_shift_tsz_bhsd iclass decode.
1545
3c17238b
MM		 15462019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1547
1548 * aarch64-asm-2.c: Regenerated.
1549 * aarch64-dis-2.c: Regenerated.
1550 * aarch64-opc-2.c: Regenerated.
1551 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1552 (aarch64_encode_variant_using_iclass): Handle
1553 sve_shift_tsz_hsd iclass encode.
1554 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1555 sve_shift_tsz_hsd iclass decode.
1556 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1557 for SVE_SHRIMM_UNPRED_22.
1558 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1559 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1560 operand.
1561
cd50a87a
MM		 15622019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1563
1564 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1565 sve_size_013 iclass encode.
1566 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1567 sve_size_013 iclass decode.
1568
3c705960
MM		 15692019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1570
1571 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1572 sve_size_bh iclass encode.
1573 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1574 sve_size_bh iclass decode.
1575
0a57e14f
MM		 15762019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1577
1578 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1579 sve_size_sd2 iclass encode.
1580 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1581 sve_size_sd2 iclass decode.
1582 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1583 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1584
c469c864
MM		 15852019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1586
1587 * aarch64-asm-2.c: Regenerated.
1588 * aarch64-dis-2.c: Regenerated.
1589 * aarch64-opc-2.c: Regenerated.
1590 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1591 for SVE_ADDR_ZX.
1592 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1593 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1594
116adc27
MM		 15952019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1596
1597 * aarch64-asm-2.c: Regenerated.
1598 * aarch64-dis-2.c: Regenerated.
1599 * aarch64-opc-2.c: Regenerated.
1600 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1601 for SVE_Zm3_11_INDEX.
1602 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1603 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1604 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1605 fields.
1606 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1607
3bd82c86
MM		 16082019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1609
1610 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1611 sve_size_hsd2 iclass encode.
1612 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1613 sve_size_hsd2 iclass decode.
1614 * aarch64-opc.c (fields): Handle SVE_size field.
1615 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1616
adccc507
MM		 16172019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1618
1619 * aarch64-asm-2.c: Regenerated.
1620 * aarch64-dis-2.c: Regenerated.
1621 * aarch64-opc-2.c: Regenerated.
1622 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1623 for SVE_IMM_ROT3.
1624 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1625 (fields): Handle SVE_rot3 field.
1626 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1627 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1628
5cd99750
MM		 16292019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1630
1631 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1632 instructions.
1633
7ce2460a
MM		 16342019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1635
1636 * aarch64-tbl.h
1637 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1638 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1639 aarch64_feature_sve2bitperm): New feature sets.
1640 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1641 for feature set addresses.
1642 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1643 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1644
41cee089
FS		 16452019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1646 Faraz Shahbazker <fshahbazker@wavecomp.com>
1647
1648 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1649 argument and set ASE_EVA_R6 appropriately.
1650 (set_default_mips_dis_options): Pass ISA to above.
1651 (parse_mips_dis_option): Likewise.
1652 * mips-opc.c (EVAR6): New macro.
1653 (mips_builtin_opcodes): Add llwpe, scwpe.
1654
b83b4b13
SD		 16552019-05-01 Sudakshina Das <sudi.das@arm.com>
1656
1657 * aarch64-asm-2.c: Regenerated.
1658 * aarch64-dis-2.c: Regenerated.
1659 * aarch64-opc-2.c: Regenerated.
1660 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1661 AARCH64_OPND_TME_UIMM16.
1662 (aarch64_print_operand): Likewise.
1663 * aarch64-tbl.h (QL_IMM_NIL): New.
1664 (TME): New.
1665 (_TME_INSN): New.
1666 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1667
4a90ce95
JD		 16682019-04-29 John Darrington <john@darrington.wattle.id.au>
1669
1670 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1671
a45328b9
AB		 16722019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1673 Faraz Shahbazker <fshahbazker@wavecomp.com>
1674
1675 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1676
d10be0cb
JD		 16772019-04-24 John Darrington <john@darrington.wattle.id.au>
1678
1679 * s12z-opc.h: Add extern "C" bracketing to help
1680 users who wish to use this interface in c++ code.
1681
a679f24e
JD		 16822019-04-24 John Darrington <john@darrington.wattle.id.au>
1683
1684 * s12z-opc.c (bm_decode): Handle bit map operations with the
1685 "reserved0" mode.
1686
32c36c3c
AV		 16872019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1688
1689 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1690 specifier. Add entries for VLDR and VSTR of system registers.
1691 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1692 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1693 of %J and %K format specifier.
1694
efd6b359
AV		 16952019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1696
1697 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1698 Add new entries for VSCCLRM instruction.
1699 (print_insn_coprocessor): Handle new %C format control code.
1700
6b0dd094
AV		 17012019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1702
1703 * arm-dis.c (enum isa): New enum.
1704 (struct sopcode32): New structure.
1705 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1706 set isa field of all current entries to ANY.
1707 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1708 Only match an entry if its isa field allows the current mode.
1709
4b5a202f
AV		 17102019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1711
1712 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1713 CLRM.
1714 (print_insn_thumb32): Add logic to print %n CLRM register list.
1715
60f993ce
AV		 17162019-04-15 Sudakshina Das <sudi.das@arm.com>
1717
1718 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1719 and %Q patterns.
1720
f6b2b12d
AV		 17212019-04-15 Sudakshina Das <sudi.das@arm.com>
1722
1723 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1724 (print_insn_thumb32): Edit the switch case for %Z.
1725
1889da70
AV		 17262019-04-15 Sudakshina Das <sudi.das@arm.com>
1727
1728 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1729
65d1bc05
AV		 17302019-04-15 Sudakshina Das <sudi.das@arm.com>
1731
1732 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1733
1caf72a5
AV		 17342019-04-15 Sudakshina Das <sudi.das@arm.com>
1735
1736 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1737
f1c7f421
AV		 17382019-04-15 Sudakshina Das <sudi.das@arm.com>
1739
1740 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1741 Arm register with r13 and r15 unpredictable.
1742 (thumb32_opcodes): New instructions for bfx and bflx.
1743
4389b29a
AV		 17442019-04-15 Sudakshina Das <sudi.das@arm.com>
1745
1746 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1747
e5d6e09e
AV		 17482019-04-15 Sudakshina Das <sudi.das@arm.com>
1749
1750 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1751
e12437dc
AV		 17522019-04-15 Sudakshina Das <sudi.das@arm.com>
1753
1754 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1755
031254f2
AV		 17562019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1757
1758 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1759
e5a557ac
JD		 17602019-04-12 John Darrington <john@darrington.wattle.id.au>
1761
1762 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1763 "optr". ("operator" is a reserved word in c++).
1764
bd7ceb8d
SD		 17652019-04-11 Sudakshina Das <sudi.das@arm.com>
1766
1767 * aarch64-opc.c (aarch64_print_operand): Add case for
1768 AARCH64_OPND_Rt_SP.
1769 (verify_constraints): Likewise.
1770 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1771 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1772 to accept Rt|SP as first operand.
1773 (AARCH64_OPERANDS): Add new Rt_SP.
1774 * aarch64-asm-2.c: Regenerated.
1775 * aarch64-dis-2.c: Regenerated.
1776 * aarch64-opc-2.c: Regenerated.
1777
e54010f1
SD		 17782019-04-11 Sudakshina Das <sudi.das@arm.com>
1779
1780 * aarch64-asm-2.c: Regenerated.
1781 * aarch64-dis-2.c: Likewise.
1782 * aarch64-opc-2.c: Likewise.
1783 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1784
7e96e219
RS		 17852019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1786
1787 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1788
6f2791d5
L		 17892019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1790
1791 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1792 * i386-init.h: Regenerated.
1793
e392bad3
AM		 17942019-04-07 Alan Modra <amodra@gmail.com>
1795
1796 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1797 op_separator to control printing of spaces, comma and parens
1798 rather than need_comma, need_paren and spaces vars.
1799
dffaa15c
AM		 18002019-04-07 Alan Modra <amodra@gmail.com>
1801
1802 PR 24421
1803 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1804 (print_insn_neon, print_insn_arm): Likewise.
1805
d6aab7a1
XG		 18062019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1807
1808 * i386-dis-evex.h (evex_table): Updated to support BF16
1809 instructions.
1810 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1811 and EVEX_W_0F3872_P_3.
1812 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1813 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1814 * i386-opc.h (enum): Add CpuAVX512_BF16.
1815 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1816 * i386-opc.tbl: Add AVX512 BF16 instructions.
1817 * i386-init.h: Regenerated.
1818 * i386-tbl.h: Likewise.
1819
66e85460
AM		 18202019-04-05 Alan Modra <amodra@gmail.com>
1821
1822 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1823 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1824 to favour printing of "-" branch hint when using the "y" bit.
1825 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1826
c2b1c275
AM		 18272019-04-05 Alan Modra <amodra@gmail.com>
1828
1829 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1830 opcode until first operand is output.
1831
aae9718e
PB		 18322019-04-04 Peter Bergner <bergner@linux.ibm.com>
1833
1834 PR gas/24349
1835 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1836 (valid_bo_post_v2): Add support for 'at' branch hints.
1837 (insert_bo): Only error on branch on ctr.
1838 (get_bo_hint_mask): New function.
1839 (insert_boe): Add new 'branch_taken' formal argument. Add support
1840 for inserting 'at' branch hints.
1841 (extract_boe): Add new 'branch_taken' formal argument. Add support
1842 for extracting 'at' branch hints.
1843 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1844 (BOE): Delete operand.
1845 (BOM, BOP): New operands.
1846 (RM): Update value.
1847 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1848 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1849 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1850 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1851 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1852 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1853 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1854 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1855 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1856 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1857 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1858 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1859 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1860 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1861 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1862 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1863 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1864 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1865 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1866 bttarl+>: New extended mnemonics.
1867
96a86c01
AM		 18682019-03-28 Alan Modra <amodra@gmail.com>
1869
1870 PR 24390
1871 * ppc-opc.c (BTF): Define.
1872 (powerpc_opcodes): Use for mtfsb*.
1873 * ppc-dis.c (print_insn_powerpc): Print fields with both
1874 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1875
796d6298
TC		 18762019-03-25 Tamar Christina <tamar.christina@arm.com>
1877
1878 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1879 (mapping_symbol_for_insn): Implement new algorithm.
1880 (print_insn): Remove duplicate code.
1881
60df3720
TC		 18822019-03-25 Tamar Christina <tamar.christina@arm.com>
1883
1884 * aarch64-dis.c (print_insn_aarch64):
1885 Implement override.
1886
51457761
TC		 18872019-03-25 Tamar Christina <tamar.christina@arm.com>
1888
1889 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1890 order.
1891
53b2f36b
TC		 18922019-03-25 Tamar Christina <tamar.christina@arm.com>
1893
1894 * aarch64-dis.c (last_stop_offset): New.
1895 (print_insn_aarch64): Use stop_offset.
1896
89199bb5
L		 18972019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1898
1899 PR gas/24359
1900 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1901 CPU_ANY_AVX2_FLAGS.
1902 * i386-init.h: Regenerated.
1903
97ed31ae
L		 19042019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1905
1906 PR gas/24348
1907 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1908 vmovdqu16, vmovdqu32 and vmovdqu64.
1909 * i386-tbl.h: Regenerated.
1910
0919bfe9
AK		 19112019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1912
1913 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1914 from vstrszb, vstrszh, and vstrszf.
1915
19162019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1917
1918 * s390-opc.txt: Add instruction descriptions.
1919
21820ebe
JW		 19202019-02-08 Jim Wilson <jimw@sifive.com>
1921
1922 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1923 <bne>: Likewise.
1924
f7dd2fb2
TC		 19252019-02-07 Tamar Christina <tamar.christina@arm.com>
1926
1927 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1928
6456d318
TC		 19292019-02-07 Tamar Christina <tamar.christina@arm.com>
1930
1931 PR binutils/23212
1932 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1933 * aarch64-opc.c (verify_elem_sd): New.
1934 (fields): Add FLD_sz entr.
1935 * aarch64-tbl.h (_SIMD_INSN): New.
1936 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1937 fmulx scalar and vector by element isns.
1938
4a83b610
NC		 19392019-02-07 Nick Clifton <nickc@redhat.com>
1940
1941 * po/sv.po: Updated Swedish translation.
1942
fc60b8c8
AK		 19432019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1944
1945 * s390-mkopc.c (main): Accept arch13 as cpu string.
1946 * s390-opc.c: Add new instruction formats and instruction opcode
1947 masks.
1948 * s390-opc.txt: Add new arch13 instructions.
1949
e10620d3
TC		 19502019-01-25 Sudakshina Das <sudi.das@arm.com>
1951
1952 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1953 (aarch64_opcode): Change encoding for stg, stzg
1954 st2g and st2zg.
1955 * aarch64-asm-2.c: Regenerated.
1956 * aarch64-dis-2.c: Regenerated.
1957 * aarch64-opc-2.c: Regenerated.
1958
20a4ca55
SD		 19592019-01-25 Sudakshina Das <sudi.das@arm.com>
1960
1961 * aarch64-asm-2.c: Regenerated.
1962 * aarch64-dis-2.c: Likewise.
1963 * aarch64-opc-2.c: Likewise.
1964 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1965
550fd7bf
SD		 19662019-01-25 Sudakshina Das <sudi.das@arm.com>
1967 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1968
1969 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1970 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1971 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1972 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1973 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1974 case for ldstgv_indexed.
1975 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1976 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1977 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1978 * aarch64-asm-2.c: Regenerated.
1979 * aarch64-dis-2.c: Regenerated.
1980 * aarch64-opc-2.c: Regenerated.
1981
d9938630
NC		 19822019-01-23 Nick Clifton <nickc@redhat.com>
1983
1984 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1985
375cd423
NC		 19862019-01-21 Nick Clifton <nickc@redhat.com>
1987
1988 * po/de.po: Updated German translation.
1989 * po/uk.po: Updated Ukranian translation.
1990
57299f48
CX		 19912019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1992 * mips-dis.c (mips_arch_choices): Fix typo in
1993 gs464, gs464e and gs264e descriptors.
1994
f48dfe41
NC		 19952019-01-19 Nick Clifton <nickc@redhat.com>
1996
1997 * configure: Regenerate.
1998 * po/opcodes.pot: Regenerate.
1999
f974f26c
NC		 20002018-06-24 Nick Clifton <nickc@redhat.com>
2001
2002 2.32 branch created.
2003
39f286cd
JD		 20042019-01-09 John Darrington <john@darrington.wattle.id.au>
2005
448b8ca8
JD		 2006 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2007 if it is null.
2008 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2009 zero.
2010
3107326d
AP		 20112019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2012
2013 * configure: Regenerate.
2014
7e9ca91e
AM		 20152019-01-07 Alan Modra <amodra@gmail.com>
2016
2017 * configure: Regenerate.
2018 * po/POTFILES.in: Regenerate.
2019
ef1ad42b
JD		 20202019-01-03 John Darrington <john@darrington.wattle.id.au>
2021
2022 * s12z-opc.c: New file.
2023 * s12z-opc.h: New file.
2024 * s12z-dis.c: Removed all code not directly related to display
2025 of instructions. Used the interface provided by the new files
2026 instead.
2027 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2028 * Makefile.in: Regenerate.
ef1ad42b 2029 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2030 * configure: Regenerate.
ef1ad42b 2031
82704155
AM		 20322019-01-01 Alan Modra <amodra@gmail.com>
2033
2034 Update year range in copyright notice of all files.
2035
d5c04e1b 2036For older changes see ChangeLog-2018
3499769a 2037\f
d5c04e1b 2038Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2039
2040Copying and distribution of this file, with or without modification,
2041are permitted in any medium without royalty provided the copyright
2042notice and this notice are preserved.
2043
2044Local Variables:
2045mode: change-log
2046left-margin: 8
2047fill-column: 74
2048version-control: never
2049End:
GDB Binutils - Deliverables
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