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s12z-opc.c formatting fixes
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e7c22a69
AM		 12019-12-10 Alan Modra <amodra@gmail.com>
2
3 * s12z-opc.c: Formatting.
4
0a6aef6b
AM		 52019-12-08 Alan Modra <amodra@gmail.com>
6
7 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
8 registers.
9
2dc4b12f
JB		 102019-12-05 Jan Beulich <jbeulich@suse.com>
11
12 * aarch64-tbl.h (aarch64_feature_crypto,
13 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
14 CRYPTO_V8_2_INSN): Delete.
15
378fd436
AM		 162019-12-05 Alan Modra <amodra@gmail.com>
17
18 PR 25249
19 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
20 (struct string_buf): New.
21 (strbuf): New function.
22 (get_field): Use strbuf rather than strdup of local temp.
23 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
24 (get_field_rfsl, get_field_imm15): Likewise.
25 (get_field_rd, get_field_r1, get_field_r2): Update macros.
26 (get_field_special): Likewise. Don't strcpy spr. Formatting.
27 (print_insn_microblaze): Formatting. Init and pass string_buf to
28 get_field functions.
29
0ba59a29
JB		 302019-12-04 Jan Beulich <jbeulich@suse.com>
31
32 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
33 * i386-tbl.h: Re-generate.
34
77ad8092
JB		 352019-12-04 Jan Beulich <jbeulich@suse.com>
36
37 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
38
3036c899
JB		 392019-12-04 Jan Beulich <jbeulich@suse.com>
40
41 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
42 forms.
43 (xbegin): Drop DefaultSize.
44 * i386-tbl.h: Re-generate.
45
8b301fbb
MI		 462019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
47
48 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
49 Change the coproc CRC conditions to use the extension
50 feature set, second word, base on ARM_EXT2_CRC.
51
6aa385b9
JB		 522019-11-14 Jan Beulich <jbeulich@suse.com>
53
54 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
55 * i386-tbl.h: Re-generate.
56
0cfa3eb3
JB		 572019-11-14 Jan Beulich <jbeulich@suse.com>
58
59 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
60 JumpInterSegment, and JumpAbsolute entries.
61 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
62 JUMP_ABSOLUTE): Define.
63 (struct i386_opcode_modifier): Extend jump field to 3 bits.
64 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
65 fields.
66 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
67 JumpInterSegment): Define.
68 * i386-tbl.h: Re-generate.
69
6f2f06be
JB		 702019-11-14 Jan Beulich <jbeulich@suse.com>
71
72 * i386-gen.c (operand_type_init): Remove
73 OPERAND_TYPE_JUMPABSOLUTE entry.
74 (opcode_modifiers): Add JumpAbsolute entry.
75 (operand_types): Remove JumpAbsolute entry.
76 * i386-opc.h (JumpAbsolute): Move between enums.
77 (struct i386_opcode_modifier): Add jumpabsolute field.
78 (union i386_operand_type): Remove jumpabsolute field.
79 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
80 * i386-init.h, i386-tbl.h: Re-generate.
81
601e8564
JB		 822019-11-14 Jan Beulich <jbeulich@suse.com>
83
84 * i386-gen.c (opcode_modifiers): Add AnySize entry.
85 (operand_types): Remove AnySize entry.
86 * i386-opc.h (AnySize): Move between enums.
87 (struct i386_opcode_modifier): Add anysize field.
88 (OTUnused): Un-comment.
89 (union i386_operand_type): Remove anysize field.
90 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
91 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
92 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
93 AnySize.
94 * i386-tbl.h: Re-generate.
95
7722d40a
JW		 962019-11-12 Nelson Chu <nelson.chu@sifive.com>
97
98 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
99 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
100 use the floating point register (FPR).
101
ce760a76
MI		 1022019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
103
104 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
105 cmode 1101.
106 (is_mve_encoding_conflict): Update cmode conflict checks for
107 MVE_VMVN_IMM.
108
51c8edf6
JB		 1092019-11-12 Jan Beulich <jbeulich@suse.com>
110
111 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
112 entry.
113 (operand_types): Remove EsSeg entry.
114 (main): Replace stale use of OTMax.
115 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
116 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
117 (EsSeg): Delete.
118 (OTUnused): Comment out.
119 (union i386_operand_type): Remove esseg field.
120 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
121 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
122 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
123 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
124 * i386-init.h, i386-tbl.h: Re-generate.
125
474da251
JB		 1262019-11-12 Jan Beulich <jbeulich@suse.com>
127
128 * i386-gen.c (operand_instances): Add RegB entry.
129 * i386-opc.h (enum operand_instance): Add RegB.
130 * i386-opc.tbl (RegC, RegD, RegB): Define.
131 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
132 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
133 monitorx, mwaitx): Drop ImmExt and convert encodings
134 accordingly.
135 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
136 (edx, rdx): Add Instance=RegD.
137 (ebx, rbx): Add Instance=RegB.
138 * i386-tbl.h: Re-generate.
139
75e5731b
JB		 1402019-11-12 Jan Beulich <jbeulich@suse.com>
141
142 * i386-gen.c (operand_type_init): Adjust
143 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
144 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
145 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
146 (operand_instances): New.
147 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
148 (output_operand_type): New parameter "instance". Process it.
149 (process_i386_operand_type): New local variable "instance".
150 (main): Adjust static assertions.
151 * i386-opc.h (INSTANCE_WIDTH): Define.
152 (enum operand_instance): New.
153 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
154 (union i386_operand_type): Replace acc, inoutportreg, and
155 shiftcount by instance.
156 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
157 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
158 Add Instance=.
159 * i386-init.h, i386-tbl.h: Re-generate.
160
91802f3c
JB		 1612019-11-11 Jan Beulich <jbeulich@suse.com>
162
163 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
164 smaxp/sminp entries' "tied_operand" field to 2.
165
4f5fc85d
JB		 1662019-11-11 Jan Beulich <jbeulich@suse.com>
167
168 * aarch64-opc.c (operand_general_constraint_met_p): Replace
169 "index" local variable by that of the already existing "num".
170
dc2be329
L		 1712019-11-08 H.J. Lu <hongjiu.lu@intel.com>
172
173 PR gas/25167
174 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
175 * i386-tbl.h: Regenerated.
176
f74a6307
JB		 1772019-11-08 Jan Beulich <jbeulich@suse.com>
178
179 * i386-gen.c (operand_type_init): Add Class= to
180 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
181 OPERAND_TYPE_REGBND entry.
182 (operand_classes): Add RegMask and RegBND entries.
183 (operand_types): Drop RegMask and RegBND entry.
184 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
185 (RegMask, RegBND): Delete.
186 (union i386_operand_type): Remove regmask and regbnd fields.
187 * i386-opc.tbl (RegMask, RegBND): Define.
188 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
189 Class=RegBND.
190 * i386-init.h, i386-tbl.h: Re-generate.
191
3528c362
JB		 1922019-11-08 Jan Beulich <jbeulich@suse.com>
193
194 * i386-gen.c (operand_type_init): Add Class= to
195 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
196 OPERAND_TYPE_REGZMM entries.
197 (operand_classes): Add RegMMX and RegSIMD entries.
198 (operand_types): Drop RegMMX and RegSIMD entries.
199 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
200 (RegMMX, RegSIMD): Delete.
201 (union i386_operand_type): Remove regmmx and regsimd fields.
202 * i386-opc.tbl (RegMMX): Define.
203 (RegXMM, RegYMM, RegZMM): Add Class=.
204 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
205 Class=RegSIMD.
206 * i386-init.h, i386-tbl.h: Re-generate.
207
4a5c67ed
JB		 2082019-11-08 Jan Beulich <jbeulich@suse.com>
209
210 * i386-gen.c (operand_type_init): Add Class= to
211 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
212 entries.
213 (operand_classes): Add RegCR, RegDR, and RegTR entries.
214 (operand_types): Drop Control, Debug, and Test entries.
215 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
216 (Control, Debug, Test): Delete.
217 (union i386_operand_type): Remove control, debug, and test
218 fields.
219 * i386-opc.tbl (Control, Debug, Test): Define.
220 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
221 Class=RegDR, and Test by Class=RegTR.
222 * i386-init.h, i386-tbl.h: Re-generate.
223
00cee14f
JB		 2242019-11-08 Jan Beulich <jbeulich@suse.com>
225
226 * i386-gen.c (operand_type_init): Add Class= to
227 OPERAND_TYPE_SREG entry.
228 (operand_classes): Add SReg entry.
229 (operand_types): Drop SReg entry.
230 * i386-opc.h (enum operand_class): Add SReg.
231 (SReg): Delete.
232 (union i386_operand_type): Remove sreg field.
233 * i386-opc.tbl (SReg): Define.
234 * i386-reg.tbl: Replace SReg by Class=SReg.
235 * i386-init.h, i386-tbl.h: Re-generate.
236
bab6aec1
JB		 2372019-11-08 Jan Beulich <jbeulich@suse.com>
238
239 * i386-gen.c (operand_type_init): Add Class=. New
240 OPERAND_TYPE_ANYIMM entry.
241 (operand_classes): New.
242 (operand_types): Drop Reg entry.
243 (output_operand_type): New parameter "class". Process it.
244 (process_i386_operand_type): New local variable "class".
245 (main): Adjust static assertions.
246 * i386-opc.h (CLASS_WIDTH): Define.
247 (enum operand_class): New.
248 (Reg): Replace by Class. Adjust comment.
249 (union i386_operand_type): Replace reg by class.
250 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
251 Class=.
252 * i386-reg.tbl: Replace Reg by Class=Reg.
253 * i386-init.h: Re-generate.
254
1f4cd317
MM		 2552019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
256
257 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
258 (aarch64_opcode_table): Add data gathering hint mnemonic.
259 * opcodes/aarch64-dis-2.c: Account for new instruction.
260
616ce08e
MM		 2612019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
262
263 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
264
265
8382113f
MM		 2662019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
267
268 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
269 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
270 aarch64_feature_f64mm): New feature sets.
271 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
272 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
273 instructions.
274 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
275 macros.
276 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
277 (OP_SVE_QQQ): New qualifier.
278 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
279 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
280 the movprfx constraint.
281 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
282 (aarch64_opcode_table): Define new instructions smmla,
283 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
284 uzip{1/2}, trn{1/2}.
285 * aarch64-opc.c (operand_general_constraint_met_p): Handle
286 AARCH64_OPND_SVE_ADDR_RI_S4x32.
287 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
288 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
289 Account for new instructions.
290 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
291 S4x32 operand.
292 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
293
aab2c27d
MM		 2942019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2952019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
296
297 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
298 Armv8.6-A.
299 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
300 (neon_opcodes): Add bfloat SIMD instructions.
301 (print_insn_coprocessor): Add new control character %b to print
302 condition code without checking cp_num.
303 (print_insn_neon): Account for BFloat16 instructions that have no
304 special top-byte handling.
305
33593eaf
MM		 3062019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3072019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
308
309 * arm-dis.c (print_insn_coprocessor,
310 print_insn_generic_coprocessor): Create wrapper functions around
311 the implementation of the print_insn_coprocessor control codes.
312 (print_insn_coprocessor_1): Original print_insn_coprocessor
313 function that now takes which array to look at as an argument.
314 (print_insn_arm): Use both print_insn_coprocessor and
315 print_insn_generic_coprocessor.
316 (print_insn_thumb32): As above.
317
df678013
MM		 3182019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3192019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
320
321 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
322 in reglane special case.
323 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
324 aarch64_find_next_opcode): Account for new instructions.
325 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
326 in reglane special case.
327 * aarch64-opc.c (struct operand_qualifier_data): Add data for
328 new AARCH64_OPND_QLF_S_2H qualifier.
329 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
330 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
331 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
332 sets.
333 (BFLOAT_SVE, BFLOAT): New feature set macros.
334 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
335 instructions.
336 (aarch64_opcode_table): Define new instructions bfdot,
337 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
338 bfcvtn2, bfcvt.
339
8ae2d3d9
MM		 3402019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3412019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
342
343 * aarch64-tbl.h (ARMV8_6): New macro.
344
142861df
JB		 3452019-11-07 Jan Beulich <jbeulich@suse.com>
346
347 * i386-dis.c (prefix_table): Add mcommit.
348 (rm_table): Add rdpru.
349 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
350 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
351 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
352 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
353 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
354 * i386-opc.tbl (mcommit, rdpru): New.
355 * i386-init.h, i386-tbl.h: Re-generate.
356
081e283f
JB		 3572019-11-07 Jan Beulich <jbeulich@suse.com>
358
359 * i386-dis.c (OP_Mwait): Drop local variable "names", use
360 "names32" instead.
361 (OP_Monitor): Drop local variable "op1_names", re-purpose
362 "names" for it instead, and replace former "names" uses by
363 "names32" ones.
364
c050c89a
JB		 3652019-11-07 Jan Beulich <jbeulich@suse.com>
366
367 PR/gas 25167
368 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
369 operand-less forms.
370 * opcodes/i386-tbl.h: Re-generate.
371
7abb8d81
JB		 3722019-11-05 Jan Beulich <jbeulich@suse.com>
373
374 * i386-dis.c (OP_Mwaitx): Delete.
375 (prefix_table): Use OP_Mwait for mwaitx entry.
376 (OP_Mwait): Also handle mwaitx.
377
267b8516
JB		 3782019-11-05 Jan Beulich <jbeulich@suse.com>
379
380 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
381 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
382 (prefix_table): Add respective entries.
383 (rm_table): Link to those entries.
384
f8687e93
JB		 3852019-11-05 Jan Beulich <jbeulich@suse.com>
386
387 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
388 (REG_0F1C_P_0_MOD_0): ... this.
389 (REG_0F1E_MOD_3): Rename to ...
390 (REG_0F1E_P_1_MOD_3): ... this.
391 (RM_0F01_REG_5): Rename to ...
392 (RM_0F01_REG_5_MOD_3): ... this.
393 (RM_0F01_REG_7): Rename to ...
394 (RM_0F01_REG_7_MOD_3): ... this.
395 (RM_0F1E_MOD_3_REG_7): Rename to ...
396 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
397 (RM_0FAE_REG_6): Rename to ...
398 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
399 (RM_0FAE_REG_7): Rename to ...
400 (RM_0FAE_REG_7_MOD_3): ... this.
401 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
402 (PREFIX_0F01_REG_5_MOD_0): ... this.
403 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
404 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
405 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
406 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
407 (PREFIX_0FAE_REG_0): Rename to ...
408 (PREFIX_0FAE_REG_0_MOD_3): ... this.
409 (PREFIX_0FAE_REG_1): Rename to ...
410 (PREFIX_0FAE_REG_1_MOD_3): ... this.
411 (PREFIX_0FAE_REG_2): Rename to ...
412 (PREFIX_0FAE_REG_2_MOD_3): ... this.
413 (PREFIX_0FAE_REG_3): Rename to ...
414 (PREFIX_0FAE_REG_3_MOD_3): ... this.
415 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
416 (PREFIX_0FAE_REG_4_MOD_0): ... this.
417 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
418 (PREFIX_0FAE_REG_4_MOD_3): ... this.
419 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
420 (PREFIX_0FAE_REG_5_MOD_0): ... this.
421 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
422 (PREFIX_0FAE_REG_5_MOD_3): ... this.
423 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
424 (PREFIX_0FAE_REG_6_MOD_0): ... this.
425 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
426 (PREFIX_0FAE_REG_6_MOD_3): ... this.
427 (PREFIX_0FAE_REG_7): Rename to ...
428 (PREFIX_0FAE_REG_7_MOD_0): ... this.
429 (PREFIX_MOD_0_0FC3): Rename to ...
430 (PREFIX_0FC3_MOD_0): ... this.
431 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
432 (PREFIX_0FC7_REG_6_MOD_0): ... this.
433 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
434 (PREFIX_0FC7_REG_6_MOD_3): ... this.
435 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
436 (PREFIX_0FC7_REG_7_MOD_3): ... this.
437 (reg_table, prefix_table, mod_table, rm_table): Adjust
438 accordingly.
439
5103274f
NC		 4402019-11-04 Nick Clifton <nickc@redhat.com>
441
442 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
443 of a v850 system register. Move the v850_sreg_names array into
444 this function.
445 (get_v850_reg_name): Likewise for ordinary register names.
446 (get_v850_vreg_name): Likewise for vector register names.
447 (get_v850_cc_name): Likewise for condition codes.
448 * get_v850_float_cc_name): Likewise for floating point condition
449 codes.
450 (get_v850_cacheop_name): Likewise for cache-ops.
451 (get_v850_prefop_name): Likewise for pref-ops.
452 (disassemble): Use the new accessor functions.
453
1820262b
DB		 4542019-10-30 Delia Burduv <delia.burduv@arm.com>
455
456 * aarch64-opc.c (print_immediate_offset_address): Don't print the
457 immediate for the writeback form of ldraa/ldrab if it is 0.
458 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
459 * aarch64-opc-2.c: Regenerated.
460
3cc17af5
JB		 4612019-10-30 Jan Beulich <jbeulich@suse.com>
462
463 * i386-gen.c (operand_type_shorthands): Delete.
464 (operand_type_init): Expand previous shorthands.
465 (set_bitfield_from_shorthand): Rename back to ...
466 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
467 of operand_type_init[].
468 (set_bitfield): Adjust call to the above function.
469 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
470 RegXMM, RegYMM, RegZMM): Define.
471 * i386-reg.tbl: Expand prior shorthands.
472
a2cebd03
JB		 4732019-10-30 Jan Beulich <jbeulich@suse.com>
474
475 * i386-gen.c (output_i386_opcode): Change order of fields
476 emitted to output.
477 * i386-opc.h (struct insn_template): Move operands field.
478 Convert extension_opcode field to unsigned short.
479 * i386-tbl.h: Re-generate.
480
507916b8
JB		 4812019-10-30 Jan Beulich <jbeulich@suse.com>
482
483 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
484 of W.
485 * i386-opc.h (W): Extend comment.
486 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
487 general purpose variants not allowing for byte operands.
488 * i386-tbl.h: Re-generate.
489
efea62b4
NC		 4902019-10-29 Nick Clifton <nickc@redhat.com>
491
492 * tic30-dis.c (print_branch): Correct size of operand array.
493
9adb2591
NC		 4942019-10-29 Nick Clifton <nickc@redhat.com>
495
496 * d30v-dis.c (print_insn): Check that operand index is valid
497 before attempting to access the operands array.
498
993a00a9
NC		 4992019-10-29 Nick Clifton <nickc@redhat.com>
500
501 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
502 locating the bit to be tested.
503
66a66a17
NC		 5042019-10-29 Nick Clifton <nickc@redhat.com>
505
506 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
507 values.
508 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
509 (print_insn_s12z): Check for illegal size values.
510
1ee3542c
NC		 5112019-10-28 Nick Clifton <nickc@redhat.com>
512
513 * csky-dis.c (csky_chars_to_number): Check for a negative
514 count. Use an unsigned integer to construct the return value.
515
bbf9a0b5
NC		 5162019-10-28 Nick Clifton <nickc@redhat.com>
517
518 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
519 operand buffer. Set value to 15 not 13.
520 (get_register_operand): Use OPERAND_BUFFER_LEN.
521 (get_indirect_operand): Likewise.
522 (print_two_operand): Likewise.
523 (print_three_operand): Likewise.
524 (print_oar_insn): Likewise.
525
d1e304bc
NC		 5262019-10-28 Nick Clifton <nickc@redhat.com>
527
528 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
529 (bit_extract_simple): Likewise.
530 (bit_copy): Likewise.
531 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
532 index_offset array are not accessed.
533
dee33451
NC		 5342019-10-28 Nick Clifton <nickc@redhat.com>
535
536 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
537 operand.
538
27cee81d
NC		 5392019-10-25 Nick Clifton <nickc@redhat.com>
540
541 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
542 access to opcodes.op array element.
543
de6d8dc2
NC		 5442019-10-23 Nick Clifton <nickc@redhat.com>
545
546 * rx-dis.c (get_register_name): Fix spelling typo in error
547 message.
548 (get_condition_name, get_flag_name, get_double_register_name)
549 (get_double_register_high_name, get_double_register_low_name)
550 (get_double_control_register_name, get_double_condition_name)
551 (get_opsize_name, get_size_name): Likewise.
552
6207ed28
NC		 5532019-10-22 Nick Clifton <nickc@redhat.com>
554
555 * rx-dis.c (get_size_name): New function. Provides safe
556 access to name array.
557 (get_opsize_name): Likewise.
558 (print_insn_rx): Use the accessor functions.
559
12234dfd
NC		 5602019-10-16 Nick Clifton <nickc@redhat.com>
561
562 * rx-dis.c (get_register_name): New function. Provides safe
563 access to name array.
564 (get_condition_name, get_flag_name, get_double_register_name)
565 (get_double_register_high_name, get_double_register_low_name)
566 (get_double_control_register_name, get_double_condition_name):
567 Likewise.
568 (print_insn_rx): Use the accessor functions.
569
1d378749
NC		 5702019-10-09 Nick Clifton <nickc@redhat.com>
571
572 PR 25041
573 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
574 instructions.
575
d241b910
JB		 5762019-10-07 Jan Beulich <jbeulich@suse.com>
577
578 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
579 (cmpsd): Likewise. Move EsSeg to other operand.
580 * opcodes/i386-tbl.h: Re-generate.
581
f5c5b7c1
AM		 5822019-09-23 Alan Modra <amodra@gmail.com>
583
584 * m68k-dis.c: Include cpu-m68k.h
585
7beeaeb8
AM		 5862019-09-23 Alan Modra <amodra@gmail.com>
587
588 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
589 "elf/mips.h" earlier.
590
3f9aad11
JB		 5912018-09-20 Jan Beulich <jbeulich@suse.com>
592
593 PR gas/25012
594 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
595 with SReg operand.
596 * i386-tbl.h: Re-generate.
597
fd361982
AM		 5982019-09-18 Alan Modra <amodra@gmail.com>
599
600 * arc-ext.c: Update throughout for bfd section macro changes.
601
e0b2a78c
SM		 6022019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
603
604 * Makefile.in: Re-generate.
605 * configure: Re-generate.
606
7e9ad3a3
JW		 6072019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
608
609 * riscv-opc.c (riscv_opcodes): Change subset field
610 to insn_class field for all instructions.
611 (riscv_insn_types): Likewise.
612
bb695960
PB		 6132019-09-16 Phil Blundell <pb@pbcl.net>
614
615 * configure: Regenerated.
616
8063ab7e
MV		 6172019-09-10 Miod Vallat <miod@online.fr>
618
619 PR 24982
620 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
621
60391a25
PB		 6222019-09-09 Phil Blundell <pb@pbcl.net>
623
624 binutils 2.33 branch created.
625
f44b758d
NC		 6262019-09-03 Nick Clifton <nickc@redhat.com>
627
628 PR 24961
629 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
630 greater than zero before indexing via (bufcnt -1).
631
1e4b5e7d
NC		 6322019-09-03 Nick Clifton <nickc@redhat.com>
633
634 PR 24958
635 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
636 (MAX_SPEC_REG_NAME_LEN): Define.
637 (struct mmix_dis_info): Use defined constants for array lengths.
638 (get_reg_name): New function.
639 (get_sprec_reg_name): New function.
640 (print_insn_mmix): Use new functions.
641
c4a23bf8
SP		 6422019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
643
644 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
645 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
646 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
647
a051e2f3
KT		 6482019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
649
650 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
651 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
652 (aarch64_sys_reg_supported_p): Update checks for the above.
653
08132bdd
SP		 6542019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
655
656 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
657 cases MVE_SQRSHRL and MVE_UQRSHLL.
658 (print_insn_mve): Add case for specifier 'k' to check
659 specific bit of the instruction.
660
d88bdcb4
PA		 6612019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
662
663 PR 24854
664 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
665 encountering an unknown machine type.
666 (print_insn_arc): Handle arc_insn_length returning 0. In error
667 cases return -1 rather than calling abort.
668
bc750500
JB		 6692019-08-07 Jan Beulich <jbeulich@suse.com>
670
671 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
672 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
673 IgnoreSize.
674 * i386-tbl.h: Re-generate.
675
23d188c7
BW		 6762019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
677
678 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
679 instructions.
680
c0d6f62f
JW		 6812019-07-30 Mel Chen <mel.chen@sifive.com>
682
683 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
684 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
685
686 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
687 fscsr.
688
0f3f7167
CZ		 6892019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
690
691 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
692 and MPY class instructions.
693 (parse_option): Add nps400 option.
694 (print_arc_disassembler_options): Add nps400 info.
695
7e126ba3
CZ		 6962019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
697
698 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
699 (bspop): Likewise.
700 (modapp): Likewise.
701 * arc-opc.c (RAD_CHK): Add.
702 * arc-tbl.h: Regenerate.
703
a028026d
KT		 7042019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
705
706 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
707 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
708
ac79ff9e
NC		 7092019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
710
711 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
712 instructions as UNPREDICTABLE.
713
231097b0
JM		 7142019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
715
716 * bpf-desc.c: Regenerated.
717
1d942ae9
JB		 7182019-07-17 Jan Beulich <jbeulich@suse.com>
719
720 * i386-gen.c (static_assert): Define.
721 (main): Use it.
722 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
723 (Opcode_Modifier_Num): ... this.
724 (Mem): Delete.
725
dfd69174
JB		 7262019-07-16 Jan Beulich <jbeulich@suse.com>
727
728 * i386-gen.c (operand_types): Move RegMem ...
729 (opcode_modifiers): ... here.
730 * i386-opc.h (RegMem): Move to opcode modifer enum.
731 (union i386_operand_type): Move regmem field ...
732 (struct i386_opcode_modifier): ... here.
733 * i386-opc.tbl (RegMem): Define.
734 (mov, movq): Move RegMem on segment, control, debug, and test
735 register flavors.
736 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
737 to non-SSE2AVX flavor.
738 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
739 Move RegMem on register only flavors. Drop IgnoreSize from
740 legacy encoding flavors.
741 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
742 flavors.
743 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
744 register only flavors.
745 (vmovd): Move RegMem and drop IgnoreSize on register only
746 flavor. Change opcode and operand order to store form.
747 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
748
21df382b
JB		 7492019-07-16 Jan Beulich <jbeulich@suse.com>
750
751 * i386-gen.c (operand_type_init, operand_types): Replace SReg
752 entries.
753 * i386-opc.h (SReg2, SReg3): Replace by ...
754 (SReg): ... this.
755 (union i386_operand_type): Replace sreg fields.
756 * i386-opc.tbl (mov, ): Use SReg.
757 (push, pop): Likewies. Drop i386 and x86-64 specific segment
758 register flavors.
759 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
760 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
761
3719fd55
JM		 7622019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
763
764 * bpf-desc.c: Regenerate.
765 * bpf-opc.c: Likewise.
766 * bpf-opc.h: Likewise.
767
92434a14
JM		 7682019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
769
770 * bpf-desc.c: Regenerate.
771 * bpf-opc.c: Likewise.
772
43dd7626
HPN		 7732019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
774
775 * arm-dis.c (print_insn_coprocessor): Rename index to
776 index_operand.
777
98602811
JW		 7782019-07-05 Kito Cheng <kito.cheng@sifive.com>
779
780 * riscv-opc.c (riscv_insn_types): Add r4 type.
781
782 * riscv-opc.c (riscv_insn_types): Add b and j type.
783
784 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
785 format for sb type and correct s type.
786
01c1ee4a
RS		 7872019-07-02 Richard Sandiford <richard.sandiford@arm.com>
788
789 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
790 SVE FMOV alias of FCPY.
791
83adff69
RS		 7922019-07-02 Richard Sandiford <richard.sandiford@arm.com>
793
794 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
795 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
796
89418844
RS		 7972019-07-02 Richard Sandiford <richard.sandiford@arm.com>
798
799 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
800 registers in an instruction prefixed by MOVPRFX.
801
41be57ca
MM		 8022019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
803
804 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
805 sve_size_13 icode to account for variant behaviour of
806 pmull{t,b}.
807 * aarch64-dis-2.c: Regenerate.
808 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
809 sve_size_13 icode to account for variant behaviour of
810 pmull{t,b}.
811 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
812 (OP_SVE_VVV_Q_D): Add new qualifier.
813 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
814 (struct aarch64_opcode): Split pmull{t,b} into those requiring
815 AES and those not.
816
9d3bf266
JB		 8172019-07-01 Jan Beulich <jbeulich@suse.com>
818
819 * opcodes/i386-gen.c (operand_type_init): Remove
820 OPERAND_TYPE_VEC_IMM4 entry.
821 (operand_types): Remove Vec_Imm4.
822 * opcodes/i386-opc.h (Vec_Imm4): Delete.
823 (union i386_operand_type): Remove vec_imm4.
824 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
825 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
826
c3949f43
JB		 8272019-07-01 Jan Beulich <jbeulich@suse.com>
828
829 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
830 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
831 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
832 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
833 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
834 monitorx, mwaitx): Drop ImmExt from operand-less forms.
835 * i386-tbl.h: Re-generate.
836
5641ec01
JB		 8372019-07-01 Jan Beulich <jbeulich@suse.com>
838
839 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
840 register operands.
841 * i386-tbl.h: Re-generate.
842
79dec6b7
JB		 8432019-07-01 Jan Beulich <jbeulich@suse.com>
844
845 * i386-opc.tbl (C): New.
846 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
847 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
848 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
849 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
850 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
851 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
852 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
853 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
854 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
855 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
856 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
857 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
858 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
859 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
860 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
861 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
862 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
863 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
864 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
865 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
866 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
867 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
868 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
869 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
870 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
871 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
872 flavors.
873 * i386-tbl.h: Re-generate.
874
a0a1771e
JB		 8752019-07-01 Jan Beulich <jbeulich@suse.com>
876
877 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
878 register operands.
879 * i386-tbl.h: Re-generate.
880
cd546e7b
JB		 8812019-07-01 Jan Beulich <jbeulich@suse.com>
882
883 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
884 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
885 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
886 * i386-tbl.h: Re-generate.
887
e3bba3fc
JB		 8882019-07-01 Jan Beulich <jbeulich@suse.com>
889
890 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
891 Disp8MemShift from register only templates.
892 * i386-tbl.h: Re-generate.
893
36cc073e
JB		 8942019-07-01 Jan Beulich <jbeulich@suse.com>
895
896 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
897 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
898 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
899 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
900 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
901 EVEX_W_0F11_P_3_M_1): Delete.
902 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
903 EVEX_W_0F11_P_3): New.
904 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
905 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
906 MOD_EVEX_0F11_PREFIX_3 table entries.
907 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
908 PREFIX_EVEX_0F11 table entries.
909 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
910 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
911 EVEX_W_0F11_P_3_M_{0,1} table entries.
912
219920a7
JB		 9132019-07-01 Jan Beulich <jbeulich@suse.com>
914
915 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
916 Delete.
917
e395f487
L		 9182019-06-27 H.J. Lu <hongjiu.lu@intel.com>
919
920 PR binutils/24719
921 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
922 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
923 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
924 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
925 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
926 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
927 EVEX_LEN_0F38C7_R_6_P_2_W_1.
928 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
929 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
930 PREFIX_EVEX_0F38C6_REG_6 entries.
931 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
932 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
933 EVEX_W_0F38C7_R_6_P_2 entries.
934 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
935 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
936 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
937 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
938 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
939 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
940 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
941
2b7bcc87
JB		 9422019-06-27 Jan Beulich <jbeulich@suse.com>
943
944 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
945 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
946 VEX_LEN_0F2D_P_3): Delete.
947 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
948 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
949 (prefix_table): ... here.
950
c1dc7af5
JB		 9512019-06-27 Jan Beulich <jbeulich@suse.com>
952
953 * i386-dis.c (Iq): Delete.
954 (Id): New.
955 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
956 TBM insns.
957 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
958 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
959 (OP_E_memory): Also honor needindex when deciding whether an
960 address size prefix needs printing.
961 (OP_I): Remove handling of q_mode. Add handling of d_mode.
962
d7560e2d
JW		 9632019-06-26 Jim Wilson <jimw@sifive.com>
964
965 PR binutils/24739
966 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
967 Set info->display_endian to info->endian_code.
968
2c703856
JB		 9692019-06-25 Jan Beulich <jbeulich@suse.com>
970
971 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
972 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
973 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
974 OPERAND_TYPE_ACC64 entries.
975 * i386-init.h: Re-generate.
976
54fbadc0
JB		 9772019-06-25 Jan Beulich <jbeulich@suse.com>
978
979 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
980 Delete.
981 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
982 of dqa_mode.
983 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
984 entries here.
985 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
986 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
987
a280ab8e
JB		 9882019-06-25 Jan Beulich <jbeulich@suse.com>
989
990 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
991 variables.
992
e1a1babd
JB		 9932019-06-25 Jan Beulich <jbeulich@suse.com>
994
995 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
996 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
997 movnti.
d7560e2d 998 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 999 * i386-tbl.h: Re-generate.
1000
b8364fa7
JB		 10012019-06-25 Jan Beulich <jbeulich@suse.com>
1002
1003 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1004 * i386-tbl.h: Re-generate.
1005
ad692897
L		 10062019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1007
1008 * i386-dis-evex.h: Break into ...
1009 * i386-dis-evex-len.h: New file.
1010 * i386-dis-evex-mod.h: Likewise.
1011 * i386-dis-evex-prefix.h: Likewise.
1012 * i386-dis-evex-reg.h: Likewise.
1013 * i386-dis-evex-w.h: Likewise.
1014 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1015 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1016 i386-dis-evex-mod.h.
1017
f0a6222e
L		 10182019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1019
1020 PR binutils/24700
1021 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1022 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1023 EVEX_W_0F385B_P_2.
1024 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1025 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1026 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1027 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1028 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1029 EVEX_LEN_0F385B_P_2_W_1.
1030 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1031 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1032 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1033 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1034 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1035 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1036 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1037 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1038 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1039 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1040
6e1c90b7
L		 10412019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1042
1043 PR binutils/24691
1044 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1045 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1046 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1047 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1048 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1049 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1050 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1051 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1052 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1053 EVEX_LEN_0F3A43_P_2_W_1.
1054 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1055 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1056 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1057 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1058 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1059 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1060 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1061 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1062 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1063 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1064 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1065 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1066
bcc5a6eb
NC		 10672019-06-14 Nick Clifton <nickc@redhat.com>
1068
1069 * po/fr.po; Updated French translation.
1070
e4c4ac46
SH		 10712019-06-13 Stafford Horne <shorne@gmail.com>
1072
1073 * or1k-asm.c: Regenerated.
1074 * or1k-desc.c: Regenerated.
1075 * or1k-desc.h: Regenerated.
1076 * or1k-dis.c: Regenerated.
1077 * or1k-ibld.c: Regenerated.
1078 * or1k-opc.c: Regenerated.
1079 * or1k-opc.h: Regenerated.
1080 * or1k-opinst.c: Regenerated.
1081
a0e44ef5
PB		 10822019-06-12 Peter Bergner <bergner@linux.ibm.com>
1083
1084 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1085
12efd68d
L		 10862019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1087
1088 PR binutils/24633
1089 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1090 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1091 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1092 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1093 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1094 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1095 EVEX_LEN_0F3A1B_P_2_W_1.
1096 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1097 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1098 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1099 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1100 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1101 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1102 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1103 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1104
63c6fc6c
L		 11052019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1106
1107 PR binutils/24626
1108 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1109 EVEX.vvvv when disassembling VEX and EVEX instructions.
1110 (OP_VEX): Set vex.register_specifier to 0 after readding
1111 vex.register_specifier.
1112 (OP_Vex_2src_1): Likewise.
1113 (OP_Vex_2src_2): Likewise.
1114 (OP_LWP_E): Likewise.
1115 (OP_EX_Vex): Don't check vex.register_specifier.
1116 (OP_XMM_Vex): Likewise.
1117
9186c494
L		 11182019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1119 Lili Cui <lili.cui@intel.com>
1120
1121 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1122 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1123 instructions.
1124 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1125 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1126 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1127 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1128 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1129 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1130 * i386-init.h: Regenerated.
1131 * i386-tbl.h: Likewise.
1132
5d79adc4
L		 11332019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1134 Lili Cui <lili.cui@intel.com>
1135
1136 * doc/c-i386.texi: Document enqcmd.
1137 * testsuite/gas/i386/enqcmd-intel.d: New file.
1138 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1139 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1140 * testsuite/gas/i386/enqcmd.d: Likewise.
1141 * testsuite/gas/i386/enqcmd.s: Likewise.
1142 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1143 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1144 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1145 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1146 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1147 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1148 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1149 and x86-64-enqcmd.
1150
a9d96ab9
AH		 11512019-06-04 Alan Hayward <alan.hayward@arm.com>
1152
1153 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1154
4f6d070a
AM		 11552019-06-03 Alan Modra <amodra@gmail.com>
1156
1157 * ppc-dis.c (prefix_opcd_indices): Correct size.
1158
a2f4b66c
L		 11592019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1160
1161 PR gas/24625
1162 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1163 Disp8ShiftVL.
1164 * i386-tbl.h: Regenerated.
1165
405b5bd8
AM		 11662019-05-24 Alan Modra <amodra@gmail.com>
1167
1168 * po/POTFILES.in: Regenerate.
1169
8acf1435
PB		 11702019-05-24 Peter Bergner <bergner@linux.ibm.com>
1171 Alan Modra <amodra@gmail.com>
1172
1173 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1174 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1175 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1176 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1177 XTOP>): Define and add entries.
1178 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1179 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1180 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1181 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1182
dd7efa79
PB		 11832019-05-24 Peter Bergner <bergner@linux.ibm.com>
1184 Alan Modra <amodra@gmail.com>
1185
1186 * ppc-dis.c (ppc_opts): Add "future" entry.
1187 (PREFIX_OPCD_SEGS): Define.
1188 (prefix_opcd_indices): New array.
1189 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1190 (lookup_prefix): New function.
1191 (print_insn_powerpc): Handle 64-bit prefix instructions.
1192 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1193 (PMRR, POWERXX): Define.
1194 (prefix_opcodes): New instruction table.
1195 (prefix_num_opcodes): New constant.
1196
79472b45
JM		 11972019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1198
1199 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1200 * configure: Regenerated.
1201 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1202 and cpu/bpf.opc.
1203 (HFILES): Add bpf-desc.h and bpf-opc.h.
1204 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1205 bpf-ibld.c and bpf-opc.c.
1206 (BPF_DEPS): Define.
1207 * Makefile.in: Regenerated.
1208 * disassemble.c (ARCH_bpf): Define.
1209 (disassembler): Add case for bfd_arch_bpf.
1210 (disassemble_init_for_target): Likewise.
1211 (enum epbf_isa_attr): Define.
1212 * disassemble.h: extern print_insn_bpf.
1213 * bpf-asm.c: Generated.
1214 * bpf-opc.h: Likewise.
1215 * bpf-opc.c: Likewise.
1216 * bpf-ibld.c: Likewise.
1217 * bpf-dis.c: Likewise.
1218 * bpf-desc.h: Likewise.
1219 * bpf-desc.c: Likewise.
1220
ba6cd17f
SD		 12212019-05-21 Sudakshina Das <sudi.das@arm.com>
1222
1223 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1224 and VMSR with the new operands.
1225
e39c1607
SD		 12262019-05-21 Sudakshina Das <sudi.das@arm.com>
1227
1228 * arm-dis.c (enum mve_instructions): New enum
1229 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1230 and cneg.
1231 (mve_opcodes): New instructions as above.
1232 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1233 csneg and csel.
1234 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1235
23d00a41
SD		 12362019-05-21 Sudakshina Das <sudi.das@arm.com>
1237
1238 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1239 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1240 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1241 uqshl, urshrl and urshr.
1242 (is_mve_okay_in_it): Add new instructions to TRUE list.
1243 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1244 (print_insn_mve): Updated to accept new %j,
1245 %<bitfield>m and %<bitfield>n patterns.
1246
cd4797ee
FS		 12472019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1248
1249 * mips-opc.c (mips_builtin_opcodes): Change source register
1250 constraint for DAUI.
1251
999b073b
NC		 12522019-05-20 Nick Clifton <nickc@redhat.com>
1253
1254 * po/fr.po: Updated French translation.
1255
14b456f2
AV		 12562019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1257 Michael Collison <michael.collison@arm.com>
1258
1259 * arm-dis.c (thumb32_opcodes): Add new instructions.
1260 (enum mve_instructions): Likewise.
1261 (enum mve_undefined): Add new reasons.
1262 (is_mve_encoding_conflict): Handle new instructions.
1263 (is_mve_undefined): Likewise.
1264 (is_mve_unpredictable): Likewise.
1265 (print_mve_undefined): Likewise.
1266 (print_mve_size): Likewise.
1267
f49bb598
AV		 12682019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1269 Michael Collison <michael.collison@arm.com>
1270
1271 * arm-dis.c (thumb32_opcodes): Add new instructions.
1272 (enum mve_instructions): Likewise.
1273 (is_mve_encoding_conflict): Handle new instructions.
1274 (is_mve_undefined): Likewise.
1275 (is_mve_unpredictable): Likewise.
1276 (print_mve_size): Likewise.
1277
56858bea
AV		 12782019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1279 Michael Collison <michael.collison@arm.com>
1280
1281 * arm-dis.c (thumb32_opcodes): Add new instructions.
1282 (enum mve_instructions): Likewise.
1283 (is_mve_encoding_conflict): Likewise.
1284 (is_mve_unpredictable): Likewise.
1285 (print_mve_size): Likewise.
1286
e523f101
AV		 12872019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1288 Michael Collison <michael.collison@arm.com>
1289
1290 * arm-dis.c (thumb32_opcodes): Add new instructions.
1291 (enum mve_instructions): Likewise.
1292 (is_mve_encoding_conflict): Handle new instructions.
1293 (is_mve_undefined): Likewise.
1294 (is_mve_unpredictable): Likewise.
1295 (print_mve_size): Likewise.
1296
66dcaa5d
AV		 12972019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1298 Michael Collison <michael.collison@arm.com>
1299
1300 * arm-dis.c (thumb32_opcodes): Add new instructions.
1301 (enum mve_instructions): Likewise.
1302 (is_mve_encoding_conflict): Handle new instructions.
1303 (is_mve_undefined): Likewise.
1304 (is_mve_unpredictable): Likewise.
1305 (print_mve_size): Likewise.
1306 (print_insn_mve): Likewise.
1307
d052b9b7
AV		 13082019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1309 Michael Collison <michael.collison@arm.com>
1310
1311 * arm-dis.c (thumb32_opcodes): Add new instructions.
1312 (print_insn_thumb32): Handle new instructions.
1313
ed63aa17
AV		 13142019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1315 Michael Collison <michael.collison@arm.com>
1316
1317 * arm-dis.c (enum mve_instructions): Add new instructions.
1318 (enum mve_undefined): Add new reasons.
1319 (is_mve_encoding_conflict): Handle new instructions.
1320 (is_mve_undefined): Likewise.
1321 (is_mve_unpredictable): Likewise.
1322 (print_mve_undefined): Likewise.
1323 (print_mve_size): Likewise.
1324 (print_mve_shift_n): Likewise.
1325 (print_insn_mve): Likewise.
1326
897b9bbc
AV		 13272019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1328 Michael Collison <michael.collison@arm.com>
1329
1330 * arm-dis.c (enum mve_instructions): Add new instructions.
1331 (is_mve_encoding_conflict): Handle new instructions.
1332 (is_mve_unpredictable): Likewise.
1333 (print_mve_rotate): Likewise.
1334 (print_mve_size): Likewise.
1335 (print_insn_mve): Likewise.
1336
1c8f2df8
AV		 13372019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1338 Michael Collison <michael.collison@arm.com>
1339
1340 * arm-dis.c (enum mve_instructions): Add new instructions.
1341 (is_mve_encoding_conflict): Handle new instructions.
1342 (is_mve_unpredictable): Likewise.
1343 (print_mve_size): Likewise.
1344 (print_insn_mve): Likewise.
1345
d3b63143
AV		 13462019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1347 Michael Collison <michael.collison@arm.com>
1348
1349 * arm-dis.c (enum mve_instructions): Add new instructions.
1350 (enum mve_undefined): Add new reasons.
1351 (is_mve_encoding_conflict): Handle new instructions.
1352 (is_mve_undefined): Likewise.
1353 (is_mve_unpredictable): Likewise.
1354 (print_mve_undefined): Likewise.
1355 (print_mve_size): Likewise.
1356 (print_insn_mve): Likewise.
1357
14925797
AV		 13582019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1359 Michael Collison <michael.collison@arm.com>
1360
1361 * arm-dis.c (enum mve_instructions): Add new instructions.
1362 (is_mve_encoding_conflict): Handle new instructions.
1363 (is_mve_undefined): Likewise.
1364 (is_mve_unpredictable): Likewise.
1365 (print_mve_size): Likewise.
1366 (print_insn_mve): Likewise.
1367
c507f10b
AV		 13682019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1369 Michael Collison <michael.collison@arm.com>
1370
1371 * arm-dis.c (enum mve_instructions): Add new instructions.
1372 (enum mve_unpredictable): Add new reasons.
1373 (enum mve_undefined): Likewise.
1374 (is_mve_okay_in_it): Handle new isntructions.
1375 (is_mve_encoding_conflict): Likewise.
1376 (is_mve_undefined): Likewise.
1377 (is_mve_unpredictable): Likewise.
1378 (print_mve_vmov_index): Likewise.
1379 (print_simd_imm8): Likewise.
1380 (print_mve_undefined): Likewise.
1381 (print_mve_unpredictable): Likewise.
1382 (print_mve_size): Likewise.
1383 (print_insn_mve): Likewise.
1384
bf0b396d
AV		 13852019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1386 Michael Collison <michael.collison@arm.com>
1387
1388 * arm-dis.c (enum mve_instructions): Add new instructions.
1389 (enum mve_unpredictable): Add new reasons.
1390 (enum mve_undefined): Likewise.
1391 (is_mve_encoding_conflict): Handle new instructions.
1392 (is_mve_undefined): Likewise.
1393 (is_mve_unpredictable): Likewise.
1394 (print_mve_undefined): Likewise.
1395 (print_mve_unpredictable): Likewise.
1396 (print_mve_rounding_mode): Likewise.
1397 (print_mve_vcvt_size): Likewise.
1398 (print_mve_size): Likewise.
1399 (print_insn_mve): Likewise.
1400
ef1576a1
AV		 14012019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1402 Michael Collison <michael.collison@arm.com>
1403
1404 * arm-dis.c (enum mve_instructions): Add new instructions.
1405 (enum mve_unpredictable): Add new reasons.
1406 (enum mve_undefined): Likewise.
1407 (is_mve_undefined): Handle new instructions.
1408 (is_mve_unpredictable): Likewise.
1409 (print_mve_undefined): Likewise.
1410 (print_mve_unpredictable): Likewise.
1411 (print_mve_size): Likewise.
1412 (print_insn_mve): Likewise.
1413
aef6d006
AV		 14142019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1415 Michael Collison <michael.collison@arm.com>
1416
1417 * arm-dis.c (enum mve_instructions): Add new instructions.
1418 (enum mve_undefined): Add new reasons.
1419 (insns): Add new instructions.
1420 (is_mve_encoding_conflict):
1421 (print_mve_vld_str_addr): New print function.
1422 (is_mve_undefined): Handle new instructions.
1423 (is_mve_unpredictable): Likewise.
1424 (print_mve_undefined): Likewise.
1425 (print_mve_size): Likewise.
1426 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1427 (print_insn_mve): Handle new operands.
1428
04d54ace
AV		 14292019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1430 Michael Collison <michael.collison@arm.com>
1431
1432 * arm-dis.c (enum mve_instructions): Add new instructions.
1433 (enum mve_unpredictable): Add new reasons.
1434 (is_mve_encoding_conflict): Handle new instructions.
1435 (is_mve_unpredictable): Likewise.
1436 (mve_opcodes): Add new instructions.
1437 (print_mve_unpredictable): Handle new reasons.
1438 (print_mve_register_blocks): New print function.
1439 (print_mve_size): Handle new instructions.
1440 (print_insn_mve): Likewise.
1441
9743db03
AV		 14422019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1443 Michael Collison <michael.collison@arm.com>
1444
1445 * arm-dis.c (enum mve_instructions): Add new instructions.
1446 (enum mve_unpredictable): Add new reasons.
1447 (enum mve_undefined): Likewise.
1448 (is_mve_encoding_conflict): Handle new instructions.
1449 (is_mve_undefined): Likewise.
1450 (is_mve_unpredictable): Likewise.
1451 (coprocessor_opcodes): Move NEON VDUP from here...
1452 (neon_opcodes): ... to here.
1453 (mve_opcodes): Add new instructions.
1454 (print_mve_undefined): Handle new reasons.
1455 (print_mve_unpredictable): Likewise.
1456 (print_mve_size): Handle new instructions.
1457 (print_insn_neon): Handle vdup.
1458 (print_insn_mve): Handle new operands.
1459
143275ea
AV		 14602019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1461 Michael Collison <michael.collison@arm.com>
1462
1463 * arm-dis.c (enum mve_instructions): Add new instructions.
1464 (enum mve_unpredictable): Add new values.
1465 (mve_opcodes): Add new instructions.
1466 (vec_condnames): New array with vector conditions.
1467 (mve_predicatenames): New array with predicate suffixes.
1468 (mve_vec_sizename): New array with vector sizes.
1469 (enum vpt_pred_state): New enum with vector predication states.
1470 (struct vpt_block): New struct type for vpt blocks.
1471 (vpt_block_state): Global struct to keep track of state.
1472 (mve_extract_pred_mask): New helper function.
1473 (num_instructions_vpt_block): Likewise.
1474 (mark_outside_vpt_block): Likewise.
1475 (mark_inside_vpt_block): Likewise.
1476 (invert_next_predicate_state): Likewise.
1477 (update_next_predicate_state): Likewise.
1478 (update_vpt_block_state): Likewise.
1479 (is_vpt_instruction): Likewise.
1480 (is_mve_encoding_conflict): Add entries for new instructions.
1481 (is_mve_unpredictable): Likewise.
1482 (print_mve_unpredictable): Handle new cases.
1483 (print_instruction_predicate): Likewise.
1484 (print_mve_size): New function.
1485 (print_vec_condition): New function.
1486 (print_insn_mve): Handle vpt blocks and new print operands.
1487
f08d8ce3
AV		 14882019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1489
1490 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1491 8, 14 and 15 for Armv8.1-M Mainline.
1492
73cd51e5
AV		 14932019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1494 Michael Collison <michael.collison@arm.com>
1495
1496 * arm-dis.c (enum mve_instructions): New enum.
1497 (enum mve_unpredictable): Likewise.
1498 (enum mve_undefined): Likewise.
1499 (struct mopcode32): New struct.
1500 (is_mve_okay_in_it): New function.
1501 (is_mve_architecture): Likewise.
1502 (arm_decode_field): Likewise.
1503 (arm_decode_field_multiple): Likewise.
1504 (is_mve_encoding_conflict): Likewise.
1505 (is_mve_undefined): Likewise.
1506 (is_mve_unpredictable): Likewise.
1507 (print_mve_undefined): Likewise.
1508 (print_mve_unpredictable): Likewise.
1509 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1510 (print_insn_mve): New function.
1511 (print_insn_thumb32): Handle MVE architecture.
1512 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1513
3076e594
NC		 15142019-05-10 Nick Clifton <nickc@redhat.com>
1515
1516 PR 24538
1517 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1518 end of the table prematurely.
1519
387e7624
FS		 15202019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1521
1522 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1523 macros for R6.
1524
0067be51
AM		 15252019-05-11 Alan Modra <amodra@gmail.com>
1526
1527 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1528 when -Mraw is in effect.
1529
42e6288f
MM		 15302019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1531
1532 * aarch64-dis-2.c: Regenerate.
1533 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1534 (OP_SVE_BBB): New variant set.
1535 (OP_SVE_DDDD): New variant set.
1536 (OP_SVE_HHH): New variant set.
1537 (OP_SVE_HHHU): New variant set.
1538 (OP_SVE_SSS): New variant set.
1539 (OP_SVE_SSSU): New variant set.
1540 (OP_SVE_SHH): New variant set.
1541 (OP_SVE_SBBU): New variant set.
1542 (OP_SVE_DSS): New variant set.
1543 (OP_SVE_DHHU): New variant set.
1544 (OP_SVE_VMV_HSD_BHS): New variant set.
1545 (OP_SVE_VVU_HSD_BHS): New variant set.
1546 (OP_SVE_VVVU_SD_BH): New variant set.
1547 (OP_SVE_VVVU_BHSD): New variant set.
1548 (OP_SVE_VVV_QHD_DBS): New variant set.
1549 (OP_SVE_VVV_HSD_BHS): New variant set.
1550 (OP_SVE_VVV_HSD_BHS2): New variant set.
1551 (OP_SVE_VVV_BHS_HSD): New variant set.
1552 (OP_SVE_VV_BHS_HSD): New variant set.
1553 (OP_SVE_VVV_SD): New variant set.
1554 (OP_SVE_VVU_BHS_HSD): New variant set.
1555 (OP_SVE_VZVV_SD): New variant set.
1556 (OP_SVE_VZVV_BH): New variant set.
1557 (OP_SVE_VZV_SD): New variant set.
1558 (aarch64_opcode_table): Add sve2 instructions.
1559
28ed815a
MM		 15602019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1561
1562 * aarch64-asm-2.c: Regenerated.
1563 * aarch64-dis-2.c: Regenerated.
1564 * aarch64-opc-2.c: Regenerated.
1565 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1566 for SVE_SHLIMM_UNPRED_22.
1567 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1568 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1569 operand.
1570
fd1dc4a0
MM		 15712019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1572
1573 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1574 sve_size_tsz_bhs iclass encode.
1575 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1576 sve_size_tsz_bhs iclass decode.
1577
31e36ab3
MM		 15782019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1579
1580 * aarch64-asm-2.c: Regenerated.
1581 * aarch64-dis-2.c: Regenerated.
1582 * aarch64-opc-2.c: Regenerated.
1583 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1584 for SVE_Zm4_11_INDEX.
1585 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1586 (fields): Handle SVE_i2h field.
1587 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1588 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1589
1be5f94f
MM		 15902019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1591
1592 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1593 sve_shift_tsz_bhsd iclass encode.
1594 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1595 sve_shift_tsz_bhsd iclass decode.
1596
3c17238b
MM		 15972019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1598
1599 * aarch64-asm-2.c: Regenerated.
1600 * aarch64-dis-2.c: Regenerated.
1601 * aarch64-opc-2.c: Regenerated.
1602 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1603 (aarch64_encode_variant_using_iclass): Handle
1604 sve_shift_tsz_hsd iclass encode.
1605 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1606 sve_shift_tsz_hsd iclass decode.
1607 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1608 for SVE_SHRIMM_UNPRED_22.
1609 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1610 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1611 operand.
1612
cd50a87a
MM		 16132019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1614
1615 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1616 sve_size_013 iclass encode.
1617 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1618 sve_size_013 iclass decode.
1619
3c705960
MM		 16202019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1621
1622 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1623 sve_size_bh iclass encode.
1624 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1625 sve_size_bh iclass decode.
1626
0a57e14f
MM		 16272019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1628
1629 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1630 sve_size_sd2 iclass encode.
1631 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1632 sve_size_sd2 iclass decode.
1633 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1634 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1635
c469c864
MM		 16362019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1637
1638 * aarch64-asm-2.c: Regenerated.
1639 * aarch64-dis-2.c: Regenerated.
1640 * aarch64-opc-2.c: Regenerated.
1641 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1642 for SVE_ADDR_ZX.
1643 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1644 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1645
116adc27
MM		 16462019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1647
1648 * aarch64-asm-2.c: Regenerated.
1649 * aarch64-dis-2.c: Regenerated.
1650 * aarch64-opc-2.c: Regenerated.
1651 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1652 for SVE_Zm3_11_INDEX.
1653 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1654 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1655 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1656 fields.
1657 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1658
3bd82c86
MM		 16592019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1660
1661 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1662 sve_size_hsd2 iclass encode.
1663 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1664 sve_size_hsd2 iclass decode.
1665 * aarch64-opc.c (fields): Handle SVE_size field.
1666 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1667
adccc507
MM		 16682019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1669
1670 * aarch64-asm-2.c: Regenerated.
1671 * aarch64-dis-2.c: Regenerated.
1672 * aarch64-opc-2.c: Regenerated.
1673 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1674 for SVE_IMM_ROT3.
1675 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1676 (fields): Handle SVE_rot3 field.
1677 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1678 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1679
5cd99750
MM		 16802019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1681
1682 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1683 instructions.
1684
7ce2460a
MM		 16852019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1686
1687 * aarch64-tbl.h
1688 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1689 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1690 aarch64_feature_sve2bitperm): New feature sets.
1691 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1692 for feature set addresses.
1693 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1694 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1695
41cee089
FS		 16962019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1697 Faraz Shahbazker <fshahbazker@wavecomp.com>
1698
1699 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1700 argument and set ASE_EVA_R6 appropriately.
1701 (set_default_mips_dis_options): Pass ISA to above.
1702 (parse_mips_dis_option): Likewise.
1703 * mips-opc.c (EVAR6): New macro.
1704 (mips_builtin_opcodes): Add llwpe, scwpe.
1705
b83b4b13
SD		 17062019-05-01 Sudakshina Das <sudi.das@arm.com>
1707
1708 * aarch64-asm-2.c: Regenerated.
1709 * aarch64-dis-2.c: Regenerated.
1710 * aarch64-opc-2.c: Regenerated.
1711 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1712 AARCH64_OPND_TME_UIMM16.
1713 (aarch64_print_operand): Likewise.
1714 * aarch64-tbl.h (QL_IMM_NIL): New.
1715 (TME): New.
1716 (_TME_INSN): New.
1717 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1718
4a90ce95
JD		 17192019-04-29 John Darrington <john@darrington.wattle.id.au>
1720
1721 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1722
a45328b9
AB		 17232019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1724 Faraz Shahbazker <fshahbazker@wavecomp.com>
1725
1726 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1727
d10be0cb
JD		 17282019-04-24 John Darrington <john@darrington.wattle.id.au>
1729
1730 * s12z-opc.h: Add extern "C" bracketing to help
1731 users who wish to use this interface in c++ code.
1732
a679f24e
JD		 17332019-04-24 John Darrington <john@darrington.wattle.id.au>
1734
1735 * s12z-opc.c (bm_decode): Handle bit map operations with the
1736 "reserved0" mode.
1737
32c36c3c
AV		 17382019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1739
1740 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1741 specifier. Add entries for VLDR and VSTR of system registers.
1742 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1743 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1744 of %J and %K format specifier.
1745
efd6b359
AV		 17462019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1747
1748 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1749 Add new entries for VSCCLRM instruction.
1750 (print_insn_coprocessor): Handle new %C format control code.
1751
6b0dd094
AV		 17522019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1753
1754 * arm-dis.c (enum isa): New enum.
1755 (struct sopcode32): New structure.
1756 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1757 set isa field of all current entries to ANY.
1758 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1759 Only match an entry if its isa field allows the current mode.
1760
4b5a202f
AV		 17612019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1762
1763 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1764 CLRM.
1765 (print_insn_thumb32): Add logic to print %n CLRM register list.
1766
60f993ce
AV		 17672019-04-15 Sudakshina Das <sudi.das@arm.com>
1768
1769 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1770 and %Q patterns.
1771
f6b2b12d
AV		 17722019-04-15 Sudakshina Das <sudi.das@arm.com>
1773
1774 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1775 (print_insn_thumb32): Edit the switch case for %Z.
1776
1889da70
AV		 17772019-04-15 Sudakshina Das <sudi.das@arm.com>
1778
1779 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1780
65d1bc05
AV		 17812019-04-15 Sudakshina Das <sudi.das@arm.com>
1782
1783 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1784
1caf72a5
AV		 17852019-04-15 Sudakshina Das <sudi.das@arm.com>
1786
1787 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1788
f1c7f421
AV		 17892019-04-15 Sudakshina Das <sudi.das@arm.com>
1790
1791 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1792 Arm register with r13 and r15 unpredictable.
1793 (thumb32_opcodes): New instructions for bfx and bflx.
1794
4389b29a
AV		 17952019-04-15 Sudakshina Das <sudi.das@arm.com>
1796
1797 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1798
e5d6e09e
AV		 17992019-04-15 Sudakshina Das <sudi.das@arm.com>
1800
1801 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1802
e12437dc
AV		 18032019-04-15 Sudakshina Das <sudi.das@arm.com>
1804
1805 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1806
031254f2
AV		 18072019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1808
1809 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1810
e5a557ac
JD		 18112019-04-12 John Darrington <john@darrington.wattle.id.au>
1812
1813 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1814 "optr". ("operator" is a reserved word in c++).
1815
bd7ceb8d
SD		 18162019-04-11 Sudakshina Das <sudi.das@arm.com>
1817
1818 * aarch64-opc.c (aarch64_print_operand): Add case for
1819 AARCH64_OPND_Rt_SP.
1820 (verify_constraints): Likewise.
1821 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1822 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1823 to accept Rt|SP as first operand.
1824 (AARCH64_OPERANDS): Add new Rt_SP.
1825 * aarch64-asm-2.c: Regenerated.
1826 * aarch64-dis-2.c: Regenerated.
1827 * aarch64-opc-2.c: Regenerated.
1828
e54010f1
SD		 18292019-04-11 Sudakshina Das <sudi.das@arm.com>
1830
1831 * aarch64-asm-2.c: Regenerated.
1832 * aarch64-dis-2.c: Likewise.
1833 * aarch64-opc-2.c: Likewise.
1834 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1835
7e96e219
RS		 18362019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1837
1838 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1839
6f2791d5
L		 18402019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1841
1842 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1843 * i386-init.h: Regenerated.
1844
e392bad3
AM		 18452019-04-07 Alan Modra <amodra@gmail.com>
1846
1847 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1848 op_separator to control printing of spaces, comma and parens
1849 rather than need_comma, need_paren and spaces vars.
1850
dffaa15c
AM		 18512019-04-07 Alan Modra <amodra@gmail.com>
1852
1853 PR 24421
1854 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1855 (print_insn_neon, print_insn_arm): Likewise.
1856
d6aab7a1
XG		 18572019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1858
1859 * i386-dis-evex.h (evex_table): Updated to support BF16
1860 instructions.
1861 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1862 and EVEX_W_0F3872_P_3.
1863 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1864 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1865 * i386-opc.h (enum): Add CpuAVX512_BF16.
1866 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1867 * i386-opc.tbl: Add AVX512 BF16 instructions.
1868 * i386-init.h: Regenerated.
1869 * i386-tbl.h: Likewise.
1870
66e85460
AM		 18712019-04-05 Alan Modra <amodra@gmail.com>
1872
1873 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1874 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1875 to favour printing of "-" branch hint when using the "y" bit.
1876 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1877
c2b1c275
AM		 18782019-04-05 Alan Modra <amodra@gmail.com>
1879
1880 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1881 opcode until first operand is output.
1882
aae9718e
PB		 18832019-04-04 Peter Bergner <bergner@linux.ibm.com>
1884
1885 PR gas/24349
1886 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1887 (valid_bo_post_v2): Add support for 'at' branch hints.
1888 (insert_bo): Only error on branch on ctr.
1889 (get_bo_hint_mask): New function.
1890 (insert_boe): Add new 'branch_taken' formal argument. Add support
1891 for inserting 'at' branch hints.
1892 (extract_boe): Add new 'branch_taken' formal argument. Add support
1893 for extracting 'at' branch hints.
1894 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1895 (BOE): Delete operand.
1896 (BOM, BOP): New operands.
1897 (RM): Update value.
1898 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1899 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1900 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1901 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1902 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1903 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1904 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1905 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1906 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1907 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1908 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1909 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1910 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1911 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1912 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1913 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1914 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1915 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1916 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1917 bttarl+>: New extended mnemonics.
1918
96a86c01
AM		 19192019-03-28 Alan Modra <amodra@gmail.com>
1920
1921 PR 24390
1922 * ppc-opc.c (BTF): Define.
1923 (powerpc_opcodes): Use for mtfsb*.
1924 * ppc-dis.c (print_insn_powerpc): Print fields with both
1925 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1926
796d6298
TC		 19272019-03-25 Tamar Christina <tamar.christina@arm.com>
1928
1929 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1930 (mapping_symbol_for_insn): Implement new algorithm.
1931 (print_insn): Remove duplicate code.
1932
60df3720
TC		 19332019-03-25 Tamar Christina <tamar.christina@arm.com>
1934
1935 * aarch64-dis.c (print_insn_aarch64):
1936 Implement override.
1937
51457761
TC		 19382019-03-25 Tamar Christina <tamar.christina@arm.com>
1939
1940 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1941 order.
1942
53b2f36b
TC		 19432019-03-25 Tamar Christina <tamar.christina@arm.com>
1944
1945 * aarch64-dis.c (last_stop_offset): New.
1946 (print_insn_aarch64): Use stop_offset.
1947
89199bb5
L		 19482019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1949
1950 PR gas/24359
1951 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1952 CPU_ANY_AVX2_FLAGS.
1953 * i386-init.h: Regenerated.
1954
97ed31ae
L		 19552019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1956
1957 PR gas/24348
1958 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1959 vmovdqu16, vmovdqu32 and vmovdqu64.
1960 * i386-tbl.h: Regenerated.
1961
0919bfe9
AK		 19622019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1963
1964 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1965 from vstrszb, vstrszh, and vstrszf.
1966
19672019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1968
1969 * s390-opc.txt: Add instruction descriptions.
1970
21820ebe
JW		 19712019-02-08 Jim Wilson <jimw@sifive.com>
1972
1973 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1974 <bne>: Likewise.
1975
f7dd2fb2
TC		 19762019-02-07 Tamar Christina <tamar.christina@arm.com>
1977
1978 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1979
6456d318
TC		 19802019-02-07 Tamar Christina <tamar.christina@arm.com>
1981
1982 PR binutils/23212
1983 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1984 * aarch64-opc.c (verify_elem_sd): New.
1985 (fields): Add FLD_sz entr.
1986 * aarch64-tbl.h (_SIMD_INSN): New.
1987 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1988 fmulx scalar and vector by element isns.
1989
4a83b610
NC		 19902019-02-07 Nick Clifton <nickc@redhat.com>
1991
1992 * po/sv.po: Updated Swedish translation.
1993
fc60b8c8
AK		 19942019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1995
1996 * s390-mkopc.c (main): Accept arch13 as cpu string.
1997 * s390-opc.c: Add new instruction formats and instruction opcode
1998 masks.
1999 * s390-opc.txt: Add new arch13 instructions.
2000
e10620d3
TC		 20012019-01-25 Sudakshina Das <sudi.das@arm.com>
2002
2003 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2004 (aarch64_opcode): Change encoding for stg, stzg
2005 st2g and st2zg.
2006 * aarch64-asm-2.c: Regenerated.
2007 * aarch64-dis-2.c: Regenerated.
2008 * aarch64-opc-2.c: Regenerated.
2009
20a4ca55
SD		 20102019-01-25 Sudakshina Das <sudi.das@arm.com>
2011
2012 * aarch64-asm-2.c: Regenerated.
2013 * aarch64-dis-2.c: Likewise.
2014 * aarch64-opc-2.c: Likewise.
2015 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2016
550fd7bf
SD		 20172019-01-25 Sudakshina Das <sudi.das@arm.com>
2018 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2019
2020 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2021 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2022 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2023 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2024 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2025 case for ldstgv_indexed.
2026 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2027 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2028 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2029 * aarch64-asm-2.c: Regenerated.
2030 * aarch64-dis-2.c: Regenerated.
2031 * aarch64-opc-2.c: Regenerated.
2032
d9938630
NC		 20332019-01-23 Nick Clifton <nickc@redhat.com>
2034
2035 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2036
375cd423
NC		 20372019-01-21 Nick Clifton <nickc@redhat.com>
2038
2039 * po/de.po: Updated German translation.
2040 * po/uk.po: Updated Ukranian translation.
2041
57299f48
CX		 20422019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2043 * mips-dis.c (mips_arch_choices): Fix typo in
2044 gs464, gs464e and gs264e descriptors.
2045
f48dfe41
NC		 20462019-01-19 Nick Clifton <nickc@redhat.com>
2047
2048 * configure: Regenerate.
2049 * po/opcodes.pot: Regenerate.
2050
f974f26c
NC		 20512018-06-24 Nick Clifton <nickc@redhat.com>
2052
2053 2.32 branch created.
2054
39f286cd
JD		 20552019-01-09 John Darrington <john@darrington.wattle.id.au>
2056
448b8ca8
JD		 2057 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2058 if it is null.
2059 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2060 zero.
2061
3107326d
AP		 20622019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2063
2064 * configure: Regenerate.
2065
7e9ca91e
AM		 20662019-01-07 Alan Modra <amodra@gmail.com>
2067
2068 * configure: Regenerate.
2069 * po/POTFILES.in: Regenerate.
2070
ef1ad42b
JD		 20712019-01-03 John Darrington <john@darrington.wattle.id.au>
2072
2073 * s12z-opc.c: New file.
2074 * s12z-opc.h: New file.
2075 * s12z-dis.c: Removed all code not directly related to display
2076 of instructions. Used the interface provided by the new files
2077 instead.
2078 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2079 * Makefile.in: Regenerate.
ef1ad42b 2080 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2081 * configure: Regenerate.
ef1ad42b 2082
82704155
AM		 20832019-01-01 Alan Modra <amodra@gmail.com>
2084
2085 Update year range in copyright notice of all files.
2086
d5c04e1b 2087For older changes see ChangeLog-2018
3499769a 2088\f
d5c04e1b 2089Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2090
2091Copying and distribution of this file, with or without modification,
2092are permitted in any medium without royalty provided the copyright
2093notice and this notice are preserved.
2094
2095Local Variables:
2096mode: change-log
2097left-margin: 8
2098fill-column: 74
2099version-control: never
2100End:
GDB Binutils - Deliverables
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