Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
b3adc24a | 2 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
5b872f7d | 40 | #include "safe-ctype.h" |
252b5132 RH |
41 | |
42 | #include <setjmp.h> | |
43 | ||
26ca5450 AJ |
44 | static int print_insn (bfd_vma, disassemble_info *); |
45 | static void dofloat (int); | |
46 | static void OP_ST (int, int); | |
47 | static void OP_STi (int, int); | |
48 | static int putop (const char *, int); | |
49 | static void oappend (const char *); | |
50 | static void append_seg (void); | |
51 | static void OP_indirE (int, int); | |
52 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 53 | static void OP_E_register (int, int); |
c1e679ec | 54 | static void OP_E_memory (int, int); |
5d669648 | 55 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
56 | static void OP_E (int, int); |
57 | static void OP_G (int, int); | |
58 | static bfd_vma get64 (void); | |
59 | static bfd_signed_vma get32 (void); | |
60 | static bfd_signed_vma get32s (void); | |
61 | static int get16 (void); | |
62 | static void set_op (bfd_vma, int); | |
b844680a | 63 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
64 | static void OP_REG (int, int); |
65 | static void OP_IMREG (int, int); | |
66 | static void OP_I (int, int); | |
67 | static void OP_I64 (int, int); | |
68 | static void OP_sI (int, int); | |
69 | static void OP_J (int, int); | |
70 | static void OP_SEG (int, int); | |
71 | static void OP_DIR (int, int); | |
72 | static void OP_OFF (int, int); | |
73 | static void OP_OFF64 (int, int); | |
74 | static void ptr_reg (int, int); | |
75 | static void OP_ESreg (int, int); | |
76 | static void OP_DSreg (int, int); | |
77 | static void OP_C (int, int); | |
78 | static void OP_D (int, int); | |
79 | static void OP_T (int, int); | |
6f74c397 | 80 | static void OP_R (int, int); |
26ca5450 AJ |
81 | static void OP_MMX (int, int); |
82 | static void OP_XMM (int, int); | |
83 | static void OP_EM (int, int); | |
84 | static void OP_EX (int, int); | |
4d9567e0 MM |
85 | static void OP_EMC (int,int); |
86 | static void OP_MXC (int,int); | |
26ca5450 AJ |
87 | static void OP_MS (int, int); |
88 | static void OP_XS (int, int); | |
cc0ec051 | 89 | static void OP_M (int, int); |
c0f3af97 L |
90 | static void OP_VEX (int, int); |
91 | static void OP_EX_Vex (int, int); | |
922d8de8 | 92 | static void OP_EX_VexW (int, int); |
a683cc34 | 93 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 94 | static void OP_XMM_Vex (int, int); |
922d8de8 | 95 | static void OP_XMM_VexW (int, int); |
43234a1e | 96 | static void OP_Rounding (int, int); |
c0f3af97 L |
97 | static void OP_REG_VexI4 (int, int); |
98 | static void PCLMUL_Fixup (int, int); | |
c0f3af97 | 99 | static void VCMP_Fixup (int, int); |
43234a1e | 100 | static void VPCMP_Fixup (int, int); |
be92cb14 | 101 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 102 | static void OP_0f07 (int, int); |
b844680a L |
103 | static void OP_Monitor (int, int); |
104 | static void OP_Mwait (int, int); | |
46e883c5 L |
105 | static void NOP_Fixup1 (int, int); |
106 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 107 | static void OP_3DNowSuffix (int, int); |
ad19981d | 108 | static void CMP_Fixup (int, int); |
26ca5450 | 109 | static void BadOp (void); |
35c52694 | 110 | static void REP_Fixup (int, int); |
d835a58b | 111 | static void SEP_Fixup (int, int); |
7e8b059b | 112 | static void BND_Fixup (int, int); |
04ef582a | 113 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
114 | static void HLE_Fixup1 (int, int); |
115 | static void HLE_Fixup2 (int, int); | |
116 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 117 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 118 | static void XMM_Fixup (int, int); |
381d071f | 119 | static void CRC32_Fixup (int, int); |
eacc9c89 | 120 | static void FXSAVE_Fixup (int, int); |
15c7c1d8 | 121 | static void PCMPESTR_Fixup (int, int); |
f88c9eb0 SP |
122 | static void OP_LWPCB_E (int, int); |
123 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
124 | static void OP_Vex_2src_1 (int, int); |
125 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 126 | |
f1f8f695 | 127 | static void MOVBE_Fixup (int, int); |
bc31405e | 128 | static void MOVSXD_Fixup (int, int); |
252b5132 | 129 | |
43234a1e L |
130 | static void OP_Mask (int, int); |
131 | ||
6608db57 | 132 | struct dis_private { |
252b5132 RH |
133 | /* Points to first byte not fetched. */ |
134 | bfd_byte *max_fetched; | |
0b1cf022 | 135 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 136 | bfd_vma insn_start; |
e396998b | 137 | int orig_sizeflag; |
8df14d78 | 138 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
139 | }; |
140 | ||
cb712a9e L |
141 | enum address_mode |
142 | { | |
143 | mode_16bit, | |
144 | mode_32bit, | |
145 | mode_64bit | |
146 | }; | |
147 | ||
148 | enum address_mode address_mode; | |
52b15da3 | 149 | |
5076851f ILT |
150 | /* Flags for the prefixes for the current instruction. See below. */ |
151 | static int prefixes; | |
152 | ||
52b15da3 JH |
153 | /* REX prefix the current instruction. See below. */ |
154 | static int rex; | |
155 | /* Bits of REX we've already used. */ | |
156 | static int rex_used; | |
52b15da3 JH |
157 | /* Mark parts used in the REX prefix. When we are testing for |
158 | empty prefix (for 8bit register REX extension), just mask it | |
159 | out. Otherwise test for REX bit is excuse for existence of REX | |
160 | only in case value is nonzero. */ | |
161 | #define USED_REX(value) \ | |
162 | { \ | |
163 | if (value) \ | |
161a04f6 L |
164 | { \ |
165 | if ((rex & value)) \ | |
166 | rex_used |= (value) | REX_OPCODE; \ | |
167 | } \ | |
52b15da3 | 168 | else \ |
161a04f6 | 169 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
170 | } |
171 | ||
7d421014 ILT |
172 | /* Flags for prefixes which we somehow handled when printing the |
173 | current instruction. */ | |
174 | static int used_prefixes; | |
175 | ||
5076851f ILT |
176 | /* Flags stored in PREFIXES. */ |
177 | #define PREFIX_REPZ 1 | |
178 | #define PREFIX_REPNZ 2 | |
179 | #define PREFIX_LOCK 4 | |
180 | #define PREFIX_CS 8 | |
181 | #define PREFIX_SS 0x10 | |
182 | #define PREFIX_DS 0x20 | |
183 | #define PREFIX_ES 0x40 | |
184 | #define PREFIX_FS 0x80 | |
185 | #define PREFIX_GS 0x100 | |
186 | #define PREFIX_DATA 0x200 | |
187 | #define PREFIX_ADDR 0x400 | |
188 | #define PREFIX_FWAIT 0x800 | |
189 | ||
252b5132 RH |
190 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
191 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
192 | on error. */ | |
193 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 194 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
195 | ? 1 : fetch_data ((info), (addr))) |
196 | ||
197 | static int | |
26ca5450 | 198 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
199 | { |
200 | int status; | |
6608db57 | 201 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
202 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
203 | ||
0b1cf022 | 204 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
205 | status = (*info->read_memory_func) (start, |
206 | priv->max_fetched, | |
207 | addr - priv->max_fetched, | |
208 | info); | |
209 | else | |
210 | status = -1; | |
252b5132 RH |
211 | if (status != 0) |
212 | { | |
7d421014 | 213 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
214 | print_insn_i386 will do something sensible. Otherwise, print |
215 | an error. We do that here because this is where we know | |
216 | STATUS. */ | |
7d421014 | 217 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 218 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 219 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
220 | } |
221 | else | |
222 | priv->max_fetched = addr; | |
223 | return 1; | |
224 | } | |
225 | ||
bf890a93 | 226 | /* Possible values for prefix requirement. */ |
507bd325 L |
227 | #define PREFIX_IGNORED_SHIFT 16 |
228 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
229 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
232 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
233 | ||
234 | /* Opcode prefixes. */ | |
235 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
236 | | PREFIX_REPNZ \ | |
237 | | PREFIX_DATA) | |
238 | ||
239 | /* Prefixes ignored. */ | |
240 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
241 | | PREFIX_IGNORED_REPNZ \ | |
242 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 243 | |
ce518a5f | 244 | #define XX { NULL, 0 } |
507bd325 | 245 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
246 | |
247 | #define Eb { OP_E, b_mode } | |
7e8b059b | 248 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 249 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 250 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 251 | #define Ev { OP_E, v_mode } |
de89d0a3 | 252 | #define Eva { OP_E, va_mode } |
7e8b059b | 253 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 254 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
255 | #define Ed { OP_E, d_mode } |
256 | #define Edq { OP_E, dq_mode } | |
257 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 258 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
259 | #define Edb { OP_E, db_mode } |
260 | #define Edw { OP_E, dw_mode } | |
42903f7f | 261 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 262 | #define Eq { OP_E, q_mode } |
07f5af7d | 263 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
264 | #define indirEp { OP_indirE, f_mode } |
265 | #define stackEv { OP_E, stack_v_mode } | |
266 | #define Em { OP_E, m_mode } | |
267 | #define Ew { OP_E, w_mode } | |
268 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 269 | #define Ma { OP_M, a_mode } |
b844680a | 270 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 271 | #define Md { OP_M, d_mode } |
f1f8f695 | 272 | #define Mo { OP_M, o_mode } |
ce518a5f L |
273 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
274 | #define Mq { OP_M, q_mode } | |
d276ec69 | 275 | #define Mv_bnd { OP_M, v_bndmk_mode } |
4ee52178 | 276 | #define Mx { OP_M, x_mode } |
c0f3af97 | 277 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 278 | #define Gb { OP_G, b_mode } |
7e8b059b | 279 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
280 | #define Gv { OP_G, v_mode } |
281 | #define Gd { OP_G, d_mode } | |
282 | #define Gdq { OP_G, dq_mode } | |
283 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 284 | #define Gva { OP_G, va_mode } |
ce518a5f | 285 | #define Gw { OP_G, w_mode } |
6f74c397 | 286 | #define Rd { OP_R, d_mode } |
43234a1e | 287 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 288 | #define Rm { OP_R, m_mode } |
ce518a5f L |
289 | #define Ib { OP_I, b_mode } |
290 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 291 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 292 | #define Iv { OP_I, v_mode } |
7bb15c6f | 293 | #define sIv { OP_sI, v_mode } |
ce518a5f | 294 | #define Iv64 { OP_I64, v_mode } |
c1dc7af5 | 295 | #define Id { OP_I, d_mode } |
ce518a5f L |
296 | #define Iw { OP_I, w_mode } |
297 | #define I1 { OP_I, const_1_mode } | |
298 | #define Jb { OP_J, b_mode } | |
299 | #define Jv { OP_J, v_mode } | |
376cd056 | 300 | #define Jdqw { OP_J, dqw_mode } |
ce518a5f L |
301 | #define Cm { OP_C, m_mode } |
302 | #define Dm { OP_D, m_mode } | |
303 | #define Td { OP_T, d_mode } | |
b844680a | 304 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
305 | |
306 | #define RMeAX { OP_REG, eAX_reg } | |
307 | #define RMeBX { OP_REG, eBX_reg } | |
308 | #define RMeCX { OP_REG, eCX_reg } | |
309 | #define RMeDX { OP_REG, eDX_reg } | |
310 | #define RMeSP { OP_REG, eSP_reg } | |
311 | #define RMeBP { OP_REG, eBP_reg } | |
312 | #define RMeSI { OP_REG, eSI_reg } | |
313 | #define RMeDI { OP_REG, eDI_reg } | |
314 | #define RMrAX { OP_REG, rAX_reg } | |
315 | #define RMrBX { OP_REG, rBX_reg } | |
316 | #define RMrCX { OP_REG, rCX_reg } | |
317 | #define RMrDX { OP_REG, rDX_reg } | |
318 | #define RMrSP { OP_REG, rSP_reg } | |
319 | #define RMrBP { OP_REG, rBP_reg } | |
320 | #define RMrSI { OP_REG, rSI_reg } | |
321 | #define RMrDI { OP_REG, rDI_reg } | |
322 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
323 | #define RMCL { OP_REG, cl_reg } |
324 | #define RMDL { OP_REG, dl_reg } | |
325 | #define RMBL { OP_REG, bl_reg } | |
326 | #define RMAH { OP_REG, ah_reg } | |
327 | #define RMCH { OP_REG, ch_reg } | |
328 | #define RMDH { OP_REG, dh_reg } | |
329 | #define RMBH { OP_REG, bh_reg } | |
330 | #define RMAX { OP_REG, ax_reg } | |
331 | #define RMDX { OP_REG, dx_reg } | |
332 | ||
333 | #define eAX { OP_IMREG, eAX_reg } | |
334 | #define eBX { OP_IMREG, eBX_reg } | |
335 | #define eCX { OP_IMREG, eCX_reg } | |
336 | #define eDX { OP_IMREG, eDX_reg } | |
337 | #define eSP { OP_IMREG, eSP_reg } | |
338 | #define eBP { OP_IMREG, eBP_reg } | |
339 | #define eSI { OP_IMREG, eSI_reg } | |
340 | #define eDI { OP_IMREG, eDI_reg } | |
341 | #define AL { OP_IMREG, al_reg } | |
342 | #define CL { OP_IMREG, cl_reg } | |
343 | #define DL { OP_IMREG, dl_reg } | |
344 | #define BL { OP_IMREG, bl_reg } | |
345 | #define AH { OP_IMREG, ah_reg } | |
346 | #define CH { OP_IMREG, ch_reg } | |
347 | #define DH { OP_IMREG, dh_reg } | |
348 | #define BH { OP_IMREG, bh_reg } | |
349 | #define AX { OP_IMREG, ax_reg } | |
350 | #define DX { OP_IMREG, dx_reg } | |
351 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
352 | #define indirDX { OP_IMREG, indir_dx_reg } | |
353 | ||
354 | #define Sw { OP_SEG, w_mode } | |
355 | #define Sv { OP_SEG, v_mode } | |
356 | #define Ap { OP_DIR, 0 } | |
357 | #define Ob { OP_OFF64, b_mode } | |
358 | #define Ov { OP_OFF64, v_mode } | |
359 | #define Xb { OP_DSreg, eSI_reg } | |
360 | #define Xv { OP_DSreg, eSI_reg } | |
361 | #define Xz { OP_DSreg, eSI_reg } | |
362 | #define Yb { OP_ESreg, eDI_reg } | |
363 | #define Yv { OP_ESreg, eDI_reg } | |
364 | #define DSBX { OP_DSreg, eBX_reg } | |
365 | ||
366 | #define es { OP_REG, es_reg } | |
367 | #define ss { OP_REG, ss_reg } | |
368 | #define cs { OP_REG, cs_reg } | |
369 | #define ds { OP_REG, ds_reg } | |
370 | #define fs { OP_REG, fs_reg } | |
371 | #define gs { OP_REG, gs_reg } | |
372 | ||
373 | #define MX { OP_MMX, 0 } | |
374 | #define XM { OP_XMM, 0 } | |
539f890d | 375 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 376 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 377 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 378 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 379 | #define EM { OP_EM, v_mode } |
b6169b20 | 380 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 381 | #define EMd { OP_EM, d_mode } |
14051056 | 382 | #define EMx { OP_EM, x_mode } |
53467f57 | 383 | #define EXbScalar { OP_EX, b_scalar_mode } |
8976381e | 384 | #define EXw { OP_EX, w_mode } |
53467f57 | 385 | #define EXwScalar { OP_EX, w_scalar_mode } |
09a2c6cf | 386 | #define EXd { OP_EX, d_mode } |
fa99fab2 | 387 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 388 | #define EXq { OP_EX, q_mode } |
b6169b20 | 389 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 390 | #define EXx { OP_EX, x_mode } |
b6169b20 | 391 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 392 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 393 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 394 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 395 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
396 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
397 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
398 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
399 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
400 | #define EXxmmdw { OP_EX, xmmdw_mode } | |
401 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 402 | #define EXymmq { OP_EX, ymmq_mode } |
1c480963 | 403 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
404 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
405 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
406 | #define MS { OP_MS, v_mode } |
407 | #define XS { OP_XS, v_mode } | |
09335d05 | 408 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 409 | #define MXC { OP_MXC, 0 } |
ce518a5f | 410 | #define OPSUF { OP_3DNowSuffix, 0 } |
d835a58b | 411 | #define SEP { SEP_Fixup, 0 } |
ad19981d | 412 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 413 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 414 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
415 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
416 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 417 | |
c0f3af97 | 418 | #define Vex { OP_VEX, vex_mode } |
539f890d | 419 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 420 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
421 | #define Vex128 { OP_VEX, vex128_mode } |
422 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 423 | #define VexGdq { OP_VEX, dq_mode } |
539f890d | 424 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
539f890d | 425 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
426 | #define EXVexW { OP_EX_VexW, x_mode } |
427 | #define EXdVexW { OP_EX_VexW, d_mode } | |
428 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 429 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
539f890d | 430 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 431 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
432 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
433 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
c0f3af97 | 434 | #define VCMP { VCMP_Fixup, 0 } |
43234a1e | 435 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 436 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
437 | |
438 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
70df6fc9 | 439 | #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } |
43234a1e L |
440 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
441 | ||
442 | #define XMask { OP_Mask, mask_mode } | |
443 | #define MaskG { OP_G, mask_mode } | |
444 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 445 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
446 | #define MaskR { OP_R, mask_mode } |
447 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 448 | |
6c30d220 | 449 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 450 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 451 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 452 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 453 | |
35c52694 | 454 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
455 | #define Xbr { REP_Fixup, eSI_reg } |
456 | #define Xvr { REP_Fixup, eSI_reg } | |
457 | #define Ybr { REP_Fixup, eDI_reg } | |
458 | #define Yvr { REP_Fixup, eDI_reg } | |
459 | #define Yzr { REP_Fixup, eDI_reg } | |
460 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
461 | #define ALr { REP_Fixup, al_reg } | |
462 | #define eAXr { REP_Fixup, eAX_reg } | |
463 | ||
42164a71 L |
464 | /* Used handle HLE prefix for lockable instructions. */ |
465 | #define Ebh1 { HLE_Fixup1, b_mode } | |
466 | #define Evh1 { HLE_Fixup1, v_mode } | |
467 | #define Ebh2 { HLE_Fixup2, b_mode } | |
468 | #define Evh2 { HLE_Fixup2, v_mode } | |
469 | #define Ebh3 { HLE_Fixup3, b_mode } | |
470 | #define Evh3 { HLE_Fixup3, v_mode } | |
471 | ||
7e8b059b | 472 | #define BND { BND_Fixup, 0 } |
04ef582a | 473 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 474 | |
ce518a5f L |
475 | #define cond_jump_flag { NULL, cond_jump_mode } |
476 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 477 | |
252b5132 | 478 | /* bits in sizeflag */ |
252b5132 | 479 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
480 | #define AFLAG 2 |
481 | #define DFLAG 1 | |
482 | ||
51e7da1b L |
483 | enum |
484 | { | |
485 | /* byte operand */ | |
486 | b_mode = 1, | |
487 | /* byte operand with operand swapped */ | |
3873ba12 | 488 | b_swap_mode, |
e3949f17 L |
489 | /* byte operand, sign extend like 'T' suffix */ |
490 | b_T_mode, | |
51e7da1b | 491 | /* operand size depends on prefixes */ |
3873ba12 | 492 | v_mode, |
51e7da1b | 493 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 494 | v_swap_mode, |
de89d0a3 IT |
495 | /* operand size depends on address prefix */ |
496 | va_mode, | |
51e7da1b | 497 | /* word operand */ |
3873ba12 | 498 | w_mode, |
51e7da1b | 499 | /* double word operand */ |
3873ba12 | 500 | d_mode, |
51e7da1b | 501 | /* double word operand with operand swapped */ |
3873ba12 | 502 | d_swap_mode, |
51e7da1b | 503 | /* quad word operand */ |
3873ba12 | 504 | q_mode, |
51e7da1b | 505 | /* quad word operand with operand swapped */ |
3873ba12 | 506 | q_swap_mode, |
51e7da1b | 507 | /* ten-byte operand */ |
3873ba12 | 508 | t_mode, |
43234a1e L |
509 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
510 | broadcast enabled. */ | |
3873ba12 | 511 | x_mode, |
43234a1e L |
512 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
513 | evex_x_gscat_mode, | |
514 | /* Similar to x_mode, but with disabled broadcast. */ | |
515 | evex_x_nobcst_mode, | |
516 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
517 | in EVEX. */ | |
3873ba12 | 518 | x_swap_mode, |
51e7da1b | 519 | /* 16-byte XMM operand */ |
3873ba12 | 520 | xmm_mode, |
43234a1e L |
521 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
522 | memory operand (depending on vector length). Broadcast isn't | |
523 | allowed. */ | |
3873ba12 | 524 | xmmq_mode, |
43234a1e L |
525 | /* Same as xmmq_mode, but broadcast is allowed. */ |
526 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
527 | /* XMM register or byte memory operand */ |
528 | xmm_mb_mode, | |
529 | /* XMM register or word memory operand */ | |
530 | xmm_mw_mode, | |
531 | /* XMM register or double word memory operand */ | |
532 | xmm_md_mode, | |
533 | /* XMM register or quad word memory operand */ | |
534 | xmm_mq_mode, | |
43234a1e | 535 | /* 16-byte XMM, word, double word or quad word operand. */ |
6c30d220 | 536 | xmmdw_mode, |
43234a1e | 537 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 538 | xmmqd_mode, |
43234a1e L |
539 | /* 32-byte YMM operand */ |
540 | ymm_mode, | |
541 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 542 | ymmq_mode, |
6c30d220 L |
543 | /* 32-byte YMM or 16-byte word operand */ |
544 | ymmxmm_mode, | |
51e7da1b | 545 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 546 | m_mode, |
51e7da1b | 547 | /* pair of v_mode operands */ |
3873ba12 L |
548 | a_mode, |
549 | cond_jump_mode, | |
550 | loop_jcxz_mode, | |
bc31405e | 551 | movsxd_mode, |
7e8b059b | 552 | v_bnd_mode, |
d276ec69 JB |
553 | /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ |
554 | v_bndmk_mode, | |
51e7da1b | 555 | /* operand size depends on REX prefixes. */ |
3873ba12 | 556 | dq_mode, |
376cd056 JB |
557 | /* registers like dq_mode, memory like w_mode, displacements like |
558 | v_mode without considering Intel64 ISA. */ | |
3873ba12 | 559 | dqw_mode, |
9f79e886 | 560 | /* bounds operand */ |
7e8b059b | 561 | bnd_mode, |
9f79e886 JB |
562 | /* bounds operand with operand swapped */ |
563 | bnd_swap_mode, | |
51e7da1b | 564 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
565 | f_mode, |
566 | const_1_mode, | |
07f5af7d L |
567 | /* v_mode for indirect branch opcodes. */ |
568 | indir_v_mode, | |
51e7da1b | 569 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 570 | stack_v_mode, |
51e7da1b | 571 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 572 | z_mode, |
51e7da1b | 573 | /* 16-byte operand */ |
3873ba12 | 574 | o_mode, |
51e7da1b | 575 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 576 | dqb_mode, |
1ba585e8 IT |
577 | /* registers like d_mode, memory like b_mode. */ |
578 | db_mode, | |
579 | /* registers like d_mode, memory like w_mode. */ | |
580 | dw_mode, | |
51e7da1b | 581 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 582 | dqd_mode, |
51e7da1b | 583 | /* normal vex mode */ |
3873ba12 | 584 | vex_mode, |
51e7da1b | 585 | /* 128bit vex mode */ |
3873ba12 | 586 | vex128_mode, |
51e7da1b | 587 | /* 256bit vex mode */ |
3873ba12 | 588 | vex256_mode, |
d55ee72f | 589 | |
825bd36c | 590 | /* Operand size depends on the VEX.W bit, with VSIB dword indices. */ |
6c30d220 | 591 | vex_vsib_d_w_dq_mode, |
5fc35d96 IT |
592 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
593 | vex_vsib_d_w_d_mode, | |
825bd36c | 594 | /* Operand size depends on the VEX.W bit, with VSIB qword indices. */ |
6c30d220 | 595 | vex_vsib_q_w_dq_mode, |
5fc35d96 IT |
596 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
597 | vex_vsib_q_w_d_mode, | |
6c30d220 | 598 | |
539f890d L |
599 | /* scalar, ignore vector length. */ |
600 | scalar_mode, | |
53467f57 IT |
601 | /* like b_mode, ignore vector length. */ |
602 | b_scalar_mode, | |
603 | /* like w_mode, ignore vector length. */ | |
604 | w_scalar_mode, | |
539f890d L |
605 | /* like d_swap_mode, ignore vector length. */ |
606 | d_scalar_swap_mode, | |
539f890d L |
607 | /* like q_swap_mode, ignore vector length. */ |
608 | q_scalar_swap_mode, | |
609 | /* like vex_mode, ignore vector length. */ | |
610 | vex_scalar_mode, | |
825bd36c | 611 | /* Operand size depends on the VEX.W bit, ignore vector length. */ |
1c480963 | 612 | vex_scalar_w_dq_mode, |
539f890d | 613 | |
43234a1e L |
614 | /* Static rounding. */ |
615 | evex_rounding_mode, | |
70df6fc9 L |
616 | /* Static rounding, 64-bit mode only. */ |
617 | evex_rounding_64_mode, | |
43234a1e L |
618 | /* Supress all exceptions. */ |
619 | evex_sae_mode, | |
620 | ||
621 | /* Mask register operand. */ | |
622 | mask_mode, | |
1ba585e8 IT |
623 | /* Mask register operand. */ |
624 | mask_bd_mode, | |
43234a1e | 625 | |
3873ba12 L |
626 | es_reg, |
627 | cs_reg, | |
628 | ss_reg, | |
629 | ds_reg, | |
630 | fs_reg, | |
631 | gs_reg, | |
d55ee72f | 632 | |
3873ba12 L |
633 | eAX_reg, |
634 | eCX_reg, | |
635 | eDX_reg, | |
636 | eBX_reg, | |
637 | eSP_reg, | |
638 | eBP_reg, | |
639 | eSI_reg, | |
640 | eDI_reg, | |
d55ee72f | 641 | |
3873ba12 L |
642 | al_reg, |
643 | cl_reg, | |
644 | dl_reg, | |
645 | bl_reg, | |
646 | ah_reg, | |
647 | ch_reg, | |
648 | dh_reg, | |
649 | bh_reg, | |
d55ee72f | 650 | |
3873ba12 L |
651 | ax_reg, |
652 | cx_reg, | |
653 | dx_reg, | |
654 | bx_reg, | |
655 | sp_reg, | |
656 | bp_reg, | |
657 | si_reg, | |
658 | di_reg, | |
d55ee72f | 659 | |
3873ba12 L |
660 | rAX_reg, |
661 | rCX_reg, | |
662 | rDX_reg, | |
663 | rBX_reg, | |
664 | rSP_reg, | |
665 | rBP_reg, | |
666 | rSI_reg, | |
667 | rDI_reg, | |
d55ee72f | 668 | |
3873ba12 L |
669 | z_mode_ax_reg, |
670 | indir_dx_reg | |
51e7da1b | 671 | }; |
252b5132 | 672 | |
51e7da1b L |
673 | enum |
674 | { | |
675 | FLOATCODE = 1, | |
3873ba12 L |
676 | USE_REG_TABLE, |
677 | USE_MOD_TABLE, | |
678 | USE_RM_TABLE, | |
679 | USE_PREFIX_TABLE, | |
680 | USE_X86_64_TABLE, | |
681 | USE_3BYTE_TABLE, | |
f88c9eb0 | 682 | USE_XOP_8F_TABLE, |
3873ba12 L |
683 | USE_VEX_C4_TABLE, |
684 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 685 | USE_VEX_LEN_TABLE, |
43234a1e | 686 | USE_VEX_W_TABLE, |
04e2a182 L |
687 | USE_EVEX_TABLE, |
688 | USE_EVEX_LEN_TABLE | |
51e7da1b | 689 | }; |
6439fc28 | 690 | |
bf890a93 | 691 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 692 | |
bf890a93 IT |
693 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
694 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
695 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
696 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
697 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
698 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
699 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
700 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 701 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 702 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
703 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
704 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
705 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 706 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 707 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
04e2a182 | 708 | #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) |
1ceb70f8 | 709 | |
51e7da1b L |
710 | enum |
711 | { | |
712 | REG_80 = 0, | |
3873ba12 | 713 | REG_81, |
7148c369 | 714 | REG_83, |
3873ba12 L |
715 | REG_8F, |
716 | REG_C0, | |
717 | REG_C1, | |
718 | REG_C6, | |
719 | REG_C7, | |
720 | REG_D0, | |
721 | REG_D1, | |
722 | REG_D2, | |
723 | REG_D3, | |
724 | REG_F6, | |
725 | REG_F7, | |
726 | REG_FE, | |
727 | REG_FF, | |
728 | REG_0F00, | |
729 | REG_0F01, | |
730 | REG_0F0D, | |
731 | REG_0F18, | |
f8687e93 JB |
732 | REG_0F1C_P_0_MOD_0, |
733 | REG_0F1E_P_1_MOD_3, | |
3873ba12 L |
734 | REG_0F71, |
735 | REG_0F72, | |
736 | REG_0F73, | |
737 | REG_0FA6, | |
738 | REG_0FA7, | |
739 | REG_0FAE, | |
740 | REG_0FBA, | |
741 | REG_0FC7, | |
592a252b L |
742 | REG_VEX_0F71, |
743 | REG_VEX_0F72, | |
744 | REG_VEX_0F73, | |
745 | REG_VEX_0FAE, | |
f12dc422 | 746 | REG_VEX_0F38F3, |
f88c9eb0 | 747 | REG_XOP_LWPCB, |
2a2a0f38 QN |
748 | REG_XOP_LWP, |
749 | REG_XOP_TBM_01, | |
43234a1e L |
750 | REG_XOP_TBM_02, |
751 | ||
1ba585e8 | 752 | REG_EVEX_0F71, |
43234a1e L |
753 | REG_EVEX_0F72, |
754 | REG_EVEX_0F73, | |
755 | REG_EVEX_0F38C6, | |
756 | REG_EVEX_0F38C7 | |
51e7da1b | 757 | }; |
1ceb70f8 | 758 | |
51e7da1b L |
759 | enum |
760 | { | |
761 | MOD_8D = 0, | |
42164a71 L |
762 | MOD_C6_REG_7, |
763 | MOD_C7_REG_7, | |
4a357820 MZ |
764 | MOD_FF_REG_3, |
765 | MOD_FF_REG_5, | |
3873ba12 L |
766 | MOD_0F01_REG_0, |
767 | MOD_0F01_REG_1, | |
768 | MOD_0F01_REG_2, | |
769 | MOD_0F01_REG_3, | |
8eab4136 | 770 | MOD_0F01_REG_5, |
3873ba12 L |
771 | MOD_0F01_REG_7, |
772 | MOD_0F12_PREFIX_0, | |
18897deb | 773 | MOD_0F12_PREFIX_2, |
3873ba12 L |
774 | MOD_0F13, |
775 | MOD_0F16_PREFIX_0, | |
18897deb | 776 | MOD_0F16_PREFIX_2, |
3873ba12 L |
777 | MOD_0F17, |
778 | MOD_0F18_REG_0, | |
779 | MOD_0F18_REG_1, | |
780 | MOD_0F18_REG_2, | |
781 | MOD_0F18_REG_3, | |
d7189fa5 RM |
782 | MOD_0F18_REG_4, |
783 | MOD_0F18_REG_5, | |
784 | MOD_0F18_REG_6, | |
785 | MOD_0F18_REG_7, | |
7e8b059b L |
786 | MOD_0F1A_PREFIX_0, |
787 | MOD_0F1B_PREFIX_0, | |
788 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 789 | MOD_0F1C_PREFIX_0, |
603555e5 | 790 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
791 | MOD_0F24, |
792 | MOD_0F26, | |
793 | MOD_0F2B_PREFIX_0, | |
794 | MOD_0F2B_PREFIX_1, | |
795 | MOD_0F2B_PREFIX_2, | |
796 | MOD_0F2B_PREFIX_3, | |
a5aaedb9 | 797 | MOD_0F50, |
3873ba12 L |
798 | MOD_0F71_REG_2, |
799 | MOD_0F71_REG_4, | |
800 | MOD_0F71_REG_6, | |
801 | MOD_0F72_REG_2, | |
802 | MOD_0F72_REG_4, | |
803 | MOD_0F72_REG_6, | |
804 | MOD_0F73_REG_2, | |
805 | MOD_0F73_REG_3, | |
806 | MOD_0F73_REG_6, | |
807 | MOD_0F73_REG_7, | |
808 | MOD_0FAE_REG_0, | |
809 | MOD_0FAE_REG_1, | |
810 | MOD_0FAE_REG_2, | |
811 | MOD_0FAE_REG_3, | |
812 | MOD_0FAE_REG_4, | |
813 | MOD_0FAE_REG_5, | |
814 | MOD_0FAE_REG_6, | |
815 | MOD_0FAE_REG_7, | |
816 | MOD_0FB2, | |
817 | MOD_0FB4, | |
818 | MOD_0FB5, | |
a8484f96 | 819 | MOD_0FC3, |
963f3586 IT |
820 | MOD_0FC7_REG_3, |
821 | MOD_0FC7_REG_4, | |
822 | MOD_0FC7_REG_5, | |
3873ba12 L |
823 | MOD_0FC7_REG_6, |
824 | MOD_0FC7_REG_7, | |
825 | MOD_0FD7, | |
826 | MOD_0FE7_PREFIX_2, | |
827 | MOD_0FF0_PREFIX_3, | |
828 | MOD_0F382A_PREFIX_2, | |
603555e5 L |
829 | MOD_0F38F5_PREFIX_2, |
830 | MOD_0F38F6_PREFIX_0, | |
5d79adc4 | 831 | MOD_0F38F8_PREFIX_1, |
c0a30a9f | 832 | MOD_0F38F8_PREFIX_2, |
5d79adc4 | 833 | MOD_0F38F8_PREFIX_3, |
c0a30a9f | 834 | MOD_0F38F9_PREFIX_0, |
3873ba12 L |
835 | MOD_62_32BIT, |
836 | MOD_C4_32BIT, | |
837 | MOD_C5_32BIT, | |
592a252b | 838 | MOD_VEX_0F12_PREFIX_0, |
18897deb | 839 | MOD_VEX_0F12_PREFIX_2, |
592a252b L |
840 | MOD_VEX_0F13, |
841 | MOD_VEX_0F16_PREFIX_0, | |
18897deb | 842 | MOD_VEX_0F16_PREFIX_2, |
592a252b L |
843 | MOD_VEX_0F17, |
844 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
845 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
846 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
847 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
848 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
849 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
850 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
851 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
852 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
853 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
854 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
855 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
856 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
857 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
858 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
859 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
860 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
861 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
862 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
863 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
864 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
865 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
866 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
867 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
868 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
869 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
870 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
871 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
872 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
873 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
874 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
875 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
876 | MOD_VEX_0F50, |
877 | MOD_VEX_0F71_REG_2, | |
878 | MOD_VEX_0F71_REG_4, | |
879 | MOD_VEX_0F71_REG_6, | |
880 | MOD_VEX_0F72_REG_2, | |
881 | MOD_VEX_0F72_REG_4, | |
882 | MOD_VEX_0F72_REG_6, | |
883 | MOD_VEX_0F73_REG_2, | |
884 | MOD_VEX_0F73_REG_3, | |
885 | MOD_VEX_0F73_REG_6, | |
886 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
887 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
888 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
889 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
890 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
891 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
892 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
58a211d2 | 893 | MOD_VEX_0F92_P_3_LEN_0, |
ab4e4ed5 AF |
894 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
895 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
58a211d2 | 896 | MOD_VEX_0F93_P_3_LEN_0, |
ab4e4ed5 AF |
897 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
898 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
899 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
900 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
901 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
902 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
903 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
904 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
905 | MOD_VEX_0FAE_REG_2, |
906 | MOD_VEX_0FAE_REG_3, | |
907 | MOD_VEX_0FD7_PREFIX_2, | |
908 | MOD_VEX_0FE7_PREFIX_2, | |
909 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
910 | MOD_VEX_0F381A_PREFIX_2, |
911 | MOD_VEX_0F382A_PREFIX_2, | |
912 | MOD_VEX_0F382C_PREFIX_2, | |
913 | MOD_VEX_0F382D_PREFIX_2, | |
914 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
915 | MOD_VEX_0F382F_PREFIX_2, |
916 | MOD_VEX_0F385A_PREFIX_2, | |
917 | MOD_VEX_0F388C_PREFIX_2, | |
918 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
919 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
920 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
921 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
922 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
923 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
924 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
925 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
926 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e | 927 | |
43234a1e | 928 | MOD_EVEX_0F12_PREFIX_0, |
97e6786a JB |
929 | MOD_EVEX_0F12_PREFIX_2, |
930 | MOD_EVEX_0F13, | |
43234a1e | 931 | MOD_EVEX_0F16_PREFIX_0, |
97e6786a JB |
932 | MOD_EVEX_0F16_PREFIX_2, |
933 | MOD_EVEX_0F17, | |
934 | MOD_EVEX_0F2B, | |
43234a1e L |
935 | MOD_EVEX_0F38C6_REG_1, |
936 | MOD_EVEX_0F38C6_REG_2, | |
937 | MOD_EVEX_0F38C6_REG_5, | |
938 | MOD_EVEX_0F38C6_REG_6, | |
939 | MOD_EVEX_0F38C7_REG_1, | |
940 | MOD_EVEX_0F38C7_REG_2, | |
941 | MOD_EVEX_0F38C7_REG_5, | |
942 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 943 | }; |
1ceb70f8 | 944 | |
51e7da1b L |
945 | enum |
946 | { | |
42164a71 L |
947 | RM_C6_REG_7 = 0, |
948 | RM_C7_REG_7, | |
949 | RM_0F01_REG_0, | |
3873ba12 L |
950 | RM_0F01_REG_1, |
951 | RM_0F01_REG_2, | |
952 | RM_0F01_REG_3, | |
f8687e93 JB |
953 | RM_0F01_REG_5_MOD_3, |
954 | RM_0F01_REG_7_MOD_3, | |
955 | RM_0F1E_P_1_MOD_3_REG_7, | |
956 | RM_0FAE_REG_6_MOD_3_P_0, | |
957 | RM_0FAE_REG_7_MOD_3, | |
51e7da1b | 958 | }; |
1ceb70f8 | 959 | |
51e7da1b L |
960 | enum |
961 | { | |
962 | PREFIX_90 = 0, | |
a847e322 | 963 | PREFIX_0F01_REG_3_RM_1, |
f8687e93 JB |
964 | PREFIX_0F01_REG_5_MOD_0, |
965 | PREFIX_0F01_REG_5_MOD_3_RM_0, | |
bb651e8b | 966 | PREFIX_0F01_REG_5_MOD_3_RM_1, |
f8687e93 | 967 | PREFIX_0F01_REG_5_MOD_3_RM_2, |
267b8516 JB |
968 | PREFIX_0F01_REG_7_MOD_3_RM_2, |
969 | PREFIX_0F01_REG_7_MOD_3_RM_3, | |
3233d7d0 | 970 | PREFIX_0F09, |
3873ba12 L |
971 | PREFIX_0F10, |
972 | PREFIX_0F11, | |
973 | PREFIX_0F12, | |
974 | PREFIX_0F16, | |
7e8b059b L |
975 | PREFIX_0F1A, |
976 | PREFIX_0F1B, | |
c48935d7 | 977 | PREFIX_0F1C, |
603555e5 | 978 | PREFIX_0F1E, |
3873ba12 L |
979 | PREFIX_0F2A, |
980 | PREFIX_0F2B, | |
981 | PREFIX_0F2C, | |
982 | PREFIX_0F2D, | |
983 | PREFIX_0F2E, | |
984 | PREFIX_0F2F, | |
985 | PREFIX_0F51, | |
986 | PREFIX_0F52, | |
987 | PREFIX_0F53, | |
988 | PREFIX_0F58, | |
989 | PREFIX_0F59, | |
990 | PREFIX_0F5A, | |
991 | PREFIX_0F5B, | |
992 | PREFIX_0F5C, | |
993 | PREFIX_0F5D, | |
994 | PREFIX_0F5E, | |
995 | PREFIX_0F5F, | |
996 | PREFIX_0F60, | |
997 | PREFIX_0F61, | |
998 | PREFIX_0F62, | |
999 | PREFIX_0F6C, | |
1000 | PREFIX_0F6D, | |
1001 | PREFIX_0F6F, | |
1002 | PREFIX_0F70, | |
1003 | PREFIX_0F73_REG_3, | |
1004 | PREFIX_0F73_REG_7, | |
1005 | PREFIX_0F78, | |
1006 | PREFIX_0F79, | |
1007 | PREFIX_0F7C, | |
1008 | PREFIX_0F7D, | |
1009 | PREFIX_0F7E, | |
1010 | PREFIX_0F7F, | |
f8687e93 JB |
1011 | PREFIX_0FAE_REG_0_MOD_3, |
1012 | PREFIX_0FAE_REG_1_MOD_3, | |
1013 | PREFIX_0FAE_REG_2_MOD_3, | |
1014 | PREFIX_0FAE_REG_3_MOD_3, | |
1015 | PREFIX_0FAE_REG_4_MOD_0, | |
1016 | PREFIX_0FAE_REG_4_MOD_3, | |
1017 | PREFIX_0FAE_REG_5_MOD_0, | |
1018 | PREFIX_0FAE_REG_5_MOD_3, | |
1019 | PREFIX_0FAE_REG_6_MOD_0, | |
1020 | PREFIX_0FAE_REG_6_MOD_3, | |
1021 | PREFIX_0FAE_REG_7_MOD_0, | |
3873ba12 | 1022 | PREFIX_0FB8, |
f12dc422 | 1023 | PREFIX_0FBC, |
3873ba12 L |
1024 | PREFIX_0FBD, |
1025 | PREFIX_0FC2, | |
f8687e93 JB |
1026 | PREFIX_0FC3_MOD_0, |
1027 | PREFIX_0FC7_REG_6_MOD_0, | |
1028 | PREFIX_0FC7_REG_6_MOD_3, | |
1029 | PREFIX_0FC7_REG_7_MOD_3, | |
3873ba12 L |
1030 | PREFIX_0FD0, |
1031 | PREFIX_0FD6, | |
1032 | PREFIX_0FE6, | |
1033 | PREFIX_0FE7, | |
1034 | PREFIX_0FF0, | |
1035 | PREFIX_0FF7, | |
1036 | PREFIX_0F3810, | |
1037 | PREFIX_0F3814, | |
1038 | PREFIX_0F3815, | |
1039 | PREFIX_0F3817, | |
1040 | PREFIX_0F3820, | |
1041 | PREFIX_0F3821, | |
1042 | PREFIX_0F3822, | |
1043 | PREFIX_0F3823, | |
1044 | PREFIX_0F3824, | |
1045 | PREFIX_0F3825, | |
1046 | PREFIX_0F3828, | |
1047 | PREFIX_0F3829, | |
1048 | PREFIX_0F382A, | |
1049 | PREFIX_0F382B, | |
1050 | PREFIX_0F3830, | |
1051 | PREFIX_0F3831, | |
1052 | PREFIX_0F3832, | |
1053 | PREFIX_0F3833, | |
1054 | PREFIX_0F3834, | |
1055 | PREFIX_0F3835, | |
1056 | PREFIX_0F3837, | |
1057 | PREFIX_0F3838, | |
1058 | PREFIX_0F3839, | |
1059 | PREFIX_0F383A, | |
1060 | PREFIX_0F383B, | |
1061 | PREFIX_0F383C, | |
1062 | PREFIX_0F383D, | |
1063 | PREFIX_0F383E, | |
1064 | PREFIX_0F383F, | |
1065 | PREFIX_0F3840, | |
1066 | PREFIX_0F3841, | |
1067 | PREFIX_0F3880, | |
1068 | PREFIX_0F3881, | |
6c30d220 | 1069 | PREFIX_0F3882, |
a0046408 L |
1070 | PREFIX_0F38C8, |
1071 | PREFIX_0F38C9, | |
1072 | PREFIX_0F38CA, | |
1073 | PREFIX_0F38CB, | |
1074 | PREFIX_0F38CC, | |
1075 | PREFIX_0F38CD, | |
48521003 | 1076 | PREFIX_0F38CF, |
3873ba12 L |
1077 | PREFIX_0F38DB, |
1078 | PREFIX_0F38DC, | |
1079 | PREFIX_0F38DD, | |
1080 | PREFIX_0F38DE, | |
1081 | PREFIX_0F38DF, | |
1082 | PREFIX_0F38F0, | |
1083 | PREFIX_0F38F1, | |
603555e5 | 1084 | PREFIX_0F38F5, |
e2e1fcde | 1085 | PREFIX_0F38F6, |
c0a30a9f L |
1086 | PREFIX_0F38F8, |
1087 | PREFIX_0F38F9, | |
3873ba12 L |
1088 | PREFIX_0F3A08, |
1089 | PREFIX_0F3A09, | |
1090 | PREFIX_0F3A0A, | |
1091 | PREFIX_0F3A0B, | |
1092 | PREFIX_0F3A0C, | |
1093 | PREFIX_0F3A0D, | |
1094 | PREFIX_0F3A0E, | |
1095 | PREFIX_0F3A14, | |
1096 | PREFIX_0F3A15, | |
1097 | PREFIX_0F3A16, | |
1098 | PREFIX_0F3A17, | |
1099 | PREFIX_0F3A20, | |
1100 | PREFIX_0F3A21, | |
1101 | PREFIX_0F3A22, | |
1102 | PREFIX_0F3A40, | |
1103 | PREFIX_0F3A41, | |
1104 | PREFIX_0F3A42, | |
1105 | PREFIX_0F3A44, | |
1106 | PREFIX_0F3A60, | |
1107 | PREFIX_0F3A61, | |
1108 | PREFIX_0F3A62, | |
1109 | PREFIX_0F3A63, | |
a0046408 | 1110 | PREFIX_0F3ACC, |
48521003 IT |
1111 | PREFIX_0F3ACE, |
1112 | PREFIX_0F3ACF, | |
3873ba12 | 1113 | PREFIX_0F3ADF, |
592a252b L |
1114 | PREFIX_VEX_0F10, |
1115 | PREFIX_VEX_0F11, | |
1116 | PREFIX_VEX_0F12, | |
1117 | PREFIX_VEX_0F16, | |
1118 | PREFIX_VEX_0F2A, | |
1119 | PREFIX_VEX_0F2C, | |
1120 | PREFIX_VEX_0F2D, | |
1121 | PREFIX_VEX_0F2E, | |
1122 | PREFIX_VEX_0F2F, | |
43234a1e L |
1123 | PREFIX_VEX_0F41, |
1124 | PREFIX_VEX_0F42, | |
1125 | PREFIX_VEX_0F44, | |
1126 | PREFIX_VEX_0F45, | |
1127 | PREFIX_VEX_0F46, | |
1128 | PREFIX_VEX_0F47, | |
1ba585e8 | 1129 | PREFIX_VEX_0F4A, |
43234a1e | 1130 | PREFIX_VEX_0F4B, |
592a252b L |
1131 | PREFIX_VEX_0F51, |
1132 | PREFIX_VEX_0F52, | |
1133 | PREFIX_VEX_0F53, | |
1134 | PREFIX_VEX_0F58, | |
1135 | PREFIX_VEX_0F59, | |
1136 | PREFIX_VEX_0F5A, | |
1137 | PREFIX_VEX_0F5B, | |
1138 | PREFIX_VEX_0F5C, | |
1139 | PREFIX_VEX_0F5D, | |
1140 | PREFIX_VEX_0F5E, | |
1141 | PREFIX_VEX_0F5F, | |
1142 | PREFIX_VEX_0F60, | |
1143 | PREFIX_VEX_0F61, | |
1144 | PREFIX_VEX_0F62, | |
1145 | PREFIX_VEX_0F63, | |
1146 | PREFIX_VEX_0F64, | |
1147 | PREFIX_VEX_0F65, | |
1148 | PREFIX_VEX_0F66, | |
1149 | PREFIX_VEX_0F67, | |
1150 | PREFIX_VEX_0F68, | |
1151 | PREFIX_VEX_0F69, | |
1152 | PREFIX_VEX_0F6A, | |
1153 | PREFIX_VEX_0F6B, | |
1154 | PREFIX_VEX_0F6C, | |
1155 | PREFIX_VEX_0F6D, | |
1156 | PREFIX_VEX_0F6E, | |
1157 | PREFIX_VEX_0F6F, | |
1158 | PREFIX_VEX_0F70, | |
1159 | PREFIX_VEX_0F71_REG_2, | |
1160 | PREFIX_VEX_0F71_REG_4, | |
1161 | PREFIX_VEX_0F71_REG_6, | |
1162 | PREFIX_VEX_0F72_REG_2, | |
1163 | PREFIX_VEX_0F72_REG_4, | |
1164 | PREFIX_VEX_0F72_REG_6, | |
1165 | PREFIX_VEX_0F73_REG_2, | |
1166 | PREFIX_VEX_0F73_REG_3, | |
1167 | PREFIX_VEX_0F73_REG_6, | |
1168 | PREFIX_VEX_0F73_REG_7, | |
1169 | PREFIX_VEX_0F74, | |
1170 | PREFIX_VEX_0F75, | |
1171 | PREFIX_VEX_0F76, | |
1172 | PREFIX_VEX_0F77, | |
1173 | PREFIX_VEX_0F7C, | |
1174 | PREFIX_VEX_0F7D, | |
1175 | PREFIX_VEX_0F7E, | |
1176 | PREFIX_VEX_0F7F, | |
43234a1e L |
1177 | PREFIX_VEX_0F90, |
1178 | PREFIX_VEX_0F91, | |
1179 | PREFIX_VEX_0F92, | |
1180 | PREFIX_VEX_0F93, | |
1181 | PREFIX_VEX_0F98, | |
1ba585e8 | 1182 | PREFIX_VEX_0F99, |
592a252b L |
1183 | PREFIX_VEX_0FC2, |
1184 | PREFIX_VEX_0FC4, | |
1185 | PREFIX_VEX_0FC5, | |
1186 | PREFIX_VEX_0FD0, | |
1187 | PREFIX_VEX_0FD1, | |
1188 | PREFIX_VEX_0FD2, | |
1189 | PREFIX_VEX_0FD3, | |
1190 | PREFIX_VEX_0FD4, | |
1191 | PREFIX_VEX_0FD5, | |
1192 | PREFIX_VEX_0FD6, | |
1193 | PREFIX_VEX_0FD7, | |
1194 | PREFIX_VEX_0FD8, | |
1195 | PREFIX_VEX_0FD9, | |
1196 | PREFIX_VEX_0FDA, | |
1197 | PREFIX_VEX_0FDB, | |
1198 | PREFIX_VEX_0FDC, | |
1199 | PREFIX_VEX_0FDD, | |
1200 | PREFIX_VEX_0FDE, | |
1201 | PREFIX_VEX_0FDF, | |
1202 | PREFIX_VEX_0FE0, | |
1203 | PREFIX_VEX_0FE1, | |
1204 | PREFIX_VEX_0FE2, | |
1205 | PREFIX_VEX_0FE3, | |
1206 | PREFIX_VEX_0FE4, | |
1207 | PREFIX_VEX_0FE5, | |
1208 | PREFIX_VEX_0FE6, | |
1209 | PREFIX_VEX_0FE7, | |
1210 | PREFIX_VEX_0FE8, | |
1211 | PREFIX_VEX_0FE9, | |
1212 | PREFIX_VEX_0FEA, | |
1213 | PREFIX_VEX_0FEB, | |
1214 | PREFIX_VEX_0FEC, | |
1215 | PREFIX_VEX_0FED, | |
1216 | PREFIX_VEX_0FEE, | |
1217 | PREFIX_VEX_0FEF, | |
1218 | PREFIX_VEX_0FF0, | |
1219 | PREFIX_VEX_0FF1, | |
1220 | PREFIX_VEX_0FF2, | |
1221 | PREFIX_VEX_0FF3, | |
1222 | PREFIX_VEX_0FF4, | |
1223 | PREFIX_VEX_0FF5, | |
1224 | PREFIX_VEX_0FF6, | |
1225 | PREFIX_VEX_0FF7, | |
1226 | PREFIX_VEX_0FF8, | |
1227 | PREFIX_VEX_0FF9, | |
1228 | PREFIX_VEX_0FFA, | |
1229 | PREFIX_VEX_0FFB, | |
1230 | PREFIX_VEX_0FFC, | |
1231 | PREFIX_VEX_0FFD, | |
1232 | PREFIX_VEX_0FFE, | |
1233 | PREFIX_VEX_0F3800, | |
1234 | PREFIX_VEX_0F3801, | |
1235 | PREFIX_VEX_0F3802, | |
1236 | PREFIX_VEX_0F3803, | |
1237 | PREFIX_VEX_0F3804, | |
1238 | PREFIX_VEX_0F3805, | |
1239 | PREFIX_VEX_0F3806, | |
1240 | PREFIX_VEX_0F3807, | |
1241 | PREFIX_VEX_0F3808, | |
1242 | PREFIX_VEX_0F3809, | |
1243 | PREFIX_VEX_0F380A, | |
1244 | PREFIX_VEX_0F380B, | |
1245 | PREFIX_VEX_0F380C, | |
1246 | PREFIX_VEX_0F380D, | |
1247 | PREFIX_VEX_0F380E, | |
1248 | PREFIX_VEX_0F380F, | |
1249 | PREFIX_VEX_0F3813, | |
6c30d220 | 1250 | PREFIX_VEX_0F3816, |
592a252b L |
1251 | PREFIX_VEX_0F3817, |
1252 | PREFIX_VEX_0F3818, | |
1253 | PREFIX_VEX_0F3819, | |
1254 | PREFIX_VEX_0F381A, | |
1255 | PREFIX_VEX_0F381C, | |
1256 | PREFIX_VEX_0F381D, | |
1257 | PREFIX_VEX_0F381E, | |
1258 | PREFIX_VEX_0F3820, | |
1259 | PREFIX_VEX_0F3821, | |
1260 | PREFIX_VEX_0F3822, | |
1261 | PREFIX_VEX_0F3823, | |
1262 | PREFIX_VEX_0F3824, | |
1263 | PREFIX_VEX_0F3825, | |
1264 | PREFIX_VEX_0F3828, | |
1265 | PREFIX_VEX_0F3829, | |
1266 | PREFIX_VEX_0F382A, | |
1267 | PREFIX_VEX_0F382B, | |
1268 | PREFIX_VEX_0F382C, | |
1269 | PREFIX_VEX_0F382D, | |
1270 | PREFIX_VEX_0F382E, | |
1271 | PREFIX_VEX_0F382F, | |
1272 | PREFIX_VEX_0F3830, | |
1273 | PREFIX_VEX_0F3831, | |
1274 | PREFIX_VEX_0F3832, | |
1275 | PREFIX_VEX_0F3833, | |
1276 | PREFIX_VEX_0F3834, | |
1277 | PREFIX_VEX_0F3835, | |
6c30d220 | 1278 | PREFIX_VEX_0F3836, |
592a252b L |
1279 | PREFIX_VEX_0F3837, |
1280 | PREFIX_VEX_0F3838, | |
1281 | PREFIX_VEX_0F3839, | |
1282 | PREFIX_VEX_0F383A, | |
1283 | PREFIX_VEX_0F383B, | |
1284 | PREFIX_VEX_0F383C, | |
1285 | PREFIX_VEX_0F383D, | |
1286 | PREFIX_VEX_0F383E, | |
1287 | PREFIX_VEX_0F383F, | |
1288 | PREFIX_VEX_0F3840, | |
1289 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1290 | PREFIX_VEX_0F3845, |
1291 | PREFIX_VEX_0F3846, | |
1292 | PREFIX_VEX_0F3847, | |
1293 | PREFIX_VEX_0F3858, | |
1294 | PREFIX_VEX_0F3859, | |
1295 | PREFIX_VEX_0F385A, | |
1296 | PREFIX_VEX_0F3878, | |
1297 | PREFIX_VEX_0F3879, | |
1298 | PREFIX_VEX_0F388C, | |
1299 | PREFIX_VEX_0F388E, | |
1300 | PREFIX_VEX_0F3890, | |
1301 | PREFIX_VEX_0F3891, | |
1302 | PREFIX_VEX_0F3892, | |
1303 | PREFIX_VEX_0F3893, | |
592a252b L |
1304 | PREFIX_VEX_0F3896, |
1305 | PREFIX_VEX_0F3897, | |
1306 | PREFIX_VEX_0F3898, | |
1307 | PREFIX_VEX_0F3899, | |
1308 | PREFIX_VEX_0F389A, | |
1309 | PREFIX_VEX_0F389B, | |
1310 | PREFIX_VEX_0F389C, | |
1311 | PREFIX_VEX_0F389D, | |
1312 | PREFIX_VEX_0F389E, | |
1313 | PREFIX_VEX_0F389F, | |
1314 | PREFIX_VEX_0F38A6, | |
1315 | PREFIX_VEX_0F38A7, | |
1316 | PREFIX_VEX_0F38A8, | |
1317 | PREFIX_VEX_0F38A9, | |
1318 | PREFIX_VEX_0F38AA, | |
1319 | PREFIX_VEX_0F38AB, | |
1320 | PREFIX_VEX_0F38AC, | |
1321 | PREFIX_VEX_0F38AD, | |
1322 | PREFIX_VEX_0F38AE, | |
1323 | PREFIX_VEX_0F38AF, | |
1324 | PREFIX_VEX_0F38B6, | |
1325 | PREFIX_VEX_0F38B7, | |
1326 | PREFIX_VEX_0F38B8, | |
1327 | PREFIX_VEX_0F38B9, | |
1328 | PREFIX_VEX_0F38BA, | |
1329 | PREFIX_VEX_0F38BB, | |
1330 | PREFIX_VEX_0F38BC, | |
1331 | PREFIX_VEX_0F38BD, | |
1332 | PREFIX_VEX_0F38BE, | |
1333 | PREFIX_VEX_0F38BF, | |
48521003 | 1334 | PREFIX_VEX_0F38CF, |
592a252b L |
1335 | PREFIX_VEX_0F38DB, |
1336 | PREFIX_VEX_0F38DC, | |
1337 | PREFIX_VEX_0F38DD, | |
1338 | PREFIX_VEX_0F38DE, | |
1339 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1340 | PREFIX_VEX_0F38F2, |
1341 | PREFIX_VEX_0F38F3_REG_1, | |
1342 | PREFIX_VEX_0F38F3_REG_2, | |
1343 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1344 | PREFIX_VEX_0F38F5, |
1345 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1346 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1347 | PREFIX_VEX_0F3A00, |
1348 | PREFIX_VEX_0F3A01, | |
1349 | PREFIX_VEX_0F3A02, | |
592a252b L |
1350 | PREFIX_VEX_0F3A04, |
1351 | PREFIX_VEX_0F3A05, | |
1352 | PREFIX_VEX_0F3A06, | |
1353 | PREFIX_VEX_0F3A08, | |
1354 | PREFIX_VEX_0F3A09, | |
1355 | PREFIX_VEX_0F3A0A, | |
1356 | PREFIX_VEX_0F3A0B, | |
1357 | PREFIX_VEX_0F3A0C, | |
1358 | PREFIX_VEX_0F3A0D, | |
1359 | PREFIX_VEX_0F3A0E, | |
1360 | PREFIX_VEX_0F3A0F, | |
1361 | PREFIX_VEX_0F3A14, | |
1362 | PREFIX_VEX_0F3A15, | |
1363 | PREFIX_VEX_0F3A16, | |
1364 | PREFIX_VEX_0F3A17, | |
1365 | PREFIX_VEX_0F3A18, | |
1366 | PREFIX_VEX_0F3A19, | |
1367 | PREFIX_VEX_0F3A1D, | |
1368 | PREFIX_VEX_0F3A20, | |
1369 | PREFIX_VEX_0F3A21, | |
1370 | PREFIX_VEX_0F3A22, | |
43234a1e | 1371 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1372 | PREFIX_VEX_0F3A31, |
43234a1e | 1373 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1374 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1375 | PREFIX_VEX_0F3A38, |
1376 | PREFIX_VEX_0F3A39, | |
592a252b L |
1377 | PREFIX_VEX_0F3A40, |
1378 | PREFIX_VEX_0F3A41, | |
1379 | PREFIX_VEX_0F3A42, | |
1380 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1381 | PREFIX_VEX_0F3A46, |
592a252b L |
1382 | PREFIX_VEX_0F3A48, |
1383 | PREFIX_VEX_0F3A49, | |
1384 | PREFIX_VEX_0F3A4A, | |
1385 | PREFIX_VEX_0F3A4B, | |
1386 | PREFIX_VEX_0F3A4C, | |
1387 | PREFIX_VEX_0F3A5C, | |
1388 | PREFIX_VEX_0F3A5D, | |
1389 | PREFIX_VEX_0F3A5E, | |
1390 | PREFIX_VEX_0F3A5F, | |
1391 | PREFIX_VEX_0F3A60, | |
1392 | PREFIX_VEX_0F3A61, | |
1393 | PREFIX_VEX_0F3A62, | |
1394 | PREFIX_VEX_0F3A63, | |
1395 | PREFIX_VEX_0F3A68, | |
1396 | PREFIX_VEX_0F3A69, | |
1397 | PREFIX_VEX_0F3A6A, | |
1398 | PREFIX_VEX_0F3A6B, | |
1399 | PREFIX_VEX_0F3A6C, | |
1400 | PREFIX_VEX_0F3A6D, | |
1401 | PREFIX_VEX_0F3A6E, | |
1402 | PREFIX_VEX_0F3A6F, | |
1403 | PREFIX_VEX_0F3A78, | |
1404 | PREFIX_VEX_0F3A79, | |
1405 | PREFIX_VEX_0F3A7A, | |
1406 | PREFIX_VEX_0F3A7B, | |
1407 | PREFIX_VEX_0F3A7C, | |
1408 | PREFIX_VEX_0F3A7D, | |
1409 | PREFIX_VEX_0F3A7E, | |
1410 | PREFIX_VEX_0F3A7F, | |
48521003 IT |
1411 | PREFIX_VEX_0F3ACE, |
1412 | PREFIX_VEX_0F3ACF, | |
6c30d220 | 1413 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1414 | PREFIX_VEX_0F3AF0, |
1415 | ||
1416 | PREFIX_EVEX_0F10, | |
1417 | PREFIX_EVEX_0F11, | |
1418 | PREFIX_EVEX_0F12, | |
43234a1e | 1419 | PREFIX_EVEX_0F16, |
43234a1e | 1420 | PREFIX_EVEX_0F2A, |
43234a1e L |
1421 | PREFIX_EVEX_0F2C, |
1422 | PREFIX_EVEX_0F2D, | |
1423 | PREFIX_EVEX_0F2E, | |
1424 | PREFIX_EVEX_0F2F, | |
1425 | PREFIX_EVEX_0F51, | |
1426 | PREFIX_EVEX_0F58, | |
1427 | PREFIX_EVEX_0F59, | |
1428 | PREFIX_EVEX_0F5A, | |
1429 | PREFIX_EVEX_0F5B, | |
1430 | PREFIX_EVEX_0F5C, | |
1431 | PREFIX_EVEX_0F5D, | |
1432 | PREFIX_EVEX_0F5E, | |
1433 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1434 | PREFIX_EVEX_0F64, |
1435 | PREFIX_EVEX_0F65, | |
43234a1e | 1436 | PREFIX_EVEX_0F66, |
43234a1e L |
1437 | PREFIX_EVEX_0F6E, |
1438 | PREFIX_EVEX_0F6F, | |
1439 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1440 | PREFIX_EVEX_0F71_REG_2, |
1441 | PREFIX_EVEX_0F71_REG_4, | |
1442 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1443 | PREFIX_EVEX_0F72_REG_0, |
1444 | PREFIX_EVEX_0F72_REG_1, | |
1445 | PREFIX_EVEX_0F72_REG_2, | |
1446 | PREFIX_EVEX_0F72_REG_4, | |
1447 | PREFIX_EVEX_0F72_REG_6, | |
1448 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1449 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1450 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1451 | PREFIX_EVEX_0F73_REG_7, |
1452 | PREFIX_EVEX_0F74, | |
1453 | PREFIX_EVEX_0F75, | |
43234a1e L |
1454 | PREFIX_EVEX_0F76, |
1455 | PREFIX_EVEX_0F78, | |
1456 | PREFIX_EVEX_0F79, | |
1457 | PREFIX_EVEX_0F7A, | |
1458 | PREFIX_EVEX_0F7B, | |
1459 | PREFIX_EVEX_0F7E, | |
1460 | PREFIX_EVEX_0F7F, | |
1461 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1462 | PREFIX_EVEX_0FC4, |
1463 | PREFIX_EVEX_0FC5, | |
43234a1e L |
1464 | PREFIX_EVEX_0FD6, |
1465 | PREFIX_EVEX_0FDB, | |
1466 | PREFIX_EVEX_0FDF, | |
1467 | PREFIX_EVEX_0FE2, | |
1468 | PREFIX_EVEX_0FE6, | |
1469 | PREFIX_EVEX_0FE7, | |
1470 | PREFIX_EVEX_0FEB, | |
1471 | PREFIX_EVEX_0FEF, | |
43234a1e | 1472 | PREFIX_EVEX_0F380D, |
1ba585e8 | 1473 | PREFIX_EVEX_0F3810, |
43234a1e L |
1474 | PREFIX_EVEX_0F3811, |
1475 | PREFIX_EVEX_0F3812, | |
1476 | PREFIX_EVEX_0F3813, | |
1477 | PREFIX_EVEX_0F3814, | |
1478 | PREFIX_EVEX_0F3815, | |
1479 | PREFIX_EVEX_0F3816, | |
43234a1e L |
1480 | PREFIX_EVEX_0F3819, |
1481 | PREFIX_EVEX_0F381A, | |
1482 | PREFIX_EVEX_0F381B, | |
1483 | PREFIX_EVEX_0F381E, | |
1484 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1485 | PREFIX_EVEX_0F3820, |
43234a1e L |
1486 | PREFIX_EVEX_0F3821, |
1487 | PREFIX_EVEX_0F3822, | |
1488 | PREFIX_EVEX_0F3823, | |
1489 | PREFIX_EVEX_0F3824, | |
1490 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1491 | PREFIX_EVEX_0F3826, |
43234a1e L |
1492 | PREFIX_EVEX_0F3827, |
1493 | PREFIX_EVEX_0F3828, | |
1494 | PREFIX_EVEX_0F3829, | |
1495 | PREFIX_EVEX_0F382A, | |
1496 | PREFIX_EVEX_0F382C, | |
1497 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1498 | PREFIX_EVEX_0F3830, |
43234a1e L |
1499 | PREFIX_EVEX_0F3831, |
1500 | PREFIX_EVEX_0F3832, | |
1501 | PREFIX_EVEX_0F3833, | |
1502 | PREFIX_EVEX_0F3834, | |
1503 | PREFIX_EVEX_0F3835, | |
1504 | PREFIX_EVEX_0F3836, | |
1505 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1506 | PREFIX_EVEX_0F3838, |
43234a1e L |
1507 | PREFIX_EVEX_0F3839, |
1508 | PREFIX_EVEX_0F383A, | |
1509 | PREFIX_EVEX_0F383B, | |
1510 | PREFIX_EVEX_0F383D, | |
1511 | PREFIX_EVEX_0F383F, | |
1512 | PREFIX_EVEX_0F3840, | |
1513 | PREFIX_EVEX_0F3842, | |
1514 | PREFIX_EVEX_0F3843, | |
1515 | PREFIX_EVEX_0F3844, | |
1516 | PREFIX_EVEX_0F3845, | |
1517 | PREFIX_EVEX_0F3846, | |
1518 | PREFIX_EVEX_0F3847, | |
1519 | PREFIX_EVEX_0F384C, | |
1520 | PREFIX_EVEX_0F384D, | |
1521 | PREFIX_EVEX_0F384E, | |
1522 | PREFIX_EVEX_0F384F, | |
8cfcb765 IT |
1523 | PREFIX_EVEX_0F3850, |
1524 | PREFIX_EVEX_0F3851, | |
47acf0bd IT |
1525 | PREFIX_EVEX_0F3852, |
1526 | PREFIX_EVEX_0F3853, | |
ee6872be | 1527 | PREFIX_EVEX_0F3854, |
620214f7 | 1528 | PREFIX_EVEX_0F3855, |
43234a1e L |
1529 | PREFIX_EVEX_0F3859, |
1530 | PREFIX_EVEX_0F385A, | |
1531 | PREFIX_EVEX_0F385B, | |
53467f57 IT |
1532 | PREFIX_EVEX_0F3862, |
1533 | PREFIX_EVEX_0F3863, | |
43234a1e L |
1534 | PREFIX_EVEX_0F3864, |
1535 | PREFIX_EVEX_0F3865, | |
1ba585e8 | 1536 | PREFIX_EVEX_0F3866, |
9186c494 | 1537 | PREFIX_EVEX_0F3868, |
53467f57 IT |
1538 | PREFIX_EVEX_0F3870, |
1539 | PREFIX_EVEX_0F3871, | |
1540 | PREFIX_EVEX_0F3872, | |
1541 | PREFIX_EVEX_0F3873, | |
1ba585e8 | 1542 | PREFIX_EVEX_0F3875, |
43234a1e L |
1543 | PREFIX_EVEX_0F3876, |
1544 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1545 | PREFIX_EVEX_0F387A, |
1546 | PREFIX_EVEX_0F387B, | |
43234a1e | 1547 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1548 | PREFIX_EVEX_0F387D, |
43234a1e L |
1549 | PREFIX_EVEX_0F387E, |
1550 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1551 | PREFIX_EVEX_0F3883, |
43234a1e L |
1552 | PREFIX_EVEX_0F3888, |
1553 | PREFIX_EVEX_0F3889, | |
1554 | PREFIX_EVEX_0F388A, | |
1555 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1556 | PREFIX_EVEX_0F388D, |
ee6872be | 1557 | PREFIX_EVEX_0F388F, |
43234a1e L |
1558 | PREFIX_EVEX_0F3890, |
1559 | PREFIX_EVEX_0F3891, | |
1560 | PREFIX_EVEX_0F3892, | |
1561 | PREFIX_EVEX_0F3893, | |
43234a1e L |
1562 | PREFIX_EVEX_0F389A, |
1563 | PREFIX_EVEX_0F389B, | |
43234a1e L |
1564 | PREFIX_EVEX_0F38A0, |
1565 | PREFIX_EVEX_0F38A1, | |
1566 | PREFIX_EVEX_0F38A2, | |
1567 | PREFIX_EVEX_0F38A3, | |
43234a1e L |
1568 | PREFIX_EVEX_0F38AA, |
1569 | PREFIX_EVEX_0F38AB, | |
2cc1b5aa IT |
1570 | PREFIX_EVEX_0F38B4, |
1571 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1572 | PREFIX_EVEX_0F38C4, |
1573 | PREFIX_EVEX_0F38C6_REG_1, | |
1574 | PREFIX_EVEX_0F38C6_REG_2, | |
1575 | PREFIX_EVEX_0F38C6_REG_5, | |
1576 | PREFIX_EVEX_0F38C6_REG_6, | |
1577 | PREFIX_EVEX_0F38C7_REG_1, | |
1578 | PREFIX_EVEX_0F38C7_REG_2, | |
1579 | PREFIX_EVEX_0F38C7_REG_5, | |
1580 | PREFIX_EVEX_0F38C7_REG_6, | |
1581 | PREFIX_EVEX_0F38C8, | |
1582 | PREFIX_EVEX_0F38CA, | |
1583 | PREFIX_EVEX_0F38CB, | |
1584 | PREFIX_EVEX_0F38CC, | |
1585 | PREFIX_EVEX_0F38CD, | |
1586 | ||
1587 | PREFIX_EVEX_0F3A00, | |
1588 | PREFIX_EVEX_0F3A01, | |
1589 | PREFIX_EVEX_0F3A03, | |
43234a1e L |
1590 | PREFIX_EVEX_0F3A05, |
1591 | PREFIX_EVEX_0F3A08, | |
1592 | PREFIX_EVEX_0F3A09, | |
1593 | PREFIX_EVEX_0F3A0A, | |
1594 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1595 | PREFIX_EVEX_0F3A14, |
1596 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1597 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1598 | PREFIX_EVEX_0F3A17, |
1599 | PREFIX_EVEX_0F3A18, | |
1600 | PREFIX_EVEX_0F3A19, | |
1601 | PREFIX_EVEX_0F3A1A, | |
1602 | PREFIX_EVEX_0F3A1B, | |
43234a1e L |
1603 | PREFIX_EVEX_0F3A1E, |
1604 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1605 | PREFIX_EVEX_0F3A20, |
43234a1e | 1606 | PREFIX_EVEX_0F3A21, |
90a915bf | 1607 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1608 | PREFIX_EVEX_0F3A23, |
1609 | PREFIX_EVEX_0F3A25, | |
1610 | PREFIX_EVEX_0F3A26, | |
1611 | PREFIX_EVEX_0F3A27, | |
1612 | PREFIX_EVEX_0F3A38, | |
1613 | PREFIX_EVEX_0F3A39, | |
1614 | PREFIX_EVEX_0F3A3A, | |
1615 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1616 | PREFIX_EVEX_0F3A3E, |
1617 | PREFIX_EVEX_0F3A3F, | |
1618 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1619 | PREFIX_EVEX_0F3A43, |
90a915bf IT |
1620 | PREFIX_EVEX_0F3A50, |
1621 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1622 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1623 | PREFIX_EVEX_0F3A55, |
1624 | PREFIX_EVEX_0F3A56, | |
1625 | PREFIX_EVEX_0F3A57, | |
1626 | PREFIX_EVEX_0F3A66, | |
53467f57 IT |
1627 | PREFIX_EVEX_0F3A67, |
1628 | PREFIX_EVEX_0F3A70, | |
1629 | PREFIX_EVEX_0F3A71, | |
1630 | PREFIX_EVEX_0F3A72, | |
48521003 | 1631 | PREFIX_EVEX_0F3A73, |
51e7da1b | 1632 | }; |
4e7d34a6 | 1633 | |
51e7da1b L |
1634 | enum |
1635 | { | |
1636 | X86_64_06 = 0, | |
3873ba12 | 1637 | X86_64_07, |
1673df32 | 1638 | X86_64_0E, |
3873ba12 L |
1639 | X86_64_16, |
1640 | X86_64_17, | |
1641 | X86_64_1E, | |
1642 | X86_64_1F, | |
1643 | X86_64_27, | |
1644 | X86_64_2F, | |
1645 | X86_64_37, | |
1646 | X86_64_3F, | |
1647 | X86_64_60, | |
1648 | X86_64_61, | |
1649 | X86_64_62, | |
1650 | X86_64_63, | |
1651 | X86_64_6D, | |
1652 | X86_64_6F, | |
d039fef3 | 1653 | X86_64_82, |
3873ba12 | 1654 | X86_64_9A, |
aeab2b26 JB |
1655 | X86_64_C2, |
1656 | X86_64_C3, | |
3873ba12 L |
1657 | X86_64_C4, |
1658 | X86_64_C5, | |
1659 | X86_64_CE, | |
1660 | X86_64_D4, | |
1661 | X86_64_D5, | |
a72d2af2 L |
1662 | X86_64_E8, |
1663 | X86_64_E9, | |
3873ba12 L |
1664 | X86_64_EA, |
1665 | X86_64_0F01_REG_0, | |
1666 | X86_64_0F01_REG_1, | |
1667 | X86_64_0F01_REG_2, | |
1668 | X86_64_0F01_REG_3 | |
51e7da1b | 1669 | }; |
4e7d34a6 | 1670 | |
51e7da1b L |
1671 | enum |
1672 | { | |
1673 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1674 | THREE_BYTE_0F3A |
51e7da1b | 1675 | }; |
4e7d34a6 | 1676 | |
f88c9eb0 SP |
1677 | enum |
1678 | { | |
5dd85c99 SP |
1679 | XOP_08 = 0, |
1680 | XOP_09, | |
f88c9eb0 SP |
1681 | XOP_0A |
1682 | }; | |
1683 | ||
51e7da1b L |
1684 | enum |
1685 | { | |
1686 | VEX_0F = 0, | |
3873ba12 L |
1687 | VEX_0F38, |
1688 | VEX_0F3A | |
51e7da1b | 1689 | }; |
c0f3af97 | 1690 | |
43234a1e L |
1691 | enum |
1692 | { | |
1693 | EVEX_0F = 0, | |
1694 | EVEX_0F38, | |
1695 | EVEX_0F3A | |
1696 | }; | |
1697 | ||
51e7da1b L |
1698 | enum |
1699 | { | |
ec6f095a | 1700 | VEX_LEN_0F12_P_0_M_0 = 0, |
592a252b | 1701 | VEX_LEN_0F12_P_0_M_1, |
18897deb | 1702 | #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0 |
592a252b L |
1703 | VEX_LEN_0F13_M_0, |
1704 | VEX_LEN_0F16_P_0_M_0, | |
1705 | VEX_LEN_0F16_P_0_M_1, | |
18897deb | 1706 | #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0 |
592a252b | 1707 | VEX_LEN_0F17_M_0, |
43234a1e | 1708 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1709 | VEX_LEN_0F41_P_2, |
43234a1e | 1710 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1711 | VEX_LEN_0F42_P_2, |
43234a1e | 1712 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1713 | VEX_LEN_0F44_P_2, |
43234a1e | 1714 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1715 | VEX_LEN_0F45_P_2, |
43234a1e | 1716 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1717 | VEX_LEN_0F46_P_2, |
43234a1e | 1718 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1719 | VEX_LEN_0F47_P_2, |
1720 | VEX_LEN_0F4A_P_0, | |
1721 | VEX_LEN_0F4A_P_2, | |
1722 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1723 | VEX_LEN_0F4B_P_2, |
592a252b | 1724 | VEX_LEN_0F6E_P_2, |
ec6f095a | 1725 | VEX_LEN_0F77_P_0, |
592a252b L |
1726 | VEX_LEN_0F7E_P_1, |
1727 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1728 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1729 | VEX_LEN_0F90_P_2, |
43234a1e | 1730 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1731 | VEX_LEN_0F91_P_2, |
43234a1e | 1732 | VEX_LEN_0F92_P_0, |
90a915bf | 1733 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1734 | VEX_LEN_0F92_P_3, |
43234a1e | 1735 | VEX_LEN_0F93_P_0, |
90a915bf | 1736 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1737 | VEX_LEN_0F93_P_3, |
43234a1e | 1738 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1739 | VEX_LEN_0F98_P_2, |
1740 | VEX_LEN_0F99_P_0, | |
1741 | VEX_LEN_0F99_P_2, | |
592a252b L |
1742 | VEX_LEN_0FAE_R_2_M_0, |
1743 | VEX_LEN_0FAE_R_3_M_0, | |
592a252b L |
1744 | VEX_LEN_0FC4_P_2, |
1745 | VEX_LEN_0FC5_P_2, | |
592a252b | 1746 | VEX_LEN_0FD6_P_2, |
592a252b | 1747 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1748 | VEX_LEN_0F3816_P_2, |
1749 | VEX_LEN_0F3819_P_2, | |
592a252b | 1750 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1751 | VEX_LEN_0F3836_P_2, |
592a252b | 1752 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1753 | VEX_LEN_0F385A_P_2_M_0, |
592a252b | 1754 | VEX_LEN_0F38DB_P_2, |
f12dc422 L |
1755 | VEX_LEN_0F38F2_P_0, |
1756 | VEX_LEN_0F38F3_R_1_P_0, | |
1757 | VEX_LEN_0F38F3_R_2_P_0, | |
1758 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1759 | VEX_LEN_0F38F5_P_0, |
1760 | VEX_LEN_0F38F5_P_1, | |
1761 | VEX_LEN_0F38F5_P_3, | |
1762 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1763 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1764 | VEX_LEN_0F38F7_P_1, |
1765 | VEX_LEN_0F38F7_P_2, | |
1766 | VEX_LEN_0F38F7_P_3, | |
1767 | VEX_LEN_0F3A00_P_2, | |
1768 | VEX_LEN_0F3A01_P_2, | |
592a252b | 1769 | VEX_LEN_0F3A06_P_2, |
592a252b L |
1770 | VEX_LEN_0F3A14_P_2, |
1771 | VEX_LEN_0F3A15_P_2, | |
1772 | VEX_LEN_0F3A16_P_2, | |
1773 | VEX_LEN_0F3A17_P_2, | |
1774 | VEX_LEN_0F3A18_P_2, | |
1775 | VEX_LEN_0F3A19_P_2, | |
1776 | VEX_LEN_0F3A20_P_2, | |
1777 | VEX_LEN_0F3A21_P_2, | |
1778 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1779 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1780 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1781 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1782 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1783 | VEX_LEN_0F3A38_P_2, |
1784 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1785 | VEX_LEN_0F3A41_P_2, |
6c30d220 | 1786 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1787 | VEX_LEN_0F3A60_P_2, |
1788 | VEX_LEN_0F3A61_P_2, | |
1789 | VEX_LEN_0F3A62_P_2, | |
1790 | VEX_LEN_0F3A63_P_2, | |
1791 | VEX_LEN_0F3A6A_P_2, | |
1792 | VEX_LEN_0F3A6B_P_2, | |
1793 | VEX_LEN_0F3A6E_P_2, | |
1794 | VEX_LEN_0F3A6F_P_2, | |
1795 | VEX_LEN_0F3A7A_P_2, | |
1796 | VEX_LEN_0F3A7B_P_2, | |
1797 | VEX_LEN_0F3A7E_P_2, | |
1798 | VEX_LEN_0F3A7F_P_2, | |
1799 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1800 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1801 | VEX_LEN_0FXOP_08_CC, |
1802 | VEX_LEN_0FXOP_08_CD, | |
1803 | VEX_LEN_0FXOP_08_CE, | |
1804 | VEX_LEN_0FXOP_08_CF, | |
1805 | VEX_LEN_0FXOP_08_EC, | |
1806 | VEX_LEN_0FXOP_08_ED, | |
1807 | VEX_LEN_0FXOP_08_EE, | |
1808 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1809 | VEX_LEN_0FXOP_09_80, |
1810 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1811 | }; |
c0f3af97 | 1812 | |
04e2a182 L |
1813 | enum |
1814 | { | |
1815 | EVEX_LEN_0F6E_P_2 = 0, | |
1816 | EVEX_LEN_0F7E_P_1, | |
1817 | EVEX_LEN_0F7E_P_2, | |
e74d9fa9 JB |
1818 | EVEX_LEN_0FC4_P_2, |
1819 | EVEX_LEN_0FC5_P_2, | |
12efd68d | 1820 | EVEX_LEN_0FD6_P_2, |
3a57774c | 1821 | EVEX_LEN_0F3816_P_2, |
f0a6222e L |
1822 | EVEX_LEN_0F3819_P_2_W_0, |
1823 | EVEX_LEN_0F3819_P_2_W_1, | |
1824 | EVEX_LEN_0F381A_P_2_W_0, | |
1825 | EVEX_LEN_0F381A_P_2_W_1, | |
1826 | EVEX_LEN_0F381B_P_2_W_0, | |
1827 | EVEX_LEN_0F381B_P_2_W_1, | |
3a57774c | 1828 | EVEX_LEN_0F3836_P_2, |
f0a6222e L |
1829 | EVEX_LEN_0F385A_P_2_W_0, |
1830 | EVEX_LEN_0F385A_P_2_W_1, | |
1831 | EVEX_LEN_0F385B_P_2_W_0, | |
1832 | EVEX_LEN_0F385B_P_2_W_1, | |
e395f487 L |
1833 | EVEX_LEN_0F38C6_REG_1_PREFIX_2, |
1834 | EVEX_LEN_0F38C6_REG_2_PREFIX_2, | |
1835 | EVEX_LEN_0F38C6_REG_5_PREFIX_2, | |
1836 | EVEX_LEN_0F38C6_REG_6_PREFIX_2, | |
1837 | EVEX_LEN_0F38C7_R_1_P_2_W_0, | |
1838 | EVEX_LEN_0F38C7_R_1_P_2_W_1, | |
1839 | EVEX_LEN_0F38C7_R_2_P_2_W_0, | |
1840 | EVEX_LEN_0F38C7_R_2_P_2_W_1, | |
1841 | EVEX_LEN_0F38C7_R_5_P_2_W_0, | |
1842 | EVEX_LEN_0F38C7_R_5_P_2_W_1, | |
1843 | EVEX_LEN_0F38C7_R_6_P_2_W_0, | |
1844 | EVEX_LEN_0F38C7_R_6_P_2_W_1, | |
3a57774c JB |
1845 | EVEX_LEN_0F3A00_P_2_W_1, |
1846 | EVEX_LEN_0F3A01_P_2_W_1, | |
e74d9fa9 JB |
1847 | EVEX_LEN_0F3A14_P_2, |
1848 | EVEX_LEN_0F3A15_P_2, | |
1849 | EVEX_LEN_0F3A16_P_2, | |
1850 | EVEX_LEN_0F3A17_P_2, | |
12efd68d L |
1851 | EVEX_LEN_0F3A18_P_2_W_0, |
1852 | EVEX_LEN_0F3A18_P_2_W_1, | |
1853 | EVEX_LEN_0F3A19_P_2_W_0, | |
1854 | EVEX_LEN_0F3A19_P_2_W_1, | |
1855 | EVEX_LEN_0F3A1A_P_2_W_0, | |
1856 | EVEX_LEN_0F3A1A_P_2_W_1, | |
1857 | EVEX_LEN_0F3A1B_P_2_W_0, | |
6e1c90b7 | 1858 | EVEX_LEN_0F3A1B_P_2_W_1, |
e74d9fa9 JB |
1859 | EVEX_LEN_0F3A20_P_2, |
1860 | EVEX_LEN_0F3A21_P_2_W_0, | |
1861 | EVEX_LEN_0F3A22_P_2, | |
6e1c90b7 L |
1862 | EVEX_LEN_0F3A23_P_2_W_0, |
1863 | EVEX_LEN_0F3A23_P_2_W_1, | |
1864 | EVEX_LEN_0F3A38_P_2_W_0, | |
1865 | EVEX_LEN_0F3A38_P_2_W_1, | |
1866 | EVEX_LEN_0F3A39_P_2_W_0, | |
1867 | EVEX_LEN_0F3A39_P_2_W_1, | |
1868 | EVEX_LEN_0F3A3A_P_2_W_0, | |
1869 | EVEX_LEN_0F3A3A_P_2_W_1, | |
1870 | EVEX_LEN_0F3A3B_P_2_W_0, | |
1871 | EVEX_LEN_0F3A3B_P_2_W_1, | |
1872 | EVEX_LEN_0F3A43_P_2_W_0, | |
1873 | EVEX_LEN_0F3A43_P_2_W_1 | |
04e2a182 L |
1874 | }; |
1875 | ||
9e30b8e0 L |
1876 | enum |
1877 | { | |
ec6f095a | 1878 | VEX_W_0F41_P_0_LEN_1 = 0, |
1ba585e8 | 1879 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1880 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1881 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1882 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1883 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1884 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1885 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1886 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1887 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1888 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1889 | VEX_W_0F47_P_2_LEN_1, |
1890 | VEX_W_0F4A_P_0_LEN_1, | |
1891 | VEX_W_0F4A_P_2_LEN_1, | |
1892 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1893 | VEX_W_0F4B_P_2_LEN_1, |
43234a1e | 1894 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 1895 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 1896 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 1897 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 1898 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 1899 | VEX_W_0F92_P_2_LEN_0, |
43234a1e | 1900 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 1901 | VEX_W_0F93_P_2_LEN_0, |
43234a1e | 1902 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
1903 | VEX_W_0F98_P_2_LEN_0, |
1904 | VEX_W_0F99_P_0_LEN_0, | |
1905 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
1906 | VEX_W_0F380C_P_2, |
1907 | VEX_W_0F380D_P_2, | |
1908 | VEX_W_0F380E_P_2, | |
1909 | VEX_W_0F380F_P_2, | |
6431c801 | 1910 | VEX_W_0F3813_P_2, |
6c30d220 | 1911 | VEX_W_0F3816_P_2, |
6c30d220 L |
1912 | VEX_W_0F3818_P_2, |
1913 | VEX_W_0F3819_P_2, | |
592a252b | 1914 | VEX_W_0F381A_P_2_M_0, |
592a252b L |
1915 | VEX_W_0F382C_P_2_M_0, |
1916 | VEX_W_0F382D_P_2_M_0, | |
1917 | VEX_W_0F382E_P_2_M_0, | |
1918 | VEX_W_0F382F_P_2_M_0, | |
6c30d220 | 1919 | VEX_W_0F3836_P_2, |
6c30d220 L |
1920 | VEX_W_0F3846_P_2, |
1921 | VEX_W_0F3858_P_2, | |
1922 | VEX_W_0F3859_P_2, | |
1923 | VEX_W_0F385A_P_2_M_0, | |
1924 | VEX_W_0F3878_P_2, | |
1925 | VEX_W_0F3879_P_2, | |
48521003 | 1926 | VEX_W_0F38CF_P_2, |
6c30d220 L |
1927 | VEX_W_0F3A00_P_2, |
1928 | VEX_W_0F3A01_P_2, | |
1929 | VEX_W_0F3A02_P_2, | |
592a252b L |
1930 | VEX_W_0F3A04_P_2, |
1931 | VEX_W_0F3A05_P_2, | |
1932 | VEX_W_0F3A06_P_2, | |
592a252b L |
1933 | VEX_W_0F3A18_P_2, |
1934 | VEX_W_0F3A19_P_2, | |
6431c801 | 1935 | VEX_W_0F3A1D_P_2, |
43234a1e | 1936 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 1937 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 1938 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 1939 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
1940 | VEX_W_0F3A38_P_2, |
1941 | VEX_W_0F3A39_P_2, | |
6c30d220 | 1942 | VEX_W_0F3A46_P_2, |
592a252b L |
1943 | VEX_W_0F3A48_P_2, |
1944 | VEX_W_0F3A49_P_2, | |
1945 | VEX_W_0F3A4A_P_2, | |
1946 | VEX_W_0F3A4B_P_2, | |
1947 | VEX_W_0F3A4C_P_2, | |
48521003 IT |
1948 | VEX_W_0F3ACE_P_2, |
1949 | VEX_W_0F3ACF_P_2, | |
43234a1e | 1950 | |
36cc073e | 1951 | EVEX_W_0F10_P_1, |
36cc073e | 1952 | EVEX_W_0F10_P_3, |
36cc073e | 1953 | EVEX_W_0F11_P_1, |
36cc073e | 1954 | EVEX_W_0F11_P_3, |
43234a1e L |
1955 | EVEX_W_0F12_P_0_M_1, |
1956 | EVEX_W_0F12_P_1, | |
43234a1e | 1957 | EVEX_W_0F12_P_3, |
43234a1e L |
1958 | EVEX_W_0F16_P_0_M_1, |
1959 | EVEX_W_0F16_P_1, | |
43234a1e | 1960 | EVEX_W_0F2A_P_3, |
43234a1e | 1961 | EVEX_W_0F51_P_1, |
43234a1e | 1962 | EVEX_W_0F51_P_3, |
43234a1e | 1963 | EVEX_W_0F58_P_1, |
43234a1e | 1964 | EVEX_W_0F58_P_3, |
43234a1e | 1965 | EVEX_W_0F59_P_1, |
43234a1e L |
1966 | EVEX_W_0F59_P_3, |
1967 | EVEX_W_0F5A_P_0, | |
1968 | EVEX_W_0F5A_P_1, | |
1969 | EVEX_W_0F5A_P_2, | |
1970 | EVEX_W_0F5A_P_3, | |
1971 | EVEX_W_0F5B_P_0, | |
1972 | EVEX_W_0F5B_P_1, | |
1973 | EVEX_W_0F5B_P_2, | |
43234a1e | 1974 | EVEX_W_0F5C_P_1, |
43234a1e | 1975 | EVEX_W_0F5C_P_3, |
43234a1e | 1976 | EVEX_W_0F5D_P_1, |
43234a1e | 1977 | EVEX_W_0F5D_P_3, |
43234a1e | 1978 | EVEX_W_0F5E_P_1, |
43234a1e | 1979 | EVEX_W_0F5E_P_3, |
43234a1e | 1980 | EVEX_W_0F5F_P_1, |
43234a1e | 1981 | EVEX_W_0F5F_P_3, |
fedfb81e | 1982 | EVEX_W_0F62, |
43234a1e | 1983 | EVEX_W_0F66_P_2, |
fedfb81e JB |
1984 | EVEX_W_0F6A, |
1985 | EVEX_W_0F6B, | |
1986 | EVEX_W_0F6C, | |
1987 | EVEX_W_0F6D, | |
43234a1e L |
1988 | EVEX_W_0F6F_P_1, |
1989 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 1990 | EVEX_W_0F6F_P_3, |
43234a1e L |
1991 | EVEX_W_0F70_P_2, |
1992 | EVEX_W_0F72_R_2_P_2, | |
1993 | EVEX_W_0F72_R_6_P_2, | |
1994 | EVEX_W_0F73_R_2_P_2, | |
1995 | EVEX_W_0F73_R_6_P_2, | |
1996 | EVEX_W_0F76_P_2, | |
1997 | EVEX_W_0F78_P_0, | |
90a915bf | 1998 | EVEX_W_0F78_P_2, |
43234a1e | 1999 | EVEX_W_0F79_P_0, |
90a915bf | 2000 | EVEX_W_0F79_P_2, |
43234a1e | 2001 | EVEX_W_0F7A_P_1, |
90a915bf | 2002 | EVEX_W_0F7A_P_2, |
43234a1e | 2003 | EVEX_W_0F7A_P_3, |
90a915bf | 2004 | EVEX_W_0F7B_P_2, |
43234a1e L |
2005 | EVEX_W_0F7B_P_3, |
2006 | EVEX_W_0F7E_P_1, | |
43234a1e L |
2007 | EVEX_W_0F7F_P_1, |
2008 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2009 | EVEX_W_0F7F_P_3, |
43234a1e | 2010 | EVEX_W_0FC2_P_1, |
43234a1e | 2011 | EVEX_W_0FC2_P_3, |
fedfb81e JB |
2012 | EVEX_W_0FD2, |
2013 | EVEX_W_0FD3, | |
2014 | EVEX_W_0FD4, | |
43234a1e L |
2015 | EVEX_W_0FD6_P_2, |
2016 | EVEX_W_0FE6_P_1, | |
2017 | EVEX_W_0FE6_P_2, | |
2018 | EVEX_W_0FE6_P_3, | |
2019 | EVEX_W_0FE7_P_2, | |
fedfb81e JB |
2020 | EVEX_W_0FF2, |
2021 | EVEX_W_0FF3, | |
2022 | EVEX_W_0FF4, | |
2023 | EVEX_W_0FFA, | |
2024 | EVEX_W_0FFB, | |
2025 | EVEX_W_0FFE, | |
43234a1e | 2026 | EVEX_W_0F380D_P_2, |
1ba585e8 IT |
2027 | EVEX_W_0F3810_P_1, |
2028 | EVEX_W_0F3810_P_2, | |
43234a1e | 2029 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2030 | EVEX_W_0F3811_P_2, |
43234a1e | 2031 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2032 | EVEX_W_0F3812_P_2, |
43234a1e L |
2033 | EVEX_W_0F3813_P_1, |
2034 | EVEX_W_0F3813_P_2, | |
2035 | EVEX_W_0F3814_P_1, | |
2036 | EVEX_W_0F3815_P_1, | |
43234a1e L |
2037 | EVEX_W_0F3819_P_2, |
2038 | EVEX_W_0F381A_P_2, | |
2039 | EVEX_W_0F381B_P_2, | |
2040 | EVEX_W_0F381E_P_2, | |
2041 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2042 | EVEX_W_0F3820_P_1, |
43234a1e L |
2043 | EVEX_W_0F3821_P_1, |
2044 | EVEX_W_0F3822_P_1, | |
2045 | EVEX_W_0F3823_P_1, | |
2046 | EVEX_W_0F3824_P_1, | |
2047 | EVEX_W_0F3825_P_1, | |
2048 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2049 | EVEX_W_0F3826_P_1, |
2050 | EVEX_W_0F3826_P_2, | |
2051 | EVEX_W_0F3828_P_1, | |
43234a1e | 2052 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2053 | EVEX_W_0F3829_P_1, |
43234a1e L |
2054 | EVEX_W_0F3829_P_2, |
2055 | EVEX_W_0F382A_P_1, | |
2056 | EVEX_W_0F382A_P_2, | |
fedfb81e | 2057 | EVEX_W_0F382B, |
1ba585e8 | 2058 | EVEX_W_0F3830_P_1, |
43234a1e L |
2059 | EVEX_W_0F3831_P_1, |
2060 | EVEX_W_0F3832_P_1, | |
2061 | EVEX_W_0F3833_P_1, | |
2062 | EVEX_W_0F3834_P_1, | |
2063 | EVEX_W_0F3835_P_1, | |
2064 | EVEX_W_0F3835_P_2, | |
2065 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2066 | EVEX_W_0F3838_P_1, |
2067 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2068 | EVEX_W_0F383A_P_1, |
2069 | EVEX_W_0F3840_P_2, | |
d6aab7a1 | 2070 | EVEX_W_0F3852_P_1, |
ee6872be | 2071 | EVEX_W_0F3854_P_2, |
620214f7 | 2072 | EVEX_W_0F3855_P_2, |
43234a1e L |
2073 | EVEX_W_0F3859_P_2, |
2074 | EVEX_W_0F385A_P_2, | |
2075 | EVEX_W_0F385B_P_2, | |
53467f57 IT |
2076 | EVEX_W_0F3862_P_2, |
2077 | EVEX_W_0F3863_P_2, | |
1ba585e8 | 2078 | EVEX_W_0F3866_P_2, |
9186c494 | 2079 | EVEX_W_0F3868_P_3, |
53467f57 IT |
2080 | EVEX_W_0F3870_P_2, |
2081 | EVEX_W_0F3871_P_2, | |
d6aab7a1 | 2082 | EVEX_W_0F3872_P_1, |
53467f57 | 2083 | EVEX_W_0F3872_P_2, |
d6aab7a1 | 2084 | EVEX_W_0F3872_P_3, |
53467f57 | 2085 | EVEX_W_0F3873_P_2, |
1ba585e8 | 2086 | EVEX_W_0F3875_P_2, |
1ba585e8 IT |
2087 | EVEX_W_0F387A_P_2, |
2088 | EVEX_W_0F387B_P_2, | |
2089 | EVEX_W_0F387D_P_2, | |
14f195c9 | 2090 | EVEX_W_0F3883_P_2, |
1ba585e8 | 2091 | EVEX_W_0F388D_P_2, |
43234a1e L |
2092 | EVEX_W_0F3891_P_2, |
2093 | EVEX_W_0F3893_P_2, | |
2094 | EVEX_W_0F38A1_P_2, | |
2095 | EVEX_W_0F38A3_P_2, | |
2096 | EVEX_W_0F38C7_R_1_P_2, | |
2097 | EVEX_W_0F38C7_R_2_P_2, | |
2098 | EVEX_W_0F38C7_R_5_P_2, | |
2099 | EVEX_W_0F38C7_R_6_P_2, | |
2100 | ||
2101 | EVEX_W_0F3A00_P_2, | |
2102 | EVEX_W_0F3A01_P_2, | |
43234a1e L |
2103 | EVEX_W_0F3A05_P_2, |
2104 | EVEX_W_0F3A08_P_2, | |
2105 | EVEX_W_0F3A09_P_2, | |
2106 | EVEX_W_0F3A0A_P_2, | |
2107 | EVEX_W_0F3A0B_P_2, | |
2108 | EVEX_W_0F3A18_P_2, | |
2109 | EVEX_W_0F3A19_P_2, | |
2110 | EVEX_W_0F3A1A_P_2, | |
2111 | EVEX_W_0F3A1B_P_2, | |
43234a1e L |
2112 | EVEX_W_0F3A21_P_2, |
2113 | EVEX_W_0F3A23_P_2, | |
2114 | EVEX_W_0F3A38_P_2, | |
2115 | EVEX_W_0F3A39_P_2, | |
2116 | EVEX_W_0F3A3A_P_2, | |
2117 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2118 | EVEX_W_0F3A3E_P_2, |
2119 | EVEX_W_0F3A3F_P_2, | |
2120 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2121 | EVEX_W_0F3A43_P_2, |
2122 | EVEX_W_0F3A50_P_2, | |
2123 | EVEX_W_0F3A51_P_2, | |
2124 | EVEX_W_0F3A56_P_2, | |
2125 | EVEX_W_0F3A57_P_2, | |
2126 | EVEX_W_0F3A66_P_2, | |
53467f57 IT |
2127 | EVEX_W_0F3A67_P_2, |
2128 | EVEX_W_0F3A70_P_2, | |
2129 | EVEX_W_0F3A71_P_2, | |
2130 | EVEX_W_0F3A72_P_2, | |
48521003 | 2131 | EVEX_W_0F3A73_P_2, |
9e30b8e0 L |
2132 | }; |
2133 | ||
26ca5450 | 2134 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2135 | |
2136 | struct dis386 { | |
2da11e11 | 2137 | const char *name; |
ce518a5f L |
2138 | struct |
2139 | { | |
2140 | op_rtn rtn; | |
2141 | int bytemode; | |
2142 | } op[MAX_OPERANDS]; | |
bf890a93 | 2143 | unsigned int prefix_requirement; |
252b5132 RH |
2144 | }; |
2145 | ||
2146 | /* Upper case letters in the instruction names here are macros. | |
2147 | 'A' => print 'b' if no register operands or suffix_always is true | |
2148 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2149 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2150 | size prefix |
ed7841b3 | 2151 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2152 | suffix_always is true |
252b5132 | 2153 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2154 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2155 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2156 | 'H' => print ",pt" or ",pn" branch hint |
d1c36125 | 2157 | 'I' unused. |
8f570d62 | 2158 | 'J' unused. |
42903f7f | 2159 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2160 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2161 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2162 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2163 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2164 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2165 | or suffix_always is true. print 'q' if rex prefix is present. |
2166 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2167 | is true | |
a35ca55a | 2168 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2169 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2170 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2171 | prefix and behave as 'P' otherwise | |
2172 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2173 | prefix and behave as 'Q' otherwise | |
2174 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2175 | prefix and behave as 'S' otherwise | |
a35ca55a | 2176 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2177 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 2178 | 'Y' unused. |
6dd5059a | 2179 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2180 | '!' => change condition from true to false or from false to true. |
98b528ac | 2181 | '%' => add 1 upper case letter to the macro. |
5990e377 JB |
2182 | '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size |
2183 | prefix or suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2184 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2185 | on operand size prefix. | |
07f5af7d L |
2186 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2187 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2188 | otherwise | |
98b528ac L |
2189 | |
2190 | 2 upper case letter macros: | |
04d824a4 JB |
2191 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2192 | operands and no broadcast. | |
2193 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2194 | register operands and no broadcast. | |
4b06377f | 2195 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
589958d6 JB |
2196 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory |
2197 | operand or no operand at all in 64bit mode, or if suffix_always | |
2198 | is true. | |
4b06377f L |
2199 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2200 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2201 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2202 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2203 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2204 | an operand size prefix, or suffix_always is true. print | |
2205 | 'q' if rex prefix is present. | |
52b15da3 | 2206 | |
6439fc28 AM |
2207 | Many of the above letters print nothing in Intel mode. See "putop" |
2208 | for the details. | |
52b15da3 | 2209 | |
6439fc28 | 2210 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2211 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2212 | |
6439fc28 | 2213 | static const struct dis386 dis386[] = { |
252b5132 | 2214 | /* 00 */ |
bf890a93 IT |
2215 | { "addB", { Ebh1, Gb }, 0 }, |
2216 | { "addS", { Evh1, Gv }, 0 }, | |
2217 | { "addB", { Gb, EbS }, 0 }, | |
2218 | { "addS", { Gv, EvS }, 0 }, | |
2219 | { "addB", { AL, Ib }, 0 }, | |
2220 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2221 | { X86_64_TABLE (X86_64_06) }, |
2222 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2223 | /* 08 */ |
bf890a93 IT |
2224 | { "orB", { Ebh1, Gb }, 0 }, |
2225 | { "orS", { Evh1, Gv }, 0 }, | |
2226 | { "orB", { Gb, EbS }, 0 }, | |
2227 | { "orS", { Gv, EvS }, 0 }, | |
2228 | { "orB", { AL, Ib }, 0 }, | |
2229 | { "orS", { eAX, Iv }, 0 }, | |
1673df32 | 2230 | { X86_64_TABLE (X86_64_0E) }, |
592d1631 | 2231 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2232 | /* 10 */ |
bf890a93 IT |
2233 | { "adcB", { Ebh1, Gb }, 0 }, |
2234 | { "adcS", { Evh1, Gv }, 0 }, | |
2235 | { "adcB", { Gb, EbS }, 0 }, | |
2236 | { "adcS", { Gv, EvS }, 0 }, | |
2237 | { "adcB", { AL, Ib }, 0 }, | |
2238 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2239 | { X86_64_TABLE (X86_64_16) }, |
2240 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2241 | /* 18 */ |
bf890a93 IT |
2242 | { "sbbB", { Ebh1, Gb }, 0 }, |
2243 | { "sbbS", { Evh1, Gv }, 0 }, | |
2244 | { "sbbB", { Gb, EbS }, 0 }, | |
2245 | { "sbbS", { Gv, EvS }, 0 }, | |
2246 | { "sbbB", { AL, Ib }, 0 }, | |
2247 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2248 | { X86_64_TABLE (X86_64_1E) }, |
2249 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2250 | /* 20 */ |
bf890a93 IT |
2251 | { "andB", { Ebh1, Gb }, 0 }, |
2252 | { "andS", { Evh1, Gv }, 0 }, | |
2253 | { "andB", { Gb, EbS }, 0 }, | |
2254 | { "andS", { Gv, EvS }, 0 }, | |
2255 | { "andB", { AL, Ib }, 0 }, | |
2256 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2257 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2258 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2259 | /* 28 */ |
bf890a93 IT |
2260 | { "subB", { Ebh1, Gb }, 0 }, |
2261 | { "subS", { Evh1, Gv }, 0 }, | |
2262 | { "subB", { Gb, EbS }, 0 }, | |
2263 | { "subS", { Gv, EvS }, 0 }, | |
2264 | { "subB", { AL, Ib }, 0 }, | |
2265 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2266 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2267 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2268 | /* 30 */ |
bf890a93 IT |
2269 | { "xorB", { Ebh1, Gb }, 0 }, |
2270 | { "xorS", { Evh1, Gv }, 0 }, | |
2271 | { "xorB", { Gb, EbS }, 0 }, | |
2272 | { "xorS", { Gv, EvS }, 0 }, | |
2273 | { "xorB", { AL, Ib }, 0 }, | |
2274 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2275 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2276 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2277 | /* 38 */ |
bf890a93 IT |
2278 | { "cmpB", { Eb, Gb }, 0 }, |
2279 | { "cmpS", { Ev, Gv }, 0 }, | |
2280 | { "cmpB", { Gb, EbS }, 0 }, | |
2281 | { "cmpS", { Gv, EvS }, 0 }, | |
2282 | { "cmpB", { AL, Ib }, 0 }, | |
2283 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2284 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2285 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2286 | /* 40 */ |
bf890a93 IT |
2287 | { "inc{S|}", { RMeAX }, 0 }, |
2288 | { "inc{S|}", { RMeCX }, 0 }, | |
2289 | { "inc{S|}", { RMeDX }, 0 }, | |
2290 | { "inc{S|}", { RMeBX }, 0 }, | |
2291 | { "inc{S|}", { RMeSP }, 0 }, | |
2292 | { "inc{S|}", { RMeBP }, 0 }, | |
2293 | { "inc{S|}", { RMeSI }, 0 }, | |
2294 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2295 | /* 48 */ |
bf890a93 IT |
2296 | { "dec{S|}", { RMeAX }, 0 }, |
2297 | { "dec{S|}", { RMeCX }, 0 }, | |
2298 | { "dec{S|}", { RMeDX }, 0 }, | |
2299 | { "dec{S|}", { RMeBX }, 0 }, | |
2300 | { "dec{S|}", { RMeSP }, 0 }, | |
2301 | { "dec{S|}", { RMeBP }, 0 }, | |
2302 | { "dec{S|}", { RMeSI }, 0 }, | |
2303 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2304 | /* 50 */ |
bf890a93 IT |
2305 | { "pushV", { RMrAX }, 0 }, |
2306 | { "pushV", { RMrCX }, 0 }, | |
2307 | { "pushV", { RMrDX }, 0 }, | |
2308 | { "pushV", { RMrBX }, 0 }, | |
2309 | { "pushV", { RMrSP }, 0 }, | |
2310 | { "pushV", { RMrBP }, 0 }, | |
2311 | { "pushV", { RMrSI }, 0 }, | |
2312 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2313 | /* 58 */ |
bf890a93 IT |
2314 | { "popV", { RMrAX }, 0 }, |
2315 | { "popV", { RMrCX }, 0 }, | |
2316 | { "popV", { RMrDX }, 0 }, | |
2317 | { "popV", { RMrBX }, 0 }, | |
2318 | { "popV", { RMrSP }, 0 }, | |
2319 | { "popV", { RMrBP }, 0 }, | |
2320 | { "popV", { RMrSI }, 0 }, | |
2321 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2322 | /* 60 */ |
4e7d34a6 L |
2323 | { X86_64_TABLE (X86_64_60) }, |
2324 | { X86_64_TABLE (X86_64_61) }, | |
2325 | { X86_64_TABLE (X86_64_62) }, | |
2326 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2327 | { Bad_Opcode }, /* seg fs */ |
2328 | { Bad_Opcode }, /* seg gs */ | |
2329 | { Bad_Opcode }, /* op size prefix */ | |
2330 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2331 | /* 68 */ |
bf890a93 IT |
2332 | { "pushT", { sIv }, 0 }, |
2333 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2334 | { "pushT", { sIbT }, 0 }, | |
2335 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2336 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2337 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2338 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2339 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2340 | /* 70 */ |
bf890a93 IT |
2341 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2342 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2343 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2344 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2345 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2346 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2347 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2348 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2349 | /* 78 */ |
bf890a93 IT |
2350 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2351 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2352 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2353 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2354 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2355 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2356 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2357 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2358 | /* 80 */ |
1ceb70f8 L |
2359 | { REG_TABLE (REG_80) }, |
2360 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2361 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2362 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2363 | { "testB", { Eb, Gb }, 0 }, |
2364 | { "testS", { Ev, Gv }, 0 }, | |
2365 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2366 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2367 | /* 88 */ |
bf890a93 IT |
2368 | { "movB", { Ebh3, Gb }, 0 }, |
2369 | { "movS", { Evh3, Gv }, 0 }, | |
2370 | { "movB", { Gb, EbS }, 0 }, | |
2371 | { "movS", { Gv, EvS }, 0 }, | |
2372 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2373 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2374 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2375 | { REG_TABLE (REG_8F) }, |
252b5132 | 2376 | /* 90 */ |
1ceb70f8 | 2377 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2378 | { "xchgS", { RMeCX, eAX }, 0 }, |
2379 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2380 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2381 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2382 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2383 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2384 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2385 | /* 98 */ |
bf890a93 IT |
2386 | { "cW{t|}R", { XX }, 0 }, |
2387 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2388 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2389 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2390 | { "pushfT", { XX }, 0 }, |
2391 | { "popfT", { XX }, 0 }, | |
2392 | { "sahf", { XX }, 0 }, | |
2393 | { "lahf", { XX }, 0 }, | |
252b5132 | 2394 | /* a0 */ |
bf890a93 IT |
2395 | { "mov%LB", { AL, Ob }, 0 }, |
2396 | { "mov%LS", { eAX, Ov }, 0 }, | |
2397 | { "mov%LB", { Ob, AL }, 0 }, | |
2398 | { "mov%LS", { Ov, eAX }, 0 }, | |
2399 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2400 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2401 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2402 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2403 | /* a8 */ |
bf890a93 IT |
2404 | { "testB", { AL, Ib }, 0 }, |
2405 | { "testS", { eAX, Iv }, 0 }, | |
2406 | { "stosB", { Ybr, AL }, 0 }, | |
2407 | { "stosS", { Yvr, eAX }, 0 }, | |
2408 | { "lodsB", { ALr, Xb }, 0 }, | |
2409 | { "lodsS", { eAXr, Xv }, 0 }, | |
2410 | { "scasB", { AL, Yb }, 0 }, | |
2411 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2412 | /* b0 */ |
bf890a93 IT |
2413 | { "movB", { RMAL, Ib }, 0 }, |
2414 | { "movB", { RMCL, Ib }, 0 }, | |
2415 | { "movB", { RMDL, Ib }, 0 }, | |
2416 | { "movB", { RMBL, Ib }, 0 }, | |
2417 | { "movB", { RMAH, Ib }, 0 }, | |
2418 | { "movB", { RMCH, Ib }, 0 }, | |
2419 | { "movB", { RMDH, Ib }, 0 }, | |
2420 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2421 | /* b8 */ |
bf890a93 IT |
2422 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2423 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2424 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2425 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2426 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2427 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2428 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2429 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2430 | /* c0 */ |
1ceb70f8 L |
2431 | { REG_TABLE (REG_C0) }, |
2432 | { REG_TABLE (REG_C1) }, | |
aeab2b26 JB |
2433 | { X86_64_TABLE (X86_64_C2) }, |
2434 | { X86_64_TABLE (X86_64_C3) }, | |
4e7d34a6 L |
2435 | { X86_64_TABLE (X86_64_C4) }, |
2436 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2437 | { REG_TABLE (REG_C6) }, |
2438 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2439 | /* c8 */ |
bf890a93 IT |
2440 | { "enterT", { Iw, Ib }, 0 }, |
2441 | { "leaveT", { XX }, 0 }, | |
8f570d62 JB |
2442 | { "{l|}ret{|f}P", { Iw }, 0 }, |
2443 | { "{l|}ret{|f}P", { XX }, 0 }, | |
bf890a93 IT |
2444 | { "int3", { XX }, 0 }, |
2445 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2446 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2447 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2448 | /* d0 */ |
1ceb70f8 L |
2449 | { REG_TABLE (REG_D0) }, |
2450 | { REG_TABLE (REG_D1) }, | |
2451 | { REG_TABLE (REG_D2) }, | |
2452 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2453 | { X86_64_TABLE (X86_64_D4) }, |
2454 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2455 | { Bad_Opcode }, |
bf890a93 | 2456 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2457 | /* d8 */ |
2458 | { FLOAT }, | |
2459 | { FLOAT }, | |
2460 | { FLOAT }, | |
2461 | { FLOAT }, | |
2462 | { FLOAT }, | |
2463 | { FLOAT }, | |
2464 | { FLOAT }, | |
2465 | { FLOAT }, | |
2466 | /* e0 */ | |
bf890a93 IT |
2467 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2468 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2469 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2470 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2471 | { "inB", { AL, Ib }, 0 }, | |
2472 | { "inG", { zAX, Ib }, 0 }, | |
2473 | { "outB", { Ib, AL }, 0 }, | |
2474 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2475 | /* e8 */ |
a72d2af2 L |
2476 | { X86_64_TABLE (X86_64_E8) }, |
2477 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2478 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2479 | { "jmp", { Jb, BND }, 0 }, |
2480 | { "inB", { AL, indirDX }, 0 }, | |
2481 | { "inG", { zAX, indirDX }, 0 }, | |
2482 | { "outB", { indirDX, AL }, 0 }, | |
2483 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2484 | /* f0 */ |
592d1631 | 2485 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2486 | { "icebp", { XX }, 0 }, |
592d1631 L |
2487 | { Bad_Opcode }, /* repne */ |
2488 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2489 | { "hlt", { XX }, 0 }, |
2490 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2491 | { REG_TABLE (REG_F6) }, |
2492 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2493 | /* f8 */ |
bf890a93 IT |
2494 | { "clc", { XX }, 0 }, |
2495 | { "stc", { XX }, 0 }, | |
2496 | { "cli", { XX }, 0 }, | |
2497 | { "sti", { XX }, 0 }, | |
2498 | { "cld", { XX }, 0 }, | |
2499 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2500 | { REG_TABLE (REG_FE) }, |
2501 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2502 | }; |
2503 | ||
6439fc28 | 2504 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2505 | /* 00 */ |
1ceb70f8 L |
2506 | { REG_TABLE (REG_0F00 ) }, |
2507 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2508 | { "larS", { Gv, Ew }, 0 }, |
2509 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2510 | { Bad_Opcode }, |
bf890a93 IT |
2511 | { "syscall", { XX }, 0 }, |
2512 | { "clts", { XX }, 0 }, | |
589958d6 | 2513 | { "sysret%LQ", { XX }, 0 }, |
252b5132 | 2514 | /* 08 */ |
bf890a93 | 2515 | { "invd", { XX }, 0 }, |
3233d7d0 | 2516 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2517 | { Bad_Opcode }, |
bf890a93 | 2518 | { "ud2", { XX }, 0 }, |
592d1631 | 2519 | { Bad_Opcode }, |
b5b1fc4f | 2520 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2521 | { "femms", { XX }, 0 }, |
2522 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2523 | /* 10 */ |
1ceb70f8 L |
2524 | { PREFIX_TABLE (PREFIX_0F10) }, |
2525 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2526 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2527 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2528 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2529 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2530 | { PREFIX_TABLE (PREFIX_0F16) }, |
2531 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2532 | /* 18 */ |
1ceb70f8 | 2533 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2534 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2535 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2536 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2537 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2538 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2539 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2540 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2541 | /* 20 */ |
bf890a93 IT |
2542 | { "movZ", { Rm, Cm }, 0 }, |
2543 | { "movZ", { Rm, Dm }, 0 }, | |
2544 | { "movZ", { Cm, Rm }, 0 }, | |
2545 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2546 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2547 | { Bad_Opcode }, |
1ceb70f8 | 2548 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2549 | { Bad_Opcode }, |
252b5132 | 2550 | /* 28 */ |
507bd325 L |
2551 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2552 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2553 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2554 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2555 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2556 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2557 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2558 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2559 | /* 30 */ |
bf890a93 IT |
2560 | { "wrmsr", { XX }, 0 }, |
2561 | { "rdtsc", { XX }, 0 }, | |
2562 | { "rdmsr", { XX }, 0 }, | |
2563 | { "rdpmc", { XX }, 0 }, | |
d835a58b JB |
2564 | { "sysenter", { SEP }, 0 }, |
2565 | { "sysexit", { SEP }, 0 }, | |
592d1631 | 2566 | { Bad_Opcode }, |
bf890a93 | 2567 | { "getsec", { XX }, 0 }, |
252b5132 | 2568 | /* 38 */ |
507bd325 | 2569 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2570 | { Bad_Opcode }, |
507bd325 | 2571 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2572 | { Bad_Opcode }, |
2573 | { Bad_Opcode }, | |
2574 | { Bad_Opcode }, | |
2575 | { Bad_Opcode }, | |
2576 | { Bad_Opcode }, | |
252b5132 | 2577 | /* 40 */ |
bf890a93 IT |
2578 | { "cmovoS", { Gv, Ev }, 0 }, |
2579 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2580 | { "cmovbS", { Gv, Ev }, 0 }, | |
2581 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2582 | { "cmoveS", { Gv, Ev }, 0 }, | |
2583 | { "cmovneS", { Gv, Ev }, 0 }, | |
2584 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2585 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2586 | /* 48 */ |
bf890a93 IT |
2587 | { "cmovsS", { Gv, Ev }, 0 }, |
2588 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2589 | { "cmovpS", { Gv, Ev }, 0 }, | |
2590 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2591 | { "cmovlS", { Gv, Ev }, 0 }, | |
2592 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2593 | { "cmovleS", { Gv, Ev }, 0 }, | |
2594 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2595 | /* 50 */ |
a5aaedb9 | 2596 | { MOD_TABLE (MOD_0F50) }, |
1ceb70f8 L |
2597 | { PREFIX_TABLE (PREFIX_0F51) }, |
2598 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2599 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2600 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2601 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2602 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2603 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2604 | /* 58 */ |
1ceb70f8 L |
2605 | { PREFIX_TABLE (PREFIX_0F58) }, |
2606 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2607 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2608 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2609 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2610 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2611 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2612 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2613 | /* 60 */ |
1ceb70f8 L |
2614 | { PREFIX_TABLE (PREFIX_0F60) }, |
2615 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2616 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2617 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2618 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2619 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2620 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2621 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2622 | /* 68 */ |
507bd325 L |
2623 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2624 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2625 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2626 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2627 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2628 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2629 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2630 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2631 | /* 70 */ |
1ceb70f8 L |
2632 | { PREFIX_TABLE (PREFIX_0F70) }, |
2633 | { REG_TABLE (REG_0F71) }, | |
2634 | { REG_TABLE (REG_0F72) }, | |
2635 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2636 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2637 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2638 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2639 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2640 | /* 78 */ |
1ceb70f8 L |
2641 | { PREFIX_TABLE (PREFIX_0F78) }, |
2642 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2643 | { Bad_Opcode }, |
592d1631 | 2644 | { Bad_Opcode }, |
1ceb70f8 L |
2645 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2646 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2647 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2648 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2649 | /* 80 */ |
bf890a93 IT |
2650 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2651 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2652 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2653 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2654 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2655 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2656 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2657 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2658 | /* 88 */ |
bf890a93 IT |
2659 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2660 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2661 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2662 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2663 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2664 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2665 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2666 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2667 | /* 90 */ |
bf890a93 IT |
2668 | { "seto", { Eb }, 0 }, |
2669 | { "setno", { Eb }, 0 }, | |
2670 | { "setb", { Eb }, 0 }, | |
2671 | { "setae", { Eb }, 0 }, | |
2672 | { "sete", { Eb }, 0 }, | |
2673 | { "setne", { Eb }, 0 }, | |
2674 | { "setbe", { Eb }, 0 }, | |
2675 | { "seta", { Eb }, 0 }, | |
252b5132 | 2676 | /* 98 */ |
bf890a93 IT |
2677 | { "sets", { Eb }, 0 }, |
2678 | { "setns", { Eb }, 0 }, | |
2679 | { "setp", { Eb }, 0 }, | |
2680 | { "setnp", { Eb }, 0 }, | |
2681 | { "setl", { Eb }, 0 }, | |
2682 | { "setge", { Eb }, 0 }, | |
2683 | { "setle", { Eb }, 0 }, | |
2684 | { "setg", { Eb }, 0 }, | |
252b5132 | 2685 | /* a0 */ |
bf890a93 IT |
2686 | { "pushT", { fs }, 0 }, |
2687 | { "popT", { fs }, 0 }, | |
2688 | { "cpuid", { XX }, 0 }, | |
2689 | { "btS", { Ev, Gv }, 0 }, | |
2690 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2691 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2692 | { REG_TABLE (REG_0FA6) }, |
2693 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2694 | /* a8 */ |
bf890a93 IT |
2695 | { "pushT", { gs }, 0 }, |
2696 | { "popT", { gs }, 0 }, | |
2697 | { "rsm", { XX }, 0 }, | |
2698 | { "btsS", { Evh1, Gv }, 0 }, | |
2699 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
2700 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 2701 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 2702 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 2703 | /* b0 */ |
bf890a93 IT |
2704 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2705 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2706 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 2707 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
2708 | { MOD_TABLE (MOD_0FB4) }, |
2709 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
2710 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2711 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 2712 | /* b8 */ |
1ceb70f8 | 2713 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 2714 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 2715 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 2716 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 2717 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2718 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
2719 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2720 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 2721 | /* c0 */ |
bf890a93 IT |
2722 | { "xaddB", { Ebh1, Gb }, 0 }, |
2723 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2724 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 2725 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
2726 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2727 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
2728 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 2729 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2730 | /* c8 */ |
bf890a93 IT |
2731 | { "bswap", { RMeAX }, 0 }, |
2732 | { "bswap", { RMeCX }, 0 }, | |
2733 | { "bswap", { RMeDX }, 0 }, | |
2734 | { "bswap", { RMeBX }, 0 }, | |
2735 | { "bswap", { RMeSP }, 0 }, | |
2736 | { "bswap", { RMeBP }, 0 }, | |
2737 | { "bswap", { RMeSI }, 0 }, | |
2738 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 2739 | /* d0 */ |
1ceb70f8 | 2740 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
2741 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2742 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
2743 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
2744 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
2745 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2746 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2747 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2748 | /* d8 */ |
507bd325 L |
2749 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2750 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
2751 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
2752 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
2753 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
2754 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
2755 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
2756 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2757 | /* e0 */ |
507bd325 L |
2758 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2759 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
2760 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
2761 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
2762 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
2763 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2764 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2765 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2766 | /* e8 */ |
507bd325 L |
2767 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2768 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
2769 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
2770 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
2771 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
2772 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
2773 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
2774 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2775 | /* f0 */ |
1ceb70f8 | 2776 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
2777 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2778 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
2779 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
2780 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
2781 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
2782 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2783 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2784 | /* f8 */ |
507bd325 L |
2785 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2786 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
2787 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
2788 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
2789 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
2790 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
2791 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 2792 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
2793 | }; |
2794 | ||
2795 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2796 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2797 | /* ------------------------------- */ | |
2798 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2799 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2800 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2801 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2802 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2803 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2804 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2805 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2806 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2807 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2808 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2809 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2810 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2811 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2812 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2813 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2814 | /* ------------------------------- */ | |
2815 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2816 | }; |
2817 | ||
2818 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2819 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2820 | /* ------------------------------- */ | |
252b5132 | 2821 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2822 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2823 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2824 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2825 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2826 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2827 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2828 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2829 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2830 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2831 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 2832 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 2833 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2834 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2835 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 2836 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
2837 | /* ------------------------------- */ |
2838 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2839 | }; | |
2840 | ||
252b5132 RH |
2841 | static char obuf[100]; |
2842 | static char *obufp; | |
ea397f5b | 2843 | static char *mnemonicendp; |
252b5132 RH |
2844 | static char scratchbuf[100]; |
2845 | static unsigned char *start_codep; | |
2846 | static unsigned char *insn_codep; | |
2847 | static unsigned char *codep; | |
285ca992 | 2848 | static unsigned char *end_codep; |
f16cd0d5 L |
2849 | static int last_lock_prefix; |
2850 | static int last_repz_prefix; | |
2851 | static int last_repnz_prefix; | |
2852 | static int last_data_prefix; | |
2853 | static int last_addr_prefix; | |
2854 | static int last_rex_prefix; | |
2855 | static int last_seg_prefix; | |
d9949a36 | 2856 | static int fwait_prefix; |
285ca992 L |
2857 | /* The active segment register prefix. */ |
2858 | static int active_seg_prefix; | |
f16cd0d5 L |
2859 | #define MAX_CODE_LENGTH 15 |
2860 | /* We can up to 14 prefixes since the maximum instruction length is | |
2861 | 15bytes. */ | |
2862 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2863 | static disassemble_info *the_info; |
7967e09e L |
2864 | static struct |
2865 | { | |
2866 | int mod; | |
7967e09e | 2867 | int reg; |
484c222e | 2868 | int rm; |
7967e09e L |
2869 | } |
2870 | modrm; | |
4bba6815 | 2871 | static unsigned char need_modrm; |
dfc8cf43 L |
2872 | static struct |
2873 | { | |
2874 | int scale; | |
2875 | int index; | |
2876 | int base; | |
2877 | } | |
2878 | sib; | |
c0f3af97 L |
2879 | static struct |
2880 | { | |
2881 | int register_specifier; | |
2882 | int length; | |
2883 | int prefix; | |
2884 | int w; | |
43234a1e L |
2885 | int evex; |
2886 | int r; | |
2887 | int v; | |
2888 | int mask_register_specifier; | |
2889 | int zeroing; | |
2890 | int ll; | |
2891 | int b; | |
c0f3af97 L |
2892 | } |
2893 | vex; | |
2894 | static unsigned char need_vex; | |
2895 | static unsigned char need_vex_reg; | |
dae39acc | 2896 | static unsigned char vex_w_done; |
252b5132 | 2897 | |
ea397f5b L |
2898 | struct op |
2899 | { | |
2900 | const char *name; | |
2901 | unsigned int len; | |
2902 | }; | |
2903 | ||
4bba6815 AM |
2904 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
2905 | values are stale. Hitting this abort likely indicates that you | |
2906 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
2907 | #define MODRM_CHECK if (!need_modrm) abort () | |
2908 | ||
d708bcba AM |
2909 | static const char **names64; |
2910 | static const char **names32; | |
2911 | static const char **names16; | |
2912 | static const char **names8; | |
2913 | static const char **names8rex; | |
2914 | static const char **names_seg; | |
db51cc60 L |
2915 | static const char *index64; |
2916 | static const char *index32; | |
d708bcba | 2917 | static const char **index16; |
7e8b059b | 2918 | static const char **names_bnd; |
d708bcba AM |
2919 | |
2920 | static const char *intel_names64[] = { | |
2921 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
2922 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
2923 | }; | |
2924 | static const char *intel_names32[] = { | |
2925 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
2926 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
2927 | }; | |
2928 | static const char *intel_names16[] = { | |
2929 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
2930 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
2931 | }; | |
2932 | static const char *intel_names8[] = { | |
2933 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
2934 | }; | |
2935 | static const char *intel_names8rex[] = { | |
2936 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
2937 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
2938 | }; | |
2939 | static const char *intel_names_seg[] = { | |
2940 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
2941 | }; | |
db51cc60 L |
2942 | static const char *intel_index64 = "riz"; |
2943 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
2944 | static const char *intel_index16[] = { |
2945 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
2946 | }; | |
2947 | ||
2948 | static const char *att_names64[] = { | |
2949 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
2950 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
2951 | }; | |
d708bcba AM |
2952 | static const char *att_names32[] = { |
2953 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 2954 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 2955 | }; |
d708bcba AM |
2956 | static const char *att_names16[] = { |
2957 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 2958 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 2959 | }; |
d708bcba AM |
2960 | static const char *att_names8[] = { |
2961 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 2962 | }; |
d708bcba AM |
2963 | static const char *att_names8rex[] = { |
2964 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
2965 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
2966 | }; | |
d708bcba AM |
2967 | static const char *att_names_seg[] = { |
2968 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 2969 | }; |
db51cc60 L |
2970 | static const char *att_index64 = "%riz"; |
2971 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
2972 | static const char *att_index16[] = { |
2973 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
2974 | }; |
2975 | ||
b9733481 L |
2976 | static const char **names_mm; |
2977 | static const char *intel_names_mm[] = { | |
2978 | "mm0", "mm1", "mm2", "mm3", | |
2979 | "mm4", "mm5", "mm6", "mm7" | |
2980 | }; | |
2981 | static const char *att_names_mm[] = { | |
2982 | "%mm0", "%mm1", "%mm2", "%mm3", | |
2983 | "%mm4", "%mm5", "%mm6", "%mm7" | |
2984 | }; | |
2985 | ||
7e8b059b L |
2986 | static const char *intel_names_bnd[] = { |
2987 | "bnd0", "bnd1", "bnd2", "bnd3" | |
2988 | }; | |
2989 | ||
2990 | static const char *att_names_bnd[] = { | |
2991 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
2992 | }; | |
2993 | ||
b9733481 L |
2994 | static const char **names_xmm; |
2995 | static const char *intel_names_xmm[] = { | |
2996 | "xmm0", "xmm1", "xmm2", "xmm3", | |
2997 | "xmm4", "xmm5", "xmm6", "xmm7", | |
2998 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
2999 | "xmm12", "xmm13", "xmm14", "xmm15", |
3000 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3001 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3002 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3003 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3004 | }; |
3005 | static const char *att_names_xmm[] = { | |
3006 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3007 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3008 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3009 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3010 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3011 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3012 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3013 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3014 | }; |
3015 | ||
3016 | static const char **names_ymm; | |
3017 | static const char *intel_names_ymm[] = { | |
3018 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3019 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3020 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3021 | "ymm12", "ymm13", "ymm14", "ymm15", |
3022 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3023 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3024 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3025 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3026 | }; |
3027 | static const char *att_names_ymm[] = { | |
3028 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3029 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3030 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3031 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3032 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3033 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3034 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3035 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3036 | }; | |
3037 | ||
3038 | static const char **names_zmm; | |
3039 | static const char *intel_names_zmm[] = { | |
3040 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3041 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3042 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3043 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3044 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3045 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3046 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3047 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3048 | }; | |
3049 | static const char *att_names_zmm[] = { | |
3050 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3051 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3052 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3053 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3054 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3055 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3056 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3057 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3058 | }; | |
3059 | ||
3060 | static const char **names_mask; | |
3061 | static const char *intel_names_mask[] = { | |
3062 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3063 | }; | |
3064 | static const char *att_names_mask[] = { | |
3065 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3066 | }; | |
3067 | ||
3068 | static const char *names_rounding[] = | |
3069 | { | |
3070 | "{rn-sae}", | |
3071 | "{rd-sae}", | |
3072 | "{ru-sae}", | |
3073 | "{rz-sae}" | |
b9733481 L |
3074 | }; |
3075 | ||
1ceb70f8 L |
3076 | static const struct dis386 reg_table[][8] = { |
3077 | /* REG_80 */ | |
252b5132 | 3078 | { |
bf890a93 IT |
3079 | { "addA", { Ebh1, Ib }, 0 }, |
3080 | { "orA", { Ebh1, Ib }, 0 }, | |
3081 | { "adcA", { Ebh1, Ib }, 0 }, | |
3082 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3083 | { "andA", { Ebh1, Ib }, 0 }, | |
3084 | { "subA", { Ebh1, Ib }, 0 }, | |
3085 | { "xorA", { Ebh1, Ib }, 0 }, | |
3086 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3087 | }, |
1ceb70f8 | 3088 | /* REG_81 */ |
252b5132 | 3089 | { |
bf890a93 IT |
3090 | { "addQ", { Evh1, Iv }, 0 }, |
3091 | { "orQ", { Evh1, Iv }, 0 }, | |
3092 | { "adcQ", { Evh1, Iv }, 0 }, | |
3093 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3094 | { "andQ", { Evh1, Iv }, 0 }, | |
3095 | { "subQ", { Evh1, Iv }, 0 }, | |
3096 | { "xorQ", { Evh1, Iv }, 0 }, | |
3097 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3098 | }, |
7148c369 | 3099 | /* REG_83 */ |
252b5132 | 3100 | { |
bf890a93 IT |
3101 | { "addQ", { Evh1, sIb }, 0 }, |
3102 | { "orQ", { Evh1, sIb }, 0 }, | |
3103 | { "adcQ", { Evh1, sIb }, 0 }, | |
3104 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3105 | { "andQ", { Evh1, sIb }, 0 }, | |
3106 | { "subQ", { Evh1, sIb }, 0 }, | |
3107 | { "xorQ", { Evh1, sIb }, 0 }, | |
3108 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3109 | }, |
1ceb70f8 | 3110 | /* REG_8F */ |
4e7d34a6 | 3111 | { |
bf890a93 | 3112 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3113 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3114 | { Bad_Opcode }, |
3115 | { Bad_Opcode }, | |
3116 | { Bad_Opcode }, | |
f88c9eb0 | 3117 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3118 | }, |
1ceb70f8 | 3119 | /* REG_C0 */ |
252b5132 | 3120 | { |
bf890a93 IT |
3121 | { "rolA", { Eb, Ib }, 0 }, |
3122 | { "rorA", { Eb, Ib }, 0 }, | |
3123 | { "rclA", { Eb, Ib }, 0 }, | |
3124 | { "rcrA", { Eb, Ib }, 0 }, | |
3125 | { "shlA", { Eb, Ib }, 0 }, | |
3126 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 3127 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 3128 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3129 | }, |
1ceb70f8 | 3130 | /* REG_C1 */ |
252b5132 | 3131 | { |
bf890a93 IT |
3132 | { "rolQ", { Ev, Ib }, 0 }, |
3133 | { "rorQ", { Ev, Ib }, 0 }, | |
3134 | { "rclQ", { Ev, Ib }, 0 }, | |
3135 | { "rcrQ", { Ev, Ib }, 0 }, | |
3136 | { "shlQ", { Ev, Ib }, 0 }, | |
3137 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 3138 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 3139 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3140 | }, |
1ceb70f8 | 3141 | /* REG_C6 */ |
4e7d34a6 | 3142 | { |
bf890a93 | 3143 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3144 | { Bad_Opcode }, |
3145 | { Bad_Opcode }, | |
3146 | { Bad_Opcode }, | |
3147 | { Bad_Opcode }, | |
3148 | { Bad_Opcode }, | |
3149 | { Bad_Opcode }, | |
3150 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3151 | }, |
1ceb70f8 | 3152 | /* REG_C7 */ |
4e7d34a6 | 3153 | { |
bf890a93 | 3154 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3155 | { Bad_Opcode }, |
3156 | { Bad_Opcode }, | |
3157 | { Bad_Opcode }, | |
3158 | { Bad_Opcode }, | |
3159 | { Bad_Opcode }, | |
3160 | { Bad_Opcode }, | |
3161 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3162 | }, |
1ceb70f8 | 3163 | /* REG_D0 */ |
252b5132 | 3164 | { |
bf890a93 IT |
3165 | { "rolA", { Eb, I1 }, 0 }, |
3166 | { "rorA", { Eb, I1 }, 0 }, | |
3167 | { "rclA", { Eb, I1 }, 0 }, | |
3168 | { "rcrA", { Eb, I1 }, 0 }, | |
3169 | { "shlA", { Eb, I1 }, 0 }, | |
3170 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 3171 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 3172 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3173 | }, |
1ceb70f8 | 3174 | /* REG_D1 */ |
252b5132 | 3175 | { |
bf890a93 IT |
3176 | { "rolQ", { Ev, I1 }, 0 }, |
3177 | { "rorQ", { Ev, I1 }, 0 }, | |
3178 | { "rclQ", { Ev, I1 }, 0 }, | |
3179 | { "rcrQ", { Ev, I1 }, 0 }, | |
3180 | { "shlQ", { Ev, I1 }, 0 }, | |
3181 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 3182 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 3183 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3184 | }, |
1ceb70f8 | 3185 | /* REG_D2 */ |
252b5132 | 3186 | { |
bf890a93 IT |
3187 | { "rolA", { Eb, CL }, 0 }, |
3188 | { "rorA", { Eb, CL }, 0 }, | |
3189 | { "rclA", { Eb, CL }, 0 }, | |
3190 | { "rcrA", { Eb, CL }, 0 }, | |
3191 | { "shlA", { Eb, CL }, 0 }, | |
3192 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 3193 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 3194 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3195 | }, |
1ceb70f8 | 3196 | /* REG_D3 */ |
252b5132 | 3197 | { |
bf890a93 IT |
3198 | { "rolQ", { Ev, CL }, 0 }, |
3199 | { "rorQ", { Ev, CL }, 0 }, | |
3200 | { "rclQ", { Ev, CL }, 0 }, | |
3201 | { "rcrQ", { Ev, CL }, 0 }, | |
3202 | { "shlQ", { Ev, CL }, 0 }, | |
3203 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 3204 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 3205 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3206 | }, |
1ceb70f8 | 3207 | /* REG_F6 */ |
252b5132 | 3208 | { |
bf890a93 | 3209 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3210 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3211 | { "notA", { Ebh1 }, 0 }, |
3212 | { "negA", { Ebh1 }, 0 }, | |
3213 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3214 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3215 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3216 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3217 | }, |
1ceb70f8 | 3218 | /* REG_F7 */ |
252b5132 | 3219 | { |
bf890a93 | 3220 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3221 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3222 | { "notQ", { Evh1 }, 0 }, |
3223 | { "negQ", { Evh1 }, 0 }, | |
3224 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3225 | { "imulQ", { Ev }, 0 }, | |
3226 | { "divQ", { Ev }, 0 }, | |
3227 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3228 | }, |
1ceb70f8 | 3229 | /* REG_FE */ |
252b5132 | 3230 | { |
bf890a93 IT |
3231 | { "incA", { Ebh1 }, 0 }, |
3232 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3233 | }, |
1ceb70f8 | 3234 | /* REG_FF */ |
252b5132 | 3235 | { |
bf890a93 IT |
3236 | { "incQ", { Evh1 }, 0 }, |
3237 | { "decQ", { Evh1 }, 0 }, | |
9fef80d6 | 3238 | { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3239 | { MOD_TABLE (MOD_FF_REG_3) }, |
9fef80d6 | 3240 | { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3241 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3242 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3243 | { Bad_Opcode }, |
252b5132 | 3244 | }, |
1ceb70f8 | 3245 | /* REG_0F00 */ |
252b5132 | 3246 | { |
bf890a93 IT |
3247 | { "sldtD", { Sv }, 0 }, |
3248 | { "strD", { Sv }, 0 }, | |
3249 | { "lldt", { Ew }, 0 }, | |
3250 | { "ltr", { Ew }, 0 }, | |
3251 | { "verr", { Ew }, 0 }, | |
3252 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3253 | { Bad_Opcode }, |
3254 | { Bad_Opcode }, | |
252b5132 | 3255 | }, |
1ceb70f8 | 3256 | /* REG_0F01 */ |
252b5132 | 3257 | { |
1ceb70f8 L |
3258 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3259 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3260 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3261 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3262 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3263 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3264 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3265 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3266 | }, |
b5b1fc4f | 3267 | /* REG_0F0D */ |
252b5132 | 3268 | { |
bf890a93 IT |
3269 | { "prefetch", { Mb }, 0 }, |
3270 | { "prefetchw", { Mb }, 0 }, | |
3271 | { "prefetchwt1", { Mb }, 0 }, | |
3272 | { "prefetch", { Mb }, 0 }, | |
3273 | { "prefetch", { Mb }, 0 }, | |
3274 | { "prefetch", { Mb }, 0 }, | |
3275 | { "prefetch", { Mb }, 0 }, | |
3276 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3277 | }, |
1ceb70f8 | 3278 | /* REG_0F18 */ |
252b5132 | 3279 | { |
1ceb70f8 L |
3280 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3281 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3282 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3283 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3284 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3285 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3286 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3287 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3288 | }, |
f8687e93 | 3289 | /* REG_0F1C_P_0_MOD_0 */ |
c48935d7 IT |
3290 | { |
3291 | { "cldemote", { Mb }, 0 }, | |
3292 | { "nopQ", { Ev }, 0 }, | |
3293 | { "nopQ", { Ev }, 0 }, | |
3294 | { "nopQ", { Ev }, 0 }, | |
3295 | { "nopQ", { Ev }, 0 }, | |
3296 | { "nopQ", { Ev }, 0 }, | |
3297 | { "nopQ", { Ev }, 0 }, | |
3298 | { "nopQ", { Ev }, 0 }, | |
3299 | }, | |
f8687e93 | 3300 | /* REG_0F1E_P_1_MOD_3 */ |
603555e5 L |
3301 | { |
3302 | { "nopQ", { Ev }, 0 }, | |
3303 | { "rdsspK", { Rdq }, PREFIX_OPCODE }, | |
3304 | { "nopQ", { Ev }, 0 }, | |
3305 | { "nopQ", { Ev }, 0 }, | |
3306 | { "nopQ", { Ev }, 0 }, | |
3307 | { "nopQ", { Ev }, 0 }, | |
3308 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 3309 | { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, |
603555e5 | 3310 | }, |
1ceb70f8 | 3311 | /* REG_0F71 */ |
a6bd098c | 3312 | { |
592d1631 L |
3313 | { Bad_Opcode }, |
3314 | { Bad_Opcode }, | |
1ceb70f8 | 3315 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3316 | { Bad_Opcode }, |
1ceb70f8 | 3317 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3318 | { Bad_Opcode }, |
1ceb70f8 | 3319 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3320 | }, |
1ceb70f8 | 3321 | /* REG_0F72 */ |
a6bd098c | 3322 | { |
592d1631 L |
3323 | { Bad_Opcode }, |
3324 | { Bad_Opcode }, | |
1ceb70f8 | 3325 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3326 | { Bad_Opcode }, |
1ceb70f8 | 3327 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3328 | { Bad_Opcode }, |
1ceb70f8 | 3329 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3330 | }, |
1ceb70f8 | 3331 | /* REG_0F73 */ |
252b5132 | 3332 | { |
592d1631 L |
3333 | { Bad_Opcode }, |
3334 | { Bad_Opcode }, | |
1ceb70f8 L |
3335 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3336 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3337 | { Bad_Opcode }, |
3338 | { Bad_Opcode }, | |
1ceb70f8 L |
3339 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3340 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3341 | }, |
1ceb70f8 | 3342 | /* REG_0FA6 */ |
252b5132 | 3343 | { |
bf890a93 IT |
3344 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3345 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3346 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3347 | }, |
1ceb70f8 | 3348 | /* REG_0FA7 */ |
4e7d34a6 | 3349 | { |
bf890a93 IT |
3350 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3351 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3352 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3353 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3354 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3355 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3356 | }, |
1ceb70f8 | 3357 | /* REG_0FAE */ |
4e7d34a6 | 3358 | { |
1ceb70f8 L |
3359 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3360 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3361 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3362 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3363 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3364 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3365 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3366 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3367 | }, |
1ceb70f8 | 3368 | /* REG_0FBA */ |
252b5132 | 3369 | { |
592d1631 L |
3370 | { Bad_Opcode }, |
3371 | { Bad_Opcode }, | |
3372 | { Bad_Opcode }, | |
3373 | { Bad_Opcode }, | |
bf890a93 IT |
3374 | { "btQ", { Ev, Ib }, 0 }, |
3375 | { "btsQ", { Evh1, Ib }, 0 }, | |
3376 | { "btrQ", { Evh1, Ib }, 0 }, | |
3377 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3378 | }, |
1ceb70f8 | 3379 | /* REG_0FC7 */ |
c608c12e | 3380 | { |
592d1631 | 3381 | { Bad_Opcode }, |
bf890a93 | 3382 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3383 | { Bad_Opcode }, |
963f3586 IT |
3384 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3385 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3386 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3387 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3388 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3389 | }, |
592a252b | 3390 | /* REG_VEX_0F71 */ |
c0f3af97 | 3391 | { |
592d1631 L |
3392 | { Bad_Opcode }, |
3393 | { Bad_Opcode }, | |
592a252b | 3394 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3395 | { Bad_Opcode }, |
592a252b | 3396 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3397 | { Bad_Opcode }, |
592a252b | 3398 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3399 | }, |
592a252b | 3400 | /* REG_VEX_0F72 */ |
c0f3af97 | 3401 | { |
592d1631 L |
3402 | { Bad_Opcode }, |
3403 | { Bad_Opcode }, | |
592a252b | 3404 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3405 | { Bad_Opcode }, |
592a252b | 3406 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3407 | { Bad_Opcode }, |
592a252b | 3408 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3409 | }, |
592a252b | 3410 | /* REG_VEX_0F73 */ |
c0f3af97 | 3411 | { |
592d1631 L |
3412 | { Bad_Opcode }, |
3413 | { Bad_Opcode }, | |
592a252b L |
3414 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3415 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3416 | { Bad_Opcode }, |
3417 | { Bad_Opcode }, | |
592a252b L |
3418 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3419 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3420 | }, |
592a252b | 3421 | /* REG_VEX_0FAE */ |
c0f3af97 | 3422 | { |
592d1631 L |
3423 | { Bad_Opcode }, |
3424 | { Bad_Opcode }, | |
592a252b L |
3425 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3426 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3427 | }, |
f12dc422 L |
3428 | /* REG_VEX_0F38F3 */ |
3429 | { | |
3430 | { Bad_Opcode }, | |
3431 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3432 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3433 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3434 | }, | |
f88c9eb0 SP |
3435 | /* REG_XOP_LWPCB */ |
3436 | { | |
bf890a93 IT |
3437 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3438 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3439 | }, |
3440 | /* REG_XOP_LWP */ | |
3441 | { | |
c1dc7af5 JB |
3442 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, |
3443 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, | |
f88c9eb0 | 3444 | }, |
2a2a0f38 QN |
3445 | /* REG_XOP_TBM_01 */ |
3446 | { | |
3447 | { Bad_Opcode }, | |
c1dc7af5 JB |
3448 | { "blcfill", { { OP_LWP_E, 0 }, Edq }, 0 }, |
3449 | { "blsfill", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3450 | { "blcs", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3451 | { "tzmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3452 | { "blcic", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3453 | { "blsic", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3454 | { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
2a2a0f38 QN |
3455 | }, |
3456 | /* REG_XOP_TBM_02 */ | |
3457 | { | |
3458 | { Bad_Opcode }, | |
c1dc7af5 | 3459 | { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, |
2a2a0f38 QN |
3460 | { Bad_Opcode }, |
3461 | { Bad_Opcode }, | |
3462 | { Bad_Opcode }, | |
3463 | { Bad_Opcode }, | |
c1dc7af5 | 3464 | { "blci", { { OP_LWP_E, 0 }, Edq }, 0 }, |
2a2a0f38 | 3465 | }, |
ad692897 L |
3466 | |
3467 | #include "i386-dis-evex-reg.h" | |
4e7d34a6 L |
3468 | }; |
3469 | ||
1ceb70f8 L |
3470 | static const struct dis386 prefix_table[][4] = { |
3471 | /* PREFIX_90 */ | |
252b5132 | 3472 | { |
bf890a93 IT |
3473 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3474 | { "pause", { XX }, 0 }, | |
3475 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3476 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3477 | }, |
4e7d34a6 | 3478 | |
f9630fa6 | 3479 | /* PREFIX_0F01_REG_3_RM_1 */ |
a847e322 JB |
3480 | { |
3481 | { "vmmcall", { Skip_MODRM }, 0 }, | |
3482 | { "vmgexit", { Skip_MODRM }, 0 }, | |
d27c357a JB |
3483 | { Bad_Opcode }, |
3484 | { "vmgexit", { Skip_MODRM }, 0 }, | |
a847e322 JB |
3485 | }, |
3486 | ||
f8687e93 | 3487 | /* PREFIX_0F01_REG_5_MOD_0 */ |
603555e5 L |
3488 | { |
3489 | { Bad_Opcode }, | |
3490 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3491 | }, | |
3492 | ||
f8687e93 | 3493 | /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ |
603555e5 | 3494 | { |
4b27d27c | 3495 | { "serialize", { Skip_MODRM }, PREFIX_OPCODE }, |
2234eee6 | 3496 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b | 3497 | { Bad_Opcode }, |
efe30057 | 3498 | { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b CL |
3499 | }, |
3500 | ||
3501 | /* PREFIX_0F01_REG_5_MOD_3_RM_1 */ | |
3502 | { | |
3503 | { Bad_Opcode }, | |
3504 | { Bad_Opcode }, | |
3505 | { Bad_Opcode }, | |
3506 | { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE }, | |
603555e5 L |
3507 | }, |
3508 | ||
f8687e93 | 3509 | /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ |
603555e5 L |
3510 | { |
3511 | { Bad_Opcode }, | |
c2f76402 | 3512 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3513 | }, |
3514 | ||
267b8516 JB |
3515 | /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ |
3516 | { | |
3517 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, | |
142861df | 3518 | { "mcommit", { Skip_MODRM }, 0 }, |
267b8516 JB |
3519 | }, |
3520 | ||
3521 | /* PREFIX_0F01_REG_7_MOD_3_RM_3 */ | |
3522 | { | |
7abb8d81 | 3523 | { "mwaitx", { { OP_Mwait, eBX_reg } }, 0 }, |
267b8516 JB |
3524 | }, |
3525 | ||
3233d7d0 IT |
3526 | /* PREFIX_0F09 */ |
3527 | { | |
3528 | { "wbinvd", { XX }, 0 }, | |
3529 | { "wbnoinvd", { XX }, 0 }, | |
3530 | }, | |
3531 | ||
1ceb70f8 | 3532 | /* PREFIX_0F10 */ |
cc0ec051 | 3533 | { |
507bd325 L |
3534 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3535 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3536 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3537 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3538 | }, |
4e7d34a6 | 3539 | |
1ceb70f8 | 3540 | /* PREFIX_0F11 */ |
30d1c836 | 3541 | { |
507bd325 L |
3542 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3543 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3544 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3545 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3546 | }, |
252b5132 | 3547 | |
1ceb70f8 | 3548 | /* PREFIX_0F12 */ |
c608c12e | 3549 | { |
1ceb70f8 | 3550 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 | 3551 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3552 | { MOD_TABLE (MOD_0F12_PREFIX_2) }, |
507bd325 | 3553 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, |
c608c12e | 3554 | }, |
4e7d34a6 | 3555 | |
1ceb70f8 | 3556 | /* PREFIX_0F16 */ |
c608c12e | 3557 | { |
1ceb70f8 | 3558 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 | 3559 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3560 | { MOD_TABLE (MOD_0F16_PREFIX_2) }, |
c608c12e | 3561 | }, |
4e7d34a6 | 3562 | |
7e8b059b L |
3563 | /* PREFIX_0F1A */ |
3564 | { | |
3565 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3566 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3567 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3568 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3569 | }, |
3570 | ||
3571 | /* PREFIX_0F1B */ | |
3572 | { | |
3573 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3574 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3575 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3576 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3577 | }, |
3578 | ||
c48935d7 IT |
3579 | /* PREFIX_0F1C */ |
3580 | { | |
3581 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
3582 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3583 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3584 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3585 | }, | |
3586 | ||
603555e5 L |
3587 | /* PREFIX_0F1E */ |
3588 | { | |
3589 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3590 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3591 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3592 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3593 | }, | |
3594 | ||
1ceb70f8 | 3595 | /* PREFIX_0F2A */ |
c608c12e | 3596 | { |
507bd325 | 3597 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
e1a1babd | 3598 | { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE }, |
507bd325 | 3599 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, |
e1a1babd | 3600 | { "cvtsi2sd%LQ", { XM, Edq }, 0 }, |
c608c12e | 3601 | }, |
4e7d34a6 | 3602 | |
1ceb70f8 | 3603 | /* PREFIX_0F2B */ |
c608c12e | 3604 | { |
75c135a8 L |
3605 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3606 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3607 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3608 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3609 | }, |
4e7d34a6 | 3610 | |
1ceb70f8 | 3611 | /* PREFIX_0F2C */ |
c608c12e | 3612 | { |
507bd325 | 3613 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3614 | { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3615 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3616 | { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3617 | }, |
4e7d34a6 | 3618 | |
1ceb70f8 | 3619 | /* PREFIX_0F2D */ |
c608c12e | 3620 | { |
507bd325 | 3621 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3622 | { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3623 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3624 | { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3625 | }, |
4e7d34a6 | 3626 | |
1ceb70f8 | 3627 | /* PREFIX_0F2E */ |
c608c12e | 3628 | { |
bf890a93 | 3629 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3630 | { Bad_Opcode }, |
bf890a93 | 3631 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3632 | }, |
4e7d34a6 | 3633 | |
1ceb70f8 | 3634 | /* PREFIX_0F2F */ |
c608c12e | 3635 | { |
bf890a93 | 3636 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3637 | { Bad_Opcode }, |
bf890a93 | 3638 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3639 | }, |
4e7d34a6 | 3640 | |
1ceb70f8 | 3641 | /* PREFIX_0F51 */ |
c608c12e | 3642 | { |
507bd325 L |
3643 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3644 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3645 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3646 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3647 | }, |
4e7d34a6 | 3648 | |
1ceb70f8 | 3649 | /* PREFIX_0F52 */ |
c608c12e | 3650 | { |
507bd325 L |
3651 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3652 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3653 | }, |
4e7d34a6 | 3654 | |
1ceb70f8 | 3655 | /* PREFIX_0F53 */ |
c608c12e | 3656 | { |
507bd325 L |
3657 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3658 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3659 | }, |
4e7d34a6 | 3660 | |
1ceb70f8 | 3661 | /* PREFIX_0F58 */ |
c608c12e | 3662 | { |
507bd325 L |
3663 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3664 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3665 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3666 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3667 | }, |
4e7d34a6 | 3668 | |
1ceb70f8 | 3669 | /* PREFIX_0F59 */ |
c608c12e | 3670 | { |
507bd325 L |
3671 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3672 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3673 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3674 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3675 | }, |
4e7d34a6 | 3676 | |
1ceb70f8 | 3677 | /* PREFIX_0F5A */ |
041bd2e0 | 3678 | { |
507bd325 L |
3679 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3680 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3681 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3682 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3683 | }, |
4e7d34a6 | 3684 | |
1ceb70f8 | 3685 | /* PREFIX_0F5B */ |
041bd2e0 | 3686 | { |
507bd325 L |
3687 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3688 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3689 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3690 | }, |
4e7d34a6 | 3691 | |
1ceb70f8 | 3692 | /* PREFIX_0F5C */ |
041bd2e0 | 3693 | { |
507bd325 L |
3694 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3695 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3696 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3697 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3698 | }, |
4e7d34a6 | 3699 | |
1ceb70f8 | 3700 | /* PREFIX_0F5D */ |
041bd2e0 | 3701 | { |
507bd325 L |
3702 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3703 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3704 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3705 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3706 | }, |
4e7d34a6 | 3707 | |
1ceb70f8 | 3708 | /* PREFIX_0F5E */ |
041bd2e0 | 3709 | { |
507bd325 L |
3710 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3711 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3712 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3713 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3714 | }, |
4e7d34a6 | 3715 | |
1ceb70f8 | 3716 | /* PREFIX_0F5F */ |
041bd2e0 | 3717 | { |
507bd325 L |
3718 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3719 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3720 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3721 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3722 | }, |
4e7d34a6 | 3723 | |
1ceb70f8 | 3724 | /* PREFIX_0F60 */ |
041bd2e0 | 3725 | { |
507bd325 | 3726 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3727 | { Bad_Opcode }, |
507bd325 | 3728 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3729 | }, |
4e7d34a6 | 3730 | |
1ceb70f8 | 3731 | /* PREFIX_0F61 */ |
041bd2e0 | 3732 | { |
507bd325 | 3733 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3734 | { Bad_Opcode }, |
507bd325 | 3735 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3736 | }, |
4e7d34a6 | 3737 | |
1ceb70f8 | 3738 | /* PREFIX_0F62 */ |
041bd2e0 | 3739 | { |
507bd325 | 3740 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3741 | { Bad_Opcode }, |
507bd325 | 3742 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3743 | }, |
4e7d34a6 | 3744 | |
1ceb70f8 | 3745 | /* PREFIX_0F6C */ |
041bd2e0 | 3746 | { |
592d1631 L |
3747 | { Bad_Opcode }, |
3748 | { Bad_Opcode }, | |
507bd325 | 3749 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 3750 | }, |
4e7d34a6 | 3751 | |
1ceb70f8 | 3752 | /* PREFIX_0F6D */ |
0f17484f | 3753 | { |
592d1631 L |
3754 | { Bad_Opcode }, |
3755 | { Bad_Opcode }, | |
507bd325 | 3756 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 3757 | }, |
4e7d34a6 | 3758 | |
1ceb70f8 | 3759 | /* PREFIX_0F6F */ |
ca164297 | 3760 | { |
507bd325 L |
3761 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3762 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3763 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3764 | }, |
4e7d34a6 | 3765 | |
1ceb70f8 | 3766 | /* PREFIX_0F70 */ |
4e7d34a6 | 3767 | { |
507bd325 L |
3768 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3769 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3770 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3771 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3772 | }, |
3773 | ||
92fddf8e L |
3774 | /* PREFIX_0F73_REG_3 */ |
3775 | { | |
592d1631 L |
3776 | { Bad_Opcode }, |
3777 | { Bad_Opcode }, | |
bf890a93 | 3778 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
3779 | }, |
3780 | ||
3781 | /* PREFIX_0F73_REG_7 */ | |
3782 | { | |
592d1631 L |
3783 | { Bad_Opcode }, |
3784 | { Bad_Opcode }, | |
bf890a93 | 3785 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
3786 | }, |
3787 | ||
1ceb70f8 | 3788 | /* PREFIX_0F78 */ |
4e7d34a6 | 3789 | { |
bf890a93 | 3790 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 3791 | { Bad_Opcode }, |
bf890a93 IT |
3792 | {"extrq", { XS, Ib, Ib }, 0 }, |
3793 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
3794 | }, |
3795 | ||
1ceb70f8 | 3796 | /* PREFIX_0F79 */ |
4e7d34a6 | 3797 | { |
bf890a93 | 3798 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 3799 | { Bad_Opcode }, |
bf890a93 IT |
3800 | {"extrq", { XM, XS }, 0 }, |
3801 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
3802 | }, |
3803 | ||
1ceb70f8 | 3804 | /* PREFIX_0F7C */ |
ca164297 | 3805 | { |
592d1631 L |
3806 | { Bad_Opcode }, |
3807 | { Bad_Opcode }, | |
507bd325 L |
3808 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3809 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3810 | }, |
4e7d34a6 | 3811 | |
1ceb70f8 | 3812 | /* PREFIX_0F7D */ |
ca164297 | 3813 | { |
592d1631 L |
3814 | { Bad_Opcode }, |
3815 | { Bad_Opcode }, | |
507bd325 L |
3816 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3817 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3818 | }, |
4e7d34a6 | 3819 | |
1ceb70f8 | 3820 | /* PREFIX_0F7E */ |
ca164297 | 3821 | { |
507bd325 L |
3822 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3823 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
3824 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 3825 | }, |
4e7d34a6 | 3826 | |
1ceb70f8 | 3827 | /* PREFIX_0F7F */ |
ca164297 | 3828 | { |
507bd325 L |
3829 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3830 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
3831 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 3832 | }, |
4e7d34a6 | 3833 | |
f8687e93 | 3834 | /* PREFIX_0FAE_REG_0_MOD_3 */ |
c7b8aa3a L |
3835 | { |
3836 | { Bad_Opcode }, | |
bf890a93 | 3837 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3838 | }, |
3839 | ||
f8687e93 | 3840 | /* PREFIX_0FAE_REG_1_MOD_3 */ |
c7b8aa3a L |
3841 | { |
3842 | { Bad_Opcode }, | |
bf890a93 | 3843 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3844 | }, |
3845 | ||
f8687e93 | 3846 | /* PREFIX_0FAE_REG_2_MOD_3 */ |
c7b8aa3a L |
3847 | { |
3848 | { Bad_Opcode }, | |
bf890a93 | 3849 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3850 | }, |
3851 | ||
f8687e93 | 3852 | /* PREFIX_0FAE_REG_3_MOD_3 */ |
c7b8aa3a L |
3853 | { |
3854 | { Bad_Opcode }, | |
bf890a93 | 3855 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3856 | }, |
3857 | ||
f8687e93 | 3858 | /* PREFIX_0FAE_REG_4_MOD_0 */ |
6b40c462 L |
3859 | { |
3860 | { "xsave", { FXSAVE }, 0 }, | |
3861 | { "ptwrite%LQ", { Edq }, 0 }, | |
3862 | }, | |
3863 | ||
f8687e93 | 3864 | /* PREFIX_0FAE_REG_4_MOD_3 */ |
6b40c462 L |
3865 | { |
3866 | { Bad_Opcode }, | |
3867 | { "ptwrite%LQ", { Edq }, 0 }, | |
3868 | }, | |
3869 | ||
f8687e93 | 3870 | /* PREFIX_0FAE_REG_5_MOD_0 */ |
603555e5 L |
3871 | { |
3872 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, | |
2234eee6 L |
3873 | }, |
3874 | ||
f8687e93 | 3875 | /* PREFIX_0FAE_REG_5_MOD_3 */ |
2234eee6 L |
3876 | { |
3877 | { "lfence", { Skip_MODRM }, 0 }, | |
3878 | { "incsspK", { Rdq }, PREFIX_OPCODE }, | |
603555e5 L |
3879 | }, |
3880 | ||
f8687e93 | 3881 | /* PREFIX_0FAE_REG_6_MOD_0 */ |
c5e7287a | 3882 | { |
603555e5 L |
3883 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
3884 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
3885 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
3886 | }, |
3887 | ||
f8687e93 | 3888 | /* PREFIX_0FAE_REG_6_MOD_3 */ |
de89d0a3 | 3889 | { |
f8687e93 | 3890 | { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, |
de89d0a3 | 3891 | { "umonitor", { Eva }, PREFIX_OPCODE }, |
ae1d3843 L |
3892 | { "tpause", { Edq }, PREFIX_OPCODE }, |
3893 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
3894 | }, |
3895 | ||
f8687e93 | 3896 | /* PREFIX_0FAE_REG_7_MOD_0 */ |
963f3586 | 3897 | { |
bf890a93 | 3898 | { "clflush", { Mb }, 0 }, |
963f3586 | 3899 | { Bad_Opcode }, |
bf890a93 | 3900 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
3901 | }, |
3902 | ||
1ceb70f8 | 3903 | /* PREFIX_0FB8 */ |
ca164297 | 3904 | { |
592d1631 | 3905 | { Bad_Opcode }, |
bf890a93 | 3906 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 3907 | }, |
4e7d34a6 | 3908 | |
f12dc422 L |
3909 | /* PREFIX_0FBC */ |
3910 | { | |
bf890a93 IT |
3911 | { "bsfS", { Gv, Ev }, 0 }, |
3912 | { "tzcntS", { Gv, Ev }, 0 }, | |
3913 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
3914 | }, |
3915 | ||
1ceb70f8 | 3916 | /* PREFIX_0FBD */ |
050dfa73 | 3917 | { |
bf890a93 IT |
3918 | { "bsrS", { Gv, Ev }, 0 }, |
3919 | { "lzcntS", { Gv, Ev }, 0 }, | |
3920 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
3921 | }, |
3922 | ||
1ceb70f8 | 3923 | /* PREFIX_0FC2 */ |
050dfa73 | 3924 | { |
507bd325 L |
3925 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
3926 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
3927 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
3928 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 3929 | }, |
246c51aa | 3930 | |
f8687e93 | 3931 | /* PREFIX_0FC3_MOD_0 */ |
4ee52178 | 3932 | { |
e1a1babd | 3933 | { "movntiS", { Edq, Gdq }, PREFIX_OPCODE }, |
4ee52178 L |
3934 | }, |
3935 | ||
f8687e93 | 3936 | /* PREFIX_0FC7_REG_6_MOD_0 */ |
92fddf8e | 3937 | { |
bf890a93 IT |
3938 | { "vmptrld",{ Mq }, 0 }, |
3939 | { "vmxon", { Mq }, 0 }, | |
3940 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
3941 | }, |
3942 | ||
f8687e93 | 3943 | /* PREFIX_0FC7_REG_6_MOD_3 */ |
f24bcbaa L |
3944 | { |
3945 | { "rdrand", { Ev }, 0 }, | |
3946 | { Bad_Opcode }, | |
3947 | { "rdrand", { Ev }, 0 } | |
3948 | }, | |
3949 | ||
f8687e93 | 3950 | /* PREFIX_0FC7_REG_7_MOD_3 */ |
f24bcbaa L |
3951 | { |
3952 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 3953 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
3954 | { "rdseed", { Ev }, 0 }, |
3955 | }, | |
3956 | ||
1ceb70f8 | 3957 | /* PREFIX_0FD0 */ |
050dfa73 | 3958 | { |
592d1631 L |
3959 | { Bad_Opcode }, |
3960 | { Bad_Opcode }, | |
bf890a93 IT |
3961 | { "addsubpd", { XM, EXx }, 0 }, |
3962 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 3963 | }, |
050dfa73 | 3964 | |
1ceb70f8 | 3965 | /* PREFIX_0FD6 */ |
050dfa73 | 3966 | { |
592d1631 | 3967 | { Bad_Opcode }, |
bf890a93 IT |
3968 | { "movq2dq",{ XM, MS }, 0 }, |
3969 | { "movq", { EXqS, XM }, 0 }, | |
3970 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
3971 | }, |
3972 | ||
1ceb70f8 | 3973 | /* PREFIX_0FE6 */ |
7918206c | 3974 | { |
592d1631 | 3975 | { Bad_Opcode }, |
507bd325 L |
3976 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
3977 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3978 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 3979 | }, |
8b38ad71 | 3980 | |
1ceb70f8 | 3981 | /* PREFIX_0FE7 */ |
8b38ad71 | 3982 | { |
507bd325 | 3983 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 3984 | { Bad_Opcode }, |
75c135a8 | 3985 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
3986 | }, |
3987 | ||
1ceb70f8 | 3988 | /* PREFIX_0FF0 */ |
4e7d34a6 | 3989 | { |
592d1631 L |
3990 | { Bad_Opcode }, |
3991 | { Bad_Opcode }, | |
3992 | { Bad_Opcode }, | |
1ceb70f8 | 3993 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
3994 | }, |
3995 | ||
1ceb70f8 | 3996 | /* PREFIX_0FF7 */ |
4e7d34a6 | 3997 | { |
507bd325 | 3998 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 3999 | { Bad_Opcode }, |
507bd325 | 4000 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4001 | }, |
42903f7f | 4002 | |
1ceb70f8 | 4003 | /* PREFIX_0F3810 */ |
42903f7f | 4004 | { |
592d1631 L |
4005 | { Bad_Opcode }, |
4006 | { Bad_Opcode }, | |
507bd325 | 4007 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4008 | }, |
4009 | ||
1ceb70f8 | 4010 | /* PREFIX_0F3814 */ |
42903f7f | 4011 | { |
592d1631 L |
4012 | { Bad_Opcode }, |
4013 | { Bad_Opcode }, | |
507bd325 | 4014 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4015 | }, |
4016 | ||
1ceb70f8 | 4017 | /* PREFIX_0F3815 */ |
42903f7f | 4018 | { |
592d1631 L |
4019 | { Bad_Opcode }, |
4020 | { Bad_Opcode }, | |
507bd325 | 4021 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4022 | }, |
4023 | ||
1ceb70f8 | 4024 | /* PREFIX_0F3817 */ |
42903f7f | 4025 | { |
592d1631 L |
4026 | { Bad_Opcode }, |
4027 | { Bad_Opcode }, | |
507bd325 | 4028 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4029 | }, |
4030 | ||
1ceb70f8 | 4031 | /* PREFIX_0F3820 */ |
42903f7f | 4032 | { |
592d1631 L |
4033 | { Bad_Opcode }, |
4034 | { Bad_Opcode }, | |
507bd325 | 4035 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4036 | }, |
4037 | ||
1ceb70f8 | 4038 | /* PREFIX_0F3821 */ |
42903f7f | 4039 | { |
592d1631 L |
4040 | { Bad_Opcode }, |
4041 | { Bad_Opcode }, | |
507bd325 | 4042 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4043 | }, |
4044 | ||
1ceb70f8 | 4045 | /* PREFIX_0F3822 */ |
42903f7f | 4046 | { |
592d1631 L |
4047 | { Bad_Opcode }, |
4048 | { Bad_Opcode }, | |
507bd325 | 4049 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4050 | }, |
4051 | ||
1ceb70f8 | 4052 | /* PREFIX_0F3823 */ |
42903f7f | 4053 | { |
592d1631 L |
4054 | { Bad_Opcode }, |
4055 | { Bad_Opcode }, | |
507bd325 | 4056 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4057 | }, |
4058 | ||
1ceb70f8 | 4059 | /* PREFIX_0F3824 */ |
42903f7f | 4060 | { |
592d1631 L |
4061 | { Bad_Opcode }, |
4062 | { Bad_Opcode }, | |
507bd325 | 4063 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4064 | }, |
4065 | ||
1ceb70f8 | 4066 | /* PREFIX_0F3825 */ |
42903f7f | 4067 | { |
592d1631 L |
4068 | { Bad_Opcode }, |
4069 | { Bad_Opcode }, | |
507bd325 | 4070 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4071 | }, |
4072 | ||
1ceb70f8 | 4073 | /* PREFIX_0F3828 */ |
42903f7f | 4074 | { |
592d1631 L |
4075 | { Bad_Opcode }, |
4076 | { Bad_Opcode }, | |
507bd325 | 4077 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4078 | }, |
4079 | ||
1ceb70f8 | 4080 | /* PREFIX_0F3829 */ |
42903f7f | 4081 | { |
592d1631 L |
4082 | { Bad_Opcode }, |
4083 | { Bad_Opcode }, | |
507bd325 | 4084 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4085 | }, |
4086 | ||
1ceb70f8 | 4087 | /* PREFIX_0F382A */ |
42903f7f | 4088 | { |
592d1631 L |
4089 | { Bad_Opcode }, |
4090 | { Bad_Opcode }, | |
75c135a8 | 4091 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4092 | }, |
4093 | ||
1ceb70f8 | 4094 | /* PREFIX_0F382B */ |
42903f7f | 4095 | { |
592d1631 L |
4096 | { Bad_Opcode }, |
4097 | { Bad_Opcode }, | |
507bd325 | 4098 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4099 | }, |
4100 | ||
1ceb70f8 | 4101 | /* PREFIX_0F3830 */ |
42903f7f | 4102 | { |
592d1631 L |
4103 | { Bad_Opcode }, |
4104 | { Bad_Opcode }, | |
507bd325 | 4105 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4106 | }, |
4107 | ||
1ceb70f8 | 4108 | /* PREFIX_0F3831 */ |
42903f7f | 4109 | { |
592d1631 L |
4110 | { Bad_Opcode }, |
4111 | { Bad_Opcode }, | |
507bd325 | 4112 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4113 | }, |
4114 | ||
1ceb70f8 | 4115 | /* PREFIX_0F3832 */ |
42903f7f | 4116 | { |
592d1631 L |
4117 | { Bad_Opcode }, |
4118 | { Bad_Opcode }, | |
507bd325 | 4119 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4120 | }, |
4121 | ||
1ceb70f8 | 4122 | /* PREFIX_0F3833 */ |
42903f7f | 4123 | { |
592d1631 L |
4124 | { Bad_Opcode }, |
4125 | { Bad_Opcode }, | |
507bd325 | 4126 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4127 | }, |
4128 | ||
1ceb70f8 | 4129 | /* PREFIX_0F3834 */ |
42903f7f | 4130 | { |
592d1631 L |
4131 | { Bad_Opcode }, |
4132 | { Bad_Opcode }, | |
507bd325 | 4133 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4134 | }, |
4135 | ||
1ceb70f8 | 4136 | /* PREFIX_0F3835 */ |
42903f7f | 4137 | { |
592d1631 L |
4138 | { Bad_Opcode }, |
4139 | { Bad_Opcode }, | |
507bd325 | 4140 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4141 | }, |
4142 | ||
1ceb70f8 | 4143 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4144 | { |
592d1631 L |
4145 | { Bad_Opcode }, |
4146 | { Bad_Opcode }, | |
507bd325 | 4147 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4148 | }, |
4149 | ||
1ceb70f8 | 4150 | /* PREFIX_0F3838 */ |
42903f7f | 4151 | { |
592d1631 L |
4152 | { Bad_Opcode }, |
4153 | { Bad_Opcode }, | |
507bd325 | 4154 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4155 | }, |
4156 | ||
1ceb70f8 | 4157 | /* PREFIX_0F3839 */ |
42903f7f | 4158 | { |
592d1631 L |
4159 | { Bad_Opcode }, |
4160 | { Bad_Opcode }, | |
507bd325 | 4161 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4162 | }, |
4163 | ||
1ceb70f8 | 4164 | /* PREFIX_0F383A */ |
42903f7f | 4165 | { |
592d1631 L |
4166 | { Bad_Opcode }, |
4167 | { Bad_Opcode }, | |
507bd325 | 4168 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4169 | }, |
4170 | ||
1ceb70f8 | 4171 | /* PREFIX_0F383B */ |
42903f7f | 4172 | { |
592d1631 L |
4173 | { Bad_Opcode }, |
4174 | { Bad_Opcode }, | |
507bd325 | 4175 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4176 | }, |
4177 | ||
1ceb70f8 | 4178 | /* PREFIX_0F383C */ |
42903f7f | 4179 | { |
592d1631 L |
4180 | { Bad_Opcode }, |
4181 | { Bad_Opcode }, | |
507bd325 | 4182 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4183 | }, |
4184 | ||
1ceb70f8 | 4185 | /* PREFIX_0F383D */ |
42903f7f | 4186 | { |
592d1631 L |
4187 | { Bad_Opcode }, |
4188 | { Bad_Opcode }, | |
507bd325 | 4189 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4190 | }, |
4191 | ||
1ceb70f8 | 4192 | /* PREFIX_0F383E */ |
42903f7f | 4193 | { |
592d1631 L |
4194 | { Bad_Opcode }, |
4195 | { Bad_Opcode }, | |
507bd325 | 4196 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4197 | }, |
4198 | ||
1ceb70f8 | 4199 | /* PREFIX_0F383F */ |
42903f7f | 4200 | { |
592d1631 L |
4201 | { Bad_Opcode }, |
4202 | { Bad_Opcode }, | |
507bd325 | 4203 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4204 | }, |
4205 | ||
1ceb70f8 | 4206 | /* PREFIX_0F3840 */ |
42903f7f | 4207 | { |
592d1631 L |
4208 | { Bad_Opcode }, |
4209 | { Bad_Opcode }, | |
507bd325 | 4210 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4211 | }, |
4212 | ||
1ceb70f8 | 4213 | /* PREFIX_0F3841 */ |
42903f7f | 4214 | { |
592d1631 L |
4215 | { Bad_Opcode }, |
4216 | { Bad_Opcode }, | |
507bd325 | 4217 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4218 | }, |
4219 | ||
f1f8f695 L |
4220 | /* PREFIX_0F3880 */ |
4221 | { | |
592d1631 L |
4222 | { Bad_Opcode }, |
4223 | { Bad_Opcode }, | |
507bd325 | 4224 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4225 | }, |
4226 | ||
4227 | /* PREFIX_0F3881 */ | |
4228 | { | |
592d1631 L |
4229 | { Bad_Opcode }, |
4230 | { Bad_Opcode }, | |
507bd325 | 4231 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4232 | }, |
4233 | ||
6c30d220 L |
4234 | /* PREFIX_0F3882 */ |
4235 | { | |
4236 | { Bad_Opcode }, | |
4237 | { Bad_Opcode }, | |
507bd325 | 4238 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4239 | }, |
4240 | ||
a0046408 L |
4241 | /* PREFIX_0F38C8 */ |
4242 | { | |
507bd325 | 4243 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4244 | }, |
4245 | ||
4246 | /* PREFIX_0F38C9 */ | |
4247 | { | |
507bd325 | 4248 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4249 | }, |
4250 | ||
4251 | /* PREFIX_0F38CA */ | |
4252 | { | |
507bd325 | 4253 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4254 | }, |
4255 | ||
4256 | /* PREFIX_0F38CB */ | |
4257 | { | |
507bd325 | 4258 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4259 | }, |
4260 | ||
4261 | /* PREFIX_0F38CC */ | |
4262 | { | |
507bd325 | 4263 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4264 | }, |
4265 | ||
4266 | /* PREFIX_0F38CD */ | |
4267 | { | |
507bd325 | 4268 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4269 | }, |
4270 | ||
48521003 IT |
4271 | /* PREFIX_0F38CF */ |
4272 | { | |
4273 | { Bad_Opcode }, | |
4274 | { Bad_Opcode }, | |
4275 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, | |
4276 | }, | |
4277 | ||
c0f3af97 L |
4278 | /* PREFIX_0F38DB */ |
4279 | { | |
592d1631 L |
4280 | { Bad_Opcode }, |
4281 | { Bad_Opcode }, | |
507bd325 | 4282 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4283 | }, |
4284 | ||
4285 | /* PREFIX_0F38DC */ | |
4286 | { | |
592d1631 L |
4287 | { Bad_Opcode }, |
4288 | { Bad_Opcode }, | |
507bd325 | 4289 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4290 | }, |
4291 | ||
4292 | /* PREFIX_0F38DD */ | |
4293 | { | |
592d1631 L |
4294 | { Bad_Opcode }, |
4295 | { Bad_Opcode }, | |
507bd325 | 4296 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4297 | }, |
4298 | ||
4299 | /* PREFIX_0F38DE */ | |
4300 | { | |
592d1631 L |
4301 | { Bad_Opcode }, |
4302 | { Bad_Opcode }, | |
507bd325 | 4303 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4304 | }, |
4305 | ||
4306 | /* PREFIX_0F38DF */ | |
4307 | { | |
592d1631 L |
4308 | { Bad_Opcode }, |
4309 | { Bad_Opcode }, | |
507bd325 | 4310 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4311 | }, |
4312 | ||
1ceb70f8 | 4313 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4314 | { |
507bd325 | 4315 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4316 | { Bad_Opcode }, |
507bd325 L |
4317 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4318 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4319 | }, |
4320 | ||
1ceb70f8 | 4321 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4322 | { |
507bd325 | 4323 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4324 | { Bad_Opcode }, |
507bd325 L |
4325 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4326 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4327 | }, |
4328 | ||
603555e5 | 4329 | /* PREFIX_0F38F5 */ |
e2e1fcde L |
4330 | { |
4331 | { Bad_Opcode }, | |
603555e5 L |
4332 | { Bad_Opcode }, |
4333 | { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, | |
4334 | }, | |
4335 | ||
4336 | /* PREFIX_0F38F6 */ | |
4337 | { | |
4338 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
4339 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4340 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4341 | { Bad_Opcode }, |
4342 | }, | |
4343 | ||
c0a30a9f L |
4344 | /* PREFIX_0F38F8 */ |
4345 | { | |
4346 | { Bad_Opcode }, | |
5d79adc4 | 4347 | { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, |
c0a30a9f | 4348 | { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, |
5d79adc4 | 4349 | { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, |
c0a30a9f L |
4350 | }, |
4351 | ||
4352 | /* PREFIX_0F38F9 */ | |
4353 | { | |
4354 | { MOD_TABLE (MOD_0F38F9_PREFIX_0) }, | |
4355 | }, | |
4356 | ||
1ceb70f8 | 4357 | /* PREFIX_0F3A08 */ |
42903f7f | 4358 | { |
592d1631 L |
4359 | { Bad_Opcode }, |
4360 | { Bad_Opcode }, | |
507bd325 | 4361 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4362 | }, |
4363 | ||
1ceb70f8 | 4364 | /* PREFIX_0F3A09 */ |
42903f7f | 4365 | { |
592d1631 L |
4366 | { Bad_Opcode }, |
4367 | { Bad_Opcode }, | |
507bd325 | 4368 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4369 | }, |
4370 | ||
1ceb70f8 | 4371 | /* PREFIX_0F3A0A */ |
42903f7f | 4372 | { |
592d1631 L |
4373 | { Bad_Opcode }, |
4374 | { Bad_Opcode }, | |
507bd325 | 4375 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4376 | }, |
4377 | ||
1ceb70f8 | 4378 | /* PREFIX_0F3A0B */ |
42903f7f | 4379 | { |
592d1631 L |
4380 | { Bad_Opcode }, |
4381 | { Bad_Opcode }, | |
507bd325 | 4382 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4383 | }, |
4384 | ||
1ceb70f8 | 4385 | /* PREFIX_0F3A0C */ |
42903f7f | 4386 | { |
592d1631 L |
4387 | { Bad_Opcode }, |
4388 | { Bad_Opcode }, | |
507bd325 | 4389 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4390 | }, |
4391 | ||
1ceb70f8 | 4392 | /* PREFIX_0F3A0D */ |
42903f7f | 4393 | { |
592d1631 L |
4394 | { Bad_Opcode }, |
4395 | { Bad_Opcode }, | |
507bd325 | 4396 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4397 | }, |
4398 | ||
1ceb70f8 | 4399 | /* PREFIX_0F3A0E */ |
42903f7f | 4400 | { |
592d1631 L |
4401 | { Bad_Opcode }, |
4402 | { Bad_Opcode }, | |
507bd325 | 4403 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4404 | }, |
4405 | ||
1ceb70f8 | 4406 | /* PREFIX_0F3A14 */ |
42903f7f | 4407 | { |
592d1631 L |
4408 | { Bad_Opcode }, |
4409 | { Bad_Opcode }, | |
507bd325 | 4410 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4411 | }, |
4412 | ||
1ceb70f8 | 4413 | /* PREFIX_0F3A15 */ |
42903f7f | 4414 | { |
592d1631 L |
4415 | { Bad_Opcode }, |
4416 | { Bad_Opcode }, | |
507bd325 | 4417 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4418 | }, |
4419 | ||
1ceb70f8 | 4420 | /* PREFIX_0F3A16 */ |
42903f7f | 4421 | { |
592d1631 L |
4422 | { Bad_Opcode }, |
4423 | { Bad_Opcode }, | |
507bd325 | 4424 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4425 | }, |
4426 | ||
1ceb70f8 | 4427 | /* PREFIX_0F3A17 */ |
42903f7f | 4428 | { |
592d1631 L |
4429 | { Bad_Opcode }, |
4430 | { Bad_Opcode }, | |
507bd325 | 4431 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4432 | }, |
4433 | ||
1ceb70f8 | 4434 | /* PREFIX_0F3A20 */ |
42903f7f | 4435 | { |
592d1631 L |
4436 | { Bad_Opcode }, |
4437 | { Bad_Opcode }, | |
507bd325 | 4438 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4439 | }, |
4440 | ||
1ceb70f8 | 4441 | /* PREFIX_0F3A21 */ |
42903f7f | 4442 | { |
592d1631 L |
4443 | { Bad_Opcode }, |
4444 | { Bad_Opcode }, | |
507bd325 | 4445 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4446 | }, |
4447 | ||
1ceb70f8 | 4448 | /* PREFIX_0F3A22 */ |
42903f7f | 4449 | { |
592d1631 L |
4450 | { Bad_Opcode }, |
4451 | { Bad_Opcode }, | |
507bd325 | 4452 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4453 | }, |
4454 | ||
1ceb70f8 | 4455 | /* PREFIX_0F3A40 */ |
42903f7f | 4456 | { |
592d1631 L |
4457 | { Bad_Opcode }, |
4458 | { Bad_Opcode }, | |
507bd325 | 4459 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4460 | }, |
4461 | ||
1ceb70f8 | 4462 | /* PREFIX_0F3A41 */ |
42903f7f | 4463 | { |
592d1631 L |
4464 | { Bad_Opcode }, |
4465 | { Bad_Opcode }, | |
507bd325 | 4466 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4467 | }, |
4468 | ||
1ceb70f8 | 4469 | /* PREFIX_0F3A42 */ |
42903f7f | 4470 | { |
592d1631 L |
4471 | { Bad_Opcode }, |
4472 | { Bad_Opcode }, | |
507bd325 | 4473 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4474 | }, |
381d071f | 4475 | |
c0f3af97 L |
4476 | /* PREFIX_0F3A44 */ |
4477 | { | |
592d1631 L |
4478 | { Bad_Opcode }, |
4479 | { Bad_Opcode }, | |
507bd325 | 4480 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4481 | }, |
4482 | ||
1ceb70f8 | 4483 | /* PREFIX_0F3A60 */ |
381d071f | 4484 | { |
592d1631 L |
4485 | { Bad_Opcode }, |
4486 | { Bad_Opcode }, | |
15c7c1d8 | 4487 | { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4488 | }, |
4489 | ||
1ceb70f8 | 4490 | /* PREFIX_0F3A61 */ |
381d071f | 4491 | { |
592d1631 L |
4492 | { Bad_Opcode }, |
4493 | { Bad_Opcode }, | |
15c7c1d8 | 4494 | { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4495 | }, |
4496 | ||
1ceb70f8 | 4497 | /* PREFIX_0F3A62 */ |
381d071f | 4498 | { |
592d1631 L |
4499 | { Bad_Opcode }, |
4500 | { Bad_Opcode }, | |
507bd325 | 4501 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4502 | }, |
4503 | ||
1ceb70f8 | 4504 | /* PREFIX_0F3A63 */ |
381d071f | 4505 | { |
592d1631 L |
4506 | { Bad_Opcode }, |
4507 | { Bad_Opcode }, | |
507bd325 | 4508 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4509 | }, |
09a2c6cf | 4510 | |
a0046408 L |
4511 | /* PREFIX_0F3ACC */ |
4512 | { | |
507bd325 | 4513 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4514 | }, |
4515 | ||
48521003 IT |
4516 | /* PREFIX_0F3ACE */ |
4517 | { | |
4518 | { Bad_Opcode }, | |
4519 | { Bad_Opcode }, | |
4520 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4521 | }, | |
4522 | ||
4523 | /* PREFIX_0F3ACF */ | |
4524 | { | |
4525 | { Bad_Opcode }, | |
4526 | { Bad_Opcode }, | |
4527 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4528 | }, | |
4529 | ||
c0f3af97 | 4530 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4531 | { |
592d1631 L |
4532 | { Bad_Opcode }, |
4533 | { Bad_Opcode }, | |
507bd325 | 4534 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4535 | }, |
4536 | ||
592a252b | 4537 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4538 | { |
ec6f095a | 4539 | { "vmovups", { XM, EXx }, 0 }, |
5b872f7d | 4540 | { "vmovss", { XMVexScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4541 | { "vmovupd", { XM, EXx }, 0 }, |
5b872f7d | 4542 | { "vmovsd", { XMVexScalar, VexScalar, EXxmm_mq }, 0 }, |
09a2c6cf L |
4543 | }, |
4544 | ||
592a252b | 4545 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4546 | { |
ec6f095a L |
4547 | { "vmovups", { EXxS, XM }, 0 }, |
4548 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, | |
4549 | { "vmovupd", { EXxS, XM }, 0 }, | |
4550 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, | |
09a2c6cf L |
4551 | }, |
4552 | ||
592a252b | 4553 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4554 | { |
592a252b | 4555 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
ec6f095a | 4556 | { "vmovsldup", { XM, EXx }, 0 }, |
18897deb | 4557 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) }, |
ec6f095a | 4558 | { "vmovddup", { XM, EXymmq }, 0 }, |
09a2c6cf L |
4559 | }, |
4560 | ||
592a252b | 4561 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4562 | { |
592a252b | 4563 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
ec6f095a | 4564 | { "vmovshdup", { XM, EXx }, 0 }, |
18897deb | 4565 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) }, |
5f754f58 | 4566 | }, |
7c52e0e8 | 4567 | |
592a252b | 4568 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4569 | { |
592d1631 | 4570 | { Bad_Opcode }, |
2b7bcc87 | 4571 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 }, |
592d1631 | 4572 | { Bad_Opcode }, |
2b7bcc87 | 4573 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 }, |
5f754f58 | 4574 | }, |
7c52e0e8 | 4575 | |
592a252b | 4576 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4577 | { |
592d1631 | 4578 | { Bad_Opcode }, |
5b872f7d | 4579 | { "vcvttss2si", { Gdq, EXxmm_md }, 0 }, |
592d1631 | 4580 | { Bad_Opcode }, |
5b872f7d | 4581 | { "vcvttsd2si", { Gdq, EXxmm_mq }, 0 }, |
5f754f58 | 4582 | }, |
7c52e0e8 | 4583 | |
592a252b | 4584 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4585 | { |
592d1631 | 4586 | { Bad_Opcode }, |
5b872f7d | 4587 | { "vcvtss2si", { Gdq, EXxmm_md }, 0 }, |
592d1631 | 4588 | { Bad_Opcode }, |
5b872f7d | 4589 | { "vcvtsd2si", { Gdq, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4590 | }, |
4591 | ||
592a252b | 4592 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4593 | { |
5b872f7d | 4594 | { "vucomiss", { XMScalar, EXxmm_md }, 0 }, |
592d1631 | 4595 | { Bad_Opcode }, |
5b872f7d | 4596 | { "vucomisd", { XMScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4597 | }, |
4598 | ||
592a252b | 4599 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4600 | { |
5b872f7d | 4601 | { "vcomiss", { XMScalar, EXxmm_md }, 0 }, |
592d1631 | 4602 | { Bad_Opcode }, |
5b872f7d | 4603 | { "vcomisd", { XMScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4604 | }, |
4605 | ||
43234a1e L |
4606 | /* PREFIX_VEX_0F41 */ |
4607 | { | |
4608 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4609 | { Bad_Opcode }, |
4610 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4611 | }, |
4612 | ||
4613 | /* PREFIX_VEX_0F42 */ | |
4614 | { | |
4615 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4616 | { Bad_Opcode }, |
4617 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4618 | }, |
4619 | ||
4620 | /* PREFIX_VEX_0F44 */ | |
4621 | { | |
4622 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4623 | { Bad_Opcode }, |
4624 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4625 | }, |
4626 | ||
4627 | /* PREFIX_VEX_0F45 */ | |
4628 | { | |
4629 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4630 | { Bad_Opcode }, |
4631 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4632 | }, |
4633 | ||
4634 | /* PREFIX_VEX_0F46 */ | |
4635 | { | |
4636 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4637 | { Bad_Opcode }, |
4638 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4639 | }, |
4640 | ||
4641 | /* PREFIX_VEX_0F47 */ | |
4642 | { | |
4643 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4644 | { Bad_Opcode }, |
4645 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4646 | }, |
4647 | ||
1ba585e8 | 4648 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4649 | { |
1ba585e8 | 4650 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4651 | { Bad_Opcode }, |
1ba585e8 IT |
4652 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4653 | }, | |
4654 | ||
4655 | /* PREFIX_VEX_0F4B */ | |
4656 | { | |
4657 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4658 | { Bad_Opcode }, |
4659 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4660 | }, | |
4661 | ||
592a252b | 4662 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4663 | { |
ec6f095a | 4664 | { "vsqrtps", { XM, EXx }, 0 }, |
5b872f7d | 4665 | { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4666 | { "vsqrtpd", { XM, EXx }, 0 }, |
5b872f7d | 4667 | { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4668 | }, |
4669 | ||
592a252b | 4670 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4671 | { |
ec6f095a | 4672 | { "vrsqrtps", { XM, EXx }, 0 }, |
5b872f7d | 4673 | { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
7c52e0e8 L |
4674 | }, |
4675 | ||
592a252b | 4676 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4677 | { |
ec6f095a | 4678 | { "vrcpps", { XM, EXx }, 0 }, |
5b872f7d | 4679 | { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
7c52e0e8 L |
4680 | }, |
4681 | ||
592a252b | 4682 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4683 | { |
ec6f095a | 4684 | { "vaddps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4685 | { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4686 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4687 | { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4688 | }, |
4689 | ||
592a252b | 4690 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4691 | { |
ec6f095a | 4692 | { "vmulps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4693 | { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4694 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4695 | { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4696 | }, |
4697 | ||
592a252b | 4698 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4699 | { |
ec6f095a | 4700 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
5b872f7d | 4701 | { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4702 | { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, |
5b872f7d | 4703 | { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4704 | }, |
4705 | ||
592a252b | 4706 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4707 | { |
ec6f095a L |
4708 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
4709 | { "vcvttps2dq", { XM, EXx }, 0 }, | |
4710 | { "vcvtps2dq", { XM, EXx }, 0 }, | |
7c52e0e8 L |
4711 | }, |
4712 | ||
592a252b | 4713 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4714 | { |
ec6f095a | 4715 | { "vsubps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4716 | { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4717 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4718 | { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4719 | }, |
4720 | ||
592a252b | 4721 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4722 | { |
ec6f095a | 4723 | { "vminps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4724 | { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4725 | { "vminpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4726 | { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4727 | }, |
4728 | ||
592a252b | 4729 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4730 | { |
ec6f095a | 4731 | { "vdivps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4732 | { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4733 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4734 | { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4735 | }, |
4736 | ||
592a252b | 4737 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4738 | { |
ec6f095a | 4739 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4740 | { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4741 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4742 | { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4743 | }, |
4744 | ||
592a252b | 4745 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4746 | { |
592d1631 L |
4747 | { Bad_Opcode }, |
4748 | { Bad_Opcode }, | |
ec6f095a | 4749 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4750 | }, |
4751 | ||
592a252b | 4752 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4753 | { |
592d1631 L |
4754 | { Bad_Opcode }, |
4755 | { Bad_Opcode }, | |
ec6f095a | 4756 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4757 | }, |
4758 | ||
592a252b | 4759 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4760 | { |
592d1631 L |
4761 | { Bad_Opcode }, |
4762 | { Bad_Opcode }, | |
ec6f095a | 4763 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4764 | }, |
4765 | ||
592a252b | 4766 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4767 | { |
592d1631 L |
4768 | { Bad_Opcode }, |
4769 | { Bad_Opcode }, | |
ec6f095a | 4770 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4771 | }, |
4772 | ||
592a252b | 4773 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4774 | { |
592d1631 L |
4775 | { Bad_Opcode }, |
4776 | { Bad_Opcode }, | |
ec6f095a | 4777 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4778 | }, |
4779 | ||
592a252b | 4780 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4781 | { |
592d1631 L |
4782 | { Bad_Opcode }, |
4783 | { Bad_Opcode }, | |
ec6f095a | 4784 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4785 | }, |
4786 | ||
592a252b | 4787 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4788 | { |
592d1631 L |
4789 | { Bad_Opcode }, |
4790 | { Bad_Opcode }, | |
ec6f095a | 4791 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 | 4792 | }, |
6439fc28 | 4793 | |
592a252b | 4794 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4795 | { |
592d1631 L |
4796 | { Bad_Opcode }, |
4797 | { Bad_Opcode }, | |
ec6f095a | 4798 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4799 | }, |
4800 | ||
592a252b | 4801 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4802 | { |
592d1631 L |
4803 | { Bad_Opcode }, |
4804 | { Bad_Opcode }, | |
ec6f095a | 4805 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4806 | }, |
4807 | ||
592a252b | 4808 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4809 | { |
592d1631 L |
4810 | { Bad_Opcode }, |
4811 | { Bad_Opcode }, | |
ec6f095a | 4812 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4813 | }, |
4814 | ||
592a252b | 4815 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4816 | { |
592d1631 L |
4817 | { Bad_Opcode }, |
4818 | { Bad_Opcode }, | |
ec6f095a | 4819 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4820 | }, |
4821 | ||
592a252b | 4822 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4823 | { |
592d1631 L |
4824 | { Bad_Opcode }, |
4825 | { Bad_Opcode }, | |
ec6f095a | 4826 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4827 | }, |
4828 | ||
592a252b | 4829 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4830 | { |
592d1631 L |
4831 | { Bad_Opcode }, |
4832 | { Bad_Opcode }, | |
ec6f095a | 4833 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4834 | }, |
4835 | ||
592a252b | 4836 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4837 | { |
592d1631 L |
4838 | { Bad_Opcode }, |
4839 | { Bad_Opcode }, | |
ec6f095a | 4840 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4841 | }, |
4842 | ||
592a252b | 4843 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4844 | { |
592d1631 L |
4845 | { Bad_Opcode }, |
4846 | { Bad_Opcode }, | |
592a252b | 4847 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
4848 | }, |
4849 | ||
592a252b | 4850 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 4851 | { |
592d1631 | 4852 | { Bad_Opcode }, |
ec6f095a L |
4853 | { "vmovdqu", { XM, EXx }, 0 }, |
4854 | { "vmovdqa", { XM, EXx }, 0 }, | |
c0f3af97 L |
4855 | }, |
4856 | ||
592a252b | 4857 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 4858 | { |
592d1631 | 4859 | { Bad_Opcode }, |
ec6f095a L |
4860 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
4861 | { "vpshufd", { XM, EXx, Ib }, 0 }, | |
4862 | { "vpshuflw", { XM, EXx, Ib }, 0 }, | |
c0f3af97 L |
4863 | }, |
4864 | ||
592a252b | 4865 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 4866 | { |
592d1631 L |
4867 | { Bad_Opcode }, |
4868 | { Bad_Opcode }, | |
ec6f095a | 4869 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4870 | }, |
4871 | ||
592a252b | 4872 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 4873 | { |
592d1631 L |
4874 | { Bad_Opcode }, |
4875 | { Bad_Opcode }, | |
ec6f095a | 4876 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4877 | }, |
4878 | ||
592a252b | 4879 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 4880 | { |
592d1631 L |
4881 | { Bad_Opcode }, |
4882 | { Bad_Opcode }, | |
ec6f095a | 4883 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4884 | }, |
4885 | ||
592a252b | 4886 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 4887 | { |
592d1631 L |
4888 | { Bad_Opcode }, |
4889 | { Bad_Opcode }, | |
ec6f095a | 4890 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4891 | }, |
4892 | ||
592a252b | 4893 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 4894 | { |
592d1631 L |
4895 | { Bad_Opcode }, |
4896 | { Bad_Opcode }, | |
ec6f095a | 4897 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4898 | }, |
4899 | ||
592a252b | 4900 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 4901 | { |
592d1631 L |
4902 | { Bad_Opcode }, |
4903 | { Bad_Opcode }, | |
ec6f095a | 4904 | { "vpslld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4905 | }, |
4906 | ||
592a252b | 4907 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 4908 | { |
592d1631 L |
4909 | { Bad_Opcode }, |
4910 | { Bad_Opcode }, | |
ec6f095a | 4911 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4912 | }, |
4913 | ||
592a252b | 4914 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 4915 | { |
592d1631 L |
4916 | { Bad_Opcode }, |
4917 | { Bad_Opcode }, | |
ec6f095a | 4918 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4919 | }, |
4920 | ||
592a252b | 4921 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 4922 | { |
592d1631 L |
4923 | { Bad_Opcode }, |
4924 | { Bad_Opcode }, | |
ec6f095a | 4925 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4926 | }, |
4927 | ||
592a252b | 4928 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 4929 | { |
592d1631 L |
4930 | { Bad_Opcode }, |
4931 | { Bad_Opcode }, | |
ec6f095a | 4932 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4933 | }, |
4934 | ||
592a252b | 4935 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 4936 | { |
592d1631 L |
4937 | { Bad_Opcode }, |
4938 | { Bad_Opcode }, | |
ec6f095a | 4939 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4940 | }, |
4941 | ||
592a252b | 4942 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 4943 | { |
592d1631 L |
4944 | { Bad_Opcode }, |
4945 | { Bad_Opcode }, | |
ec6f095a | 4946 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4947 | }, |
4948 | ||
592a252b | 4949 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 4950 | { |
592d1631 L |
4951 | { Bad_Opcode }, |
4952 | { Bad_Opcode }, | |
ec6f095a | 4953 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4954 | }, |
4955 | ||
592a252b | 4956 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 4957 | { |
ec6f095a | 4958 | { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) }, |
c0f3af97 L |
4959 | }, |
4960 | ||
592a252b | 4961 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 4962 | { |
592d1631 L |
4963 | { Bad_Opcode }, |
4964 | { Bad_Opcode }, | |
ec6f095a L |
4965 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
4966 | { "vhaddps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
4967 | }, |
4968 | ||
592a252b | 4969 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 4970 | { |
592d1631 L |
4971 | { Bad_Opcode }, |
4972 | { Bad_Opcode }, | |
ec6f095a L |
4973 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
4974 | { "vhsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
4975 | }, |
4976 | ||
592a252b | 4977 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 4978 | { |
592d1631 | 4979 | { Bad_Opcode }, |
592a252b L |
4980 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
4981 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
4982 | }, |
4983 | ||
592a252b | 4984 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 4985 | { |
592d1631 | 4986 | { Bad_Opcode }, |
ec6f095a L |
4987 | { "vmovdqu", { EXxS, XM }, 0 }, |
4988 | { "vmovdqa", { EXxS, XM }, 0 }, | |
c0f3af97 L |
4989 | }, |
4990 | ||
43234a1e L |
4991 | /* PREFIX_VEX_0F90 */ |
4992 | { | |
4993 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
4994 | { Bad_Opcode }, |
4995 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
4996 | }, |
4997 | ||
4998 | /* PREFIX_VEX_0F91 */ | |
4999 | { | |
5000 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5001 | { Bad_Opcode }, |
5002 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5003 | }, |
5004 | ||
5005 | /* PREFIX_VEX_0F92 */ | |
5006 | { | |
5007 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5008 | { Bad_Opcode }, |
90a915bf | 5009 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5010 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5011 | }, |
5012 | ||
5013 | /* PREFIX_VEX_0F93 */ | |
5014 | { | |
5015 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5016 | { Bad_Opcode }, |
90a915bf | 5017 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5018 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5019 | }, |
5020 | ||
5021 | /* PREFIX_VEX_0F98 */ | |
5022 | { | |
5023 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5024 | { Bad_Opcode }, |
5025 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5026 | }, | |
5027 | ||
5028 | /* PREFIX_VEX_0F99 */ | |
5029 | { | |
5030 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5031 | { Bad_Opcode }, | |
5032 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5033 | }, |
5034 | ||
592a252b | 5035 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5036 | { |
ec6f095a | 5037 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
5b872f7d | 5038 | { "vcmpss", { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 }, |
ec6f095a | 5039 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, |
5b872f7d | 5040 | { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 }, |
c0f3af97 L |
5041 | }, |
5042 | ||
592a252b | 5043 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5044 | { |
592d1631 L |
5045 | { Bad_Opcode }, |
5046 | { Bad_Opcode }, | |
592a252b | 5047 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5048 | }, |
5049 | ||
592a252b | 5050 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5051 | { |
592d1631 L |
5052 | { Bad_Opcode }, |
5053 | { Bad_Opcode }, | |
592a252b | 5054 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5055 | }, |
5056 | ||
592a252b | 5057 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5058 | { |
592d1631 L |
5059 | { Bad_Opcode }, |
5060 | { Bad_Opcode }, | |
ec6f095a L |
5061 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
5062 | { "vaddsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5063 | }, |
5064 | ||
592a252b | 5065 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5066 | { |
592d1631 L |
5067 | { Bad_Opcode }, |
5068 | { Bad_Opcode }, | |
ec6f095a | 5069 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5070 | }, |
5071 | ||
592a252b | 5072 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5073 | { |
592d1631 L |
5074 | { Bad_Opcode }, |
5075 | { Bad_Opcode }, | |
ec6f095a | 5076 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5077 | }, |
5078 | ||
592a252b | 5079 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5080 | { |
592d1631 L |
5081 | { Bad_Opcode }, |
5082 | { Bad_Opcode }, | |
ec6f095a | 5083 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5084 | }, |
5085 | ||
592a252b | 5086 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5087 | { |
592d1631 L |
5088 | { Bad_Opcode }, |
5089 | { Bad_Opcode }, | |
ec6f095a | 5090 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5091 | }, |
5092 | ||
592a252b | 5093 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5094 | { |
592d1631 L |
5095 | { Bad_Opcode }, |
5096 | { Bad_Opcode }, | |
ec6f095a | 5097 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5098 | }, |
5099 | ||
592a252b | 5100 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5101 | { |
592d1631 L |
5102 | { Bad_Opcode }, |
5103 | { Bad_Opcode }, | |
592a252b | 5104 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5105 | }, |
5106 | ||
592a252b | 5107 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5108 | { |
592d1631 L |
5109 | { Bad_Opcode }, |
5110 | { Bad_Opcode }, | |
592a252b | 5111 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5112 | }, |
5113 | ||
592a252b | 5114 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5115 | { |
592d1631 L |
5116 | { Bad_Opcode }, |
5117 | { Bad_Opcode }, | |
ec6f095a | 5118 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5119 | }, |
5120 | ||
592a252b | 5121 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5122 | { |
592d1631 L |
5123 | { Bad_Opcode }, |
5124 | { Bad_Opcode }, | |
ec6f095a | 5125 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5126 | }, |
5127 | ||
592a252b | 5128 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5129 | { |
592d1631 L |
5130 | { Bad_Opcode }, |
5131 | { Bad_Opcode }, | |
ec6f095a | 5132 | { "vpminub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5133 | }, |
5134 | ||
592a252b | 5135 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5136 | { |
592d1631 L |
5137 | { Bad_Opcode }, |
5138 | { Bad_Opcode }, | |
ec6f095a | 5139 | { "vpand", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5140 | }, |
5141 | ||
592a252b | 5142 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5143 | { |
592d1631 L |
5144 | { Bad_Opcode }, |
5145 | { Bad_Opcode }, | |
ec6f095a | 5146 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5147 | }, |
5148 | ||
592a252b | 5149 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5150 | { |
592d1631 L |
5151 | { Bad_Opcode }, |
5152 | { Bad_Opcode }, | |
ec6f095a | 5153 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5154 | }, |
5155 | ||
592a252b | 5156 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5157 | { |
592d1631 L |
5158 | { Bad_Opcode }, |
5159 | { Bad_Opcode }, | |
ec6f095a | 5160 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5161 | }, |
5162 | ||
592a252b | 5163 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5164 | { |
592d1631 L |
5165 | { Bad_Opcode }, |
5166 | { Bad_Opcode }, | |
ec6f095a | 5167 | { "vpandn", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5168 | }, |
5169 | ||
592a252b | 5170 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5171 | { |
592d1631 L |
5172 | { Bad_Opcode }, |
5173 | { Bad_Opcode }, | |
ec6f095a | 5174 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5175 | }, |
5176 | ||
592a252b | 5177 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5178 | { |
592d1631 L |
5179 | { Bad_Opcode }, |
5180 | { Bad_Opcode }, | |
ec6f095a | 5181 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5182 | }, |
5183 | ||
592a252b | 5184 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5185 | { |
592d1631 L |
5186 | { Bad_Opcode }, |
5187 | { Bad_Opcode }, | |
ec6f095a | 5188 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5189 | }, |
5190 | ||
592a252b | 5191 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5192 | { |
592d1631 L |
5193 | { Bad_Opcode }, |
5194 | { Bad_Opcode }, | |
ec6f095a | 5195 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5196 | }, |
5197 | ||
592a252b | 5198 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5199 | { |
592d1631 L |
5200 | { Bad_Opcode }, |
5201 | { Bad_Opcode }, | |
ec6f095a | 5202 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5203 | }, |
5204 | ||
592a252b | 5205 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5206 | { |
592d1631 L |
5207 | { Bad_Opcode }, |
5208 | { Bad_Opcode }, | |
ec6f095a | 5209 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5210 | }, |
5211 | ||
592a252b | 5212 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5213 | { |
592d1631 | 5214 | { Bad_Opcode }, |
ec6f095a L |
5215 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
5216 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, | |
5217 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, | |
c0f3af97 L |
5218 | }, |
5219 | ||
592a252b | 5220 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5221 | { |
592d1631 L |
5222 | { Bad_Opcode }, |
5223 | { Bad_Opcode }, | |
592a252b | 5224 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5225 | }, |
5226 | ||
592a252b | 5227 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5228 | { |
592d1631 L |
5229 | { Bad_Opcode }, |
5230 | { Bad_Opcode }, | |
ec6f095a | 5231 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5232 | }, |
5233 | ||
592a252b | 5234 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5235 | { |
592d1631 L |
5236 | { Bad_Opcode }, |
5237 | { Bad_Opcode }, | |
ec6f095a | 5238 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5239 | }, |
5240 | ||
592a252b | 5241 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5242 | { |
592d1631 L |
5243 | { Bad_Opcode }, |
5244 | { Bad_Opcode }, | |
ec6f095a | 5245 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5246 | }, |
5247 | ||
592a252b | 5248 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5249 | { |
592d1631 L |
5250 | { Bad_Opcode }, |
5251 | { Bad_Opcode }, | |
ec6f095a | 5252 | { "vpor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5253 | }, |
5254 | ||
592a252b | 5255 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5256 | { |
592d1631 L |
5257 | { Bad_Opcode }, |
5258 | { Bad_Opcode }, | |
ec6f095a | 5259 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5260 | }, |
5261 | ||
592a252b | 5262 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5263 | { |
592d1631 L |
5264 | { Bad_Opcode }, |
5265 | { Bad_Opcode }, | |
ec6f095a | 5266 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5267 | }, |
5268 | ||
592a252b | 5269 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5270 | { |
592d1631 L |
5271 | { Bad_Opcode }, |
5272 | { Bad_Opcode }, | |
ec6f095a | 5273 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5274 | }, |
5275 | ||
592a252b | 5276 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5277 | { |
592d1631 L |
5278 | { Bad_Opcode }, |
5279 | { Bad_Opcode }, | |
ec6f095a | 5280 | { "vpxor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5281 | }, |
5282 | ||
592a252b | 5283 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5284 | { |
592d1631 L |
5285 | { Bad_Opcode }, |
5286 | { Bad_Opcode }, | |
5287 | { Bad_Opcode }, | |
592a252b | 5288 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5289 | }, |
5290 | ||
592a252b | 5291 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5292 | { |
592d1631 L |
5293 | { Bad_Opcode }, |
5294 | { Bad_Opcode }, | |
ec6f095a | 5295 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5296 | }, |
5297 | ||
592a252b | 5298 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5299 | { |
592d1631 L |
5300 | { Bad_Opcode }, |
5301 | { Bad_Opcode }, | |
ec6f095a | 5302 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5303 | }, |
5304 | ||
592a252b | 5305 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5306 | { |
592d1631 L |
5307 | { Bad_Opcode }, |
5308 | { Bad_Opcode }, | |
ec6f095a | 5309 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5310 | }, |
5311 | ||
592a252b | 5312 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5313 | { |
592d1631 L |
5314 | { Bad_Opcode }, |
5315 | { Bad_Opcode }, | |
ec6f095a | 5316 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5317 | }, |
5318 | ||
592a252b | 5319 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5320 | { |
592d1631 L |
5321 | { Bad_Opcode }, |
5322 | { Bad_Opcode }, | |
ec6f095a | 5323 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5324 | }, |
5325 | ||
592a252b | 5326 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5327 | { |
592d1631 L |
5328 | { Bad_Opcode }, |
5329 | { Bad_Opcode }, | |
ec6f095a | 5330 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5331 | }, |
5332 | ||
592a252b | 5333 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5334 | { |
592d1631 L |
5335 | { Bad_Opcode }, |
5336 | { Bad_Opcode }, | |
592a252b | 5337 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5338 | }, |
5339 | ||
592a252b | 5340 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5341 | { |
592d1631 L |
5342 | { Bad_Opcode }, |
5343 | { Bad_Opcode }, | |
ec6f095a | 5344 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5345 | }, |
5346 | ||
592a252b | 5347 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5348 | { |
592d1631 L |
5349 | { Bad_Opcode }, |
5350 | { Bad_Opcode }, | |
ec6f095a | 5351 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5352 | }, |
5353 | ||
592a252b | 5354 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5355 | { |
592d1631 L |
5356 | { Bad_Opcode }, |
5357 | { Bad_Opcode }, | |
ec6f095a | 5358 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5359 | }, |
5360 | ||
592a252b | 5361 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5362 | { |
592d1631 L |
5363 | { Bad_Opcode }, |
5364 | { Bad_Opcode }, | |
ec6f095a | 5365 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5366 | }, |
5367 | ||
592a252b | 5368 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5369 | { |
592d1631 L |
5370 | { Bad_Opcode }, |
5371 | { Bad_Opcode }, | |
ec6f095a | 5372 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5373 | }, |
5374 | ||
592a252b | 5375 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5376 | { |
592d1631 L |
5377 | { Bad_Opcode }, |
5378 | { Bad_Opcode }, | |
ec6f095a | 5379 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5380 | }, |
5381 | ||
592a252b | 5382 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5383 | { |
592d1631 L |
5384 | { Bad_Opcode }, |
5385 | { Bad_Opcode }, | |
ec6f095a | 5386 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5387 | }, |
5388 | ||
592a252b | 5389 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5390 | { |
592d1631 L |
5391 | { Bad_Opcode }, |
5392 | { Bad_Opcode }, | |
ec6f095a | 5393 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5394 | }, |
5395 | ||
592a252b | 5396 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5397 | { |
592d1631 L |
5398 | { Bad_Opcode }, |
5399 | { Bad_Opcode }, | |
ec6f095a | 5400 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5401 | }, |
5402 | ||
592a252b | 5403 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5404 | { |
592d1631 L |
5405 | { Bad_Opcode }, |
5406 | { Bad_Opcode }, | |
ec6f095a | 5407 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5408 | }, |
5409 | ||
592a252b | 5410 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5411 | { |
592d1631 L |
5412 | { Bad_Opcode }, |
5413 | { Bad_Opcode }, | |
ec6f095a | 5414 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5415 | }, |
5416 | ||
592a252b | 5417 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5418 | { |
592d1631 L |
5419 | { Bad_Opcode }, |
5420 | { Bad_Opcode }, | |
ec6f095a | 5421 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5422 | }, |
5423 | ||
592a252b | 5424 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5425 | { |
592d1631 L |
5426 | { Bad_Opcode }, |
5427 | { Bad_Opcode }, | |
ec6f095a | 5428 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5429 | }, |
5430 | ||
592a252b | 5431 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5432 | { |
592d1631 L |
5433 | { Bad_Opcode }, |
5434 | { Bad_Opcode }, | |
ec6f095a | 5435 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5436 | }, |
5437 | ||
592a252b | 5438 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5439 | { |
592d1631 L |
5440 | { Bad_Opcode }, |
5441 | { Bad_Opcode }, | |
ec6f095a | 5442 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5443 | }, |
5444 | ||
592a252b | 5445 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5446 | { |
592d1631 L |
5447 | { Bad_Opcode }, |
5448 | { Bad_Opcode }, | |
ec6f095a | 5449 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5450 | }, |
5451 | ||
592a252b | 5452 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5453 | { |
592d1631 L |
5454 | { Bad_Opcode }, |
5455 | { Bad_Opcode }, | |
ec6f095a | 5456 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5457 | }, |
5458 | ||
592a252b | 5459 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5460 | { |
592d1631 L |
5461 | { Bad_Opcode }, |
5462 | { Bad_Opcode }, | |
ec6f095a | 5463 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5464 | }, |
5465 | ||
592a252b | 5466 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5467 | { |
592d1631 L |
5468 | { Bad_Opcode }, |
5469 | { Bad_Opcode }, | |
ec6f095a | 5470 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5471 | }, |
5472 | ||
592a252b | 5473 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5474 | { |
592d1631 L |
5475 | { Bad_Opcode }, |
5476 | { Bad_Opcode }, | |
592a252b | 5477 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5478 | }, |
5479 | ||
592a252b | 5480 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5481 | { |
592d1631 L |
5482 | { Bad_Opcode }, |
5483 | { Bad_Opcode }, | |
592a252b | 5484 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5485 | }, |
5486 | ||
592a252b | 5487 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5488 | { |
592d1631 L |
5489 | { Bad_Opcode }, |
5490 | { Bad_Opcode }, | |
592a252b | 5491 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5492 | }, |
5493 | ||
592a252b | 5494 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5495 | { |
592d1631 L |
5496 | { Bad_Opcode }, |
5497 | { Bad_Opcode }, | |
592a252b | 5498 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5499 | }, |
5500 | ||
592a252b | 5501 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5502 | { |
5503 | { Bad_Opcode }, | |
5504 | { Bad_Opcode }, | |
6431c801 | 5505 | { VEX_W_TABLE (VEX_W_0F3813_P_2) }, |
c7b8aa3a L |
5506 | }, |
5507 | ||
6c30d220 L |
5508 | /* PREFIX_VEX_0F3816 */ |
5509 | { | |
5510 | { Bad_Opcode }, | |
5511 | { Bad_Opcode }, | |
5512 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5513 | }, | |
5514 | ||
592a252b | 5515 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5516 | { |
592d1631 L |
5517 | { Bad_Opcode }, |
5518 | { Bad_Opcode }, | |
ec6f095a | 5519 | { "vptest", { XM, EXx }, 0 }, |
c0f3af97 L |
5520 | }, |
5521 | ||
592a252b | 5522 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5523 | { |
592d1631 L |
5524 | { Bad_Opcode }, |
5525 | { Bad_Opcode }, | |
6c30d220 | 5526 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5527 | }, |
5528 | ||
592a252b | 5529 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5530 | { |
592d1631 L |
5531 | { Bad_Opcode }, |
5532 | { Bad_Opcode }, | |
6c30d220 | 5533 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5534 | }, |
5535 | ||
592a252b | 5536 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5537 | { |
592d1631 L |
5538 | { Bad_Opcode }, |
5539 | { Bad_Opcode }, | |
592a252b | 5540 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5541 | }, |
5542 | ||
592a252b | 5543 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5544 | { |
592d1631 L |
5545 | { Bad_Opcode }, |
5546 | { Bad_Opcode }, | |
ec6f095a | 5547 | { "vpabsb", { XM, EXx }, 0 }, |
c0f3af97 L |
5548 | }, |
5549 | ||
592a252b | 5550 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5551 | { |
592d1631 L |
5552 | { Bad_Opcode }, |
5553 | { Bad_Opcode }, | |
ec6f095a | 5554 | { "vpabsw", { XM, EXx }, 0 }, |
c0f3af97 L |
5555 | }, |
5556 | ||
592a252b | 5557 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5558 | { |
592d1631 L |
5559 | { Bad_Opcode }, |
5560 | { Bad_Opcode }, | |
ec6f095a | 5561 | { "vpabsd", { XM, EXx }, 0 }, |
c0f3af97 L |
5562 | }, |
5563 | ||
592a252b | 5564 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5565 | { |
592d1631 L |
5566 | { Bad_Opcode }, |
5567 | { Bad_Opcode }, | |
ec6f095a | 5568 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5569 | }, |
5570 | ||
592a252b | 5571 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5572 | { |
592d1631 L |
5573 | { Bad_Opcode }, |
5574 | { Bad_Opcode }, | |
ec6f095a | 5575 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5576 | }, |
5577 | ||
592a252b | 5578 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5579 | { |
592d1631 L |
5580 | { Bad_Opcode }, |
5581 | { Bad_Opcode }, | |
ec6f095a | 5582 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5583 | }, |
5584 | ||
592a252b | 5585 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5586 | { |
592d1631 L |
5587 | { Bad_Opcode }, |
5588 | { Bad_Opcode }, | |
ec6f095a | 5589 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5590 | }, |
5591 | ||
592a252b | 5592 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5593 | { |
592d1631 L |
5594 | { Bad_Opcode }, |
5595 | { Bad_Opcode }, | |
ec6f095a | 5596 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5597 | }, |
5598 | ||
592a252b | 5599 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5600 | { |
592d1631 L |
5601 | { Bad_Opcode }, |
5602 | { Bad_Opcode }, | |
ec6f095a | 5603 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5604 | }, |
5605 | ||
592a252b | 5606 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5607 | { |
592d1631 L |
5608 | { Bad_Opcode }, |
5609 | { Bad_Opcode }, | |
ec6f095a | 5610 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5611 | }, |
5612 | ||
592a252b | 5613 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5614 | { |
592d1631 L |
5615 | { Bad_Opcode }, |
5616 | { Bad_Opcode }, | |
ec6f095a | 5617 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5618 | }, |
5619 | ||
592a252b | 5620 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5621 | { |
592d1631 L |
5622 | { Bad_Opcode }, |
5623 | { Bad_Opcode }, | |
592a252b | 5624 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5625 | }, |
5626 | ||
592a252b | 5627 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5628 | { |
592d1631 L |
5629 | { Bad_Opcode }, |
5630 | { Bad_Opcode }, | |
ec6f095a | 5631 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5632 | }, |
5633 | ||
592a252b | 5634 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5635 | { |
592d1631 L |
5636 | { Bad_Opcode }, |
5637 | { Bad_Opcode }, | |
592a252b | 5638 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5639 | }, |
5640 | ||
592a252b | 5641 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5642 | { |
592d1631 L |
5643 | { Bad_Opcode }, |
5644 | { Bad_Opcode }, | |
592a252b | 5645 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5646 | }, |
5647 | ||
592a252b | 5648 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5649 | { |
592d1631 L |
5650 | { Bad_Opcode }, |
5651 | { Bad_Opcode }, | |
592a252b | 5652 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5653 | }, |
5654 | ||
592a252b | 5655 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5656 | { |
592d1631 L |
5657 | { Bad_Opcode }, |
5658 | { Bad_Opcode }, | |
592a252b | 5659 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5660 | }, |
5661 | ||
592a252b | 5662 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5663 | { |
592d1631 L |
5664 | { Bad_Opcode }, |
5665 | { Bad_Opcode }, | |
ec6f095a | 5666 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5667 | }, |
5668 | ||
592a252b | 5669 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5670 | { |
592d1631 L |
5671 | { Bad_Opcode }, |
5672 | { Bad_Opcode }, | |
ec6f095a | 5673 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5674 | }, |
5675 | ||
592a252b | 5676 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5677 | { |
592d1631 L |
5678 | { Bad_Opcode }, |
5679 | { Bad_Opcode }, | |
ec6f095a | 5680 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5681 | }, |
5682 | ||
592a252b | 5683 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5684 | { |
592d1631 L |
5685 | { Bad_Opcode }, |
5686 | { Bad_Opcode }, | |
ec6f095a | 5687 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5688 | }, |
5689 | ||
592a252b | 5690 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5691 | { |
592d1631 L |
5692 | { Bad_Opcode }, |
5693 | { Bad_Opcode }, | |
ec6f095a | 5694 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5695 | }, |
5696 | ||
592a252b | 5697 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5698 | { |
592d1631 L |
5699 | { Bad_Opcode }, |
5700 | { Bad_Opcode }, | |
ec6f095a | 5701 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
5702 | }, |
5703 | ||
5704 | /* PREFIX_VEX_0F3836 */ | |
5705 | { | |
5706 | { Bad_Opcode }, | |
5707 | { Bad_Opcode }, | |
5708 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5709 | }, |
5710 | ||
592a252b | 5711 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5712 | { |
592d1631 L |
5713 | { Bad_Opcode }, |
5714 | { Bad_Opcode }, | |
ec6f095a | 5715 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5716 | }, |
5717 | ||
592a252b | 5718 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5719 | { |
592d1631 L |
5720 | { Bad_Opcode }, |
5721 | { Bad_Opcode }, | |
ec6f095a | 5722 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5723 | }, |
5724 | ||
592a252b | 5725 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5726 | { |
592d1631 L |
5727 | { Bad_Opcode }, |
5728 | { Bad_Opcode }, | |
ec6f095a | 5729 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5730 | }, |
5731 | ||
592a252b | 5732 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5733 | { |
592d1631 L |
5734 | { Bad_Opcode }, |
5735 | { Bad_Opcode }, | |
ec6f095a | 5736 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5737 | }, |
5738 | ||
592a252b | 5739 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5740 | { |
592d1631 L |
5741 | { Bad_Opcode }, |
5742 | { Bad_Opcode }, | |
ec6f095a | 5743 | { "vpminud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5744 | }, |
5745 | ||
592a252b | 5746 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5747 | { |
592d1631 L |
5748 | { Bad_Opcode }, |
5749 | { Bad_Opcode }, | |
ec6f095a | 5750 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5751 | }, |
5752 | ||
592a252b | 5753 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5754 | { |
592d1631 L |
5755 | { Bad_Opcode }, |
5756 | { Bad_Opcode }, | |
ec6f095a | 5757 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5758 | }, |
5759 | ||
592a252b | 5760 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5761 | { |
592d1631 L |
5762 | { Bad_Opcode }, |
5763 | { Bad_Opcode }, | |
ec6f095a | 5764 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5765 | }, |
5766 | ||
592a252b | 5767 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5768 | { |
592d1631 L |
5769 | { Bad_Opcode }, |
5770 | { Bad_Opcode }, | |
ec6f095a | 5771 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5772 | }, |
5773 | ||
592a252b | 5774 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5775 | { |
592d1631 L |
5776 | { Bad_Opcode }, |
5777 | { Bad_Opcode }, | |
ec6f095a | 5778 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5779 | }, |
5780 | ||
592a252b | 5781 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5782 | { |
592d1631 L |
5783 | { Bad_Opcode }, |
5784 | { Bad_Opcode }, | |
592a252b | 5785 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5786 | }, |
5787 | ||
6c30d220 L |
5788 | /* PREFIX_VEX_0F3845 */ |
5789 | { | |
5790 | { Bad_Opcode }, | |
5791 | { Bad_Opcode }, | |
bf890a93 | 5792 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5793 | }, |
5794 | ||
5795 | /* PREFIX_VEX_0F3846 */ | |
5796 | { | |
5797 | { Bad_Opcode }, | |
5798 | { Bad_Opcode }, | |
5799 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5800 | }, | |
5801 | ||
5802 | /* PREFIX_VEX_0F3847 */ | |
5803 | { | |
5804 | { Bad_Opcode }, | |
5805 | { Bad_Opcode }, | |
bf890a93 | 5806 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5807 | }, |
5808 | ||
5809 | /* PREFIX_VEX_0F3858 */ | |
5810 | { | |
5811 | { Bad_Opcode }, | |
5812 | { Bad_Opcode }, | |
5813 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5814 | }, | |
5815 | ||
5816 | /* PREFIX_VEX_0F3859 */ | |
5817 | { | |
5818 | { Bad_Opcode }, | |
5819 | { Bad_Opcode }, | |
5820 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5821 | }, | |
5822 | ||
5823 | /* PREFIX_VEX_0F385A */ | |
5824 | { | |
5825 | { Bad_Opcode }, | |
5826 | { Bad_Opcode }, | |
5827 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5828 | }, | |
5829 | ||
5830 | /* PREFIX_VEX_0F3878 */ | |
5831 | { | |
5832 | { Bad_Opcode }, | |
5833 | { Bad_Opcode }, | |
5834 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5835 | }, | |
5836 | ||
5837 | /* PREFIX_VEX_0F3879 */ | |
5838 | { | |
5839 | { Bad_Opcode }, | |
5840 | { Bad_Opcode }, | |
5841 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5842 | }, | |
5843 | ||
5844 | /* PREFIX_VEX_0F388C */ | |
5845 | { | |
5846 | { Bad_Opcode }, | |
5847 | { Bad_Opcode }, | |
f7002f42 | 5848 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
5849 | }, |
5850 | ||
5851 | /* PREFIX_VEX_0F388E */ | |
5852 | { | |
5853 | { Bad_Opcode }, | |
5854 | { Bad_Opcode }, | |
f7002f42 | 5855 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
5856 | }, |
5857 | ||
5858 | /* PREFIX_VEX_0F3890 */ | |
5859 | { | |
5860 | { Bad_Opcode }, | |
5861 | { Bad_Opcode }, | |
bf890a93 | 5862 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5863 | }, |
5864 | ||
5865 | /* PREFIX_VEX_0F3891 */ | |
5866 | { | |
5867 | { Bad_Opcode }, | |
5868 | { Bad_Opcode }, | |
bf890a93 | 5869 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5870 | }, |
5871 | ||
5872 | /* PREFIX_VEX_0F3892 */ | |
5873 | { | |
5874 | { Bad_Opcode }, | |
5875 | { Bad_Opcode }, | |
bf890a93 | 5876 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5877 | }, |
5878 | ||
5879 | /* PREFIX_VEX_0F3893 */ | |
5880 | { | |
5881 | { Bad_Opcode }, | |
5882 | { Bad_Opcode }, | |
bf890a93 | 5883 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5884 | }, |
5885 | ||
592a252b | 5886 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 5887 | { |
592d1631 L |
5888 | { Bad_Opcode }, |
5889 | { Bad_Opcode }, | |
6df22cf6 | 5890 | { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
5891 | }, |
5892 | ||
592a252b | 5893 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 5894 | { |
592d1631 L |
5895 | { Bad_Opcode }, |
5896 | { Bad_Opcode }, | |
6df22cf6 | 5897 | { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
5898 | }, |
5899 | ||
592a252b | 5900 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 5901 | { |
592d1631 L |
5902 | { Bad_Opcode }, |
5903 | { Bad_Opcode }, | |
6df22cf6 | 5904 | { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
5905 | }, |
5906 | ||
592a252b | 5907 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 5908 | { |
592d1631 L |
5909 | { Bad_Opcode }, |
5910 | { Bad_Opcode }, | |
6df22cf6 | 5911 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
a5ff0eb2 L |
5912 | }, |
5913 | ||
592a252b | 5914 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 5915 | { |
592d1631 L |
5916 | { Bad_Opcode }, |
5917 | { Bad_Opcode }, | |
bf890a93 | 5918 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
5919 | }, |
5920 | ||
592a252b | 5921 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 5922 | { |
592d1631 L |
5923 | { Bad_Opcode }, |
5924 | { Bad_Opcode }, | |
bf890a93 | 5925 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
5926 | }, |
5927 | ||
592a252b | 5928 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 5929 | { |
592d1631 L |
5930 | { Bad_Opcode }, |
5931 | { Bad_Opcode }, | |
6df22cf6 | 5932 | { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
5933 | }, |
5934 | ||
592a252b | 5935 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 5936 | { |
592d1631 L |
5937 | { Bad_Opcode }, |
5938 | { Bad_Opcode }, | |
6df22cf6 | 5939 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
5940 | }, |
5941 | ||
592a252b | 5942 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 5943 | { |
592d1631 L |
5944 | { Bad_Opcode }, |
5945 | { Bad_Opcode }, | |
6df22cf6 | 5946 | { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
5947 | }, |
5948 | ||
592a252b | 5949 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 5950 | { |
592d1631 L |
5951 | { Bad_Opcode }, |
5952 | { Bad_Opcode }, | |
6df22cf6 | 5953 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
5954 | }, |
5955 | ||
592a252b | 5956 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 5957 | { |
592d1631 L |
5958 | { Bad_Opcode }, |
5959 | { Bad_Opcode }, | |
6df22cf6 | 5960 | { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
592d1631 | 5961 | { Bad_Opcode }, |
c0f3af97 L |
5962 | }, |
5963 | ||
592a252b | 5964 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 5965 | { |
592d1631 L |
5966 | { Bad_Opcode }, |
5967 | { Bad_Opcode }, | |
6df22cf6 | 5968 | { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
5969 | }, |
5970 | ||
592a252b | 5971 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 5972 | { |
592d1631 L |
5973 | { Bad_Opcode }, |
5974 | { Bad_Opcode }, | |
6df22cf6 | 5975 | { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
5976 | }, |
5977 | ||
592a252b | 5978 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 5979 | { |
592d1631 L |
5980 | { Bad_Opcode }, |
5981 | { Bad_Opcode }, | |
6df22cf6 | 5982 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
5983 | }, |
5984 | ||
592a252b | 5985 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 5986 | { |
592d1631 L |
5987 | { Bad_Opcode }, |
5988 | { Bad_Opcode }, | |
bf890a93 | 5989 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5990 | }, |
5991 | ||
592a252b | 5992 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 5993 | { |
592d1631 L |
5994 | { Bad_Opcode }, |
5995 | { Bad_Opcode }, | |
bf890a93 | 5996 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
5997 | }, |
5998 | ||
592a252b | 5999 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6000 | { |
592d1631 L |
6001 | { Bad_Opcode }, |
6002 | { Bad_Opcode }, | |
6df22cf6 | 6003 | { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6004 | }, |
6005 | ||
592a252b | 6006 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6007 | { |
592d1631 L |
6008 | { Bad_Opcode }, |
6009 | { Bad_Opcode }, | |
6df22cf6 | 6010 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6011 | }, |
6012 | ||
592a252b | 6013 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6014 | { |
592d1631 L |
6015 | { Bad_Opcode }, |
6016 | { Bad_Opcode }, | |
6df22cf6 | 6017 | { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6018 | }, |
6019 | ||
592a252b | 6020 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6021 | { |
592d1631 L |
6022 | { Bad_Opcode }, |
6023 | { Bad_Opcode }, | |
6df22cf6 | 6024 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6025 | }, |
6026 | ||
592a252b | 6027 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6028 | { |
592d1631 L |
6029 | { Bad_Opcode }, |
6030 | { Bad_Opcode }, | |
6df22cf6 | 6031 | { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6032 | }, |
6033 | ||
592a252b | 6034 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6035 | { |
592d1631 L |
6036 | { Bad_Opcode }, |
6037 | { Bad_Opcode }, | |
6df22cf6 | 6038 | { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6039 | }, |
6040 | ||
592a252b | 6041 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6042 | { |
592d1631 L |
6043 | { Bad_Opcode }, |
6044 | { Bad_Opcode }, | |
6df22cf6 | 6045 | { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6046 | }, |
6047 | ||
592a252b | 6048 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6049 | { |
592d1631 L |
6050 | { Bad_Opcode }, |
6051 | { Bad_Opcode }, | |
6df22cf6 | 6052 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6053 | }, |
6054 | ||
592a252b | 6055 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6056 | { |
592d1631 L |
6057 | { Bad_Opcode }, |
6058 | { Bad_Opcode }, | |
6df22cf6 | 6059 | { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6060 | }, |
6061 | ||
592a252b | 6062 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6063 | { |
592d1631 L |
6064 | { Bad_Opcode }, |
6065 | { Bad_Opcode }, | |
6df22cf6 | 6066 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6067 | }, |
6068 | ||
592a252b | 6069 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6070 | { |
592d1631 L |
6071 | { Bad_Opcode }, |
6072 | { Bad_Opcode }, | |
6df22cf6 | 6073 | { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6074 | }, |
6075 | ||
592a252b | 6076 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6077 | { |
592d1631 L |
6078 | { Bad_Opcode }, |
6079 | { Bad_Opcode }, | |
6df22cf6 | 6080 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6081 | }, |
6082 | ||
592a252b | 6083 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6084 | { |
592d1631 L |
6085 | { Bad_Opcode }, |
6086 | { Bad_Opcode }, | |
6df22cf6 | 6087 | { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6088 | }, |
6089 | ||
592a252b | 6090 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6091 | { |
592d1631 L |
6092 | { Bad_Opcode }, |
6093 | { Bad_Opcode }, | |
6df22cf6 | 6094 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6095 | }, |
6096 | ||
48521003 IT |
6097 | /* PREFIX_VEX_0F38CF */ |
6098 | { | |
6099 | { Bad_Opcode }, | |
6100 | { Bad_Opcode }, | |
6101 | { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, | |
6102 | }, | |
6103 | ||
592a252b | 6104 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6105 | { |
592d1631 L |
6106 | { Bad_Opcode }, |
6107 | { Bad_Opcode }, | |
592a252b | 6108 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6109 | }, |
6110 | ||
592a252b | 6111 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6112 | { |
592d1631 L |
6113 | { Bad_Opcode }, |
6114 | { Bad_Opcode }, | |
8dcf1fad | 6115 | { "vaesenc", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6116 | }, |
6117 | ||
592a252b | 6118 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6119 | { |
592d1631 L |
6120 | { Bad_Opcode }, |
6121 | { Bad_Opcode }, | |
8dcf1fad | 6122 | { "vaesenclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6123 | }, |
6124 | ||
592a252b | 6125 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6126 | { |
592d1631 L |
6127 | { Bad_Opcode }, |
6128 | { Bad_Opcode }, | |
8dcf1fad | 6129 | { "vaesdec", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6130 | }, |
6131 | ||
592a252b | 6132 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6133 | { |
592d1631 L |
6134 | { Bad_Opcode }, |
6135 | { Bad_Opcode }, | |
8dcf1fad | 6136 | { "vaesdeclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6137 | }, |
6138 | ||
f12dc422 L |
6139 | /* PREFIX_VEX_0F38F2 */ |
6140 | { | |
6141 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6142 | }, | |
6143 | ||
6144 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6145 | { | |
6146 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6147 | }, | |
6148 | ||
6149 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6150 | { | |
6151 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6152 | }, | |
6153 | ||
6154 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6155 | { | |
6156 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6157 | }, | |
6158 | ||
6c30d220 L |
6159 | /* PREFIX_VEX_0F38F5 */ |
6160 | { | |
6161 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6162 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6163 | { Bad_Opcode }, | |
6164 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6165 | }, | |
6166 | ||
6167 | /* PREFIX_VEX_0F38F6 */ | |
6168 | { | |
6169 | { Bad_Opcode }, | |
6170 | { Bad_Opcode }, | |
6171 | { Bad_Opcode }, | |
6172 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6173 | }, | |
6174 | ||
f12dc422 L |
6175 | /* PREFIX_VEX_0F38F7 */ |
6176 | { | |
6177 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6178 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6179 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6180 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6181 | }, | |
6182 | ||
6183 | /* PREFIX_VEX_0F3A00 */ | |
6184 | { | |
6185 | { Bad_Opcode }, | |
6186 | { Bad_Opcode }, | |
6187 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6188 | }, | |
6189 | ||
6190 | /* PREFIX_VEX_0F3A01 */ | |
6191 | { | |
6192 | { Bad_Opcode }, | |
6193 | { Bad_Opcode }, | |
6194 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6195 | }, | |
6196 | ||
6197 | /* PREFIX_VEX_0F3A02 */ | |
6198 | { | |
6199 | { Bad_Opcode }, | |
6200 | { Bad_Opcode }, | |
6201 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6202 | }, |
6203 | ||
592a252b | 6204 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6205 | { |
592d1631 L |
6206 | { Bad_Opcode }, |
6207 | { Bad_Opcode }, | |
592a252b | 6208 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6209 | }, |
6210 | ||
592a252b | 6211 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6212 | { |
592d1631 L |
6213 | { Bad_Opcode }, |
6214 | { Bad_Opcode }, | |
592a252b | 6215 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6216 | }, |
6217 | ||
592a252b | 6218 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6219 | { |
592d1631 L |
6220 | { Bad_Opcode }, |
6221 | { Bad_Opcode }, | |
592a252b | 6222 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6223 | }, |
6224 | ||
592a252b | 6225 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6226 | { |
592d1631 L |
6227 | { Bad_Opcode }, |
6228 | { Bad_Opcode }, | |
ec6f095a | 6229 | { "vroundps", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6230 | }, |
6231 | ||
592a252b | 6232 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6233 | { |
592d1631 L |
6234 | { Bad_Opcode }, |
6235 | { Bad_Opcode }, | |
ec6f095a | 6236 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6237 | }, |
6238 | ||
592a252b | 6239 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6240 | { |
592d1631 L |
6241 | { Bad_Opcode }, |
6242 | { Bad_Opcode }, | |
5b872f7d | 6243 | { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, 0 }, |
0bfee649 L |
6244 | }, |
6245 | ||
592a252b | 6246 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6247 | { |
592d1631 L |
6248 | { Bad_Opcode }, |
6249 | { Bad_Opcode }, | |
5b872f7d | 6250 | { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 }, |
0bfee649 L |
6251 | }, |
6252 | ||
592a252b | 6253 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6254 | { |
592d1631 L |
6255 | { Bad_Opcode }, |
6256 | { Bad_Opcode }, | |
ec6f095a | 6257 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6258 | }, |
6259 | ||
592a252b | 6260 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6261 | { |
592d1631 L |
6262 | { Bad_Opcode }, |
6263 | { Bad_Opcode }, | |
ec6f095a | 6264 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6265 | }, |
6266 | ||
592a252b | 6267 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6268 | { |
592d1631 L |
6269 | { Bad_Opcode }, |
6270 | { Bad_Opcode }, | |
ec6f095a | 6271 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6272 | }, |
6273 | ||
592a252b | 6274 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6275 | { |
592d1631 L |
6276 | { Bad_Opcode }, |
6277 | { Bad_Opcode }, | |
ec6f095a | 6278 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6279 | }, |
6280 | ||
592a252b | 6281 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6282 | { |
592d1631 L |
6283 | { Bad_Opcode }, |
6284 | { Bad_Opcode }, | |
592a252b | 6285 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6286 | }, |
6287 | ||
592a252b | 6288 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6289 | { |
592d1631 L |
6290 | { Bad_Opcode }, |
6291 | { Bad_Opcode }, | |
592a252b | 6292 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6293 | }, |
6294 | ||
592a252b | 6295 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6296 | { |
592d1631 L |
6297 | { Bad_Opcode }, |
6298 | { Bad_Opcode }, | |
592a252b | 6299 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6300 | }, |
6301 | ||
592a252b | 6302 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6303 | { |
592d1631 L |
6304 | { Bad_Opcode }, |
6305 | { Bad_Opcode }, | |
592a252b | 6306 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6307 | }, |
6308 | ||
592a252b | 6309 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6310 | { |
592d1631 L |
6311 | { Bad_Opcode }, |
6312 | { Bad_Opcode }, | |
592a252b | 6313 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6314 | }, |
6315 | ||
592a252b | 6316 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6317 | { |
592d1631 L |
6318 | { Bad_Opcode }, |
6319 | { Bad_Opcode }, | |
592a252b | 6320 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6321 | }, |
6322 | ||
592a252b | 6323 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6324 | { |
6325 | { Bad_Opcode }, | |
6326 | { Bad_Opcode }, | |
6431c801 | 6327 | { VEX_W_TABLE (VEX_W_0F3A1D_P_2) }, |
c7b8aa3a L |
6328 | }, |
6329 | ||
592a252b | 6330 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6331 | { |
592d1631 L |
6332 | { Bad_Opcode }, |
6333 | { Bad_Opcode }, | |
592a252b | 6334 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6335 | }, |
6336 | ||
592a252b | 6337 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6338 | { |
592d1631 L |
6339 | { Bad_Opcode }, |
6340 | { Bad_Opcode }, | |
592a252b | 6341 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6342 | }, |
6343 | ||
592a252b | 6344 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6345 | { |
592d1631 L |
6346 | { Bad_Opcode }, |
6347 | { Bad_Opcode }, | |
592a252b | 6348 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6349 | }, |
6350 | ||
43234a1e L |
6351 | /* PREFIX_VEX_0F3A30 */ |
6352 | { | |
6353 | { Bad_Opcode }, | |
6354 | { Bad_Opcode }, | |
6355 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6356 | }, | |
6357 | ||
1ba585e8 IT |
6358 | /* PREFIX_VEX_0F3A31 */ |
6359 | { | |
6360 | { Bad_Opcode }, | |
6361 | { Bad_Opcode }, | |
6362 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6363 | }, | |
6364 | ||
43234a1e L |
6365 | /* PREFIX_VEX_0F3A32 */ |
6366 | { | |
6367 | { Bad_Opcode }, | |
6368 | { Bad_Opcode }, | |
6369 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6370 | }, | |
6371 | ||
1ba585e8 IT |
6372 | /* PREFIX_VEX_0F3A33 */ |
6373 | { | |
6374 | { Bad_Opcode }, | |
6375 | { Bad_Opcode }, | |
6376 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6377 | }, | |
6378 | ||
6c30d220 L |
6379 | /* PREFIX_VEX_0F3A38 */ |
6380 | { | |
6381 | { Bad_Opcode }, | |
6382 | { Bad_Opcode }, | |
6383 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6384 | }, | |
6385 | ||
6386 | /* PREFIX_VEX_0F3A39 */ | |
6387 | { | |
6388 | { Bad_Opcode }, | |
6389 | { Bad_Opcode }, | |
6390 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6391 | }, | |
6392 | ||
592a252b | 6393 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6394 | { |
592d1631 L |
6395 | { Bad_Opcode }, |
6396 | { Bad_Opcode }, | |
ec6f095a | 6397 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6398 | }, |
6399 | ||
592a252b | 6400 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6401 | { |
592d1631 L |
6402 | { Bad_Opcode }, |
6403 | { Bad_Opcode }, | |
592a252b | 6404 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6405 | }, |
6406 | ||
592a252b | 6407 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6408 | { |
592d1631 L |
6409 | { Bad_Opcode }, |
6410 | { Bad_Opcode }, | |
ec6f095a | 6411 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6412 | }, |
6413 | ||
592a252b | 6414 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6415 | { |
592d1631 L |
6416 | { Bad_Opcode }, |
6417 | { Bad_Opcode }, | |
ff1982d5 | 6418 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, |
ce2f5b3c L |
6419 | }, |
6420 | ||
6c30d220 L |
6421 | /* PREFIX_VEX_0F3A46 */ |
6422 | { | |
6423 | { Bad_Opcode }, | |
6424 | { Bad_Opcode }, | |
6425 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6426 | }, | |
6427 | ||
592a252b | 6428 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6429 | { |
6430 | { Bad_Opcode }, | |
6431 | { Bad_Opcode }, | |
592a252b | 6432 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6433 | }, |
6434 | ||
592a252b | 6435 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6436 | { |
6437 | { Bad_Opcode }, | |
6438 | { Bad_Opcode }, | |
592a252b | 6439 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6440 | }, |
6441 | ||
592a252b | 6442 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6443 | { |
592d1631 L |
6444 | { Bad_Opcode }, |
6445 | { Bad_Opcode }, | |
592a252b | 6446 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6447 | }, |
6448 | ||
592a252b | 6449 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6450 | { |
592d1631 L |
6451 | { Bad_Opcode }, |
6452 | { Bad_Opcode }, | |
592a252b | 6453 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6454 | }, |
6455 | ||
592a252b | 6456 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6457 | { |
592d1631 L |
6458 | { Bad_Opcode }, |
6459 | { Bad_Opcode }, | |
6c30d220 | 6460 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6461 | }, |
6462 | ||
592a252b | 6463 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6464 | { |
592d1631 L |
6465 | { Bad_Opcode }, |
6466 | { Bad_Opcode }, | |
3a2430e0 | 6467 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6468 | }, |
6469 | ||
592a252b | 6470 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6471 | { |
592d1631 L |
6472 | { Bad_Opcode }, |
6473 | { Bad_Opcode }, | |
3a2430e0 | 6474 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6475 | }, |
6476 | ||
592a252b | 6477 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6478 | { |
592d1631 L |
6479 | { Bad_Opcode }, |
6480 | { Bad_Opcode }, | |
3a2430e0 | 6481 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6482 | }, |
6483 | ||
592a252b | 6484 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6485 | { |
592d1631 L |
6486 | { Bad_Opcode }, |
6487 | { Bad_Opcode }, | |
3a2430e0 | 6488 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6489 | }, |
6490 | ||
592a252b | 6491 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6492 | { |
592d1631 L |
6493 | { Bad_Opcode }, |
6494 | { Bad_Opcode }, | |
592a252b | 6495 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6496 | { Bad_Opcode }, |
c0f3af97 L |
6497 | }, |
6498 | ||
592a252b | 6499 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6500 | { |
592d1631 L |
6501 | { Bad_Opcode }, |
6502 | { Bad_Opcode }, | |
592a252b | 6503 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6504 | }, |
6505 | ||
592a252b | 6506 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6507 | { |
592d1631 L |
6508 | { Bad_Opcode }, |
6509 | { Bad_Opcode }, | |
592a252b | 6510 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6511 | }, |
6512 | ||
592a252b | 6513 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6514 | { |
592d1631 L |
6515 | { Bad_Opcode }, |
6516 | { Bad_Opcode }, | |
592a252b | 6517 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6518 | }, |
a5ff0eb2 | 6519 | |
592a252b | 6520 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6521 | { |
592d1631 L |
6522 | { Bad_Opcode }, |
6523 | { Bad_Opcode }, | |
3a2430e0 | 6524 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6525 | }, |
6526 | ||
592a252b | 6527 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6528 | { |
592d1631 L |
6529 | { Bad_Opcode }, |
6530 | { Bad_Opcode }, | |
3a2430e0 | 6531 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6532 | }, |
6533 | ||
592a252b | 6534 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6535 | { |
592d1631 L |
6536 | { Bad_Opcode }, |
6537 | { Bad_Opcode }, | |
592a252b | 6538 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6539 | }, |
6540 | ||
592a252b | 6541 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6542 | { |
592d1631 L |
6543 | { Bad_Opcode }, |
6544 | { Bad_Opcode }, | |
592a252b | 6545 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6546 | }, |
6547 | ||
592a252b | 6548 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6549 | { |
592d1631 L |
6550 | { Bad_Opcode }, |
6551 | { Bad_Opcode }, | |
3a2430e0 | 6552 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6553 | }, |
6554 | ||
592a252b | 6555 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6556 | { |
592d1631 L |
6557 | { Bad_Opcode }, |
6558 | { Bad_Opcode }, | |
3a2430e0 | 6559 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6560 | }, |
6561 | ||
592a252b | 6562 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6563 | { |
592d1631 L |
6564 | { Bad_Opcode }, |
6565 | { Bad_Opcode }, | |
592a252b | 6566 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6567 | }, |
6568 | ||
592a252b | 6569 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6570 | { |
592d1631 L |
6571 | { Bad_Opcode }, |
6572 | { Bad_Opcode }, | |
592a252b | 6573 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6574 | }, |
6575 | ||
592a252b | 6576 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6577 | { |
592d1631 L |
6578 | { Bad_Opcode }, |
6579 | { Bad_Opcode }, | |
3a2430e0 | 6580 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6581 | }, |
6582 | ||
592a252b | 6583 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6584 | { |
592d1631 L |
6585 | { Bad_Opcode }, |
6586 | { Bad_Opcode }, | |
3a2430e0 | 6587 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6588 | }, |
6589 | ||
592a252b | 6590 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6591 | { |
592d1631 L |
6592 | { Bad_Opcode }, |
6593 | { Bad_Opcode }, | |
592a252b | 6594 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6595 | }, |
6596 | ||
592a252b | 6597 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6598 | { |
592d1631 L |
6599 | { Bad_Opcode }, |
6600 | { Bad_Opcode }, | |
592a252b | 6601 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6602 | }, |
6603 | ||
592a252b | 6604 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6605 | { |
592d1631 L |
6606 | { Bad_Opcode }, |
6607 | { Bad_Opcode }, | |
3a2430e0 | 6608 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 6609 | { Bad_Opcode }, |
922d8de8 DR |
6610 | }, |
6611 | ||
592a252b | 6612 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6613 | { |
592d1631 L |
6614 | { Bad_Opcode }, |
6615 | { Bad_Opcode }, | |
3a2430e0 | 6616 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6617 | }, |
6618 | ||
592a252b | 6619 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6620 | { |
592d1631 L |
6621 | { Bad_Opcode }, |
6622 | { Bad_Opcode }, | |
592a252b | 6623 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6624 | }, |
6625 | ||
592a252b | 6626 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6627 | { |
592d1631 L |
6628 | { Bad_Opcode }, |
6629 | { Bad_Opcode }, | |
592a252b | 6630 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6631 | }, |
6632 | ||
48521003 IT |
6633 | /* PREFIX_VEX_0F3ACE */ |
6634 | { | |
6635 | { Bad_Opcode }, | |
6636 | { Bad_Opcode }, | |
6637 | { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, | |
6638 | }, | |
6639 | ||
6640 | /* PREFIX_VEX_0F3ACF */ | |
6641 | { | |
6642 | { Bad_Opcode }, | |
6643 | { Bad_Opcode }, | |
6644 | { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, | |
6645 | }, | |
6646 | ||
592a252b | 6647 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6648 | { |
592d1631 L |
6649 | { Bad_Opcode }, |
6650 | { Bad_Opcode }, | |
592a252b | 6651 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6652 | }, |
6c30d220 L |
6653 | |
6654 | /* PREFIX_VEX_0F3AF0 */ | |
6655 | { | |
6656 | { Bad_Opcode }, | |
6657 | { Bad_Opcode }, | |
6658 | { Bad_Opcode }, | |
6659 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6660 | }, | |
43234a1e | 6661 | |
ad692897 | 6662 | #include "i386-dis-evex-prefix.h" |
c0f3af97 L |
6663 | }; |
6664 | ||
6665 | static const struct dis386 x86_64_table[][2] = { | |
6666 | /* X86_64_06 */ | |
6667 | { | |
bf890a93 | 6668 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6669 | }, |
6670 | ||
6671 | /* X86_64_07 */ | |
6672 | { | |
bf890a93 | 6673 | { "popP", { es }, 0 }, |
c0f3af97 L |
6674 | }, |
6675 | ||
1673df32 | 6676 | /* X86_64_0E */ |
c0f3af97 | 6677 | { |
bf890a93 | 6678 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6679 | }, |
6680 | ||
6681 | /* X86_64_16 */ | |
6682 | { | |
bf890a93 | 6683 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6684 | }, |
6685 | ||
6686 | /* X86_64_17 */ | |
6687 | { | |
bf890a93 | 6688 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6689 | }, |
6690 | ||
6691 | /* X86_64_1E */ | |
6692 | { | |
bf890a93 | 6693 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6694 | }, |
6695 | ||
6696 | /* X86_64_1F */ | |
6697 | { | |
bf890a93 | 6698 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6699 | }, |
6700 | ||
6701 | /* X86_64_27 */ | |
6702 | { | |
bf890a93 | 6703 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6704 | }, |
6705 | ||
6706 | /* X86_64_2F */ | |
6707 | { | |
bf890a93 | 6708 | { "das", { XX }, 0 }, |
c0f3af97 L |
6709 | }, |
6710 | ||
6711 | /* X86_64_37 */ | |
6712 | { | |
bf890a93 | 6713 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
6714 | }, |
6715 | ||
6716 | /* X86_64_3F */ | |
6717 | { | |
bf890a93 | 6718 | { "aas", { XX }, 0 }, |
c0f3af97 L |
6719 | }, |
6720 | ||
6721 | /* X86_64_60 */ | |
6722 | { | |
bf890a93 | 6723 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
6724 | }, |
6725 | ||
6726 | /* X86_64_61 */ | |
6727 | { | |
bf890a93 | 6728 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
6729 | }, |
6730 | ||
6731 | /* X86_64_62 */ | |
6732 | { | |
6733 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6734 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6735 | }, |
6736 | ||
6737 | /* X86_64_63 */ | |
6738 | { | |
bf890a93 | 6739 | { "arpl", { Ew, Gw }, 0 }, |
bc31405e | 6740 | { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 }, |
c0f3af97 L |
6741 | }, |
6742 | ||
6743 | /* X86_64_6D */ | |
6744 | { | |
bf890a93 IT |
6745 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6746 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
6747 | }, |
6748 | ||
6749 | /* X86_64_6F */ | |
6750 | { | |
bf890a93 IT |
6751 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6752 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
6753 | }, |
6754 | ||
d039fef3 | 6755 | /* X86_64_82 */ |
8b89fe14 | 6756 | { |
de194d85 | 6757 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 6758 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
6759 | }, |
6760 | ||
c0f3af97 L |
6761 | /* X86_64_9A */ |
6762 | { | |
8f570d62 | 6763 | { "{l|}call{T|}", { Ap }, 0 }, |
c0f3af97 L |
6764 | }, |
6765 | ||
aeab2b26 JB |
6766 | /* X86_64_C2 */ |
6767 | { | |
6768 | { "retP", { Iw, BND }, 0 }, | |
6769 | { "ret@", { Iw, BND }, 0 }, | |
6770 | }, | |
6771 | ||
6772 | /* X86_64_C3 */ | |
6773 | { | |
6774 | { "retP", { BND }, 0 }, | |
6775 | { "ret@", { BND }, 0 }, | |
6776 | }, | |
6777 | ||
c0f3af97 L |
6778 | /* X86_64_C4 */ |
6779 | { | |
6780 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6781 | { VEX_C4_TABLE (VEX_0F) }, | |
6782 | }, | |
6783 | ||
6784 | /* X86_64_C5 */ | |
6785 | { | |
6786 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6787 | { VEX_C5_TABLE (VEX_0F) }, | |
6788 | }, | |
6789 | ||
6790 | /* X86_64_CE */ | |
6791 | { | |
bf890a93 | 6792 | { "into", { XX }, 0 }, |
c0f3af97 L |
6793 | }, |
6794 | ||
6795 | /* X86_64_D4 */ | |
6796 | { | |
bf890a93 | 6797 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
6798 | }, |
6799 | ||
6800 | /* X86_64_D5 */ | |
6801 | { | |
bf890a93 | 6802 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
6803 | }, |
6804 | ||
a72d2af2 L |
6805 | /* X86_64_E8 */ |
6806 | { | |
6807 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 6808 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
6809 | }, |
6810 | ||
6811 | /* X86_64_E9 */ | |
6812 | { | |
6813 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 6814 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
6815 | }, |
6816 | ||
c0f3af97 L |
6817 | /* X86_64_EA */ |
6818 | { | |
8f570d62 | 6819 | { "{l|}jmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
6820 | }, |
6821 | ||
6822 | /* X86_64_0F01_REG_0 */ | |
6823 | { | |
d1c36125 | 6824 | { "sgdt{Q|Q}", { M }, 0 }, |
bf890a93 | 6825 | { "sgdt", { M }, 0 }, |
c0f3af97 L |
6826 | }, |
6827 | ||
6828 | /* X86_64_0F01_REG_1 */ | |
6829 | { | |
d1c36125 | 6830 | { "sidt{Q|Q}", { M }, 0 }, |
bf890a93 | 6831 | { "sidt", { M }, 0 }, |
c0f3af97 L |
6832 | }, |
6833 | ||
6834 | /* X86_64_0F01_REG_2 */ | |
6835 | { | |
bf890a93 IT |
6836 | { "lgdt{Q|Q}", { M }, 0 }, |
6837 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
6838 | }, |
6839 | ||
6840 | /* X86_64_0F01_REG_3 */ | |
6841 | { | |
bf890a93 IT |
6842 | { "lidt{Q|Q}", { M }, 0 }, |
6843 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
6844 | }, |
6845 | }; | |
6846 | ||
6847 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
6848 | |
6849 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
6850 | { |
6851 | /* 00 */ | |
507bd325 L |
6852 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
6853 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
6854 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
6855 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
6856 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
6857 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
6858 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
6859 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 6860 | /* 08 */ |
507bd325 L |
6861 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
6862 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
6863 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
6864 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
6865 | { Bad_Opcode }, |
6866 | { Bad_Opcode }, | |
6867 | { Bad_Opcode }, | |
6868 | { Bad_Opcode }, | |
f88c9eb0 SP |
6869 | /* 10 */ |
6870 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
6871 | { Bad_Opcode }, |
6872 | { Bad_Opcode }, | |
6873 | { Bad_Opcode }, | |
f88c9eb0 SP |
6874 | { PREFIX_TABLE (PREFIX_0F3814) }, |
6875 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 6876 | { Bad_Opcode }, |
f88c9eb0 SP |
6877 | { PREFIX_TABLE (PREFIX_0F3817) }, |
6878 | /* 18 */ | |
592d1631 L |
6879 | { Bad_Opcode }, |
6880 | { Bad_Opcode }, | |
6881 | { Bad_Opcode }, | |
6882 | { Bad_Opcode }, | |
507bd325 L |
6883 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
6884 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
6885 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 6886 | { Bad_Opcode }, |
f88c9eb0 SP |
6887 | /* 20 */ |
6888 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
6889 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
6890 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
6891 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
6892 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
6893 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
6894 | { Bad_Opcode }, |
6895 | { Bad_Opcode }, | |
f88c9eb0 SP |
6896 | /* 28 */ |
6897 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
6898 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
6899 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
6900 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
6901 | { Bad_Opcode }, |
6902 | { Bad_Opcode }, | |
6903 | { Bad_Opcode }, | |
6904 | { Bad_Opcode }, | |
f88c9eb0 SP |
6905 | /* 30 */ |
6906 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
6907 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
6908 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
6909 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
6910 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
6911 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 6912 | { Bad_Opcode }, |
f88c9eb0 SP |
6913 | { PREFIX_TABLE (PREFIX_0F3837) }, |
6914 | /* 38 */ | |
6915 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
6916 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
6917 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
6918 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
6919 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
6920 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
6921 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
6922 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
6923 | /* 40 */ | |
6924 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
6925 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
6926 | { Bad_Opcode }, |
6927 | { Bad_Opcode }, | |
6928 | { Bad_Opcode }, | |
6929 | { Bad_Opcode }, | |
6930 | { Bad_Opcode }, | |
6931 | { Bad_Opcode }, | |
f88c9eb0 | 6932 | /* 48 */ |
592d1631 L |
6933 | { Bad_Opcode }, |
6934 | { Bad_Opcode }, | |
6935 | { Bad_Opcode }, | |
6936 | { Bad_Opcode }, | |
6937 | { Bad_Opcode }, | |
6938 | { Bad_Opcode }, | |
6939 | { Bad_Opcode }, | |
6940 | { Bad_Opcode }, | |
f88c9eb0 | 6941 | /* 50 */ |
592d1631 L |
6942 | { Bad_Opcode }, |
6943 | { Bad_Opcode }, | |
6944 | { Bad_Opcode }, | |
6945 | { Bad_Opcode }, | |
6946 | { Bad_Opcode }, | |
6947 | { Bad_Opcode }, | |
6948 | { Bad_Opcode }, | |
6949 | { Bad_Opcode }, | |
f88c9eb0 | 6950 | /* 58 */ |
592d1631 L |
6951 | { Bad_Opcode }, |
6952 | { Bad_Opcode }, | |
6953 | { Bad_Opcode }, | |
6954 | { Bad_Opcode }, | |
6955 | { Bad_Opcode }, | |
6956 | { Bad_Opcode }, | |
6957 | { Bad_Opcode }, | |
6958 | { Bad_Opcode }, | |
f88c9eb0 | 6959 | /* 60 */ |
592d1631 L |
6960 | { Bad_Opcode }, |
6961 | { Bad_Opcode }, | |
6962 | { Bad_Opcode }, | |
6963 | { Bad_Opcode }, | |
6964 | { Bad_Opcode }, | |
6965 | { Bad_Opcode }, | |
6966 | { Bad_Opcode }, | |
6967 | { Bad_Opcode }, | |
f88c9eb0 | 6968 | /* 68 */ |
592d1631 L |
6969 | { Bad_Opcode }, |
6970 | { Bad_Opcode }, | |
6971 | { Bad_Opcode }, | |
6972 | { Bad_Opcode }, | |
6973 | { Bad_Opcode }, | |
6974 | { Bad_Opcode }, | |
6975 | { Bad_Opcode }, | |
6976 | { Bad_Opcode }, | |
f88c9eb0 | 6977 | /* 70 */ |
592d1631 L |
6978 | { Bad_Opcode }, |
6979 | { Bad_Opcode }, | |
6980 | { Bad_Opcode }, | |
6981 | { Bad_Opcode }, | |
6982 | { Bad_Opcode }, | |
6983 | { Bad_Opcode }, | |
6984 | { Bad_Opcode }, | |
6985 | { Bad_Opcode }, | |
f88c9eb0 | 6986 | /* 78 */ |
592d1631 L |
6987 | { Bad_Opcode }, |
6988 | { Bad_Opcode }, | |
6989 | { Bad_Opcode }, | |
6990 | { Bad_Opcode }, | |
6991 | { Bad_Opcode }, | |
6992 | { Bad_Opcode }, | |
6993 | { Bad_Opcode }, | |
6994 | { Bad_Opcode }, | |
f88c9eb0 SP |
6995 | /* 80 */ |
6996 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
6997 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 6998 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
6999 | { Bad_Opcode }, |
7000 | { Bad_Opcode }, | |
7001 | { Bad_Opcode }, | |
7002 | { Bad_Opcode }, | |
7003 | { Bad_Opcode }, | |
f88c9eb0 | 7004 | /* 88 */ |
592d1631 L |
7005 | { Bad_Opcode }, |
7006 | { Bad_Opcode }, | |
7007 | { Bad_Opcode }, | |
7008 | { Bad_Opcode }, | |
7009 | { Bad_Opcode }, | |
7010 | { Bad_Opcode }, | |
7011 | { Bad_Opcode }, | |
7012 | { Bad_Opcode }, | |
f88c9eb0 | 7013 | /* 90 */ |
592d1631 L |
7014 | { Bad_Opcode }, |
7015 | { Bad_Opcode }, | |
7016 | { Bad_Opcode }, | |
7017 | { Bad_Opcode }, | |
7018 | { Bad_Opcode }, | |
7019 | { Bad_Opcode }, | |
7020 | { Bad_Opcode }, | |
7021 | { Bad_Opcode }, | |
f88c9eb0 | 7022 | /* 98 */ |
592d1631 L |
7023 | { Bad_Opcode }, |
7024 | { Bad_Opcode }, | |
7025 | { Bad_Opcode }, | |
7026 | { Bad_Opcode }, | |
7027 | { Bad_Opcode }, | |
7028 | { Bad_Opcode }, | |
7029 | { Bad_Opcode }, | |
7030 | { Bad_Opcode }, | |
f88c9eb0 | 7031 | /* a0 */ |
592d1631 L |
7032 | { Bad_Opcode }, |
7033 | { Bad_Opcode }, | |
7034 | { Bad_Opcode }, | |
7035 | { Bad_Opcode }, | |
7036 | { Bad_Opcode }, | |
7037 | { Bad_Opcode }, | |
7038 | { Bad_Opcode }, | |
7039 | { Bad_Opcode }, | |
f88c9eb0 | 7040 | /* a8 */ |
592d1631 L |
7041 | { Bad_Opcode }, |
7042 | { Bad_Opcode }, | |
7043 | { Bad_Opcode }, | |
7044 | { Bad_Opcode }, | |
7045 | { Bad_Opcode }, | |
7046 | { Bad_Opcode }, | |
7047 | { Bad_Opcode }, | |
7048 | { Bad_Opcode }, | |
f88c9eb0 | 7049 | /* b0 */ |
592d1631 L |
7050 | { Bad_Opcode }, |
7051 | { Bad_Opcode }, | |
7052 | { Bad_Opcode }, | |
7053 | { Bad_Opcode }, | |
7054 | { Bad_Opcode }, | |
7055 | { Bad_Opcode }, | |
7056 | { Bad_Opcode }, | |
7057 | { Bad_Opcode }, | |
f88c9eb0 | 7058 | /* b8 */ |
592d1631 L |
7059 | { Bad_Opcode }, |
7060 | { Bad_Opcode }, | |
7061 | { Bad_Opcode }, | |
7062 | { Bad_Opcode }, | |
7063 | { Bad_Opcode }, | |
7064 | { Bad_Opcode }, | |
7065 | { Bad_Opcode }, | |
7066 | { Bad_Opcode }, | |
f88c9eb0 | 7067 | /* c0 */ |
592d1631 L |
7068 | { Bad_Opcode }, |
7069 | { Bad_Opcode }, | |
7070 | { Bad_Opcode }, | |
7071 | { Bad_Opcode }, | |
7072 | { Bad_Opcode }, | |
7073 | { Bad_Opcode }, | |
7074 | { Bad_Opcode }, | |
7075 | { Bad_Opcode }, | |
f88c9eb0 | 7076 | /* c8 */ |
a0046408 L |
7077 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7078 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7079 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7080 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7081 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7082 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 | 7083 | { Bad_Opcode }, |
48521003 | 7084 | { PREFIX_TABLE (PREFIX_0F38CF) }, |
f88c9eb0 | 7085 | /* d0 */ |
592d1631 L |
7086 | { Bad_Opcode }, |
7087 | { Bad_Opcode }, | |
7088 | { Bad_Opcode }, | |
7089 | { Bad_Opcode }, | |
7090 | { Bad_Opcode }, | |
7091 | { Bad_Opcode }, | |
7092 | { Bad_Opcode }, | |
7093 | { Bad_Opcode }, | |
f88c9eb0 | 7094 | /* d8 */ |
592d1631 L |
7095 | { Bad_Opcode }, |
7096 | { Bad_Opcode }, | |
7097 | { Bad_Opcode }, | |
f88c9eb0 SP |
7098 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7099 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7100 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7101 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7102 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7103 | /* e0 */ | |
592d1631 L |
7104 | { Bad_Opcode }, |
7105 | { Bad_Opcode }, | |
7106 | { Bad_Opcode }, | |
7107 | { Bad_Opcode }, | |
7108 | { Bad_Opcode }, | |
7109 | { Bad_Opcode }, | |
7110 | { Bad_Opcode }, | |
7111 | { Bad_Opcode }, | |
f88c9eb0 | 7112 | /* e8 */ |
592d1631 L |
7113 | { Bad_Opcode }, |
7114 | { Bad_Opcode }, | |
7115 | { Bad_Opcode }, | |
7116 | { Bad_Opcode }, | |
7117 | { Bad_Opcode }, | |
7118 | { Bad_Opcode }, | |
7119 | { Bad_Opcode }, | |
7120 | { Bad_Opcode }, | |
f88c9eb0 SP |
7121 | /* f0 */ |
7122 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7123 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7124 | { Bad_Opcode }, |
7125 | { Bad_Opcode }, | |
7126 | { Bad_Opcode }, | |
603555e5 | 7127 | { PREFIX_TABLE (PREFIX_0F38F5) }, |
e2e1fcde | 7128 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7129 | { Bad_Opcode }, |
f88c9eb0 | 7130 | /* f8 */ |
c0a30a9f L |
7131 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
7132 | { PREFIX_TABLE (PREFIX_0F38F9) }, | |
592d1631 L |
7133 | { Bad_Opcode }, |
7134 | { Bad_Opcode }, | |
7135 | { Bad_Opcode }, | |
7136 | { Bad_Opcode }, | |
7137 | { Bad_Opcode }, | |
7138 | { Bad_Opcode }, | |
f88c9eb0 SP |
7139 | }, |
7140 | /* THREE_BYTE_0F3A */ | |
7141 | { | |
7142 | /* 00 */ | |
592d1631 L |
7143 | { Bad_Opcode }, |
7144 | { Bad_Opcode }, | |
7145 | { Bad_Opcode }, | |
7146 | { Bad_Opcode }, | |
7147 | { Bad_Opcode }, | |
7148 | { Bad_Opcode }, | |
7149 | { Bad_Opcode }, | |
7150 | { Bad_Opcode }, | |
f88c9eb0 SP |
7151 | /* 08 */ |
7152 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7153 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7154 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7155 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7156 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7157 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7158 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7159 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7160 | /* 10 */ |
592d1631 L |
7161 | { Bad_Opcode }, |
7162 | { Bad_Opcode }, | |
7163 | { Bad_Opcode }, | |
7164 | { Bad_Opcode }, | |
f88c9eb0 SP |
7165 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7166 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7167 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7168 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7169 | /* 18 */ | |
592d1631 L |
7170 | { Bad_Opcode }, |
7171 | { Bad_Opcode }, | |
7172 | { Bad_Opcode }, | |
7173 | { Bad_Opcode }, | |
7174 | { Bad_Opcode }, | |
7175 | { Bad_Opcode }, | |
7176 | { Bad_Opcode }, | |
7177 | { Bad_Opcode }, | |
f88c9eb0 SP |
7178 | /* 20 */ |
7179 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7180 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7181 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7182 | { Bad_Opcode }, |
7183 | { Bad_Opcode }, | |
7184 | { Bad_Opcode }, | |
7185 | { Bad_Opcode }, | |
7186 | { Bad_Opcode }, | |
f88c9eb0 | 7187 | /* 28 */ |
592d1631 L |
7188 | { Bad_Opcode }, |
7189 | { Bad_Opcode }, | |
7190 | { Bad_Opcode }, | |
7191 | { Bad_Opcode }, | |
7192 | { Bad_Opcode }, | |
7193 | { Bad_Opcode }, | |
7194 | { Bad_Opcode }, | |
7195 | { Bad_Opcode }, | |
f88c9eb0 | 7196 | /* 30 */ |
592d1631 L |
7197 | { Bad_Opcode }, |
7198 | { Bad_Opcode }, | |
7199 | { Bad_Opcode }, | |
7200 | { Bad_Opcode }, | |
7201 | { Bad_Opcode }, | |
7202 | { Bad_Opcode }, | |
7203 | { Bad_Opcode }, | |
7204 | { Bad_Opcode }, | |
f88c9eb0 | 7205 | /* 38 */ |
592d1631 L |
7206 | { Bad_Opcode }, |
7207 | { Bad_Opcode }, | |
7208 | { Bad_Opcode }, | |
7209 | { Bad_Opcode }, | |
7210 | { Bad_Opcode }, | |
7211 | { Bad_Opcode }, | |
7212 | { Bad_Opcode }, | |
7213 | { Bad_Opcode }, | |
f88c9eb0 SP |
7214 | /* 40 */ |
7215 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7216 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7217 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7218 | { Bad_Opcode }, |
f88c9eb0 | 7219 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7220 | { Bad_Opcode }, |
7221 | { Bad_Opcode }, | |
7222 | { Bad_Opcode }, | |
f88c9eb0 | 7223 | /* 48 */ |
592d1631 L |
7224 | { Bad_Opcode }, |
7225 | { Bad_Opcode }, | |
7226 | { Bad_Opcode }, | |
7227 | { Bad_Opcode }, | |
7228 | { Bad_Opcode }, | |
7229 | { Bad_Opcode }, | |
7230 | { Bad_Opcode }, | |
7231 | { Bad_Opcode }, | |
f88c9eb0 | 7232 | /* 50 */ |
592d1631 L |
7233 | { Bad_Opcode }, |
7234 | { Bad_Opcode }, | |
7235 | { Bad_Opcode }, | |
7236 | { Bad_Opcode }, | |
7237 | { Bad_Opcode }, | |
7238 | { Bad_Opcode }, | |
7239 | { Bad_Opcode }, | |
7240 | { Bad_Opcode }, | |
f88c9eb0 | 7241 | /* 58 */ |
592d1631 L |
7242 | { Bad_Opcode }, |
7243 | { Bad_Opcode }, | |
7244 | { Bad_Opcode }, | |
7245 | { Bad_Opcode }, | |
7246 | { Bad_Opcode }, | |
7247 | { Bad_Opcode }, | |
7248 | { Bad_Opcode }, | |
7249 | { Bad_Opcode }, | |
f88c9eb0 SP |
7250 | /* 60 */ |
7251 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7252 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7253 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7254 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7255 | { Bad_Opcode }, |
7256 | { Bad_Opcode }, | |
7257 | { Bad_Opcode }, | |
7258 | { Bad_Opcode }, | |
f88c9eb0 | 7259 | /* 68 */ |
592d1631 L |
7260 | { Bad_Opcode }, |
7261 | { Bad_Opcode }, | |
7262 | { Bad_Opcode }, | |
7263 | { Bad_Opcode }, | |
7264 | { Bad_Opcode }, | |
7265 | { Bad_Opcode }, | |
7266 | { Bad_Opcode }, | |
7267 | { Bad_Opcode }, | |
f88c9eb0 | 7268 | /* 70 */ |
592d1631 L |
7269 | { Bad_Opcode }, |
7270 | { Bad_Opcode }, | |
7271 | { Bad_Opcode }, | |
7272 | { Bad_Opcode }, | |
7273 | { Bad_Opcode }, | |
7274 | { Bad_Opcode }, | |
7275 | { Bad_Opcode }, | |
7276 | { Bad_Opcode }, | |
f88c9eb0 | 7277 | /* 78 */ |
592d1631 L |
7278 | { Bad_Opcode }, |
7279 | { Bad_Opcode }, | |
7280 | { Bad_Opcode }, | |
7281 | { Bad_Opcode }, | |
7282 | { Bad_Opcode }, | |
7283 | { Bad_Opcode }, | |
7284 | { Bad_Opcode }, | |
7285 | { Bad_Opcode }, | |
f88c9eb0 | 7286 | /* 80 */ |
592d1631 L |
7287 | { Bad_Opcode }, |
7288 | { Bad_Opcode }, | |
7289 | { Bad_Opcode }, | |
7290 | { Bad_Opcode }, | |
7291 | { Bad_Opcode }, | |
7292 | { Bad_Opcode }, | |
7293 | { Bad_Opcode }, | |
7294 | { Bad_Opcode }, | |
f88c9eb0 | 7295 | /* 88 */ |
592d1631 L |
7296 | { Bad_Opcode }, |
7297 | { Bad_Opcode }, | |
7298 | { Bad_Opcode }, | |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
7301 | { Bad_Opcode }, | |
7302 | { Bad_Opcode }, | |
7303 | { Bad_Opcode }, | |
f88c9eb0 | 7304 | /* 90 */ |
592d1631 L |
7305 | { Bad_Opcode }, |
7306 | { Bad_Opcode }, | |
7307 | { Bad_Opcode }, | |
7308 | { Bad_Opcode }, | |
7309 | { Bad_Opcode }, | |
7310 | { Bad_Opcode }, | |
7311 | { Bad_Opcode }, | |
7312 | { Bad_Opcode }, | |
f88c9eb0 | 7313 | /* 98 */ |
592d1631 L |
7314 | { Bad_Opcode }, |
7315 | { Bad_Opcode }, | |
7316 | { Bad_Opcode }, | |
7317 | { Bad_Opcode }, | |
7318 | { Bad_Opcode }, | |
7319 | { Bad_Opcode }, | |
7320 | { Bad_Opcode }, | |
7321 | { Bad_Opcode }, | |
f88c9eb0 | 7322 | /* a0 */ |
592d1631 L |
7323 | { Bad_Opcode }, |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
7326 | { Bad_Opcode }, | |
7327 | { Bad_Opcode }, | |
7328 | { Bad_Opcode }, | |
7329 | { Bad_Opcode }, | |
7330 | { Bad_Opcode }, | |
f88c9eb0 | 7331 | /* a8 */ |
592d1631 L |
7332 | { Bad_Opcode }, |
7333 | { Bad_Opcode }, | |
7334 | { Bad_Opcode }, | |
7335 | { Bad_Opcode }, | |
7336 | { Bad_Opcode }, | |
7337 | { Bad_Opcode }, | |
7338 | { Bad_Opcode }, | |
7339 | { Bad_Opcode }, | |
f88c9eb0 | 7340 | /* b0 */ |
592d1631 L |
7341 | { Bad_Opcode }, |
7342 | { Bad_Opcode }, | |
7343 | { Bad_Opcode }, | |
7344 | { Bad_Opcode }, | |
7345 | { Bad_Opcode }, | |
7346 | { Bad_Opcode }, | |
7347 | { Bad_Opcode }, | |
7348 | { Bad_Opcode }, | |
f88c9eb0 | 7349 | /* b8 */ |
592d1631 L |
7350 | { Bad_Opcode }, |
7351 | { Bad_Opcode }, | |
7352 | { Bad_Opcode }, | |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
7355 | { Bad_Opcode }, | |
7356 | { Bad_Opcode }, | |
7357 | { Bad_Opcode }, | |
f88c9eb0 | 7358 | /* c0 */ |
592d1631 L |
7359 | { Bad_Opcode }, |
7360 | { Bad_Opcode }, | |
7361 | { Bad_Opcode }, | |
7362 | { Bad_Opcode }, | |
7363 | { Bad_Opcode }, | |
7364 | { Bad_Opcode }, | |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
f88c9eb0 | 7367 | /* c8 */ |
592d1631 L |
7368 | { Bad_Opcode }, |
7369 | { Bad_Opcode }, | |
7370 | { Bad_Opcode }, | |
7371 | { Bad_Opcode }, | |
a0046408 | 7372 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 | 7373 | { Bad_Opcode }, |
48521003 IT |
7374 | { PREFIX_TABLE (PREFIX_0F3ACE) }, |
7375 | { PREFIX_TABLE (PREFIX_0F3ACF) }, | |
f88c9eb0 | 7376 | /* d0 */ |
592d1631 L |
7377 | { Bad_Opcode }, |
7378 | { Bad_Opcode }, | |
7379 | { Bad_Opcode }, | |
7380 | { Bad_Opcode }, | |
7381 | { Bad_Opcode }, | |
7382 | { Bad_Opcode }, | |
7383 | { Bad_Opcode }, | |
7384 | { Bad_Opcode }, | |
f88c9eb0 | 7385 | /* d8 */ |
592d1631 L |
7386 | { Bad_Opcode }, |
7387 | { Bad_Opcode }, | |
7388 | { Bad_Opcode }, | |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
7391 | { Bad_Opcode }, | |
7392 | { Bad_Opcode }, | |
f88c9eb0 SP |
7393 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7394 | /* e0 */ | |
592d1631 L |
7395 | { Bad_Opcode }, |
7396 | { Bad_Opcode }, | |
7397 | { Bad_Opcode }, | |
7398 | { Bad_Opcode }, | |
7399 | { Bad_Opcode }, | |
592d1631 L |
7400 | { Bad_Opcode }, |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
85f10a01 | 7403 | /* e8 */ |
592d1631 L |
7404 | { Bad_Opcode }, |
7405 | { Bad_Opcode }, | |
7406 | { Bad_Opcode }, | |
7407 | { Bad_Opcode }, | |
7408 | { Bad_Opcode }, | |
7409 | { Bad_Opcode }, | |
7410 | { Bad_Opcode }, | |
7411 | { Bad_Opcode }, | |
85f10a01 | 7412 | /* f0 */ |
592d1631 L |
7413 | { Bad_Opcode }, |
7414 | { Bad_Opcode }, | |
7415 | { Bad_Opcode }, | |
7416 | { Bad_Opcode }, | |
7417 | { Bad_Opcode }, | |
7418 | { Bad_Opcode }, | |
7419 | { Bad_Opcode }, | |
7420 | { Bad_Opcode }, | |
85f10a01 | 7421 | /* f8 */ |
592d1631 L |
7422 | { Bad_Opcode }, |
7423 | { Bad_Opcode }, | |
7424 | { Bad_Opcode }, | |
7425 | { Bad_Opcode }, | |
7426 | { Bad_Opcode }, | |
7427 | { Bad_Opcode }, | |
7428 | { Bad_Opcode }, | |
7429 | { Bad_Opcode }, | |
85f10a01 | 7430 | }, |
f88c9eb0 SP |
7431 | }; |
7432 | ||
7433 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7434 | /* XOP_08 */ |
85f10a01 MM |
7435 | { |
7436 | /* 00 */ | |
592d1631 L |
7437 | { Bad_Opcode }, |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
7440 | { Bad_Opcode }, | |
7441 | { Bad_Opcode }, | |
7442 | { Bad_Opcode }, | |
7443 | { Bad_Opcode }, | |
7444 | { Bad_Opcode }, | |
85f10a01 | 7445 | /* 08 */ |
592d1631 L |
7446 | { Bad_Opcode }, |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
7449 | { Bad_Opcode }, | |
7450 | { Bad_Opcode }, | |
7451 | { Bad_Opcode }, | |
7452 | { Bad_Opcode }, | |
7453 | { Bad_Opcode }, | |
85f10a01 | 7454 | /* 10 */ |
3929df09 | 7455 | { Bad_Opcode }, |
592d1631 L |
7456 | { Bad_Opcode }, |
7457 | { Bad_Opcode }, | |
7458 | { Bad_Opcode }, | |
7459 | { Bad_Opcode }, | |
7460 | { Bad_Opcode }, | |
7461 | { Bad_Opcode }, | |
7462 | { Bad_Opcode }, | |
85f10a01 | 7463 | /* 18 */ |
592d1631 L |
7464 | { Bad_Opcode }, |
7465 | { Bad_Opcode }, | |
7466 | { Bad_Opcode }, | |
7467 | { Bad_Opcode }, | |
7468 | { Bad_Opcode }, | |
7469 | { Bad_Opcode }, | |
7470 | { Bad_Opcode }, | |
7471 | { Bad_Opcode }, | |
85f10a01 | 7472 | /* 20 */ |
592d1631 L |
7473 | { Bad_Opcode }, |
7474 | { Bad_Opcode }, | |
7475 | { Bad_Opcode }, | |
7476 | { Bad_Opcode }, | |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
85f10a01 | 7481 | /* 28 */ |
592d1631 L |
7482 | { Bad_Opcode }, |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
7485 | { Bad_Opcode }, | |
7486 | { Bad_Opcode }, | |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
7489 | { Bad_Opcode }, | |
c0f3af97 | 7490 | /* 30 */ |
592d1631 L |
7491 | { Bad_Opcode }, |
7492 | { Bad_Opcode }, | |
7493 | { Bad_Opcode }, | |
7494 | { Bad_Opcode }, | |
7495 | { Bad_Opcode }, | |
7496 | { Bad_Opcode }, | |
7497 | { Bad_Opcode }, | |
7498 | { Bad_Opcode }, | |
c0f3af97 | 7499 | /* 38 */ |
592d1631 L |
7500 | { Bad_Opcode }, |
7501 | { Bad_Opcode }, | |
7502 | { Bad_Opcode }, | |
7503 | { Bad_Opcode }, | |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
7507 | { Bad_Opcode }, | |
c0f3af97 | 7508 | /* 40 */ |
592d1631 L |
7509 | { Bad_Opcode }, |
7510 | { Bad_Opcode }, | |
7511 | { Bad_Opcode }, | |
7512 | { Bad_Opcode }, | |
7513 | { Bad_Opcode }, | |
7514 | { Bad_Opcode }, | |
7515 | { Bad_Opcode }, | |
7516 | { Bad_Opcode }, | |
85f10a01 | 7517 | /* 48 */ |
592d1631 L |
7518 | { Bad_Opcode }, |
7519 | { Bad_Opcode }, | |
7520 | { Bad_Opcode }, | |
7521 | { Bad_Opcode }, | |
7522 | { Bad_Opcode }, | |
7523 | { Bad_Opcode }, | |
7524 | { Bad_Opcode }, | |
7525 | { Bad_Opcode }, | |
c0f3af97 | 7526 | /* 50 */ |
592d1631 L |
7527 | { Bad_Opcode }, |
7528 | { Bad_Opcode }, | |
7529 | { Bad_Opcode }, | |
7530 | { Bad_Opcode }, | |
7531 | { Bad_Opcode }, | |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
7534 | { Bad_Opcode }, | |
85f10a01 | 7535 | /* 58 */ |
592d1631 L |
7536 | { Bad_Opcode }, |
7537 | { Bad_Opcode }, | |
7538 | { Bad_Opcode }, | |
7539 | { Bad_Opcode }, | |
7540 | { Bad_Opcode }, | |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
c1e679ec | 7544 | /* 60 */ |
592d1631 L |
7545 | { Bad_Opcode }, |
7546 | { Bad_Opcode }, | |
7547 | { Bad_Opcode }, | |
7548 | { Bad_Opcode }, | |
7549 | { Bad_Opcode }, | |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
7552 | { Bad_Opcode }, | |
c0f3af97 | 7553 | /* 68 */ |
592d1631 L |
7554 | { Bad_Opcode }, |
7555 | { Bad_Opcode }, | |
7556 | { Bad_Opcode }, | |
7557 | { Bad_Opcode }, | |
7558 | { Bad_Opcode }, | |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
7561 | { Bad_Opcode }, | |
85f10a01 | 7562 | /* 70 */ |
592d1631 L |
7563 | { Bad_Opcode }, |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
7566 | { Bad_Opcode }, | |
7567 | { Bad_Opcode }, | |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
85f10a01 | 7571 | /* 78 */ |
592d1631 L |
7572 | { Bad_Opcode }, |
7573 | { Bad_Opcode }, | |
7574 | { Bad_Opcode }, | |
7575 | { Bad_Opcode }, | |
7576 | { Bad_Opcode }, | |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
85f10a01 | 7580 | /* 80 */ |
592d1631 L |
7581 | { Bad_Opcode }, |
7582 | { Bad_Opcode }, | |
7583 | { Bad_Opcode }, | |
7584 | { Bad_Opcode }, | |
7585 | { Bad_Opcode }, | |
3a2430e0 JB |
7586 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7587 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7588 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7589 | /* 88 */ |
592d1631 L |
7590 | { Bad_Opcode }, |
7591 | { Bad_Opcode }, | |
7592 | { Bad_Opcode }, | |
7593 | { Bad_Opcode }, | |
7594 | { Bad_Opcode }, | |
7595 | { Bad_Opcode }, | |
3a2430e0 JB |
7596 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7597 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7598 | /* 90 */ |
592d1631 L |
7599 | { Bad_Opcode }, |
7600 | { Bad_Opcode }, | |
7601 | { Bad_Opcode }, | |
7602 | { Bad_Opcode }, | |
7603 | { Bad_Opcode }, | |
3a2430e0 JB |
7604 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7605 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7606 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7607 | /* 98 */ |
592d1631 L |
7608 | { Bad_Opcode }, |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
7611 | { Bad_Opcode }, | |
7612 | { Bad_Opcode }, | |
7613 | { Bad_Opcode }, | |
3a2430e0 JB |
7614 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7615 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7616 | /* a0 */ |
592d1631 L |
7617 | { Bad_Opcode }, |
7618 | { Bad_Opcode }, | |
3a2430e0 JB |
7619 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7620 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
592d1631 L |
7621 | { Bad_Opcode }, |
7622 | { Bad_Opcode }, | |
3a2430e0 | 7623 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7624 | { Bad_Opcode }, |
5dd85c99 | 7625 | /* a8 */ |
592d1631 L |
7626 | { Bad_Opcode }, |
7627 | { Bad_Opcode }, | |
7628 | { Bad_Opcode }, | |
7629 | { Bad_Opcode }, | |
7630 | { Bad_Opcode }, | |
7631 | { Bad_Opcode }, | |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
5dd85c99 | 7634 | /* b0 */ |
592d1631 L |
7635 | { Bad_Opcode }, |
7636 | { Bad_Opcode }, | |
7637 | { Bad_Opcode }, | |
7638 | { Bad_Opcode }, | |
7639 | { Bad_Opcode }, | |
7640 | { Bad_Opcode }, | |
3a2430e0 | 7641 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7642 | { Bad_Opcode }, |
5dd85c99 | 7643 | /* b8 */ |
592d1631 L |
7644 | { Bad_Opcode }, |
7645 | { Bad_Opcode }, | |
7646 | { Bad_Opcode }, | |
7647 | { Bad_Opcode }, | |
7648 | { Bad_Opcode }, | |
7649 | { Bad_Opcode }, | |
7650 | { Bad_Opcode }, | |
7651 | { Bad_Opcode }, | |
5dd85c99 | 7652 | /* c0 */ |
bf890a93 IT |
7653 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7654 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
7655 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
7656 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
7657 | { Bad_Opcode }, |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
5dd85c99 | 7661 | /* c8 */ |
592d1631 L |
7662 | { Bad_Opcode }, |
7663 | { Bad_Opcode }, | |
7664 | { Bad_Opcode }, | |
7665 | { Bad_Opcode }, | |
ff688e1f L |
7666 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7667 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7668 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7669 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7670 | /* d0 */ |
592d1631 L |
7671 | { Bad_Opcode }, |
7672 | { Bad_Opcode }, | |
7673 | { Bad_Opcode }, | |
7674 | { Bad_Opcode }, | |
7675 | { Bad_Opcode }, | |
7676 | { Bad_Opcode }, | |
7677 | { Bad_Opcode }, | |
7678 | { Bad_Opcode }, | |
5dd85c99 | 7679 | /* d8 */ |
592d1631 L |
7680 | { Bad_Opcode }, |
7681 | { Bad_Opcode }, | |
7682 | { Bad_Opcode }, | |
7683 | { Bad_Opcode }, | |
7684 | { Bad_Opcode }, | |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
5dd85c99 | 7688 | /* e0 */ |
592d1631 L |
7689 | { Bad_Opcode }, |
7690 | { Bad_Opcode }, | |
7691 | { Bad_Opcode }, | |
7692 | { Bad_Opcode }, | |
7693 | { Bad_Opcode }, | |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
5dd85c99 | 7697 | /* e8 */ |
592d1631 L |
7698 | { Bad_Opcode }, |
7699 | { Bad_Opcode }, | |
7700 | { Bad_Opcode }, | |
7701 | { Bad_Opcode }, | |
ff688e1f L |
7702 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7703 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7704 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7705 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7706 | /* f0 */ |
592d1631 L |
7707 | { Bad_Opcode }, |
7708 | { Bad_Opcode }, | |
7709 | { Bad_Opcode }, | |
7710 | { Bad_Opcode }, | |
7711 | { Bad_Opcode }, | |
7712 | { Bad_Opcode }, | |
7713 | { Bad_Opcode }, | |
7714 | { Bad_Opcode }, | |
5dd85c99 | 7715 | /* f8 */ |
592d1631 L |
7716 | { Bad_Opcode }, |
7717 | { Bad_Opcode }, | |
7718 | { Bad_Opcode }, | |
7719 | { Bad_Opcode }, | |
7720 | { Bad_Opcode }, | |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
5dd85c99 SP |
7724 | }, |
7725 | /* XOP_09 */ | |
7726 | { | |
7727 | /* 00 */ | |
592d1631 | 7728 | { Bad_Opcode }, |
2a2a0f38 QN |
7729 | { REG_TABLE (REG_XOP_TBM_01) }, |
7730 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
7731 | { Bad_Opcode }, |
7732 | { Bad_Opcode }, | |
7733 | { Bad_Opcode }, | |
7734 | { Bad_Opcode }, | |
7735 | { Bad_Opcode }, | |
5dd85c99 | 7736 | /* 08 */ |
592d1631 L |
7737 | { Bad_Opcode }, |
7738 | { Bad_Opcode }, | |
7739 | { Bad_Opcode }, | |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
7743 | { Bad_Opcode }, | |
7744 | { Bad_Opcode }, | |
5dd85c99 | 7745 | /* 10 */ |
592d1631 L |
7746 | { Bad_Opcode }, |
7747 | { Bad_Opcode }, | |
5dd85c99 | 7748 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
7749 | { Bad_Opcode }, |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
7753 | { Bad_Opcode }, | |
5dd85c99 | 7754 | /* 18 */ |
592d1631 L |
7755 | { Bad_Opcode }, |
7756 | { Bad_Opcode }, | |
7757 | { Bad_Opcode }, | |
7758 | { Bad_Opcode }, | |
7759 | { Bad_Opcode }, | |
7760 | { Bad_Opcode }, | |
7761 | { Bad_Opcode }, | |
7762 | { Bad_Opcode }, | |
5dd85c99 | 7763 | /* 20 */ |
592d1631 L |
7764 | { Bad_Opcode }, |
7765 | { Bad_Opcode }, | |
7766 | { Bad_Opcode }, | |
7767 | { Bad_Opcode }, | |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
7771 | { Bad_Opcode }, | |
5dd85c99 | 7772 | /* 28 */ |
592d1631 L |
7773 | { Bad_Opcode }, |
7774 | { Bad_Opcode }, | |
7775 | { Bad_Opcode }, | |
7776 | { Bad_Opcode }, | |
7777 | { Bad_Opcode }, | |
7778 | { Bad_Opcode }, | |
7779 | { Bad_Opcode }, | |
7780 | { Bad_Opcode }, | |
5dd85c99 | 7781 | /* 30 */ |
592d1631 L |
7782 | { Bad_Opcode }, |
7783 | { Bad_Opcode }, | |
7784 | { Bad_Opcode }, | |
7785 | { Bad_Opcode }, | |
7786 | { Bad_Opcode }, | |
7787 | { Bad_Opcode }, | |
7788 | { Bad_Opcode }, | |
7789 | { Bad_Opcode }, | |
5dd85c99 | 7790 | /* 38 */ |
592d1631 L |
7791 | { Bad_Opcode }, |
7792 | { Bad_Opcode }, | |
7793 | { Bad_Opcode }, | |
7794 | { Bad_Opcode }, | |
7795 | { Bad_Opcode }, | |
7796 | { Bad_Opcode }, | |
7797 | { Bad_Opcode }, | |
7798 | { Bad_Opcode }, | |
5dd85c99 | 7799 | /* 40 */ |
592d1631 L |
7800 | { Bad_Opcode }, |
7801 | { Bad_Opcode }, | |
7802 | { Bad_Opcode }, | |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
7805 | { Bad_Opcode }, | |
7806 | { Bad_Opcode }, | |
7807 | { Bad_Opcode }, | |
5dd85c99 | 7808 | /* 48 */ |
592d1631 L |
7809 | { Bad_Opcode }, |
7810 | { Bad_Opcode }, | |
7811 | { Bad_Opcode }, | |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
7816 | { Bad_Opcode }, | |
5dd85c99 | 7817 | /* 50 */ |
592d1631 L |
7818 | { Bad_Opcode }, |
7819 | { Bad_Opcode }, | |
7820 | { Bad_Opcode }, | |
7821 | { Bad_Opcode }, | |
7822 | { Bad_Opcode }, | |
7823 | { Bad_Opcode }, | |
7824 | { Bad_Opcode }, | |
7825 | { Bad_Opcode }, | |
5dd85c99 | 7826 | /* 58 */ |
592d1631 L |
7827 | { Bad_Opcode }, |
7828 | { Bad_Opcode }, | |
7829 | { Bad_Opcode }, | |
7830 | { Bad_Opcode }, | |
7831 | { Bad_Opcode }, | |
7832 | { Bad_Opcode }, | |
7833 | { Bad_Opcode }, | |
7834 | { Bad_Opcode }, | |
5dd85c99 | 7835 | /* 60 */ |
592d1631 L |
7836 | { Bad_Opcode }, |
7837 | { Bad_Opcode }, | |
7838 | { Bad_Opcode }, | |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
7841 | { Bad_Opcode }, | |
7842 | { Bad_Opcode }, | |
7843 | { Bad_Opcode }, | |
5dd85c99 | 7844 | /* 68 */ |
592d1631 L |
7845 | { Bad_Opcode }, |
7846 | { Bad_Opcode }, | |
7847 | { Bad_Opcode }, | |
7848 | { Bad_Opcode }, | |
7849 | { Bad_Opcode }, | |
7850 | { Bad_Opcode }, | |
7851 | { Bad_Opcode }, | |
7852 | { Bad_Opcode }, | |
5dd85c99 | 7853 | /* 70 */ |
592d1631 L |
7854 | { Bad_Opcode }, |
7855 | { Bad_Opcode }, | |
7856 | { Bad_Opcode }, | |
7857 | { Bad_Opcode }, | |
7858 | { Bad_Opcode }, | |
7859 | { Bad_Opcode }, | |
7860 | { Bad_Opcode }, | |
7861 | { Bad_Opcode }, | |
5dd85c99 | 7862 | /* 78 */ |
592d1631 L |
7863 | { Bad_Opcode }, |
7864 | { Bad_Opcode }, | |
7865 | { Bad_Opcode }, | |
7866 | { Bad_Opcode }, | |
7867 | { Bad_Opcode }, | |
7868 | { Bad_Opcode }, | |
7869 | { Bad_Opcode }, | |
7870 | { Bad_Opcode }, | |
5dd85c99 | 7871 | /* 80 */ |
592a252b L |
7872 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
7873 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
bf890a93 IT |
7874 | { "vfrczss", { XM, EXd }, 0 }, |
7875 | { "vfrczsd", { XM, EXq }, 0 }, | |
592d1631 L |
7876 | { Bad_Opcode }, |
7877 | { Bad_Opcode }, | |
7878 | { Bad_Opcode }, | |
7879 | { Bad_Opcode }, | |
5dd85c99 | 7880 | /* 88 */ |
592d1631 L |
7881 | { Bad_Opcode }, |
7882 | { Bad_Opcode }, | |
7883 | { Bad_Opcode }, | |
7884 | { Bad_Opcode }, | |
7885 | { Bad_Opcode }, | |
7886 | { Bad_Opcode }, | |
7887 | { Bad_Opcode }, | |
7888 | { Bad_Opcode }, | |
5dd85c99 | 7889 | /* 90 */ |
bf890a93 IT |
7890 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7891 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7892 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7893 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7894 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7895 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7896 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7897 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 7898 | /* 98 */ |
bf890a93 IT |
7899 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7900 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7901 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7902 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
7903 | { Bad_Opcode }, |
7904 | { Bad_Opcode }, | |
7905 | { Bad_Opcode }, | |
7906 | { Bad_Opcode }, | |
5dd85c99 | 7907 | /* a0 */ |
592d1631 L |
7908 | { Bad_Opcode }, |
7909 | { Bad_Opcode }, | |
7910 | { Bad_Opcode }, | |
7911 | { Bad_Opcode }, | |
7912 | { Bad_Opcode }, | |
7913 | { Bad_Opcode }, | |
7914 | { Bad_Opcode }, | |
7915 | { Bad_Opcode }, | |
5dd85c99 | 7916 | /* a8 */ |
592d1631 L |
7917 | { Bad_Opcode }, |
7918 | { Bad_Opcode }, | |
7919 | { Bad_Opcode }, | |
7920 | { Bad_Opcode }, | |
7921 | { Bad_Opcode }, | |
7922 | { Bad_Opcode }, | |
7923 | { Bad_Opcode }, | |
7924 | { Bad_Opcode }, | |
5dd85c99 | 7925 | /* b0 */ |
592d1631 L |
7926 | { Bad_Opcode }, |
7927 | { Bad_Opcode }, | |
7928 | { Bad_Opcode }, | |
7929 | { Bad_Opcode }, | |
7930 | { Bad_Opcode }, | |
7931 | { Bad_Opcode }, | |
7932 | { Bad_Opcode }, | |
7933 | { Bad_Opcode }, | |
5dd85c99 | 7934 | /* b8 */ |
592d1631 L |
7935 | { Bad_Opcode }, |
7936 | { Bad_Opcode }, | |
7937 | { Bad_Opcode }, | |
7938 | { Bad_Opcode }, | |
7939 | { Bad_Opcode }, | |
7940 | { Bad_Opcode }, | |
7941 | { Bad_Opcode }, | |
7942 | { Bad_Opcode }, | |
5dd85c99 | 7943 | /* c0 */ |
592d1631 | 7944 | { Bad_Opcode }, |
bf890a93 IT |
7945 | { "vphaddbw", { XM, EXxmm }, 0 }, |
7946 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
7947 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
7948 | { Bad_Opcode }, |
7949 | { Bad_Opcode }, | |
bf890a93 IT |
7950 | { "vphaddwd", { XM, EXxmm }, 0 }, |
7951 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 7952 | /* c8 */ |
592d1631 L |
7953 | { Bad_Opcode }, |
7954 | { Bad_Opcode }, | |
7955 | { Bad_Opcode }, | |
bf890a93 | 7956 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
7957 | { Bad_Opcode }, |
7958 | { Bad_Opcode }, | |
7959 | { Bad_Opcode }, | |
7960 | { Bad_Opcode }, | |
5dd85c99 | 7961 | /* d0 */ |
592d1631 | 7962 | { Bad_Opcode }, |
bf890a93 IT |
7963 | { "vphaddubw", { XM, EXxmm }, 0 }, |
7964 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
7965 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
7966 | { Bad_Opcode }, |
7967 | { Bad_Opcode }, | |
bf890a93 IT |
7968 | { "vphadduwd", { XM, EXxmm }, 0 }, |
7969 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 7970 | /* d8 */ |
592d1631 L |
7971 | { Bad_Opcode }, |
7972 | { Bad_Opcode }, | |
7973 | { Bad_Opcode }, | |
bf890a93 | 7974 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
7975 | { Bad_Opcode }, |
7976 | { Bad_Opcode }, | |
7977 | { Bad_Opcode }, | |
7978 | { Bad_Opcode }, | |
5dd85c99 | 7979 | /* e0 */ |
592d1631 | 7980 | { Bad_Opcode }, |
bf890a93 IT |
7981 | { "vphsubbw", { XM, EXxmm }, 0 }, |
7982 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
7983 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
7984 | { Bad_Opcode }, |
7985 | { Bad_Opcode }, | |
7986 | { Bad_Opcode }, | |
7987 | { Bad_Opcode }, | |
4e7d34a6 | 7988 | /* e8 */ |
592d1631 L |
7989 | { Bad_Opcode }, |
7990 | { Bad_Opcode }, | |
7991 | { Bad_Opcode }, | |
7992 | { Bad_Opcode }, | |
7993 | { Bad_Opcode }, | |
7994 | { Bad_Opcode }, | |
7995 | { Bad_Opcode }, | |
7996 | { Bad_Opcode }, | |
4e7d34a6 | 7997 | /* f0 */ |
592d1631 L |
7998 | { Bad_Opcode }, |
7999 | { Bad_Opcode }, | |
8000 | { Bad_Opcode }, | |
8001 | { Bad_Opcode }, | |
8002 | { Bad_Opcode }, | |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
4e7d34a6 | 8006 | /* f8 */ |
592d1631 L |
8007 | { Bad_Opcode }, |
8008 | { Bad_Opcode }, | |
8009 | { Bad_Opcode }, | |
8010 | { Bad_Opcode }, | |
8011 | { Bad_Opcode }, | |
8012 | { Bad_Opcode }, | |
8013 | { Bad_Opcode }, | |
8014 | { Bad_Opcode }, | |
4e7d34a6 | 8015 | }, |
f88c9eb0 | 8016 | /* XOP_0A */ |
4e7d34a6 L |
8017 | { |
8018 | /* 00 */ | |
592d1631 L |
8019 | { Bad_Opcode }, |
8020 | { Bad_Opcode }, | |
8021 | { Bad_Opcode }, | |
8022 | { Bad_Opcode }, | |
8023 | { Bad_Opcode }, | |
8024 | { Bad_Opcode }, | |
8025 | { Bad_Opcode }, | |
8026 | { Bad_Opcode }, | |
4e7d34a6 | 8027 | /* 08 */ |
592d1631 L |
8028 | { Bad_Opcode }, |
8029 | { Bad_Opcode }, | |
8030 | { Bad_Opcode }, | |
8031 | { Bad_Opcode }, | |
8032 | { Bad_Opcode }, | |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
8035 | { Bad_Opcode }, | |
4e7d34a6 | 8036 | /* 10 */ |
c1dc7af5 | 8037 | { "bextrS", { Gdq, Edq, Id }, 0 }, |
592d1631 | 8038 | { Bad_Opcode }, |
f88c9eb0 | 8039 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8040 | { Bad_Opcode }, |
8041 | { Bad_Opcode }, | |
8042 | { Bad_Opcode }, | |
8043 | { Bad_Opcode }, | |
8044 | { Bad_Opcode }, | |
4e7d34a6 | 8045 | /* 18 */ |
592d1631 L |
8046 | { Bad_Opcode }, |
8047 | { Bad_Opcode }, | |
8048 | { Bad_Opcode }, | |
8049 | { Bad_Opcode }, | |
8050 | { Bad_Opcode }, | |
8051 | { Bad_Opcode }, | |
8052 | { Bad_Opcode }, | |
8053 | { Bad_Opcode }, | |
4e7d34a6 | 8054 | /* 20 */ |
592d1631 L |
8055 | { Bad_Opcode }, |
8056 | { Bad_Opcode }, | |
8057 | { Bad_Opcode }, | |
8058 | { Bad_Opcode }, | |
8059 | { Bad_Opcode }, | |
8060 | { Bad_Opcode }, | |
8061 | { Bad_Opcode }, | |
8062 | { Bad_Opcode }, | |
4e7d34a6 | 8063 | /* 28 */ |
592d1631 L |
8064 | { Bad_Opcode }, |
8065 | { Bad_Opcode }, | |
8066 | { Bad_Opcode }, | |
8067 | { Bad_Opcode }, | |
8068 | { Bad_Opcode }, | |
8069 | { Bad_Opcode }, | |
8070 | { Bad_Opcode }, | |
8071 | { Bad_Opcode }, | |
4e7d34a6 | 8072 | /* 30 */ |
592d1631 L |
8073 | { Bad_Opcode }, |
8074 | { Bad_Opcode }, | |
8075 | { Bad_Opcode }, | |
8076 | { Bad_Opcode }, | |
8077 | { Bad_Opcode }, | |
8078 | { Bad_Opcode }, | |
8079 | { Bad_Opcode }, | |
8080 | { Bad_Opcode }, | |
c0f3af97 | 8081 | /* 38 */ |
592d1631 L |
8082 | { Bad_Opcode }, |
8083 | { Bad_Opcode }, | |
8084 | { Bad_Opcode }, | |
8085 | { Bad_Opcode }, | |
8086 | { Bad_Opcode }, | |
8087 | { Bad_Opcode }, | |
8088 | { Bad_Opcode }, | |
8089 | { Bad_Opcode }, | |
c0f3af97 | 8090 | /* 40 */ |
592d1631 L |
8091 | { Bad_Opcode }, |
8092 | { Bad_Opcode }, | |
8093 | { Bad_Opcode }, | |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
8096 | { Bad_Opcode }, | |
8097 | { Bad_Opcode }, | |
8098 | { Bad_Opcode }, | |
c1e679ec | 8099 | /* 48 */ |
592d1631 L |
8100 | { Bad_Opcode }, |
8101 | { Bad_Opcode }, | |
8102 | { Bad_Opcode }, | |
8103 | { Bad_Opcode }, | |
8104 | { Bad_Opcode }, | |
8105 | { Bad_Opcode }, | |
8106 | { Bad_Opcode }, | |
8107 | { Bad_Opcode }, | |
c1e679ec | 8108 | /* 50 */ |
592d1631 L |
8109 | { Bad_Opcode }, |
8110 | { Bad_Opcode }, | |
8111 | { Bad_Opcode }, | |
8112 | { Bad_Opcode }, | |
8113 | { Bad_Opcode }, | |
8114 | { Bad_Opcode }, | |
8115 | { Bad_Opcode }, | |
8116 | { Bad_Opcode }, | |
4e7d34a6 | 8117 | /* 58 */ |
592d1631 L |
8118 | { Bad_Opcode }, |
8119 | { Bad_Opcode }, | |
8120 | { Bad_Opcode }, | |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
8123 | { Bad_Opcode }, | |
8124 | { Bad_Opcode }, | |
8125 | { Bad_Opcode }, | |
4e7d34a6 | 8126 | /* 60 */ |
592d1631 L |
8127 | { Bad_Opcode }, |
8128 | { Bad_Opcode }, | |
8129 | { Bad_Opcode }, | |
8130 | { Bad_Opcode }, | |
8131 | { Bad_Opcode }, | |
8132 | { Bad_Opcode }, | |
8133 | { Bad_Opcode }, | |
8134 | { Bad_Opcode }, | |
4e7d34a6 | 8135 | /* 68 */ |
592d1631 L |
8136 | { Bad_Opcode }, |
8137 | { Bad_Opcode }, | |
8138 | { Bad_Opcode }, | |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
8141 | { Bad_Opcode }, | |
8142 | { Bad_Opcode }, | |
8143 | { Bad_Opcode }, | |
4e7d34a6 | 8144 | /* 70 */ |
592d1631 L |
8145 | { Bad_Opcode }, |
8146 | { Bad_Opcode }, | |
8147 | { Bad_Opcode }, | |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
8150 | { Bad_Opcode }, | |
8151 | { Bad_Opcode }, | |
8152 | { Bad_Opcode }, | |
4e7d34a6 | 8153 | /* 78 */ |
592d1631 L |
8154 | { Bad_Opcode }, |
8155 | { Bad_Opcode }, | |
8156 | { Bad_Opcode }, | |
8157 | { Bad_Opcode }, | |
8158 | { Bad_Opcode }, | |
8159 | { Bad_Opcode }, | |
8160 | { Bad_Opcode }, | |
8161 | { Bad_Opcode }, | |
4e7d34a6 | 8162 | /* 80 */ |
592d1631 L |
8163 | { Bad_Opcode }, |
8164 | { Bad_Opcode }, | |
8165 | { Bad_Opcode }, | |
8166 | { Bad_Opcode }, | |
8167 | { Bad_Opcode }, | |
8168 | { Bad_Opcode }, | |
8169 | { Bad_Opcode }, | |
8170 | { Bad_Opcode }, | |
4e7d34a6 | 8171 | /* 88 */ |
592d1631 L |
8172 | { Bad_Opcode }, |
8173 | { Bad_Opcode }, | |
8174 | { Bad_Opcode }, | |
8175 | { Bad_Opcode }, | |
8176 | { Bad_Opcode }, | |
8177 | { Bad_Opcode }, | |
8178 | { Bad_Opcode }, | |
8179 | { Bad_Opcode }, | |
4e7d34a6 | 8180 | /* 90 */ |
592d1631 L |
8181 | { Bad_Opcode }, |
8182 | { Bad_Opcode }, | |
8183 | { Bad_Opcode }, | |
8184 | { Bad_Opcode }, | |
8185 | { Bad_Opcode }, | |
8186 | { Bad_Opcode }, | |
8187 | { Bad_Opcode }, | |
8188 | { Bad_Opcode }, | |
4e7d34a6 | 8189 | /* 98 */ |
592d1631 L |
8190 | { Bad_Opcode }, |
8191 | { Bad_Opcode }, | |
8192 | { Bad_Opcode }, | |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
8195 | { Bad_Opcode }, | |
8196 | { Bad_Opcode }, | |
8197 | { Bad_Opcode }, | |
4e7d34a6 | 8198 | /* a0 */ |
592d1631 L |
8199 | { Bad_Opcode }, |
8200 | { Bad_Opcode }, | |
8201 | { Bad_Opcode }, | |
8202 | { Bad_Opcode }, | |
8203 | { Bad_Opcode }, | |
8204 | { Bad_Opcode }, | |
8205 | { Bad_Opcode }, | |
8206 | { Bad_Opcode }, | |
4e7d34a6 | 8207 | /* a8 */ |
592d1631 L |
8208 | { Bad_Opcode }, |
8209 | { Bad_Opcode }, | |
8210 | { Bad_Opcode }, | |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
8213 | { Bad_Opcode }, | |
8214 | { Bad_Opcode }, | |
8215 | { Bad_Opcode }, | |
d5d7db8e | 8216 | /* b0 */ |
592d1631 L |
8217 | { Bad_Opcode }, |
8218 | { Bad_Opcode }, | |
8219 | { Bad_Opcode }, | |
8220 | { Bad_Opcode }, | |
8221 | { Bad_Opcode }, | |
8222 | { Bad_Opcode }, | |
8223 | { Bad_Opcode }, | |
8224 | { Bad_Opcode }, | |
85f10a01 | 8225 | /* b8 */ |
592d1631 L |
8226 | { Bad_Opcode }, |
8227 | { Bad_Opcode }, | |
8228 | { Bad_Opcode }, | |
8229 | { Bad_Opcode }, | |
8230 | { Bad_Opcode }, | |
8231 | { Bad_Opcode }, | |
8232 | { Bad_Opcode }, | |
8233 | { Bad_Opcode }, | |
85f10a01 | 8234 | /* c0 */ |
592d1631 L |
8235 | { Bad_Opcode }, |
8236 | { Bad_Opcode }, | |
8237 | { Bad_Opcode }, | |
8238 | { Bad_Opcode }, | |
8239 | { Bad_Opcode }, | |
8240 | { Bad_Opcode }, | |
8241 | { Bad_Opcode }, | |
8242 | { Bad_Opcode }, | |
85f10a01 | 8243 | /* c8 */ |
592d1631 L |
8244 | { Bad_Opcode }, |
8245 | { Bad_Opcode }, | |
8246 | { Bad_Opcode }, | |
8247 | { Bad_Opcode }, | |
8248 | { Bad_Opcode }, | |
8249 | { Bad_Opcode }, | |
8250 | { Bad_Opcode }, | |
8251 | { Bad_Opcode }, | |
85f10a01 | 8252 | /* d0 */ |
592d1631 L |
8253 | { Bad_Opcode }, |
8254 | { Bad_Opcode }, | |
8255 | { Bad_Opcode }, | |
8256 | { Bad_Opcode }, | |
8257 | { Bad_Opcode }, | |
8258 | { Bad_Opcode }, | |
8259 | { Bad_Opcode }, | |
8260 | { Bad_Opcode }, | |
85f10a01 | 8261 | /* d8 */ |
592d1631 L |
8262 | { Bad_Opcode }, |
8263 | { Bad_Opcode }, | |
8264 | { Bad_Opcode }, | |
8265 | { Bad_Opcode }, | |
8266 | { Bad_Opcode }, | |
8267 | { Bad_Opcode }, | |
8268 | { Bad_Opcode }, | |
8269 | { Bad_Opcode }, | |
85f10a01 | 8270 | /* e0 */ |
592d1631 L |
8271 | { Bad_Opcode }, |
8272 | { Bad_Opcode }, | |
8273 | { Bad_Opcode }, | |
8274 | { Bad_Opcode }, | |
8275 | { Bad_Opcode }, | |
8276 | { Bad_Opcode }, | |
8277 | { Bad_Opcode }, | |
8278 | { Bad_Opcode }, | |
85f10a01 | 8279 | /* e8 */ |
592d1631 L |
8280 | { Bad_Opcode }, |
8281 | { Bad_Opcode }, | |
8282 | { Bad_Opcode }, | |
8283 | { Bad_Opcode }, | |
8284 | { Bad_Opcode }, | |
8285 | { Bad_Opcode }, | |
8286 | { Bad_Opcode }, | |
8287 | { Bad_Opcode }, | |
85f10a01 | 8288 | /* f0 */ |
592d1631 L |
8289 | { Bad_Opcode }, |
8290 | { Bad_Opcode }, | |
8291 | { Bad_Opcode }, | |
8292 | { Bad_Opcode }, | |
8293 | { Bad_Opcode }, | |
8294 | { Bad_Opcode }, | |
8295 | { Bad_Opcode }, | |
8296 | { Bad_Opcode }, | |
85f10a01 | 8297 | /* f8 */ |
592d1631 L |
8298 | { Bad_Opcode }, |
8299 | { Bad_Opcode }, | |
8300 | { Bad_Opcode }, | |
8301 | { Bad_Opcode }, | |
8302 | { Bad_Opcode }, | |
8303 | { Bad_Opcode }, | |
8304 | { Bad_Opcode }, | |
8305 | { Bad_Opcode }, | |
85f10a01 | 8306 | }, |
c0f3af97 L |
8307 | }; |
8308 | ||
8309 | static const struct dis386 vex_table[][256] = { | |
8310 | /* VEX_0F */ | |
85f10a01 MM |
8311 | { |
8312 | /* 00 */ | |
592d1631 L |
8313 | { Bad_Opcode }, |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
8316 | { Bad_Opcode }, | |
8317 | { Bad_Opcode }, | |
8318 | { Bad_Opcode }, | |
8319 | { Bad_Opcode }, | |
8320 | { Bad_Opcode }, | |
85f10a01 | 8321 | /* 08 */ |
592d1631 L |
8322 | { Bad_Opcode }, |
8323 | { Bad_Opcode }, | |
8324 | { Bad_Opcode }, | |
8325 | { Bad_Opcode }, | |
8326 | { Bad_Opcode }, | |
8327 | { Bad_Opcode }, | |
8328 | { Bad_Opcode }, | |
8329 | { Bad_Opcode }, | |
c0f3af97 | 8330 | /* 10 */ |
592a252b L |
8331 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8332 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8333 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8334 | { MOD_TABLE (MOD_VEX_0F13) }, | |
bf926894 JB |
8335 | { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
8336 | { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
592a252b L |
8337 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
8338 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8339 | /* 18 */ |
592d1631 L |
8340 | { Bad_Opcode }, |
8341 | { Bad_Opcode }, | |
8342 | { Bad_Opcode }, | |
8343 | { Bad_Opcode }, | |
8344 | { Bad_Opcode }, | |
8345 | { Bad_Opcode }, | |
8346 | { Bad_Opcode }, | |
8347 | { Bad_Opcode }, | |
c0f3af97 | 8348 | /* 20 */ |
592d1631 L |
8349 | { Bad_Opcode }, |
8350 | { Bad_Opcode }, | |
8351 | { Bad_Opcode }, | |
8352 | { Bad_Opcode }, | |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
8355 | { Bad_Opcode }, | |
8356 | { Bad_Opcode }, | |
c0f3af97 | 8357 | /* 28 */ |
bf926894 JB |
8358 | { "vmovapX", { XM, EXx }, PREFIX_OPCODE }, |
8359 | { "vmovapX", { EXxS, XM }, PREFIX_OPCODE }, | |
592a252b L |
8360 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
8361 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8362 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8363 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8364 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8365 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8366 | /* 30 */ |
592d1631 L |
8367 | { Bad_Opcode }, |
8368 | { Bad_Opcode }, | |
8369 | { Bad_Opcode }, | |
8370 | { Bad_Opcode }, | |
8371 | { Bad_Opcode }, | |
8372 | { Bad_Opcode }, | |
8373 | { Bad_Opcode }, | |
8374 | { Bad_Opcode }, | |
4e7d34a6 | 8375 | /* 38 */ |
592d1631 L |
8376 | { Bad_Opcode }, |
8377 | { Bad_Opcode }, | |
8378 | { Bad_Opcode }, | |
8379 | { Bad_Opcode }, | |
8380 | { Bad_Opcode }, | |
8381 | { Bad_Opcode }, | |
8382 | { Bad_Opcode }, | |
8383 | { Bad_Opcode }, | |
d5d7db8e | 8384 | /* 40 */ |
592d1631 | 8385 | { Bad_Opcode }, |
43234a1e L |
8386 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8387 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8388 | { Bad_Opcode }, |
43234a1e L |
8389 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8390 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8391 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8392 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8393 | /* 48 */ |
592d1631 L |
8394 | { Bad_Opcode }, |
8395 | { Bad_Opcode }, | |
1ba585e8 | 8396 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8397 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8398 | { Bad_Opcode }, |
8399 | { Bad_Opcode }, | |
8400 | { Bad_Opcode }, | |
8401 | { Bad_Opcode }, | |
d5d7db8e | 8402 | /* 50 */ |
592a252b L |
8403 | { MOD_TABLE (MOD_VEX_0F50) }, |
8404 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8405 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8406 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf926894 JB |
8407 | { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
8408 | { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
8409 | { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
8410 | { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
c0f3af97 | 8411 | /* 58 */ |
592a252b L |
8412 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8413 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8414 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8415 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8416 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8417 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8418 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8419 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8420 | /* 60 */ |
592a252b L |
8421 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8422 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8423 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8424 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8425 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8426 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8427 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8428 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8429 | /* 68 */ |
592a252b L |
8430 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8431 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8432 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8433 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8434 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8435 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8436 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8437 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8438 | /* 70 */ |
592a252b L |
8439 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8440 | { REG_TABLE (REG_VEX_0F71) }, | |
8441 | { REG_TABLE (REG_VEX_0F72) }, | |
8442 | { REG_TABLE (REG_VEX_0F73) }, | |
8443 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8444 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8445 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8446 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8447 | /* 78 */ |
592d1631 L |
8448 | { Bad_Opcode }, |
8449 | { Bad_Opcode }, | |
8450 | { Bad_Opcode }, | |
8451 | { Bad_Opcode }, | |
592a252b L |
8452 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8453 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8454 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8455 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8456 | /* 80 */ |
592d1631 L |
8457 | { Bad_Opcode }, |
8458 | { Bad_Opcode }, | |
8459 | { Bad_Opcode }, | |
8460 | { Bad_Opcode }, | |
8461 | { Bad_Opcode }, | |
8462 | { Bad_Opcode }, | |
8463 | { Bad_Opcode }, | |
8464 | { Bad_Opcode }, | |
c0f3af97 | 8465 | /* 88 */ |
592d1631 L |
8466 | { Bad_Opcode }, |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
8469 | { Bad_Opcode }, | |
8470 | { Bad_Opcode }, | |
8471 | { Bad_Opcode }, | |
8472 | { Bad_Opcode }, | |
8473 | { Bad_Opcode }, | |
c0f3af97 | 8474 | /* 90 */ |
43234a1e L |
8475 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8476 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8477 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8478 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8479 | { Bad_Opcode }, |
8480 | { Bad_Opcode }, | |
8481 | { Bad_Opcode }, | |
8482 | { Bad_Opcode }, | |
c0f3af97 | 8483 | /* 98 */ |
43234a1e | 8484 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8485 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8486 | { Bad_Opcode }, |
8487 | { Bad_Opcode }, | |
8488 | { Bad_Opcode }, | |
8489 | { Bad_Opcode }, | |
8490 | { Bad_Opcode }, | |
8491 | { Bad_Opcode }, | |
c0f3af97 | 8492 | /* a0 */ |
592d1631 L |
8493 | { Bad_Opcode }, |
8494 | { Bad_Opcode }, | |
8495 | { Bad_Opcode }, | |
8496 | { Bad_Opcode }, | |
8497 | { Bad_Opcode }, | |
8498 | { Bad_Opcode }, | |
8499 | { Bad_Opcode }, | |
8500 | { Bad_Opcode }, | |
c0f3af97 | 8501 | /* a8 */ |
592d1631 L |
8502 | { Bad_Opcode }, |
8503 | { Bad_Opcode }, | |
8504 | { Bad_Opcode }, | |
8505 | { Bad_Opcode }, | |
8506 | { Bad_Opcode }, | |
8507 | { Bad_Opcode }, | |
592a252b | 8508 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8509 | { Bad_Opcode }, |
c0f3af97 | 8510 | /* b0 */ |
592d1631 L |
8511 | { Bad_Opcode }, |
8512 | { Bad_Opcode }, | |
8513 | { Bad_Opcode }, | |
8514 | { Bad_Opcode }, | |
8515 | { Bad_Opcode }, | |
8516 | { Bad_Opcode }, | |
8517 | { Bad_Opcode }, | |
8518 | { Bad_Opcode }, | |
c0f3af97 | 8519 | /* b8 */ |
592d1631 L |
8520 | { Bad_Opcode }, |
8521 | { Bad_Opcode }, | |
8522 | { Bad_Opcode }, | |
8523 | { Bad_Opcode }, | |
8524 | { Bad_Opcode }, | |
8525 | { Bad_Opcode }, | |
8526 | { Bad_Opcode }, | |
8527 | { Bad_Opcode }, | |
c0f3af97 | 8528 | /* c0 */ |
592d1631 L |
8529 | { Bad_Opcode }, |
8530 | { Bad_Opcode }, | |
592a252b | 8531 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8532 | { Bad_Opcode }, |
592a252b L |
8533 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8534 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf926894 | 8535 | { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE }, |
592d1631 | 8536 | { Bad_Opcode }, |
c0f3af97 | 8537 | /* c8 */ |
592d1631 L |
8538 | { Bad_Opcode }, |
8539 | { Bad_Opcode }, | |
8540 | { Bad_Opcode }, | |
8541 | { Bad_Opcode }, | |
8542 | { Bad_Opcode }, | |
8543 | { Bad_Opcode }, | |
8544 | { Bad_Opcode }, | |
8545 | { Bad_Opcode }, | |
c0f3af97 | 8546 | /* d0 */ |
592a252b L |
8547 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8548 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8549 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8550 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8551 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8552 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8553 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8554 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8555 | /* d8 */ |
592a252b L |
8556 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8557 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8558 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8559 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8560 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8561 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8562 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8563 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8564 | /* e0 */ |
592a252b L |
8565 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8566 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8567 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8568 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8569 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8570 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8571 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8572 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8573 | /* e8 */ |
592a252b L |
8574 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8575 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8576 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8577 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8578 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8579 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8580 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8581 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8582 | /* f0 */ |
592a252b L |
8583 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8584 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8585 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8586 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8587 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8588 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8589 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8590 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8591 | /* f8 */ |
592a252b L |
8592 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8593 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8594 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8595 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8596 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8597 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8598 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8599 | { Bad_Opcode }, |
c0f3af97 L |
8600 | }, |
8601 | /* VEX_0F38 */ | |
8602 | { | |
8603 | /* 00 */ | |
592a252b L |
8604 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8605 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8606 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8607 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8608 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8609 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8610 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8611 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8612 | /* 08 */ |
592a252b L |
8613 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8614 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8615 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8616 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8617 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8618 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8619 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8620 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8621 | /* 10 */ |
592d1631 L |
8622 | { Bad_Opcode }, |
8623 | { Bad_Opcode }, | |
8624 | { Bad_Opcode }, | |
592a252b | 8625 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8626 | { Bad_Opcode }, |
8627 | { Bad_Opcode }, | |
6c30d220 | 8628 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8629 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8630 | /* 18 */ |
592a252b L |
8631 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8632 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8633 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8634 | { Bad_Opcode }, |
592a252b L |
8635 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8636 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8637 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8638 | { Bad_Opcode }, |
c0f3af97 | 8639 | /* 20 */ |
592a252b L |
8640 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8641 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8642 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8643 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8644 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8645 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8646 | { Bad_Opcode }, |
8647 | { Bad_Opcode }, | |
c0f3af97 | 8648 | /* 28 */ |
592a252b L |
8649 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8650 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8651 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8652 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8653 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8654 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8655 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8656 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8657 | /* 30 */ |
592a252b L |
8658 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8659 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8660 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8661 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8662 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8663 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8664 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8665 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8666 | /* 38 */ |
592a252b L |
8667 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8668 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8669 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8670 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8671 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8672 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8673 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8674 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8675 | /* 40 */ |
592a252b L |
8676 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8677 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8678 | { Bad_Opcode }, |
8679 | { Bad_Opcode }, | |
8680 | { Bad_Opcode }, | |
6c30d220 L |
8681 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8682 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8683 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8684 | /* 48 */ |
592d1631 L |
8685 | { Bad_Opcode }, |
8686 | { Bad_Opcode }, | |
8687 | { Bad_Opcode }, | |
8688 | { Bad_Opcode }, | |
8689 | { Bad_Opcode }, | |
8690 | { Bad_Opcode }, | |
8691 | { Bad_Opcode }, | |
8692 | { Bad_Opcode }, | |
c0f3af97 | 8693 | /* 50 */ |
592d1631 L |
8694 | { Bad_Opcode }, |
8695 | { Bad_Opcode }, | |
8696 | { Bad_Opcode }, | |
8697 | { Bad_Opcode }, | |
8698 | { Bad_Opcode }, | |
8699 | { Bad_Opcode }, | |
8700 | { Bad_Opcode }, | |
8701 | { Bad_Opcode }, | |
c0f3af97 | 8702 | /* 58 */ |
6c30d220 L |
8703 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8704 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8705 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
8706 | { Bad_Opcode }, |
8707 | { Bad_Opcode }, | |
8708 | { Bad_Opcode }, | |
8709 | { Bad_Opcode }, | |
8710 | { Bad_Opcode }, | |
c0f3af97 | 8711 | /* 60 */ |
592d1631 L |
8712 | { Bad_Opcode }, |
8713 | { Bad_Opcode }, | |
8714 | { Bad_Opcode }, | |
8715 | { Bad_Opcode }, | |
8716 | { Bad_Opcode }, | |
8717 | { Bad_Opcode }, | |
8718 | { Bad_Opcode }, | |
8719 | { Bad_Opcode }, | |
c0f3af97 | 8720 | /* 68 */ |
592d1631 L |
8721 | { Bad_Opcode }, |
8722 | { Bad_Opcode }, | |
8723 | { Bad_Opcode }, | |
8724 | { Bad_Opcode }, | |
8725 | { Bad_Opcode }, | |
8726 | { Bad_Opcode }, | |
8727 | { Bad_Opcode }, | |
8728 | { Bad_Opcode }, | |
c0f3af97 | 8729 | /* 70 */ |
592d1631 L |
8730 | { Bad_Opcode }, |
8731 | { Bad_Opcode }, | |
8732 | { Bad_Opcode }, | |
8733 | { Bad_Opcode }, | |
8734 | { Bad_Opcode }, | |
8735 | { Bad_Opcode }, | |
8736 | { Bad_Opcode }, | |
8737 | { Bad_Opcode }, | |
c0f3af97 | 8738 | /* 78 */ |
6c30d220 L |
8739 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8740 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
8741 | { Bad_Opcode }, |
8742 | { Bad_Opcode }, | |
8743 | { Bad_Opcode }, | |
8744 | { Bad_Opcode }, | |
8745 | { Bad_Opcode }, | |
8746 | { Bad_Opcode }, | |
c0f3af97 | 8747 | /* 80 */ |
592d1631 L |
8748 | { Bad_Opcode }, |
8749 | { Bad_Opcode }, | |
8750 | { Bad_Opcode }, | |
8751 | { Bad_Opcode }, | |
8752 | { Bad_Opcode }, | |
8753 | { Bad_Opcode }, | |
8754 | { Bad_Opcode }, | |
8755 | { Bad_Opcode }, | |
c0f3af97 | 8756 | /* 88 */ |
592d1631 L |
8757 | { Bad_Opcode }, |
8758 | { Bad_Opcode }, | |
8759 | { Bad_Opcode }, | |
8760 | { Bad_Opcode }, | |
6c30d220 | 8761 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8762 | { Bad_Opcode }, |
6c30d220 | 8763 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8764 | { Bad_Opcode }, |
c0f3af97 | 8765 | /* 90 */ |
6c30d220 L |
8766 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8767 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8768 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8769 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8770 | { Bad_Opcode }, |
8771 | { Bad_Opcode }, | |
592a252b L |
8772 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8773 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8774 | /* 98 */ |
592a252b L |
8775 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8776 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8777 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8778 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8779 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8780 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8781 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8782 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8783 | /* a0 */ |
592d1631 L |
8784 | { Bad_Opcode }, |
8785 | { Bad_Opcode }, | |
8786 | { Bad_Opcode }, | |
8787 | { Bad_Opcode }, | |
8788 | { Bad_Opcode }, | |
8789 | { Bad_Opcode }, | |
592a252b L |
8790 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8791 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8792 | /* a8 */ |
592a252b L |
8793 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8794 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8795 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8796 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8797 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8798 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8799 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8800 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8801 | /* b0 */ |
592d1631 L |
8802 | { Bad_Opcode }, |
8803 | { Bad_Opcode }, | |
8804 | { Bad_Opcode }, | |
8805 | { Bad_Opcode }, | |
8806 | { Bad_Opcode }, | |
8807 | { Bad_Opcode }, | |
592a252b L |
8808 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8809 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 8810 | /* b8 */ |
592a252b L |
8811 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8812 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
8813 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
8814 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
8815 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
8816 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
8817 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
8818 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 8819 | /* c0 */ |
592d1631 L |
8820 | { Bad_Opcode }, |
8821 | { Bad_Opcode }, | |
8822 | { Bad_Opcode }, | |
8823 | { Bad_Opcode }, | |
8824 | { Bad_Opcode }, | |
8825 | { Bad_Opcode }, | |
8826 | { Bad_Opcode }, | |
8827 | { Bad_Opcode }, | |
c0f3af97 | 8828 | /* c8 */ |
592d1631 L |
8829 | { Bad_Opcode }, |
8830 | { Bad_Opcode }, | |
8831 | { Bad_Opcode }, | |
8832 | { Bad_Opcode }, | |
8833 | { Bad_Opcode }, | |
8834 | { Bad_Opcode }, | |
8835 | { Bad_Opcode }, | |
48521003 | 8836 | { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, |
c0f3af97 | 8837 | /* d0 */ |
592d1631 L |
8838 | { Bad_Opcode }, |
8839 | { Bad_Opcode }, | |
8840 | { Bad_Opcode }, | |
8841 | { Bad_Opcode }, | |
8842 | { Bad_Opcode }, | |
8843 | { Bad_Opcode }, | |
8844 | { Bad_Opcode }, | |
8845 | { Bad_Opcode }, | |
c0f3af97 | 8846 | /* d8 */ |
592d1631 L |
8847 | { Bad_Opcode }, |
8848 | { Bad_Opcode }, | |
8849 | { Bad_Opcode }, | |
592a252b L |
8850 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
8851 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
8852 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
8853 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
8854 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 8855 | /* e0 */ |
592d1631 L |
8856 | { Bad_Opcode }, |
8857 | { Bad_Opcode }, | |
8858 | { Bad_Opcode }, | |
8859 | { Bad_Opcode }, | |
8860 | { Bad_Opcode }, | |
8861 | { Bad_Opcode }, | |
8862 | { Bad_Opcode }, | |
8863 | { Bad_Opcode }, | |
c0f3af97 | 8864 | /* e8 */ |
592d1631 L |
8865 | { Bad_Opcode }, |
8866 | { Bad_Opcode }, | |
8867 | { Bad_Opcode }, | |
8868 | { Bad_Opcode }, | |
8869 | { Bad_Opcode }, | |
8870 | { Bad_Opcode }, | |
8871 | { Bad_Opcode }, | |
8872 | { Bad_Opcode }, | |
c0f3af97 | 8873 | /* f0 */ |
592d1631 L |
8874 | { Bad_Opcode }, |
8875 | { Bad_Opcode }, | |
f12dc422 L |
8876 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
8877 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 8878 | { Bad_Opcode }, |
6c30d220 L |
8879 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
8880 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 8881 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 8882 | /* f8 */ |
592d1631 L |
8883 | { Bad_Opcode }, |
8884 | { Bad_Opcode }, | |
8885 | { Bad_Opcode }, | |
8886 | { Bad_Opcode }, | |
8887 | { Bad_Opcode }, | |
8888 | { Bad_Opcode }, | |
8889 | { Bad_Opcode }, | |
8890 | { Bad_Opcode }, | |
c0f3af97 L |
8891 | }, |
8892 | /* VEX_0F3A */ | |
8893 | { | |
8894 | /* 00 */ | |
6c30d220 L |
8895 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
8896 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
8897 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 8898 | { Bad_Opcode }, |
592a252b L |
8899 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
8900 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
8901 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 8902 | { Bad_Opcode }, |
c0f3af97 | 8903 | /* 08 */ |
592a252b L |
8904 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
8905 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
8906 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
8907 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
8908 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
8909 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
8910 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
8911 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 8912 | /* 10 */ |
592d1631 L |
8913 | { Bad_Opcode }, |
8914 | { Bad_Opcode }, | |
8915 | { Bad_Opcode }, | |
8916 | { Bad_Opcode }, | |
592a252b L |
8917 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
8918 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
8919 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
8920 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 8921 | /* 18 */ |
592a252b L |
8922 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
8923 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
8924 | { Bad_Opcode }, |
8925 | { Bad_Opcode }, | |
8926 | { Bad_Opcode }, | |
592a252b | 8927 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
8928 | { Bad_Opcode }, |
8929 | { Bad_Opcode }, | |
c0f3af97 | 8930 | /* 20 */ |
592a252b L |
8931 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
8932 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
8933 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
8934 | { Bad_Opcode }, |
8935 | { Bad_Opcode }, | |
8936 | { Bad_Opcode }, | |
8937 | { Bad_Opcode }, | |
8938 | { Bad_Opcode }, | |
c0f3af97 | 8939 | /* 28 */ |
592d1631 L |
8940 | { Bad_Opcode }, |
8941 | { Bad_Opcode }, | |
8942 | { Bad_Opcode }, | |
8943 | { Bad_Opcode }, | |
8944 | { Bad_Opcode }, | |
8945 | { Bad_Opcode }, | |
8946 | { Bad_Opcode }, | |
8947 | { Bad_Opcode }, | |
c0f3af97 | 8948 | /* 30 */ |
43234a1e | 8949 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 8950 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 8951 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 8952 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
8953 | { Bad_Opcode }, |
8954 | { Bad_Opcode }, | |
8955 | { Bad_Opcode }, | |
8956 | { Bad_Opcode }, | |
c0f3af97 | 8957 | /* 38 */ |
6c30d220 L |
8958 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
8959 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
8960 | { Bad_Opcode }, |
8961 | { Bad_Opcode }, | |
8962 | { Bad_Opcode }, | |
8963 | { Bad_Opcode }, | |
8964 | { Bad_Opcode }, | |
8965 | { Bad_Opcode }, | |
c0f3af97 | 8966 | /* 40 */ |
592a252b L |
8967 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
8968 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
8969 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 8970 | { Bad_Opcode }, |
592a252b | 8971 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 8972 | { Bad_Opcode }, |
6c30d220 | 8973 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 8974 | { Bad_Opcode }, |
c0f3af97 | 8975 | /* 48 */ |
592a252b L |
8976 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
8977 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
8978 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
8979 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
8980 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
8981 | { Bad_Opcode }, |
8982 | { Bad_Opcode }, | |
8983 | { Bad_Opcode }, | |
c0f3af97 | 8984 | /* 50 */ |
592d1631 L |
8985 | { Bad_Opcode }, |
8986 | { Bad_Opcode }, | |
8987 | { Bad_Opcode }, | |
8988 | { Bad_Opcode }, | |
8989 | { Bad_Opcode }, | |
8990 | { Bad_Opcode }, | |
8991 | { Bad_Opcode }, | |
8992 | { Bad_Opcode }, | |
c0f3af97 | 8993 | /* 58 */ |
592d1631 L |
8994 | { Bad_Opcode }, |
8995 | { Bad_Opcode }, | |
8996 | { Bad_Opcode }, | |
8997 | { Bad_Opcode }, | |
592a252b L |
8998 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
8999 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9000 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9001 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9002 | /* 60 */ |
592a252b L |
9003 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9004 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9005 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9006 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9007 | { Bad_Opcode }, |
9008 | { Bad_Opcode }, | |
9009 | { Bad_Opcode }, | |
9010 | { Bad_Opcode }, | |
c0f3af97 | 9011 | /* 68 */ |
592a252b L |
9012 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9013 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9014 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9015 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9016 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9017 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9018 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9019 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9020 | /* 70 */ |
592d1631 L |
9021 | { Bad_Opcode }, |
9022 | { Bad_Opcode }, | |
9023 | { Bad_Opcode }, | |
9024 | { Bad_Opcode }, | |
9025 | { Bad_Opcode }, | |
9026 | { Bad_Opcode }, | |
9027 | { Bad_Opcode }, | |
9028 | { Bad_Opcode }, | |
c0f3af97 | 9029 | /* 78 */ |
592a252b L |
9030 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9031 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9032 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9033 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9034 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9035 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9036 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9037 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9038 | /* 80 */ |
592d1631 L |
9039 | { Bad_Opcode }, |
9040 | { Bad_Opcode }, | |
9041 | { Bad_Opcode }, | |
9042 | { Bad_Opcode }, | |
9043 | { Bad_Opcode }, | |
9044 | { Bad_Opcode }, | |
9045 | { Bad_Opcode }, | |
9046 | { Bad_Opcode }, | |
c0f3af97 | 9047 | /* 88 */ |
592d1631 L |
9048 | { Bad_Opcode }, |
9049 | { Bad_Opcode }, | |
9050 | { Bad_Opcode }, | |
9051 | { Bad_Opcode }, | |
9052 | { Bad_Opcode }, | |
9053 | { Bad_Opcode }, | |
9054 | { Bad_Opcode }, | |
9055 | { Bad_Opcode }, | |
c0f3af97 | 9056 | /* 90 */ |
592d1631 L |
9057 | { Bad_Opcode }, |
9058 | { Bad_Opcode }, | |
9059 | { Bad_Opcode }, | |
9060 | { Bad_Opcode }, | |
9061 | { Bad_Opcode }, | |
9062 | { Bad_Opcode }, | |
9063 | { Bad_Opcode }, | |
9064 | { Bad_Opcode }, | |
c0f3af97 | 9065 | /* 98 */ |
592d1631 L |
9066 | { Bad_Opcode }, |
9067 | { Bad_Opcode }, | |
9068 | { Bad_Opcode }, | |
9069 | { Bad_Opcode }, | |
9070 | { Bad_Opcode }, | |
9071 | { Bad_Opcode }, | |
9072 | { Bad_Opcode }, | |
9073 | { Bad_Opcode }, | |
c0f3af97 | 9074 | /* a0 */ |
592d1631 L |
9075 | { Bad_Opcode }, |
9076 | { Bad_Opcode }, | |
9077 | { Bad_Opcode }, | |
9078 | { Bad_Opcode }, | |
9079 | { Bad_Opcode }, | |
9080 | { Bad_Opcode }, | |
9081 | { Bad_Opcode }, | |
9082 | { Bad_Opcode }, | |
c0f3af97 | 9083 | /* a8 */ |
592d1631 L |
9084 | { Bad_Opcode }, |
9085 | { Bad_Opcode }, | |
9086 | { Bad_Opcode }, | |
9087 | { Bad_Opcode }, | |
9088 | { Bad_Opcode }, | |
9089 | { Bad_Opcode }, | |
9090 | { Bad_Opcode }, | |
9091 | { Bad_Opcode }, | |
c0f3af97 | 9092 | /* b0 */ |
592d1631 L |
9093 | { Bad_Opcode }, |
9094 | { Bad_Opcode }, | |
9095 | { Bad_Opcode }, | |
9096 | { Bad_Opcode }, | |
9097 | { Bad_Opcode }, | |
9098 | { Bad_Opcode }, | |
9099 | { Bad_Opcode }, | |
9100 | { Bad_Opcode }, | |
c0f3af97 | 9101 | /* b8 */ |
592d1631 L |
9102 | { Bad_Opcode }, |
9103 | { Bad_Opcode }, | |
9104 | { Bad_Opcode }, | |
9105 | { Bad_Opcode }, | |
9106 | { Bad_Opcode }, | |
9107 | { Bad_Opcode }, | |
9108 | { Bad_Opcode }, | |
9109 | { Bad_Opcode }, | |
c0f3af97 | 9110 | /* c0 */ |
592d1631 L |
9111 | { Bad_Opcode }, |
9112 | { Bad_Opcode }, | |
9113 | { Bad_Opcode }, | |
9114 | { Bad_Opcode }, | |
9115 | { Bad_Opcode }, | |
9116 | { Bad_Opcode }, | |
9117 | { Bad_Opcode }, | |
9118 | { Bad_Opcode }, | |
c0f3af97 | 9119 | /* c8 */ |
592d1631 L |
9120 | { Bad_Opcode }, |
9121 | { Bad_Opcode }, | |
9122 | { Bad_Opcode }, | |
9123 | { Bad_Opcode }, | |
9124 | { Bad_Opcode }, | |
9125 | { Bad_Opcode }, | |
48521003 IT |
9126 | { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, |
9127 | { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, | |
c0f3af97 | 9128 | /* d0 */ |
592d1631 L |
9129 | { Bad_Opcode }, |
9130 | { Bad_Opcode }, | |
9131 | { Bad_Opcode }, | |
9132 | { Bad_Opcode }, | |
9133 | { Bad_Opcode }, | |
9134 | { Bad_Opcode }, | |
9135 | { Bad_Opcode }, | |
9136 | { Bad_Opcode }, | |
c0f3af97 | 9137 | /* d8 */ |
592d1631 L |
9138 | { Bad_Opcode }, |
9139 | { Bad_Opcode }, | |
9140 | { Bad_Opcode }, | |
9141 | { Bad_Opcode }, | |
9142 | { Bad_Opcode }, | |
9143 | { Bad_Opcode }, | |
9144 | { Bad_Opcode }, | |
592a252b | 9145 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9146 | /* e0 */ |
592d1631 L |
9147 | { Bad_Opcode }, |
9148 | { Bad_Opcode }, | |
9149 | { Bad_Opcode }, | |
9150 | { Bad_Opcode }, | |
9151 | { Bad_Opcode }, | |
9152 | { Bad_Opcode }, | |
9153 | { Bad_Opcode }, | |
9154 | { Bad_Opcode }, | |
c0f3af97 | 9155 | /* e8 */ |
592d1631 L |
9156 | { Bad_Opcode }, |
9157 | { Bad_Opcode }, | |
9158 | { Bad_Opcode }, | |
9159 | { Bad_Opcode }, | |
9160 | { Bad_Opcode }, | |
9161 | { Bad_Opcode }, | |
9162 | { Bad_Opcode }, | |
9163 | { Bad_Opcode }, | |
c0f3af97 | 9164 | /* f0 */ |
6c30d220 | 9165 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9166 | { Bad_Opcode }, |
9167 | { Bad_Opcode }, | |
9168 | { Bad_Opcode }, | |
9169 | { Bad_Opcode }, | |
9170 | { Bad_Opcode }, | |
9171 | { Bad_Opcode }, | |
9172 | { Bad_Opcode }, | |
c0f3af97 | 9173 | /* f8 */ |
592d1631 L |
9174 | { Bad_Opcode }, |
9175 | { Bad_Opcode }, | |
9176 | { Bad_Opcode }, | |
9177 | { Bad_Opcode }, | |
9178 | { Bad_Opcode }, | |
9179 | { Bad_Opcode }, | |
9180 | { Bad_Opcode }, | |
9181 | { Bad_Opcode }, | |
c0f3af97 L |
9182 | }, |
9183 | }; | |
9184 | ||
43234a1e | 9185 | #include "i386-dis-evex.h" |
ad692897 | 9186 | |
c0f3af97 | 9187 | static const struct dis386 vex_len_table[][2] = { |
18897deb | 9188 | /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */ |
c0f3af97 | 9189 | { |
18897deb | 9190 | { "vmovlpX", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9191 | }, |
9192 | ||
592a252b | 9193 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9194 | { |
ec6f095a | 9195 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9196 | }, |
9197 | ||
592a252b | 9198 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9199 | { |
bf926894 | 9200 | { "vmovlpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
9201 | }, |
9202 | ||
18897deb | 9203 | /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */ |
c0f3af97 | 9204 | { |
18897deb | 9205 | { "vmovhpX", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9206 | }, |
9207 | ||
592a252b | 9208 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9209 | { |
ec6f095a | 9210 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9211 | }, |
9212 | ||
592a252b | 9213 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9214 | { |
bf926894 | 9215 | { "vmovhpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
9216 | }, |
9217 | ||
43234a1e L |
9218 | /* VEX_LEN_0F41_P_0 */ |
9219 | { | |
9220 | { Bad_Opcode }, | |
9221 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9222 | }, | |
1ba585e8 IT |
9223 | /* VEX_LEN_0F41_P_2 */ |
9224 | { | |
9225 | { Bad_Opcode }, | |
9226 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9227 | }, | |
43234a1e L |
9228 | /* VEX_LEN_0F42_P_0 */ |
9229 | { | |
9230 | { Bad_Opcode }, | |
9231 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9232 | }, | |
1ba585e8 IT |
9233 | /* VEX_LEN_0F42_P_2 */ |
9234 | { | |
9235 | { Bad_Opcode }, | |
9236 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9237 | }, | |
43234a1e L |
9238 | /* VEX_LEN_0F44_P_0 */ |
9239 | { | |
9240 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9241 | }, | |
1ba585e8 IT |
9242 | /* VEX_LEN_0F44_P_2 */ |
9243 | { | |
9244 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9245 | }, | |
43234a1e L |
9246 | /* VEX_LEN_0F45_P_0 */ |
9247 | { | |
9248 | { Bad_Opcode }, | |
9249 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9250 | }, | |
1ba585e8 IT |
9251 | /* VEX_LEN_0F45_P_2 */ |
9252 | { | |
9253 | { Bad_Opcode }, | |
9254 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9255 | }, | |
43234a1e L |
9256 | /* VEX_LEN_0F46_P_0 */ |
9257 | { | |
9258 | { Bad_Opcode }, | |
9259 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9260 | }, | |
1ba585e8 IT |
9261 | /* VEX_LEN_0F46_P_2 */ |
9262 | { | |
9263 | { Bad_Opcode }, | |
9264 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9265 | }, | |
43234a1e L |
9266 | /* VEX_LEN_0F47_P_0 */ |
9267 | { | |
9268 | { Bad_Opcode }, | |
9269 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9270 | }, | |
1ba585e8 IT |
9271 | /* VEX_LEN_0F47_P_2 */ |
9272 | { | |
9273 | { Bad_Opcode }, | |
9274 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9275 | }, | |
9276 | /* VEX_LEN_0F4A_P_0 */ | |
9277 | { | |
9278 | { Bad_Opcode }, | |
9279 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9280 | }, | |
9281 | /* VEX_LEN_0F4A_P_2 */ | |
9282 | { | |
9283 | { Bad_Opcode }, | |
9284 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9285 | }, | |
9286 | /* VEX_LEN_0F4B_P_0 */ | |
9287 | { | |
9288 | { Bad_Opcode }, | |
9289 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9290 | }, | |
43234a1e L |
9291 | /* VEX_LEN_0F4B_P_2 */ |
9292 | { | |
9293 | { Bad_Opcode }, | |
9294 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9295 | }, | |
9296 | ||
ec6f095a | 9297 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9298 | { |
ec6f095a | 9299 | { "vmovK", { XMScalar, Edq }, 0 }, |
c0f3af97 L |
9300 | }, |
9301 | ||
ec6f095a | 9302 | /* VEX_LEN_0F77_P_1 */ |
c0f3af97 | 9303 | { |
ec6f095a L |
9304 | { "vzeroupper", { XX }, 0 }, |
9305 | { "vzeroall", { XX }, 0 }, | |
c0f3af97 L |
9306 | }, |
9307 | ||
ec6f095a | 9308 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9309 | { |
5b872f7d | 9310 | { "vmovq", { XMScalar, EXxmm_mq }, 0 }, |
c0f3af97 L |
9311 | }, |
9312 | ||
ec6f095a | 9313 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9314 | { |
ec6f095a | 9315 | { "vmovK", { Edq, XMScalar }, 0 }, |
c0f3af97 L |
9316 | }, |
9317 | ||
ec6f095a | 9318 | /* VEX_LEN_0F90_P_0 */ |
c0f3af97 | 9319 | { |
ec6f095a | 9320 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
c0f3af97 L |
9321 | }, |
9322 | ||
ec6f095a | 9323 | /* VEX_LEN_0F90_P_2 */ |
c0f3af97 | 9324 | { |
ec6f095a | 9325 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
c0f3af97 L |
9326 | }, |
9327 | ||
ec6f095a | 9328 | /* VEX_LEN_0F91_P_0 */ |
c0f3af97 | 9329 | { |
ec6f095a | 9330 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
c0f3af97 L |
9331 | }, |
9332 | ||
ec6f095a | 9333 | /* VEX_LEN_0F91_P_2 */ |
c0f3af97 | 9334 | { |
ec6f095a | 9335 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
c0f3af97 L |
9336 | }, |
9337 | ||
ec6f095a | 9338 | /* VEX_LEN_0F92_P_0 */ |
c0f3af97 | 9339 | { |
ec6f095a | 9340 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
c0f3af97 L |
9341 | }, |
9342 | ||
ec6f095a | 9343 | /* VEX_LEN_0F92_P_2 */ |
c0f3af97 | 9344 | { |
ec6f095a | 9345 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
c0f3af97 L |
9346 | }, |
9347 | ||
ec6f095a | 9348 | /* VEX_LEN_0F92_P_3 */ |
c0f3af97 | 9349 | { |
58a211d2 | 9350 | { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, |
c0f3af97 L |
9351 | }, |
9352 | ||
ec6f095a | 9353 | /* VEX_LEN_0F93_P_0 */ |
c0f3af97 | 9354 | { |
ec6f095a | 9355 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
c0f3af97 L |
9356 | }, |
9357 | ||
ec6f095a | 9358 | /* VEX_LEN_0F93_P_2 */ |
c0f3af97 | 9359 | { |
ec6f095a | 9360 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
c0f3af97 L |
9361 | }, |
9362 | ||
ec6f095a | 9363 | /* VEX_LEN_0F93_P_3 */ |
c0f3af97 | 9364 | { |
58a211d2 | 9365 | { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, |
c0f3af97 L |
9366 | }, |
9367 | ||
ec6f095a | 9368 | /* VEX_LEN_0F98_P_0 */ |
43234a1e L |
9369 | { |
9370 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9371 | }, | |
9372 | ||
1ba585e8 IT |
9373 | /* VEX_LEN_0F98_P_2 */ |
9374 | { | |
9375 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9376 | }, | |
9377 | ||
9378 | /* VEX_LEN_0F99_P_0 */ | |
9379 | { | |
9380 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9381 | }, | |
9382 | ||
9383 | /* VEX_LEN_0F99_P_2 */ | |
9384 | { | |
9385 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9386 | }, | |
9387 | ||
6c30d220 | 9388 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9389 | { |
ec6f095a | 9390 | { "vldmxcsr", { Md }, 0 }, |
c0f3af97 L |
9391 | }, |
9392 | ||
6c30d220 | 9393 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9394 | { |
ec6f095a | 9395 | { "vstmxcsr", { Md }, 0 }, |
c0f3af97 L |
9396 | }, |
9397 | ||
6c30d220 | 9398 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9399 | { |
b50c9f31 | 9400 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
c0f3af97 L |
9401 | }, |
9402 | ||
6c30d220 | 9403 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9404 | { |
b50c9f31 | 9405 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
c0f3af97 L |
9406 | }, |
9407 | ||
6c30d220 | 9408 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9409 | { |
39e0f456 | 9410 | { "vmovq", { EXqVexScalarS, XMScalar }, 0 }, |
c0f3af97 L |
9411 | }, |
9412 | ||
6c30d220 | 9413 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9414 | { |
ec6f095a | 9415 | { "vmaskmovdqu", { XM, XS }, 0 }, |
c0f3af97 L |
9416 | }, |
9417 | ||
6c30d220 | 9418 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9419 | { |
6c30d220 L |
9420 | { Bad_Opcode }, |
9421 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9422 | }, |
9423 | ||
6c30d220 | 9424 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9425 | { |
6c30d220 L |
9426 | { Bad_Opcode }, |
9427 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9428 | }, |
9429 | ||
6c30d220 | 9430 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9431 | { |
6c30d220 L |
9432 | { Bad_Opcode }, |
9433 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9434 | }, |
9435 | ||
6c30d220 | 9436 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9437 | { |
6c30d220 L |
9438 | { Bad_Opcode }, |
9439 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9440 | }, |
9441 | ||
592a252b | 9442 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9443 | { |
ec6f095a | 9444 | { "vphminposuw", { XM, EXx }, 0 }, |
c0f3af97 L |
9445 | }, |
9446 | ||
6c30d220 L |
9447 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9448 | { | |
9449 | { Bad_Opcode }, | |
9450 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9451 | }, | |
9452 | ||
592a252b | 9453 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9454 | { |
ec6f095a | 9455 | { "vaesimc", { XM, EXx }, 0 }, |
a5ff0eb2 L |
9456 | }, |
9457 | ||
f12dc422 L |
9458 | /* VEX_LEN_0F38F2_P_0 */ |
9459 | { | |
bf890a93 | 9460 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
9461 | }, |
9462 | ||
9463 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9464 | { | |
bf890a93 | 9465 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9466 | }, |
9467 | ||
9468 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9469 | { | |
bf890a93 | 9470 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9471 | }, |
9472 | ||
9473 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9474 | { | |
bf890a93 | 9475 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9476 | }, |
9477 | ||
6c30d220 L |
9478 | /* VEX_LEN_0F38F5_P_0 */ |
9479 | { | |
bf890a93 | 9480 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9481 | }, |
9482 | ||
9483 | /* VEX_LEN_0F38F5_P_1 */ | |
9484 | { | |
bf890a93 | 9485 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9486 | }, |
9487 | ||
9488 | /* VEX_LEN_0F38F5_P_3 */ | |
9489 | { | |
bf890a93 | 9490 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9491 | }, |
9492 | ||
9493 | /* VEX_LEN_0F38F6_P_3 */ | |
9494 | { | |
bf890a93 | 9495 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9496 | }, |
9497 | ||
f12dc422 L |
9498 | /* VEX_LEN_0F38F7_P_0 */ |
9499 | { | |
bf890a93 | 9500 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
9501 | }, |
9502 | ||
6c30d220 L |
9503 | /* VEX_LEN_0F38F7_P_1 */ |
9504 | { | |
bf890a93 | 9505 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9506 | }, |
9507 | ||
9508 | /* VEX_LEN_0F38F7_P_2 */ | |
9509 | { | |
bf890a93 | 9510 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9511 | }, |
9512 | ||
9513 | /* VEX_LEN_0F38F7_P_3 */ | |
9514 | { | |
bf890a93 | 9515 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9516 | }, |
9517 | ||
9518 | /* VEX_LEN_0F3A00_P_2 */ | |
9519 | { | |
9520 | { Bad_Opcode }, | |
9521 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
9522 | }, | |
9523 | ||
9524 | /* VEX_LEN_0F3A01_P_2 */ | |
9525 | { | |
9526 | { Bad_Opcode }, | |
9527 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
9528 | }, | |
9529 | ||
592a252b | 9530 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 9531 | { |
592d1631 | 9532 | { Bad_Opcode }, |
592a252b | 9533 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
9534 | }, |
9535 | ||
592a252b | 9536 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 9537 | { |
b50c9f31 | 9538 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
c0f3af97 L |
9539 | }, |
9540 | ||
592a252b | 9541 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 9542 | { |
b50c9f31 | 9543 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
c0f3af97 L |
9544 | }, |
9545 | ||
592a252b | 9546 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 9547 | { |
bf890a93 | 9548 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
9549 | }, |
9550 | ||
592a252b | 9551 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 9552 | { |
bf890a93 | 9553 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
9554 | }, |
9555 | ||
592a252b | 9556 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 9557 | { |
592d1631 | 9558 | { Bad_Opcode }, |
592a252b | 9559 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
9560 | }, |
9561 | ||
592a252b | 9562 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 9563 | { |
592d1631 | 9564 | { Bad_Opcode }, |
592a252b | 9565 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
9566 | }, |
9567 | ||
592a252b | 9568 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 9569 | { |
b50c9f31 | 9570 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
c0f3af97 L |
9571 | }, |
9572 | ||
592a252b | 9573 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 9574 | { |
ec6f095a | 9575 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
c0f3af97 L |
9576 | }, |
9577 | ||
592a252b | 9578 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 9579 | { |
bf890a93 | 9580 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
9581 | }, |
9582 | ||
43234a1e L |
9583 | /* VEX_LEN_0F3A30_P_2 */ |
9584 | { | |
9585 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
9586 | }, | |
9587 | ||
1ba585e8 IT |
9588 | /* VEX_LEN_0F3A31_P_2 */ |
9589 | { | |
9590 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
9591 | }, | |
9592 | ||
43234a1e L |
9593 | /* VEX_LEN_0F3A32_P_2 */ |
9594 | { | |
9595 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
9596 | }, | |
9597 | ||
1ba585e8 IT |
9598 | /* VEX_LEN_0F3A33_P_2 */ |
9599 | { | |
9600 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
9601 | }, | |
9602 | ||
6c30d220 | 9603 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 9604 | { |
6c30d220 L |
9605 | { Bad_Opcode }, |
9606 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
9607 | }, |
9608 | ||
6c30d220 | 9609 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 9610 | { |
6c30d220 L |
9611 | { Bad_Opcode }, |
9612 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
9613 | }, | |
9614 | ||
9615 | /* VEX_LEN_0F3A41_P_2 */ | |
9616 | { | |
ec6f095a | 9617 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
c0f3af97 L |
9618 | }, |
9619 | ||
6c30d220 | 9620 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 9621 | { |
6c30d220 L |
9622 | { Bad_Opcode }, |
9623 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
9624 | }, |
9625 | ||
592a252b | 9626 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 9627 | { |
15c7c1d8 | 9628 | { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9629 | }, |
9630 | ||
592a252b | 9631 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 9632 | { |
15c7c1d8 | 9633 | { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9634 | }, |
9635 | ||
592a252b | 9636 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 9637 | { |
ec6f095a | 9638 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9639 | }, |
9640 | ||
592a252b | 9641 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 9642 | { |
ec6f095a | 9643 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9644 | }, |
9645 | ||
592a252b | 9646 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 9647 | { |
3a2430e0 | 9648 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9649 | }, |
9650 | ||
592a252b | 9651 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 9652 | { |
3a2430e0 | 9653 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9654 | }, |
9655 | ||
592a252b | 9656 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 9657 | { |
3a2430e0 | 9658 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9659 | }, |
9660 | ||
592a252b | 9661 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 9662 | { |
3a2430e0 | 9663 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9664 | }, |
9665 | ||
592a252b | 9666 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 9667 | { |
3a2430e0 | 9668 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9669 | }, |
9670 | ||
592a252b | 9671 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 9672 | { |
3a2430e0 | 9673 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9674 | }, |
9675 | ||
592a252b | 9676 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 9677 | { |
3a2430e0 | 9678 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9679 | }, |
9680 | ||
592a252b | 9681 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 9682 | { |
3a2430e0 | 9683 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9684 | }, |
9685 | ||
592a252b | 9686 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 9687 | { |
ec6f095a | 9688 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
a5ff0eb2 | 9689 | }, |
4c807e72 | 9690 | |
6c30d220 L |
9691 | /* VEX_LEN_0F3AF0_P_3 */ |
9692 | { | |
bf890a93 | 9693 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
9694 | }, |
9695 | ||
ff688e1f L |
9696 | /* VEX_LEN_0FXOP_08_CC */ |
9697 | { | |
be92cb14 | 9698 | { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9699 | }, |
9700 | ||
9701 | /* VEX_LEN_0FXOP_08_CD */ | |
9702 | { | |
be92cb14 | 9703 | { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9704 | }, |
9705 | ||
9706 | /* VEX_LEN_0FXOP_08_CE */ | |
9707 | { | |
be92cb14 | 9708 | { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9709 | }, |
9710 | ||
9711 | /* VEX_LEN_0FXOP_08_CF */ | |
9712 | { | |
be92cb14 | 9713 | { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9714 | }, |
9715 | ||
9716 | /* VEX_LEN_0FXOP_08_EC */ | |
9717 | { | |
be92cb14 | 9718 | { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9719 | }, |
9720 | ||
9721 | /* VEX_LEN_0FXOP_08_ED */ | |
9722 | { | |
be92cb14 | 9723 | { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9724 | }, |
9725 | ||
9726 | /* VEX_LEN_0FXOP_08_EE */ | |
9727 | { | |
be92cb14 | 9728 | { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9729 | }, |
9730 | ||
9731 | /* VEX_LEN_0FXOP_08_EF */ | |
9732 | { | |
be92cb14 | 9733 | { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9734 | }, |
9735 | ||
592a252b | 9736 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 9737 | { |
bf890a93 IT |
9738 | { "vfrczps", { XM, EXxmm }, 0 }, |
9739 | { "vfrczps", { XM, EXymmq }, 0 }, | |
5dd85c99 | 9740 | }, |
4c807e72 | 9741 | |
592a252b | 9742 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 9743 | { |
bf890a93 IT |
9744 | { "vfrczpd", { XM, EXxmm }, 0 }, |
9745 | { "vfrczpd", { XM, EXymmq }, 0 }, | |
5dd85c99 | 9746 | }, |
331d2d0d L |
9747 | }; |
9748 | ||
ad692897 | 9749 | #include "i386-dis-evex-len.h" |
04e2a182 | 9750 | |
9e30b8e0 | 9751 | static const struct dis386 vex_w_table[][2] = { |
43234a1e L |
9752 | { |
9753 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9754 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
9755 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
9756 | }, |
9757 | { | |
9758 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9759 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
9760 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
9761 | }, |
9762 | { | |
9763 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9764 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
9765 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
9766 | }, |
9767 | { | |
9768 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9769 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
9770 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
9771 | }, |
9772 | { | |
9773 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
9774 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
9775 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
9776 | }, |
9777 | { | |
9778 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
9779 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
9780 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
9781 | }, |
9782 | { | |
ec6f095a L |
9783 | /* VEX_W_0F45_P_0_LEN_1 */ |
9784 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, | |
9785 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
9e30b8e0 L |
9786 | }, |
9787 | { | |
ec6f095a L |
9788 | /* VEX_W_0F45_P_2_LEN_1 */ |
9789 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, | |
9790 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
9e30b8e0 L |
9791 | }, |
9792 | { | |
ec6f095a L |
9793 | /* VEX_W_0F46_P_0_LEN_1 */ |
9794 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, | |
9795 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
9e30b8e0 L |
9796 | }, |
9797 | { | |
ec6f095a L |
9798 | /* VEX_W_0F46_P_2_LEN_1 */ |
9799 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, | |
9800 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
9e30b8e0 L |
9801 | }, |
9802 | { | |
ec6f095a L |
9803 | /* VEX_W_0F47_P_0_LEN_1 */ |
9804 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, | |
9805 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
9e30b8e0 L |
9806 | }, |
9807 | { | |
ec6f095a L |
9808 | /* VEX_W_0F47_P_2_LEN_1 */ |
9809 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, | |
9810 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
9e30b8e0 L |
9811 | }, |
9812 | { | |
ec6f095a L |
9813 | /* VEX_W_0F4A_P_0_LEN_1 */ |
9814 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, | |
9815 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
9e30b8e0 L |
9816 | }, |
9817 | { | |
ec6f095a L |
9818 | /* VEX_W_0F4A_P_2_LEN_1 */ |
9819 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, | |
9820 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
9e30b8e0 L |
9821 | }, |
9822 | { | |
ec6f095a L |
9823 | /* VEX_W_0F4B_P_0_LEN_1 */ |
9824 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, | |
9825 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
9e30b8e0 L |
9826 | }, |
9827 | { | |
ec6f095a L |
9828 | /* VEX_W_0F4B_P_2_LEN_1 */ |
9829 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, | |
9e30b8e0 L |
9830 | }, |
9831 | { | |
ec6f095a L |
9832 | /* VEX_W_0F90_P_0_LEN_0 */ |
9833 | { "kmovw", { MaskG, MaskE }, 0 }, | |
9834 | { "kmovq", { MaskG, MaskE }, 0 }, | |
9e30b8e0 L |
9835 | }, |
9836 | { | |
ec6f095a L |
9837 | /* VEX_W_0F90_P_2_LEN_0 */ |
9838 | { "kmovb", { MaskG, MaskBDE }, 0 }, | |
9839 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
9e30b8e0 L |
9840 | }, |
9841 | { | |
ec6f095a L |
9842 | /* VEX_W_0F91_P_0_LEN_0 */ |
9843 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, | |
9844 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
9e30b8e0 L |
9845 | }, |
9846 | { | |
ec6f095a L |
9847 | /* VEX_W_0F91_P_2_LEN_0 */ |
9848 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, | |
9849 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
9e30b8e0 L |
9850 | }, |
9851 | { | |
ec6f095a L |
9852 | /* VEX_W_0F92_P_0_LEN_0 */ |
9853 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, | |
9e30b8e0 L |
9854 | }, |
9855 | { | |
ec6f095a L |
9856 | /* VEX_W_0F92_P_2_LEN_0 */ |
9857 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, | |
9e30b8e0 | 9858 | }, |
9e30b8e0 | 9859 | { |
ec6f095a L |
9860 | /* VEX_W_0F93_P_0_LEN_0 */ |
9861 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, | |
9e30b8e0 L |
9862 | }, |
9863 | { | |
ec6f095a L |
9864 | /* VEX_W_0F93_P_2_LEN_0 */ |
9865 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, | |
9e30b8e0 | 9866 | }, |
9e30b8e0 | 9867 | { |
ec6f095a L |
9868 | /* VEX_W_0F98_P_0_LEN_0 */ |
9869 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, | |
9870 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
9e30b8e0 L |
9871 | }, |
9872 | { | |
ec6f095a L |
9873 | /* VEX_W_0F98_P_2_LEN_0 */ |
9874 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, | |
9875 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
9e30b8e0 L |
9876 | }, |
9877 | { | |
ec6f095a L |
9878 | /* VEX_W_0F99_P_0_LEN_0 */ |
9879 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, | |
9880 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
9e30b8e0 L |
9881 | }, |
9882 | { | |
ec6f095a L |
9883 | /* VEX_W_0F99_P_2_LEN_0 */ |
9884 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, | |
9885 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
9e30b8e0 | 9886 | }, |
9e30b8e0 | 9887 | { |
592a252b | 9888 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 9889 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
9890 | }, |
9891 | { | |
592a252b | 9892 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 9893 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
9894 | }, |
9895 | { | |
592a252b | 9896 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 9897 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
9898 | }, |
9899 | { | |
592a252b | 9900 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 9901 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 9902 | }, |
6431c801 JB |
9903 | { |
9904 | /* VEX_W_0F3813_P_2 */ | |
9905 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, | |
9906 | }, | |
6c30d220 L |
9907 | { |
9908 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 9909 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 9910 | }, |
bcf2684f | 9911 | { |
6c30d220 | 9912 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 9913 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 9914 | }, |
9e30b8e0 | 9915 | { |
6c30d220 | 9916 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 9917 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
9918 | }, |
9919 | { | |
592a252b | 9920 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 9921 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 | 9922 | }, |
53aa04a0 | 9923 | { |
592a252b | 9924 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 9925 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
9926 | }, |
9927 | { | |
592a252b | 9928 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 9929 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
9930 | }, |
9931 | { | |
592a252b | 9932 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 9933 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
9934 | }, |
9935 | { | |
592a252b | 9936 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 9937 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 9938 | }, |
6c30d220 L |
9939 | { |
9940 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 9941 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 9942 | }, |
6c30d220 L |
9943 | { |
9944 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 9945 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
9946 | }, |
9947 | { | |
9948 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 9949 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
9950 | }, |
9951 | { | |
9952 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 9953 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
9954 | }, |
9955 | { | |
9956 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 9957 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
9958 | }, |
9959 | { | |
9960 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 9961 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
9962 | }, |
9963 | { | |
9964 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 9965 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 9966 | }, |
48521003 IT |
9967 | { |
9968 | /* VEX_W_0F38CF_P_2 */ | |
9969 | { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, | |
9970 | }, | |
6c30d220 L |
9971 | { |
9972 | /* VEX_W_0F3A00_P_2 */ | |
9973 | { Bad_Opcode }, | |
bf890a93 | 9974 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
9975 | }, |
9976 | { | |
9977 | /* VEX_W_0F3A01_P_2 */ | |
9978 | { Bad_Opcode }, | |
bf890a93 | 9979 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
9980 | }, |
9981 | { | |
9982 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 9983 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 9984 | }, |
9e30b8e0 | 9985 | { |
592a252b | 9986 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 9987 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
9988 | }, |
9989 | { | |
592a252b | 9990 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 9991 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
9992 | }, |
9993 | { | |
592a252b | 9994 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 9995 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 | 9996 | }, |
9e30b8e0 | 9997 | { |
592a252b | 9998 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 9999 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
10000 | }, |
10001 | { | |
592a252b | 10002 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 10003 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 | 10004 | }, |
6431c801 JB |
10005 | { |
10006 | /* VEX_W_0F3A1D_P_2 */ | |
10007 | { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 }, | |
10008 | }, | |
43234a1e | 10009 | { |
1ba585e8 | 10010 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
10011 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
10012 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
10013 | }, |
10014 | { | |
1ba585e8 | 10015 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
10016 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
10017 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
10018 | }, |
10019 | { | |
10020 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10021 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
10022 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 10023 | }, |
1ba585e8 IT |
10024 | { |
10025 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10026 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
10027 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 10028 | }, |
6c30d220 L |
10029 | { |
10030 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 10031 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
10032 | }, |
10033 | { | |
10034 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 10035 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 10036 | }, |
6c30d220 L |
10037 | { |
10038 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 10039 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 10040 | }, |
a683cc34 | 10041 | { |
592a252b | 10042 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
10043 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10044 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
10045 | }, |
10046 | { | |
592a252b | 10047 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
10048 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10049 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 10050 | }, |
9e30b8e0 | 10051 | { |
592a252b | 10052 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 10053 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10054 | }, |
10055 | { | |
592a252b | 10056 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 10057 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10058 | }, |
10059 | { | |
592a252b | 10060 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 10061 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 10062 | }, |
48521003 IT |
10063 | { |
10064 | /* VEX_W_0F3ACE_P_2 */ | |
10065 | { Bad_Opcode }, | |
10066 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, | |
10067 | }, | |
10068 | { | |
10069 | /* VEX_W_0F3ACF_P_2 */ | |
10070 | { Bad_Opcode }, | |
10071 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, | |
10072 | }, | |
ad692897 L |
10073 | |
10074 | #include "i386-dis-evex-w.h" | |
9e30b8e0 L |
10075 | }; |
10076 | ||
10077 | static const struct dis386 mod_table[][2] = { | |
10078 | { | |
10079 | /* MOD_8D */ | |
bf890a93 | 10080 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 10081 | }, |
42164a71 L |
10082 | { |
10083 | /* MOD_C6_REG_7 */ | |
10084 | { Bad_Opcode }, | |
10085 | { RM_TABLE (RM_C6_REG_7) }, | |
10086 | }, | |
10087 | { | |
10088 | /* MOD_C7_REG_7 */ | |
10089 | { Bad_Opcode }, | |
10090 | { RM_TABLE (RM_C7_REG_7) }, | |
10091 | }, | |
4a357820 MZ |
10092 | { |
10093 | /* MOD_FF_REG_3 */ | |
8f570d62 | 10094 | { "{l|}call^", { indirEp }, 0 }, |
4a357820 MZ |
10095 | }, |
10096 | { | |
10097 | /* MOD_FF_REG_5 */ | |
8f570d62 | 10098 | { "{l|}jmp^", { indirEp }, 0 }, |
4a357820 | 10099 | }, |
9e30b8e0 L |
10100 | { |
10101 | /* MOD_0F01_REG_0 */ | |
10102 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
10103 | { RM_TABLE (RM_0F01_REG_0) }, | |
10104 | }, | |
10105 | { | |
10106 | /* MOD_0F01_REG_1 */ | |
10107 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
10108 | { RM_TABLE (RM_0F01_REG_1) }, | |
10109 | }, | |
10110 | { | |
10111 | /* MOD_0F01_REG_2 */ | |
10112 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
10113 | { RM_TABLE (RM_0F01_REG_2) }, | |
10114 | }, | |
10115 | { | |
10116 | /* MOD_0F01_REG_3 */ | |
10117 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
10118 | { RM_TABLE (RM_0F01_REG_3) }, | |
10119 | }, | |
8eab4136 L |
10120 | { |
10121 | /* MOD_0F01_REG_5 */ | |
f8687e93 JB |
10122 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, |
10123 | { RM_TABLE (RM_0F01_REG_5_MOD_3) }, | |
8eab4136 | 10124 | }, |
9e30b8e0 L |
10125 | { |
10126 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 10127 | { "invlpg", { Mb }, 0 }, |
f8687e93 | 10128 | { RM_TABLE (RM_0F01_REG_7_MOD_3) }, |
9e30b8e0 L |
10129 | }, |
10130 | { | |
10131 | /* MOD_0F12_PREFIX_0 */ | |
18897deb JB |
10132 | { "movlpX", { XM, EXq }, 0 }, |
10133 | { "movhlps", { XM, EXq }, 0 }, | |
10134 | }, | |
10135 | { | |
10136 | /* MOD_0F12_PREFIX_2 */ | |
10137 | { "movlpX", { XM, EXq }, 0 }, | |
9e30b8e0 L |
10138 | }, |
10139 | { | |
10140 | /* MOD_0F13 */ | |
507bd325 | 10141 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10142 | }, |
10143 | { | |
10144 | /* MOD_0F16_PREFIX_0 */ | |
18897deb | 10145 | { "movhpX", { XM, EXq }, 0 }, |
bf890a93 | 10146 | { "movlhps", { XM, EXq }, 0 }, |
9e30b8e0 | 10147 | }, |
18897deb JB |
10148 | { |
10149 | /* MOD_0F16_PREFIX_2 */ | |
10150 | { "movhpX", { XM, EXq }, 0 }, | |
10151 | }, | |
9e30b8e0 L |
10152 | { |
10153 | /* MOD_0F17 */ | |
507bd325 | 10154 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10155 | }, |
10156 | { | |
10157 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 10158 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
10159 | }, |
10160 | { | |
10161 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 10162 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
10163 | }, |
10164 | { | |
10165 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 10166 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
10167 | }, |
10168 | { | |
10169 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 10170 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 10171 | }, |
d7189fa5 RM |
10172 | { |
10173 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 10174 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10175 | }, |
10176 | { | |
10177 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 10178 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10179 | }, |
10180 | { | |
10181 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 10182 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10183 | }, |
10184 | { | |
10185 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 10186 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 10187 | }, |
7e8b059b L |
10188 | { |
10189 | /* MOD_0F1A_PREFIX_0 */ | |
d276ec69 | 10190 | { "bndldx", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10191 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10192 | }, |
10193 | { | |
10194 | /* MOD_0F1B_PREFIX_0 */ | |
d276ec69 | 10195 | { "bndstx", { Mv_bnd, Gbnd }, 0 }, |
bf890a93 | 10196 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10197 | }, |
10198 | { | |
10199 | /* MOD_0F1B_PREFIX_1 */ | |
d276ec69 | 10200 | { "bndmk", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10201 | { "nopQ", { Ev }, 0 }, |
7e8b059b | 10202 | }, |
c48935d7 IT |
10203 | { |
10204 | /* MOD_0F1C_PREFIX_0 */ | |
f8687e93 | 10205 | { REG_TABLE (REG_0F1C_P_0_MOD_0) }, |
c48935d7 IT |
10206 | { "nopQ", { Ev }, 0 }, |
10207 | }, | |
603555e5 L |
10208 | { |
10209 | /* MOD_0F1E_PREFIX_1 */ | |
10210 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 10211 | { REG_TABLE (REG_0F1E_P_1_MOD_3) }, |
603555e5 | 10212 | }, |
b844680a | 10213 | { |
92fddf8e | 10214 | /* MOD_0F24 */ |
7bb15c6f | 10215 | { Bad_Opcode }, |
bf890a93 | 10216 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
10217 | }, |
10218 | { | |
92fddf8e | 10219 | /* MOD_0F26 */ |
592d1631 | 10220 | { Bad_Opcode }, |
bf890a93 | 10221 | { "movL", { Td, Rd }, 0 }, |
b844680a | 10222 | }, |
75c135a8 L |
10223 | { |
10224 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 10225 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10226 | }, |
10227 | { | |
10228 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 10229 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10230 | }, |
10231 | { | |
10232 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 10233 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10234 | }, |
10235 | { | |
10236 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 10237 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10238 | }, |
10239 | { | |
a5aaedb9 | 10240 | /* MOD_0F50 */ |
592d1631 | 10241 | { Bad_Opcode }, |
507bd325 | 10242 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 10243 | }, |
b844680a | 10244 | { |
1ceb70f8 | 10245 | /* MOD_0F71_REG_2 */ |
592d1631 | 10246 | { Bad_Opcode }, |
bf890a93 | 10247 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
10248 | }, |
10249 | { | |
1ceb70f8 | 10250 | /* MOD_0F71_REG_4 */ |
592d1631 | 10251 | { Bad_Opcode }, |
bf890a93 | 10252 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
10253 | }, |
10254 | { | |
1ceb70f8 | 10255 | /* MOD_0F71_REG_6 */ |
592d1631 | 10256 | { Bad_Opcode }, |
bf890a93 | 10257 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
10258 | }, |
10259 | { | |
1ceb70f8 | 10260 | /* MOD_0F72_REG_2 */ |
592d1631 | 10261 | { Bad_Opcode }, |
bf890a93 | 10262 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
10263 | }, |
10264 | { | |
1ceb70f8 | 10265 | /* MOD_0F72_REG_4 */ |
592d1631 | 10266 | { Bad_Opcode }, |
bf890a93 | 10267 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
10268 | }, |
10269 | { | |
1ceb70f8 | 10270 | /* MOD_0F72_REG_6 */ |
592d1631 | 10271 | { Bad_Opcode }, |
bf890a93 | 10272 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
10273 | }, |
10274 | { | |
1ceb70f8 | 10275 | /* MOD_0F73_REG_2 */ |
592d1631 | 10276 | { Bad_Opcode }, |
bf890a93 | 10277 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
10278 | }, |
10279 | { | |
1ceb70f8 | 10280 | /* MOD_0F73_REG_3 */ |
592d1631 | 10281 | { Bad_Opcode }, |
c0f3af97 L |
10282 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
10283 | }, | |
10284 | { | |
10285 | /* MOD_0F73_REG_6 */ | |
592d1631 | 10286 | { Bad_Opcode }, |
bf890a93 | 10287 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
10288 | }, |
10289 | { | |
10290 | /* MOD_0F73_REG_7 */ | |
592d1631 | 10291 | { Bad_Opcode }, |
c0f3af97 L |
10292 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
10293 | }, | |
10294 | { | |
10295 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 10296 | { "fxsave", { FXSAVE }, 0 }, |
f8687e93 | 10297 | { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, |
c0f3af97 L |
10298 | }, |
10299 | { | |
10300 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 10301 | { "fxrstor", { FXSAVE }, 0 }, |
f8687e93 | 10302 | { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, |
c0f3af97 L |
10303 | }, |
10304 | { | |
10305 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 10306 | { "ldmxcsr", { Md }, 0 }, |
f8687e93 | 10307 | { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, |
c0f3af97 L |
10308 | }, |
10309 | { | |
10310 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 10311 | { "stmxcsr", { Md }, 0 }, |
f8687e93 | 10312 | { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, |
c0f3af97 L |
10313 | }, |
10314 | { | |
10315 | /* MOD_0FAE_REG_4 */ | |
f8687e93 JB |
10316 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, |
10317 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, | |
c0f3af97 L |
10318 | }, |
10319 | { | |
10320 | /* MOD_0FAE_REG_5 */ | |
f8687e93 JB |
10321 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) }, |
10322 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, | |
c0f3af97 L |
10323 | }, |
10324 | { | |
10325 | /* MOD_0FAE_REG_6 */ | |
f8687e93 JB |
10326 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, |
10327 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, | |
c0f3af97 L |
10328 | }, |
10329 | { | |
10330 | /* MOD_0FAE_REG_7 */ | |
f8687e93 JB |
10331 | { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, |
10332 | { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, | |
c0f3af97 L |
10333 | }, |
10334 | { | |
10335 | /* MOD_0FB2 */ | |
bf890a93 | 10336 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10337 | }, |
10338 | { | |
10339 | /* MOD_0FB4 */ | |
bf890a93 | 10340 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10341 | }, |
10342 | { | |
10343 | /* MOD_0FB5 */ | |
bf890a93 | 10344 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 10345 | }, |
a8484f96 L |
10346 | { |
10347 | /* MOD_0FC3 */ | |
f8687e93 | 10348 | { PREFIX_TABLE (PREFIX_0FC3_MOD_0) }, |
a8484f96 | 10349 | }, |
963f3586 IT |
10350 | { |
10351 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 10352 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
10353 | }, |
10354 | { | |
10355 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 10356 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
10357 | }, |
10358 | { | |
10359 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 10360 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 10361 | }, |
c0f3af97 L |
10362 | { |
10363 | /* MOD_0FC7_REG_6 */ | |
f8687e93 JB |
10364 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, |
10365 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } | |
c0f3af97 L |
10366 | }, |
10367 | { | |
10368 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 10369 | { "vmptrst", { Mq }, 0 }, |
f8687e93 | 10370 | { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } |
c0f3af97 L |
10371 | }, |
10372 | { | |
10373 | /* MOD_0FD7 */ | |
592d1631 | 10374 | { Bad_Opcode }, |
bf890a93 | 10375 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
10376 | }, |
10377 | { | |
10378 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 10379 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
10380 | }, |
10381 | { | |
10382 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 10383 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
10384 | }, |
10385 | { | |
10386 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 10387 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 | 10388 | }, |
603555e5 L |
10389 | { |
10390 | /* MOD_0F38F5_PREFIX_2 */ | |
10391 | { "wrussK", { M, Gdq }, PREFIX_OPCODE }, | |
10392 | }, | |
10393 | { | |
10394 | /* MOD_0F38F6_PREFIX_0 */ | |
10395 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
10396 | }, | |
5d79adc4 L |
10397 | { |
10398 | /* MOD_0F38F8_PREFIX_1 */ | |
10399 | { "enqcmds", { Gva, M }, PREFIX_OPCODE }, | |
10400 | }, | |
c0a30a9f L |
10401 | { |
10402 | /* MOD_0F38F8_PREFIX_2 */ | |
10403 | { "movdir64b", { Gva, M }, PREFIX_OPCODE }, | |
10404 | }, | |
5d79adc4 L |
10405 | { |
10406 | /* MOD_0F38F8_PREFIX_3 */ | |
10407 | { "enqcmd", { Gva, M }, PREFIX_OPCODE }, | |
10408 | }, | |
c0a30a9f L |
10409 | { |
10410 | /* MOD_0F38F9_PREFIX_0 */ | |
77ad8092 | 10411 | { "movdiri", { Ev, Gv }, PREFIX_OPCODE }, |
c0a30a9f | 10412 | }, |
c0f3af97 L |
10413 | { |
10414 | /* MOD_62_32BIT */ | |
bf890a93 | 10415 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 10416 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
10417 | }, |
10418 | { | |
10419 | /* MOD_C4_32BIT */ | |
bf890a93 | 10420 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10421 | { VEX_C4_TABLE (VEX_0F) }, |
10422 | }, | |
10423 | { | |
10424 | /* MOD_C5_32BIT */ | |
bf890a93 | 10425 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10426 | { VEX_C5_TABLE (VEX_0F) }, |
10427 | }, | |
10428 | { | |
592a252b L |
10429 | /* MOD_VEX_0F12_PREFIX_0 */ |
10430 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
10431 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 | 10432 | }, |
18897deb JB |
10433 | { |
10434 | /* MOD_VEX_0F12_PREFIX_2 */ | |
10435 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) }, | |
10436 | }, | |
c0f3af97 | 10437 | { |
592a252b L |
10438 | /* MOD_VEX_0F13 */ |
10439 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
10440 | }, |
10441 | { | |
592a252b L |
10442 | /* MOD_VEX_0F16_PREFIX_0 */ |
10443 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
10444 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 | 10445 | }, |
18897deb JB |
10446 | { |
10447 | /* MOD_VEX_0F16_PREFIX_2 */ | |
10448 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) }, | |
10449 | }, | |
c0f3af97 | 10450 | { |
592a252b L |
10451 | /* MOD_VEX_0F17 */ |
10452 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
10453 | }, |
10454 | { | |
592a252b | 10455 | /* MOD_VEX_0F2B */ |
bf926894 | 10456 | { "vmovntpX", { Mx, XM }, PREFIX_OPCODE }, |
c0f3af97 | 10457 | }, |
ab4e4ed5 AF |
10458 | { |
10459 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
10460 | { Bad_Opcode }, | |
10461 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
10462 | }, | |
10463 | { | |
10464 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
10465 | { Bad_Opcode }, | |
10466 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
10467 | }, | |
10468 | { | |
10469 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
10470 | { Bad_Opcode }, | |
10471 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
10472 | }, | |
10473 | { | |
10474 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
10475 | { Bad_Opcode }, | |
10476 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
10477 | }, | |
10478 | { | |
10479 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
10480 | { Bad_Opcode }, | |
10481 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
10482 | }, | |
10483 | { | |
10484 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
10485 | { Bad_Opcode }, | |
10486 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
10487 | }, | |
10488 | { | |
10489 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
10490 | { Bad_Opcode }, | |
10491 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
10492 | }, | |
10493 | { | |
10494 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
10495 | { Bad_Opcode }, | |
10496 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
10497 | }, | |
10498 | { | |
10499 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
10500 | { Bad_Opcode }, | |
10501 | { "knotw", { MaskG, MaskR }, 0 }, | |
10502 | }, | |
10503 | { | |
10504 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
10505 | { Bad_Opcode }, | |
10506 | { "knotq", { MaskG, MaskR }, 0 }, | |
10507 | }, | |
10508 | { | |
10509 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
10510 | { Bad_Opcode }, | |
10511 | { "knotb", { MaskG, MaskR }, 0 }, | |
10512 | }, | |
10513 | { | |
10514 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
10515 | { Bad_Opcode }, | |
10516 | { "knotd", { MaskG, MaskR }, 0 }, | |
10517 | }, | |
10518 | { | |
10519 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
10520 | { Bad_Opcode }, | |
10521 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
10522 | }, | |
10523 | { | |
10524 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
10525 | { Bad_Opcode }, | |
10526 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
10527 | }, | |
10528 | { | |
10529 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
10530 | { Bad_Opcode }, | |
10531 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
10532 | }, | |
10533 | { | |
10534 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
10535 | { Bad_Opcode }, | |
10536 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
10537 | }, | |
10538 | { | |
10539 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
10540 | { Bad_Opcode }, | |
10541 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10542 | }, | |
10543 | { | |
10544 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
10545 | { Bad_Opcode }, | |
10546 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10547 | }, | |
10548 | { | |
10549 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
10550 | { Bad_Opcode }, | |
10551 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10552 | }, | |
10553 | { | |
10554 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
10555 | { Bad_Opcode }, | |
10556 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
10557 | }, | |
10558 | { | |
10559 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
10560 | { Bad_Opcode }, | |
10561 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10562 | }, | |
10563 | { | |
10564 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
10565 | { Bad_Opcode }, | |
10566 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10567 | }, | |
10568 | { | |
10569 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
10570 | { Bad_Opcode }, | |
10571 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10572 | }, | |
10573 | { | |
10574 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
10575 | { Bad_Opcode }, | |
10576 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
10577 | }, | |
10578 | { | |
10579 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
10580 | { Bad_Opcode }, | |
10581 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
10582 | }, | |
10583 | { | |
10584 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
10585 | { Bad_Opcode }, | |
10586 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
10587 | }, | |
10588 | { | |
10589 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
10590 | { Bad_Opcode }, | |
10591 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
10592 | }, | |
10593 | { | |
10594 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
10595 | { Bad_Opcode }, | |
10596 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
10597 | }, | |
10598 | { | |
10599 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
10600 | { Bad_Opcode }, | |
10601 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
10602 | }, | |
10603 | { | |
10604 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
10605 | { Bad_Opcode }, | |
10606 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
10607 | }, | |
10608 | { | |
10609 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
10610 | { Bad_Opcode }, | |
10611 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
10612 | }, | |
c0f3af97 | 10613 | { |
592a252b | 10614 | /* MOD_VEX_0F50 */ |
592d1631 | 10615 | { Bad_Opcode }, |
bf926894 | 10616 | { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
c0f3af97 L |
10617 | }, |
10618 | { | |
592a252b | 10619 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 10620 | { Bad_Opcode }, |
592a252b | 10621 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
10622 | }, |
10623 | { | |
592a252b | 10624 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 10625 | { Bad_Opcode }, |
592a252b | 10626 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
10627 | }, |
10628 | { | |
592a252b | 10629 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 10630 | { Bad_Opcode }, |
592a252b | 10631 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
10632 | }, |
10633 | { | |
592a252b | 10634 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 10635 | { Bad_Opcode }, |
592a252b | 10636 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 10637 | }, |
d8faab4e | 10638 | { |
592a252b | 10639 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 10640 | { Bad_Opcode }, |
592a252b | 10641 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
10642 | }, |
10643 | { | |
592a252b | 10644 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 10645 | { Bad_Opcode }, |
592a252b | 10646 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 10647 | }, |
876d4bfa | 10648 | { |
592a252b | 10649 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 10650 | { Bad_Opcode }, |
592a252b | 10651 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
10652 | }, |
10653 | { | |
592a252b | 10654 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 10655 | { Bad_Opcode }, |
592a252b | 10656 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
10657 | }, |
10658 | { | |
592a252b | 10659 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 10660 | { Bad_Opcode }, |
592a252b | 10661 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
10662 | }, |
10663 | { | |
592a252b | 10664 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 10665 | { Bad_Opcode }, |
592a252b | 10666 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 10667 | }, |
ab4e4ed5 AF |
10668 | { |
10669 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10670 | { "kmovw", { Ew, MaskG }, 0 }, | |
10671 | { Bad_Opcode }, | |
10672 | }, | |
10673 | { | |
10674 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10675 | { "kmovq", { Eq, MaskG }, 0 }, | |
10676 | { Bad_Opcode }, | |
10677 | }, | |
10678 | { | |
10679 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10680 | { "kmovb", { Eb, MaskG }, 0 }, | |
10681 | { Bad_Opcode }, | |
10682 | }, | |
10683 | { | |
10684 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10685 | { "kmovd", { Ed, MaskG }, 0 }, | |
10686 | { Bad_Opcode }, | |
10687 | }, | |
10688 | { | |
10689 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
10690 | { Bad_Opcode }, | |
10691 | { "kmovw", { MaskG, Rdq }, 0 }, | |
10692 | }, | |
10693 | { | |
10694 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
10695 | { Bad_Opcode }, | |
10696 | { "kmovb", { MaskG, Rdq }, 0 }, | |
10697 | }, | |
10698 | { | |
58a211d2 | 10699 | /* MOD_VEX_0F92_P_3_LEN_0 */ |
ab4e4ed5 | 10700 | { Bad_Opcode }, |
58a211d2 | 10701 | { "kmovK", { MaskG, Rdq }, 0 }, |
ab4e4ed5 AF |
10702 | }, |
10703 | { | |
10704 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
10705 | { Bad_Opcode }, | |
10706 | { "kmovw", { Gdq, MaskR }, 0 }, | |
10707 | }, | |
10708 | { | |
10709 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
10710 | { Bad_Opcode }, | |
10711 | { "kmovb", { Gdq, MaskR }, 0 }, | |
10712 | }, | |
10713 | { | |
58a211d2 | 10714 | /* MOD_VEX_0F93_P_3_LEN_0 */ |
ab4e4ed5 | 10715 | { Bad_Opcode }, |
58a211d2 | 10716 | { "kmovK", { Gdq, MaskR }, 0 }, |
ab4e4ed5 AF |
10717 | }, |
10718 | { | |
10719 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
10720 | { Bad_Opcode }, | |
10721 | { "kortestw", { MaskG, MaskR }, 0 }, | |
10722 | }, | |
10723 | { | |
10724 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
10725 | { Bad_Opcode }, | |
10726 | { "kortestq", { MaskG, MaskR }, 0 }, | |
10727 | }, | |
10728 | { | |
10729 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
10730 | { Bad_Opcode }, | |
10731 | { "kortestb", { MaskG, MaskR }, 0 }, | |
10732 | }, | |
10733 | { | |
10734 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
10735 | { Bad_Opcode }, | |
10736 | { "kortestd", { MaskG, MaskR }, 0 }, | |
10737 | }, | |
10738 | { | |
10739 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
10740 | { Bad_Opcode }, | |
10741 | { "ktestw", { MaskG, MaskR }, 0 }, | |
10742 | }, | |
10743 | { | |
10744 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
10745 | { Bad_Opcode }, | |
10746 | { "ktestq", { MaskG, MaskR }, 0 }, | |
10747 | }, | |
10748 | { | |
10749 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
10750 | { Bad_Opcode }, | |
10751 | { "ktestb", { MaskG, MaskR }, 0 }, | |
10752 | }, | |
10753 | { | |
10754 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
10755 | { Bad_Opcode }, | |
10756 | { "ktestd", { MaskG, MaskR }, 0 }, | |
10757 | }, | |
876d4bfa | 10758 | { |
592a252b L |
10759 | /* MOD_VEX_0FAE_REG_2 */ |
10760 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 10761 | }, |
bbedc832 | 10762 | { |
592a252b L |
10763 | /* MOD_VEX_0FAE_REG_3 */ |
10764 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 10765 | }, |
144c41d9 | 10766 | { |
592a252b | 10767 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 10768 | { Bad_Opcode }, |
ec6f095a | 10769 | { "vpmovmskb", { Gdq, XS }, 0 }, |
144c41d9 | 10770 | }, |
1afd85e3 | 10771 | { |
592a252b | 10772 | /* MOD_VEX_0FE7_PREFIX_2 */ |
ec6f095a | 10773 | { "vmovntdq", { Mx, XM }, 0 }, |
1afd85e3 L |
10774 | }, |
10775 | { | |
592a252b | 10776 | /* MOD_VEX_0FF0_PREFIX_3 */ |
ec6f095a | 10777 | { "vlddqu", { XM, M }, 0 }, |
92fddf8e | 10778 | }, |
75c135a8 | 10779 | { |
592a252b L |
10780 | /* MOD_VEX_0F381A_PREFIX_2 */ |
10781 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 10782 | }, |
1afd85e3 | 10783 | { |
592a252b | 10784 | /* MOD_VEX_0F382A_PREFIX_2 */ |
ec6f095a | 10785 | { "vmovntdqa", { XM, Mx }, 0 }, |
1afd85e3 | 10786 | }, |
75c135a8 | 10787 | { |
592a252b L |
10788 | /* MOD_VEX_0F382C_PREFIX_2 */ |
10789 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 10790 | }, |
1afd85e3 | 10791 | { |
592a252b L |
10792 | /* MOD_VEX_0F382D_PREFIX_2 */ |
10793 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
10794 | }, |
10795 | { | |
592a252b L |
10796 | /* MOD_VEX_0F382E_PREFIX_2 */ |
10797 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
10798 | }, |
10799 | { | |
592a252b L |
10800 | /* MOD_VEX_0F382F_PREFIX_2 */ |
10801 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 10802 | }, |
6c30d220 L |
10803 | { |
10804 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
10805 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
10806 | }, | |
10807 | { | |
10808 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 10809 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
10810 | }, |
10811 | { | |
10812 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 10813 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 10814 | }, |
ab4e4ed5 AF |
10815 | { |
10816 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
10817 | { Bad_Opcode }, | |
10818 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
10819 | }, | |
10820 | { | |
10821 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
10822 | { Bad_Opcode }, | |
10823 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
10824 | }, | |
10825 | { | |
10826 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
10827 | { Bad_Opcode }, | |
10828 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
10829 | }, | |
10830 | { | |
10831 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
10832 | { Bad_Opcode }, | |
10833 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
10834 | }, | |
10835 | { | |
10836 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
10837 | { Bad_Opcode }, | |
10838 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
10839 | }, | |
10840 | { | |
10841 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
10842 | { Bad_Opcode }, | |
10843 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
10844 | }, | |
10845 | { | |
10846 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
10847 | { Bad_Opcode }, | |
10848 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
10849 | }, | |
10850 | { | |
10851 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
10852 | { Bad_Opcode }, | |
10853 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
10854 | }, | |
ad692897 L |
10855 | |
10856 | #include "i386-dis-evex-mod.h" | |
b844680a L |
10857 | }; |
10858 | ||
1ceb70f8 | 10859 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
10860 | { |
10861 | /* RM_C6_REG_7 */ | |
bf890a93 | 10862 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
10863 | }, |
10864 | { | |
10865 | /* RM_C7_REG_7 */ | |
376cd056 | 10866 | { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, |
42164a71 | 10867 | }, |
b844680a | 10868 | { |
1ceb70f8 | 10869 | /* RM_0F01_REG_0 */ |
a4e78aa5 | 10870 | { "enclv", { Skip_MODRM }, 0 }, |
bf890a93 IT |
10871 | { "vmcall", { Skip_MODRM }, 0 }, |
10872 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
10873 | { "vmresume", { Skip_MODRM }, 0 }, | |
10874 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 10875 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
10876 | }, |
10877 | { | |
1ceb70f8 | 10878 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
10879 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
10880 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
10881 | { "clac", { Skip_MODRM }, 0 }, | |
10882 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
10883 | { Bad_Opcode }, |
10884 | { Bad_Opcode }, | |
10885 | { Bad_Opcode }, | |
bf890a93 | 10886 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 10887 | }, |
475a2301 L |
10888 | { |
10889 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
10890 | { "xgetbv", { Skip_MODRM }, 0 }, |
10891 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
10892 | { Bad_Opcode }, |
10893 | { Bad_Opcode }, | |
bf890a93 IT |
10894 | { "vmfunc", { Skip_MODRM }, 0 }, |
10895 | { "xend", { Skip_MODRM }, 0 }, | |
10896 | { "xtest", { Skip_MODRM }, 0 }, | |
10897 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 10898 | }, |
b844680a | 10899 | { |
1ceb70f8 | 10900 | /* RM_0F01_REG_3 */ |
bf890a93 | 10901 | { "vmrun", { Skip_MODRM }, 0 }, |
a847e322 | 10902 | { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) }, |
bf890a93 IT |
10903 | { "vmload", { Skip_MODRM }, 0 }, |
10904 | { "vmsave", { Skip_MODRM }, 0 }, | |
10905 | { "stgi", { Skip_MODRM }, 0 }, | |
10906 | { "clgi", { Skip_MODRM }, 0 }, | |
10907 | { "skinit", { Skip_MODRM }, 0 }, | |
10908 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 10909 | }, |
8eab4136 | 10910 | { |
f8687e93 JB |
10911 | /* RM_0F01_REG_5_MOD_3 */ |
10912 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, | |
bb651e8b | 10913 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) }, |
f8687e93 | 10914 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, |
8eab4136 L |
10915 | { Bad_Opcode }, |
10916 | { Bad_Opcode }, | |
10917 | { Bad_Opcode }, | |
10918 | { "rdpkru", { Skip_MODRM }, 0 }, | |
10919 | { "wrpkru", { Skip_MODRM }, 0 }, | |
10920 | }, | |
4e7d34a6 | 10921 | { |
f8687e93 | 10922 | /* RM_0F01_REG_7_MOD_3 */ |
bf890a93 IT |
10923 | { "swapgs", { Skip_MODRM }, 0 }, |
10924 | { "rdtscp", { Skip_MODRM }, 0 }, | |
267b8516 JB |
10925 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, |
10926 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) }, | |
bf890a93 | 10927 | { "clzero", { Skip_MODRM }, 0 }, |
142861df | 10928 | { "rdpru", { Skip_MODRM }, 0 }, |
b844680a | 10929 | }, |
603555e5 | 10930 | { |
f8687e93 | 10931 | /* RM_0F1E_P_1_MOD_3_REG_7 */ |
603555e5 L |
10932 | { "nopQ", { Ev }, 0 }, |
10933 | { "nopQ", { Ev }, 0 }, | |
10934 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
10935 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
10936 | { "nopQ", { Ev }, 0 }, | |
10937 | { "nopQ", { Ev }, 0 }, | |
10938 | { "nopQ", { Ev }, 0 }, | |
10939 | { "nopQ", { Ev }, 0 }, | |
10940 | }, | |
b844680a | 10941 | { |
f8687e93 | 10942 | /* RM_0FAE_REG_6_MOD_3 */ |
bf890a93 | 10943 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 10944 | }, |
bbedc832 | 10945 | { |
f8687e93 | 10946 | /* RM_0FAE_REG_7_MOD_3 */ |
b5cefcca L |
10947 | { "sfence", { Skip_MODRM }, 0 }, |
10948 | ||
144c41d9 | 10949 | }, |
b844680a L |
10950 | }; |
10951 | ||
c608c12e AM |
10952 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
10953 | ||
f16cd0d5 L |
10954 | /* We use the high bit to indicate different name for the same |
10955 | prefix. */ | |
f16cd0d5 | 10956 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
10957 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
10958 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 10959 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 10960 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 | 10961 | |
1d67fe3b TT |
10962 | /* Remember if the current op is a jump instruction. */ |
10963 | static bfd_boolean op_is_jump = FALSE; | |
10964 | ||
f16cd0d5 | 10965 | static int |
26ca5450 | 10966 | ckprefix (void) |
252b5132 | 10967 | { |
f16cd0d5 | 10968 | int newrex, i, length; |
52b15da3 | 10969 | rex = 0; |
252b5132 | 10970 | prefixes = 0; |
7d421014 | 10971 | used_prefixes = 0; |
52b15da3 | 10972 | rex_used = 0; |
f16cd0d5 L |
10973 | last_lock_prefix = -1; |
10974 | last_repz_prefix = -1; | |
10975 | last_repnz_prefix = -1; | |
10976 | last_data_prefix = -1; | |
10977 | last_addr_prefix = -1; | |
10978 | last_rex_prefix = -1; | |
10979 | last_seg_prefix = -1; | |
d9949a36 | 10980 | fwait_prefix = -1; |
285ca992 | 10981 | active_seg_prefix = 0; |
f310f33d L |
10982 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
10983 | all_prefixes[i] = 0; | |
10984 | i = 0; | |
f16cd0d5 L |
10985 | length = 0; |
10986 | /* The maximum instruction length is 15bytes. */ | |
10987 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
10988 | { |
10989 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 10990 | newrex = 0; |
252b5132 RH |
10991 | switch (*codep) |
10992 | { | |
52b15da3 JH |
10993 | /* REX prefixes family. */ |
10994 | case 0x40: | |
10995 | case 0x41: | |
10996 | case 0x42: | |
10997 | case 0x43: | |
10998 | case 0x44: | |
10999 | case 0x45: | |
11000 | case 0x46: | |
11001 | case 0x47: | |
11002 | case 0x48: | |
11003 | case 0x49: | |
11004 | case 0x4a: | |
11005 | case 0x4b: | |
11006 | case 0x4c: | |
11007 | case 0x4d: | |
11008 | case 0x4e: | |
11009 | case 0x4f: | |
f16cd0d5 L |
11010 | if (address_mode == mode_64bit) |
11011 | newrex = *codep; | |
11012 | else | |
11013 | return 1; | |
11014 | last_rex_prefix = i; | |
52b15da3 | 11015 | break; |
252b5132 RH |
11016 | case 0xf3: |
11017 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 11018 | last_repz_prefix = i; |
252b5132 RH |
11019 | break; |
11020 | case 0xf2: | |
11021 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 11022 | last_repnz_prefix = i; |
252b5132 RH |
11023 | break; |
11024 | case 0xf0: | |
11025 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 11026 | last_lock_prefix = i; |
252b5132 RH |
11027 | break; |
11028 | case 0x2e: | |
11029 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 11030 | last_seg_prefix = i; |
285ca992 | 11031 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
11032 | break; |
11033 | case 0x36: | |
11034 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 11035 | last_seg_prefix = i; |
285ca992 | 11036 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
11037 | break; |
11038 | case 0x3e: | |
11039 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 11040 | last_seg_prefix = i; |
285ca992 | 11041 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
11042 | break; |
11043 | case 0x26: | |
11044 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 11045 | last_seg_prefix = i; |
285ca992 | 11046 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
11047 | break; |
11048 | case 0x64: | |
11049 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 11050 | last_seg_prefix = i; |
285ca992 | 11051 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
11052 | break; |
11053 | case 0x65: | |
11054 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 11055 | last_seg_prefix = i; |
285ca992 | 11056 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
11057 | break; |
11058 | case 0x66: | |
11059 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 11060 | last_data_prefix = i; |
252b5132 RH |
11061 | break; |
11062 | case 0x67: | |
11063 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 11064 | last_addr_prefix = i; |
252b5132 | 11065 | break; |
5076851f | 11066 | case FWAIT_OPCODE: |
252b5132 RH |
11067 | /* fwait is really an instruction. If there are prefixes |
11068 | before the fwait, they belong to the fwait, *not* to the | |
11069 | following instruction. */ | |
d9949a36 | 11070 | fwait_prefix = i; |
3e7d61b2 | 11071 | if (prefixes || rex) |
252b5132 RH |
11072 | { |
11073 | prefixes |= PREFIX_FWAIT; | |
11074 | codep++; | |
6c067bbb RM |
11075 | /* This ensures that the previous REX prefixes are noticed |
11076 | as unused prefixes, as in the return case below. */ | |
11077 | rex_used = rex; | |
f16cd0d5 | 11078 | return 1; |
252b5132 RH |
11079 | } |
11080 | prefixes = PREFIX_FWAIT; | |
11081 | break; | |
11082 | default: | |
f16cd0d5 | 11083 | return 1; |
252b5132 | 11084 | } |
52b15da3 JH |
11085 | /* Rex is ignored when followed by another prefix. */ |
11086 | if (rex) | |
11087 | { | |
3e7d61b2 | 11088 | rex_used = rex; |
f16cd0d5 | 11089 | return 1; |
52b15da3 | 11090 | } |
f16cd0d5 | 11091 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 11092 | all_prefixes[i++] = *codep; |
52b15da3 | 11093 | rex = newrex; |
252b5132 | 11094 | codep++; |
f16cd0d5 L |
11095 | length++; |
11096 | } | |
11097 | return 0; | |
11098 | } | |
11099 | ||
7d421014 ILT |
11100 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
11101 | prefix byte. */ | |
11102 | ||
11103 | static const char * | |
26ca5450 | 11104 | prefix_name (int pref, int sizeflag) |
7d421014 | 11105 | { |
0003779b L |
11106 | static const char *rexes [16] = |
11107 | { | |
11108 | "rex", /* 0x40 */ | |
11109 | "rex.B", /* 0x41 */ | |
11110 | "rex.X", /* 0x42 */ | |
11111 | "rex.XB", /* 0x43 */ | |
11112 | "rex.R", /* 0x44 */ | |
11113 | "rex.RB", /* 0x45 */ | |
11114 | "rex.RX", /* 0x46 */ | |
11115 | "rex.RXB", /* 0x47 */ | |
11116 | "rex.W", /* 0x48 */ | |
11117 | "rex.WB", /* 0x49 */ | |
11118 | "rex.WX", /* 0x4a */ | |
11119 | "rex.WXB", /* 0x4b */ | |
11120 | "rex.WR", /* 0x4c */ | |
11121 | "rex.WRB", /* 0x4d */ | |
11122 | "rex.WRX", /* 0x4e */ | |
11123 | "rex.WRXB", /* 0x4f */ | |
11124 | }; | |
11125 | ||
7d421014 ILT |
11126 | switch (pref) |
11127 | { | |
52b15da3 JH |
11128 | /* REX prefixes family. */ |
11129 | case 0x40: | |
52b15da3 | 11130 | case 0x41: |
52b15da3 | 11131 | case 0x42: |
52b15da3 | 11132 | case 0x43: |
52b15da3 | 11133 | case 0x44: |
52b15da3 | 11134 | case 0x45: |
52b15da3 | 11135 | case 0x46: |
52b15da3 | 11136 | case 0x47: |
52b15da3 | 11137 | case 0x48: |
52b15da3 | 11138 | case 0x49: |
52b15da3 | 11139 | case 0x4a: |
52b15da3 | 11140 | case 0x4b: |
52b15da3 | 11141 | case 0x4c: |
52b15da3 | 11142 | case 0x4d: |
52b15da3 | 11143 | case 0x4e: |
52b15da3 | 11144 | case 0x4f: |
0003779b | 11145 | return rexes [pref - 0x40]; |
7d421014 ILT |
11146 | case 0xf3: |
11147 | return "repz"; | |
11148 | case 0xf2: | |
11149 | return "repnz"; | |
11150 | case 0xf0: | |
11151 | return "lock"; | |
11152 | case 0x2e: | |
11153 | return "cs"; | |
11154 | case 0x36: | |
11155 | return "ss"; | |
11156 | case 0x3e: | |
11157 | return "ds"; | |
11158 | case 0x26: | |
11159 | return "es"; | |
11160 | case 0x64: | |
11161 | return "fs"; | |
11162 | case 0x65: | |
11163 | return "gs"; | |
11164 | case 0x66: | |
11165 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
11166 | case 0x67: | |
cb712a9e | 11167 | if (address_mode == mode_64bit) |
db6eb5be | 11168 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 11169 | else |
2888cb7a | 11170 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
11171 | case FWAIT_OPCODE: |
11172 | return "fwait"; | |
f16cd0d5 L |
11173 | case REP_PREFIX: |
11174 | return "rep"; | |
42164a71 L |
11175 | case XACQUIRE_PREFIX: |
11176 | return "xacquire"; | |
11177 | case XRELEASE_PREFIX: | |
11178 | return "xrelease"; | |
7e8b059b L |
11179 | case BND_PREFIX: |
11180 | return "bnd"; | |
04ef582a L |
11181 | case NOTRACK_PREFIX: |
11182 | return "notrack"; | |
7d421014 ILT |
11183 | default: |
11184 | return NULL; | |
11185 | } | |
11186 | } | |
11187 | ||
ce518a5f L |
11188 | static char op_out[MAX_OPERANDS][100]; |
11189 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 11190 | static int two_source_ops; |
ce518a5f L |
11191 | static bfd_vma op_address[MAX_OPERANDS]; |
11192 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 11193 | static bfd_vma start_pc; |
ce518a5f | 11194 | |
252b5132 RH |
11195 | /* |
11196 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
11197 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
11198 | * section of the "Virtual 8086 Mode" chapter.) | |
11199 | * 'pc' should be the address of this instruction, it will | |
11200 | * be used to print the target address if this is a relative jump or call | |
11201 | * The function returns the length of this instruction in bytes. | |
11202 | */ | |
11203 | ||
252b5132 | 11204 | static char intel_syntax; |
9d141669 | 11205 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
11206 | static char open_char; |
11207 | static char close_char; | |
11208 | static char separator_char; | |
11209 | static char scale_char; | |
11210 | ||
5db04b09 L |
11211 | enum x86_64_isa |
11212 | { | |
d835a58b | 11213 | amd64 = 1, |
5db04b09 L |
11214 | intel64 |
11215 | }; | |
11216 | ||
11217 | static enum x86_64_isa isa64; | |
11218 | ||
e396998b AM |
11219 | /* Here for backwards compatibility. When gdb stops using |
11220 | print_insn_i386_att and print_insn_i386_intel these functions can | |
11221 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 11222 | int |
26ca5450 | 11223 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11224 | { |
11225 | intel_syntax = 0; | |
e396998b AM |
11226 | |
11227 | return print_insn (pc, info); | |
252b5132 RH |
11228 | } |
11229 | ||
11230 | int | |
26ca5450 | 11231 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11232 | { |
11233 | intel_syntax = 1; | |
e396998b AM |
11234 | |
11235 | return print_insn (pc, info); | |
252b5132 RH |
11236 | } |
11237 | ||
e396998b | 11238 | int |
26ca5450 | 11239 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
11240 | { |
11241 | intel_syntax = -1; | |
11242 | ||
11243 | return print_insn (pc, info); | |
11244 | } | |
11245 | ||
f59a29b9 L |
11246 | void |
11247 | print_i386_disassembler_options (FILE *stream) | |
11248 | { | |
11249 | fprintf (stream, _("\n\ | |
11250 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
11251 | with the -M switch (multiple options should be separated by commas):\n")); | |
11252 | ||
11253 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
11254 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
11255 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
11256 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
11257 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
11258 | fprintf (stream, _(" att-mnemonic\n" |
11259 | " Display instruction in AT&T mnemonic\n")); | |
11260 | fprintf (stream, _(" intel-mnemonic\n" | |
11261 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
11262 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
11263 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
11264 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
11265 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
11266 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
11267 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
11268 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
11269 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
11270 | } |
11271 | ||
592d1631 | 11272 | /* Bad opcode. */ |
bf890a93 | 11273 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 11274 | |
b844680a L |
11275 | /* Get a pointer to struct dis386 with a valid name. */ |
11276 | ||
11277 | static const struct dis386 * | |
8bb15339 | 11278 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 11279 | { |
91d6fa6a | 11280 | int vindex, vex_table_index; |
b844680a L |
11281 | |
11282 | if (dp->name != NULL) | |
11283 | return dp; | |
11284 | ||
11285 | switch (dp->op[0].bytemode) | |
11286 | { | |
1ceb70f8 L |
11287 | case USE_REG_TABLE: |
11288 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
11289 | break; | |
11290 | ||
11291 | case USE_MOD_TABLE: | |
91d6fa6a NC |
11292 | vindex = modrm.mod == 0x3 ? 1 : 0; |
11293 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
11294 | break; |
11295 | ||
11296 | case USE_RM_TABLE: | |
11297 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
11298 | break; |
11299 | ||
4e7d34a6 | 11300 | case USE_PREFIX_TABLE: |
c0f3af97 | 11301 | if (need_vex) |
b844680a | 11302 | { |
c0f3af97 L |
11303 | /* The prefix in VEX is implicit. */ |
11304 | switch (vex.prefix) | |
11305 | { | |
11306 | case 0: | |
91d6fa6a | 11307 | vindex = 0; |
c0f3af97 L |
11308 | break; |
11309 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 11310 | vindex = 1; |
c0f3af97 L |
11311 | break; |
11312 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 11313 | vindex = 2; |
c0f3af97 L |
11314 | break; |
11315 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 11316 | vindex = 3; |
c0f3af97 L |
11317 | break; |
11318 | default: | |
11319 | abort (); | |
11320 | break; | |
11321 | } | |
b844680a | 11322 | } |
7bb15c6f | 11323 | else |
b844680a | 11324 | { |
285ca992 L |
11325 | int last_prefix = -1; |
11326 | int prefix = 0; | |
91d6fa6a | 11327 | vindex = 0; |
285ca992 L |
11328 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
11329 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
11330 | last one wins. */ | |
11331 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 11332 | { |
285ca992 | 11333 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 11334 | { |
285ca992 L |
11335 | vindex = 1; |
11336 | prefix = PREFIX_REPZ; | |
11337 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
11338 | } |
11339 | else | |
b844680a | 11340 | { |
285ca992 L |
11341 | vindex = 3; |
11342 | prefix = PREFIX_REPNZ; | |
11343 | last_prefix = last_repnz_prefix; | |
b844680a | 11344 | } |
285ca992 | 11345 | |
507bd325 L |
11346 | /* Check if prefix should be ignored. */ |
11347 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
11348 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
11349 | & prefix) != 0) | |
285ca992 L |
11350 | vindex = 0; |
11351 | } | |
11352 | ||
11353 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
11354 | { | |
11355 | vindex = 2; | |
11356 | prefix = PREFIX_DATA; | |
11357 | last_prefix = last_data_prefix; | |
11358 | } | |
11359 | ||
11360 | if (vindex != 0) | |
11361 | { | |
11362 | used_prefixes |= prefix; | |
11363 | all_prefixes[last_prefix] = 0; | |
b844680a L |
11364 | } |
11365 | } | |
91d6fa6a | 11366 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
11367 | break; |
11368 | ||
4e7d34a6 | 11369 | case USE_X86_64_TABLE: |
91d6fa6a NC |
11370 | vindex = address_mode == mode_64bit ? 1 : 0; |
11371 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
11372 | break; |
11373 | ||
4e7d34a6 | 11374 | case USE_3BYTE_TABLE: |
8bb15339 | 11375 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
11376 | vindex = *codep++; |
11377 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11378 | end_codep = codep; |
8bb15339 L |
11379 | modrm.mod = (*codep >> 6) & 3; |
11380 | modrm.reg = (*codep >> 3) & 7; | |
11381 | modrm.rm = *codep & 7; | |
11382 | break; | |
11383 | ||
c0f3af97 L |
11384 | case USE_VEX_LEN_TABLE: |
11385 | if (!need_vex) | |
11386 | abort (); | |
11387 | ||
11388 | switch (vex.length) | |
11389 | { | |
11390 | case 128: | |
91d6fa6a | 11391 | vindex = 0; |
c0f3af97 L |
11392 | break; |
11393 | case 256: | |
91d6fa6a | 11394 | vindex = 1; |
c0f3af97 L |
11395 | break; |
11396 | default: | |
11397 | abort (); | |
11398 | break; | |
11399 | } | |
11400 | ||
91d6fa6a | 11401 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
11402 | break; |
11403 | ||
04e2a182 L |
11404 | case USE_EVEX_LEN_TABLE: |
11405 | if (!vex.evex) | |
11406 | abort (); | |
11407 | ||
11408 | switch (vex.length) | |
11409 | { | |
11410 | case 128: | |
11411 | vindex = 0; | |
11412 | break; | |
11413 | case 256: | |
11414 | vindex = 1; | |
11415 | break; | |
11416 | case 512: | |
11417 | vindex = 2; | |
11418 | break; | |
11419 | default: | |
11420 | abort (); | |
11421 | break; | |
11422 | } | |
11423 | ||
11424 | dp = &evex_len_table[dp->op[1].bytemode][vindex]; | |
11425 | break; | |
11426 | ||
f88c9eb0 SP |
11427 | case USE_XOP_8F_TABLE: |
11428 | FETCH_DATA (info, codep + 3); | |
f88c9eb0 SP |
11429 | rex = ~(*codep >> 5) & 0x7; |
11430 | ||
11431 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
11432 | switch ((*codep & 0x1f)) | |
11433 | { | |
11434 | default: | |
f07af43e L |
11435 | dp = &bad_opcode; |
11436 | return dp; | |
5dd85c99 SP |
11437 | case 0x8: |
11438 | vex_table_index = XOP_08; | |
11439 | break; | |
f88c9eb0 SP |
11440 | case 0x9: |
11441 | vex_table_index = XOP_09; | |
11442 | break; | |
11443 | case 0xa: | |
11444 | vex_table_index = XOP_0A; | |
11445 | break; | |
11446 | } | |
11447 | codep++; | |
11448 | vex.w = *codep & 0x80; | |
11449 | if (vex.w && address_mode == mode_64bit) | |
11450 | rex |= REX_W; | |
11451 | ||
11452 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 11453 | if (address_mode != mode_64bit) |
f07af43e | 11454 | { |
abfcb414 AP |
11455 | /* In 16/32-bit mode REX_B is silently ignored. */ |
11456 | rex &= ~REX_B; | |
f07af43e | 11457 | } |
f88c9eb0 SP |
11458 | |
11459 | vex.length = (*codep & 0x4) ? 256 : 128; | |
11460 | switch ((*codep & 0x3)) | |
11461 | { | |
11462 | case 0: | |
f88c9eb0 SP |
11463 | break; |
11464 | case 1: | |
11465 | vex.prefix = DATA_PREFIX_OPCODE; | |
11466 | break; | |
11467 | case 2: | |
11468 | vex.prefix = REPE_PREFIX_OPCODE; | |
11469 | break; | |
11470 | case 3: | |
11471 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11472 | break; | |
11473 | } | |
11474 | need_vex = 1; | |
11475 | need_vex_reg = 1; | |
11476 | codep++; | |
91d6fa6a NC |
11477 | vindex = *codep++; |
11478 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 11479 | |
285ca992 | 11480 | end_codep = codep; |
c48244a5 SP |
11481 | FETCH_DATA (info, codep + 1); |
11482 | modrm.mod = (*codep >> 6) & 3; | |
11483 | modrm.reg = (*codep >> 3) & 7; | |
11484 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
11485 | break; |
11486 | ||
c0f3af97 | 11487 | case USE_VEX_C4_TABLE: |
43234a1e | 11488 | /* VEX prefix. */ |
c0f3af97 | 11489 | FETCH_DATA (info, codep + 3); |
c0f3af97 L |
11490 | rex = ~(*codep >> 5) & 0x7; |
11491 | switch ((*codep & 0x1f)) | |
11492 | { | |
11493 | default: | |
f07af43e L |
11494 | dp = &bad_opcode; |
11495 | return dp; | |
c0f3af97 | 11496 | case 0x1: |
f88c9eb0 | 11497 | vex_table_index = VEX_0F; |
c0f3af97 L |
11498 | break; |
11499 | case 0x2: | |
f88c9eb0 | 11500 | vex_table_index = VEX_0F38; |
c0f3af97 L |
11501 | break; |
11502 | case 0x3: | |
f88c9eb0 | 11503 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
11504 | break; |
11505 | } | |
11506 | codep++; | |
11507 | vex.w = *codep & 0x80; | |
9889cbb1 | 11508 | if (address_mode == mode_64bit) |
f07af43e | 11509 | { |
9889cbb1 L |
11510 | if (vex.w) |
11511 | rex |= REX_W; | |
9889cbb1 L |
11512 | } |
11513 | else | |
11514 | { | |
11515 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
11516 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 11517 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 11518 | rex = 0; |
f07af43e | 11519 | } |
5f847646 | 11520 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11521 | vex.length = (*codep & 0x4) ? 256 : 128; |
11522 | switch ((*codep & 0x3)) | |
11523 | { | |
11524 | case 0: | |
c0f3af97 L |
11525 | break; |
11526 | case 1: | |
11527 | vex.prefix = DATA_PREFIX_OPCODE; | |
11528 | break; | |
11529 | case 2: | |
11530 | vex.prefix = REPE_PREFIX_OPCODE; | |
11531 | break; | |
11532 | case 3: | |
11533 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11534 | break; | |
11535 | } | |
11536 | need_vex = 1; | |
11537 | need_vex_reg = 1; | |
11538 | codep++; | |
91d6fa6a NC |
11539 | vindex = *codep++; |
11540 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 11541 | end_codep = codep; |
53c4d625 JB |
11542 | /* There is no MODRM byte for VEX0F 77. */ |
11543 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
11544 | { |
11545 | FETCH_DATA (info, codep + 1); | |
11546 | modrm.mod = (*codep >> 6) & 3; | |
11547 | modrm.reg = (*codep >> 3) & 7; | |
11548 | modrm.rm = *codep & 7; | |
11549 | } | |
11550 | break; | |
11551 | ||
11552 | case USE_VEX_C5_TABLE: | |
43234a1e | 11553 | /* VEX prefix. */ |
c0f3af97 | 11554 | FETCH_DATA (info, codep + 2); |
c0f3af97 L |
11555 | rex = (*codep & 0x80) ? 0 : REX_R; |
11556 | ||
9889cbb1 L |
11557 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
11558 | VEX.vvvv is 1. */ | |
c0f3af97 | 11559 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11560 | vex.length = (*codep & 0x4) ? 256 : 128; |
11561 | switch ((*codep & 0x3)) | |
11562 | { | |
11563 | case 0: | |
c0f3af97 L |
11564 | break; |
11565 | case 1: | |
11566 | vex.prefix = DATA_PREFIX_OPCODE; | |
11567 | break; | |
11568 | case 2: | |
11569 | vex.prefix = REPE_PREFIX_OPCODE; | |
11570 | break; | |
11571 | case 3: | |
11572 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11573 | break; | |
11574 | } | |
11575 | need_vex = 1; | |
11576 | need_vex_reg = 1; | |
11577 | codep++; | |
91d6fa6a NC |
11578 | vindex = *codep++; |
11579 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11580 | end_codep = codep; |
53c4d625 JB |
11581 | /* There is no MODRM byte for VEX 77. */ |
11582 | if (vindex != 0x77) | |
c0f3af97 L |
11583 | { |
11584 | FETCH_DATA (info, codep + 1); | |
11585 | modrm.mod = (*codep >> 6) & 3; | |
11586 | modrm.reg = (*codep >> 3) & 7; | |
11587 | modrm.rm = *codep & 7; | |
11588 | } | |
11589 | break; | |
11590 | ||
9e30b8e0 L |
11591 | case USE_VEX_W_TABLE: |
11592 | if (!need_vex) | |
11593 | abort (); | |
11594 | ||
11595 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
11596 | break; | |
11597 | ||
43234a1e L |
11598 | case USE_EVEX_TABLE: |
11599 | two_source_ops = 0; | |
11600 | /* EVEX prefix. */ | |
11601 | vex.evex = 1; | |
11602 | FETCH_DATA (info, codep + 4); | |
43234a1e L |
11603 | /* The first byte after 0x62. */ |
11604 | rex = ~(*codep >> 5) & 0x7; | |
11605 | vex.r = *codep & 0x10; | |
11606 | switch ((*codep & 0xf)) | |
11607 | { | |
11608 | default: | |
11609 | return &bad_opcode; | |
11610 | case 0x1: | |
11611 | vex_table_index = EVEX_0F; | |
11612 | break; | |
11613 | case 0x2: | |
11614 | vex_table_index = EVEX_0F38; | |
11615 | break; | |
11616 | case 0x3: | |
11617 | vex_table_index = EVEX_0F3A; | |
11618 | break; | |
11619 | } | |
11620 | ||
11621 | /* The second byte after 0x62. */ | |
11622 | codep++; | |
11623 | vex.w = *codep & 0x80; | |
11624 | if (vex.w && address_mode == mode_64bit) | |
11625 | rex |= REX_W; | |
11626 | ||
11627 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
11628 | |
11629 | /* The U bit. */ | |
11630 | if (!(*codep & 0x4)) | |
11631 | return &bad_opcode; | |
11632 | ||
11633 | switch ((*codep & 0x3)) | |
11634 | { | |
11635 | case 0: | |
43234a1e L |
11636 | break; |
11637 | case 1: | |
11638 | vex.prefix = DATA_PREFIX_OPCODE; | |
11639 | break; | |
11640 | case 2: | |
11641 | vex.prefix = REPE_PREFIX_OPCODE; | |
11642 | break; | |
11643 | case 3: | |
11644 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11645 | break; | |
11646 | } | |
11647 | ||
11648 | /* The third byte after 0x62. */ | |
11649 | codep++; | |
11650 | ||
11651 | /* Remember the static rounding bits. */ | |
11652 | vex.ll = (*codep >> 5) & 3; | |
11653 | vex.b = (*codep & 0x10) != 0; | |
11654 | ||
11655 | vex.v = *codep & 0x8; | |
11656 | vex.mask_register_specifier = *codep & 0x7; | |
11657 | vex.zeroing = *codep & 0x80; | |
11658 | ||
5f847646 JB |
11659 | if (address_mode != mode_64bit) |
11660 | { | |
11661 | /* In 16/32-bit mode silently ignore following bits. */ | |
11662 | rex &= ~REX_B; | |
11663 | vex.r = 1; | |
11664 | vex.v = 1; | |
11665 | } | |
11666 | ||
43234a1e L |
11667 | need_vex = 1; |
11668 | need_vex_reg = 1; | |
11669 | codep++; | |
11670 | vindex = *codep++; | |
11671 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 11672 | end_codep = codep; |
43234a1e L |
11673 | FETCH_DATA (info, codep + 1); |
11674 | modrm.mod = (*codep >> 6) & 3; | |
11675 | modrm.reg = (*codep >> 3) & 7; | |
11676 | modrm.rm = *codep & 7; | |
11677 | ||
11678 | /* Set vector length. */ | |
11679 | if (modrm.mod == 3 && vex.b) | |
11680 | vex.length = 512; | |
11681 | else | |
11682 | { | |
11683 | switch (vex.ll) | |
11684 | { | |
11685 | case 0x0: | |
11686 | vex.length = 128; | |
11687 | break; | |
11688 | case 0x1: | |
11689 | vex.length = 256; | |
11690 | break; | |
11691 | case 0x2: | |
11692 | vex.length = 512; | |
11693 | break; | |
11694 | default: | |
11695 | return &bad_opcode; | |
11696 | } | |
11697 | } | |
11698 | break; | |
11699 | ||
592d1631 L |
11700 | case 0: |
11701 | dp = &bad_opcode; | |
11702 | break; | |
11703 | ||
b844680a | 11704 | default: |
d34b5006 | 11705 | abort (); |
b844680a L |
11706 | } |
11707 | ||
11708 | if (dp->name != NULL) | |
11709 | return dp; | |
11710 | else | |
8bb15339 | 11711 | return get_valid_dis386 (dp, info); |
b844680a L |
11712 | } |
11713 | ||
dfc8cf43 | 11714 | static void |
55cf16e1 | 11715 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
11716 | { |
11717 | /* If modrm.mod == 3, operand must be register. */ | |
11718 | if (need_modrm | |
55cf16e1 | 11719 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
11720 | && modrm.mod != 3 |
11721 | && modrm.rm == 4) | |
11722 | { | |
11723 | FETCH_DATA (info, codep + 2); | |
11724 | sib.index = (codep [1] >> 3) & 7; | |
11725 | sib.scale = (codep [1] >> 6) & 3; | |
11726 | sib.base = codep [1] & 7; | |
11727 | } | |
11728 | } | |
11729 | ||
e396998b | 11730 | static int |
26ca5450 | 11731 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 11732 | { |
2da11e11 | 11733 | const struct dis386 *dp; |
252b5132 | 11734 | int i; |
ce518a5f | 11735 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 11736 | int needcomma; |
df18fdba | 11737 | int sizeflag, orig_sizeflag; |
e396998b | 11738 | const char *p; |
252b5132 | 11739 | struct dis_private priv; |
f16cd0d5 | 11740 | int prefix_length; |
252b5132 | 11741 | |
d7921315 L |
11742 | priv.orig_sizeflag = AFLAG | DFLAG; |
11743 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 11744 | address_mode = mode_32bit; |
2da11e11 | 11745 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
11746 | { |
11747 | address_mode = mode_16bit; | |
11748 | priv.orig_sizeflag = 0; | |
11749 | } | |
2da11e11 | 11750 | else |
d7921315 L |
11751 | address_mode = mode_64bit; |
11752 | ||
11753 | if (intel_syntax == (char) -1) | |
11754 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
11755 | |
11756 | for (p = info->disassembler_options; p != NULL; ) | |
11757 | { | |
5db04b09 L |
11758 | if (CONST_STRNEQ (p, "amd64")) |
11759 | isa64 = amd64; | |
11760 | else if (CONST_STRNEQ (p, "intel64")) | |
11761 | isa64 = intel64; | |
11762 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 11763 | { |
cb712a9e | 11764 | address_mode = mode_64bit; |
2a1bb84c | 11765 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 11766 | } |
0112cd26 | 11767 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 11768 | { |
cb712a9e | 11769 | address_mode = mode_32bit; |
2a1bb84c | 11770 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 11771 | } |
0112cd26 | 11772 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 11773 | { |
cb712a9e | 11774 | address_mode = mode_16bit; |
2a1bb84c | 11775 | priv.orig_sizeflag &= ~(AFLAG | DFLAG); |
e396998b | 11776 | } |
0112cd26 | 11777 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
11778 | { |
11779 | intel_syntax = 1; | |
9d141669 L |
11780 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
11781 | intel_mnemonic = 1; | |
e396998b | 11782 | } |
0112cd26 | 11783 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
11784 | { |
11785 | intel_syntax = 0; | |
9d141669 L |
11786 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
11787 | intel_mnemonic = 0; | |
e396998b | 11788 | } |
0112cd26 | 11789 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 11790 | { |
f59a29b9 L |
11791 | if (address_mode == mode_64bit) |
11792 | { | |
11793 | if (p[4] == '3' && p[5] == '2') | |
11794 | priv.orig_sizeflag &= ~AFLAG; | |
11795 | else if (p[4] == '6' && p[5] == '4') | |
11796 | priv.orig_sizeflag |= AFLAG; | |
11797 | } | |
11798 | else | |
11799 | { | |
11800 | if (p[4] == '1' && p[5] == '6') | |
11801 | priv.orig_sizeflag &= ~AFLAG; | |
11802 | else if (p[4] == '3' && p[5] == '2') | |
11803 | priv.orig_sizeflag |= AFLAG; | |
11804 | } | |
e396998b | 11805 | } |
0112cd26 | 11806 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
11807 | { |
11808 | if (p[4] == '1' && p[5] == '6') | |
11809 | priv.orig_sizeflag &= ~DFLAG; | |
11810 | else if (p[4] == '3' && p[5] == '2') | |
11811 | priv.orig_sizeflag |= DFLAG; | |
11812 | } | |
0112cd26 | 11813 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
11814 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
11815 | ||
11816 | p = strchr (p, ','); | |
11817 | if (p != NULL) | |
11818 | p++; | |
11819 | } | |
11820 | ||
c0f92bf9 L |
11821 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
11822 | { | |
11823 | (*info->fprintf_func) (info->stream, | |
11824 | _("64-bit address is disabled")); | |
11825 | return -1; | |
11826 | } | |
11827 | ||
e396998b AM |
11828 | if (intel_syntax) |
11829 | { | |
11830 | names64 = intel_names64; | |
11831 | names32 = intel_names32; | |
11832 | names16 = intel_names16; | |
11833 | names8 = intel_names8; | |
11834 | names8rex = intel_names8rex; | |
11835 | names_seg = intel_names_seg; | |
b9733481 | 11836 | names_mm = intel_names_mm; |
7e8b059b | 11837 | names_bnd = intel_names_bnd; |
b9733481 L |
11838 | names_xmm = intel_names_xmm; |
11839 | names_ymm = intel_names_ymm; | |
43234a1e | 11840 | names_zmm = intel_names_zmm; |
db51cc60 L |
11841 | index64 = intel_index64; |
11842 | index32 = intel_index32; | |
43234a1e | 11843 | names_mask = intel_names_mask; |
e396998b AM |
11844 | index16 = intel_index16; |
11845 | open_char = '['; | |
11846 | close_char = ']'; | |
11847 | separator_char = '+'; | |
11848 | scale_char = '*'; | |
11849 | } | |
11850 | else | |
11851 | { | |
11852 | names64 = att_names64; | |
11853 | names32 = att_names32; | |
11854 | names16 = att_names16; | |
11855 | names8 = att_names8; | |
11856 | names8rex = att_names8rex; | |
11857 | names_seg = att_names_seg; | |
b9733481 | 11858 | names_mm = att_names_mm; |
7e8b059b | 11859 | names_bnd = att_names_bnd; |
b9733481 L |
11860 | names_xmm = att_names_xmm; |
11861 | names_ymm = att_names_ymm; | |
43234a1e | 11862 | names_zmm = att_names_zmm; |
db51cc60 L |
11863 | index64 = att_index64; |
11864 | index32 = att_index32; | |
43234a1e | 11865 | names_mask = att_names_mask; |
e396998b AM |
11866 | index16 = att_index16; |
11867 | open_char = '('; | |
11868 | close_char = ')'; | |
11869 | separator_char = ','; | |
11870 | scale_char = ','; | |
11871 | } | |
2da11e11 | 11872 | |
4fe53c98 | 11873 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
11874 | puts most long word instructions on a single line. Use 8 bytes |
11875 | for Intel L1OM. */ | |
d7921315 | 11876 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
11877 | info->bytes_per_line = 8; |
11878 | else | |
11879 | info->bytes_per_line = 7; | |
252b5132 | 11880 | |
26ca5450 | 11881 | info->private_data = &priv; |
252b5132 RH |
11882 | priv.max_fetched = priv.the_buffer; |
11883 | priv.insn_start = pc; | |
252b5132 RH |
11884 | |
11885 | obuf[0] = 0; | |
ce518a5f L |
11886 | for (i = 0; i < MAX_OPERANDS; ++i) |
11887 | { | |
11888 | op_out[i][0] = 0; | |
11889 | op_index[i] = -1; | |
11890 | } | |
252b5132 RH |
11891 | |
11892 | the_info = info; | |
11893 | start_pc = pc; | |
e396998b AM |
11894 | start_codep = priv.the_buffer; |
11895 | codep = priv.the_buffer; | |
252b5132 | 11896 | |
8df14d78 | 11897 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 11898 | { |
7d421014 ILT |
11899 | const char *name; |
11900 | ||
5076851f | 11901 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
11902 | means we have an incomplete instruction of some sort. Just |
11903 | print the first byte as a prefix or a .byte pseudo-op. */ | |
11904 | if (codep > priv.the_buffer) | |
5076851f | 11905 | { |
e396998b | 11906 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
11907 | if (name != NULL) |
11908 | (*info->fprintf_func) (info->stream, "%s", name); | |
11909 | else | |
5076851f | 11910 | { |
7d421014 ILT |
11911 | /* Just print the first byte as a .byte instruction. */ |
11912 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 11913 | (unsigned int) priv.the_buffer[0]); |
5076851f | 11914 | } |
5076851f | 11915 | |
7d421014 | 11916 | return 1; |
5076851f ILT |
11917 | } |
11918 | ||
11919 | return -1; | |
11920 | } | |
11921 | ||
52b15da3 | 11922 | obufp = obuf; |
f16cd0d5 L |
11923 | sizeflag = priv.orig_sizeflag; |
11924 | ||
11925 | if (!ckprefix () || rex_used) | |
11926 | { | |
11927 | /* Too many prefixes or unused REX prefixes. */ | |
11928 | for (i = 0; | |
f6dd4781 | 11929 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 11930 | i++) |
de882298 | 11931 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 11932 | i == 0 ? "" : " ", |
f16cd0d5 | 11933 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 11934 | return i; |
f16cd0d5 | 11935 | } |
252b5132 RH |
11936 | |
11937 | insn_codep = codep; | |
11938 | ||
11939 | FETCH_DATA (info, codep + 1); | |
11940 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
11941 | ||
3e7d61b2 | 11942 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 11943 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 11944 | { |
86a80a50 | 11945 | /* Handle prefixes before fwait. */ |
d9949a36 | 11946 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
11947 | i++) |
11948 | (*info->fprintf_func) (info->stream, "%s ", | |
11949 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 11950 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 11951 | return i + 1; |
252b5132 RH |
11952 | } |
11953 | ||
252b5132 RH |
11954 | if (*codep == 0x0f) |
11955 | { | |
eec0f4ca | 11956 | unsigned char threebyte; |
5f40e14d JS |
11957 | |
11958 | codep++; | |
11959 | FETCH_DATA (info, codep + 1); | |
11960 | threebyte = *codep; | |
eec0f4ca | 11961 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 11962 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 11963 | codep++; |
252b5132 RH |
11964 | } |
11965 | else | |
11966 | { | |
6439fc28 | 11967 | dp = &dis386[*codep]; |
252b5132 | 11968 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 11969 | codep++; |
252b5132 | 11970 | } |
246c51aa | 11971 | |
df18fdba L |
11972 | /* Save sizeflag for printing the extra prefixes later before updating |
11973 | it for mnemonic and operand processing. The prefix names depend | |
11974 | only on the address mode. */ | |
11975 | orig_sizeflag = sizeflag; | |
c608c12e | 11976 | if (prefixes & PREFIX_ADDR) |
df18fdba | 11977 | sizeflag ^= AFLAG; |
b844680a | 11978 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 11979 | sizeflag ^= DFLAG; |
3ffd33cf | 11980 | |
285ca992 | 11981 | end_codep = codep; |
8bb15339 | 11982 | if (need_modrm) |
252b5132 RH |
11983 | { |
11984 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
11985 | modrm.mod = (*codep >> 6) & 3; |
11986 | modrm.reg = (*codep >> 3) & 7; | |
11987 | modrm.rm = *codep & 7; | |
252b5132 RH |
11988 | } |
11989 | ||
42d5f9c6 MS |
11990 | need_vex = 0; |
11991 | need_vex_reg = 0; | |
11992 | vex_w_done = 0; | |
caf0678c | 11993 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 11994 | |
ce518a5f | 11995 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 11996 | { |
55cf16e1 | 11997 | get_sib (info, sizeflag); |
252b5132 RH |
11998 | dofloat (sizeflag); |
11999 | } | |
12000 | else | |
12001 | { | |
8bb15339 | 12002 | dp = get_valid_dis386 (dp, info); |
b844680a | 12003 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 12004 | { |
55cf16e1 | 12005 | get_sib (info, sizeflag); |
ce518a5f L |
12006 | for (i = 0; i < MAX_OPERANDS; ++i) |
12007 | { | |
246c51aa | 12008 | obufp = op_out[i]; |
ce518a5f L |
12009 | op_ad = MAX_OPERANDS - 1 - i; |
12010 | if (dp->op[i].rtn) | |
12011 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
12012 | /* For EVEX instruction after the last operand masking |
12013 | should be printed. */ | |
12014 | if (i == 0 && vex.evex) | |
12015 | { | |
12016 | /* Don't print {%k0}. */ | |
12017 | if (vex.mask_register_specifier) | |
12018 | { | |
12019 | oappend ("{"); | |
12020 | oappend (names_mask[vex.mask_register_specifier]); | |
12021 | oappend ("}"); | |
12022 | } | |
12023 | if (vex.zeroing) | |
12024 | oappend ("{z}"); | |
12025 | } | |
ce518a5f | 12026 | } |
6439fc28 | 12027 | } |
252b5132 RH |
12028 | } |
12029 | ||
1d67fe3b TT |
12030 | /* Clear instruction information. */ |
12031 | if (the_info) | |
12032 | { | |
12033 | the_info->insn_info_valid = 0; | |
12034 | the_info->branch_delay_insns = 0; | |
12035 | the_info->data_size = 0; | |
12036 | the_info->insn_type = dis_noninsn; | |
12037 | the_info->target = 0; | |
12038 | the_info->target2 = 0; | |
12039 | } | |
12040 | ||
12041 | /* Reset jump operation indicator. */ | |
12042 | op_is_jump = FALSE; | |
12043 | ||
12044 | { | |
12045 | int jump_detection = 0; | |
12046 | ||
12047 | /* Extract flags. */ | |
12048 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12049 | { | |
12050 | if ((dp->op[i].rtn == OP_J) | |
12051 | || (dp->op[i].rtn == OP_indirE)) | |
12052 | jump_detection |= 1; | |
12053 | else if ((dp->op[i].rtn == BND_Fixup) | |
12054 | || (!dp->op[i].rtn && !dp->op[i].bytemode)) | |
12055 | jump_detection |= 2; | |
12056 | else if ((dp->op[i].bytemode == cond_jump_mode) | |
12057 | || (dp->op[i].bytemode == loop_jcxz_mode)) | |
12058 | jump_detection |= 4; | |
12059 | } | |
12060 | ||
12061 | /* Determine if this is a jump or branch. */ | |
12062 | if ((jump_detection & 0x3) == 0x3) | |
12063 | { | |
12064 | op_is_jump = TRUE; | |
12065 | if (jump_detection & 0x4) | |
12066 | the_info->insn_type = dis_condbranch; | |
12067 | else | |
12068 | the_info->insn_type = | |
12069 | (dp->name && !strncmp(dp->name, "call", 4)) | |
12070 | ? dis_jsr : dis_branch; | |
12071 | } | |
12072 | } | |
12073 | ||
63c6fc6c L |
12074 | /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which |
12075 | are all 0s in inverted form. */ | |
12076 | if (need_vex && vex.register_specifier != 0) | |
12077 | { | |
12078 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12079 | return end_codep - priv.the_buffer; | |
12080 | } | |
12081 | ||
d869730d | 12082 | /* Check if the REX prefix is used. */ |
73239888 | 12083 | if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0) |
f16cd0d5 L |
12084 | all_prefixes[last_rex_prefix] = 0; |
12085 | ||
5e6718e4 | 12086 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
12087 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
12088 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 12089 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
12090 | all_prefixes[last_seg_prefix] = 0; |
12091 | ||
5e6718e4 | 12092 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
12093 | if ((prefixes & PREFIX_ADDR) != 0 |
12094 | && (used_prefixes & PREFIX_ADDR) != 0) | |
12095 | all_prefixes[last_addr_prefix] = 0; | |
12096 | ||
df18fdba L |
12097 | /* Check if the DATA prefix is used. */ |
12098 | if ((prefixes & PREFIX_DATA) != 0 | |
73239888 JB |
12099 | && (used_prefixes & PREFIX_DATA) != 0 |
12100 | && !need_vex) | |
df18fdba | 12101 | all_prefixes[last_data_prefix] = 0; |
f16cd0d5 | 12102 | |
df18fdba | 12103 | /* Print the extra prefixes. */ |
f16cd0d5 | 12104 | prefix_length = 0; |
f310f33d | 12105 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
12106 | if (all_prefixes[i]) |
12107 | { | |
12108 | const char *name; | |
df18fdba | 12109 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
12110 | if (name == NULL) |
12111 | abort (); | |
12112 | prefix_length += strlen (name) + 1; | |
12113 | (*info->fprintf_func) (info->stream, "%s ", name); | |
12114 | } | |
b844680a | 12115 | |
285ca992 L |
12116 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
12117 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
12118 | used by putop and MMX/SSE operand and may be overriden by the | |
12119 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
12120 | separately. */ | |
3888916d | 12121 | if (dp->prefix_requirement == PREFIX_OPCODE |
bf926894 JB |
12122 | && (((need_vex |
12123 | ? vex.prefix == REPE_PREFIX_OPCODE | |
12124 | || vex.prefix == REPNE_PREFIX_OPCODE | |
12125 | : (prefixes | |
12126 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
285ca992 L |
12127 | && (used_prefixes |
12128 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
bf926894 JB |
12129 | || (((need_vex |
12130 | ? vex.prefix == DATA_PREFIX_OPCODE | |
12131 | : ((prefixes | |
12132 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
12133 | == PREFIX_DATA)) | |
97e6786a JB |
12134 | && (used_prefixes & PREFIX_DATA) == 0)) |
12135 | || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA)))) | |
285ca992 L |
12136 | { |
12137 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12138 | return end_codep - priv.the_buffer; | |
12139 | } | |
12140 | ||
f16cd0d5 L |
12141 | /* Check maximum code length. */ |
12142 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
12143 | { | |
12144 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12145 | return MAX_CODE_LENGTH; | |
12146 | } | |
b844680a | 12147 | |
ea397f5b | 12148 | obufp = mnemonicendp; |
f16cd0d5 | 12149 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
12150 | oappend (" "); |
12151 | oappend (" "); | |
12152 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
12153 | ||
12154 | /* The enter and bound instructions are printed with operands in the same | |
12155 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 12156 | if (intel_syntax || two_source_ops) |
252b5132 | 12157 | { |
185b1163 L |
12158 | bfd_vma riprel; |
12159 | ||
ce518a5f | 12160 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12161 | op_txt[i] = op_out[i]; |
246c51aa | 12162 | |
3a8547d2 JB |
12163 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
12164 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
12165 | { | |
12166 | op_txt[2] = op_out[3]; | |
12167 | op_txt[3] = op_out[2]; | |
12168 | } | |
12169 | ||
ce518a5f L |
12170 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
12171 | { | |
6c067bbb RM |
12172 | op_ad = op_index[i]; |
12173 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
12174 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
12175 | riprel = op_riprel[i]; |
12176 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
12177 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 12178 | } |
252b5132 RH |
12179 | } |
12180 | else | |
12181 | { | |
ce518a5f | 12182 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12183 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
12184 | } |
12185 | ||
ce518a5f L |
12186 | needcomma = 0; |
12187 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12188 | if (*op_txt[i]) | |
12189 | { | |
12190 | if (needcomma) | |
12191 | (*info->fprintf_func) (info->stream, ","); | |
12192 | if (op_index[i] != -1 && !op_riprel[i]) | |
1d67fe3b TT |
12193 | { |
12194 | bfd_vma target = (bfd_vma) op_address[op_index[i]]; | |
12195 | ||
12196 | if (the_info && op_is_jump) | |
12197 | { | |
12198 | the_info->insn_info_valid = 1; | |
12199 | the_info->branch_delay_insns = 0; | |
12200 | the_info->data_size = 0; | |
12201 | the_info->target = target; | |
12202 | the_info->target2 = 0; | |
12203 | } | |
12204 | (*info->print_address_func) (target, info); | |
12205 | } | |
ce518a5f L |
12206 | else |
12207 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
12208 | needcomma = 1; | |
12209 | } | |
050dfa73 | 12210 | |
ce518a5f | 12211 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
12212 | if (op_index[i] != -1 && op_riprel[i]) |
12213 | { | |
12214 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 12215 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 12216 | + op_address[op_index[i]]), info); |
185b1163 | 12217 | break; |
52b15da3 | 12218 | } |
e396998b | 12219 | return codep - priv.the_buffer; |
252b5132 RH |
12220 | } |
12221 | ||
6439fc28 | 12222 | static const char *float_mem[] = { |
252b5132 | 12223 | /* d8 */ |
7c52e0e8 L |
12224 | "fadd{s|}", |
12225 | "fmul{s|}", | |
12226 | "fcom{s|}", | |
12227 | "fcomp{s|}", | |
12228 | "fsub{s|}", | |
12229 | "fsubr{s|}", | |
12230 | "fdiv{s|}", | |
12231 | "fdivr{s|}", | |
db6eb5be | 12232 | /* d9 */ |
7c52e0e8 | 12233 | "fld{s|}", |
252b5132 | 12234 | "(bad)", |
7c52e0e8 L |
12235 | "fst{s|}", |
12236 | "fstp{s|}", | |
d1c36125 | 12237 | "fldenv{C|C}", |
252b5132 | 12238 | "fldcw", |
d1c36125 | 12239 | "fNstenv{C|C}", |
252b5132 RH |
12240 | "fNstcw", |
12241 | /* da */ | |
7c52e0e8 L |
12242 | "fiadd{l|}", |
12243 | "fimul{l|}", | |
12244 | "ficom{l|}", | |
12245 | "ficomp{l|}", | |
12246 | "fisub{l|}", | |
12247 | "fisubr{l|}", | |
12248 | "fidiv{l|}", | |
12249 | "fidivr{l|}", | |
252b5132 | 12250 | /* db */ |
7c52e0e8 L |
12251 | "fild{l|}", |
12252 | "fisttp{l|}", | |
12253 | "fist{l|}", | |
12254 | "fistp{l|}", | |
252b5132 | 12255 | "(bad)", |
464dc4af | 12256 | "fld{t|}", |
252b5132 | 12257 | "(bad)", |
464dc4af | 12258 | "fstp{t|}", |
252b5132 | 12259 | /* dc */ |
7c52e0e8 L |
12260 | "fadd{l|}", |
12261 | "fmul{l|}", | |
12262 | "fcom{l|}", | |
12263 | "fcomp{l|}", | |
12264 | "fsub{l|}", | |
12265 | "fsubr{l|}", | |
12266 | "fdiv{l|}", | |
12267 | "fdivr{l|}", | |
252b5132 | 12268 | /* dd */ |
7c52e0e8 L |
12269 | "fld{l|}", |
12270 | "fisttp{ll|}", | |
12271 | "fst{l||}", | |
12272 | "fstp{l|}", | |
d1c36125 | 12273 | "frstor{C|C}", |
252b5132 | 12274 | "(bad)", |
d1c36125 | 12275 | "fNsave{C|C}", |
252b5132 RH |
12276 | "fNstsw", |
12277 | /* de */ | |
ac465521 JB |
12278 | "fiadd{s|}", |
12279 | "fimul{s|}", | |
12280 | "ficom{s|}", | |
12281 | "ficomp{s|}", | |
12282 | "fisub{s|}", | |
12283 | "fisubr{s|}", | |
12284 | "fidiv{s|}", | |
12285 | "fidivr{s|}", | |
252b5132 | 12286 | /* df */ |
ac465521 JB |
12287 | "fild{s|}", |
12288 | "fisttp{s|}", | |
12289 | "fist{s|}", | |
12290 | "fistp{s|}", | |
252b5132 | 12291 | "fbld", |
7c52e0e8 | 12292 | "fild{ll|}", |
252b5132 | 12293 | "fbstp", |
7c52e0e8 | 12294 | "fistp{ll|}", |
1d9f512f AM |
12295 | }; |
12296 | ||
12297 | static const unsigned char float_mem_mode[] = { | |
12298 | /* d8 */ | |
12299 | d_mode, | |
12300 | d_mode, | |
12301 | d_mode, | |
12302 | d_mode, | |
12303 | d_mode, | |
12304 | d_mode, | |
12305 | d_mode, | |
12306 | d_mode, | |
12307 | /* d9 */ | |
12308 | d_mode, | |
12309 | 0, | |
12310 | d_mode, | |
12311 | d_mode, | |
12312 | 0, | |
12313 | w_mode, | |
12314 | 0, | |
12315 | w_mode, | |
12316 | /* da */ | |
12317 | d_mode, | |
12318 | d_mode, | |
12319 | d_mode, | |
12320 | d_mode, | |
12321 | d_mode, | |
12322 | d_mode, | |
12323 | d_mode, | |
12324 | d_mode, | |
12325 | /* db */ | |
12326 | d_mode, | |
12327 | d_mode, | |
12328 | d_mode, | |
12329 | d_mode, | |
12330 | 0, | |
9306ca4a | 12331 | t_mode, |
1d9f512f | 12332 | 0, |
9306ca4a | 12333 | t_mode, |
1d9f512f AM |
12334 | /* dc */ |
12335 | q_mode, | |
12336 | q_mode, | |
12337 | q_mode, | |
12338 | q_mode, | |
12339 | q_mode, | |
12340 | q_mode, | |
12341 | q_mode, | |
12342 | q_mode, | |
12343 | /* dd */ | |
12344 | q_mode, | |
12345 | q_mode, | |
12346 | q_mode, | |
12347 | q_mode, | |
12348 | 0, | |
12349 | 0, | |
12350 | 0, | |
12351 | w_mode, | |
12352 | /* de */ | |
12353 | w_mode, | |
12354 | w_mode, | |
12355 | w_mode, | |
12356 | w_mode, | |
12357 | w_mode, | |
12358 | w_mode, | |
12359 | w_mode, | |
12360 | w_mode, | |
12361 | /* df */ | |
12362 | w_mode, | |
12363 | w_mode, | |
12364 | w_mode, | |
12365 | w_mode, | |
9306ca4a | 12366 | t_mode, |
1d9f512f | 12367 | q_mode, |
9306ca4a | 12368 | t_mode, |
1d9f512f | 12369 | q_mode |
252b5132 RH |
12370 | }; |
12371 | ||
ce518a5f L |
12372 | #define ST { OP_ST, 0 } |
12373 | #define STi { OP_STi, 0 } | |
252b5132 | 12374 | |
48c97fa1 L |
12375 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
12376 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
12377 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
12378 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
12379 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
12380 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
12381 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
12382 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
12383 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 12384 | |
2da11e11 | 12385 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
12386 | /* d8 */ |
12387 | { | |
bf890a93 IT |
12388 | { "fadd", { ST, STi }, 0 }, |
12389 | { "fmul", { ST, STi }, 0 }, | |
12390 | { "fcom", { STi }, 0 }, | |
12391 | { "fcomp", { STi }, 0 }, | |
12392 | { "fsub", { ST, STi }, 0 }, | |
12393 | { "fsubr", { ST, STi }, 0 }, | |
12394 | { "fdiv", { ST, STi }, 0 }, | |
12395 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
12396 | }, |
12397 | /* d9 */ | |
12398 | { | |
bf890a93 IT |
12399 | { "fld", { STi }, 0 }, |
12400 | { "fxch", { STi }, 0 }, | |
252b5132 | 12401 | { FGRPd9_2 }, |
592d1631 | 12402 | { Bad_Opcode }, |
252b5132 RH |
12403 | { FGRPd9_4 }, |
12404 | { FGRPd9_5 }, | |
12405 | { FGRPd9_6 }, | |
12406 | { FGRPd9_7 }, | |
12407 | }, | |
12408 | /* da */ | |
12409 | { | |
bf890a93 IT |
12410 | { "fcmovb", { ST, STi }, 0 }, |
12411 | { "fcmove", { ST, STi }, 0 }, | |
12412 | { "fcmovbe",{ ST, STi }, 0 }, | |
12413 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 12414 | { Bad_Opcode }, |
252b5132 | 12415 | { FGRPda_5 }, |
592d1631 L |
12416 | { Bad_Opcode }, |
12417 | { Bad_Opcode }, | |
252b5132 RH |
12418 | }, |
12419 | /* db */ | |
12420 | { | |
bf890a93 IT |
12421 | { "fcmovnb",{ ST, STi }, 0 }, |
12422 | { "fcmovne",{ ST, STi }, 0 }, | |
12423 | { "fcmovnbe",{ ST, STi }, 0 }, | |
12424 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 12425 | { FGRPdb_4 }, |
bf890a93 IT |
12426 | { "fucomi", { ST, STi }, 0 }, |
12427 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 12428 | { Bad_Opcode }, |
252b5132 RH |
12429 | }, |
12430 | /* dc */ | |
12431 | { | |
bf890a93 IT |
12432 | { "fadd", { STi, ST }, 0 }, |
12433 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
12434 | { Bad_Opcode }, |
12435 | { Bad_Opcode }, | |
d53e6b98 JB |
12436 | { "fsub{!M|r}", { STi, ST }, 0 }, |
12437 | { "fsub{M|}", { STi, ST }, 0 }, | |
12438 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
12439 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
12440 | }, |
12441 | /* dd */ | |
12442 | { | |
bf890a93 | 12443 | { "ffree", { STi }, 0 }, |
592d1631 | 12444 | { Bad_Opcode }, |
bf890a93 IT |
12445 | { "fst", { STi }, 0 }, |
12446 | { "fstp", { STi }, 0 }, | |
12447 | { "fucom", { STi }, 0 }, | |
12448 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
12449 | { Bad_Opcode }, |
12450 | { Bad_Opcode }, | |
252b5132 RH |
12451 | }, |
12452 | /* de */ | |
12453 | { | |
bf890a93 IT |
12454 | { "faddp", { STi, ST }, 0 }, |
12455 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 12456 | { Bad_Opcode }, |
252b5132 | 12457 | { FGRPde_3 }, |
d53e6b98 JB |
12458 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
12459 | { "fsub{M|}p", { STi, ST }, 0 }, | |
12460 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
12461 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
12462 | }, |
12463 | /* df */ | |
12464 | { | |
bf890a93 | 12465 | { "ffreep", { STi }, 0 }, |
592d1631 L |
12466 | { Bad_Opcode }, |
12467 | { Bad_Opcode }, | |
12468 | { Bad_Opcode }, | |
252b5132 | 12469 | { FGRPdf_4 }, |
bf890a93 IT |
12470 | { "fucomip", { ST, STi }, 0 }, |
12471 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 12472 | { Bad_Opcode }, |
252b5132 RH |
12473 | }, |
12474 | }; | |
12475 | ||
252b5132 | 12476 | static char *fgrps[][8] = { |
48c97fa1 L |
12477 | /* Bad opcode 0 */ |
12478 | { | |
12479 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12480 | }, | |
12481 | ||
12482 | /* d9_2 1 */ | |
252b5132 RH |
12483 | { |
12484 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12485 | }, | |
12486 | ||
48c97fa1 | 12487 | /* d9_4 2 */ |
252b5132 RH |
12488 | { |
12489 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
12490 | }, | |
12491 | ||
48c97fa1 | 12492 | /* d9_5 3 */ |
252b5132 RH |
12493 | { |
12494 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
12495 | }, | |
12496 | ||
48c97fa1 | 12497 | /* d9_6 4 */ |
252b5132 RH |
12498 | { |
12499 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
12500 | }, | |
12501 | ||
48c97fa1 | 12502 | /* d9_7 5 */ |
252b5132 RH |
12503 | { |
12504 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
12505 | }, | |
12506 | ||
48c97fa1 | 12507 | /* da_5 6 */ |
252b5132 RH |
12508 | { |
12509 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12510 | }, | |
12511 | ||
48c97fa1 | 12512 | /* db_4 7 */ |
252b5132 | 12513 | { |
309d3373 JB |
12514 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
12515 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
12516 | }, |
12517 | ||
48c97fa1 | 12518 | /* de_3 8 */ |
252b5132 RH |
12519 | { |
12520 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12521 | }, | |
12522 | ||
48c97fa1 | 12523 | /* df_4 9 */ |
252b5132 RH |
12524 | { |
12525 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12526 | }, | |
12527 | }; | |
12528 | ||
b6169b20 L |
12529 | static void |
12530 | swap_operand (void) | |
12531 | { | |
12532 | mnemonicendp[0] = '.'; | |
12533 | mnemonicendp[1] = 's'; | |
12534 | mnemonicendp += 2; | |
12535 | } | |
12536 | ||
b844680a L |
12537 | static void |
12538 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
12539 | int sizeflag ATTRIBUTE_UNUSED) | |
12540 | { | |
12541 | /* Skip mod/rm byte. */ | |
12542 | MODRM_CHECK; | |
12543 | codep++; | |
12544 | } | |
12545 | ||
252b5132 | 12546 | static void |
26ca5450 | 12547 | dofloat (int sizeflag) |
252b5132 | 12548 | { |
2da11e11 | 12549 | const struct dis386 *dp; |
252b5132 RH |
12550 | unsigned char floatop; |
12551 | ||
12552 | floatop = codep[-1]; | |
12553 | ||
7967e09e | 12554 | if (modrm.mod != 3) |
252b5132 | 12555 | { |
7967e09e | 12556 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
12557 | |
12558 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 12559 | obufp = op_out[0]; |
6e50d963 | 12560 | op_ad = 2; |
1d9f512f | 12561 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
12562 | return; |
12563 | } | |
6608db57 | 12564 | /* Skip mod/rm byte. */ |
4bba6815 | 12565 | MODRM_CHECK; |
252b5132 RH |
12566 | codep++; |
12567 | ||
7967e09e | 12568 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
12569 | if (dp->name == NULL) |
12570 | { | |
7967e09e | 12571 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 12572 | |
6608db57 | 12573 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 12574 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 12575 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
12576 | } |
12577 | else | |
12578 | { | |
12579 | putop (dp->name, sizeflag); | |
12580 | ||
ce518a5f | 12581 | obufp = op_out[0]; |
6e50d963 | 12582 | op_ad = 2; |
ce518a5f L |
12583 | if (dp->op[0].rtn) |
12584 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 12585 | |
ce518a5f | 12586 | obufp = op_out[1]; |
6e50d963 | 12587 | op_ad = 1; |
ce518a5f L |
12588 | if (dp->op[1].rtn) |
12589 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
12590 | } |
12591 | } | |
12592 | ||
9ce09ba2 RM |
12593 | /* Like oappend (below), but S is a string starting with '%'. |
12594 | In Intel syntax, the '%' is elided. */ | |
12595 | static void | |
12596 | oappend_maybe_intel (const char *s) | |
12597 | { | |
12598 | oappend (s + intel_syntax); | |
12599 | } | |
12600 | ||
252b5132 | 12601 | static void |
26ca5450 | 12602 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12603 | { |
9ce09ba2 | 12604 | oappend_maybe_intel ("%st"); |
252b5132 RH |
12605 | } |
12606 | ||
252b5132 | 12607 | static void |
26ca5450 | 12608 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12609 | { |
7967e09e | 12610 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 12611 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12612 | } |
12613 | ||
6608db57 | 12614 | /* Capital letters in template are macros. */ |
6439fc28 | 12615 | static int |
d3ce72d0 | 12616 | putop (const char *in_template, int sizeflag) |
252b5132 | 12617 | { |
2da11e11 | 12618 | const char *p; |
9306ca4a | 12619 | int alt = 0; |
9d141669 | 12620 | int cond = 1; |
98b528ac L |
12621 | unsigned int l = 0, len = 1; |
12622 | char last[4]; | |
12623 | ||
12624 | #define SAVE_LAST(c) \ | |
12625 | if (l < len && l < sizeof (last)) \ | |
12626 | last[l++] = c; \ | |
12627 | else \ | |
12628 | abort (); | |
252b5132 | 12629 | |
d3ce72d0 | 12630 | for (p = in_template; *p; p++) |
252b5132 RH |
12631 | { |
12632 | switch (*p) | |
12633 | { | |
12634 | default: | |
12635 | *obufp++ = *p; | |
12636 | break; | |
98b528ac L |
12637 | case '%': |
12638 | len++; | |
12639 | break; | |
9d141669 L |
12640 | case '!': |
12641 | cond = 0; | |
12642 | break; | |
6439fc28 | 12643 | case '{': |
6439fc28 | 12644 | if (intel_syntax) |
6439fc28 AM |
12645 | { |
12646 | while (*++p != '|') | |
7c52e0e8 L |
12647 | if (*p == '}' || *p == '\0') |
12648 | abort (); | |
d1c36125 | 12649 | alt = 1; |
6439fc28 | 12650 | } |
d1c36125 | 12651 | break; |
6439fc28 AM |
12652 | case '|': |
12653 | while (*++p != '}') | |
12654 | { | |
12655 | if (*p == '\0') | |
12656 | abort (); | |
12657 | } | |
12658 | break; | |
12659 | case '}': | |
d1c36125 | 12660 | alt = 0; |
6439fc28 | 12661 | break; |
252b5132 | 12662 | case 'A': |
db6eb5be AM |
12663 | if (intel_syntax) |
12664 | break; | |
7967e09e | 12665 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
12666 | *obufp++ = 'b'; |
12667 | break; | |
12668 | case 'B': | |
4b06377f L |
12669 | if (l == 0 && len == 1) |
12670 | { | |
dc1e8a47 | 12671 | case_B: |
4b06377f L |
12672 | if (intel_syntax) |
12673 | break; | |
12674 | if (sizeflag & SUFFIX_ALWAYS) | |
12675 | *obufp++ = 'b'; | |
12676 | } | |
12677 | else | |
12678 | { | |
12679 | if (l != 1 | |
12680 | || len != 2 | |
12681 | || last[0] != 'L') | |
12682 | { | |
12683 | SAVE_LAST (*p); | |
12684 | break; | |
12685 | } | |
12686 | ||
12687 | if (address_mode == mode_64bit | |
12688 | && !(prefixes & PREFIX_ADDR)) | |
12689 | { | |
12690 | *obufp++ = 'a'; | |
12691 | *obufp++ = 'b'; | |
12692 | *obufp++ = 's'; | |
12693 | } | |
12694 | ||
12695 | goto case_B; | |
12696 | } | |
252b5132 | 12697 | break; |
9306ca4a JB |
12698 | case 'C': |
12699 | if (intel_syntax && !alt) | |
12700 | break; | |
12701 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
12702 | { | |
12703 | if (sizeflag & DFLAG) | |
12704 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12705 | else | |
12706 | *obufp++ = intel_syntax ? 'w' : 's'; | |
12707 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12708 | } | |
12709 | break; | |
ed7841b3 JB |
12710 | case 'D': |
12711 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
12712 | break; | |
161a04f6 | 12713 | USED_REX (REX_W); |
7967e09e | 12714 | if (modrm.mod == 3) |
ed7841b3 | 12715 | { |
161a04f6 | 12716 | if (rex & REX_W) |
ed7841b3 | 12717 | *obufp++ = 'q'; |
ed7841b3 | 12718 | else |
f16cd0d5 L |
12719 | { |
12720 | if (sizeflag & DFLAG) | |
12721 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12722 | else | |
12723 | *obufp++ = 'w'; | |
12724 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12725 | } | |
ed7841b3 JB |
12726 | } |
12727 | else | |
12728 | *obufp++ = 'w'; | |
12729 | break; | |
252b5132 | 12730 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 12731 | if (address_mode == mode_64bit) |
c1a64871 JH |
12732 | { |
12733 | if (sizeflag & AFLAG) | |
12734 | *obufp++ = 'r'; | |
12735 | else | |
12736 | *obufp++ = 'e'; | |
12737 | } | |
12738 | else | |
12739 | if (sizeflag & AFLAG) | |
12740 | *obufp++ = 'e'; | |
3ffd33cf AM |
12741 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12742 | break; | |
12743 | case 'F': | |
db6eb5be AM |
12744 | if (intel_syntax) |
12745 | break; | |
e396998b | 12746 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
12747 | { |
12748 | if (sizeflag & AFLAG) | |
cb712a9e | 12749 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 12750 | else |
cb712a9e | 12751 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
12752 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12753 | } | |
252b5132 | 12754 | break; |
52fd6d94 JB |
12755 | case 'G': |
12756 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
12757 | break; | |
161a04f6 | 12758 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12759 | *obufp++ = 'l'; |
12760 | else | |
12761 | *obufp++ = 'w'; | |
161a04f6 | 12762 | if (!(rex & REX_W)) |
52fd6d94 JB |
12763 | used_prefixes |= (prefixes & PREFIX_DATA); |
12764 | break; | |
5dd0794d | 12765 | case 'H': |
db6eb5be AM |
12766 | if (intel_syntax) |
12767 | break; | |
5dd0794d AM |
12768 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
12769 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
12770 | { | |
12771 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
12772 | *obufp++ = ','; | |
12773 | *obufp++ = 'p'; | |
12774 | if (prefixes & PREFIX_DS) | |
12775 | *obufp++ = 't'; | |
12776 | else | |
12777 | *obufp++ = 'n'; | |
12778 | } | |
12779 | break; | |
42903f7f L |
12780 | case 'K': |
12781 | USED_REX (REX_W); | |
12782 | if (rex & REX_W) | |
12783 | *obufp++ = 'q'; | |
12784 | else | |
12785 | *obufp++ = 'd'; | |
12786 | break; | |
6dd5059a | 12787 | case 'Z': |
04d824a4 JB |
12788 | if (l != 0 || len != 1) |
12789 | { | |
12790 | if (l != 1 || len != 2 || last[0] != 'X') | |
12791 | { | |
12792 | SAVE_LAST (*p); | |
12793 | break; | |
12794 | } | |
12795 | if (!need_vex || !vex.evex) | |
12796 | abort (); | |
12797 | if (intel_syntax | |
12798 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
12799 | break; | |
12800 | switch (vex.length) | |
12801 | { | |
12802 | case 128: | |
12803 | *obufp++ = 'x'; | |
12804 | break; | |
12805 | case 256: | |
12806 | *obufp++ = 'y'; | |
12807 | break; | |
12808 | case 512: | |
12809 | *obufp++ = 'z'; | |
12810 | break; | |
12811 | default: | |
12812 | abort (); | |
12813 | } | |
12814 | break; | |
12815 | } | |
6dd5059a L |
12816 | if (intel_syntax) |
12817 | break; | |
12818 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
12819 | { | |
12820 | *obufp++ = 'q'; | |
12821 | break; | |
12822 | } | |
12823 | /* Fall through. */ | |
98b528ac | 12824 | goto case_L; |
252b5132 | 12825 | case 'L': |
98b528ac L |
12826 | if (l != 0 || len != 1) |
12827 | { | |
12828 | SAVE_LAST (*p); | |
12829 | break; | |
12830 | } | |
dc1e8a47 | 12831 | case_L: |
db6eb5be AM |
12832 | if (intel_syntax) |
12833 | break; | |
252b5132 RH |
12834 | if (sizeflag & SUFFIX_ALWAYS) |
12835 | *obufp++ = 'l'; | |
252b5132 | 12836 | break; |
9d141669 L |
12837 | case 'M': |
12838 | if (intel_mnemonic != cond) | |
12839 | *obufp++ = 'r'; | |
12840 | break; | |
252b5132 RH |
12841 | case 'N': |
12842 | if ((prefixes & PREFIX_FWAIT) == 0) | |
12843 | *obufp++ = 'n'; | |
7d421014 ILT |
12844 | else |
12845 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 12846 | break; |
52b15da3 | 12847 | case 'O': |
161a04f6 L |
12848 | USED_REX (REX_W); |
12849 | if (rex & REX_W) | |
6439fc28 | 12850 | *obufp++ = 'o'; |
a35ca55a JB |
12851 | else if (intel_syntax && (sizeflag & DFLAG)) |
12852 | *obufp++ = 'q'; | |
52b15da3 JH |
12853 | else |
12854 | *obufp++ = 'd'; | |
161a04f6 | 12855 | if (!(rex & REX_W)) |
a35ca55a | 12856 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 12857 | break; |
07f5af7d L |
12858 | case '&': |
12859 | if (!intel_syntax | |
12860 | && address_mode == mode_64bit | |
12861 | && isa64 == intel64) | |
12862 | { | |
12863 | *obufp++ = 'q'; | |
12864 | break; | |
12865 | } | |
12866 | /* Fall through. */ | |
6439fc28 | 12867 | case 'T': |
d9e3625e L |
12868 | if (!intel_syntax |
12869 | && address_mode == mode_64bit | |
7bb15c6f | 12870 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
12871 | { |
12872 | *obufp++ = 'q'; | |
12873 | break; | |
12874 | } | |
6608db57 | 12875 | /* Fall through. */ |
4b4c407a | 12876 | goto case_P; |
252b5132 | 12877 | case 'P': |
4b4c407a | 12878 | if (l == 0 && len == 1) |
d9e3625e | 12879 | { |
dc1e8a47 | 12880 | case_P: |
4b4c407a | 12881 | if (intel_syntax) |
d9e3625e | 12882 | { |
4b4c407a L |
12883 | if ((rex & REX_W) == 0 |
12884 | && (prefixes & PREFIX_DATA)) | |
12885 | { | |
12886 | if ((sizeflag & DFLAG) == 0) | |
12887 | *obufp++ = 'w'; | |
12888 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12889 | } | |
12890 | break; | |
12891 | } | |
12892 | if ((prefixes & PREFIX_DATA) | |
12893 | || (rex & REX_W) | |
12894 | || (sizeflag & SUFFIX_ALWAYS)) | |
12895 | { | |
12896 | USED_REX (REX_W); | |
12897 | if (rex & REX_W) | |
12898 | *obufp++ = 'q'; | |
12899 | else | |
12900 | { | |
12901 | if (sizeflag & DFLAG) | |
12902 | *obufp++ = 'l'; | |
12903 | else | |
12904 | *obufp++ = 'w'; | |
12905 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12906 | } | |
d9e3625e | 12907 | } |
d9e3625e | 12908 | } |
4b4c407a | 12909 | else |
252b5132 | 12910 | { |
4b4c407a L |
12911 | if (l != 1 || len != 2 || last[0] != 'L') |
12912 | { | |
12913 | SAVE_LAST (*p); | |
12914 | break; | |
12915 | } | |
12916 | ||
12917 | if ((prefixes & PREFIX_DATA) | |
12918 | || (rex & REX_W) | |
12919 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 12920 | { |
4b4c407a L |
12921 | USED_REX (REX_W); |
12922 | if (rex & REX_W) | |
12923 | *obufp++ = 'q'; | |
12924 | else | |
12925 | { | |
12926 | if (sizeflag & DFLAG) | |
12927 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12928 | else | |
12929 | *obufp++ = 'w'; | |
12930 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12931 | } | |
52b15da3 | 12932 | } |
252b5132 RH |
12933 | } |
12934 | break; | |
6439fc28 | 12935 | case 'U': |
db6eb5be AM |
12936 | if (intel_syntax) |
12937 | break; | |
7bb15c6f | 12938 | if (address_mode == mode_64bit |
6c067bbb | 12939 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 12940 | { |
7967e09e | 12941 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 12942 | *obufp++ = 'q'; |
6439fc28 AM |
12943 | break; |
12944 | } | |
6608db57 | 12945 | /* Fall through. */ |
98b528ac | 12946 | goto case_Q; |
252b5132 | 12947 | case 'Q': |
98b528ac | 12948 | if (l == 0 && len == 1) |
252b5132 | 12949 | { |
dc1e8a47 | 12950 | case_Q: |
98b528ac L |
12951 | if (intel_syntax && !alt) |
12952 | break; | |
12953 | USED_REX (REX_W); | |
12954 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 12955 | { |
98b528ac L |
12956 | if (rex & REX_W) |
12957 | *obufp++ = 'q'; | |
52b15da3 | 12958 | else |
98b528ac L |
12959 | { |
12960 | if (sizeflag & DFLAG) | |
12961 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12962 | else | |
12963 | *obufp++ = 'w'; | |
f16cd0d5 | 12964 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 12965 | } |
52b15da3 | 12966 | } |
98b528ac L |
12967 | } |
12968 | else | |
12969 | { | |
12970 | if (l != 1 || len != 2 || last[0] != 'L') | |
12971 | { | |
12972 | SAVE_LAST (*p); | |
12973 | break; | |
12974 | } | |
589958d6 | 12975 | if ((intel_syntax && need_modrm) |
98b528ac L |
12976 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) |
12977 | break; | |
12978 | if ((rex & REX_W)) | |
12979 | { | |
12980 | USED_REX (REX_W); | |
12981 | *obufp++ = 'q'; | |
12982 | } | |
589958d6 JB |
12983 | else if((address_mode == mode_64bit && need_modrm) |
12984 | || (sizeflag & SUFFIX_ALWAYS)) | |
12985 | *obufp++ = intel_syntax? 'd' : 'l'; | |
252b5132 RH |
12986 | } |
12987 | break; | |
12988 | case 'R': | |
161a04f6 L |
12989 | USED_REX (REX_W); |
12990 | if (rex & REX_W) | |
a35ca55a JB |
12991 | *obufp++ = 'q'; |
12992 | else if (sizeflag & DFLAG) | |
c608c12e | 12993 | { |
a35ca55a | 12994 | if (intel_syntax) |
c608c12e | 12995 | *obufp++ = 'd'; |
c608c12e | 12996 | else |
a35ca55a | 12997 | *obufp++ = 'l'; |
c608c12e | 12998 | } |
252b5132 | 12999 | else |
a35ca55a JB |
13000 | *obufp++ = 'w'; |
13001 | if (intel_syntax && !p[1] | |
161a04f6 | 13002 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 13003 | *obufp++ = 'e'; |
161a04f6 | 13004 | if (!(rex & REX_W)) |
52b15da3 | 13005 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 13006 | break; |
1a114b12 | 13007 | case 'V': |
4b06377f | 13008 | if (l == 0 && len == 1) |
1a114b12 | 13009 | { |
4b06377f L |
13010 | if (intel_syntax) |
13011 | break; | |
7bb15c6f | 13012 | if (address_mode == mode_64bit |
6c067bbb | 13013 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
13014 | { |
13015 | if (sizeflag & SUFFIX_ALWAYS) | |
13016 | *obufp++ = 'q'; | |
13017 | break; | |
13018 | } | |
13019 | } | |
13020 | else | |
13021 | { | |
13022 | if (l != 1 | |
13023 | || len != 2 | |
13024 | || last[0] != 'L') | |
13025 | { | |
13026 | SAVE_LAST (*p); | |
13027 | break; | |
13028 | } | |
13029 | ||
13030 | if (rex & REX_W) | |
13031 | { | |
13032 | *obufp++ = 'a'; | |
13033 | *obufp++ = 'b'; | |
13034 | *obufp++ = 's'; | |
13035 | } | |
1a114b12 JB |
13036 | } |
13037 | /* Fall through. */ | |
4b06377f | 13038 | goto case_S; |
252b5132 | 13039 | case 'S': |
4b06377f | 13040 | if (l == 0 && len == 1) |
252b5132 | 13041 | { |
dc1e8a47 | 13042 | case_S: |
4b06377f L |
13043 | if (intel_syntax) |
13044 | break; | |
13045 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 13046 | { |
4b06377f L |
13047 | if (rex & REX_W) |
13048 | *obufp++ = 'q'; | |
52b15da3 | 13049 | else |
4b06377f L |
13050 | { |
13051 | if (sizeflag & DFLAG) | |
13052 | *obufp++ = 'l'; | |
13053 | else | |
13054 | *obufp++ = 'w'; | |
13055 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13056 | } | |
13057 | } | |
13058 | } | |
13059 | else | |
13060 | { | |
13061 | if (l != 1 | |
13062 | || len != 2 | |
13063 | || last[0] != 'L') | |
13064 | { | |
13065 | SAVE_LAST (*p); | |
13066 | break; | |
52b15da3 | 13067 | } |
4b06377f L |
13068 | |
13069 | if (address_mode == mode_64bit | |
13070 | && !(prefixes & PREFIX_ADDR)) | |
13071 | { | |
13072 | *obufp++ = 'a'; | |
13073 | *obufp++ = 'b'; | |
13074 | *obufp++ = 's'; | |
13075 | } | |
13076 | ||
13077 | goto case_S; | |
252b5132 | 13078 | } |
252b5132 | 13079 | break; |
041bd2e0 | 13080 | case 'X': |
c0f3af97 L |
13081 | if (l != 0 || len != 1) |
13082 | { | |
13083 | SAVE_LAST (*p); | |
13084 | break; | |
13085 | } | |
bf926894 JB |
13086 | if (need_vex |
13087 | ? vex.prefix == DATA_PREFIX_OPCODE | |
13088 | : prefixes & PREFIX_DATA) | |
c0f3af97 | 13089 | { |
bf926894 JB |
13090 | *obufp++ = 'd'; |
13091 | used_prefixes |= PREFIX_DATA; | |
c0f3af97 | 13092 | } |
041bd2e0 | 13093 | else |
bf926894 | 13094 | *obufp++ = 's'; |
041bd2e0 | 13095 | break; |
76f227a5 | 13096 | case 'Y': |
c0f3af97 | 13097 | if (l == 0 && len == 1) |
9646c87b | 13098 | abort (); |
c0f3af97 L |
13099 | else |
13100 | { | |
13101 | if (l != 1 || len != 2 || last[0] != 'X') | |
13102 | { | |
13103 | SAVE_LAST (*p); | |
13104 | break; | |
13105 | } | |
13106 | if (!need_vex) | |
13107 | abort (); | |
13108 | if (intel_syntax | |
04d824a4 | 13109 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
13110 | break; |
13111 | switch (vex.length) | |
13112 | { | |
13113 | case 128: | |
13114 | *obufp++ = 'x'; | |
13115 | break; | |
13116 | case 256: | |
13117 | *obufp++ = 'y'; | |
13118 | break; | |
04d824a4 JB |
13119 | case 512: |
13120 | if (!vex.evex) | |
c0f3af97 | 13121 | default: |
04d824a4 | 13122 | abort (); |
c0f3af97 | 13123 | } |
76f227a5 JH |
13124 | } |
13125 | break; | |
252b5132 | 13126 | case 'W': |
0bfee649 | 13127 | if (l == 0 && len == 1) |
a35ca55a | 13128 | { |
0bfee649 L |
13129 | /* operand size flag for cwtl, cbtw */ |
13130 | USED_REX (REX_W); | |
13131 | if (rex & REX_W) | |
13132 | { | |
13133 | if (intel_syntax) | |
13134 | *obufp++ = 'd'; | |
13135 | else | |
13136 | *obufp++ = 'l'; | |
13137 | } | |
13138 | else if (sizeflag & DFLAG) | |
13139 | *obufp++ = 'w'; | |
a35ca55a | 13140 | else |
0bfee649 L |
13141 | *obufp++ = 'b'; |
13142 | if (!(rex & REX_W)) | |
13143 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 13144 | } |
252b5132 | 13145 | else |
0bfee649 | 13146 | { |
6c30d220 L |
13147 | if (l != 1 |
13148 | || len != 2 | |
13149 | || (last[0] != 'X' | |
13150 | && last[0] != 'L')) | |
0bfee649 L |
13151 | { |
13152 | SAVE_LAST (*p); | |
13153 | break; | |
13154 | } | |
13155 | if (!need_vex) | |
13156 | abort (); | |
6c30d220 L |
13157 | if (last[0] == 'X') |
13158 | *obufp++ = vex.w ? 'd': 's'; | |
13159 | else | |
13160 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 13161 | } |
252b5132 | 13162 | break; |
a72d2af2 L |
13163 | case '^': |
13164 | if (intel_syntax) | |
13165 | break; | |
5990e377 JB |
13166 | if (isa64 == intel64 && (rex & REX_W)) |
13167 | { | |
13168 | USED_REX (REX_W); | |
13169 | *obufp++ = 'q'; | |
13170 | break; | |
13171 | } | |
a72d2af2 L |
13172 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
13173 | { | |
13174 | if (sizeflag & DFLAG) | |
13175 | *obufp++ = 'l'; | |
13176 | else | |
13177 | *obufp++ = 'w'; | |
13178 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13179 | } | |
13180 | break; | |
5db04b09 L |
13181 | case '@': |
13182 | if (intel_syntax) | |
13183 | break; | |
13184 | if (address_mode == mode_64bit | |
13185 | && (isa64 == intel64 | |
13186 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
13187 | *obufp++ = 'q'; | |
13188 | else if ((prefixes & PREFIX_DATA)) | |
13189 | { | |
13190 | if (!(sizeflag & DFLAG)) | |
13191 | *obufp++ = 'w'; | |
13192 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13193 | } | |
13194 | break; | |
252b5132 RH |
13195 | } |
13196 | } | |
13197 | *obufp = 0; | |
ea397f5b | 13198 | mnemonicendp = obufp; |
6439fc28 | 13199 | return 0; |
252b5132 RH |
13200 | } |
13201 | ||
13202 | static void | |
26ca5450 | 13203 | oappend (const char *s) |
252b5132 | 13204 | { |
ea397f5b | 13205 | obufp = stpcpy (obufp, s); |
252b5132 RH |
13206 | } |
13207 | ||
13208 | static void | |
26ca5450 | 13209 | append_seg (void) |
252b5132 | 13210 | { |
285ca992 L |
13211 | /* Only print the active segment register. */ |
13212 | if (!active_seg_prefix) | |
13213 | return; | |
13214 | ||
13215 | used_prefixes |= active_seg_prefix; | |
13216 | switch (active_seg_prefix) | |
7d421014 | 13217 | { |
285ca992 | 13218 | case PREFIX_CS: |
9ce09ba2 | 13219 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
13220 | break; |
13221 | case PREFIX_DS: | |
9ce09ba2 | 13222 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
13223 | break; |
13224 | case PREFIX_SS: | |
9ce09ba2 | 13225 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
13226 | break; |
13227 | case PREFIX_ES: | |
9ce09ba2 | 13228 | oappend_maybe_intel ("%es:"); |
285ca992 L |
13229 | break; |
13230 | case PREFIX_FS: | |
9ce09ba2 | 13231 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
13232 | break; |
13233 | case PREFIX_GS: | |
9ce09ba2 | 13234 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
13235 | break; |
13236 | default: | |
13237 | break; | |
7d421014 | 13238 | } |
252b5132 RH |
13239 | } |
13240 | ||
13241 | static void | |
26ca5450 | 13242 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
13243 | { |
13244 | if (!intel_syntax) | |
13245 | oappend ("*"); | |
13246 | OP_E (bytemode, sizeflag); | |
13247 | } | |
13248 | ||
52b15da3 | 13249 | static void |
26ca5450 | 13250 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 13251 | { |
cb712a9e | 13252 | if (address_mode == mode_64bit) |
52b15da3 JH |
13253 | { |
13254 | if (hex) | |
13255 | { | |
13256 | char tmp[30]; | |
13257 | int i; | |
13258 | buf[0] = '0'; | |
13259 | buf[1] = 'x'; | |
13260 | sprintf_vma (tmp, disp); | |
6608db57 | 13261 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
13262 | strcpy (buf + 2, tmp + i); |
13263 | } | |
13264 | else | |
13265 | { | |
13266 | bfd_signed_vma v = disp; | |
13267 | char tmp[30]; | |
13268 | int i; | |
13269 | if (v < 0) | |
13270 | { | |
13271 | *(buf++) = '-'; | |
13272 | v = -disp; | |
6608db57 | 13273 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
13274 | if (v < 0) |
13275 | { | |
13276 | strcpy (buf, "9223372036854775808"); | |
13277 | return; | |
13278 | } | |
13279 | } | |
13280 | if (!v) | |
13281 | { | |
13282 | strcpy (buf, "0"); | |
13283 | return; | |
13284 | } | |
13285 | ||
13286 | i = 0; | |
13287 | tmp[29] = 0; | |
13288 | while (v) | |
13289 | { | |
6608db57 | 13290 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
13291 | v /= 10; |
13292 | i++; | |
13293 | } | |
13294 | strcpy (buf, tmp + 29 - i); | |
13295 | } | |
13296 | } | |
13297 | else | |
13298 | { | |
13299 | if (hex) | |
13300 | sprintf (buf, "0x%x", (unsigned int) disp); | |
13301 | else | |
13302 | sprintf (buf, "%d", (int) disp); | |
13303 | } | |
13304 | } | |
13305 | ||
5d669648 L |
13306 | /* Put DISP in BUF as signed hex number. */ |
13307 | ||
13308 | static void | |
13309 | print_displacement (char *buf, bfd_vma disp) | |
13310 | { | |
13311 | bfd_signed_vma val = disp; | |
13312 | char tmp[30]; | |
13313 | int i, j = 0; | |
13314 | ||
13315 | if (val < 0) | |
13316 | { | |
13317 | buf[j++] = '-'; | |
13318 | val = -disp; | |
13319 | ||
13320 | /* Check for possible overflow. */ | |
13321 | if (val < 0) | |
13322 | { | |
13323 | switch (address_mode) | |
13324 | { | |
13325 | case mode_64bit: | |
13326 | strcpy (buf + j, "0x8000000000000000"); | |
13327 | break; | |
13328 | case mode_32bit: | |
13329 | strcpy (buf + j, "0x80000000"); | |
13330 | break; | |
13331 | case mode_16bit: | |
13332 | strcpy (buf + j, "0x8000"); | |
13333 | break; | |
13334 | } | |
13335 | return; | |
13336 | } | |
13337 | } | |
13338 | ||
13339 | buf[j++] = '0'; | |
13340 | buf[j++] = 'x'; | |
13341 | ||
0af1713e | 13342 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
13343 | for (i = 0; tmp[i] == '0'; i++) |
13344 | continue; | |
13345 | if (tmp[i] == '\0') | |
13346 | i--; | |
13347 | strcpy (buf + j, tmp + i); | |
13348 | } | |
13349 | ||
3f31e633 JB |
13350 | static void |
13351 | intel_operand_size (int bytemode, int sizeflag) | |
13352 | { | |
43234a1e L |
13353 | if (vex.evex |
13354 | && vex.b | |
13355 | && (bytemode == x_mode | |
13356 | || bytemode == evex_half_bcst_xmmq_mode)) | |
13357 | { | |
13358 | if (vex.w) | |
13359 | oappend ("QWORD PTR "); | |
13360 | else | |
13361 | oappend ("DWORD PTR "); | |
13362 | return; | |
13363 | } | |
3f31e633 JB |
13364 | switch (bytemode) |
13365 | { | |
13366 | case b_mode: | |
b6169b20 | 13367 | case b_swap_mode: |
42903f7f | 13368 | case dqb_mode: |
1ba585e8 | 13369 | case db_mode: |
3f31e633 JB |
13370 | oappend ("BYTE PTR "); |
13371 | break; | |
13372 | case w_mode: | |
1ba585e8 | 13373 | case dw_mode: |
3f31e633 JB |
13374 | case dqw_mode: |
13375 | oappend ("WORD PTR "); | |
13376 | break; | |
07f5af7d L |
13377 | case indir_v_mode: |
13378 | if (address_mode == mode_64bit && isa64 == intel64) | |
13379 | { | |
13380 | oappend ("QWORD PTR "); | |
13381 | break; | |
13382 | } | |
1a0670f3 | 13383 | /* Fall through. */ |
1a114b12 | 13384 | case stack_v_mode: |
7bb15c6f | 13385 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
13386 | { |
13387 | oappend ("QWORD PTR "); | |
3f31e633 JB |
13388 | break; |
13389 | } | |
1a0670f3 | 13390 | /* Fall through. */ |
3f31e633 | 13391 | case v_mode: |
b6169b20 | 13392 | case v_swap_mode: |
3f31e633 | 13393 | case dq_mode: |
161a04f6 L |
13394 | USED_REX (REX_W); |
13395 | if (rex & REX_W) | |
3f31e633 | 13396 | oappend ("QWORD PTR "); |
3f31e633 | 13397 | else |
f16cd0d5 L |
13398 | { |
13399 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
13400 | oappend ("DWORD PTR "); | |
13401 | else | |
13402 | oappend ("WORD PTR "); | |
13403 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13404 | } | |
3f31e633 | 13405 | break; |
52fd6d94 | 13406 | case z_mode: |
161a04f6 | 13407 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13408 | *obufp++ = 'D'; |
13409 | oappend ("WORD PTR "); | |
161a04f6 | 13410 | if (!(rex & REX_W)) |
52fd6d94 JB |
13411 | used_prefixes |= (prefixes & PREFIX_DATA); |
13412 | break; | |
34b772a6 JB |
13413 | case a_mode: |
13414 | if (sizeflag & DFLAG) | |
13415 | oappend ("QWORD PTR "); | |
13416 | else | |
13417 | oappend ("DWORD PTR "); | |
13418 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13419 | break; | |
bc31405e L |
13420 | case movsxd_mode: |
13421 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
13422 | oappend ("WORD PTR "); | |
13423 | else | |
13424 | oappend ("DWORD PTR "); | |
13425 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13426 | break; | |
3f31e633 | 13427 | case d_mode: |
539f890d | 13428 | case d_scalar_swap_mode: |
fa99fab2 | 13429 | case d_swap_mode: |
42903f7f | 13430 | case dqd_mode: |
3f31e633 JB |
13431 | oappend ("DWORD PTR "); |
13432 | break; | |
13433 | case q_mode: | |
539f890d | 13434 | case q_scalar_swap_mode: |
b6169b20 | 13435 | case q_swap_mode: |
3f31e633 JB |
13436 | oappend ("QWORD PTR "); |
13437 | break; | |
13438 | case m_mode: | |
cb712a9e | 13439 | if (address_mode == mode_64bit) |
3f31e633 JB |
13440 | oappend ("QWORD PTR "); |
13441 | else | |
13442 | oappend ("DWORD PTR "); | |
13443 | break; | |
13444 | case f_mode: | |
13445 | if (sizeflag & DFLAG) | |
13446 | oappend ("FWORD PTR "); | |
13447 | else | |
13448 | oappend ("DWORD PTR "); | |
13449 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13450 | break; | |
13451 | case t_mode: | |
13452 | oappend ("TBYTE PTR "); | |
13453 | break; | |
13454 | case x_mode: | |
b6169b20 | 13455 | case x_swap_mode: |
43234a1e L |
13456 | case evex_x_gscat_mode: |
13457 | case evex_x_nobcst_mode: | |
53467f57 IT |
13458 | case b_scalar_mode: |
13459 | case w_scalar_mode: | |
c0f3af97 L |
13460 | if (need_vex) |
13461 | { | |
13462 | switch (vex.length) | |
13463 | { | |
13464 | case 128: | |
13465 | oappend ("XMMWORD PTR "); | |
13466 | break; | |
13467 | case 256: | |
13468 | oappend ("YMMWORD PTR "); | |
13469 | break; | |
43234a1e L |
13470 | case 512: |
13471 | oappend ("ZMMWORD PTR "); | |
13472 | break; | |
c0f3af97 L |
13473 | default: |
13474 | abort (); | |
13475 | } | |
13476 | } | |
13477 | else | |
13478 | oappend ("XMMWORD PTR "); | |
13479 | break; | |
13480 | case xmm_mode: | |
3f31e633 JB |
13481 | oappend ("XMMWORD PTR "); |
13482 | break; | |
43234a1e L |
13483 | case ymm_mode: |
13484 | oappend ("YMMWORD PTR "); | |
13485 | break; | |
c0f3af97 | 13486 | case xmmq_mode: |
43234a1e | 13487 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
13488 | if (!need_vex) |
13489 | abort (); | |
13490 | ||
13491 | switch (vex.length) | |
13492 | { | |
13493 | case 128: | |
13494 | oappend ("QWORD PTR "); | |
13495 | break; | |
13496 | case 256: | |
13497 | oappend ("XMMWORD PTR "); | |
13498 | break; | |
43234a1e L |
13499 | case 512: |
13500 | oappend ("YMMWORD PTR "); | |
13501 | break; | |
c0f3af97 L |
13502 | default: |
13503 | abort (); | |
13504 | } | |
13505 | break; | |
6c30d220 L |
13506 | case xmm_mb_mode: |
13507 | if (!need_vex) | |
13508 | abort (); | |
13509 | ||
13510 | switch (vex.length) | |
13511 | { | |
13512 | case 128: | |
13513 | case 256: | |
43234a1e | 13514 | case 512: |
6c30d220 L |
13515 | oappend ("BYTE PTR "); |
13516 | break; | |
13517 | default: | |
13518 | abort (); | |
13519 | } | |
13520 | break; | |
13521 | case xmm_mw_mode: | |
13522 | if (!need_vex) | |
13523 | abort (); | |
13524 | ||
13525 | switch (vex.length) | |
13526 | { | |
13527 | case 128: | |
13528 | case 256: | |
43234a1e | 13529 | case 512: |
6c30d220 L |
13530 | oappend ("WORD PTR "); |
13531 | break; | |
13532 | default: | |
13533 | abort (); | |
13534 | } | |
13535 | break; | |
13536 | case xmm_md_mode: | |
13537 | if (!need_vex) | |
13538 | abort (); | |
13539 | ||
13540 | switch (vex.length) | |
13541 | { | |
13542 | case 128: | |
13543 | case 256: | |
43234a1e | 13544 | case 512: |
6c30d220 L |
13545 | oappend ("DWORD PTR "); |
13546 | break; | |
13547 | default: | |
13548 | abort (); | |
13549 | } | |
13550 | break; | |
13551 | case xmm_mq_mode: | |
13552 | if (!need_vex) | |
13553 | abort (); | |
13554 | ||
13555 | switch (vex.length) | |
13556 | { | |
13557 | case 128: | |
13558 | case 256: | |
43234a1e | 13559 | case 512: |
6c30d220 L |
13560 | oappend ("QWORD PTR "); |
13561 | break; | |
13562 | default: | |
13563 | abort (); | |
13564 | } | |
13565 | break; | |
13566 | case xmmdw_mode: | |
13567 | if (!need_vex) | |
13568 | abort (); | |
13569 | ||
13570 | switch (vex.length) | |
13571 | { | |
13572 | case 128: | |
13573 | oappend ("WORD PTR "); | |
13574 | break; | |
13575 | case 256: | |
13576 | oappend ("DWORD PTR "); | |
13577 | break; | |
43234a1e L |
13578 | case 512: |
13579 | oappend ("QWORD PTR "); | |
13580 | break; | |
6c30d220 L |
13581 | default: |
13582 | abort (); | |
13583 | } | |
13584 | break; | |
13585 | case xmmqd_mode: | |
13586 | if (!need_vex) | |
13587 | abort (); | |
13588 | ||
13589 | switch (vex.length) | |
13590 | { | |
13591 | case 128: | |
13592 | oappend ("DWORD PTR "); | |
13593 | break; | |
13594 | case 256: | |
13595 | oappend ("QWORD PTR "); | |
13596 | break; | |
43234a1e L |
13597 | case 512: |
13598 | oappend ("XMMWORD PTR "); | |
13599 | break; | |
6c30d220 L |
13600 | default: |
13601 | abort (); | |
13602 | } | |
13603 | break; | |
c0f3af97 L |
13604 | case ymmq_mode: |
13605 | if (!need_vex) | |
13606 | abort (); | |
13607 | ||
13608 | switch (vex.length) | |
13609 | { | |
13610 | case 128: | |
13611 | oappend ("QWORD PTR "); | |
13612 | break; | |
13613 | case 256: | |
13614 | oappend ("YMMWORD PTR "); | |
13615 | break; | |
43234a1e L |
13616 | case 512: |
13617 | oappend ("ZMMWORD PTR "); | |
13618 | break; | |
c0f3af97 L |
13619 | default: |
13620 | abort (); | |
13621 | } | |
13622 | break; | |
6c30d220 L |
13623 | case ymmxmm_mode: |
13624 | if (!need_vex) | |
13625 | abort (); | |
13626 | ||
13627 | switch (vex.length) | |
13628 | { | |
13629 | case 128: | |
13630 | case 256: | |
13631 | oappend ("XMMWORD PTR "); | |
13632 | break; | |
13633 | default: | |
13634 | abort (); | |
13635 | } | |
13636 | break; | |
fb9c77c7 L |
13637 | case o_mode: |
13638 | oappend ("OWORD PTR "); | |
13639 | break; | |
1c480963 | 13640 | case vex_scalar_w_dq_mode: |
0bfee649 L |
13641 | if (!need_vex) |
13642 | abort (); | |
13643 | ||
13644 | if (vex.w) | |
13645 | oappend ("QWORD PTR "); | |
13646 | else | |
13647 | oappend ("DWORD PTR "); | |
13648 | break; | |
43234a1e L |
13649 | case vex_vsib_d_w_dq_mode: |
13650 | case vex_vsib_q_w_dq_mode: | |
13651 | if (!need_vex) | |
13652 | abort (); | |
13653 | ||
13654 | if (!vex.evex) | |
13655 | { | |
13656 | if (vex.w) | |
13657 | oappend ("QWORD PTR "); | |
13658 | else | |
13659 | oappend ("DWORD PTR "); | |
13660 | } | |
13661 | else | |
13662 | { | |
b28d1bda IT |
13663 | switch (vex.length) |
13664 | { | |
13665 | case 128: | |
13666 | oappend ("XMMWORD PTR "); | |
13667 | break; | |
13668 | case 256: | |
13669 | oappend ("YMMWORD PTR "); | |
13670 | break; | |
13671 | case 512: | |
13672 | oappend ("ZMMWORD PTR "); | |
13673 | break; | |
13674 | default: | |
13675 | abort (); | |
13676 | } | |
43234a1e L |
13677 | } |
13678 | break; | |
5fc35d96 IT |
13679 | case vex_vsib_q_w_d_mode: |
13680 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 13681 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
13682 | abort (); |
13683 | ||
b28d1bda IT |
13684 | switch (vex.length) |
13685 | { | |
13686 | case 128: | |
13687 | oappend ("QWORD PTR "); | |
13688 | break; | |
13689 | case 256: | |
13690 | oappend ("XMMWORD PTR "); | |
13691 | break; | |
13692 | case 512: | |
13693 | oappend ("YMMWORD PTR "); | |
13694 | break; | |
13695 | default: | |
13696 | abort (); | |
13697 | } | |
5fc35d96 IT |
13698 | |
13699 | break; | |
1ba585e8 IT |
13700 | case mask_bd_mode: |
13701 | if (!need_vex || vex.length != 128) | |
13702 | abort (); | |
13703 | if (vex.w) | |
13704 | oappend ("DWORD PTR "); | |
13705 | else | |
13706 | oappend ("BYTE PTR "); | |
13707 | break; | |
43234a1e L |
13708 | case mask_mode: |
13709 | if (!need_vex) | |
13710 | abort (); | |
1ba585e8 IT |
13711 | if (vex.w) |
13712 | oappend ("QWORD PTR "); | |
13713 | else | |
13714 | oappend ("WORD PTR "); | |
43234a1e | 13715 | break; |
6c75cc62 | 13716 | case v_bnd_mode: |
d276ec69 | 13717 | case v_bndmk_mode: |
3f31e633 JB |
13718 | default: |
13719 | break; | |
13720 | } | |
13721 | } | |
13722 | ||
252b5132 | 13723 | static void |
c0f3af97 | 13724 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 13725 | { |
c0f3af97 L |
13726 | int reg = modrm.rm; |
13727 | const char **names; | |
252b5132 | 13728 | |
c0f3af97 L |
13729 | USED_REX (REX_B); |
13730 | if ((rex & REX_B)) | |
13731 | reg += 8; | |
252b5132 | 13732 | |
b6169b20 | 13733 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 13734 | && (bytemode == b_swap_mode |
9f79e886 | 13735 | || bytemode == bnd_swap_mode |
60227d64 | 13736 | || bytemode == v_swap_mode)) |
b6169b20 L |
13737 | swap_operand (); |
13738 | ||
c0f3af97 | 13739 | switch (bytemode) |
252b5132 | 13740 | { |
c0f3af97 | 13741 | case b_mode: |
b6169b20 | 13742 | case b_swap_mode: |
c0f3af97 L |
13743 | USED_REX (0); |
13744 | if (rex) | |
13745 | names = names8rex; | |
13746 | else | |
13747 | names = names8; | |
13748 | break; | |
13749 | case w_mode: | |
13750 | names = names16; | |
13751 | break; | |
13752 | case d_mode: | |
1ba585e8 IT |
13753 | case dw_mode: |
13754 | case db_mode: | |
c0f3af97 L |
13755 | names = names32; |
13756 | break; | |
13757 | case q_mode: | |
13758 | names = names64; | |
13759 | break; | |
13760 | case m_mode: | |
6c75cc62 | 13761 | case v_bnd_mode: |
c0f3af97 L |
13762 | names = address_mode == mode_64bit ? names64 : names32; |
13763 | break; | |
7e8b059b | 13764 | case bnd_mode: |
9f79e886 | 13765 | case bnd_swap_mode: |
0d96e4df L |
13766 | if (reg > 0x3) |
13767 | { | |
13768 | oappend ("(bad)"); | |
13769 | return; | |
13770 | } | |
7e8b059b L |
13771 | names = names_bnd; |
13772 | break; | |
07f5af7d L |
13773 | case indir_v_mode: |
13774 | if (address_mode == mode_64bit && isa64 == intel64) | |
13775 | { | |
13776 | names = names64; | |
13777 | break; | |
13778 | } | |
1a0670f3 | 13779 | /* Fall through. */ |
c0f3af97 | 13780 | case stack_v_mode: |
7bb15c6f | 13781 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 13782 | { |
c0f3af97 | 13783 | names = names64; |
252b5132 | 13784 | break; |
252b5132 | 13785 | } |
c0f3af97 | 13786 | bytemode = v_mode; |
1a0670f3 | 13787 | /* Fall through. */ |
c0f3af97 | 13788 | case v_mode: |
b6169b20 | 13789 | case v_swap_mode: |
c0f3af97 L |
13790 | case dq_mode: |
13791 | case dqb_mode: | |
13792 | case dqd_mode: | |
13793 | case dqw_mode: | |
13794 | USED_REX (REX_W); | |
13795 | if (rex & REX_W) | |
13796 | names = names64; | |
c0f3af97 | 13797 | else |
f16cd0d5 | 13798 | { |
7bb15c6f | 13799 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
13800 | || (bytemode != v_mode |
13801 | && bytemode != v_swap_mode)) | |
13802 | names = names32; | |
13803 | else | |
13804 | names = names16; | |
13805 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13806 | } | |
c0f3af97 | 13807 | break; |
bc31405e L |
13808 | case movsxd_mode: |
13809 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
13810 | names = names16; | |
13811 | else | |
13812 | names = names32; | |
13813 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13814 | break; | |
de89d0a3 IT |
13815 | case va_mode: |
13816 | names = (address_mode == mode_64bit | |
13817 | ? names64 : names32); | |
13818 | if (!(prefixes & PREFIX_ADDR)) | |
aa178437 IT |
13819 | names = (address_mode == mode_16bit |
13820 | ? names16 : names); | |
de89d0a3 IT |
13821 | else |
13822 | { | |
13823 | /* Remove "addr16/addr32". */ | |
13824 | all_prefixes[last_addr_prefix] = 0; | |
13825 | names = (address_mode != mode_32bit | |
13826 | ? names32 : names16); | |
13827 | used_prefixes |= PREFIX_ADDR; | |
13828 | } | |
13829 | break; | |
1ba585e8 | 13830 | case mask_bd_mode: |
43234a1e | 13831 | case mask_mode: |
9889cbb1 L |
13832 | if (reg > 0x7) |
13833 | { | |
13834 | oappend ("(bad)"); | |
13835 | return; | |
13836 | } | |
43234a1e L |
13837 | names = names_mask; |
13838 | break; | |
c0f3af97 L |
13839 | case 0: |
13840 | return; | |
13841 | default: | |
13842 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
13843 | return; |
13844 | } | |
c0f3af97 L |
13845 | oappend (names[reg]); |
13846 | } | |
13847 | ||
13848 | static void | |
c1e679ec | 13849 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
13850 | { |
13851 | bfd_vma disp = 0; | |
13852 | int add = (rex & REX_B) ? 8 : 0; | |
13853 | int riprel = 0; | |
43234a1e L |
13854 | int shift; |
13855 | ||
13856 | if (vex.evex) | |
13857 | { | |
13858 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
13859 | if (vex.b | |
13860 | && bytemode != x_mode | |
90a915bf | 13861 | && bytemode != xmmq_mode |
43234a1e L |
13862 | && bytemode != evex_half_bcst_xmmq_mode) |
13863 | { | |
13864 | BadOp (); | |
13865 | return; | |
13866 | } | |
13867 | switch (bytemode) | |
13868 | { | |
1ba585e8 IT |
13869 | case dqw_mode: |
13870 | case dw_mode: | |
1ba585e8 IT |
13871 | shift = 1; |
13872 | break; | |
13873 | case dqb_mode: | |
13874 | case db_mode: | |
13875 | shift = 0; | |
13876 | break; | |
b50c9f31 JB |
13877 | case dq_mode: |
13878 | if (address_mode != mode_64bit) | |
13879 | { | |
13880 | shift = 2; | |
13881 | break; | |
13882 | } | |
13883 | /* fall through */ | |
4102be5c | 13884 | case vex_scalar_w_dq_mode: |
43234a1e | 13885 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 13886 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 13887 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 13888 | case vex_vsib_q_w_d_mode: |
43234a1e | 13889 | case evex_x_gscat_mode: |
43234a1e L |
13890 | shift = vex.w ? 3 : 2; |
13891 | break; | |
43234a1e L |
13892 | case x_mode: |
13893 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 13894 | case xmmq_mode: |
43234a1e L |
13895 | if (vex.b) |
13896 | { | |
13897 | shift = vex.w ? 3 : 2; | |
13898 | break; | |
13899 | } | |
1a0670f3 | 13900 | /* Fall through. */ |
43234a1e L |
13901 | case xmmqd_mode: |
13902 | case xmmdw_mode: | |
43234a1e L |
13903 | case ymmq_mode: |
13904 | case evex_x_nobcst_mode: | |
13905 | case x_swap_mode: | |
13906 | switch (vex.length) | |
13907 | { | |
13908 | case 128: | |
13909 | shift = 4; | |
13910 | break; | |
13911 | case 256: | |
13912 | shift = 5; | |
13913 | break; | |
13914 | case 512: | |
13915 | shift = 6; | |
13916 | break; | |
13917 | default: | |
13918 | abort (); | |
13919 | } | |
13920 | break; | |
13921 | case ymm_mode: | |
13922 | shift = 5; | |
13923 | break; | |
13924 | case xmm_mode: | |
13925 | shift = 4; | |
13926 | break; | |
13927 | case xmm_mq_mode: | |
13928 | case q_mode: | |
43234a1e L |
13929 | case q_swap_mode: |
13930 | case q_scalar_swap_mode: | |
13931 | shift = 3; | |
13932 | break; | |
13933 | case dqd_mode: | |
13934 | case xmm_md_mode: | |
13935 | case d_mode: | |
43234a1e L |
13936 | case d_swap_mode: |
13937 | case d_scalar_swap_mode: | |
13938 | shift = 2; | |
13939 | break; | |
5074ad8a | 13940 | case w_scalar_mode: |
43234a1e L |
13941 | case xmm_mw_mode: |
13942 | shift = 1; | |
13943 | break; | |
5074ad8a | 13944 | case b_scalar_mode: |
43234a1e L |
13945 | case xmm_mb_mode: |
13946 | shift = 0; | |
13947 | break; | |
13948 | default: | |
13949 | abort (); | |
13950 | } | |
13951 | /* Make necessary corrections to shift for modes that need it. | |
13952 | For these modes we currently have shift 4, 5 or 6 depending on | |
13953 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
13954 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
13955 | xmmq_mode). In case of broadcast enabled the corrections | |
13956 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
13957 | if (!vex.b |
13958 | && (bytemode == xmmq_mode | |
13959 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
13960 | shift -= 1; |
13961 | else if (bytemode == xmmqd_mode) | |
13962 | shift -= 2; | |
13963 | else if (bytemode == xmmdw_mode) | |
13964 | shift -= 3; | |
b28d1bda IT |
13965 | else if (bytemode == ymmq_mode && vex.length == 128) |
13966 | shift -= 1; | |
43234a1e L |
13967 | } |
13968 | else | |
13969 | shift = 0; | |
252b5132 | 13970 | |
c0f3af97 | 13971 | USED_REX (REX_B); |
3f31e633 JB |
13972 | if (intel_syntax) |
13973 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
13974 | append_seg (); |
13975 | ||
5d669648 | 13976 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 13977 | { |
5d669648 L |
13978 | /* 32/64 bit address mode */ |
13979 | int havedisp; | |
252b5132 RH |
13980 | int havesib; |
13981 | int havebase; | |
0f7da397 | 13982 | int haveindex; |
20afcfb7 | 13983 | int needindex; |
1bc60e56 | 13984 | int needaddr32; |
82c18208 | 13985 | int base, rbase; |
91d6fa6a | 13986 | int vindex = 0; |
252b5132 | 13987 | int scale = 0; |
7e8b059b L |
13988 | int addr32flag = !((sizeflag & AFLAG) |
13989 | || bytemode == v_bnd_mode | |
d276ec69 | 13990 | || bytemode == v_bndmk_mode |
9f79e886 JB |
13991 | || bytemode == bnd_mode |
13992 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
13993 | const char **indexes64 = names64; |
13994 | const char **indexes32 = names32; | |
252b5132 RH |
13995 | |
13996 | havesib = 0; | |
13997 | havebase = 1; | |
0f7da397 | 13998 | haveindex = 0; |
7967e09e | 13999 | base = modrm.rm; |
252b5132 RH |
14000 | |
14001 | if (base == 4) | |
14002 | { | |
14003 | havesib = 1; | |
dfc8cf43 | 14004 | vindex = sib.index; |
161a04f6 L |
14005 | USED_REX (REX_X); |
14006 | if (rex & REX_X) | |
91d6fa6a | 14007 | vindex += 8; |
6c30d220 L |
14008 | switch (bytemode) |
14009 | { | |
14010 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 14011 | case vex_vsib_d_w_d_mode: |
6c30d220 | 14012 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14013 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
14014 | if (!need_vex) |
14015 | abort (); | |
43234a1e L |
14016 | if (vex.evex) |
14017 | { | |
14018 | if (!vex.v) | |
14019 | vindex += 16; | |
14020 | } | |
6c30d220 L |
14021 | |
14022 | haveindex = 1; | |
14023 | switch (vex.length) | |
14024 | { | |
14025 | case 128: | |
7bb15c6f | 14026 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
14027 | break; |
14028 | case 256: | |
5fc35d96 IT |
14029 | if (!vex.w |
14030 | || bytemode == vex_vsib_q_w_dq_mode | |
14031 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 14032 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 14033 | else |
7bb15c6f | 14034 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 14035 | break; |
43234a1e | 14036 | case 512: |
5fc35d96 IT |
14037 | if (!vex.w |
14038 | || bytemode == vex_vsib_q_w_dq_mode | |
14039 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
14040 | indexes64 = indexes32 = names_zmm; |
14041 | else | |
14042 | indexes64 = indexes32 = names_ymm; | |
14043 | break; | |
6c30d220 L |
14044 | default: |
14045 | abort (); | |
14046 | } | |
14047 | break; | |
14048 | default: | |
14049 | haveindex = vindex != 4; | |
14050 | break; | |
14051 | } | |
14052 | scale = sib.scale; | |
14053 | base = sib.base; | |
252b5132 RH |
14054 | codep++; |
14055 | } | |
82c18208 | 14056 | rbase = base + add; |
252b5132 | 14057 | |
7967e09e | 14058 | switch (modrm.mod) |
252b5132 RH |
14059 | { |
14060 | case 0: | |
82c18208 | 14061 | if (base == 5) |
252b5132 RH |
14062 | { |
14063 | havebase = 0; | |
cb712a9e | 14064 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
14065 | riprel = 1; |
14066 | disp = get32s (); | |
d276ec69 JB |
14067 | if (riprel && bytemode == v_bndmk_mode) |
14068 | { | |
14069 | oappend ("(bad)"); | |
14070 | return; | |
14071 | } | |
252b5132 RH |
14072 | } |
14073 | break; | |
14074 | case 1: | |
14075 | FETCH_DATA (the_info, codep + 1); | |
14076 | disp = *codep++; | |
14077 | if ((disp & 0x80) != 0) | |
14078 | disp -= 0x100; | |
43234a1e L |
14079 | if (vex.evex && shift > 0) |
14080 | disp <<= shift; | |
252b5132 RH |
14081 | break; |
14082 | case 2: | |
52b15da3 | 14083 | disp = get32s (); |
252b5132 RH |
14084 | break; |
14085 | } | |
14086 | ||
1bc60e56 L |
14087 | needindex = 0; |
14088 | needaddr32 = 0; | |
14089 | if (havesib | |
14090 | && !havebase | |
14091 | && !haveindex | |
14092 | && address_mode != mode_16bit) | |
14093 | { | |
14094 | if (address_mode == mode_64bit) | |
14095 | { | |
14096 | /* Display eiz instead of addr32. */ | |
14097 | needindex = addr32flag; | |
14098 | needaddr32 = 1; | |
14099 | } | |
14100 | else | |
14101 | { | |
14102 | /* In 32-bit mode, we need index register to tell [offset] | |
14103 | from [eiz*1 + offset]. */ | |
14104 | needindex = 1; | |
14105 | } | |
14106 | } | |
14107 | ||
20afcfb7 L |
14108 | havedisp = (havebase |
14109 | || needindex | |
14110 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 14111 | |
252b5132 | 14112 | if (!intel_syntax) |
82c18208 | 14113 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14114 | { |
5d669648 L |
14115 | if (havedisp || riprel) |
14116 | print_displacement (scratchbuf, disp); | |
14117 | else | |
14118 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 14119 | oappend (scratchbuf); |
52b15da3 JH |
14120 | if (riprel) |
14121 | { | |
14122 | set_op (disp, 1); | |
28596323 | 14123 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 14124 | } |
db6eb5be | 14125 | } |
2da11e11 | 14126 | |
c1dc7af5 | 14127 | if ((havebase || haveindex || needindex || needaddr32 || riprel) |
a23b33b3 JB |
14128 | && (address_mode != mode_64bit |
14129 | || ((bytemode != v_bnd_mode) | |
14130 | && (bytemode != v_bndmk_mode) | |
14131 | && (bytemode != bnd_mode) | |
14132 | && (bytemode != bnd_swap_mode)))) | |
87767711 JB |
14133 | used_prefixes |= PREFIX_ADDR; |
14134 | ||
5d669648 | 14135 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 14136 | { |
252b5132 | 14137 | *obufp++ = open_char; |
52b15da3 | 14138 | if (intel_syntax && riprel) |
185b1163 L |
14139 | { |
14140 | set_op (disp, 1); | |
28596323 | 14141 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 14142 | } |
db6eb5be | 14143 | *obufp = '\0'; |
252b5132 | 14144 | if (havebase) |
7e8b059b | 14145 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 14146 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
14147 | if (havesib) |
14148 | { | |
db51cc60 L |
14149 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
14150 | print index to tell base + index from base. */ | |
14151 | if (scale != 0 | |
20afcfb7 | 14152 | || needindex |
db51cc60 L |
14153 | || haveindex |
14154 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 14155 | { |
9306ca4a | 14156 | if (!intel_syntax || havebase) |
db6eb5be | 14157 | { |
9306ca4a JB |
14158 | *obufp++ = separator_char; |
14159 | *obufp = '\0'; | |
db6eb5be | 14160 | } |
db51cc60 | 14161 | if (haveindex) |
7e8b059b | 14162 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 14163 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 14164 | else |
7e8b059b | 14165 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
14166 | ? index64 : index32); |
14167 | ||
db6eb5be AM |
14168 | *obufp++ = scale_char; |
14169 | *obufp = '\0'; | |
14170 | sprintf (scratchbuf, "%d", 1 << scale); | |
14171 | oappend (scratchbuf); | |
14172 | } | |
252b5132 | 14173 | } |
185b1163 | 14174 | if (intel_syntax |
82c18208 | 14175 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 14176 | { |
db51cc60 | 14177 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14178 | { |
14179 | *obufp++ = '+'; | |
14180 | *obufp = '\0'; | |
14181 | } | |
05203043 | 14182 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
14183 | { |
14184 | *obufp++ = '-'; | |
14185 | *obufp = '\0'; | |
14186 | disp = - (bfd_signed_vma) disp; | |
14187 | } | |
14188 | ||
db51cc60 L |
14189 | if (havedisp) |
14190 | print_displacement (scratchbuf, disp); | |
14191 | else | |
14192 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
14193 | oappend (scratchbuf); |
14194 | } | |
252b5132 RH |
14195 | |
14196 | *obufp++ = close_char; | |
db6eb5be | 14197 | *obufp = '\0'; |
252b5132 RH |
14198 | } |
14199 | else if (intel_syntax) | |
db6eb5be | 14200 | { |
82c18208 | 14201 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14202 | { |
285ca992 | 14203 | if (!active_seg_prefix) |
252b5132 | 14204 | { |
d708bcba | 14205 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14206 | oappend (":"); |
14207 | } | |
52b15da3 | 14208 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
14209 | oappend (scratchbuf); |
14210 | } | |
14211 | } | |
252b5132 | 14212 | } |
a23b33b3 JB |
14213 | else if (bytemode == v_bnd_mode |
14214 | || bytemode == v_bndmk_mode | |
14215 | || bytemode == bnd_mode | |
14216 | || bytemode == bnd_swap_mode) | |
14217 | { | |
14218 | oappend ("(bad)"); | |
14219 | return; | |
14220 | } | |
252b5132 | 14221 | else |
f16cd0d5 L |
14222 | { |
14223 | /* 16 bit address mode */ | |
14224 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 14225 | switch (modrm.mod) |
252b5132 RH |
14226 | { |
14227 | case 0: | |
7967e09e | 14228 | if (modrm.rm == 6) |
252b5132 RH |
14229 | { |
14230 | disp = get16 (); | |
14231 | if ((disp & 0x8000) != 0) | |
14232 | disp -= 0x10000; | |
14233 | } | |
14234 | break; | |
14235 | case 1: | |
14236 | FETCH_DATA (the_info, codep + 1); | |
14237 | disp = *codep++; | |
14238 | if ((disp & 0x80) != 0) | |
14239 | disp -= 0x100; | |
65f3ed04 JB |
14240 | if (vex.evex && shift > 0) |
14241 | disp <<= shift; | |
252b5132 RH |
14242 | break; |
14243 | case 2: | |
14244 | disp = get16 (); | |
14245 | if ((disp & 0x8000) != 0) | |
14246 | disp -= 0x10000; | |
14247 | break; | |
14248 | } | |
14249 | ||
14250 | if (!intel_syntax) | |
7967e09e | 14251 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 14252 | { |
5d669648 | 14253 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
14254 | oappend (scratchbuf); |
14255 | } | |
252b5132 | 14256 | |
7967e09e | 14257 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
14258 | { |
14259 | *obufp++ = open_char; | |
db6eb5be | 14260 | *obufp = '\0'; |
7967e09e | 14261 | oappend (index16[modrm.rm]); |
5d669648 L |
14262 | if (intel_syntax |
14263 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 14264 | { |
5d669648 | 14265 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14266 | { |
14267 | *obufp++ = '+'; | |
14268 | *obufp = '\0'; | |
14269 | } | |
7967e09e | 14270 | else if (modrm.mod != 1) |
3d456fa1 JB |
14271 | { |
14272 | *obufp++ = '-'; | |
14273 | *obufp = '\0'; | |
14274 | disp = - (bfd_signed_vma) disp; | |
14275 | } | |
14276 | ||
5d669648 | 14277 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
14278 | oappend (scratchbuf); |
14279 | } | |
14280 | ||
db6eb5be AM |
14281 | *obufp++ = close_char; |
14282 | *obufp = '\0'; | |
252b5132 | 14283 | } |
3d456fa1 JB |
14284 | else if (intel_syntax) |
14285 | { | |
285ca992 | 14286 | if (!active_seg_prefix) |
3d456fa1 JB |
14287 | { |
14288 | oappend (names_seg[ds_reg - es_reg]); | |
14289 | oappend (":"); | |
14290 | } | |
14291 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
14292 | oappend (scratchbuf); | |
14293 | } | |
252b5132 | 14294 | } |
43234a1e L |
14295 | if (vex.evex && vex.b |
14296 | && (bytemode == x_mode | |
90a915bf | 14297 | || bytemode == xmmq_mode |
43234a1e L |
14298 | || bytemode == evex_half_bcst_xmmq_mode)) |
14299 | { | |
90a915bf IT |
14300 | if (vex.w |
14301 | || bytemode == xmmq_mode | |
14302 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
14303 | { |
14304 | switch (vex.length) | |
14305 | { | |
14306 | case 128: | |
14307 | oappend ("{1to2}"); | |
14308 | break; | |
14309 | case 256: | |
14310 | oappend ("{1to4}"); | |
14311 | break; | |
14312 | case 512: | |
14313 | oappend ("{1to8}"); | |
14314 | break; | |
14315 | default: | |
14316 | abort (); | |
14317 | } | |
14318 | } | |
43234a1e | 14319 | else |
b28d1bda IT |
14320 | { |
14321 | switch (vex.length) | |
14322 | { | |
14323 | case 128: | |
14324 | oappend ("{1to4}"); | |
14325 | break; | |
14326 | case 256: | |
14327 | oappend ("{1to8}"); | |
14328 | break; | |
14329 | case 512: | |
14330 | oappend ("{1to16}"); | |
14331 | break; | |
14332 | default: | |
14333 | abort (); | |
14334 | } | |
14335 | } | |
43234a1e | 14336 | } |
252b5132 RH |
14337 | } |
14338 | ||
c0f3af97 | 14339 | static void |
8b3f93e7 | 14340 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
14341 | { |
14342 | /* Skip mod/rm byte. */ | |
14343 | MODRM_CHECK; | |
14344 | codep++; | |
14345 | ||
14346 | if (modrm.mod == 3) | |
14347 | OP_E_register (bytemode, sizeflag); | |
14348 | else | |
c1e679ec | 14349 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
14350 | } |
14351 | ||
252b5132 | 14352 | static void |
26ca5450 | 14353 | OP_G (int bytemode, int sizeflag) |
252b5132 | 14354 | { |
52b15da3 | 14355 | int add = 0; |
c0a30a9f | 14356 | const char **names; |
161a04f6 L |
14357 | USED_REX (REX_R); |
14358 | if (rex & REX_R) | |
52b15da3 | 14359 | add += 8; |
252b5132 RH |
14360 | switch (bytemode) |
14361 | { | |
14362 | case b_mode: | |
52b15da3 JH |
14363 | USED_REX (0); |
14364 | if (rex) | |
7967e09e | 14365 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 14366 | else |
7967e09e | 14367 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
14368 | break; |
14369 | case w_mode: | |
7967e09e | 14370 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
14371 | break; |
14372 | case d_mode: | |
1ba585e8 IT |
14373 | case db_mode: |
14374 | case dw_mode: | |
7967e09e | 14375 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
14376 | break; |
14377 | case q_mode: | |
7967e09e | 14378 | oappend (names64[modrm.reg + add]); |
252b5132 | 14379 | break; |
7e8b059b | 14380 | case bnd_mode: |
0d96e4df L |
14381 | if (modrm.reg > 0x3) |
14382 | { | |
14383 | oappend ("(bad)"); | |
14384 | return; | |
14385 | } | |
7e8b059b L |
14386 | oappend (names_bnd[modrm.reg]); |
14387 | break; | |
252b5132 | 14388 | case v_mode: |
9306ca4a | 14389 | case dq_mode: |
42903f7f L |
14390 | case dqb_mode: |
14391 | case dqd_mode: | |
9306ca4a | 14392 | case dqw_mode: |
bc31405e | 14393 | case movsxd_mode: |
161a04f6 L |
14394 | USED_REX (REX_W); |
14395 | if (rex & REX_W) | |
7967e09e | 14396 | oappend (names64[modrm.reg + add]); |
252b5132 | 14397 | else |
f16cd0d5 | 14398 | { |
bc31405e L |
14399 | if ((sizeflag & DFLAG) |
14400 | || (bytemode != v_mode && bytemode != movsxd_mode)) | |
f16cd0d5 L |
14401 | oappend (names32[modrm.reg + add]); |
14402 | else | |
14403 | oappend (names16[modrm.reg + add]); | |
14404 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14405 | } | |
252b5132 | 14406 | break; |
c0a30a9f L |
14407 | case va_mode: |
14408 | names = (address_mode == mode_64bit | |
14409 | ? names64 : names32); | |
14410 | if (!(prefixes & PREFIX_ADDR)) | |
14411 | { | |
14412 | if (address_mode == mode_16bit) | |
14413 | names = names16; | |
14414 | } | |
14415 | else | |
14416 | { | |
14417 | /* Remove "addr16/addr32". */ | |
14418 | all_prefixes[last_addr_prefix] = 0; | |
14419 | names = (address_mode != mode_32bit | |
14420 | ? names32 : names16); | |
14421 | used_prefixes |= PREFIX_ADDR; | |
14422 | } | |
14423 | oappend (names[modrm.reg + add]); | |
14424 | break; | |
90700ea2 | 14425 | case m_mode: |
cb712a9e | 14426 | if (address_mode == mode_64bit) |
7967e09e | 14427 | oappend (names64[modrm.reg + add]); |
90700ea2 | 14428 | else |
7967e09e | 14429 | oappend (names32[modrm.reg + add]); |
90700ea2 | 14430 | break; |
1ba585e8 | 14431 | case mask_bd_mode: |
43234a1e | 14432 | case mask_mode: |
9889cbb1 L |
14433 | if ((modrm.reg + add) > 0x7) |
14434 | { | |
14435 | oappend ("(bad)"); | |
14436 | return; | |
14437 | } | |
43234a1e L |
14438 | oappend (names_mask[modrm.reg + add]); |
14439 | break; | |
252b5132 RH |
14440 | default: |
14441 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14442 | break; | |
14443 | } | |
14444 | } | |
14445 | ||
52b15da3 | 14446 | static bfd_vma |
26ca5450 | 14447 | get64 (void) |
52b15da3 | 14448 | { |
5dd0794d | 14449 | bfd_vma x; |
52b15da3 | 14450 | #ifdef BFD64 |
5dd0794d AM |
14451 | unsigned int a; |
14452 | unsigned int b; | |
14453 | ||
52b15da3 JH |
14454 | FETCH_DATA (the_info, codep + 8); |
14455 | a = *codep++ & 0xff; | |
14456 | a |= (*codep++ & 0xff) << 8; | |
14457 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 14458 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 14459 | b = *codep++ & 0xff; |
52b15da3 JH |
14460 | b |= (*codep++ & 0xff) << 8; |
14461 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 14462 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
14463 | x = a + ((bfd_vma) b << 32); |
14464 | #else | |
6608db57 | 14465 | abort (); |
5dd0794d | 14466 | x = 0; |
52b15da3 JH |
14467 | #endif |
14468 | return x; | |
14469 | } | |
14470 | ||
14471 | static bfd_signed_vma | |
26ca5450 | 14472 | get32 (void) |
252b5132 | 14473 | { |
52b15da3 | 14474 | bfd_signed_vma x = 0; |
252b5132 RH |
14475 | |
14476 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
14477 | x = *codep++ & (bfd_signed_vma) 0xff; |
14478 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14479 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14480 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14481 | return x; | |
14482 | } | |
14483 | ||
14484 | static bfd_signed_vma | |
26ca5450 | 14485 | get32s (void) |
52b15da3 JH |
14486 | { |
14487 | bfd_signed_vma x = 0; | |
14488 | ||
14489 | FETCH_DATA (the_info, codep + 4); | |
14490 | x = *codep++ & (bfd_signed_vma) 0xff; | |
14491 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14492 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14493 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14494 | ||
14495 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
14496 | ||
252b5132 RH |
14497 | return x; |
14498 | } | |
14499 | ||
14500 | static int | |
26ca5450 | 14501 | get16 (void) |
252b5132 RH |
14502 | { |
14503 | int x = 0; | |
14504 | ||
14505 | FETCH_DATA (the_info, codep + 2); | |
14506 | x = *codep++ & 0xff; | |
14507 | x |= (*codep++ & 0xff) << 8; | |
14508 | return x; | |
14509 | } | |
14510 | ||
14511 | static void | |
26ca5450 | 14512 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
14513 | { |
14514 | op_index[op_ad] = op_ad; | |
cb712a9e | 14515 | if (address_mode == mode_64bit) |
7081ff04 AJ |
14516 | { |
14517 | op_address[op_ad] = op; | |
14518 | op_riprel[op_ad] = riprel; | |
14519 | } | |
14520 | else | |
14521 | { | |
14522 | /* Mask to get a 32-bit address. */ | |
14523 | op_address[op_ad] = op & 0xffffffff; | |
14524 | op_riprel[op_ad] = riprel & 0xffffffff; | |
14525 | } | |
252b5132 RH |
14526 | } |
14527 | ||
14528 | static void | |
26ca5450 | 14529 | OP_REG (int code, int sizeflag) |
252b5132 | 14530 | { |
2da11e11 | 14531 | const char *s; |
9b60702d | 14532 | int add; |
de882298 RM |
14533 | |
14534 | switch (code) | |
14535 | { | |
14536 | case es_reg: case ss_reg: case cs_reg: | |
14537 | case ds_reg: case fs_reg: case gs_reg: | |
14538 | oappend (names_seg[code - es_reg]); | |
14539 | return; | |
14540 | } | |
14541 | ||
161a04f6 L |
14542 | USED_REX (REX_B); |
14543 | if (rex & REX_B) | |
52b15da3 | 14544 | add = 8; |
9b60702d L |
14545 | else |
14546 | add = 0; | |
52b15da3 JH |
14547 | |
14548 | switch (code) | |
14549 | { | |
52b15da3 JH |
14550 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
14551 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14552 | s = names16[code - ax_reg + add]; | |
14553 | break; | |
52b15da3 JH |
14554 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
14555 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
14556 | USED_REX (0); | |
14557 | if (rex) | |
14558 | s = names8rex[code - al_reg + add]; | |
14559 | else | |
14560 | s = names8[code - al_reg]; | |
14561 | break; | |
6439fc28 AM |
14562 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
14563 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 14564 | if (address_mode == mode_64bit |
6c067bbb | 14565 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14566 | { |
14567 | s = names64[code - rAX_reg + add]; | |
14568 | break; | |
14569 | } | |
14570 | code += eAX_reg - rAX_reg; | |
6608db57 | 14571 | /* Fall through. */ |
52b15da3 JH |
14572 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
14573 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14574 | USED_REX (REX_W); |
14575 | if (rex & REX_W) | |
52b15da3 | 14576 | s = names64[code - eAX_reg + add]; |
52b15da3 | 14577 | else |
f16cd0d5 L |
14578 | { |
14579 | if (sizeflag & DFLAG) | |
14580 | s = names32[code - eAX_reg + add]; | |
14581 | else | |
14582 | s = names16[code - eAX_reg + add]; | |
14583 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14584 | } | |
52b15da3 | 14585 | break; |
52b15da3 JH |
14586 | default: |
14587 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14588 | break; | |
14589 | } | |
14590 | oappend (s); | |
14591 | } | |
14592 | ||
14593 | static void | |
26ca5450 | 14594 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
14595 | { |
14596 | const char *s; | |
252b5132 RH |
14597 | |
14598 | switch (code) | |
14599 | { | |
14600 | case indir_dx_reg: | |
d708bcba | 14601 | if (intel_syntax) |
52fd6d94 | 14602 | s = "dx"; |
d708bcba | 14603 | else |
db6eb5be | 14604 | s = "(%dx)"; |
252b5132 RH |
14605 | break; |
14606 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
14607 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14608 | s = names16[code - ax_reg]; | |
14609 | break; | |
14610 | case es_reg: case ss_reg: case cs_reg: | |
14611 | case ds_reg: case fs_reg: case gs_reg: | |
14612 | s = names_seg[code - es_reg]; | |
14613 | break; | |
14614 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
14615 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
14616 | USED_REX (0); |
14617 | if (rex) | |
14618 | s = names8rex[code - al_reg]; | |
14619 | else | |
14620 | s = names8[code - al_reg]; | |
252b5132 RH |
14621 | break; |
14622 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
14623 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14624 | USED_REX (REX_W); |
14625 | if (rex & REX_W) | |
52b15da3 | 14626 | s = names64[code - eAX_reg]; |
252b5132 | 14627 | else |
f16cd0d5 L |
14628 | { |
14629 | if (sizeflag & DFLAG) | |
14630 | s = names32[code - eAX_reg]; | |
14631 | else | |
14632 | s = names16[code - eAX_reg]; | |
14633 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14634 | } | |
252b5132 | 14635 | break; |
52fd6d94 | 14636 | case z_mode_ax_reg: |
161a04f6 | 14637 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14638 | s = *names32; |
14639 | else | |
14640 | s = *names16; | |
161a04f6 | 14641 | if (!(rex & REX_W)) |
52fd6d94 JB |
14642 | used_prefixes |= (prefixes & PREFIX_DATA); |
14643 | break; | |
252b5132 RH |
14644 | default: |
14645 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14646 | break; | |
14647 | } | |
14648 | oappend (s); | |
14649 | } | |
14650 | ||
14651 | static void | |
26ca5450 | 14652 | OP_I (int bytemode, int sizeflag) |
252b5132 | 14653 | { |
52b15da3 JH |
14654 | bfd_signed_vma op; |
14655 | bfd_signed_vma mask = -1; | |
252b5132 RH |
14656 | |
14657 | switch (bytemode) | |
14658 | { | |
14659 | case b_mode: | |
14660 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
14661 | op = *codep++; |
14662 | mask = 0xff; | |
14663 | break; | |
252b5132 | 14664 | case v_mode: |
161a04f6 L |
14665 | USED_REX (REX_W); |
14666 | if (rex & REX_W) | |
52b15da3 | 14667 | op = get32s (); |
252b5132 | 14668 | else |
52b15da3 | 14669 | { |
f16cd0d5 L |
14670 | if (sizeflag & DFLAG) |
14671 | { | |
14672 | op = get32 (); | |
14673 | mask = 0xffffffff; | |
14674 | } | |
14675 | else | |
14676 | { | |
14677 | op = get16 (); | |
14678 | mask = 0xfffff; | |
14679 | } | |
14680 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 14681 | } |
252b5132 | 14682 | break; |
c1dc7af5 JB |
14683 | case d_mode: |
14684 | mask = 0xffffffff; | |
14685 | op = get32 (); | |
14686 | break; | |
252b5132 | 14687 | case w_mode: |
52b15da3 | 14688 | mask = 0xfffff; |
252b5132 RH |
14689 | op = get16 (); |
14690 | break; | |
9306ca4a JB |
14691 | case const_1_mode: |
14692 | if (intel_syntax) | |
6c067bbb | 14693 | oappend ("1"); |
9306ca4a | 14694 | return; |
252b5132 RH |
14695 | default: |
14696 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14697 | return; | |
14698 | } | |
14699 | ||
52b15da3 JH |
14700 | op &= mask; |
14701 | scratchbuf[0] = '$'; | |
d708bcba | 14702 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 14703 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
14704 | scratchbuf[0] = '\0'; |
14705 | } | |
14706 | ||
14707 | static void | |
26ca5450 | 14708 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 | 14709 | { |
a280ab8e | 14710 | if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W)) |
6439fc28 AM |
14711 | { |
14712 | OP_I (bytemode, sizeflag); | |
14713 | return; | |
14714 | } | |
14715 | ||
a280ab8e | 14716 | USED_REX (REX_W); |
52b15da3 | 14717 | |
52b15da3 | 14718 | scratchbuf[0] = '$'; |
a280ab8e | 14719 | print_operand_value (scratchbuf + 1, 1, get64 ()); |
9ce09ba2 | 14720 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14721 | scratchbuf[0] = '\0'; |
14722 | } | |
14723 | ||
14724 | static void | |
26ca5450 | 14725 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 14726 | { |
52b15da3 | 14727 | bfd_signed_vma op; |
252b5132 RH |
14728 | |
14729 | switch (bytemode) | |
14730 | { | |
14731 | case b_mode: | |
e3949f17 | 14732 | case b_T_mode: |
252b5132 RH |
14733 | FETCH_DATA (the_info, codep + 1); |
14734 | op = *codep++; | |
14735 | if ((op & 0x80) != 0) | |
14736 | op -= 0x100; | |
e3949f17 L |
14737 | if (bytemode == b_T_mode) |
14738 | { | |
14739 | if (address_mode != mode_64bit | |
7bb15c6f | 14740 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 14741 | { |
6c067bbb RM |
14742 | /* The operand-size prefix is overridden by a REX prefix. */ |
14743 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
14744 | op &= 0xffffffff; |
14745 | else | |
14746 | op &= 0xffff; | |
14747 | } | |
14748 | } | |
14749 | else | |
14750 | { | |
14751 | if (!(rex & REX_W)) | |
14752 | { | |
14753 | if (sizeflag & DFLAG) | |
14754 | op &= 0xffffffff; | |
14755 | else | |
14756 | op &= 0xffff; | |
14757 | } | |
14758 | } | |
252b5132 RH |
14759 | break; |
14760 | case v_mode: | |
7bb15c6f RM |
14761 | /* The operand-size prefix is overridden by a REX prefix. */ |
14762 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 14763 | op = get32s (); |
252b5132 | 14764 | else |
d9e3625e | 14765 | op = get16 (); |
252b5132 RH |
14766 | break; |
14767 | default: | |
14768 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14769 | return; | |
14770 | } | |
52b15da3 JH |
14771 | |
14772 | scratchbuf[0] = '$'; | |
14773 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 14774 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14775 | } |
14776 | ||
14777 | static void | |
26ca5450 | 14778 | OP_J (int bytemode, int sizeflag) |
252b5132 | 14779 | { |
52b15da3 | 14780 | bfd_vma disp; |
7081ff04 | 14781 | bfd_vma mask = -1; |
65ca155d | 14782 | bfd_vma segment = 0; |
252b5132 RH |
14783 | |
14784 | switch (bytemode) | |
14785 | { | |
14786 | case b_mode: | |
14787 | FETCH_DATA (the_info, codep + 1); | |
14788 | disp = *codep++; | |
14789 | if ((disp & 0x80) != 0) | |
14790 | disp -= 0x100; | |
14791 | break; | |
14792 | case v_mode: | |
d835a58b | 14793 | if (isa64 != intel64) |
376cd056 | 14794 | case dqw_mode: |
5db04b09 L |
14795 | USED_REX (REX_W); |
14796 | if ((sizeflag & DFLAG) | |
14797 | || (address_mode == mode_64bit | |
d835a58b | 14798 | && ((isa64 == intel64 && bytemode != dqw_mode) |
376cd056 | 14799 | || (rex & REX_W)))) |
52b15da3 | 14800 | disp = get32s (); |
252b5132 RH |
14801 | else |
14802 | { | |
14803 | disp = get16 (); | |
206717e8 L |
14804 | if ((disp & 0x8000) != 0) |
14805 | disp -= 0x10000; | |
65ca155d L |
14806 | /* In 16bit mode, address is wrapped around at 64k within |
14807 | the same segment. Otherwise, a data16 prefix on a jump | |
14808 | instruction means that the pc is masked to 16 bits after | |
14809 | the displacement is added! */ | |
14810 | mask = 0xffff; | |
14811 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 14812 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 14813 | & ~((bfd_vma) 0xffff)); |
252b5132 | 14814 | } |
5db04b09 | 14815 | if (address_mode != mode_64bit |
d835a58b | 14816 | || (isa64 != intel64 && !(rex & REX_W))) |
f16cd0d5 | 14817 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
14818 | break; |
14819 | default: | |
14820 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14821 | return; | |
14822 | } | |
42d5f9c6 | 14823 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
14824 | set_op (disp, 0); |
14825 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
14826 | oappend (scratchbuf); |
14827 | } | |
14828 | ||
252b5132 | 14829 | static void |
ed7841b3 | 14830 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 14831 | { |
ed7841b3 | 14832 | if (bytemode == w_mode) |
7967e09e | 14833 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 14834 | else |
7967e09e | 14835 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
14836 | } |
14837 | ||
14838 | static void | |
26ca5450 | 14839 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
14840 | { |
14841 | int seg, offset; | |
14842 | ||
c608c12e | 14843 | if (sizeflag & DFLAG) |
252b5132 | 14844 | { |
c608c12e AM |
14845 | offset = get32 (); |
14846 | seg = get16 (); | |
252b5132 | 14847 | } |
c608c12e AM |
14848 | else |
14849 | { | |
14850 | offset = get16 (); | |
14851 | seg = get16 (); | |
14852 | } | |
7d421014 | 14853 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 14854 | if (intel_syntax) |
3f31e633 | 14855 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
14856 | else |
14857 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 14858 | oappend (scratchbuf); |
252b5132 RH |
14859 | } |
14860 | ||
252b5132 | 14861 | static void |
3f31e633 | 14862 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 14863 | { |
52b15da3 | 14864 | bfd_vma off; |
252b5132 | 14865 | |
3f31e633 JB |
14866 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14867 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14868 | append_seg (); |
14869 | ||
cb712a9e | 14870 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
14871 | off = get32 (); |
14872 | else | |
14873 | off = get16 (); | |
14874 | ||
14875 | if (intel_syntax) | |
14876 | { | |
285ca992 | 14877 | if (!active_seg_prefix) |
252b5132 | 14878 | { |
d708bcba | 14879 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14880 | oappend (":"); |
14881 | } | |
14882 | } | |
52b15da3 JH |
14883 | print_operand_value (scratchbuf, 1, off); |
14884 | oappend (scratchbuf); | |
14885 | } | |
6439fc28 | 14886 | |
52b15da3 | 14887 | static void |
3f31e633 | 14888 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
14889 | { |
14890 | bfd_vma off; | |
14891 | ||
539e75ad L |
14892 | if (address_mode != mode_64bit |
14893 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
14894 | { |
14895 | OP_OFF (bytemode, sizeflag); | |
14896 | return; | |
14897 | } | |
14898 | ||
3f31e633 JB |
14899 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14900 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
14901 | append_seg (); |
14902 | ||
6608db57 | 14903 | off = get64 (); |
52b15da3 JH |
14904 | |
14905 | if (intel_syntax) | |
14906 | { | |
285ca992 | 14907 | if (!active_seg_prefix) |
52b15da3 | 14908 | { |
d708bcba | 14909 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
14910 | oappend (":"); |
14911 | } | |
14912 | } | |
14913 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
14914 | oappend (scratchbuf); |
14915 | } | |
14916 | ||
14917 | static void | |
26ca5450 | 14918 | ptr_reg (int code, int sizeflag) |
252b5132 | 14919 | { |
2da11e11 | 14920 | const char *s; |
d708bcba | 14921 | |
1d9f512f | 14922 | *obufp++ = open_char; |
20f0a1fc | 14923 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 14924 | if (address_mode == mode_64bit) |
c1a64871 JH |
14925 | { |
14926 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 14927 | s = names32[code - eAX_reg]; |
c1a64871 | 14928 | else |
db6eb5be | 14929 | s = names64[code - eAX_reg]; |
c1a64871 | 14930 | } |
52b15da3 | 14931 | else if (sizeflag & AFLAG) |
252b5132 RH |
14932 | s = names32[code - eAX_reg]; |
14933 | else | |
14934 | s = names16[code - eAX_reg]; | |
14935 | oappend (s); | |
1d9f512f AM |
14936 | *obufp++ = close_char; |
14937 | *obufp = 0; | |
252b5132 RH |
14938 | } |
14939 | ||
14940 | static void | |
26ca5450 | 14941 | OP_ESreg (int code, int sizeflag) |
252b5132 | 14942 | { |
9306ca4a | 14943 | if (intel_syntax) |
52fd6d94 JB |
14944 | { |
14945 | switch (codep[-1]) | |
14946 | { | |
14947 | case 0x6d: /* insw/insl */ | |
14948 | intel_operand_size (z_mode, sizeflag); | |
14949 | break; | |
14950 | case 0xa5: /* movsw/movsl/movsq */ | |
14951 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
14952 | case 0xab: /* stosw/stosl */ | |
14953 | case 0xaf: /* scasw/scasl */ | |
14954 | intel_operand_size (v_mode, sizeflag); | |
14955 | break; | |
14956 | default: | |
14957 | intel_operand_size (b_mode, sizeflag); | |
14958 | } | |
14959 | } | |
9ce09ba2 | 14960 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
14961 | ptr_reg (code, sizeflag); |
14962 | } | |
14963 | ||
14964 | static void | |
26ca5450 | 14965 | OP_DSreg (int code, int sizeflag) |
252b5132 | 14966 | { |
9306ca4a | 14967 | if (intel_syntax) |
52fd6d94 JB |
14968 | { |
14969 | switch (codep[-1]) | |
14970 | { | |
14971 | case 0x6f: /* outsw/outsl */ | |
14972 | intel_operand_size (z_mode, sizeflag); | |
14973 | break; | |
14974 | case 0xa5: /* movsw/movsl/movsq */ | |
14975 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
14976 | case 0xad: /* lodsw/lodsl/lodsq */ | |
14977 | intel_operand_size (v_mode, sizeflag); | |
14978 | break; | |
14979 | default: | |
14980 | intel_operand_size (b_mode, sizeflag); | |
14981 | } | |
14982 | } | |
285ca992 L |
14983 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
14984 | default segment register DS is printed. */ | |
14985 | if (!active_seg_prefix) | |
14986 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 14987 | append_seg (); |
252b5132 RH |
14988 | ptr_reg (code, sizeflag); |
14989 | } | |
14990 | ||
252b5132 | 14991 | static void |
26ca5450 | 14992 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 14993 | { |
9b60702d | 14994 | int add; |
161a04f6 | 14995 | if (rex & REX_R) |
c4a530c5 | 14996 | { |
161a04f6 | 14997 | USED_REX (REX_R); |
c4a530c5 JB |
14998 | add = 8; |
14999 | } | |
cb712a9e | 15000 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 15001 | { |
f16cd0d5 | 15002 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
15003 | used_prefixes |= PREFIX_LOCK; |
15004 | add = 8; | |
15005 | } | |
9b60702d L |
15006 | else |
15007 | add = 0; | |
7967e09e | 15008 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 15009 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15010 | } |
15011 | ||
252b5132 | 15012 | static void |
26ca5450 | 15013 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15014 | { |
9b60702d | 15015 | int add; |
161a04f6 L |
15016 | USED_REX (REX_R); |
15017 | if (rex & REX_R) | |
52b15da3 | 15018 | add = 8; |
9b60702d L |
15019 | else |
15020 | add = 0; | |
d708bcba | 15021 | if (intel_syntax) |
7967e09e | 15022 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 15023 | else |
7967e09e | 15024 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
15025 | oappend (scratchbuf); |
15026 | } | |
15027 | ||
252b5132 | 15028 | static void |
26ca5450 | 15029 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15030 | { |
7967e09e | 15031 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 15032 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15033 | } |
15034 | ||
15035 | static void | |
6f74c397 | 15036 | OP_R (int bytemode, int sizeflag) |
252b5132 | 15037 | { |
68f34464 L |
15038 | /* Skip mod/rm byte. */ |
15039 | MODRM_CHECK; | |
15040 | codep++; | |
15041 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
15042 | } |
15043 | ||
15044 | static void | |
26ca5450 | 15045 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15046 | { |
b9733481 L |
15047 | int reg = modrm.reg; |
15048 | const char **names; | |
15049 | ||
041bd2e0 JH |
15050 | used_prefixes |= (prefixes & PREFIX_DATA); |
15051 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 15052 | { |
b9733481 | 15053 | names = names_xmm; |
161a04f6 L |
15054 | USED_REX (REX_R); |
15055 | if (rex & REX_R) | |
b9733481 | 15056 | reg += 8; |
20f0a1fc | 15057 | } |
041bd2e0 | 15058 | else |
b9733481 L |
15059 | names = names_mm; |
15060 | oappend (names[reg]); | |
252b5132 RH |
15061 | } |
15062 | ||
c608c12e | 15063 | static void |
c0f3af97 | 15064 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 15065 | { |
b9733481 L |
15066 | int reg = modrm.reg; |
15067 | const char **names; | |
15068 | ||
161a04f6 L |
15069 | USED_REX (REX_R); |
15070 | if (rex & REX_R) | |
b9733481 | 15071 | reg += 8; |
43234a1e L |
15072 | if (vex.evex) |
15073 | { | |
15074 | if (!vex.r) | |
15075 | reg += 16; | |
15076 | } | |
15077 | ||
539f890d L |
15078 | if (need_vex |
15079 | && bytemode != xmm_mode | |
43234a1e L |
15080 | && bytemode != xmmq_mode |
15081 | && bytemode != evex_half_bcst_xmmq_mode | |
15082 | && bytemode != ymm_mode | |
539f890d | 15083 | && bytemode != scalar_mode) |
c0f3af97 L |
15084 | { |
15085 | switch (vex.length) | |
15086 | { | |
15087 | case 128: | |
b9733481 | 15088 | names = names_xmm; |
c0f3af97 L |
15089 | break; |
15090 | case 256: | |
5fc35d96 IT |
15091 | if (vex.w |
15092 | || (bytemode != vex_vsib_q_w_dq_mode | |
15093 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
15094 | names = names_ymm; |
15095 | else | |
15096 | names = names_xmm; | |
c0f3af97 | 15097 | break; |
43234a1e L |
15098 | case 512: |
15099 | names = names_zmm; | |
15100 | break; | |
c0f3af97 L |
15101 | default: |
15102 | abort (); | |
15103 | } | |
15104 | } | |
43234a1e L |
15105 | else if (bytemode == xmmq_mode |
15106 | || bytemode == evex_half_bcst_xmmq_mode) | |
15107 | { | |
15108 | switch (vex.length) | |
15109 | { | |
15110 | case 128: | |
15111 | case 256: | |
15112 | names = names_xmm; | |
15113 | break; | |
15114 | case 512: | |
15115 | names = names_ymm; | |
15116 | break; | |
15117 | default: | |
15118 | abort (); | |
15119 | } | |
15120 | } | |
15121 | else if (bytemode == ymm_mode) | |
15122 | names = names_ymm; | |
c0f3af97 | 15123 | else |
b9733481 L |
15124 | names = names_xmm; |
15125 | oappend (names[reg]); | |
c608c12e AM |
15126 | } |
15127 | ||
252b5132 | 15128 | static void |
26ca5450 | 15129 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 15130 | { |
b9733481 L |
15131 | int reg; |
15132 | const char **names; | |
15133 | ||
7967e09e | 15134 | if (modrm.mod != 3) |
252b5132 | 15135 | { |
b6169b20 L |
15136 | if (intel_syntax |
15137 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
15138 | { |
15139 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15140 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15141 | } |
252b5132 RH |
15142 | OP_E (bytemode, sizeflag); |
15143 | return; | |
15144 | } | |
15145 | ||
b6169b20 L |
15146 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
15147 | swap_operand (); | |
15148 | ||
6608db57 | 15149 | /* Skip mod/rm byte. */ |
4bba6815 | 15150 | MODRM_CHECK; |
252b5132 | 15151 | codep++; |
041bd2e0 | 15152 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 15153 | reg = modrm.rm; |
041bd2e0 | 15154 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 15155 | { |
b9733481 | 15156 | names = names_xmm; |
161a04f6 L |
15157 | USED_REX (REX_B); |
15158 | if (rex & REX_B) | |
b9733481 | 15159 | reg += 8; |
20f0a1fc | 15160 | } |
041bd2e0 | 15161 | else |
b9733481 L |
15162 | names = names_mm; |
15163 | oappend (names[reg]); | |
252b5132 RH |
15164 | } |
15165 | ||
246c51aa L |
15166 | /* cvt* are the only instructions in sse2 which have |
15167 | both SSE and MMX operands and also have 0x66 prefix | |
15168 | in their opcode. 0x66 was originally used to differentiate | |
15169 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
15170 | cvt* separately using OP_EMC and OP_MXC */ |
15171 | static void | |
15172 | OP_EMC (int bytemode, int sizeflag) | |
15173 | { | |
7967e09e | 15174 | if (modrm.mod != 3) |
4d9567e0 MM |
15175 | { |
15176 | if (intel_syntax && bytemode == v_mode) | |
15177 | { | |
15178 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15179 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15180 | } |
4d9567e0 MM |
15181 | OP_E (bytemode, sizeflag); |
15182 | return; | |
15183 | } | |
246c51aa | 15184 | |
4d9567e0 MM |
15185 | /* Skip mod/rm byte. */ |
15186 | MODRM_CHECK; | |
15187 | codep++; | |
15188 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15189 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
15190 | } |
15191 | ||
15192 | static void | |
15193 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15194 | { | |
15195 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15196 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
15197 | } |
15198 | ||
c608c12e | 15199 | static void |
26ca5450 | 15200 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 15201 | { |
b9733481 L |
15202 | int reg; |
15203 | const char **names; | |
d6f574e0 L |
15204 | |
15205 | /* Skip mod/rm byte. */ | |
15206 | MODRM_CHECK; | |
15207 | codep++; | |
15208 | ||
7967e09e | 15209 | if (modrm.mod != 3) |
c608c12e | 15210 | { |
c1e679ec | 15211 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
15212 | return; |
15213 | } | |
d6f574e0 | 15214 | |
b9733481 | 15215 | reg = modrm.rm; |
161a04f6 L |
15216 | USED_REX (REX_B); |
15217 | if (rex & REX_B) | |
b9733481 | 15218 | reg += 8; |
43234a1e L |
15219 | if (vex.evex) |
15220 | { | |
15221 | USED_REX (REX_X); | |
15222 | if ((rex & REX_X)) | |
15223 | reg += 16; | |
15224 | } | |
c608c12e | 15225 | |
b6169b20 | 15226 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
15227 | && (bytemode == x_swap_mode |
15228 | || bytemode == d_swap_mode | |
7bb15c6f | 15229 | || bytemode == d_scalar_swap_mode |
539f890d L |
15230 | || bytemode == q_swap_mode |
15231 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
15232 | swap_operand (); |
15233 | ||
c0f3af97 L |
15234 | if (need_vex |
15235 | && bytemode != xmm_mode | |
6c30d220 L |
15236 | && bytemode != xmmdw_mode |
15237 | && bytemode != xmmqd_mode | |
15238 | && bytemode != xmm_mb_mode | |
15239 | && bytemode != xmm_mw_mode | |
15240 | && bytemode != xmm_md_mode | |
15241 | && bytemode != xmm_mq_mode | |
539f890d | 15242 | && bytemode != xmmq_mode |
43234a1e L |
15243 | && bytemode != evex_half_bcst_xmmq_mode |
15244 | && bytemode != ymm_mode | |
7bb15c6f | 15245 | && bytemode != d_scalar_swap_mode |
1c480963 L |
15246 | && bytemode != q_scalar_swap_mode |
15247 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
15248 | { |
15249 | switch (vex.length) | |
15250 | { | |
15251 | case 128: | |
b9733481 | 15252 | names = names_xmm; |
c0f3af97 L |
15253 | break; |
15254 | case 256: | |
b9733481 | 15255 | names = names_ymm; |
c0f3af97 | 15256 | break; |
43234a1e L |
15257 | case 512: |
15258 | names = names_zmm; | |
15259 | break; | |
c0f3af97 L |
15260 | default: |
15261 | abort (); | |
15262 | } | |
15263 | } | |
43234a1e L |
15264 | else if (bytemode == xmmq_mode |
15265 | || bytemode == evex_half_bcst_xmmq_mode) | |
15266 | { | |
15267 | switch (vex.length) | |
15268 | { | |
15269 | case 128: | |
15270 | case 256: | |
15271 | names = names_xmm; | |
15272 | break; | |
15273 | case 512: | |
15274 | names = names_ymm; | |
15275 | break; | |
15276 | default: | |
15277 | abort (); | |
15278 | } | |
15279 | } | |
15280 | else if (bytemode == ymm_mode) | |
15281 | names = names_ymm; | |
c0f3af97 | 15282 | else |
b9733481 L |
15283 | names = names_xmm; |
15284 | oappend (names[reg]); | |
c608c12e AM |
15285 | } |
15286 | ||
252b5132 | 15287 | static void |
26ca5450 | 15288 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 15289 | { |
7967e09e | 15290 | if (modrm.mod == 3) |
2da11e11 AM |
15291 | OP_EM (bytemode, sizeflag); |
15292 | else | |
6608db57 | 15293 | BadOp (); |
252b5132 RH |
15294 | } |
15295 | ||
992aaec9 | 15296 | static void |
26ca5450 | 15297 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 15298 | { |
7967e09e | 15299 | if (modrm.mod == 3) |
992aaec9 AM |
15300 | OP_EX (bytemode, sizeflag); |
15301 | else | |
6608db57 | 15302 | BadOp (); |
992aaec9 AM |
15303 | } |
15304 | ||
cc0ec051 AM |
15305 | static void |
15306 | OP_M (int bytemode, int sizeflag) | |
15307 | { | |
7967e09e | 15308 | if (modrm.mod == 3) |
75413a22 L |
15309 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
15310 | BadOp (); | |
cc0ec051 AM |
15311 | else |
15312 | OP_E (bytemode, sizeflag); | |
15313 | } | |
15314 | ||
15315 | static void | |
15316 | OP_0f07 (int bytemode, int sizeflag) | |
15317 | { | |
7967e09e | 15318 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
15319 | BadOp (); |
15320 | else | |
15321 | OP_E (bytemode, sizeflag); | |
15322 | } | |
15323 | ||
46e883c5 | 15324 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 15325 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 15326 | |
cc0ec051 | 15327 | static void |
46e883c5 | 15328 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 15329 | { |
8b38ad71 L |
15330 | if ((prefixes & PREFIX_DATA) != 0 |
15331 | || (rex != 0 | |
15332 | && rex != 0x48 | |
15333 | && address_mode == mode_64bit)) | |
46e883c5 L |
15334 | OP_REG (bytemode, sizeflag); |
15335 | else | |
15336 | strcpy (obuf, "nop"); | |
15337 | } | |
15338 | ||
15339 | static void | |
15340 | NOP_Fixup2 (int bytemode, int sizeflag) | |
15341 | { | |
8b38ad71 L |
15342 | if ((prefixes & PREFIX_DATA) != 0 |
15343 | || (rex != 0 | |
15344 | && rex != 0x48 | |
15345 | && address_mode == mode_64bit)) | |
46e883c5 | 15346 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
15347 | } |
15348 | ||
84037f8c | 15349 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
15350 | /* 00 */ NULL, NULL, NULL, NULL, |
15351 | /* 04 */ NULL, NULL, NULL, NULL, | |
15352 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15353 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
15354 | /* 10 */ NULL, NULL, NULL, NULL, |
15355 | /* 14 */ NULL, NULL, NULL, NULL, | |
15356 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15357 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
15358 | /* 20 */ NULL, NULL, NULL, NULL, |
15359 | /* 24 */ NULL, NULL, NULL, NULL, | |
15360 | /* 28 */ NULL, NULL, NULL, NULL, | |
15361 | /* 2C */ NULL, NULL, NULL, NULL, | |
15362 | /* 30 */ NULL, NULL, NULL, NULL, | |
15363 | /* 34 */ NULL, NULL, NULL, NULL, | |
15364 | /* 38 */ NULL, NULL, NULL, NULL, | |
15365 | /* 3C */ NULL, NULL, NULL, NULL, | |
15366 | /* 40 */ NULL, NULL, NULL, NULL, | |
15367 | /* 44 */ NULL, NULL, NULL, NULL, | |
15368 | /* 48 */ NULL, NULL, NULL, NULL, | |
15369 | /* 4C */ NULL, NULL, NULL, NULL, | |
15370 | /* 50 */ NULL, NULL, NULL, NULL, | |
15371 | /* 54 */ NULL, NULL, NULL, NULL, | |
15372 | /* 58 */ NULL, NULL, NULL, NULL, | |
15373 | /* 5C */ NULL, NULL, NULL, NULL, | |
15374 | /* 60 */ NULL, NULL, NULL, NULL, | |
15375 | /* 64 */ NULL, NULL, NULL, NULL, | |
15376 | /* 68 */ NULL, NULL, NULL, NULL, | |
15377 | /* 6C */ NULL, NULL, NULL, NULL, | |
15378 | /* 70 */ NULL, NULL, NULL, NULL, | |
15379 | /* 74 */ NULL, NULL, NULL, NULL, | |
15380 | /* 78 */ NULL, NULL, NULL, NULL, | |
15381 | /* 7C */ NULL, NULL, NULL, NULL, | |
15382 | /* 80 */ NULL, NULL, NULL, NULL, | |
15383 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
15384 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
15385 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
15386 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
15387 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
15388 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
15389 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
15390 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
15391 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
15392 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
15393 | /* AC */ NULL, NULL, "pfacc", NULL, | |
15394 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 15395 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 15396 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
15397 | /* BC */ NULL, NULL, NULL, "pavgusb", |
15398 | /* C0 */ NULL, NULL, NULL, NULL, | |
15399 | /* C4 */ NULL, NULL, NULL, NULL, | |
15400 | /* C8 */ NULL, NULL, NULL, NULL, | |
15401 | /* CC */ NULL, NULL, NULL, NULL, | |
15402 | /* D0 */ NULL, NULL, NULL, NULL, | |
15403 | /* D4 */ NULL, NULL, NULL, NULL, | |
15404 | /* D8 */ NULL, NULL, NULL, NULL, | |
15405 | /* DC */ NULL, NULL, NULL, NULL, | |
15406 | /* E0 */ NULL, NULL, NULL, NULL, | |
15407 | /* E4 */ NULL, NULL, NULL, NULL, | |
15408 | /* E8 */ NULL, NULL, NULL, NULL, | |
15409 | /* EC */ NULL, NULL, NULL, NULL, | |
15410 | /* F0 */ NULL, NULL, NULL, NULL, | |
15411 | /* F4 */ NULL, NULL, NULL, NULL, | |
15412 | /* F8 */ NULL, NULL, NULL, NULL, | |
15413 | /* FC */ NULL, NULL, NULL, NULL, | |
15414 | }; | |
15415 | ||
15416 | static void | |
26ca5450 | 15417 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
15418 | { |
15419 | const char *mnemonic; | |
15420 | ||
15421 | FETCH_DATA (the_info, codep + 1); | |
15422 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
15423 | place where an 8-bit immediate would normally go. ie. the last | |
15424 | byte of the instruction. */ | |
ea397f5b | 15425 | obufp = mnemonicendp; |
c608c12e | 15426 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 15427 | if (mnemonic) |
2da11e11 | 15428 | oappend (mnemonic); |
252b5132 RH |
15429 | else |
15430 | { | |
15431 | /* Since a variable sized modrm/sib chunk is between the start | |
15432 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
15433 | all the modrm processing first, and don't know until now that | |
15434 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
15435 | op_out[0][0] = '\0'; |
15436 | op_out[1][0] = '\0'; | |
6608db57 | 15437 | BadOp (); |
252b5132 | 15438 | } |
ea397f5b | 15439 | mnemonicendp = obufp; |
252b5132 | 15440 | } |
c608c12e | 15441 | |
ea397f5b L |
15442 | static struct op simd_cmp_op[] = |
15443 | { | |
15444 | { STRING_COMMA_LEN ("eq") }, | |
15445 | { STRING_COMMA_LEN ("lt") }, | |
15446 | { STRING_COMMA_LEN ("le") }, | |
15447 | { STRING_COMMA_LEN ("unord") }, | |
15448 | { STRING_COMMA_LEN ("neq") }, | |
15449 | { STRING_COMMA_LEN ("nlt") }, | |
15450 | { STRING_COMMA_LEN ("nle") }, | |
15451 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
15452 | }; |
15453 | ||
15454 | static void | |
ad19981d | 15455 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
15456 | { |
15457 | unsigned int cmp_type; | |
15458 | ||
15459 | FETCH_DATA (the_info, codep + 1); | |
15460 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 15461 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 15462 | { |
ad19981d | 15463 | char suffix [3]; |
ea397f5b | 15464 | char *p = mnemonicendp - 2; |
ad19981d L |
15465 | suffix[0] = p[0]; |
15466 | suffix[1] = p[1]; | |
15467 | suffix[2] = '\0'; | |
ea397f5b L |
15468 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
15469 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
15470 | } |
15471 | else | |
15472 | { | |
ad19981d L |
15473 | /* We have a reserved extension byte. Output it directly. */ |
15474 | scratchbuf[0] = '$'; | |
15475 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 15476 | oappend_maybe_intel (scratchbuf); |
ad19981d | 15477 | scratchbuf[0] = '\0'; |
c608c12e AM |
15478 | } |
15479 | } | |
15480 | ||
9916071f | 15481 | static void |
7abb8d81 | 15482 | OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
9916071f | 15483 | { |
7abb8d81 | 15484 | /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ |
b844680a L |
15485 | if (!intel_syntax) |
15486 | { | |
081e283f JB |
15487 | strcpy (op_out[0], names32[0]); |
15488 | strcpy (op_out[1], names32[1]); | |
7abb8d81 | 15489 | if (bytemode == eBX_reg) |
081e283f | 15490 | strcpy (op_out[2], names32[3]); |
b844680a L |
15491 | two_source_ops = 1; |
15492 | } | |
15493 | /* Skip mod/rm byte. */ | |
15494 | MODRM_CHECK; | |
15495 | codep++; | |
15496 | } | |
15497 | ||
15498 | static void | |
15499 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
15500 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 15501 | { |
081e283f | 15502 | /* monitor %{e,r,}ax,%ecx,%edx" */ |
b844680a | 15503 | if (!intel_syntax) |
ca164297 | 15504 | { |
cb712a9e L |
15505 | const char **names = (address_mode == mode_64bit |
15506 | ? names64 : names32); | |
1d9f512f | 15507 | |
081e283f | 15508 | if (prefixes & PREFIX_ADDR) |
ca164297 | 15509 | { |
b844680a | 15510 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 15511 | all_prefixes[last_addr_prefix] = 0; |
081e283f JB |
15512 | names = (address_mode != mode_32bit |
15513 | ? names32 : names16); | |
b844680a | 15514 | used_prefixes |= PREFIX_ADDR; |
ca164297 | 15515 | } |
081e283f JB |
15516 | else if (address_mode == mode_16bit) |
15517 | names = names16; | |
15518 | strcpy (op_out[0], names[0]); | |
15519 | strcpy (op_out[1], names32[1]); | |
15520 | strcpy (op_out[2], names32[2]); | |
b844680a | 15521 | two_source_ops = 1; |
ca164297 | 15522 | } |
b844680a L |
15523 | /* Skip mod/rm byte. */ |
15524 | MODRM_CHECK; | |
15525 | codep++; | |
30123838 JB |
15526 | } |
15527 | ||
6608db57 KH |
15528 | static void |
15529 | BadOp (void) | |
2da11e11 | 15530 | { |
6608db57 KH |
15531 | /* Throw away prefixes and 1st. opcode byte. */ |
15532 | codep = insn_codep + 1; | |
2da11e11 AM |
15533 | oappend ("(bad)"); |
15534 | } | |
4cc91dba | 15535 | |
35c52694 L |
15536 | static void |
15537 | REP_Fixup (int bytemode, int sizeflag) | |
15538 | { | |
15539 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
15540 | lods and stos. */ | |
35c52694 | 15541 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 15542 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
15543 | |
15544 | switch (bytemode) | |
15545 | { | |
15546 | case al_reg: | |
15547 | case eAX_reg: | |
15548 | case indir_dx_reg: | |
15549 | OP_IMREG (bytemode, sizeflag); | |
15550 | break; | |
15551 | case eDI_reg: | |
15552 | OP_ESreg (bytemode, sizeflag); | |
15553 | break; | |
15554 | case eSI_reg: | |
15555 | OP_DSreg (bytemode, sizeflag); | |
15556 | break; | |
15557 | default: | |
15558 | abort (); | |
15559 | break; | |
15560 | } | |
15561 | } | |
f5804c90 | 15562 | |
d835a58b JB |
15563 | static void |
15564 | SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15565 | { | |
15566 | if ( isa64 != amd64 ) | |
15567 | return; | |
15568 | ||
15569 | obufp = obuf; | |
15570 | BadOp (); | |
15571 | mnemonicendp = obufp; | |
15572 | ++codep; | |
15573 | } | |
15574 | ||
7e8b059b L |
15575 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
15576 | "bnd". */ | |
15577 | ||
15578 | static void | |
15579 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15580 | { | |
15581 | if (prefixes & PREFIX_REPNZ) | |
15582 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
15583 | } | |
15584 | ||
04ef582a L |
15585 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
15586 | "notrack". */ | |
15587 | ||
15588 | static void | |
15589 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
15590 | int sizeflag ATTRIBUTE_UNUSED) | |
15591 | { | |
9fef80d6 | 15592 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
15593 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
15594 | { | |
4e9ac44a | 15595 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 15596 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
15597 | active_seg_prefix = 0; |
15598 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
15599 | } | |
15600 | } | |
15601 | ||
42164a71 L |
15602 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
15603 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
15604 | */ | |
15605 | ||
15606 | static void | |
15607 | HLE_Fixup1 (int bytemode, int sizeflag) | |
15608 | { | |
15609 | if (modrm.mod != 3 | |
15610 | && (prefixes & PREFIX_LOCK) != 0) | |
15611 | { | |
15612 | if (prefixes & PREFIX_REPZ) | |
15613 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15614 | if (prefixes & PREFIX_REPNZ) | |
15615 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15616 | } | |
15617 | ||
15618 | OP_E (bytemode, sizeflag); | |
15619 | } | |
15620 | ||
15621 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
15622 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
15623 | */ | |
15624 | ||
15625 | static void | |
15626 | HLE_Fixup2 (int bytemode, int sizeflag) | |
15627 | { | |
15628 | if (modrm.mod != 3) | |
15629 | { | |
15630 | if (prefixes & PREFIX_REPZ) | |
15631 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15632 | if (prefixes & PREFIX_REPNZ) | |
15633 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15634 | } | |
15635 | ||
15636 | OP_E (bytemode, sizeflag); | |
15637 | } | |
15638 | ||
15639 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
15640 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
15641 | ||
15642 | static void | |
15643 | HLE_Fixup3 (int bytemode, int sizeflag) | |
15644 | { | |
15645 | if (modrm.mod != 3 | |
15646 | && last_repz_prefix > last_repnz_prefix | |
15647 | && (prefixes & PREFIX_REPZ) != 0) | |
15648 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15649 | ||
15650 | OP_E (bytemode, sizeflag); | |
15651 | } | |
15652 | ||
f5804c90 L |
15653 | static void |
15654 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
15655 | { | |
161a04f6 L |
15656 | USED_REX (REX_W); |
15657 | if (rex & REX_W) | |
f5804c90 L |
15658 | { |
15659 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
15660 | char *p = mnemonicendp - 2; |
15661 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 15662 | bytemode = o_mode; |
f5804c90 | 15663 | } |
42164a71 L |
15664 | else if ((prefixes & PREFIX_LOCK) != 0) |
15665 | { | |
15666 | if (prefixes & PREFIX_REPZ) | |
15667 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15668 | if (prefixes & PREFIX_REPNZ) | |
15669 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15670 | } | |
15671 | ||
f5804c90 L |
15672 | OP_M (bytemode, sizeflag); |
15673 | } | |
42903f7f L |
15674 | |
15675 | static void | |
15676 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
15677 | { | |
b9733481 L |
15678 | const char **names; |
15679 | ||
c0f3af97 L |
15680 | if (need_vex) |
15681 | { | |
15682 | switch (vex.length) | |
15683 | { | |
15684 | case 128: | |
b9733481 | 15685 | names = names_xmm; |
c0f3af97 L |
15686 | break; |
15687 | case 256: | |
b9733481 | 15688 | names = names_ymm; |
c0f3af97 L |
15689 | break; |
15690 | default: | |
15691 | abort (); | |
15692 | } | |
15693 | } | |
15694 | else | |
b9733481 L |
15695 | names = names_xmm; |
15696 | oappend (names[reg]); | |
42903f7f | 15697 | } |
381d071f L |
15698 | |
15699 | static void | |
15700 | CRC32_Fixup (int bytemode, int sizeflag) | |
15701 | { | |
15702 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 15703 | char *p = mnemonicendp; |
381d071f L |
15704 | |
15705 | switch (bytemode) | |
15706 | { | |
15707 | case b_mode: | |
20592a94 | 15708 | if (intel_syntax) |
ea397f5b | 15709 | goto skip; |
20592a94 | 15710 | |
381d071f L |
15711 | *p++ = 'b'; |
15712 | break; | |
15713 | case v_mode: | |
20592a94 | 15714 | if (intel_syntax) |
ea397f5b | 15715 | goto skip; |
20592a94 | 15716 | |
381d071f L |
15717 | USED_REX (REX_W); |
15718 | if (rex & REX_W) | |
15719 | *p++ = 'q'; | |
7bb15c6f | 15720 | else |
f16cd0d5 L |
15721 | { |
15722 | if (sizeflag & DFLAG) | |
15723 | *p++ = 'l'; | |
15724 | else | |
15725 | *p++ = 'w'; | |
15726 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15727 | } | |
381d071f L |
15728 | break; |
15729 | default: | |
15730 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15731 | break; | |
15732 | } | |
ea397f5b | 15733 | mnemonicendp = p; |
381d071f L |
15734 | *p = '\0'; |
15735 | ||
dc1e8a47 | 15736 | skip: |
381d071f L |
15737 | if (modrm.mod == 3) |
15738 | { | |
15739 | int add; | |
15740 | ||
15741 | /* Skip mod/rm byte. */ | |
15742 | MODRM_CHECK; | |
15743 | codep++; | |
15744 | ||
15745 | USED_REX (REX_B); | |
15746 | add = (rex & REX_B) ? 8 : 0; | |
15747 | if (bytemode == b_mode) | |
15748 | { | |
15749 | USED_REX (0); | |
15750 | if (rex) | |
15751 | oappend (names8rex[modrm.rm + add]); | |
15752 | else | |
15753 | oappend (names8[modrm.rm + add]); | |
15754 | } | |
15755 | else | |
15756 | { | |
15757 | USED_REX (REX_W); | |
15758 | if (rex & REX_W) | |
15759 | oappend (names64[modrm.rm + add]); | |
15760 | else if ((prefixes & PREFIX_DATA)) | |
15761 | oappend (names16[modrm.rm + add]); | |
15762 | else | |
15763 | oappend (names32[modrm.rm + add]); | |
15764 | } | |
15765 | } | |
15766 | else | |
9344ff29 | 15767 | OP_E (bytemode, sizeflag); |
381d071f | 15768 | } |
85f10a01 | 15769 | |
eacc9c89 L |
15770 | static void |
15771 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
15772 | { | |
15773 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
15774 | USED_REX (REX_W); | |
15775 | if (rex & REX_W) | |
15776 | { | |
15777 | char *p = mnemonicendp; | |
15778 | *p++ = '6'; | |
15779 | *p++ = '4'; | |
15780 | *p = '\0'; | |
15781 | mnemonicendp = p; | |
15782 | } | |
15783 | OP_M (bytemode, sizeflag); | |
15784 | } | |
15785 | ||
15c7c1d8 JB |
15786 | static void |
15787 | PCMPESTR_Fixup (int bytemode, int sizeflag) | |
15788 | { | |
15789 | /* Add proper suffix to "{,v}pcmpestr{i,m}". */ | |
15790 | if (!intel_syntax) | |
15791 | { | |
15792 | char *p = mnemonicendp; | |
15793 | ||
15794 | USED_REX (REX_W); | |
15795 | if (rex & REX_W) | |
15796 | *p++ = 'q'; | |
15797 | else if (sizeflag & SUFFIX_ALWAYS) | |
15798 | *p++ = 'l'; | |
15799 | ||
15800 | *p = '\0'; | |
15801 | mnemonicendp = p; | |
15802 | } | |
15803 | ||
15804 | OP_EX (bytemode, sizeflag); | |
15805 | } | |
15806 | ||
c0f3af97 L |
15807 | /* Display the destination register operand for instructions with |
15808 | VEX. */ | |
15809 | ||
15810 | static void | |
15811 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
15812 | { | |
539f890d | 15813 | int reg; |
b9733481 L |
15814 | const char **names; |
15815 | ||
c0f3af97 L |
15816 | if (!need_vex) |
15817 | abort (); | |
15818 | ||
15819 | if (!need_vex_reg) | |
15820 | return; | |
15821 | ||
539f890d | 15822 | reg = vex.register_specifier; |
63c6fc6c | 15823 | vex.register_specifier = 0; |
5f847646 JB |
15824 | if (address_mode != mode_64bit) |
15825 | reg &= 7; | |
15826 | else if (vex.evex && !vex.v) | |
15827 | reg += 16; | |
43234a1e | 15828 | |
539f890d L |
15829 | if (bytemode == vex_scalar_mode) |
15830 | { | |
15831 | oappend (names_xmm[reg]); | |
15832 | return; | |
15833 | } | |
15834 | ||
c0f3af97 L |
15835 | switch (vex.length) |
15836 | { | |
15837 | case 128: | |
15838 | switch (bytemode) | |
15839 | { | |
15840 | case vex_mode: | |
15841 | case vex128_mode: | |
6c30d220 | 15842 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15843 | case vex_vsib_q_w_d_mode: |
cb21baef L |
15844 | names = names_xmm; |
15845 | break; | |
15846 | case dq_mode: | |
390a6789 | 15847 | if (rex & REX_W) |
cb21baef L |
15848 | names = names64; |
15849 | else | |
15850 | names = names32; | |
c0f3af97 | 15851 | break; |
1ba585e8 | 15852 | case mask_bd_mode: |
43234a1e | 15853 | case mask_mode: |
9889cbb1 L |
15854 | if (reg > 0x7) |
15855 | { | |
15856 | oappend ("(bad)"); | |
15857 | return; | |
15858 | } | |
43234a1e L |
15859 | names = names_mask; |
15860 | break; | |
c0f3af97 L |
15861 | default: |
15862 | abort (); | |
15863 | return; | |
15864 | } | |
c0f3af97 L |
15865 | break; |
15866 | case 256: | |
15867 | switch (bytemode) | |
15868 | { | |
15869 | case vex_mode: | |
15870 | case vex256_mode: | |
6c30d220 L |
15871 | names = names_ymm; |
15872 | break; | |
15873 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 15874 | case vex_vsib_q_w_d_mode: |
6c30d220 | 15875 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 15876 | break; |
1ba585e8 | 15877 | case mask_bd_mode: |
43234a1e | 15878 | case mask_mode: |
9889cbb1 L |
15879 | if (reg > 0x7) |
15880 | { | |
15881 | oappend ("(bad)"); | |
15882 | return; | |
15883 | } | |
43234a1e L |
15884 | names = names_mask; |
15885 | break; | |
c0f3af97 | 15886 | default: |
a37a2806 NC |
15887 | /* See PR binutils/20893 for a reproducer. */ |
15888 | oappend ("(bad)"); | |
c0f3af97 L |
15889 | return; |
15890 | } | |
c0f3af97 | 15891 | break; |
43234a1e L |
15892 | case 512: |
15893 | names = names_zmm; | |
15894 | break; | |
c0f3af97 L |
15895 | default: |
15896 | abort (); | |
15897 | break; | |
15898 | } | |
539f890d | 15899 | oappend (names[reg]); |
c0f3af97 L |
15900 | } |
15901 | ||
922d8de8 DR |
15902 | /* Get the VEX immediate byte without moving codep. */ |
15903 | ||
15904 | static unsigned char | |
ccc5981b | 15905 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
15906 | { |
15907 | int bytes_before_imm = 0; | |
15908 | ||
922d8de8 DR |
15909 | if (modrm.mod != 3) |
15910 | { | |
15911 | /* There are SIB/displacement bytes. */ | |
15912 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 15913 | { |
922d8de8 | 15914 | /* 32/64 bit address mode */ |
6c067bbb | 15915 | int base = modrm.rm; |
922d8de8 DR |
15916 | |
15917 | /* Check SIB byte. */ | |
6c067bbb RM |
15918 | if (base == 4) |
15919 | { | |
15920 | FETCH_DATA (the_info, codep + 1); | |
15921 | base = *codep & 7; | |
15922 | /* When decoding the third source, don't increase | |
15923 | bytes_before_imm as this has already been incremented | |
15924 | by one in OP_E_memory while decoding the second | |
15925 | source operand. */ | |
15926 | if (opnum == 0) | |
15927 | bytes_before_imm++; | |
15928 | } | |
15929 | ||
15930 | /* Don't increase bytes_before_imm when decoding the third source, | |
15931 | it has already been incremented by OP_E_memory while decoding | |
15932 | the second source operand. */ | |
15933 | if (opnum == 0) | |
15934 | { | |
15935 | switch (modrm.mod) | |
15936 | { | |
15937 | case 0: | |
15938 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
15939 | SIB == 5, there is a 4 byte displacement. */ | |
15940 | if (base != 5) | |
15941 | /* No displacement. */ | |
15942 | break; | |
1a0670f3 | 15943 | /* Fall through. */ |
6c067bbb RM |
15944 | case 2: |
15945 | /* 4 byte displacement. */ | |
15946 | bytes_before_imm += 4; | |
15947 | break; | |
15948 | case 1: | |
15949 | /* 1 byte displacement. */ | |
15950 | bytes_before_imm++; | |
15951 | break; | |
15952 | } | |
15953 | } | |
15954 | } | |
922d8de8 | 15955 | else |
02e647f9 SP |
15956 | { |
15957 | /* 16 bit address mode */ | |
6c067bbb RM |
15958 | /* Don't increase bytes_before_imm when decoding the third source, |
15959 | it has already been incremented by OP_E_memory while decoding | |
15960 | the second source operand. */ | |
15961 | if (opnum == 0) | |
15962 | { | |
02e647f9 SP |
15963 | switch (modrm.mod) |
15964 | { | |
15965 | case 0: | |
15966 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
15967 | if (modrm.rm != 6) | |
15968 | /* No displacement. */ | |
15969 | break; | |
1a0670f3 | 15970 | /* Fall through. */ |
02e647f9 SP |
15971 | case 2: |
15972 | /* 2 byte displacement. */ | |
15973 | bytes_before_imm += 2; | |
15974 | break; | |
15975 | case 1: | |
15976 | /* 1 byte displacement: when decoding the third source, | |
15977 | don't increase bytes_before_imm as this has already | |
15978 | been incremented by one in OP_E_memory while decoding | |
15979 | the second source operand. */ | |
15980 | if (opnum == 0) | |
15981 | bytes_before_imm++; | |
ccc5981b | 15982 | |
02e647f9 SP |
15983 | break; |
15984 | } | |
922d8de8 DR |
15985 | } |
15986 | } | |
15987 | } | |
15988 | ||
15989 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
15990 | return codep [bytes_before_imm]; | |
15991 | } | |
15992 | ||
15993 | static void | |
15994 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
15995 | { | |
b9733481 L |
15996 | const char **names; |
15997 | ||
922d8de8 DR |
15998 | if (reg == -1 && modrm.mod != 3) |
15999 | { | |
16000 | OP_E_memory (bytemode, sizeflag); | |
16001 | return; | |
16002 | } | |
16003 | else | |
16004 | { | |
16005 | if (reg == -1) | |
16006 | { | |
16007 | reg = modrm.rm; | |
16008 | USED_REX (REX_B); | |
16009 | if (rex & REX_B) | |
16010 | reg += 8; | |
16011 | } | |
5f847646 JB |
16012 | if (address_mode != mode_64bit) |
16013 | reg &= 7; | |
922d8de8 DR |
16014 | } |
16015 | ||
16016 | switch (vex.length) | |
16017 | { | |
16018 | case 128: | |
b9733481 | 16019 | names = names_xmm; |
922d8de8 DR |
16020 | break; |
16021 | case 256: | |
b9733481 | 16022 | names = names_ymm; |
922d8de8 DR |
16023 | break; |
16024 | default: | |
16025 | abort (); | |
16026 | } | |
b9733481 | 16027 | oappend (names[reg]); |
922d8de8 DR |
16028 | } |
16029 | ||
a683cc34 SP |
16030 | static void |
16031 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
16032 | { | |
16033 | int reg = -1; | |
16034 | static unsigned char vex_imm8; | |
16035 | ||
16036 | if (vex_w_done == 0) | |
16037 | { | |
16038 | vex_w_done = 1; | |
16039 | ||
16040 | /* Skip mod/rm byte. */ | |
16041 | MODRM_CHECK; | |
16042 | codep++; | |
16043 | ||
16044 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
16045 | ||
16046 | if (vex.w) | |
16047 | reg = vex_imm8 >> 4; | |
16048 | ||
16049 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16050 | } | |
16051 | else if (vex_w_done == 1) | |
16052 | { | |
16053 | vex_w_done = 2; | |
16054 | ||
16055 | if (!vex.w) | |
16056 | reg = vex_imm8 >> 4; | |
16057 | ||
16058 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16059 | } | |
16060 | else | |
16061 | { | |
16062 | /* Output the imm8 directly. */ | |
16063 | scratchbuf[0] = '$'; | |
16064 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 16065 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
16066 | scratchbuf[0] = '\0'; |
16067 | codep++; | |
16068 | } | |
16069 | } | |
16070 | ||
5dd85c99 SP |
16071 | static void |
16072 | OP_Vex_2src (int bytemode, int sizeflag) | |
16073 | { | |
16074 | if (modrm.mod == 3) | |
16075 | { | |
b9733481 | 16076 | int reg = modrm.rm; |
5dd85c99 | 16077 | USED_REX (REX_B); |
b9733481 L |
16078 | if (rex & REX_B) |
16079 | reg += 8; | |
16080 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
16081 | } |
16082 | else | |
16083 | { | |
16084 | if (intel_syntax | |
16085 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
16086 | { | |
16087 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16088 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16089 | } | |
16090 | OP_E (bytemode, sizeflag); | |
16091 | } | |
16092 | } | |
16093 | ||
16094 | static void | |
16095 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
16096 | { | |
16097 | if (modrm.mod == 3) | |
16098 | { | |
16099 | /* Skip mod/rm byte. */ | |
16100 | MODRM_CHECK; | |
16101 | codep++; | |
16102 | } | |
16103 | ||
16104 | if (vex.w) | |
5f847646 JB |
16105 | { |
16106 | unsigned int reg = vex.register_specifier; | |
63c6fc6c | 16107 | vex.register_specifier = 0; |
5f847646 JB |
16108 | |
16109 | if (address_mode != mode_64bit) | |
16110 | reg &= 7; | |
16111 | oappend (names_xmm[reg]); | |
16112 | } | |
5dd85c99 SP |
16113 | else |
16114 | OP_Vex_2src (bytemode, sizeflag); | |
16115 | } | |
16116 | ||
16117 | static void | |
16118 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
16119 | { | |
16120 | if (vex.w) | |
16121 | OP_Vex_2src (bytemode, sizeflag); | |
16122 | else | |
5f847646 JB |
16123 | { |
16124 | unsigned int reg = vex.register_specifier; | |
63c6fc6c | 16125 | vex.register_specifier = 0; |
5f847646 JB |
16126 | |
16127 | if (address_mode != mode_64bit) | |
16128 | reg &= 7; | |
16129 | oappend (names_xmm[reg]); | |
16130 | } | |
5dd85c99 SP |
16131 | } |
16132 | ||
922d8de8 DR |
16133 | static void |
16134 | OP_EX_VexW (int bytemode, int sizeflag) | |
16135 | { | |
16136 | int reg = -1; | |
16137 | ||
16138 | if (!vex_w_done) | |
16139 | { | |
41effecb SP |
16140 | /* Skip mod/rm byte. */ |
16141 | MODRM_CHECK; | |
16142 | codep++; | |
16143 | ||
922d8de8 | 16144 | if (vex.w) |
ccc5981b | 16145 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
16146 | } |
16147 | else | |
16148 | { | |
16149 | if (!vex.w) | |
ccc5981b | 16150 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
16151 | } |
16152 | ||
16153 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
922d8de8 | 16154 | |
3a2430e0 JB |
16155 | if (vex_w_done) |
16156 | codep++; | |
16157 | vex_w_done = 1; | |
922d8de8 DR |
16158 | } |
16159 | ||
c0f3af97 L |
16160 | static void |
16161 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16162 | { | |
16163 | int reg; | |
b9733481 L |
16164 | const char **names; |
16165 | ||
c0f3af97 L |
16166 | FETCH_DATA (the_info, codep + 1); |
16167 | reg = *codep++; | |
16168 | ||
16169 | if (bytemode != x_mode) | |
16170 | abort (); | |
16171 | ||
c0f3af97 | 16172 | reg >>= 4; |
5f847646 JB |
16173 | if (address_mode != mode_64bit) |
16174 | reg &= 7; | |
dae39acc | 16175 | |
c0f3af97 L |
16176 | switch (vex.length) |
16177 | { | |
16178 | case 128: | |
b9733481 | 16179 | names = names_xmm; |
c0f3af97 L |
16180 | break; |
16181 | case 256: | |
b9733481 | 16182 | names = names_ymm; |
c0f3af97 L |
16183 | break; |
16184 | default: | |
16185 | abort (); | |
16186 | } | |
b9733481 | 16187 | oappend (names[reg]); |
c0f3af97 L |
16188 | } |
16189 | ||
922d8de8 DR |
16190 | static void |
16191 | OP_XMM_VexW (int bytemode, int sizeflag) | |
16192 | { | |
16193 | /* Turn off the REX.W bit since it is used for swapping operands | |
16194 | now. */ | |
16195 | rex &= ~REX_W; | |
16196 | OP_XMM (bytemode, sizeflag); | |
16197 | } | |
16198 | ||
c0f3af97 L |
16199 | static void |
16200 | OP_EX_Vex (int bytemode, int sizeflag) | |
16201 | { | |
16202 | if (modrm.mod != 3) | |
63c6fc6c | 16203 | need_vex_reg = 0; |
c0f3af97 L |
16204 | OP_EX (bytemode, sizeflag); |
16205 | } | |
16206 | ||
16207 | static void | |
16208 | OP_XMM_Vex (int bytemode, int sizeflag) | |
16209 | { | |
16210 | if (modrm.mod != 3) | |
63c6fc6c | 16211 | need_vex_reg = 0; |
c0f3af97 L |
16212 | OP_XMM (bytemode, sizeflag); |
16213 | } | |
16214 | ||
ea397f5b L |
16215 | static struct op vex_cmp_op[] = |
16216 | { | |
16217 | { STRING_COMMA_LEN ("eq") }, | |
16218 | { STRING_COMMA_LEN ("lt") }, | |
16219 | { STRING_COMMA_LEN ("le") }, | |
16220 | { STRING_COMMA_LEN ("unord") }, | |
16221 | { STRING_COMMA_LEN ("neq") }, | |
16222 | { STRING_COMMA_LEN ("nlt") }, | |
16223 | { STRING_COMMA_LEN ("nle") }, | |
16224 | { STRING_COMMA_LEN ("ord") }, | |
16225 | { STRING_COMMA_LEN ("eq_uq") }, | |
16226 | { STRING_COMMA_LEN ("nge") }, | |
16227 | { STRING_COMMA_LEN ("ngt") }, | |
16228 | { STRING_COMMA_LEN ("false") }, | |
16229 | { STRING_COMMA_LEN ("neq_oq") }, | |
16230 | { STRING_COMMA_LEN ("ge") }, | |
16231 | { STRING_COMMA_LEN ("gt") }, | |
16232 | { STRING_COMMA_LEN ("true") }, | |
16233 | { STRING_COMMA_LEN ("eq_os") }, | |
16234 | { STRING_COMMA_LEN ("lt_oq") }, | |
16235 | { STRING_COMMA_LEN ("le_oq") }, | |
16236 | { STRING_COMMA_LEN ("unord_s") }, | |
16237 | { STRING_COMMA_LEN ("neq_us") }, | |
16238 | { STRING_COMMA_LEN ("nlt_uq") }, | |
16239 | { STRING_COMMA_LEN ("nle_uq") }, | |
16240 | { STRING_COMMA_LEN ("ord_s") }, | |
16241 | { STRING_COMMA_LEN ("eq_us") }, | |
16242 | { STRING_COMMA_LEN ("nge_uq") }, | |
16243 | { STRING_COMMA_LEN ("ngt_uq") }, | |
16244 | { STRING_COMMA_LEN ("false_os") }, | |
16245 | { STRING_COMMA_LEN ("neq_os") }, | |
16246 | { STRING_COMMA_LEN ("ge_oq") }, | |
16247 | { STRING_COMMA_LEN ("gt_oq") }, | |
16248 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
16249 | }; |
16250 | ||
16251 | static void | |
16252 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16253 | { | |
16254 | unsigned int cmp_type; | |
16255 | ||
16256 | FETCH_DATA (the_info, codep + 1); | |
16257 | cmp_type = *codep++ & 0xff; | |
16258 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
16259 | { | |
16260 | char suffix [3]; | |
ea397f5b | 16261 | char *p = mnemonicendp - 2; |
c0f3af97 L |
16262 | suffix[0] = p[0]; |
16263 | suffix[1] = p[1]; | |
16264 | suffix[2] = '\0'; | |
ea397f5b L |
16265 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
16266 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
16267 | } |
16268 | else | |
16269 | { | |
16270 | /* We have a reserved extension byte. Output it directly. */ | |
16271 | scratchbuf[0] = '$'; | |
16272 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16273 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16274 | scratchbuf[0] = '\0'; |
16275 | } | |
16276 | } | |
16277 | ||
43234a1e L |
16278 | static void |
16279 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16280 | int sizeflag ATTRIBUTE_UNUSED) | |
16281 | { | |
16282 | unsigned int cmp_type; | |
16283 | ||
16284 | if (!vex.evex) | |
16285 | abort (); | |
16286 | ||
16287 | FETCH_DATA (the_info, codep + 1); | |
16288 | cmp_type = *codep++ & 0xff; | |
16289 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
16290 | If it's the case, print suffix, otherwise - print the immediate. */ | |
16291 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
16292 | && cmp_type != 3 | |
16293 | && cmp_type != 7) | |
16294 | { | |
16295 | char suffix [3]; | |
16296 | char *p = mnemonicendp - 2; | |
16297 | ||
16298 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
16299 | if (p[0] == 'p') | |
16300 | { | |
16301 | p++; | |
16302 | suffix[0] = p[0]; | |
16303 | suffix[1] = '\0'; | |
16304 | } | |
16305 | else | |
16306 | { | |
16307 | suffix[0] = p[0]; | |
16308 | suffix[1] = p[1]; | |
16309 | suffix[2] = '\0'; | |
16310 | } | |
16311 | ||
16312 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
16313 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
16314 | } | |
be92cb14 JB |
16315 | else |
16316 | { | |
16317 | /* We have a reserved extension byte. Output it directly. */ | |
16318 | scratchbuf[0] = '$'; | |
16319 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
16320 | oappend_maybe_intel (scratchbuf); | |
16321 | scratchbuf[0] = '\0'; | |
16322 | } | |
16323 | } | |
16324 | ||
16325 | static const struct op xop_cmp_op[] = | |
16326 | { | |
16327 | { STRING_COMMA_LEN ("lt") }, | |
16328 | { STRING_COMMA_LEN ("le") }, | |
16329 | { STRING_COMMA_LEN ("gt") }, | |
16330 | { STRING_COMMA_LEN ("ge") }, | |
16331 | { STRING_COMMA_LEN ("eq") }, | |
16332 | { STRING_COMMA_LEN ("neq") }, | |
16333 | { STRING_COMMA_LEN ("false") }, | |
16334 | { STRING_COMMA_LEN ("true") } | |
16335 | }; | |
16336 | ||
16337 | static void | |
16338 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16339 | int sizeflag ATTRIBUTE_UNUSED) | |
16340 | { | |
16341 | unsigned int cmp_type; | |
16342 | ||
16343 | FETCH_DATA (the_info, codep + 1); | |
16344 | cmp_type = *codep++ & 0xff; | |
16345 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
16346 | { | |
16347 | char suffix[3]; | |
16348 | char *p = mnemonicendp - 2; | |
16349 | ||
16350 | /* vpcom* can have both one- and two-lettered suffix. */ | |
16351 | if (p[0] == 'm') | |
16352 | { | |
16353 | p++; | |
16354 | suffix[0] = p[0]; | |
16355 | suffix[1] = '\0'; | |
16356 | } | |
16357 | else | |
16358 | { | |
16359 | suffix[0] = p[0]; | |
16360 | suffix[1] = p[1]; | |
16361 | suffix[2] = '\0'; | |
16362 | } | |
16363 | ||
16364 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
16365 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
16366 | } | |
43234a1e L |
16367 | else |
16368 | { | |
16369 | /* We have a reserved extension byte. Output it directly. */ | |
16370 | scratchbuf[0] = '$'; | |
16371 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16372 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
16373 | scratchbuf[0] = '\0'; |
16374 | } | |
16375 | } | |
16376 | ||
ea397f5b L |
16377 | static const struct op pclmul_op[] = |
16378 | { | |
16379 | { STRING_COMMA_LEN ("lql") }, | |
16380 | { STRING_COMMA_LEN ("hql") }, | |
16381 | { STRING_COMMA_LEN ("lqh") }, | |
16382 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
16383 | }; |
16384 | ||
16385 | static void | |
16386 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16387 | int sizeflag ATTRIBUTE_UNUSED) | |
16388 | { | |
16389 | unsigned int pclmul_type; | |
16390 | ||
16391 | FETCH_DATA (the_info, codep + 1); | |
16392 | pclmul_type = *codep++ & 0xff; | |
16393 | switch (pclmul_type) | |
16394 | { | |
16395 | case 0x10: | |
16396 | pclmul_type = 2; | |
16397 | break; | |
16398 | case 0x11: | |
16399 | pclmul_type = 3; | |
16400 | break; | |
16401 | default: | |
16402 | break; | |
7bb15c6f | 16403 | } |
c0f3af97 L |
16404 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
16405 | { | |
16406 | char suffix [4]; | |
ea397f5b | 16407 | char *p = mnemonicendp - 3; |
c0f3af97 L |
16408 | suffix[0] = p[0]; |
16409 | suffix[1] = p[1]; | |
16410 | suffix[2] = p[2]; | |
16411 | suffix[3] = '\0'; | |
ea397f5b L |
16412 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
16413 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
16414 | } |
16415 | else | |
16416 | { | |
16417 | /* We have a reserved extension byte. Output it directly. */ | |
16418 | scratchbuf[0] = '$'; | |
16419 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 16420 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16421 | scratchbuf[0] = '\0'; |
16422 | } | |
16423 | } | |
16424 | ||
f1f8f695 L |
16425 | static void |
16426 | MOVBE_Fixup (int bytemode, int sizeflag) | |
16427 | { | |
16428 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 16429 | char *p = mnemonicendp; |
f1f8f695 L |
16430 | |
16431 | switch (bytemode) | |
16432 | { | |
16433 | case v_mode: | |
16434 | if (intel_syntax) | |
ea397f5b | 16435 | goto skip; |
f1f8f695 L |
16436 | |
16437 | USED_REX (REX_W); | |
16438 | if (sizeflag & SUFFIX_ALWAYS) | |
16439 | { | |
16440 | if (rex & REX_W) | |
16441 | *p++ = 'q'; | |
f1f8f695 | 16442 | else |
f16cd0d5 L |
16443 | { |
16444 | if (sizeflag & DFLAG) | |
16445 | *p++ = 'l'; | |
16446 | else | |
16447 | *p++ = 'w'; | |
16448 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16449 | } | |
f1f8f695 | 16450 | } |
f1f8f695 L |
16451 | break; |
16452 | default: | |
16453 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16454 | break; | |
16455 | } | |
ea397f5b | 16456 | mnemonicendp = p; |
f1f8f695 L |
16457 | *p = '\0'; |
16458 | ||
dc1e8a47 | 16459 | skip: |
f1f8f695 L |
16460 | OP_M (bytemode, sizeflag); |
16461 | } | |
f88c9eb0 | 16462 | |
bc31405e L |
16463 | static void |
16464 | MOVSXD_Fixup (int bytemode, int sizeflag) | |
16465 | { | |
16466 | /* Add proper suffix to "movsxd". */ | |
16467 | char *p = mnemonicendp; | |
16468 | ||
16469 | switch (bytemode) | |
16470 | { | |
16471 | case movsxd_mode: | |
16472 | if (intel_syntax) | |
16473 | { | |
16474 | *p++ = 'x'; | |
16475 | *p++ = 'd'; | |
16476 | goto skip; | |
16477 | } | |
16478 | ||
16479 | USED_REX (REX_W); | |
16480 | if (rex & REX_W) | |
16481 | { | |
16482 | *p++ = 'l'; | |
16483 | *p++ = 'q'; | |
16484 | } | |
16485 | else | |
16486 | { | |
16487 | *p++ = 'x'; | |
16488 | *p++ = 'd'; | |
16489 | } | |
16490 | break; | |
16491 | default: | |
16492 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16493 | break; | |
16494 | } | |
16495 | ||
dc1e8a47 | 16496 | skip: |
bc31405e L |
16497 | mnemonicendp = p; |
16498 | *p = '\0'; | |
16499 | OP_E (bytemode, sizeflag); | |
16500 | } | |
16501 | ||
f88c9eb0 SP |
16502 | static void |
16503 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16504 | { | |
16505 | int reg; | |
16506 | const char **names; | |
16507 | ||
16508 | /* Skip mod/rm byte. */ | |
16509 | MODRM_CHECK; | |
16510 | codep++; | |
16511 | ||
390a6789 | 16512 | if (rex & REX_W) |
f88c9eb0 | 16513 | names = names64; |
f88c9eb0 | 16514 | else |
ce7d077e | 16515 | names = names32; |
f88c9eb0 SP |
16516 | |
16517 | reg = modrm.rm; | |
16518 | USED_REX (REX_B); | |
16519 | if (rex & REX_B) | |
16520 | reg += 8; | |
16521 | ||
16522 | oappend (names[reg]); | |
16523 | } | |
16524 | ||
16525 | static void | |
16526 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16527 | { | |
16528 | const char **names; | |
5f847646 | 16529 | unsigned int reg = vex.register_specifier; |
63c6fc6c | 16530 | vex.register_specifier = 0; |
f88c9eb0 | 16531 | |
390a6789 | 16532 | if (rex & REX_W) |
f88c9eb0 | 16533 | names = names64; |
f88c9eb0 | 16534 | else |
ce7d077e | 16535 | names = names32; |
f88c9eb0 | 16536 | |
5f847646 JB |
16537 | if (address_mode != mode_64bit) |
16538 | reg &= 7; | |
16539 | oappend (names[reg]); | |
f88c9eb0 | 16540 | } |
43234a1e L |
16541 | |
16542 | static void | |
16543 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16544 | { | |
16545 | if (!vex.evex | |
1ba585e8 | 16546 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
16547 | abort (); |
16548 | ||
16549 | USED_REX (REX_R); | |
16550 | if ((rex & REX_R) != 0 || !vex.r) | |
16551 | { | |
16552 | BadOp (); | |
16553 | return; | |
16554 | } | |
16555 | ||
16556 | oappend (names_mask [modrm.reg]); | |
16557 | } | |
16558 | ||
16559 | static void | |
16560 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16561 | { | |
43234a1e L |
16562 | if (modrm.mod == 3 && vex.b) |
16563 | switch (bytemode) | |
16564 | { | |
70df6fc9 L |
16565 | case evex_rounding_64_mode: |
16566 | if (address_mode != mode_64bit) | |
16567 | { | |
16568 | oappend ("(bad)"); | |
16569 | break; | |
16570 | } | |
16571 | /* Fall through. */ | |
43234a1e L |
16572 | case evex_rounding_mode: |
16573 | oappend (names_rounding[vex.ll]); | |
16574 | break; | |
16575 | case evex_sae_mode: | |
16576 | oappend ("{sae}"); | |
16577 | break; | |
16578 | default: | |
6df22cf6 | 16579 | abort (); |
43234a1e L |
16580 | break; |
16581 | } | |
16582 | } |