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ubsan: moxie: left shift of negative value
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
cf950fd4
AM		 12019-12-16 Alan Modra <amodra@gmail.com>
2
3 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
4 (print_insn_moxie): Remove unnecessary cast.
5
967354c3
AM		 62019-12-12 Alan Modra <amodra@gmail.com>
7
8 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
9 mask.
10
1d61b032
AM		 112019-12-11 Alan Modra <amodra@gmail.com>
12
13 * arc-dis.c (BITS): Don't truncate high bits with shifts.
14 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
15 * tic54x-dis.c (print_instruction): Likewise.
16 * tilegx-opc.c (parse_insn_tilegx): Likewise.
17 * tilepro-opc.c (parse_insn_tilepro): Likewise.
18 * visium-dis.c (disassem_class0): Likewise.
19 * pdp11-dis.c (sign_extend): Likewise.
20 (SIGN_BITS): Delete.
21 * epiphany-ibld.c: Regenerate.
22 * lm32-ibld.c: Regenerate.
23 * m32c-ibld.c: Regenerate.
24
5afa80e9
AM		 252019-12-11 Alan Modra <amodra@gmail.com>
26
27 * ns32k-dis.c (sign_extend): Correct last patch.
28
5c05618a
AM		 292019-12-11 Alan Modra <amodra@gmail.com>
30
31 * vax-dis.c (NEXTLONG): Avoid signed overflow.
32
2a81ccbb
AM		 332019-12-11 Alan Modra <amodra@gmail.com>
34
35 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
36 sign extend using shifts.
37
b84f6152
AM		 382019-12-11 Alan Modra <amodra@gmail.com>
39
40 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
41
66152f16
AM		 422019-12-11 Alan Modra <amodra@gmail.com>
43
44 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
45 on NULL registertable entry.
46 (tic4x_hash_opcode): Use unsigned arithmetic.
47
205c426a
AM		 482019-12-11 Alan Modra <amodra@gmail.com>
49
50 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
51
fb4cb4e2
AM		 522019-12-11 Alan Modra <amodra@gmail.com>
53
54 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
55 (bit_extract_simple, sign_extend): Likewise.
56
96f1f604
AM		 572019-12-11 Alan Modra <amodra@gmail.com>
58
59 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
60
8c9b4171
AM		 612019-12-11 Alan Modra <amodra@gmail.com>
62
63 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
64
334175b6
AM		 652019-12-11 Alan Modra <amodra@gmail.com>
66
67 * m68k-dis.c (COERCE32): Cast value first.
68 (NEXTLONG, NEXTULONG): Avoid signed overflow.
69
f8a87c78
AM		 702019-12-11 Alan Modra <amodra@gmail.com>
71
72 * h8300-dis.c (extract_immediate): Avoid signed overflow.
73 (bfd_h8_disassemble): Likewise.
74
159653d8
AM		 752019-12-11 Alan Modra <amodra@gmail.com>
76
77 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
78 past end of operands array.
79
d93bba9e
AM		 802019-12-11 Alan Modra <amodra@gmail.com>
81
82 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
83 overflow when collecting bytes of a number.
84
c202f69e
AM		 852019-12-11 Alan Modra <amodra@gmail.com>
86
87 * cris-dis.c (print_with_operands): Avoid signed integer
88 overflow when collecting bytes of a 32-bit integer.
89
0ef562a4
AM		 902019-12-11 Alan Modra <amodra@gmail.com>
91
92 * cr16-dis.c (EXTRACT, SBM): Rewrite.
93 (cr16_match_opcode): Delete duplicate bcond test.
94
2fd2b153
AM		 952019-12-11 Alan Modra <amodra@gmail.com>
96
97 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
98 (SIGNBIT): New.
99 (MASKBITS, SIGNEXTEND): Rewrite.
100 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
101 unsigned arithmetic, instead assign result of SIGNEXTEND back
102 to x.
103 (fmtconst_val): Use 1u in shift expression.
104
a11db3e9
AM		 1052019-12-11 Alan Modra <amodra@gmail.com>
106
107 * arc-dis.c (find_format_from_table): Use ull constant when
108 shifting by up to 32.
109
9d48687b
AM		 1102019-12-11 Alan Modra <amodra@gmail.com>
111
112 PR 25270
113 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
114 false when field is zero for sve_size_tsz_bhs.
115
b8e61daa
AM		 1162019-12-11 Alan Modra <amodra@gmail.com>
117
118 * epiphany-ibld.c: Regenerate.
119
20135676
AM		 1202019-12-10 Alan Modra <amodra@gmail.com>
121
122 PR 24960
123 * disassemble.c (disassemble_free_target): New function.
124
103ebbc3
AM		 1252019-12-10 Alan Modra <amodra@gmail.com>
126
127 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
128 * disassemble.c (disassemble_init_for_target): Likewise.
129 * bpf-dis.c: Regenerate.
130 * epiphany-dis.c: Regenerate.
131 * fr30-dis.c: Regenerate.
132 * frv-dis.c: Regenerate.
133 * ip2k-dis.c: Regenerate.
134 * iq2000-dis.c: Regenerate.
135 * lm32-dis.c: Regenerate.
136 * m32c-dis.c: Regenerate.
137 * m32r-dis.c: Regenerate.
138 * mep-dis.c: Regenerate.
139 * mt-dis.c: Regenerate.
140 * or1k-dis.c: Regenerate.
141 * xc16x-dis.c: Regenerate.
142 * xstormy16-dis.c: Regenerate.
143
6f0e0752
AM		 1442019-12-10 Alan Modra <amodra@gmail.com>
145
146 * ppc-dis.c (private): Delete variable.
147 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
148 (powerpc_init_dialect): Don't use global private.
149
e7c22a69
AM		 1502019-12-10 Alan Modra <amodra@gmail.com>
151
152 * s12z-opc.c: Formatting.
153
0a6aef6b
AM		 1542019-12-08 Alan Modra <amodra@gmail.com>
155
156 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
157 registers.
158
2dc4b12f
JB		 1592019-12-05 Jan Beulich <jbeulich@suse.com>
160
161 * aarch64-tbl.h (aarch64_feature_crypto,
162 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
163 CRYPTO_V8_2_INSN): Delete.
164
378fd436
AM		 1652019-12-05 Alan Modra <amodra@gmail.com>
166
167 PR 25249
168 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
169 (struct string_buf): New.
170 (strbuf): New function.
171 (get_field): Use strbuf rather than strdup of local temp.
172 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
173 (get_field_rfsl, get_field_imm15): Likewise.
174 (get_field_rd, get_field_r1, get_field_r2): Update macros.
175 (get_field_special): Likewise. Don't strcpy spr. Formatting.
176 (print_insn_microblaze): Formatting. Init and pass string_buf to
177 get_field functions.
178
0ba59a29
JB		 1792019-12-04 Jan Beulich <jbeulich@suse.com>
180
181 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
182 * i386-tbl.h: Re-generate.
183
77ad8092
JB		 1842019-12-04 Jan Beulich <jbeulich@suse.com>
185
186 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
187
3036c899
JB		 1882019-12-04 Jan Beulich <jbeulich@suse.com>
189
190 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
191 forms.
192 (xbegin): Drop DefaultSize.
193 * i386-tbl.h: Re-generate.
194
8b301fbb
MI		 1952019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
196
197 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
198 Change the coproc CRC conditions to use the extension
199 feature set, second word, base on ARM_EXT2_CRC.
200
6aa385b9
JB		 2012019-11-14 Jan Beulich <jbeulich@suse.com>
202
203 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
204 * i386-tbl.h: Re-generate.
205
0cfa3eb3
JB		 2062019-11-14 Jan Beulich <jbeulich@suse.com>
207
208 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
209 JumpInterSegment, and JumpAbsolute entries.
210 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
211 JUMP_ABSOLUTE): Define.
212 (struct i386_opcode_modifier): Extend jump field to 3 bits.
213 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
214 fields.
215 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
216 JumpInterSegment): Define.
217 * i386-tbl.h: Re-generate.
218
6f2f06be
JB		 2192019-11-14 Jan Beulich <jbeulich@suse.com>
220
221 * i386-gen.c (operand_type_init): Remove
222 OPERAND_TYPE_JUMPABSOLUTE entry.
223 (opcode_modifiers): Add JumpAbsolute entry.
224 (operand_types): Remove JumpAbsolute entry.
225 * i386-opc.h (JumpAbsolute): Move between enums.
226 (struct i386_opcode_modifier): Add jumpabsolute field.
227 (union i386_operand_type): Remove jumpabsolute field.
228 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
229 * i386-init.h, i386-tbl.h: Re-generate.
230
601e8564
JB		 2312019-11-14 Jan Beulich <jbeulich@suse.com>
232
233 * i386-gen.c (opcode_modifiers): Add AnySize entry.
234 (operand_types): Remove AnySize entry.
235 * i386-opc.h (AnySize): Move between enums.
236 (struct i386_opcode_modifier): Add anysize field.
237 (OTUnused): Un-comment.
238 (union i386_operand_type): Remove anysize field.
239 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
240 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
241 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
242 AnySize.
243 * i386-tbl.h: Re-generate.
244
7722d40a
JW		 2452019-11-12 Nelson Chu <nelson.chu@sifive.com>
246
247 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
248 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
249 use the floating point register (FPR).
250
ce760a76
MI		 2512019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
252
253 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
254 cmode 1101.
255 (is_mve_encoding_conflict): Update cmode conflict checks for
256 MVE_VMVN_IMM.
257
51c8edf6
JB		 2582019-11-12 Jan Beulich <jbeulich@suse.com>
259
260 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
261 entry.
262 (operand_types): Remove EsSeg entry.
263 (main): Replace stale use of OTMax.
264 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
265 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
266 (EsSeg): Delete.
267 (OTUnused): Comment out.
268 (union i386_operand_type): Remove esseg field.
269 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
270 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
271 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
272 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
273 * i386-init.h, i386-tbl.h: Re-generate.
274
474da251
JB		 2752019-11-12 Jan Beulich <jbeulich@suse.com>
276
277 * i386-gen.c (operand_instances): Add RegB entry.
278 * i386-opc.h (enum operand_instance): Add RegB.
279 * i386-opc.tbl (RegC, RegD, RegB): Define.
280 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
281 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
282 monitorx, mwaitx): Drop ImmExt and convert encodings
283 accordingly.
284 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
285 (edx, rdx): Add Instance=RegD.
286 (ebx, rbx): Add Instance=RegB.
287 * i386-tbl.h: Re-generate.
288
75e5731b
JB		 2892019-11-12 Jan Beulich <jbeulich@suse.com>
290
291 * i386-gen.c (operand_type_init): Adjust
292 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
293 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
294 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
295 (operand_instances): New.
296 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
297 (output_operand_type): New parameter "instance". Process it.
298 (process_i386_operand_type): New local variable "instance".
299 (main): Adjust static assertions.
300 * i386-opc.h (INSTANCE_WIDTH): Define.
301 (enum operand_instance): New.
302 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
303 (union i386_operand_type): Replace acc, inoutportreg, and
304 shiftcount by instance.
305 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
306 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
307 Add Instance=.
308 * i386-init.h, i386-tbl.h: Re-generate.
309
91802f3c
JB		 3102019-11-11 Jan Beulich <jbeulich@suse.com>
311
312 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
313 smaxp/sminp entries' "tied_operand" field to 2.
314
4f5fc85d
JB		 3152019-11-11 Jan Beulich <jbeulich@suse.com>
316
317 * aarch64-opc.c (operand_general_constraint_met_p): Replace
318 "index" local variable by that of the already existing "num".
319
dc2be329
L		 3202019-11-08 H.J. Lu <hongjiu.lu@intel.com>
321
322 PR gas/25167
323 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
324 * i386-tbl.h: Regenerated.
325
f74a6307
JB		 3262019-11-08 Jan Beulich <jbeulich@suse.com>
327
328 * i386-gen.c (operand_type_init): Add Class= to
329 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
330 OPERAND_TYPE_REGBND entry.
331 (operand_classes): Add RegMask and RegBND entries.
332 (operand_types): Drop RegMask and RegBND entry.
333 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
334 (RegMask, RegBND): Delete.
335 (union i386_operand_type): Remove regmask and regbnd fields.
336 * i386-opc.tbl (RegMask, RegBND): Define.
337 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
338 Class=RegBND.
339 * i386-init.h, i386-tbl.h: Re-generate.
340
3528c362
JB		 3412019-11-08 Jan Beulich <jbeulich@suse.com>
342
343 * i386-gen.c (operand_type_init): Add Class= to
344 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
345 OPERAND_TYPE_REGZMM entries.
346 (operand_classes): Add RegMMX and RegSIMD entries.
347 (operand_types): Drop RegMMX and RegSIMD entries.
348 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
349 (RegMMX, RegSIMD): Delete.
350 (union i386_operand_type): Remove regmmx and regsimd fields.
351 * i386-opc.tbl (RegMMX): Define.
352 (RegXMM, RegYMM, RegZMM): Add Class=.
353 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
354 Class=RegSIMD.
355 * i386-init.h, i386-tbl.h: Re-generate.
356
4a5c67ed
JB		 3572019-11-08 Jan Beulich <jbeulich@suse.com>
358
359 * i386-gen.c (operand_type_init): Add Class= to
360 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
361 entries.
362 (operand_classes): Add RegCR, RegDR, and RegTR entries.
363 (operand_types): Drop Control, Debug, and Test entries.
364 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
365 (Control, Debug, Test): Delete.
366 (union i386_operand_type): Remove control, debug, and test
367 fields.
368 * i386-opc.tbl (Control, Debug, Test): Define.
369 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
370 Class=RegDR, and Test by Class=RegTR.
371 * i386-init.h, i386-tbl.h: Re-generate.
372
00cee14f
JB		 3732019-11-08 Jan Beulich <jbeulich@suse.com>
374
375 * i386-gen.c (operand_type_init): Add Class= to
376 OPERAND_TYPE_SREG entry.
377 (operand_classes): Add SReg entry.
378 (operand_types): Drop SReg entry.
379 * i386-opc.h (enum operand_class): Add SReg.
380 (SReg): Delete.
381 (union i386_operand_type): Remove sreg field.
382 * i386-opc.tbl (SReg): Define.
383 * i386-reg.tbl: Replace SReg by Class=SReg.
384 * i386-init.h, i386-tbl.h: Re-generate.
385
bab6aec1
JB		 3862019-11-08 Jan Beulich <jbeulich@suse.com>
387
388 * i386-gen.c (operand_type_init): Add Class=. New
389 OPERAND_TYPE_ANYIMM entry.
390 (operand_classes): New.
391 (operand_types): Drop Reg entry.
392 (output_operand_type): New parameter "class". Process it.
393 (process_i386_operand_type): New local variable "class".
394 (main): Adjust static assertions.
395 * i386-opc.h (CLASS_WIDTH): Define.
396 (enum operand_class): New.
397 (Reg): Replace by Class. Adjust comment.
398 (union i386_operand_type): Replace reg by class.
399 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
400 Class=.
401 * i386-reg.tbl: Replace Reg by Class=Reg.
402 * i386-init.h: Re-generate.
403
1f4cd317
MM		 4042019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
405
406 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
407 (aarch64_opcode_table): Add data gathering hint mnemonic.
408 * opcodes/aarch64-dis-2.c: Account for new instruction.
409
616ce08e
MM		 4102019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
411
412 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
413
414
8382113f
MM		 4152019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
416
417 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
418 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
419 aarch64_feature_f64mm): New feature sets.
420 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
421 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
422 instructions.
423 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
424 macros.
425 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
426 (OP_SVE_QQQ): New qualifier.
427 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
428 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
429 the movprfx constraint.
430 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
431 (aarch64_opcode_table): Define new instructions smmla,
432 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
433 uzip{1/2}, trn{1/2}.
434 * aarch64-opc.c (operand_general_constraint_met_p): Handle
435 AARCH64_OPND_SVE_ADDR_RI_S4x32.
436 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
437 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
438 Account for new instructions.
439 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
440 S4x32 operand.
441 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
442
aab2c27d
MM		 4432019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4442019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
445
446 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
447 Armv8.6-A.
448 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
449 (neon_opcodes): Add bfloat SIMD instructions.
450 (print_insn_coprocessor): Add new control character %b to print
451 condition code without checking cp_num.
452 (print_insn_neon): Account for BFloat16 instructions that have no
453 special top-byte handling.
454
33593eaf
MM		 4552019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4562019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
457
458 * arm-dis.c (print_insn_coprocessor,
459 print_insn_generic_coprocessor): Create wrapper functions around
460 the implementation of the print_insn_coprocessor control codes.
461 (print_insn_coprocessor_1): Original print_insn_coprocessor
462 function that now takes which array to look at as an argument.
463 (print_insn_arm): Use both print_insn_coprocessor and
464 print_insn_generic_coprocessor.
465 (print_insn_thumb32): As above.
466
df678013
MM		 4672019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4682019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
469
470 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
471 in reglane special case.
472 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
473 aarch64_find_next_opcode): Account for new instructions.
474 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
475 in reglane special case.
476 * aarch64-opc.c (struct operand_qualifier_data): Add data for
477 new AARCH64_OPND_QLF_S_2H qualifier.
478 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
479 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
480 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
481 sets.
482 (BFLOAT_SVE, BFLOAT): New feature set macros.
483 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
484 instructions.
485 (aarch64_opcode_table): Define new instructions bfdot,
486 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
487 bfcvtn2, bfcvt.
488
8ae2d3d9
MM		 4892019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4902019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
491
492 * aarch64-tbl.h (ARMV8_6): New macro.
493
142861df
JB		 4942019-11-07 Jan Beulich <jbeulich@suse.com>
495
496 * i386-dis.c (prefix_table): Add mcommit.
497 (rm_table): Add rdpru.
498 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
499 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
500 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
501 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
502 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
503 * i386-opc.tbl (mcommit, rdpru): New.
504 * i386-init.h, i386-tbl.h: Re-generate.
505
081e283f
JB		 5062019-11-07 Jan Beulich <jbeulich@suse.com>
507
508 * i386-dis.c (OP_Mwait): Drop local variable "names", use
509 "names32" instead.
510 (OP_Monitor): Drop local variable "op1_names", re-purpose
511 "names" for it instead, and replace former "names" uses by
512 "names32" ones.
513
c050c89a
JB		 5142019-11-07 Jan Beulich <jbeulich@suse.com>
515
516 PR/gas 25167
517 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
518 operand-less forms.
519 * opcodes/i386-tbl.h: Re-generate.
520
7abb8d81
JB		 5212019-11-05 Jan Beulich <jbeulich@suse.com>
522
523 * i386-dis.c (OP_Mwaitx): Delete.
524 (prefix_table): Use OP_Mwait for mwaitx entry.
525 (OP_Mwait): Also handle mwaitx.
526
267b8516
JB		 5272019-11-05 Jan Beulich <jbeulich@suse.com>
528
529 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
530 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
531 (prefix_table): Add respective entries.
532 (rm_table): Link to those entries.
533
f8687e93
JB		 5342019-11-05 Jan Beulich <jbeulich@suse.com>
535
536 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
537 (REG_0F1C_P_0_MOD_0): ... this.
538 (REG_0F1E_MOD_3): Rename to ...
539 (REG_0F1E_P_1_MOD_3): ... this.
540 (RM_0F01_REG_5): Rename to ...
541 (RM_0F01_REG_5_MOD_3): ... this.
542 (RM_0F01_REG_7): Rename to ...
543 (RM_0F01_REG_7_MOD_3): ... this.
544 (RM_0F1E_MOD_3_REG_7): Rename to ...
545 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
546 (RM_0FAE_REG_6): Rename to ...
547 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
548 (RM_0FAE_REG_7): Rename to ...
549 (RM_0FAE_REG_7_MOD_3): ... this.
550 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
551 (PREFIX_0F01_REG_5_MOD_0): ... this.
552 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
553 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
554 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
555 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
556 (PREFIX_0FAE_REG_0): Rename to ...
557 (PREFIX_0FAE_REG_0_MOD_3): ... this.
558 (PREFIX_0FAE_REG_1): Rename to ...
559 (PREFIX_0FAE_REG_1_MOD_3): ... this.
560 (PREFIX_0FAE_REG_2): Rename to ...
561 (PREFIX_0FAE_REG_2_MOD_3): ... this.
562 (PREFIX_0FAE_REG_3): Rename to ...
563 (PREFIX_0FAE_REG_3_MOD_3): ... this.
564 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
565 (PREFIX_0FAE_REG_4_MOD_0): ... this.
566 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
567 (PREFIX_0FAE_REG_4_MOD_3): ... this.
568 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
569 (PREFIX_0FAE_REG_5_MOD_0): ... this.
570 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
571 (PREFIX_0FAE_REG_5_MOD_3): ... this.
572 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
573 (PREFIX_0FAE_REG_6_MOD_0): ... this.
574 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
575 (PREFIX_0FAE_REG_6_MOD_3): ... this.
576 (PREFIX_0FAE_REG_7): Rename to ...
577 (PREFIX_0FAE_REG_7_MOD_0): ... this.
578 (PREFIX_MOD_0_0FC3): Rename to ...
579 (PREFIX_0FC3_MOD_0): ... this.
580 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
581 (PREFIX_0FC7_REG_6_MOD_0): ... this.
582 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
583 (PREFIX_0FC7_REG_6_MOD_3): ... this.
584 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
585 (PREFIX_0FC7_REG_7_MOD_3): ... this.
586 (reg_table, prefix_table, mod_table, rm_table): Adjust
587 accordingly.
588
5103274f
NC		 5892019-11-04 Nick Clifton <nickc@redhat.com>
590
591 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
592 of a v850 system register. Move the v850_sreg_names array into
593 this function.
594 (get_v850_reg_name): Likewise for ordinary register names.
595 (get_v850_vreg_name): Likewise for vector register names.
596 (get_v850_cc_name): Likewise for condition codes.
597 * get_v850_float_cc_name): Likewise for floating point condition
598 codes.
599 (get_v850_cacheop_name): Likewise for cache-ops.
600 (get_v850_prefop_name): Likewise for pref-ops.
601 (disassemble): Use the new accessor functions.
602
1820262b
DB		 6032019-10-30 Delia Burduv <delia.burduv@arm.com>
604
605 * aarch64-opc.c (print_immediate_offset_address): Don't print the
606 immediate for the writeback form of ldraa/ldrab if it is 0.
607 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
608 * aarch64-opc-2.c: Regenerated.
609
3cc17af5
JB		 6102019-10-30 Jan Beulich <jbeulich@suse.com>
611
612 * i386-gen.c (operand_type_shorthands): Delete.
613 (operand_type_init): Expand previous shorthands.
614 (set_bitfield_from_shorthand): Rename back to ...
615 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
616 of operand_type_init[].
617 (set_bitfield): Adjust call to the above function.
618 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
619 RegXMM, RegYMM, RegZMM): Define.
620 * i386-reg.tbl: Expand prior shorthands.
621
a2cebd03
JB		 6222019-10-30 Jan Beulich <jbeulich@suse.com>
623
624 * i386-gen.c (output_i386_opcode): Change order of fields
625 emitted to output.
626 * i386-opc.h (struct insn_template): Move operands field.
627 Convert extension_opcode field to unsigned short.
628 * i386-tbl.h: Re-generate.
629
507916b8
JB		 6302019-10-30 Jan Beulich <jbeulich@suse.com>
631
632 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
633 of W.
634 * i386-opc.h (W): Extend comment.
635 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
636 general purpose variants not allowing for byte operands.
637 * i386-tbl.h: Re-generate.
638
efea62b4
NC		 6392019-10-29 Nick Clifton <nickc@redhat.com>
640
641 * tic30-dis.c (print_branch): Correct size of operand array.
642
9adb2591
NC		 6432019-10-29 Nick Clifton <nickc@redhat.com>
644
645 * d30v-dis.c (print_insn): Check that operand index is valid
646 before attempting to access the operands array.
647
993a00a9
NC		 6482019-10-29 Nick Clifton <nickc@redhat.com>
649
650 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
651 locating the bit to be tested.
652
66a66a17
NC		 6532019-10-29 Nick Clifton <nickc@redhat.com>
654
655 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
656 values.
657 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
658 (print_insn_s12z): Check for illegal size values.
659
1ee3542c
NC		 6602019-10-28 Nick Clifton <nickc@redhat.com>
661
662 * csky-dis.c (csky_chars_to_number): Check for a negative
663 count. Use an unsigned integer to construct the return value.
664
bbf9a0b5
NC		 6652019-10-28 Nick Clifton <nickc@redhat.com>
666
667 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
668 operand buffer. Set value to 15 not 13.
669 (get_register_operand): Use OPERAND_BUFFER_LEN.
670 (get_indirect_operand): Likewise.
671 (print_two_operand): Likewise.
672 (print_three_operand): Likewise.
673 (print_oar_insn): Likewise.
674
d1e304bc
NC		 6752019-10-28 Nick Clifton <nickc@redhat.com>
676
677 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
678 (bit_extract_simple): Likewise.
679 (bit_copy): Likewise.
680 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
681 index_offset array are not accessed.
682
dee33451
NC		 6832019-10-28 Nick Clifton <nickc@redhat.com>
684
685 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
686 operand.
687
27cee81d
NC		 6882019-10-25 Nick Clifton <nickc@redhat.com>
689
690 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
691 access to opcodes.op array element.
692
de6d8dc2
NC		 6932019-10-23 Nick Clifton <nickc@redhat.com>
694
695 * rx-dis.c (get_register_name): Fix spelling typo in error
696 message.
697 (get_condition_name, get_flag_name, get_double_register_name)
698 (get_double_register_high_name, get_double_register_low_name)
699 (get_double_control_register_name, get_double_condition_name)
700 (get_opsize_name, get_size_name): Likewise.
701
6207ed28
NC		 7022019-10-22 Nick Clifton <nickc@redhat.com>
703
704 * rx-dis.c (get_size_name): New function. Provides safe
705 access to name array.
706 (get_opsize_name): Likewise.
707 (print_insn_rx): Use the accessor functions.
708
12234dfd
NC		 7092019-10-16 Nick Clifton <nickc@redhat.com>
710
711 * rx-dis.c (get_register_name): New function. Provides safe
712 access to name array.
713 (get_condition_name, get_flag_name, get_double_register_name)
714 (get_double_register_high_name, get_double_register_low_name)
715 (get_double_control_register_name, get_double_condition_name):
716 Likewise.
717 (print_insn_rx): Use the accessor functions.
718
1d378749
NC		 7192019-10-09 Nick Clifton <nickc@redhat.com>
720
721 PR 25041
722 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
723 instructions.
724
d241b910
JB		 7252019-10-07 Jan Beulich <jbeulich@suse.com>
726
727 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
728 (cmpsd): Likewise. Move EsSeg to other operand.
729 * opcodes/i386-tbl.h: Re-generate.
730
f5c5b7c1
AM		 7312019-09-23 Alan Modra <amodra@gmail.com>
732
733 * m68k-dis.c: Include cpu-m68k.h
734
7beeaeb8
AM		 7352019-09-23 Alan Modra <amodra@gmail.com>
736
737 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
738 "elf/mips.h" earlier.
739
3f9aad11
JB		 7402018-09-20 Jan Beulich <jbeulich@suse.com>
741
742 PR gas/25012
743 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
744 with SReg operand.
745 * i386-tbl.h: Re-generate.
746
fd361982
AM		 7472019-09-18 Alan Modra <amodra@gmail.com>
748
749 * arc-ext.c: Update throughout for bfd section macro changes.
750
e0b2a78c
SM		 7512019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
752
753 * Makefile.in: Re-generate.
754 * configure: Re-generate.
755
7e9ad3a3
JW		 7562019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
757
758 * riscv-opc.c (riscv_opcodes): Change subset field
759 to insn_class field for all instructions.
760 (riscv_insn_types): Likewise.
761
bb695960
PB		 7622019-09-16 Phil Blundell <pb@pbcl.net>
763
764 * configure: Regenerated.
765
8063ab7e
MV		 7662019-09-10 Miod Vallat <miod@online.fr>
767
768 PR 24982
769 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
770
60391a25
PB		 7712019-09-09 Phil Blundell <pb@pbcl.net>
772
773 binutils 2.33 branch created.
774
f44b758d
NC		 7752019-09-03 Nick Clifton <nickc@redhat.com>
776
777 PR 24961
778 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
779 greater than zero before indexing via (bufcnt -1).
780
1e4b5e7d
NC		 7812019-09-03 Nick Clifton <nickc@redhat.com>
782
783 PR 24958
784 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
785 (MAX_SPEC_REG_NAME_LEN): Define.
786 (struct mmix_dis_info): Use defined constants for array lengths.
787 (get_reg_name): New function.
788 (get_sprec_reg_name): New function.
789 (print_insn_mmix): Use new functions.
790
c4a23bf8
SP		 7912019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
792
793 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
794 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
795 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
796
a051e2f3
KT		 7972019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
798
799 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
800 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
801 (aarch64_sys_reg_supported_p): Update checks for the above.
802
08132bdd
SP		 8032019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
804
805 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
806 cases MVE_SQRSHRL and MVE_UQRSHLL.
807 (print_insn_mve): Add case for specifier 'k' to check
808 specific bit of the instruction.
809
d88bdcb4
PA		 8102019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
811
812 PR 24854
813 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
814 encountering an unknown machine type.
815 (print_insn_arc): Handle arc_insn_length returning 0. In error
816 cases return -1 rather than calling abort.
817
bc750500
JB		 8182019-08-07 Jan Beulich <jbeulich@suse.com>
819
820 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
821 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
822 IgnoreSize.
823 * i386-tbl.h: Re-generate.
824
23d188c7
BW		 8252019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
826
827 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
828 instructions.
829
c0d6f62f
JW		 8302019-07-30 Mel Chen <mel.chen@sifive.com>
831
832 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
833 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
834
835 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
836 fscsr.
837
0f3f7167
CZ		 8382019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
839
840 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
841 and MPY class instructions.
842 (parse_option): Add nps400 option.
843 (print_arc_disassembler_options): Add nps400 info.
844
7e126ba3
CZ		 8452019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
846
847 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
848 (bspop): Likewise.
849 (modapp): Likewise.
850 * arc-opc.c (RAD_CHK): Add.
851 * arc-tbl.h: Regenerate.
852
a028026d
KT		 8532019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
854
855 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
856 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
857
ac79ff9e
NC		 8582019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
859
860 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
861 instructions as UNPREDICTABLE.
862
231097b0
JM		 8632019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
864
865 * bpf-desc.c: Regenerated.
866
1d942ae9
JB		 8672019-07-17 Jan Beulich <jbeulich@suse.com>
868
869 * i386-gen.c (static_assert): Define.
870 (main): Use it.
871 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
872 (Opcode_Modifier_Num): ... this.
873 (Mem): Delete.
874
dfd69174
JB		 8752019-07-16 Jan Beulich <jbeulich@suse.com>
876
877 * i386-gen.c (operand_types): Move RegMem ...
878 (opcode_modifiers): ... here.
879 * i386-opc.h (RegMem): Move to opcode modifer enum.
880 (union i386_operand_type): Move regmem field ...
881 (struct i386_opcode_modifier): ... here.
882 * i386-opc.tbl (RegMem): Define.
883 (mov, movq): Move RegMem on segment, control, debug, and test
884 register flavors.
885 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
886 to non-SSE2AVX flavor.
887 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
888 Move RegMem on register only flavors. Drop IgnoreSize from
889 legacy encoding flavors.
890 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
891 flavors.
892 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
893 register only flavors.
894 (vmovd): Move RegMem and drop IgnoreSize on register only
895 flavor. Change opcode and operand order to store form.
896 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
897
21df382b
JB		 8982019-07-16 Jan Beulich <jbeulich@suse.com>
899
900 * i386-gen.c (operand_type_init, operand_types): Replace SReg
901 entries.
902 * i386-opc.h (SReg2, SReg3): Replace by ...
903 (SReg): ... this.
904 (union i386_operand_type): Replace sreg fields.
905 * i386-opc.tbl (mov, ): Use SReg.
906 (push, pop): Likewies. Drop i386 and x86-64 specific segment
907 register flavors.
908 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
909 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
910
3719fd55
JM		 9112019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
912
913 * bpf-desc.c: Regenerate.
914 * bpf-opc.c: Likewise.
915 * bpf-opc.h: Likewise.
916
92434a14
JM		 9172019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
918
919 * bpf-desc.c: Regenerate.
920 * bpf-opc.c: Likewise.
921
43dd7626
HPN		 9222019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
923
924 * arm-dis.c (print_insn_coprocessor): Rename index to
925 index_operand.
926
98602811
JW		 9272019-07-05 Kito Cheng <kito.cheng@sifive.com>
928
929 * riscv-opc.c (riscv_insn_types): Add r4 type.
930
931 * riscv-opc.c (riscv_insn_types): Add b and j type.
932
933 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
934 format for sb type and correct s type.
935
01c1ee4a
RS		 9362019-07-02 Richard Sandiford <richard.sandiford@arm.com>
937
938 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
939 SVE FMOV alias of FCPY.
940
83adff69
RS		 9412019-07-02 Richard Sandiford <richard.sandiford@arm.com>
942
943 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
944 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
945
89418844
RS		 9462019-07-02 Richard Sandiford <richard.sandiford@arm.com>
947
948 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
949 registers in an instruction prefixed by MOVPRFX.
950
41be57ca
MM		 9512019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
952
953 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
954 sve_size_13 icode to account for variant behaviour of
955 pmull{t,b}.
956 * aarch64-dis-2.c: Regenerate.
957 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
958 sve_size_13 icode to account for variant behaviour of
959 pmull{t,b}.
960 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
961 (OP_SVE_VVV_Q_D): Add new qualifier.
962 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
963 (struct aarch64_opcode): Split pmull{t,b} into those requiring
964 AES and those not.
965
9d3bf266
JB		 9662019-07-01 Jan Beulich <jbeulich@suse.com>
967
968 * opcodes/i386-gen.c (operand_type_init): Remove
969 OPERAND_TYPE_VEC_IMM4 entry.
970 (operand_types): Remove Vec_Imm4.
971 * opcodes/i386-opc.h (Vec_Imm4): Delete.
972 (union i386_operand_type): Remove vec_imm4.
973 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
974 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
975
c3949f43
JB		 9762019-07-01 Jan Beulich <jbeulich@suse.com>
977
978 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
979 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
980 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
981 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
982 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
983 monitorx, mwaitx): Drop ImmExt from operand-less forms.
984 * i386-tbl.h: Re-generate.
985
5641ec01
JB		 9862019-07-01 Jan Beulich <jbeulich@suse.com>
987
988 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
989 register operands.
990 * i386-tbl.h: Re-generate.
991
79dec6b7
JB		 9922019-07-01 Jan Beulich <jbeulich@suse.com>
993
994 * i386-opc.tbl (C): New.
995 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
996 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
997 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
998 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
999 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1000 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1001 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1002 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1003 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1004 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1005 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1006 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1007 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1008 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1009 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1010 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1011 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1012 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1013 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1014 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1015 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1016 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1017 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1018 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1019 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1020 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1021 flavors.
1022 * i386-tbl.h: Re-generate.
1023
a0a1771e
JB		 10242019-07-01 Jan Beulich <jbeulich@suse.com>
1025
1026 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1027 register operands.
1028 * i386-tbl.h: Re-generate.
1029
cd546e7b
JB		 10302019-07-01 Jan Beulich <jbeulich@suse.com>
1031
1032 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1033 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1034 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1035 * i386-tbl.h: Re-generate.
1036
e3bba3fc
JB		 10372019-07-01 Jan Beulich <jbeulich@suse.com>
1038
1039 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1040 Disp8MemShift from register only templates.
1041 * i386-tbl.h: Re-generate.
1042
36cc073e
JB		 10432019-07-01 Jan Beulich <jbeulich@suse.com>
1044
1045 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1046 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1047 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1048 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1049 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1050 EVEX_W_0F11_P_3_M_1): Delete.
1051 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1052 EVEX_W_0F11_P_3): New.
1053 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1054 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1055 MOD_EVEX_0F11_PREFIX_3 table entries.
1056 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1057 PREFIX_EVEX_0F11 table entries.
1058 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1059 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1060 EVEX_W_0F11_P_3_M_{0,1} table entries.
1061
219920a7
JB		 10622019-07-01 Jan Beulich <jbeulich@suse.com>
1063
1064 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1065 Delete.
1066
e395f487
L		 10672019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1068
1069 PR binutils/24719
1070 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1071 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1072 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1073 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1074 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1075 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1076 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1077 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1078 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1079 PREFIX_EVEX_0F38C6_REG_6 entries.
1080 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1081 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1082 EVEX_W_0F38C7_R_6_P_2 entries.
1083 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1084 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1085 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1086 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1087 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1088 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1089 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1090
2b7bcc87
JB		 10912019-06-27 Jan Beulich <jbeulich@suse.com>
1092
1093 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1094 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1095 VEX_LEN_0F2D_P_3): Delete.
1096 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1097 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1098 (prefix_table): ... here.
1099
c1dc7af5
JB		 11002019-06-27 Jan Beulich <jbeulich@suse.com>
1101
1102 * i386-dis.c (Iq): Delete.
1103 (Id): New.
1104 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1105 TBM insns.
1106 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1107 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1108 (OP_E_memory): Also honor needindex when deciding whether an
1109 address size prefix needs printing.
1110 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1111
d7560e2d
JW		 11122019-06-26 Jim Wilson <jimw@sifive.com>
1113
1114 PR binutils/24739
1115 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1116 Set info->display_endian to info->endian_code.
1117
2c703856
JB		 11182019-06-25 Jan Beulich <jbeulich@suse.com>
1119
1120 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1121 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1122 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1123 OPERAND_TYPE_ACC64 entries.
1124 * i386-init.h: Re-generate.
1125
54fbadc0
JB		 11262019-06-25 Jan Beulich <jbeulich@suse.com>
1127
1128 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1129 Delete.
1130 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1131 of dqa_mode.
1132 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1133 entries here.
1134 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1135 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1136
a280ab8e
JB		 11372019-06-25 Jan Beulich <jbeulich@suse.com>
1138
1139 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1140 variables.
1141
e1a1babd
JB		 11422019-06-25 Jan Beulich <jbeulich@suse.com>
1143
1144 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1145 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1146 movnti.
d7560e2d 1147 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1148 * i386-tbl.h: Re-generate.
1149
b8364fa7
JB		 11502019-06-25 Jan Beulich <jbeulich@suse.com>
1151
1152 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1153 * i386-tbl.h: Re-generate.
1154
ad692897
L		 11552019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1156
1157 * i386-dis-evex.h: Break into ...
1158 * i386-dis-evex-len.h: New file.
1159 * i386-dis-evex-mod.h: Likewise.
1160 * i386-dis-evex-prefix.h: Likewise.
1161 * i386-dis-evex-reg.h: Likewise.
1162 * i386-dis-evex-w.h: Likewise.
1163 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1164 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1165 i386-dis-evex-mod.h.
1166
f0a6222e
L		 11672019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1168
1169 PR binutils/24700
1170 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1171 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1172 EVEX_W_0F385B_P_2.
1173 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1174 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1175 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1176 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1177 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1178 EVEX_LEN_0F385B_P_2_W_1.
1179 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1180 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1181 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1182 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1183 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1184 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1185 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1186 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1187 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1188 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1189
6e1c90b7
L		 11902019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1191
1192 PR binutils/24691
1193 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1194 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1195 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1196 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1197 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1198 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1199 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1200 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1201 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1202 EVEX_LEN_0F3A43_P_2_W_1.
1203 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1204 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1205 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1206 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1207 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1208 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1209 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1210 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1211 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1212 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1213 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1214 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1215
bcc5a6eb
NC		 12162019-06-14 Nick Clifton <nickc@redhat.com>
1217
1218 * po/fr.po; Updated French translation.
1219
e4c4ac46
SH		 12202019-06-13 Stafford Horne <shorne@gmail.com>
1221
1222 * or1k-asm.c: Regenerated.
1223 * or1k-desc.c: Regenerated.
1224 * or1k-desc.h: Regenerated.
1225 * or1k-dis.c: Regenerated.
1226 * or1k-ibld.c: Regenerated.
1227 * or1k-opc.c: Regenerated.
1228 * or1k-opc.h: Regenerated.
1229 * or1k-opinst.c: Regenerated.
1230
a0e44ef5
PB		 12312019-06-12 Peter Bergner <bergner@linux.ibm.com>
1232
1233 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1234
12efd68d
L		 12352019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1236
1237 PR binutils/24633
1238 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1239 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1240 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1241 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1242 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1243 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1244 EVEX_LEN_0F3A1B_P_2_W_1.
1245 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1246 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1247 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1248 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1249 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1250 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1251 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1252 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1253
63c6fc6c
L		 12542019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1255
1256 PR binutils/24626
1257 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1258 EVEX.vvvv when disassembling VEX and EVEX instructions.
1259 (OP_VEX): Set vex.register_specifier to 0 after readding
1260 vex.register_specifier.
1261 (OP_Vex_2src_1): Likewise.
1262 (OP_Vex_2src_2): Likewise.
1263 (OP_LWP_E): Likewise.
1264 (OP_EX_Vex): Don't check vex.register_specifier.
1265 (OP_XMM_Vex): Likewise.
1266
9186c494
L		 12672019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1268 Lili Cui <lili.cui@intel.com>
1269
1270 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1271 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1272 instructions.
1273 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1274 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1275 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1276 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1277 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1278 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1279 * i386-init.h: Regenerated.
1280 * i386-tbl.h: Likewise.
1281
5d79adc4
L		 12822019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1283 Lili Cui <lili.cui@intel.com>
1284
1285 * doc/c-i386.texi: Document enqcmd.
1286 * testsuite/gas/i386/enqcmd-intel.d: New file.
1287 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1288 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1289 * testsuite/gas/i386/enqcmd.d: Likewise.
1290 * testsuite/gas/i386/enqcmd.s: Likewise.
1291 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1292 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1293 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1294 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1295 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1296 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1297 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1298 and x86-64-enqcmd.
1299
a9d96ab9
AH		 13002019-06-04 Alan Hayward <alan.hayward@arm.com>
1301
1302 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1303
4f6d070a
AM		 13042019-06-03 Alan Modra <amodra@gmail.com>
1305
1306 * ppc-dis.c (prefix_opcd_indices): Correct size.
1307
a2f4b66c
L		 13082019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1309
1310 PR gas/24625
1311 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1312 Disp8ShiftVL.
1313 * i386-tbl.h: Regenerated.
1314
405b5bd8
AM		 13152019-05-24 Alan Modra <amodra@gmail.com>
1316
1317 * po/POTFILES.in: Regenerate.
1318
8acf1435
PB		 13192019-05-24 Peter Bergner <bergner@linux.ibm.com>
1320 Alan Modra <amodra@gmail.com>
1321
1322 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1323 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1324 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1325 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1326 XTOP>): Define and add entries.
1327 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1328 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1329 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1330 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1331
dd7efa79
PB		 13322019-05-24 Peter Bergner <bergner@linux.ibm.com>
1333 Alan Modra <amodra@gmail.com>
1334
1335 * ppc-dis.c (ppc_opts): Add "future" entry.
1336 (PREFIX_OPCD_SEGS): Define.
1337 (prefix_opcd_indices): New array.
1338 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1339 (lookup_prefix): New function.
1340 (print_insn_powerpc): Handle 64-bit prefix instructions.
1341 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1342 (PMRR, POWERXX): Define.
1343 (prefix_opcodes): New instruction table.
1344 (prefix_num_opcodes): New constant.
1345
79472b45
JM		 13462019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1347
1348 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1349 * configure: Regenerated.
1350 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1351 and cpu/bpf.opc.
1352 (HFILES): Add bpf-desc.h and bpf-opc.h.
1353 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1354 bpf-ibld.c and bpf-opc.c.
1355 (BPF_DEPS): Define.
1356 * Makefile.in: Regenerated.
1357 * disassemble.c (ARCH_bpf): Define.
1358 (disassembler): Add case for bfd_arch_bpf.
1359 (disassemble_init_for_target): Likewise.
1360 (enum epbf_isa_attr): Define.
1361 * disassemble.h: extern print_insn_bpf.
1362 * bpf-asm.c: Generated.
1363 * bpf-opc.h: Likewise.
1364 * bpf-opc.c: Likewise.
1365 * bpf-ibld.c: Likewise.
1366 * bpf-dis.c: Likewise.
1367 * bpf-desc.h: Likewise.
1368 * bpf-desc.c: Likewise.
1369
ba6cd17f
SD		 13702019-05-21 Sudakshina Das <sudi.das@arm.com>
1371
1372 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1373 and VMSR with the new operands.
1374
e39c1607
SD		 13752019-05-21 Sudakshina Das <sudi.das@arm.com>
1376
1377 * arm-dis.c (enum mve_instructions): New enum
1378 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1379 and cneg.
1380 (mve_opcodes): New instructions as above.
1381 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1382 csneg and csel.
1383 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1384
23d00a41
SD		 13852019-05-21 Sudakshina Das <sudi.das@arm.com>
1386
1387 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1388 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1389 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1390 uqshl, urshrl and urshr.
1391 (is_mve_okay_in_it): Add new instructions to TRUE list.
1392 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1393 (print_insn_mve): Updated to accept new %j,
1394 %<bitfield>m and %<bitfield>n patterns.
1395
cd4797ee
FS		 13962019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1397
1398 * mips-opc.c (mips_builtin_opcodes): Change source register
1399 constraint for DAUI.
1400
999b073b
NC		 14012019-05-20 Nick Clifton <nickc@redhat.com>
1402
1403 * po/fr.po: Updated French translation.
1404
14b456f2
AV		 14052019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1406 Michael Collison <michael.collison@arm.com>
1407
1408 * arm-dis.c (thumb32_opcodes): Add new instructions.
1409 (enum mve_instructions): Likewise.
1410 (enum mve_undefined): Add new reasons.
1411 (is_mve_encoding_conflict): Handle new instructions.
1412 (is_mve_undefined): Likewise.
1413 (is_mve_unpredictable): Likewise.
1414 (print_mve_undefined): Likewise.
1415 (print_mve_size): Likewise.
1416
f49bb598
AV		 14172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1418 Michael Collison <michael.collison@arm.com>
1419
1420 * arm-dis.c (thumb32_opcodes): Add new instructions.
1421 (enum mve_instructions): Likewise.
1422 (is_mve_encoding_conflict): Handle new instructions.
1423 (is_mve_undefined): Likewise.
1424 (is_mve_unpredictable): Likewise.
1425 (print_mve_size): Likewise.
1426
56858bea
AV		 14272019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1428 Michael Collison <michael.collison@arm.com>
1429
1430 * arm-dis.c (thumb32_opcodes): Add new instructions.
1431 (enum mve_instructions): Likewise.
1432 (is_mve_encoding_conflict): Likewise.
1433 (is_mve_unpredictable): Likewise.
1434 (print_mve_size): Likewise.
1435
e523f101
AV		 14362019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1437 Michael Collison <michael.collison@arm.com>
1438
1439 * arm-dis.c (thumb32_opcodes): Add new instructions.
1440 (enum mve_instructions): Likewise.
1441 (is_mve_encoding_conflict): Handle new instructions.
1442 (is_mve_undefined): Likewise.
1443 (is_mve_unpredictable): Likewise.
1444 (print_mve_size): Likewise.
1445
66dcaa5d
AV		 14462019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1447 Michael Collison <michael.collison@arm.com>
1448
1449 * arm-dis.c (thumb32_opcodes): Add new instructions.
1450 (enum mve_instructions): Likewise.
1451 (is_mve_encoding_conflict): Handle new instructions.
1452 (is_mve_undefined): Likewise.
1453 (is_mve_unpredictable): Likewise.
1454 (print_mve_size): Likewise.
1455 (print_insn_mve): Likewise.
1456
d052b9b7
AV		 14572019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1458 Michael Collison <michael.collison@arm.com>
1459
1460 * arm-dis.c (thumb32_opcodes): Add new instructions.
1461 (print_insn_thumb32): Handle new instructions.
1462
ed63aa17
AV		 14632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1464 Michael Collison <michael.collison@arm.com>
1465
1466 * arm-dis.c (enum mve_instructions): Add new instructions.
1467 (enum mve_undefined): Add new reasons.
1468 (is_mve_encoding_conflict): Handle new instructions.
1469 (is_mve_undefined): Likewise.
1470 (is_mve_unpredictable): Likewise.
1471 (print_mve_undefined): Likewise.
1472 (print_mve_size): Likewise.
1473 (print_mve_shift_n): Likewise.
1474 (print_insn_mve): Likewise.
1475
897b9bbc
AV		 14762019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1477 Michael Collison <michael.collison@arm.com>
1478
1479 * arm-dis.c (enum mve_instructions): Add new instructions.
1480 (is_mve_encoding_conflict): Handle new instructions.
1481 (is_mve_unpredictable): Likewise.
1482 (print_mve_rotate): Likewise.
1483 (print_mve_size): Likewise.
1484 (print_insn_mve): Likewise.
1485
1c8f2df8
AV		 14862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1487 Michael Collison <michael.collison@arm.com>
1488
1489 * arm-dis.c (enum mve_instructions): Add new instructions.
1490 (is_mve_encoding_conflict): Handle new instructions.
1491 (is_mve_unpredictable): Likewise.
1492 (print_mve_size): Likewise.
1493 (print_insn_mve): Likewise.
1494
d3b63143
AV		 14952019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1496 Michael Collison <michael.collison@arm.com>
1497
1498 * arm-dis.c (enum mve_instructions): Add new instructions.
1499 (enum mve_undefined): Add new reasons.
1500 (is_mve_encoding_conflict): Handle new instructions.
1501 (is_mve_undefined): Likewise.
1502 (is_mve_unpredictable): Likewise.
1503 (print_mve_undefined): Likewise.
1504 (print_mve_size): Likewise.
1505 (print_insn_mve): Likewise.
1506
14925797
AV		 15072019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1508 Michael Collison <michael.collison@arm.com>
1509
1510 * arm-dis.c (enum mve_instructions): Add new instructions.
1511 (is_mve_encoding_conflict): Handle new instructions.
1512 (is_mve_undefined): Likewise.
1513 (is_mve_unpredictable): Likewise.
1514 (print_mve_size): Likewise.
1515 (print_insn_mve): Likewise.
1516
c507f10b
AV		 15172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1518 Michael Collison <michael.collison@arm.com>
1519
1520 * arm-dis.c (enum mve_instructions): Add new instructions.
1521 (enum mve_unpredictable): Add new reasons.
1522 (enum mve_undefined): Likewise.
1523 (is_mve_okay_in_it): Handle new isntructions.
1524 (is_mve_encoding_conflict): Likewise.
1525 (is_mve_undefined): Likewise.
1526 (is_mve_unpredictable): Likewise.
1527 (print_mve_vmov_index): Likewise.
1528 (print_simd_imm8): Likewise.
1529 (print_mve_undefined): Likewise.
1530 (print_mve_unpredictable): Likewise.
1531 (print_mve_size): Likewise.
1532 (print_insn_mve): Likewise.
1533
bf0b396d
AV		 15342019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1535 Michael Collison <michael.collison@arm.com>
1536
1537 * arm-dis.c (enum mve_instructions): Add new instructions.
1538 (enum mve_unpredictable): Add new reasons.
1539 (enum mve_undefined): Likewise.
1540 (is_mve_encoding_conflict): Handle new instructions.
1541 (is_mve_undefined): Likewise.
1542 (is_mve_unpredictable): Likewise.
1543 (print_mve_undefined): Likewise.
1544 (print_mve_unpredictable): Likewise.
1545 (print_mve_rounding_mode): Likewise.
1546 (print_mve_vcvt_size): Likewise.
1547 (print_mve_size): Likewise.
1548 (print_insn_mve): Likewise.
1549
ef1576a1
AV		 15502019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1551 Michael Collison <michael.collison@arm.com>
1552
1553 * arm-dis.c (enum mve_instructions): Add new instructions.
1554 (enum mve_unpredictable): Add new reasons.
1555 (enum mve_undefined): Likewise.
1556 (is_mve_undefined): Handle new instructions.
1557 (is_mve_unpredictable): Likewise.
1558 (print_mve_undefined): Likewise.
1559 (print_mve_unpredictable): Likewise.
1560 (print_mve_size): Likewise.
1561 (print_insn_mve): Likewise.
1562
aef6d006
AV		 15632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1564 Michael Collison <michael.collison@arm.com>
1565
1566 * arm-dis.c (enum mve_instructions): Add new instructions.
1567 (enum mve_undefined): Add new reasons.
1568 (insns): Add new instructions.
1569 (is_mve_encoding_conflict):
1570 (print_mve_vld_str_addr): New print function.
1571 (is_mve_undefined): Handle new instructions.
1572 (is_mve_unpredictable): Likewise.
1573 (print_mve_undefined): Likewise.
1574 (print_mve_size): Likewise.
1575 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1576 (print_insn_mve): Handle new operands.
1577
04d54ace
AV		 15782019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1579 Michael Collison <michael.collison@arm.com>
1580
1581 * arm-dis.c (enum mve_instructions): Add new instructions.
1582 (enum mve_unpredictable): Add new reasons.
1583 (is_mve_encoding_conflict): Handle new instructions.
1584 (is_mve_unpredictable): Likewise.
1585 (mve_opcodes): Add new instructions.
1586 (print_mve_unpredictable): Handle new reasons.
1587 (print_mve_register_blocks): New print function.
1588 (print_mve_size): Handle new instructions.
1589 (print_insn_mve): Likewise.
1590
9743db03
AV		 15912019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1592 Michael Collison <michael.collison@arm.com>
1593
1594 * arm-dis.c (enum mve_instructions): Add new instructions.
1595 (enum mve_unpredictable): Add new reasons.
1596 (enum mve_undefined): Likewise.
1597 (is_mve_encoding_conflict): Handle new instructions.
1598 (is_mve_undefined): Likewise.
1599 (is_mve_unpredictable): Likewise.
1600 (coprocessor_opcodes): Move NEON VDUP from here...
1601 (neon_opcodes): ... to here.
1602 (mve_opcodes): Add new instructions.
1603 (print_mve_undefined): Handle new reasons.
1604 (print_mve_unpredictable): Likewise.
1605 (print_mve_size): Handle new instructions.
1606 (print_insn_neon): Handle vdup.
1607 (print_insn_mve): Handle new operands.
1608
143275ea
AV		 16092019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1610 Michael Collison <michael.collison@arm.com>
1611
1612 * arm-dis.c (enum mve_instructions): Add new instructions.
1613 (enum mve_unpredictable): Add new values.
1614 (mve_opcodes): Add new instructions.
1615 (vec_condnames): New array with vector conditions.
1616 (mve_predicatenames): New array with predicate suffixes.
1617 (mve_vec_sizename): New array with vector sizes.
1618 (enum vpt_pred_state): New enum with vector predication states.
1619 (struct vpt_block): New struct type for vpt blocks.
1620 (vpt_block_state): Global struct to keep track of state.
1621 (mve_extract_pred_mask): New helper function.
1622 (num_instructions_vpt_block): Likewise.
1623 (mark_outside_vpt_block): Likewise.
1624 (mark_inside_vpt_block): Likewise.
1625 (invert_next_predicate_state): Likewise.
1626 (update_next_predicate_state): Likewise.
1627 (update_vpt_block_state): Likewise.
1628 (is_vpt_instruction): Likewise.
1629 (is_mve_encoding_conflict): Add entries for new instructions.
1630 (is_mve_unpredictable): Likewise.
1631 (print_mve_unpredictable): Handle new cases.
1632 (print_instruction_predicate): Likewise.
1633 (print_mve_size): New function.
1634 (print_vec_condition): New function.
1635 (print_insn_mve): Handle vpt blocks and new print operands.
1636
f08d8ce3
AV		 16372019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1638
1639 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1640 8, 14 and 15 for Armv8.1-M Mainline.
1641
73cd51e5
AV		 16422019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1643 Michael Collison <michael.collison@arm.com>
1644
1645 * arm-dis.c (enum mve_instructions): New enum.
1646 (enum mve_unpredictable): Likewise.
1647 (enum mve_undefined): Likewise.
1648 (struct mopcode32): New struct.
1649 (is_mve_okay_in_it): New function.
1650 (is_mve_architecture): Likewise.
1651 (arm_decode_field): Likewise.
1652 (arm_decode_field_multiple): Likewise.
1653 (is_mve_encoding_conflict): Likewise.
1654 (is_mve_undefined): Likewise.
1655 (is_mve_unpredictable): Likewise.
1656 (print_mve_undefined): Likewise.
1657 (print_mve_unpredictable): Likewise.
1658 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1659 (print_insn_mve): New function.
1660 (print_insn_thumb32): Handle MVE architecture.
1661 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1662
3076e594
NC		 16632019-05-10 Nick Clifton <nickc@redhat.com>
1664
1665 PR 24538
1666 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1667 end of the table prematurely.
1668
387e7624
FS		 16692019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1670
1671 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1672 macros for R6.
1673
0067be51
AM		 16742019-05-11 Alan Modra <amodra@gmail.com>
1675
1676 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1677 when -Mraw is in effect.
1678
42e6288f
MM		 16792019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1680
1681 * aarch64-dis-2.c: Regenerate.
1682 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1683 (OP_SVE_BBB): New variant set.
1684 (OP_SVE_DDDD): New variant set.
1685 (OP_SVE_HHH): New variant set.
1686 (OP_SVE_HHHU): New variant set.
1687 (OP_SVE_SSS): New variant set.
1688 (OP_SVE_SSSU): New variant set.
1689 (OP_SVE_SHH): New variant set.
1690 (OP_SVE_SBBU): New variant set.
1691 (OP_SVE_DSS): New variant set.
1692 (OP_SVE_DHHU): New variant set.
1693 (OP_SVE_VMV_HSD_BHS): New variant set.
1694 (OP_SVE_VVU_HSD_BHS): New variant set.
1695 (OP_SVE_VVVU_SD_BH): New variant set.
1696 (OP_SVE_VVVU_BHSD): New variant set.
1697 (OP_SVE_VVV_QHD_DBS): New variant set.
1698 (OP_SVE_VVV_HSD_BHS): New variant set.
1699 (OP_SVE_VVV_HSD_BHS2): New variant set.
1700 (OP_SVE_VVV_BHS_HSD): New variant set.
1701 (OP_SVE_VV_BHS_HSD): New variant set.
1702 (OP_SVE_VVV_SD): New variant set.
1703 (OP_SVE_VVU_BHS_HSD): New variant set.
1704 (OP_SVE_VZVV_SD): New variant set.
1705 (OP_SVE_VZVV_BH): New variant set.
1706 (OP_SVE_VZV_SD): New variant set.
1707 (aarch64_opcode_table): Add sve2 instructions.
1708
28ed815a
MM		 17092019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1710
1711 * aarch64-asm-2.c: Regenerated.
1712 * aarch64-dis-2.c: Regenerated.
1713 * aarch64-opc-2.c: Regenerated.
1714 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1715 for SVE_SHLIMM_UNPRED_22.
1716 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1717 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1718 operand.
1719
fd1dc4a0
MM		 17202019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1721
1722 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1723 sve_size_tsz_bhs iclass encode.
1724 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1725 sve_size_tsz_bhs iclass decode.
1726
31e36ab3
MM		 17272019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1728
1729 * aarch64-asm-2.c: Regenerated.
1730 * aarch64-dis-2.c: Regenerated.
1731 * aarch64-opc-2.c: Regenerated.
1732 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1733 for SVE_Zm4_11_INDEX.
1734 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1735 (fields): Handle SVE_i2h field.
1736 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1737 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1738
1be5f94f
MM		 17392019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1740
1741 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1742 sve_shift_tsz_bhsd iclass encode.
1743 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1744 sve_shift_tsz_bhsd iclass decode.
1745
3c17238b
MM		 17462019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1747
1748 * aarch64-asm-2.c: Regenerated.
1749 * aarch64-dis-2.c: Regenerated.
1750 * aarch64-opc-2.c: Regenerated.
1751 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1752 (aarch64_encode_variant_using_iclass): Handle
1753 sve_shift_tsz_hsd iclass encode.
1754 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1755 sve_shift_tsz_hsd iclass decode.
1756 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1757 for SVE_SHRIMM_UNPRED_22.
1758 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1759 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1760 operand.
1761
cd50a87a
MM		 17622019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1763
1764 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1765 sve_size_013 iclass encode.
1766 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1767 sve_size_013 iclass decode.
1768
3c705960
MM		 17692019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1770
1771 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1772 sve_size_bh iclass encode.
1773 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1774 sve_size_bh iclass decode.
1775
0a57e14f
MM		 17762019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1777
1778 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1779 sve_size_sd2 iclass encode.
1780 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1781 sve_size_sd2 iclass decode.
1782 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1783 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1784
c469c864
MM		 17852019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1786
1787 * aarch64-asm-2.c: Regenerated.
1788 * aarch64-dis-2.c: Regenerated.
1789 * aarch64-opc-2.c: Regenerated.
1790 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1791 for SVE_ADDR_ZX.
1792 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1793 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1794
116adc27
MM		 17952019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1796
1797 * aarch64-asm-2.c: Regenerated.
1798 * aarch64-dis-2.c: Regenerated.
1799 * aarch64-opc-2.c: Regenerated.
1800 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1801 for SVE_Zm3_11_INDEX.
1802 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1803 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1804 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1805 fields.
1806 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1807
3bd82c86
MM		 18082019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1809
1810 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1811 sve_size_hsd2 iclass encode.
1812 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1813 sve_size_hsd2 iclass decode.
1814 * aarch64-opc.c (fields): Handle SVE_size field.
1815 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1816
adccc507
MM		 18172019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1818
1819 * aarch64-asm-2.c: Regenerated.
1820 * aarch64-dis-2.c: Regenerated.
1821 * aarch64-opc-2.c: Regenerated.
1822 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1823 for SVE_IMM_ROT3.
1824 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1825 (fields): Handle SVE_rot3 field.
1826 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1827 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1828
5cd99750
MM		 18292019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1830
1831 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1832 instructions.
1833
7ce2460a
MM		 18342019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1835
1836 * aarch64-tbl.h
1837 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1838 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1839 aarch64_feature_sve2bitperm): New feature sets.
1840 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1841 for feature set addresses.
1842 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1843 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1844
41cee089
FS		 18452019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1846 Faraz Shahbazker <fshahbazker@wavecomp.com>
1847
1848 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1849 argument and set ASE_EVA_R6 appropriately.
1850 (set_default_mips_dis_options): Pass ISA to above.
1851 (parse_mips_dis_option): Likewise.
1852 * mips-opc.c (EVAR6): New macro.
1853 (mips_builtin_opcodes): Add llwpe, scwpe.
1854
b83b4b13
SD		 18552019-05-01 Sudakshina Das <sudi.das@arm.com>
1856
1857 * aarch64-asm-2.c: Regenerated.
1858 * aarch64-dis-2.c: Regenerated.
1859 * aarch64-opc-2.c: Regenerated.
1860 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1861 AARCH64_OPND_TME_UIMM16.
1862 (aarch64_print_operand): Likewise.
1863 * aarch64-tbl.h (QL_IMM_NIL): New.
1864 (TME): New.
1865 (_TME_INSN): New.
1866 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1867
4a90ce95
JD		 18682019-04-29 John Darrington <john@darrington.wattle.id.au>
1869
1870 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1871
a45328b9
AB		 18722019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1873 Faraz Shahbazker <fshahbazker@wavecomp.com>
1874
1875 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1876
d10be0cb
JD		 18772019-04-24 John Darrington <john@darrington.wattle.id.au>
1878
1879 * s12z-opc.h: Add extern "C" bracketing to help
1880 users who wish to use this interface in c++ code.
1881
a679f24e
JD		 18822019-04-24 John Darrington <john@darrington.wattle.id.au>
1883
1884 * s12z-opc.c (bm_decode): Handle bit map operations with the
1885 "reserved0" mode.
1886
32c36c3c
AV		 18872019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1888
1889 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1890 specifier. Add entries for VLDR and VSTR of system registers.
1891 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1892 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1893 of %J and %K format specifier.
1894
efd6b359
AV		 18952019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1896
1897 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1898 Add new entries for VSCCLRM instruction.
1899 (print_insn_coprocessor): Handle new %C format control code.
1900
6b0dd094
AV		 19012019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1902
1903 * arm-dis.c (enum isa): New enum.
1904 (struct sopcode32): New structure.
1905 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1906 set isa field of all current entries to ANY.
1907 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1908 Only match an entry if its isa field allows the current mode.
1909
4b5a202f
AV		 19102019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1911
1912 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1913 CLRM.
1914 (print_insn_thumb32): Add logic to print %n CLRM register list.
1915
60f993ce
AV		 19162019-04-15 Sudakshina Das <sudi.das@arm.com>
1917
1918 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1919 and %Q patterns.
1920
f6b2b12d
AV		 19212019-04-15 Sudakshina Das <sudi.das@arm.com>
1922
1923 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1924 (print_insn_thumb32): Edit the switch case for %Z.
1925
1889da70
AV		 19262019-04-15 Sudakshina Das <sudi.das@arm.com>
1927
1928 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1929
65d1bc05
AV		 19302019-04-15 Sudakshina Das <sudi.das@arm.com>
1931
1932 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1933
1caf72a5
AV		 19342019-04-15 Sudakshina Das <sudi.das@arm.com>
1935
1936 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1937
f1c7f421
AV		 19382019-04-15 Sudakshina Das <sudi.das@arm.com>
1939
1940 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1941 Arm register with r13 and r15 unpredictable.
1942 (thumb32_opcodes): New instructions for bfx and bflx.
1943
4389b29a
AV		 19442019-04-15 Sudakshina Das <sudi.das@arm.com>
1945
1946 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1947
e5d6e09e
AV		 19482019-04-15 Sudakshina Das <sudi.das@arm.com>
1949
1950 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1951
e12437dc
AV		 19522019-04-15 Sudakshina Das <sudi.das@arm.com>
1953
1954 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1955
031254f2
AV		 19562019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1957
1958 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1959
e5a557ac
JD		 19602019-04-12 John Darrington <john@darrington.wattle.id.au>
1961
1962 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1963 "optr". ("operator" is a reserved word in c++).
1964
bd7ceb8d
SD		 19652019-04-11 Sudakshina Das <sudi.das@arm.com>
1966
1967 * aarch64-opc.c (aarch64_print_operand): Add case for
1968 AARCH64_OPND_Rt_SP.
1969 (verify_constraints): Likewise.
1970 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1971 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1972 to accept Rt|SP as first operand.
1973 (AARCH64_OPERANDS): Add new Rt_SP.
1974 * aarch64-asm-2.c: Regenerated.
1975 * aarch64-dis-2.c: Regenerated.
1976 * aarch64-opc-2.c: Regenerated.
1977
e54010f1
SD		 19782019-04-11 Sudakshina Das <sudi.das@arm.com>
1979
1980 * aarch64-asm-2.c: Regenerated.
1981 * aarch64-dis-2.c: Likewise.
1982 * aarch64-opc-2.c: Likewise.
1983 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1984
7e96e219
RS		 19852019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1986
1987 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1988
6f2791d5
L		 19892019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1990
1991 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1992 * i386-init.h: Regenerated.
1993
e392bad3
AM		 19942019-04-07 Alan Modra <amodra@gmail.com>
1995
1996 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1997 op_separator to control printing of spaces, comma and parens
1998 rather than need_comma, need_paren and spaces vars.
1999
dffaa15c
AM		 20002019-04-07 Alan Modra <amodra@gmail.com>
2001
2002 PR 24421
2003 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2004 (print_insn_neon, print_insn_arm): Likewise.
2005
d6aab7a1
XG		 20062019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2007
2008 * i386-dis-evex.h (evex_table): Updated to support BF16
2009 instructions.
2010 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2011 and EVEX_W_0F3872_P_3.
2012 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2013 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2014 * i386-opc.h (enum): Add CpuAVX512_BF16.
2015 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2016 * i386-opc.tbl: Add AVX512 BF16 instructions.
2017 * i386-init.h: Regenerated.
2018 * i386-tbl.h: Likewise.
2019
66e85460
AM		 20202019-04-05 Alan Modra <amodra@gmail.com>
2021
2022 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2023 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2024 to favour printing of "-" branch hint when using the "y" bit.
2025 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2026
c2b1c275
AM		 20272019-04-05 Alan Modra <amodra@gmail.com>
2028
2029 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2030 opcode until first operand is output.
2031
aae9718e
PB		 20322019-04-04 Peter Bergner <bergner@linux.ibm.com>
2033
2034 PR gas/24349
2035 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2036 (valid_bo_post_v2): Add support for 'at' branch hints.
2037 (insert_bo): Only error on branch on ctr.
2038 (get_bo_hint_mask): New function.
2039 (insert_boe): Add new 'branch_taken' formal argument. Add support
2040 for inserting 'at' branch hints.
2041 (extract_boe): Add new 'branch_taken' formal argument. Add support
2042 for extracting 'at' branch hints.
2043 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2044 (BOE): Delete operand.
2045 (BOM, BOP): New operands.
2046 (RM): Update value.
2047 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2048 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2049 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2050 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2051 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2052 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2053 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2054 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2055 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2056 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2057 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2058 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2059 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2060 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2061 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2062 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2063 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2064 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2065 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2066 bttarl+>: New extended mnemonics.
2067
96a86c01
AM		 20682019-03-28 Alan Modra <amodra@gmail.com>
2069
2070 PR 24390
2071 * ppc-opc.c (BTF): Define.
2072 (powerpc_opcodes): Use for mtfsb*.
2073 * ppc-dis.c (print_insn_powerpc): Print fields with both
2074 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2075
796d6298
TC		 20762019-03-25 Tamar Christina <tamar.christina@arm.com>
2077
2078 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2079 (mapping_symbol_for_insn): Implement new algorithm.
2080 (print_insn): Remove duplicate code.
2081
60df3720
TC		 20822019-03-25 Tamar Christina <tamar.christina@arm.com>
2083
2084 * aarch64-dis.c (print_insn_aarch64):
2085 Implement override.
2086
51457761
TC		 20872019-03-25 Tamar Christina <tamar.christina@arm.com>
2088
2089 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2090 order.
2091
53b2f36b
TC		 20922019-03-25 Tamar Christina <tamar.christina@arm.com>
2093
2094 * aarch64-dis.c (last_stop_offset): New.
2095 (print_insn_aarch64): Use stop_offset.
2096
89199bb5
L		 20972019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2098
2099 PR gas/24359
2100 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2101 CPU_ANY_AVX2_FLAGS.
2102 * i386-init.h: Regenerated.
2103
97ed31ae
L		 21042019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2105
2106 PR gas/24348
2107 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2108 vmovdqu16, vmovdqu32 and vmovdqu64.
2109 * i386-tbl.h: Regenerated.
2110
0919bfe9
AK		 21112019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2112
2113 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2114 from vstrszb, vstrszh, and vstrszf.
2115
21162019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2117
2118 * s390-opc.txt: Add instruction descriptions.
2119
21820ebe
JW		 21202019-02-08 Jim Wilson <jimw@sifive.com>
2121
2122 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2123 <bne>: Likewise.
2124
f7dd2fb2
TC		 21252019-02-07 Tamar Christina <tamar.christina@arm.com>
2126
2127 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2128
6456d318
TC		 21292019-02-07 Tamar Christina <tamar.christina@arm.com>
2130
2131 PR binutils/23212
2132 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2133 * aarch64-opc.c (verify_elem_sd): New.
2134 (fields): Add FLD_sz entr.
2135 * aarch64-tbl.h (_SIMD_INSN): New.
2136 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2137 fmulx scalar and vector by element isns.
2138
4a83b610
NC		 21392019-02-07 Nick Clifton <nickc@redhat.com>
2140
2141 * po/sv.po: Updated Swedish translation.
2142
fc60b8c8
AK		 21432019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2144
2145 * s390-mkopc.c (main): Accept arch13 as cpu string.
2146 * s390-opc.c: Add new instruction formats and instruction opcode
2147 masks.
2148 * s390-opc.txt: Add new arch13 instructions.
2149
e10620d3
TC		 21502019-01-25 Sudakshina Das <sudi.das@arm.com>
2151
2152 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2153 (aarch64_opcode): Change encoding for stg, stzg
2154 st2g and st2zg.
2155 * aarch64-asm-2.c: Regenerated.
2156 * aarch64-dis-2.c: Regenerated.
2157 * aarch64-opc-2.c: Regenerated.
2158
20a4ca55
SD		 21592019-01-25 Sudakshina Das <sudi.das@arm.com>
2160
2161 * aarch64-asm-2.c: Regenerated.
2162 * aarch64-dis-2.c: Likewise.
2163 * aarch64-opc-2.c: Likewise.
2164 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2165
550fd7bf
SD		 21662019-01-25 Sudakshina Das <sudi.das@arm.com>
2167 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2168
2169 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2170 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2171 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2172 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2173 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2174 case for ldstgv_indexed.
2175 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2176 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2177 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2178 * aarch64-asm-2.c: Regenerated.
2179 * aarch64-dis-2.c: Regenerated.
2180 * aarch64-opc-2.c: Regenerated.
2181
d9938630
NC		 21822019-01-23 Nick Clifton <nickc@redhat.com>
2183
2184 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2185
375cd423
NC		 21862019-01-21 Nick Clifton <nickc@redhat.com>
2187
2188 * po/de.po: Updated German translation.
2189 * po/uk.po: Updated Ukranian translation.
2190
57299f48
CX		 21912019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2192 * mips-dis.c (mips_arch_choices): Fix typo in
2193 gs464, gs464e and gs264e descriptors.
2194
f48dfe41
NC		 21952019-01-19 Nick Clifton <nickc@redhat.com>
2196
2197 * configure: Regenerate.
2198 * po/opcodes.pot: Regenerate.
2199
f974f26c
NC		 22002018-06-24 Nick Clifton <nickc@redhat.com>
2201
2202 2.32 branch created.
2203
39f286cd
JD		 22042019-01-09 John Darrington <john@darrington.wattle.id.au>
2205
448b8ca8
JD		 2206 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2207 if it is null.
2208 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2209 zero.
2210
3107326d
AP		 22112019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2212
2213 * configure: Regenerate.
2214
7e9ca91e
AM		 22152019-01-07 Alan Modra <amodra@gmail.com>
2216
2217 * configure: Regenerate.
2218 * po/POTFILES.in: Regenerate.
2219
ef1ad42b
JD		 22202019-01-03 John Darrington <john@darrington.wattle.id.au>
2221
2222 * s12z-opc.c: New file.
2223 * s12z-opc.h: New file.
2224 * s12z-dis.c: Removed all code not directly related to display
2225 of instructions. Used the interface provided by the new files
2226 instead.
2227 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2228 * Makefile.in: Regenerate.
ef1ad42b 2229 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2230 * configure: Regenerate.
ef1ad42b 2231
82704155
AM		 22322019-01-01 Alan Modra <amodra@gmail.com>
2233
2234 Update year range in copyright notice of all files.
2235
d5c04e1b 2236For older changes see ChangeLog-2018
3499769a 2237\f
d5c04e1b 2238Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2239
2240Copying and distribution of this file, with or without modification,
2241are permitted in any medium without royalty provided the copyright
2242notice and this notice are preserved.
2243
2244Local Variables:
2245mode: change-log
2246left-margin: 8
2247fill-column: 74
2248version-control: never
2249End:
GDB Binutils - Deliverables
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