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perf/x86/intel: Enforce HT bug workaround with PEBS for SNB/IVB/HSW
[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_event_intel.c
CommitLineData
a7e3ed1e 1/*
efc9f05d
SE		 2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
a7e3ed1e 6 */
de0428a7 7
c767a54b
JP		 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
de0428a7
KW		 10#include <linux/stddef.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
69c60c88 14#include <linux/export.h>
de0428a7 15
3a632cb2 16#include <asm/cpufeature.h>
de0428a7
KW		 17#include <asm/hardirq.h>
18#include <asm/apic.h>
19
20#include "perf_event.h"
a7e3ed1e 21
f22f54f4 22/*
b622d644 23 * Intel PerfMon, used on Core and later.
f22f54f4 24 */
ec75a716 25static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4 26{
c3b7cdf1
PE		 27 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
28 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
29 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
30 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
31 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
32 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
33 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
34 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
f22f54f4
PZ		 35};
36
5c543e3c 37static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 38{
39 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
40 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
41 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
42 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
43 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
44 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
45 EVENT_CONSTRAINT_END
46};
47
5c543e3c 48static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 49{
b622d644
PZ		 50 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
51 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 52 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 53 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
54 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
55 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
56 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
57 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
58 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
59 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
60 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 61 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 62 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
63 EVENT_CONSTRAINT_END
64};
65
5c543e3c 66static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 67{
b622d644
PZ		 68 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
69 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 70 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 71 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
72 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
73 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
74 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
75 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
76 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
77 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
78 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
79 EVENT_CONSTRAINT_END
80};
81
5c543e3c 82static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 83{
53ad0447
YZ		 84 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
85 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
f20093ee 86 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 87 EVENT_EXTRA_END
88};
89
5c543e3c 90static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 91{
b622d644
PZ		 92 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
93 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 94 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 95 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
96 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
97 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 98 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 99 EVENT_CONSTRAINT_END
100};
101
5c543e3c 102static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 103{
104 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
105 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 106 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
fd4a5aef
SE		 107 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
108 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
109 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
110 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
b06b3d49 111 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
b06b3d49
LM		 112 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
113 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
f8378f52
AK		 114 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
115 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
93fcf72c
MD		 116
117 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
118 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
119 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
120 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
121
b06b3d49
LM		 122 EVENT_CONSTRAINT_END
123};
124
69943182
SE		 125static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
126{
127 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
128 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
129 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
130 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
131 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
132 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
6113af14 133 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
69943182
SE		 134 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
135 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
136 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
137 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
138 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
139 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
93fcf72c
MD		 140
141 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
142 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
143 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
144 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
145
69943182
SE		 146 EVENT_CONSTRAINT_END
147};
148
5c543e3c 149static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 150{
53ad0447
YZ		 151 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
152 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
153 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
f20093ee 154 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 155 EVENT_EXTRA_END
156};
157
0af3ac1f
AK		 158static struct event_constraint intel_v1_event_constraints[] __read_mostly =
159{
160 EVENT_CONSTRAINT_END
161};
162
5c543e3c 163static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 164{
b622d644
PZ		 165 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
166 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 167 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 168 EVENT_CONSTRAINT_END
169};
170
1fa64180
YZ		 171static struct event_constraint intel_slm_event_constraints[] __read_mostly =
172{
173 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
174 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
1fa64180
YZ		 175 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
176 EVENT_CONSTRAINT_END
177};
178
ee89cbc2 179static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
53ad0447
YZ		 180 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
181 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
182 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
f20093ee 183 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
f1923820
SE		 184 EVENT_EXTRA_END
185};
186
187static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
53ad0447
YZ		 188 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
189 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
190 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
f1a52789 191 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
ee89cbc2
SE		 192 EVENT_EXTRA_END
193};
194
7f2ee91f
IM		 195EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
196EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
197EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
f20093ee
SE		 198
199struct attribute *nhm_events_attrs[] = {
200 EVENT_PTR(mem_ld_nhm),
201 NULL,
202};
203
204struct attribute *snb_events_attrs[] = {
205 EVENT_PTR(mem_ld_snb),
9ad64c0f 206 EVENT_PTR(mem_st_snb),
f20093ee
SE		 207 NULL,
208};
209
3a632cb2
AK		 210static struct event_constraint intel_hsw_event_constraints[] = {
211 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
212 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
213 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
214 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
215 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
216 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
217 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
c420f19b 218 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
3a632cb2 219 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
c420f19b 220 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
3a632cb2 221 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
c420f19b 222 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
93fcf72c
MD		 223
224 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
225 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
226 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
227 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
228
3a632cb2
AK		 229 EVENT_CONSTRAINT_END
230};
231
91f1b705
AK		 232struct event_constraint intel_bdw_event_constraints[] = {
233 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
234 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
235 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
236 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
237 INTEL_EVENT_CONSTRAINT(0xa3, 0x4), /* CYCLE_ACTIVITY.* */
238 EVENT_CONSTRAINT_END
239};
240
f22f54f4
PZ		 241static u64 intel_pmu_event_map(int hw_event)
242{
243 return intel_perfmon_event_map[hw_event];
244}
245
74e6543f
YZ		 246#define SNB_DMND_DATA_RD (1ULL << 0)
247#define SNB_DMND_RFO (1ULL << 1)
248#define SNB_DMND_IFETCH (1ULL << 2)
249#define SNB_DMND_WB (1ULL << 3)
250#define SNB_PF_DATA_RD (1ULL << 4)
251#define SNB_PF_RFO (1ULL << 5)
252#define SNB_PF_IFETCH (1ULL << 6)
253#define SNB_LLC_DATA_RD (1ULL << 7)
254#define SNB_LLC_RFO (1ULL << 8)
255#define SNB_LLC_IFETCH (1ULL << 9)
256#define SNB_BUS_LOCKS (1ULL << 10)
257#define SNB_STRM_ST (1ULL << 11)
258#define SNB_OTHER (1ULL << 15)
259#define SNB_RESP_ANY (1ULL << 16)
260#define SNB_NO_SUPP (1ULL << 17)
261#define SNB_LLC_HITM (1ULL << 18)
262#define SNB_LLC_HITE (1ULL << 19)
263#define SNB_LLC_HITS (1ULL << 20)
264#define SNB_LLC_HITF (1ULL << 21)
265#define SNB_LOCAL (1ULL << 22)
266#define SNB_REMOTE (0xffULL << 23)
267#define SNB_SNP_NONE (1ULL << 31)
268#define SNB_SNP_NOT_NEEDED (1ULL << 32)
269#define SNB_SNP_MISS (1ULL << 33)
270#define SNB_NO_FWD (1ULL << 34)
271#define SNB_SNP_FWD (1ULL << 35)
272#define SNB_HITM (1ULL << 36)
273#define SNB_NON_DRAM (1ULL << 37)
274
275#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
276#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
277#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
278
279#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
280 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
281 SNB_HITM)
282
283#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
284#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
285
286#define SNB_L3_ACCESS SNB_RESP_ANY
287#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
288
289static __initconst const u64 snb_hw_cache_extra_regs
290 [PERF_COUNT_HW_CACHE_MAX]
291 [PERF_COUNT_HW_CACHE_OP_MAX]
292 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
293{
294 [ C(LL ) ] = {
295 [ C(OP_READ) ] = {
296 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
297 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
298 },
299 [ C(OP_WRITE) ] = {
300 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
301 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
302 },
303 [ C(OP_PREFETCH) ] = {
304 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
305 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
306 },
307 },
308 [ C(NODE) ] = {
309 [ C(OP_READ) ] = {
310 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
311 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
312 },
313 [ C(OP_WRITE) ] = {
314 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
315 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
316 },
317 [ C(OP_PREFETCH) ] = {
318 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
319 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
320 },
321 },
322};
323
b06b3d49
LM		 324static __initconst const u64 snb_hw_cache_event_ids
325 [PERF_COUNT_HW_CACHE_MAX]
326 [PERF_COUNT_HW_CACHE_OP_MAX]
327 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
328{
329 [ C(L1D) ] = {
330 [ C(OP_READ) ] = {
331 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
332 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
333 },
334 [ C(OP_WRITE) ] = {
335 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
336 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
337 },
338 [ C(OP_PREFETCH) ] = {
339 [ C(RESULT_ACCESS) ] = 0x0,
340 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
341 },
342 },
343 [ C(L1I ) ] = {
344 [ C(OP_READ) ] = {
345 [ C(RESULT_ACCESS) ] = 0x0,
346 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
347 },
348 [ C(OP_WRITE) ] = {
349 [ C(RESULT_ACCESS) ] = -1,
350 [ C(RESULT_MISS) ] = -1,
351 },
352 [ C(OP_PREFETCH) ] = {
353 [ C(RESULT_ACCESS) ] = 0x0,
354 [ C(RESULT_MISS) ] = 0x0,
355 },
356 },
357 [ C(LL ) ] = {
b06b3d49 358 [ C(OP_READ) ] = {
63b6a675 359 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 360 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 361 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
362 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 363 },
364 [ C(OP_WRITE) ] = {
63b6a675 365 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 366 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 367 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
368 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 369 },
370 [ C(OP_PREFETCH) ] = {
63b6a675 371 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 372 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 373 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
374 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 375 },
376 },
377 [ C(DTLB) ] = {
378 [ C(OP_READ) ] = {
379 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
380 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
381 },
382 [ C(OP_WRITE) ] = {
383 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
384 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
385 },
386 [ C(OP_PREFETCH) ] = {
387 [ C(RESULT_ACCESS) ] = 0x0,
388 [ C(RESULT_MISS) ] = 0x0,
389 },
390 },
391 [ C(ITLB) ] = {
392 [ C(OP_READ) ] = {
393 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
394 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
395 },
396 [ C(OP_WRITE) ] = {
397 [ C(RESULT_ACCESS) ] = -1,
398 [ C(RESULT_MISS) ] = -1,
399 },
400 [ C(OP_PREFETCH) ] = {
401 [ C(RESULT_ACCESS) ] = -1,
402 [ C(RESULT_MISS) ] = -1,
403 },
404 },
405 [ C(BPU ) ] = {
406 [ C(OP_READ) ] = {
407 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
408 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
409 },
410 [ C(OP_WRITE) ] = {
411 [ C(RESULT_ACCESS) ] = -1,
412 [ C(RESULT_MISS) ] = -1,
413 },
414 [ C(OP_PREFETCH) ] = {
415 [ C(RESULT_ACCESS) ] = -1,
416 [ C(RESULT_MISS) ] = -1,
417 },
418 },
89d6c0b5
PZ		 419 [ C(NODE) ] = {
420 [ C(OP_READ) ] = {
74e6543f
YZ		 421 [ C(RESULT_ACCESS) ] = 0x01b7,
422 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 423 },
424 [ C(OP_WRITE) ] = {
74e6543f
YZ		 425 [ C(RESULT_ACCESS) ] = 0x01b7,
426 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 427 },
428 [ C(OP_PREFETCH) ] = {
74e6543f
YZ		 429 [ C(RESULT_ACCESS) ] = 0x01b7,
430 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 431 },
432 },
433
b06b3d49
LM		 434};
435
0f1b5ca2
AK		 436/*
437 * Notes on the events:
438 * - data reads do not include code reads (comparable to earlier tables)
439 * - data counts include speculative execution (except L1 write, dtlb, bpu)
440 * - remote node access includes remote memory, remote cache, remote mmio.
441 * - prefetches are not included in the counts because they are not
442 * reliably counted.
443 */
444
445#define HSW_DEMAND_DATA_RD BIT_ULL(0)
446#define HSW_DEMAND_RFO BIT_ULL(1)
447#define HSW_ANY_RESPONSE BIT_ULL(16)
448#define HSW_SUPPLIER_NONE BIT_ULL(17)
449#define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
450#define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
451#define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
452#define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
453#define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
454 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
455 HSW_L3_MISS_REMOTE_HOP2P)
456#define HSW_SNOOP_NONE BIT_ULL(31)
457#define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
458#define HSW_SNOOP_MISS BIT_ULL(33)
459#define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
460#define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
461#define HSW_SNOOP_HITM BIT_ULL(36)
462#define HSW_SNOOP_NON_DRAM BIT_ULL(37)
463#define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
464 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
465 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
466 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
467#define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
468#define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
469#define HSW_DEMAND_WRITE HSW_DEMAND_RFO
470#define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
471 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
472#define HSW_LLC_ACCESS HSW_ANY_RESPONSE
473
91f1b705
AK		 474#define BDW_L3_MISS_LOCAL BIT(26)
475#define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
476 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
477 HSW_L3_MISS_REMOTE_HOP2P)
478
479
0f1b5ca2
AK		 480static __initconst const u64 hsw_hw_cache_event_ids
481 [PERF_COUNT_HW_CACHE_MAX]
482 [PERF_COUNT_HW_CACHE_OP_MAX]
483 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
484{
485 [ C(L1D ) ] = {
486 [ C(OP_READ) ] = {
487 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
488 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
489 },
490 [ C(OP_WRITE) ] = {
491 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
492 [ C(RESULT_MISS) ] = 0x0,
493 },
494 [ C(OP_PREFETCH) ] = {
495 [ C(RESULT_ACCESS) ] = 0x0,
496 [ C(RESULT_MISS) ] = 0x0,
497 },
498 },
499 [ C(L1I ) ] = {
500 [ C(OP_READ) ] = {
501 [ C(RESULT_ACCESS) ] = 0x0,
502 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
503 },
504 [ C(OP_WRITE) ] = {
505 [ C(RESULT_ACCESS) ] = -1,
506 [ C(RESULT_MISS) ] = -1,
507 },
508 [ C(OP_PREFETCH) ] = {
509 [ C(RESULT_ACCESS) ] = 0x0,
510 [ C(RESULT_MISS) ] = 0x0,
511 },
512 },
513 [ C(LL ) ] = {
514 [ C(OP_READ) ] = {
515 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
516 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
517 },
518 [ C(OP_WRITE) ] = {
519 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
520 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
521 },
522 [ C(OP_PREFETCH) ] = {
523 [ C(RESULT_ACCESS) ] = 0x0,
524 [ C(RESULT_MISS) ] = 0x0,
525 },
526 },
527 [ C(DTLB) ] = {
528 [ C(OP_READ) ] = {
529 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
530 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
531 },
532 [ C(OP_WRITE) ] = {
533 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
534 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
535 },
536 [ C(OP_PREFETCH) ] = {
537 [ C(RESULT_ACCESS) ] = 0x0,
538 [ C(RESULT_MISS) ] = 0x0,
539 },
540 },
541 [ C(ITLB) ] = {
542 [ C(OP_READ) ] = {
543 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
544 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
545 },
546 [ C(OP_WRITE) ] = {
547 [ C(RESULT_ACCESS) ] = -1,
548 [ C(RESULT_MISS) ] = -1,
549 },
550 [ C(OP_PREFETCH) ] = {
551 [ C(RESULT_ACCESS) ] = -1,
552 [ C(RESULT_MISS) ] = -1,
553 },
554 },
555 [ C(BPU ) ] = {
556 [ C(OP_READ) ] = {
557 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
558 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
559 },
560 [ C(OP_WRITE) ] = {
561 [ C(RESULT_ACCESS) ] = -1,
562 [ C(RESULT_MISS) ] = -1,
563 },
564 [ C(OP_PREFETCH) ] = {
565 [ C(RESULT_ACCESS) ] = -1,
566 [ C(RESULT_MISS) ] = -1,
567 },
568 },
569 [ C(NODE) ] = {
570 [ C(OP_READ) ] = {
571 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
572 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
573 },
574 [ C(OP_WRITE) ] = {
575 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
576 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
577 },
578 [ C(OP_PREFETCH) ] = {
579 [ C(RESULT_ACCESS) ] = 0x0,
580 [ C(RESULT_MISS) ] = 0x0,
581 },
582 },
583};
584
585static __initconst const u64 hsw_hw_cache_extra_regs
586 [PERF_COUNT_HW_CACHE_MAX]
587 [PERF_COUNT_HW_CACHE_OP_MAX]
588 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
589{
590 [ C(LL ) ] = {
591 [ C(OP_READ) ] = {
592 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
593 HSW_LLC_ACCESS,
594 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
595 HSW_L3_MISS|HSW_ANY_SNOOP,
596 },
597 [ C(OP_WRITE) ] = {
598 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
599 HSW_LLC_ACCESS,
600 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
601 HSW_L3_MISS|HSW_ANY_SNOOP,
602 },
603 [ C(OP_PREFETCH) ] = {
604 [ C(RESULT_ACCESS) ] = 0x0,
605 [ C(RESULT_MISS) ] = 0x0,
606 },
607 },
608 [ C(NODE) ] = {
609 [ C(OP_READ) ] = {
610 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
611 HSW_L3_MISS_LOCAL_DRAM|
612 HSW_SNOOP_DRAM,
613 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
614 HSW_L3_MISS_REMOTE|
615 HSW_SNOOP_DRAM,
616 },
617 [ C(OP_WRITE) ] = {
618 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
619 HSW_L3_MISS_LOCAL_DRAM|
620 HSW_SNOOP_DRAM,
621 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
622 HSW_L3_MISS_REMOTE|
623 HSW_SNOOP_DRAM,
624 },
625 [ C(OP_PREFETCH) ] = {
626 [ C(RESULT_ACCESS) ] = 0x0,
627 [ C(RESULT_MISS) ] = 0x0,
628 },
629 },
630};
631
caaa8be3 632static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 633 [PERF_COUNT_HW_CACHE_MAX]
634 [PERF_COUNT_HW_CACHE_OP_MAX]
635 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
636{
637 [ C(L1D) ] = {
638 [ C(OP_READ) ] = {
639 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
640 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
641 },
642 [ C(OP_WRITE) ] = {
643 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
644 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
645 },
646 [ C(OP_PREFETCH) ] = {
647 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
648 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
649 },
650 },
651 [ C(L1I ) ] = {
652 [ C(OP_READ) ] = {
653 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
654 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
655 },
656 [ C(OP_WRITE) ] = {
657 [ C(RESULT_ACCESS) ] = -1,
658 [ C(RESULT_MISS) ] = -1,
659 },
660 [ C(OP_PREFETCH) ] = {
661 [ C(RESULT_ACCESS) ] = 0x0,
662 [ C(RESULT_MISS) ] = 0x0,
663 },
664 },
665 [ C(LL ) ] = {
666 [ C(OP_READ) ] = {
63b6a675 667 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 668 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 669 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
670 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 671 },
e994d7d2
AK		 672 /*
673 * Use RFO, not WRITEBACK, because a write miss would typically occur
674 * on RFO.
675 */
f22f54f4 676 [ C(OP_WRITE) ] = {
63b6a675
PZ		 677 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
678 [ C(RESULT_ACCESS) ] = 0x01b7,
679 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 680 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 681 },
682 [ C(OP_PREFETCH) ] = {
63b6a675 683 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 684 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 685 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
686 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 687 },
688 },
689 [ C(DTLB) ] = {
690 [ C(OP_READ) ] = {
691 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
692 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
693 },
694 [ C(OP_WRITE) ] = {
695 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
696 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
697 },
698 [ C(OP_PREFETCH) ] = {
699 [ C(RESULT_ACCESS) ] = 0x0,
700 [ C(RESULT_MISS) ] = 0x0,
701 },
702 },
703 [ C(ITLB) ] = {
704 [ C(OP_READ) ] = {
705 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
706 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
707 },
708 [ C(OP_WRITE) ] = {
709 [ C(RESULT_ACCESS) ] = -1,
710 [ C(RESULT_MISS) ] = -1,
711 },
712 [ C(OP_PREFETCH) ] = {
713 [ C(RESULT_ACCESS) ] = -1,
714 [ C(RESULT_MISS) ] = -1,
715 },
716 },
717 [ C(BPU ) ] = {
718 [ C(OP_READ) ] = {
719 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
720 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
721 },
722 [ C(OP_WRITE) ] = {
723 [ C(RESULT_ACCESS) ] = -1,
724 [ C(RESULT_MISS) ] = -1,
725 },
726 [ C(OP_PREFETCH) ] = {
727 [ C(RESULT_ACCESS) ] = -1,
728 [ C(RESULT_MISS) ] = -1,
729 },
730 },
89d6c0b5
PZ		 731 [ C(NODE) ] = {
732 [ C(OP_READ) ] = {
733 [ C(RESULT_ACCESS) ] = 0x01b7,
734 [ C(RESULT_MISS) ] = 0x01b7,
735 },
736 [ C(OP_WRITE) ] = {
737 [ C(RESULT_ACCESS) ] = 0x01b7,
738 [ C(RESULT_MISS) ] = 0x01b7,
739 },
740 [ C(OP_PREFETCH) ] = {
741 [ C(RESULT_ACCESS) ] = 0x01b7,
742 [ C(RESULT_MISS) ] = 0x01b7,
743 },
744 },
f22f54f4
PZ		 745};
746
e994d7d2 747/*
63b6a675
PZ		 748 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
749 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 750 */
751
63b6a675
PZ		 752#define NHM_DMND_DATA_RD (1 << 0)
753#define NHM_DMND_RFO (1 << 1)
754#define NHM_DMND_IFETCH (1 << 2)
755#define NHM_DMND_WB (1 << 3)
756#define NHM_PF_DATA_RD (1 << 4)
757#define NHM_PF_DATA_RFO (1 << 5)
758#define NHM_PF_IFETCH (1 << 6)
759#define NHM_OFFCORE_OTHER (1 << 7)
760#define NHM_UNCORE_HIT (1 << 8)
761#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
762#define NHM_OTHER_CORE_HITM (1 << 10)
763 /* reserved */
764#define NHM_REMOTE_CACHE_FWD (1 << 12)
765#define NHM_REMOTE_DRAM (1 << 13)
766#define NHM_LOCAL_DRAM (1 << 14)
767#define NHM_NON_DRAM (1 << 15)
768
87e24f4b
PZ		 769#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
770#define NHM_REMOTE (NHM_REMOTE_DRAM)
63b6a675
PZ		 771
772#define NHM_DMND_READ (NHM_DMND_DATA_RD)
773#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
774#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
775
776#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
87e24f4b 777#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
63b6a675 778#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 779
780static __initconst const u64 nehalem_hw_cache_extra_regs
781 [PERF_COUNT_HW_CACHE_MAX]
782 [PERF_COUNT_HW_CACHE_OP_MAX]
783 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
784{
785 [ C(LL ) ] = {
786 [ C(OP_READ) ] = {
63b6a675
PZ		 787 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
788 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 789 },
790 [ C(OP_WRITE) ] = {
63b6a675
PZ		 791 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
792 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 793 },
794 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 795 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
796 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2 797 },
89d6c0b5
PZ		 798 },
799 [ C(NODE) ] = {
800 [ C(OP_READ) ] = {
87e24f4b
PZ		 801 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
802 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
89d6c0b5
PZ		 803 },
804 [ C(OP_WRITE) ] = {
87e24f4b
PZ		 805 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
806 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
89d6c0b5
PZ		 807 },
808 [ C(OP_PREFETCH) ] = {
87e24f4b
PZ		 809 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
810 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
89d6c0b5
PZ		 811 },
812 },
e994d7d2
AK		 813};
814
caaa8be3 815static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 816 [PERF_COUNT_HW_CACHE_MAX]
817 [PERF_COUNT_HW_CACHE_OP_MAX]
818 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
819{
820 [ C(L1D) ] = {
821 [ C(OP_READ) ] = {
f4929bd3
PZ		 822 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
823 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 824 },
825 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 826 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
827 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 828 },
829 [ C(OP_PREFETCH) ] = {
830 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
831 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
832 },
833 },
834 [ C(L1I ) ] = {
835 [ C(OP_READ) ] = {
836 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
837 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
838 },
839 [ C(OP_WRITE) ] = {
840 [ C(RESULT_ACCESS) ] = -1,
841 [ C(RESULT_MISS) ] = -1,
842 },
843 [ C(OP_PREFETCH) ] = {
844 [ C(RESULT_ACCESS) ] = 0x0,
845 [ C(RESULT_MISS) ] = 0x0,
846 },
847 },
848 [ C(LL ) ] = {
849 [ C(OP_READ) ] = {
e994d7d2
AK		 850 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
851 [ C(RESULT_ACCESS) ] = 0x01b7,
852 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
853 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 854 },
e994d7d2
AK		 855 /*
856 * Use RFO, not WRITEBACK, because a write miss would typically occur
857 * on RFO.
858 */
f22f54f4 859 [ C(OP_WRITE) ] = {
e994d7d2
AK		 860 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
861 [ C(RESULT_ACCESS) ] = 0x01b7,
862 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
863 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 864 },
865 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 866 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
867 [ C(RESULT_ACCESS) ] = 0x01b7,
868 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
869 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 870 },
871 },
872 [ C(DTLB) ] = {
873 [ C(OP_READ) ] = {
874 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
875 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
876 },
877 [ C(OP_WRITE) ] = {
878 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
879 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
880 },
881 [ C(OP_PREFETCH) ] = {
882 [ C(RESULT_ACCESS) ] = 0x0,
883 [ C(RESULT_MISS) ] = 0x0,
884 },
885 },
886 [ C(ITLB) ] = {
887 [ C(OP_READ) ] = {
888 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
889 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
890 },
891 [ C(OP_WRITE) ] = {
892 [ C(RESULT_ACCESS) ] = -1,
893 [ C(RESULT_MISS) ] = -1,
894 },
895 [ C(OP_PREFETCH) ] = {
896 [ C(RESULT_ACCESS) ] = -1,
897 [ C(RESULT_MISS) ] = -1,
898 },
899 },
900 [ C(BPU ) ] = {
901 [ C(OP_READ) ] = {
902 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
903 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
904 },
905 [ C(OP_WRITE) ] = {
906 [ C(RESULT_ACCESS) ] = -1,
907 [ C(RESULT_MISS) ] = -1,
908 },
909 [ C(OP_PREFETCH) ] = {
910 [ C(RESULT_ACCESS) ] = -1,
911 [ C(RESULT_MISS) ] = -1,
912 },
913 },
89d6c0b5
PZ		 914 [ C(NODE) ] = {
915 [ C(OP_READ) ] = {
916 [ C(RESULT_ACCESS) ] = 0x01b7,
917 [ C(RESULT_MISS) ] = 0x01b7,
918 },
919 [ C(OP_WRITE) ] = {
920 [ C(RESULT_ACCESS) ] = 0x01b7,
921 [ C(RESULT_MISS) ] = 0x01b7,
922 },
923 [ C(OP_PREFETCH) ] = {
924 [ C(RESULT_ACCESS) ] = 0x01b7,
925 [ C(RESULT_MISS) ] = 0x01b7,
926 },
927 },
f22f54f4
PZ		 928};
929
caaa8be3 930static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 931 [PERF_COUNT_HW_CACHE_MAX]
932 [PERF_COUNT_HW_CACHE_OP_MAX]
933 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
934{
935 [ C(L1D) ] = {
936 [ C(OP_READ) ] = {
937 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
938 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
939 },
940 [ C(OP_WRITE) ] = {
941 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
942 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
943 },
944 [ C(OP_PREFETCH) ] = {
945 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
946 [ C(RESULT_MISS) ] = 0,
947 },
948 },
949 [ C(L1I ) ] = {
950 [ C(OP_READ) ] = {
951 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
952 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
953 },
954 [ C(OP_WRITE) ] = {
955 [ C(RESULT_ACCESS) ] = -1,
956 [ C(RESULT_MISS) ] = -1,
957 },
958 [ C(OP_PREFETCH) ] = {
959 [ C(RESULT_ACCESS) ] = 0,
960 [ C(RESULT_MISS) ] = 0,
961 },
962 },
963 [ C(LL ) ] = {
964 [ C(OP_READ) ] = {
965 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
966 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
967 },
968 [ C(OP_WRITE) ] = {
969 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
970 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
971 },
972 [ C(OP_PREFETCH) ] = {
973 [ C(RESULT_ACCESS) ] = 0,
974 [ C(RESULT_MISS) ] = 0,
975 },
976 },
977 [ C(DTLB) ] = {
978 [ C(OP_READ) ] = {
979 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
980 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
981 },
982 [ C(OP_WRITE) ] = {
983 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
984 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
985 },
986 [ C(OP_PREFETCH) ] = {
987 [ C(RESULT_ACCESS) ] = 0,
988 [ C(RESULT_MISS) ] = 0,
989 },
990 },
991 [ C(ITLB) ] = {
992 [ C(OP_READ) ] = {
993 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
994 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
995 },
996 [ C(OP_WRITE) ] = {
997 [ C(RESULT_ACCESS) ] = -1,
998 [ C(RESULT_MISS) ] = -1,
999 },
1000 [ C(OP_PREFETCH) ] = {
1001 [ C(RESULT_ACCESS) ] = -1,
1002 [ C(RESULT_MISS) ] = -1,
1003 },
1004 },
1005 [ C(BPU ) ] = {
1006 [ C(OP_READ) ] = {
1007 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1008 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1009 },
1010 [ C(OP_WRITE) ] = {
1011 [ C(RESULT_ACCESS) ] = -1,
1012 [ C(RESULT_MISS) ] = -1,
1013 },
1014 [ C(OP_PREFETCH) ] = {
1015 [ C(RESULT_ACCESS) ] = -1,
1016 [ C(RESULT_MISS) ] = -1,
1017 },
1018 },
1019};
1020
caaa8be3 1021static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 1022 [PERF_COUNT_HW_CACHE_MAX]
1023 [PERF_COUNT_HW_CACHE_OP_MAX]
1024 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1025{
1026 [ C(L1D) ] = {
1027 [ C(OP_READ) ] = {
1028 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1029 [ C(RESULT_MISS) ] = 0,
1030 },
1031 [ C(OP_WRITE) ] = {
1032 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1033 [ C(RESULT_MISS) ] = 0,
1034 },
1035 [ C(OP_PREFETCH) ] = {
1036 [ C(RESULT_ACCESS) ] = 0x0,
1037 [ C(RESULT_MISS) ] = 0,
1038 },
1039 },
1040 [ C(L1I ) ] = {
1041 [ C(OP_READ) ] = {
1042 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1043 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1044 },
1045 [ C(OP_WRITE) ] = {
1046 [ C(RESULT_ACCESS) ] = -1,
1047 [ C(RESULT_MISS) ] = -1,
1048 },
1049 [ C(OP_PREFETCH) ] = {
1050 [ C(RESULT_ACCESS) ] = 0,
1051 [ C(RESULT_MISS) ] = 0,
1052 },
1053 },
1054 [ C(LL ) ] = {
1055 [ C(OP_READ) ] = {
1056 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1057 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1058 },
1059 [ C(OP_WRITE) ] = {
1060 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1061 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1062 },
1063 [ C(OP_PREFETCH) ] = {
1064 [ C(RESULT_ACCESS) ] = 0,
1065 [ C(RESULT_MISS) ] = 0,
1066 },
1067 },
1068 [ C(DTLB) ] = {
1069 [ C(OP_READ) ] = {
1070 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1071 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1072 },
1073 [ C(OP_WRITE) ] = {
1074 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1075 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1076 },
1077 [ C(OP_PREFETCH) ] = {
1078 [ C(RESULT_ACCESS) ] = 0,
1079 [ C(RESULT_MISS) ] = 0,
1080 },
1081 },
1082 [ C(ITLB) ] = {
1083 [ C(OP_READ) ] = {
1084 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1085 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1086 },
1087 [ C(OP_WRITE) ] = {
1088 [ C(RESULT_ACCESS) ] = -1,
1089 [ C(RESULT_MISS) ] = -1,
1090 },
1091 [ C(OP_PREFETCH) ] = {
1092 [ C(RESULT_ACCESS) ] = -1,
1093 [ C(RESULT_MISS) ] = -1,
1094 },
1095 },
1096 [ C(BPU ) ] = {
1097 [ C(OP_READ) ] = {
1098 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1099 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1100 },
1101 [ C(OP_WRITE) ] = {
1102 [ C(RESULT_ACCESS) ] = -1,
1103 [ C(RESULT_MISS) ] = -1,
1104 },
1105 [ C(OP_PREFETCH) ] = {
1106 [ C(RESULT_ACCESS) ] = -1,
1107 [ C(RESULT_MISS) ] = -1,
1108 },
1109 },
1110};
1111
1fa64180
YZ		 1112static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1113{
1114 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
06c939c1
PZ		 1115 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1116 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x768005ffffull, RSP_1),
1fa64180
YZ		 1117 EVENT_EXTRA_END
1118};
1119
1120#define SLM_DMND_READ SNB_DMND_DATA_RD
1121#define SLM_DMND_WRITE SNB_DMND_RFO
1122#define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1123
1124#define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1125#define SLM_LLC_ACCESS SNB_RESP_ANY
1126#define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1127
1128static __initconst const u64 slm_hw_cache_extra_regs
1129 [PERF_COUNT_HW_CACHE_MAX]
1130 [PERF_COUNT_HW_CACHE_OP_MAX]
1131 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1132{
1133 [ C(LL ) ] = {
1134 [ C(OP_READ) ] = {
1135 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1136 [ C(RESULT_MISS) ] = SLM_DMND_READ|SLM_LLC_MISS,
1137 },
1138 [ C(OP_WRITE) ] = {
1139 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1140 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1141 },
1142 [ C(OP_PREFETCH) ] = {
1143 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1144 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1145 },
1146 },
1147};
1148
1149static __initconst const u64 slm_hw_cache_event_ids
1150 [PERF_COUNT_HW_CACHE_MAX]
1151 [PERF_COUNT_HW_CACHE_OP_MAX]
1152 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1153{
1154 [ C(L1D) ] = {
1155 [ C(OP_READ) ] = {
1156 [ C(RESULT_ACCESS) ] = 0,
1157 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1158 },
1159 [ C(OP_WRITE) ] = {
1160 [ C(RESULT_ACCESS) ] = 0,
1161 [ C(RESULT_MISS) ] = 0,
1162 },
1163 [ C(OP_PREFETCH) ] = {
1164 [ C(RESULT_ACCESS) ] = 0,
1165 [ C(RESULT_MISS) ] = 0,
1166 },
1167 },
1168 [ C(L1I ) ] = {
1169 [ C(OP_READ) ] = {
1170 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1171 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1172 },
1173 [ C(OP_WRITE) ] = {
1174 [ C(RESULT_ACCESS) ] = -1,
1175 [ C(RESULT_MISS) ] = -1,
1176 },
1177 [ C(OP_PREFETCH) ] = {
1178 [ C(RESULT_ACCESS) ] = 0,
1179 [ C(RESULT_MISS) ] = 0,
1180 },
1181 },
1182 [ C(LL ) ] = {
1183 [ C(OP_READ) ] = {
1184 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1185 [ C(RESULT_ACCESS) ] = 0x01b7,
1186 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1187 [ C(RESULT_MISS) ] = 0x01b7,
1188 },
1189 [ C(OP_WRITE) ] = {
1190 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1191 [ C(RESULT_ACCESS) ] = 0x01b7,
1192 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1193 [ C(RESULT_MISS) ] = 0x01b7,
1194 },
1195 [ C(OP_PREFETCH) ] = {
1196 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1197 [ C(RESULT_ACCESS) ] = 0x01b7,
1198 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1199 [ C(RESULT_MISS) ] = 0x01b7,
1200 },
1201 },
1202 [ C(DTLB) ] = {
1203 [ C(OP_READ) ] = {
1204 [ C(RESULT_ACCESS) ] = 0,
1205 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1206 },
1207 [ C(OP_WRITE) ] = {
1208 [ C(RESULT_ACCESS) ] = 0,
1209 [ C(RESULT_MISS) ] = 0,
1210 },
1211 [ C(OP_PREFETCH) ] = {
1212 [ C(RESULT_ACCESS) ] = 0,
1213 [ C(RESULT_MISS) ] = 0,
1214 },
1215 },
1216 [ C(ITLB) ] = {
1217 [ C(OP_READ) ] = {
1218 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1219 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1220 },
1221 [ C(OP_WRITE) ] = {
1222 [ C(RESULT_ACCESS) ] = -1,
1223 [ C(RESULT_MISS) ] = -1,
1224 },
1225 [ C(OP_PREFETCH) ] = {
1226 [ C(RESULT_ACCESS) ] = -1,
1227 [ C(RESULT_MISS) ] = -1,
1228 },
1229 },
1230 [ C(BPU ) ] = {
1231 [ C(OP_READ) ] = {
1232 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1233 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1234 },
1235 [ C(OP_WRITE) ] = {
1236 [ C(RESULT_ACCESS) ] = -1,
1237 [ C(RESULT_MISS) ] = -1,
1238 },
1239 [ C(OP_PREFETCH) ] = {
1240 [ C(RESULT_ACCESS) ] = -1,
1241 [ C(RESULT_MISS) ] = -1,
1242 },
1243 },
1244};
1245
f22f54f4
PZ		 1246static void intel_pmu_disable_all(void)
1247{
89cbc767 1248 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4
PZ		 1249
1250 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1251
15c7ad51 1252 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
f22f54f4 1253 intel_pmu_disable_bts();
8062382c
AS		 1254 else
1255 intel_bts_disable_local();
ca037701
PZ		 1256
1257 intel_pmu_pebs_disable_all();
caff2bef 1258 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 1259}
1260
11164cd4 1261static void intel_pmu_enable_all(int added)
f22f54f4 1262{
89cbc767 1263 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4 1264
d329527e
PZ		 1265 intel_pmu_pebs_enable_all();
1266 intel_pmu_lbr_enable_all();
144d31e6
GN		 1267 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1268 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
f22f54f4 1269
15c7ad51 1270 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
f22f54f4 1271 struct perf_event *event =
15c7ad51 1272 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
f22f54f4
PZ		 1273
1274 if (WARN_ON_ONCE(!event))
1275 return;
1276
1277 intel_pmu_enable_bts(event->hw.config);
8062382c
AS		 1278 } else
1279 intel_bts_enable_local();
f22f54f4
PZ		 1280}
1281
11164cd4
PZ		 1282/*
1283 * Workaround for:
1284 * Intel Errata AAK100 (model 26)
1285 * Intel Errata AAP53 (model 30)
40b91cd1 1286 * Intel Errata BD53 (model 44)
11164cd4 1287 *
351af072
ZY		 1288 * The official story:
1289 * These chips need to be 'reset' when adding counters by programming the
1290 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1291 * in sequence on the same PMC or on different PMCs.
1292 *
1293 * In practise it appears some of these events do in fact count, and
1294 * we need to programm all 4 events.
11164cd4 1295 */
351af072 1296static void intel_pmu_nhm_workaround(void)
11164cd4 1297{
89cbc767 1298 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
351af072
ZY		 1299 static const unsigned long nhm_magic[4] = {
1300 0x4300B5,
1301 0x4300D2,
1302 0x4300B1,
1303 0x4300B1
1304 };
1305 struct perf_event *event;
1306 int i;
11164cd4 1307
351af072
ZY		 1308 /*
1309 * The Errata requires below steps:
1310 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1311 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1312 * the corresponding PMCx;
1313 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1314 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1315 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1316 */
11164cd4 1317
351af072
ZY		 1318 /*
1319 * The real steps we choose are a little different from above.
1320 * A) To reduce MSR operations, we don't run step 1) as they
1321 * are already cleared before this function is called;
1322 * B) Call x86_perf_event_update to save PMCx before configuring
1323 * PERFEVTSELx with magic number;
1324 * C) With step 5), we do clear only when the PERFEVTSELx is
1325 * not used currently.
1326 * D) Call x86_perf_event_set_period to restore PMCx;
1327 */
11164cd4 1328
351af072
ZY		 1329 /* We always operate 4 pairs of PERF Counters */
1330 for (i = 0; i < 4; i++) {
1331 event = cpuc->events[i];
1332 if (event)
1333 x86_perf_event_update(event);
1334 }
11164cd4 1335
351af072
ZY		 1336 for (i = 0; i < 4; i++) {
1337 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1338 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1339 }
1340
1341 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1342 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 1343
351af072
ZY		 1344 for (i = 0; i < 4; i++) {
1345 event = cpuc->events[i];
1346
1347 if (event) {
1348 x86_perf_event_set_period(event);
31fa58af 1349 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 1350 ARCH_PERFMON_EVENTSEL_ENABLE);
1351 } else
1352 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 1353 }
351af072
ZY		 1354}
1355
1356static void intel_pmu_nhm_enable_all(int added)
1357{
1358 if (added)
1359 intel_pmu_nhm_workaround();
11164cd4
PZ		 1360 intel_pmu_enable_all(added);
1361}
1362
f22f54f4
PZ		 1363static inline u64 intel_pmu_get_status(void)
1364{
1365 u64 status;
1366
1367 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1368
1369 return status;
1370}
1371
1372static inline void intel_pmu_ack_status(u64 ack)
1373{
1374 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1375}
1376
ca037701 1377static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 1378{
15c7ad51 1379 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4
PZ		 1380 u64 ctrl_val, mask;
1381
1382 mask = 0xfULL << (idx * 4);
1383
1384 rdmsrl(hwc->config_base, ctrl_val);
1385 ctrl_val &= ~mask;
7645a24c 1386 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1387}
1388
2b9e344d
PZ		 1389static inline bool event_is_checkpointed(struct perf_event *event)
1390{
1391 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
1392}
1393
ca037701 1394static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 1395{
aff3d91a 1396 struct hw_perf_event *hwc = &event->hw;
89cbc767 1397 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
aff3d91a 1398
15c7ad51 1399 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 1400 intel_pmu_disable_bts();
1401 intel_pmu_drain_bts_buffer();
1402 return;
1403 }
1404
144d31e6
GN		 1405 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1406 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
2b9e344d 1407 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
144d31e6 1408
60ce0fbd
SE		 1409 /*
1410 * must disable before any actual event
1411 * because any event may be combined with LBR
1412 */
a46a2300 1413 if (needs_branch_stack(event))
60ce0fbd
SE		 1414 intel_pmu_lbr_disable(event);
1415
f22f54f4 1416 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1417 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 1418 return;
1419 }
1420
aff3d91a 1421 x86_pmu_disable_event(event);
ca037701 1422
ab608344 1423 if (unlikely(event->attr.precise_ip))
ef21f683 1424 intel_pmu_pebs_disable(event);
f22f54f4
PZ		 1425}
1426
ca037701 1427static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
f22f54f4 1428{
15c7ad51 1429 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4 1430 u64 ctrl_val, bits, mask;
f22f54f4
PZ		 1431
1432 /*
1433 * Enable IRQ generation (0x8),
1434 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1435 * if requested:
1436 */
1437 bits = 0x8ULL;
1438 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1439 bits |= 0x2;
1440 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1441 bits |= 0x1;
1442
1443 /*
1444 * ANY bit is supported in v3 and up
1445 */
1446 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1447 bits |= 0x4;
1448
1449 bits <<= (idx * 4);
1450 mask = 0xfULL << (idx * 4);
1451
1452 rdmsrl(hwc->config_base, ctrl_val);
1453 ctrl_val &= ~mask;
1454 ctrl_val |= bits;
7645a24c 1455 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1456}
1457
aff3d91a 1458static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 1459{
aff3d91a 1460 struct hw_perf_event *hwc = &event->hw;
89cbc767 1461 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
aff3d91a 1462
15c7ad51 1463 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
0a3aee0d 1464 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 1465 return;
1466
1467 intel_pmu_enable_bts(hwc->config);
1468 return;
1469 }
60ce0fbd
SE		 1470 /*
1471 * must enabled before any actual event
1472 * because any event may be combined with LBR
1473 */
a46a2300 1474 if (needs_branch_stack(event))
60ce0fbd 1475 intel_pmu_lbr_enable(event);
f22f54f4 1476
144d31e6
GN		 1477 if (event->attr.exclude_host)
1478 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1479 if (event->attr.exclude_guest)
1480 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1481
2b9e344d
PZ		 1482 if (unlikely(event_is_checkpointed(event)))
1483 cpuc->intel_cp_status |= (1ull << hwc->idx);
1484
f22f54f4 1485 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1486 intel_pmu_enable_fixed(hwc);
f22f54f4
PZ		 1487 return;
1488 }
1489
ab608344 1490 if (unlikely(event->attr.precise_ip))
ef21f683 1491 intel_pmu_pebs_enable(event);
ca037701 1492
31fa58af 1493 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 1494}
1495
1496/*
1497 * Save and restart an expired event. Called by NMI contexts,
1498 * so it has to be careful about preempting normal event ops:
1499 */
de0428a7 1500int intel_pmu_save_and_restart(struct perf_event *event)
f22f54f4 1501{
cc2ad4ba 1502 x86_perf_event_update(event);
2dbf0116
AK		 1503 /*
1504 * For a checkpointed counter always reset back to 0. This
1505 * avoids a situation where the counter overflows, aborts the
1506 * transaction and is then set back to shortly before the
1507 * overflow, and overflows and aborts again.
1508 */
1509 if (unlikely(event_is_checkpointed(event))) {
1510 /* No race with NMIs because the counter should not be armed */
1511 wrmsrl(event->hw.event_base, 0);
1512 local64_set(&event->hw.prev_count, 0);
1513 }
cc2ad4ba 1514 return x86_perf_event_set_period(event);
f22f54f4
PZ		 1515}
1516
1517static void intel_pmu_reset(void)
1518{
0a3aee0d 1519 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 1520 unsigned long flags;
1521 int idx;
1522
948b1bb8 1523 if (!x86_pmu.num_counters)
f22f54f4
PZ		 1524 return;
1525
1526 local_irq_save(flags);
1527
c767a54b 1528 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
f22f54f4 1529
948b1bb8 1530 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
715c85b1
PA		 1531 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1532 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
f22f54f4 1533 }
948b1bb8 1534 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
715c85b1 1535 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 1536
f22f54f4
PZ		 1537 if (ds)
1538 ds->bts_index = ds->bts_buffer_base;
1539
1540 local_irq_restore(flags);
1541}
1542
1543/*
1544 * This handler is triggered by the local APIC, so the APIC IRQ handling
1545 * rules apply:
1546 */
1547static int intel_pmu_handle_irq(struct pt_regs *regs)
1548{
1549 struct perf_sample_data data;
1550 struct cpu_hw_events *cpuc;
1551 int bit, loops;
2e556b5b 1552 u64 status;
b0b2072d 1553 int handled;
f22f54f4 1554
89cbc767 1555 cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4 1556
2bce5dac 1557 /*
72db5596
AK		 1558 * No known reason to not always do late ACK,
1559 * but just in case do it opt-in.
2bce5dac 1560 */
72db5596
AK		 1561 if (!x86_pmu.late_ack)
1562 apic_write(APIC_LVTPC, APIC_DM_NMI);
3fb2b8dd 1563 intel_pmu_disable_all();
b0b2072d 1564 handled = intel_pmu_drain_bts_buffer();
8062382c 1565 handled += intel_bts_interrupt();
f22f54f4 1566 status = intel_pmu_get_status();
a3ef2229
MM		 1567 if (!status)
1568 goto done;
f22f54f4
PZ		 1569
1570 loops = 0;
1571again:
2e556b5b 1572 intel_pmu_ack_status(status);
f22f54f4 1573 if (++loops > 100) {
ae0def05
DH		 1574 static bool warned = false;
1575 if (!warned) {
1576 WARN(1, "perfevents: irq loop stuck!\n");
1577 perf_event_print_debug();
1578 warned = true;
1579 }
f22f54f4 1580 intel_pmu_reset();
3fb2b8dd 1581 goto done;
f22f54f4
PZ		 1582 }
1583
1584 inc_irq_stat(apic_perf_irqs);
ca037701 1585
caff2bef
PZ		 1586 intel_pmu_lbr_read();
1587
b292d7a1
HD		 1588 /*
1589 * CondChgd bit 63 doesn't mean any overflow status. Ignore
1590 * and clear the bit.
1591 */
1592 if (__test_and_clear_bit(63, (unsigned long *)&status)) {
1593 if (!status)
1594 goto done;
1595 }
1596
ca037701
PZ		 1597 /*
1598 * PEBS overflow sets bit 62 in the global status register
1599 */
de725dec
PZ		 1600 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1601 handled++;
ca037701 1602 x86_pmu.drain_pebs(regs);
de725dec 1603 }
ca037701 1604
52ca9ced
AS		 1605 /*
1606 * Intel PT
1607 */
1608 if (__test_and_clear_bit(55, (unsigned long *)&status)) {
1609 handled++;
1610 intel_pt_interrupt();
1611 }
1612
2dbf0116 1613 /*
2b9e344d
PZ		 1614 * Checkpointed counters can lead to 'spurious' PMIs because the
1615 * rollback caused by the PMI will have cleared the overflow status
1616 * bit. Therefore always force probe these counters.
2dbf0116 1617 */
2b9e344d 1618 status |= cpuc->intel_cp_status;
2dbf0116 1619
984b3f57 1620 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 1621 struct perf_event *event = cpuc->events[bit];
1622
de725dec
PZ		 1623 handled++;
1624
f22f54f4
PZ		 1625 if (!test_bit(bit, cpuc->active_mask))
1626 continue;
1627
1628 if (!intel_pmu_save_and_restart(event))
1629 continue;
1630
fd0d000b 1631 perf_sample_data_init(&data, 0, event->hw.last_period);
f22f54f4 1632
60ce0fbd
SE		 1633 if (has_branch_stack(event))
1634 data.br_stack = &cpuc->lbr_stack;
1635
a8b0ca17 1636 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 1637 x86_pmu_stop(event, 0);
f22f54f4
PZ		 1638 }
1639
f22f54f4
PZ		 1640 /*
1641 * Repeat if there is more work to be done:
1642 */
1643 status = intel_pmu_get_status();
1644 if (status)
1645 goto again;
1646
3fb2b8dd 1647done:
11164cd4 1648 intel_pmu_enable_all(0);
72db5596
AK		 1649 /*
1650 * Only unmask the NMI after the overflow counters
1651 * have been reset. This avoids spurious NMIs on
1652 * Haswell CPUs.
1653 */
1654 if (x86_pmu.late_ack)
1655 apic_write(APIC_LVTPC, APIC_DM_NMI);
de725dec 1656 return handled;
f22f54f4
PZ		 1657}
1658
f22f54f4 1659static struct event_constraint *
ca037701 1660intel_bts_constraints(struct perf_event *event)
f22f54f4 1661{
ca037701
PZ		 1662 struct hw_perf_event *hwc = &event->hw;
1663 unsigned int hw_event, bts_event;
f22f54f4 1664
18a073a3
PZ		 1665 if (event->attr.freq)
1666 return NULL;
1667
ca037701
PZ		 1668 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1669 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 1670
ca037701 1671 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 1672 return &bts_constraint;
ca037701 1673
f22f54f4
PZ		 1674 return NULL;
1675}
1676
5a425294 1677static int intel_alt_er(int idx)
b79e8941 1678{
9a5e3fb5 1679 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
5a425294 1680 return idx;
b79e8941 1681
5a425294
PZ		 1682 if (idx == EXTRA_REG_RSP_0)
1683 return EXTRA_REG_RSP_1;
1684
1685 if (idx == EXTRA_REG_RSP_1)
1686 return EXTRA_REG_RSP_0;
1687
1688 return idx;
1689}
1690
1691static void intel_fixup_er(struct perf_event *event, int idx)
1692{
1693 event->hw.extra_reg.idx = idx;
1694
1695 if (idx == EXTRA_REG_RSP_0) {
b79e8941 1696 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 1697 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
b79e8941 1698 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
5a425294
PZ		 1699 } else if (idx == EXTRA_REG_RSP_1) {
1700 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 1701 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
5a425294 1702 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
b79e8941 1703 }
b79e8941
PZ		 1704}
1705
efc9f05d
SE		 1706/*
1707 * manage allocation of shared extra msr for certain events
1708 *
1709 * sharing can be:
1710 * per-cpu: to be shared between the various events on a single PMU
1711 * per-core: per-cpu + shared by HT threads
1712 */
a7e3ed1e 1713static struct event_constraint *
efc9f05d 1714__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
b36817e8
SE		 1715 struct perf_event *event,
1716 struct hw_perf_event_extra *reg)
a7e3ed1e 1717{
efc9f05d 1718 struct event_constraint *c = &emptyconstraint;
a7e3ed1e 1719 struct er_account *era;
cd8a38d3 1720 unsigned long flags;
5a425294 1721 int idx = reg->idx;
a7e3ed1e 1722
5a425294
PZ		 1723 /*
1724 * reg->alloc can be set due to existing state, so for fake cpuc we
1725 * need to ignore this, otherwise we might fail to allocate proper fake
1726 * state for this extra reg constraint. Also see the comment below.
1727 */
1728 if (reg->alloc && !cpuc->is_fake)
b36817e8 1729 return NULL; /* call x86_get_event_constraint() */
a7e3ed1e 1730
b79e8941 1731again:
5a425294 1732 era = &cpuc->shared_regs->regs[idx];
cd8a38d3
SE		 1733 /*
1734 * we use spin_lock_irqsave() to avoid lockdep issues when
1735 * passing a fake cpuc
1736 */
1737 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 1738
1739 if (!atomic_read(&era->ref) || era->config == reg->config) {
1740
5a425294
PZ		 1741 /*
1742 * If its a fake cpuc -- as per validate_{group,event}() we
1743 * shouldn't touch event state and we can avoid doing so
1744 * since both will only call get_event_constraints() once
1745 * on each event, this avoids the need for reg->alloc.
1746 *
1747 * Not doing the ER fixup will only result in era->reg being
1748 * wrong, but since we won't actually try and program hardware
1749 * this isn't a problem either.
1750 */
1751 if (!cpuc->is_fake) {
1752 if (idx != reg->idx)
1753 intel_fixup_er(event, idx);
1754
1755 /*
1756 * x86_schedule_events() can call get_event_constraints()
1757 * multiple times on events in the case of incremental
1758 * scheduling(). reg->alloc ensures we only do the ER
1759 * allocation once.
1760 */
1761 reg->alloc = 1;
1762 }
1763
efc9f05d
SE		 1764 /* lock in msr value */
1765 era->config = reg->config;
1766 era->reg = reg->reg;
1767
1768 /* one more user */
1769 atomic_inc(&era->ref);
1770
a7e3ed1e 1771 /*
b36817e8
SE		 1772 * need to call x86_get_event_constraint()
1773 * to check if associated event has constraints
a7e3ed1e 1774 */
b36817e8 1775 c = NULL;
5a425294
PZ		 1776 } else {
1777 idx = intel_alt_er(idx);
1778 if (idx != reg->idx) {
1779 raw_spin_unlock_irqrestore(&era->lock, flags);
1780 goto again;
1781 }
a7e3ed1e 1782 }
cd8a38d3 1783 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 1784
efc9f05d
SE		 1785 return c;
1786}
1787
1788static void
1789__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1790 struct hw_perf_event_extra *reg)
1791{
1792 struct er_account *era;
1793
1794 /*
5a425294
PZ		 1795 * Only put constraint if extra reg was actually allocated. Also takes
1796 * care of event which do not use an extra shared reg.
1797 *
1798 * Also, if this is a fake cpuc we shouldn't touch any event state
1799 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1800 * either since it'll be thrown out.
efc9f05d 1801 */
5a425294 1802 if (!reg->alloc || cpuc->is_fake)
efc9f05d
SE		 1803 return;
1804
1805 era = &cpuc->shared_regs->regs[reg->idx];
1806
1807 /* one fewer user */
1808 atomic_dec(&era->ref);
1809
1810 /* allocate again next time */
1811 reg->alloc = 0;
1812}
1813
1814static struct event_constraint *
1815intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1816 struct perf_event *event)
1817{
b36817e8
SE		 1818 struct event_constraint *c = NULL, *d;
1819 struct hw_perf_event_extra *xreg, *breg;
1820
1821 xreg = &event->hw.extra_reg;
1822 if (xreg->idx != EXTRA_REG_NONE) {
1823 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1824 if (c == &emptyconstraint)
1825 return c;
1826 }
1827 breg = &event->hw.branch_reg;
1828 if (breg->idx != EXTRA_REG_NONE) {
1829 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1830 if (d == &emptyconstraint) {
1831 __intel_shared_reg_put_constraints(cpuc, xreg);
1832 c = d;
1833 }
1834 }
efc9f05d 1835 return c;
a7e3ed1e
AK		 1836}
1837
de0428a7 1838struct event_constraint *
79cba822
SE		 1839x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
1840 struct perf_event *event)
de0428a7
KW		 1841{
1842 struct event_constraint *c;
1843
1844 if (x86_pmu.event_constraints) {
1845 for_each_event_constraint(c, x86_pmu.event_constraints) {
9fac2cf3 1846 if ((event->hw.config & c->cmask) == c->code) {
9fac2cf3 1847 event->hw.flags |= c->flags;
de0428a7 1848 return c;
9fac2cf3 1849 }
de0428a7
KW		 1850 }
1851 }
1852
1853 return &unconstrained;
1854}
1855
f22f54f4 1856static struct event_constraint *
e979121b 1857__intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
79cba822 1858 struct perf_event *event)
f22f54f4
PZ		 1859{
1860 struct event_constraint *c;
1861
ca037701
PZ		 1862 c = intel_bts_constraints(event);
1863 if (c)
1864 return c;
1865
687805e4 1866 c = intel_shared_regs_constraints(cpuc, event);
f22f54f4
PZ		 1867 if (c)
1868 return c;
1869
687805e4 1870 c = intel_pebs_constraints(event);
a7e3ed1e
AK		 1871 if (c)
1872 return c;
1873
79cba822 1874 return x86_get_event_constraints(cpuc, idx, event);
f22f54f4
PZ		 1875}
1876
e979121b
MD		 1877static void
1878intel_start_scheduling(struct cpu_hw_events *cpuc)
1879{
1880 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1881 struct intel_excl_states *xl, *xlo;
1882 int tid = cpuc->excl_thread_id;
1883 int o_tid = 1 - tid; /* sibling thread */
1884
1885 /*
1886 * nothing needed if in group validation mode
1887 */
1888 if (cpuc->is_fake)
1889 return;
1890 /*
1891 * no exclusion needed
1892 */
1893 if (!excl_cntrs)
1894 return;
1895
1896 xlo = &excl_cntrs->states[o_tid];
1897 xl = &excl_cntrs->states[tid];
1898
1899 xl->sched_started = true;
1900
1901 /*
1902 * lock shared state until we are done scheduling
1903 * in stop_event_scheduling()
1904 * makes scheduling appear as a transaction
1905 */
1906 WARN_ON_ONCE(!irqs_disabled());
1907 raw_spin_lock(&excl_cntrs->lock);
1908
1909 /*
1910 * save initial state of sibling thread
1911 */
1912 memcpy(xlo->init_state, xlo->state, sizeof(xlo->init_state));
1913}
1914
1915static void
1916intel_stop_scheduling(struct cpu_hw_events *cpuc)
1917{
1918 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1919 struct intel_excl_states *xl, *xlo;
1920 int tid = cpuc->excl_thread_id;
1921 int o_tid = 1 - tid; /* sibling thread */
1922
1923 /*
1924 * nothing needed if in group validation mode
1925 */
1926 if (cpuc->is_fake)
1927 return;
1928 /*
1929 * no exclusion needed
1930 */
1931 if (!excl_cntrs)
1932 return;
1933
1934 xlo = &excl_cntrs->states[o_tid];
1935 xl = &excl_cntrs->states[tid];
1936
1937 /*
1938 * make new sibling thread state visible
1939 */
1940 memcpy(xlo->state, xlo->init_state, sizeof(xlo->state));
1941
1942 xl->sched_started = false;
1943 /*
1944 * release shared state lock (acquired in intel_start_scheduling())
1945 */
1946 raw_spin_unlock(&excl_cntrs->lock);
1947}
1948
1949static struct event_constraint *
1950intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
1951 int idx, struct event_constraint *c)
1952{
1953 struct event_constraint *cx;
1954 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1955 struct intel_excl_states *xl, *xlo;
1956 int is_excl, i;
1957 int tid = cpuc->excl_thread_id;
1958 int o_tid = 1 - tid; /* alternate */
1959
1960 /*
1961 * validating a group does not require
1962 * enforcing cross-thread exclusion
1963 */
1964 if (cpuc->is_fake)
1965 return c;
1966
1967 /*
1968 * event requires exclusive counter access
1969 * across HT threads
1970 */
1971 is_excl = c->flags & PERF_X86_EVENT_EXCL;
1972
1973 /*
1974 * xl = state of current HT
1975 * xlo = state of sibling HT
1976 */
1977 xl = &excl_cntrs->states[tid];
1978 xlo = &excl_cntrs->states[o_tid];
1979
1980 cx = c;
1981
1982 /*
1983 * because we modify the constraint, we need
1984 * to make a copy. Static constraints come
1985 * from static const tables.
1986 *
1987 * only needed when constraint has not yet
1988 * been cloned (marked dynamic)
1989 */
1990 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
1991
1992 /* sanity check */
1993 if (idx < 0)
1994 return &emptyconstraint;
1995
1996 /*
1997 * grab pre-allocated constraint entry
1998 */
1999 cx = &cpuc->constraint_list[idx];
2000
2001 /*
2002 * initialize dynamic constraint
2003 * with static constraint
2004 */
2005 memcpy(cx, c, sizeof(*cx));
2006
2007 /*
2008 * mark constraint as dynamic, so we
2009 * can free it later on
2010 */
2011 cx->flags |= PERF_X86_EVENT_DYNAMIC;
2012 }
2013
2014 /*
2015 * From here on, the constraint is dynamic.
2016 * Either it was just allocated above, or it
2017 * was allocated during a earlier invocation
2018 * of this function
2019 */
2020
2021 /*
2022 * Modify static constraint with current dynamic
2023 * state of thread
2024 *
2025 * EXCLUSIVE: sibling counter measuring exclusive event
2026 * SHARED : sibling counter measuring non-exclusive event
2027 * UNUSED : sibling counter unused
2028 */
2029 for_each_set_bit(i, cx->idxmsk, X86_PMC_IDX_MAX) {
2030 /*
2031 * exclusive event in sibling counter
2032 * our corresponding counter cannot be used
2033 * regardless of our event
2034 */
2035 if (xl->state[i] == INTEL_EXCL_EXCLUSIVE)
2036 __clear_bit(i, cx->idxmsk);
2037 /*
2038 * if measuring an exclusive event, sibling
2039 * measuring non-exclusive, then counter cannot
2040 * be used
2041 */
2042 if (is_excl && xl->state[i] == INTEL_EXCL_SHARED)
2043 __clear_bit(i, cx->idxmsk);
2044 }
2045
2046 /*
2047 * recompute actual bit weight for scheduling algorithm
2048 */
2049 cx->weight = hweight64(cx->idxmsk64);
2050
2051 /*
2052 * if we return an empty mask, then switch
2053 * back to static empty constraint to avoid
2054 * the cost of freeing later on
2055 */
2056 if (cx->weight == 0)
2057 cx = &emptyconstraint;
2058
2059 return cx;
2060}
2061
2062static struct event_constraint *
2063intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2064 struct perf_event *event)
2065{
2066 struct event_constraint *c = event->hw.constraint;
2067
2068 /*
2069 * first time only
2070 * - static constraint: no change across incremental scheduling calls
2071 * - dynamic constraint: handled by intel_get_excl_constraints()
2072 */
2073 if (!c)
2074 c = __intel_get_event_constraints(cpuc, idx, event);
2075
2076 if (cpuc->excl_cntrs)
2077 return intel_get_excl_constraints(cpuc, event, idx, c);
2078
2079 return c;
2080}
2081
2082static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
2083 struct perf_event *event)
2084{
2085 struct hw_perf_event *hwc = &event->hw;
2086 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2087 struct intel_excl_states *xlo, *xl;
2088 unsigned long flags = 0; /* keep compiler happy */
2089 int tid = cpuc->excl_thread_id;
2090 int o_tid = 1 - tid;
2091
2092 /*
2093 * nothing needed if in group validation mode
2094 */
2095 if (cpuc->is_fake)
2096 return;
2097
2098 WARN_ON_ONCE(!excl_cntrs);
2099
2100 if (!excl_cntrs)
2101 return;
2102
2103 xl = &excl_cntrs->states[tid];
2104 xlo = &excl_cntrs->states[o_tid];
2105
2106 /*
2107 * put_constraint may be called from x86_schedule_events()
2108 * which already has the lock held so here make locking
2109 * conditional
2110 */
2111 if (!xl->sched_started)
2112 raw_spin_lock_irqsave(&excl_cntrs->lock, flags);
2113
2114 /*
2115 * if event was actually assigned, then mark the
2116 * counter state as unused now
2117 */
2118 if (hwc->idx >= 0)
2119 xlo->state[hwc->idx] = INTEL_EXCL_UNUSED;
2120
2121 if (!xl->sched_started)
2122 raw_spin_unlock_irqrestore(&excl_cntrs->lock, flags);
2123}
2124
efc9f05d
SE		 2125static void
2126intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 2127 struct perf_event *event)
2128{
efc9f05d 2129 struct hw_perf_event_extra *reg;
a7e3ed1e 2130
efc9f05d
SE		 2131 reg = &event->hw.extra_reg;
2132 if (reg->idx != EXTRA_REG_NONE)
2133 __intel_shared_reg_put_constraints(cpuc, reg);
b36817e8
SE		 2134
2135 reg = &event->hw.branch_reg;
2136 if (reg->idx != EXTRA_REG_NONE)
2137 __intel_shared_reg_put_constraints(cpuc, reg);
efc9f05d 2138}
a7e3ed1e 2139
efc9f05d
SE		 2140static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
2141 struct perf_event *event)
2142{
e979121b
MD		 2143 struct event_constraint *c = event->hw.constraint;
2144
efc9f05d 2145 intel_put_shared_regs_event_constraints(cpuc, event);
e979121b
MD		 2146
2147 /*
2148 * is PMU has exclusive counter restrictions, then
2149 * all events are subject to and must call the
2150 * put_excl_constraints() routine
2151 */
2152 if (c && cpuc->excl_cntrs)
2153 intel_put_excl_constraints(cpuc, event);
2154
2155 /* cleanup dynamic constraint */
2156 if (c && (c->flags & PERF_X86_EVENT_DYNAMIC))
2157 event->hw.constraint = NULL;
2158}
2159
2160static void intel_commit_scheduling(struct cpu_hw_events *cpuc,
2161 struct perf_event *event, int cntr)
2162{
2163 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2164 struct event_constraint *c = event->hw.constraint;
2165 struct intel_excl_states *xlo, *xl;
2166 int tid = cpuc->excl_thread_id;
2167 int o_tid = 1 - tid;
2168 int is_excl;
2169
2170 if (cpuc->is_fake || !c)
2171 return;
2172
2173 is_excl = c->flags & PERF_X86_EVENT_EXCL;
2174
2175 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2176 return;
2177
2178 WARN_ON_ONCE(!excl_cntrs);
2179
2180 if (!excl_cntrs)
2181 return;
2182
2183 xl = &excl_cntrs->states[tid];
2184 xlo = &excl_cntrs->states[o_tid];
2185
2186 WARN_ON_ONCE(!raw_spin_is_locked(&excl_cntrs->lock));
2187
2188 if (cntr >= 0) {
2189 if (is_excl)
2190 xlo->init_state[cntr] = INTEL_EXCL_EXCLUSIVE;
2191 else
2192 xlo->init_state[cntr] = INTEL_EXCL_SHARED;
2193 }
a7e3ed1e
AK		 2194}
2195
0780c927 2196static void intel_pebs_aliases_core2(struct perf_event *event)
b4cdc5c2 2197{
0780c927 2198 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
7639dae0
PZ		 2199 /*
2200 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2201 * (0x003c) so that we can use it with PEBS.
2202 *
2203 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2204 * PEBS capable. However we can use INST_RETIRED.ANY_P
2205 * (0x00c0), which is a PEBS capable event, to get the same
2206 * count.
2207 *
2208 * INST_RETIRED.ANY_P counts the number of cycles that retires
2209 * CNTMASK instructions. By setting CNTMASK to a value (16)
2210 * larger than the maximum number of instructions that can be
2211 * retired per cycle (4) and then inverting the condition, we
2212 * count all cycles that retire 16 or less instructions, which
2213 * is every cycle.
2214 *
2215 * Thereby we gain a PEBS capable cycle counter.
2216 */
f9b4eeb8
PZ		 2217 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
2218
0780c927
PZ		 2219 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2220 event->hw.config = alt_config;
2221 }
2222}
2223
2224static void intel_pebs_aliases_snb(struct perf_event *event)
2225{
2226 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2227 /*
2228 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2229 * (0x003c) so that we can use it with PEBS.
2230 *
2231 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2232 * PEBS capable. However we can use UOPS_RETIRED.ALL
2233 * (0x01c2), which is a PEBS capable event, to get the same
2234 * count.
2235 *
2236 * UOPS_RETIRED.ALL counts the number of cycles that retires
2237 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
2238 * larger than the maximum number of micro-ops that can be
2239 * retired per cycle (4) and then inverting the condition, we
2240 * count all cycles that retire 16 or less micro-ops, which
2241 * is every cycle.
2242 *
2243 * Thereby we gain a PEBS capable cycle counter.
2244 */
2245 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
7639dae0
PZ		 2246
2247 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2248 event->hw.config = alt_config;
2249 }
0780c927
PZ		 2250}
2251
2252static int intel_pmu_hw_config(struct perf_event *event)
2253{
2254 int ret = x86_pmu_hw_config(event);
2255
2256 if (ret)
2257 return ret;
2258
2259 if (event->attr.precise_ip && x86_pmu.pebs_aliases)
2260 x86_pmu.pebs_aliases(event);
7639dae0 2261
a46a2300 2262 if (needs_branch_stack(event)) {
60ce0fbd
SE		 2263 ret = intel_pmu_setup_lbr_filter(event);
2264 if (ret)
2265 return ret;
48070342
AS		 2266
2267 /*
2268 * BTS is set up earlier in this path, so don't account twice
2269 */
2270 if (!intel_pmu_has_bts(event)) {
2271 /* disallow lbr if conflicting events are present */
2272 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
2273 return -EBUSY;
2274
2275 event->destroy = hw_perf_lbr_event_destroy;
2276 }
60ce0fbd
SE		 2277 }
2278
b4cdc5c2
PZ		 2279 if (event->attr.type != PERF_TYPE_RAW)
2280 return 0;
2281
2282 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
2283 return 0;
2284
2285 if (x86_pmu.version < 3)
2286 return -EINVAL;
2287
2288 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
2289 return -EACCES;
2290
2291 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
2292
2293 return 0;
2294}
2295
144d31e6
GN		 2296struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
2297{
2298 if (x86_pmu.guest_get_msrs)
2299 return x86_pmu.guest_get_msrs(nr);
2300 *nr = 0;
2301 return NULL;
2302}
2303EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
2304
2305static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
2306{
89cbc767 2307 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2308 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2309
2310 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
2311 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
2312 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
26a4f3c0
GN		 2313 /*
2314 * If PMU counter has PEBS enabled it is not enough to disable counter
2315 * on a guest entry since PEBS memory write can overshoot guest entry
2316 * and corrupt guest memory. Disabling PEBS solves the problem.
2317 */
2318 arr[1].msr = MSR_IA32_PEBS_ENABLE;
2319 arr[1].host = cpuc->pebs_enabled;
2320 arr[1].guest = 0;
144d31e6 2321
26a4f3c0 2322 *nr = 2;
144d31e6
GN		 2323 return arr;
2324}
2325
2326static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
2327{
89cbc767 2328 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2329 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2330 int idx;
2331
2332 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2333 struct perf_event *event = cpuc->events[idx];
2334
2335 arr[idx].msr = x86_pmu_config_addr(idx);
2336 arr[idx].host = arr[idx].guest = 0;
2337
2338 if (!test_bit(idx, cpuc->active_mask))
2339 continue;
2340
2341 arr[idx].host = arr[idx].guest =
2342 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
2343
2344 if (event->attr.exclude_host)
2345 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2346 else if (event->attr.exclude_guest)
2347 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2348 }
2349
2350 *nr = x86_pmu.num_counters;
2351 return arr;
2352}
2353
2354static void core_pmu_enable_event(struct perf_event *event)
2355{
2356 if (!event->attr.exclude_host)
2357 x86_pmu_enable_event(event);
2358}
2359
2360static void core_pmu_enable_all(int added)
2361{
89cbc767 2362 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2363 int idx;
2364
2365 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2366 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
2367
2368 if (!test_bit(idx, cpuc->active_mask) ||
2369 cpuc->events[idx]->attr.exclude_host)
2370 continue;
2371
2372 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2373 }
2374}
2375
3a632cb2
AK		 2376static int hsw_hw_config(struct perf_event *event)
2377{
2378 int ret = intel_pmu_hw_config(event);
2379
2380 if (ret)
2381 return ret;
2382 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
2383 return 0;
2384 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
2385
2386 /*
2387 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
2388 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
2389 * this combination.
2390 */
2391 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
2392 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
2393 event->attr.precise_ip > 0))
2394 return -EOPNOTSUPP;
2395
2dbf0116
AK		 2396 if (event_is_checkpointed(event)) {
2397 /*
2398 * Sampling of checkpointed events can cause situations where
2399 * the CPU constantly aborts because of a overflow, which is
2400 * then checkpointed back and ignored. Forbid checkpointing
2401 * for sampling.
2402 *
2403 * But still allow a long sampling period, so that perf stat
2404 * from KVM works.
2405 */
2406 if (event->attr.sample_period > 0 &&
2407 event->attr.sample_period < 0x7fffffff)
2408 return -EOPNOTSUPP;
2409 }
3a632cb2
AK		 2410 return 0;
2411}
2412
2413static struct event_constraint counter2_constraint =
2414 EVENT_CONSTRAINT(0, 0x4, 0);
2415
2416static struct event_constraint *
79cba822
SE		 2417hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2418 struct perf_event *event)
3a632cb2 2419{
79cba822
SE		 2420 struct event_constraint *c;
2421
2422 c = intel_get_event_constraints(cpuc, idx, event);
3a632cb2
AK		 2423
2424 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
2425 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
2426 if (c->idxmsk64 & (1U << 2))
2427 return &counter2_constraint;
2428 return &emptyconstraint;
2429 }
2430
2431 return c;
2432}
2433
294fe0f5
AK		 2434/*
2435 * Broadwell:
2436 *
2437 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
2438 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
2439 * the two to enforce a minimum period of 128 (the smallest value that has bits
2440 * 0-5 cleared and >= 100).
2441 *
2442 * Because of how the code in x86_perf_event_set_period() works, the truncation
2443 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
2444 * to make up for the 'lost' events due to carrying the 'error' in period_left.
2445 *
2446 * Therefore the effective (average) period matches the requested period,
2447 * despite coarser hardware granularity.
2448 */
2449static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
2450{
2451 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
2452 X86_CONFIG(.event=0xc0, .umask=0x01)) {
2453 if (left < 128)
2454 left = 128;
2455 left &= ~0x3fu;
2456 }
2457 return left;
2458}
2459
641cc938
JO		 2460PMU_FORMAT_ATTR(event, "config:0-7" );
2461PMU_FORMAT_ATTR(umask, "config:8-15" );
2462PMU_FORMAT_ATTR(edge, "config:18" );
2463PMU_FORMAT_ATTR(pc, "config:19" );
2464PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
2465PMU_FORMAT_ATTR(inv, "config:23" );
2466PMU_FORMAT_ATTR(cmask, "config:24-31" );
3a632cb2
AK		 2467PMU_FORMAT_ATTR(in_tx, "config:32");
2468PMU_FORMAT_ATTR(in_tx_cp, "config:33");
641cc938
JO		 2469
2470static struct attribute *intel_arch_formats_attr[] = {
2471 &format_attr_event.attr,
2472 &format_attr_umask.attr,
2473 &format_attr_edge.attr,
2474 &format_attr_pc.attr,
2475 &format_attr_inv.attr,
2476 &format_attr_cmask.attr,
2477 NULL,
2478};
2479
0bf79d44
JO		 2480ssize_t intel_event_sysfs_show(char *page, u64 config)
2481{
2482 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
2483
2484 return x86_event_sysfs_show(page, config, event);
2485}
2486
caaa8be3 2487static __initconst const struct x86_pmu core_pmu = {
f22f54f4
PZ		 2488 .name = "core",
2489 .handle_irq = x86_pmu_handle_irq,
2490 .disable_all = x86_pmu_disable_all,
144d31e6
GN		 2491 .enable_all = core_pmu_enable_all,
2492 .enable = core_pmu_enable_event,
f22f54f4 2493 .disable = x86_pmu_disable_event,
b4cdc5c2 2494 .hw_config = x86_pmu_hw_config,
a072738e 2495 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 2496 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2497 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
2498 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 2499 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
2500 .apic = 1,
2501 /*
2502 * Intel PMCs cannot be accessed sanely above 32 bit width,
2503 * so we install an artificial 1<<31 period regardless of
2504 * the generic event period:
2505 */
2506 .max_period = (1ULL << 31) - 1,
2507 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 2508 .put_event_constraints = intel_put_event_constraints,
f22f54f4 2509 .event_constraints = intel_core_event_constraints,
144d31e6 2510 .guest_get_msrs = core_guest_get_msrs,
641cc938 2511 .format_attrs = intel_arch_formats_attr,
0bf79d44 2512 .events_sysfs_show = intel_event_sysfs_show,
f22f54f4
PZ		 2513};
2514
de0428a7 2515struct intel_shared_regs *allocate_shared_regs(int cpu)
efc9f05d
SE		 2516{
2517 struct intel_shared_regs *regs;
2518 int i;
2519
2520 regs = kzalloc_node(sizeof(struct intel_shared_regs),
2521 GFP_KERNEL, cpu_to_node(cpu));
2522 if (regs) {
2523 /*
2524 * initialize the locks to keep lockdep happy
2525 */
2526 for (i = 0; i < EXTRA_REG_MAX; i++)
2527 raw_spin_lock_init(&regs->regs[i].lock);
2528
2529 regs->core_id = -1;
2530 }
2531 return regs;
2532}
2533
6f6539ca
MD		 2534static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
2535{
2536 struct intel_excl_cntrs *c;
2537 int i;
2538
2539 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
2540 GFP_KERNEL, cpu_to_node(cpu));
2541 if (c) {
2542 raw_spin_lock_init(&c->lock);
2543 for (i = 0; i < X86_PMC_IDX_MAX; i++) {
2544 c->states[0].state[i] = INTEL_EXCL_UNUSED;
2545 c->states[0].init_state[i] = INTEL_EXCL_UNUSED;
2546
2547 c->states[1].state[i] = INTEL_EXCL_UNUSED;
2548 c->states[1].init_state[i] = INTEL_EXCL_UNUSED;
2549 }
2550 c->core_id = -1;
2551 }
2552 return c;
2553}
2554
a7e3ed1e
AK		 2555static int intel_pmu_cpu_prepare(int cpu)
2556{
2557 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2558
6f6539ca
MD		 2559 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
2560 cpuc->shared_regs = allocate_shared_regs(cpu);
2561 if (!cpuc->shared_regs)
2562 return NOTIFY_BAD;
2563 }
69092624 2564
6f6539ca
MD		 2565 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
2566 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
2567
2568 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);
2569 if (!cpuc->constraint_list)
2570 return NOTIFY_BAD;
2571
2572 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
2573 if (!cpuc->excl_cntrs) {
2574 kfree(cpuc->constraint_list);
2575 kfree(cpuc->shared_regs);
2576 return NOTIFY_BAD;
2577 }
2578 cpuc->excl_thread_id = 0;
2579 }
a7e3ed1e 2580
a7e3ed1e
AK		 2581 return NOTIFY_OK;
2582}
2583
74846d35
PZ		 2584static void intel_pmu_cpu_starting(int cpu)
2585{
a7e3ed1e
AK		 2586 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2587 int core_id = topology_core_id(cpu);
2588 int i;
2589
69092624
LM		 2590 init_debug_store_on_cpu(cpu);
2591 /*
2592 * Deal with CPUs that don't clear their LBRs on power-up.
2593 */
2594 intel_pmu_lbr_reset();
2595
b36817e8
SE		 2596 cpuc->lbr_sel = NULL;
2597
2598 if (!cpuc->shared_regs)
69092624
LM		 2599 return;
2600
9a5e3fb5 2601 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
90413464
SE		 2602 void **onln = &cpuc->kfree_on_online[X86_PERF_KFREE_SHARED];
2603
b36817e8
SE		 2604 for_each_cpu(i, topology_thread_cpumask(cpu)) {
2605 struct intel_shared_regs *pc;
a7e3ed1e 2606
b36817e8
SE		 2607 pc = per_cpu(cpu_hw_events, i).shared_regs;
2608 if (pc && pc->core_id == core_id) {
90413464 2609 *onln = cpuc->shared_regs;
b36817e8
SE		 2610 cpuc->shared_regs = pc;
2611 break;
2612 }
a7e3ed1e 2613 }
b36817e8
SE		 2614 cpuc->shared_regs->core_id = core_id;
2615 cpuc->shared_regs->refcnt++;
a7e3ed1e
AK		 2616 }
2617
b36817e8
SE		 2618 if (x86_pmu.lbr_sel_map)
2619 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
6f6539ca
MD		 2620
2621 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
2622 for_each_cpu(i, topology_thread_cpumask(cpu)) {
2623 struct intel_excl_cntrs *c;
2624
2625 c = per_cpu(cpu_hw_events, i).excl_cntrs;
2626 if (c && c->core_id == core_id) {
2627 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
2628 cpuc->excl_cntrs = c;
2629 cpuc->excl_thread_id = 1;
2630 break;
2631 }
2632 }
2633 cpuc->excl_cntrs->core_id = core_id;
2634 cpuc->excl_cntrs->refcnt++;
2635 }
74846d35
PZ		 2636}
2637
2638static void intel_pmu_cpu_dying(int cpu)
2639{
a7e3ed1e 2640 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
efc9f05d 2641 struct intel_shared_regs *pc;
6f6539ca 2642 struct intel_excl_cntrs *c;
a7e3ed1e 2643
efc9f05d 2644 pc = cpuc->shared_regs;
a7e3ed1e
AK		 2645 if (pc) {
2646 if (pc->core_id == -1 || --pc->refcnt == 0)
2647 kfree(pc);
efc9f05d 2648 cpuc->shared_regs = NULL;
a7e3ed1e 2649 }
6f6539ca
MD		 2650 c = cpuc->excl_cntrs;
2651 if (c) {
2652 if (c->core_id == -1 || --c->refcnt == 0)
2653 kfree(c);
2654 cpuc->excl_cntrs = NULL;
2655 kfree(cpuc->constraint_list);
2656 cpuc->constraint_list = NULL;
2657 }
a7e3ed1e 2658
e979121b
MD		 2659 c = cpuc->excl_cntrs;
2660 if (c) {
2661 if (c->core_id == -1 || --c->refcnt == 0)
2662 kfree(c);
2663 cpuc->excl_cntrs = NULL;
2664 }
2665
74846d35
PZ		 2666 fini_debug_store_on_cpu(cpu);
2667}
2668
641cc938
JO		 2669PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
2670
a63fcab4
SE		 2671PMU_FORMAT_ATTR(ldlat, "config1:0-15");
2672
641cc938
JO		 2673static struct attribute *intel_arch3_formats_attr[] = {
2674 &format_attr_event.attr,
2675 &format_attr_umask.attr,
2676 &format_attr_edge.attr,
2677 &format_attr_pc.attr,
2678 &format_attr_any.attr,
2679 &format_attr_inv.attr,
2680 &format_attr_cmask.attr,
3a632cb2
AK		 2681 &format_attr_in_tx.attr,
2682 &format_attr_in_tx_cp.attr,
641cc938
JO		 2683
2684 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
a63fcab4 2685 &format_attr_ldlat.attr, /* PEBS load latency */
641cc938
JO		 2686 NULL,
2687};
2688
caaa8be3 2689static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 2690 .name = "Intel",
2691 .handle_irq = intel_pmu_handle_irq,
2692 .disable_all = intel_pmu_disable_all,
2693 .enable_all = intel_pmu_enable_all,
2694 .enable = intel_pmu_enable_event,
2695 .disable = intel_pmu_disable_event,
b4cdc5c2 2696 .hw_config = intel_pmu_hw_config,
a072738e 2697 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 2698 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2699 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
2700 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 2701 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
2702 .apic = 1,
2703 /*
2704 * Intel PMCs cannot be accessed sanely above 32 bit width,
2705 * so we install an artificial 1<<31 period regardless of
2706 * the generic event period:
2707 */
2708 .max_period = (1ULL << 31) - 1,
3f6da390 2709 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 2710 .put_event_constraints = intel_put_event_constraints,
0780c927 2711 .pebs_aliases = intel_pebs_aliases_core2,
3f6da390 2712
641cc938 2713 .format_attrs = intel_arch3_formats_attr,
0bf79d44 2714 .events_sysfs_show = intel_event_sysfs_show,
641cc938 2715
a7e3ed1e 2716 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 2717 .cpu_starting = intel_pmu_cpu_starting,
2718 .cpu_dying = intel_pmu_cpu_dying,
144d31e6 2719 .guest_get_msrs = intel_guest_get_msrs,
2a0ad3b3 2720 .sched_task = intel_pmu_lbr_sched_task,
f22f54f4
PZ		 2721};
2722
c1d6f42f 2723static __init void intel_clovertown_quirk(void)
3c44780b
PZ		 2724{
2725 /*
2726 * PEBS is unreliable due to:
2727 *
2728 * AJ67 - PEBS may experience CPL leaks
2729 * AJ68 - PEBS PMI may be delayed by one event
2730 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
2731 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
2732 *
2733 * AJ67 could be worked around by restricting the OS/USR flags.
2734 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
2735 *
2736 * AJ106 could possibly be worked around by not allowing LBR
2737 * usage from PEBS, including the fixup.
2738 * AJ68 could possibly be worked around by always programming
ec75a716 2739 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 2740 *
2741 * But taken together it might just make sense to not enable PEBS on
2742 * these chips.
2743 */
c767a54b 2744 pr_warn("PEBS disabled due to CPU errata\n");
3c44780b
PZ		 2745 x86_pmu.pebs = 0;
2746 x86_pmu.pebs_constraints = NULL;
2747}
2748
c93dc84c
PZ		 2749static int intel_snb_pebs_broken(int cpu)
2750{
2751 u32 rev = UINT_MAX; /* default to broken for unknown models */
2752
2753 switch (cpu_data(cpu).x86_model) {
2754 case 42: /* SNB */
2755 rev = 0x28;
2756 break;
2757
2758 case 45: /* SNB-EP */
2759 switch (cpu_data(cpu).x86_mask) {
2760 case 6: rev = 0x618; break;
2761 case 7: rev = 0x70c; break;
2762 }
2763 }
2764
2765 return (cpu_data(cpu).microcode < rev);
2766}
2767
2768static void intel_snb_check_microcode(void)
2769{
2770 int pebs_broken = 0;
2771 int cpu;
2772
2773 get_online_cpus();
2774 for_each_online_cpu(cpu) {
2775 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
2776 break;
2777 }
2778 put_online_cpus();
2779
2780 if (pebs_broken == x86_pmu.pebs_broken)
2781 return;
2782
2783 /*
2784 * Serialized by the microcode lock..
2785 */
2786 if (x86_pmu.pebs_broken) {
2787 pr_info("PEBS enabled due to microcode update\n");
2788 x86_pmu.pebs_broken = 0;
2789 } else {
2790 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
2791 x86_pmu.pebs_broken = 1;
2792 }
2793}
2794
338b522c
KL		 2795/*
2796 * Under certain circumstances, access certain MSR may cause #GP.
2797 * The function tests if the input MSR can be safely accessed.
2798 */
2799static bool check_msr(unsigned long msr, u64 mask)
2800{
2801 u64 val_old, val_new, val_tmp;
2802
2803 /*
2804 * Read the current value, change it and read it back to see if it
2805 * matches, this is needed to detect certain hardware emulators
2806 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
2807 */
2808 if (rdmsrl_safe(msr, &val_old))
2809 return false;
2810
2811 /*
2812 * Only change the bits which can be updated by wrmsrl.
2813 */
2814 val_tmp = val_old ^ mask;
2815 if (wrmsrl_safe(msr, val_tmp) ||
2816 rdmsrl_safe(msr, &val_new))
2817 return false;
2818
2819 if (val_new != val_tmp)
2820 return false;
2821
2822 /* Here it's sure that the MSR can be safely accessed.
2823 * Restore the old value and return.
2824 */
2825 wrmsrl(msr, val_old);
2826
2827 return true;
2828}
2829
c1d6f42f 2830static __init void intel_sandybridge_quirk(void)
6a600a8b 2831{
c93dc84c
PZ		 2832 x86_pmu.check_microcode = intel_snb_check_microcode;
2833 intel_snb_check_microcode();
6a600a8b
PZ		 2834}
2835
c1d6f42f
PZ		 2836static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
2837 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
2838 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
2839 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
2840 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
2841 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
2842 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
2843 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
ffb871bc
GN		 2844};
2845
c1d6f42f
PZ		 2846static __init void intel_arch_events_quirk(void)
2847{
2848 int bit;
2849
2850 /* disable event that reported as not presend by cpuid */
2851 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
2852 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
c767a54b
JP		 2853 pr_warn("CPUID marked event: \'%s\' unavailable\n",
2854 intel_arch_events_map[bit].name);
c1d6f42f
PZ		 2855 }
2856}
2857
2858static __init void intel_nehalem_quirk(void)
2859{
2860 union cpuid10_ebx ebx;
2861
2862 ebx.full = x86_pmu.events_maskl;
2863 if (ebx.split.no_branch_misses_retired) {
2864 /*
2865 * Erratum AAJ80 detected, we work it around by using
2866 * the BR_MISP_EXEC.ANY event. This will over-count
2867 * branch-misses, but it's still much better than the
2868 * architectural event which is often completely bogus:
2869 */
2870 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
2871 ebx.split.no_branch_misses_retired = 0;
2872 x86_pmu.events_maskl = ebx.full;
c767a54b 2873 pr_info("CPU erratum AAJ80 worked around\n");
c1d6f42f
PZ		 2874 }
2875}
2876
93fcf72c
MD		 2877/*
2878 * enable software workaround for errata:
2879 * SNB: BJ122
2880 * IVB: BV98
2881 * HSW: HSD29
2882 *
2883 * Only needed when HT is enabled. However detecting
2884 * this is too difficult and model specific so we enable
2885 * it even with HT off for now.
2886 */
2887static __init void intel_ht_bug(void)
2888{
2889 x86_pmu.flags |= PMU_FL_EXCL_CNTRS;
2890
2891 x86_pmu.commit_scheduling = intel_commit_scheduling;
2892 x86_pmu.start_scheduling = intel_start_scheduling;
2893 x86_pmu.stop_scheduling = intel_stop_scheduling;
2894
2895 pr_info("CPU erratum BJ122, BV98, HSD29 worked around\n");
2896}
2897
7f2ee91f
IM		 2898EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
2899EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
f9134f36 2900
4b2c4f1f 2901/* Haswell special events */
7f2ee91f
IM		 2902EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
2903EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
2904EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
2905EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
2906EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
2907EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
2908EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
2909EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
2910EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
2911EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
2912EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
2913EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
4b2c4f1f 2914
f9134f36 2915static struct attribute *hsw_events_attrs[] = {
4b2c4f1f
AK		 2916 EVENT_PTR(tx_start),
2917 EVENT_PTR(tx_commit),
2918 EVENT_PTR(tx_abort),
2919 EVENT_PTR(tx_capacity),
2920 EVENT_PTR(tx_conflict),
2921 EVENT_PTR(el_start),
2922 EVENT_PTR(el_commit),
2923 EVENT_PTR(el_abort),
2924 EVENT_PTR(el_capacity),
2925 EVENT_PTR(el_conflict),
2926 EVENT_PTR(cycles_t),
2927 EVENT_PTR(cycles_ct),
f9134f36
AK		 2928 EVENT_PTR(mem_ld_hsw),
2929 EVENT_PTR(mem_st_hsw),
2930 NULL
2931};
2932
de0428a7 2933__init int intel_pmu_init(void)
f22f54f4
PZ		 2934{
2935 union cpuid10_edx edx;
2936 union cpuid10_eax eax;
ffb871bc 2937 union cpuid10_ebx ebx;
a1eac7ac 2938 struct event_constraint *c;
f22f54f4 2939 unsigned int unused;
338b522c
KL		 2940 struct extra_reg *er;
2941 int version, i;
f22f54f4
PZ		 2942
2943 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 2944 switch (boot_cpu_data.x86) {
2945 case 0x6:
2946 return p6_pmu_init();
e717bf4e
VW		 2947 case 0xb:
2948 return knc_pmu_init();
a072738e
CG		 2949 case 0xf:
2950 return p4_pmu_init();
2951 }
f22f54f4 2952 return -ENODEV;
f22f54f4
PZ		 2953 }
2954
2955 /*
2956 * Check whether the Architectural PerfMon supports
2957 * Branch Misses Retired hw_event or not.
2958 */
ffb871bc
GN		 2959 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
2960 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
f22f54f4
PZ		 2961 return -ENODEV;
2962
2963 version = eax.split.version_id;
2964 if (version < 2)
2965 x86_pmu = core_pmu;
2966 else
2967 x86_pmu = intel_pmu;
2968
2969 x86_pmu.version = version;
948b1bb8
RR		 2970 x86_pmu.num_counters = eax.split.num_counters;
2971 x86_pmu.cntval_bits = eax.split.bit_width;
2972 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4 2973
c1d6f42f
PZ		 2974 x86_pmu.events_maskl = ebx.full;
2975 x86_pmu.events_mask_len = eax.split.mask_length;
2976
70ab7003
AK		 2977 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
2978
f22f54f4
PZ		 2979 /*
2980 * Quirk: v2 perfmon does not report fixed-purpose events, so
2981 * assume at least 3 events:
2982 */
2983 if (version > 1)
948b1bb8 2984 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
f22f54f4 2985
c9b08884 2986 if (boot_cpu_has(X86_FEATURE_PDCM)) {
8db909a7
PZ		 2987 u64 capabilities;
2988
2989 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
2990 x86_pmu.intel_cap.capabilities = capabilities;
2991 }
2992
ca037701
PZ		 2993 intel_ds_init();
2994
c1d6f42f
PZ		 2995 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
2996
f22f54f4
PZ		 2997 /*
2998 * Install the hw-cache-events table:
2999 */
3000 switch (boot_cpu_data.x86_model) {
0f7c29ce 3001 case 14: /* 65nm Core "Yonah" */
f22f54f4
PZ		 3002 pr_cont("Core events, ");
3003 break;
3004
0f7c29ce 3005 case 15: /* 65nm Core2 "Merom" */
c1d6f42f 3006 x86_add_quirk(intel_clovertown_quirk);
0f7c29ce
PZ		 3007 case 22: /* 65nm Core2 "Merom-L" */
3008 case 23: /* 45nm Core2 "Penryn" */
3009 case 29: /* 45nm Core2 "Dunnington (MP) */
f22f54f4
PZ		 3010 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
3011 sizeof(hw_cache_event_ids));
3012
caff2bef
PZ		 3013 intel_pmu_lbr_init_core();
3014
f22f54f4 3015 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 3016 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4
PZ		 3017 pr_cont("Core2 events, ");
3018 break;
3019
0f7c29ce
PZ		 3020 case 30: /* 45nm Nehalem */
3021 case 26: /* 45nm Nehalem-EP */
3022 case 46: /* 45nm Nehalem-EX */
f22f54f4
PZ		 3023 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
3024 sizeof(hw_cache_event_ids));
e994d7d2
AK		 3025 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3026 sizeof(hw_cache_extra_regs));
f22f54f4 3027
caff2bef
PZ		 3028 intel_pmu_lbr_init_nhm();
3029
f22f54f4 3030 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 3031 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 3032 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 3033 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 3034
f20093ee
SE		 3035 x86_pmu.cpu_events = nhm_events_attrs;
3036
91fc4cc0 3037 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 3038 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3039 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
91fc4cc0 3040 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 3041 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3042 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
94403f88 3043
c1d6f42f 3044 x86_add_quirk(intel_nehalem_quirk);
ec75a716 3045
11164cd4 3046 pr_cont("Nehalem events, ");
f22f54f4 3047 break;
caff2bef 3048
0f7c29ce
PZ		 3049 case 28: /* 45nm Atom "Pineview" */
3050 case 38: /* 45nm Atom "Lincroft" */
3051 case 39: /* 32nm Atom "Penwell" */
3052 case 53: /* 32nm Atom "Cloverview" */
3053 case 54: /* 32nm Atom "Cedarview" */
f22f54f4
PZ		 3054 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
3055 sizeof(hw_cache_event_ids));
3056
caff2bef
PZ		 3057 intel_pmu_lbr_init_atom();
3058
f22f54f4 3059 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 3060 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
f22f54f4
PZ		 3061 pr_cont("Atom events, ");
3062 break;
3063
0f7c29ce 3064 case 55: /* 22nm Atom "Silvermont" */
ef454cae 3065 case 76: /* 14nm Atom "Airmont" */
0f7c29ce 3066 case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
1fa64180
YZ		 3067 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
3068 sizeof(hw_cache_event_ids));
3069 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
3070 sizeof(hw_cache_extra_regs));
3071
3072 intel_pmu_lbr_init_atom();
3073
3074 x86_pmu.event_constraints = intel_slm_event_constraints;
3075 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3076 x86_pmu.extra_regs = intel_slm_extra_regs;
9a5e3fb5 3077 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
1fa64180
YZ		 3078 pr_cont("Silvermont events, ");
3079 break;
3080
0f7c29ce
PZ		 3081 case 37: /* 32nm Westmere */
3082 case 44: /* 32nm Westmere-EP */
3083 case 47: /* 32nm Westmere-EX */
f22f54f4
PZ		 3084 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
3085 sizeof(hw_cache_event_ids));
e994d7d2
AK		 3086 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3087 sizeof(hw_cache_extra_regs));
f22f54f4 3088
caff2bef
PZ		 3089 intel_pmu_lbr_init_nhm();
3090
f22f54f4 3091 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 3092 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 3093 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 3094 x86_pmu.extra_regs = intel_westmere_extra_regs;
9a5e3fb5 3095 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
30112039 3096
f20093ee
SE		 3097 x86_pmu.cpu_events = nhm_events_attrs;
3098
30112039 3099 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 3100 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3101 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
30112039 3102 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 3103 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3104 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
30112039 3105
f22f54f4
PZ		 3106 pr_cont("Westmere events, ");
3107 break;
b622d644 3108
0f7c29ce
PZ		 3109 case 42: /* 32nm SandyBridge */
3110 case 45: /* 32nm SandyBridge-E/EN/EP */
47a8863d 3111 x86_add_quirk(intel_sandybridge_quirk);
93fcf72c 3112 x86_add_quirk(intel_ht_bug);
b06b3d49
LM		 3113 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3114 sizeof(hw_cache_event_ids));
74e6543f
YZ		 3115 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3116 sizeof(hw_cache_extra_regs));
b06b3d49 3117
c5cc2cd9 3118 intel_pmu_lbr_init_snb();
b06b3d49
LM		 3119
3120 x86_pmu.event_constraints = intel_snb_event_constraints;
de0428a7 3121 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
0780c927 3122 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 3123 if (boot_cpu_data.x86_model == 45)
3124 x86_pmu.extra_regs = intel_snbep_extra_regs;
3125 else
3126 x86_pmu.extra_regs = intel_snb_extra_regs;
93fcf72c
MD		 3127
3128
ee89cbc2 3129 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3130 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3131 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
e04d1b23 3132
f20093ee
SE		 3133 x86_pmu.cpu_events = snb_events_attrs;
3134
e04d1b23 3135 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
f9b4eeb8
PZ		 3136 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3137 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 3138 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
f9b4eeb8
PZ		 3139 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3140 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 3141
b06b3d49
LM		 3142 pr_cont("SandyBridge events, ");
3143 break;
0f7c29ce
PZ		 3144
3145 case 58: /* 22nm IvyBridge */
3146 case 62: /* 22nm IvyBridge-EP/EX */
93fcf72c 3147 x86_add_quirk(intel_ht_bug);
20a36e39
SE		 3148 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3149 sizeof(hw_cache_event_ids));
1996388e
VW		 3150 /* dTLB-load-misses on IVB is different than SNB */
3151 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
3152
20a36e39
SE		 3153 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3154 sizeof(hw_cache_extra_regs));
3155
3156 intel_pmu_lbr_init_snb();
3157
69943182 3158 x86_pmu.event_constraints = intel_ivb_event_constraints;
20a36e39
SE		 3159 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
3160 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 3161 if (boot_cpu_data.x86_model == 62)
3162 x86_pmu.extra_regs = intel_snbep_extra_regs;
3163 else
3164 x86_pmu.extra_regs = intel_snb_extra_regs;
20a36e39 3165 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3166 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3167 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
20a36e39 3168
f20093ee
SE		 3169 x86_pmu.cpu_events = snb_events_attrs;
3170
20a36e39
SE		 3171 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3172 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3173 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3174
3175 pr_cont("IvyBridge events, ");
3176 break;
3177
b06b3d49 3178
d86c8eaf
AK		 3179 case 60: /* 22nm Haswell Core */
3180 case 63: /* 22nm Haswell Server */
3181 case 69: /* 22nm Haswell ULT */
3182 case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
93fcf72c 3183 x86_add_quirk(intel_ht_bug);
72db5596 3184 x86_pmu.late_ack = true;
0f1b5ca2
AK		 3185 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3186 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3a632cb2 3187
e9d7f7cd 3188 intel_pmu_lbr_init_hsw();
3a632cb2
AK		 3189
3190 x86_pmu.event_constraints = intel_hsw_event_constraints;
3044318f 3191 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
36bbb2f2 3192 x86_pmu.extra_regs = intel_snbep_extra_regs;
3044318f 3193 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3a632cb2 3194 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3195 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3196 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3a632cb2
AK		 3197
3198 x86_pmu.hw_config = hsw_hw_config;
3199 x86_pmu.get_event_constraints = hsw_get_event_constraints;
f9134f36 3200 x86_pmu.cpu_events = hsw_events_attrs;
b7af41a1 3201 x86_pmu.lbr_double_abort = true;
3a632cb2
AK		 3202 pr_cont("Haswell events, ");
3203 break;
3204
91f1b705
AK		 3205 case 61: /* 14nm Broadwell Core-M */
3206 case 86: /* 14nm Broadwell Xeon D */
3207 x86_pmu.late_ack = true;
3208 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3209 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3210
3211 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
3212 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
3213 BDW_L3_MISS|HSW_SNOOP_DRAM;
3214 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
3215 HSW_SNOOP_DRAM;
3216 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
3217 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3218 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
3219 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3220
3221 intel_pmu_lbr_init_snb();
3222
3223 x86_pmu.event_constraints = intel_bdw_event_constraints;
3224 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3225 x86_pmu.extra_regs = intel_snbep_extra_regs;
3226 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3227 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3228 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3229 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
91f1b705
AK		 3230
3231 x86_pmu.hw_config = hsw_hw_config;
3232 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3233 x86_pmu.cpu_events = hsw_events_attrs;
294fe0f5 3234 x86_pmu.limit_period = bdw_limit_period;
91f1b705
AK		 3235 pr_cont("Broadwell events, ");
3236 break;
3237
f22f54f4 3238 default:
0af3ac1f
AK		 3239 switch (x86_pmu.version) {
3240 case 1:
3241 x86_pmu.event_constraints = intel_v1_event_constraints;
3242 pr_cont("generic architected perfmon v1, ");
3243 break;
3244 default:
3245 /*
3246 * default constraints for v2 and up
3247 */
3248 x86_pmu.event_constraints = intel_gen_event_constraints;
3249 pr_cont("generic architected perfmon, ");
3250 break;
3251 }
f22f54f4 3252 }
ffb871bc 3253
a1eac7ac
RR		 3254 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
3255 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
3256 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
3257 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
3258 }
3259 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
3260
3261 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
3262 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
3263 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
3264 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
3265 }
3266
3267 x86_pmu.intel_ctrl |=
3268 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
3269
3270 if (x86_pmu.event_constraints) {
3271 /*
3272 * event on fixed counter2 (REF_CYCLES) only works on this
3273 * counter, so do not extend mask to generic counters
3274 */
3275 for_each_event_constraint(c, x86_pmu.event_constraints) {
3a632cb2 3276 if (c->cmask != FIXED_EVENT_FLAGS
a1eac7ac
RR		 3277 || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
3278 continue;
3279 }
3280
3281 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
3282 c->weight += x86_pmu.num_counters;
3283 }
3284 }
3285
338b522c
KL		 3286 /*
3287 * Access LBR MSR may cause #GP under certain circumstances.
3288 * E.g. KVM doesn't support LBR MSR
3289 * Check all LBT MSR here.
3290 * Disable LBR access if any LBR MSRs can not be accessed.
3291 */
3292 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
3293 x86_pmu.lbr_nr = 0;
3294 for (i = 0; i < x86_pmu.lbr_nr; i++) {
3295 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
3296 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
3297 x86_pmu.lbr_nr = 0;
3298 }
3299
3300 /*
3301 * Access extra MSR may cause #GP under certain circumstances.
3302 * E.g. KVM doesn't support offcore event
3303 * Check all extra_regs here.
3304 */
3305 if (x86_pmu.extra_regs) {
3306 for (er = x86_pmu.extra_regs; er->msr; er++) {
3307 er->extra_msr_access = check_msr(er->msr, 0x1ffUL);
3308 /* Disable LBR select mapping */
3309 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
3310 x86_pmu.lbr_sel_map = NULL;
3311 }
3312 }
3313
069e0c3c
AK		 3314 /* Support full width counters using alternative MSR range */
3315 if (x86_pmu.intel_cap.full_width_write) {
3316 x86_pmu.max_period = x86_pmu.cntval_mask;
3317 x86_pmu.perfctr = MSR_IA32_PMC0;
3318 pr_cont("full-width counters, ");
3319 }
3320
f22f54f4
PZ		 3321 return 0;
3322}
Linux kernel - Deliverables
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