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drm/i915: Don't use link_bw for PLL setup
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
45244b87
ED		 37/* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
10122051 41static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 51};
52
10122051 53static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 63};
64
10122051
JN		 65static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 79};
80
10122051 81static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 91};
92
10122051 93static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 103};
104
10122051 105static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 115};
116
10122051
JN		 117static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 129};
130
f8896f5d 131/* Skylake H, S, and Skylake Y with 0.95V VccIO */
7f88e3af 132static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x00009010, 0x000000C7, 0x0 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x00007011, 0x000000C7, 0x0 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x00005012, 0x000000C7, 0x0 },
7f88e3af
DL		 142};
143
f8896f5d
DW		 144/* Skylake U */
145static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
146 { 0x00002016, 0x000000A2, 0x0 },
147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x00007011, 0x00000087, 0x0 },
149 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost */
150 { 0x00002016, 0x0000009D, 0x0 },
151 { 0x00005012, 0x000000C7, 0x0 },
152 { 0x00007011, 0x000000C7, 0x0 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x00005012, 0x000000C7, 0x0 },
155};
156
157/* Skylake Y with 0.85V VccIO */
158static const struct ddi_buf_trans skl_y_085v_ddi_translations_dp[] = {
159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x00007011, 0x00000087, 0x0 },
162 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost */
163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x00005012, 0x000000C7, 0x0 },
165 { 0x00007011, 0x000000C7, 0x0 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x00005012, 0x000000C7, 0x0 },
168};
169
170/*
171 * Skylake H and S, and Skylake Y with 0.95V VccIO
172 * eDP 1.4 low vswing translation parameters
173 */
7ad14a29 174static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185};
186
187/*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 202};
203
f8896f5d
DW		 204/*
205 * Skylake Y with 0.95V VccIO
206 * eDP 1.4 low vswing translation parameters
207 */
208static const struct ddi_buf_trans skl_y_085v_ddi_translations_edp[] = {
209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219};
7ad14a29 220
f8896f5d 221/* Skylake H, S and U, and Skylake Y with 0.95V VccIO */
7f88e3af 222static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x00006012, 0x00000087, 0x0 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x00003015, 0x00000087, 0x0 }, /* Default */
232 { 0x00003015, 0x000000C7, 0x0 },
233 { 0x00000018, 0x000000C7, 0x0 },
234};
235
236/* Skylake Y with 0.85V VccIO */
237static const struct ddi_buf_trans skl_y_085v_ddi_translations_hdmi[] = {
238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x00007011, 0x00000084, 0x0 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x00006013, 0x000000C7, 0x0 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x00003015, 0x000000C7, 0x0 }, /* Default */
247 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost */
248 { 0x00000018, 0x000000C7, 0x0 },
7f88e3af
DL		 249};
250
96fb9f9b
VK		 251struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257};
258
259/* BSpec does not define separate vswing/pre-emphasis values for eDP.
260 * Using DP values for eDP as well.
261 */
262static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
263 /* Idx NT mV diff db */
fe4c63c8
ID		 264 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
265 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
266 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
267 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
268 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
269 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
270 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
271 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
272 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 273 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 274};
275
276/* BSpec has 2 recommended values - entries 0 and 8.
277 * Using the entry with higher vswing.
278 */
279static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
280 /* Idx NT mV diff db */
fe4c63c8
ID		 281 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
282 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
283 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
284 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
285 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
286 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
287 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
288 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
289 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 290 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
291};
292
f8896f5d
DW		 293static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
294 enum port port, int type);
295
a1e6ad66
ID		 296static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
297 struct intel_digital_port **dig_port,
298 enum port *port)
fc914639 299{
0bdee30e 300 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 301 int type = intel_encoder->type;
302
0e32b39c 303 if (type == INTEL_OUTPUT_DP_MST) {
a1e6ad66
ID		 304 *dig_port = enc_to_mst(encoder)->primary;
305 *port = (*dig_port)->port;
0e32b39c 306 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 307 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
a1e6ad66
ID		 308 *dig_port = enc_to_dig_port(encoder);
309 *port = (*dig_port)->port;
fc914639 310 } else if (type == INTEL_OUTPUT_ANALOG) {
a1e6ad66
ID		 311 *dig_port = NULL;
312 *port = PORT_E;
fc914639
PZ		 313 } else {
314 DRM_ERROR("Invalid DDI encoder type %d\n", type);
315 BUG();
316 }
317}
318
a1e6ad66
ID		 319enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
320{
321 struct intel_digital_port *dig_port;
322 enum port port;
323
324 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
325
326 return port;
327}
328
ce3b7e9b
DL		 329static bool
330intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
331{
332 return intel_dig_port->hdmi.hdmi_reg;
333}
334
f8896f5d
DW		 335static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev,
336 int *n_entries)
337{
338 struct drm_i915_private *dev_priv = dev->dev_private;
339 const struct ddi_buf_trans *ddi_translations;
340 static int is_095v = -1;
341
342 if (is_095v == -1) {
343 u32 spr1 = I915_READ(UAIMI_SPR1);
344
345 is_095v = spr1 & SKL_VCCIO_MASK;
346 }
347
348 if (IS_SKL_ULX(dev) && !is_095v) {
349 ddi_translations = skl_y_085v_ddi_translations_dp;
350 *n_entries = ARRAY_SIZE(skl_y_085v_ddi_translations_dp);
351 } else if (IS_SKL_ULT(dev)) {
352 ddi_translations = skl_u_ddi_translations_dp;
353 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
354 } else {
355 ddi_translations = skl_ddi_translations_dp;
356 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
357 }
358
359 return ddi_translations;
360}
361
362static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev,
363 int *n_entries)
364{
365 struct drm_i915_private *dev_priv = dev->dev_private;
366 const struct ddi_buf_trans *ddi_translations;
367 static int is_095v = -1;
368
369 if (is_095v == -1) {
370 u32 spr1 = I915_READ(UAIMI_SPR1);
371
372 is_095v = spr1 & SKL_VCCIO_MASK;
373 }
374
375 if (IS_SKL_ULX(dev) && !is_095v) {
376 if (dev_priv->edp_low_vswing) {
377 ddi_translations = skl_y_085v_ddi_translations_edp;
378 *n_entries =
379 ARRAY_SIZE(skl_y_085v_ddi_translations_edp);
380 } else {
381 ddi_translations = skl_y_085v_ddi_translations_dp;
382 *n_entries =
383 ARRAY_SIZE(skl_y_085v_ddi_translations_dp);
384 }
385 } else if (IS_SKL_ULT(dev)) {
386 if (dev_priv->edp_low_vswing) {
387 ddi_translations = skl_u_ddi_translations_edp;
388 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
389 } else {
390 ddi_translations = skl_u_ddi_translations_dp;
391 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
392 }
393 } else {
394 if (dev_priv->edp_low_vswing) {
395 ddi_translations = skl_ddi_translations_edp;
396 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
397 } else {
398 ddi_translations = skl_ddi_translations_dp;
399 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
400 }
401 }
402
403 return ddi_translations;
404}
405
406static const struct ddi_buf_trans *
407skl_get_buf_trans_hdmi(struct drm_device *dev,
408 int *n_entries)
409{
410 struct drm_i915_private *dev_priv = dev->dev_private;
411 const struct ddi_buf_trans *ddi_translations;
412 static int is_095v = -1;
413
414 if (is_095v == -1) {
415 u32 spr1 = I915_READ(UAIMI_SPR1);
416
417 is_095v = spr1 & SKL_VCCIO_MASK;
418 }
419
420 if (IS_SKL_ULX(dev) && !is_095v) {
421 ddi_translations = skl_y_085v_ddi_translations_hdmi;
422 *n_entries = ARRAY_SIZE(skl_y_085v_ddi_translations_hdmi);
423 } else {
424 ddi_translations = skl_ddi_translations_hdmi;
425 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
426 }
427
428 return ddi_translations;
429}
430
e58623cb
AR		 431/*
432 * Starting with Haswell, DDI port buffers must be programmed with correct
433 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 434 * but the HDMI/DVI fields are shared among those. So we program the DDI
435 * in either FDI or DP modes only, as HDMI connections will work with both
436 * of those
437 */
faa0cdbe
ID		 438static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
439 bool supports_hdmi)
45244b87
ED		 440{
441 struct drm_i915_private *dev_priv = dev->dev_private;
442 u32 reg;
75067dde 443 u32 iboost_bit = 0;
7ff44670 444 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 445 size;
6acab15a 446 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 447 const struct ddi_buf_trans *ddi_translations_fdi;
448 const struct ddi_buf_trans *ddi_translations_dp;
449 const struct ddi_buf_trans *ddi_translations_edp;
450 const struct ddi_buf_trans *ddi_translations_hdmi;
451 const struct ddi_buf_trans *ddi_translations;
e58623cb 452
96fb9f9b 453 if (IS_BROXTON(dev)) {
faa0cdbe 454 if (!supports_hdmi)
96fb9f9b
VK		 455 return;
456
457 /* Vswing programming for HDMI */
458 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
459 INTEL_OUTPUT_HDMI);
460 return;
461 } else if (IS_SKYLAKE(dev)) {
c30400fc 462 ddi_translations_fdi = NULL;
f8896f5d
DW		 463 ddi_translations_dp =
464 skl_get_buf_trans_dp(dev, &n_dp_entries);
465 ddi_translations_edp =
466 skl_get_buf_trans_edp(dev, &n_edp_entries);
467 ddi_translations_hdmi =
468 skl_get_buf_trans_hdmi(dev, &n_hdmi_entries);
469 hdmi_default_entry = 8;
75067dde
AK		 470 /* If we're boosting the current, set bit 31 of trans1 */
471 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
472 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
473 iboost_bit = 1<<31;
7f88e3af 474 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 475 ddi_translations_fdi = bdw_ddi_translations_fdi;
476 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 477 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 478 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 479 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
480 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 481 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 482 hdmi_default_entry = 7;
e58623cb
AR		 483 } else if (IS_HASWELL(dev)) {
484 ddi_translations_fdi = hsw_ddi_translations_fdi;
485 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 486 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 487 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 488 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 489 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 490 hdmi_default_entry = 6;
e58623cb
AR		 491 } else {
492 WARN(1, "ddi translation table missing\n");
300644c7 493 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 494 ddi_translations_fdi = bdw_ddi_translations_fdi;
495 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 496 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 497 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
498 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 499 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 500 hdmi_default_entry = 7;
e58623cb
AR		 501 }
502
300644c7
PZ		 503 switch (port) {
504 case PORT_A:
505 ddi_translations = ddi_translations_edp;
7ad14a29 506 size = n_edp_entries;
300644c7
PZ		 507 break;
508 case PORT_B:
509 case PORT_C:
300644c7 510 ddi_translations = ddi_translations_dp;
7ad14a29 511 size = n_dp_entries;
300644c7 512 break;
77d8d009 513 case PORT_D:
7ad14a29 514 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 515 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 516 size = n_edp_entries;
517 } else {
77d8d009 518 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 519 size = n_dp_entries;
520 }
77d8d009 521 break;
300644c7 522 case PORT_E:
7f88e3af
DL		 523 if (ddi_translations_fdi)
524 ddi_translations = ddi_translations_fdi;
525 else
526 ddi_translations = ddi_translations_dp;
7ad14a29 527 size = n_dp_entries;
300644c7
PZ		 528 break;
529 default:
530 BUG();
531 }
45244b87 532
7ad14a29 533 for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
75067dde 534 I915_WRITE(reg, ddi_translations[i].trans1 | iboost_bit);
10122051
JN		 535 reg += 4;
536 I915_WRITE(reg, ddi_translations[i].trans2);
45244b87
ED		 537 reg += 4;
538 }
ce4dd49e 539
faa0cdbe 540 if (!supports_hdmi)
ce3b7e9b
DL		 541 return;
542
ce4dd49e
DL		 543 /* Choose a good default if VBT is badly populated */
544 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
545 hdmi_level >= n_hdmi_entries)
7ff44670 546 hdmi_level = hdmi_default_entry;
ce4dd49e 547
6acab15a 548 /* Entry 9 is for HDMI: */
75067dde 549 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
10122051
JN		 550 reg += 4;
551 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
552 reg += 4;
45244b87
ED		 553}
554
555/* Program DDI buffers translations for DP. By default, program ports A-D in DP
556 * mode and port E for FDI.
557 */
558void intel_prepare_ddi(struct drm_device *dev)
559{
faa0cdbe 560 struct intel_encoder *intel_encoder;
b403745c 561 bool visited[I915_MAX_PORTS] = { 0, };
45244b87 562
0d536cb4
PZ		 563 if (!HAS_DDI(dev))
564 return;
45244b87 565
faa0cdbe
ID		 566 for_each_intel_encoder(dev, intel_encoder) {
567 struct intel_digital_port *intel_dig_port;
568 enum port port;
569 bool supports_hdmi;
570
571 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
572
573 if (visited[port])
b403745c
DL		 574 continue;
575
faa0cdbe
ID		 576 supports_hdmi = intel_dig_port &&
577 intel_dig_port_supports_hdmi(intel_dig_port);
578
579 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
580 visited[port] = true;
b403745c 581 }
45244b87 582}
c82e4d26 583
248138b5
PZ		 584static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
585 enum port port)
586{
587 uint32_t reg = DDI_BUF_CTL(port);
588 int i;
589
3449ca85 590 for (i = 0; i < 16; i++) {
248138b5
PZ		 591 udelay(1);
592 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
593 return;
594 }
595 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
596}
c82e4d26
ED		 597
598/* Starting with Haswell, different DDI ports can work in FDI mode for
599 * connection to the PCH-located connectors. For this, it is necessary to train
600 * both the DDI port and PCH receiver for the desired DDI buffer settings.
601 *
602 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
603 * please note that when FDI mode is active on DDI E, it shares 2 lines with
604 * DDI A (which is used for eDP)
605 */
606
607void hsw_fdi_link_train(struct drm_crtc *crtc)
608{
609 struct drm_device *dev = crtc->dev;
610 struct drm_i915_private *dev_priv = dev->dev_private;
611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 612 u32 temp, i, rx_ctl_val;
c82e4d26 613
04945641
PZ		 614 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
615 * mode set "sequence for CRT port" document:
616 * - TP1 to TP2 time with the default value
617 * - FDI delay to 90h
8693a824
DL		 618 *
619 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 620 */
621 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
622 FDI_RX_PWRDN_LANE0_VAL(2) |
623 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
624
625 /* Enable the PCH Receiver FDI PLL */
3e68320e 626 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 627 FDI_RX_PLL_ENABLE |
6e3c9717 628 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
04945641
PZ		 629 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
630 POSTING_READ(_FDI_RXA_CTL);
631 udelay(220);
632
633 /* Switch from Rawclk to PCDclk */
634 rx_ctl_val |= FDI_PCDCLK;
635 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
636
637 /* Configure Port Clock Select */
6e3c9717
ACO		 638 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
639 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 640
641 /* Start the training iterating through available voltages and emphasis,
642 * testing each value twice. */
10122051 643 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 644 /* Configure DP_TP_CTL with auto-training */
645 I915_WRITE(DP_TP_CTL(PORT_E),
646 DP_TP_CTL_FDI_AUTOTRAIN |
647 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
648 DP_TP_CTL_LINK_TRAIN_PAT1 |
649 DP_TP_CTL_ENABLE);
650
876a8cdf
DL		 651 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
652 * DDI E does not support port reversal, the functionality is
653 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
654 * port reversal bit */
c82e4d26 655 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 656 DDI_BUF_CTL_ENABLE |
6e3c9717 657 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 658 DDI_BUF_TRANS_SELECT(i / 2));
04945641 659 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 660
661 udelay(600);
662
04945641
PZ		 663 /* Program PCH FDI Receiver TU */
664 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
665
666 /* Enable PCH FDI Receiver with auto-training */
667 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
668 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
669 POSTING_READ(_FDI_RXA_CTL);
670
671 /* Wait for FDI receiver lane calibration */
672 udelay(30);
673
674 /* Unset FDI_RX_MISC pwrdn lanes */
675 temp = I915_READ(_FDI_RXA_MISC);
676 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
677 I915_WRITE(_FDI_RXA_MISC, temp);
678 POSTING_READ(_FDI_RXA_MISC);
679
680 /* Wait for FDI auto training time */
681 udelay(5);
c82e4d26
ED		 682
683 temp = I915_READ(DP_TP_STATUS(PORT_E));
684 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 685 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 686
687 /* Enable normal pixel sending for FDI */
688 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 689 DP_TP_CTL_FDI_AUTOTRAIN |
690 DP_TP_CTL_LINK_TRAIN_NORMAL |
691 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
692 DP_TP_CTL_ENABLE);
c82e4d26 693
04945641 694 return;
c82e4d26 695 }
04945641 696
248138b5
PZ		 697 temp = I915_READ(DDI_BUF_CTL(PORT_E));
698 temp &= ~DDI_BUF_CTL_ENABLE;
699 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
700 POSTING_READ(DDI_BUF_CTL(PORT_E));
701
04945641 702 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 703 temp = I915_READ(DP_TP_CTL(PORT_E));
704 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
705 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
706 I915_WRITE(DP_TP_CTL(PORT_E), temp);
707 POSTING_READ(DP_TP_CTL(PORT_E));
708
709 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 710
711 rx_ctl_val &= ~FDI_RX_ENABLE;
712 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 713 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 714
715 /* Reset FDI_RX_MISC pwrdn lanes */
716 temp = I915_READ(_FDI_RXA_MISC);
717 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
718 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
719 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 720 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 721 }
722
04945641 723 DRM_ERROR("FDI link training failed!\n");
c82e4d26 724}
0e72a5b5 725
44905a27
DA		 726void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
727{
728 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
729 struct intel_digital_port *intel_dig_port =
730 enc_to_dig_port(&encoder->base);
731
732 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 733 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
44905a27
DA		 734 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
735
736}
737
8d9ddbcb
PZ		 738static struct intel_encoder *
739intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
740{
741 struct drm_device *dev = crtc->dev;
742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
743 struct intel_encoder *intel_encoder, *ret = NULL;
744 int num_encoders = 0;
745
746 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
747 ret = intel_encoder;
748 num_encoders++;
749 }
750
751 if (num_encoders != 1)
84f44ce7
VS		 752 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
753 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 754
755 BUG_ON(ret == NULL);
756 return ret;
757}
758
bcddf610 759struct intel_encoder *
3165c074 760intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 761{
3165c074
ACO		 762 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
763 struct intel_encoder *ret = NULL;
764 struct drm_atomic_state *state;
da3ced29
ACO		 765 struct drm_connector *connector;
766 struct drm_connector_state *connector_state;
d0737e1d 767 int num_encoders = 0;
3165c074 768 int i;
d0737e1d 769
3165c074
ACO		 770 state = crtc_state->base.state;
771
da3ced29
ACO		 772 for_each_connector_in_state(state, connector, connector_state, i) {
773 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 774 continue;
775
da3ced29 776 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 777 num_encoders++;
d0737e1d
ACO		 778 }
779
780 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
781 pipe_name(crtc->pipe));
782
783 BUG_ON(ret == NULL);
784 return ret;
785}
786
1c0b85c5 787#define LC_FREQ 2700
27893390 788#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 789
790#define P_MIN 2
791#define P_MAX 64
792#define P_INC 2
793
794/* Constraints for PLL good behavior */
795#define REF_MIN 48
796#define REF_MAX 400
797#define VCO_MIN 2400
798#define VCO_MAX 4800
799
27893390
DL		 800#define abs_diff(a, b) ({ \
801 typeof(a) __a = (a); \
802 typeof(b) __b = (b); \
803 (void) (&__a == &__b); \
804 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5 805
63582983 806struct hsw_wrpll_rnp {
1c0b85c5
DL		 807 unsigned p, n2, r2;
808};
809
63582983 810static unsigned hsw_wrpll_get_budget_for_freq(int clock)
6441ab5f 811{
1c0b85c5
DL		 812 unsigned budget;
813
814 switch (clock) {
815 case 25175000:
816 case 25200000:
817 case 27000000:
818 case 27027000:
819 case 37762500:
820 case 37800000:
821 case 40500000:
822 case 40541000:
823 case 54000000:
824 case 54054000:
825 case 59341000:
826 case 59400000:
827 case 72000000:
828 case 74176000:
829 case 74250000:
830 case 81000000:
831 case 81081000:
832 case 89012000:
833 case 89100000:
834 case 108000000:
835 case 108108000:
836 case 111264000:
837 case 111375000:
838 case 148352000:
839 case 148500000:
840 case 162000000:
841 case 162162000:
842 case 222525000:
843 case 222750000:
844 case 296703000:
845 case 297000000:
846 budget = 0;
847 break;
848 case 233500000:
849 case 245250000:
850 case 247750000:
851 case 253250000:
852 case 298000000:
853 budget = 1500;
854 break;
855 case 169128000:
856 case 169500000:
857 case 179500000:
858 case 202000000:
859 budget = 2000;
860 break;
861 case 256250000:
862 case 262500000:
863 case 270000000:
864 case 272500000:
865 case 273750000:
866 case 280750000:
867 case 281250000:
868 case 286000000:
869 case 291750000:
870 budget = 4000;
871 break;
872 case 267250000:
873 case 268500000:
874 budget = 5000;
875 break;
876 default:
877 budget = 1000;
878 break;
879 }
6441ab5f 880
1c0b85c5
DL		 881 return budget;
882}
883
63582983
DL		 884static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
885 unsigned r2, unsigned n2, unsigned p,
886 struct hsw_wrpll_rnp *best)
1c0b85c5
DL		 887{
888 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 889
1c0b85c5
DL		 890 /* No best (r,n,p) yet */
891 if (best->p == 0) {
892 best->p = p;
893 best->n2 = n2;
894 best->r2 = r2;
895 return;
896 }
6441ab5f 897
1c0b85c5
DL		 898 /*
899 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
900 * freq2k.
901 *
902 * delta = 1e6 *
903 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
904 * freq2k;
905 *
906 * and we would like delta <= budget.
907 *
908 * If the discrepancy is above the PPM-based budget, always prefer to
909 * improve upon the previous solution. However, if you're within the
910 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
911 */
912 a = freq2k * budget * p * r2;
913 b = freq2k * budget * best->p * best->r2;
27893390
DL		 914 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
915 diff_best = abs_diff(freq2k * best->p * best->r2,
916 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 917 c = 1000000 * diff;
918 d = 1000000 * diff_best;
919
920 if (a < c && b < d) {
921 /* If both are above the budget, pick the closer */
922 if (best->p * best->r2 * diff < p * r2 * diff_best) {
923 best->p = p;
924 best->n2 = n2;
925 best->r2 = r2;
926 }
927 } else if (a >= c && b < d) {
928 /* If A is below the threshold but B is above it? Update. */
929 best->p = p;
930 best->n2 = n2;
931 best->r2 = r2;
932 } else if (a >= c && b >= d) {
933 /* Both are below the limit, so pick the higher n2/(r2*r2) */
934 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
935 best->p = p;
936 best->n2 = n2;
937 best->r2 = r2;
938 }
939 }
940 /* Otherwise a < c && b >= d, do nothing */
941}
942
63582983 943static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
11578553
JB		 944{
945 int refclk = LC_FREQ;
946 int n, p, r;
947 u32 wrpll;
948
949 wrpll = I915_READ(reg);
114fe488
DV		 950 switch (wrpll & WRPLL_PLL_REF_MASK) {
951 case WRPLL_PLL_SSC:
952 case WRPLL_PLL_NON_SSC:
11578553
JB		 953 /*
954 * We could calculate spread here, but our checking
955 * code only cares about 5% accuracy, and spread is a max of
956 * 0.5% downspread.
957 */
958 refclk = 135;
959 break;
114fe488 960 case WRPLL_PLL_LCPLL:
11578553
JB		 961 refclk = LC_FREQ;
962 break;
963 default:
964 WARN(1, "bad wrpll refclk\n");
965 return 0;
966 }
967
968 r = wrpll & WRPLL_DIVIDER_REF_MASK;
969 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
970 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
971
20f0ec16
JB		 972 /* Convert to KHz, p & r have a fixed point portion */
973 return (refclk * n * 100) / (p * r);
11578553
JB		 974}
975
540e732c
S		 976static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
977 uint32_t dpll)
978{
979 uint32_t cfgcr1_reg, cfgcr2_reg;
980 uint32_t cfgcr1_val, cfgcr2_val;
981 uint32_t p0, p1, p2, dco_freq;
982
983 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
984 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
985
986 cfgcr1_val = I915_READ(cfgcr1_reg);
987 cfgcr2_val = I915_READ(cfgcr2_reg);
988
989 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
990 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
991
992 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
993 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
994 else
995 p1 = 1;
996
997
998 switch (p0) {
999 case DPLL_CFGCR2_PDIV_1:
1000 p0 = 1;
1001 break;
1002 case DPLL_CFGCR2_PDIV_2:
1003 p0 = 2;
1004 break;
1005 case DPLL_CFGCR2_PDIV_3:
1006 p0 = 3;
1007 break;
1008 case DPLL_CFGCR2_PDIV_7:
1009 p0 = 7;
1010 break;
1011 }
1012
1013 switch (p2) {
1014 case DPLL_CFGCR2_KDIV_5:
1015 p2 = 5;
1016 break;
1017 case DPLL_CFGCR2_KDIV_2:
1018 p2 = 2;
1019 break;
1020 case DPLL_CFGCR2_KDIV_3:
1021 p2 = 3;
1022 break;
1023 case DPLL_CFGCR2_KDIV_1:
1024 p2 = 1;
1025 break;
1026 }
1027
1028 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1029
1030 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1031 1000) / 0x8000;
1032
1033 return dco_freq / (p0 * p1 * p2 * 5);
1034}
1035
398a017e
VS		 1036static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1037{
1038 int dotclock;
1039
1040 if (pipe_config->has_pch_encoder)
1041 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1042 &pipe_config->fdi_m_n);
1043 else if (pipe_config->has_dp_encoder)
1044 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1045 &pipe_config->dp_m_n);
1046 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1047 dotclock = pipe_config->port_clock * 2 / 3;
1048 else
1049 dotclock = pipe_config->port_clock;
1050
1051 if (pipe_config->pixel_multiplier)
1052 dotclock /= pipe_config->pixel_multiplier;
1053
1054 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1055}
540e732c
S		 1056
1057static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1058 struct intel_crtc_state *pipe_config)
540e732c
S		 1059{
1060 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 1061 int link_clock = 0;
1062 uint32_t dpll_ctl1, dpll;
1063
134ffa44 1064 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 1065
1066 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1067
1068 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1069 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1070 } else {
71cd8423
DL		 1071 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1072 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1073
1074 switch (link_clock) {
71cd8423 1075 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1076 link_clock = 81000;
1077 break;
71cd8423 1078 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1079 link_clock = 108000;
1080 break;
71cd8423 1081 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1082 link_clock = 135000;
1083 break;
71cd8423 1084 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1085 link_clock = 162000;
1086 break;
71cd8423 1087 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1088 link_clock = 216000;
1089 break;
71cd8423 1090 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1091 link_clock = 270000;
1092 break;
1093 default:
1094 WARN(1, "Unsupported link rate\n");
1095 break;
1096 }
1097 link_clock *= 2;
1098 }
1099
1100 pipe_config->port_clock = link_clock;
1101
398a017e 1102 ddi_dotclock_get(pipe_config);
540e732c
S		 1103}
1104
3d51278a 1105static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1106 struct intel_crtc_state *pipe_config)
11578553
JB		 1107{
1108 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 1109 int link_clock = 0;
1110 u32 val, pll;
1111
26804afd 1112 val = pipe_config->ddi_pll_sel;
11578553
JB		 1113 switch (val & PORT_CLK_SEL_MASK) {
1114 case PORT_CLK_SEL_LCPLL_810:
1115 link_clock = 81000;
1116 break;
1117 case PORT_CLK_SEL_LCPLL_1350:
1118 link_clock = 135000;
1119 break;
1120 case PORT_CLK_SEL_LCPLL_2700:
1121 link_clock = 270000;
1122 break;
1123 case PORT_CLK_SEL_WRPLL1:
63582983 1124 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
11578553
JB		 1125 break;
1126 case PORT_CLK_SEL_WRPLL2:
63582983 1127 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
11578553
JB		 1128 break;
1129 case PORT_CLK_SEL_SPLL:
1130 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1131 if (pll == SPLL_PLL_FREQ_810MHz)
1132 link_clock = 81000;
1133 else if (pll == SPLL_PLL_FREQ_1350MHz)
1134 link_clock = 135000;
1135 else if (pll == SPLL_PLL_FREQ_2700MHz)
1136 link_clock = 270000;
1137 else {
1138 WARN(1, "bad spll freq\n");
1139 return;
1140 }
1141 break;
1142 default:
1143 WARN(1, "bad port clock sel\n");
1144 return;
1145 }
1146
1147 pipe_config->port_clock = link_clock * 2;
1148
398a017e 1149 ddi_dotclock_get(pipe_config);
11578553
JB		 1150}
1151
977bb38d
S		 1152static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1153 enum intel_dpll_id dpll)
1154{
aa610dcb
ID		 1155 struct intel_shared_dpll *pll;
1156 struct intel_dpll_hw_state *state;
1157 intel_clock_t clock;
1158
1159 /* For DDI ports we always use a shared PLL. */
1160 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1161 return 0;
1162
1163 pll = &dev_priv->shared_dplls[dpll];
1164 state = &pll->config.hw_state;
1165
1166 clock.m1 = 2;
1167 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1168 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1169 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1170 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1171 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1172 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1173
1174 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1175}
1176
1177static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1178 struct intel_crtc_state *pipe_config)
1179{
1180 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1181 enum port port = intel_ddi_get_encoder_port(encoder);
1182 uint32_t dpll = port;
1183
398a017e 1184 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 1185
398a017e 1186 ddi_dotclock_get(pipe_config);
977bb38d
S		 1187}
1188
3d51278a 1189void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1190 struct intel_crtc_state *pipe_config)
3d51278a 1191{
22606a18
DL		 1192 struct drm_device *dev = encoder->base.dev;
1193
1194 if (INTEL_INFO(dev)->gen <= 8)
1195 hsw_ddi_clock_get(encoder, pipe_config);
977bb38d 1196 else if (IS_SKYLAKE(dev))
22606a18 1197 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1198 else if (IS_BROXTON(dev))
1199 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1200}
1201
1c0b85c5 1202static void
d664c0ce
DL		 1203hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1204 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1205{
1206 uint64_t freq2k;
1207 unsigned p, n2, r2;
63582983 1208 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1c0b85c5
DL		 1209 unsigned budget;
1210
1211 freq2k = clock / 100;
1212
63582983 1213 budget = hsw_wrpll_get_budget_for_freq(clock);
1c0b85c5
DL		 1214
1215 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1216 * and directly pass the LC PLL to it. */
1217 if (freq2k == 5400000) {
1218 *n2_out = 2;
1219 *p_out = 1;
1220 *r2_out = 2;
1221 return;
1222 }
1223
1224 /*
1225 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1226 * the WR PLL.
1227 *
1228 * We want R so that REF_MIN <= Ref <= REF_MAX.
1229 * Injecting R2 = 2 * R gives:
1230 * REF_MAX * r2 > LC_FREQ * 2 and
1231 * REF_MIN * r2 < LC_FREQ * 2
1232 *
1233 * Which means the desired boundaries for r2 are:
1234 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1235 *
1236 */
1237 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1238 r2 <= LC_FREQ * 2 / REF_MIN;
1239 r2++) {
1240
1241 /*
1242 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1243 *
1244 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1245 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1246 * VCO_MAX * r2 > n2 * LC_FREQ and
1247 * VCO_MIN * r2 < n2 * LC_FREQ)
1248 *
1249 * Which means the desired boundaries for n2 are:
1250 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1251 */
1252 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1253 n2 <= VCO_MAX * r2 / LC_FREQ;
1254 n2++) {
1255
1256 for (p = P_MIN; p <= P_MAX; p += P_INC)
63582983
DL		 1257 hsw_wrpll_update_rnp(freq2k, budget,
1258 r2, n2, p, &best);
1c0b85c5
DL		 1259 }
1260 }
6441ab5f 1261
1c0b85c5
DL		 1262 *n2_out = best.n2;
1263 *p_out = best.p;
1264 *r2_out = best.r2;
6441ab5f
PZ		 1265}
1266
0220ab6e 1267static bool
d664c0ce 1268hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1269 struct intel_crtc_state *crtc_state,
d664c0ce
DL		 1270 struct intel_encoder *intel_encoder,
1271 int clock)
6441ab5f 1272{
d664c0ce 1273 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1274 struct intel_shared_dpll *pll;
716c2e55 1275 uint32_t val;
1c0b85c5 1276 unsigned p, n2, r2;
6441ab5f 1277
d664c0ce 1278 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1279
114fe488 1280 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1281 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1282 WRPLL_DIVIDER_POST(p);
1283
dd3cd74a
ACO		 1284 memset(&crtc_state->dpll_hw_state, 0,
1285 sizeof(crtc_state->dpll_hw_state));
1286
190f68c5 1287 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1288
190f68c5 1289 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1290 if (pll == NULL) {
1291 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1292 pipe_name(intel_crtc->pipe));
1293 return false;
0694001b 1294 }
d452c5b6 1295
190f68c5 1296 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 1297 }
1298
6441ab5f
PZ		 1299 return true;
1300}
1301
dc253813
DL		 1302struct skl_wrpll_context {
1303 uint64_t min_deviation; /* current minimal deviation */
1304 uint64_t central_freq; /* chosen central freq */
1305 uint64_t dco_freq; /* chosen dco freq */
1306 unsigned int p; /* chosen divider */
1307};
1308
1309static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1310{
1311 memset(ctx, 0, sizeof(*ctx));
1312
1313 ctx->min_deviation = U64_MAX;
1314}
1315
1316/* DCO freq must be within +1%/-6% of the DCO central freq */
1317#define SKL_DCO_MAX_PDEVIATION 100
1318#define SKL_DCO_MAX_NDEVIATION 600
1319
1320static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1321 uint64_t central_freq,
1322 uint64_t dco_freq,
1323 unsigned int divider)
1324{
1325 uint64_t deviation;
1326
1327 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1328 central_freq);
1329
1330 /* positive deviation */
1331 if (dco_freq >= central_freq) {
1332 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1333 deviation < ctx->min_deviation) {
1334 ctx->min_deviation = deviation;
1335 ctx->central_freq = central_freq;
1336 ctx->dco_freq = dco_freq;
1337 ctx->p = divider;
1338 }
1339 /* negative deviation */
1340 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1341 deviation < ctx->min_deviation) {
1342 ctx->min_deviation = deviation;
1343 ctx->central_freq = central_freq;
1344 ctx->dco_freq = dco_freq;
1345 ctx->p = divider;
1346 }
dc253813
DL		 1347}
1348
1349static void skl_wrpll_get_multipliers(unsigned int p,
1350 unsigned int *p0 /* out */,
1351 unsigned int *p1 /* out */,
1352 unsigned int *p2 /* out */)
1353{
1354 /* even dividers */
1355 if (p % 2 == 0) {
1356 unsigned int half = p / 2;
1357
1358 if (half == 1 || half == 2 || half == 3 || half == 5) {
1359 *p0 = 2;
1360 *p1 = 1;
1361 *p2 = half;
1362 } else if (half % 2 == 0) {
1363 *p0 = 2;
1364 *p1 = half / 2;
1365 *p2 = 2;
1366 } else if (half % 3 == 0) {
1367 *p0 = 3;
1368 *p1 = half / 3;
1369 *p2 = 2;
1370 } else if (half % 7 == 0) {
1371 *p0 = 7;
1372 *p1 = half / 7;
1373 *p2 = 2;
1374 }
1375 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1376 *p0 = 3;
1377 *p1 = 1;
1378 *p2 = p / 3;
1379 } else if (p == 5 || p == 7) {
1380 *p0 = p;
1381 *p1 = 1;
1382 *p2 = 1;
1383 } else if (p == 15) {
1384 *p0 = 3;
1385 *p1 = 1;
1386 *p2 = 5;
1387 } else if (p == 21) {
1388 *p0 = 7;
1389 *p1 = 1;
1390 *p2 = 3;
1391 } else if (p == 35) {
1392 *p0 = 7;
1393 *p1 = 1;
1394 *p2 = 5;
1395 }
1396}
1397
82d35437
S		 1398struct skl_wrpll_params {
1399 uint32_t dco_fraction;
1400 uint32_t dco_integer;
1401 uint32_t qdiv_ratio;
1402 uint32_t qdiv_mode;
1403 uint32_t kdiv;
1404 uint32_t pdiv;
1405 uint32_t central_freq;
1406};
1407
76516fbc
DL		 1408static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1409 uint64_t afe_clock,
1410 uint64_t central_freq,
1411 uint32_t p0, uint32_t p1, uint32_t p2)
1412{
1413 uint64_t dco_freq;
1414
76516fbc
DL		 1415 switch (central_freq) {
1416 case 9600000000ULL:
1417 params->central_freq = 0;
1418 break;
1419 case 9000000000ULL:
1420 params->central_freq = 1;
1421 break;
1422 case 8400000000ULL:
1423 params->central_freq = 3;
1424 }
1425
1426 switch (p0) {
1427 case 1:
1428 params->pdiv = 0;
1429 break;
1430 case 2:
1431 params->pdiv = 1;
1432 break;
1433 case 3:
1434 params->pdiv = 2;
1435 break;
1436 case 7:
1437 params->pdiv = 4;
1438 break;
1439 default:
1440 WARN(1, "Incorrect PDiv\n");
1441 }
1442
1443 switch (p2) {
1444 case 5:
1445 params->kdiv = 0;
1446 break;
1447 case 2:
1448 params->kdiv = 1;
1449 break;
1450 case 3:
1451 params->kdiv = 2;
1452 break;
1453 case 1:
1454 params->kdiv = 3;
1455 break;
1456 default:
1457 WARN(1, "Incorrect KDiv\n");
1458 }
1459
1460 params->qdiv_ratio = p1;
1461 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1462
1463 dco_freq = p0 * p1 * p2 * afe_clock;
1464
1465 /*
1466 * Intermediate values are in Hz.
1467 * Divide by MHz to match bsepc
1468 */
30a7862d 1469 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
76516fbc 1470 params->dco_fraction =
30a7862d
DL		 1471 div_u64((div_u64(dco_freq, 24) -
1472 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
76516fbc
DL		 1473}
1474
318bd821 1475static bool
82d35437
S		 1476skl_ddi_calculate_wrpll(int clock /* in Hz */,
1477 struct skl_wrpll_params *wrpll_params)
1478{
1479 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1480 uint64_t dco_central_freq[3] = {8400000000ULL,
1481 9000000000ULL,
1482 9600000000ULL};
dc253813
DL		 1483 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1484 24, 28, 30, 32, 36, 40, 42, 44,
1485 48, 52, 54, 56, 60, 64, 66, 68,
1486 70, 72, 76, 78, 80, 84, 88, 90,
1487 92, 96, 98 };
1488 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1489 static const struct {
1490 const int *list;
1491 int n_dividers;
1492 } dividers[] = {
1493 { even_dividers, ARRAY_SIZE(even_dividers) },
1494 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1495 };
1496 struct skl_wrpll_context ctx;
1497 unsigned int dco, d, i;
1498 unsigned int p0, p1, p2;
1499
1500 skl_wrpll_context_init(&ctx);
1501
1502 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1503 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1504 for (i = 0; i < dividers[d].n_dividers; i++) {
1505 unsigned int p = dividers[d].list[i];
1506 uint64_t dco_freq = p * afe_clock;
1507
1508 skl_wrpll_try_divider(&ctx,
1509 dco_central_freq[dco],
1510 dco_freq,
1511 p);
e7ad9878
DL		 1512 /*
1513 * Skip the remaining dividers if we're sure to
1514 * have found the definitive divider, we can't
1515 * improve a 0 deviation.
1516 */
1517 if (ctx.min_deviation == 0)
1518 goto skip_remaining_dividers;
82d35437
S		 1519 }
1520 }
267db663 1521
e7ad9878 1522skip_remaining_dividers:
267db663
DL		 1523 /*
1524 * If a solution is found with an even divider, prefer
1525 * this one.
1526 */
1527 if (d == 0 && ctx.p)
1528 break;
82d35437
S		 1529 }
1530
dc253813
DL		 1531 if (!ctx.p) {
1532 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
318bd821 1533 return false;
dc253813 1534 }
82d35437 1535
dc253813
DL		 1536 /*
1537 * gcc incorrectly analyses that these can be used without being
1538 * initialized. To be fair, it's hard to guess.
1539 */
1540 p0 = p1 = p2 = 0;
1541 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1542 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1543 p0, p1, p2);
318bd821
DL		 1544
1545 return true;
82d35437
S		 1546}
1547
82d35437
S		 1548static bool
1549skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1550 struct intel_crtc_state *crtc_state,
82d35437
S		 1551 struct intel_encoder *intel_encoder,
1552 int clock)
1553{
1554 struct intel_shared_dpll *pll;
1555 uint32_t ctrl1, cfgcr1, cfgcr2;
1556
1557 /*
1558 * See comment in intel_dpll_hw_state to understand why we always use 0
1559 * as the DPLL id in this function.
1560 */
1561
1562 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1563
1564 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1565 struct skl_wrpll_params wrpll_params = { 0, };
1566
1567 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1568
318bd821
DL		 1569 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1570 return false;
82d35437
S		 1571
1572 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1573 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1574 wrpll_params.dco_integer;
1575
1576 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1577 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1578 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1579 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1580 wrpll_params.central_freq;
1581 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
840b32b7
VS		 1582 switch (crtc_state->port_clock / 2) {
1583 case 81000:
71cd8423 1584 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
82d35437 1585 break;
840b32b7 1586 case 135000:
71cd8423 1587 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
82d35437 1588 break;
840b32b7 1589 case 270000:
71cd8423 1590 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
82d35437
S		 1591 break;
1592 }
1593
1594 cfgcr1 = cfgcr2 = 0;
1595 } else /* eDP */
1596 return true;
1597
dd3cd74a
ACO		 1598 memset(&crtc_state->dpll_hw_state, 0,
1599 sizeof(crtc_state->dpll_hw_state));
1600
190f68c5
ACO		 1601 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1602 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1603 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1604
190f68c5 1605 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1606 if (pll == NULL) {
1607 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1608 pipe_name(intel_crtc->pipe));
1609 return false;
1610 }
1611
1612 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1613 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1614
1615 return true;
1616}
0220ab6e 1617
d683f3bc
S		 1618/* bxt clock parameters */
1619struct bxt_clk_div {
64987fc5 1620 int clock;
d683f3bc
S		 1621 uint32_t p1;
1622 uint32_t p2;
1623 uint32_t m2_int;
1624 uint32_t m2_frac;
1625 bool m2_frac_en;
1626 uint32_t n;
d683f3bc
S		 1627};
1628
1629/* pre-calculated values for DP linkrates */
64987fc5
SJ		 1630static const struct bxt_clk_div bxt_dp_clk_val[] = {
1631 {162000, 4, 2, 32, 1677722, 1, 1},
1632 {270000, 4, 1, 27, 0, 0, 1},
1633 {540000, 2, 1, 27, 0, 0, 1},
1634 {216000, 3, 2, 32, 1677722, 1, 1},
1635 {243000, 4, 1, 24, 1258291, 1, 1},
1636 {324000, 4, 1, 32, 1677722, 1, 1},
1637 {432000, 3, 1, 32, 1677722, 1, 1}
d683f3bc
S		 1638};
1639
1640static bool
1641bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1642 struct intel_crtc_state *crtc_state,
1643 struct intel_encoder *intel_encoder,
1644 int clock)
1645{
1646 struct intel_shared_dpll *pll;
1647 struct bxt_clk_div clk_div = {0};
b6dc71f3
VK		 1648 int vco = 0;
1649 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
e6292556 1650 uint32_t lanestagger;
d683f3bc
S		 1651
1652 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1653 intel_clock_t best_clock;
1654
1655 /* Calculate HDMI div */
1656 /*
1657 * FIXME: tie the following calculation into
1658 * i9xx_crtc_compute_clock
1659 */
1660 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1661 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1662 clock, pipe_name(intel_crtc->pipe));
1663 return false;
1664 }
1665
1666 clk_div.p1 = best_clock.p1;
1667 clk_div.p2 = best_clock.p2;
1668 WARN_ON(best_clock.m1 != 2);
1669 clk_div.n = best_clock.n;
1670 clk_div.m2_int = best_clock.m2 >> 22;
1671 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1672 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1673
b6dc71f3 1674 vco = best_clock.vco;
d683f3bc
S		 1675 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1676 intel_encoder->type == INTEL_OUTPUT_EDP) {
64987fc5 1677 int i;
d683f3bc 1678
64987fc5
SJ		 1679 clk_div = bxt_dp_clk_val[0];
1680 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1681 if (bxt_dp_clk_val[i].clock == clock) {
1682 clk_div = bxt_dp_clk_val[i];
1683 break;
1684 }
d683f3bc 1685 }
b6dc71f3
VK		 1686 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1687 }
1688
e6292556 1689 if (vco >= 6200000 && vco <= 6700000) {
b6dc71f3
VK		 1690 prop_coef = 4;
1691 int_coef = 9;
1692 gain_ctl = 3;
1693 targ_cnt = 8;
1694 } else if ((vco > 5400000 && vco < 6200000) ||
1695 (vco >= 4800000 && vco < 5400000)) {
1696 prop_coef = 5;
1697 int_coef = 11;
1698 gain_ctl = 3;
1699 targ_cnt = 9;
b6dc71f3
VK		 1700 } else if (vco == 5400000) {
1701 prop_coef = 3;
1702 int_coef = 8;
1703 gain_ctl = 1;
1704 targ_cnt = 9;
1705 } else {
1706 DRM_ERROR("Invalid VCO\n");
1707 return false;
d683f3bc
S		 1708 }
1709
dd3cd74a
ACO		 1710 memset(&crtc_state->dpll_hw_state, 0,
1711 sizeof(crtc_state->dpll_hw_state));
1712
e0681e38
VK		 1713 if (clock > 270000)
1714 lanestagger = 0x18;
1715 else if (clock > 135000)
1716 lanestagger = 0x0d;
1717 else if (clock > 67000)
1718 lanestagger = 0x07;
1719 else if (clock > 33000)
1720 lanestagger = 0x04;
1721 else
1722 lanestagger = 0x02;
1723
d683f3bc
S		 1724 crtc_state->dpll_hw_state.ebb0 =
1725 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1726 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1727 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1728 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1729
1730 if (clk_div.m2_frac_en)
1731 crtc_state->dpll_hw_state.pll3 =
1732 PORT_PLL_M2_FRAC_ENABLE;
1733
1734 crtc_state->dpll_hw_state.pll6 =
b6dc71f3 1735 prop_coef | PORT_PLL_INT_COEFF(int_coef);
d683f3bc 1736 crtc_state->dpll_hw_state.pll6 |=
b6dc71f3
VK		 1737 PORT_PLL_GAIN_CTL(gain_ctl);
1738
1739 crtc_state->dpll_hw_state.pll8 = targ_cnt;
d683f3bc 1740
05712c15
ID		 1741 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1742
e6292556
VK		 1743 crtc_state->dpll_hw_state.pll10 =
1744 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1745 | PORT_PLL_DCO_AMP_OVR_EN_H;
d683f3bc 1746
05712c15
ID		 1747 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1748
d683f3bc 1749 crtc_state->dpll_hw_state.pcsdw12 =
e0681e38 1750 LANESTAGGER_STRAP_OVRD | lanestagger;
d683f3bc
S		 1751
1752 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1753 if (pll == NULL) {
1754 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1755 pipe_name(intel_crtc->pipe));
1756 return false;
1757 }
1758
1759 /* shared DPLL id 0 is DPLL A */
1760 crtc_state->ddi_pll_sel = pll->id;
1761
1762 return true;
1763}
1764
0220ab6e
DL		 1765/*
1766 * Tries to find a *shared* PLL for the CRTC and store it in
1767 * intel_crtc->ddi_pll_sel.
1768 *
1769 * For private DPLLs, compute_config() should do the selection for us. This
1770 * function should be folded into compute_config() eventually.
1771 */
190f68c5
ACO		 1772bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1773 struct intel_crtc_state *crtc_state)
0220ab6e 1774{
82d35437 1775 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1776 struct intel_encoder *intel_encoder =
3165c074 1777 intel_ddi_get_crtc_new_encoder(crtc_state);
190f68c5 1778 int clock = crtc_state->port_clock;
0220ab6e 1779
82d35437 1780 if (IS_SKYLAKE(dev))
190f68c5
ACO		 1781 return skl_ddi_pll_select(intel_crtc, crtc_state,
1782 intel_encoder, clock);
d683f3bc
S		 1783 else if (IS_BROXTON(dev))
1784 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1785 intel_encoder, clock);
82d35437 1786 else
190f68c5
ACO		 1787 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1788 intel_encoder, clock);
0220ab6e
DL		 1789}
1790
dae84799
PZ		 1791void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1792{
1793 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1795 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1796 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1797 int type = intel_encoder->type;
1798 uint32_t temp;
1799
0e32b39c 1800 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1801 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1802 switch (intel_crtc->config->pipe_bpp) {
dae84799 1803 case 18:
c9809791 1804 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1805 break;
1806 case 24:
c9809791 1807 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1808 break;
1809 case 30:
c9809791 1810 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1811 break;
1812 case 36:
c9809791 1813 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1814 break;
1815 default:
4e53c2e0 1816 BUG();
dae84799 1817 }
c9809791 1818 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1819 }
1820}
1821
0e32b39c
DA		 1822void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1823{
1824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1825 struct drm_device *dev = crtc->dev;
1826 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1827 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1828 uint32_t temp;
1829 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1830 if (state == true)
1831 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1832 else
1833 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1834 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1835}
1836
8228c251 1837void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1838{
1839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1840 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1841 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1842 struct drm_device *dev = crtc->dev;
1843 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1844 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1845 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1846 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1847 int type = intel_encoder->type;
8d9ddbcb
PZ		 1848 uint32_t temp;
1849
ad80a810
PZ		 1850 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1851 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1852 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1853
6e3c9717 1854 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1855 case 18:
ad80a810 1856 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1857 break;
1858 case 24:
ad80a810 1859 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1860 break;
1861 case 30:
ad80a810 1862 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1863 break;
1864 case 36:
ad80a810 1865 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1866 break;
1867 default:
4e53c2e0 1868 BUG();
dfcef252 1869 }
72662e10 1870
6e3c9717 1871 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1872 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1873 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1874 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1875
e6f0bfc4
PZ		 1876 if (cpu_transcoder == TRANSCODER_EDP) {
1877 switch (pipe) {
1878 case PIPE_A:
c7670b10
PZ		 1879 /* On Haswell, can only use the always-on power well for
1880 * eDP when not using the panel fitter, and when not
1881 * using motion blur mitigation (which we don't
1882 * support). */
fabf6e51 1883 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1884 (intel_crtc->config->pch_pfit.enabled ||
1885 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1886 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1887 else
1888 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1889 break;
1890 case PIPE_B:
1891 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1892 break;
1893 case PIPE_C:
1894 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1895 break;
1896 default:
1897 BUG();
1898 break;
1899 }
1900 }
1901
7739c33b 1902 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1903 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1904 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1905 else
ad80a810 1906 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1907
7739c33b 1908 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1909 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1910 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1911
1912 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1913 type == INTEL_OUTPUT_EDP) {
1914 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1915
0e32b39c
DA		 1916 if (intel_dp->is_mst) {
1917 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1918 } else
1919 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1920
1921 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1922 } else if (type == INTEL_OUTPUT_DP_MST) {
1923 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1924
1925 if (intel_dp->is_mst) {
1926 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1927 } else
1928 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1929
17aa6be9 1930 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1931 } else {
84f44ce7
VS		 1932 WARN(1, "Invalid encoder type %d for pipe %c\n",
1933 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1934 }
1935
ad80a810 1936 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1937}
72662e10 1938
ad80a810
PZ		 1939void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1940 enum transcoder cpu_transcoder)
8d9ddbcb 1941{
ad80a810 1942 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1943 uint32_t val = I915_READ(reg);
1944
0e32b39c 1945 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1946 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1947 I915_WRITE(reg, val);
72662e10
ED		 1948}
1949
bcbc889b
PZ		 1950bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1951{
1952 struct drm_device *dev = intel_connector->base.dev;
1953 struct drm_i915_private *dev_priv = dev->dev_private;
1954 struct intel_encoder *intel_encoder = intel_connector->encoder;
1955 int type = intel_connector->base.connector_type;
1956 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1957 enum pipe pipe = 0;
1958 enum transcoder cpu_transcoder;
882244a3 1959 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1960 uint32_t tmp;
1961
882244a3 1962 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1963 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1964 return false;
1965
bcbc889b
PZ		 1966 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1967 return false;
1968
1969 if (port == PORT_A)
1970 cpu_transcoder = TRANSCODER_EDP;
1971 else
1a240d4d 1972 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1973
1974 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1975
1976 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1977 case TRANS_DDI_MODE_SELECT_HDMI:
1978 case TRANS_DDI_MODE_SELECT_DVI:
1979 return (type == DRM_MODE_CONNECTOR_HDMIA);
1980
1981 case TRANS_DDI_MODE_SELECT_DP_SST:
1982 if (type == DRM_MODE_CONNECTOR_eDP)
1983 return true;
bcbc889b 1984 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1985 case TRANS_DDI_MODE_SELECT_DP_MST:
1986 /* if the transcoder is in MST state then
1987 * connector isn't connected */
1988 return false;
bcbc889b
PZ		 1989
1990 case TRANS_DDI_MODE_SELECT_FDI:
1991 return (type == DRM_MODE_CONNECTOR_VGA);
1992
1993 default:
1994 return false;
1995 }
1996}
1997
85234cdc
DV		 1998bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1999 enum pipe *pipe)
2000{
2001 struct drm_device *dev = encoder->base.dev;
2002 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 2003 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 2004 enum intel_display_power_domain power_domain;
85234cdc
DV		 2005 u32 tmp;
2006 int i;
2007
6d129bea 2008 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 2009 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 2010 return false;
2011
fe43d3f5 2012 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 2013
2014 if (!(tmp & DDI_BUF_CTL_ENABLE))
2015 return false;
2016
ad80a810
PZ		 2017 if (port == PORT_A) {
2018 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 2019
ad80a810
PZ		 2020 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2021 case TRANS_DDI_EDP_INPUT_A_ON:
2022 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2023 *pipe = PIPE_A;
2024 break;
2025 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2026 *pipe = PIPE_B;
2027 break;
2028 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2029 *pipe = PIPE_C;
2030 break;
2031 }
2032
2033 return true;
2034 } else {
2035 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
2036 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
2037
2038 if ((tmp & TRANS_DDI_PORT_MASK)
2039 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 2040 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
2041 return false;
2042
ad80a810
PZ		 2043 *pipe = i;
2044 return true;
2045 }
85234cdc
DV		 2046 }
2047 }
2048
84f44ce7 2049 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 2050
22f9fe50 2051 return false;
85234cdc
DV		 2052}
2053
fc914639
PZ		 2054void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2055{
2056 struct drm_crtc *crtc = &intel_crtc->base;
2057 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2058 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2059 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 2060 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2061
bb523fc0
PZ		 2062 if (cpu_transcoder != TRANSCODER_EDP)
2063 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2064 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2065}
2066
2067void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2068{
2069 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 2070 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2071
bb523fc0
PZ		 2072 if (cpu_transcoder != TRANSCODER_EDP)
2073 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2074 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2075}
2076
f8896f5d
DW		 2077static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
2078 enum port port, int type)
2079{
2080 struct drm_i915_private *dev_priv = dev->dev_private;
2081 const struct ddi_buf_trans *ddi_translations;
2082 uint8_t iboost;
75067dde 2083 uint8_t dp_iboost, hdmi_iboost;
f8896f5d
DW		 2084 int n_entries;
2085 u32 reg;
2086
75067dde
AK		 2087 /* VBT may override standard boost values */
2088 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2089 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2090
f8896f5d 2091 if (type == INTEL_OUTPUT_DISPLAYPORT) {
75067dde
AK		 2092 if (dp_iboost) {
2093 iboost = dp_iboost;
2094 } else {
2095 ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
2096 iboost = ddi_translations[port].i_boost;
2097 }
f8896f5d 2098 } else if (type == INTEL_OUTPUT_EDP) {
75067dde
AK		 2099 if (dp_iboost) {
2100 iboost = dp_iboost;
2101 } else {
2102 ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
2103 iboost = ddi_translations[port].i_boost;
2104 }
f8896f5d 2105 } else if (type == INTEL_OUTPUT_HDMI) {
75067dde
AK		 2106 if (hdmi_iboost) {
2107 iboost = hdmi_iboost;
2108 } else {
2109 ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
2110 iboost = ddi_translations[port].i_boost;
2111 }
f8896f5d
DW		 2112 } else {
2113 return;
2114 }
2115
2116 /* Make sure that the requested I_boost is valid */
2117 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2118 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2119 return;
2120 }
2121
2122 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2123 reg &= ~BALANCE_LEG_MASK(port);
2124 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2125
2126 if (iboost)
2127 reg |= iboost << BALANCE_LEG_SHIFT(port);
2128 else
2129 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2130
2131 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2132}
2133
2134static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
2135 enum port port, int type)
96fb9f9b
VK		 2136{
2137 struct drm_i915_private *dev_priv = dev->dev_private;
2138 const struct bxt_ddi_buf_trans *ddi_translations;
2139 u32 n_entries, i;
2140 uint32_t val;
2141
2142 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2143 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2144 ddi_translations = bxt_ddi_translations_dp;
2145 } else if (type == INTEL_OUTPUT_HDMI) {
2146 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2147 ddi_translations = bxt_ddi_translations_hdmi;
2148 } else {
2149 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2150 type);
2151 return;
2152 }
2153
2154 /* Check if default value has to be used */
2155 if (level >= n_entries ||
2156 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2157 for (i = 0; i < n_entries; i++) {
2158 if (ddi_translations[i].default_index) {
2159 level = i;
2160 break;
2161 }
2162 }
2163 }
2164
2165 /*
2166 * While we write to the group register to program all lanes at once we
2167 * can read only lane registers and we pick lanes 0/1 for that.
2168 */
2169 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2170 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2171 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2172
2173 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2174 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2175 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2176 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2177 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2178
2179 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
2180 val &= ~UNIQE_TRANGE_EN_METHOD;
2181 if (ddi_translations[level].enable)
2182 val |= UNIQE_TRANGE_EN_METHOD;
2183 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2184
2185 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2186 val &= ~DE_EMPHASIS;
2187 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2188 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2189
2190 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2191 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2192 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2193}
2194
f8896f5d
DW		 2195static uint32_t translate_signal_level(int signal_levels)
2196{
2197 uint32_t level;
2198
2199 switch (signal_levels) {
2200 default:
2201 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2202 signal_levels);
2203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2204 level = 0;
2205 break;
2206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2207 level = 1;
2208 break;
2209 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2210 level = 2;
2211 break;
2212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2213 level = 3;
2214 break;
2215
2216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2217 level = 4;
2218 break;
2219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2220 level = 5;
2221 break;
2222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2223 level = 6;
2224 break;
2225
2226 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2227 level = 7;
2228 break;
2229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2230 level = 8;
2231 break;
2232
2233 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2234 level = 9;
2235 break;
2236 }
2237
2238 return level;
2239}
2240
2241uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2242{
2243 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2244 struct drm_device *dev = dport->base.base.dev;
2245 struct intel_encoder *encoder = &dport->base;
2246 uint8_t train_set = intel_dp->train_set[0];
2247 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2248 DP_TRAIN_PRE_EMPHASIS_MASK);
2249 enum port port = dport->port;
2250 uint32_t level;
2251
2252 level = translate_signal_level(signal_levels);
2253
2254 if (IS_SKYLAKE(dev))
2255 skl_ddi_set_iboost(dev, level, port, encoder->type);
2256 else if (IS_BROXTON(dev))
2257 bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
2258
2259 return DDI_BUF_TRANS_SELECT(level);
2260}
2261
00c09d70 2262static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 2263{
c19b0669 2264 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2265 struct drm_device *dev = encoder->dev;
2266 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 2267 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 2268 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2269 int type = intel_encoder->type;
96fb9f9b 2270 int hdmi_level;
6441ab5f 2271
82a4d9c0
PZ		 2272 if (type == INTEL_OUTPUT_EDP) {
2273 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 2274 intel_edp_panel_on(intel_dp);
82a4d9c0 2275 }
6441ab5f 2276
efa80add 2277 if (IS_SKYLAKE(dev)) {
6e3c9717 2278 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 2279 uint32_t val;
2280
5416d871
DL		 2281 /*
2282 * DPLL0 is used for eDP and is the only "private" DPLL (as
2283 * opposed to shared) on SKL
2284 */
2285 if (type == INTEL_OUTPUT_EDP) {
2286 WARN_ON(dpll != SKL_DPLL0);
2287
2288 val = I915_READ(DPLL_CTRL1);
2289
2290 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2291 DPLL_CTRL1_SSC(dpll) |
71cd8423 2292 DPLL_CTRL1_LINK_RATE_MASK(dpll));
6e3c9717 2293 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 2294
2295 I915_WRITE(DPLL_CTRL1, val);
2296 POSTING_READ(DPLL_CTRL1);
2297 }
2298
2299 /* DDI -> PLL mapping */
efa80add
S		 2300 val = I915_READ(DPLL_CTRL2);
2301
2302 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2303 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2304 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2305 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2306
2307 I915_WRITE(DPLL_CTRL2, val);
5416d871 2308
1ab23380 2309 } else if (INTEL_INFO(dev)->gen < 9) {
6e3c9717
ACO		 2310 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2311 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 2312 }
c19b0669 2313
82a4d9c0 2314 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 2315 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 2316
44905a27 2317 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 2318
2319 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2320 intel_dp_start_link_train(intel_dp);
2321 intel_dp_complete_link_train(intel_dp);
23f08d83 2322 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 2323 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 2324 } else if (type == INTEL_OUTPUT_HDMI) {
2325 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2326
96fb9f9b
VK		 2327 if (IS_BROXTON(dev)) {
2328 hdmi_level = dev_priv->vbt.
2329 ddi_port_info[port].hdmi_level_shift;
2330 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
2331 INTEL_OUTPUT_HDMI);
2332 }
30cf6db8 2333 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 2334 crtc->config->has_hdmi_sink,
2335 &crtc->config->base.adjusted_mode);
c19b0669 2336 }
6441ab5f
PZ		 2337}
2338
00c09d70 2339static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 2340{
2341 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2342 struct drm_device *dev = encoder->dev;
2343 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 2344 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2345 int type = intel_encoder->type;
2886e93f 2346 uint32_t val;
a836bdf9 2347 bool wait = false;
2886e93f
PZ		 2348
2349 val = I915_READ(DDI_BUF_CTL(port));
2350 if (val & DDI_BUF_CTL_ENABLE) {
2351 val &= ~DDI_BUF_CTL_ENABLE;
2352 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2353 wait = true;
2886e93f 2354 }
6441ab5f 2355
a836bdf9
PZ		 2356 val = I915_READ(DP_TP_CTL(port));
2357 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2358 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2359 I915_WRITE(DP_TP_CTL(port), val);
2360
2361 if (wait)
2362 intel_wait_ddi_buf_idle(dev_priv, port);
2363
76bb80ed 2364 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 2365 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 2366 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 2367 intel_edp_panel_vdd_on(intel_dp);
4be73780 2368 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2369 }
2370
efa80add
S		 2371 if (IS_SKYLAKE(dev))
2372 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2373 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 2374 else if (INTEL_INFO(dev)->gen < 9)
efa80add 2375 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 2376}
2377
00c09d70 2378static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 2379{
6547fef8 2380 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2381 struct drm_crtc *crtc = encoder->crtc;
2382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 2383 struct drm_device *dev = encoder->dev;
72662e10 2384 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 2385 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2386 int type = intel_encoder->type;
72662e10 2387
6547fef8 2388 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2389 struct intel_digital_port *intel_dig_port =
2390 enc_to_dig_port(encoder);
2391
6547fef8
PZ		 2392 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2393 * are ignored so nothing special needs to be done besides
2394 * enabling the port.
2395 */
876a8cdf 2396 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2397 intel_dig_port->saved_port_bits |
2398 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2399 } else if (type == INTEL_OUTPUT_EDP) {
2400 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2401
23f08d83 2402 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 2403 intel_dp_stop_link_train(intel_dp);
2404
4be73780 2405 intel_edp_backlight_on(intel_dp);
0bc12bcb 2406 intel_psr_enable(intel_dp);
c395578e 2407 intel_edp_drrs_enable(intel_dp);
6547fef8 2408 }
7b9f35a6 2409
6e3c9717 2410 if (intel_crtc->config->has_audio) {
d45a0bf5 2411 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 2412 intel_audio_codec_enable(intel_encoder);
7b9f35a6 2413 }
5ab432ef
DV		 2414}
2415
00c09d70 2416static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 2417{
d6c50ff8 2418 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2419 struct drm_crtc *crtc = encoder->crtc;
2420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 2421 int type = intel_encoder->type;
7b9f35a6
WX		 2422 struct drm_device *dev = encoder->dev;
2423 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 2424
6e3c9717 2425 if (intel_crtc->config->has_audio) {
69bfe1a9 2426 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 2427 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2428 }
2831d842 2429
d6c50ff8
PZ		 2430 if (type == INTEL_OUTPUT_EDP) {
2431 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2432
c395578e 2433 intel_edp_drrs_disable(intel_dp);
0bc12bcb 2434 intel_psr_disable(intel_dp);
4be73780 2435 intel_edp_backlight_off(intel_dp);
d6c50ff8 2436 }
72662e10 2437}
79f689aa 2438
e0b01be4
DV		 2439static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
2440 struct intel_shared_dpll *pll)
2441{
3e369b76 2442 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 2443 POSTING_READ(WRPLL_CTL(pll->id));
2444 udelay(20);
2445}
2446
12030431
DV		 2447static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
2448 struct intel_shared_dpll *pll)
2449{
2450 uint32_t val;
2451
2452 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2453 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2454 POSTING_READ(WRPLL_CTL(pll->id));
2455}
2456
d452c5b6
DV		 2457static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2458 struct intel_shared_dpll *pll,
2459 struct intel_dpll_hw_state *hw_state)
2460{
2461 uint32_t val;
2462
f458ebbc 2463 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2464 return false;
2465
2466 val = I915_READ(WRPLL_CTL(pll->id));
2467 hw_state->wrpll = val;
2468
2469 return val & WRPLL_PLL_ENABLE;
2470}
2471
ca1381b5 2472static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2473 "WRPLL 1",
2474 "WRPLL 2",
2475};
2476
143b307c 2477static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2478{
9cd86933
DV		 2479 int i;
2480
716c2e55 2481 dev_priv->num_shared_dpll = 2;
9cd86933 2482
716c2e55 2483 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 2484 dev_priv->shared_dplls[i].id = i;
2485 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 2486 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 2487 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 2488 dev_priv->shared_dplls[i].get_hw_state =
2489 hsw_ddi_pll_get_hw_state;
9cd86933 2490 }
143b307c
DL		 2491}
2492
d1a2dc78
S		 2493static const char * const skl_ddi_pll_names[] = {
2494 "DPLL 1",
2495 "DPLL 2",
2496 "DPLL 3",
2497};
2498
2499struct skl_dpll_regs {
2500 u32 ctl, cfgcr1, cfgcr2;
2501};
2502
2503/* this array is indexed by the *shared* pll id */
2504static const struct skl_dpll_regs skl_dpll_regs[3] = {
2505 {
2506 /* DPLL 1 */
2507 .ctl = LCPLL2_CTL,
2508 .cfgcr1 = DPLL1_CFGCR1,
2509 .cfgcr2 = DPLL1_CFGCR2,
2510 },
2511 {
2512 /* DPLL 2 */
2513 .ctl = WRPLL_CTL1,
2514 .cfgcr1 = DPLL2_CFGCR1,
2515 .cfgcr2 = DPLL2_CFGCR2,
2516 },
2517 {
2518 /* DPLL 3 */
2519 .ctl = WRPLL_CTL2,
2520 .cfgcr1 = DPLL3_CFGCR1,
2521 .cfgcr2 = DPLL3_CFGCR2,
2522 },
2523};
2524
2525static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2526 struct intel_shared_dpll *pll)
2527{
2528 uint32_t val;
2529 unsigned int dpll;
2530 const struct skl_dpll_regs *regs = skl_dpll_regs;
2531
2532 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2533 dpll = pll->id + 1;
2534
2535 val = I915_READ(DPLL_CTRL1);
2536
2537 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
71cd8423 2538 DPLL_CTRL1_LINK_RATE_MASK(dpll));
d1a2dc78
S		 2539 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2540
2541 I915_WRITE(DPLL_CTRL1, val);
2542 POSTING_READ(DPLL_CTRL1);
2543
2544 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2545 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2546 POSTING_READ(regs[pll->id].cfgcr1);
2547 POSTING_READ(regs[pll->id].cfgcr2);
2548
2549 /* the enable bit is always bit 31 */
2550 I915_WRITE(regs[pll->id].ctl,
2551 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2552
2553 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2554 DRM_ERROR("DPLL %d not locked\n", dpll);
2555}
2556
2557static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2558 struct intel_shared_dpll *pll)
2559{
2560 const struct skl_dpll_regs *regs = skl_dpll_regs;
2561
2562 /* the enable bit is always bit 31 */
2563 I915_WRITE(regs[pll->id].ctl,
2564 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2565 POSTING_READ(regs[pll->id].ctl);
2566}
2567
2568static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2569 struct intel_shared_dpll *pll,
2570 struct intel_dpll_hw_state *hw_state)
2571{
2572 uint32_t val;
2573 unsigned int dpll;
2574 const struct skl_dpll_regs *regs = skl_dpll_regs;
2575
2576 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2577 return false;
2578
2579 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2580 dpll = pll->id + 1;
2581
2582 val = I915_READ(regs[pll->id].ctl);
2583 if (!(val & LCPLL_PLL_ENABLE))
2584 return false;
2585
2586 val = I915_READ(DPLL_CTRL1);
2587 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2588
2589 /* avoid reading back stale values if HDMI mode is not enabled */
2590 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2591 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2592 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2593 }
2594
2595 return true;
2596}
2597
2598static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2599{
2600 int i;
2601
2602 dev_priv->num_shared_dpll = 3;
2603
2604 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2605 dev_priv->shared_dplls[i].id = i;
2606 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2607 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2608 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2609 dev_priv->shared_dplls[i].get_hw_state =
2610 skl_ddi_pll_get_hw_state;
2611 }
2612}
2613
5c6706e5
VK		 2614static void broxton_phy_init(struct drm_i915_private *dev_priv,
2615 enum dpio_phy phy)
2616{
2617 enum port port;
2618 uint32_t val;
2619
2620 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2621 val |= GT_DISPLAY_POWER_ON(phy);
2622 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2623
2624 /* Considering 10ms timeout until BSpec is updated */
2625 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2626 DRM_ERROR("timeout during PHY%d power on\n", phy);
2627
2628 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2629 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2630 int lane;
2631
2632 for (lane = 0; lane < 4; lane++) {
2633 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2634 /*
2635 * Note that on CHV this flag is called UPAR, but has
2636 * the same function.
2637 */
2638 val &= ~LATENCY_OPTIM;
2639 if (lane != 1)
2640 val |= LATENCY_OPTIM;
2641
2642 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2643 }
2644 }
2645
2646 /* Program PLL Rcomp code offset */
2647 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2648 val &= ~IREF0RC_OFFSET_MASK;
2649 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2650 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2651
2652 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2653 val &= ~IREF1RC_OFFSET_MASK;
2654 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2655 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2656
2657 /* Program power gating */
2658 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2659 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2660 SUS_CLK_CONFIG;
2661 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2662
2663 if (phy == DPIO_PHY0) {
2664 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2665 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2666 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2667 }
2668
2669 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2670 val &= ~OCL2_LDOFUSE_PWR_DIS;
2671 /*
2672 * On PHY1 disable power on the second channel, since no port is
2673 * connected there. On PHY0 both channels have a port, so leave it
2674 * enabled.
2675 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2676 * power down the second channel on PHY0 as well.
2677 */
2678 if (phy == DPIO_PHY1)
2679 val |= OCL2_LDOFUSE_PWR_DIS;
2680 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2681
2682 if (phy == DPIO_PHY0) {
2683 uint32_t grc_code;
2684 /*
2685 * PHY0 isn't connected to an RCOMP resistor so copy over
2686 * the corresponding calibrated value from PHY1, and disable
2687 * the automatic calibration on PHY0.
2688 */
2689 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2690 10))
2691 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2692
2693 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2694 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2695 grc_code = val << GRC_CODE_FAST_SHIFT |
2696 val << GRC_CODE_SLOW_SHIFT |
2697 val;
2698 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2699
2700 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2701 val |= GRC_DIS | GRC_RDY_OVRD;
2702 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2703 }
2704
2705 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2706 val |= COMMON_RESET_DIS;
2707 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2708}
2709
2710void broxton_ddi_phy_init(struct drm_device *dev)
2711{
2712 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2713 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2714 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2715}
2716
2717static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2718 enum dpio_phy phy)
2719{
2720 uint32_t val;
2721
2722 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2723 val &= ~COMMON_RESET_DIS;
2724 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2725}
2726
2727void broxton_ddi_phy_uninit(struct drm_device *dev)
2728{
2729 struct drm_i915_private *dev_priv = dev->dev_private;
2730
2731 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2732 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2733
2734 /* FIXME: do this in broxton_phy_uninit per phy */
2735 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2736}
2737
dfb82408
S		 2738static const char * const bxt_ddi_pll_names[] = {
2739 "PORT PLL A",
2740 "PORT PLL B",
2741 "PORT PLL C",
2742};
2743
2744static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2745 struct intel_shared_dpll *pll)
2746{
2747 uint32_t temp;
2748 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2749
2750 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2751 temp &= ~PORT_PLL_REF_SEL;
2752 /* Non-SSC reference */
2753 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2754
2755 /* Disable 10 bit clock */
2756 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2757 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2758 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2759
2760 /* Write P1 & P2 */
2761 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2762 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2763 temp |= pll->config.hw_state.ebb0;
2764 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2765
2766 /* Write M2 integer */
2767 temp = I915_READ(BXT_PORT_PLL(port, 0));
2768 temp &= ~PORT_PLL_M2_MASK;
2769 temp |= pll->config.hw_state.pll0;
2770 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2771
2772 /* Write N */
2773 temp = I915_READ(BXT_PORT_PLL(port, 1));
2774 temp &= ~PORT_PLL_N_MASK;
2775 temp |= pll->config.hw_state.pll1;
2776 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2777
2778 /* Write M2 fraction */
2779 temp = I915_READ(BXT_PORT_PLL(port, 2));
2780 temp &= ~PORT_PLL_M2_FRAC_MASK;
2781 temp |= pll->config.hw_state.pll2;
2782 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2783
2784 /* Write M2 fraction enable */
2785 temp = I915_READ(BXT_PORT_PLL(port, 3));
2786 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2787 temp |= pll->config.hw_state.pll3;
2788 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2789
2790 /* Write coeff */
2791 temp = I915_READ(BXT_PORT_PLL(port, 6));
2792 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2793 temp &= ~PORT_PLL_INT_COEFF_MASK;
2794 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2795 temp |= pll->config.hw_state.pll6;
2796 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2797
2798 /* Write calibration val */
2799 temp = I915_READ(BXT_PORT_PLL(port, 8));
2800 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2801 temp |= pll->config.hw_state.pll8;
2802 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2803
b6dc71f3
VK		 2804 temp = I915_READ(BXT_PORT_PLL(port, 9));
2805 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
05712c15 2806 temp |= pll->config.hw_state.pll9;
b6dc71f3
VK		 2807 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2808
2809 temp = I915_READ(BXT_PORT_PLL(port, 10));
2810 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2811 temp &= ~PORT_PLL_DCO_AMP_MASK;
2812 temp |= pll->config.hw_state.pll10;
2813 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
dfb82408
S		 2814
2815 /* Recalibrate with new settings */
2816 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2817 temp |= PORT_PLL_RECALIBRATE;
2818 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
05712c15
ID		 2819 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2820 temp |= pll->config.hw_state.ebb4;
dfb82408
S		 2821 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2822
2823 /* Enable PLL */
2824 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2825 temp |= PORT_PLL_ENABLE;
2826 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2827 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2828
2829 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2830 PORT_PLL_LOCK), 200))
2831 DRM_ERROR("PLL %d not locked\n", port);
2832
2833 /*
2834 * While we write to the group register to program all lanes at once we
2835 * can read only lane registers and we pick lanes 0/1 for that.
2836 */
2837 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2838 temp &= ~LANE_STAGGER_MASK;
2839 temp &= ~LANESTAGGER_STRAP_OVRD;
2840 temp |= pll->config.hw_state.pcsdw12;
2841 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2842}
2843
2844static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2845 struct intel_shared_dpll *pll)
2846{
2847 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2848 uint32_t temp;
2849
2850 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2851 temp &= ~PORT_PLL_ENABLE;
2852 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2853 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2854}
2855
2856static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2857 struct intel_shared_dpll *pll,
2858 struct intel_dpll_hw_state *hw_state)
2859{
2860 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2861 uint32_t val;
2862
2863 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2864 return false;
2865
2866 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2867 if (!(val & PORT_PLL_ENABLE))
2868 return false;
2869
2870 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
793dfa59
ID		 2871 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2872
05712c15
ID		 2873 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2874 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2875
dfb82408 2876 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
793dfa59
ID		 2877 hw_state->pll0 &= PORT_PLL_M2_MASK;
2878
dfb82408 2879 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
793dfa59
ID		 2880 hw_state->pll1 &= PORT_PLL_N_MASK;
2881
dfb82408 2882 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
793dfa59
ID		 2883 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2884
dfb82408 2885 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
793dfa59
ID		 2886 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2887
dfb82408 2888 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
793dfa59
ID		 2889 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2890 PORT_PLL_INT_COEFF_MASK |
2891 PORT_PLL_GAIN_CTL_MASK;
2892
dfb82408 2893 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
793dfa59
ID		 2894 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2895
05712c15
ID		 2896 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
2897 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2898
b6dc71f3 2899 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
793dfa59
ID		 2900 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2901 PORT_PLL_DCO_AMP_MASK;
2902
dfb82408
S		 2903 /*
2904 * While we write to the group register to program all lanes at once we
2905 * can read only lane registers. We configure all lanes the same way, so
2906 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2907 */
2908 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2909 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
2910 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2911 hw_state->pcsdw12,
2912 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
793dfa59 2913 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
dfb82408
S		 2914
2915 return true;
2916}
2917
2918static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2919{
2920 int i;
2921
2922 dev_priv->num_shared_dpll = 3;
2923
2924 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2925 dev_priv->shared_dplls[i].id = i;
2926 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2927 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2928 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2929 dev_priv->shared_dplls[i].get_hw_state =
2930 bxt_ddi_pll_get_hw_state;
2931 }
2932}
2933
143b307c
DL		 2934void intel_ddi_pll_init(struct drm_device *dev)
2935{
2936 struct drm_i915_private *dev_priv = dev->dev_private;
2937 uint32_t val = I915_READ(LCPLL_CTL);
2938
d1a2dc78
S		 2939 if (IS_SKYLAKE(dev))
2940 skl_shared_dplls_init(dev_priv);
dfb82408
S		 2941 else if (IS_BROXTON(dev))
2942 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 2943 else
2944 hsw_shared_dplls_init(dev_priv);
79f689aa 2945
121643c2 2946 if (IS_SKYLAKE(dev)) {
d9062ae5
DL		 2947 int cdclk_freq;
2948
2949 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5d96d8af 2950 dev_priv->skl_boot_cdclk = cdclk_freq;
121643c2
S		 2951 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2952 DRM_ERROR("LCPLL1 is disabled\n");
5d96d8af
DL		 2953 else
2954 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
f8437dd1
VK		 2955 } else if (IS_BROXTON(dev)) {
2956 broxton_init_cdclk(dev);
5c6706e5 2957 broxton_ddi_phy_init(dev);
121643c2
S		 2958 } else {
2959 /*
2960 * The LCPLL register should be turned on by the BIOS. For now
2961 * let's just check its state and print errors in case
2962 * something is wrong. Don't even try to turn it on.
2963 */
2964
2965 if (val & LCPLL_CD_SOURCE_FCLK)
2966 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 2967
121643c2
S		 2968 if (val & LCPLL_PLL_DISABLE)
2969 DRM_ERROR("LCPLL is disabled\n");
2970 }
79f689aa 2971}
c19b0669
PZ		 2972
2973void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
2974{
174edf1f
PZ		 2975 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2976 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 2977 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 2978 enum port port = intel_dig_port->port;
c19b0669 2979 uint32_t val;
f3e227df 2980 bool wait = false;
c19b0669
PZ		 2981
2982 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2983 val = I915_READ(DDI_BUF_CTL(port));
2984 if (val & DDI_BUF_CTL_ENABLE) {
2985 val &= ~DDI_BUF_CTL_ENABLE;
2986 I915_WRITE(DDI_BUF_CTL(port), val);
2987 wait = true;
2988 }
2989
2990 val = I915_READ(DP_TP_CTL(port));
2991 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2992 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2993 I915_WRITE(DP_TP_CTL(port), val);
2994 POSTING_READ(DP_TP_CTL(port));
2995
2996 if (wait)
2997 intel_wait_ddi_buf_idle(dev_priv, port);
2998 }
2999
0e32b39c 3000 val = DP_TP_CTL_ENABLE |
c19b0669 3001 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 3002 if (intel_dp->is_mst)
3003 val |= DP_TP_CTL_MODE_MST;
3004 else {
3005 val |= DP_TP_CTL_MODE_SST;
3006 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3007 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3008 }
c19b0669
PZ		 3009 I915_WRITE(DP_TP_CTL(port), val);
3010 POSTING_READ(DP_TP_CTL(port));
3011
3012 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3013 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3014 POSTING_READ(DDI_BUF_CTL(port));
3015
3016 udelay(600);
3017}
00c09d70 3018
1ad960f2
PZ		 3019void intel_ddi_fdi_disable(struct drm_crtc *crtc)
3020{
3021 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3022 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3023 uint32_t val;
3024
3025 intel_ddi_post_disable(intel_encoder);
3026
3027 val = I915_READ(_FDI_RXA_CTL);
3028 val &= ~FDI_RX_ENABLE;
3029 I915_WRITE(_FDI_RXA_CTL, val);
3030
3031 val = I915_READ(_FDI_RXA_MISC);
3032 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3033 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3034 I915_WRITE(_FDI_RXA_MISC, val);
3035
3036 val = I915_READ(_FDI_RXA_CTL);
3037 val &= ~FDI_PCDCLK;
3038 I915_WRITE(_FDI_RXA_CTL, val);
3039
3040 val = I915_READ(_FDI_RXA_CTL);
3041 val &= ~FDI_RX_PLL_ENABLE;
3042 I915_WRITE(_FDI_RXA_CTL, val);
3043}
3044
6801c18c 3045void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3046 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 3047{
3048 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3049 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 3050 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 3051 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 3052 u32 temp, flags = 0;
3053
3054 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3055 if (temp & TRANS_DDI_PHSYNC)
3056 flags |= DRM_MODE_FLAG_PHSYNC;
3057 else
3058 flags |= DRM_MODE_FLAG_NHSYNC;
3059 if (temp & TRANS_DDI_PVSYNC)
3060 flags |= DRM_MODE_FLAG_PVSYNC;
3061 else
3062 flags |= DRM_MODE_FLAG_NVSYNC;
3063
2d112de7 3064 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3065
3066 switch (temp & TRANS_DDI_BPC_MASK) {
3067 case TRANS_DDI_BPC_6:
3068 pipe_config->pipe_bpp = 18;
3069 break;
3070 case TRANS_DDI_BPC_8:
3071 pipe_config->pipe_bpp = 24;
3072 break;
3073 case TRANS_DDI_BPC_10:
3074 pipe_config->pipe_bpp = 30;
3075 break;
3076 case TRANS_DDI_BPC_12:
3077 pipe_config->pipe_bpp = 36;
3078 break;
3079 default:
3080 break;
3081 }
eb14cb74
VS		 3082
3083 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3084 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3085 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 3086 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3087
3088 if (intel_hdmi->infoframe_enabled(&encoder->base))
3089 pipe_config->has_infoframe = true;
cbc572a9 3090 break;
eb14cb74
VS		 3091 case TRANS_DDI_MODE_SELECT_DVI:
3092 case TRANS_DDI_MODE_SELECT_FDI:
3093 break;
3094 case TRANS_DDI_MODE_SELECT_DP_SST:
3095 case TRANS_DDI_MODE_SELECT_DP_MST:
3096 pipe_config->has_dp_encoder = true;
3097 intel_dp_get_m_n(intel_crtc, pipe_config);
3098 break;
3099 default:
3100 break;
3101 }
10214420 3102
f458ebbc 3103 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 3104 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 3105 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 3106 pipe_config->has_audio = true;
3107 }
9ed109a7 3108
10214420
DV		 3109 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3110 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3111 /*
3112 * This is a big fat ugly hack.
3113 *
3114 * Some machines in UEFI boot mode provide us a VBT that has 18
3115 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3116 * unknown we fail to light up. Yet the same BIOS boots up with
3117 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3118 * max, not what it tells us to use.
3119 *
3120 * Note: This will still be broken if the eDP panel is not lit
3121 * up by the BIOS, and thus we can't get the mode at module
3122 * load.
3123 */
3124 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3125 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3126 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3127 }
11578553 3128
22606a18 3129 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 3130}
3131
00c09d70
PZ		 3132static void intel_ddi_destroy(struct drm_encoder *encoder)
3133{
3134 /* HDMI has nothing special to destroy, so we can go with this. */
3135 intel_dp_encoder_destroy(encoder);
3136}
3137
5bfe2ac0 3138static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 3139 struct intel_crtc_state *pipe_config)
00c09d70 3140{
5bfe2ac0 3141 int type = encoder->type;
eccb140b 3142 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 3143
5bfe2ac0 3144 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 3145
eccb140b
DV		 3146 if (port == PORT_A)
3147 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3148
00c09d70 3149 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 3150 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 3151 else
5bfe2ac0 3152 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 3153}
3154
3155static const struct drm_encoder_funcs intel_ddi_funcs = {
3156 .destroy = intel_ddi_destroy,
3157};
3158
4a28ae58
PZ		 3159static struct intel_connector *
3160intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3161{
3162 struct intel_connector *connector;
3163 enum port port = intel_dig_port->port;
3164
9bdbd0b9 3165 connector = intel_connector_alloc();
4a28ae58
PZ		 3166 if (!connector)
3167 return NULL;
3168
3169 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3170 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3171 kfree(connector);
3172 return NULL;
3173 }
3174
3175 return connector;
3176}
3177
3178static struct intel_connector *
3179intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3180{
3181 struct intel_connector *connector;
3182 enum port port = intel_dig_port->port;
3183
9bdbd0b9 3184 connector = intel_connector_alloc();
4a28ae58
PZ		 3185 if (!connector)
3186 return NULL;
3187
3188 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3189 intel_hdmi_init_connector(intel_dig_port, connector);
3190
3191 return connector;
3192}
3193
00c09d70
PZ		 3194void intel_ddi_init(struct drm_device *dev, enum port port)
3195{
876a8cdf 3196 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 3197 struct intel_digital_port *intel_dig_port;
3198 struct intel_encoder *intel_encoder;
3199 struct drm_encoder *encoder;
311a2094
PZ		 3200 bool init_hdmi, init_dp;
3201
3202 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3203 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3204 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3205 if (!init_dp && !init_hdmi) {
500ea70d 3206 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 3207 port_name(port));
500ea70d 3208 return;
311a2094 3209 }
00c09d70 3210
b14c5679 3211 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 3212 if (!intel_dig_port)
3213 return;
3214
00c09d70
PZ		 3215 intel_encoder = &intel_dig_port->base;
3216 encoder = &intel_encoder->base;
3217
3218 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
3219 DRM_MODE_ENCODER_TMDS);
00c09d70 3220
5bfe2ac0 3221 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 3222 intel_encoder->enable = intel_enable_ddi;
3223 intel_encoder->pre_enable = intel_ddi_pre_enable;
3224 intel_encoder->disable = intel_disable_ddi;
3225 intel_encoder->post_disable = intel_ddi_post_disable;
3226 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 3227 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 3228
3229 intel_dig_port->port = port;
bcf53de4
SM		 3230 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3231 (DDI_BUF_PORT_REVERSAL |
3232 DDI_A_4_LANES);
00c09d70
PZ		 3233
3234 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 3235 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3236 intel_encoder->cloneable = 0;
00c09d70 3237
f68d697e
CW		 3238 if (init_dp) {
3239 if (!intel_ddi_init_dp_connector(intel_dig_port))
3240 goto err;
13cf5504 3241
f68d697e 3242 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
cf1d5883
SJ		 3243 /*
3244 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
3245 * interrupts to check the external panel connection.
3246 */
3247 if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)
3248 && port == PORT_B)
3249 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
3250 else
3251 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 3252 }
21a8e6a4 3253
311a2094
PZ		 3254 /* In theory we don't need the encoder->type check, but leave it just in
3255 * case we have some really bad VBTs... */
f68d697e
CW		 3256 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3257 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3258 goto err;
21a8e6a4 3259 }
f68d697e
CW		 3260
3261 return;
3262
3263err:
3264 drm_encoder_cleanup(encoder);
3265 kfree(intel_dig_port);
00c09d70 3266}
Linux kernel - Deliverables
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