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drm/i915: Expose I915_EXEC_RESOURCE_STREAMER flag and getparam
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
45244b87
ED		 37/* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
10122051 41static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 51};
52
10122051 53static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 63};
64
10122051
JN		 65static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 79};
80
10122051 81static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 91};
92
10122051 93static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 103};
104
10122051 105static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 115};
116
10122051
JN		 117static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 129};
130
f8896f5d 131/* Skylake H, S, and Skylake Y with 0.95V VccIO */
7f88e3af 132static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x00009010, 0x000000C7, 0x0 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x00007011, 0x000000C7, 0x0 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x00005012, 0x000000C7, 0x0 },
7f88e3af
DL		 142};
143
f8896f5d
DW		 144/* Skylake U */
145static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
146 { 0x00002016, 0x000000A2, 0x0 },
147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x00007011, 0x00000087, 0x0 },
149 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost */
150 { 0x00002016, 0x0000009D, 0x0 },
151 { 0x00005012, 0x000000C7, 0x0 },
152 { 0x00007011, 0x000000C7, 0x0 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x00005012, 0x000000C7, 0x0 },
155};
156
157/* Skylake Y with 0.85V VccIO */
158static const struct ddi_buf_trans skl_y_085v_ddi_translations_dp[] = {
159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x00007011, 0x00000087, 0x0 },
162 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost */
163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x00005012, 0x000000C7, 0x0 },
165 { 0x00007011, 0x000000C7, 0x0 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x00005012, 0x000000C7, 0x0 },
168};
169
170/*
171 * Skylake H and S, and Skylake Y with 0.95V VccIO
172 * eDP 1.4 low vswing translation parameters
173 */
7ad14a29 174static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185};
186
187/*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 202};
203
f8896f5d
DW		 204/*
205 * Skylake Y with 0.95V VccIO
206 * eDP 1.4 low vswing translation parameters
207 */
208static const struct ddi_buf_trans skl_y_085v_ddi_translations_edp[] = {
209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219};
7ad14a29 220
f8896f5d 221/* Skylake H, S and U, and Skylake Y with 0.95V VccIO */
7f88e3af 222static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x00006012, 0x00000087, 0x0 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x00003015, 0x00000087, 0x0 }, /* Default */
232 { 0x00003015, 0x000000C7, 0x0 },
233 { 0x00000018, 0x000000C7, 0x0 },
234};
235
236/* Skylake Y with 0.85V VccIO */
237static const struct ddi_buf_trans skl_y_085v_ddi_translations_hdmi[] = {
238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x00007011, 0x00000084, 0x0 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x00006013, 0x000000C7, 0x0 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x00003015, 0x000000C7, 0x0 }, /* Default */
247 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost */
248 { 0x00000018, 0x000000C7, 0x0 },
7f88e3af
DL		 249};
250
96fb9f9b
VK		 251struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257};
258
259/* BSpec does not define separate vswing/pre-emphasis values for eDP.
260 * Using DP values for eDP as well.
261 */
262static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
263 /* Idx NT mV diff db */
fe4c63c8
ID		 264 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
265 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
266 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
267 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
268 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
269 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
270 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
271 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
272 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 273 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 274};
275
276/* BSpec has 2 recommended values - entries 0 and 8.
277 * Using the entry with higher vswing.
278 */
279static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
280 /* Idx NT mV diff db */
fe4c63c8
ID		 281 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
282 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
283 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
284 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
285 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
286 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
287 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
288 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
289 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 290 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
291};
292
f8896f5d
DW		 293static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
294 enum port port, int type);
295
a1e6ad66
ID		 296static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
297 struct intel_digital_port **dig_port,
298 enum port *port)
fc914639 299{
0bdee30e 300 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 301 int type = intel_encoder->type;
302
0e32b39c 303 if (type == INTEL_OUTPUT_DP_MST) {
a1e6ad66
ID		 304 *dig_port = enc_to_mst(encoder)->primary;
305 *port = (*dig_port)->port;
0e32b39c 306 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 307 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
a1e6ad66
ID		 308 *dig_port = enc_to_dig_port(encoder);
309 *port = (*dig_port)->port;
fc914639 310 } else if (type == INTEL_OUTPUT_ANALOG) {
a1e6ad66
ID		 311 *dig_port = NULL;
312 *port = PORT_E;
fc914639
PZ		 313 } else {
314 DRM_ERROR("Invalid DDI encoder type %d\n", type);
315 BUG();
316 }
317}
318
a1e6ad66
ID		 319enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
320{
321 struct intel_digital_port *dig_port;
322 enum port port;
323
324 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
325
326 return port;
327}
328
ce3b7e9b
DL		 329static bool
330intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
331{
332 return intel_dig_port->hdmi.hdmi_reg;
333}
334
f8896f5d
DW		 335static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev,
336 int *n_entries)
337{
338 struct drm_i915_private *dev_priv = dev->dev_private;
339 const struct ddi_buf_trans *ddi_translations;
340 static int is_095v = -1;
341
342 if (is_095v == -1) {
343 u32 spr1 = I915_READ(UAIMI_SPR1);
344
345 is_095v = spr1 & SKL_VCCIO_MASK;
346 }
347
348 if (IS_SKL_ULX(dev) && !is_095v) {
349 ddi_translations = skl_y_085v_ddi_translations_dp;
350 *n_entries = ARRAY_SIZE(skl_y_085v_ddi_translations_dp);
351 } else if (IS_SKL_ULT(dev)) {
352 ddi_translations = skl_u_ddi_translations_dp;
353 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
354 } else {
355 ddi_translations = skl_ddi_translations_dp;
356 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
357 }
358
359 return ddi_translations;
360}
361
362static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev,
363 int *n_entries)
364{
365 struct drm_i915_private *dev_priv = dev->dev_private;
366 const struct ddi_buf_trans *ddi_translations;
367 static int is_095v = -1;
368
369 if (is_095v == -1) {
370 u32 spr1 = I915_READ(UAIMI_SPR1);
371
372 is_095v = spr1 & SKL_VCCIO_MASK;
373 }
374
375 if (IS_SKL_ULX(dev) && !is_095v) {
376 if (dev_priv->edp_low_vswing) {
377 ddi_translations = skl_y_085v_ddi_translations_edp;
378 *n_entries =
379 ARRAY_SIZE(skl_y_085v_ddi_translations_edp);
380 } else {
381 ddi_translations = skl_y_085v_ddi_translations_dp;
382 *n_entries =
383 ARRAY_SIZE(skl_y_085v_ddi_translations_dp);
384 }
385 } else if (IS_SKL_ULT(dev)) {
386 if (dev_priv->edp_low_vswing) {
387 ddi_translations = skl_u_ddi_translations_edp;
388 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
389 } else {
390 ddi_translations = skl_u_ddi_translations_dp;
391 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
392 }
393 } else {
394 if (dev_priv->edp_low_vswing) {
395 ddi_translations = skl_ddi_translations_edp;
396 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
397 } else {
398 ddi_translations = skl_ddi_translations_dp;
399 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
400 }
401 }
402
403 return ddi_translations;
404}
405
406static const struct ddi_buf_trans *
407skl_get_buf_trans_hdmi(struct drm_device *dev,
408 int *n_entries)
409{
410 struct drm_i915_private *dev_priv = dev->dev_private;
411 const struct ddi_buf_trans *ddi_translations;
412 static int is_095v = -1;
413
414 if (is_095v == -1) {
415 u32 spr1 = I915_READ(UAIMI_SPR1);
416
417 is_095v = spr1 & SKL_VCCIO_MASK;
418 }
419
420 if (IS_SKL_ULX(dev) && !is_095v) {
421 ddi_translations = skl_y_085v_ddi_translations_hdmi;
422 *n_entries = ARRAY_SIZE(skl_y_085v_ddi_translations_hdmi);
423 } else {
424 ddi_translations = skl_ddi_translations_hdmi;
425 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
426 }
427
428 return ddi_translations;
429}
430
e58623cb
AR		 431/*
432 * Starting with Haswell, DDI port buffers must be programmed with correct
433 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 434 * but the HDMI/DVI fields are shared among those. So we program the DDI
435 * in either FDI or DP modes only, as HDMI connections will work with both
436 * of those
437 */
faa0cdbe
ID		 438static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
439 bool supports_hdmi)
45244b87
ED		 440{
441 struct drm_i915_private *dev_priv = dev->dev_private;
442 u32 reg;
7ff44670 443 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 444 size;
6acab15a 445 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 446 const struct ddi_buf_trans *ddi_translations_fdi;
447 const struct ddi_buf_trans *ddi_translations_dp;
448 const struct ddi_buf_trans *ddi_translations_edp;
449 const struct ddi_buf_trans *ddi_translations_hdmi;
450 const struct ddi_buf_trans *ddi_translations;
e58623cb 451
96fb9f9b 452 if (IS_BROXTON(dev)) {
faa0cdbe 453 if (!supports_hdmi)
96fb9f9b
VK		 454 return;
455
456 /* Vswing programming for HDMI */
457 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
458 INTEL_OUTPUT_HDMI);
459 return;
460 } else if (IS_SKYLAKE(dev)) {
f8896f5d
DW		 461 ddi_translations_dp =
462 skl_get_buf_trans_dp(dev, &n_dp_entries);
463 ddi_translations_edp =
464 skl_get_buf_trans_edp(dev, &n_edp_entries);
465 ddi_translations_hdmi =
466 skl_get_buf_trans_hdmi(dev, &n_hdmi_entries);
467 hdmi_default_entry = 8;
7f88e3af 468 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 469 ddi_translations_fdi = bdw_ddi_translations_fdi;
470 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 471 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 472 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 473 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
474 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 475 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 476 hdmi_default_entry = 7;
e58623cb
AR		 477 } else if (IS_HASWELL(dev)) {
478 ddi_translations_fdi = hsw_ddi_translations_fdi;
479 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 480 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 481 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 482 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 483 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 484 hdmi_default_entry = 6;
e58623cb
AR		 485 } else {
486 WARN(1, "ddi translation table missing\n");
300644c7 487 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 488 ddi_translations_fdi = bdw_ddi_translations_fdi;
489 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 490 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 491 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
492 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 493 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 494 hdmi_default_entry = 7;
e58623cb
AR		 495 }
496
300644c7
PZ		 497 switch (port) {
498 case PORT_A:
499 ddi_translations = ddi_translations_edp;
7ad14a29 500 size = n_edp_entries;
300644c7
PZ		 501 break;
502 case PORT_B:
503 case PORT_C:
300644c7 504 ddi_translations = ddi_translations_dp;
7ad14a29 505 size = n_dp_entries;
300644c7 506 break;
77d8d009 507 case PORT_D:
7ad14a29 508 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 509 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 510 size = n_edp_entries;
511 } else {
77d8d009 512 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 513 size = n_dp_entries;
514 }
77d8d009 515 break;
300644c7 516 case PORT_E:
7f88e3af
DL		 517 if (ddi_translations_fdi)
518 ddi_translations = ddi_translations_fdi;
519 else
520 ddi_translations = ddi_translations_dp;
7ad14a29 521 size = n_dp_entries;
300644c7
PZ		 522 break;
523 default:
524 BUG();
525 }
45244b87 526
7ad14a29 527 for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
10122051
JN		 528 I915_WRITE(reg, ddi_translations[i].trans1);
529 reg += 4;
530 I915_WRITE(reg, ddi_translations[i].trans2);
45244b87
ED		 531 reg += 4;
532 }
ce4dd49e 533
faa0cdbe 534 if (!supports_hdmi)
ce3b7e9b
DL		 535 return;
536
ce4dd49e
DL		 537 /* Choose a good default if VBT is badly populated */
538 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
539 hdmi_level >= n_hdmi_entries)
7ff44670 540 hdmi_level = hdmi_default_entry;
ce4dd49e 541
6acab15a 542 /* Entry 9 is for HDMI: */
10122051
JN		 543 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
544 reg += 4;
545 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
546 reg += 4;
45244b87
ED		 547}
548
549/* Program DDI buffers translations for DP. By default, program ports A-D in DP
550 * mode and port E for FDI.
551 */
552void intel_prepare_ddi(struct drm_device *dev)
553{
faa0cdbe 554 struct intel_encoder *intel_encoder;
b403745c 555 bool visited[I915_MAX_PORTS] = { 0, };
45244b87 556
0d536cb4
PZ		 557 if (!HAS_DDI(dev))
558 return;
45244b87 559
faa0cdbe
ID		 560 for_each_intel_encoder(dev, intel_encoder) {
561 struct intel_digital_port *intel_dig_port;
562 enum port port;
563 bool supports_hdmi;
564
565 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
566
567 if (visited[port])
b403745c
DL		 568 continue;
569
faa0cdbe
ID		 570 supports_hdmi = intel_dig_port &&
571 intel_dig_port_supports_hdmi(intel_dig_port);
572
573 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
574 visited[port] = true;
b403745c 575 }
45244b87 576}
c82e4d26 577
248138b5
PZ		 578static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
579 enum port port)
580{
581 uint32_t reg = DDI_BUF_CTL(port);
582 int i;
583
3449ca85 584 for (i = 0; i < 16; i++) {
248138b5
PZ		 585 udelay(1);
586 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
587 return;
588 }
589 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
590}
c82e4d26
ED		 591
592/* Starting with Haswell, different DDI ports can work in FDI mode for
593 * connection to the PCH-located connectors. For this, it is necessary to train
594 * both the DDI port and PCH receiver for the desired DDI buffer settings.
595 *
596 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
597 * please note that when FDI mode is active on DDI E, it shares 2 lines with
598 * DDI A (which is used for eDP)
599 */
600
601void hsw_fdi_link_train(struct drm_crtc *crtc)
602{
603 struct drm_device *dev = crtc->dev;
604 struct drm_i915_private *dev_priv = dev->dev_private;
605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 606 u32 temp, i, rx_ctl_val;
c82e4d26 607
04945641
PZ		 608 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
609 * mode set "sequence for CRT port" document:
610 * - TP1 to TP2 time with the default value
611 * - FDI delay to 90h
8693a824
DL		 612 *
613 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 614 */
615 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
616 FDI_RX_PWRDN_LANE0_VAL(2) |
617 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
618
619 /* Enable the PCH Receiver FDI PLL */
3e68320e 620 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 621 FDI_RX_PLL_ENABLE |
6e3c9717 622 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
04945641
PZ		 623 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
624 POSTING_READ(_FDI_RXA_CTL);
625 udelay(220);
626
627 /* Switch from Rawclk to PCDclk */
628 rx_ctl_val |= FDI_PCDCLK;
629 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
630
631 /* Configure Port Clock Select */
6e3c9717
ACO		 632 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
633 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 634
635 /* Start the training iterating through available voltages and emphasis,
636 * testing each value twice. */
10122051 637 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 638 /* Configure DP_TP_CTL with auto-training */
639 I915_WRITE(DP_TP_CTL(PORT_E),
640 DP_TP_CTL_FDI_AUTOTRAIN |
641 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
642 DP_TP_CTL_LINK_TRAIN_PAT1 |
643 DP_TP_CTL_ENABLE);
644
876a8cdf
DL		 645 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
646 * DDI E does not support port reversal, the functionality is
647 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
648 * port reversal bit */
c82e4d26 649 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 650 DDI_BUF_CTL_ENABLE |
6e3c9717 651 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 652 DDI_BUF_TRANS_SELECT(i / 2));
04945641 653 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 654
655 udelay(600);
656
04945641
PZ		 657 /* Program PCH FDI Receiver TU */
658 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
659
660 /* Enable PCH FDI Receiver with auto-training */
661 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
662 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
663 POSTING_READ(_FDI_RXA_CTL);
664
665 /* Wait for FDI receiver lane calibration */
666 udelay(30);
667
668 /* Unset FDI_RX_MISC pwrdn lanes */
669 temp = I915_READ(_FDI_RXA_MISC);
670 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
671 I915_WRITE(_FDI_RXA_MISC, temp);
672 POSTING_READ(_FDI_RXA_MISC);
673
674 /* Wait for FDI auto training time */
675 udelay(5);
c82e4d26
ED		 676
677 temp = I915_READ(DP_TP_STATUS(PORT_E));
678 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 679 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 680
681 /* Enable normal pixel sending for FDI */
682 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 683 DP_TP_CTL_FDI_AUTOTRAIN |
684 DP_TP_CTL_LINK_TRAIN_NORMAL |
685 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
686 DP_TP_CTL_ENABLE);
c82e4d26 687
04945641 688 return;
c82e4d26 689 }
04945641 690
248138b5
PZ		 691 temp = I915_READ(DDI_BUF_CTL(PORT_E));
692 temp &= ~DDI_BUF_CTL_ENABLE;
693 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
694 POSTING_READ(DDI_BUF_CTL(PORT_E));
695
04945641 696 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 697 temp = I915_READ(DP_TP_CTL(PORT_E));
698 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
699 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
700 I915_WRITE(DP_TP_CTL(PORT_E), temp);
701 POSTING_READ(DP_TP_CTL(PORT_E));
702
703 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 704
705 rx_ctl_val &= ~FDI_RX_ENABLE;
706 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 707 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 708
709 /* Reset FDI_RX_MISC pwrdn lanes */
710 temp = I915_READ(_FDI_RXA_MISC);
711 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
712 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
713 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 714 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 715 }
716
04945641 717 DRM_ERROR("FDI link training failed!\n");
c82e4d26 718}
0e72a5b5 719
44905a27
DA		 720void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
721{
722 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
723 struct intel_digital_port *intel_dig_port =
724 enc_to_dig_port(&encoder->base);
725
726 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 727 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
44905a27
DA		 728 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
729
730}
731
8d9ddbcb
PZ		 732static struct intel_encoder *
733intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
734{
735 struct drm_device *dev = crtc->dev;
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737 struct intel_encoder *intel_encoder, *ret = NULL;
738 int num_encoders = 0;
739
740 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
741 ret = intel_encoder;
742 num_encoders++;
743 }
744
745 if (num_encoders != 1)
84f44ce7
VS		 746 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
747 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 748
749 BUG_ON(ret == NULL);
750 return ret;
751}
752
bcddf610 753struct intel_encoder *
3165c074 754intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 755{
3165c074
ACO		 756 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
757 struct intel_encoder *ret = NULL;
758 struct drm_atomic_state *state;
da3ced29
ACO		 759 struct drm_connector *connector;
760 struct drm_connector_state *connector_state;
d0737e1d 761 int num_encoders = 0;
3165c074 762 int i;
d0737e1d 763
3165c074
ACO		 764 state = crtc_state->base.state;
765
da3ced29
ACO		 766 for_each_connector_in_state(state, connector, connector_state, i) {
767 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 768 continue;
769
da3ced29 770 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 771 num_encoders++;
d0737e1d
ACO		 772 }
773
774 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
775 pipe_name(crtc->pipe));
776
777 BUG_ON(ret == NULL);
778 return ret;
779}
780
1c0b85c5 781#define LC_FREQ 2700
27893390 782#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 783
784#define P_MIN 2
785#define P_MAX 64
786#define P_INC 2
787
788/* Constraints for PLL good behavior */
789#define REF_MIN 48
790#define REF_MAX 400
791#define VCO_MIN 2400
792#define VCO_MAX 4800
793
27893390
DL		 794#define abs_diff(a, b) ({ \
795 typeof(a) __a = (a); \
796 typeof(b) __b = (b); \
797 (void) (&__a == &__b); \
798 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5 799
63582983 800struct hsw_wrpll_rnp {
1c0b85c5
DL		 801 unsigned p, n2, r2;
802};
803
63582983 804static unsigned hsw_wrpll_get_budget_for_freq(int clock)
6441ab5f 805{
1c0b85c5
DL		 806 unsigned budget;
807
808 switch (clock) {
809 case 25175000:
810 case 25200000:
811 case 27000000:
812 case 27027000:
813 case 37762500:
814 case 37800000:
815 case 40500000:
816 case 40541000:
817 case 54000000:
818 case 54054000:
819 case 59341000:
820 case 59400000:
821 case 72000000:
822 case 74176000:
823 case 74250000:
824 case 81000000:
825 case 81081000:
826 case 89012000:
827 case 89100000:
828 case 108000000:
829 case 108108000:
830 case 111264000:
831 case 111375000:
832 case 148352000:
833 case 148500000:
834 case 162000000:
835 case 162162000:
836 case 222525000:
837 case 222750000:
838 case 296703000:
839 case 297000000:
840 budget = 0;
841 break;
842 case 233500000:
843 case 245250000:
844 case 247750000:
845 case 253250000:
846 case 298000000:
847 budget = 1500;
848 break;
849 case 169128000:
850 case 169500000:
851 case 179500000:
852 case 202000000:
853 budget = 2000;
854 break;
855 case 256250000:
856 case 262500000:
857 case 270000000:
858 case 272500000:
859 case 273750000:
860 case 280750000:
861 case 281250000:
862 case 286000000:
863 case 291750000:
864 budget = 4000;
865 break;
866 case 267250000:
867 case 268500000:
868 budget = 5000;
869 break;
870 default:
871 budget = 1000;
872 break;
873 }
6441ab5f 874
1c0b85c5
DL		 875 return budget;
876}
877
63582983
DL		 878static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
879 unsigned r2, unsigned n2, unsigned p,
880 struct hsw_wrpll_rnp *best)
1c0b85c5
DL		 881{
882 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 883
1c0b85c5
DL		 884 /* No best (r,n,p) yet */
885 if (best->p == 0) {
886 best->p = p;
887 best->n2 = n2;
888 best->r2 = r2;
889 return;
890 }
6441ab5f 891
1c0b85c5
DL		 892 /*
893 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
894 * freq2k.
895 *
896 * delta = 1e6 *
897 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
898 * freq2k;
899 *
900 * and we would like delta <= budget.
901 *
902 * If the discrepancy is above the PPM-based budget, always prefer to
903 * improve upon the previous solution. However, if you're within the
904 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
905 */
906 a = freq2k * budget * p * r2;
907 b = freq2k * budget * best->p * best->r2;
27893390
DL		 908 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
909 diff_best = abs_diff(freq2k * best->p * best->r2,
910 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 911 c = 1000000 * diff;
912 d = 1000000 * diff_best;
913
914 if (a < c && b < d) {
915 /* If both are above the budget, pick the closer */
916 if (best->p * best->r2 * diff < p * r2 * diff_best) {
917 best->p = p;
918 best->n2 = n2;
919 best->r2 = r2;
920 }
921 } else if (a >= c && b < d) {
922 /* If A is below the threshold but B is above it? Update. */
923 best->p = p;
924 best->n2 = n2;
925 best->r2 = r2;
926 } else if (a >= c && b >= d) {
927 /* Both are below the limit, so pick the higher n2/(r2*r2) */
928 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
929 best->p = p;
930 best->n2 = n2;
931 best->r2 = r2;
932 }
933 }
934 /* Otherwise a < c && b >= d, do nothing */
935}
936
63582983 937static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
11578553
JB		 938{
939 int refclk = LC_FREQ;
940 int n, p, r;
941 u32 wrpll;
942
943 wrpll = I915_READ(reg);
114fe488
DV		 944 switch (wrpll & WRPLL_PLL_REF_MASK) {
945 case WRPLL_PLL_SSC:
946 case WRPLL_PLL_NON_SSC:
11578553
JB		 947 /*
948 * We could calculate spread here, but our checking
949 * code only cares about 5% accuracy, and spread is a max of
950 * 0.5% downspread.
951 */
952 refclk = 135;
953 break;
114fe488 954 case WRPLL_PLL_LCPLL:
11578553
JB		 955 refclk = LC_FREQ;
956 break;
957 default:
958 WARN(1, "bad wrpll refclk\n");
959 return 0;
960 }
961
962 r = wrpll & WRPLL_DIVIDER_REF_MASK;
963 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
964 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
965
20f0ec16
JB		 966 /* Convert to KHz, p & r have a fixed point portion */
967 return (refclk * n * 100) / (p * r);
11578553
JB		 968}
969
540e732c
S		 970static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
971 uint32_t dpll)
972{
973 uint32_t cfgcr1_reg, cfgcr2_reg;
974 uint32_t cfgcr1_val, cfgcr2_val;
975 uint32_t p0, p1, p2, dco_freq;
976
977 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
978 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
979
980 cfgcr1_val = I915_READ(cfgcr1_reg);
981 cfgcr2_val = I915_READ(cfgcr2_reg);
982
983 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
984 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
985
986 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
987 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
988 else
989 p1 = 1;
990
991
992 switch (p0) {
993 case DPLL_CFGCR2_PDIV_1:
994 p0 = 1;
995 break;
996 case DPLL_CFGCR2_PDIV_2:
997 p0 = 2;
998 break;
999 case DPLL_CFGCR2_PDIV_3:
1000 p0 = 3;
1001 break;
1002 case DPLL_CFGCR2_PDIV_7:
1003 p0 = 7;
1004 break;
1005 }
1006
1007 switch (p2) {
1008 case DPLL_CFGCR2_KDIV_5:
1009 p2 = 5;
1010 break;
1011 case DPLL_CFGCR2_KDIV_2:
1012 p2 = 2;
1013 break;
1014 case DPLL_CFGCR2_KDIV_3:
1015 p2 = 3;
1016 break;
1017 case DPLL_CFGCR2_KDIV_1:
1018 p2 = 1;
1019 break;
1020 }
1021
1022 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1023
1024 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1025 1000) / 0x8000;
1026
1027 return dco_freq / (p0 * p1 * p2 * 5);
1028}
1029
398a017e
VS		 1030static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1031{
1032 int dotclock;
1033
1034 if (pipe_config->has_pch_encoder)
1035 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1036 &pipe_config->fdi_m_n);
1037 else if (pipe_config->has_dp_encoder)
1038 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1039 &pipe_config->dp_m_n);
1040 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1041 dotclock = pipe_config->port_clock * 2 / 3;
1042 else
1043 dotclock = pipe_config->port_clock;
1044
1045 if (pipe_config->pixel_multiplier)
1046 dotclock /= pipe_config->pixel_multiplier;
1047
1048 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1049}
540e732c
S		 1050
1051static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1052 struct intel_crtc_state *pipe_config)
540e732c
S		 1053{
1054 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 1055 int link_clock = 0;
1056 uint32_t dpll_ctl1, dpll;
1057
134ffa44 1058 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 1059
1060 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1061
1062 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1063 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1064 } else {
71cd8423
DL		 1065 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1066 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1067
1068 switch (link_clock) {
71cd8423 1069 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1070 link_clock = 81000;
1071 break;
71cd8423 1072 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1073 link_clock = 108000;
1074 break;
71cd8423 1075 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1076 link_clock = 135000;
1077 break;
71cd8423 1078 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1079 link_clock = 162000;
1080 break;
71cd8423 1081 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1082 link_clock = 216000;
1083 break;
71cd8423 1084 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1085 link_clock = 270000;
1086 break;
1087 default:
1088 WARN(1, "Unsupported link rate\n");
1089 break;
1090 }
1091 link_clock *= 2;
1092 }
1093
1094 pipe_config->port_clock = link_clock;
1095
398a017e 1096 ddi_dotclock_get(pipe_config);
540e732c
S		 1097}
1098
3d51278a 1099static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1100 struct intel_crtc_state *pipe_config)
11578553
JB		 1101{
1102 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 1103 int link_clock = 0;
1104 u32 val, pll;
1105
26804afd 1106 val = pipe_config->ddi_pll_sel;
11578553
JB		 1107 switch (val & PORT_CLK_SEL_MASK) {
1108 case PORT_CLK_SEL_LCPLL_810:
1109 link_clock = 81000;
1110 break;
1111 case PORT_CLK_SEL_LCPLL_1350:
1112 link_clock = 135000;
1113 break;
1114 case PORT_CLK_SEL_LCPLL_2700:
1115 link_clock = 270000;
1116 break;
1117 case PORT_CLK_SEL_WRPLL1:
63582983 1118 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
11578553
JB		 1119 break;
1120 case PORT_CLK_SEL_WRPLL2:
63582983 1121 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
11578553
JB		 1122 break;
1123 case PORT_CLK_SEL_SPLL:
1124 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1125 if (pll == SPLL_PLL_FREQ_810MHz)
1126 link_clock = 81000;
1127 else if (pll == SPLL_PLL_FREQ_1350MHz)
1128 link_clock = 135000;
1129 else if (pll == SPLL_PLL_FREQ_2700MHz)
1130 link_clock = 270000;
1131 else {
1132 WARN(1, "bad spll freq\n");
1133 return;
1134 }
1135 break;
1136 default:
1137 WARN(1, "bad port clock sel\n");
1138 return;
1139 }
1140
1141 pipe_config->port_clock = link_clock * 2;
1142
398a017e 1143 ddi_dotclock_get(pipe_config);
11578553
JB		 1144}
1145
977bb38d
S		 1146static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1147 enum intel_dpll_id dpll)
1148{
aa610dcb
ID		 1149 struct intel_shared_dpll *pll;
1150 struct intel_dpll_hw_state *state;
1151 intel_clock_t clock;
1152
1153 /* For DDI ports we always use a shared PLL. */
1154 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1155 return 0;
1156
1157 pll = &dev_priv->shared_dplls[dpll];
1158 state = &pll->config.hw_state;
1159
1160 clock.m1 = 2;
1161 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1162 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1163 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1164 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1165 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1166 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1167
1168 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1169}
1170
1171static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1172 struct intel_crtc_state *pipe_config)
1173{
1174 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1175 enum port port = intel_ddi_get_encoder_port(encoder);
1176 uint32_t dpll = port;
1177
398a017e 1178 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 1179
398a017e 1180 ddi_dotclock_get(pipe_config);
977bb38d
S		 1181}
1182
3d51278a 1183void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1184 struct intel_crtc_state *pipe_config)
3d51278a 1185{
22606a18
DL		 1186 struct drm_device *dev = encoder->base.dev;
1187
1188 if (INTEL_INFO(dev)->gen <= 8)
1189 hsw_ddi_clock_get(encoder, pipe_config);
977bb38d 1190 else if (IS_SKYLAKE(dev))
22606a18 1191 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1192 else if (IS_BROXTON(dev))
1193 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1194}
1195
1c0b85c5 1196static void
d664c0ce
DL		 1197hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1198 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1199{
1200 uint64_t freq2k;
1201 unsigned p, n2, r2;
63582983 1202 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1c0b85c5
DL		 1203 unsigned budget;
1204
1205 freq2k = clock / 100;
1206
63582983 1207 budget = hsw_wrpll_get_budget_for_freq(clock);
1c0b85c5
DL		 1208
1209 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1210 * and directly pass the LC PLL to it. */
1211 if (freq2k == 5400000) {
1212 *n2_out = 2;
1213 *p_out = 1;
1214 *r2_out = 2;
1215 return;
1216 }
1217
1218 /*
1219 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1220 * the WR PLL.
1221 *
1222 * We want R so that REF_MIN <= Ref <= REF_MAX.
1223 * Injecting R2 = 2 * R gives:
1224 * REF_MAX * r2 > LC_FREQ * 2 and
1225 * REF_MIN * r2 < LC_FREQ * 2
1226 *
1227 * Which means the desired boundaries for r2 are:
1228 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1229 *
1230 */
1231 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1232 r2 <= LC_FREQ * 2 / REF_MIN;
1233 r2++) {
1234
1235 /*
1236 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1237 *
1238 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1239 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1240 * VCO_MAX * r2 > n2 * LC_FREQ and
1241 * VCO_MIN * r2 < n2 * LC_FREQ)
1242 *
1243 * Which means the desired boundaries for n2 are:
1244 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1245 */
1246 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1247 n2 <= VCO_MAX * r2 / LC_FREQ;
1248 n2++) {
1249
1250 for (p = P_MIN; p <= P_MAX; p += P_INC)
63582983
DL		 1251 hsw_wrpll_update_rnp(freq2k, budget,
1252 r2, n2, p, &best);
1c0b85c5
DL		 1253 }
1254 }
6441ab5f 1255
1c0b85c5
DL		 1256 *n2_out = best.n2;
1257 *p_out = best.p;
1258 *r2_out = best.r2;
6441ab5f
PZ		 1259}
1260
0220ab6e 1261static bool
d664c0ce 1262hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1263 struct intel_crtc_state *crtc_state,
d664c0ce
DL		 1264 struct intel_encoder *intel_encoder,
1265 int clock)
6441ab5f 1266{
d664c0ce 1267 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1268 struct intel_shared_dpll *pll;
716c2e55 1269 uint32_t val;
1c0b85c5 1270 unsigned p, n2, r2;
6441ab5f 1271
d664c0ce 1272 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1273
114fe488 1274 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1275 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1276 WRPLL_DIVIDER_POST(p);
1277
dd3cd74a
ACO		 1278 memset(&crtc_state->dpll_hw_state, 0,
1279 sizeof(crtc_state->dpll_hw_state));
1280
190f68c5 1281 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1282
190f68c5 1283 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1284 if (pll == NULL) {
1285 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1286 pipe_name(intel_crtc->pipe));
1287 return false;
0694001b 1288 }
d452c5b6 1289
190f68c5 1290 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 1291 }
1292
6441ab5f
PZ		 1293 return true;
1294}
1295
dc253813
DL		 1296struct skl_wrpll_context {
1297 uint64_t min_deviation; /* current minimal deviation */
1298 uint64_t central_freq; /* chosen central freq */
1299 uint64_t dco_freq; /* chosen dco freq */
1300 unsigned int p; /* chosen divider */
1301};
1302
1303static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1304{
1305 memset(ctx, 0, sizeof(*ctx));
1306
1307 ctx->min_deviation = U64_MAX;
1308}
1309
1310/* DCO freq must be within +1%/-6% of the DCO central freq */
1311#define SKL_DCO_MAX_PDEVIATION 100
1312#define SKL_DCO_MAX_NDEVIATION 600
1313
1314static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1315 uint64_t central_freq,
1316 uint64_t dco_freq,
1317 unsigned int divider)
1318{
1319 uint64_t deviation;
1320
1321 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1322 central_freq);
1323
1324 /* positive deviation */
1325 if (dco_freq >= central_freq) {
1326 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1327 deviation < ctx->min_deviation) {
1328 ctx->min_deviation = deviation;
1329 ctx->central_freq = central_freq;
1330 ctx->dco_freq = dco_freq;
1331 ctx->p = divider;
1332 }
1333 /* negative deviation */
1334 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1335 deviation < ctx->min_deviation) {
1336 ctx->min_deviation = deviation;
1337 ctx->central_freq = central_freq;
1338 ctx->dco_freq = dco_freq;
1339 ctx->p = divider;
1340 }
dc253813
DL		 1341}
1342
1343static void skl_wrpll_get_multipliers(unsigned int p,
1344 unsigned int *p0 /* out */,
1345 unsigned int *p1 /* out */,
1346 unsigned int *p2 /* out */)
1347{
1348 /* even dividers */
1349 if (p % 2 == 0) {
1350 unsigned int half = p / 2;
1351
1352 if (half == 1 || half == 2 || half == 3 || half == 5) {
1353 *p0 = 2;
1354 *p1 = 1;
1355 *p2 = half;
1356 } else if (half % 2 == 0) {
1357 *p0 = 2;
1358 *p1 = half / 2;
1359 *p2 = 2;
1360 } else if (half % 3 == 0) {
1361 *p0 = 3;
1362 *p1 = half / 3;
1363 *p2 = 2;
1364 } else if (half % 7 == 0) {
1365 *p0 = 7;
1366 *p1 = half / 7;
1367 *p2 = 2;
1368 }
1369 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1370 *p0 = 3;
1371 *p1 = 1;
1372 *p2 = p / 3;
1373 } else if (p == 5 || p == 7) {
1374 *p0 = p;
1375 *p1 = 1;
1376 *p2 = 1;
1377 } else if (p == 15) {
1378 *p0 = 3;
1379 *p1 = 1;
1380 *p2 = 5;
1381 } else if (p == 21) {
1382 *p0 = 7;
1383 *p1 = 1;
1384 *p2 = 3;
1385 } else if (p == 35) {
1386 *p0 = 7;
1387 *p1 = 1;
1388 *p2 = 5;
1389 }
1390}
1391
82d35437
S		 1392struct skl_wrpll_params {
1393 uint32_t dco_fraction;
1394 uint32_t dco_integer;
1395 uint32_t qdiv_ratio;
1396 uint32_t qdiv_mode;
1397 uint32_t kdiv;
1398 uint32_t pdiv;
1399 uint32_t central_freq;
1400};
1401
76516fbc
DL		 1402static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1403 uint64_t afe_clock,
1404 uint64_t central_freq,
1405 uint32_t p0, uint32_t p1, uint32_t p2)
1406{
1407 uint64_t dco_freq;
1408
76516fbc
DL		 1409 switch (central_freq) {
1410 case 9600000000ULL:
1411 params->central_freq = 0;
1412 break;
1413 case 9000000000ULL:
1414 params->central_freq = 1;
1415 break;
1416 case 8400000000ULL:
1417 params->central_freq = 3;
1418 }
1419
1420 switch (p0) {
1421 case 1:
1422 params->pdiv = 0;
1423 break;
1424 case 2:
1425 params->pdiv = 1;
1426 break;
1427 case 3:
1428 params->pdiv = 2;
1429 break;
1430 case 7:
1431 params->pdiv = 4;
1432 break;
1433 default:
1434 WARN(1, "Incorrect PDiv\n");
1435 }
1436
1437 switch (p2) {
1438 case 5:
1439 params->kdiv = 0;
1440 break;
1441 case 2:
1442 params->kdiv = 1;
1443 break;
1444 case 3:
1445 params->kdiv = 2;
1446 break;
1447 case 1:
1448 params->kdiv = 3;
1449 break;
1450 default:
1451 WARN(1, "Incorrect KDiv\n");
1452 }
1453
1454 params->qdiv_ratio = p1;
1455 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1456
1457 dco_freq = p0 * p1 * p2 * afe_clock;
1458
1459 /*
1460 * Intermediate values are in Hz.
1461 * Divide by MHz to match bsepc
1462 */
30a7862d 1463 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
76516fbc 1464 params->dco_fraction =
30a7862d
DL		 1465 div_u64((div_u64(dco_freq, 24) -
1466 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
76516fbc
DL		 1467}
1468
318bd821 1469static bool
82d35437
S		 1470skl_ddi_calculate_wrpll(int clock /* in Hz */,
1471 struct skl_wrpll_params *wrpll_params)
1472{
1473 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1474 uint64_t dco_central_freq[3] = {8400000000ULL,
1475 9000000000ULL,
1476 9600000000ULL};
dc253813
DL		 1477 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1478 24, 28, 30, 32, 36, 40, 42, 44,
1479 48, 52, 54, 56, 60, 64, 66, 68,
1480 70, 72, 76, 78, 80, 84, 88, 90,
1481 92, 96, 98 };
1482 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1483 static const struct {
1484 const int *list;
1485 int n_dividers;
1486 } dividers[] = {
1487 { even_dividers, ARRAY_SIZE(even_dividers) },
1488 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1489 };
1490 struct skl_wrpll_context ctx;
1491 unsigned int dco, d, i;
1492 unsigned int p0, p1, p2;
1493
1494 skl_wrpll_context_init(&ctx);
1495
1496 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1497 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1498 for (i = 0; i < dividers[d].n_dividers; i++) {
1499 unsigned int p = dividers[d].list[i];
1500 uint64_t dco_freq = p * afe_clock;
1501
1502 skl_wrpll_try_divider(&ctx,
1503 dco_central_freq[dco],
1504 dco_freq,
1505 p);
e7ad9878
DL		 1506 /*
1507 * Skip the remaining dividers if we're sure to
1508 * have found the definitive divider, we can't
1509 * improve a 0 deviation.
1510 */
1511 if (ctx.min_deviation == 0)
1512 goto skip_remaining_dividers;
82d35437
S		 1513 }
1514 }
267db663 1515
e7ad9878 1516skip_remaining_dividers:
267db663
DL		 1517 /*
1518 * If a solution is found with an even divider, prefer
1519 * this one.
1520 */
1521 if (d == 0 && ctx.p)
1522 break;
82d35437
S		 1523 }
1524
dc253813
DL		 1525 if (!ctx.p) {
1526 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
318bd821 1527 return false;
dc253813 1528 }
82d35437 1529
dc253813
DL		 1530 /*
1531 * gcc incorrectly analyses that these can be used without being
1532 * initialized. To be fair, it's hard to guess.
1533 */
1534 p0 = p1 = p2 = 0;
1535 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1536 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1537 p0, p1, p2);
318bd821
DL		 1538
1539 return true;
82d35437
S		 1540}
1541
82d35437
S		 1542static bool
1543skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1544 struct intel_crtc_state *crtc_state,
82d35437
S		 1545 struct intel_encoder *intel_encoder,
1546 int clock)
1547{
1548 struct intel_shared_dpll *pll;
1549 uint32_t ctrl1, cfgcr1, cfgcr2;
1550
1551 /*
1552 * See comment in intel_dpll_hw_state to understand why we always use 0
1553 * as the DPLL id in this function.
1554 */
1555
1556 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1557
1558 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1559 struct skl_wrpll_params wrpll_params = { 0, };
1560
1561 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1562
318bd821
DL		 1563 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1564 return false;
82d35437
S		 1565
1566 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1567 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1568 wrpll_params.dco_integer;
1569
1570 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1571 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1572 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1573 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1574 wrpll_params.central_freq;
1575 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1576 struct drm_encoder *encoder = &intel_encoder->base;
1577 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1578
1579 switch (intel_dp->link_bw) {
1580 case DP_LINK_BW_1_62:
71cd8423 1581 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
82d35437
S		 1582 break;
1583 case DP_LINK_BW_2_7:
71cd8423 1584 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
82d35437
S		 1585 break;
1586 case DP_LINK_BW_5_4:
71cd8423 1587 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
82d35437
S		 1588 break;
1589 }
1590
1591 cfgcr1 = cfgcr2 = 0;
1592 } else /* eDP */
1593 return true;
1594
dd3cd74a
ACO		 1595 memset(&crtc_state->dpll_hw_state, 0,
1596 sizeof(crtc_state->dpll_hw_state));
1597
190f68c5
ACO		 1598 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1599 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1600 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1601
190f68c5 1602 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1603 if (pll == NULL) {
1604 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1605 pipe_name(intel_crtc->pipe));
1606 return false;
1607 }
1608
1609 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1610 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1611
1612 return true;
1613}
0220ab6e 1614
d683f3bc
S		 1615/* bxt clock parameters */
1616struct bxt_clk_div {
64987fc5 1617 int clock;
d683f3bc
S		 1618 uint32_t p1;
1619 uint32_t p2;
1620 uint32_t m2_int;
1621 uint32_t m2_frac;
1622 bool m2_frac_en;
1623 uint32_t n;
d683f3bc
S		 1624};
1625
1626/* pre-calculated values for DP linkrates */
64987fc5
SJ		 1627static const struct bxt_clk_div bxt_dp_clk_val[] = {
1628 {162000, 4, 2, 32, 1677722, 1, 1},
1629 {270000, 4, 1, 27, 0, 0, 1},
1630 {540000, 2, 1, 27, 0, 0, 1},
1631 {216000, 3, 2, 32, 1677722, 1, 1},
1632 {243000, 4, 1, 24, 1258291, 1, 1},
1633 {324000, 4, 1, 32, 1677722, 1, 1},
1634 {432000, 3, 1, 32, 1677722, 1, 1}
d683f3bc
S		 1635};
1636
1637static bool
1638bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1639 struct intel_crtc_state *crtc_state,
1640 struct intel_encoder *intel_encoder,
1641 int clock)
1642{
1643 struct intel_shared_dpll *pll;
1644 struct bxt_clk_div clk_div = {0};
b6dc71f3
VK		 1645 int vco = 0;
1646 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
e6292556 1647 uint32_t lanestagger;
d683f3bc
S		 1648
1649 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1650 intel_clock_t best_clock;
1651
1652 /* Calculate HDMI div */
1653 /*
1654 * FIXME: tie the following calculation into
1655 * i9xx_crtc_compute_clock
1656 */
1657 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1658 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1659 clock, pipe_name(intel_crtc->pipe));
1660 return false;
1661 }
1662
1663 clk_div.p1 = best_clock.p1;
1664 clk_div.p2 = best_clock.p2;
1665 WARN_ON(best_clock.m1 != 2);
1666 clk_div.n = best_clock.n;
1667 clk_div.m2_int = best_clock.m2 >> 22;
1668 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1669 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1670
b6dc71f3 1671 vco = best_clock.vco;
d683f3bc
S		 1672 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1673 intel_encoder->type == INTEL_OUTPUT_EDP) {
64987fc5 1674 int i;
d683f3bc 1675
64987fc5
SJ		 1676 clk_div = bxt_dp_clk_val[0];
1677 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1678 if (bxt_dp_clk_val[i].clock == clock) {
1679 clk_div = bxt_dp_clk_val[i];
1680 break;
1681 }
d683f3bc 1682 }
b6dc71f3
VK		 1683 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1684 }
1685
e6292556 1686 if (vco >= 6200000 && vco <= 6700000) {
b6dc71f3
VK		 1687 prop_coef = 4;
1688 int_coef = 9;
1689 gain_ctl = 3;
1690 targ_cnt = 8;
1691 } else if ((vco > 5400000 && vco < 6200000) ||
1692 (vco >= 4800000 && vco < 5400000)) {
1693 prop_coef = 5;
1694 int_coef = 11;
1695 gain_ctl = 3;
1696 targ_cnt = 9;
b6dc71f3
VK		 1697 } else if (vco == 5400000) {
1698 prop_coef = 3;
1699 int_coef = 8;
1700 gain_ctl = 1;
1701 targ_cnt = 9;
1702 } else {
1703 DRM_ERROR("Invalid VCO\n");
1704 return false;
d683f3bc
S		 1705 }
1706
dd3cd74a
ACO		 1707 memset(&crtc_state->dpll_hw_state, 0,
1708 sizeof(crtc_state->dpll_hw_state));
1709
e0681e38
VK		 1710 if (clock > 270000)
1711 lanestagger = 0x18;
1712 else if (clock > 135000)
1713 lanestagger = 0x0d;
1714 else if (clock > 67000)
1715 lanestagger = 0x07;
1716 else if (clock > 33000)
1717 lanestagger = 0x04;
1718 else
1719 lanestagger = 0x02;
1720
d683f3bc
S		 1721 crtc_state->dpll_hw_state.ebb0 =
1722 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1723 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1724 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1725 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1726
1727 if (clk_div.m2_frac_en)
1728 crtc_state->dpll_hw_state.pll3 =
1729 PORT_PLL_M2_FRAC_ENABLE;
1730
1731 crtc_state->dpll_hw_state.pll6 =
b6dc71f3 1732 prop_coef | PORT_PLL_INT_COEFF(int_coef);
d683f3bc 1733 crtc_state->dpll_hw_state.pll6 |=
b6dc71f3
VK		 1734 PORT_PLL_GAIN_CTL(gain_ctl);
1735
1736 crtc_state->dpll_hw_state.pll8 = targ_cnt;
d683f3bc 1737
05712c15
ID		 1738 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1739
e6292556
VK		 1740 crtc_state->dpll_hw_state.pll10 =
1741 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1742 | PORT_PLL_DCO_AMP_OVR_EN_H;
d683f3bc 1743
05712c15
ID		 1744 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1745
d683f3bc 1746 crtc_state->dpll_hw_state.pcsdw12 =
e0681e38 1747 LANESTAGGER_STRAP_OVRD | lanestagger;
d683f3bc
S		 1748
1749 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1750 if (pll == NULL) {
1751 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1752 pipe_name(intel_crtc->pipe));
1753 return false;
1754 }
1755
1756 /* shared DPLL id 0 is DPLL A */
1757 crtc_state->ddi_pll_sel = pll->id;
1758
1759 return true;
1760}
1761
0220ab6e
DL		 1762/*
1763 * Tries to find a *shared* PLL for the CRTC and store it in
1764 * intel_crtc->ddi_pll_sel.
1765 *
1766 * For private DPLLs, compute_config() should do the selection for us. This
1767 * function should be folded into compute_config() eventually.
1768 */
190f68c5
ACO		 1769bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1770 struct intel_crtc_state *crtc_state)
0220ab6e 1771{
82d35437 1772 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1773 struct intel_encoder *intel_encoder =
3165c074 1774 intel_ddi_get_crtc_new_encoder(crtc_state);
190f68c5 1775 int clock = crtc_state->port_clock;
0220ab6e 1776
82d35437 1777 if (IS_SKYLAKE(dev))
190f68c5
ACO		 1778 return skl_ddi_pll_select(intel_crtc, crtc_state,
1779 intel_encoder, clock);
d683f3bc
S		 1780 else if (IS_BROXTON(dev))
1781 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1782 intel_encoder, clock);
82d35437 1783 else
190f68c5
ACO		 1784 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1785 intel_encoder, clock);
0220ab6e
DL		 1786}
1787
dae84799
PZ		 1788void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1789{
1790 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1792 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1793 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1794 int type = intel_encoder->type;
1795 uint32_t temp;
1796
0e32b39c 1797 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1798 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1799 switch (intel_crtc->config->pipe_bpp) {
dae84799 1800 case 18:
c9809791 1801 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1802 break;
1803 case 24:
c9809791 1804 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1805 break;
1806 case 30:
c9809791 1807 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1808 break;
1809 case 36:
c9809791 1810 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1811 break;
1812 default:
4e53c2e0 1813 BUG();
dae84799 1814 }
c9809791 1815 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1816 }
1817}
1818
0e32b39c
DA		 1819void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1820{
1821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1822 struct drm_device *dev = crtc->dev;
1823 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1824 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1825 uint32_t temp;
1826 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1827 if (state == true)
1828 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1829 else
1830 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1831 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1832}
1833
8228c251 1834void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1835{
1836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1837 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1838 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1839 struct drm_device *dev = crtc->dev;
1840 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1841 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1842 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1843 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1844 int type = intel_encoder->type;
8d9ddbcb
PZ		 1845 uint32_t temp;
1846
ad80a810
PZ		 1847 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1848 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1849 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1850
6e3c9717 1851 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1852 case 18:
ad80a810 1853 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1854 break;
1855 case 24:
ad80a810 1856 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1857 break;
1858 case 30:
ad80a810 1859 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1860 break;
1861 case 36:
ad80a810 1862 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1863 break;
1864 default:
4e53c2e0 1865 BUG();
dfcef252 1866 }
72662e10 1867
6e3c9717 1868 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1869 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1870 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1871 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1872
e6f0bfc4
PZ		 1873 if (cpu_transcoder == TRANSCODER_EDP) {
1874 switch (pipe) {
1875 case PIPE_A:
c7670b10
PZ		 1876 /* On Haswell, can only use the always-on power well for
1877 * eDP when not using the panel fitter, and when not
1878 * using motion blur mitigation (which we don't
1879 * support). */
fabf6e51 1880 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1881 (intel_crtc->config->pch_pfit.enabled ||
1882 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1883 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1884 else
1885 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1886 break;
1887 case PIPE_B:
1888 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1889 break;
1890 case PIPE_C:
1891 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1892 break;
1893 default:
1894 BUG();
1895 break;
1896 }
1897 }
1898
7739c33b 1899 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1900 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1901 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1902 else
ad80a810 1903 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1904
7739c33b 1905 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1906 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1907 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1908
1909 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1910 type == INTEL_OUTPUT_EDP) {
1911 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1912
0e32b39c
DA		 1913 if (intel_dp->is_mst) {
1914 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1915 } else
1916 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1917
1918 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1919 } else if (type == INTEL_OUTPUT_DP_MST) {
1920 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1921
1922 if (intel_dp->is_mst) {
1923 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1924 } else
1925 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1926
17aa6be9 1927 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1928 } else {
84f44ce7
VS		 1929 WARN(1, "Invalid encoder type %d for pipe %c\n",
1930 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1931 }
1932
ad80a810 1933 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1934}
72662e10 1935
ad80a810
PZ		 1936void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1937 enum transcoder cpu_transcoder)
8d9ddbcb 1938{
ad80a810 1939 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1940 uint32_t val = I915_READ(reg);
1941
0e32b39c 1942 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1943 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1944 I915_WRITE(reg, val);
72662e10
ED		 1945}
1946
bcbc889b
PZ		 1947bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1948{
1949 struct drm_device *dev = intel_connector->base.dev;
1950 struct drm_i915_private *dev_priv = dev->dev_private;
1951 struct intel_encoder *intel_encoder = intel_connector->encoder;
1952 int type = intel_connector->base.connector_type;
1953 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1954 enum pipe pipe = 0;
1955 enum transcoder cpu_transcoder;
882244a3 1956 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1957 uint32_t tmp;
1958
882244a3 1959 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1960 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1961 return false;
1962
bcbc889b
PZ		 1963 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1964 return false;
1965
1966 if (port == PORT_A)
1967 cpu_transcoder = TRANSCODER_EDP;
1968 else
1a240d4d 1969 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1970
1971 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1972
1973 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1974 case TRANS_DDI_MODE_SELECT_HDMI:
1975 case TRANS_DDI_MODE_SELECT_DVI:
1976 return (type == DRM_MODE_CONNECTOR_HDMIA);
1977
1978 case TRANS_DDI_MODE_SELECT_DP_SST:
1979 if (type == DRM_MODE_CONNECTOR_eDP)
1980 return true;
bcbc889b 1981 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1982 case TRANS_DDI_MODE_SELECT_DP_MST:
1983 /* if the transcoder is in MST state then
1984 * connector isn't connected */
1985 return false;
bcbc889b
PZ		 1986
1987 case TRANS_DDI_MODE_SELECT_FDI:
1988 return (type == DRM_MODE_CONNECTOR_VGA);
1989
1990 default:
1991 return false;
1992 }
1993}
1994
85234cdc
DV		 1995bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1996 enum pipe *pipe)
1997{
1998 struct drm_device *dev = encoder->base.dev;
1999 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 2000 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 2001 enum intel_display_power_domain power_domain;
85234cdc
DV		 2002 u32 tmp;
2003 int i;
2004
6d129bea 2005 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 2006 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 2007 return false;
2008
fe43d3f5 2009 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 2010
2011 if (!(tmp & DDI_BUF_CTL_ENABLE))
2012 return false;
2013
ad80a810
PZ		 2014 if (port == PORT_A) {
2015 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 2016
ad80a810
PZ		 2017 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2018 case TRANS_DDI_EDP_INPUT_A_ON:
2019 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2020 *pipe = PIPE_A;
2021 break;
2022 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2023 *pipe = PIPE_B;
2024 break;
2025 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2026 *pipe = PIPE_C;
2027 break;
2028 }
2029
2030 return true;
2031 } else {
2032 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
2033 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
2034
2035 if ((tmp & TRANS_DDI_PORT_MASK)
2036 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 2037 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
2038 return false;
2039
ad80a810
PZ		 2040 *pipe = i;
2041 return true;
2042 }
85234cdc
DV		 2043 }
2044 }
2045
84f44ce7 2046 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 2047
22f9fe50 2048 return false;
85234cdc
DV		 2049}
2050
fc914639
PZ		 2051void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2052{
2053 struct drm_crtc *crtc = &intel_crtc->base;
2054 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2055 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2056 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 2057 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2058
bb523fc0
PZ		 2059 if (cpu_transcoder != TRANSCODER_EDP)
2060 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2061 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2062}
2063
2064void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2065{
2066 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 2067 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2068
bb523fc0
PZ		 2069 if (cpu_transcoder != TRANSCODER_EDP)
2070 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2071 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2072}
2073
f8896f5d
DW		 2074static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
2075 enum port port, int type)
2076{
2077 struct drm_i915_private *dev_priv = dev->dev_private;
2078 const struct ddi_buf_trans *ddi_translations;
2079 uint8_t iboost;
2080 int n_entries;
2081 u32 reg;
2082
2083 if (type == INTEL_OUTPUT_DISPLAYPORT) {
2084 ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
2085 iboost = ddi_translations[port].i_boost;
2086 } else if (type == INTEL_OUTPUT_EDP) {
2087 ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
2088 iboost = ddi_translations[port].i_boost;
2089 } else if (type == INTEL_OUTPUT_HDMI) {
2090 ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
2091 iboost = ddi_translations[port].i_boost;
2092 } else {
2093 return;
2094 }
2095
2096 /* Make sure that the requested I_boost is valid */
2097 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2098 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2099 return;
2100 }
2101
2102 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2103 reg &= ~BALANCE_LEG_MASK(port);
2104 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2105
2106 if (iboost)
2107 reg |= iboost << BALANCE_LEG_SHIFT(port);
2108 else
2109 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2110
2111 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2112}
2113
2114static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
2115 enum port port, int type)
96fb9f9b
VK		 2116{
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2118 const struct bxt_ddi_buf_trans *ddi_translations;
2119 u32 n_entries, i;
2120 uint32_t val;
2121
2122 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2123 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2124 ddi_translations = bxt_ddi_translations_dp;
2125 } else if (type == INTEL_OUTPUT_HDMI) {
2126 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2127 ddi_translations = bxt_ddi_translations_hdmi;
2128 } else {
2129 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2130 type);
2131 return;
2132 }
2133
2134 /* Check if default value has to be used */
2135 if (level >= n_entries ||
2136 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2137 for (i = 0; i < n_entries; i++) {
2138 if (ddi_translations[i].default_index) {
2139 level = i;
2140 break;
2141 }
2142 }
2143 }
2144
2145 /*
2146 * While we write to the group register to program all lanes at once we
2147 * can read only lane registers and we pick lanes 0/1 for that.
2148 */
2149 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2150 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2151 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2152
2153 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2154 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2155 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2156 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2157 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2158
2159 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
2160 val &= ~UNIQE_TRANGE_EN_METHOD;
2161 if (ddi_translations[level].enable)
2162 val |= UNIQE_TRANGE_EN_METHOD;
2163 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2164
2165 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2166 val &= ~DE_EMPHASIS;
2167 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2168 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2169
2170 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2171 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2172 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2173}
2174
f8896f5d
DW		 2175static uint32_t translate_signal_level(int signal_levels)
2176{
2177 uint32_t level;
2178
2179 switch (signal_levels) {
2180 default:
2181 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2182 signal_levels);
2183 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2184 level = 0;
2185 break;
2186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2187 level = 1;
2188 break;
2189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2190 level = 2;
2191 break;
2192 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2193 level = 3;
2194 break;
2195
2196 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2197 level = 4;
2198 break;
2199 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2200 level = 5;
2201 break;
2202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2203 level = 6;
2204 break;
2205
2206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2207 level = 7;
2208 break;
2209 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2210 level = 8;
2211 break;
2212
2213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2214 level = 9;
2215 break;
2216 }
2217
2218 return level;
2219}
2220
2221uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2222{
2223 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2224 struct drm_device *dev = dport->base.base.dev;
2225 struct intel_encoder *encoder = &dport->base;
2226 uint8_t train_set = intel_dp->train_set[0];
2227 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2228 DP_TRAIN_PRE_EMPHASIS_MASK);
2229 enum port port = dport->port;
2230 uint32_t level;
2231
2232 level = translate_signal_level(signal_levels);
2233
2234 if (IS_SKYLAKE(dev))
2235 skl_ddi_set_iboost(dev, level, port, encoder->type);
2236 else if (IS_BROXTON(dev))
2237 bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
2238
2239 return DDI_BUF_TRANS_SELECT(level);
2240}
2241
00c09d70 2242static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 2243{
c19b0669 2244 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2245 struct drm_device *dev = encoder->dev;
2246 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 2247 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 2248 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2249 int type = intel_encoder->type;
96fb9f9b 2250 int hdmi_level;
6441ab5f 2251
82a4d9c0
PZ		 2252 if (type == INTEL_OUTPUT_EDP) {
2253 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 2254 intel_edp_panel_on(intel_dp);
82a4d9c0 2255 }
6441ab5f 2256
efa80add 2257 if (IS_SKYLAKE(dev)) {
6e3c9717 2258 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 2259 uint32_t val;
2260
5416d871
DL		 2261 /*
2262 * DPLL0 is used for eDP and is the only "private" DPLL (as
2263 * opposed to shared) on SKL
2264 */
2265 if (type == INTEL_OUTPUT_EDP) {
2266 WARN_ON(dpll != SKL_DPLL0);
2267
2268 val = I915_READ(DPLL_CTRL1);
2269
2270 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2271 DPLL_CTRL1_SSC(dpll) |
71cd8423 2272 DPLL_CTRL1_LINK_RATE_MASK(dpll));
6e3c9717 2273 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 2274
2275 I915_WRITE(DPLL_CTRL1, val);
2276 POSTING_READ(DPLL_CTRL1);
2277 }
2278
2279 /* DDI -> PLL mapping */
efa80add
S		 2280 val = I915_READ(DPLL_CTRL2);
2281
2282 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2283 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2284 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2285 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2286
2287 I915_WRITE(DPLL_CTRL2, val);
5416d871 2288
1ab23380 2289 } else if (INTEL_INFO(dev)->gen < 9) {
6e3c9717
ACO		 2290 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2291 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 2292 }
c19b0669 2293
82a4d9c0 2294 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 2295 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 2296
44905a27 2297 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 2298
2299 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2300 intel_dp_start_link_train(intel_dp);
2301 intel_dp_complete_link_train(intel_dp);
23f08d83 2302 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 2303 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 2304 } else if (type == INTEL_OUTPUT_HDMI) {
2305 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2306
96fb9f9b
VK		 2307 if (IS_BROXTON(dev)) {
2308 hdmi_level = dev_priv->vbt.
2309 ddi_port_info[port].hdmi_level_shift;
2310 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
2311 INTEL_OUTPUT_HDMI);
2312 }
30cf6db8 2313 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 2314 crtc->config->has_hdmi_sink,
2315 &crtc->config->base.adjusted_mode);
c19b0669 2316 }
6441ab5f
PZ		 2317}
2318
00c09d70 2319static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 2320{
2321 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2322 struct drm_device *dev = encoder->dev;
2323 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 2324 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2325 int type = intel_encoder->type;
2886e93f 2326 uint32_t val;
a836bdf9 2327 bool wait = false;
2886e93f
PZ		 2328
2329 val = I915_READ(DDI_BUF_CTL(port));
2330 if (val & DDI_BUF_CTL_ENABLE) {
2331 val &= ~DDI_BUF_CTL_ENABLE;
2332 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2333 wait = true;
2886e93f 2334 }
6441ab5f 2335
a836bdf9
PZ		 2336 val = I915_READ(DP_TP_CTL(port));
2337 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2338 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2339 I915_WRITE(DP_TP_CTL(port), val);
2340
2341 if (wait)
2342 intel_wait_ddi_buf_idle(dev_priv, port);
2343
76bb80ed 2344 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 2345 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 2346 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 2347 intel_edp_panel_vdd_on(intel_dp);
4be73780 2348 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2349 }
2350
efa80add
S		 2351 if (IS_SKYLAKE(dev))
2352 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2353 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 2354 else if (INTEL_INFO(dev)->gen < 9)
efa80add 2355 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 2356}
2357
00c09d70 2358static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 2359{
6547fef8 2360 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2361 struct drm_crtc *crtc = encoder->crtc;
2362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 2363 struct drm_device *dev = encoder->dev;
72662e10 2364 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 2365 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2366 int type = intel_encoder->type;
72662e10 2367
6547fef8 2368 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2369 struct intel_digital_port *intel_dig_port =
2370 enc_to_dig_port(encoder);
2371
6547fef8
PZ		 2372 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2373 * are ignored so nothing special needs to be done besides
2374 * enabling the port.
2375 */
876a8cdf 2376 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2377 intel_dig_port->saved_port_bits |
2378 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2379 } else if (type == INTEL_OUTPUT_EDP) {
2380 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2381
23f08d83 2382 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 2383 intel_dp_stop_link_train(intel_dp);
2384
4be73780 2385 intel_edp_backlight_on(intel_dp);
0bc12bcb 2386 intel_psr_enable(intel_dp);
c395578e 2387 intel_edp_drrs_enable(intel_dp);
6547fef8 2388 }
7b9f35a6 2389
6e3c9717 2390 if (intel_crtc->config->has_audio) {
d45a0bf5 2391 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 2392 intel_audio_codec_enable(intel_encoder);
7b9f35a6 2393 }
5ab432ef
DV		 2394}
2395
00c09d70 2396static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 2397{
d6c50ff8 2398 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2399 struct drm_crtc *crtc = encoder->crtc;
2400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 2401 int type = intel_encoder->type;
7b9f35a6
WX		 2402 struct drm_device *dev = encoder->dev;
2403 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 2404
6e3c9717 2405 if (intel_crtc->config->has_audio) {
69bfe1a9 2406 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 2407 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2408 }
2831d842 2409
d6c50ff8
PZ		 2410 if (type == INTEL_OUTPUT_EDP) {
2411 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2412
c395578e 2413 intel_edp_drrs_disable(intel_dp);
0bc12bcb 2414 intel_psr_disable(intel_dp);
4be73780 2415 intel_edp_backlight_off(intel_dp);
d6c50ff8 2416 }
72662e10 2417}
79f689aa 2418
e0b01be4
DV		 2419static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
2420 struct intel_shared_dpll *pll)
2421{
3e369b76 2422 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 2423 POSTING_READ(WRPLL_CTL(pll->id));
2424 udelay(20);
2425}
2426
12030431
DV		 2427static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
2428 struct intel_shared_dpll *pll)
2429{
2430 uint32_t val;
2431
2432 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2433 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2434 POSTING_READ(WRPLL_CTL(pll->id));
2435}
2436
d452c5b6
DV		 2437static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2438 struct intel_shared_dpll *pll,
2439 struct intel_dpll_hw_state *hw_state)
2440{
2441 uint32_t val;
2442
f458ebbc 2443 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2444 return false;
2445
2446 val = I915_READ(WRPLL_CTL(pll->id));
2447 hw_state->wrpll = val;
2448
2449 return val & WRPLL_PLL_ENABLE;
2450}
2451
ca1381b5 2452static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2453 "WRPLL 1",
2454 "WRPLL 2",
2455};
2456
143b307c 2457static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2458{
9cd86933
DV		 2459 int i;
2460
716c2e55 2461 dev_priv->num_shared_dpll = 2;
9cd86933 2462
716c2e55 2463 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 2464 dev_priv->shared_dplls[i].id = i;
2465 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 2466 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 2467 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 2468 dev_priv->shared_dplls[i].get_hw_state =
2469 hsw_ddi_pll_get_hw_state;
9cd86933 2470 }
143b307c
DL		 2471}
2472
d1a2dc78
S		 2473static const char * const skl_ddi_pll_names[] = {
2474 "DPLL 1",
2475 "DPLL 2",
2476 "DPLL 3",
2477};
2478
2479struct skl_dpll_regs {
2480 u32 ctl, cfgcr1, cfgcr2;
2481};
2482
2483/* this array is indexed by the *shared* pll id */
2484static const struct skl_dpll_regs skl_dpll_regs[3] = {
2485 {
2486 /* DPLL 1 */
2487 .ctl = LCPLL2_CTL,
2488 .cfgcr1 = DPLL1_CFGCR1,
2489 .cfgcr2 = DPLL1_CFGCR2,
2490 },
2491 {
2492 /* DPLL 2 */
2493 .ctl = WRPLL_CTL1,
2494 .cfgcr1 = DPLL2_CFGCR1,
2495 .cfgcr2 = DPLL2_CFGCR2,
2496 },
2497 {
2498 /* DPLL 3 */
2499 .ctl = WRPLL_CTL2,
2500 .cfgcr1 = DPLL3_CFGCR1,
2501 .cfgcr2 = DPLL3_CFGCR2,
2502 },
2503};
2504
2505static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2506 struct intel_shared_dpll *pll)
2507{
2508 uint32_t val;
2509 unsigned int dpll;
2510 const struct skl_dpll_regs *regs = skl_dpll_regs;
2511
2512 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2513 dpll = pll->id + 1;
2514
2515 val = I915_READ(DPLL_CTRL1);
2516
2517 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
71cd8423 2518 DPLL_CTRL1_LINK_RATE_MASK(dpll));
d1a2dc78
S		 2519 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2520
2521 I915_WRITE(DPLL_CTRL1, val);
2522 POSTING_READ(DPLL_CTRL1);
2523
2524 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2525 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2526 POSTING_READ(regs[pll->id].cfgcr1);
2527 POSTING_READ(regs[pll->id].cfgcr2);
2528
2529 /* the enable bit is always bit 31 */
2530 I915_WRITE(regs[pll->id].ctl,
2531 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2532
2533 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2534 DRM_ERROR("DPLL %d not locked\n", dpll);
2535}
2536
2537static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2538 struct intel_shared_dpll *pll)
2539{
2540 const struct skl_dpll_regs *regs = skl_dpll_regs;
2541
2542 /* the enable bit is always bit 31 */
2543 I915_WRITE(regs[pll->id].ctl,
2544 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2545 POSTING_READ(regs[pll->id].ctl);
2546}
2547
2548static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2549 struct intel_shared_dpll *pll,
2550 struct intel_dpll_hw_state *hw_state)
2551{
2552 uint32_t val;
2553 unsigned int dpll;
2554 const struct skl_dpll_regs *regs = skl_dpll_regs;
2555
2556 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2557 return false;
2558
2559 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2560 dpll = pll->id + 1;
2561
2562 val = I915_READ(regs[pll->id].ctl);
2563 if (!(val & LCPLL_PLL_ENABLE))
2564 return false;
2565
2566 val = I915_READ(DPLL_CTRL1);
2567 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2568
2569 /* avoid reading back stale values if HDMI mode is not enabled */
2570 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2571 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2572 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2573 }
2574
2575 return true;
2576}
2577
2578static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2579{
2580 int i;
2581
2582 dev_priv->num_shared_dpll = 3;
2583
2584 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2585 dev_priv->shared_dplls[i].id = i;
2586 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2587 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2588 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2589 dev_priv->shared_dplls[i].get_hw_state =
2590 skl_ddi_pll_get_hw_state;
2591 }
2592}
2593
5c6706e5
VK		 2594static void broxton_phy_init(struct drm_i915_private *dev_priv,
2595 enum dpio_phy phy)
2596{
2597 enum port port;
2598 uint32_t val;
2599
2600 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2601 val |= GT_DISPLAY_POWER_ON(phy);
2602 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2603
2604 /* Considering 10ms timeout until BSpec is updated */
2605 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2606 DRM_ERROR("timeout during PHY%d power on\n", phy);
2607
2608 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2609 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2610 int lane;
2611
2612 for (lane = 0; lane < 4; lane++) {
2613 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2614 /*
2615 * Note that on CHV this flag is called UPAR, but has
2616 * the same function.
2617 */
2618 val &= ~LATENCY_OPTIM;
2619 if (lane != 1)
2620 val |= LATENCY_OPTIM;
2621
2622 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2623 }
2624 }
2625
2626 /* Program PLL Rcomp code offset */
2627 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2628 val &= ~IREF0RC_OFFSET_MASK;
2629 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2630 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2631
2632 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2633 val &= ~IREF1RC_OFFSET_MASK;
2634 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2635 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2636
2637 /* Program power gating */
2638 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2639 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2640 SUS_CLK_CONFIG;
2641 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2642
2643 if (phy == DPIO_PHY0) {
2644 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2645 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2646 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2647 }
2648
2649 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2650 val &= ~OCL2_LDOFUSE_PWR_DIS;
2651 /*
2652 * On PHY1 disable power on the second channel, since no port is
2653 * connected there. On PHY0 both channels have a port, so leave it
2654 * enabled.
2655 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2656 * power down the second channel on PHY0 as well.
2657 */
2658 if (phy == DPIO_PHY1)
2659 val |= OCL2_LDOFUSE_PWR_DIS;
2660 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2661
2662 if (phy == DPIO_PHY0) {
2663 uint32_t grc_code;
2664 /*
2665 * PHY0 isn't connected to an RCOMP resistor so copy over
2666 * the corresponding calibrated value from PHY1, and disable
2667 * the automatic calibration on PHY0.
2668 */
2669 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2670 10))
2671 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2672
2673 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2674 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2675 grc_code = val << GRC_CODE_FAST_SHIFT |
2676 val << GRC_CODE_SLOW_SHIFT |
2677 val;
2678 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2679
2680 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2681 val |= GRC_DIS | GRC_RDY_OVRD;
2682 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2683 }
2684
2685 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2686 val |= COMMON_RESET_DIS;
2687 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2688}
2689
2690void broxton_ddi_phy_init(struct drm_device *dev)
2691{
2692 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2693 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2694 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2695}
2696
2697static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2698 enum dpio_phy phy)
2699{
2700 uint32_t val;
2701
2702 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2703 val &= ~COMMON_RESET_DIS;
2704 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2705}
2706
2707void broxton_ddi_phy_uninit(struct drm_device *dev)
2708{
2709 struct drm_i915_private *dev_priv = dev->dev_private;
2710
2711 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2712 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2713
2714 /* FIXME: do this in broxton_phy_uninit per phy */
2715 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2716}
2717
dfb82408
S		 2718static const char * const bxt_ddi_pll_names[] = {
2719 "PORT PLL A",
2720 "PORT PLL B",
2721 "PORT PLL C",
2722};
2723
2724static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2725 struct intel_shared_dpll *pll)
2726{
2727 uint32_t temp;
2728 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2729
2730 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2731 temp &= ~PORT_PLL_REF_SEL;
2732 /* Non-SSC reference */
2733 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2734
2735 /* Disable 10 bit clock */
2736 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2737 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2738 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2739
2740 /* Write P1 & P2 */
2741 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2742 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2743 temp |= pll->config.hw_state.ebb0;
2744 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2745
2746 /* Write M2 integer */
2747 temp = I915_READ(BXT_PORT_PLL(port, 0));
2748 temp &= ~PORT_PLL_M2_MASK;
2749 temp |= pll->config.hw_state.pll0;
2750 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2751
2752 /* Write N */
2753 temp = I915_READ(BXT_PORT_PLL(port, 1));
2754 temp &= ~PORT_PLL_N_MASK;
2755 temp |= pll->config.hw_state.pll1;
2756 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2757
2758 /* Write M2 fraction */
2759 temp = I915_READ(BXT_PORT_PLL(port, 2));
2760 temp &= ~PORT_PLL_M2_FRAC_MASK;
2761 temp |= pll->config.hw_state.pll2;
2762 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2763
2764 /* Write M2 fraction enable */
2765 temp = I915_READ(BXT_PORT_PLL(port, 3));
2766 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2767 temp |= pll->config.hw_state.pll3;
2768 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2769
2770 /* Write coeff */
2771 temp = I915_READ(BXT_PORT_PLL(port, 6));
2772 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2773 temp &= ~PORT_PLL_INT_COEFF_MASK;
2774 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2775 temp |= pll->config.hw_state.pll6;
2776 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2777
2778 /* Write calibration val */
2779 temp = I915_READ(BXT_PORT_PLL(port, 8));
2780 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2781 temp |= pll->config.hw_state.pll8;
2782 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2783
b6dc71f3
VK		 2784 temp = I915_READ(BXT_PORT_PLL(port, 9));
2785 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
05712c15 2786 temp |= pll->config.hw_state.pll9;
b6dc71f3
VK		 2787 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2788
2789 temp = I915_READ(BXT_PORT_PLL(port, 10));
2790 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2791 temp &= ~PORT_PLL_DCO_AMP_MASK;
2792 temp |= pll->config.hw_state.pll10;
2793 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
dfb82408
S		 2794
2795 /* Recalibrate with new settings */
2796 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2797 temp |= PORT_PLL_RECALIBRATE;
2798 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
05712c15
ID		 2799 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2800 temp |= pll->config.hw_state.ebb4;
dfb82408
S		 2801 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2802
2803 /* Enable PLL */
2804 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2805 temp |= PORT_PLL_ENABLE;
2806 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2807 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2808
2809 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2810 PORT_PLL_LOCK), 200))
2811 DRM_ERROR("PLL %d not locked\n", port);
2812
2813 /*
2814 * While we write to the group register to program all lanes at once we
2815 * can read only lane registers and we pick lanes 0/1 for that.
2816 */
2817 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2818 temp &= ~LANE_STAGGER_MASK;
2819 temp &= ~LANESTAGGER_STRAP_OVRD;
2820 temp |= pll->config.hw_state.pcsdw12;
2821 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2822}
2823
2824static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2825 struct intel_shared_dpll *pll)
2826{
2827 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2828 uint32_t temp;
2829
2830 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2831 temp &= ~PORT_PLL_ENABLE;
2832 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2833 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2834}
2835
2836static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2837 struct intel_shared_dpll *pll,
2838 struct intel_dpll_hw_state *hw_state)
2839{
2840 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2841 uint32_t val;
2842
2843 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2844 return false;
2845
2846 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2847 if (!(val & PORT_PLL_ENABLE))
2848 return false;
2849
2850 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
793dfa59
ID		 2851 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2852
05712c15
ID		 2853 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2854 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2855
dfb82408 2856 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
793dfa59
ID		 2857 hw_state->pll0 &= PORT_PLL_M2_MASK;
2858
dfb82408 2859 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
793dfa59
ID		 2860 hw_state->pll1 &= PORT_PLL_N_MASK;
2861
dfb82408 2862 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
793dfa59
ID		 2863 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2864
dfb82408 2865 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
793dfa59
ID		 2866 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2867
dfb82408 2868 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
793dfa59
ID		 2869 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2870 PORT_PLL_INT_COEFF_MASK |
2871 PORT_PLL_GAIN_CTL_MASK;
2872
dfb82408 2873 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
793dfa59
ID		 2874 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2875
05712c15
ID		 2876 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
2877 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2878
b6dc71f3 2879 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
793dfa59
ID		 2880 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2881 PORT_PLL_DCO_AMP_MASK;
2882
dfb82408
S		 2883 /*
2884 * While we write to the group register to program all lanes at once we
2885 * can read only lane registers. We configure all lanes the same way, so
2886 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2887 */
2888 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2889 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
2890 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2891 hw_state->pcsdw12,
2892 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
793dfa59 2893 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
dfb82408
S		 2894
2895 return true;
2896}
2897
2898static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2899{
2900 int i;
2901
2902 dev_priv->num_shared_dpll = 3;
2903
2904 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2905 dev_priv->shared_dplls[i].id = i;
2906 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2907 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2908 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2909 dev_priv->shared_dplls[i].get_hw_state =
2910 bxt_ddi_pll_get_hw_state;
2911 }
2912}
2913
143b307c
DL		 2914void intel_ddi_pll_init(struct drm_device *dev)
2915{
2916 struct drm_i915_private *dev_priv = dev->dev_private;
2917 uint32_t val = I915_READ(LCPLL_CTL);
2918
d1a2dc78
S		 2919 if (IS_SKYLAKE(dev))
2920 skl_shared_dplls_init(dev_priv);
dfb82408
S		 2921 else if (IS_BROXTON(dev))
2922 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 2923 else
2924 hsw_shared_dplls_init(dev_priv);
79f689aa 2925
121643c2 2926 if (IS_SKYLAKE(dev)) {
d9062ae5
DL		 2927 int cdclk_freq;
2928
2929 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5d96d8af 2930 dev_priv->skl_boot_cdclk = cdclk_freq;
121643c2
S		 2931 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2932 DRM_ERROR("LCPLL1 is disabled\n");
5d96d8af
DL		 2933 else
2934 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
f8437dd1
VK		 2935 } else if (IS_BROXTON(dev)) {
2936 broxton_init_cdclk(dev);
5c6706e5 2937 broxton_ddi_phy_init(dev);
121643c2
S		 2938 } else {
2939 /*
2940 * The LCPLL register should be turned on by the BIOS. For now
2941 * let's just check its state and print errors in case
2942 * something is wrong. Don't even try to turn it on.
2943 */
2944
2945 if (val & LCPLL_CD_SOURCE_FCLK)
2946 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 2947
121643c2
S		 2948 if (val & LCPLL_PLL_DISABLE)
2949 DRM_ERROR("LCPLL is disabled\n");
2950 }
79f689aa 2951}
c19b0669
PZ		 2952
2953void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
2954{
174edf1f
PZ		 2955 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2956 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 2957 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 2958 enum port port = intel_dig_port->port;
c19b0669 2959 uint32_t val;
f3e227df 2960 bool wait = false;
c19b0669
PZ		 2961
2962 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2963 val = I915_READ(DDI_BUF_CTL(port));
2964 if (val & DDI_BUF_CTL_ENABLE) {
2965 val &= ~DDI_BUF_CTL_ENABLE;
2966 I915_WRITE(DDI_BUF_CTL(port), val);
2967 wait = true;
2968 }
2969
2970 val = I915_READ(DP_TP_CTL(port));
2971 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2972 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2973 I915_WRITE(DP_TP_CTL(port), val);
2974 POSTING_READ(DP_TP_CTL(port));
2975
2976 if (wait)
2977 intel_wait_ddi_buf_idle(dev_priv, port);
2978 }
2979
0e32b39c 2980 val = DP_TP_CTL_ENABLE |
c19b0669 2981 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 2982 if (intel_dp->is_mst)
2983 val |= DP_TP_CTL_MODE_MST;
2984 else {
2985 val |= DP_TP_CTL_MODE_SST;
2986 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2987 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2988 }
c19b0669
PZ		 2989 I915_WRITE(DP_TP_CTL(port), val);
2990 POSTING_READ(DP_TP_CTL(port));
2991
2992 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2993 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2994 POSTING_READ(DDI_BUF_CTL(port));
2995
2996 udelay(600);
2997}
00c09d70 2998
1ad960f2
PZ		 2999void intel_ddi_fdi_disable(struct drm_crtc *crtc)
3000{
3001 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3002 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3003 uint32_t val;
3004
3005 intel_ddi_post_disable(intel_encoder);
3006
3007 val = I915_READ(_FDI_RXA_CTL);
3008 val &= ~FDI_RX_ENABLE;
3009 I915_WRITE(_FDI_RXA_CTL, val);
3010
3011 val = I915_READ(_FDI_RXA_MISC);
3012 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3013 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3014 I915_WRITE(_FDI_RXA_MISC, val);
3015
3016 val = I915_READ(_FDI_RXA_CTL);
3017 val &= ~FDI_PCDCLK;
3018 I915_WRITE(_FDI_RXA_CTL, val);
3019
3020 val = I915_READ(_FDI_RXA_CTL);
3021 val &= ~FDI_RX_PLL_ENABLE;
3022 I915_WRITE(_FDI_RXA_CTL, val);
3023}
3024
6801c18c 3025void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3026 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 3027{
3028 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3029 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 3030 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 3031 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 3032 u32 temp, flags = 0;
3033
3034 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3035 if (temp & TRANS_DDI_PHSYNC)
3036 flags |= DRM_MODE_FLAG_PHSYNC;
3037 else
3038 flags |= DRM_MODE_FLAG_NHSYNC;
3039 if (temp & TRANS_DDI_PVSYNC)
3040 flags |= DRM_MODE_FLAG_PVSYNC;
3041 else
3042 flags |= DRM_MODE_FLAG_NVSYNC;
3043
2d112de7 3044 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3045
3046 switch (temp & TRANS_DDI_BPC_MASK) {
3047 case TRANS_DDI_BPC_6:
3048 pipe_config->pipe_bpp = 18;
3049 break;
3050 case TRANS_DDI_BPC_8:
3051 pipe_config->pipe_bpp = 24;
3052 break;
3053 case TRANS_DDI_BPC_10:
3054 pipe_config->pipe_bpp = 30;
3055 break;
3056 case TRANS_DDI_BPC_12:
3057 pipe_config->pipe_bpp = 36;
3058 break;
3059 default:
3060 break;
3061 }
eb14cb74
VS		 3062
3063 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3064 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3065 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 3066 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3067
3068 if (intel_hdmi->infoframe_enabled(&encoder->base))
3069 pipe_config->has_infoframe = true;
cbc572a9 3070 break;
eb14cb74
VS		 3071 case TRANS_DDI_MODE_SELECT_DVI:
3072 case TRANS_DDI_MODE_SELECT_FDI:
3073 break;
3074 case TRANS_DDI_MODE_SELECT_DP_SST:
3075 case TRANS_DDI_MODE_SELECT_DP_MST:
3076 pipe_config->has_dp_encoder = true;
3077 intel_dp_get_m_n(intel_crtc, pipe_config);
3078 break;
3079 default:
3080 break;
3081 }
10214420 3082
f458ebbc 3083 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 3084 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 3085 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 3086 pipe_config->has_audio = true;
3087 }
9ed109a7 3088
10214420
DV		 3089 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3090 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3091 /*
3092 * This is a big fat ugly hack.
3093 *
3094 * Some machines in UEFI boot mode provide us a VBT that has 18
3095 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3096 * unknown we fail to light up. Yet the same BIOS boots up with
3097 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3098 * max, not what it tells us to use.
3099 *
3100 * Note: This will still be broken if the eDP panel is not lit
3101 * up by the BIOS, and thus we can't get the mode at module
3102 * load.
3103 */
3104 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3105 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3106 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3107 }
11578553 3108
22606a18 3109 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 3110}
3111
00c09d70
PZ		 3112static void intel_ddi_destroy(struct drm_encoder *encoder)
3113{
3114 /* HDMI has nothing special to destroy, so we can go with this. */
3115 intel_dp_encoder_destroy(encoder);
3116}
3117
5bfe2ac0 3118static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 3119 struct intel_crtc_state *pipe_config)
00c09d70 3120{
5bfe2ac0 3121 int type = encoder->type;
eccb140b 3122 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 3123
5bfe2ac0 3124 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 3125
eccb140b
DV		 3126 if (port == PORT_A)
3127 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3128
00c09d70 3129 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 3130 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 3131 else
5bfe2ac0 3132 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 3133}
3134
3135static const struct drm_encoder_funcs intel_ddi_funcs = {
3136 .destroy = intel_ddi_destroy,
3137};
3138
4a28ae58
PZ		 3139static struct intel_connector *
3140intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3141{
3142 struct intel_connector *connector;
3143 enum port port = intel_dig_port->port;
3144
9bdbd0b9 3145 connector = intel_connector_alloc();
4a28ae58
PZ		 3146 if (!connector)
3147 return NULL;
3148
3149 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3150 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3151 kfree(connector);
3152 return NULL;
3153 }
3154
3155 return connector;
3156}
3157
3158static struct intel_connector *
3159intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3160{
3161 struct intel_connector *connector;
3162 enum port port = intel_dig_port->port;
3163
9bdbd0b9 3164 connector = intel_connector_alloc();
4a28ae58
PZ		 3165 if (!connector)
3166 return NULL;
3167
3168 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3169 intel_hdmi_init_connector(intel_dig_port, connector);
3170
3171 return connector;
3172}
3173
00c09d70
PZ		 3174void intel_ddi_init(struct drm_device *dev, enum port port)
3175{
876a8cdf 3176 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 3177 struct intel_digital_port *intel_dig_port;
3178 struct intel_encoder *intel_encoder;
3179 struct drm_encoder *encoder;
311a2094
PZ		 3180 bool init_hdmi, init_dp;
3181
3182 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3183 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3184 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3185 if (!init_dp && !init_hdmi) {
f68d697e 3186 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
311a2094
PZ		 3187 port_name(port));
3188 init_hdmi = true;
3189 init_dp = true;
3190 }
00c09d70 3191
b14c5679 3192 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 3193 if (!intel_dig_port)
3194 return;
3195
00c09d70
PZ		 3196 intel_encoder = &intel_dig_port->base;
3197 encoder = &intel_encoder->base;
3198
3199 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
3200 DRM_MODE_ENCODER_TMDS);
00c09d70 3201
5bfe2ac0 3202 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 3203 intel_encoder->enable = intel_enable_ddi;
3204 intel_encoder->pre_enable = intel_ddi_pre_enable;
3205 intel_encoder->disable = intel_disable_ddi;
3206 intel_encoder->post_disable = intel_ddi_post_disable;
3207 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 3208 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 3209
3210 intel_dig_port->port = port;
bcf53de4
SM		 3211 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3212 (DDI_BUF_PORT_REVERSAL |
3213 DDI_A_4_LANES);
00c09d70
PZ		 3214
3215 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 3216 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3217 intel_encoder->cloneable = 0;
00c09d70 3218
f68d697e
CW		 3219 if (init_dp) {
3220 if (!intel_ddi_init_dp_connector(intel_dig_port))
3221 goto err;
13cf5504 3222
f68d697e 3223 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 3224 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 3225 }
21a8e6a4 3226
311a2094
PZ		 3227 /* In theory we don't need the encoder->type check, but leave it just in
3228 * case we have some really bad VBTs... */
f68d697e
CW		 3229 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3230 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3231 goto err;
21a8e6a4 3232 }
f68d697e
CW		 3233
3234 return;
3235
3236err:
3237 drm_encoder_cleanup(encoder);
3238 kfree(intel_dig_port);
00c09d70 3239}
Linux kernel - Deliverables
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