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GPU-DRM: Delete an unnecessary check before drm_property_unreference_blob()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
45244b87
ED		 37/* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
10122051 41static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 51};
52
10122051 53static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 63};
64
10122051
JN		 65static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 79};
80
10122051 81static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 91};
92
10122051 93static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 103};
104
10122051 105static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 115};
116
10122051
JN		 117static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 129};
130
f8896f5d 131/* Skylake H, S, and Skylake Y with 0.95V VccIO */
7f88e3af 132static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x00009010, 0x000000C7, 0x0 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x00007011, 0x000000C7, 0x0 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x00005012, 0x000000C7, 0x0 },
7f88e3af
DL		 142};
143
f8896f5d
DW		 144/* Skylake U */
145static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
146 { 0x00002016, 0x000000A2, 0x0 },
147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x00007011, 0x00000087, 0x0 },
149 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost */
150 { 0x00002016, 0x0000009D, 0x0 },
151 { 0x00005012, 0x000000C7, 0x0 },
152 { 0x00007011, 0x000000C7, 0x0 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x00005012, 0x000000C7, 0x0 },
155};
156
157/* Skylake Y with 0.85V VccIO */
158static const struct ddi_buf_trans skl_y_085v_ddi_translations_dp[] = {
159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x00007011, 0x00000087, 0x0 },
162 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost */
163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x00005012, 0x000000C7, 0x0 },
165 { 0x00007011, 0x000000C7, 0x0 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x00005012, 0x000000C7, 0x0 },
168};
169
170/*
171 * Skylake H and S, and Skylake Y with 0.95V VccIO
172 * eDP 1.4 low vswing translation parameters
173 */
7ad14a29 174static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185};
186
187/*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 202};
203
f8896f5d
DW		 204/*
205 * Skylake Y with 0.95V VccIO
206 * eDP 1.4 low vswing translation parameters
207 */
208static const struct ddi_buf_trans skl_y_085v_ddi_translations_edp[] = {
209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219};
7ad14a29 220
f8896f5d 221/* Skylake H, S and U, and Skylake Y with 0.95V VccIO */
7f88e3af 222static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x00006012, 0x00000087, 0x0 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x00003015, 0x00000087, 0x0 }, /* Default */
232 { 0x00003015, 0x000000C7, 0x0 },
233 { 0x00000018, 0x000000C7, 0x0 },
234};
235
236/* Skylake Y with 0.85V VccIO */
237static const struct ddi_buf_trans skl_y_085v_ddi_translations_hdmi[] = {
238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x00007011, 0x00000084, 0x0 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x00006013, 0x000000C7, 0x0 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x00003015, 0x000000C7, 0x0 }, /* Default */
247 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost */
248 { 0x00000018, 0x000000C7, 0x0 },
7f88e3af
DL		 249};
250
96fb9f9b
VK		 251struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257};
258
259/* BSpec does not define separate vswing/pre-emphasis values for eDP.
260 * Using DP values for eDP as well.
261 */
262static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
263 /* Idx NT mV diff db */
fe4c63c8
ID		 264 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
265 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
266 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
267 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
268 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
269 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
270 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
271 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
272 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 273 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 274};
275
276/* BSpec has 2 recommended values - entries 0 and 8.
277 * Using the entry with higher vswing.
278 */
279static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
280 /* Idx NT mV diff db */
fe4c63c8
ID		 281 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
282 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
283 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
284 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
285 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
286 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
287 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
288 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
289 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 290 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
291};
292
f8896f5d
DW		 293static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
294 enum port port, int type);
295
a1e6ad66
ID		 296static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
297 struct intel_digital_port **dig_port,
298 enum port *port)
fc914639 299{
0bdee30e 300 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 301 int type = intel_encoder->type;
302
0e32b39c 303 if (type == INTEL_OUTPUT_DP_MST) {
a1e6ad66
ID		 304 *dig_port = enc_to_mst(encoder)->primary;
305 *port = (*dig_port)->port;
0e32b39c 306 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 307 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
a1e6ad66
ID		 308 *dig_port = enc_to_dig_port(encoder);
309 *port = (*dig_port)->port;
fc914639 310 } else if (type == INTEL_OUTPUT_ANALOG) {
a1e6ad66
ID		 311 *dig_port = NULL;
312 *port = PORT_E;
fc914639
PZ		 313 } else {
314 DRM_ERROR("Invalid DDI encoder type %d\n", type);
315 BUG();
316 }
317}
318
a1e6ad66
ID		 319enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
320{
321 struct intel_digital_port *dig_port;
322 enum port port;
323
324 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
325
326 return port;
327}
328
ce3b7e9b
DL		 329static bool
330intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
331{
332 return intel_dig_port->hdmi.hdmi_reg;
333}
334
f8896f5d
DW		 335static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev,
336 int *n_entries)
337{
338 struct drm_i915_private *dev_priv = dev->dev_private;
339 const struct ddi_buf_trans *ddi_translations;
340 static int is_095v = -1;
341
342 if (is_095v == -1) {
343 u32 spr1 = I915_READ(UAIMI_SPR1);
344
345 is_095v = spr1 & SKL_VCCIO_MASK;
346 }
347
348 if (IS_SKL_ULX(dev) && !is_095v) {
349 ddi_translations = skl_y_085v_ddi_translations_dp;
350 *n_entries = ARRAY_SIZE(skl_y_085v_ddi_translations_dp);
351 } else if (IS_SKL_ULT(dev)) {
352 ddi_translations = skl_u_ddi_translations_dp;
353 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
354 } else {
355 ddi_translations = skl_ddi_translations_dp;
356 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
357 }
358
359 return ddi_translations;
360}
361
362static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev,
363 int *n_entries)
364{
365 struct drm_i915_private *dev_priv = dev->dev_private;
366 const struct ddi_buf_trans *ddi_translations;
367 static int is_095v = -1;
368
369 if (is_095v == -1) {
370 u32 spr1 = I915_READ(UAIMI_SPR1);
371
372 is_095v = spr1 & SKL_VCCIO_MASK;
373 }
374
375 if (IS_SKL_ULX(dev) && !is_095v) {
376 if (dev_priv->edp_low_vswing) {
377 ddi_translations = skl_y_085v_ddi_translations_edp;
378 *n_entries =
379 ARRAY_SIZE(skl_y_085v_ddi_translations_edp);
380 } else {
381 ddi_translations = skl_y_085v_ddi_translations_dp;
382 *n_entries =
383 ARRAY_SIZE(skl_y_085v_ddi_translations_dp);
384 }
385 } else if (IS_SKL_ULT(dev)) {
386 if (dev_priv->edp_low_vswing) {
387 ddi_translations = skl_u_ddi_translations_edp;
388 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
389 } else {
390 ddi_translations = skl_u_ddi_translations_dp;
391 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
392 }
393 } else {
394 if (dev_priv->edp_low_vswing) {
395 ddi_translations = skl_ddi_translations_edp;
396 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
397 } else {
398 ddi_translations = skl_ddi_translations_dp;
399 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
400 }
401 }
402
403 return ddi_translations;
404}
405
406static const struct ddi_buf_trans *
407skl_get_buf_trans_hdmi(struct drm_device *dev,
408 int *n_entries)
409{
410 struct drm_i915_private *dev_priv = dev->dev_private;
411 const struct ddi_buf_trans *ddi_translations;
412 static int is_095v = -1;
413
414 if (is_095v == -1) {
415 u32 spr1 = I915_READ(UAIMI_SPR1);
416
417 is_095v = spr1 & SKL_VCCIO_MASK;
418 }
419
420 if (IS_SKL_ULX(dev) && !is_095v) {
421 ddi_translations = skl_y_085v_ddi_translations_hdmi;
422 *n_entries = ARRAY_SIZE(skl_y_085v_ddi_translations_hdmi);
423 } else {
424 ddi_translations = skl_ddi_translations_hdmi;
425 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
426 }
427
428 return ddi_translations;
429}
430
e58623cb
AR		 431/*
432 * Starting with Haswell, DDI port buffers must be programmed with correct
433 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 434 * but the HDMI/DVI fields are shared among those. So we program the DDI
435 * in either FDI or DP modes only, as HDMI connections will work with both
436 * of those
437 */
faa0cdbe
ID		 438static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
439 bool supports_hdmi)
45244b87
ED		 440{
441 struct drm_i915_private *dev_priv = dev->dev_private;
442 u32 reg;
7ff44670 443 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 444 size;
6acab15a 445 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 446 const struct ddi_buf_trans *ddi_translations_fdi;
447 const struct ddi_buf_trans *ddi_translations_dp;
448 const struct ddi_buf_trans *ddi_translations_edp;
449 const struct ddi_buf_trans *ddi_translations_hdmi;
450 const struct ddi_buf_trans *ddi_translations;
e58623cb 451
96fb9f9b 452 if (IS_BROXTON(dev)) {
faa0cdbe 453 if (!supports_hdmi)
96fb9f9b
VK		 454 return;
455
456 /* Vswing programming for HDMI */
457 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
458 INTEL_OUTPUT_HDMI);
459 return;
460 } else if (IS_SKYLAKE(dev)) {
f8896f5d
DW		 461 ddi_translations_dp =
462 skl_get_buf_trans_dp(dev, &n_dp_entries);
463 ddi_translations_edp =
464 skl_get_buf_trans_edp(dev, &n_edp_entries);
465 ddi_translations_hdmi =
466 skl_get_buf_trans_hdmi(dev, &n_hdmi_entries);
467 hdmi_default_entry = 8;
7f88e3af 468 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 469 ddi_translations_fdi = bdw_ddi_translations_fdi;
470 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 471 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 472 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 473 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
474 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 475 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 476 hdmi_default_entry = 7;
e58623cb
AR		 477 } else if (IS_HASWELL(dev)) {
478 ddi_translations_fdi = hsw_ddi_translations_fdi;
479 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 480 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 481 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 482 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 483 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 484 hdmi_default_entry = 6;
e58623cb
AR		 485 } else {
486 WARN(1, "ddi translation table missing\n");
300644c7 487 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 488 ddi_translations_fdi = bdw_ddi_translations_fdi;
489 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 490 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 491 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
492 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 493 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 494 hdmi_default_entry = 7;
e58623cb
AR		 495 }
496
300644c7
PZ		 497 switch (port) {
498 case PORT_A:
499 ddi_translations = ddi_translations_edp;
7ad14a29 500 size = n_edp_entries;
300644c7
PZ		 501 break;
502 case PORT_B:
503 case PORT_C:
300644c7 504 ddi_translations = ddi_translations_dp;
7ad14a29 505 size = n_dp_entries;
300644c7 506 break;
77d8d009 507 case PORT_D:
7ad14a29 508 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 509 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 510 size = n_edp_entries;
511 } else {
77d8d009 512 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 513 size = n_dp_entries;
514 }
77d8d009 515 break;
300644c7 516 case PORT_E:
7f88e3af
DL		 517 if (ddi_translations_fdi)
518 ddi_translations = ddi_translations_fdi;
519 else
520 ddi_translations = ddi_translations_dp;
7ad14a29 521 size = n_dp_entries;
300644c7
PZ		 522 break;
523 default:
524 BUG();
525 }
45244b87 526
7ad14a29 527 for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
10122051
JN		 528 I915_WRITE(reg, ddi_translations[i].trans1);
529 reg += 4;
530 I915_WRITE(reg, ddi_translations[i].trans2);
45244b87
ED		 531 reg += 4;
532 }
ce4dd49e 533
faa0cdbe 534 if (!supports_hdmi)
ce3b7e9b
DL		 535 return;
536
ce4dd49e
DL		 537 /* Choose a good default if VBT is badly populated */
538 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
539 hdmi_level >= n_hdmi_entries)
7ff44670 540 hdmi_level = hdmi_default_entry;
ce4dd49e 541
6acab15a 542 /* Entry 9 is for HDMI: */
10122051
JN		 543 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
544 reg += 4;
545 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
546 reg += 4;
45244b87
ED		 547}
548
549/* Program DDI buffers translations for DP. By default, program ports A-D in DP
550 * mode and port E for FDI.
551 */
552void intel_prepare_ddi(struct drm_device *dev)
553{
faa0cdbe 554 struct intel_encoder *intel_encoder;
b403745c 555 bool visited[I915_MAX_PORTS] = { 0, };
45244b87 556
0d536cb4
PZ		 557 if (!HAS_DDI(dev))
558 return;
45244b87 559
faa0cdbe
ID		 560 for_each_intel_encoder(dev, intel_encoder) {
561 struct intel_digital_port *intel_dig_port;
562 enum port port;
563 bool supports_hdmi;
564
565 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
566
567 if (visited[port])
b403745c
DL		 568 continue;
569
faa0cdbe
ID		 570 supports_hdmi = intel_dig_port &&
571 intel_dig_port_supports_hdmi(intel_dig_port);
572
573 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
574 visited[port] = true;
b403745c 575 }
45244b87 576}
c82e4d26 577
248138b5
PZ		 578static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
579 enum port port)
580{
581 uint32_t reg = DDI_BUF_CTL(port);
582 int i;
583
3449ca85 584 for (i = 0; i < 16; i++) {
248138b5
PZ		 585 udelay(1);
586 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
587 return;
588 }
589 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
590}
c82e4d26
ED		 591
592/* Starting with Haswell, different DDI ports can work in FDI mode for
593 * connection to the PCH-located connectors. For this, it is necessary to train
594 * both the DDI port and PCH receiver for the desired DDI buffer settings.
595 *
596 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
597 * please note that when FDI mode is active on DDI E, it shares 2 lines with
598 * DDI A (which is used for eDP)
599 */
600
601void hsw_fdi_link_train(struct drm_crtc *crtc)
602{
603 struct drm_device *dev = crtc->dev;
604 struct drm_i915_private *dev_priv = dev->dev_private;
605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 606 u32 temp, i, rx_ctl_val;
c82e4d26 607
04945641
PZ		 608 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
609 * mode set "sequence for CRT port" document:
610 * - TP1 to TP2 time with the default value
611 * - FDI delay to 90h
8693a824
DL		 612 *
613 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 614 */
615 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
616 FDI_RX_PWRDN_LANE0_VAL(2) |
617 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
618
619 /* Enable the PCH Receiver FDI PLL */
3e68320e 620 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 621 FDI_RX_PLL_ENABLE |
6e3c9717 622 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
04945641
PZ		 623 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
624 POSTING_READ(_FDI_RXA_CTL);
625 udelay(220);
626
627 /* Switch from Rawclk to PCDclk */
628 rx_ctl_val |= FDI_PCDCLK;
629 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
630
631 /* Configure Port Clock Select */
6e3c9717
ACO		 632 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
633 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 634
635 /* Start the training iterating through available voltages and emphasis,
636 * testing each value twice. */
10122051 637 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 638 /* Configure DP_TP_CTL with auto-training */
639 I915_WRITE(DP_TP_CTL(PORT_E),
640 DP_TP_CTL_FDI_AUTOTRAIN |
641 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
642 DP_TP_CTL_LINK_TRAIN_PAT1 |
643 DP_TP_CTL_ENABLE);
644
876a8cdf
DL		 645 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
646 * DDI E does not support port reversal, the functionality is
647 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
648 * port reversal bit */
c82e4d26 649 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 650 DDI_BUF_CTL_ENABLE |
6e3c9717 651 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 652 DDI_BUF_TRANS_SELECT(i / 2));
04945641 653 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 654
655 udelay(600);
656
04945641
PZ		 657 /* Program PCH FDI Receiver TU */
658 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
659
660 /* Enable PCH FDI Receiver with auto-training */
661 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
662 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
663 POSTING_READ(_FDI_RXA_CTL);
664
665 /* Wait for FDI receiver lane calibration */
666 udelay(30);
667
668 /* Unset FDI_RX_MISC pwrdn lanes */
669 temp = I915_READ(_FDI_RXA_MISC);
670 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
671 I915_WRITE(_FDI_RXA_MISC, temp);
672 POSTING_READ(_FDI_RXA_MISC);
673
674 /* Wait for FDI auto training time */
675 udelay(5);
c82e4d26
ED		 676
677 temp = I915_READ(DP_TP_STATUS(PORT_E));
678 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 679 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 680
681 /* Enable normal pixel sending for FDI */
682 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 683 DP_TP_CTL_FDI_AUTOTRAIN |
684 DP_TP_CTL_LINK_TRAIN_NORMAL |
685 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
686 DP_TP_CTL_ENABLE);
c82e4d26 687
04945641 688 return;
c82e4d26 689 }
04945641 690
248138b5
PZ		 691 temp = I915_READ(DDI_BUF_CTL(PORT_E));
692 temp &= ~DDI_BUF_CTL_ENABLE;
693 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
694 POSTING_READ(DDI_BUF_CTL(PORT_E));
695
04945641 696 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 697 temp = I915_READ(DP_TP_CTL(PORT_E));
698 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
699 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
700 I915_WRITE(DP_TP_CTL(PORT_E), temp);
701 POSTING_READ(DP_TP_CTL(PORT_E));
702
703 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 704
705 rx_ctl_val &= ~FDI_RX_ENABLE;
706 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 707 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 708
709 /* Reset FDI_RX_MISC pwrdn lanes */
710 temp = I915_READ(_FDI_RXA_MISC);
711 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
712 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
713 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 714 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 715 }
716
04945641 717 DRM_ERROR("FDI link training failed!\n");
c82e4d26 718}
0e72a5b5 719
44905a27
DA		 720void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
721{
722 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
723 struct intel_digital_port *intel_dig_port =
724 enc_to_dig_port(&encoder->base);
725
726 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 727 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
44905a27
DA		 728 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
729
730}
731
8d9ddbcb
PZ		 732static struct intel_encoder *
733intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
734{
735 struct drm_device *dev = crtc->dev;
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737 struct intel_encoder *intel_encoder, *ret = NULL;
738 int num_encoders = 0;
739
740 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
741 ret = intel_encoder;
742 num_encoders++;
743 }
744
745 if (num_encoders != 1)
84f44ce7
VS		 746 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
747 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 748
749 BUG_ON(ret == NULL);
750 return ret;
751}
752
bcddf610 753struct intel_encoder *
3165c074 754intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 755{
3165c074
ACO		 756 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
757 struct intel_encoder *ret = NULL;
758 struct drm_atomic_state *state;
da3ced29
ACO		 759 struct drm_connector *connector;
760 struct drm_connector_state *connector_state;
d0737e1d 761 int num_encoders = 0;
3165c074 762 int i;
d0737e1d 763
3165c074
ACO		 764 state = crtc_state->base.state;
765
da3ced29
ACO		 766 for_each_connector_in_state(state, connector, connector_state, i) {
767 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 768 continue;
769
da3ced29 770 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 771 num_encoders++;
d0737e1d
ACO		 772 }
773
774 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
775 pipe_name(crtc->pipe));
776
777 BUG_ON(ret == NULL);
778 return ret;
779}
780
1c0b85c5 781#define LC_FREQ 2700
27893390 782#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 783
784#define P_MIN 2
785#define P_MAX 64
786#define P_INC 2
787
788/* Constraints for PLL good behavior */
789#define REF_MIN 48
790#define REF_MAX 400
791#define VCO_MIN 2400
792#define VCO_MAX 4800
793
27893390
DL		 794#define abs_diff(a, b) ({ \
795 typeof(a) __a = (a); \
796 typeof(b) __b = (b); \
797 (void) (&__a == &__b); \
798 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5 799
63582983 800struct hsw_wrpll_rnp {
1c0b85c5
DL		 801 unsigned p, n2, r2;
802};
803
63582983 804static unsigned hsw_wrpll_get_budget_for_freq(int clock)
6441ab5f 805{
1c0b85c5
DL		 806 unsigned budget;
807
808 switch (clock) {
809 case 25175000:
810 case 25200000:
811 case 27000000:
812 case 27027000:
813 case 37762500:
814 case 37800000:
815 case 40500000:
816 case 40541000:
817 case 54000000:
818 case 54054000:
819 case 59341000:
820 case 59400000:
821 case 72000000:
822 case 74176000:
823 case 74250000:
824 case 81000000:
825 case 81081000:
826 case 89012000:
827 case 89100000:
828 case 108000000:
829 case 108108000:
830 case 111264000:
831 case 111375000:
832 case 148352000:
833 case 148500000:
834 case 162000000:
835 case 162162000:
836 case 222525000:
837 case 222750000:
838 case 296703000:
839 case 297000000:
840 budget = 0;
841 break;
842 case 233500000:
843 case 245250000:
844 case 247750000:
845 case 253250000:
846 case 298000000:
847 budget = 1500;
848 break;
849 case 169128000:
850 case 169500000:
851 case 179500000:
852 case 202000000:
853 budget = 2000;
854 break;
855 case 256250000:
856 case 262500000:
857 case 270000000:
858 case 272500000:
859 case 273750000:
860 case 280750000:
861 case 281250000:
862 case 286000000:
863 case 291750000:
864 budget = 4000;
865 break;
866 case 267250000:
867 case 268500000:
868 budget = 5000;
869 break;
870 default:
871 budget = 1000;
872 break;
873 }
6441ab5f 874
1c0b85c5
DL		 875 return budget;
876}
877
63582983
DL		 878static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
879 unsigned r2, unsigned n2, unsigned p,
880 struct hsw_wrpll_rnp *best)
1c0b85c5
DL		 881{
882 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 883
1c0b85c5
DL		 884 /* No best (r,n,p) yet */
885 if (best->p == 0) {
886 best->p = p;
887 best->n2 = n2;
888 best->r2 = r2;
889 return;
890 }
6441ab5f 891
1c0b85c5
DL		 892 /*
893 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
894 * freq2k.
895 *
896 * delta = 1e6 *
897 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
898 * freq2k;
899 *
900 * and we would like delta <= budget.
901 *
902 * If the discrepancy is above the PPM-based budget, always prefer to
903 * improve upon the previous solution. However, if you're within the
904 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
905 */
906 a = freq2k * budget * p * r2;
907 b = freq2k * budget * best->p * best->r2;
27893390
DL		 908 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
909 diff_best = abs_diff(freq2k * best->p * best->r2,
910 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 911 c = 1000000 * diff;
912 d = 1000000 * diff_best;
913
914 if (a < c && b < d) {
915 /* If both are above the budget, pick the closer */
916 if (best->p * best->r2 * diff < p * r2 * diff_best) {
917 best->p = p;
918 best->n2 = n2;
919 best->r2 = r2;
920 }
921 } else if (a >= c && b < d) {
922 /* If A is below the threshold but B is above it? Update. */
923 best->p = p;
924 best->n2 = n2;
925 best->r2 = r2;
926 } else if (a >= c && b >= d) {
927 /* Both are below the limit, so pick the higher n2/(r2*r2) */
928 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
929 best->p = p;
930 best->n2 = n2;
931 best->r2 = r2;
932 }
933 }
934 /* Otherwise a < c && b >= d, do nothing */
935}
936
63582983 937static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
11578553
JB		 938{
939 int refclk = LC_FREQ;
940 int n, p, r;
941 u32 wrpll;
942
943 wrpll = I915_READ(reg);
114fe488
DV		 944 switch (wrpll & WRPLL_PLL_REF_MASK) {
945 case WRPLL_PLL_SSC:
946 case WRPLL_PLL_NON_SSC:
11578553
JB		 947 /*
948 * We could calculate spread here, but our checking
949 * code only cares about 5% accuracy, and spread is a max of
950 * 0.5% downspread.
951 */
952 refclk = 135;
953 break;
114fe488 954 case WRPLL_PLL_LCPLL:
11578553
JB		 955 refclk = LC_FREQ;
956 break;
957 default:
958 WARN(1, "bad wrpll refclk\n");
959 return 0;
960 }
961
962 r = wrpll & WRPLL_DIVIDER_REF_MASK;
963 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
964 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
965
20f0ec16
JB		 966 /* Convert to KHz, p & r have a fixed point portion */
967 return (refclk * n * 100) / (p * r);
11578553
JB		 968}
969
540e732c
S		 970static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
971 uint32_t dpll)
972{
973 uint32_t cfgcr1_reg, cfgcr2_reg;
974 uint32_t cfgcr1_val, cfgcr2_val;
975 uint32_t p0, p1, p2, dco_freq;
976
977 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
978 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
979
980 cfgcr1_val = I915_READ(cfgcr1_reg);
981 cfgcr2_val = I915_READ(cfgcr2_reg);
982
983 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
984 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
985
986 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
987 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
988 else
989 p1 = 1;
990
991
992 switch (p0) {
993 case DPLL_CFGCR2_PDIV_1:
994 p0 = 1;
995 break;
996 case DPLL_CFGCR2_PDIV_2:
997 p0 = 2;
998 break;
999 case DPLL_CFGCR2_PDIV_3:
1000 p0 = 3;
1001 break;
1002 case DPLL_CFGCR2_PDIV_7:
1003 p0 = 7;
1004 break;
1005 }
1006
1007 switch (p2) {
1008 case DPLL_CFGCR2_KDIV_5:
1009 p2 = 5;
1010 break;
1011 case DPLL_CFGCR2_KDIV_2:
1012 p2 = 2;
1013 break;
1014 case DPLL_CFGCR2_KDIV_3:
1015 p2 = 3;
1016 break;
1017 case DPLL_CFGCR2_KDIV_1:
1018 p2 = 1;
1019 break;
1020 }
1021
1022 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1023
1024 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1025 1000) / 0x8000;
1026
1027 return dco_freq / (p0 * p1 * p2 * 5);
1028}
1029
1030
1031static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1032 struct intel_crtc_state *pipe_config)
540e732c
S		 1033{
1034 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 1035 int link_clock = 0;
1036 uint32_t dpll_ctl1, dpll;
1037
134ffa44 1038 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 1039
1040 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1041
1042 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1043 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1044 } else {
71cd8423
DL		 1045 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1046 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1047
1048 switch (link_clock) {
71cd8423 1049 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1050 link_clock = 81000;
1051 break;
71cd8423 1052 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1053 link_clock = 108000;
1054 break;
71cd8423 1055 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1056 link_clock = 135000;
1057 break;
71cd8423 1058 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1059 link_clock = 162000;
1060 break;
71cd8423 1061 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1062 link_clock = 216000;
1063 break;
71cd8423 1064 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1065 link_clock = 270000;
1066 break;
1067 default:
1068 WARN(1, "Unsupported link rate\n");
1069 break;
1070 }
1071 link_clock *= 2;
1072 }
1073
1074 pipe_config->port_clock = link_clock;
1075
1076 if (pipe_config->has_dp_encoder)
2d112de7 1077 pipe_config->base.adjusted_mode.crtc_clock =
540e732c
S		 1078 intel_dotclock_calculate(pipe_config->port_clock,
1079 &pipe_config->dp_m_n);
1080 else
2d112de7 1081 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
540e732c
S		 1082}
1083
3d51278a 1084static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1085 struct intel_crtc_state *pipe_config)
11578553
JB		 1086{
1087 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 1088 int link_clock = 0;
1089 u32 val, pll;
1090
26804afd 1091 val = pipe_config->ddi_pll_sel;
11578553
JB		 1092 switch (val & PORT_CLK_SEL_MASK) {
1093 case PORT_CLK_SEL_LCPLL_810:
1094 link_clock = 81000;
1095 break;
1096 case PORT_CLK_SEL_LCPLL_1350:
1097 link_clock = 135000;
1098 break;
1099 case PORT_CLK_SEL_LCPLL_2700:
1100 link_clock = 270000;
1101 break;
1102 case PORT_CLK_SEL_WRPLL1:
63582983 1103 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
11578553
JB		 1104 break;
1105 case PORT_CLK_SEL_WRPLL2:
63582983 1106 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
11578553
JB		 1107 break;
1108 case PORT_CLK_SEL_SPLL:
1109 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1110 if (pll == SPLL_PLL_FREQ_810MHz)
1111 link_clock = 81000;
1112 else if (pll == SPLL_PLL_FREQ_1350MHz)
1113 link_clock = 135000;
1114 else if (pll == SPLL_PLL_FREQ_2700MHz)
1115 link_clock = 270000;
1116 else {
1117 WARN(1, "bad spll freq\n");
1118 return;
1119 }
1120 break;
1121 default:
1122 WARN(1, "bad port clock sel\n");
1123 return;
1124 }
1125
1126 pipe_config->port_clock = link_clock * 2;
1127
1128 if (pipe_config->has_pch_encoder)
2d112de7 1129 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 1130 intel_dotclock_calculate(pipe_config->port_clock,
1131 &pipe_config->fdi_m_n);
1132 else if (pipe_config->has_dp_encoder)
2d112de7 1133 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 1134 intel_dotclock_calculate(pipe_config->port_clock,
1135 &pipe_config->dp_m_n);
1136 else
2d112de7 1137 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
11578553
JB		 1138}
1139
977bb38d
S		 1140static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1141 enum intel_dpll_id dpll)
1142{
aa610dcb
ID		 1143 struct intel_shared_dpll *pll;
1144 struct intel_dpll_hw_state *state;
1145 intel_clock_t clock;
1146
1147 /* For DDI ports we always use a shared PLL. */
1148 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1149 return 0;
1150
1151 pll = &dev_priv->shared_dplls[dpll];
1152 state = &pll->config.hw_state;
1153
1154 clock.m1 = 2;
1155 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1156 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1157 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1158 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1159 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1160 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1161
1162 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1163}
1164
1165static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1166 struct intel_crtc_state *pipe_config)
1167{
1168 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1169 enum port port = intel_ddi_get_encoder_port(encoder);
1170 uint32_t dpll = port;
1171
1172 pipe_config->port_clock =
1173 bxt_calc_pll_link(dev_priv, dpll);
1174
1175 if (pipe_config->has_dp_encoder)
1176 pipe_config->base.adjusted_mode.crtc_clock =
1177 intel_dotclock_calculate(pipe_config->port_clock,
1178 &pipe_config->dp_m_n);
1179 else
1180 pipe_config->base.adjusted_mode.crtc_clock =
1181 pipe_config->port_clock;
1182}
1183
3d51278a 1184void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1185 struct intel_crtc_state *pipe_config)
3d51278a 1186{
22606a18
DL		 1187 struct drm_device *dev = encoder->base.dev;
1188
1189 if (INTEL_INFO(dev)->gen <= 8)
1190 hsw_ddi_clock_get(encoder, pipe_config);
977bb38d 1191 else if (IS_SKYLAKE(dev))
22606a18 1192 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1193 else if (IS_BROXTON(dev))
1194 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1195}
1196
1c0b85c5 1197static void
d664c0ce
DL		 1198hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1199 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1200{
1201 uint64_t freq2k;
1202 unsigned p, n2, r2;
63582983 1203 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1c0b85c5
DL		 1204 unsigned budget;
1205
1206 freq2k = clock / 100;
1207
63582983 1208 budget = hsw_wrpll_get_budget_for_freq(clock);
1c0b85c5
DL		 1209
1210 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1211 * and directly pass the LC PLL to it. */
1212 if (freq2k == 5400000) {
1213 *n2_out = 2;
1214 *p_out = 1;
1215 *r2_out = 2;
1216 return;
1217 }
1218
1219 /*
1220 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1221 * the WR PLL.
1222 *
1223 * We want R so that REF_MIN <= Ref <= REF_MAX.
1224 * Injecting R2 = 2 * R gives:
1225 * REF_MAX * r2 > LC_FREQ * 2 and
1226 * REF_MIN * r2 < LC_FREQ * 2
1227 *
1228 * Which means the desired boundaries for r2 are:
1229 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1230 *
1231 */
1232 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1233 r2 <= LC_FREQ * 2 / REF_MIN;
1234 r2++) {
1235
1236 /*
1237 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1238 *
1239 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1240 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1241 * VCO_MAX * r2 > n2 * LC_FREQ and
1242 * VCO_MIN * r2 < n2 * LC_FREQ)
1243 *
1244 * Which means the desired boundaries for n2 are:
1245 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1246 */
1247 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1248 n2 <= VCO_MAX * r2 / LC_FREQ;
1249 n2++) {
1250
1251 for (p = P_MIN; p <= P_MAX; p += P_INC)
63582983
DL		 1252 hsw_wrpll_update_rnp(freq2k, budget,
1253 r2, n2, p, &best);
1c0b85c5
DL		 1254 }
1255 }
6441ab5f 1256
1c0b85c5
DL		 1257 *n2_out = best.n2;
1258 *p_out = best.p;
1259 *r2_out = best.r2;
6441ab5f
PZ		 1260}
1261
0220ab6e 1262static bool
d664c0ce 1263hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1264 struct intel_crtc_state *crtc_state,
d664c0ce
DL		 1265 struct intel_encoder *intel_encoder,
1266 int clock)
6441ab5f 1267{
d664c0ce 1268 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1269 struct intel_shared_dpll *pll;
716c2e55 1270 uint32_t val;
1c0b85c5 1271 unsigned p, n2, r2;
6441ab5f 1272
d664c0ce 1273 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1274
114fe488 1275 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1276 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1277 WRPLL_DIVIDER_POST(p);
1278
dd3cd74a
ACO		 1279 memset(&crtc_state->dpll_hw_state, 0,
1280 sizeof(crtc_state->dpll_hw_state));
1281
190f68c5 1282 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1283
190f68c5 1284 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1285 if (pll == NULL) {
1286 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1287 pipe_name(intel_crtc->pipe));
1288 return false;
0694001b 1289 }
d452c5b6 1290
190f68c5 1291 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 1292 }
1293
6441ab5f
PZ		 1294 return true;
1295}
1296
dc253813
DL		 1297struct skl_wrpll_context {
1298 uint64_t min_deviation; /* current minimal deviation */
1299 uint64_t central_freq; /* chosen central freq */
1300 uint64_t dco_freq; /* chosen dco freq */
1301 unsigned int p; /* chosen divider */
1302};
1303
1304static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1305{
1306 memset(ctx, 0, sizeof(*ctx));
1307
1308 ctx->min_deviation = U64_MAX;
1309}
1310
1311/* DCO freq must be within +1%/-6% of the DCO central freq */
1312#define SKL_DCO_MAX_PDEVIATION 100
1313#define SKL_DCO_MAX_NDEVIATION 600
1314
1315static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1316 uint64_t central_freq,
1317 uint64_t dco_freq,
1318 unsigned int divider)
1319{
1320 uint64_t deviation;
1321
1322 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1323 central_freq);
1324
1325 /* positive deviation */
1326 if (dco_freq >= central_freq) {
1327 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1328 deviation < ctx->min_deviation) {
1329 ctx->min_deviation = deviation;
1330 ctx->central_freq = central_freq;
1331 ctx->dco_freq = dco_freq;
1332 ctx->p = divider;
1333 }
1334 /* negative deviation */
1335 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1336 deviation < ctx->min_deviation) {
1337 ctx->min_deviation = deviation;
1338 ctx->central_freq = central_freq;
1339 ctx->dco_freq = dco_freq;
1340 ctx->p = divider;
1341 }
dc253813
DL		 1342}
1343
1344static void skl_wrpll_get_multipliers(unsigned int p,
1345 unsigned int *p0 /* out */,
1346 unsigned int *p1 /* out */,
1347 unsigned int *p2 /* out */)
1348{
1349 /* even dividers */
1350 if (p % 2 == 0) {
1351 unsigned int half = p / 2;
1352
1353 if (half == 1 || half == 2 || half == 3 || half == 5) {
1354 *p0 = 2;
1355 *p1 = 1;
1356 *p2 = half;
1357 } else if (half % 2 == 0) {
1358 *p0 = 2;
1359 *p1 = half / 2;
1360 *p2 = 2;
1361 } else if (half % 3 == 0) {
1362 *p0 = 3;
1363 *p1 = half / 3;
1364 *p2 = 2;
1365 } else if (half % 7 == 0) {
1366 *p0 = 7;
1367 *p1 = half / 7;
1368 *p2 = 2;
1369 }
1370 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1371 *p0 = 3;
1372 *p1 = 1;
1373 *p2 = p / 3;
1374 } else if (p == 5 || p == 7) {
1375 *p0 = p;
1376 *p1 = 1;
1377 *p2 = 1;
1378 } else if (p == 15) {
1379 *p0 = 3;
1380 *p1 = 1;
1381 *p2 = 5;
1382 } else if (p == 21) {
1383 *p0 = 7;
1384 *p1 = 1;
1385 *p2 = 3;
1386 } else if (p == 35) {
1387 *p0 = 7;
1388 *p1 = 1;
1389 *p2 = 5;
1390 }
1391}
1392
82d35437
S		 1393struct skl_wrpll_params {
1394 uint32_t dco_fraction;
1395 uint32_t dco_integer;
1396 uint32_t qdiv_ratio;
1397 uint32_t qdiv_mode;
1398 uint32_t kdiv;
1399 uint32_t pdiv;
1400 uint32_t central_freq;
1401};
1402
76516fbc
DL		 1403static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1404 uint64_t afe_clock,
1405 uint64_t central_freq,
1406 uint32_t p0, uint32_t p1, uint32_t p2)
1407{
1408 uint64_t dco_freq;
1409
76516fbc
DL		 1410 switch (central_freq) {
1411 case 9600000000ULL:
1412 params->central_freq = 0;
1413 break;
1414 case 9000000000ULL:
1415 params->central_freq = 1;
1416 break;
1417 case 8400000000ULL:
1418 params->central_freq = 3;
1419 }
1420
1421 switch (p0) {
1422 case 1:
1423 params->pdiv = 0;
1424 break;
1425 case 2:
1426 params->pdiv = 1;
1427 break;
1428 case 3:
1429 params->pdiv = 2;
1430 break;
1431 case 7:
1432 params->pdiv = 4;
1433 break;
1434 default:
1435 WARN(1, "Incorrect PDiv\n");
1436 }
1437
1438 switch (p2) {
1439 case 5:
1440 params->kdiv = 0;
1441 break;
1442 case 2:
1443 params->kdiv = 1;
1444 break;
1445 case 3:
1446 params->kdiv = 2;
1447 break;
1448 case 1:
1449 params->kdiv = 3;
1450 break;
1451 default:
1452 WARN(1, "Incorrect KDiv\n");
1453 }
1454
1455 params->qdiv_ratio = p1;
1456 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1457
1458 dco_freq = p0 * p1 * p2 * afe_clock;
1459
1460 /*
1461 * Intermediate values are in Hz.
1462 * Divide by MHz to match bsepc
1463 */
30a7862d 1464 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
76516fbc 1465 params->dco_fraction =
30a7862d
DL		 1466 div_u64((div_u64(dco_freq, 24) -
1467 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
76516fbc
DL		 1468}
1469
318bd821 1470static bool
82d35437
S		 1471skl_ddi_calculate_wrpll(int clock /* in Hz */,
1472 struct skl_wrpll_params *wrpll_params)
1473{
1474 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1475 uint64_t dco_central_freq[3] = {8400000000ULL,
1476 9000000000ULL,
1477 9600000000ULL};
dc253813
DL		 1478 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1479 24, 28, 30, 32, 36, 40, 42, 44,
1480 48, 52, 54, 56, 60, 64, 66, 68,
1481 70, 72, 76, 78, 80, 84, 88, 90,
1482 92, 96, 98 };
1483 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1484 static const struct {
1485 const int *list;
1486 int n_dividers;
1487 } dividers[] = {
1488 { even_dividers, ARRAY_SIZE(even_dividers) },
1489 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1490 };
1491 struct skl_wrpll_context ctx;
1492 unsigned int dco, d, i;
1493 unsigned int p0, p1, p2;
1494
1495 skl_wrpll_context_init(&ctx);
1496
1497 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1498 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1499 for (i = 0; i < dividers[d].n_dividers; i++) {
1500 unsigned int p = dividers[d].list[i];
1501 uint64_t dco_freq = p * afe_clock;
1502
1503 skl_wrpll_try_divider(&ctx,
1504 dco_central_freq[dco],
1505 dco_freq,
1506 p);
e7ad9878
DL		 1507 /*
1508 * Skip the remaining dividers if we're sure to
1509 * have found the definitive divider, we can't
1510 * improve a 0 deviation.
1511 */
1512 if (ctx.min_deviation == 0)
1513 goto skip_remaining_dividers;
82d35437
S		 1514 }
1515 }
267db663 1516
e7ad9878 1517skip_remaining_dividers:
267db663
DL		 1518 /*
1519 * If a solution is found with an even divider, prefer
1520 * this one.
1521 */
1522 if (d == 0 && ctx.p)
1523 break;
82d35437
S		 1524 }
1525
dc253813
DL		 1526 if (!ctx.p) {
1527 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
318bd821 1528 return false;
dc253813 1529 }
82d35437 1530
dc253813
DL		 1531 /*
1532 * gcc incorrectly analyses that these can be used without being
1533 * initialized. To be fair, it's hard to guess.
1534 */
1535 p0 = p1 = p2 = 0;
1536 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1537 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1538 p0, p1, p2);
318bd821
DL		 1539
1540 return true;
82d35437
S		 1541}
1542
82d35437
S		 1543static bool
1544skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1545 struct intel_crtc_state *crtc_state,
82d35437
S		 1546 struct intel_encoder *intel_encoder,
1547 int clock)
1548{
1549 struct intel_shared_dpll *pll;
1550 uint32_t ctrl1, cfgcr1, cfgcr2;
1551
1552 /*
1553 * See comment in intel_dpll_hw_state to understand why we always use 0
1554 * as the DPLL id in this function.
1555 */
1556
1557 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1558
1559 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1560 struct skl_wrpll_params wrpll_params = { 0, };
1561
1562 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1563
318bd821
DL		 1564 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1565 return false;
82d35437
S		 1566
1567 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1568 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1569 wrpll_params.dco_integer;
1570
1571 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1572 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1573 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1574 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1575 wrpll_params.central_freq;
1576 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1577 struct drm_encoder *encoder = &intel_encoder->base;
1578 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1579
1580 switch (intel_dp->link_bw) {
1581 case DP_LINK_BW_1_62:
71cd8423 1582 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
82d35437
S		 1583 break;
1584 case DP_LINK_BW_2_7:
71cd8423 1585 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
82d35437
S		 1586 break;
1587 case DP_LINK_BW_5_4:
71cd8423 1588 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
82d35437
S		 1589 break;
1590 }
1591
1592 cfgcr1 = cfgcr2 = 0;
1593 } else /* eDP */
1594 return true;
1595
dd3cd74a
ACO		 1596 memset(&crtc_state->dpll_hw_state, 0,
1597 sizeof(crtc_state->dpll_hw_state));
1598
190f68c5
ACO		 1599 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1600 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1601 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1602
190f68c5 1603 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1604 if (pll == NULL) {
1605 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1606 pipe_name(intel_crtc->pipe));
1607 return false;
1608 }
1609
1610 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1611 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1612
1613 return true;
1614}
0220ab6e 1615
d683f3bc
S		 1616/* bxt clock parameters */
1617struct bxt_clk_div {
64987fc5 1618 int clock;
d683f3bc
S		 1619 uint32_t p1;
1620 uint32_t p2;
1621 uint32_t m2_int;
1622 uint32_t m2_frac;
1623 bool m2_frac_en;
1624 uint32_t n;
d683f3bc
S		 1625};
1626
1627/* pre-calculated values for DP linkrates */
64987fc5
SJ		 1628static const struct bxt_clk_div bxt_dp_clk_val[] = {
1629 {162000, 4, 2, 32, 1677722, 1, 1},
1630 {270000, 4, 1, 27, 0, 0, 1},
1631 {540000, 2, 1, 27, 0, 0, 1},
1632 {216000, 3, 2, 32, 1677722, 1, 1},
1633 {243000, 4, 1, 24, 1258291, 1, 1},
1634 {324000, 4, 1, 32, 1677722, 1, 1},
1635 {432000, 3, 1, 32, 1677722, 1, 1}
d683f3bc
S		 1636};
1637
1638static bool
1639bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1640 struct intel_crtc_state *crtc_state,
1641 struct intel_encoder *intel_encoder,
1642 int clock)
1643{
1644 struct intel_shared_dpll *pll;
1645 struct bxt_clk_div clk_div = {0};
b6dc71f3
VK		 1646 int vco = 0;
1647 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
e0681e38 1648 uint32_t dcoampovr_en_h, dco_amp, lanestagger;
d683f3bc
S		 1649
1650 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1651 intel_clock_t best_clock;
1652
1653 /* Calculate HDMI div */
1654 /*
1655 * FIXME: tie the following calculation into
1656 * i9xx_crtc_compute_clock
1657 */
1658 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1659 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1660 clock, pipe_name(intel_crtc->pipe));
1661 return false;
1662 }
1663
1664 clk_div.p1 = best_clock.p1;
1665 clk_div.p2 = best_clock.p2;
1666 WARN_ON(best_clock.m1 != 2);
1667 clk_div.n = best_clock.n;
1668 clk_div.m2_int = best_clock.m2 >> 22;
1669 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1670 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1671
b6dc71f3 1672 vco = best_clock.vco;
d683f3bc
S		 1673 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1674 intel_encoder->type == INTEL_OUTPUT_EDP) {
64987fc5 1675 int i;
d683f3bc 1676
64987fc5
SJ		 1677 clk_div = bxt_dp_clk_val[0];
1678 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1679 if (bxt_dp_clk_val[i].clock == clock) {
1680 clk_div = bxt_dp_clk_val[i];
1681 break;
1682 }
d683f3bc 1683 }
b6dc71f3
VK		 1684 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1685 }
1686
1687 dco_amp = 15;
1688 dcoampovr_en_h = 0;
1689 if (vco >= 6200000 && vco <= 6480000) {
1690 prop_coef = 4;
1691 int_coef = 9;
1692 gain_ctl = 3;
1693 targ_cnt = 8;
1694 } else if ((vco > 5400000 && vco < 6200000) ||
1695 (vco >= 4800000 && vco < 5400000)) {
1696 prop_coef = 5;
1697 int_coef = 11;
1698 gain_ctl = 3;
1699 targ_cnt = 9;
1700 if (vco >= 4800000 && vco < 5400000)
1701 dcoampovr_en_h = 1;
1702 } else if (vco == 5400000) {
1703 prop_coef = 3;
1704 int_coef = 8;
1705 gain_ctl = 1;
1706 targ_cnt = 9;
1707 } else {
1708 DRM_ERROR("Invalid VCO\n");
1709 return false;
d683f3bc
S		 1710 }
1711
dd3cd74a
ACO		 1712 memset(&crtc_state->dpll_hw_state, 0,
1713 sizeof(crtc_state->dpll_hw_state));
1714
e0681e38
VK		 1715 if (clock > 270000)
1716 lanestagger = 0x18;
1717 else if (clock > 135000)
1718 lanestagger = 0x0d;
1719 else if (clock > 67000)
1720 lanestagger = 0x07;
1721 else if (clock > 33000)
1722 lanestagger = 0x04;
1723 else
1724 lanestagger = 0x02;
1725
d683f3bc
S		 1726 crtc_state->dpll_hw_state.ebb0 =
1727 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1728 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1729 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1730 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1731
1732 if (clk_div.m2_frac_en)
1733 crtc_state->dpll_hw_state.pll3 =
1734 PORT_PLL_M2_FRAC_ENABLE;
1735
1736 crtc_state->dpll_hw_state.pll6 =
b6dc71f3 1737 prop_coef | PORT_PLL_INT_COEFF(int_coef);
d683f3bc 1738 crtc_state->dpll_hw_state.pll6 |=
b6dc71f3
VK		 1739 PORT_PLL_GAIN_CTL(gain_ctl);
1740
1741 crtc_state->dpll_hw_state.pll8 = targ_cnt;
d683f3bc 1742
05712c15
ID		 1743 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1744
b6dc71f3
VK		 1745 if (dcoampovr_en_h)
1746 crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H;
1747
1748 crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp);
d683f3bc 1749
05712c15
ID		 1750 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1751
d683f3bc 1752 crtc_state->dpll_hw_state.pcsdw12 =
e0681e38 1753 LANESTAGGER_STRAP_OVRD | lanestagger;
d683f3bc
S		 1754
1755 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1756 if (pll == NULL) {
1757 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1758 pipe_name(intel_crtc->pipe));
1759 return false;
1760 }
1761
1762 /* shared DPLL id 0 is DPLL A */
1763 crtc_state->ddi_pll_sel = pll->id;
1764
1765 return true;
1766}
1767
0220ab6e
DL		 1768/*
1769 * Tries to find a *shared* PLL for the CRTC and store it in
1770 * intel_crtc->ddi_pll_sel.
1771 *
1772 * For private DPLLs, compute_config() should do the selection for us. This
1773 * function should be folded into compute_config() eventually.
1774 */
190f68c5
ACO		 1775bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1776 struct intel_crtc_state *crtc_state)
0220ab6e 1777{
82d35437 1778 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1779 struct intel_encoder *intel_encoder =
3165c074 1780 intel_ddi_get_crtc_new_encoder(crtc_state);
190f68c5 1781 int clock = crtc_state->port_clock;
0220ab6e 1782
82d35437 1783 if (IS_SKYLAKE(dev))
190f68c5
ACO		 1784 return skl_ddi_pll_select(intel_crtc, crtc_state,
1785 intel_encoder, clock);
d683f3bc
S		 1786 else if (IS_BROXTON(dev))
1787 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1788 intel_encoder, clock);
82d35437 1789 else
190f68c5
ACO		 1790 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1791 intel_encoder, clock);
0220ab6e
DL		 1792}
1793
dae84799
PZ		 1794void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1795{
1796 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1798 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1799 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1800 int type = intel_encoder->type;
1801 uint32_t temp;
1802
0e32b39c 1803 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1804 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1805 switch (intel_crtc->config->pipe_bpp) {
dae84799 1806 case 18:
c9809791 1807 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1808 break;
1809 case 24:
c9809791 1810 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1811 break;
1812 case 30:
c9809791 1813 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1814 break;
1815 case 36:
c9809791 1816 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1817 break;
1818 default:
4e53c2e0 1819 BUG();
dae84799 1820 }
c9809791 1821 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1822 }
1823}
1824
0e32b39c
DA		 1825void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1826{
1827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1828 struct drm_device *dev = crtc->dev;
1829 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1830 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1831 uint32_t temp;
1832 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1833 if (state == true)
1834 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1835 else
1836 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1837 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1838}
1839
8228c251 1840void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1841{
1842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1843 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1844 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1845 struct drm_device *dev = crtc->dev;
1846 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1847 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1848 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1849 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1850 int type = intel_encoder->type;
8d9ddbcb
PZ		 1851 uint32_t temp;
1852
ad80a810
PZ		 1853 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1854 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1855 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1856
6e3c9717 1857 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1858 case 18:
ad80a810 1859 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1860 break;
1861 case 24:
ad80a810 1862 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1863 break;
1864 case 30:
ad80a810 1865 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1866 break;
1867 case 36:
ad80a810 1868 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1869 break;
1870 default:
4e53c2e0 1871 BUG();
dfcef252 1872 }
72662e10 1873
6e3c9717 1874 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1875 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1876 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1877 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1878
e6f0bfc4
PZ		 1879 if (cpu_transcoder == TRANSCODER_EDP) {
1880 switch (pipe) {
1881 case PIPE_A:
c7670b10
PZ		 1882 /* On Haswell, can only use the always-on power well for
1883 * eDP when not using the panel fitter, and when not
1884 * using motion blur mitigation (which we don't
1885 * support). */
fabf6e51 1886 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1887 (intel_crtc->config->pch_pfit.enabled ||
1888 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1889 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1890 else
1891 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1892 break;
1893 case PIPE_B:
1894 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1895 break;
1896 case PIPE_C:
1897 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1898 break;
1899 default:
1900 BUG();
1901 break;
1902 }
1903 }
1904
7739c33b 1905 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1906 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1907 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1908 else
ad80a810 1909 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1910
7739c33b 1911 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1912 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1913 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1914
1915 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1916 type == INTEL_OUTPUT_EDP) {
1917 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1918
0e32b39c
DA		 1919 if (intel_dp->is_mst) {
1920 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1921 } else
1922 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1923
1924 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1925 } else if (type == INTEL_OUTPUT_DP_MST) {
1926 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1927
1928 if (intel_dp->is_mst) {
1929 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1930 } else
1931 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1932
17aa6be9 1933 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1934 } else {
84f44ce7
VS		 1935 WARN(1, "Invalid encoder type %d for pipe %c\n",
1936 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1937 }
1938
ad80a810 1939 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1940}
72662e10 1941
ad80a810
PZ		 1942void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1943 enum transcoder cpu_transcoder)
8d9ddbcb 1944{
ad80a810 1945 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1946 uint32_t val = I915_READ(reg);
1947
0e32b39c 1948 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1949 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1950 I915_WRITE(reg, val);
72662e10
ED		 1951}
1952
bcbc889b
PZ		 1953bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1954{
1955 struct drm_device *dev = intel_connector->base.dev;
1956 struct drm_i915_private *dev_priv = dev->dev_private;
1957 struct intel_encoder *intel_encoder = intel_connector->encoder;
1958 int type = intel_connector->base.connector_type;
1959 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1960 enum pipe pipe = 0;
1961 enum transcoder cpu_transcoder;
882244a3 1962 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1963 uint32_t tmp;
1964
882244a3 1965 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1966 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1967 return false;
1968
bcbc889b
PZ		 1969 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1970 return false;
1971
1972 if (port == PORT_A)
1973 cpu_transcoder = TRANSCODER_EDP;
1974 else
1a240d4d 1975 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1976
1977 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1978
1979 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1980 case TRANS_DDI_MODE_SELECT_HDMI:
1981 case TRANS_DDI_MODE_SELECT_DVI:
1982 return (type == DRM_MODE_CONNECTOR_HDMIA);
1983
1984 case TRANS_DDI_MODE_SELECT_DP_SST:
1985 if (type == DRM_MODE_CONNECTOR_eDP)
1986 return true;
bcbc889b 1987 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1988 case TRANS_DDI_MODE_SELECT_DP_MST:
1989 /* if the transcoder is in MST state then
1990 * connector isn't connected */
1991 return false;
bcbc889b
PZ		 1992
1993 case TRANS_DDI_MODE_SELECT_FDI:
1994 return (type == DRM_MODE_CONNECTOR_VGA);
1995
1996 default:
1997 return false;
1998 }
1999}
2000
85234cdc
DV		 2001bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2002 enum pipe *pipe)
2003{
2004 struct drm_device *dev = encoder->base.dev;
2005 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 2006 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 2007 enum intel_display_power_domain power_domain;
85234cdc
DV		 2008 u32 tmp;
2009 int i;
2010
6d129bea 2011 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 2012 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 2013 return false;
2014
fe43d3f5 2015 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 2016
2017 if (!(tmp & DDI_BUF_CTL_ENABLE))
2018 return false;
2019
ad80a810
PZ		 2020 if (port == PORT_A) {
2021 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 2022
ad80a810
PZ		 2023 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2024 case TRANS_DDI_EDP_INPUT_A_ON:
2025 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2026 *pipe = PIPE_A;
2027 break;
2028 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2029 *pipe = PIPE_B;
2030 break;
2031 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2032 *pipe = PIPE_C;
2033 break;
2034 }
2035
2036 return true;
2037 } else {
2038 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
2039 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
2040
2041 if ((tmp & TRANS_DDI_PORT_MASK)
2042 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 2043 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
2044 return false;
2045
ad80a810
PZ		 2046 *pipe = i;
2047 return true;
2048 }
85234cdc
DV		 2049 }
2050 }
2051
84f44ce7 2052 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 2053
22f9fe50 2054 return false;
85234cdc
DV		 2055}
2056
fc914639
PZ		 2057void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2058{
2059 struct drm_crtc *crtc = &intel_crtc->base;
2060 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2061 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2062 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 2063 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2064
bb523fc0
PZ		 2065 if (cpu_transcoder != TRANSCODER_EDP)
2066 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2067 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2068}
2069
2070void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2071{
2072 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 2073 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2074
bb523fc0
PZ		 2075 if (cpu_transcoder != TRANSCODER_EDP)
2076 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2077 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2078}
2079
f8896f5d
DW		 2080static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
2081 enum port port, int type)
2082{
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 const struct ddi_buf_trans *ddi_translations;
2085 uint8_t iboost;
2086 int n_entries;
2087 u32 reg;
2088
2089 if (type == INTEL_OUTPUT_DISPLAYPORT) {
2090 ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
2091 iboost = ddi_translations[port].i_boost;
2092 } else if (type == INTEL_OUTPUT_EDP) {
2093 ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
2094 iboost = ddi_translations[port].i_boost;
2095 } else if (type == INTEL_OUTPUT_HDMI) {
2096 ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
2097 iboost = ddi_translations[port].i_boost;
2098 } else {
2099 return;
2100 }
2101
2102 /* Make sure that the requested I_boost is valid */
2103 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2104 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2105 return;
2106 }
2107
2108 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2109 reg &= ~BALANCE_LEG_MASK(port);
2110 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2111
2112 if (iboost)
2113 reg |= iboost << BALANCE_LEG_SHIFT(port);
2114 else
2115 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2116
2117 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2118}
2119
2120static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
2121 enum port port, int type)
96fb9f9b
VK		 2122{
2123 struct drm_i915_private *dev_priv = dev->dev_private;
2124 const struct bxt_ddi_buf_trans *ddi_translations;
2125 u32 n_entries, i;
2126 uint32_t val;
2127
2128 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2129 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2130 ddi_translations = bxt_ddi_translations_dp;
2131 } else if (type == INTEL_OUTPUT_HDMI) {
2132 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2133 ddi_translations = bxt_ddi_translations_hdmi;
2134 } else {
2135 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2136 type);
2137 return;
2138 }
2139
2140 /* Check if default value has to be used */
2141 if (level >= n_entries ||
2142 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2143 for (i = 0; i < n_entries; i++) {
2144 if (ddi_translations[i].default_index) {
2145 level = i;
2146 break;
2147 }
2148 }
2149 }
2150
2151 /*
2152 * While we write to the group register to program all lanes at once we
2153 * can read only lane registers and we pick lanes 0/1 for that.
2154 */
2155 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2156 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2157 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2158
2159 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2160 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2161 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2162 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2163 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2164
2165 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
2166 val &= ~UNIQE_TRANGE_EN_METHOD;
2167 if (ddi_translations[level].enable)
2168 val |= UNIQE_TRANGE_EN_METHOD;
2169 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2170
2171 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2172 val &= ~DE_EMPHASIS;
2173 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2174 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2175
2176 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2177 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2178 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2179}
2180
f8896f5d
DW		 2181static uint32_t translate_signal_level(int signal_levels)
2182{
2183 uint32_t level;
2184
2185 switch (signal_levels) {
2186 default:
2187 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2188 signal_levels);
2189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2190 level = 0;
2191 break;
2192 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2193 level = 1;
2194 break;
2195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2196 level = 2;
2197 break;
2198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2199 level = 3;
2200 break;
2201
2202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2203 level = 4;
2204 break;
2205 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2206 level = 5;
2207 break;
2208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2209 level = 6;
2210 break;
2211
2212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2213 level = 7;
2214 break;
2215 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2216 level = 8;
2217 break;
2218
2219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2220 level = 9;
2221 break;
2222 }
2223
2224 return level;
2225}
2226
2227uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2228{
2229 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2230 struct drm_device *dev = dport->base.base.dev;
2231 struct intel_encoder *encoder = &dport->base;
2232 uint8_t train_set = intel_dp->train_set[0];
2233 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2234 DP_TRAIN_PRE_EMPHASIS_MASK);
2235 enum port port = dport->port;
2236 uint32_t level;
2237
2238 level = translate_signal_level(signal_levels);
2239
2240 if (IS_SKYLAKE(dev))
2241 skl_ddi_set_iboost(dev, level, port, encoder->type);
2242 else if (IS_BROXTON(dev))
2243 bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
2244
2245 return DDI_BUF_TRANS_SELECT(level);
2246}
2247
00c09d70 2248static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 2249{
c19b0669 2250 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2251 struct drm_device *dev = encoder->dev;
2252 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 2253 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 2254 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2255 int type = intel_encoder->type;
96fb9f9b 2256 int hdmi_level;
6441ab5f 2257
82a4d9c0
PZ		 2258 if (type == INTEL_OUTPUT_EDP) {
2259 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 2260 intel_edp_panel_on(intel_dp);
82a4d9c0 2261 }
6441ab5f 2262
efa80add 2263 if (IS_SKYLAKE(dev)) {
6e3c9717 2264 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 2265 uint32_t val;
2266
5416d871
DL		 2267 /*
2268 * DPLL0 is used for eDP and is the only "private" DPLL (as
2269 * opposed to shared) on SKL
2270 */
2271 if (type == INTEL_OUTPUT_EDP) {
2272 WARN_ON(dpll != SKL_DPLL0);
2273
2274 val = I915_READ(DPLL_CTRL1);
2275
2276 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2277 DPLL_CTRL1_SSC(dpll) |
71cd8423 2278 DPLL_CTRL1_LINK_RATE_MASK(dpll));
6e3c9717 2279 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 2280
2281 I915_WRITE(DPLL_CTRL1, val);
2282 POSTING_READ(DPLL_CTRL1);
2283 }
2284
2285 /* DDI -> PLL mapping */
efa80add
S		 2286 val = I915_READ(DPLL_CTRL2);
2287
2288 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2289 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2290 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2291 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2292
2293 I915_WRITE(DPLL_CTRL2, val);
5416d871 2294
1ab23380 2295 } else if (INTEL_INFO(dev)->gen < 9) {
6e3c9717
ACO		 2296 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2297 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 2298 }
c19b0669 2299
82a4d9c0 2300 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 2301 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 2302
44905a27 2303 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 2304
2305 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2306 intel_dp_start_link_train(intel_dp);
2307 intel_dp_complete_link_train(intel_dp);
23f08d83 2308 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 2309 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 2310 } else if (type == INTEL_OUTPUT_HDMI) {
2311 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2312
96fb9f9b
VK		 2313 if (IS_BROXTON(dev)) {
2314 hdmi_level = dev_priv->vbt.
2315 ddi_port_info[port].hdmi_level_shift;
2316 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
2317 INTEL_OUTPUT_HDMI);
2318 }
30cf6db8 2319 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 2320 crtc->config->has_hdmi_sink,
2321 &crtc->config->base.adjusted_mode);
c19b0669 2322 }
6441ab5f
PZ		 2323}
2324
00c09d70 2325static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 2326{
2327 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2328 struct drm_device *dev = encoder->dev;
2329 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 2330 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2331 int type = intel_encoder->type;
2886e93f 2332 uint32_t val;
a836bdf9 2333 bool wait = false;
2886e93f
PZ		 2334
2335 val = I915_READ(DDI_BUF_CTL(port));
2336 if (val & DDI_BUF_CTL_ENABLE) {
2337 val &= ~DDI_BUF_CTL_ENABLE;
2338 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2339 wait = true;
2886e93f 2340 }
6441ab5f 2341
a836bdf9
PZ		 2342 val = I915_READ(DP_TP_CTL(port));
2343 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2344 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2345 I915_WRITE(DP_TP_CTL(port), val);
2346
2347 if (wait)
2348 intel_wait_ddi_buf_idle(dev_priv, port);
2349
76bb80ed 2350 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 2351 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 2352 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 2353 intel_edp_panel_vdd_on(intel_dp);
4be73780 2354 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2355 }
2356
efa80add
S		 2357 if (IS_SKYLAKE(dev))
2358 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2359 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 2360 else if (INTEL_INFO(dev)->gen < 9)
efa80add 2361 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 2362}
2363
00c09d70 2364static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 2365{
6547fef8 2366 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2367 struct drm_crtc *crtc = encoder->crtc;
2368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 2369 struct drm_device *dev = encoder->dev;
72662e10 2370 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 2371 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2372 int type = intel_encoder->type;
72662e10 2373
6547fef8 2374 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2375 struct intel_digital_port *intel_dig_port =
2376 enc_to_dig_port(encoder);
2377
6547fef8
PZ		 2378 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2379 * are ignored so nothing special needs to be done besides
2380 * enabling the port.
2381 */
876a8cdf 2382 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2383 intel_dig_port->saved_port_bits |
2384 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2385 } else if (type == INTEL_OUTPUT_EDP) {
2386 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2387
23f08d83 2388 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 2389 intel_dp_stop_link_train(intel_dp);
2390
4be73780 2391 intel_edp_backlight_on(intel_dp);
0bc12bcb 2392 intel_psr_enable(intel_dp);
c395578e 2393 intel_edp_drrs_enable(intel_dp);
6547fef8 2394 }
7b9f35a6 2395
6e3c9717 2396 if (intel_crtc->config->has_audio) {
d45a0bf5 2397 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 2398 intel_audio_codec_enable(intel_encoder);
7b9f35a6 2399 }
5ab432ef
DV		 2400}
2401
00c09d70 2402static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 2403{
d6c50ff8 2404 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2405 struct drm_crtc *crtc = encoder->crtc;
2406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 2407 int type = intel_encoder->type;
7b9f35a6
WX		 2408 struct drm_device *dev = encoder->dev;
2409 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 2410
6e3c9717 2411 if (intel_crtc->config->has_audio) {
69bfe1a9 2412 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 2413 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2414 }
2831d842 2415
d6c50ff8
PZ		 2416 if (type == INTEL_OUTPUT_EDP) {
2417 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2418
c395578e 2419 intel_edp_drrs_disable(intel_dp);
0bc12bcb 2420 intel_psr_disable(intel_dp);
4be73780 2421 intel_edp_backlight_off(intel_dp);
d6c50ff8 2422 }
72662e10 2423}
79f689aa 2424
e0b01be4
DV		 2425static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
2426 struct intel_shared_dpll *pll)
2427{
3e369b76 2428 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 2429 POSTING_READ(WRPLL_CTL(pll->id));
2430 udelay(20);
2431}
2432
12030431
DV		 2433static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
2434 struct intel_shared_dpll *pll)
2435{
2436 uint32_t val;
2437
2438 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2439 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2440 POSTING_READ(WRPLL_CTL(pll->id));
2441}
2442
d452c5b6
DV		 2443static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2444 struct intel_shared_dpll *pll,
2445 struct intel_dpll_hw_state *hw_state)
2446{
2447 uint32_t val;
2448
f458ebbc 2449 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2450 return false;
2451
2452 val = I915_READ(WRPLL_CTL(pll->id));
2453 hw_state->wrpll = val;
2454
2455 return val & WRPLL_PLL_ENABLE;
2456}
2457
ca1381b5 2458static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2459 "WRPLL 1",
2460 "WRPLL 2",
2461};
2462
143b307c 2463static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2464{
9cd86933
DV		 2465 int i;
2466
716c2e55 2467 dev_priv->num_shared_dpll = 2;
9cd86933 2468
716c2e55 2469 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 2470 dev_priv->shared_dplls[i].id = i;
2471 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 2472 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 2473 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 2474 dev_priv->shared_dplls[i].get_hw_state =
2475 hsw_ddi_pll_get_hw_state;
9cd86933 2476 }
143b307c
DL		 2477}
2478
d1a2dc78
S		 2479static const char * const skl_ddi_pll_names[] = {
2480 "DPLL 1",
2481 "DPLL 2",
2482 "DPLL 3",
2483};
2484
2485struct skl_dpll_regs {
2486 u32 ctl, cfgcr1, cfgcr2;
2487};
2488
2489/* this array is indexed by the *shared* pll id */
2490static const struct skl_dpll_regs skl_dpll_regs[3] = {
2491 {
2492 /* DPLL 1 */
2493 .ctl = LCPLL2_CTL,
2494 .cfgcr1 = DPLL1_CFGCR1,
2495 .cfgcr2 = DPLL1_CFGCR2,
2496 },
2497 {
2498 /* DPLL 2 */
2499 .ctl = WRPLL_CTL1,
2500 .cfgcr1 = DPLL2_CFGCR1,
2501 .cfgcr2 = DPLL2_CFGCR2,
2502 },
2503 {
2504 /* DPLL 3 */
2505 .ctl = WRPLL_CTL2,
2506 .cfgcr1 = DPLL3_CFGCR1,
2507 .cfgcr2 = DPLL3_CFGCR2,
2508 },
2509};
2510
2511static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2512 struct intel_shared_dpll *pll)
2513{
2514 uint32_t val;
2515 unsigned int dpll;
2516 const struct skl_dpll_regs *regs = skl_dpll_regs;
2517
2518 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2519 dpll = pll->id + 1;
2520
2521 val = I915_READ(DPLL_CTRL1);
2522
2523 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
71cd8423 2524 DPLL_CTRL1_LINK_RATE_MASK(dpll));
d1a2dc78
S		 2525 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2526
2527 I915_WRITE(DPLL_CTRL1, val);
2528 POSTING_READ(DPLL_CTRL1);
2529
2530 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2531 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2532 POSTING_READ(regs[pll->id].cfgcr1);
2533 POSTING_READ(regs[pll->id].cfgcr2);
2534
2535 /* the enable bit is always bit 31 */
2536 I915_WRITE(regs[pll->id].ctl,
2537 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2538
2539 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2540 DRM_ERROR("DPLL %d not locked\n", dpll);
2541}
2542
2543static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2544 struct intel_shared_dpll *pll)
2545{
2546 const struct skl_dpll_regs *regs = skl_dpll_regs;
2547
2548 /* the enable bit is always bit 31 */
2549 I915_WRITE(regs[pll->id].ctl,
2550 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2551 POSTING_READ(regs[pll->id].ctl);
2552}
2553
2554static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2555 struct intel_shared_dpll *pll,
2556 struct intel_dpll_hw_state *hw_state)
2557{
2558 uint32_t val;
2559 unsigned int dpll;
2560 const struct skl_dpll_regs *regs = skl_dpll_regs;
2561
2562 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2563 return false;
2564
2565 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2566 dpll = pll->id + 1;
2567
2568 val = I915_READ(regs[pll->id].ctl);
2569 if (!(val & LCPLL_PLL_ENABLE))
2570 return false;
2571
2572 val = I915_READ(DPLL_CTRL1);
2573 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2574
2575 /* avoid reading back stale values if HDMI mode is not enabled */
2576 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2577 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2578 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2579 }
2580
2581 return true;
2582}
2583
2584static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2585{
2586 int i;
2587
2588 dev_priv->num_shared_dpll = 3;
2589
2590 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2591 dev_priv->shared_dplls[i].id = i;
2592 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2593 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2594 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2595 dev_priv->shared_dplls[i].get_hw_state =
2596 skl_ddi_pll_get_hw_state;
2597 }
2598}
2599
5c6706e5
VK		 2600static void broxton_phy_init(struct drm_i915_private *dev_priv,
2601 enum dpio_phy phy)
2602{
2603 enum port port;
2604 uint32_t val;
2605
2606 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2607 val |= GT_DISPLAY_POWER_ON(phy);
2608 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2609
2610 /* Considering 10ms timeout until BSpec is updated */
2611 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2612 DRM_ERROR("timeout during PHY%d power on\n", phy);
2613
2614 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2615 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2616 int lane;
2617
2618 for (lane = 0; lane < 4; lane++) {
2619 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2620 /*
2621 * Note that on CHV this flag is called UPAR, but has
2622 * the same function.
2623 */
2624 val &= ~LATENCY_OPTIM;
2625 if (lane != 1)
2626 val |= LATENCY_OPTIM;
2627
2628 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2629 }
2630 }
2631
2632 /* Program PLL Rcomp code offset */
2633 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2634 val &= ~IREF0RC_OFFSET_MASK;
2635 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2636 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2637
2638 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2639 val &= ~IREF1RC_OFFSET_MASK;
2640 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2641 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2642
2643 /* Program power gating */
2644 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2645 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2646 SUS_CLK_CONFIG;
2647 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2648
2649 if (phy == DPIO_PHY0) {
2650 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2651 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2652 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2653 }
2654
2655 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2656 val &= ~OCL2_LDOFUSE_PWR_DIS;
2657 /*
2658 * On PHY1 disable power on the second channel, since no port is
2659 * connected there. On PHY0 both channels have a port, so leave it
2660 * enabled.
2661 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2662 * power down the second channel on PHY0 as well.
2663 */
2664 if (phy == DPIO_PHY1)
2665 val |= OCL2_LDOFUSE_PWR_DIS;
2666 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2667
2668 if (phy == DPIO_PHY0) {
2669 uint32_t grc_code;
2670 /*
2671 * PHY0 isn't connected to an RCOMP resistor so copy over
2672 * the corresponding calibrated value from PHY1, and disable
2673 * the automatic calibration on PHY0.
2674 */
2675 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2676 10))
2677 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2678
2679 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2680 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2681 grc_code = val << GRC_CODE_FAST_SHIFT |
2682 val << GRC_CODE_SLOW_SHIFT |
2683 val;
2684 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2685
2686 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2687 val |= GRC_DIS | GRC_RDY_OVRD;
2688 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2689 }
2690
2691 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2692 val |= COMMON_RESET_DIS;
2693 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2694}
2695
2696void broxton_ddi_phy_init(struct drm_device *dev)
2697{
2698 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2699 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2700 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2701}
2702
2703static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2704 enum dpio_phy phy)
2705{
2706 uint32_t val;
2707
2708 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2709 val &= ~COMMON_RESET_DIS;
2710 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2711}
2712
2713void broxton_ddi_phy_uninit(struct drm_device *dev)
2714{
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716
2717 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2718 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2719
2720 /* FIXME: do this in broxton_phy_uninit per phy */
2721 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2722}
2723
dfb82408
S		 2724static const char * const bxt_ddi_pll_names[] = {
2725 "PORT PLL A",
2726 "PORT PLL B",
2727 "PORT PLL C",
2728};
2729
2730static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2731 struct intel_shared_dpll *pll)
2732{
2733 uint32_t temp;
2734 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2735
2736 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2737 temp &= ~PORT_PLL_REF_SEL;
2738 /* Non-SSC reference */
2739 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2740
2741 /* Disable 10 bit clock */
2742 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2743 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2744 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2745
2746 /* Write P1 & P2 */
2747 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2748 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2749 temp |= pll->config.hw_state.ebb0;
2750 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2751
2752 /* Write M2 integer */
2753 temp = I915_READ(BXT_PORT_PLL(port, 0));
2754 temp &= ~PORT_PLL_M2_MASK;
2755 temp |= pll->config.hw_state.pll0;
2756 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2757
2758 /* Write N */
2759 temp = I915_READ(BXT_PORT_PLL(port, 1));
2760 temp &= ~PORT_PLL_N_MASK;
2761 temp |= pll->config.hw_state.pll1;
2762 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2763
2764 /* Write M2 fraction */
2765 temp = I915_READ(BXT_PORT_PLL(port, 2));
2766 temp &= ~PORT_PLL_M2_FRAC_MASK;
2767 temp |= pll->config.hw_state.pll2;
2768 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2769
2770 /* Write M2 fraction enable */
2771 temp = I915_READ(BXT_PORT_PLL(port, 3));
2772 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2773 temp |= pll->config.hw_state.pll3;
2774 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2775
2776 /* Write coeff */
2777 temp = I915_READ(BXT_PORT_PLL(port, 6));
2778 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2779 temp &= ~PORT_PLL_INT_COEFF_MASK;
2780 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2781 temp |= pll->config.hw_state.pll6;
2782 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2783
2784 /* Write calibration val */
2785 temp = I915_READ(BXT_PORT_PLL(port, 8));
2786 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2787 temp |= pll->config.hw_state.pll8;
2788 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2789
b6dc71f3
VK		 2790 temp = I915_READ(BXT_PORT_PLL(port, 9));
2791 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
05712c15 2792 temp |= pll->config.hw_state.pll9;
b6dc71f3
VK		 2793 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2794
2795 temp = I915_READ(BXT_PORT_PLL(port, 10));
2796 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2797 temp &= ~PORT_PLL_DCO_AMP_MASK;
2798 temp |= pll->config.hw_state.pll10;
2799 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
dfb82408
S		 2800
2801 /* Recalibrate with new settings */
2802 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2803 temp |= PORT_PLL_RECALIBRATE;
2804 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
05712c15
ID		 2805 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2806 temp |= pll->config.hw_state.ebb4;
dfb82408
S		 2807 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2808
2809 /* Enable PLL */
2810 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2811 temp |= PORT_PLL_ENABLE;
2812 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2813 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2814
2815 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2816 PORT_PLL_LOCK), 200))
2817 DRM_ERROR("PLL %d not locked\n", port);
2818
2819 /*
2820 * While we write to the group register to program all lanes at once we
2821 * can read only lane registers and we pick lanes 0/1 for that.
2822 */
2823 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2824 temp &= ~LANE_STAGGER_MASK;
2825 temp &= ~LANESTAGGER_STRAP_OVRD;
2826 temp |= pll->config.hw_state.pcsdw12;
2827 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2828}
2829
2830static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2831 struct intel_shared_dpll *pll)
2832{
2833 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2834 uint32_t temp;
2835
2836 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2837 temp &= ~PORT_PLL_ENABLE;
2838 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2839 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2840}
2841
2842static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2843 struct intel_shared_dpll *pll,
2844 struct intel_dpll_hw_state *hw_state)
2845{
2846 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2847 uint32_t val;
2848
2849 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2850 return false;
2851
2852 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2853 if (!(val & PORT_PLL_ENABLE))
2854 return false;
2855
2856 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
793dfa59
ID		 2857 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2858
05712c15
ID		 2859 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2860 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2861
dfb82408 2862 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
793dfa59
ID		 2863 hw_state->pll0 &= PORT_PLL_M2_MASK;
2864
dfb82408 2865 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
793dfa59
ID		 2866 hw_state->pll1 &= PORT_PLL_N_MASK;
2867
dfb82408 2868 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
793dfa59
ID		 2869 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2870
dfb82408 2871 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
793dfa59
ID		 2872 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2873
dfb82408 2874 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
793dfa59
ID		 2875 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2876 PORT_PLL_INT_COEFF_MASK |
2877 PORT_PLL_GAIN_CTL_MASK;
2878
dfb82408 2879 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
793dfa59
ID		 2880 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2881
05712c15
ID		 2882 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
2883 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2884
b6dc71f3 2885 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
793dfa59
ID		 2886 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2887 PORT_PLL_DCO_AMP_MASK;
2888
dfb82408
S		 2889 /*
2890 * While we write to the group register to program all lanes at once we
2891 * can read only lane registers. We configure all lanes the same way, so
2892 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2893 */
2894 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2895 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
2896 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2897 hw_state->pcsdw12,
2898 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
793dfa59 2899 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
dfb82408
S		 2900
2901 return true;
2902}
2903
2904static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2905{
2906 int i;
2907
2908 dev_priv->num_shared_dpll = 3;
2909
2910 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2911 dev_priv->shared_dplls[i].id = i;
2912 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2913 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2914 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2915 dev_priv->shared_dplls[i].get_hw_state =
2916 bxt_ddi_pll_get_hw_state;
2917 }
2918}
2919
143b307c
DL		 2920void intel_ddi_pll_init(struct drm_device *dev)
2921{
2922 struct drm_i915_private *dev_priv = dev->dev_private;
2923 uint32_t val = I915_READ(LCPLL_CTL);
2924
d1a2dc78
S		 2925 if (IS_SKYLAKE(dev))
2926 skl_shared_dplls_init(dev_priv);
dfb82408
S		 2927 else if (IS_BROXTON(dev))
2928 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 2929 else
2930 hsw_shared_dplls_init(dev_priv);
79f689aa 2931
121643c2 2932 if (IS_SKYLAKE(dev)) {
d9062ae5
DL		 2933 int cdclk_freq;
2934
2935 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5d96d8af 2936 dev_priv->skl_boot_cdclk = cdclk_freq;
121643c2
S		 2937 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2938 DRM_ERROR("LCPLL1 is disabled\n");
5d96d8af
DL		 2939 else
2940 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
f8437dd1
VK		 2941 } else if (IS_BROXTON(dev)) {
2942 broxton_init_cdclk(dev);
5c6706e5 2943 broxton_ddi_phy_init(dev);
121643c2
S		 2944 } else {
2945 /*
2946 * The LCPLL register should be turned on by the BIOS. For now
2947 * let's just check its state and print errors in case
2948 * something is wrong. Don't even try to turn it on.
2949 */
2950
2951 if (val & LCPLL_CD_SOURCE_FCLK)
2952 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 2953
121643c2
S		 2954 if (val & LCPLL_PLL_DISABLE)
2955 DRM_ERROR("LCPLL is disabled\n");
2956 }
79f689aa 2957}
c19b0669
PZ		 2958
2959void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
2960{
174edf1f
PZ		 2961 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2962 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 2963 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 2964 enum port port = intel_dig_port->port;
c19b0669 2965 uint32_t val;
f3e227df 2966 bool wait = false;
c19b0669
PZ		 2967
2968 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2969 val = I915_READ(DDI_BUF_CTL(port));
2970 if (val & DDI_BUF_CTL_ENABLE) {
2971 val &= ~DDI_BUF_CTL_ENABLE;
2972 I915_WRITE(DDI_BUF_CTL(port), val);
2973 wait = true;
2974 }
2975
2976 val = I915_READ(DP_TP_CTL(port));
2977 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2978 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2979 I915_WRITE(DP_TP_CTL(port), val);
2980 POSTING_READ(DP_TP_CTL(port));
2981
2982 if (wait)
2983 intel_wait_ddi_buf_idle(dev_priv, port);
2984 }
2985
0e32b39c 2986 val = DP_TP_CTL_ENABLE |
c19b0669 2987 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 2988 if (intel_dp->is_mst)
2989 val |= DP_TP_CTL_MODE_MST;
2990 else {
2991 val |= DP_TP_CTL_MODE_SST;
2992 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2993 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2994 }
c19b0669
PZ		 2995 I915_WRITE(DP_TP_CTL(port), val);
2996 POSTING_READ(DP_TP_CTL(port));
2997
2998 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2999 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3000 POSTING_READ(DDI_BUF_CTL(port));
3001
3002 udelay(600);
3003}
00c09d70 3004
1ad960f2
PZ		 3005void intel_ddi_fdi_disable(struct drm_crtc *crtc)
3006{
3007 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3008 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3009 uint32_t val;
3010
3011 intel_ddi_post_disable(intel_encoder);
3012
3013 val = I915_READ(_FDI_RXA_CTL);
3014 val &= ~FDI_RX_ENABLE;
3015 I915_WRITE(_FDI_RXA_CTL, val);
3016
3017 val = I915_READ(_FDI_RXA_MISC);
3018 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3019 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3020 I915_WRITE(_FDI_RXA_MISC, val);
3021
3022 val = I915_READ(_FDI_RXA_CTL);
3023 val &= ~FDI_PCDCLK;
3024 I915_WRITE(_FDI_RXA_CTL, val);
3025
3026 val = I915_READ(_FDI_RXA_CTL);
3027 val &= ~FDI_RX_PLL_ENABLE;
3028 I915_WRITE(_FDI_RXA_CTL, val);
3029}
3030
6801c18c 3031void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3032 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 3033{
3034 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3035 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 3036 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 3037 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 3038 u32 temp, flags = 0;
3039
3040 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3041 if (temp & TRANS_DDI_PHSYNC)
3042 flags |= DRM_MODE_FLAG_PHSYNC;
3043 else
3044 flags |= DRM_MODE_FLAG_NHSYNC;
3045 if (temp & TRANS_DDI_PVSYNC)
3046 flags |= DRM_MODE_FLAG_PVSYNC;
3047 else
3048 flags |= DRM_MODE_FLAG_NVSYNC;
3049
2d112de7 3050 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3051
3052 switch (temp & TRANS_DDI_BPC_MASK) {
3053 case TRANS_DDI_BPC_6:
3054 pipe_config->pipe_bpp = 18;
3055 break;
3056 case TRANS_DDI_BPC_8:
3057 pipe_config->pipe_bpp = 24;
3058 break;
3059 case TRANS_DDI_BPC_10:
3060 pipe_config->pipe_bpp = 30;
3061 break;
3062 case TRANS_DDI_BPC_12:
3063 pipe_config->pipe_bpp = 36;
3064 break;
3065 default:
3066 break;
3067 }
eb14cb74
VS		 3068
3069 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3070 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3071 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 3072 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3073
3074 if (intel_hdmi->infoframe_enabled(&encoder->base))
3075 pipe_config->has_infoframe = true;
cbc572a9 3076 break;
eb14cb74
VS		 3077 case TRANS_DDI_MODE_SELECT_DVI:
3078 case TRANS_DDI_MODE_SELECT_FDI:
3079 break;
3080 case TRANS_DDI_MODE_SELECT_DP_SST:
3081 case TRANS_DDI_MODE_SELECT_DP_MST:
3082 pipe_config->has_dp_encoder = true;
3083 intel_dp_get_m_n(intel_crtc, pipe_config);
3084 break;
3085 default:
3086 break;
3087 }
10214420 3088
f458ebbc 3089 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 3090 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 3091 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 3092 pipe_config->has_audio = true;
3093 }
9ed109a7 3094
10214420
DV		 3095 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3096 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3097 /*
3098 * This is a big fat ugly hack.
3099 *
3100 * Some machines in UEFI boot mode provide us a VBT that has 18
3101 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3102 * unknown we fail to light up. Yet the same BIOS boots up with
3103 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3104 * max, not what it tells us to use.
3105 *
3106 * Note: This will still be broken if the eDP panel is not lit
3107 * up by the BIOS, and thus we can't get the mode at module
3108 * load.
3109 */
3110 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3111 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3112 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3113 }
11578553 3114
22606a18 3115 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 3116}
3117
00c09d70
PZ		 3118static void intel_ddi_destroy(struct drm_encoder *encoder)
3119{
3120 /* HDMI has nothing special to destroy, so we can go with this. */
3121 intel_dp_encoder_destroy(encoder);
3122}
3123
5bfe2ac0 3124static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 3125 struct intel_crtc_state *pipe_config)
00c09d70 3126{
5bfe2ac0 3127 int type = encoder->type;
eccb140b 3128 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 3129
5bfe2ac0 3130 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 3131
eccb140b
DV		 3132 if (port == PORT_A)
3133 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3134
00c09d70 3135 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 3136 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 3137 else
5bfe2ac0 3138 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 3139}
3140
3141static const struct drm_encoder_funcs intel_ddi_funcs = {
3142 .destroy = intel_ddi_destroy,
3143};
3144
4a28ae58
PZ		 3145static struct intel_connector *
3146intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3147{
3148 struct intel_connector *connector;
3149 enum port port = intel_dig_port->port;
3150
9bdbd0b9 3151 connector = intel_connector_alloc();
4a28ae58
PZ		 3152 if (!connector)
3153 return NULL;
3154
3155 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3156 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3157 kfree(connector);
3158 return NULL;
3159 }
3160
3161 return connector;
3162}
3163
3164static struct intel_connector *
3165intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3166{
3167 struct intel_connector *connector;
3168 enum port port = intel_dig_port->port;
3169
9bdbd0b9 3170 connector = intel_connector_alloc();
4a28ae58
PZ		 3171 if (!connector)
3172 return NULL;
3173
3174 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3175 intel_hdmi_init_connector(intel_dig_port, connector);
3176
3177 return connector;
3178}
3179
00c09d70
PZ		 3180void intel_ddi_init(struct drm_device *dev, enum port port)
3181{
876a8cdf 3182 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 3183 struct intel_digital_port *intel_dig_port;
3184 struct intel_encoder *intel_encoder;
3185 struct drm_encoder *encoder;
311a2094
PZ		 3186 bool init_hdmi, init_dp;
3187
3188 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3189 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3190 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3191 if (!init_dp && !init_hdmi) {
f68d697e 3192 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
311a2094
PZ		 3193 port_name(port));
3194 init_hdmi = true;
3195 init_dp = true;
3196 }
00c09d70 3197
b14c5679 3198 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 3199 if (!intel_dig_port)
3200 return;
3201
00c09d70
PZ		 3202 intel_encoder = &intel_dig_port->base;
3203 encoder = &intel_encoder->base;
3204
3205 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
3206 DRM_MODE_ENCODER_TMDS);
00c09d70 3207
5bfe2ac0 3208 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 3209 intel_encoder->enable = intel_enable_ddi;
3210 intel_encoder->pre_enable = intel_ddi_pre_enable;
3211 intel_encoder->disable = intel_disable_ddi;
3212 intel_encoder->post_disable = intel_ddi_post_disable;
3213 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 3214 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 3215
3216 intel_dig_port->port = port;
bcf53de4
SM		 3217 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3218 (DDI_BUF_PORT_REVERSAL |
3219 DDI_A_4_LANES);
00c09d70
PZ		 3220
3221 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 3222 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3223 intel_encoder->cloneable = 0;
00c09d70 3224
f68d697e
CW		 3225 if (init_dp) {
3226 if (!intel_ddi_init_dp_connector(intel_dig_port))
3227 goto err;
13cf5504 3228
f68d697e 3229 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 3230 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 3231 }
21a8e6a4 3232
311a2094
PZ		 3233 /* In theory we don't need the encoder->type check, but leave it just in
3234 * case we have some really bad VBTs... */
f68d697e
CW		 3235 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3236 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3237 goto err;
21a8e6a4 3238 }
f68d697e
CW		 3239
3240 return;
3241
3242err:
3243 drm_encoder_cleanup(encoder);
3244 kfree(intel_dig_port);
00c09d70 3245}
Linux kernel - Deliverables
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