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drm/i915: show unknown sdvox registers on hdmi init
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
021357ac
CW		 101static inline u32 /* units of 100MHz */
102intel_fdi_link_freq(struct drm_device *dev)
103{
8b99e68c
CW		 104 if (IS_GEN5(dev)) {
105 struct drm_i915_private *dev_priv = dev->dev_private;
106 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
107 } else
108 return 27;
021357ac
CW		 109}
110
e4b36699 111static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 112 .dot = { .min = 25000, .max = 350000 },
113 .vco = { .min = 930000, .max = 1400000 },
114 .n = { .min = 3, .max = 16 },
115 .m = { .min = 96, .max = 140 },
116 .m1 = { .min = 18, .max = 26 },
117 .m2 = { .min = 6, .max = 16 },
118 .p = { .min = 4, .max = 128 },
119 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 120 .p2 = { .dot_limit = 165000,
121 .p2_slow = 4, .p2_fast = 2 },
d4906093 122 .find_pll = intel_find_best_PLL,
e4b36699
KP		 123};
124
125static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 126 .dot = { .min = 25000, .max = 350000 },
127 .vco = { .min = 930000, .max = 1400000 },
128 .n = { .min = 3, .max = 16 },
129 .m = { .min = 96, .max = 140 },
130 .m1 = { .min = 18, .max = 26 },
131 .m2 = { .min = 6, .max = 16 },
132 .p = { .min = 4, .max = 128 },
133 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 134 .p2 = { .dot_limit = 165000,
135 .p2_slow = 14, .p2_fast = 7 },
d4906093 136 .find_pll = intel_find_best_PLL,
e4b36699 137};
273e27ca 138
e4b36699 139static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 140 .dot = { .min = 20000, .max = 400000 },
141 .vco = { .min = 1400000, .max = 2800000 },
142 .n = { .min = 1, .max = 6 },
143 .m = { .min = 70, .max = 120 },
144 .m1 = { .min = 10, .max = 22 },
145 .m2 = { .min = 5, .max = 9 },
146 .p = { .min = 5, .max = 80 },
147 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 148 .p2 = { .dot_limit = 200000,
149 .p2_slow = 10, .p2_fast = 5 },
d4906093 150 .find_pll = intel_find_best_PLL,
e4b36699
KP		 151};
152
153static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 154 .dot = { .min = 20000, .max = 400000 },
155 .vco = { .min = 1400000, .max = 2800000 },
156 .n = { .min = 1, .max = 6 },
157 .m = { .min = 70, .max = 120 },
158 .m1 = { .min = 10, .max = 22 },
159 .m2 = { .min = 5, .max = 9 },
160 .p = { .min = 7, .max = 98 },
161 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 162 .p2 = { .dot_limit = 112000,
163 .p2_slow = 14, .p2_fast = 7 },
d4906093 164 .find_pll = intel_find_best_PLL,
e4b36699
KP		 165};
166
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 169 .dot = { .min = 25000, .max = 270000 },
170 .vco = { .min = 1750000, .max = 3500000},
171 .n = { .min = 1, .max = 4 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 10, .max = 30 },
176 .p1 = { .min = 1, .max = 3},
177 .p2 = { .dot_limit = 270000,
178 .p2_slow = 10,
179 .p2_fast = 10
044c7c41 180 },
d4906093 181 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 182};
183
184static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 185 .dot = { .min = 22000, .max = 400000 },
186 .vco = { .min = 1750000, .max = 3500000},
187 .n = { .min = 1, .max = 4 },
188 .m = { .min = 104, .max = 138 },
189 .m1 = { .min = 16, .max = 23 },
190 .m2 = { .min = 5, .max = 11 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8},
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 10, .p2_fast = 5 },
d4906093 195 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 196};
197
198static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 199 .dot = { .min = 20000, .max = 115000 },
200 .vco = { .min = 1750000, .max = 3500000 },
201 .n = { .min = 1, .max = 3 },
202 .m = { .min = 104, .max = 138 },
203 .m1 = { .min = 17, .max = 23 },
204 .m2 = { .min = 5, .max = 11 },
205 .p = { .min = 28, .max = 112 },
206 .p1 = { .min = 2, .max = 8 },
207 .p2 = { .dot_limit = 0,
208 .p2_slow = 14, .p2_fast = 14
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 80000, .max = 224000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 14, .max = 42 },
221 .p1 = { .min = 2, .max = 6 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 7, .p2_fast = 7
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 229 .dot = { .min = 161670, .max = 227000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 2 },
232 .m = { .min = 97, .max = 108 },
233 .m1 = { .min = 0x10, .max = 0x12 },
234 .m2 = { .min = 0x05, .max = 0x06 },
235 .p = { .min = 10, .max = 20 },
236 .p1 = { .min = 1, .max = 2},
237 .p2 = { .dot_limit = 0,
273e27ca 238 .p2_slow = 10, .p2_fast = 10 },
0206e353 239 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 240};
241
f2b115e6 242static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 243 .dot = { .min = 20000, .max = 400000},
244 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 245 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
273e27ca 248 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 249 .m1 = { .min = 0, .max = 0 },
250 .m2 = { .min = 0, .max = 254 },
251 .p = { .min = 5, .max = 80 },
252 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 253 .p2 = { .dot_limit = 200000,
254 .p2_slow = 10, .p2_fast = 5 },
6115707b 255 .find_pll = intel_find_best_PLL,
e4b36699
KP		 256};
257
f2b115e6 258static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 259 .dot = { .min = 20000, .max = 400000 },
260 .vco = { .min = 1700000, .max = 3500000 },
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 .m1 = { .min = 0, .max = 0 },
264 .m2 = { .min = 0, .max = 254 },
265 .p = { .min = 7, .max = 112 },
266 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 267 .p2 = { .dot_limit = 112000,
268 .p2_slow = 14, .p2_fast = 14 },
6115707b 269 .find_pll = intel_find_best_PLL,
e4b36699
KP		 270};
271
273e27ca
EA		 272/* Ironlake / Sandybridge
273 *
274 * We calculate clock using (register_value + 2) for N/M1/M2, so here
275 * the range value for them is (actual_value - 2).
276 */
b91ad0ec 277static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 278 .dot = { .min = 25000, .max = 350000 },
279 .vco = { .min = 1760000, .max = 3510000 },
280 .n = { .min = 1, .max = 5 },
281 .m = { .min = 79, .max = 127 },
282 .m1 = { .min = 12, .max = 22 },
283 .m2 = { .min = 5, .max = 9 },
284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
286 .p2 = { .dot_limit = 225000,
287 .p2_slow = 10, .p2_fast = 5 },
4547668a 288 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 289};
290
b91ad0ec 291static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 292 .dot = { .min = 25000, .max = 350000 },
293 .vco = { .min = 1760000, .max = 3510000 },
294 .n = { .min = 1, .max = 3 },
295 .m = { .min = 79, .max = 118 },
296 .m1 = { .min = 12, .max = 22 },
297 .m2 = { .min = 5, .max = 9 },
298 .p = { .min = 28, .max = 112 },
299 .p1 = { .min = 2, .max = 8 },
300 .p2 = { .dot_limit = 225000,
301 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 302 .find_pll = intel_g4x_find_best_PLL,
303};
304
305static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 3 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 14, .max = 56 },
313 .p1 = { .min = 2, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 316 .find_pll = intel_g4x_find_best_PLL,
317};
318
273e27ca 319/* LVDS 100mhz refclk limits. */
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 2 },
324 .m = { .min = 79, .max = 126 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
0206e353 328 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 42 },
0206e353 342 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
348static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 349 .dot = { .min = 25000, .max = 350000 },
350 .vco = { .min = 1760000, .max = 3510000},
351 .n = { .min = 1, .max = 2 },
352 .m = { .min = 81, .max = 90 },
353 .m1 = { .min = 12, .max = 22 },
354 .m2 = { .min = 5, .max = 9 },
355 .p = { .min = 10, .max = 20 },
356 .p1 = { .min = 1, .max = 2},
357 .p2 = { .dot_limit = 0,
273e27ca 358 .p2_slow = 10, .p2_fast = 10 },
0206e353 359 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 360};
361
57f350b6
JB		 362u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
363{
364 unsigned long flags;
365 u32 val = 0;
366
367 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
368 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
369 DRM_ERROR("DPIO idle wait timed out\n");
370 goto out_unlock;
371 }
372
373 I915_WRITE(DPIO_REG, reg);
374 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
375 DPIO_BYTE);
376 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
377 DRM_ERROR("DPIO read wait timed out\n");
378 goto out_unlock;
379 }
380 val = I915_READ(DPIO_DATA);
381
382out_unlock:
383 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
384 return val;
385}
386
57f350b6
JB		 387static void vlv_init_dpio(struct drm_device *dev)
388{
389 struct drm_i915_private *dev_priv = dev->dev_private;
390
391 /* Reset the DPIO config */
392 I915_WRITE(DPIO_CTL, 0);
393 POSTING_READ(DPIO_CTL);
394 I915_WRITE(DPIO_CTL, 1);
395 POSTING_READ(DPIO_CTL);
396}
397
618563e3
DV		 398static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
399{
400 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
401 return 1;
402}
403
404static const struct dmi_system_id intel_dual_link_lvds[] = {
405 {
406 .callback = intel_dual_link_lvds_callback,
407 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
408 .matches = {
409 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
410 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
411 },
412 },
413 { } /* terminating entry */
414};
415
b0354385
TI		 416static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
417 unsigned int reg)
418{
419 unsigned int val;
420
121d527a
TI		 421 /* use the module option value if specified */
422 if (i915_lvds_channel_mode > 0)
423 return i915_lvds_channel_mode == 2;
424
618563e3
DV		 425 if (dmi_check_system(intel_dual_link_lvds))
426 return true;
427
b0354385
TI		 428 if (dev_priv->lvds_val)
429 val = dev_priv->lvds_val;
430 else {
431 /* BIOS should set the proper LVDS register value at boot, but
432 * in reality, it doesn't set the value when the lid is closed;
433 * we need to check "the value to be set" in VBT when LVDS
434 * register is uninitialized.
435 */
436 val = I915_READ(reg);
437 if (!(val & ~LVDS_DETECTED))
438 val = dev_priv->bios_lvds_val;
439 dev_priv->lvds_val = val;
440 }
441 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
442}
443
1b894b59
CW		 444static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
445 int refclk)
2c07245f 446{
b91ad0ec
ZW		 447 struct drm_device *dev = crtc->dev;
448 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 449 const intel_limit_t *limit;
b91ad0ec
ZW		 450
451 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 452 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 453 /* LVDS dual channel */
1b894b59 454 if (refclk == 100000)
b91ad0ec
ZW		 455 limit = &intel_limits_ironlake_dual_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_dual_lvds;
458 } else {
1b894b59 459 if (refclk == 100000)
b91ad0ec
ZW		 460 limit = &intel_limits_ironlake_single_lvds_100m;
461 else
462 limit = &intel_limits_ironlake_single_lvds;
463 }
464 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 465 HAS_eDP)
466 limit = &intel_limits_ironlake_display_port;
2c07245f 467 else
b91ad0ec 468 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 469
470 return limit;
471}
472
044c7c41
ML		 473static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
474{
475 struct drm_device *dev = crtc->dev;
476 struct drm_i915_private *dev_priv = dev->dev_private;
477 const intel_limit_t *limit;
478
479 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 480 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 481 /* LVDS with dual channel */
e4b36699 482 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 483 else
484 /* LVDS with dual channel */
e4b36699 485 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 486 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
487 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 488 limit = &intel_limits_g4x_hdmi;
044c7c41 489 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 490 limit = &intel_limits_g4x_sdvo;
0206e353 491 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 492 limit = &intel_limits_g4x_display_port;
044c7c41 493 } else /* The option is for other outputs */
e4b36699 494 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 495
496 return limit;
497}
498
1b894b59 499static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 500{
501 struct drm_device *dev = crtc->dev;
502 const intel_limit_t *limit;
503
bad720ff 504 if (HAS_PCH_SPLIT(dev))
1b894b59 505 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 506 else if (IS_G4X(dev)) {
044c7c41 507 limit = intel_g4x_limit(crtc);
f2b115e6 508 } else if (IS_PINEVIEW(dev)) {
2177832f 509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 510 limit = &intel_limits_pineview_lvds;
2177832f 511 else
f2b115e6 512 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 513 } else if (!IS_GEN2(dev)) {
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i9xx_lvds;
516 else
517 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 518 } else {
519 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 520 limit = &intel_limits_i8xx_lvds;
79e53945 521 else
e4b36699 522 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 523 }
524 return limit;
525}
526
f2b115e6
AJ		 527/* m1 is reserved as 0 in Pineview, n is a ring counter */
528static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 529{
2177832f
SL		 530 clock->m = clock->m2 + 2;
531 clock->p = clock->p1 * clock->p2;
532 clock->vco = refclk * clock->m / clock->n;
533 clock->dot = clock->vco / clock->p;
534}
535
536static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
537{
f2b115e6
AJ		 538 if (IS_PINEVIEW(dev)) {
539 pineview_clock(refclk, clock);
2177832f
SL		 540 return;
541 }
79e53945
JB		 542 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
543 clock->p = clock->p1 * clock->p2;
544 clock->vco = refclk * clock->m / (clock->n + 2);
545 clock->dot = clock->vco / clock->p;
546}
547
79e53945
JB		 548/**
549 * Returns whether any output on the specified pipe is of the specified type
550 */
4ef69c7a 551bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 552{
4ef69c7a
CW		 553 struct drm_device *dev = crtc->dev;
554 struct drm_mode_config *mode_config = &dev->mode_config;
555 struct intel_encoder *encoder;
556
557 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
558 if (encoder->base.crtc == crtc && encoder->type == type)
559 return true;
560
561 return false;
79e53945
JB		 562}
563
7c04d1d9 564#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 565/**
566 * Returns whether the given set of divisors are valid for a given refclk with
567 * the given connectors.
568 */
569
1b894b59
CW		 570static bool intel_PLL_is_valid(struct drm_device *dev,
571 const intel_limit_t *limit,
572 const intel_clock_t *clock)
79e53945 573{
79e53945 574 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 575 INTELPllInvalid("p1 out of range\n");
79e53945 576 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 577 INTELPllInvalid("p out of range\n");
79e53945 578 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 579 INTELPllInvalid("m2 out of range\n");
79e53945 580 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 581 INTELPllInvalid("m1 out of range\n");
f2b115e6 582 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 583 INTELPllInvalid("m1 <= m2\n");
79e53945 584 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 585 INTELPllInvalid("m out of range\n");
79e53945 586 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 587 INTELPllInvalid("n out of range\n");
79e53945 588 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 589 INTELPllInvalid("vco out of range\n");
79e53945
JB		 590 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
591 * connector, etc., rather than just a single range.
592 */
593 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 594 INTELPllInvalid("dot out of range\n");
79e53945
JB		 595
596 return true;
597}
598
d4906093
ML		 599static bool
600intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 601 int target, int refclk, intel_clock_t *match_clock,
602 intel_clock_t *best_clock)
d4906093 603
79e53945
JB		 604{
605 struct drm_device *dev = crtc->dev;
606 struct drm_i915_private *dev_priv = dev->dev_private;
607 intel_clock_t clock;
79e53945
JB		 608 int err = target;
609
bc5e5718 610 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 611 (I915_READ(LVDS)) != 0) {
79e53945
JB		 612 /*
613 * For LVDS, if the panel is on, just rely on its current
614 * settings for dual-channel. We haven't figured out how to
615 * reliably set up different single/dual channel state, if we
616 * even can.
617 */
b0354385 618 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 619 clock.p2 = limit->p2.p2_fast;
620 else
621 clock.p2 = limit->p2.p2_slow;
622 } else {
623 if (target < limit->p2.dot_limit)
624 clock.p2 = limit->p2.p2_slow;
625 else
626 clock.p2 = limit->p2.p2_fast;
627 }
628
0206e353 629 memset(best_clock, 0, sizeof(*best_clock));
79e53945 630
42158660
ZY		 631 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
632 clock.m1++) {
633 for (clock.m2 = limit->m2.min;
634 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 635 /* m1 is always 0 in Pineview */
636 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 637 break;
638 for (clock.n = limit->n.min;
639 clock.n <= limit->n.max; clock.n++) {
640 for (clock.p1 = limit->p1.min;
641 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 642 int this_err;
643
2177832f 644 intel_clock(dev, refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
79e53945 647 continue;
cec2f356
SP		 648 if (match_clock &&
649 clock.p != match_clock->p)
650 continue;
79e53945
JB		 651
652 this_err = abs(clock.dot - target);
653 if (this_err < err) {
654 *best_clock = clock;
655 err = this_err;
656 }
657 }
658 }
659 }
660 }
661
662 return (err != target);
663}
664
d4906093
ML		 665static bool
666intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 667 int target, int refclk, intel_clock_t *match_clock,
668 intel_clock_t *best_clock)
d4906093
ML		 669{
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 intel_clock_t clock;
673 int max_n;
674 bool found;
6ba770dc
AJ		 675 /* approximately equals target * 0.00585 */
676 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 677 found = false;
678
679 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 680 int lvds_reg;
681
c619eed4 682 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 683 lvds_reg = PCH_LVDS;
684 else
685 lvds_reg = LVDS;
686 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 687 LVDS_CLKB_POWER_UP)
688 clock.p2 = limit->p2.p2_fast;
689 else
690 clock.p2 = limit->p2.p2_slow;
691 } else {
692 if (target < limit->p2.dot_limit)
693 clock.p2 = limit->p2.p2_slow;
694 else
695 clock.p2 = limit->p2.p2_fast;
696 }
697
698 memset(best_clock, 0, sizeof(*best_clock));
699 max_n = limit->n.max;
f77f13e2 700 /* based on hardware requirement, prefer smaller n to precision */
d4906093 701 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 702 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 703 for (clock.m1 = limit->m1.max;
704 clock.m1 >= limit->m1.min; clock.m1--) {
705 for (clock.m2 = limit->m2.max;
706 clock.m2 >= limit->m2.min; clock.m2--) {
707 for (clock.p1 = limit->p1.max;
708 clock.p1 >= limit->p1.min; clock.p1--) {
709 int this_err;
710
2177832f 711 intel_clock(dev, refclk, &clock);
1b894b59
CW		 712 if (!intel_PLL_is_valid(dev, limit,
713 &clock))
d4906093 714 continue;
cec2f356
SP		 715 if (match_clock &&
716 clock.p != match_clock->p)
717 continue;
1b894b59
CW		 718
719 this_err = abs(clock.dot - target);
d4906093
ML		 720 if (this_err < err_most) {
721 *best_clock = clock;
722 err_most = this_err;
723 max_n = clock.n;
724 found = true;
725 }
726 }
727 }
728 }
729 }
2c07245f
ZW		 730 return found;
731}
732
5eb08b69 733static bool
f2b115e6 734intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 735 int target, int refclk, intel_clock_t *match_clock,
736 intel_clock_t *best_clock)
5eb08b69
ZW		 737{
738 struct drm_device *dev = crtc->dev;
739 intel_clock_t clock;
4547668a 740
5eb08b69
ZW		 741 if (target < 200000) {
742 clock.n = 1;
743 clock.p1 = 2;
744 clock.p2 = 10;
745 clock.m1 = 12;
746 clock.m2 = 9;
747 } else {
748 clock.n = 2;
749 clock.p1 = 1;
750 clock.p2 = 10;
751 clock.m1 = 14;
752 clock.m2 = 8;
753 }
754 intel_clock(dev, refclk, &clock);
755 memcpy(best_clock, &clock, sizeof(intel_clock_t));
756 return true;
757}
758
a4fc5ed6
KP		 759/* DisplayPort has only two frequencies, 162MHz and 270MHz */
760static bool
761intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
a4fc5ed6 764{
5eddb70b
CW		 765 intel_clock_t clock;
766 if (target < 200000) {
767 clock.p1 = 2;
768 clock.p2 = 10;
769 clock.n = 2;
770 clock.m1 = 23;
771 clock.m2 = 8;
772 } else {
773 clock.p1 = 1;
774 clock.p2 = 10;
775 clock.n = 1;
776 clock.m1 = 14;
777 clock.m2 = 2;
778 }
779 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
780 clock.p = (clock.p1 * clock.p2);
781 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
782 clock.vco = 0;
783 memcpy(best_clock, &clock, sizeof(intel_clock_t));
784 return true;
a4fc5ed6
KP		 785}
786
a928d536
PZ		 787static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
788{
789 struct drm_i915_private *dev_priv = dev->dev_private;
790 u32 frame, frame_reg = PIPEFRAME(pipe);
791
792 frame = I915_READ(frame_reg);
793
794 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
795 DRM_DEBUG_KMS("vblank wait timed out\n");
796}
797
9d0498a2
JB		 798/**
799 * intel_wait_for_vblank - wait for vblank on a given pipe
800 * @dev: drm device
801 * @pipe: pipe to wait for
802 *
803 * Wait for vblank to occur on a given pipe. Needed for various bits of
804 * mode setting code.
805 */
806void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 807{
9d0498a2 808 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 809 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 810
a928d536
PZ		 811 if (INTEL_INFO(dev)->gen >= 5) {
812 ironlake_wait_for_vblank(dev, pipe);
813 return;
814 }
815
300387c0
CW		 816 /* Clear existing vblank status. Note this will clear any other
817 * sticky status fields as well.
818 *
819 * This races with i915_driver_irq_handler() with the result
820 * that either function could miss a vblank event. Here it is not
821 * fatal, as we will either wait upon the next vblank interrupt or
822 * timeout. Generally speaking intel_wait_for_vblank() is only
823 * called during modeset at which time the GPU should be idle and
824 * should *not* be performing page flips and thus not waiting on
825 * vblanks...
826 * Currently, the result of us stealing a vblank from the irq
827 * handler is that a single frame will be skipped during swapbuffers.
828 */
829 I915_WRITE(pipestat_reg,
830 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
831
9d0498a2 832 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 833 if (wait_for(I915_READ(pipestat_reg) &
834 PIPE_VBLANK_INTERRUPT_STATUS,
835 50))
9d0498a2
JB		 836 DRM_DEBUG_KMS("vblank wait timed out\n");
837}
838
ab7ad7f6
KP		 839/*
840 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 841 * @dev: drm device
842 * @pipe: pipe to wait for
843 *
844 * After disabling a pipe, we can't wait for vblank in the usual way,
845 * spinning on the vblank interrupt status bit, since we won't actually
846 * see an interrupt when the pipe is disabled.
847 *
ab7ad7f6
KP		 848 * On Gen4 and above:
849 * wait for the pipe register state bit to turn off
850 *
851 * Otherwise:
852 * wait for the display line value to settle (it usually
853 * ends up stopping at the start of the next frame).
58e10eb9 854 *
9d0498a2 855 */
58e10eb9 856void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 857{
858 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 859
860 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 861 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 862
863 /* Wait for the Pipe State to go off */
58e10eb9
CW		 864 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
865 100))
ab7ad7f6
KP		 866 DRM_DEBUG_KMS("pipe_off wait timed out\n");
867 } else {
837ba00f 868 u32 last_line, line_mask;
58e10eb9 869 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 870 unsigned long timeout = jiffies + msecs_to_jiffies(100);
871
837ba00f
PZ		 872 if (IS_GEN2(dev))
873 line_mask = DSL_LINEMASK_GEN2;
874 else
875 line_mask = DSL_LINEMASK_GEN3;
876
ab7ad7f6
KP		 877 /* Wait for the display line to settle */
878 do {
837ba00f 879 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 880 mdelay(5);
837ba00f 881 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 882 time_after(timeout, jiffies));
883 if (time_after(jiffies, timeout))
884 DRM_DEBUG_KMS("pipe_off wait timed out\n");
885 }
79e53945
JB		 886}
887
b24e7179
JB		 888static const char *state_string(bool enabled)
889{
890 return enabled ? "on" : "off";
891}
892
893/* Only for pre-ILK configs */
894static void assert_pll(struct drm_i915_private *dev_priv,
895 enum pipe pipe, bool state)
896{
897 int reg;
898 u32 val;
899 bool cur_state;
900
901 reg = DPLL(pipe);
902 val = I915_READ(reg);
903 cur_state = !!(val & DPLL_VCO_ENABLE);
904 WARN(cur_state != state,
905 "PLL state assertion failure (expected %s, current %s)\n",
906 state_string(state), state_string(cur_state));
907}
908#define assert_pll_enabled(d, p) assert_pll(d, p, true)
909#define assert_pll_disabled(d, p) assert_pll(d, p, false)
910
040484af
JB		 911/* For ILK+ */
912static void assert_pch_pll(struct drm_i915_private *dev_priv,
ee7b9f93 913 struct intel_crtc *intel_crtc, bool state)
040484af
JB		 914{
915 int reg;
916 u32 val;
917 bool cur_state;
918
ee7b9f93
JB		 919 if (!intel_crtc->pch_pll) {
920 WARN(1, "asserting PCH PLL enabled with no PLL\n");
921 return;
922 }
923
d3ccbe86
JB		 924 if (HAS_PCH_CPT(dev_priv->dev)) {
925 u32 pch_dpll;
926
927 pch_dpll = I915_READ(PCH_DPLL_SEL);
928
929 /* Make sure the selected PLL is enabled to the transcoder */
ee7b9f93
JB		 930 WARN(!((pch_dpll >> (4 * intel_crtc->pipe)) & 8),
931 "transcoder %d PLL not enabled\n", intel_crtc->pipe);
d3ccbe86
JB		 932 }
933
ee7b9f93 934 reg = intel_crtc->pch_pll->pll_reg;
040484af
JB		 935 val = I915_READ(reg);
936 cur_state = !!(val & DPLL_VCO_ENABLE);
937 WARN(cur_state != state,
938 "PCH PLL state assertion failure (expected %s, current %s)\n",
939 state_string(state), state_string(cur_state));
940}
941#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
942#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
943
944static void assert_fdi_tx(struct drm_i915_private *dev_priv,
945 enum pipe pipe, bool state)
946{
947 int reg;
948 u32 val;
949 bool cur_state;
950
951 reg = FDI_TX_CTL(pipe);
952 val = I915_READ(reg);
953 cur_state = !!(val & FDI_TX_ENABLE);
954 WARN(cur_state != state,
955 "FDI TX state assertion failure (expected %s, current %s)\n",
956 state_string(state), state_string(cur_state));
957}
958#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
959#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
960
961static void assert_fdi_rx(struct drm_i915_private *dev_priv,
962 enum pipe pipe, bool state)
963{
964 int reg;
965 u32 val;
966 bool cur_state;
967
968 reg = FDI_RX_CTL(pipe);
969 val = I915_READ(reg);
970 cur_state = !!(val & FDI_RX_ENABLE);
971 WARN(cur_state != state,
972 "FDI RX state assertion failure (expected %s, current %s)\n",
973 state_string(state), state_string(cur_state));
974}
975#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
976#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
977
978static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
979 enum pipe pipe)
980{
981 int reg;
982 u32 val;
983
984 /* ILK FDI PLL is always enabled */
985 if (dev_priv->info->gen == 5)
986 return;
987
988 reg = FDI_TX_CTL(pipe);
989 val = I915_READ(reg);
990 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
991}
992
993static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
994 enum pipe pipe)
995{
996 int reg;
997 u32 val;
998
999 reg = FDI_RX_CTL(pipe);
1000 val = I915_READ(reg);
1001 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1002}
1003
ea0760cf
JB		 1004static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1005 enum pipe pipe)
1006{
1007 int pp_reg, lvds_reg;
1008 u32 val;
1009 enum pipe panel_pipe = PIPE_A;
0de3b485 1010 bool locked = true;
ea0760cf
JB		 1011
1012 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1013 pp_reg = PCH_PP_CONTROL;
1014 lvds_reg = PCH_LVDS;
1015 } else {
1016 pp_reg = PP_CONTROL;
1017 lvds_reg = LVDS;
1018 }
1019
1020 val = I915_READ(pp_reg);
1021 if (!(val & PANEL_POWER_ON) ||
1022 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1023 locked = false;
1024
1025 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1026 panel_pipe = PIPE_B;
1027
1028 WARN(panel_pipe == pipe && locked,
1029 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1030 pipe_name(pipe));
ea0760cf
JB		 1031}
1032
b840d907
JB		 1033void assert_pipe(struct drm_i915_private *dev_priv,
1034 enum pipe pipe, bool state)
b24e7179
JB		 1035{
1036 int reg;
1037 u32 val;
63d7bbe9 1038 bool cur_state;
b24e7179 1039
8e636784
DV		 1040 /* if we need the pipe A quirk it must be always on */
1041 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1042 state = true;
1043
b24e7179
JB		 1044 reg = PIPECONF(pipe);
1045 val = I915_READ(reg);
63d7bbe9
JB		 1046 cur_state = !!(val & PIPECONF_ENABLE);
1047 WARN(cur_state != state,
1048 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1049 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1050}
1051
931872fc
CW		 1052static void assert_plane(struct drm_i915_private *dev_priv,
1053 enum plane plane, bool state)
b24e7179
JB		 1054{
1055 int reg;
1056 u32 val;
931872fc 1057 bool cur_state;
b24e7179
JB		 1058
1059 reg = DSPCNTR(plane);
1060 val = I915_READ(reg);
931872fc
CW		 1061 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1062 WARN(cur_state != state,
1063 "plane %c assertion failure (expected %s, current %s)\n",
1064 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1065}
1066
931872fc
CW		 1067#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1068#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1069
b24e7179
JB		 1070static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1071 enum pipe pipe)
1072{
1073 int reg, i;
1074 u32 val;
1075 int cur_pipe;
1076
19ec1358 1077 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1078 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1079 reg = DSPCNTR(pipe);
1080 val = I915_READ(reg);
1081 WARN((val & DISPLAY_PLANE_ENABLE),
1082 "plane %c assertion failure, should be disabled but not\n",
1083 plane_name(pipe));
19ec1358 1084 return;
28c05794 1085 }
19ec1358 1086
b24e7179
JB		 1087 /* Need to check both planes against the pipe */
1088 for (i = 0; i < 2; i++) {
1089 reg = DSPCNTR(i);
1090 val = I915_READ(reg);
1091 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1092 DISPPLANE_SEL_PIPE_SHIFT;
1093 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1094 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1095 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1096 }
1097}
1098
92f2584a
JB		 1099static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1100{
1101 u32 val;
1102 bool enabled;
1103
1104 val = I915_READ(PCH_DREF_CONTROL);
1105 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1106 DREF_SUPERSPREAD_SOURCE_MASK));
1107 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1108}
1109
1110static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1111 enum pipe pipe)
1112{
1113 int reg;
1114 u32 val;
1115 bool enabled;
1116
1117 reg = TRANSCONF(pipe);
1118 val = I915_READ(reg);
1119 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1120 WARN(enabled,
1121 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1122 pipe_name(pipe));
92f2584a
JB		 1123}
1124
4e634389
KP		 1125static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1127{
1128 if ((val & DP_PORT_EN) == 0)
1129 return false;
1130
1131 if (HAS_PCH_CPT(dev_priv->dev)) {
1132 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1133 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1134 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1135 return false;
1136 } else {
1137 if ((val & DP_PIPE_MASK) != (pipe << 30))
1138 return false;
1139 }
1140 return true;
1141}
1142
1519b995
KP		 1143static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1144 enum pipe pipe, u32 val)
1145{
1146 if ((val & PORT_ENABLE) == 0)
1147 return false;
1148
1149 if (HAS_PCH_CPT(dev_priv->dev)) {
1150 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1151 return false;
1152 } else {
1153 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1154 return false;
1155 }
1156 return true;
1157}
1158
1159static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1160 enum pipe pipe, u32 val)
1161{
1162 if ((val & LVDS_PORT_EN) == 0)
1163 return false;
1164
1165 if (HAS_PCH_CPT(dev_priv->dev)) {
1166 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1167 return false;
1168 } else {
1169 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1170 return false;
1171 }
1172 return true;
1173}
1174
1175static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1176 enum pipe pipe, u32 val)
1177{
1178 if ((val & ADPA_DAC_ENABLE) == 0)
1179 return false;
1180 if (HAS_PCH_CPT(dev_priv->dev)) {
1181 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1182 return false;
1183 } else {
1184 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1185 return false;
1186 }
1187 return true;
1188}
1189
291906f1 1190static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1191 enum pipe pipe, int reg, u32 port_sel)
291906f1 1192{
47a05eca 1193 u32 val = I915_READ(reg);
4e634389 1194 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1195 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1196 reg, pipe_name(pipe));
291906f1
JB		 1197}
1198
1199static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1200 enum pipe pipe, int reg)
1201{
47a05eca 1202 u32 val = I915_READ(reg);
1519b995 1203 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1204 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1205 reg, pipe_name(pipe));
291906f1
JB		 1206}
1207
1208static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1209 enum pipe pipe)
1210{
1211 int reg;
1212 u32 val;
291906f1 1213
f0575e92
KP		 1214 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1215 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1216 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1217
1218 reg = PCH_ADPA;
1219 val = I915_READ(reg);
1519b995 1220 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1221 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1222 pipe_name(pipe));
291906f1
JB		 1223
1224 reg = PCH_LVDS;
1225 val = I915_READ(reg);
1519b995 1226 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1227 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1228 pipe_name(pipe));
291906f1
JB		 1229
1230 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1231 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1232 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1233}
1234
63d7bbe9
JB		 1235/**
1236 * intel_enable_pll - enable a PLL
1237 * @dev_priv: i915 private structure
1238 * @pipe: pipe PLL to enable
1239 *
1240 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1241 * make sure the PLL reg is writable first though, since the panel write
1242 * protect mechanism may be enabled.
1243 *
1244 * Note! This is for pre-ILK only.
1245 */
1246static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1247{
1248 int reg;
1249 u32 val;
1250
1251 /* No really, not for ILK+ */
1252 BUG_ON(dev_priv->info->gen >= 5);
1253
1254 /* PLL is protected by panel, make sure we can write it */
1255 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1256 assert_panel_unlocked(dev_priv, pipe);
1257
1258 reg = DPLL(pipe);
1259 val = I915_READ(reg);
1260 val |= DPLL_VCO_ENABLE;
1261
1262 /* We do this three times for luck */
1263 I915_WRITE(reg, val);
1264 POSTING_READ(reg);
1265 udelay(150); /* wait for warmup */
1266 I915_WRITE(reg, val);
1267 POSTING_READ(reg);
1268 udelay(150); /* wait for warmup */
1269 I915_WRITE(reg, val);
1270 POSTING_READ(reg);
1271 udelay(150); /* wait for warmup */
1272}
1273
1274/**
1275 * intel_disable_pll - disable a PLL
1276 * @dev_priv: i915 private structure
1277 * @pipe: pipe PLL to disable
1278 *
1279 * Disable the PLL for @pipe, making sure the pipe is off first.
1280 *
1281 * Note! This is for pre-ILK only.
1282 */
1283static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1284{
1285 int reg;
1286 u32 val;
1287
1288 /* Don't disable pipe A or pipe A PLLs if needed */
1289 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1290 return;
1291
1292 /* Make sure the pipe isn't still relying on us */
1293 assert_pipe_disabled(dev_priv, pipe);
1294
1295 reg = DPLL(pipe);
1296 val = I915_READ(reg);
1297 val &= ~DPLL_VCO_ENABLE;
1298 I915_WRITE(reg, val);
1299 POSTING_READ(reg);
1300}
1301
a416edef
ED		 1302/* SBI access */
1303static void
1304intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1305{
1306 unsigned long flags;
1307
1308 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1309 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1310 100)) {
1311 DRM_ERROR("timeout waiting for SBI to become ready\n");
1312 goto out_unlock;
1313 }
1314
1315 I915_WRITE(SBI_ADDR,
1316 (reg << 16));
1317 I915_WRITE(SBI_DATA,
1318 value);
1319 I915_WRITE(SBI_CTL_STAT,
1320 SBI_BUSY |
1321 SBI_CTL_OP_CRWR);
1322
1323 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1324 100)) {
1325 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1326 goto out_unlock;
1327 }
1328
1329out_unlock:
1330 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1331}
1332
1333static u32
1334intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1335{
1336 unsigned long flags;
1337 u32 value;
1338
1339 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1340 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1341 100)) {
1342 DRM_ERROR("timeout waiting for SBI to become ready\n");
1343 goto out_unlock;
1344 }
1345
1346 I915_WRITE(SBI_ADDR,
1347 (reg << 16));
1348 I915_WRITE(SBI_CTL_STAT,
1349 SBI_BUSY |
1350 SBI_CTL_OP_CRRD);
1351
1352 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1353 100)) {
1354 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1355 goto out_unlock;
1356 }
1357
1358 value = I915_READ(SBI_DATA);
1359
1360out_unlock:
1361 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1362 return value;
1363}
1364
92f2584a
JB		 1365/**
1366 * intel_enable_pch_pll - enable PCH PLL
1367 * @dev_priv: i915 private structure
1368 * @pipe: pipe PLL to enable
1369 *
1370 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1371 * drives the transcoder clock.
1372 */
ee7b9f93 1373static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1374{
ee7b9f93
JB		 1375 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1376 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a
JB		 1377 int reg;
1378 u32 val;
1379
1380 /* PCH only available on ILK+ */
1381 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1382 BUG_ON(pll == NULL);
1383 BUG_ON(pll->refcount == 0);
1384
1385 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1386 pll->pll_reg, pll->active, pll->on,
1387 intel_crtc->base.base.id);
92f2584a
JB		 1388
1389 /* PCH refclock must be enabled first */
1390 assert_pch_refclk_enabled(dev_priv);
1391
ee7b9f93
JB		 1392 if (pll->active++ && pll->on) {
1393 assert_pch_pll_enabled(dev_priv, intel_crtc);
1394 return;
1395 }
1396
1397 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1398
1399 reg = pll->pll_reg;
92f2584a
JB		 1400 val = I915_READ(reg);
1401 val |= DPLL_VCO_ENABLE;
1402 I915_WRITE(reg, val);
1403 POSTING_READ(reg);
1404 udelay(200);
ee7b9f93
JB		 1405
1406 pll->on = true;
92f2584a
JB		 1407}
1408
ee7b9f93 1409static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1410{
ee7b9f93
JB		 1411 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1412 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1413 int reg;
ee7b9f93 1414 u32 val;
4c609cb8 1415
92f2584a
JB		 1416 /* PCH only available on ILK+ */
1417 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1418 if (pll == NULL)
1419 return;
92f2584a 1420
ee7b9f93 1421 BUG_ON(pll->refcount == 0);
7a419866 1422
ee7b9f93
JB		 1423 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1424 pll->pll_reg, pll->active, pll->on,
1425 intel_crtc->base.base.id);
7a419866 1426
ee7b9f93
JB		 1427 BUG_ON(pll->active == 0);
1428 if (--pll->active) {
1429 assert_pch_pll_enabled(dev_priv, intel_crtc);
7a419866 1430 return;
ee7b9f93
JB		 1431 }
1432
1433 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1434
1435 /* Make sure transcoder isn't still depending on us */
1436 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1437
ee7b9f93 1438 reg = pll->pll_reg;
92f2584a
JB		 1439 val = I915_READ(reg);
1440 val &= ~DPLL_VCO_ENABLE;
1441 I915_WRITE(reg, val);
1442 POSTING_READ(reg);
1443 udelay(200);
ee7b9f93
JB		 1444
1445 pll->on = false;
92f2584a
JB		 1446}
1447
040484af
JB		 1448static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1449 enum pipe pipe)
1450{
1451 int reg;
5f7f726d 1452 u32 val, pipeconf_val;
7c26e5c6 1453 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1454
1455 /* PCH only available on ILK+ */
1456 BUG_ON(dev_priv->info->gen < 5);
1457
1458 /* Make sure PCH DPLL is enabled */
ee7b9f93 1459 assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
040484af
JB		 1460
1461 /* FDI must be feeding us bits for PCH ports */
1462 assert_fdi_tx_enabled(dev_priv, pipe);
1463 assert_fdi_rx_enabled(dev_priv, pipe);
1464
1465 reg = TRANSCONF(pipe);
1466 val = I915_READ(reg);
5f7f726d 1467 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1468
1469 if (HAS_PCH_IBX(dev_priv->dev)) {
1470 /*
1471 * make the BPC in transcoder be consistent with
1472 * that in pipeconf reg.
1473 */
1474 val &= ~PIPE_BPC_MASK;
5f7f726d 1475 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1476 }
5f7f726d
PZ		 1477
1478 val &= ~TRANS_INTERLACE_MASK;
1479 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1480 if (HAS_PCH_IBX(dev_priv->dev) &&
1481 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1482 val |= TRANS_LEGACY_INTERLACED_ILK;
1483 else
1484 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1485 else
1486 val |= TRANS_PROGRESSIVE;
1487
040484af
JB		 1488 I915_WRITE(reg, val | TRANS_ENABLE);
1489 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1490 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1491}
1492
1493static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1494 enum pipe pipe)
1495{
1496 int reg;
1497 u32 val;
1498
1499 /* FDI relies on the transcoder */
1500 assert_fdi_tx_disabled(dev_priv, pipe);
1501 assert_fdi_rx_disabled(dev_priv, pipe);
1502
291906f1
JB		 1503 /* Ports must be off as well */
1504 assert_pch_ports_disabled(dev_priv, pipe);
1505
040484af
JB		 1506 reg = TRANSCONF(pipe);
1507 val = I915_READ(reg);
1508 val &= ~TRANS_ENABLE;
1509 I915_WRITE(reg, val);
1510 /* wait for PCH transcoder off, transcoder state */
1511 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1512 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1513}
1514
b24e7179 1515/**
309cfea8 1516 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1517 * @dev_priv: i915 private structure
1518 * @pipe: pipe to enable
040484af 1519 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1520 *
1521 * Enable @pipe, making sure that various hardware specific requirements
1522 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1523 *
1524 * @pipe should be %PIPE_A or %PIPE_B.
1525 *
1526 * Will wait until the pipe is actually running (i.e. first vblank) before
1527 * returning.
1528 */
040484af
JB		 1529static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1530 bool pch_port)
b24e7179
JB		 1531{
1532 int reg;
1533 u32 val;
1534
1535 /*
1536 * A pipe without a PLL won't actually be able to drive bits from
1537 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1538 * need the check.
1539 */
1540 if (!HAS_PCH_SPLIT(dev_priv->dev))
1541 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1542 else {
1543 if (pch_port) {
1544 /* if driving the PCH, we need FDI enabled */
1545 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1546 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1547 }
1548 /* FIXME: assert CPU port conditions for SNB+ */
1549 }
b24e7179
JB		 1550
1551 reg = PIPECONF(pipe);
1552 val = I915_READ(reg);
00d70b15
CW		 1553 if (val & PIPECONF_ENABLE)
1554 return;
1555
1556 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1557 intel_wait_for_vblank(dev_priv->dev, pipe);
1558}
1559
1560/**
309cfea8 1561 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1562 * @dev_priv: i915 private structure
1563 * @pipe: pipe to disable
1564 *
1565 * Disable @pipe, making sure that various hardware specific requirements
1566 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1567 *
1568 * @pipe should be %PIPE_A or %PIPE_B.
1569 *
1570 * Will wait until the pipe has shut down before returning.
1571 */
1572static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1573 enum pipe pipe)
1574{
1575 int reg;
1576 u32 val;
1577
1578 /*
1579 * Make sure planes won't keep trying to pump pixels to us,
1580 * or we might hang the display.
1581 */
1582 assert_planes_disabled(dev_priv, pipe);
1583
1584 /* Don't disable pipe A or pipe A PLLs if needed */
1585 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1586 return;
1587
1588 reg = PIPECONF(pipe);
1589 val = I915_READ(reg);
00d70b15
CW		 1590 if ((val & PIPECONF_ENABLE) == 0)
1591 return;
1592
1593 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1594 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1595}
1596
d74362c9
KP		 1597/*
1598 * Plane regs are double buffered, going from enabled->disabled needs a
1599 * trigger in order to latch. The display address reg provides this.
1600 */
6f1d69b0 1601void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1602 enum plane plane)
1603{
1604 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1605 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1606}
1607
b24e7179
JB		 1608/**
1609 * intel_enable_plane - enable a display plane on a given pipe
1610 * @dev_priv: i915 private structure
1611 * @plane: plane to enable
1612 * @pipe: pipe being fed
1613 *
1614 * Enable @plane on @pipe, making sure that @pipe is running first.
1615 */
1616static void intel_enable_plane(struct drm_i915_private *dev_priv,
1617 enum plane plane, enum pipe pipe)
1618{
1619 int reg;
1620 u32 val;
1621
1622 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1623 assert_pipe_enabled(dev_priv, pipe);
1624
1625 reg = DSPCNTR(plane);
1626 val = I915_READ(reg);
00d70b15
CW		 1627 if (val & DISPLAY_PLANE_ENABLE)
1628 return;
1629
1630 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1631 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1632 intel_wait_for_vblank(dev_priv->dev, pipe);
1633}
1634
b24e7179
JB		 1635/**
1636 * intel_disable_plane - disable a display plane
1637 * @dev_priv: i915 private structure
1638 * @plane: plane to disable
1639 * @pipe: pipe consuming the data
1640 *
1641 * Disable @plane; should be an independent operation.
1642 */
1643static void intel_disable_plane(struct drm_i915_private *dev_priv,
1644 enum plane plane, enum pipe pipe)
1645{
1646 int reg;
1647 u32 val;
1648
1649 reg = DSPCNTR(plane);
1650 val = I915_READ(reg);
00d70b15
CW		 1651 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1652 return;
1653
1654 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1655 intel_flush_display_plane(dev_priv, plane);
1656 intel_wait_for_vblank(dev_priv->dev, pipe);
1657}
1658
47a05eca 1659static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1660 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1661{
1662 u32 val = I915_READ(reg);
4e634389 1663 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1664 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1665 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1666 }
47a05eca
JB		 1667}
1668
1669static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1670 enum pipe pipe, int reg)
1671{
1672 u32 val = I915_READ(reg);
1519b995 1673 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1674 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1675 reg, pipe);
47a05eca 1676 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1677 }
47a05eca
JB		 1678}
1679
1680/* Disable any ports connected to this transcoder */
1681static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1682 enum pipe pipe)
1683{
1684 u32 reg, val;
1685
1686 val = I915_READ(PCH_PP_CONTROL);
1687 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1688
f0575e92
KP		 1689 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1690 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1691 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1692
1693 reg = PCH_ADPA;
1694 val = I915_READ(reg);
1519b995 1695 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1696 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1697
1698 reg = PCH_LVDS;
1699 val = I915_READ(reg);
1519b995
KP		 1700 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1701 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1702 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1703 POSTING_READ(reg);
1704 udelay(100);
1705 }
1706
1707 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1708 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1709 disable_pch_hdmi(dev_priv, pipe, HDMID);
1710}
1711
127bd2ac 1712int
48b956c5 1713intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1714 struct drm_i915_gem_object *obj,
919926ae 1715 struct intel_ring_buffer *pipelined)
6b95a207 1716{
ce453d81 1717 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1718 u32 alignment;
1719 int ret;
1720
05394f39 1721 switch (obj->tiling_mode) {
6b95a207 1722 case I915_TILING_NONE:
534843da
CW		 1723 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1724 alignment = 128 * 1024;
a6c45cf0 1725 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1726 alignment = 4 * 1024;
1727 else
1728 alignment = 64 * 1024;
6b95a207
KH		 1729 break;
1730 case I915_TILING_X:
1731 /* pin() will align the object as required by fence */
1732 alignment = 0;
1733 break;
1734 case I915_TILING_Y:
1735 /* FIXME: Is this true? */
1736 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1737 return -EINVAL;
1738 default:
1739 BUG();
1740 }
1741
ce453d81 1742 dev_priv->mm.interruptible = false;
2da3b9b9 1743 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1744 if (ret)
ce453d81 1745 goto err_interruptible;
6b95a207
KH		 1746
1747 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1748 * fence, whereas 965+ only requires a fence if using
1749 * framebuffer compression. For simplicity, we always install
1750 * a fence as the cost is not that onerous.
1751 */
06d98131 1752 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1753 if (ret)
1754 goto err_unpin;
1690e1eb 1755
9a5a53b3 1756 i915_gem_object_pin_fence(obj);
6b95a207 1757
ce453d81 1758 dev_priv->mm.interruptible = true;
6b95a207 1759 return 0;
48b956c5
CW		 1760
1761err_unpin:
1762 i915_gem_object_unpin(obj);
ce453d81
CW		 1763err_interruptible:
1764 dev_priv->mm.interruptible = true;
48b956c5 1765 return ret;
6b95a207
KH		 1766}
1767
1690e1eb
CW		 1768void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1769{
1770 i915_gem_object_unpin_fence(obj);
1771 i915_gem_object_unpin(obj);
1772}
1773
17638cd6
JB		 1774static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1775 int x, int y)
81255565
JB		 1776{
1777 struct drm_device *dev = crtc->dev;
1778 struct drm_i915_private *dev_priv = dev->dev_private;
1779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1780 struct intel_framebuffer *intel_fb;
05394f39 1781 struct drm_i915_gem_object *obj;
81255565
JB		 1782 int plane = intel_crtc->plane;
1783 unsigned long Start, Offset;
81255565 1784 u32 dspcntr;
5eddb70b 1785 u32 reg;
81255565
JB		 1786
1787 switch (plane) {
1788 case 0:
1789 case 1:
1790 break;
1791 default:
1792 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1793 return -EINVAL;
1794 }
1795
1796 intel_fb = to_intel_framebuffer(fb);
1797 obj = intel_fb->obj;
81255565 1798
5eddb70b
CW		 1799 reg = DSPCNTR(plane);
1800 dspcntr = I915_READ(reg);
81255565
JB		 1801 /* Mask out pixel format bits in case we change it */
1802 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1803 switch (fb->bits_per_pixel) {
1804 case 8:
1805 dspcntr |= DISPPLANE_8BPP;
1806 break;
1807 case 16:
1808 if (fb->depth == 15)
1809 dspcntr |= DISPPLANE_15_16BPP;
1810 else
1811 dspcntr |= DISPPLANE_16BPP;
1812 break;
1813 case 24:
1814 case 32:
1815 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1816 break;
1817 default:
17638cd6 1818 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 1819 return -EINVAL;
1820 }
a6c45cf0 1821 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1822 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1823 dspcntr |= DISPPLANE_TILED;
1824 else
1825 dspcntr &= ~DISPPLANE_TILED;
1826 }
1827
5eddb70b 1828 I915_WRITE(reg, dspcntr);
81255565 1829
05394f39 1830 Start = obj->gtt_offset;
01f2c773 1831 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1832
4e6cfefc 1833 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 1834 Start, Offset, x, y, fb->pitches[0]);
1835 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1836 if (INTEL_INFO(dev)->gen >= 4) {
446f2545 1837 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
5eddb70b
CW		 1838 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1839 I915_WRITE(DSPADDR(plane), Offset);
1840 } else
1841 I915_WRITE(DSPADDR(plane), Start + Offset);
1842 POSTING_READ(reg);
81255565 1843
17638cd6
JB		 1844 return 0;
1845}
1846
1847static int ironlake_update_plane(struct drm_crtc *crtc,
1848 struct drm_framebuffer *fb, int x, int y)
1849{
1850 struct drm_device *dev = crtc->dev;
1851 struct drm_i915_private *dev_priv = dev->dev_private;
1852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1853 struct intel_framebuffer *intel_fb;
1854 struct drm_i915_gem_object *obj;
1855 int plane = intel_crtc->plane;
1856 unsigned long Start, Offset;
1857 u32 dspcntr;
1858 u32 reg;
1859
1860 switch (plane) {
1861 case 0:
1862 case 1:
27f8227b 1863 case 2:
17638cd6
JB		 1864 break;
1865 default:
1866 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1867 return -EINVAL;
1868 }
1869
1870 intel_fb = to_intel_framebuffer(fb);
1871 obj = intel_fb->obj;
1872
1873 reg = DSPCNTR(plane);
1874 dspcntr = I915_READ(reg);
1875 /* Mask out pixel format bits in case we change it */
1876 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1877 switch (fb->bits_per_pixel) {
1878 case 8:
1879 dspcntr |= DISPPLANE_8BPP;
1880 break;
1881 case 16:
1882 if (fb->depth != 16)
1883 return -EINVAL;
1884
1885 dspcntr |= DISPPLANE_16BPP;
1886 break;
1887 case 24:
1888 case 32:
1889 if (fb->depth == 24)
1890 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1891 else if (fb->depth == 30)
1892 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1893 else
1894 return -EINVAL;
1895 break;
1896 default:
1897 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1898 return -EINVAL;
1899 }
1900
1901 if (obj->tiling_mode != I915_TILING_NONE)
1902 dspcntr |= DISPPLANE_TILED;
1903 else
1904 dspcntr &= ~DISPPLANE_TILED;
1905
1906 /* must disable */
1907 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1908
1909 I915_WRITE(reg, dspcntr);
1910
1911 Start = obj->gtt_offset;
01f2c773 1912 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 1913
1914 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 1915 Start, Offset, x, y, fb->pitches[0]);
1916 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
446f2545 1917 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
17638cd6
JB		 1918 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1919 I915_WRITE(DSPADDR(plane), Offset);
1920 POSTING_READ(reg);
1921
1922 return 0;
1923}
1924
1925/* Assume fb object is pinned & idle & fenced and just update base pointers */
1926static int
1927intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1928 int x, int y, enum mode_set_atomic state)
1929{
1930 struct drm_device *dev = crtc->dev;
1931 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 1932
6b8e6ed0
CW		 1933 if (dev_priv->display.disable_fbc)
1934 dev_priv->display.disable_fbc(dev);
3dec0095 1935 intel_increase_pllclock(crtc);
81255565 1936
6b8e6ed0 1937 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 1938}
1939
14667a4b
CW		 1940static int
1941intel_finish_fb(struct drm_framebuffer *old_fb)
1942{
1943 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1944 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1945 bool was_interruptible = dev_priv->mm.interruptible;
1946 int ret;
1947
1948 wait_event(dev_priv->pending_flip_queue,
1949 atomic_read(&dev_priv->mm.wedged) ||
1950 atomic_read(&obj->pending_flip) == 0);
1951
1952 /* Big Hammer, we also need to ensure that any pending
1953 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1954 * current scanout is retired before unpinning the old
1955 * framebuffer.
1956 *
1957 * This should only fail upon a hung GPU, in which case we
1958 * can safely continue.
1959 */
1960 dev_priv->mm.interruptible = false;
1961 ret = i915_gem_object_finish_gpu(obj);
1962 dev_priv->mm.interruptible = was_interruptible;
1963
1964 return ret;
1965}
1966
5c3b82e2 1967static int
3c4fdcfb
KH		 1968intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1969 struct drm_framebuffer *old_fb)
79e53945
JB		 1970{
1971 struct drm_device *dev = crtc->dev;
6b8e6ed0 1972 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 1973 struct drm_i915_master_private *master_priv;
1974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 1975 int ret;
79e53945
JB		 1976
1977 /* no fb bound */
1978 if (!crtc->fb) {
a5071c2f 1979 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 1980 return 0;
1981 }
1982
5826eca5
ED		 1983 if(intel_crtc->plane > dev_priv->num_pipe) {
1984 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
1985 intel_crtc->plane,
1986 dev_priv->num_pipe);
5c3b82e2 1987 return -EINVAL;
79e53945
JB		 1988 }
1989
5c3b82e2 1990 mutex_lock(&dev->struct_mutex);
265db958
CW		 1991 ret = intel_pin_and_fence_fb_obj(dev,
1992 to_intel_framebuffer(crtc->fb)->obj,
919926ae 1993 NULL);
5c3b82e2
CW		 1994 if (ret != 0) {
1995 mutex_unlock(&dev->struct_mutex);
a5071c2f 1996 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 1997 return ret;
1998 }
79e53945 1999
14667a4b
CW		 2000 if (old_fb)
2001 intel_finish_fb(old_fb);
265db958 2002
6b8e6ed0 2003 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
4e6cfefc 2004 if (ret) {
1690e1eb 2005 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2006 mutex_unlock(&dev->struct_mutex);
a5071c2f 2007 DRM_ERROR("failed to update base address\n");
4e6cfefc 2008 return ret;
79e53945 2009 }
3c4fdcfb 2010
b7f1de28
CW		 2011 if (old_fb) {
2012 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2013 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2014 }
652c393a 2015
6b8e6ed0 2016 intel_update_fbc(dev);
5c3b82e2 2017 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2018
2019 if (!dev->primary->master)
5c3b82e2 2020 return 0;
79e53945
JB		 2021
2022 master_priv = dev->primary->master->driver_priv;
2023 if (!master_priv->sarea_priv)
5c3b82e2 2024 return 0;
79e53945 2025
265db958 2026 if (intel_crtc->pipe) {
79e53945
JB		 2027 master_priv->sarea_priv->pipeB_x = x;
2028 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2029 } else {
2030 master_priv->sarea_priv->pipeA_x = x;
2031 master_priv->sarea_priv->pipeA_y = y;
79e53945 2032 }
5c3b82e2
CW		 2033
2034 return 0;
79e53945
JB		 2035}
2036
5eddb70b 2037static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2038{
2039 struct drm_device *dev = crtc->dev;
2040 struct drm_i915_private *dev_priv = dev->dev_private;
2041 u32 dpa_ctl;
2042
28c97730 2043 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2044 dpa_ctl = I915_READ(DP_A);
2045 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2046
2047 if (clock < 200000) {
2048 u32 temp;
2049 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2050 /* workaround for 160Mhz:
2051 1) program 0x4600c bits 15:0 = 0x8124
2052 2) program 0x46010 bit 0 = 1
2053 3) program 0x46034 bit 24 = 1
2054 4) program 0x64000 bit 14 = 1
2055 */
2056 temp = I915_READ(0x4600c);
2057 temp &= 0xffff0000;
2058 I915_WRITE(0x4600c, temp | 0x8124);
2059
2060 temp = I915_READ(0x46010);
2061 I915_WRITE(0x46010, temp | 1);
2062
2063 temp = I915_READ(0x46034);
2064 I915_WRITE(0x46034, temp | (1 << 24));
2065 } else {
2066 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2067 }
2068 I915_WRITE(DP_A, dpa_ctl);
2069
5eddb70b 2070 POSTING_READ(DP_A);
32f9d658
ZW		 2071 udelay(500);
2072}
2073
5e84e1a4
ZW		 2074static void intel_fdi_normal_train(struct drm_crtc *crtc)
2075{
2076 struct drm_device *dev = crtc->dev;
2077 struct drm_i915_private *dev_priv = dev->dev_private;
2078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2079 int pipe = intel_crtc->pipe;
2080 u32 reg, temp;
2081
2082 /* enable normal train */
2083 reg = FDI_TX_CTL(pipe);
2084 temp = I915_READ(reg);
61e499bf 2085 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2086 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2087 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2088 } else {
2089 temp &= ~FDI_LINK_TRAIN_NONE;
2090 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2091 }
5e84e1a4
ZW		 2092 I915_WRITE(reg, temp);
2093
2094 reg = FDI_RX_CTL(pipe);
2095 temp = I915_READ(reg);
2096 if (HAS_PCH_CPT(dev)) {
2097 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2098 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2099 } else {
2100 temp &= ~FDI_LINK_TRAIN_NONE;
2101 temp |= FDI_LINK_TRAIN_NONE;
2102 }
2103 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2104
2105 /* wait one idle pattern time */
2106 POSTING_READ(reg);
2107 udelay(1000);
357555c0
JB		 2108
2109 /* IVB wants error correction enabled */
2110 if (IS_IVYBRIDGE(dev))
2111 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2112 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2113}
2114
291427f5
JB		 2115static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2116{
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2118 u32 flags = I915_READ(SOUTH_CHICKEN1);
2119
2120 flags |= FDI_PHASE_SYNC_OVR(pipe);
2121 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2122 flags |= FDI_PHASE_SYNC_EN(pipe);
2123 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2124 POSTING_READ(SOUTH_CHICKEN1);
2125}
2126
8db9d77b
ZW		 2127/* The FDI link training functions for ILK/Ibexpeak. */
2128static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2129{
2130 struct drm_device *dev = crtc->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133 int pipe = intel_crtc->pipe;
0fc932b8 2134 int plane = intel_crtc->plane;
5eddb70b 2135 u32 reg, temp, tries;
8db9d77b 2136
0fc932b8
JB		 2137 /* FDI needs bits from pipe & plane first */
2138 assert_pipe_enabled(dev_priv, pipe);
2139 assert_plane_enabled(dev_priv, plane);
2140
e1a44743
AJ		 2141 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2142 for train result */
5eddb70b
CW		 2143 reg = FDI_RX_IMR(pipe);
2144 temp = I915_READ(reg);
e1a44743
AJ		 2145 temp &= ~FDI_RX_SYMBOL_LOCK;
2146 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2147 I915_WRITE(reg, temp);
2148 I915_READ(reg);
e1a44743
AJ		 2149 udelay(150);
2150
8db9d77b 2151 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2152 reg = FDI_TX_CTL(pipe);
2153 temp = I915_READ(reg);
77ffb597
AJ		 2154 temp &= ~(7 << 19);
2155 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2156 temp &= ~FDI_LINK_TRAIN_NONE;
2157 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2158 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2159
5eddb70b
CW		 2160 reg = FDI_RX_CTL(pipe);
2161 temp = I915_READ(reg);
8db9d77b
ZW		 2162 temp &= ~FDI_LINK_TRAIN_NONE;
2163 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2164 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2165
2166 POSTING_READ(reg);
8db9d77b
ZW		 2167 udelay(150);
2168
5b2adf89 2169 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2170 if (HAS_PCH_IBX(dev)) {
2171 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2172 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2173 FDI_RX_PHASE_SYNC_POINTER_EN);
2174 }
5b2adf89 2175
5eddb70b 2176 reg = FDI_RX_IIR(pipe);
e1a44743 2177 for (tries = 0; tries < 5; tries++) {
5eddb70b 2178 temp = I915_READ(reg);
8db9d77b
ZW		 2179 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2180
2181 if ((temp & FDI_RX_BIT_LOCK)) {
2182 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2183 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2184 break;
2185 }
8db9d77b 2186 }
e1a44743 2187 if (tries == 5)
5eddb70b 2188 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2189
2190 /* Train 2 */
5eddb70b
CW		 2191 reg = FDI_TX_CTL(pipe);
2192 temp = I915_READ(reg);
8db9d77b
ZW		 2193 temp &= ~FDI_LINK_TRAIN_NONE;
2194 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2195 I915_WRITE(reg, temp);
8db9d77b 2196
5eddb70b
CW		 2197 reg = FDI_RX_CTL(pipe);
2198 temp = I915_READ(reg);
8db9d77b
ZW		 2199 temp &= ~FDI_LINK_TRAIN_NONE;
2200 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2201 I915_WRITE(reg, temp);
8db9d77b 2202
5eddb70b
CW		 2203 POSTING_READ(reg);
2204 udelay(150);
8db9d77b 2205
5eddb70b 2206 reg = FDI_RX_IIR(pipe);
e1a44743 2207 for (tries = 0; tries < 5; tries++) {
5eddb70b 2208 temp = I915_READ(reg);
8db9d77b
ZW		 2209 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2210
2211 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2212 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2213 DRM_DEBUG_KMS("FDI train 2 done.\n");
2214 break;
2215 }
8db9d77b 2216 }
e1a44743 2217 if (tries == 5)
5eddb70b 2218 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2219
2220 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2221
8db9d77b
ZW		 2222}
2223
0206e353 2224static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2225 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2226 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2227 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2228 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2229};
2230
2231/* The FDI link training functions for SNB/Cougarpoint. */
2232static void gen6_fdi_link_train(struct drm_crtc *crtc)
2233{
2234 struct drm_device *dev = crtc->dev;
2235 struct drm_i915_private *dev_priv = dev->dev_private;
2236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2237 int pipe = intel_crtc->pipe;
fa37d39e 2238 u32 reg, temp, i, retry;
8db9d77b 2239
e1a44743
AJ		 2240 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2241 for train result */
5eddb70b
CW		 2242 reg = FDI_RX_IMR(pipe);
2243 temp = I915_READ(reg);
e1a44743
AJ		 2244 temp &= ~FDI_RX_SYMBOL_LOCK;
2245 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2246 I915_WRITE(reg, temp);
2247
2248 POSTING_READ(reg);
e1a44743
AJ		 2249 udelay(150);
2250
8db9d77b 2251 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2252 reg = FDI_TX_CTL(pipe);
2253 temp = I915_READ(reg);
77ffb597
AJ		 2254 temp &= ~(7 << 19);
2255 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2256 temp &= ~FDI_LINK_TRAIN_NONE;
2257 temp |= FDI_LINK_TRAIN_PATTERN_1;
2258 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2259 /* SNB-B */
2260 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2261 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2262
5eddb70b
CW		 2263 reg = FDI_RX_CTL(pipe);
2264 temp = I915_READ(reg);
8db9d77b
ZW		 2265 if (HAS_PCH_CPT(dev)) {
2266 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2267 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2268 } else {
2269 temp &= ~FDI_LINK_TRAIN_NONE;
2270 temp |= FDI_LINK_TRAIN_PATTERN_1;
2271 }
5eddb70b
CW		 2272 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2273
2274 POSTING_READ(reg);
8db9d77b
ZW		 2275 udelay(150);
2276
291427f5
JB		 2277 if (HAS_PCH_CPT(dev))
2278 cpt_phase_pointer_enable(dev, pipe);
2279
0206e353 2280 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2281 reg = FDI_TX_CTL(pipe);
2282 temp = I915_READ(reg);
8db9d77b
ZW		 2283 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2284 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2285 I915_WRITE(reg, temp);
2286
2287 POSTING_READ(reg);
8db9d77b
ZW		 2288 udelay(500);
2289
fa37d39e
SP		 2290 for (retry = 0; retry < 5; retry++) {
2291 reg = FDI_RX_IIR(pipe);
2292 temp = I915_READ(reg);
2293 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2294 if (temp & FDI_RX_BIT_LOCK) {
2295 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2296 DRM_DEBUG_KMS("FDI train 1 done.\n");
2297 break;
2298 }
2299 udelay(50);
8db9d77b 2300 }
fa37d39e
SP		 2301 if (retry < 5)
2302 break;
8db9d77b
ZW		 2303 }
2304 if (i == 4)
5eddb70b 2305 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2306
2307 /* Train 2 */
5eddb70b
CW		 2308 reg = FDI_TX_CTL(pipe);
2309 temp = I915_READ(reg);
8db9d77b
ZW		 2310 temp &= ~FDI_LINK_TRAIN_NONE;
2311 temp |= FDI_LINK_TRAIN_PATTERN_2;
2312 if (IS_GEN6(dev)) {
2313 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2314 /* SNB-B */
2315 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2316 }
5eddb70b 2317 I915_WRITE(reg, temp);
8db9d77b 2318
5eddb70b
CW		 2319 reg = FDI_RX_CTL(pipe);
2320 temp = I915_READ(reg);
8db9d77b
ZW		 2321 if (HAS_PCH_CPT(dev)) {
2322 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2323 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2324 } else {
2325 temp &= ~FDI_LINK_TRAIN_NONE;
2326 temp |= FDI_LINK_TRAIN_PATTERN_2;
2327 }
5eddb70b
CW		 2328 I915_WRITE(reg, temp);
2329
2330 POSTING_READ(reg);
8db9d77b
ZW		 2331 udelay(150);
2332
0206e353 2333 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2334 reg = FDI_TX_CTL(pipe);
2335 temp = I915_READ(reg);
8db9d77b
ZW		 2336 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2337 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2338 I915_WRITE(reg, temp);
2339
2340 POSTING_READ(reg);
8db9d77b
ZW		 2341 udelay(500);
2342
fa37d39e
SP		 2343 for (retry = 0; retry < 5; retry++) {
2344 reg = FDI_RX_IIR(pipe);
2345 temp = I915_READ(reg);
2346 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2347 if (temp & FDI_RX_SYMBOL_LOCK) {
2348 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2349 DRM_DEBUG_KMS("FDI train 2 done.\n");
2350 break;
2351 }
2352 udelay(50);
8db9d77b 2353 }
fa37d39e
SP		 2354 if (retry < 5)
2355 break;
8db9d77b
ZW		 2356 }
2357 if (i == 4)
5eddb70b 2358 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2359
2360 DRM_DEBUG_KMS("FDI train done.\n");
2361}
2362
357555c0
JB		 2363/* Manual link training for Ivy Bridge A0 parts */
2364static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2365{
2366 struct drm_device *dev = crtc->dev;
2367 struct drm_i915_private *dev_priv = dev->dev_private;
2368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2369 int pipe = intel_crtc->pipe;
2370 u32 reg, temp, i;
2371
2372 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2373 for train result */
2374 reg = FDI_RX_IMR(pipe);
2375 temp = I915_READ(reg);
2376 temp &= ~FDI_RX_SYMBOL_LOCK;
2377 temp &= ~FDI_RX_BIT_LOCK;
2378 I915_WRITE(reg, temp);
2379
2380 POSTING_READ(reg);
2381 udelay(150);
2382
2383 /* enable CPU FDI TX and PCH FDI RX */
2384 reg = FDI_TX_CTL(pipe);
2385 temp = I915_READ(reg);
2386 temp &= ~(7 << 19);
2387 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2388 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2389 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2390 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2391 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2392 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2393 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2394
2395 reg = FDI_RX_CTL(pipe);
2396 temp = I915_READ(reg);
2397 temp &= ~FDI_LINK_TRAIN_AUTO;
2398 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2399 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2400 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2401 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2402
2403 POSTING_READ(reg);
2404 udelay(150);
2405
291427f5
JB		 2406 if (HAS_PCH_CPT(dev))
2407 cpt_phase_pointer_enable(dev, pipe);
2408
0206e353 2409 for (i = 0; i < 4; i++) {
357555c0
JB		 2410 reg = FDI_TX_CTL(pipe);
2411 temp = I915_READ(reg);
2412 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2413 temp |= snb_b_fdi_train_param[i];
2414 I915_WRITE(reg, temp);
2415
2416 POSTING_READ(reg);
2417 udelay(500);
2418
2419 reg = FDI_RX_IIR(pipe);
2420 temp = I915_READ(reg);
2421 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2422
2423 if (temp & FDI_RX_BIT_LOCK ||
2424 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2425 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2426 DRM_DEBUG_KMS("FDI train 1 done.\n");
2427 break;
2428 }
2429 }
2430 if (i == 4)
2431 DRM_ERROR("FDI train 1 fail!\n");
2432
2433 /* Train 2 */
2434 reg = FDI_TX_CTL(pipe);
2435 temp = I915_READ(reg);
2436 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2437 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2438 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2439 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2440 I915_WRITE(reg, temp);
2441
2442 reg = FDI_RX_CTL(pipe);
2443 temp = I915_READ(reg);
2444 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2445 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2446 I915_WRITE(reg, temp);
2447
2448 POSTING_READ(reg);
2449 udelay(150);
2450
0206e353 2451 for (i = 0; i < 4; i++) {
357555c0
JB		 2452 reg = FDI_TX_CTL(pipe);
2453 temp = I915_READ(reg);
2454 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2455 temp |= snb_b_fdi_train_param[i];
2456 I915_WRITE(reg, temp);
2457
2458 POSTING_READ(reg);
2459 udelay(500);
2460
2461 reg = FDI_RX_IIR(pipe);
2462 temp = I915_READ(reg);
2463 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2464
2465 if (temp & FDI_RX_SYMBOL_LOCK) {
2466 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2467 DRM_DEBUG_KMS("FDI train 2 done.\n");
2468 break;
2469 }
2470 }
2471 if (i == 4)
2472 DRM_ERROR("FDI train 2 fail!\n");
2473
2474 DRM_DEBUG_KMS("FDI train done.\n");
2475}
2476
2477static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2478{
2479 struct drm_device *dev = crtc->dev;
2480 struct drm_i915_private *dev_priv = dev->dev_private;
2481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2482 int pipe = intel_crtc->pipe;
5eddb70b 2483 u32 reg, temp;
79e53945 2484
c64e311e 2485 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2486 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2487 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2488
c98e9dcf 2489 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2490 reg = FDI_RX_CTL(pipe);
2491 temp = I915_READ(reg);
2492 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2493 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2494 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2495 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2496
2497 POSTING_READ(reg);
c98e9dcf
JB		 2498 udelay(200);
2499
2500 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2501 temp = I915_READ(reg);
2502 I915_WRITE(reg, temp | FDI_PCDCLK);
2503
2504 POSTING_READ(reg);
c98e9dcf
JB		 2505 udelay(200);
2506
2507 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2508 reg = FDI_TX_CTL(pipe);
2509 temp = I915_READ(reg);
c98e9dcf 2510 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2511 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2512
2513 POSTING_READ(reg);
c98e9dcf 2514 udelay(100);
6be4a607 2515 }
0e23b99d
JB		 2516}
2517
291427f5
JB		 2518static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2519{
2520 struct drm_i915_private *dev_priv = dev->dev_private;
2521 u32 flags = I915_READ(SOUTH_CHICKEN1);
2522
2523 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2524 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2525 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2526 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2527 POSTING_READ(SOUTH_CHICKEN1);
2528}
0fc932b8
JB		 2529static void ironlake_fdi_disable(struct drm_crtc *crtc)
2530{
2531 struct drm_device *dev = crtc->dev;
2532 struct drm_i915_private *dev_priv = dev->dev_private;
2533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2534 int pipe = intel_crtc->pipe;
2535 u32 reg, temp;
2536
2537 /* disable CPU FDI tx and PCH FDI rx */
2538 reg = FDI_TX_CTL(pipe);
2539 temp = I915_READ(reg);
2540 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2541 POSTING_READ(reg);
2542
2543 reg = FDI_RX_CTL(pipe);
2544 temp = I915_READ(reg);
2545 temp &= ~(0x7 << 16);
2546 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2547 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2548
2549 POSTING_READ(reg);
2550 udelay(100);
2551
2552 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2553 if (HAS_PCH_IBX(dev)) {
2554 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2555 I915_WRITE(FDI_RX_CHICKEN(pipe),
2556 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2557 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2558 } else if (HAS_PCH_CPT(dev)) {
2559 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2560 }
0fc932b8
JB		 2561
2562 /* still set train pattern 1 */
2563 reg = FDI_TX_CTL(pipe);
2564 temp = I915_READ(reg);
2565 temp &= ~FDI_LINK_TRAIN_NONE;
2566 temp |= FDI_LINK_TRAIN_PATTERN_1;
2567 I915_WRITE(reg, temp);
2568
2569 reg = FDI_RX_CTL(pipe);
2570 temp = I915_READ(reg);
2571 if (HAS_PCH_CPT(dev)) {
2572 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2573 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2574 } else {
2575 temp &= ~FDI_LINK_TRAIN_NONE;
2576 temp |= FDI_LINK_TRAIN_PATTERN_1;
2577 }
2578 /* BPC in FDI rx is consistent with that in PIPECONF */
2579 temp &= ~(0x07 << 16);
2580 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2581 I915_WRITE(reg, temp);
2582
2583 POSTING_READ(reg);
2584 udelay(100);
2585}
2586
e6c3a2a6
CW		 2587static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2588{
0f91128d 2589 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2590
2591 if (crtc->fb == NULL)
2592 return;
2593
0f91128d
CW		 2594 mutex_lock(&dev->struct_mutex);
2595 intel_finish_fb(crtc->fb);
2596 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2597}
2598
040484af
JB		 2599static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2600{
2601 struct drm_device *dev = crtc->dev;
2602 struct drm_mode_config *mode_config = &dev->mode_config;
2603 struct intel_encoder *encoder;
2604
2605 /*
2606 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2607 * must be driven by its own crtc; no sharing is possible.
2608 */
2609 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2610 if (encoder->base.crtc != crtc)
2611 continue;
2612
2613 switch (encoder->type) {
2614 case INTEL_OUTPUT_EDP:
2615 if (!intel_encoder_is_pch_edp(&encoder->base))
2616 return false;
2617 continue;
2618 }
2619 }
2620
2621 return true;
2622}
2623
f67a559d
JB		 2624/*
2625 * Enable PCH resources required for PCH ports:
2626 * - PCH PLLs
2627 * - FDI training & RX/TX
2628 * - update transcoder timings
2629 * - DP transcoding bits
2630 * - transcoder
2631 */
2632static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2633{
2634 struct drm_device *dev = crtc->dev;
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2637 int pipe = intel_crtc->pipe;
ee7b9f93 2638 u32 reg, temp;
2c07245f 2639
c98e9dcf 2640 /* For PCH output, training FDI link */
674cf967 2641 dev_priv->display.fdi_link_train(crtc);
2c07245f 2642
ee7b9f93 2643 intel_enable_pch_pll(intel_crtc);
8db9d77b 2644
c98e9dcf 2645 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2646 u32 sel;
4b645f14 2647
c98e9dcf 2648 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2649 switch (pipe) {
2650 default:
2651 case 0:
2652 temp |= TRANSA_DPLL_ENABLE;
2653 sel = TRANSA_DPLLB_SEL;
2654 break;
2655 case 1:
2656 temp |= TRANSB_DPLL_ENABLE;
2657 sel = TRANSB_DPLLB_SEL;
2658 break;
2659 case 2:
2660 temp |= TRANSC_DPLL_ENABLE;
2661 sel = TRANSC_DPLLB_SEL;
2662 break;
d64311ab 2663 }
ee7b9f93
JB		 2664 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2665 temp |= sel;
2666 else
2667 temp &= ~sel;
c98e9dcf 2668 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2669 }
5eddb70b 2670
d9b6cb56
JB		 2671 /* set transcoder timing, panel must allow it */
2672 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2673 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2674 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2675 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2676
5eddb70b
CW		 2677 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2678 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2679 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 2680 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 2681
5e84e1a4
ZW		 2682 intel_fdi_normal_train(crtc);
2683
c98e9dcf
JB		 2684 /* For PCH DP, enable TRANS_DP_CTL */
2685 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2686 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2687 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 2688 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2689 reg = TRANS_DP_CTL(pipe);
2690 temp = I915_READ(reg);
2691 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2692 TRANS_DP_SYNC_MASK |
2693 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2694 temp |= (TRANS_DP_OUTPUT_ENABLE |
2695 TRANS_DP_ENH_FRAMING);
9325c9f0 2696 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2697
2698 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2699 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2700 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2701 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2702
2703 switch (intel_trans_dp_port_sel(crtc)) {
2704 case PCH_DP_B:
5eddb70b 2705 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2706 break;
2707 case PCH_DP_C:
5eddb70b 2708 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2709 break;
2710 case PCH_DP_D:
5eddb70b 2711 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2712 break;
2713 default:
2714 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2715 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2716 break;
32f9d658 2717 }
2c07245f 2718
5eddb70b 2719 I915_WRITE(reg, temp);
6be4a607 2720 }
b52eb4dc 2721
040484af 2722 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2723}
2724
ee7b9f93
JB		 2725static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2726{
2727 struct intel_pch_pll *pll = intel_crtc->pch_pll;
2728
2729 if (pll == NULL)
2730 return;
2731
2732 if (pll->refcount == 0) {
2733 WARN(1, "bad PCH PLL refcount\n");
2734 return;
2735 }
2736
2737 --pll->refcount;
2738 intel_crtc->pch_pll = NULL;
2739}
2740
2741static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2742{
2743 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2744 struct intel_pch_pll *pll;
2745 int i;
2746
2747 pll = intel_crtc->pch_pll;
2748 if (pll) {
2749 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2750 intel_crtc->base.base.id, pll->pll_reg);
2751 goto prepare;
2752 }
2753
2754 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2755 pll = &dev_priv->pch_plls[i];
2756
2757 /* Only want to check enabled timings first */
2758 if (pll->refcount == 0)
2759 continue;
2760
2761 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2762 fp == I915_READ(pll->fp0_reg)) {
2763 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2764 intel_crtc->base.base.id,
2765 pll->pll_reg, pll->refcount, pll->active);
2766
2767 goto found;
2768 }
2769 }
2770
2771 /* Ok no matching timings, maybe there's a free one? */
2772 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2773 pll = &dev_priv->pch_plls[i];
2774 if (pll->refcount == 0) {
2775 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2776 intel_crtc->base.base.id, pll->pll_reg);
2777 goto found;
2778 }
2779 }
2780
2781 return NULL;
2782
2783found:
2784 intel_crtc->pch_pll = pll;
2785 pll->refcount++;
2786 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2787prepare: /* separate function? */
2788 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 2789
e04c7350
CW		 2790 /* Wait for the clocks to stabilize before rewriting the regs */
2791 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 2792 POSTING_READ(pll->pll_reg);
2793 udelay(150);
e04c7350
CW		 2794
2795 I915_WRITE(pll->fp0_reg, fp);
2796 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 2797 pll->on = false;
2798 return pll;
2799}
2800
d4270e57
JB		 2801void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2802{
2803 struct drm_i915_private *dev_priv = dev->dev_private;
2804 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2805 u32 temp;
2806
2807 temp = I915_READ(dslreg);
2808 udelay(500);
2809 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2810 /* Without this, mode sets may fail silently on FDI */
2811 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2812 udelay(250);
2813 I915_WRITE(tc2reg, 0);
2814 if (wait_for(I915_READ(dslreg) != temp, 5))
2815 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2816 }
2817}
2818
f67a559d
JB		 2819static void ironlake_crtc_enable(struct drm_crtc *crtc)
2820{
2821 struct drm_device *dev = crtc->dev;
2822 struct drm_i915_private *dev_priv = dev->dev_private;
2823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2824 int pipe = intel_crtc->pipe;
2825 int plane = intel_crtc->plane;
2826 u32 temp;
2827 bool is_pch_port;
2828
2829 if (intel_crtc->active)
2830 return;
2831
2832 intel_crtc->active = true;
2833 intel_update_watermarks(dev);
2834
2835 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2836 temp = I915_READ(PCH_LVDS);
2837 if ((temp & LVDS_PORT_EN) == 0)
2838 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2839 }
2840
2841 is_pch_port = intel_crtc_driving_pch(crtc);
2842
2843 if (is_pch_port)
357555c0 2844 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2845 else
2846 ironlake_fdi_disable(crtc);
2847
2848 /* Enable panel fitting for LVDS */
2849 if (dev_priv->pch_pf_size &&
2850 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2851 /* Force use of hard-coded filter coefficients
2852 * as some pre-programmed values are broken,
2853 * e.g. x201.
2854 */
9db4a9c7
JB		 2855 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2856 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2857 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2858 }
2859
9c54c0dd
JB		 2860 /*
2861 * On ILK+ LUT must be loaded before the pipe is running but with
2862 * clocks enabled
2863 */
2864 intel_crtc_load_lut(crtc);
2865
f67a559d
JB		 2866 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2867 intel_enable_plane(dev_priv, plane, pipe);
2868
2869 if (is_pch_port)
2870 ironlake_pch_enable(crtc);
c98e9dcf 2871
d1ebd816 2872 mutex_lock(&dev->struct_mutex);
bed4a673 2873 intel_update_fbc(dev);
d1ebd816
BW		 2874 mutex_unlock(&dev->struct_mutex);
2875
6b383a7f 2876 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2877}
2878
2879static void ironlake_crtc_disable(struct drm_crtc *crtc)
2880{
2881 struct drm_device *dev = crtc->dev;
2882 struct drm_i915_private *dev_priv = dev->dev_private;
2883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2884 int pipe = intel_crtc->pipe;
2885 int plane = intel_crtc->plane;
5eddb70b 2886 u32 reg, temp;
b52eb4dc 2887
f7abfe8b
CW		 2888 if (!intel_crtc->active)
2889 return;
2890
e6c3a2a6 2891 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 2892 drm_vblank_off(dev, pipe);
6b383a7f 2893 intel_crtc_update_cursor(crtc, false);
5eddb70b 2894
b24e7179 2895 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 2896
973d04f9
CW		 2897 if (dev_priv->cfb_plane == plane)
2898 intel_disable_fbc(dev);
2c07245f 2899
b24e7179 2900 intel_disable_pipe(dev_priv, pipe);
32f9d658 2901
6be4a607 2902 /* Disable PF */
9db4a9c7
JB		 2903 I915_WRITE(PF_CTL(pipe), 0);
2904 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 2905
0fc932b8 2906 ironlake_fdi_disable(crtc);
2c07245f 2907
47a05eca
JB		 2908 /* This is a horrible layering violation; we should be doing this in
2909 * the connector/encoder ->prepare instead, but we don't always have
2910 * enough information there about the config to know whether it will
2911 * actually be necessary or just cause undesired flicker.
2912 */
2913 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 2914
040484af 2915 intel_disable_transcoder(dev_priv, pipe);
913d8d11 2916
6be4a607
JB		 2917 if (HAS_PCH_CPT(dev)) {
2918 /* disable TRANS_DP_CTL */
5eddb70b
CW		 2919 reg = TRANS_DP_CTL(pipe);
2920 temp = I915_READ(reg);
2921 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 2922 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 2923 I915_WRITE(reg, temp);
6be4a607
JB		 2924
2925 /* disable DPLL_SEL */
2926 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 2927 switch (pipe) {
2928 case 0:
d64311ab 2929 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 2930 break;
2931 case 1:
6be4a607 2932 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 2933 break;
2934 case 2:
4b645f14 2935 /* C shares PLL A or B */
d64311ab 2936 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 2937 break;
2938 default:
2939 BUG(); /* wtf */
2940 }
6be4a607 2941 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 2942 }
e3421a18 2943
6be4a607 2944 /* disable PCH DPLL */
ee7b9f93 2945 intel_disable_pch_pll(intel_crtc);
8db9d77b 2946
6be4a607 2947 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 2948 reg = FDI_RX_CTL(pipe);
2949 temp = I915_READ(reg);
2950 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 2951
6be4a607 2952 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 2953 reg = FDI_TX_CTL(pipe);
2954 temp = I915_READ(reg);
2955 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2956
2957 POSTING_READ(reg);
6be4a607 2958 udelay(100);
8db9d77b 2959
5eddb70b
CW		 2960 reg = FDI_RX_CTL(pipe);
2961 temp = I915_READ(reg);
2962 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 2963
6be4a607 2964 /* Wait for the clocks to turn off. */
5eddb70b 2965 POSTING_READ(reg);
6be4a607 2966 udelay(100);
6b383a7f 2967
f7abfe8b 2968 intel_crtc->active = false;
6b383a7f 2969 intel_update_watermarks(dev);
d1ebd816
BW		 2970
2971 mutex_lock(&dev->struct_mutex);
6b383a7f 2972 intel_update_fbc(dev);
d1ebd816 2973 mutex_unlock(&dev->struct_mutex);
6be4a607 2974}
1b3c7a47 2975
6be4a607
JB		 2976static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2977{
2978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2979 int pipe = intel_crtc->pipe;
2980 int plane = intel_crtc->plane;
8db9d77b 2981
6be4a607
JB		 2982 /* XXX: When our outputs are all unaware of DPMS modes other than off
2983 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2984 */
2985 switch (mode) {
2986 case DRM_MODE_DPMS_ON:
2987 case DRM_MODE_DPMS_STANDBY:
2988 case DRM_MODE_DPMS_SUSPEND:
2989 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2990 ironlake_crtc_enable(crtc);
2991 break;
1b3c7a47 2992
6be4a607
JB		 2993 case DRM_MODE_DPMS_OFF:
2994 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2995 ironlake_crtc_disable(crtc);
2c07245f
ZW		 2996 break;
2997 }
2998}
2999
ee7b9f93
JB		 3000static void ironlake_crtc_off(struct drm_crtc *crtc)
3001{
3002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3003 intel_put_pch_pll(intel_crtc);
3004}
3005
02e792fb
DV		 3006static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3007{
02e792fb 3008 if (!enable && intel_crtc->overlay) {
23f09ce3 3009 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3010 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3011
23f09ce3 3012 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3013 dev_priv->mm.interruptible = false;
3014 (void) intel_overlay_switch_off(intel_crtc->overlay);
3015 dev_priv->mm.interruptible = true;
23f09ce3 3016 mutex_unlock(&dev->struct_mutex);
02e792fb 3017 }
02e792fb 3018
5dcdbcb0
CW		 3019 /* Let userspace switch the overlay on again. In most cases userspace
3020 * has to recompute where to put it anyway.
3021 */
02e792fb
DV		 3022}
3023
0b8765c6 3024static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3025{
3026 struct drm_device *dev = crtc->dev;
79e53945
JB		 3027 struct drm_i915_private *dev_priv = dev->dev_private;
3028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3029 int pipe = intel_crtc->pipe;
80824003 3030 int plane = intel_crtc->plane;
79e53945 3031
f7abfe8b
CW		 3032 if (intel_crtc->active)
3033 return;
3034
3035 intel_crtc->active = true;
6b383a7f
CW		 3036 intel_update_watermarks(dev);
3037
63d7bbe9 3038 intel_enable_pll(dev_priv, pipe);
040484af 3039 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3040 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3041
0b8765c6 3042 intel_crtc_load_lut(crtc);
bed4a673 3043 intel_update_fbc(dev);
79e53945 3044
0b8765c6
JB		 3045 /* Give the overlay scaler a chance to enable if it's on this pipe */
3046 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3047 intel_crtc_update_cursor(crtc, true);
0b8765c6 3048}
79e53945 3049
0b8765c6
JB		 3050static void i9xx_crtc_disable(struct drm_crtc *crtc)
3051{
3052 struct drm_device *dev = crtc->dev;
3053 struct drm_i915_private *dev_priv = dev->dev_private;
3054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3055 int pipe = intel_crtc->pipe;
3056 int plane = intel_crtc->plane;
b690e96c 3057
f7abfe8b
CW		 3058 if (!intel_crtc->active)
3059 return;
3060
0b8765c6 3061 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3062 intel_crtc_wait_for_pending_flips(crtc);
3063 drm_vblank_off(dev, pipe);
0b8765c6 3064 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3065 intel_crtc_update_cursor(crtc, false);
0b8765c6 3066
973d04f9
CW		 3067 if (dev_priv->cfb_plane == plane)
3068 intel_disable_fbc(dev);
79e53945 3069
b24e7179 3070 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3071 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3072 intel_disable_pll(dev_priv, pipe);
0b8765c6 3073
f7abfe8b 3074 intel_crtc->active = false;
6b383a7f
CW		 3075 intel_update_fbc(dev);
3076 intel_update_watermarks(dev);
0b8765c6
JB		 3077}
3078
3079static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3080{
3081 /* XXX: When our outputs are all unaware of DPMS modes other than off
3082 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3083 */
3084 switch (mode) {
3085 case DRM_MODE_DPMS_ON:
3086 case DRM_MODE_DPMS_STANDBY:
3087 case DRM_MODE_DPMS_SUSPEND:
3088 i9xx_crtc_enable(crtc);
3089 break;
3090 case DRM_MODE_DPMS_OFF:
3091 i9xx_crtc_disable(crtc);
79e53945
JB		 3092 break;
3093 }
2c07245f
ZW		 3094}
3095
ee7b9f93
JB		 3096static void i9xx_crtc_off(struct drm_crtc *crtc)
3097{
3098}
3099
2c07245f
ZW		 3100/**
3101 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3102 */
3103static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3104{
3105 struct drm_device *dev = crtc->dev;
e70236a8 3106 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3107 struct drm_i915_master_private *master_priv;
3108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3109 int pipe = intel_crtc->pipe;
3110 bool enabled;
3111
032d2a0d
CW		 3112 if (intel_crtc->dpms_mode == mode)
3113 return;
3114
65655d4a 3115 intel_crtc->dpms_mode = mode;
debcaddc 3116
e70236a8 3117 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3118
3119 if (!dev->primary->master)
3120 return;
3121
3122 master_priv = dev->primary->master->driver_priv;
3123 if (!master_priv->sarea_priv)
3124 return;
3125
3126 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3127
3128 switch (pipe) {
3129 case 0:
3130 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3131 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3132 break;
3133 case 1:
3134 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3135 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3136 break;
3137 default:
9db4a9c7 3138 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3139 break;
3140 }
79e53945
JB		 3141}
3142
cdd59983
CW		 3143static void intel_crtc_disable(struct drm_crtc *crtc)
3144{
3145 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3146 struct drm_device *dev = crtc->dev;
ee7b9f93 3147 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983
CW		 3148
3149 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
ee7b9f93
JB		 3150 dev_priv->display.off(crtc);
3151
931872fc
CW		 3152 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3153 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3154
3155 if (crtc->fb) {
3156 mutex_lock(&dev->struct_mutex);
1690e1eb 3157 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3158 mutex_unlock(&dev->struct_mutex);
3159 }
3160}
3161
7e7d76c3
JB		 3162/* Prepare for a mode set.
3163 *
3164 * Note we could be a lot smarter here. We need to figure out which outputs
3165 * will be enabled, which disabled (in short, how the config will changes)
3166 * and perform the minimum necessary steps to accomplish that, e.g. updating
3167 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3168 * panel fitting is in the proper state, etc.
3169 */
3170static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3171{
7e7d76c3 3172 i9xx_crtc_disable(crtc);
79e53945
JB		 3173}
3174
7e7d76c3 3175static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3176{
7e7d76c3 3177 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3178}
3179
3180static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3181{
7e7d76c3 3182 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3183}
3184
3185static void ironlake_crtc_commit(struct drm_crtc *crtc)
3186{
7e7d76c3 3187 ironlake_crtc_enable(crtc);
79e53945
JB		 3188}
3189
0206e353 3190void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3191{
3192 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3193 /* lvds has its own version of prepare see intel_lvds_prepare */
3194 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3195}
3196
0206e353 3197void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3198{
3199 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57 3200 struct drm_device *dev = encoder->dev;
d47d7cb8 3201 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
d4270e57 3202
79e53945
JB		 3203 /* lvds has its own version of commit see intel_lvds_commit */
3204 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3205
3206 if (HAS_PCH_CPT(dev))
3207 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3208}
3209
ea5b213a
CW		 3210void intel_encoder_destroy(struct drm_encoder *encoder)
3211{
4ef69c7a 3212 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3213
ea5b213a
CW		 3214 drm_encoder_cleanup(encoder);
3215 kfree(intel_encoder);
3216}
3217
79e53945
JB		 3218static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3219 struct drm_display_mode *mode,
3220 struct drm_display_mode *adjusted_mode)
3221{
2c07245f 3222 struct drm_device *dev = crtc->dev;
89749350 3223
bad720ff 3224 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3225 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3226 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3227 return false;
2c07245f 3228 }
89749350 3229
f9bef081
DV		 3230 /* All interlaced capable intel hw wants timings in frames. Note though
3231 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3232 * timings, so we need to be careful not to clobber these.*/
3233 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3234 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3235
79e53945
JB		 3236 return true;
3237}
3238
25eb05fc
JB		 3239static int valleyview_get_display_clock_speed(struct drm_device *dev)
3240{
3241 return 400000; /* FIXME */
3242}
3243
e70236a8
JB		 3244static int i945_get_display_clock_speed(struct drm_device *dev)
3245{
3246 return 400000;
3247}
79e53945 3248
e70236a8 3249static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3250{
e70236a8
JB		 3251 return 333000;
3252}
79e53945 3253
e70236a8
JB		 3254static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3255{
3256 return 200000;
3257}
79e53945 3258
e70236a8
JB		 3259static int i915gm_get_display_clock_speed(struct drm_device *dev)
3260{
3261 u16 gcfgc = 0;
79e53945 3262
e70236a8
JB		 3263 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3264
3265 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3266 return 133000;
3267 else {
3268 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3269 case GC_DISPLAY_CLOCK_333_MHZ:
3270 return 333000;
3271 default:
3272 case GC_DISPLAY_CLOCK_190_200_MHZ:
3273 return 190000;
79e53945 3274 }
e70236a8
JB		 3275 }
3276}
3277
3278static int i865_get_display_clock_speed(struct drm_device *dev)
3279{
3280 return 266000;
3281}
3282
3283static int i855_get_display_clock_speed(struct drm_device *dev)
3284{
3285 u16 hpllcc = 0;
3286 /* Assume that the hardware is in the high speed state. This
3287 * should be the default.
3288 */
3289 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3290 case GC_CLOCK_133_200:
3291 case GC_CLOCK_100_200:
3292 return 200000;
3293 case GC_CLOCK_166_250:
3294 return 250000;
3295 case GC_CLOCK_100_133:
79e53945 3296 return 133000;
e70236a8 3297 }
79e53945 3298
e70236a8
JB		 3299 /* Shouldn't happen */
3300 return 0;
3301}
79e53945 3302
e70236a8
JB		 3303static int i830_get_display_clock_speed(struct drm_device *dev)
3304{
3305 return 133000;
79e53945
JB		 3306}
3307
2c07245f
ZW		 3308struct fdi_m_n {
3309 u32 tu;
3310 u32 gmch_m;
3311 u32 gmch_n;
3312 u32 link_m;
3313 u32 link_n;
3314};
3315
3316static void
3317fdi_reduce_ratio(u32 *num, u32 *den)
3318{
3319 while (*num > 0xffffff || *den > 0xffffff) {
3320 *num >>= 1;
3321 *den >>= 1;
3322 }
3323}
3324
2c07245f 3325static void
f2b115e6
AJ		 3326ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3327 int link_clock, struct fdi_m_n *m_n)
2c07245f 3328{
2c07245f
ZW		 3329 m_n->tu = 64; /* default size */
3330
22ed1113
CW		 3331 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3332 m_n->gmch_m = bits_per_pixel * pixel_clock;
3333 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3334 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3335
22ed1113
CW		 3336 m_n->link_m = pixel_clock;
3337 m_n->link_n = link_clock;
2c07245f
ZW		 3338 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3339}
3340
a7615030
CW		 3341static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3342{
72bbe58c
KP		 3343 if (i915_panel_use_ssc >= 0)
3344 return i915_panel_use_ssc != 0;
3345 return dev_priv->lvds_use_ssc
435793df 3346 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3347}
3348
5a354204
JB		 3349/**
3350 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3351 * @crtc: CRTC structure
3b5c78a3 3352 * @mode: requested mode
5a354204
JB		 3353 *
3354 * A pipe may be connected to one or more outputs. Based on the depth of the
3355 * attached framebuffer, choose a good color depth to use on the pipe.
3356 *
3357 * If possible, match the pipe depth to the fb depth. In some cases, this
3358 * isn't ideal, because the connected output supports a lesser or restricted
3359 * set of depths. Resolve that here:
3360 * LVDS typically supports only 6bpc, so clamp down in that case
3361 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3362 * Displays may support a restricted set as well, check EDID and clamp as
3363 * appropriate.
3b5c78a3 3364 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3365 *
3366 * RETURNS:
3367 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3368 * true if they don't match).
3369 */
3370static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 3371 unsigned int *pipe_bpp,
3372 struct drm_display_mode *mode)
5a354204
JB		 3373{
3374 struct drm_device *dev = crtc->dev;
3375 struct drm_i915_private *dev_priv = dev->dev_private;
3376 struct drm_encoder *encoder;
3377 struct drm_connector *connector;
3378 unsigned int display_bpc = UINT_MAX, bpc;
3379
3380 /* Walk the encoders & connectors on this crtc, get min bpc */
3381 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3382 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3383
3384 if (encoder->crtc != crtc)
3385 continue;
3386
3387 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3388 unsigned int lvds_bpc;
3389
3390 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3391 LVDS_A3_POWER_UP)
3392 lvds_bpc = 8;
3393 else
3394 lvds_bpc = 6;
3395
3396 if (lvds_bpc < display_bpc) {
82820490 3397 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3398 display_bpc = lvds_bpc;
3399 }
3400 continue;
3401 }
3402
3403 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3404 /* Use VBT settings if we have an eDP panel */
3405 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3406
3407 if (edp_bpc < display_bpc) {
82820490 3408 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 3409 display_bpc = edp_bpc;
3410 }
3411 continue;
3412 }
3413
3414 /* Not one of the known troublemakers, check the EDID */
3415 list_for_each_entry(connector, &dev->mode_config.connector_list,
3416 head) {
3417 if (connector->encoder != encoder)
3418 continue;
3419
62ac41a6
JB		 3420 /* Don't use an invalid EDID bpc value */
3421 if (connector->display_info.bpc &&
3422 connector->display_info.bpc < display_bpc) {
82820490 3423 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3424 display_bpc = connector->display_info.bpc;
3425 }
3426 }
3427
3428 /*
3429 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3430 * through, clamp it down. (Note: >12bpc will be caught below.)
3431 */
3432 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3433 if (display_bpc > 8 && display_bpc < 12) {
82820490 3434 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3435 display_bpc = 12;
3436 } else {
82820490 3437 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3438 display_bpc = 8;
3439 }
3440 }
3441 }
3442
3b5c78a3
AJ		 3443 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3444 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3445 display_bpc = 6;
3446 }
3447
5a354204
JB		 3448 /*
3449 * We could just drive the pipe at the highest bpc all the time and
3450 * enable dithering as needed, but that costs bandwidth. So choose
3451 * the minimum value that expresses the full color range of the fb but
3452 * also stays within the max display bpc discovered above.
3453 */
3454
3455 switch (crtc->fb->depth) {
3456 case 8:
3457 bpc = 8; /* since we go through a colormap */
3458 break;
3459 case 15:
3460 case 16:
3461 bpc = 6; /* min is 18bpp */
3462 break;
3463 case 24:
578393cd 3464 bpc = 8;
5a354204
JB		 3465 break;
3466 case 30:
578393cd 3467 bpc = 10;
5a354204
JB		 3468 break;
3469 case 48:
578393cd 3470 bpc = 12;
5a354204
JB		 3471 break;
3472 default:
3473 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3474 bpc = min((unsigned int)8, display_bpc);
3475 break;
3476 }
3477
578393cd
KP		 3478 display_bpc = min(display_bpc, bpc);
3479
82820490
AJ		 3480 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3481 bpc, display_bpc);
5a354204 3482
578393cd 3483 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3484
3485 return display_bpc != bpc;
3486}
3487
c65d77d8
JB		 3488static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3489{
3490 struct drm_device *dev = crtc->dev;
3491 struct drm_i915_private *dev_priv = dev->dev_private;
3492 int refclk;
3493
3494 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3495 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3496 refclk = dev_priv->lvds_ssc_freq * 1000;
3497 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3498 refclk / 1000);
3499 } else if (!IS_GEN2(dev)) {
3500 refclk = 96000;
3501 } else {
3502 refclk = 48000;
3503 }
3504
3505 return refclk;
3506}
3507
3508static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3509 intel_clock_t *clock)
3510{
3511 /* SDVO TV has fixed PLL values depend on its clock range,
3512 this mirrors vbios setting. */
3513 if (adjusted_mode->clock >= 100000
3514 && adjusted_mode->clock < 140500) {
3515 clock->p1 = 2;
3516 clock->p2 = 10;
3517 clock->n = 3;
3518 clock->m1 = 16;
3519 clock->m2 = 8;
3520 } else if (adjusted_mode->clock >= 140500
3521 && adjusted_mode->clock <= 200000) {
3522 clock->p1 = 1;
3523 clock->p2 = 10;
3524 clock->n = 6;
3525 clock->m1 = 12;
3526 clock->m2 = 8;
3527 }
3528}
3529
a7516a05
JB		 3530static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3531 intel_clock_t *clock,
3532 intel_clock_t *reduced_clock)
3533{
3534 struct drm_device *dev = crtc->dev;
3535 struct drm_i915_private *dev_priv = dev->dev_private;
3536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3537 int pipe = intel_crtc->pipe;
3538 u32 fp, fp2 = 0;
3539
3540 if (IS_PINEVIEW(dev)) {
3541 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3542 if (reduced_clock)
3543 fp2 = (1 << reduced_clock->n) << 16 |
3544 reduced_clock->m1 << 8 | reduced_clock->m2;
3545 } else {
3546 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3547 if (reduced_clock)
3548 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3549 reduced_clock->m2;
3550 }
3551
3552 I915_WRITE(FP0(pipe), fp);
3553
3554 intel_crtc->lowfreq_avail = false;
3555 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3556 reduced_clock && i915_powersave) {
3557 I915_WRITE(FP1(pipe), fp2);
3558 intel_crtc->lowfreq_avail = true;
3559 } else {
3560 I915_WRITE(FP1(pipe), fp);
3561 }
3562}
3563
93e537a1
DV		 3564static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3565 struct drm_display_mode *adjusted_mode)
3566{
3567 struct drm_device *dev = crtc->dev;
3568 struct drm_i915_private *dev_priv = dev->dev_private;
3569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3570 int pipe = intel_crtc->pipe;
284d5df5 3571 u32 temp;
93e537a1
DV		 3572
3573 temp = I915_READ(LVDS);
3574 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3575 if (pipe == 1) {
3576 temp |= LVDS_PIPEB_SELECT;
3577 } else {
3578 temp &= ~LVDS_PIPEB_SELECT;
3579 }
3580 /* set the corresponsding LVDS_BORDER bit */
3581 temp |= dev_priv->lvds_border_bits;
3582 /* Set the B0-B3 data pairs corresponding to whether we're going to
3583 * set the DPLLs for dual-channel mode or not.
3584 */
3585 if (clock->p2 == 7)
3586 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3587 else
3588 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3589
3590 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3591 * appropriately here, but we need to look more thoroughly into how
3592 * panels behave in the two modes.
3593 */
3594 /* set the dithering flag on LVDS as needed */
3595 if (INTEL_INFO(dev)->gen >= 4) {
3596 if (dev_priv->lvds_dither)
3597 temp |= LVDS_ENABLE_DITHER;
3598 else
3599 temp &= ~LVDS_ENABLE_DITHER;
3600 }
284d5df5 3601 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 3602 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 3603 temp |= LVDS_HSYNC_POLARITY;
93e537a1 3604 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 3605 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 3606 I915_WRITE(LVDS, temp);
3607}
3608
eb1cbe48
DV		 3609static void i9xx_update_pll(struct drm_crtc *crtc,
3610 struct drm_display_mode *mode,
3611 struct drm_display_mode *adjusted_mode,
3612 intel_clock_t *clock, intel_clock_t *reduced_clock,
3613 int num_connectors)
3614{
3615 struct drm_device *dev = crtc->dev;
3616 struct drm_i915_private *dev_priv = dev->dev_private;
3617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3618 int pipe = intel_crtc->pipe;
3619 u32 dpll;
3620 bool is_sdvo;
3621
3622 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3623 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3624
3625 dpll = DPLL_VGA_MODE_DIS;
3626
3627 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3628 dpll |= DPLLB_MODE_LVDS;
3629 else
3630 dpll |= DPLLB_MODE_DAC_SERIAL;
3631 if (is_sdvo) {
3632 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3633 if (pixel_multiplier > 1) {
3634 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3635 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3636 }
3637 dpll |= DPLL_DVO_HIGH_SPEED;
3638 }
3639 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3640 dpll |= DPLL_DVO_HIGH_SPEED;
3641
3642 /* compute bitmask from p1 value */
3643 if (IS_PINEVIEW(dev))
3644 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3645 else {
3646 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3647 if (IS_G4X(dev) && reduced_clock)
3648 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3649 }
3650 switch (clock->p2) {
3651 case 5:
3652 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3653 break;
3654 case 7:
3655 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3656 break;
3657 case 10:
3658 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3659 break;
3660 case 14:
3661 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3662 break;
3663 }
3664 if (INTEL_INFO(dev)->gen >= 4)
3665 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3666
3667 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3668 dpll |= PLL_REF_INPUT_TVCLKINBC;
3669 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3670 /* XXX: just matching BIOS for now */
3671 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3672 dpll |= 3;
3673 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3674 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3675 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3676 else
3677 dpll |= PLL_REF_INPUT_DREFCLK;
3678
3679 dpll |= DPLL_VCO_ENABLE;
3680 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3681 POSTING_READ(DPLL(pipe));
3682 udelay(150);
3683
3684 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3685 * This is an exception to the general rule that mode_set doesn't turn
3686 * things on.
3687 */
3688 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3689 intel_update_lvds(crtc, clock, adjusted_mode);
3690
3691 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3692 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3693
3694 I915_WRITE(DPLL(pipe), dpll);
3695
3696 /* Wait for the clocks to stabilize. */
3697 POSTING_READ(DPLL(pipe));
3698 udelay(150);
3699
3700 if (INTEL_INFO(dev)->gen >= 4) {
3701 u32 temp = 0;
3702 if (is_sdvo) {
3703 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3704 if (temp > 1)
3705 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3706 else
3707 temp = 0;
3708 }
3709 I915_WRITE(DPLL_MD(pipe), temp);
3710 } else {
3711 /* The pixel multiplier can only be updated once the
3712 * DPLL is enabled and the clocks are stable.
3713 *
3714 * So write it again.
3715 */
3716 I915_WRITE(DPLL(pipe), dpll);
3717 }
3718}
3719
3720static void i8xx_update_pll(struct drm_crtc *crtc,
3721 struct drm_display_mode *adjusted_mode,
3722 intel_clock_t *clock,
3723 int num_connectors)
3724{
3725 struct drm_device *dev = crtc->dev;
3726 struct drm_i915_private *dev_priv = dev->dev_private;
3727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3728 int pipe = intel_crtc->pipe;
3729 u32 dpll;
3730
3731 dpll = DPLL_VGA_MODE_DIS;
3732
3733 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3734 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3735 } else {
3736 if (clock->p1 == 2)
3737 dpll |= PLL_P1_DIVIDE_BY_TWO;
3738 else
3739 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3740 if (clock->p2 == 4)
3741 dpll |= PLL_P2_DIVIDE_BY_4;
3742 }
3743
3744 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3745 /* XXX: just matching BIOS for now */
3746 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3747 dpll |= 3;
3748 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3749 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3750 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3751 else
3752 dpll |= PLL_REF_INPUT_DREFCLK;
3753
3754 dpll |= DPLL_VCO_ENABLE;
3755 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3756 POSTING_READ(DPLL(pipe));
3757 udelay(150);
3758
3759 I915_WRITE(DPLL(pipe), dpll);
3760
3761 /* Wait for the clocks to stabilize. */
3762 POSTING_READ(DPLL(pipe));
3763 udelay(150);
3764
3765 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3766 * This is an exception to the general rule that mode_set doesn't turn
3767 * things on.
3768 */
3769 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3770 intel_update_lvds(crtc, clock, adjusted_mode);
3771
3772 /* The pixel multiplier can only be updated once the
3773 * DPLL is enabled and the clocks are stable.
3774 *
3775 * So write it again.
3776 */
3777 I915_WRITE(DPLL(pipe), dpll);
3778}
3779
f564048e
EA		 3780static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3781 struct drm_display_mode *mode,
3782 struct drm_display_mode *adjusted_mode,
3783 int x, int y,
3784 struct drm_framebuffer *old_fb)
79e53945
JB		 3785{
3786 struct drm_device *dev = crtc->dev;
3787 struct drm_i915_private *dev_priv = dev->dev_private;
3788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3789 int pipe = intel_crtc->pipe;
80824003 3790 int plane = intel_crtc->plane;
c751ce4f 3791 int refclk, num_connectors = 0;
652c393a 3792 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 3793 u32 dspcntr, pipeconf, vsyncshift;
3794 bool ok, has_reduced_clock = false, is_sdvo = false;
3795 bool is_lvds = false, is_tv = false, is_dp = false;
79e53945 3796 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 3797 struct intel_encoder *encoder;
d4906093 3798 const intel_limit_t *limit;
5c3b82e2 3799 int ret;
79e53945 3800
5eddb70b
CW		 3801 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3802 if (encoder->base.crtc != crtc)
79e53945
JB		 3803 continue;
3804
5eddb70b 3805 switch (encoder->type) {
79e53945
JB		 3806 case INTEL_OUTPUT_LVDS:
3807 is_lvds = true;
3808 break;
3809 case INTEL_OUTPUT_SDVO:
7d57382e 3810 case INTEL_OUTPUT_HDMI:
79e53945 3811 is_sdvo = true;
5eddb70b 3812 if (encoder->needs_tv_clock)
e2f0ba97 3813 is_tv = true;
79e53945 3814 break;
79e53945
JB		 3815 case INTEL_OUTPUT_TVOUT:
3816 is_tv = true;
3817 break;
a4fc5ed6
KP		 3818 case INTEL_OUTPUT_DISPLAYPORT:
3819 is_dp = true;
3820 break;
79e53945 3821 }
43565a06 3822
c751ce4f 3823 num_connectors++;
79e53945
JB		 3824 }
3825
c65d77d8 3826 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 3827
d4906093
ML		 3828 /*
3829 * Returns a set of divisors for the desired target clock with the given
3830 * refclk, or FALSE. The returned values represent the clock equation:
3831 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3832 */
1b894b59 3833 limit = intel_limit(crtc, refclk);
cec2f356
SP		 3834 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3835 &clock);
79e53945
JB		 3836 if (!ok) {
3837 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 3838 return -EINVAL;
79e53945
JB		 3839 }
3840
cda4b7d3 3841 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 3842 intel_crtc_update_cursor(crtc, true);
cda4b7d3 3843
ddc9003c 3844 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 3845 /*
3846 * Ensure we match the reduced clock's P to the target clock.
3847 * If the clocks don't match, we can't switch the display clock
3848 * by using the FP0/FP1. In such case we will disable the LVDS
3849 * downclock feature.
3850 */
ddc9003c 3851 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 3852 dev_priv->lvds_downclock,
3853 refclk,
cec2f356 3854 &clock,
5eddb70b 3855 &reduced_clock);
7026d4ac
ZW		 3856 }
3857
c65d77d8
JB		 3858 if (is_sdvo && is_tv)
3859 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 3860
a7516a05
JB		 3861 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
3862 &reduced_clock : NULL);
79e53945 3863
eb1cbe48
DV		 3864 if (IS_GEN2(dev))
3865 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
79e53945 3866 else
eb1cbe48
DV		 3867 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
3868 has_reduced_clock ? &reduced_clock : NULL,
3869 num_connectors);
79e53945
JB		 3870
3871 /* setup pipeconf */
5eddb70b 3872 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 3873
3874 /* Set up the display plane register */
3875 dspcntr = DISPPLANE_GAMMA_ENABLE;
3876
929c77fb
EA		 3877 if (pipe == 0)
3878 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3879 else
3880 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 3881
a6c45cf0 3882 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 3883 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3884 * core speed.
3885 *
3886 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3887 * pipe == 0 check?
3888 */
e70236a8
JB		 3889 if (mode->clock >
3890 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 3891 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 3892 else
5eddb70b 3893 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 3894 }
3895
3b5c78a3
AJ		 3896 /* default to 8bpc */
3897 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
3898 if (is_dp) {
3899 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3900 pipeconf |= PIPECONF_BPP_6 |
3901 PIPECONF_DITHER_EN |
3902 PIPECONF_DITHER_TYPE_SP;
3903 }
3904 }
3905
28c97730 3906 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 3907 drm_mode_debug_printmodeline(mode);
3908
a7516a05
JB		 3909 if (HAS_PIPE_CXSR(dev)) {
3910 if (intel_crtc->lowfreq_avail) {
28c97730 3911 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 3912 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 3913 } else {
28c97730 3914 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 3915 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3916 }
3917 }
3918
617cf884 3919 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 3920 if (!IS_GEN2(dev) &&
3921 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 3922 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3923 /* the chip adds 2 halflines automatically */
734b4157 3924 adjusted_mode->crtc_vtotal -= 1;
734b4157 3925 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 3926 vsyncshift = adjusted_mode->crtc_hsync_start
3927 - adjusted_mode->crtc_htotal/2;
3928 } else {
617cf884 3929 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 3930 vsyncshift = 0;
3931 }
3932
3933 if (!IS_GEN3(dev))
3934 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 3935
5eddb70b
CW		 3936 I915_WRITE(HTOTAL(pipe),
3937 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 3938 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 3939 I915_WRITE(HBLANK(pipe),
3940 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 3941 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 3942 I915_WRITE(HSYNC(pipe),
3943 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 3944 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 3945
3946 I915_WRITE(VTOTAL(pipe),
3947 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 3948 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 3949 I915_WRITE(VBLANK(pipe),
3950 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 3951 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 3952 I915_WRITE(VSYNC(pipe),
3953 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 3954 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 3955
3956 /* pipesrc and dspsize control the size that is scaled from,
3957 * which should always be the user's requested size.
79e53945 3958 */
929c77fb
EA		 3959 I915_WRITE(DSPSIZE(plane),
3960 ((mode->vdisplay - 1) << 16) |
3961 (mode->hdisplay - 1));
3962 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 3963 I915_WRITE(PIPESRC(pipe),
3964 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 3965
f564048e
EA		 3966 I915_WRITE(PIPECONF(pipe), pipeconf);
3967 POSTING_READ(PIPECONF(pipe));
929c77fb 3968 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 3969
3970 intel_wait_for_vblank(dev, pipe);
3971
f564048e
EA		 3972 I915_WRITE(DSPCNTR(plane), dspcntr);
3973 POSTING_READ(DSPCNTR(plane));
3974
3975 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3976
3977 intel_update_watermarks(dev);
3978
f564048e
EA		 3979 return ret;
3980}
3981
9fb526db
KP		 3982/*
3983 * Initialize reference clocks when the driver loads
3984 */
3985void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 3986{
3987 struct drm_i915_private *dev_priv = dev->dev_private;
3988 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 3989 struct intel_encoder *encoder;
13d83a67
JB		 3990 u32 temp;
3991 bool has_lvds = false;
199e5d79
KP		 3992 bool has_cpu_edp = false;
3993 bool has_pch_edp = false;
3994 bool has_panel = false;
99eb6a01
KP		 3995 bool has_ck505 = false;
3996 bool can_ssc = false;
13d83a67
JB		 3997
3998 /* We need to take the global config into account */
199e5d79
KP		 3999 list_for_each_entry(encoder, &mode_config->encoder_list,
4000 base.head) {
4001 switch (encoder->type) {
4002 case INTEL_OUTPUT_LVDS:
4003 has_panel = true;
4004 has_lvds = true;
4005 break;
4006 case INTEL_OUTPUT_EDP:
4007 has_panel = true;
4008 if (intel_encoder_is_pch_edp(&encoder->base))
4009 has_pch_edp = true;
4010 else
4011 has_cpu_edp = true;
4012 break;
13d83a67
JB		 4013 }
4014 }
4015
99eb6a01
KP		 4016 if (HAS_PCH_IBX(dev)) {
4017 has_ck505 = dev_priv->display_clock_mode;
4018 can_ssc = has_ck505;
4019 } else {
4020 has_ck505 = false;
4021 can_ssc = true;
4022 }
4023
4024 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4025 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4026 has_ck505);
13d83a67
JB		 4027
4028 /* Ironlake: try to setup display ref clock before DPLL
4029 * enabling. This is only under driver's control after
4030 * PCH B stepping, previous chipset stepping should be
4031 * ignoring this setting.
4032 */
4033 temp = I915_READ(PCH_DREF_CONTROL);
4034 /* Always enable nonspread source */
4035 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4036
99eb6a01
KP		 4037 if (has_ck505)
4038 temp |= DREF_NONSPREAD_CK505_ENABLE;
4039 else
4040 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4041
199e5d79
KP		 4042 if (has_panel) {
4043 temp &= ~DREF_SSC_SOURCE_MASK;
4044 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4045
199e5d79 4046 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4047 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4048 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4049 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4050 } else
4051 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4052
4053 /* Get SSC going before enabling the outputs */
4054 I915_WRITE(PCH_DREF_CONTROL, temp);
4055 POSTING_READ(PCH_DREF_CONTROL);
4056 udelay(200);
4057
13d83a67
JB		 4058 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4059
4060 /* Enable CPU source on CPU attached eDP */
199e5d79 4061 if (has_cpu_edp) {
99eb6a01 4062 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4063 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4064 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4065 }
13d83a67
JB		 4066 else
4067 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4068 } else
4069 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4070
4071 I915_WRITE(PCH_DREF_CONTROL, temp);
4072 POSTING_READ(PCH_DREF_CONTROL);
4073 udelay(200);
4074 } else {
4075 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4076
4077 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4078
4079 /* Turn off CPU output */
4080 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4081
4082 I915_WRITE(PCH_DREF_CONTROL, temp);
4083 POSTING_READ(PCH_DREF_CONTROL);
4084 udelay(200);
4085
4086 /* Turn off the SSC source */
4087 temp &= ~DREF_SSC_SOURCE_MASK;
4088 temp |= DREF_SSC_SOURCE_DISABLE;
4089
4090 /* Turn off SSC1 */
4091 temp &= ~ DREF_SSC1_ENABLE;
4092
13d83a67
JB		 4093 I915_WRITE(PCH_DREF_CONTROL, temp);
4094 POSTING_READ(PCH_DREF_CONTROL);
4095 udelay(200);
4096 }
4097}
4098
d9d444cb
JB		 4099static int ironlake_get_refclk(struct drm_crtc *crtc)
4100{
4101 struct drm_device *dev = crtc->dev;
4102 struct drm_i915_private *dev_priv = dev->dev_private;
4103 struct intel_encoder *encoder;
4104 struct drm_mode_config *mode_config = &dev->mode_config;
4105 struct intel_encoder *edp_encoder = NULL;
4106 int num_connectors = 0;
4107 bool is_lvds = false;
4108
4109 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4110 if (encoder->base.crtc != crtc)
4111 continue;
4112
4113 switch (encoder->type) {
4114 case INTEL_OUTPUT_LVDS:
4115 is_lvds = true;
4116 break;
4117 case INTEL_OUTPUT_EDP:
4118 edp_encoder = encoder;
4119 break;
4120 }
4121 num_connectors++;
4122 }
4123
4124 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4125 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4126 dev_priv->lvds_ssc_freq);
4127 return dev_priv->lvds_ssc_freq * 1000;
4128 }
4129
4130 return 120000;
4131}
4132
f564048e
EA		 4133static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4134 struct drm_display_mode *mode,
4135 struct drm_display_mode *adjusted_mode,
4136 int x, int y,
4137 struct drm_framebuffer *old_fb)
79e53945
JB		 4138{
4139 struct drm_device *dev = crtc->dev;
4140 struct drm_i915_private *dev_priv = dev->dev_private;
4141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4142 int pipe = intel_crtc->pipe;
80824003 4143 int plane = intel_crtc->plane;
c751ce4f 4144 int refclk, num_connectors = 0;
652c393a 4145 intel_clock_t clock, reduced_clock;
5eddb70b 4146 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4147 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4148 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4149 struct drm_mode_config *mode_config = &dev->mode_config;
e3aef172 4150 struct intel_encoder *encoder, *edp_encoder = NULL;
d4906093 4151 const intel_limit_t *limit;
5c3b82e2 4152 int ret;
2c07245f 4153 struct fdi_m_n m_n = {0};
fae14981 4154 u32 temp;
5a354204
JB		 4155 int target_clock, pixel_multiplier, lane, link_bw, factor;
4156 unsigned int pipe_bpp;
4157 bool dither;
e3aef172 4158 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4159
5eddb70b
CW		 4160 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4161 if (encoder->base.crtc != crtc)
79e53945
JB		 4162 continue;
4163
5eddb70b 4164 switch (encoder->type) {
79e53945
JB		 4165 case INTEL_OUTPUT_LVDS:
4166 is_lvds = true;
4167 break;
4168 case INTEL_OUTPUT_SDVO:
7d57382e 4169 case INTEL_OUTPUT_HDMI:
79e53945 4170 is_sdvo = true;
5eddb70b 4171 if (encoder->needs_tv_clock)
e2f0ba97 4172 is_tv = true;
79e53945 4173 break;
79e53945
JB		 4174 case INTEL_OUTPUT_TVOUT:
4175 is_tv = true;
4176 break;
4177 case INTEL_OUTPUT_ANALOG:
4178 is_crt = true;
4179 break;
a4fc5ed6
KP		 4180 case INTEL_OUTPUT_DISPLAYPORT:
4181 is_dp = true;
4182 break;
32f9d658 4183 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4184 is_dp = true;
4185 if (intel_encoder_is_pch_edp(&encoder->base))
4186 is_pch_edp = true;
4187 else
4188 is_cpu_edp = true;
4189 edp_encoder = encoder;
32f9d658 4190 break;
79e53945 4191 }
43565a06 4192
c751ce4f 4193 num_connectors++;
79e53945
JB		 4194 }
4195
d9d444cb 4196 refclk = ironlake_get_refclk(crtc);
79e53945 4197
d4906093
ML		 4198 /*
4199 * Returns a set of divisors for the desired target clock with the given
4200 * refclk, or FALSE. The returned values represent the clock equation:
4201 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4202 */
1b894b59 4203 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4204 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4205 &clock);
79e53945
JB		 4206 if (!ok) {
4207 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4208 return -EINVAL;
79e53945
JB		 4209 }
4210
cda4b7d3 4211 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4212 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4213
ddc9003c 4214 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4215 /*
4216 * Ensure we match the reduced clock's P to the target clock.
4217 * If the clocks don't match, we can't switch the display clock
4218 * by using the FP0/FP1. In such case we will disable the LVDS
4219 * downclock feature.
4220 */
ddc9003c 4221 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4222 dev_priv->lvds_downclock,
4223 refclk,
cec2f356 4224 &clock,
5eddb70b 4225 &reduced_clock);
652c393a 4226 }
7026d4ac
ZW		 4227 /* SDVO TV has fixed PLL values depend on its clock range,
4228 this mirrors vbios setting. */
4229 if (is_sdvo && is_tv) {
4230 if (adjusted_mode->clock >= 100000
5eddb70b 4231 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4232 clock.p1 = 2;
4233 clock.p2 = 10;
4234 clock.n = 3;
4235 clock.m1 = 16;
4236 clock.m2 = 8;
4237 } else if (adjusted_mode->clock >= 140500
5eddb70b 4238 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4239 clock.p1 = 1;
4240 clock.p2 = 10;
4241 clock.n = 6;
4242 clock.m1 = 12;
4243 clock.m2 = 8;
4244 }
4245 }
4246
2c07245f 4247 /* FDI link */
8febb297
EA		 4248 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4249 lane = 0;
4250 /* CPU eDP doesn't require FDI link, so just set DP M/N
4251 according to current link config */
e3aef172 4252 if (is_cpu_edp) {
8febb297 4253 target_clock = mode->clock;
e3aef172 4254 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297
EA		 4255 } else {
4256 /* [e]DP over FDI requires target mode clock
4257 instead of link clock */
e3aef172 4258 if (is_dp)
5eb08b69 4259 target_clock = mode->clock;
8febb297
EA		 4260 else
4261 target_clock = adjusted_mode->clock;
4262
4263 /* FDI is a binary signal running at ~2.7GHz, encoding
4264 * each output octet as 10 bits. The actual frequency
4265 * is stored as a divider into a 100MHz clock, and the
4266 * mode pixel clock is stored in units of 1KHz.
4267 * Hence the bw of each lane in terms of the mode signal
4268 * is:
4269 */
4270 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4271 }
58a27471 4272
8febb297
EA		 4273 /* determine panel color depth */
4274 temp = I915_READ(PIPECONF(pipe));
4275 temp &= ~PIPE_BPC_MASK;
3b5c78a3 4276 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 4277 switch (pipe_bpp) {
4278 case 18:
4279 temp |= PIPE_6BPC;
8febb297 4280 break;
5a354204
JB		 4281 case 24:
4282 temp |= PIPE_8BPC;
8febb297 4283 break;
5a354204
JB		 4284 case 30:
4285 temp |= PIPE_10BPC;
8febb297 4286 break;
5a354204
JB		 4287 case 36:
4288 temp |= PIPE_12BPC;
8febb297
EA		 4289 break;
4290 default:
62ac41a6
JB		 4291 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4292 pipe_bpp);
5a354204
JB		 4293 temp |= PIPE_8BPC;
4294 pipe_bpp = 24;
4295 break;
8febb297 4296 }
77ffb597 4297
5a354204
JB		 4298 intel_crtc->bpp = pipe_bpp;
4299 I915_WRITE(PIPECONF(pipe), temp);
4300
8febb297
EA		 4301 if (!lane) {
4302 /*
4303 * Account for spread spectrum to avoid
4304 * oversubscribing the link. Max center spread
4305 * is 2.5%; use 5% for safety's sake.
4306 */
5a354204 4307 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4308 lane = bps / (link_bw * 8) + 1;
5eb08b69 4309 }
2c07245f 4310
8febb297
EA		 4311 intel_crtc->fdi_lanes = lane;
4312
4313 if (pixel_multiplier > 1)
4314 link_bw *= pixel_multiplier;
5a354204
JB		 4315 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4316 &m_n);
8febb297 4317
a07d6787
EA		 4318 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4319 if (has_reduced_clock)
4320 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4321 reduced_clock.m2;
79e53945 4322
c1858123 4323 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4324 factor = 21;
4325 if (is_lvds) {
4326 if ((intel_panel_use_ssc(dev_priv) &&
4327 dev_priv->lvds_ssc_freq == 100) ||
4328 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4329 factor = 25;
4330 } else if (is_sdvo && is_tv)
4331 factor = 20;
c1858123 4332
cb0e0931 4333 if (clock.m < factor * clock.n)
8febb297 4334 fp |= FP_CB_TUNE;
2c07245f 4335
5eddb70b 4336 dpll = 0;
2c07245f 4337
a07d6787
EA		 4338 if (is_lvds)
4339 dpll |= DPLLB_MODE_LVDS;
4340 else
4341 dpll |= DPLLB_MODE_DAC_SERIAL;
4342 if (is_sdvo) {
4343 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4344 if (pixel_multiplier > 1) {
4345 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4346 }
a07d6787
EA		 4347 dpll |= DPLL_DVO_HIGH_SPEED;
4348 }
e3aef172 4349 if (is_dp && !is_cpu_edp)
a07d6787 4350 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4351
a07d6787
EA		 4352 /* compute bitmask from p1 value */
4353 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4354 /* also FPA1 */
4355 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4356
4357 switch (clock.p2) {
4358 case 5:
4359 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4360 break;
4361 case 7:
4362 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4363 break;
4364 case 10:
4365 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4366 break;
4367 case 14:
4368 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4369 break;
79e53945
JB		 4370 }
4371
43565a06
KH		 4372 if (is_sdvo && is_tv)
4373 dpll |= PLL_REF_INPUT_TVCLKINBC;
4374 else if (is_tv)
79e53945 4375 /* XXX: just matching BIOS for now */
43565a06 4376 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4377 dpll |= 3;
a7615030 4378 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4379 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4380 else
4381 dpll |= PLL_REF_INPUT_DREFCLK;
4382
4383 /* setup pipeconf */
5eddb70b 4384 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4385
4386 /* Set up the display plane register */
4387 dspcntr = DISPPLANE_GAMMA_ENABLE;
4388
f7cb34d4 4389 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4390 drm_mode_debug_printmodeline(mode);
4391
ee7b9f93
JB		 4392 /* CPU eDP is the only output that doesn't need a PCH PLL of its own */
4393 if (!is_cpu_edp) {
4394 struct intel_pch_pll *pll;
4b645f14 4395
ee7b9f93
JB		 4396 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4397 if (pll == NULL) {
4398 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4399 pipe);
4b645f14
JB		 4400 return -EINVAL;
4401 }
ee7b9f93
JB		 4402 } else
4403 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4404
4405 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4406 * This is an exception to the general rule that mode_set doesn't turn
4407 * things on.
4408 */
4409 if (is_lvds) {
fae14981 4410 temp = I915_READ(PCH_LVDS);
5eddb70b 4411 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4412 if (HAS_PCH_CPT(dev)) {
4413 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4414 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4415 } else {
4416 if (pipe == 1)
4417 temp |= LVDS_PIPEB_SELECT;
4418 else
4419 temp &= ~LVDS_PIPEB_SELECT;
4420 }
4b645f14 4421
a3e17eb8 4422 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4423 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4424 /* Set the B0-B3 data pairs corresponding to whether we're going to
4425 * set the DPLLs for dual-channel mode or not.
4426 */
4427 if (clock.p2 == 7)
5eddb70b 4428 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4429 else
5eddb70b 4430 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4431
4432 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4433 * appropriately here, but we need to look more thoroughly into how
4434 * panels behave in the two modes.
4435 */
284d5df5 4436 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4437 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4438 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4439 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4440 temp |= LVDS_VSYNC_POLARITY;
fae14981 4441 I915_WRITE(PCH_LVDS, temp);
79e53945 4442 }
434ed097 4443
8febb297
EA		 4444 pipeconf &= ~PIPECONF_DITHER_EN;
4445 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 4446 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 4447 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 4448 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 4449 }
e3aef172 4450 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4451 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4452 } else {
8db9d77b 4453 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4454 I915_WRITE(TRANSDATA_M1(pipe), 0);
4455 I915_WRITE(TRANSDATA_N1(pipe), 0);
4456 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4457 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4458 }
79e53945 4459
ee7b9f93
JB		 4460 if (intel_crtc->pch_pll) {
4461 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4462
32f9d658 4463 /* Wait for the clocks to stabilize. */
ee7b9f93 4464 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4465 udelay(150);
4466
8febb297
EA		 4467 /* The pixel multiplier can only be updated once the
4468 * DPLL is enabled and the clocks are stable.
4469 *
4470 * So write it again.
4471 */
ee7b9f93 4472 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 4473 }
79e53945 4474
5eddb70b 4475 intel_crtc->lowfreq_avail = false;
ee7b9f93 4476 if (intel_crtc->pch_pll) {
4b645f14 4477 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 4478 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14
JB		 4479 intel_crtc->lowfreq_avail = true;
4480 if (HAS_PIPE_CXSR(dev)) {
4481 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4482 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4483 }
4484 } else {
ee7b9f93 4485 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4b645f14
JB		 4486 if (HAS_PIPE_CXSR(dev)) {
4487 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4488 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4489 }
652c393a
JB		 4490 }
4491 }
4492
617cf884 4493 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 4494 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 4495 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 4496 /* the chip adds 2 halflines automatically */
734b4157 4497 adjusted_mode->crtc_vtotal -= 1;
734b4157 4498 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4499 I915_WRITE(VSYNCSHIFT(pipe),
4500 adjusted_mode->crtc_hsync_start
4501 - adjusted_mode->crtc_htotal/2);
4502 } else {
617cf884 4503 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4504 I915_WRITE(VSYNCSHIFT(pipe), 0);
4505 }
734b4157 4506
5eddb70b
CW		 4507 I915_WRITE(HTOTAL(pipe),
4508 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4509 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4510 I915_WRITE(HBLANK(pipe),
4511 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4512 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4513 I915_WRITE(HSYNC(pipe),
4514 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4515 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4516
4517 I915_WRITE(VTOTAL(pipe),
4518 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4519 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4520 I915_WRITE(VBLANK(pipe),
4521 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4522 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4523 I915_WRITE(VSYNC(pipe),
4524 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4525 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 4526
8febb297
EA		 4527 /* pipesrc controls the size that is scaled from, which should
4528 * always be the user's requested size.
79e53945 4529 */
5eddb70b
CW		 4530 I915_WRITE(PIPESRC(pipe),
4531 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4532
8febb297
EA		 4533 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4534 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4535 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4536 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 4537
e3aef172 4538 if (is_cpu_edp)
8febb297 4539 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 4540
5eddb70b
CW		 4541 I915_WRITE(PIPECONF(pipe), pipeconf);
4542 POSTING_READ(PIPECONF(pipe));
79e53945 4543
9d0498a2 4544 intel_wait_for_vblank(dev, pipe);
79e53945 4545
5eddb70b 4546 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 4547 POSTING_READ(DSPCNTR(plane));
79e53945 4548
5c3b82e2 4549 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 4550
4551 intel_update_watermarks(dev);
4552
1f803ee5 4553 return ret;
79e53945
JB		 4554}
4555
f564048e
EA		 4556static int intel_crtc_mode_set(struct drm_crtc *crtc,
4557 struct drm_display_mode *mode,
4558 struct drm_display_mode *adjusted_mode,
4559 int x, int y,
4560 struct drm_framebuffer *old_fb)
4561{
4562 struct drm_device *dev = crtc->dev;
4563 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 4564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4565 int pipe = intel_crtc->pipe;
f564048e
EA		 4566 int ret;
4567
0b701d27 4568 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 4569
f564048e
EA		 4570 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4571 x, y, old_fb);
79e53945 4572 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 4573
d8e70a25
JB		 4574 if (ret)
4575 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4576 else
4577 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 4578
1f803ee5 4579 return ret;
79e53945
JB		 4580}
4581
3a9627f4
WF		 4582static bool intel_eld_uptodate(struct drm_connector *connector,
4583 int reg_eldv, uint32_t bits_eldv,
4584 int reg_elda, uint32_t bits_elda,
4585 int reg_edid)
4586{
4587 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4588 uint8_t *eld = connector->eld;
4589 uint32_t i;
4590
4591 i = I915_READ(reg_eldv);
4592 i &= bits_eldv;
4593
4594 if (!eld[0])
4595 return !i;
4596
4597 if (!i)
4598 return false;
4599
4600 i = I915_READ(reg_elda);
4601 i &= ~bits_elda;
4602 I915_WRITE(reg_elda, i);
4603
4604 for (i = 0; i < eld[2]; i++)
4605 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4606 return false;
4607
4608 return true;
4609}
4610
e0dac65e
WF		 4611static void g4x_write_eld(struct drm_connector *connector,
4612 struct drm_crtc *crtc)
4613{
4614 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4615 uint8_t *eld = connector->eld;
4616 uint32_t eldv;
4617 uint32_t len;
4618 uint32_t i;
4619
4620 i = I915_READ(G4X_AUD_VID_DID);
4621
4622 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4623 eldv = G4X_ELDV_DEVCL_DEVBLC;
4624 else
4625 eldv = G4X_ELDV_DEVCTG;
4626
3a9627f4
WF		 4627 if (intel_eld_uptodate(connector,
4628 G4X_AUD_CNTL_ST, eldv,
4629 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4630 G4X_HDMIW_HDMIEDID))
4631 return;
4632
e0dac65e
WF		 4633 i = I915_READ(G4X_AUD_CNTL_ST);
4634 i &= ~(eldv | G4X_ELD_ADDR);
4635 len = (i >> 9) & 0x1f; /* ELD buffer size */
4636 I915_WRITE(G4X_AUD_CNTL_ST, i);
4637
4638 if (!eld[0])
4639 return;
4640
4641 len = min_t(uint8_t, eld[2], len);
4642 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4643 for (i = 0; i < len; i++)
4644 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4645
4646 i = I915_READ(G4X_AUD_CNTL_ST);
4647 i |= eldv;
4648 I915_WRITE(G4X_AUD_CNTL_ST, i);
4649}
4650
4651static void ironlake_write_eld(struct drm_connector *connector,
4652 struct drm_crtc *crtc)
4653{
4654 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4655 uint8_t *eld = connector->eld;
4656 uint32_t eldv;
4657 uint32_t i;
4658 int len;
4659 int hdmiw_hdmiedid;
b6daa025 4660 int aud_config;
e0dac65e
WF		 4661 int aud_cntl_st;
4662 int aud_cntrl_st2;
4663
b3f33cbf 4664 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6 4665 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
b6daa025 4666 aud_config = IBX_AUD_CONFIG_A;
1202b4c6
WF		 4667 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4668 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 4669 } else {
1202b4c6 4670 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
b6daa025 4671 aud_config = CPT_AUD_CONFIG_A;
1202b4c6
WF		 4672 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4673 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 4674 }
4675
4676 i = to_intel_crtc(crtc)->pipe;
4677 hdmiw_hdmiedid += i * 0x100;
4678 aud_cntl_st += i * 0x100;
b6daa025 4679 aud_config += i * 0x100;
e0dac65e
WF		 4680
4681 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4682
4683 i = I915_READ(aud_cntl_st);
4684 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4685 if (!i) {
4686 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4687 /* operate blindly on all ports */
1202b4c6
WF		 4688 eldv = IBX_ELD_VALIDB;
4689 eldv |= IBX_ELD_VALIDB << 4;
4690 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 4691 } else {
4692 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 4693 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 4694 }
4695
3a9627f4
WF		 4696 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4697 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4698 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 4699 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4700 } else
4701 I915_WRITE(aud_config, 0);
e0dac65e 4702
3a9627f4
WF		 4703 if (intel_eld_uptodate(connector,
4704 aud_cntrl_st2, eldv,
4705 aud_cntl_st, IBX_ELD_ADDRESS,
4706 hdmiw_hdmiedid))
4707 return;
4708
e0dac65e
WF		 4709 i = I915_READ(aud_cntrl_st2);
4710 i &= ~eldv;
4711 I915_WRITE(aud_cntrl_st2, i);
4712
4713 if (!eld[0])
4714 return;
4715
e0dac65e 4716 i = I915_READ(aud_cntl_st);
1202b4c6 4717 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 4718 I915_WRITE(aud_cntl_st, i);
4719
4720 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
4721 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4722 for (i = 0; i < len; i++)
4723 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4724
4725 i = I915_READ(aud_cntrl_st2);
4726 i |= eldv;
4727 I915_WRITE(aud_cntrl_st2, i);
4728}
4729
4730void intel_write_eld(struct drm_encoder *encoder,
4731 struct drm_display_mode *mode)
4732{
4733 struct drm_crtc *crtc = encoder->crtc;
4734 struct drm_connector *connector;
4735 struct drm_device *dev = encoder->dev;
4736 struct drm_i915_private *dev_priv = dev->dev_private;
4737
4738 connector = drm_select_eld(encoder, mode);
4739 if (!connector)
4740 return;
4741
4742 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4743 connector->base.id,
4744 drm_get_connector_name(connector),
4745 connector->encoder->base.id,
4746 drm_get_encoder_name(connector->encoder));
4747
4748 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4749
4750 if (dev_priv->display.write_eld)
4751 dev_priv->display.write_eld(connector, crtc);
4752}
4753
79e53945
JB		 4754/** Loads the palette/gamma unit for the CRTC with the prepared values */
4755void intel_crtc_load_lut(struct drm_crtc *crtc)
4756{
4757 struct drm_device *dev = crtc->dev;
4758 struct drm_i915_private *dev_priv = dev->dev_private;
4759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 4760 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 4761 int i;
4762
4763 /* The clocks have to be on to load the palette. */
aed3f09d 4764 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 4765 return;
4766
f2b115e6 4767 /* use legacy palette for Ironlake */
bad720ff 4768 if (HAS_PCH_SPLIT(dev))
9db4a9c7 4769 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 4770
79e53945
JB		 4771 for (i = 0; i < 256; i++) {
4772 I915_WRITE(palreg + 4 * i,
4773 (intel_crtc->lut_r[i] << 16) |
4774 (intel_crtc->lut_g[i] << 8) |
4775 intel_crtc->lut_b[i]);
4776 }
4777}
4778
560b85bb
CW		 4779static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4780{
4781 struct drm_device *dev = crtc->dev;
4782 struct drm_i915_private *dev_priv = dev->dev_private;
4783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4784 bool visible = base != 0;
4785 u32 cntl;
4786
4787 if (intel_crtc->cursor_visible == visible)
4788 return;
4789
9db4a9c7 4790 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 4791 if (visible) {
4792 /* On these chipsets we can only modify the base whilst
4793 * the cursor is disabled.
4794 */
9db4a9c7 4795 I915_WRITE(_CURABASE, base);
560b85bb
CW		 4796
4797 cntl &= ~(CURSOR_FORMAT_MASK);
4798 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4799 cntl |= CURSOR_ENABLE |
4800 CURSOR_GAMMA_ENABLE |
4801 CURSOR_FORMAT_ARGB;
4802 } else
4803 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 4804 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 4805
4806 intel_crtc->cursor_visible = visible;
4807}
4808
4809static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4810{
4811 struct drm_device *dev = crtc->dev;
4812 struct drm_i915_private *dev_priv = dev->dev_private;
4813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4814 int pipe = intel_crtc->pipe;
4815 bool visible = base != 0;
4816
4817 if (intel_crtc->cursor_visible != visible) {
548f245b 4818 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 4819 if (base) {
4820 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4821 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4822 cntl |= pipe << 28; /* Connect to correct pipe */
4823 } else {
4824 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4825 cntl |= CURSOR_MODE_DISABLE;
4826 }
9db4a9c7 4827 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 4828
4829 intel_crtc->cursor_visible = visible;
4830 }
4831 /* and commit changes on next vblank */
9db4a9c7 4832 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 4833}
4834
65a21cd6
JB		 4835static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4836{
4837 struct drm_device *dev = crtc->dev;
4838 struct drm_i915_private *dev_priv = dev->dev_private;
4839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4840 int pipe = intel_crtc->pipe;
4841 bool visible = base != 0;
4842
4843 if (intel_crtc->cursor_visible != visible) {
4844 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
4845 if (base) {
4846 cntl &= ~CURSOR_MODE;
4847 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4848 } else {
4849 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4850 cntl |= CURSOR_MODE_DISABLE;
4851 }
4852 I915_WRITE(CURCNTR_IVB(pipe), cntl);
4853
4854 intel_crtc->cursor_visible = visible;
4855 }
4856 /* and commit changes on next vblank */
4857 I915_WRITE(CURBASE_IVB(pipe), base);
4858}
4859
cda4b7d3 4860/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 4861static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4862 bool on)
cda4b7d3
CW		 4863{
4864 struct drm_device *dev = crtc->dev;
4865 struct drm_i915_private *dev_priv = dev->dev_private;
4866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4867 int pipe = intel_crtc->pipe;
4868 int x = intel_crtc->cursor_x;
4869 int y = intel_crtc->cursor_y;
560b85bb 4870 u32 base, pos;
cda4b7d3
CW		 4871 bool visible;
4872
4873 pos = 0;
4874
6b383a7f 4875 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 4876 base = intel_crtc->cursor_addr;
4877 if (x > (int) crtc->fb->width)
4878 base = 0;
4879
4880 if (y > (int) crtc->fb->height)
4881 base = 0;
4882 } else
4883 base = 0;
4884
4885 if (x < 0) {
4886 if (x + intel_crtc->cursor_width < 0)
4887 base = 0;
4888
4889 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4890 x = -x;
4891 }
4892 pos |= x << CURSOR_X_SHIFT;
4893
4894 if (y < 0) {
4895 if (y + intel_crtc->cursor_height < 0)
4896 base = 0;
4897
4898 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4899 y = -y;
4900 }
4901 pos |= y << CURSOR_Y_SHIFT;
4902
4903 visible = base != 0;
560b85bb 4904 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 4905 return;
4906
0cd83aa9 4907 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 4908 I915_WRITE(CURPOS_IVB(pipe), pos);
4909 ivb_update_cursor(crtc, base);
4910 } else {
4911 I915_WRITE(CURPOS(pipe), pos);
4912 if (IS_845G(dev) || IS_I865G(dev))
4913 i845_update_cursor(crtc, base);
4914 else
4915 i9xx_update_cursor(crtc, base);
4916 }
cda4b7d3
CW		 4917}
4918
79e53945 4919static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 4920 struct drm_file *file,
79e53945
JB		 4921 uint32_t handle,
4922 uint32_t width, uint32_t height)
4923{
4924 struct drm_device *dev = crtc->dev;
4925 struct drm_i915_private *dev_priv = dev->dev_private;
4926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 4927 struct drm_i915_gem_object *obj;
cda4b7d3 4928 uint32_t addr;
3f8bc370 4929 int ret;
79e53945 4930
28c97730 4931 DRM_DEBUG_KMS("\n");
79e53945
JB		 4932
4933 /* if we want to turn off the cursor ignore width and height */
4934 if (!handle) {
28c97730 4935 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 4936 addr = 0;
05394f39 4937 obj = NULL;
5004417d 4938 mutex_lock(&dev->struct_mutex);
3f8bc370 4939 goto finish;
79e53945
JB		 4940 }
4941
4942 /* Currently we only support 64x64 cursors */
4943 if (width != 64 || height != 64) {
4944 DRM_ERROR("we currently only support 64x64 cursors\n");
4945 return -EINVAL;
4946 }
4947
05394f39 4948 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 4949 if (&obj->base == NULL)
79e53945
JB		 4950 return -ENOENT;
4951
05394f39 4952 if (obj->base.size < width * height * 4) {
79e53945 4953 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 4954 ret = -ENOMEM;
4955 goto fail;
79e53945
JB		 4956 }
4957
71acb5eb 4958 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 4959 mutex_lock(&dev->struct_mutex);
b295d1b6 4960 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 4961 if (obj->tiling_mode) {
4962 DRM_ERROR("cursor cannot be tiled\n");
4963 ret = -EINVAL;
4964 goto fail_locked;
4965 }
4966
2da3b9b9 4967 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 4968 if (ret) {
4969 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 4970 goto fail_locked;
e7b526bb
CW		 4971 }
4972
d9e86c0e
CW		 4973 ret = i915_gem_object_put_fence(obj);
4974 if (ret) {
2da3b9b9 4975 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 4976 goto fail_unpin;
4977 }
4978
05394f39 4979 addr = obj->gtt_offset;
71acb5eb 4980 } else {
6eeefaf3 4981 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 4982 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 4983 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4984 align);
71acb5eb
DA		 4985 if (ret) {
4986 DRM_ERROR("failed to attach phys object\n");
7f9872e0 4987 goto fail_locked;
71acb5eb 4988 }
05394f39 4989 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 4990 }
4991
a6c45cf0 4992 if (IS_GEN2(dev))
14b60391
JB		 4993 I915_WRITE(CURSIZE, (height << 12) | width);
4994
3f8bc370 4995 finish:
3f8bc370 4996 if (intel_crtc->cursor_bo) {
b295d1b6 4997 if (dev_priv->info->cursor_needs_physical) {
05394f39 4998 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 4999 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5000 } else
5001 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5002 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5003 }
80824003 5004
7f9872e0 5005 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5006
5007 intel_crtc->cursor_addr = addr;
05394f39 5008 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5009 intel_crtc->cursor_width = width;
5010 intel_crtc->cursor_height = height;
5011
6b383a7f 5012 intel_crtc_update_cursor(crtc, true);
3f8bc370 5013
79e53945 5014 return 0;
e7b526bb 5015fail_unpin:
05394f39 5016 i915_gem_object_unpin(obj);
7f9872e0 5017fail_locked:
34b8686e 5018 mutex_unlock(&dev->struct_mutex);
bc9025bd 5019fail:
05394f39 5020 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5021 return ret;
79e53945
JB		 5022}
5023
5024static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5025{
79e53945 5026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5027
cda4b7d3
CW		 5028 intel_crtc->cursor_x = x;
5029 intel_crtc->cursor_y = y;
652c393a 5030
6b383a7f 5031 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5032
5033 return 0;
5034}
5035
5036/** Sets the color ramps on behalf of RandR */
5037void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5038 u16 blue, int regno)
5039{
5040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5041
5042 intel_crtc->lut_r[regno] = red >> 8;
5043 intel_crtc->lut_g[regno] = green >> 8;
5044 intel_crtc->lut_b[regno] = blue >> 8;
5045}
5046
b8c00ac5
DA		 5047void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5048 u16 *blue, int regno)
5049{
5050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5051
5052 *red = intel_crtc->lut_r[regno] << 8;
5053 *green = intel_crtc->lut_g[regno] << 8;
5054 *blue = intel_crtc->lut_b[regno] << 8;
5055}
5056
79e53945 5057static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5058 u16 *blue, uint32_t start, uint32_t size)
79e53945 5059{
7203425a 5060 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5062
7203425a 5063 for (i = start; i < end; i++) {
79e53945
JB		 5064 intel_crtc->lut_r[i] = red[i] >> 8;
5065 intel_crtc->lut_g[i] = green[i] >> 8;
5066 intel_crtc->lut_b[i] = blue[i] >> 8;
5067 }
5068
5069 intel_crtc_load_lut(crtc);
5070}
5071
5072/**
5073 * Get a pipe with a simple mode set on it for doing load-based monitor
5074 * detection.
5075 *
5076 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5077 * its requirements. The pipe will be connected to no other encoders.
79e53945 5078 *
c751ce4f 5079 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5080 * configured for it. In the future, it could choose to temporarily disable
5081 * some outputs to free up a pipe for its use.
5082 *
5083 * \return crtc, or NULL if no pipes are available.
5084 */
5085
5086/* VESA 640x480x72Hz mode to set on the pipe */
5087static struct drm_display_mode load_detect_mode = {
5088 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5089 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5090};
5091
d2dff872
CW		 5092static struct drm_framebuffer *
5093intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5094 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5095 struct drm_i915_gem_object *obj)
5096{
5097 struct intel_framebuffer *intel_fb;
5098 int ret;
5099
5100 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5101 if (!intel_fb) {
5102 drm_gem_object_unreference_unlocked(&obj->base);
5103 return ERR_PTR(-ENOMEM);
5104 }
5105
5106 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5107 if (ret) {
5108 drm_gem_object_unreference_unlocked(&obj->base);
5109 kfree(intel_fb);
5110 return ERR_PTR(ret);
5111 }
5112
5113 return &intel_fb->base;
5114}
5115
5116static u32
5117intel_framebuffer_pitch_for_width(int width, int bpp)
5118{
5119 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5120 return ALIGN(pitch, 64);
5121}
5122
5123static u32
5124intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5125{
5126 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5127 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5128}
5129
5130static struct drm_framebuffer *
5131intel_framebuffer_create_for_mode(struct drm_device *dev,
5132 struct drm_display_mode *mode,
5133 int depth, int bpp)
5134{
5135 struct drm_i915_gem_object *obj;
308e5bcb 5136 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5137
5138 obj = i915_gem_alloc_object(dev,
5139 intel_framebuffer_size_for_mode(mode, bpp));
5140 if (obj == NULL)
5141 return ERR_PTR(-ENOMEM);
5142
5143 mode_cmd.width = mode->hdisplay;
5144 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5145 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5146 bpp);
5ca0c34a 5147 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5148
5149 return intel_framebuffer_create(dev, &mode_cmd, obj);
5150}
5151
5152static struct drm_framebuffer *
5153mode_fits_in_fbdev(struct drm_device *dev,
5154 struct drm_display_mode *mode)
5155{
5156 struct drm_i915_private *dev_priv = dev->dev_private;
5157 struct drm_i915_gem_object *obj;
5158 struct drm_framebuffer *fb;
5159
5160 if (dev_priv->fbdev == NULL)
5161 return NULL;
5162
5163 obj = dev_priv->fbdev->ifb.obj;
5164 if (obj == NULL)
5165 return NULL;
5166
5167 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5168 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5169 fb->bits_per_pixel))
d2dff872
CW		 5170 return NULL;
5171
01f2c773 5172 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5173 return NULL;
5174
5175 return fb;
5176}
5177
7173188d
CW		 5178bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5179 struct drm_connector *connector,
5180 struct drm_display_mode *mode,
8261b191 5181 struct intel_load_detect_pipe *old)
79e53945
JB		 5182{
5183 struct intel_crtc *intel_crtc;
5184 struct drm_crtc *possible_crtc;
4ef69c7a 5185 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5186 struct drm_crtc *crtc = NULL;
5187 struct drm_device *dev = encoder->dev;
d2dff872 5188 struct drm_framebuffer *old_fb;
79e53945
JB		 5189 int i = -1;
5190
d2dff872
CW		 5191 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5192 connector->base.id, drm_get_connector_name(connector),
5193 encoder->base.id, drm_get_encoder_name(encoder));
5194
79e53945
JB		 5195 /*
5196 * Algorithm gets a little messy:
7a5e4805 5197 *
79e53945
JB		 5198 * - if the connector already has an assigned crtc, use it (but make
5199 * sure it's on first)
7a5e4805 5200 *
79e53945
JB		 5201 * - try to find the first unused crtc that can drive this connector,
5202 * and use that if we find one
79e53945
JB		 5203 */
5204
5205 /* See if we already have a CRTC for this connector */
5206 if (encoder->crtc) {
5207 crtc = encoder->crtc;
8261b191 5208
79e53945 5209 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5210 old->dpms_mode = intel_crtc->dpms_mode;
5211 old->load_detect_temp = false;
5212
5213 /* Make sure the crtc and connector are running */
79e53945 5214 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5215 struct drm_encoder_helper_funcs *encoder_funcs;
5216 struct drm_crtc_helper_funcs *crtc_funcs;
5217
79e53945
JB		 5218 crtc_funcs = crtc->helper_private;
5219 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5220
5221 encoder_funcs = encoder->helper_private;
79e53945
JB		 5222 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5223 }
8261b191 5224
7173188d 5225 return true;
79e53945
JB		 5226 }
5227
5228 /* Find an unused one (if possible) */
5229 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5230 i++;
5231 if (!(encoder->possible_crtcs & (1 << i)))
5232 continue;
5233 if (!possible_crtc->enabled) {
5234 crtc = possible_crtc;
5235 break;
5236 }
79e53945
JB		 5237 }
5238
5239 /*
5240 * If we didn't find an unused CRTC, don't use any.
5241 */
5242 if (!crtc) {
7173188d
CW		 5243 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5244 return false;
79e53945
JB		 5245 }
5246
5247 encoder->crtc = crtc;
c1c43977 5248 connector->encoder = encoder;
79e53945
JB		 5249
5250 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5251 old->dpms_mode = intel_crtc->dpms_mode;
5252 old->load_detect_temp = true;
d2dff872 5253 old->release_fb = NULL;
79e53945 5254
6492711d
CW		 5255 if (!mode)
5256 mode = &load_detect_mode;
79e53945 5257
d2dff872
CW		 5258 old_fb = crtc->fb;
5259
5260 /* We need a framebuffer large enough to accommodate all accesses
5261 * that the plane may generate whilst we perform load detection.
5262 * We can not rely on the fbcon either being present (we get called
5263 * during its initialisation to detect all boot displays, or it may
5264 * not even exist) or that it is large enough to satisfy the
5265 * requested mode.
5266 */
5267 crtc->fb = mode_fits_in_fbdev(dev, mode);
5268 if (crtc->fb == NULL) {
5269 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5270 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5271 old->release_fb = crtc->fb;
5272 } else
5273 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5274 if (IS_ERR(crtc->fb)) {
5275 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5276 crtc->fb = old_fb;
5277 return false;
79e53945 5278 }
79e53945 5279
d2dff872 5280 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5281 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5282 if (old->release_fb)
5283 old->release_fb->funcs->destroy(old->release_fb);
5284 crtc->fb = old_fb;
6492711d 5285 return false;
79e53945 5286 }
7173188d 5287
79e53945 5288 /* let the connector get through one full cycle before testing */
9d0498a2 5289 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5290
7173188d 5291 return true;
79e53945
JB		 5292}
5293
c1c43977 5294void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5295 struct drm_connector *connector,
5296 struct intel_load_detect_pipe *old)
79e53945 5297{
4ef69c7a 5298 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5299 struct drm_device *dev = encoder->dev;
5300 struct drm_crtc *crtc = encoder->crtc;
5301 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5302 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5303
d2dff872
CW		 5304 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5305 connector->base.id, drm_get_connector_name(connector),
5306 encoder->base.id, drm_get_encoder_name(encoder));
5307
8261b191 5308 if (old->load_detect_temp) {
c1c43977 5309 connector->encoder = NULL;
79e53945 5310 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5311
5312 if (old->release_fb)
5313 old->release_fb->funcs->destroy(old->release_fb);
5314
0622a53c 5315 return;
79e53945
JB		 5316 }
5317
c751ce4f 5318 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5319 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5320 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5321 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5322 }
5323}
5324
5325/* Returns the clock of the currently programmed mode of the given pipe. */
5326static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5327{
5328 struct drm_i915_private *dev_priv = dev->dev_private;
5329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5330 int pipe = intel_crtc->pipe;
548f245b 5331 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5332 u32 fp;
5333 intel_clock_t clock;
5334
5335 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5336 fp = I915_READ(FP0(pipe));
79e53945 5337 else
39adb7a5 5338 fp = I915_READ(FP1(pipe));
79e53945
JB		 5339
5340 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5341 if (IS_PINEVIEW(dev)) {
5342 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5343 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5344 } else {
5345 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5346 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5347 }
5348
a6c45cf0 5349 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5350 if (IS_PINEVIEW(dev))
5351 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5352 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5353 else
5354 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5355 DPLL_FPA01_P1_POST_DIV_SHIFT);
5356
5357 switch (dpll & DPLL_MODE_MASK) {
5358 case DPLLB_MODE_DAC_SERIAL:
5359 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5360 5 : 10;
5361 break;
5362 case DPLLB_MODE_LVDS:
5363 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5364 7 : 14;
5365 break;
5366 default:
28c97730 5367 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5368 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5369 return 0;
5370 }
5371
5372 /* XXX: Handle the 100Mhz refclk */
2177832f 5373 intel_clock(dev, 96000, &clock);
79e53945
JB		 5374 } else {
5375 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5376
5377 if (is_lvds) {
5378 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5379 DPLL_FPA01_P1_POST_DIV_SHIFT);
5380 clock.p2 = 14;
5381
5382 if ((dpll & PLL_REF_INPUT_MASK) ==
5383 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5384 /* XXX: might not be 66MHz */
2177832f 5385 intel_clock(dev, 66000, &clock);
79e53945 5386 } else
2177832f 5387 intel_clock(dev, 48000, &clock);
79e53945
JB		 5388 } else {
5389 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5390 clock.p1 = 2;
5391 else {
5392 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5393 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5394 }
5395 if (dpll & PLL_P2_DIVIDE_BY_4)
5396 clock.p2 = 4;
5397 else
5398 clock.p2 = 2;
5399
2177832f 5400 intel_clock(dev, 48000, &clock);
79e53945
JB		 5401 }
5402 }
5403
5404 /* XXX: It would be nice to validate the clocks, but we can't reuse
5405 * i830PllIsValid() because it relies on the xf86_config connector
5406 * configuration being accurate, which it isn't necessarily.
5407 */
5408
5409 return clock.dot;
5410}
5411
5412/** Returns the currently programmed mode of the given pipe. */
5413struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5414 struct drm_crtc *crtc)
5415{
548f245b 5416 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5418 int pipe = intel_crtc->pipe;
5419 struct drm_display_mode *mode;
548f245b
JB		 5420 int htot = I915_READ(HTOTAL(pipe));
5421 int hsync = I915_READ(HSYNC(pipe));
5422 int vtot = I915_READ(VTOTAL(pipe));
5423 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5424
5425 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5426 if (!mode)
5427 return NULL;
5428
5429 mode->clock = intel_crtc_clock_get(dev, crtc);
5430 mode->hdisplay = (htot & 0xffff) + 1;
5431 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5432 mode->hsync_start = (hsync & 0xffff) + 1;
5433 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5434 mode->vdisplay = (vtot & 0xffff) + 1;
5435 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5436 mode->vsync_start = (vsync & 0xffff) + 1;
5437 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5438
5439 drm_mode_set_name(mode);
79e53945
JB		 5440
5441 return mode;
5442}
5443
652c393a
JB		 5444#define GPU_IDLE_TIMEOUT 500 /* ms */
5445
5446/* When this timer fires, we've been idle for awhile */
5447static void intel_gpu_idle_timer(unsigned long arg)
5448{
5449 struct drm_device *dev = (struct drm_device *)arg;
5450 drm_i915_private_t *dev_priv = dev->dev_private;
5451
ff7ea4c0
CW		 5452 if (!list_empty(&dev_priv->mm.active_list)) {
5453 /* Still processing requests, so just re-arm the timer. */
5454 mod_timer(&dev_priv->idle_timer, jiffies +
5455 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5456 return;
5457 }
652c393a 5458
ff7ea4c0 5459 dev_priv->busy = false;
01dfba93 5460 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5461}
5462
652c393a
JB		 5463#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5464
5465static void intel_crtc_idle_timer(unsigned long arg)
5466{
5467 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5468 struct drm_crtc *crtc = &intel_crtc->base;
5469 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5470 struct intel_framebuffer *intel_fb;
652c393a 5471
ff7ea4c0
CW		 5472 intel_fb = to_intel_framebuffer(crtc->fb);
5473 if (intel_fb && intel_fb->obj->active) {
5474 /* The framebuffer is still being accessed by the GPU. */
5475 mod_timer(&intel_crtc->idle_timer, jiffies +
5476 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5477 return;
5478 }
652c393a 5479
ff7ea4c0 5480 intel_crtc->busy = false;
01dfba93 5481 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5482}
5483
3dec0095 5484static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5485{
5486 struct drm_device *dev = crtc->dev;
5487 drm_i915_private_t *dev_priv = dev->dev_private;
5488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5489 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5490 int dpll_reg = DPLL(pipe);
5491 int dpll;
652c393a 5492
bad720ff 5493 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5494 return;
5495
5496 if (!dev_priv->lvds_downclock_avail)
5497 return;
5498
dbdc6479 5499 dpll = I915_READ(dpll_reg);
652c393a 5500 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5501 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 5502
8ac5a6d5 5503 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 5504
5505 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5506 I915_WRITE(dpll_reg, dpll);
9d0498a2 5507 intel_wait_for_vblank(dev, pipe);
dbdc6479 5508
652c393a
JB		 5509 dpll = I915_READ(dpll_reg);
5510 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5511 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 5512 }
5513
5514 /* Schedule downclock */
3dec0095
DV		 5515 mod_timer(&intel_crtc->idle_timer, jiffies +
5516 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 5517}
5518
5519static void intel_decrease_pllclock(struct drm_crtc *crtc)
5520{
5521 struct drm_device *dev = crtc->dev;
5522 drm_i915_private_t *dev_priv = dev->dev_private;
5523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 5524
bad720ff 5525 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5526 return;
5527
5528 if (!dev_priv->lvds_downclock_avail)
5529 return;
5530
5531 /*
5532 * Since this is called by a timer, we should never get here in
5533 * the manual case.
5534 */
5535 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 5536 int pipe = intel_crtc->pipe;
5537 int dpll_reg = DPLL(pipe);
5538 int dpll;
f6e5b160 5539
44d98a61 5540 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 5541
8ac5a6d5 5542 assert_panel_unlocked(dev_priv, pipe);
652c393a 5543
dc257cf1 5544 dpll = I915_READ(dpll_reg);
652c393a
JB		 5545 dpll |= DISPLAY_RATE_SELECT_FPA1;
5546 I915_WRITE(dpll_reg, dpll);
9d0498a2 5547 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 5548 dpll = I915_READ(dpll_reg);
5549 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 5550 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 5551 }
5552
5553}
5554
5555/**
5556 * intel_idle_update - adjust clocks for idleness
5557 * @work: work struct
5558 *
5559 * Either the GPU or display (or both) went idle. Check the busy status
5560 * here and adjust the CRTC and GPU clocks as necessary.
5561 */
5562static void intel_idle_update(struct work_struct *work)
5563{
5564 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5565 idle_work);
5566 struct drm_device *dev = dev_priv->dev;
5567 struct drm_crtc *crtc;
5568 struct intel_crtc *intel_crtc;
5569
5570 if (!i915_powersave)
5571 return;
5572
5573 mutex_lock(&dev->struct_mutex);
5574
7648fa99
JB		 5575 i915_update_gfx_val(dev_priv);
5576
652c393a
JB		 5577 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5578 /* Skip inactive CRTCs */
5579 if (!crtc->fb)
5580 continue;
5581
5582 intel_crtc = to_intel_crtc(crtc);
5583 if (!intel_crtc->busy)
5584 intel_decrease_pllclock(crtc);
5585 }
5586
45ac22c8 5587
652c393a
JB		 5588 mutex_unlock(&dev->struct_mutex);
5589}
5590
5591/**
5592 * intel_mark_busy - mark the GPU and possibly the display busy
5593 * @dev: drm device
5594 * @obj: object we're operating on
5595 *
5596 * Callers can use this function to indicate that the GPU is busy processing
5597 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5598 * buffer), we'll also mark the display as busy, so we know to increase its
5599 * clock frequency.
5600 */
05394f39 5601void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 5602{
5603 drm_i915_private_t *dev_priv = dev->dev_private;
5604 struct drm_crtc *crtc = NULL;
5605 struct intel_framebuffer *intel_fb;
5606 struct intel_crtc *intel_crtc;
5607
5e17ee74
ZW		 5608 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5609 return;
5610
9104183d
CW		 5611 if (!dev_priv->busy) {
5612 intel_sanitize_pm(dev);
28cf798f 5613 dev_priv->busy = true;
9104183d 5614 } else
28cf798f
CW		 5615 mod_timer(&dev_priv->idle_timer, jiffies +
5616 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a 5617
acb87dfb
CW		 5618 if (obj == NULL)
5619 return;
5620
652c393a
JB		 5621 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5622 if (!crtc->fb)
5623 continue;
5624
5625 intel_crtc = to_intel_crtc(crtc);
5626 intel_fb = to_intel_framebuffer(crtc->fb);
5627 if (intel_fb->obj == obj) {
5628 if (!intel_crtc->busy) {
5629 /* Non-busy -> busy, upclock */
3dec0095 5630 intel_increase_pllclock(crtc);
652c393a
JB		 5631 intel_crtc->busy = true;
5632 } else {
5633 /* Busy -> busy, put off timer */
5634 mod_timer(&intel_crtc->idle_timer, jiffies +
5635 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5636 }
5637 }
5638 }
5639}
5640
79e53945
JB		 5641static void intel_crtc_destroy(struct drm_crtc *crtc)
5642{
5643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 5644 struct drm_device *dev = crtc->dev;
5645 struct intel_unpin_work *work;
5646 unsigned long flags;
5647
5648 spin_lock_irqsave(&dev->event_lock, flags);
5649 work = intel_crtc->unpin_work;
5650 intel_crtc->unpin_work = NULL;
5651 spin_unlock_irqrestore(&dev->event_lock, flags);
5652
5653 if (work) {
5654 cancel_work_sync(&work->work);
5655 kfree(work);
5656 }
79e53945
JB		 5657
5658 drm_crtc_cleanup(crtc);
67e77c5a 5659
79e53945
JB		 5660 kfree(intel_crtc);
5661}
5662
6b95a207
KH		 5663static void intel_unpin_work_fn(struct work_struct *__work)
5664{
5665 struct intel_unpin_work *work =
5666 container_of(__work, struct intel_unpin_work, work);
5667
5668 mutex_lock(&work->dev->struct_mutex);
1690e1eb 5669 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 5670 drm_gem_object_unreference(&work->pending_flip_obj->base);
5671 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 5672
7782de3b 5673 intel_update_fbc(work->dev);
6b95a207
KH		 5674 mutex_unlock(&work->dev->struct_mutex);
5675 kfree(work);
5676}
5677
1afe3e9d 5678static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 5679 struct drm_crtc *crtc)
6b95a207
KH		 5680{
5681 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 5682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5683 struct intel_unpin_work *work;
05394f39 5684 struct drm_i915_gem_object *obj;
6b95a207 5685 struct drm_pending_vblank_event *e;
49b14a5c 5686 struct timeval tnow, tvbl;
6b95a207
KH		 5687 unsigned long flags;
5688
5689 /* Ignore early vblank irqs */
5690 if (intel_crtc == NULL)
5691 return;
5692
49b14a5c
MK		 5693 do_gettimeofday(&tnow);
5694
6b95a207
KH		 5695 spin_lock_irqsave(&dev->event_lock, flags);
5696 work = intel_crtc->unpin_work;
5697 if (work == NULL || !work->pending) {
5698 spin_unlock_irqrestore(&dev->event_lock, flags);
5699 return;
5700 }
5701
5702 intel_crtc->unpin_work = NULL;
6b95a207
KH		 5703
5704 if (work->event) {
5705 e = work->event;
49b14a5c 5706 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 5707
5708 /* Called before vblank count and timestamps have
5709 * been updated for the vblank interval of flip
5710 * completion? Need to increment vblank count and
5711 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 5712 * to account for this. We assume this happened if we
5713 * get called over 0.9 frame durations after the last
5714 * timestamped vblank.
5715 *
5716 * This calculation can not be used with vrefresh rates
5717 * below 5Hz (10Hz to be on the safe side) without
5718 * promoting to 64 integers.
0af7e4df 5719 */
49b14a5c
MK		 5720 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5721 9 * crtc->framedur_ns) {
0af7e4df 5722 e->event.sequence++;
49b14a5c
MK		 5723 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5724 crtc->framedur_ns);
0af7e4df
MK		 5725 }
5726
49b14a5c
MK		 5727 e->event.tv_sec = tvbl.tv_sec;
5728 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 5729
6b95a207
KH		 5730 list_add_tail(&e->base.link,
5731 &e->base.file_priv->event_list);
5732 wake_up_interruptible(&e->base.file_priv->event_wait);
5733 }
5734
0af7e4df
MK		 5735 drm_vblank_put(dev, intel_crtc->pipe);
5736
6b95a207
KH		 5737 spin_unlock_irqrestore(&dev->event_lock, flags);
5738
05394f39 5739 obj = work->old_fb_obj;
d9e86c0e 5740
e59f2bac 5741 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 5742 &obj->pending_flip.counter);
5743 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 5744 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 5745
6b95a207 5746 schedule_work(&work->work);
e5510fac
JB		 5747
5748 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 5749}
5750
1afe3e9d
JB		 5751void intel_finish_page_flip(struct drm_device *dev, int pipe)
5752{
5753 drm_i915_private_t *dev_priv = dev->dev_private;
5754 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5755
49b14a5c 5756 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 5757}
5758
5759void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5760{
5761 drm_i915_private_t *dev_priv = dev->dev_private;
5762 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5763
49b14a5c 5764 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 5765}
5766
6b95a207
KH		 5767void intel_prepare_page_flip(struct drm_device *dev, int plane)
5768{
5769 drm_i915_private_t *dev_priv = dev->dev_private;
5770 struct intel_crtc *intel_crtc =
5771 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5772 unsigned long flags;
5773
5774 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 5775 if (intel_crtc->unpin_work) {
4e5359cd
SF		 5776 if ((++intel_crtc->unpin_work->pending) > 1)
5777 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 5778 } else {
5779 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5780 }
6b95a207
KH		 5781 spin_unlock_irqrestore(&dev->event_lock, flags);
5782}
5783
8c9f3aaf
JB		 5784static int intel_gen2_queue_flip(struct drm_device *dev,
5785 struct drm_crtc *crtc,
5786 struct drm_framebuffer *fb,
5787 struct drm_i915_gem_object *obj)
5788{
5789 struct drm_i915_private *dev_priv = dev->dev_private;
5790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5791 unsigned long offset;
5792 u32 flip_mask;
6d90c952 5793 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5794 int ret;
5795
6d90c952 5796 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5797 if (ret)
83d4092b 5798 goto err;
8c9f3aaf
JB		 5799
5800 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 5801 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf 5802
6d90c952 5803 ret = intel_ring_begin(ring, 6);
8c9f3aaf 5804 if (ret)
83d4092b 5805 goto err_unpin;
8c9f3aaf
JB		 5806
5807 /* Can't queue multiple flips, so wait for the previous
5808 * one to finish before executing the next.
5809 */
5810 if (intel_crtc->plane)
5811 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5812 else
5813 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 5814 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5815 intel_ring_emit(ring, MI_NOOP);
5816 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5817 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5818 intel_ring_emit(ring, fb->pitches[0]);
5819 intel_ring_emit(ring, obj->gtt_offset + offset);
5820 intel_ring_emit(ring, 0); /* aux display base address, unused */
5821 intel_ring_advance(ring);
83d4092b
CW		 5822 return 0;
5823
5824err_unpin:
5825 intel_unpin_fb_obj(obj);
5826err:
8c9f3aaf
JB		 5827 return ret;
5828}
5829
5830static int intel_gen3_queue_flip(struct drm_device *dev,
5831 struct drm_crtc *crtc,
5832 struct drm_framebuffer *fb,
5833 struct drm_i915_gem_object *obj)
5834{
5835 struct drm_i915_private *dev_priv = dev->dev_private;
5836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5837 unsigned long offset;
5838 u32 flip_mask;
6d90c952 5839 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5840 int ret;
5841
6d90c952 5842 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5843 if (ret)
83d4092b 5844 goto err;
8c9f3aaf
JB		 5845
5846 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 5847 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf 5848
6d90c952 5849 ret = intel_ring_begin(ring, 6);
8c9f3aaf 5850 if (ret)
83d4092b 5851 goto err_unpin;
8c9f3aaf
JB		 5852
5853 if (intel_crtc->plane)
5854 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5855 else
5856 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 5857 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5858 intel_ring_emit(ring, MI_NOOP);
5859 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
5860 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5861 intel_ring_emit(ring, fb->pitches[0]);
5862 intel_ring_emit(ring, obj->gtt_offset + offset);
5863 intel_ring_emit(ring, MI_NOOP);
5864
5865 intel_ring_advance(ring);
83d4092b
CW		 5866 return 0;
5867
5868err_unpin:
5869 intel_unpin_fb_obj(obj);
5870err:
8c9f3aaf
JB		 5871 return ret;
5872}
5873
5874static int intel_gen4_queue_flip(struct drm_device *dev,
5875 struct drm_crtc *crtc,
5876 struct drm_framebuffer *fb,
5877 struct drm_i915_gem_object *obj)
5878{
5879 struct drm_i915_private *dev_priv = dev->dev_private;
5880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5881 uint32_t pf, pipesrc;
6d90c952 5882 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5883 int ret;
5884
6d90c952 5885 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5886 if (ret)
83d4092b 5887 goto err;
8c9f3aaf 5888
6d90c952 5889 ret = intel_ring_begin(ring, 4);
8c9f3aaf 5890 if (ret)
83d4092b 5891 goto err_unpin;
8c9f3aaf
JB		 5892
5893 /* i965+ uses the linear or tiled offsets from the
5894 * Display Registers (which do not change across a page-flip)
5895 * so we need only reprogram the base address.
5896 */
6d90c952
DV		 5897 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5898 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5899 intel_ring_emit(ring, fb->pitches[0]);
5900 intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
8c9f3aaf
JB		 5901
5902 /* XXX Enabling the panel-fitter across page-flip is so far
5903 * untested on non-native modes, so ignore it for now.
5904 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5905 */
5906 pf = 0;
5907 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 5908 intel_ring_emit(ring, pf | pipesrc);
5909 intel_ring_advance(ring);
83d4092b
CW		 5910 return 0;
5911
5912err_unpin:
5913 intel_unpin_fb_obj(obj);
5914err:
8c9f3aaf
JB		 5915 return ret;
5916}
5917
5918static int intel_gen6_queue_flip(struct drm_device *dev,
5919 struct drm_crtc *crtc,
5920 struct drm_framebuffer *fb,
5921 struct drm_i915_gem_object *obj)
5922{
5923 struct drm_i915_private *dev_priv = dev->dev_private;
5924 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 5925 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5926 uint32_t pf, pipesrc;
5927 int ret;
5928
6d90c952 5929 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5930 if (ret)
83d4092b 5931 goto err;
8c9f3aaf 5932
6d90c952 5933 ret = intel_ring_begin(ring, 4);
8c9f3aaf 5934 if (ret)
83d4092b 5935 goto err_unpin;
8c9f3aaf 5936
6d90c952
DV		 5937 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5938 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5939 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
5940 intel_ring_emit(ring, obj->gtt_offset);
8c9f3aaf 5941
dc257cf1
DV		 5942 /* Contrary to the suggestions in the documentation,
5943 * "Enable Panel Fitter" does not seem to be required when page
5944 * flipping with a non-native mode, and worse causes a normal
5945 * modeset to fail.
5946 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
5947 */
5948 pf = 0;
8c9f3aaf 5949 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 5950 intel_ring_emit(ring, pf | pipesrc);
5951 intel_ring_advance(ring);
83d4092b
CW		 5952 return 0;
5953
5954err_unpin:
5955 intel_unpin_fb_obj(obj);
5956err:
8c9f3aaf
JB		 5957 return ret;
5958}
5959
7c9017e5
JB		 5960/*
5961 * On gen7 we currently use the blit ring because (in early silicon at least)
5962 * the render ring doesn't give us interrpts for page flip completion, which
5963 * means clients will hang after the first flip is queued. Fortunately the
5964 * blit ring generates interrupts properly, so use it instead.
5965 */
5966static int intel_gen7_queue_flip(struct drm_device *dev,
5967 struct drm_crtc *crtc,
5968 struct drm_framebuffer *fb,
5969 struct drm_i915_gem_object *obj)
5970{
5971 struct drm_i915_private *dev_priv = dev->dev_private;
5972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5973 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
5974 int ret;
5975
5976 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5977 if (ret)
83d4092b 5978 goto err;
7c9017e5
JB		 5979
5980 ret = intel_ring_begin(ring, 4);
5981 if (ret)
83d4092b 5982 goto err_unpin;
7c9017e5
JB		 5983
5984 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 5985 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 5986 intel_ring_emit(ring, (obj->gtt_offset));
5987 intel_ring_emit(ring, (MI_NOOP));
5988 intel_ring_advance(ring);
83d4092b
CW		 5989 return 0;
5990
5991err_unpin:
5992 intel_unpin_fb_obj(obj);
5993err:
7c9017e5
JB		 5994 return ret;
5995}
5996
8c9f3aaf
JB		 5997static int intel_default_queue_flip(struct drm_device *dev,
5998 struct drm_crtc *crtc,
5999 struct drm_framebuffer *fb,
6000 struct drm_i915_gem_object *obj)
6001{
6002 return -ENODEV;
6003}
6004
6b95a207
KH		 6005static int intel_crtc_page_flip(struct drm_crtc *crtc,
6006 struct drm_framebuffer *fb,
6007 struct drm_pending_vblank_event *event)
6008{
6009 struct drm_device *dev = crtc->dev;
6010 struct drm_i915_private *dev_priv = dev->dev_private;
6011 struct intel_framebuffer *intel_fb;
05394f39 6012 struct drm_i915_gem_object *obj;
6b95a207
KH		 6013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6014 struct intel_unpin_work *work;
8c9f3aaf 6015 unsigned long flags;
52e68630 6016 int ret;
6b95a207
KH		 6017
6018 work = kzalloc(sizeof *work, GFP_KERNEL);
6019 if (work == NULL)
6020 return -ENOMEM;
6021
6b95a207
KH		 6022 work->event = event;
6023 work->dev = crtc->dev;
6024 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6025 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6026 INIT_WORK(&work->work, intel_unpin_work_fn);
6027
7317c75e
JB		 6028 ret = drm_vblank_get(dev, intel_crtc->pipe);
6029 if (ret)
6030 goto free_work;
6031
6b95a207
KH		 6032 /* We borrow the event spin lock for protecting unpin_work */
6033 spin_lock_irqsave(&dev->event_lock, flags);
6034 if (intel_crtc->unpin_work) {
6035 spin_unlock_irqrestore(&dev->event_lock, flags);
6036 kfree(work);
7317c75e 6037 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6038
6039 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6040 return -EBUSY;
6041 }
6042 intel_crtc->unpin_work = work;
6043 spin_unlock_irqrestore(&dev->event_lock, flags);
6044
6045 intel_fb = to_intel_framebuffer(fb);
6046 obj = intel_fb->obj;
6047
468f0b44 6048 mutex_lock(&dev->struct_mutex);
6b95a207 6049
75dfca80 6050 /* Reference the objects for the scheduled work. */
05394f39
CW		 6051 drm_gem_object_reference(&work->old_fb_obj->base);
6052 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6053
6054 crtc->fb = fb;
96b099fd 6055
e1f99ce6 6056 work->pending_flip_obj = obj;
e1f99ce6 6057
4e5359cd
SF		 6058 work->enable_stall_check = true;
6059
e1f99ce6
CW		 6060 /* Block clients from rendering to the new back buffer until
6061 * the flip occurs and the object is no longer visible.
6062 */
05394f39 6063 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6064
8c9f3aaf
JB		 6065 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6066 if (ret)
6067 goto cleanup_pending;
6b95a207 6068
7782de3b 6069 intel_disable_fbc(dev);
acb87dfb 6070 intel_mark_busy(dev, obj);
6b95a207
KH		 6071 mutex_unlock(&dev->struct_mutex);
6072
e5510fac
JB		 6073 trace_i915_flip_request(intel_crtc->plane, obj);
6074
6b95a207 6075 return 0;
96b099fd 6076
8c9f3aaf
JB		 6077cleanup_pending:
6078 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6079 drm_gem_object_unreference(&work->old_fb_obj->base);
6080 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6081 mutex_unlock(&dev->struct_mutex);
6082
6083 spin_lock_irqsave(&dev->event_lock, flags);
6084 intel_crtc->unpin_work = NULL;
6085 spin_unlock_irqrestore(&dev->event_lock, flags);
6086
7317c75e
JB		 6087 drm_vblank_put(dev, intel_crtc->pipe);
6088free_work:
96b099fd
CW		 6089 kfree(work);
6090
6091 return ret;
6b95a207
KH		 6092}
6093
47f1c6c9
CW		 6094static void intel_sanitize_modesetting(struct drm_device *dev,
6095 int pipe, int plane)
6096{
6097 struct drm_i915_private *dev_priv = dev->dev_private;
6098 u32 reg, val;
6099
f47166d2
CW		 6100 /* Clear any frame start delays used for debugging left by the BIOS */
6101 for_each_pipe(pipe) {
6102 reg = PIPECONF(pipe);
6103 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6104 }
6105
47f1c6c9
CW		 6106 if (HAS_PCH_SPLIT(dev))
6107 return;
6108
6109 /* Who knows what state these registers were left in by the BIOS or
6110 * grub?
6111 *
6112 * If we leave the registers in a conflicting state (e.g. with the
6113 * display plane reading from the other pipe than the one we intend
6114 * to use) then when we attempt to teardown the active mode, we will
6115 * not disable the pipes and planes in the correct order -- leaving
6116 * a plane reading from a disabled pipe and possibly leading to
6117 * undefined behaviour.
6118 */
6119
6120 reg = DSPCNTR(plane);
6121 val = I915_READ(reg);
6122
6123 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6124 return;
6125 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6126 return;
6127
6128 /* This display plane is active and attached to the other CPU pipe. */
6129 pipe = !pipe;
6130
6131 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6132 intel_disable_plane(dev_priv, plane, pipe);
6133 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6134}
79e53945 6135
f6e5b160
CW		 6136static void intel_crtc_reset(struct drm_crtc *crtc)
6137{
6138 struct drm_device *dev = crtc->dev;
6139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6140
6141 /* Reset flags back to the 'unknown' status so that they
6142 * will be correctly set on the initial modeset.
6143 */
6144 intel_crtc->dpms_mode = -1;
6145
6146 /* We need to fix up any BIOS configuration that conflicts with
6147 * our expectations.
6148 */
6149 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6150}
6151
6152static struct drm_crtc_helper_funcs intel_helper_funcs = {
6153 .dpms = intel_crtc_dpms,
6154 .mode_fixup = intel_crtc_mode_fixup,
6155 .mode_set = intel_crtc_mode_set,
6156 .mode_set_base = intel_pipe_set_base,
6157 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6158 .load_lut = intel_crtc_load_lut,
6159 .disable = intel_crtc_disable,
6160};
6161
6162static const struct drm_crtc_funcs intel_crtc_funcs = {
6163 .reset = intel_crtc_reset,
6164 .cursor_set = intel_crtc_cursor_set,
6165 .cursor_move = intel_crtc_cursor_move,
6166 .gamma_set = intel_crtc_gamma_set,
6167 .set_config = drm_crtc_helper_set_config,
6168 .destroy = intel_crtc_destroy,
6169 .page_flip = intel_crtc_page_flip,
6170};
6171
ee7b9f93
JB		 6172static void intel_pch_pll_init(struct drm_device *dev)
6173{
6174 drm_i915_private_t *dev_priv = dev->dev_private;
6175 int i;
6176
6177 if (dev_priv->num_pch_pll == 0) {
6178 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6179 return;
6180 }
6181
6182 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6183 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6184 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6185 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6186 }
6187}
6188
b358d0a6 6189static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6190{
22fd0fab 6191 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6192 struct intel_crtc *intel_crtc;
6193 int i;
6194
6195 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6196 if (intel_crtc == NULL)
6197 return;
6198
6199 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6200
6201 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6202 for (i = 0; i < 256; i++) {
6203 intel_crtc->lut_r[i] = i;
6204 intel_crtc->lut_g[i] = i;
6205 intel_crtc->lut_b[i] = i;
6206 }
6207
80824003
JB		 6208 /* Swap pipes & planes for FBC on pre-965 */
6209 intel_crtc->pipe = pipe;
6210 intel_crtc->plane = pipe;
e2e767ab 6211 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6212 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6213 intel_crtc->plane = !pipe;
80824003
JB		 6214 }
6215
22fd0fab
JB		 6216 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6217 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6218 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6219 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6220
5d1d0cc8 6221 intel_crtc_reset(&intel_crtc->base);
04dbff52 6222 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 6223 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 6224
6225 if (HAS_PCH_SPLIT(dev)) {
6226 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6227 intel_helper_funcs.commit = ironlake_crtc_commit;
6228 } else {
6229 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6230 intel_helper_funcs.commit = i9xx_crtc_commit;
6231 }
6232
79e53945
JB		 6233 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6234
652c393a
JB		 6235 intel_crtc->busy = false;
6236
6237 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6238 (unsigned long)intel_crtc);
79e53945
JB		 6239}
6240
08d7b3d1 6241int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6242 struct drm_file *file)
08d7b3d1 6243{
08d7b3d1 6244 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6245 struct drm_mode_object *drmmode_obj;
6246 struct intel_crtc *crtc;
08d7b3d1 6247
1cff8f6b
DV		 6248 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6249 return -ENODEV;
08d7b3d1 6250
c05422d5
DV		 6251 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6252 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6253
c05422d5 6254 if (!drmmode_obj) {
08d7b3d1
CW		 6255 DRM_ERROR("no such CRTC id\n");
6256 return -EINVAL;
6257 }
6258
c05422d5
DV		 6259 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6260 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6261
c05422d5 6262 return 0;
08d7b3d1
CW		 6263}
6264
c5e4df33 6265static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6266{
4ef69c7a 6267 struct intel_encoder *encoder;
79e53945 6268 int index_mask = 0;
79e53945
JB		 6269 int entry = 0;
6270
4ef69c7a
CW		 6271 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6272 if (type_mask & encoder->clone_mask)
79e53945
JB		 6273 index_mask |= (1 << entry);
6274 entry++;
6275 }
4ef69c7a 6276
79e53945
JB		 6277 return index_mask;
6278}
6279
4d302442
CW		 6280static bool has_edp_a(struct drm_device *dev)
6281{
6282 struct drm_i915_private *dev_priv = dev->dev_private;
6283
6284 if (!IS_MOBILE(dev))
6285 return false;
6286
6287 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6288 return false;
6289
6290 if (IS_GEN5(dev) &&
6291 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6292 return false;
6293
6294 return true;
6295}
6296
79e53945
JB		 6297static void intel_setup_outputs(struct drm_device *dev)
6298{
725e30ad 6299 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6300 struct intel_encoder *encoder;
cb0953d7 6301 bool dpd_is_edp = false;
f3cfcba6 6302 bool has_lvds;
79e53945 6303
f3cfcba6 6304 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 6305 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6306 /* disable the panel fitter on everything but LVDS */
6307 I915_WRITE(PFIT_CONTROL, 0);
6308 }
79e53945 6309
bad720ff 6310 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6311 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6312
4d302442 6313 if (has_edp_a(dev))
32f9d658
ZW		 6314 intel_dp_init(dev, DP_A);
6315
cb0953d7
AJ		 6316 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6317 intel_dp_init(dev, PCH_DP_D);
6318 }
6319
6320 intel_crt_init(dev);
6321
6322 if (HAS_PCH_SPLIT(dev)) {
6323 int found;
6324
30ad48b7 6325 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 6326 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 6327 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7
ZW		 6328 if (!found)
6329 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6330 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6331 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6332 }
6333
6334 if (I915_READ(HDMIC) & PORT_DETECTED)
6335 intel_hdmi_init(dev, HDMIC);
6336
6337 if (I915_READ(HDMID) & PORT_DETECTED)
6338 intel_hdmi_init(dev, HDMID);
6339
5eb08b69
ZW		 6340 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6341 intel_dp_init(dev, PCH_DP_C);
6342
cb0953d7 6343 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6344 intel_dp_init(dev, PCH_DP_D);
6345
103a196f 6346 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6347 bool found = false;
7d57382e 6348
725e30ad 6349 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6350 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 6351 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 6352 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6353 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6354 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6355 }
27185ae1 6356
b01f2c3a
JB		 6357 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6358 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6359 intel_dp_init(dev, DP_B);
b01f2c3a 6360 }
725e30ad 6361 }
13520b05
KH		 6362
6363 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6364
b01f2c3a
JB		 6365 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6366 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 6367 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 6368 }
27185ae1
ML		 6369
6370 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6371
b01f2c3a
JB		 6372 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6373 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6374 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6375 }
6376 if (SUPPORTS_INTEGRATED_DP(dev)) {
6377 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6378 intel_dp_init(dev, DP_C);
b01f2c3a 6379 }
725e30ad 6380 }
27185ae1 6381
b01f2c3a
JB		 6382 if (SUPPORTS_INTEGRATED_DP(dev) &&
6383 (I915_READ(DP_D) & DP_DETECTED)) {
6384 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6385 intel_dp_init(dev, DP_D);
b01f2c3a 6386 }
bad720ff 6387 } else if (IS_GEN2(dev))
79e53945
JB		 6388 intel_dvo_init(dev);
6389
103a196f 6390 if (SUPPORTS_TV(dev))
79e53945
JB		 6391 intel_tv_init(dev);
6392
4ef69c7a
CW		 6393 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6394 encoder->base.possible_crtcs = encoder->crtc_mask;
6395 encoder->base.possible_clones =
6396 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6397 }
47356eb6 6398
2c7111db
CW		 6399 /* disable all the possible outputs/crtcs before entering KMS mode */
6400 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 6401
6402 if (HAS_PCH_SPLIT(dev))
6403 ironlake_init_pch_refclk(dev);
79e53945
JB		 6404}
6405
6406static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6407{
6408 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6409
6410 drm_framebuffer_cleanup(fb);
05394f39 6411 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6412
6413 kfree(intel_fb);
6414}
6415
6416static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6417 struct drm_file *file,
79e53945
JB		 6418 unsigned int *handle)
6419{
6420 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6421 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6422
05394f39 6423 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6424}
6425
6426static const struct drm_framebuffer_funcs intel_fb_funcs = {
6427 .destroy = intel_user_framebuffer_destroy,
6428 .create_handle = intel_user_framebuffer_create_handle,
6429};
6430
38651674
DA		 6431int intel_framebuffer_init(struct drm_device *dev,
6432 struct intel_framebuffer *intel_fb,
308e5bcb 6433 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 6434 struct drm_i915_gem_object *obj)
79e53945 6435{
79e53945
JB		 6436 int ret;
6437
05394f39 6438 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6439 return -EINVAL;
6440
308e5bcb 6441 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 6442 return -EINVAL;
6443
308e5bcb 6444 switch (mode_cmd->pixel_format) {
04b3924d
VS		 6445 case DRM_FORMAT_RGB332:
6446 case DRM_FORMAT_RGB565:
6447 case DRM_FORMAT_XRGB8888:
b250da79 6448 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 6449 case DRM_FORMAT_ARGB8888:
6450 case DRM_FORMAT_XRGB2101010:
6451 case DRM_FORMAT_ARGB2101010:
308e5bcb 6452 /* RGB formats are common across chipsets */
b5626747 6453 break;
04b3924d
VS		 6454 case DRM_FORMAT_YUYV:
6455 case DRM_FORMAT_UYVY:
6456 case DRM_FORMAT_YVYU:
6457 case DRM_FORMAT_VYUY:
57cd6508
CW		 6458 break;
6459 default:
aca25848
ED		 6460 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6461 mode_cmd->pixel_format);
57cd6508
CW		 6462 return -EINVAL;
6463 }
6464
79e53945
JB		 6465 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6466 if (ret) {
6467 DRM_ERROR("framebuffer init failed %d\n", ret);
6468 return ret;
6469 }
6470
6471 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6472 intel_fb->obj = obj;
79e53945
JB		 6473 return 0;
6474}
6475
79e53945
JB		 6476static struct drm_framebuffer *
6477intel_user_framebuffer_create(struct drm_device *dev,
6478 struct drm_file *filp,
308e5bcb 6479 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 6480{
05394f39 6481 struct drm_i915_gem_object *obj;
79e53945 6482
308e5bcb
JB		 6483 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6484 mode_cmd->handles[0]));
c8725226 6485 if (&obj->base == NULL)
cce13ff7 6486 return ERR_PTR(-ENOENT);
79e53945 6487
d2dff872 6488 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6489}
6490
79e53945 6491static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6492 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6493 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6494};
6495
e70236a8
JB		 6496/* Set up chip specific display functions */
6497static void intel_init_display(struct drm_device *dev)
6498{
6499 struct drm_i915_private *dev_priv = dev->dev_private;
6500
6501 /* We always want a DPMS function */
f564048e 6502 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 6503 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 6504 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
ee7b9f93 6505 dev_priv->display.off = ironlake_crtc_off;
17638cd6 6506 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 6507 } else {
e70236a8 6508 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 6509 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
ee7b9f93 6510 dev_priv->display.off = i9xx_crtc_off;
17638cd6 6511 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 6512 }
e70236a8 6513
e70236a8 6514 /* Returns the core display clock speed */
25eb05fc
JB		 6515 if (IS_VALLEYVIEW(dev))
6516 dev_priv->display.get_display_clock_speed =
6517 valleyview_get_display_clock_speed;
6518 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 6519 dev_priv->display.get_display_clock_speed =
6520 i945_get_display_clock_speed;
6521 else if (IS_I915G(dev))
6522 dev_priv->display.get_display_clock_speed =
6523 i915_get_display_clock_speed;
f2b115e6 6524 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 6525 dev_priv->display.get_display_clock_speed =
6526 i9xx_misc_get_display_clock_speed;
6527 else if (IS_I915GM(dev))
6528 dev_priv->display.get_display_clock_speed =
6529 i915gm_get_display_clock_speed;
6530 else if (IS_I865G(dev))
6531 dev_priv->display.get_display_clock_speed =
6532 i865_get_display_clock_speed;
f0f8a9ce 6533 else if (IS_I85X(dev))
e70236a8
JB		 6534 dev_priv->display.get_display_clock_speed =
6535 i855_get_display_clock_speed;
6536 else /* 852, 830 */
6537 dev_priv->display.get_display_clock_speed =
6538 i830_get_display_clock_speed;
6539
7f8a8569 6540 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 6541 if (IS_GEN5(dev)) {
674cf967 6542 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 6543 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 6544 } else if (IS_GEN6(dev)) {
674cf967 6545 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 6546 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 6547 } else if (IS_IVYBRIDGE(dev)) {
6548 /* FIXME: detect B0+ stepping and use auto training */
6549 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 6550 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 6551 } else
6552 dev_priv->display.update_wm = NULL;
ceb04246 6553 } else if (IS_VALLEYVIEW(dev)) {
575155a9
JB		 6554 dev_priv->display.force_wake_get = vlv_force_wake_get;
6555 dev_priv->display.force_wake_put = vlv_force_wake_put;
6067aaea 6556 } else if (IS_G4X(dev)) {
e0dac65e 6557 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 6558 }
8c9f3aaf
JB		 6559
6560 /* Default just returns -ENODEV to indicate unsupported */
6561 dev_priv->display.queue_flip = intel_default_queue_flip;
6562
6563 switch (INTEL_INFO(dev)->gen) {
6564 case 2:
6565 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6566 break;
6567
6568 case 3:
6569 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6570 break;
6571
6572 case 4:
6573 case 5:
6574 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6575 break;
6576
6577 case 6:
6578 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6579 break;
7c9017e5
JB		 6580 case 7:
6581 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6582 break;
8c9f3aaf 6583 }
e70236a8
JB		 6584}
6585
b690e96c
JB		 6586/*
6587 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6588 * resume, or other times. This quirk makes sure that's the case for
6589 * affected systems.
6590 */
0206e353 6591static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 6592{
6593 struct drm_i915_private *dev_priv = dev->dev_private;
6594
6595 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 6596 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 6597}
6598
435793df
KP		 6599/*
6600 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6601 */
6602static void quirk_ssc_force_disable(struct drm_device *dev)
6603{
6604 struct drm_i915_private *dev_priv = dev->dev_private;
6605 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 6606 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 6607}
6608
4dca20ef 6609/*
5a15ab5b
CE		 6610 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6611 * brightness value
4dca20ef
CE		 6612 */
6613static void quirk_invert_brightness(struct drm_device *dev)
6614{
6615 struct drm_i915_private *dev_priv = dev->dev_private;
6616 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 6617 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 6618}
6619
b690e96c
JB		 6620struct intel_quirk {
6621 int device;
6622 int subsystem_vendor;
6623 int subsystem_device;
6624 void (*hook)(struct drm_device *dev);
6625};
6626
c43b5634 6627static struct intel_quirk intel_quirks[] = {
b690e96c 6628 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 6629 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 6630
6631 /* Thinkpad R31 needs pipe A force quirk */
6632 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6633 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6634 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6635
6636 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6637 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6638 /* ThinkPad X40 needs pipe A force quirk */
6639
6640 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6641 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6642
6643 /* 855 & before need to leave pipe A & dpll A up */
6644 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6645 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 6646
6647 /* Lenovo U160 cannot use SSC on LVDS */
6648 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 6649
6650 /* Sony Vaio Y cannot use SSC on LVDS */
6651 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 6652
6653 /* Acer Aspire 5734Z must invert backlight brightness */
6654 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 6655};
6656
6657static void intel_init_quirks(struct drm_device *dev)
6658{
6659 struct pci_dev *d = dev->pdev;
6660 int i;
6661
6662 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6663 struct intel_quirk *q = &intel_quirks[i];
6664
6665 if (d->device == q->device &&
6666 (d->subsystem_vendor == q->subsystem_vendor ||
6667 q->subsystem_vendor == PCI_ANY_ID) &&
6668 (d->subsystem_device == q->subsystem_device ||
6669 q->subsystem_device == PCI_ANY_ID))
6670 q->hook(dev);
6671 }
6672}
6673
9cce37f4
JB		 6674/* Disable the VGA plane that we never use */
6675static void i915_disable_vga(struct drm_device *dev)
6676{
6677 struct drm_i915_private *dev_priv = dev->dev_private;
6678 u8 sr1;
6679 u32 vga_reg;
6680
6681 if (HAS_PCH_SPLIT(dev))
6682 vga_reg = CPU_VGACNTRL;
6683 else
6684 vga_reg = VGACNTRL;
6685
6686 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 6687 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 6688 sr1 = inb(VGA_SR_DATA);
6689 outb(sr1 | 1<<5, VGA_SR_DATA);
6690 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6691 udelay(300);
6692
6693 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6694 POSTING_READ(vga_reg);
6695}
6696
f82cfb6b
JB		 6697static void ivb_pch_pwm_override(struct drm_device *dev)
6698{
6699 struct drm_i915_private *dev_priv = dev->dev_private;
6700
6701 /*
6702 * IVB has CPU eDP backlight regs too, set things up to let the
6703 * PCH regs control the backlight
6704 */
6705 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6706 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6707 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6708}
6709
f817586c
DV		 6710void intel_modeset_init_hw(struct drm_device *dev)
6711{
6712 struct drm_i915_private *dev_priv = dev->dev_private;
6713
6714 intel_init_clock_gating(dev);
6715
6716 if (IS_IRONLAKE_M(dev)) {
6717 ironlake_enable_drps(dev);
1833b134 6718 ironlake_enable_rc6(dev);
f817586c
DV		 6719 intel_init_emon(dev);
6720 }
6721
b6834bd6 6722 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
f817586c
DV		 6723 gen6_enable_rps(dev_priv);
6724 gen6_update_ring_freq(dev_priv);
6725 }
f82cfb6b
JB		 6726
6727 if (IS_IVYBRIDGE(dev))
6728 ivb_pch_pwm_override(dev);
f817586c
DV		 6729}
6730
79e53945
JB		 6731void intel_modeset_init(struct drm_device *dev)
6732{
652c393a 6733 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 6734 int i, ret;
79e53945
JB		 6735
6736 drm_mode_config_init(dev);
6737
6738 dev->mode_config.min_width = 0;
6739 dev->mode_config.min_height = 0;
6740
019d96cb
DA		 6741 dev->mode_config.preferred_depth = 24;
6742 dev->mode_config.prefer_shadow = 1;
6743
79e53945
JB		 6744 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6745
b690e96c
JB		 6746 intel_init_quirks(dev);
6747
1fa61106
ED		 6748 intel_init_pm(dev);
6749
e70236a8
JB		 6750 intel_init_display(dev);
6751
a6c45cf0
CW		 6752 if (IS_GEN2(dev)) {
6753 dev->mode_config.max_width = 2048;
6754 dev->mode_config.max_height = 2048;
6755 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 6756 dev->mode_config.max_width = 4096;
6757 dev->mode_config.max_height = 4096;
79e53945 6758 } else {
a6c45cf0
CW		 6759 dev->mode_config.max_width = 8192;
6760 dev->mode_config.max_height = 8192;
79e53945 6761 }
35c3047a 6762 dev->mode_config.fb_base = dev->agp->base;
79e53945 6763
28c97730 6764 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 6765 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 6766
a3524f1b 6767 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 6768 intel_crtc_init(dev, i);
00c2064b
JB		 6769 ret = intel_plane_init(dev, i);
6770 if (ret)
6771 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 6772 }
6773
ee7b9f93
JB		 6774 intel_pch_pll_init(dev);
6775
9cce37f4
JB		 6776 /* Just disable it once at startup */
6777 i915_disable_vga(dev);
79e53945 6778 intel_setup_outputs(dev);
652c393a 6779
652c393a
JB		 6780 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6781 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6782 (unsigned long)dev);
2c7111db
CW		 6783}
6784
6785void intel_modeset_gem_init(struct drm_device *dev)
6786{
1833b134 6787 intel_modeset_init_hw(dev);
02e792fb
DV		 6788
6789 intel_setup_overlay(dev);
79e53945
JB		 6790}
6791
6792void intel_modeset_cleanup(struct drm_device *dev)
6793{
652c393a
JB		 6794 struct drm_i915_private *dev_priv = dev->dev_private;
6795 struct drm_crtc *crtc;
6796 struct intel_crtc *intel_crtc;
6797
f87ea761 6798 drm_kms_helper_poll_fini(dev);
652c393a
JB		 6799 mutex_lock(&dev->struct_mutex);
6800
723bfd70
JB		 6801 intel_unregister_dsm_handler();
6802
6803
652c393a
JB		 6804 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6805 /* Skip inactive CRTCs */
6806 if (!crtc->fb)
6807 continue;
6808
6809 intel_crtc = to_intel_crtc(crtc);
3dec0095 6810 intel_increase_pllclock(crtc);
652c393a
JB		 6811 }
6812
973d04f9 6813 intel_disable_fbc(dev);
e70236a8 6814
f97108d1
JB		 6815 if (IS_IRONLAKE_M(dev))
6816 ironlake_disable_drps(dev);
b6834bd6 6817 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
3b8d8d91 6818 gen6_disable_rps(dev);
f97108d1 6819
d5bb081b
JB		 6820 if (IS_IRONLAKE_M(dev))
6821 ironlake_disable_rc6(dev);
0cdab21f 6822
57f350b6
JB		 6823 if (IS_VALLEYVIEW(dev))
6824 vlv_init_dpio(dev);
6825
69341a5e
KH		 6826 mutex_unlock(&dev->struct_mutex);
6827
6c0d9350
DV		 6828 /* Disable the irq before mode object teardown, for the irq might
6829 * enqueue unpin/hotplug work. */
6830 drm_irq_uninstall(dev);
6831 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 6832 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 6833
1630fe75
CW		 6834 /* flush any delayed tasks or pending work */
6835 flush_scheduled_work();
6836
3dec0095
DV		 6837 /* Shut off idle work before the crtcs get freed. */
6838 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6839 intel_crtc = to_intel_crtc(crtc);
6840 del_timer_sync(&intel_crtc->idle_timer);
6841 }
6842 del_timer_sync(&dev_priv->idle_timer);
6843 cancel_work_sync(&dev_priv->idle_work);
6844
79e53945
JB		 6845 drm_mode_config_cleanup(dev);
6846}
6847
f1c79df3
ZW		 6848/*
6849 * Return which encoder is currently attached for connector.
6850 */
df0e9248 6851struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 6852{
df0e9248
CW		 6853 return &intel_attached_encoder(connector)->base;
6854}
f1c79df3 6855
df0e9248
CW		 6856void intel_connector_attach_encoder(struct intel_connector *connector,
6857 struct intel_encoder *encoder)
6858{
6859 connector->encoder = encoder;
6860 drm_mode_connector_attach_encoder(&connector->base,
6861 &encoder->base);
79e53945 6862}
28d52043
DA		 6863
6864/*
6865 * set vga decode state - true == enable VGA decode
6866 */
6867int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6868{
6869 struct drm_i915_private *dev_priv = dev->dev_private;
6870 u16 gmch_ctrl;
6871
6872 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6873 if (state)
6874 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6875 else
6876 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6877 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6878 return 0;
6879}
c4a1d9e4
CW		 6880
6881#ifdef CONFIG_DEBUG_FS
6882#include <linux/seq_file.h>
6883
6884struct intel_display_error_state {
6885 struct intel_cursor_error_state {
6886 u32 control;
6887 u32 position;
6888 u32 base;
6889 u32 size;
6890 } cursor[2];
6891
6892 struct intel_pipe_error_state {
6893 u32 conf;
6894 u32 source;
6895
6896 u32 htotal;
6897 u32 hblank;
6898 u32 hsync;
6899 u32 vtotal;
6900 u32 vblank;
6901 u32 vsync;
6902 } pipe[2];
6903
6904 struct intel_plane_error_state {
6905 u32 control;
6906 u32 stride;
6907 u32 size;
6908 u32 pos;
6909 u32 addr;
6910 u32 surface;
6911 u32 tile_offset;
6912 } plane[2];
6913};
6914
6915struct intel_display_error_state *
6916intel_display_capture_error_state(struct drm_device *dev)
6917{
0206e353 6918 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 6919 struct intel_display_error_state *error;
6920 int i;
6921
6922 error = kmalloc(sizeof(*error), GFP_ATOMIC);
6923 if (error == NULL)
6924 return NULL;
6925
6926 for (i = 0; i < 2; i++) {
6927 error->cursor[i].control = I915_READ(CURCNTR(i));
6928 error->cursor[i].position = I915_READ(CURPOS(i));
6929 error->cursor[i].base = I915_READ(CURBASE(i));
6930
6931 error->plane[i].control = I915_READ(DSPCNTR(i));
6932 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6933 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 6934 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 6935 error->plane[i].addr = I915_READ(DSPADDR(i));
6936 if (INTEL_INFO(dev)->gen >= 4) {
6937 error->plane[i].surface = I915_READ(DSPSURF(i));
6938 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6939 }
6940
6941 error->pipe[i].conf = I915_READ(PIPECONF(i));
6942 error->pipe[i].source = I915_READ(PIPESRC(i));
6943 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6944 error->pipe[i].hblank = I915_READ(HBLANK(i));
6945 error->pipe[i].hsync = I915_READ(HSYNC(i));
6946 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6947 error->pipe[i].vblank = I915_READ(VBLANK(i));
6948 error->pipe[i].vsync = I915_READ(VSYNC(i));
6949 }
6950
6951 return error;
6952}
6953
6954void
6955intel_display_print_error_state(struct seq_file *m,
6956 struct drm_device *dev,
6957 struct intel_display_error_state *error)
6958{
6959 int i;
6960
6961 for (i = 0; i < 2; i++) {
6962 seq_printf(m, "Pipe [%d]:\n", i);
6963 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
6964 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
6965 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
6966 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
6967 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
6968 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
6969 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
6970 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
6971
6972 seq_printf(m, "Plane [%d]:\n", i);
6973 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
6974 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
6975 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
6976 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
6977 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
6978 if (INTEL_INFO(dev)->gen >= 4) {
6979 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
6980 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
6981 }
6982
6983 seq_printf(m, "Cursor [%d]:\n", i);
6984 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
6985 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
6986 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
6987 }
6988}
6989#endif
Linux kernel - Deliverables
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