projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Store power sequencer delays in intel_dp
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
5ca476f8 228pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 286 struct intel_dp *intel_dp);
bf13e81b
JN		 287static void
288intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 289 struct intel_dp *intel_dp);
bf13e81b 290
773538e8
VS		 291static void pps_lock(struct intel_dp *intel_dp)
292{
293 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
294 struct intel_encoder *encoder = &intel_dig_port->base;
295 struct drm_device *dev = encoder->base.dev;
296 struct drm_i915_private *dev_priv = dev->dev_private;
297 enum intel_display_power_domain power_domain;
298
299 /*
300 * See vlv_power_sequencer_reset() why we need
301 * a power domain reference here.
302 */
303 power_domain = intel_display_port_power_domain(encoder);
304 intel_display_power_get(dev_priv, power_domain);
305
306 mutex_lock(&dev_priv->pps_mutex);
307}
308
309static void pps_unlock(struct intel_dp *intel_dp)
310{
311 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
312 struct intel_encoder *encoder = &intel_dig_port->base;
313 struct drm_device *dev = encoder->base.dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315 enum intel_display_power_domain power_domain;
316
317 mutex_unlock(&dev_priv->pps_mutex);
318
319 power_domain = intel_display_port_power_domain(encoder);
320 intel_display_power_put(dev_priv, power_domain);
321}
322
bf13e81b
JN		 323static enum pipe
324vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
325{
326 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 327 struct drm_device *dev = intel_dig_port->base.base.dev;
328 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 329 struct intel_encoder *encoder;
330 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
bf13e81b 331
e39b999a 332 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 333
a4a5d2f8
VS		 334 if (intel_dp->pps_pipe != INVALID_PIPE)
335 return intel_dp->pps_pipe;
336
337 /*
338 * We don't have power sequencer currently.
339 * Pick one that's not used by other ports.
340 */
341 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
342 base.head) {
343 struct intel_dp *tmp;
344
345 if (encoder->type != INTEL_OUTPUT_EDP)
346 continue;
347
348 tmp = enc_to_intel_dp(&encoder->base);
349
350 if (tmp->pps_pipe != INVALID_PIPE)
351 pipes &= ~(1 << tmp->pps_pipe);
352 }
353
354 /*
355 * Didn't find one. This should not happen since there
356 * are two power sequencers and up to two eDP ports.
357 */
358 if (WARN_ON(pipes == 0))
359 return PIPE_A;
360
361 intel_dp->pps_pipe = ffs(pipes) - 1;
362
363 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
364 pipe_name(intel_dp->pps_pipe),
365 port_name(intel_dig_port->port));
366
367 /* init power sequencer on this pipe and port */
36b5f425
VS		 368 intel_dp_init_panel_power_sequencer(dev, intel_dp);
369 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 370
371 return intel_dp->pps_pipe;
372}
373
6491ab27
VS		 374typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
375 enum pipe pipe);
376
377static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
378 enum pipe pipe)
379{
380 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
381}
382
383static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
384 enum pipe pipe)
385{
386 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
387}
388
389static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
390 enum pipe pipe)
391{
392 return true;
393}
bf13e81b 394
a4a5d2f8 395static enum pipe
6491ab27
VS		 396vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
397 enum port port,
398 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 399{
400 enum pipe pipe;
bf13e81b 401
bf13e81b
JN		 402 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
403 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
404 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 405
406 if (port_sel != PANEL_PORT_SELECT_VLV(port))
407 continue;
408
6491ab27
VS		 409 if (!pipe_check(dev_priv, pipe))
410 continue;
411
a4a5d2f8 412 return pipe;
bf13e81b
JN		 413 }
414
a4a5d2f8
VS		 415 return INVALID_PIPE;
416}
417
418static void
419vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
420{
421 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
422 struct drm_device *dev = intel_dig_port->base.base.dev;
423 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 424 enum port port = intel_dig_port->port;
425
426 lockdep_assert_held(&dev_priv->pps_mutex);
427
428 /* try to find a pipe with this port selected */
6491ab27
VS		 429 /* first pick one where the panel is on */
430 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
431 vlv_pipe_has_pp_on);
432 /* didn't find one? pick one where vdd is on */
433 if (intel_dp->pps_pipe == INVALID_PIPE)
434 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
435 vlv_pipe_has_vdd_on);
436 /* didn't find one? pick one with just the correct port */
437 if (intel_dp->pps_pipe == INVALID_PIPE)
438 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
439 vlv_pipe_any);
a4a5d2f8
VS		 440
441 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
442 if (intel_dp->pps_pipe == INVALID_PIPE) {
443 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
444 port_name(port));
445 return;
bf13e81b
JN		 446 }
447
a4a5d2f8
VS		 448 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
449 port_name(port), pipe_name(intel_dp->pps_pipe));
450
36b5f425
VS		 451 intel_dp_init_panel_power_sequencer(dev, intel_dp);
452 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 453}
454
773538e8
VS		 455void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
456{
457 struct drm_device *dev = dev_priv->dev;
458 struct intel_encoder *encoder;
459
460 if (WARN_ON(!IS_VALLEYVIEW(dev)))
461 return;
462
463 /*
464 * We can't grab pps_mutex here due to deadlock with power_domain
465 * mutex when power_domain functions are called while holding pps_mutex.
466 * That also means that in order to use pps_pipe the code needs to
467 * hold both a power domain reference and pps_mutex, and the power domain
468 * reference get/put must be done while _not_ holding pps_mutex.
469 * pps_{lock,unlock}() do these steps in the correct order, so one
470 * should use them always.
471 */
472
473 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
474 struct intel_dp *intel_dp;
475
476 if (encoder->type != INTEL_OUTPUT_EDP)
477 continue;
478
479 intel_dp = enc_to_intel_dp(&encoder->base);
480 intel_dp->pps_pipe = INVALID_PIPE;
481 }
bf13e81b
JN		 482}
483
484static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
485{
486 struct drm_device *dev = intel_dp_to_dev(intel_dp);
487
488 if (HAS_PCH_SPLIT(dev))
489 return PCH_PP_CONTROL;
490 else
491 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
492}
493
494static u32 _pp_stat_reg(struct intel_dp *intel_dp)
495{
496 struct drm_device *dev = intel_dp_to_dev(intel_dp);
497
498 if (HAS_PCH_SPLIT(dev))
499 return PCH_PP_STATUS;
500 else
501 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
502}
503
01527b31
CT		 504/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
505 This function only applicable when panel PM state is not to be tracked */
506static int edp_notify_handler(struct notifier_block *this, unsigned long code,
507 void *unused)
508{
509 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
510 edp_notifier);
511 struct drm_device *dev = intel_dp_to_dev(intel_dp);
512 struct drm_i915_private *dev_priv = dev->dev_private;
513 u32 pp_div;
514 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 515
516 if (!is_edp(intel_dp) || code != SYS_RESTART)
517 return 0;
518
773538e8 519 pps_lock(intel_dp);
e39b999a 520
01527b31 521 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 522 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
523
01527b31
CT		 524 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
525 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
526 pp_div = I915_READ(pp_div_reg);
527 pp_div &= PP_REFERENCE_DIVIDER_MASK;
528
529 /* 0x1F write to PP_DIV_REG sets max cycle delay */
530 I915_WRITE(pp_div_reg, pp_div | 0x1F);
531 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
532 msleep(intel_dp->panel_power_cycle_delay);
533 }
534
773538e8 535 pps_unlock(intel_dp);
e39b999a 536
01527b31
CT		 537 return 0;
538}
539
4be73780 540static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 541{
30add22d 542 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 543 struct drm_i915_private *dev_priv = dev->dev_private;
544
e39b999a
VS		 545 lockdep_assert_held(&dev_priv->pps_mutex);
546
bf13e81b 547 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 548}
549
4be73780 550static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 551{
30add22d 552 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 553 struct drm_i915_private *dev_priv = dev->dev_private;
554
e39b999a
VS		 555 lockdep_assert_held(&dev_priv->pps_mutex);
556
773538e8 557 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 558}
559
9b984dae
KP		 560static void
561intel_dp_check_edp(struct intel_dp *intel_dp)
562{
30add22d 563 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 564 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 565
9b984dae
KP		 566 if (!is_edp(intel_dp))
567 return;
453c5420 568
4be73780 569 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 570 WARN(1, "eDP powered off while attempting aux channel communication.\n");
571 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 572 I915_READ(_pp_stat_reg(intel_dp)),
573 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 574 }
575}
576
9ee32fea
DV		 577static uint32_t
578intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
579{
580 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
581 struct drm_device *dev = intel_dig_port->base.base.dev;
582 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 583 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 584 uint32_t status;
585 bool done;
586
ef04f00d 587#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 588 if (has_aux_irq)
b18ac466 589 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 590 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 591 else
592 done = wait_for_atomic(C, 10) == 0;
593 if (!done)
594 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
595 has_aux_irq);
596#undef C
597
598 return status;
599}
600
ec5b01dd 601static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 602{
174edf1f
PZ		 603 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
604 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 605
ec5b01dd
DL		 606 /*
607 * The clock divider is based off the hrawclk, and would like to run at
608 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 609 */
ec5b01dd
DL		 610 return index ? 0 : intel_hrawclk(dev) / 2;
611}
612
613static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
614{
615 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
616 struct drm_device *dev = intel_dig_port->base.base.dev;
617
618 if (index)
619 return 0;
620
621 if (intel_dig_port->port == PORT_A) {
622 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 623 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 624 else
b84a1cf8 625 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 626 } else {
627 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
628 }
629}
630
631static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
632{
633 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
634 struct drm_device *dev = intel_dig_port->base.base.dev;
635 struct drm_i915_private *dev_priv = dev->dev_private;
636
637 if (intel_dig_port->port == PORT_A) {
638 if (index)
639 return 0;
640 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 641 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
642 /* Workaround for non-ULT HSW */
bc86625a
CW		 643 switch (index) {
644 case 0: return 63;
645 case 1: return 72;
646 default: return 0;
647 }
ec5b01dd 648 } else {
bc86625a 649 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 650 }
b84a1cf8
RV		 651}
652
ec5b01dd
DL		 653static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
654{
655 return index ? 0 : 100;
656}
657
b6b5e383
DL		 658static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
659{
660 /*
661 * SKL doesn't need us to program the AUX clock divider (Hardware will
662 * derive the clock from CDCLK automatically). We still implement the
663 * get_aux_clock_divider vfunc to plug-in into the existing code.
664 */
665 return index ? 0 : 1;
666}
667
5ed12a19
DL		 668static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
669 bool has_aux_irq,
670 int send_bytes,
671 uint32_t aux_clock_divider)
672{
673 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
674 struct drm_device *dev = intel_dig_port->base.base.dev;
675 uint32_t precharge, timeout;
676
677 if (IS_GEN6(dev))
678 precharge = 3;
679 else
680 precharge = 5;
681
682 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
683 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
684 else
685 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
686
687 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 688 DP_AUX_CH_CTL_DONE |
5ed12a19 689 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 690 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 691 timeout |
788d4433 692 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 693 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
694 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 695 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 696}
697
b9ca5fad
DL		 698static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
699 bool has_aux_irq,
700 int send_bytes,
701 uint32_t unused)
702{
703 return DP_AUX_CH_CTL_SEND_BUSY |
704 DP_AUX_CH_CTL_DONE |
705 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
706 DP_AUX_CH_CTL_TIME_OUT_ERROR |
707 DP_AUX_CH_CTL_TIME_OUT_1600us |
708 DP_AUX_CH_CTL_RECEIVE_ERROR |
709 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
710 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
711}
712
b84a1cf8
RV		 713static int
714intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 715 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 716 uint8_t *recv, int recv_size)
717{
718 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
719 struct drm_device *dev = intel_dig_port->base.base.dev;
720 struct drm_i915_private *dev_priv = dev->dev_private;
721 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
722 uint32_t ch_data = ch_ctl + 4;
bc86625a 723 uint32_t aux_clock_divider;
b84a1cf8
RV		 724 int i, ret, recv_bytes;
725 uint32_t status;
5ed12a19 726 int try, clock = 0;
4e6b788c 727 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 728 bool vdd;
729
773538e8 730 pps_lock(intel_dp);
e39b999a 731
72c3500a
VS		 732 /*
733 * We will be called with VDD already enabled for dpcd/edid/oui reads.
734 * In such cases we want to leave VDD enabled and it's up to upper layers
735 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
736 * ourselves.
737 */
1e0560e0 738 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 739
740 /* dp aux is extremely sensitive to irq latency, hence request the
741 * lowest possible wakeup latency and so prevent the cpu from going into
742 * deep sleep states.
743 */
744 pm_qos_update_request(&dev_priv->pm_qos, 0);
745
746 intel_dp_check_edp(intel_dp);
5eb08b69 747
c67a470b
PZ		 748 intel_aux_display_runtime_get(dev_priv);
749
11bee43e
JB		 750 /* Try to wait for any previous AUX channel activity */
751 for (try = 0; try < 3; try++) {
ef04f00d 752 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 753 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
754 break;
755 msleep(1);
756 }
757
758 if (try == 3) {
759 WARN(1, "dp_aux_ch not started status 0x%08x\n",
760 I915_READ(ch_ctl));
9ee32fea
DV		 761 ret = -EBUSY;
762 goto out;
4f7f7b7e
CW		 763 }
764
46a5ae9f
PZ		 765 /* Only 5 data registers! */
766 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
767 ret = -E2BIG;
768 goto out;
769 }
770
ec5b01dd 771 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 772 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
773 has_aux_irq,
774 send_bytes,
775 aux_clock_divider);
5ed12a19 776
bc86625a
CW		 777 /* Must try at least 3 times according to DP spec */
778 for (try = 0; try < 5; try++) {
779 /* Load the send data into the aux channel data registers */
780 for (i = 0; i < send_bytes; i += 4)
781 I915_WRITE(ch_data + i,
782 pack_aux(send + i, send_bytes - i));
783
784 /* Send the command and wait for it to complete */
5ed12a19 785 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 786
787 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
788
789 /* Clear done status and any errors */
790 I915_WRITE(ch_ctl,
791 status |
792 DP_AUX_CH_CTL_DONE |
793 DP_AUX_CH_CTL_TIME_OUT_ERROR |
794 DP_AUX_CH_CTL_RECEIVE_ERROR);
795
796 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
797 DP_AUX_CH_CTL_RECEIVE_ERROR))
798 continue;
799 if (status & DP_AUX_CH_CTL_DONE)
800 break;
801 }
4f7f7b7e 802 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 803 break;
804 }
805
a4fc5ed6 806 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 807 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 808 ret = -EBUSY;
809 goto out;
a4fc5ed6
KP		 810 }
811
812 /* Check for timeout or receive error.
813 * Timeouts occur when the sink is not connected
814 */
a5b3da54 815 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 816 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 817 ret = -EIO;
818 goto out;
a5b3da54 819 }
1ae8c0a5
KP		 820
821 /* Timeouts occur when the device isn't connected, so they're
822 * "normal" -- don't fill the kernel log with these */
a5b3da54 823 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 824 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 825 ret = -ETIMEDOUT;
826 goto out;
a4fc5ed6
KP		 827 }
828
829 /* Unload any bytes sent back from the other side */
830 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
831 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 832 if (recv_bytes > recv_size)
833 recv_bytes = recv_size;
0206e353 834
4f7f7b7e
CW		 835 for (i = 0; i < recv_bytes; i += 4)
836 unpack_aux(I915_READ(ch_data + i),
837 recv + i, recv_bytes - i);
a4fc5ed6 838
9ee32fea
DV		 839 ret = recv_bytes;
840out:
841 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 842 intel_aux_display_runtime_put(dev_priv);
9ee32fea 843
884f19e9
JN		 844 if (vdd)
845 edp_panel_vdd_off(intel_dp, false);
846
773538e8 847 pps_unlock(intel_dp);
e39b999a 848
9ee32fea 849 return ret;
a4fc5ed6
KP		 850}
851
a6c8aff0
JN		 852#define BARE_ADDRESS_SIZE 3
853#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 854static ssize_t
855intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 856{
9d1a1031
JN		 857 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
858 uint8_t txbuf[20], rxbuf[20];
859 size_t txsize, rxsize;
a4fc5ed6 860 int ret;
a4fc5ed6 861
9d1a1031
JN		 862 txbuf[0] = msg->request << 4;
863 txbuf[1] = msg->address >> 8;
864 txbuf[2] = msg->address & 0xff;
865 txbuf[3] = msg->size - 1;
46a5ae9f 866
9d1a1031
JN		 867 switch (msg->request & ~DP_AUX_I2C_MOT) {
868 case DP_AUX_NATIVE_WRITE:
869 case DP_AUX_I2C_WRITE:
a6c8aff0 870 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 871 rxsize = 1;
f51a44b9 872
9d1a1031
JN		 873 if (WARN_ON(txsize > 20))
874 return -E2BIG;
a4fc5ed6 875
9d1a1031 876 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 877
9d1a1031
JN		 878 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
879 if (ret > 0) {
880 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 881
9d1a1031
JN		 882 /* Return payload size. */
883 ret = msg->size;
884 }
885 break;
46a5ae9f 886
9d1a1031
JN		 887 case DP_AUX_NATIVE_READ:
888 case DP_AUX_I2C_READ:
a6c8aff0 889 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 890 rxsize = msg->size + 1;
a4fc5ed6 891
9d1a1031
JN		 892 if (WARN_ON(rxsize > 20))
893 return -E2BIG;
a4fc5ed6 894
9d1a1031
JN		 895 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
896 if (ret > 0) {
897 msg->reply = rxbuf[0] >> 4;
898 /*
899 * Assume happy day, and copy the data. The caller is
900 * expected to check msg->reply before touching it.
901 *
902 * Return payload size.
903 */
904 ret--;
905 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 906 }
9d1a1031
JN		 907 break;
908
909 default:
910 ret = -EINVAL;
911 break;
a4fc5ed6 912 }
f51a44b9 913
9d1a1031 914 return ret;
a4fc5ed6
KP		 915}
916
9d1a1031
JN		 917static void
918intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
919{
920 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 921 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
922 enum port port = intel_dig_port->port;
0b99836f 923 const char *name = NULL;
ab2c0672
DA		 924 int ret;
925
33ad6626
JN		 926 switch (port) {
927 case PORT_A:
928 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 929 name = "DPDDC-A";
ab2c0672 930 break;
33ad6626
JN		 931 case PORT_B:
932 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 933 name = "DPDDC-B";
ab2c0672 934 break;
33ad6626
JN		 935 case PORT_C:
936 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 937 name = "DPDDC-C";
ab2c0672 938 break;
33ad6626
JN		 939 case PORT_D:
940 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 941 name = "DPDDC-D";
33ad6626
JN		 942 break;
943 default:
944 BUG();
ab2c0672
DA		 945 }
946
1b1aad75
DL		 947 /*
948 * The AUX_CTL register is usually DP_CTL + 0x10.
949 *
950 * On Haswell and Broadwell though:
951 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
952 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
953 *
954 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
955 */
956 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 957 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 958
0b99836f 959 intel_dp->aux.name = name;
9d1a1031
JN		 960 intel_dp->aux.dev = dev->dev;
961 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 962
0b99836f
JN		 963 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
964 connector->base.kdev->kobj.name);
8316f337 965
4f71d0cb 966 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 967 if (ret < 0) {
4f71d0cb 968 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 969 name, ret);
970 return;
ab2c0672 971 }
8a5e6aeb 972
0b99836f
JN		 973 ret = sysfs_create_link(&connector->base.kdev->kobj,
974 &intel_dp->aux.ddc.dev.kobj,
975 intel_dp->aux.ddc.dev.kobj.name);
976 if (ret < 0) {
977 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 978 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 979 }
a4fc5ed6
KP		 980}
981
80f65de3
ID		 982static void
983intel_dp_connector_unregister(struct intel_connector *intel_connector)
984{
985 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
986
0e32b39c
DA		 987 if (!intel_connector->mst_port)
988 sysfs_remove_link(&intel_connector->base.kdev->kobj,
989 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 990 intel_connector_unregister(intel_connector);
991}
992
0e50338c
DV		 993static void
994hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
995{
996 switch (link_bw) {
997 case DP_LINK_BW_1_62:
998 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
999 break;
1000 case DP_LINK_BW_2_7:
1001 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1002 break;
1003 case DP_LINK_BW_5_4:
1004 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1005 break;
1006 }
1007}
1008
c6bb3538
DV		 1009static void
1010intel_dp_set_clock(struct intel_encoder *encoder,
1011 struct intel_crtc_config *pipe_config, int link_bw)
1012{
1013 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1014 const struct dp_link_dpll *divisor = NULL;
1015 int i, count = 0;
c6bb3538
DV		 1016
1017 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1018 divisor = gen4_dpll;
1019 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1020 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1021 divisor = pch_dpll;
1022 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1023 } else if (IS_CHERRYVIEW(dev)) {
1024 divisor = chv_dpll;
1025 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1026 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1027 divisor = vlv_dpll;
1028 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1029 }
9dd4ffdf
CML		 1030
1031 if (divisor && count) {
1032 for (i = 0; i < count; i++) {
1033 if (link_bw == divisor[i].link_bw) {
1034 pipe_config->dpll = divisor[i].dpll;
1035 pipe_config->clock_set = true;
1036 break;
1037 }
1038 }
c6bb3538
DV		 1039 }
1040}
1041
00c09d70 1042bool
5bfe2ac0
DV		 1043intel_dp_compute_config(struct intel_encoder *encoder,
1044 struct intel_crtc_config *pipe_config)
a4fc5ed6 1045{
5bfe2ac0 1046 struct drm_device *dev = encoder->base.dev;
36008365 1047 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1048 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1049 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1050 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1051 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1052 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1053 int lane_count, clock;
56071a20 1054 int min_lane_count = 1;
eeb6324d 1055 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1056 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1057 int min_clock = 0;
06ea66b6 1058 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1059 int bpp, mode_rate;
06ea66b6 1060 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1061 int link_avail, link_clock;
a4fc5ed6 1062
bc7d38a4 1063 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1064 pipe_config->has_pch_encoder = true;
1065
03afc4a2 1066 pipe_config->has_dp_encoder = true;
f769cd24 1067 pipe_config->has_drrs = false;
9ed109a7 1068 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1069
dd06f90e
JN		 1070 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1071 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1072 adjusted_mode);
2dd24552
JB		 1073 if (!HAS_PCH_SPLIT(dev))
1074 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1075 intel_connector->panel.fitting_mode);
1076 else
b074cec8
JB		 1077 intel_pch_panel_fitting(intel_crtc, pipe_config,
1078 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1079 }
1080
cb1793ce 1081 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1082 return false;
1083
083f9560
DV		 1084 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1085 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1086 max_lane_count, bws[max_clock],
1087 adjusted_mode->crtc_clock);
083f9560 1088
36008365
DV		 1089 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1090 * bpc in between. */
3e7ca985 1091 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1092 if (is_edp(intel_dp)) {
1093 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1094 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1095 dev_priv->vbt.edp_bpp);
1096 bpp = dev_priv->vbt.edp_bpp;
1097 }
1098
344c5bbc
JN		 1099 /*
1100 * Use the maximum clock and number of lanes the eDP panel
1101 * advertizes being capable of. The panels are generally
1102 * designed to support only a single clock and lane
1103 * configuration, and typically these values correspond to the
1104 * native resolution of the panel.
1105 */
1106 min_lane_count = max_lane_count;
1107 min_clock = max_clock;
7984211e 1108 }
657445fe 1109
36008365 1110 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1111 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1112 bpp);
36008365 1113
c6930992
DA		 1114 for (clock = min_clock; clock <= max_clock; clock++) {
1115 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1116 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1117 link_avail = intel_dp_max_data_rate(link_clock,
1118 lane_count);
1119
1120 if (mode_rate <= link_avail) {
1121 goto found;
1122 }
1123 }
1124 }
1125 }
c4867936 1126
36008365 1127 return false;
3685a8f3 1128
36008365 1129found:
55bc60db
VS		 1130 if (intel_dp->color_range_auto) {
1131 /*
1132 * See:
1133 * CEA-861-E - 5.1 Default Encoding Parameters
1134 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1135 */
18316c8c 1136 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1137 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1138 else
1139 intel_dp->color_range = 0;
1140 }
1141
3685a8f3 1142 if (intel_dp->color_range)
50f3b016 1143 pipe_config->limited_color_range = true;
a4fc5ed6 1144
36008365
DV		 1145 intel_dp->link_bw = bws[clock];
1146 intel_dp->lane_count = lane_count;
657445fe 1147 pipe_config->pipe_bpp = bpp;
ff9a6750 1148 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1149
36008365
DV		 1150 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1151 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1152 pipe_config->port_clock, bpp);
36008365
DV		 1153 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1154 mode_rate, link_avail);
a4fc5ed6 1155
03afc4a2 1156 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1157 adjusted_mode->crtc_clock,
1158 pipe_config->port_clock,
03afc4a2 1159 &pipe_config->dp_m_n);
9d1a455b 1160
439d7ac0
PB		 1161 if (intel_connector->panel.downclock_mode != NULL &&
1162 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1163 pipe_config->has_drrs = true;
439d7ac0
PB		 1164 intel_link_compute_m_n(bpp, lane_count,
1165 intel_connector->panel.downclock_mode->clock,
1166 pipe_config->port_clock,
1167 &pipe_config->dp_m2_n2);
1168 }
1169
ea155f32 1170 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1171 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1172 else
1173 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1174
03afc4a2 1175 return true;
a4fc5ed6
KP		 1176}
1177
7c62a164 1178static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1179{
7c62a164
DV		 1180 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1181 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1182 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1183 struct drm_i915_private *dev_priv = dev->dev_private;
1184 u32 dpa_ctl;
1185
ff9a6750 1186 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1187 dpa_ctl = I915_READ(DP_A);
1188 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1189
ff9a6750 1190 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1191 /* For a long time we've carried around a ILK-DevA w/a for the
1192 * 160MHz clock. If we're really unlucky, it's still required.
1193 */
1194 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1195 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1196 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1197 } else {
1198 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1199 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1200 }
1ce17038 1201
ea9b6006
DV		 1202 I915_WRITE(DP_A, dpa_ctl);
1203
1204 POSTING_READ(DP_A);
1205 udelay(500);
1206}
1207
8ac33ed3 1208static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1209{
b934223d 1210 struct drm_device *dev = encoder->base.dev;
417e822d 1211 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1212 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1213 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1214 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1215 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1216
417e822d 1217 /*
1a2eb460 1218 * There are four kinds of DP registers:
417e822d
KP		 1219 *
1220 * IBX PCH
1a2eb460
KP		 1221 * SNB CPU
1222 * IVB CPU
417e822d
KP		 1223 * CPT PCH
1224 *
1225 * IBX PCH and CPU are the same for almost everything,
1226 * except that the CPU DP PLL is configured in this
1227 * register
1228 *
1229 * CPT PCH is quite different, having many bits moved
1230 * to the TRANS_DP_CTL register instead. That
1231 * configuration happens (oddly) in ironlake_pch_enable
1232 */
9c9e7927 1233
417e822d
KP		 1234 /* Preserve the BIOS-computed detected bit. This is
1235 * supposed to be read-only.
1236 */
1237 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1238
417e822d 1239 /* Handle DP bits in common between all three register formats */
417e822d 1240 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1241 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1242
9ed109a7 1243 if (crtc->config.has_audio) {
e0dac65e 1244 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1245 pipe_name(crtc->pipe));
ea5b213a 1246 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
33d1e7c6 1247 intel_write_eld(encoder);
e0dac65e 1248 }
247d89f6 1249
417e822d 1250 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1251
bc7d38a4 1252 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1253 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1254 intel_dp->DP |= DP_SYNC_HS_HIGH;
1255 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1256 intel_dp->DP |= DP_SYNC_VS_HIGH;
1257 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1258
6aba5b6c 1259 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1260 intel_dp->DP |= DP_ENHANCED_FRAMING;
1261
7c62a164 1262 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1263 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1264 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1265 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1266
1267 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1268 intel_dp->DP |= DP_SYNC_HS_HIGH;
1269 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1270 intel_dp->DP |= DP_SYNC_VS_HIGH;
1271 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1272
6aba5b6c 1273 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1274 intel_dp->DP |= DP_ENHANCED_FRAMING;
1275
44f37d1f
CML		 1276 if (!IS_CHERRYVIEW(dev)) {
1277 if (crtc->pipe == 1)
1278 intel_dp->DP |= DP_PIPEB_SELECT;
1279 } else {
1280 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1281 }
417e822d
KP		 1282 } else {
1283 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1284 }
a4fc5ed6
KP		 1285}
1286
ffd6749d
PZ		 1287#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1288#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1289
1a5ef5b7
PZ		 1290#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1291#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1292
ffd6749d
PZ		 1293#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1294#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1295
4be73780 1296static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1297 u32 mask,
1298 u32 value)
bd943159 1299{
30add22d 1300 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1301 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1302 u32 pp_stat_reg, pp_ctrl_reg;
1303
e39b999a
VS		 1304 lockdep_assert_held(&dev_priv->pps_mutex);
1305
bf13e81b
JN		 1306 pp_stat_reg = _pp_stat_reg(intel_dp);
1307 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1308
99ea7127 1309 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1310 mask, value,
1311 I915_READ(pp_stat_reg),
1312 I915_READ(pp_ctrl_reg));
32ce697c 1313
453c5420 1314 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1315 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1316 I915_READ(pp_stat_reg),
1317 I915_READ(pp_ctrl_reg));
32ce697c 1318 }
54c136d4
CW		 1319
1320 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1321}
32ce697c 1322
4be73780 1323static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1324{
1325 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1326 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1327}
1328
4be73780 1329static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1330{
1331 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1332 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1333}
1334
4be73780 1335static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1336{
1337 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1338
1339 /* When we disable the VDD override bit last we have to do the manual
1340 * wait. */
1341 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1342 intel_dp->panel_power_cycle_delay);
1343
4be73780 1344 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1345}
1346
4be73780 1347static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1348{
1349 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1350 intel_dp->backlight_on_delay);
1351}
1352
4be73780 1353static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1354{
1355 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1356 intel_dp->backlight_off_delay);
1357}
99ea7127 1358
832dd3c1
KP		 1359/* Read the current pp_control value, unlocking the register if it
1360 * is locked
1361 */
1362
453c5420 1363static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1364{
453c5420
JB		 1365 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 u32 control;
832dd3c1 1368
e39b999a
VS		 1369 lockdep_assert_held(&dev_priv->pps_mutex);
1370
bf13e81b 1371 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1372 control &= ~PANEL_UNLOCK_MASK;
1373 control |= PANEL_UNLOCK_REGS;
1374 return control;
bd943159
KP		 1375}
1376
951468f3
VS		 1377/*
1378 * Must be paired with edp_panel_vdd_off().
1379 * Must hold pps_mutex around the whole on/off sequence.
1380 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1381 */
1e0560e0 1382static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1383{
30add22d 1384 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1385 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1386 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1387 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1388 enum intel_display_power_domain power_domain;
5d613501 1389 u32 pp;
453c5420 1390 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1391 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1392
e39b999a
VS		 1393 lockdep_assert_held(&dev_priv->pps_mutex);
1394
97af61f5 1395 if (!is_edp(intel_dp))
adddaaf4 1396 return false;
bd943159
KP		 1397
1398 intel_dp->want_panel_vdd = true;
99ea7127 1399
4be73780 1400 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1401 return need_to_disable;
b0665d57 1402
4e6e1a54
ID		 1403 power_domain = intel_display_port_power_domain(intel_encoder);
1404 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1405
b0665d57 1406 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1407
4be73780
DV		 1408 if (!edp_have_panel_power(intel_dp))
1409 wait_panel_power_cycle(intel_dp);
99ea7127 1410
453c5420 1411 pp = ironlake_get_pp_control(intel_dp);
5d613501 1412 pp |= EDP_FORCE_VDD;
ebf33b18 1413
bf13e81b
JN		 1414 pp_stat_reg = _pp_stat_reg(intel_dp);
1415 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1416
1417 I915_WRITE(pp_ctrl_reg, pp);
1418 POSTING_READ(pp_ctrl_reg);
1419 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1420 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1421 /*
1422 * If the panel wasn't on, delay before accessing aux channel
1423 */
4be73780 1424 if (!edp_have_panel_power(intel_dp)) {
bd943159 1425 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1426 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1427 }
adddaaf4
JN		 1428
1429 return need_to_disable;
1430}
1431
951468f3
VS		 1432/*
1433 * Must be paired with intel_edp_panel_vdd_off() or
1434 * intel_edp_panel_off().
1435 * Nested calls to these functions are not allowed since
1436 * we drop the lock. Caller must use some higher level
1437 * locking to prevent nested calls from other threads.
1438 */
b80d6c78 1439void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1440{
c695b6b6 1441 bool vdd;
adddaaf4 1442
c695b6b6
VS		 1443 if (!is_edp(intel_dp))
1444 return;
1445
773538e8 1446 pps_lock(intel_dp);
c695b6b6 1447 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1448 pps_unlock(intel_dp);
c695b6b6
VS		 1449
1450 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1451}
1452
4be73780 1453static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1454{
30add22d 1455 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1456 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1457 struct intel_digital_port *intel_dig_port =
1458 dp_to_dig_port(intel_dp);
1459 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1460 enum intel_display_power_domain power_domain;
5d613501 1461 u32 pp;
453c5420 1462 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1463
e39b999a 1464 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1465
15e899a0 1466 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1467
15e899a0 1468 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1469 return;
b0665d57 1470
be2c9196 1471 DRM_DEBUG_KMS("Turning eDP VDD off\n");
bd943159 1472
be2c9196
VS		 1473 pp = ironlake_get_pp_control(intel_dp);
1474 pp &= ~EDP_FORCE_VDD;
453c5420 1475
be2c9196
VS		 1476 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1477 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1478
be2c9196
VS		 1479 I915_WRITE(pp_ctrl_reg, pp);
1480 POSTING_READ(pp_ctrl_reg);
90791a5c 1481
be2c9196
VS		 1482 /* Make sure sequencer is idle before allowing subsequent activity */
1483 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1484 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1485
be2c9196
VS		 1486 if ((pp & POWER_TARGET_ON) == 0)
1487 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1488
be2c9196
VS		 1489 power_domain = intel_display_port_power_domain(intel_encoder);
1490 intel_display_power_put(dev_priv, power_domain);
bd943159 1491}
5d613501 1492
4be73780 1493static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1494{
1495 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1496 struct intel_dp, panel_vdd_work);
bd943159 1497
773538e8 1498 pps_lock(intel_dp);
15e899a0
VS		 1499 if (!intel_dp->want_panel_vdd)
1500 edp_panel_vdd_off_sync(intel_dp);
773538e8 1501 pps_unlock(intel_dp);
bd943159
KP		 1502}
1503
aba86890
ID		 1504static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1505{
1506 unsigned long delay;
1507
1508 /*
1509 * Queue the timer to fire a long time from now (relative to the power
1510 * down delay) to keep the panel power up across a sequence of
1511 * operations.
1512 */
1513 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1514 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1515}
1516
951468f3
VS		 1517/*
1518 * Must be paired with edp_panel_vdd_on().
1519 * Must hold pps_mutex around the whole on/off sequence.
1520 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1521 */
4be73780 1522static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1523{
e39b999a
VS		 1524 struct drm_i915_private *dev_priv =
1525 intel_dp_to_dev(intel_dp)->dev_private;
1526
1527 lockdep_assert_held(&dev_priv->pps_mutex);
1528
97af61f5
KP		 1529 if (!is_edp(intel_dp))
1530 return;
5d613501 1531
bd943159 1532 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1533
bd943159
KP		 1534 intel_dp->want_panel_vdd = false;
1535
aba86890 1536 if (sync)
4be73780 1537 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1538 else
1539 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1540}
1541
951468f3
VS		 1542/*
1543 * Must be paired with intel_edp_panel_vdd_on().
1544 * Nested calls to these functions are not allowed since
1545 * we drop the lock. Caller must use some higher level
1546 * locking to prevent nested calls from other threads.
1547 */
1e0560e0
VS		 1548static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1549{
e39b999a
VS		 1550 if (!is_edp(intel_dp))
1551 return;
1552
773538e8 1553 pps_lock(intel_dp);
1e0560e0 1554 edp_panel_vdd_off(intel_dp, sync);
773538e8 1555 pps_unlock(intel_dp);
1e0560e0
VS		 1556}
1557
4be73780 1558void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1559{
30add22d 1560 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1561 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1562 u32 pp;
453c5420 1563 u32 pp_ctrl_reg;
9934c132 1564
97af61f5 1565 if (!is_edp(intel_dp))
bd943159 1566 return;
99ea7127
KP		 1567
1568 DRM_DEBUG_KMS("Turn eDP power on\n");
1569
773538e8 1570 pps_lock(intel_dp);
e39b999a 1571
4be73780 1572 if (edp_have_panel_power(intel_dp)) {
99ea7127 1573 DRM_DEBUG_KMS("eDP power already on\n");
e39b999a 1574 goto out;
99ea7127 1575 }
9934c132 1576
4be73780 1577 wait_panel_power_cycle(intel_dp);
37c6c9b0 1578
bf13e81b 1579 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1580 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1581 if (IS_GEN5(dev)) {
1582 /* ILK workaround: disable reset around power sequence */
1583 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1584 I915_WRITE(pp_ctrl_reg, pp);
1585 POSTING_READ(pp_ctrl_reg);
05ce1a49 1586 }
37c6c9b0 1587
1c0ae80a 1588 pp |= POWER_TARGET_ON;
99ea7127
KP		 1589 if (!IS_GEN5(dev))
1590 pp |= PANEL_POWER_RESET;
1591
453c5420
JB		 1592 I915_WRITE(pp_ctrl_reg, pp);
1593 POSTING_READ(pp_ctrl_reg);
9934c132 1594
4be73780 1595 wait_panel_on(intel_dp);
dce56b3c 1596 intel_dp->last_power_on = jiffies;
9934c132 1597
05ce1a49
KP		 1598 if (IS_GEN5(dev)) {
1599 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1600 I915_WRITE(pp_ctrl_reg, pp);
1601 POSTING_READ(pp_ctrl_reg);
05ce1a49 1602 }
e39b999a
VS		 1603
1604 out:
773538e8 1605 pps_unlock(intel_dp);
9934c132
JB		 1606}
1607
4be73780 1608void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1609{
4e6e1a54
ID		 1610 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1611 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1612 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1613 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1614 enum intel_display_power_domain power_domain;
99ea7127 1615 u32 pp;
453c5420 1616 u32 pp_ctrl_reg;
9934c132 1617
97af61f5
KP		 1618 if (!is_edp(intel_dp))
1619 return;
37c6c9b0 1620
99ea7127 1621 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1622
773538e8 1623 pps_lock(intel_dp);
e39b999a 1624
24f3e092
JN		 1625 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1626
453c5420 1627 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1628 /* We need to switch off panel power _and_ force vdd, for otherwise some
1629 * panels get very unhappy and cease to work. */
b3064154
PJ		 1630 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1631 EDP_BLC_ENABLE);
453c5420 1632
bf13e81b 1633 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1634
849e39f5
PZ		 1635 intel_dp->want_panel_vdd = false;
1636
453c5420
JB		 1637 I915_WRITE(pp_ctrl_reg, pp);
1638 POSTING_READ(pp_ctrl_reg);
9934c132 1639
dce56b3c 1640 intel_dp->last_power_cycle = jiffies;
4be73780 1641 wait_panel_off(intel_dp);
849e39f5
PZ		 1642
1643 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1644 power_domain = intel_display_port_power_domain(intel_encoder);
1645 intel_display_power_put(dev_priv, power_domain);
e39b999a 1646
773538e8 1647 pps_unlock(intel_dp);
9934c132
JB		 1648}
1649
1250d107
JN		 1650/* Enable backlight in the panel power control. */
1651static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1652{
da63a9f2
PZ		 1653 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1654 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 u32 pp;
453c5420 1657 u32 pp_ctrl_reg;
32f9d658 1658
01cb9ea6
JB		 1659 /*
1660 * If we enable the backlight right away following a panel power
1661 * on, we may see slight flicker as the panel syncs with the eDP
1662 * link. So delay a bit to make sure the image is solid before
1663 * allowing it to appear.
1664 */
4be73780 1665 wait_backlight_on(intel_dp);
e39b999a 1666
773538e8 1667 pps_lock(intel_dp);
e39b999a 1668
453c5420 1669 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1670 pp |= EDP_BLC_ENABLE;
453c5420 1671
bf13e81b 1672 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1673
1674 I915_WRITE(pp_ctrl_reg, pp);
1675 POSTING_READ(pp_ctrl_reg);
e39b999a 1676
773538e8 1677 pps_unlock(intel_dp);
32f9d658
ZW		 1678}
1679
1250d107
JN		 1680/* Enable backlight PWM and backlight PP control. */
1681void intel_edp_backlight_on(struct intel_dp *intel_dp)
1682{
1683 if (!is_edp(intel_dp))
1684 return;
1685
1686 DRM_DEBUG_KMS("\n");
1687
1688 intel_panel_enable_backlight(intel_dp->attached_connector);
1689 _intel_edp_backlight_on(intel_dp);
1690}
1691
1692/* Disable backlight in the panel power control. */
1693static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1694{
30add22d 1695 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1696 struct drm_i915_private *dev_priv = dev->dev_private;
1697 u32 pp;
453c5420 1698 u32 pp_ctrl_reg;
32f9d658 1699
f01eca2e
KP		 1700 if (!is_edp(intel_dp))
1701 return;
1702
773538e8 1703 pps_lock(intel_dp);
e39b999a 1704
453c5420 1705 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1706 pp &= ~EDP_BLC_ENABLE;
453c5420 1707
bf13e81b 1708 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1709
1710 I915_WRITE(pp_ctrl_reg, pp);
1711 POSTING_READ(pp_ctrl_reg);
f7d2323c 1712
773538e8 1713 pps_unlock(intel_dp);
e39b999a
VS		 1714
1715 intel_dp->last_backlight_off = jiffies;
f7d2323c 1716 edp_wait_backlight_off(intel_dp);
1250d107 1717}
f7d2323c 1718
1250d107
JN		 1719/* Disable backlight PP control and backlight PWM. */
1720void intel_edp_backlight_off(struct intel_dp *intel_dp)
1721{
1722 if (!is_edp(intel_dp))
1723 return;
1724
1725 DRM_DEBUG_KMS("\n");
f7d2323c 1726
1250d107 1727 _intel_edp_backlight_off(intel_dp);
f7d2323c 1728 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1729}
a4fc5ed6 1730
73580fb7
JN		 1731/*
1732 * Hook for controlling the panel power control backlight through the bl_power
1733 * sysfs attribute. Take care to handle multiple calls.
1734 */
1735static void intel_edp_backlight_power(struct intel_connector *connector,
1736 bool enable)
1737{
1738 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1739 bool is_enabled;
1740
773538e8 1741 pps_lock(intel_dp);
e39b999a 1742 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1743 pps_unlock(intel_dp);
73580fb7
JN		 1744
1745 if (is_enabled == enable)
1746 return;
1747
23ba9373
JN		 1748 DRM_DEBUG_KMS("panel power control backlight %s\n",
1749 enable ? "enable" : "disable");
73580fb7
JN		 1750
1751 if (enable)
1752 _intel_edp_backlight_on(intel_dp);
1753 else
1754 _intel_edp_backlight_off(intel_dp);
1755}
1756
2bd2ad64 1757static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1758{
da63a9f2
PZ		 1759 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1760 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1761 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1762 struct drm_i915_private *dev_priv = dev->dev_private;
1763 u32 dpa_ctl;
1764
2bd2ad64
DV		 1765 assert_pipe_disabled(dev_priv,
1766 to_intel_crtc(crtc)->pipe);
1767
d240f20f
JB		 1768 DRM_DEBUG_KMS("\n");
1769 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1770 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1771 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1772
1773 /* We don't adjust intel_dp->DP while tearing down the link, to
1774 * facilitate link retraining (e.g. after hotplug). Hence clear all
1775 * enable bits here to ensure that we don't enable too much. */
1776 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1777 intel_dp->DP |= DP_PLL_ENABLE;
1778 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1779 POSTING_READ(DP_A);
1780 udelay(200);
d240f20f
JB		 1781}
1782
2bd2ad64 1783static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1784{
da63a9f2
PZ		 1785 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1786 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1787 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1788 struct drm_i915_private *dev_priv = dev->dev_private;
1789 u32 dpa_ctl;
1790
2bd2ad64
DV		 1791 assert_pipe_disabled(dev_priv,
1792 to_intel_crtc(crtc)->pipe);
1793
d240f20f 1794 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1795 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1796 "dp pll off, should be on\n");
1797 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1798
1799 /* We can't rely on the value tracked for the DP register in
1800 * intel_dp->DP because link_down must not change that (otherwise link
1801 * re-training will fail. */
298b0b39 1802 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1803 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1804 POSTING_READ(DP_A);
d240f20f
JB		 1805 udelay(200);
1806}
1807
c7ad3810 1808/* If the sink supports it, try to set the power state appropriately */
c19b0669 1809void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1810{
1811 int ret, i;
1812
1813 /* Should have a valid DPCD by this point */
1814 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1815 return;
1816
1817 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1818 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1819 DP_SET_POWER_D3);
c7ad3810
JB		 1820 } else {
1821 /*
1822 * When turning on, we need to retry for 1ms to give the sink
1823 * time to wake up.
1824 */
1825 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1826 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1827 DP_SET_POWER_D0);
c7ad3810
JB		 1828 if (ret == 1)
1829 break;
1830 msleep(1);
1831 }
1832 }
f9cac721
JN		 1833
1834 if (ret != 1)
1835 DRM_DEBUG_KMS("failed to %s sink power state\n",
1836 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1837}
1838
19d8fe15
DV		 1839static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1840 enum pipe *pipe)
d240f20f 1841{
19d8fe15 1842 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1843 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1844 struct drm_device *dev = encoder->base.dev;
1845 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1846 enum intel_display_power_domain power_domain;
1847 u32 tmp;
1848
1849 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1850 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1851 return false;
1852
1853 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1854
1855 if (!(tmp & DP_PORT_EN))
1856 return false;
1857
bc7d38a4 1858 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1859 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1860 } else if (IS_CHERRYVIEW(dev)) {
1861 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1862 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1863 *pipe = PORT_TO_PIPE(tmp);
1864 } else {
1865 u32 trans_sel;
1866 u32 trans_dp;
1867 int i;
1868
1869 switch (intel_dp->output_reg) {
1870 case PCH_DP_B:
1871 trans_sel = TRANS_DP_PORT_SEL_B;
1872 break;
1873 case PCH_DP_C:
1874 trans_sel = TRANS_DP_PORT_SEL_C;
1875 break;
1876 case PCH_DP_D:
1877 trans_sel = TRANS_DP_PORT_SEL_D;
1878 break;
1879 default:
1880 return true;
1881 }
1882
055e393f 1883 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1884 trans_dp = I915_READ(TRANS_DP_CTL(i));
1885 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1886 *pipe = i;
1887 return true;
1888 }
1889 }
19d8fe15 1890
4a0833ec
DV		 1891 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1892 intel_dp->output_reg);
1893 }
d240f20f 1894
19d8fe15
DV		 1895 return true;
1896}
d240f20f 1897
045ac3b5
JB		 1898static void intel_dp_get_config(struct intel_encoder *encoder,
1899 struct intel_crtc_config *pipe_config)
1900{
1901 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1902 u32 tmp, flags = 0;
63000ef6
XZ		 1903 struct drm_device *dev = encoder->base.dev;
1904 struct drm_i915_private *dev_priv = dev->dev_private;
1905 enum port port = dp_to_dig_port(intel_dp)->port;
1906 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1907 int dotclock;
045ac3b5 1908
9ed109a7
DV		 1909 tmp = I915_READ(intel_dp->output_reg);
1910 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1911 pipe_config->has_audio = true;
1912
63000ef6 1913 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1914 if (tmp & DP_SYNC_HS_HIGH)
1915 flags |= DRM_MODE_FLAG_PHSYNC;
1916 else
1917 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1918
63000ef6
XZ		 1919 if (tmp & DP_SYNC_VS_HIGH)
1920 flags |= DRM_MODE_FLAG_PVSYNC;
1921 else
1922 flags |= DRM_MODE_FLAG_NVSYNC;
1923 } else {
1924 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1925 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1926 flags |= DRM_MODE_FLAG_PHSYNC;
1927 else
1928 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1929
63000ef6
XZ		 1930 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1931 flags |= DRM_MODE_FLAG_PVSYNC;
1932 else
1933 flags |= DRM_MODE_FLAG_NVSYNC;
1934 }
045ac3b5
JB		 1935
1936 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1937
8c875fca
VS		 1938 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1939 tmp & DP_COLOR_RANGE_16_235)
1940 pipe_config->limited_color_range = true;
1941
eb14cb74
VS		 1942 pipe_config->has_dp_encoder = true;
1943
1944 intel_dp_get_m_n(crtc, pipe_config);
1945
18442d08 1946 if (port == PORT_A) {
f1f644dc
JB		 1947 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1948 pipe_config->port_clock = 162000;
1949 else
1950 pipe_config->port_clock = 270000;
1951 }
18442d08
VS		 1952
1953 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1954 &pipe_config->dp_m_n);
1955
1956 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1957 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1958
241bfc38 1959 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1960
c6cd2ee2
JN		 1961 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1962 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1963 /*
1964 * This is a big fat ugly hack.
1965 *
1966 * Some machines in UEFI boot mode provide us a VBT that has 18
1967 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1968 * unknown we fail to light up. Yet the same BIOS boots up with
1969 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1970 * max, not what it tells us to use.
1971 *
1972 * Note: This will still be broken if the eDP panel is not lit
1973 * up by the BIOS, and thus we can't get the mode at module
1974 * load.
1975 */
1976 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1977 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1978 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1979 }
045ac3b5
JB		 1980}
1981
34eb7579 1982static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1983{
34eb7579 1984 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1985}
1986
2b28bb1b
RV		 1987static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1988{
1989 struct drm_i915_private *dev_priv = dev->dev_private;
1990
18b5992c 1991 if (!HAS_PSR(dev))
2b28bb1b
RV		 1992 return false;
1993
18b5992c 1994 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1995}
1996
1997static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1998 struct edp_vsc_psr *vsc_psr)
1999{
2000 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2001 struct drm_device *dev = dig_port->base.base.dev;
2002 struct drm_i915_private *dev_priv = dev->dev_private;
2003 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
2004 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
2005 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
2006 uint32_t *data = (uint32_t *) vsc_psr;
2007 unsigned int i;
2008
2009 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2010 the video DIP being updated before program video DIP data buffer
2011 registers for DIP being updated. */
2012 I915_WRITE(ctl_reg, 0);
2013 POSTING_READ(ctl_reg);
2014
2015 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
2016 if (i < sizeof(struct edp_vsc_psr))
2017 I915_WRITE(data_reg + i, *data++);
2018 else
2019 I915_WRITE(data_reg + i, 0);
2020 }
2021
2022 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
2023 POSTING_READ(ctl_reg);
2024}
2025
ba80f4d4 2026static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
2b28bb1b 2027{
2b28bb1b
RV		 2028 struct edp_vsc_psr psr_vsc;
2029
2b28bb1b
RV		 2030 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2031 memset(&psr_vsc, 0, sizeof(psr_vsc));
2032 psr_vsc.sdp_header.HB0 = 0;
2033 psr_vsc.sdp_header.HB1 = 0x7;
2034 psr_vsc.sdp_header.HB2 = 0x2;
2035 psr_vsc.sdp_header.HB3 = 0x8;
2036 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2b28bb1b
RV		 2037}
2038
2039static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2040{
0e0ae652
RV		 2041 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2042 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2043 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2044 uint32_t aux_clock_divider;
2b28bb1b 2045 int precharge = 0x3;
0e0ae652 2046 bool only_standby = false;
5ca476f8
VS		 2047 static const uint8_t aux_msg[] = {
2048 [0] = DP_AUX_NATIVE_WRITE << 4,
2049 [1] = DP_SET_POWER >> 8,
2050 [2] = DP_SET_POWER & 0xff,
2051 [3] = 1 - 1,
2052 [4] = DP_SET_POWER_D0,
2053 };
2054 int i;
2055
2056 BUILD_BUG_ON(sizeof(aux_msg) > 20);
2b28bb1b 2057
ec5b01dd
DL		 2058 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2059
0e0ae652
RV		 2060 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2061 only_standby = true;
2062
2b28bb1b 2063 /* Enable PSR in sink */
0e0ae652 2064 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2065 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2066 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2067 else
9d1a1031
JN		 2068 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2069 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2070
2071 /* Setup AUX registers */
5ca476f8
VS		 2072 for (i = 0; i < sizeof(aux_msg); i += 4)
2073 I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
2074 pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
2075
18b5992c 2076 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b 2077 DP_AUX_CH_CTL_TIME_OUT_400us |
5ca476f8 2078 (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2b28bb1b
RV		 2079 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2080 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2081}
2082
2083static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2084{
0e0ae652
RV		 2085 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2086 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2087 struct drm_i915_private *dev_priv = dev->dev_private;
2088 uint32_t max_sleep_time = 0x1f;
2089 uint32_t idle_frames = 1;
2090 uint32_t val = 0x0;
ed8546ac 2091 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2092 bool only_standby = false;
2093
2094 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2095 only_standby = true;
2b28bb1b 2096
0e0ae652 2097 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2098 val |= EDP_PSR_LINK_STANDBY;
2099 val |= EDP_PSR_TP2_TP3_TIME_0us;
2100 val |= EDP_PSR_TP1_TIME_0us;
2101 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2102 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2103 } else
2104 val |= EDP_PSR_LINK_DISABLE;
2105
18b5992c 2106 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2107 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2108 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2109 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2110 EDP_PSR_ENABLE);
2111}
2112
3f51e471
RV		 2113static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2114{
2115 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2116 struct drm_device *dev = dig_port->base.base.dev;
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2118 struct drm_crtc *crtc = dig_port->base.base.crtc;
2119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2120
f0355c4a 2121 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2122 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2123 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2124
a031d709
RV		 2125 dev_priv->psr.source_ok = false;
2126
9ca15301 2127 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2128 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2129 return false;
2130 }
2131
d330a953 2132 if (!i915.enable_psr) {
105b7c11 2133 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2134 return false;
2135 }
2136
4c8c7000
RV		 2137 /* Below limitations aren't valid for Broadwell */
2138 if (IS_BROADWELL(dev))
2139 goto out;
2140
3f51e471
RV		 2141 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2142 S3D_ENABLE) {
2143 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2144 return false;
2145 }
2146
ca73b4f0 2147 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2148 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2149 return false;
2150 }
2151
4c8c7000 2152 out:
a031d709 2153 dev_priv->psr.source_ok = true;
3f51e471
RV		 2154 return true;
2155}
2156
3d739d92 2157static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2158{
7c8f8a70
RV		 2159 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2160 struct drm_device *dev = intel_dig_port->base.base.dev;
2161 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2162
3638379c
DV		 2163 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2164 WARN_ON(dev_priv->psr.active);
f0355c4a 2165 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2166
7ca5a41f 2167 /* Enable/Re-enable PSR on the host */
2b28bb1b 2168 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2169
7c8f8a70 2170 dev_priv->psr.active = true;
2b28bb1b
RV		 2171}
2172
3d739d92
RV		 2173void intel_edp_psr_enable(struct intel_dp *intel_dp)
2174{
2175 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2176 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2177
4704c573
RV		 2178 if (!HAS_PSR(dev)) {
2179 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2180 return;
2181 }
2182
34eb7579
RV		 2183 if (!is_edp_psr(intel_dp)) {
2184 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2185 return;
2186 }
2187
f0355c4a 2188 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2189 if (dev_priv->psr.enabled) {
2190 DRM_DEBUG_KMS("PSR already in use\n");
0aa48783 2191 goto unlock;
109fc2ad
DV		 2192 }
2193
0aa48783
RV		 2194 if (!intel_edp_psr_match_conditions(intel_dp))
2195 goto unlock;
2196
9ca15301
DV		 2197 dev_priv->psr.busy_frontbuffer_bits = 0;
2198
ba80f4d4 2199 intel_edp_psr_setup_vsc(intel_dp);
16487254 2200
ba80f4d4
RV		 2201 /* Avoid continuous PSR exit by masking memup and hpd */
2202 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2203 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
16487254 2204
7ca5a41f
RV		 2205 /* Enable PSR on the panel */
2206 intel_edp_psr_enable_sink(intel_dp);
2207
0aa48783
RV		 2208 dev_priv->psr.enabled = intel_dp;
2209unlock:
f0355c4a 2210 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2211}
2212
2b28bb1b
RV		 2213void intel_edp_psr_disable(struct intel_dp *intel_dp)
2214{
2215 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2216 struct drm_i915_private *dev_priv = dev->dev_private;
2217
f0355c4a
DV		 2218 mutex_lock(&dev_priv->psr.lock);
2219 if (!dev_priv->psr.enabled) {
2220 mutex_unlock(&dev_priv->psr.lock);
2221 return;
2222 }
2223
3638379c
DV		 2224 if (dev_priv->psr.active) {
2225 I915_WRITE(EDP_PSR_CTL(dev),
2226 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2227
2228 /* Wait till PSR is idle */
2229 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2230 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2231 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2232
3638379c
DV		 2233 dev_priv->psr.active = false;
2234 } else {
2235 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2236 }
7c8f8a70 2237
2807cf69 2238 dev_priv->psr.enabled = NULL;
f0355c4a 2239 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2240
2241 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2242}
2243
f02a326e 2244static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2245{
2246 struct drm_i915_private *dev_priv =
2247 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2248 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2249
8d7f4fe9
RV		 2250 /* We have to make sure PSR is ready for re-enable
2251 * otherwise it keeps disabled until next full enable/disable cycle.
2252 * PSR might take some time to get fully disabled
2253 * and be ready for re-enable.
2254 */
2255 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
2256 EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
2257 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
2258 return;
2259 }
2260
f0355c4a
DV		 2261 mutex_lock(&dev_priv->psr.lock);
2262 intel_dp = dev_priv->psr.enabled;
2263
2807cf69 2264 if (!intel_dp)
f0355c4a 2265 goto unlock;
2807cf69 2266
9ca15301
DV		 2267 /*
2268 * The delayed work can race with an invalidate hence we need to
2269 * recheck. Since psr_flush first clears this and then reschedules we
2270 * won't ever miss a flush when bailing out here.
2271 */
2272 if (dev_priv->psr.busy_frontbuffer_bits)
2273 goto unlock;
2274
2275 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2276unlock:
2277 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2278}
2279
9ca15301 2280static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2281{
2282 struct drm_i915_private *dev_priv = dev->dev_private;
2283
3638379c
DV		 2284 if (dev_priv->psr.active) {
2285 u32 val = I915_READ(EDP_PSR_CTL(dev));
2286
2287 WARN_ON(!(val & EDP_PSR_ENABLE));
2288
2289 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2290
2291 dev_priv->psr.active = false;
2292 }
7c8f8a70 2293
9ca15301
DV		 2294}
2295
2296void intel_edp_psr_invalidate(struct drm_device *dev,
2297 unsigned frontbuffer_bits)
2298{
2299 struct drm_i915_private *dev_priv = dev->dev_private;
2300 struct drm_crtc *crtc;
2301 enum pipe pipe;
2302
9ca15301
DV		 2303 mutex_lock(&dev_priv->psr.lock);
2304 if (!dev_priv->psr.enabled) {
2305 mutex_unlock(&dev_priv->psr.lock);
2306 return;
2307 }
2308
2309 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2310 pipe = to_intel_crtc(crtc)->pipe;
2311
2312 intel_edp_psr_do_exit(dev);
2313
2314 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2315
2316 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2317 mutex_unlock(&dev_priv->psr.lock);
2318}
2319
2320void intel_edp_psr_flush(struct drm_device *dev,
2321 unsigned frontbuffer_bits)
2322{
2323 struct drm_i915_private *dev_priv = dev->dev_private;
2324 struct drm_crtc *crtc;
2325 enum pipe pipe;
2326
9ca15301
DV		 2327 mutex_lock(&dev_priv->psr.lock);
2328 if (!dev_priv->psr.enabled) {
2329 mutex_unlock(&dev_priv->psr.lock);
2330 return;
2331 }
2332
2333 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2334 pipe = to_intel_crtc(crtc)->pipe;
2335 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2336
2337 /*
2338 * On Haswell sprite plane updates don't result in a psr invalidating
2339 * signal in the hardware. Which means we need to manually fake this in
2340 * software for all flushes, not just when we've seen a preceding
2341 * invalidation through frontbuffer rendering.
2342 */
2343 if (IS_HASWELL(dev) &&
2344 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2345 intel_edp_psr_do_exit(dev);
2346
2347 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2348 schedule_delayed_work(&dev_priv->psr.work,
2349 msecs_to_jiffies(100));
f0355c4a 2350 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2351}
2352
2353void intel_edp_psr_init(struct drm_device *dev)
2354{
2355 struct drm_i915_private *dev_priv = dev->dev_private;
2356
7c8f8a70 2357 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2358 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2359}
2360
e8cb4558 2361static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2362{
e8cb4558 2363 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2364 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2365
2366 /* Make sure the panel is off before trying to change the mode. But also
2367 * ensure that we have vdd while we switch off the panel. */
24f3e092 2368 intel_edp_panel_vdd_on(intel_dp);
4be73780 2369 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2370 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2371 intel_edp_panel_off(intel_dp);
3739850b 2372
08aff3fe
VS		 2373 /* disable the port before the pipe on g4x */
2374 if (INTEL_INFO(dev)->gen < 5)
3739850b 2375 intel_dp_link_down(intel_dp);
d240f20f
JB		 2376}
2377
08aff3fe 2378static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2379{
2bd2ad64 2380 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2381 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2382
49277c31 2383 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2384 if (port == PORT_A)
2385 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2386}
2387
2388static void vlv_post_disable_dp(struct intel_encoder *encoder)
2389{
2390 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2391
2392 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2393}
2394
580d3811
VS		 2395static void chv_post_disable_dp(struct intel_encoder *encoder)
2396{
2397 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2398 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2399 struct drm_device *dev = encoder->base.dev;
2400 struct drm_i915_private *dev_priv = dev->dev_private;
2401 struct intel_crtc *intel_crtc =
2402 to_intel_crtc(encoder->base.crtc);
2403 enum dpio_channel ch = vlv_dport_to_channel(dport);
2404 enum pipe pipe = intel_crtc->pipe;
2405 u32 val;
2406
2407 intel_dp_link_down(intel_dp);
2408
2409 mutex_lock(&dev_priv->dpio_lock);
2410
2411 /* Propagate soft reset to data lane reset */
97fd4d5c 2412 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2413 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2414 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2415
97fd4d5c
VS		 2416 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2417 val |= CHV_PCS_REQ_SOFTRESET_EN;
2418 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2419
2420 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2421 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2422 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2423
2424 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2425 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2426 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2427
2428 mutex_unlock(&dev_priv->dpio_lock);
2429}
2430
7b13b58a
VS		 2431static void
2432_intel_dp_set_link_train(struct intel_dp *intel_dp,
2433 uint32_t *DP,
2434 uint8_t dp_train_pat)
2435{
2436 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2437 struct drm_device *dev = intel_dig_port->base.base.dev;
2438 struct drm_i915_private *dev_priv = dev->dev_private;
2439 enum port port = intel_dig_port->port;
2440
2441 if (HAS_DDI(dev)) {
2442 uint32_t temp = I915_READ(DP_TP_CTL(port));
2443
2444 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2445 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2446 else
2447 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2448
2449 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2450 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2451 case DP_TRAINING_PATTERN_DISABLE:
2452 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2453
2454 break;
2455 case DP_TRAINING_PATTERN_1:
2456 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2457 break;
2458 case DP_TRAINING_PATTERN_2:
2459 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2460 break;
2461 case DP_TRAINING_PATTERN_3:
2462 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2463 break;
2464 }
2465 I915_WRITE(DP_TP_CTL(port), temp);
2466
2467 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2468 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2469
2470 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2471 case DP_TRAINING_PATTERN_DISABLE:
2472 *DP |= DP_LINK_TRAIN_OFF_CPT;
2473 break;
2474 case DP_TRAINING_PATTERN_1:
2475 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2476 break;
2477 case DP_TRAINING_PATTERN_2:
2478 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2479 break;
2480 case DP_TRAINING_PATTERN_3:
2481 DRM_ERROR("DP training pattern 3 not supported\n");
2482 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2483 break;
2484 }
2485
2486 } else {
2487 if (IS_CHERRYVIEW(dev))
2488 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2489 else
2490 *DP &= ~DP_LINK_TRAIN_MASK;
2491
2492 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2493 case DP_TRAINING_PATTERN_DISABLE:
2494 *DP |= DP_LINK_TRAIN_OFF;
2495 break;
2496 case DP_TRAINING_PATTERN_1:
2497 *DP |= DP_LINK_TRAIN_PAT_1;
2498 break;
2499 case DP_TRAINING_PATTERN_2:
2500 *DP |= DP_LINK_TRAIN_PAT_2;
2501 break;
2502 case DP_TRAINING_PATTERN_3:
2503 if (IS_CHERRYVIEW(dev)) {
2504 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2505 } else {
2506 DRM_ERROR("DP training pattern 3 not supported\n");
2507 *DP |= DP_LINK_TRAIN_PAT_2;
2508 }
2509 break;
2510 }
2511 }
2512}
2513
2514static void intel_dp_enable_port(struct intel_dp *intel_dp)
2515{
2516 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2517 struct drm_i915_private *dev_priv = dev->dev_private;
2518
2519 intel_dp->DP |= DP_PORT_EN;
2520
2521 /* enable with pattern 1 (as per spec) */
2522 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2523 DP_TRAINING_PATTERN_1);
2524
2525 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2526 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2527}
2528
e8cb4558 2529static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2530{
e8cb4558
DV		 2531 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2532 struct drm_device *dev = encoder->base.dev;
2533 struct drm_i915_private *dev_priv = dev->dev_private;
2534 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2535
0c33d8d7
DV		 2536 if (WARN_ON(dp_reg & DP_PORT_EN))
2537 return;
5d613501 2538
7b13b58a 2539 intel_dp_enable_port(intel_dp);
24f3e092 2540 intel_edp_panel_vdd_on(intel_dp);
4be73780 2541 intel_edp_panel_on(intel_dp);
1e0560e0 2542 intel_edp_panel_vdd_off(intel_dp, true);
f01eca2e 2543 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2544 intel_dp_start_link_train(intel_dp);
33a34e4e 2545 intel_dp_complete_link_train(intel_dp);
3ab9c637 2546 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2547}
89b667f8 2548
ecff4f3b
JN		 2549static void g4x_enable_dp(struct intel_encoder *encoder)
2550{
828f5c6e
JN		 2551 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2552
ecff4f3b 2553 intel_enable_dp(encoder);
4be73780 2554 intel_edp_backlight_on(intel_dp);
ab1f90f9 2555}
89b667f8 2556
ab1f90f9
JN		 2557static void vlv_enable_dp(struct intel_encoder *encoder)
2558{
828f5c6e
JN		 2559 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2560
4be73780 2561 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2562}
2563
ecff4f3b 2564static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2565{
2566 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2567 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2568
8ac33ed3
DV		 2569 intel_dp_prepare(encoder);
2570
d41f1efb
DV		 2571 /* Only ilk+ has port A */
2572 if (dport->port == PORT_A) {
2573 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2574 ironlake_edp_pll_on(intel_dp);
d41f1efb 2575 }
ab1f90f9
JN		 2576}
2577
a4a5d2f8
VS		 2578static void vlv_steal_power_sequencer(struct drm_device *dev,
2579 enum pipe pipe)
2580{
2581 struct drm_i915_private *dev_priv = dev->dev_private;
2582 struct intel_encoder *encoder;
2583
2584 lockdep_assert_held(&dev_priv->pps_mutex);
2585
2586 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2587 base.head) {
2588 struct intel_dp *intel_dp;
773538e8 2589 enum port port;
a4a5d2f8
VS		 2590
2591 if (encoder->type != INTEL_OUTPUT_EDP)
2592 continue;
2593
2594 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2595 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2596
2597 if (intel_dp->pps_pipe != pipe)
2598 continue;
2599
2600 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2601 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 2602
2603 /* make sure vdd is off before we steal it */
2604 edp_panel_vdd_off_sync(intel_dp);
2605
2606 intel_dp->pps_pipe = INVALID_PIPE;
2607 }
2608}
2609
2610static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2611{
2612 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2613 struct intel_encoder *encoder = &intel_dig_port->base;
2614 struct drm_device *dev = encoder->base.dev;
2615 struct drm_i915_private *dev_priv = dev->dev_private;
2616 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2617
2618 lockdep_assert_held(&dev_priv->pps_mutex);
2619
2620 if (intel_dp->pps_pipe == crtc->pipe)
2621 return;
2622
2623 /*
2624 * If another power sequencer was being used on this
2625 * port previously make sure to turn off vdd there while
2626 * we still have control of it.
2627 */
2628 if (intel_dp->pps_pipe != INVALID_PIPE)
2629 edp_panel_vdd_off_sync(intel_dp);
2630
2631 /*
2632 * We may be stealing the power
2633 * sequencer from another port.
2634 */
2635 vlv_steal_power_sequencer(dev, crtc->pipe);
2636
2637 /* now it's all ours */
2638 intel_dp->pps_pipe = crtc->pipe;
2639
2640 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2641 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2642
2643 /* init power sequencer on this pipe and port */
36b5f425
VS		 2644 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2645 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2646}
2647
ab1f90f9 2648static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2649{
2bd2ad64 2650 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2651 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2652 struct drm_device *dev = encoder->base.dev;
89b667f8 2653 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2654 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2655 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2656 int pipe = intel_crtc->pipe;
2657 u32 val;
a4fc5ed6 2658
ab1f90f9 2659 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2660
ab3c759a 2661 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2662 val = 0;
2663 if (pipe)
2664 val |= (1<<21);
2665 else
2666 val &= ~(1<<21);
2667 val |= 0x001000c4;
ab3c759a
CML		 2668 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2669 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2670 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2671
ab1f90f9
JN		 2672 mutex_unlock(&dev_priv->dpio_lock);
2673
2cac613b 2674 if (is_edp(intel_dp)) {
773538e8 2675 pps_lock(intel_dp);
a4a5d2f8 2676 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2677 pps_unlock(intel_dp);
2cac613b 2678 }
bf13e81b 2679
ab1f90f9
JN		 2680 intel_enable_dp(encoder);
2681
e4607fcf 2682 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2683}
2684
ecff4f3b 2685static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2686{
2687 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2688 struct drm_device *dev = encoder->base.dev;
2689 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2690 struct intel_crtc *intel_crtc =
2691 to_intel_crtc(encoder->base.crtc);
e4607fcf 2692 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2693 int pipe = intel_crtc->pipe;
89b667f8 2694
8ac33ed3
DV		 2695 intel_dp_prepare(encoder);
2696
89b667f8 2697 /* Program Tx lane resets to default */
0980a60f 2698 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2699 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2700 DPIO_PCS_TX_LANE2_RESET |
2701 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2702 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2703 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2704 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2705 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2706 DPIO_PCS_CLK_SOFT_RESET);
2707
2708 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2709 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2710 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2711 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2712 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2713}
2714
e4a1d846
CML		 2715static void chv_pre_enable_dp(struct intel_encoder *encoder)
2716{
2717 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2718 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2719 struct drm_device *dev = encoder->base.dev;
2720 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2721 struct intel_crtc *intel_crtc =
2722 to_intel_crtc(encoder->base.crtc);
2723 enum dpio_channel ch = vlv_dport_to_channel(dport);
2724 int pipe = intel_crtc->pipe;
2725 int data, i;
949c1d43 2726 u32 val;
e4a1d846 2727
e4a1d846 2728 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2729
570e2a74
VS		 2730 /* allow hardware to manage TX FIFO reset source */
2731 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2732 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2733 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2734
2735 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2736 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2737 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2738
949c1d43 2739 /* Deassert soft data lane reset*/
97fd4d5c 2740 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2741 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2742 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2743
2744 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2745 val |= CHV_PCS_REQ_SOFTRESET_EN;
2746 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2747
2748 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2749 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2750 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2751
97fd4d5c 2752 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2753 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2754 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2755
2756 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2757 for (i = 0; i < 4; i++) {
2758 /* Set the latency optimal bit */
2759 data = (i == 1) ? 0x0 : 0x6;
2760 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2761 data << DPIO_FRC_LATENCY_SHFIT);
2762
2763 /* Set the upar bit */
2764 data = (i == 1) ? 0x0 : 0x1;
2765 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2766 data << DPIO_UPAR_SHIFT);
2767 }
2768
2769 /* Data lane stagger programming */
2770 /* FIXME: Fix up value only after power analysis */
2771
2772 mutex_unlock(&dev_priv->dpio_lock);
2773
2774 if (is_edp(intel_dp)) {
773538e8 2775 pps_lock(intel_dp);
a4a5d2f8 2776 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2777 pps_unlock(intel_dp);
e4a1d846
CML		 2778 }
2779
2780 intel_enable_dp(encoder);
2781
2782 vlv_wait_port_ready(dev_priv, dport);
2783}
2784
9197c88b
VS		 2785static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2786{
2787 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2788 struct drm_device *dev = encoder->base.dev;
2789 struct drm_i915_private *dev_priv = dev->dev_private;
2790 struct intel_crtc *intel_crtc =
2791 to_intel_crtc(encoder->base.crtc);
2792 enum dpio_channel ch = vlv_dport_to_channel(dport);
2793 enum pipe pipe = intel_crtc->pipe;
2794 u32 val;
2795
625695f8
VS		 2796 intel_dp_prepare(encoder);
2797
9197c88b
VS		 2798 mutex_lock(&dev_priv->dpio_lock);
2799
b9e5ac3c
VS		 2800 /* program left/right clock distribution */
2801 if (pipe != PIPE_B) {
2802 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2803 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2804 if (ch == DPIO_CH0)
2805 val |= CHV_BUFLEFTENA1_FORCE;
2806 if (ch == DPIO_CH1)
2807 val |= CHV_BUFRIGHTENA1_FORCE;
2808 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2809 } else {
2810 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2811 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2812 if (ch == DPIO_CH0)
2813 val |= CHV_BUFLEFTENA2_FORCE;
2814 if (ch == DPIO_CH1)
2815 val |= CHV_BUFRIGHTENA2_FORCE;
2816 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2817 }
2818
9197c88b
VS		 2819 /* program clock channel usage */
2820 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2821 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2822 if (pipe != PIPE_B)
2823 val &= ~CHV_PCS_USEDCLKCHANNEL;
2824 else
2825 val |= CHV_PCS_USEDCLKCHANNEL;
2826 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2827
2828 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2829 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2830 if (pipe != PIPE_B)
2831 val &= ~CHV_PCS_USEDCLKCHANNEL;
2832 else
2833 val |= CHV_PCS_USEDCLKCHANNEL;
2834 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2835
2836 /*
2837 * This a a bit weird since generally CL
2838 * matches the pipe, but here we need to
2839 * pick the CL based on the port.
2840 */
2841 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2842 if (pipe != PIPE_B)
2843 val &= ~CHV_CMN_USEDCLKCHANNEL;
2844 else
2845 val |= CHV_CMN_USEDCLKCHANNEL;
2846 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2847
2848 mutex_unlock(&dev_priv->dpio_lock);
2849}
2850
a4fc5ed6 2851/*
df0c237d
JB		 2852 * Native read with retry for link status and receiver capability reads for
2853 * cases where the sink may still be asleep.
9d1a1031
JN		 2854 *
2855 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2856 * supposed to retry 3 times per the spec.
a4fc5ed6 2857 */
9d1a1031
JN		 2858static ssize_t
2859intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2860 void *buffer, size_t size)
a4fc5ed6 2861{
9d1a1031
JN		 2862 ssize_t ret;
2863 int i;
61da5fab 2864
61da5fab 2865 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2866 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2867 if (ret == size)
2868 return ret;
61da5fab
JB		 2869 msleep(1);
2870 }
a4fc5ed6 2871
9d1a1031 2872 return ret;
a4fc5ed6
KP		 2873}
2874
2875/*
2876 * Fetch AUX CH registers 0x202 - 0x207 which contain
2877 * link status information
2878 */
2879static bool
93f62dad 2880intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2881{
9d1a1031
JN		 2882 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2883 DP_LANE0_1_STATUS,
2884 link_status,
2885 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2886}
2887
1100244e 2888/* These are source-specific values. */
a4fc5ed6 2889static uint8_t
1a2eb460 2890intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2891{
30add22d 2892 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2893 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2894
5a9d1f1a
DL		 2895 if (INTEL_INFO(dev)->gen >= 9)
2896 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2897 else if (IS_VALLEYVIEW(dev))
bd60018a 2898 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2899 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2900 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2901 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2902 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2903 else
bd60018a 2904 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2905}
2906
2907static uint8_t
2908intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2909{
30add22d 2910 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2911 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2912
5a9d1f1a
DL		 2913 if (INTEL_INFO(dev)->gen >= 9) {
2914 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2915 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2916 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2917 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2918 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2919 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2920 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2921 default:
2922 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2923 }
2924 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2925 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2926 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2927 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2928 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2929 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2930 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2931 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2932 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2933 default:
bd60018a 2934 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2935 }
e2fa6fba
P		 2936 } else if (IS_VALLEYVIEW(dev)) {
2937 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2938 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2939 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2940 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2941 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2942 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2943 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2944 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2945 default:
bd60018a 2946 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2947 }
bc7d38a4 2948 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2949 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2950 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2951 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2952 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2953 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2954 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2955 default:
bd60018a 2956 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2957 }
2958 } else {
2959 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2960 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2961 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2962 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2963 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2964 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2965 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2966 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2967 default:
bd60018a 2968 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2969 }
a4fc5ed6
KP		 2970 }
2971}
2972
e2fa6fba
P		 2973static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2974{
2975 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2976 struct drm_i915_private *dev_priv = dev->dev_private;
2977 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2978 struct intel_crtc *intel_crtc =
2979 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2980 unsigned long demph_reg_value, preemph_reg_value,
2981 uniqtranscale_reg_value;
2982 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2983 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2984 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2985
2986 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2987 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2988 preemph_reg_value = 0x0004000;
2989 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2990 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2991 demph_reg_value = 0x2B405555;
2992 uniqtranscale_reg_value = 0x552AB83A;
2993 break;
bd60018a 2994 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2995 demph_reg_value = 0x2B404040;
2996 uniqtranscale_reg_value = 0x5548B83A;
2997 break;
bd60018a 2998 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2999 demph_reg_value = 0x2B245555;
3000 uniqtranscale_reg_value = 0x5560B83A;
3001 break;
bd60018a 3002 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3003 demph_reg_value = 0x2B405555;
3004 uniqtranscale_reg_value = 0x5598DA3A;
3005 break;
3006 default:
3007 return 0;
3008 }
3009 break;
bd60018a 3010 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3011 preemph_reg_value = 0x0002000;
3012 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3014 demph_reg_value = 0x2B404040;
3015 uniqtranscale_reg_value = 0x5552B83A;
3016 break;
bd60018a 3017 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3018 demph_reg_value = 0x2B404848;
3019 uniqtranscale_reg_value = 0x5580B83A;
3020 break;
bd60018a 3021 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3022 demph_reg_value = 0x2B404040;
3023 uniqtranscale_reg_value = 0x55ADDA3A;
3024 break;
3025 default:
3026 return 0;
3027 }
3028 break;
bd60018a 3029 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3030 preemph_reg_value = 0x0000000;
3031 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3032 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3033 demph_reg_value = 0x2B305555;
3034 uniqtranscale_reg_value = 0x5570B83A;
3035 break;
bd60018a 3036 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3037 demph_reg_value = 0x2B2B4040;
3038 uniqtranscale_reg_value = 0x55ADDA3A;
3039 break;
3040 default:
3041 return 0;
3042 }
3043 break;
bd60018a 3044 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3045 preemph_reg_value = 0x0006000;
3046 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3047 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3048 demph_reg_value = 0x1B405555;
3049 uniqtranscale_reg_value = 0x55ADDA3A;
3050 break;
3051 default:
3052 return 0;
3053 }
3054 break;
3055 default:
3056 return 0;
3057 }
3058
0980a60f 3059 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 3060 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3061 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3062 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3063 uniqtranscale_reg_value);
ab3c759a
CML		 3064 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3065 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3066 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3067 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3068 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3069
3070 return 0;
3071}
3072
e4a1d846
CML		 3073static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3074{
3075 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3076 struct drm_i915_private *dev_priv = dev->dev_private;
3077 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3078 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3079 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3080 uint8_t train_set = intel_dp->train_set[0];
3081 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3082 enum pipe pipe = intel_crtc->pipe;
3083 int i;
e4a1d846
CML		 3084
3085 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3086 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3087 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3088 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3089 deemph_reg_value = 128;
3090 margin_reg_value = 52;
3091 break;
bd60018a 3092 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3093 deemph_reg_value = 128;
3094 margin_reg_value = 77;
3095 break;
bd60018a 3096 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3097 deemph_reg_value = 128;
3098 margin_reg_value = 102;
3099 break;
bd60018a 3100 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3101 deemph_reg_value = 128;
3102 margin_reg_value = 154;
3103 /* FIXME extra to set for 1200 */
3104 break;
3105 default:
3106 return 0;
3107 }
3108 break;
bd60018a 3109 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3110 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3111 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3112 deemph_reg_value = 85;
3113 margin_reg_value = 78;
3114 break;
bd60018a 3115 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3116 deemph_reg_value = 85;
3117 margin_reg_value = 116;
3118 break;
bd60018a 3119 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3120 deemph_reg_value = 85;
3121 margin_reg_value = 154;
3122 break;
3123 default:
3124 return 0;
3125 }
3126 break;
bd60018a 3127 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3128 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3129 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3130 deemph_reg_value = 64;
3131 margin_reg_value = 104;
3132 break;
bd60018a 3133 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3134 deemph_reg_value = 64;
3135 margin_reg_value = 154;
3136 break;
3137 default:
3138 return 0;
3139 }
3140 break;
bd60018a 3141 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3142 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3143 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3144 deemph_reg_value = 43;
3145 margin_reg_value = 154;
3146 break;
3147 default:
3148 return 0;
3149 }
3150 break;
3151 default:
3152 return 0;
3153 }
3154
3155 mutex_lock(&dev_priv->dpio_lock);
3156
3157 /* Clear calc init */
1966e59e
VS		 3158 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3159 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3160 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3161 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3162 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3163
3164 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3165 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3166 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3167 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 3168 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 3169
a02ef3c7
VS		 3170 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3171 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3172 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3173 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3174
3175 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3176 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3177 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3178 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3179
e4a1d846 3180 /* Program swing deemph */
f72df8db
VS		 3181 for (i = 0; i < 4; i++) {
3182 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3183 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3184 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3185 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3186 }
e4a1d846
CML		 3187
3188 /* Program swing margin */
f72df8db
VS		 3189 for (i = 0; i < 4; i++) {
3190 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3191 val &= ~DPIO_SWING_MARGIN000_MASK;
3192 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3193 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3194 }
e4a1d846
CML		 3195
3196 /* Disable unique transition scale */
f72df8db
VS		 3197 for (i = 0; i < 4; i++) {
3198 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3199 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3200 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3201 }
e4a1d846
CML		 3202
3203 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3204 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3205 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3206 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3207
3208 /*
3209 * The document said it needs to set bit 27 for ch0 and bit 26
3210 * for ch1. Might be a typo in the doc.
3211 * For now, for this unique transition scale selection, set bit
3212 * 27 for ch0 and ch1.
3213 */
f72df8db
VS		 3214 for (i = 0; i < 4; i++) {
3215 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3216 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3217 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3218 }
e4a1d846 3219
f72df8db
VS		 3220 for (i = 0; i < 4; i++) {
3221 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3222 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3223 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3224 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3225 }
e4a1d846
CML		 3226 }
3227
3228 /* Start swing calculation */
1966e59e
VS		 3229 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3230 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3231 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3232
3233 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3234 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3235 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3236
3237 /* LRC Bypass */
3238 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3239 val |= DPIO_LRC_BYPASS;
3240 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3241
3242 mutex_unlock(&dev_priv->dpio_lock);
3243
3244 return 0;
3245}
3246
a4fc5ed6 3247static void
0301b3ac
JN		 3248intel_get_adjust_train(struct intel_dp *intel_dp,
3249 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3250{
3251 uint8_t v = 0;
3252 uint8_t p = 0;
3253 int lane;
1a2eb460
KP		 3254 uint8_t voltage_max;
3255 uint8_t preemph_max;
a4fc5ed6 3256
33a34e4e 3257 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3258 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3259 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3260
3261 if (this_v > v)
3262 v = this_v;
3263 if (this_p > p)
3264 p = this_p;
3265 }
3266
1a2eb460 3267 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3268 if (v >= voltage_max)
3269 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3270
1a2eb460
KP		 3271 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3272 if (p >= preemph_max)
3273 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3274
3275 for (lane = 0; lane < 4; lane++)
33a34e4e 3276 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3277}
3278
3279static uint32_t
f0a3424e 3280intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3281{
3cf2efb1 3282 uint32_t signal_levels = 0;
a4fc5ed6 3283
3cf2efb1 3284 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3286 default:
3287 signal_levels |= DP_VOLTAGE_0_4;
3288 break;
bd60018a 3289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3290 signal_levels |= DP_VOLTAGE_0_6;
3291 break;
bd60018a 3292 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3293 signal_levels |= DP_VOLTAGE_0_8;
3294 break;
bd60018a 3295 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3296 signal_levels |= DP_VOLTAGE_1_2;
3297 break;
3298 }
3cf2efb1 3299 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3300 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3301 default:
3302 signal_levels |= DP_PRE_EMPHASIS_0;
3303 break;
bd60018a 3304 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3305 signal_levels |= DP_PRE_EMPHASIS_3_5;
3306 break;
bd60018a 3307 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3308 signal_levels |= DP_PRE_EMPHASIS_6;
3309 break;
bd60018a 3310 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3311 signal_levels |= DP_PRE_EMPHASIS_9_5;
3312 break;
3313 }
3314 return signal_levels;
3315}
3316
e3421a18
ZW		 3317/* Gen6's DP voltage swing and pre-emphasis control */
3318static uint32_t
3319intel_gen6_edp_signal_levels(uint8_t train_set)
3320{
3c5a62b5
YL		 3321 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3322 DP_TRAIN_PRE_EMPHASIS_MASK);
3323 switch (signal_levels) {
bd60018a
SJ		 3324 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3325 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3326 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3327 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3328 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3330 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3331 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3332 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3333 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3334 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3335 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3336 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3337 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3338 default:
3c5a62b5
YL		 3339 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3340 "0x%x\n", signal_levels);
3341 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3342 }
3343}
3344
1a2eb460
KP		 3345/* Gen7's DP voltage swing and pre-emphasis control */
3346static uint32_t
3347intel_gen7_edp_signal_levels(uint8_t train_set)
3348{
3349 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3350 DP_TRAIN_PRE_EMPHASIS_MASK);
3351 switch (signal_levels) {
bd60018a 3352 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3353 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3354 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3355 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3356 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3357 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3358
bd60018a 3359 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3360 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3361 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3362 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3363
bd60018a 3364 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3365 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3366 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3367 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3368
3369 default:
3370 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3371 "0x%x\n", signal_levels);
3372 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3373 }
3374}
3375
d6c0d722
PZ		 3376/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3377static uint32_t
f0a3424e 3378intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3379{
d6c0d722
PZ		 3380 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3381 DP_TRAIN_PRE_EMPHASIS_MASK);
3382 switch (signal_levels) {
bd60018a 3383 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3384 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3385 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3386 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3387 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3388 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3389 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3390 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3391
bd60018a 3392 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3393 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3394 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3395 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3396 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3397 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3398
bd60018a 3399 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3400 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3401 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3402 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3403 default:
3404 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3405 "0x%x\n", signal_levels);
c5fe6a06 3406 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3407 }
a4fc5ed6
KP		 3408}
3409
f0a3424e
PZ		 3410/* Properly updates "DP" with the correct signal levels. */
3411static void
3412intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3413{
3414 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3415 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3416 struct drm_device *dev = intel_dig_port->base.base.dev;
3417 uint32_t signal_levels, mask;
3418 uint8_t train_set = intel_dp->train_set[0];
3419
5a9d1f1a 3420 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3421 signal_levels = intel_hsw_signal_levels(train_set);
3422 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3423 } else if (IS_CHERRYVIEW(dev)) {
3424 signal_levels = intel_chv_signal_levels(intel_dp);
3425 mask = 0;
e2fa6fba
P		 3426 } else if (IS_VALLEYVIEW(dev)) {
3427 signal_levels = intel_vlv_signal_levels(intel_dp);
3428 mask = 0;
bc7d38a4 3429 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3430 signal_levels = intel_gen7_edp_signal_levels(train_set);
3431 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3432 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3433 signal_levels = intel_gen6_edp_signal_levels(train_set);
3434 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3435 } else {
3436 signal_levels = intel_gen4_signal_levels(train_set);
3437 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3438 }
3439
3440 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3441
3442 *DP = (*DP & ~mask) | signal_levels;
3443}
3444
a4fc5ed6 3445static bool
ea5b213a 3446intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3447 uint32_t *DP,
58e10eb9 3448 uint8_t dp_train_pat)
a4fc5ed6 3449{
174edf1f
PZ		 3450 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3451 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3452 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3453 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3454 int ret, len;
a4fc5ed6 3455
7b13b58a 3456 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3457
70aff66c 3458 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3459 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3460
2cdfe6c8
JN		 3461 buf[0] = dp_train_pat;
3462 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3463 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3464 /* don't write DP_TRAINING_LANEx_SET on disable */
3465 len = 1;
3466 } else {
3467 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3468 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3469 len = intel_dp->lane_count + 1;
47ea7542 3470 }
a4fc5ed6 3471
9d1a1031
JN		 3472 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3473 buf, len);
2cdfe6c8
JN		 3474
3475 return ret == len;
a4fc5ed6
KP		 3476}
3477
70aff66c
JN		 3478static bool
3479intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3480 uint8_t dp_train_pat)
3481{
953d22e8 3482 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3483 intel_dp_set_signal_levels(intel_dp, DP);
3484 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3485}
3486
3487static bool
3488intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3489 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3490{
3491 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3492 struct drm_device *dev = intel_dig_port->base.base.dev;
3493 struct drm_i915_private *dev_priv = dev->dev_private;
3494 int ret;
3495
3496 intel_get_adjust_train(intel_dp, link_status);
3497 intel_dp_set_signal_levels(intel_dp, DP);
3498
3499 I915_WRITE(intel_dp->output_reg, *DP);
3500 POSTING_READ(intel_dp->output_reg);
3501
9d1a1031
JN		 3502 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3503 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3504
3505 return ret == intel_dp->lane_count;
3506}
3507
3ab9c637
ID		 3508static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3509{
3510 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3511 struct drm_device *dev = intel_dig_port->base.base.dev;
3512 struct drm_i915_private *dev_priv = dev->dev_private;
3513 enum port port = intel_dig_port->port;
3514 uint32_t val;
3515
3516 if (!HAS_DDI(dev))
3517 return;
3518
3519 val = I915_READ(DP_TP_CTL(port));
3520 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3521 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3522 I915_WRITE(DP_TP_CTL(port), val);
3523
3524 /*
3525 * On PORT_A we can have only eDP in SST mode. There the only reason
3526 * we need to set idle transmission mode is to work around a HW issue
3527 * where we enable the pipe while not in idle link-training mode.
3528 * In this case there is requirement to wait for a minimum number of
3529 * idle patterns to be sent.
3530 */
3531 if (port == PORT_A)
3532 return;
3533
3534 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3535 1))
3536 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3537}
3538
33a34e4e 3539/* Enable corresponding port and start training pattern 1 */
c19b0669 3540void
33a34e4e 3541intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3542{
da63a9f2 3543 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3544 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3545 int i;
3546 uint8_t voltage;
cdb0e95b 3547 int voltage_tries, loop_tries;
ea5b213a 3548 uint32_t DP = intel_dp->DP;
6aba5b6c 3549 uint8_t link_config[2];
a4fc5ed6 3550
affa9354 3551 if (HAS_DDI(dev))
c19b0669
PZ		 3552 intel_ddi_prepare_link_retrain(encoder);
3553
3cf2efb1 3554 /* Write the link configuration data */
6aba5b6c
JN		 3555 link_config[0] = intel_dp->link_bw;
3556 link_config[1] = intel_dp->lane_count;
3557 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3558 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3559 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3560
3561 link_config[0] = 0;
3562 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3563 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3564
3565 DP |= DP_PORT_EN;
1a2eb460 3566
70aff66c
JN		 3567 /* clock recovery */
3568 if (!intel_dp_reset_link_train(intel_dp, &DP,
3569 DP_TRAINING_PATTERN_1 |
3570 DP_LINK_SCRAMBLING_DISABLE)) {
3571 DRM_ERROR("failed to enable link training\n");
3572 return;
3573 }
3574
a4fc5ed6 3575 voltage = 0xff;
cdb0e95b
KP		 3576 voltage_tries = 0;
3577 loop_tries = 0;
a4fc5ed6 3578 for (;;) {
70aff66c 3579 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3580
a7c9655f 3581 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3582 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3583 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3584 break;
93f62dad 3585 }
a4fc5ed6 3586
01916270 3587 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3588 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3589 break;
3590 }
3591
3592 /* Check to see if we've tried the max voltage */
3593 for (i = 0; i < intel_dp->lane_count; i++)
3594 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3595 break;
3b4f819d 3596 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3597 ++loop_tries;
3598 if (loop_tries == 5) {
3def84b3 3599 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3600 break;
3601 }
70aff66c
JN		 3602 intel_dp_reset_link_train(intel_dp, &DP,
3603 DP_TRAINING_PATTERN_1 |
3604 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3605 voltage_tries = 0;
3606 continue;
3607 }
a4fc5ed6 3608
3cf2efb1 3609 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3610 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3611 ++voltage_tries;
b06fbda3 3612 if (voltage_tries == 5) {
3def84b3 3613 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3614 break;
3615 }
3616 } else
3617 voltage_tries = 0;
3618 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3619
70aff66c
JN		 3620 /* Update training set as requested by target */
3621 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3622 DRM_ERROR("failed to update link training\n");
3623 break;
3624 }
a4fc5ed6
KP		 3625 }
3626
33a34e4e
JB		 3627 intel_dp->DP = DP;
3628}
3629
c19b0669 3630void
33a34e4e
JB		 3631intel_dp_complete_link_train(struct intel_dp *intel_dp)
3632{
33a34e4e 3633 bool channel_eq = false;
37f80975 3634 int tries, cr_tries;
33a34e4e 3635 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3636 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3637
3638 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3639 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3640 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3641
a4fc5ed6 3642 /* channel equalization */
70aff66c 3643 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3644 training_pattern |
70aff66c
JN		 3645 DP_LINK_SCRAMBLING_DISABLE)) {
3646 DRM_ERROR("failed to start channel equalization\n");
3647 return;
3648 }
3649
a4fc5ed6 3650 tries = 0;
37f80975 3651 cr_tries = 0;
a4fc5ed6
KP		 3652 channel_eq = false;
3653 for (;;) {
70aff66c 3654 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3655
37f80975
JB		 3656 if (cr_tries > 5) {
3657 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3658 break;
3659 }
3660
a7c9655f 3661 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3662 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3663 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3664 break;
70aff66c 3665 }
a4fc5ed6 3666
37f80975 3667 /* Make sure clock is still ok */
01916270 3668 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3669 intel_dp_start_link_train(intel_dp);
70aff66c 3670 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3671 training_pattern |
70aff66c 3672 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3673 cr_tries++;
3674 continue;
3675 }
3676
1ffdff13 3677 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3678 channel_eq = true;
3679 break;
3680 }
a4fc5ed6 3681
37f80975
JB		 3682 /* Try 5 times, then try clock recovery if that fails */
3683 if (tries > 5) {
3684 intel_dp_link_down(intel_dp);
3685 intel_dp_start_link_train(intel_dp);
70aff66c 3686 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3687 training_pattern |
70aff66c 3688 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3689 tries = 0;
3690 cr_tries++;
3691 continue;
3692 }
a4fc5ed6 3693
70aff66c
JN		 3694 /* Update training set as requested by target */
3695 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3696 DRM_ERROR("failed to update link training\n");
3697 break;
3698 }
3cf2efb1 3699 ++tries;
869184a6 3700 }
3cf2efb1 3701
3ab9c637
ID		 3702 intel_dp_set_idle_link_train(intel_dp);
3703
3704 intel_dp->DP = DP;
3705
d6c0d722 3706 if (channel_eq)
07f42258 3707 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3708
3ab9c637
ID		 3709}
3710
3711void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3712{
70aff66c 3713 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3714 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3715}
3716
3717static void
ea5b213a 3718intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3719{
da63a9f2 3720 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3721 enum port port = intel_dig_port->port;
da63a9f2 3722 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3723 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3724 struct intel_crtc *intel_crtc =
3725 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3726 uint32_t DP = intel_dp->DP;
a4fc5ed6 3727
bc76e320 3728 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3729 return;
3730
0c33d8d7 3731 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3732 return;
3733
28c97730 3734 DRM_DEBUG_KMS("\n");
32f9d658 3735
bc7d38a4 3736 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3737 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3738 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3739 } else {
aad3d14d
VS		 3740 if (IS_CHERRYVIEW(dev))
3741 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3742 else
3743 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3744 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3745 }
fe255d00 3746 POSTING_READ(intel_dp->output_reg);
5eb08b69 3747
493a7081 3748 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3749 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3750 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3751
5bddd17f
EA		 3752 /* Hardware workaround: leaving our transcoder select
3753 * set to transcoder B while it's off will prevent the
3754 * corresponding HDMI output on transcoder A.
3755 *
3756 * Combine this with another hardware workaround:
3757 * transcoder select bit can only be cleared while the
3758 * port is enabled.
3759 */
3760 DP &= ~DP_PIPEB_SELECT;
3761 I915_WRITE(intel_dp->output_reg, DP);
3762
3763 /* Changes to enable or select take place the vblank
3764 * after being written.
3765 */
ff50afe9
DV		 3766 if (WARN_ON(crtc == NULL)) {
3767 /* We should never try to disable a port without a crtc
3768 * attached. For paranoia keep the code around for a
3769 * bit. */
31acbcc4
CW		 3770 POSTING_READ(intel_dp->output_reg);
3771 msleep(50);
3772 } else
ab527efc 3773 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3774 }
3775
832afda6 3776 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3777 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3778 POSTING_READ(intel_dp->output_reg);
f01eca2e 3779 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3780}
3781
26d61aad
KP		 3782static bool
3783intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3784{
a031d709
RV		 3785 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3786 struct drm_device *dev = dig_port->base.base.dev;
3787 struct drm_i915_private *dev_priv = dev->dev_private;
3788
9d1a1031
JN		 3789 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3790 sizeof(intel_dp->dpcd)) < 0)
edb39244 3791 return false; /* aux transfer failed */
92fd8fd1 3792
a8e98153 3793 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3794
edb39244
AJ		 3795 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3796 return false; /* DPCD not present */
3797
2293bb5c
SK		 3798 /* Check if the panel supports PSR */
3799 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3800 if (is_edp(intel_dp)) {
9d1a1031
JN		 3801 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3802 intel_dp->psr_dpcd,
3803 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3804 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3805 dev_priv->psr.sink_support = true;
50003939 3806 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3807 }
50003939
JN		 3808 }
3809
06ea66b6
TP		 3810 /* Training Pattern 3 support */
3811 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3812 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3813 intel_dp->use_tps3 = true;
f8d8a672 3814 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3815 } else
3816 intel_dp->use_tps3 = false;
3817
edb39244
AJ		 3818 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3819 DP_DWN_STRM_PORT_PRESENT))
3820 return true; /* native DP sink */
3821
3822 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3823 return true; /* no per-port downstream info */
3824
9d1a1031
JN		 3825 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3826 intel_dp->downstream_ports,
3827 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3828 return false; /* downstream port status fetch failed */
3829
3830 return true;
92fd8fd1
KP		 3831}
3832
0d198328
AJ		 3833static void
3834intel_dp_probe_oui(struct intel_dp *intel_dp)
3835{
3836 u8 buf[3];
3837
3838 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3839 return;
3840
9d1a1031 3841 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3842 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3843 buf[0], buf[1], buf[2]);
3844
9d1a1031 3845 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3846 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3847 buf[0], buf[1], buf[2]);
3848}
3849
0e32b39c
DA		 3850static bool
3851intel_dp_probe_mst(struct intel_dp *intel_dp)
3852{
3853 u8 buf[1];
3854
3855 if (!intel_dp->can_mst)
3856 return false;
3857
3858 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3859 return false;
3860
0e32b39c
DA		 3861 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3862 if (buf[0] & DP_MST_CAP) {
3863 DRM_DEBUG_KMS("Sink is MST capable\n");
3864 intel_dp->is_mst = true;
3865 } else {
3866 DRM_DEBUG_KMS("Sink is not MST capable\n");
3867 intel_dp->is_mst = false;
3868 }
3869 }
0e32b39c
DA		 3870
3871 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3872 return intel_dp->is_mst;
3873}
3874
d2e216d0
RV		 3875int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3876{
3877 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3878 struct drm_device *dev = intel_dig_port->base.base.dev;
3879 struct intel_crtc *intel_crtc =
3880 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3881 u8 buf;
3882 int test_crc_count;
3883 int attempts = 6;
d2e216d0 3884
ad9dc91b 3885 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3886 return -EIO;
d2e216d0 3887
ad9dc91b 3888 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3889 return -ENOTTY;
3890
1dda5f93
RV		 3891 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3892 return -EIO;
3893
9d1a1031 3894 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3895 buf | DP_TEST_SINK_START) < 0)
bda0381e 3896 return -EIO;
d2e216d0 3897
1dda5f93 3898 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3899 return -EIO;
ad9dc91b 3900 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 3901
ad9dc91b 3902 do {
1dda5f93
RV		 3903 if (drm_dp_dpcd_readb(&intel_dp->aux,
3904 DP_TEST_SINK_MISC, &buf) < 0)
3905 return -EIO;
ad9dc91b
RV		 3906 intel_wait_for_vblank(dev, intel_crtc->pipe);
3907 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3908
3909 if (attempts == 0) {
3910 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
3911 return -EIO;
3912 }
d2e216d0 3913
9d1a1031 3914 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 3915 return -EIO;
d2e216d0 3916
1dda5f93
RV		 3917 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3918 return -EIO;
3919 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3920 buf & ~DP_TEST_SINK_START) < 0)
3921 return -EIO;
ce31d9f4 3922
d2e216d0
RV		 3923 return 0;
3924}
3925
a60f0e38
JB		 3926static bool
3927intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3928{
9d1a1031
JN		 3929 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3930 DP_DEVICE_SERVICE_IRQ_VECTOR,
3931 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3932}
3933
0e32b39c
DA		 3934static bool
3935intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3936{
3937 int ret;
3938
3939 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3940 DP_SINK_COUNT_ESI,
3941 sink_irq_vector, 14);
3942 if (ret != 14)
3943 return false;
3944
3945 return true;
3946}
3947
a60f0e38
JB		 3948static void
3949intel_dp_handle_test_request(struct intel_dp *intel_dp)
3950{
3951 /* NAK by default */
9d1a1031 3952 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3953}
3954
0e32b39c
DA		 3955static int
3956intel_dp_check_mst_status(struct intel_dp *intel_dp)
3957{
3958 bool bret;
3959
3960 if (intel_dp->is_mst) {
3961 u8 esi[16] = { 0 };
3962 int ret = 0;
3963 int retry;
3964 bool handled;
3965 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3966go_again:
3967 if (bret == true) {
3968
3969 /* check link status - esi[10] = 0x200c */
3970 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3971 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3972 intel_dp_start_link_train(intel_dp);
3973 intel_dp_complete_link_train(intel_dp);
3974 intel_dp_stop_link_train(intel_dp);
3975 }
3976
3977 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3978 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3979
3980 if (handled) {
3981 for (retry = 0; retry < 3; retry++) {
3982 int wret;
3983 wret = drm_dp_dpcd_write(&intel_dp->aux,
3984 DP_SINK_COUNT_ESI+1,
3985 &esi[1], 3);
3986 if (wret == 3) {
3987 break;
3988 }
3989 }
3990
3991 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3992 if (bret == true) {
3993 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3994 goto go_again;
3995 }
3996 } else
3997 ret = 0;
3998
3999 return ret;
4000 } else {
4001 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4002 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4003 intel_dp->is_mst = false;
4004 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4005 /* send a hotplug event */
4006 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4007 }
4008 }
4009 return -EINVAL;
4010}
4011
a4fc5ed6
KP		 4012/*
4013 * According to DP spec
4014 * 5.1.2:
4015 * 1. Read DPCD
4016 * 2. Configure link according to Receiver Capabilities
4017 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4018 * 4. Check link status on receipt of hot-plug interrupt
4019 */
00c09d70 4020void
ea5b213a 4021intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4022{
5b215bcf 4023 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4024 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4025 u8 sink_irq_vector;
93f62dad 4026 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4027
5b215bcf
DA		 4028 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4029
da63a9f2 4030 if (!intel_encoder->connectors_active)
d2b996ac 4031 return;
59cd09e1 4032
da63a9f2 4033 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 4034 return;
4035
1a125d8a
ID		 4036 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4037 return;
4038
92fd8fd1 4039 /* Try to read receiver status if the link appears to be up */
93f62dad 4040 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4041 return;
4042 }
4043
92fd8fd1 4044 /* Now read the DPCD to see if it's actually running */
26d61aad 4045 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4046 return;
4047 }
4048
a60f0e38
JB		 4049 /* Try to read the source of the interrupt */
4050 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4051 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4052 /* Clear interrupt source */
9d1a1031
JN		 4053 drm_dp_dpcd_writeb(&intel_dp->aux,
4054 DP_DEVICE_SERVICE_IRQ_VECTOR,
4055 sink_irq_vector);
a60f0e38
JB		 4056
4057 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4058 intel_dp_handle_test_request(intel_dp);
4059 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4060 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4061 }
4062
1ffdff13 4063 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4064 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4065 intel_encoder->base.name);
33a34e4e
JB		 4066 intel_dp_start_link_train(intel_dp);
4067 intel_dp_complete_link_train(intel_dp);
3ab9c637 4068 intel_dp_stop_link_train(intel_dp);
33a34e4e 4069 }
a4fc5ed6 4070}
a4fc5ed6 4071
caf9ab24 4072/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4073static enum drm_connector_status
26d61aad 4074intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4075{
caf9ab24 4076 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4077 uint8_t type;
4078
4079 if (!intel_dp_get_dpcd(intel_dp))
4080 return connector_status_disconnected;
4081
4082 /* if there's no downstream port, we're done */
4083 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4084 return connector_status_connected;
caf9ab24
AJ		 4085
4086 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4087 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4088 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4089 uint8_t reg;
9d1a1031
JN		 4090
4091 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4092 &reg, 1) < 0)
caf9ab24 4093 return connector_status_unknown;
9d1a1031 4094
23235177
AJ		 4095 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4096 : connector_status_disconnected;
caf9ab24
AJ		 4097 }
4098
4099 /* If no HPD, poke DDC gently */
0b99836f 4100 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4101 return connector_status_connected;
caf9ab24
AJ		 4102
4103 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4104 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4105 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4106 if (type == DP_DS_PORT_TYPE_VGA ||
4107 type == DP_DS_PORT_TYPE_NON_EDID)
4108 return connector_status_unknown;
4109 } else {
4110 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4111 DP_DWN_STRM_PORT_TYPE_MASK;
4112 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4113 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4114 return connector_status_unknown;
4115 }
caf9ab24
AJ		 4116
4117 /* Anything else is out of spec, warn and ignore */
4118 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4119 return connector_status_disconnected;
71ba9000
AJ		 4120}
4121
d410b56d
CW		 4122static enum drm_connector_status
4123edp_detect(struct intel_dp *intel_dp)
4124{
4125 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4126 enum drm_connector_status status;
4127
4128 status = intel_panel_detect(dev);
4129 if (status == connector_status_unknown)
4130 status = connector_status_connected;
4131
4132 return status;
4133}
4134
5eb08b69 4135static enum drm_connector_status
a9756bb5 4136ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4137{
30add22d 4138 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4139 struct drm_i915_private *dev_priv = dev->dev_private;
4140 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4141
1b469639
DL		 4142 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4143 return connector_status_disconnected;
4144
26d61aad 4145 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4146}
4147
2a592bec
DA		 4148static int g4x_digital_port_connected(struct drm_device *dev,
4149 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4150{
a4fc5ed6 4151 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4152 uint32_t bit;
5eb08b69 4153
232a6ee9
TP		 4154 if (IS_VALLEYVIEW(dev)) {
4155 switch (intel_dig_port->port) {
4156 case PORT_B:
4157 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4158 break;
4159 case PORT_C:
4160 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4161 break;
4162 case PORT_D:
4163 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4164 break;
4165 default:
2a592bec 4166 return -EINVAL;
232a6ee9
TP		 4167 }
4168 } else {
4169 switch (intel_dig_port->port) {
4170 case PORT_B:
4171 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4172 break;
4173 case PORT_C:
4174 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4175 break;
4176 case PORT_D:
4177 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4178 break;
4179 default:
2a592bec 4180 return -EINVAL;
232a6ee9 4181 }
a4fc5ed6
KP		 4182 }
4183
10f76a38 4184 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4185 return 0;
4186 return 1;
4187}
4188
4189static enum drm_connector_status
4190g4x_dp_detect(struct intel_dp *intel_dp)
4191{
4192 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4193 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4194 int ret;
4195
4196 /* Can't disconnect eDP, but you can close the lid... */
4197 if (is_edp(intel_dp)) {
4198 enum drm_connector_status status;
4199
4200 status = intel_panel_detect(dev);
4201 if (status == connector_status_unknown)
4202 status = connector_status_connected;
4203 return status;
4204 }
4205
4206 ret = g4x_digital_port_connected(dev, intel_dig_port);
4207 if (ret == -EINVAL)
4208 return connector_status_unknown;
4209 else if (ret == 0)
a4fc5ed6
KP		 4210 return connector_status_disconnected;
4211
26d61aad 4212 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4213}
4214
8c241fef 4215static struct edid *
beb60608 4216intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4217{
beb60608 4218 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4219
9cd300e0
JN		 4220 /* use cached edid if we have one */
4221 if (intel_connector->edid) {
9cd300e0
JN		 4222 /* invalid edid */
4223 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4224 return NULL;
4225
55e9edeb 4226 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4227 } else
4228 return drm_get_edid(&intel_connector->base,
4229 &intel_dp->aux.ddc);
4230}
8c241fef 4231
beb60608
CW		 4232static void
4233intel_dp_set_edid(struct intel_dp *intel_dp)
4234{
4235 struct intel_connector *intel_connector = intel_dp->attached_connector;
4236 struct edid *edid;
8c241fef 4237
beb60608
CW		 4238 edid = intel_dp_get_edid(intel_dp);
4239 intel_connector->detect_edid = edid;
4240
4241 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4242 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4243 else
4244 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4245}
4246
beb60608
CW		 4247static void
4248intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4249{
beb60608 4250 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4251
beb60608
CW		 4252 kfree(intel_connector->detect_edid);
4253 intel_connector->detect_edid = NULL;
9cd300e0 4254
beb60608
CW		 4255 intel_dp->has_audio = false;
4256}
d6f24d0f 4257
beb60608
CW		 4258static enum intel_display_power_domain
4259intel_dp_power_get(struct intel_dp *dp)
4260{
4261 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4262 enum intel_display_power_domain power_domain;
4263
4264 power_domain = intel_display_port_power_domain(encoder);
4265 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4266
4267 return power_domain;
4268}
d6f24d0f 4269
beb60608
CW		 4270static void
4271intel_dp_power_put(struct intel_dp *dp,
4272 enum intel_display_power_domain power_domain)
4273{
4274 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4275 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4276}
4277
a9756bb5
ZW		 4278static enum drm_connector_status
4279intel_dp_detect(struct drm_connector *connector, bool force)
4280{
4281 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4282 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4283 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4284 struct drm_device *dev = connector->dev;
a9756bb5 4285 enum drm_connector_status status;
671dedd2 4286 enum intel_display_power_domain power_domain;
0e32b39c 4287 bool ret;
a9756bb5 4288
164c8598 4289 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4290 connector->base.id, connector->name);
beb60608 4291 intel_dp_unset_edid(intel_dp);
164c8598 4292
0e32b39c
DA		 4293 if (intel_dp->is_mst) {
4294 /* MST devices are disconnected from a monitor POV */
4295 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4296 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4297 return connector_status_disconnected;
0e32b39c
DA		 4298 }
4299
beb60608 4300 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4301
d410b56d
CW		 4302 /* Can't disconnect eDP, but you can close the lid... */
4303 if (is_edp(intel_dp))
4304 status = edp_detect(intel_dp);
4305 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4306 status = ironlake_dp_detect(intel_dp);
4307 else
4308 status = g4x_dp_detect(intel_dp);
4309 if (status != connector_status_connected)
c8c8fb33 4310 goto out;
a9756bb5 4311
0d198328
AJ		 4312 intel_dp_probe_oui(intel_dp);
4313
0e32b39c
DA		 4314 ret = intel_dp_probe_mst(intel_dp);
4315 if (ret) {
4316 /* if we are in MST mode then this connector
4317 won't appear connected or have anything with EDID on it */
4318 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4319 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4320 status = connector_status_disconnected;
4321 goto out;
4322 }
4323
beb60608 4324 intel_dp_set_edid(intel_dp);
a9756bb5 4325
d63885da
PZ		 4326 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4327 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4328 status = connector_status_connected;
4329
4330out:
beb60608 4331 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4332 return status;
a4fc5ed6
KP		 4333}
4334
beb60608
CW		 4335static void
4336intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4337{
df0e9248 4338 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4339 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4340 enum intel_display_power_domain power_domain;
a4fc5ed6 4341
beb60608
CW		 4342 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4343 connector->base.id, connector->name);
4344 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4345
beb60608
CW		 4346 if (connector->status != connector_status_connected)
4347 return;
671dedd2 4348
beb60608
CW		 4349 power_domain = intel_dp_power_get(intel_dp);
4350
4351 intel_dp_set_edid(intel_dp);
4352
4353 intel_dp_power_put(intel_dp, power_domain);
4354
4355 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4356 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4357}
4358
4359static int intel_dp_get_modes(struct drm_connector *connector)
4360{
4361 struct intel_connector *intel_connector = to_intel_connector(connector);
4362 struct edid *edid;
4363
4364 edid = intel_connector->detect_edid;
4365 if (edid) {
4366 int ret = intel_connector_update_modes(connector, edid);
4367 if (ret)
4368 return ret;
4369 }
32f9d658 4370
f8779fda 4371 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4372 if (is_edp(intel_attached_dp(connector)) &&
4373 intel_connector->panel.fixed_mode) {
f8779fda 4374 struct drm_display_mode *mode;
beb60608
CW		 4375
4376 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4377 intel_connector->panel.fixed_mode);
f8779fda 4378 if (mode) {
32f9d658
ZW		 4379 drm_mode_probed_add(connector, mode);
4380 return 1;
4381 }
4382 }
beb60608 4383
32f9d658 4384 return 0;
a4fc5ed6
KP		 4385}
4386
1aad7ac0
CW		 4387static bool
4388intel_dp_detect_audio(struct drm_connector *connector)
4389{
1aad7ac0 4390 bool has_audio = false;
beb60608 4391 struct edid *edid;
1aad7ac0 4392
beb60608
CW		 4393 edid = to_intel_connector(connector)->detect_edid;
4394 if (edid)
1aad7ac0 4395 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4396
1aad7ac0
CW		 4397 return has_audio;
4398}
4399
f684960e
CW		 4400static int
4401intel_dp_set_property(struct drm_connector *connector,
4402 struct drm_property *property,
4403 uint64_t val)
4404{
e953fd7b 4405 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4406 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4407 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4408 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4409 int ret;
4410
662595df 4411 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4412 if (ret)
4413 return ret;
4414
3f43c48d 4415 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4416 int i = val;
4417 bool has_audio;
4418
4419 if (i == intel_dp->force_audio)
f684960e
CW		 4420 return 0;
4421
1aad7ac0 4422 intel_dp->force_audio = i;
f684960e 4423
c3e5f67b 4424 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4425 has_audio = intel_dp_detect_audio(connector);
4426 else
c3e5f67b 4427 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4428
4429 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4430 return 0;
4431
1aad7ac0 4432 intel_dp->has_audio = has_audio;
f684960e
CW		 4433 goto done;
4434 }
4435
e953fd7b 4436 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4437 bool old_auto = intel_dp->color_range_auto;
4438 uint32_t old_range = intel_dp->color_range;
4439
55bc60db
VS		 4440 switch (val) {
4441 case INTEL_BROADCAST_RGB_AUTO:
4442 intel_dp->color_range_auto = true;
4443 break;
4444 case INTEL_BROADCAST_RGB_FULL:
4445 intel_dp->color_range_auto = false;
4446 intel_dp->color_range = 0;
4447 break;
4448 case INTEL_BROADCAST_RGB_LIMITED:
4449 intel_dp->color_range_auto = false;
4450 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4451 break;
4452 default:
4453 return -EINVAL;
4454 }
ae4edb80
DV		 4455
4456 if (old_auto == intel_dp->color_range_auto &&
4457 old_range == intel_dp->color_range)
4458 return 0;
4459
e953fd7b
CW		 4460 goto done;
4461 }
4462
53b41837
YN		 4463 if (is_edp(intel_dp) &&
4464 property == connector->dev->mode_config.scaling_mode_property) {
4465 if (val == DRM_MODE_SCALE_NONE) {
4466 DRM_DEBUG_KMS("no scaling not supported\n");
4467 return -EINVAL;
4468 }
4469
4470 if (intel_connector->panel.fitting_mode == val) {
4471 /* the eDP scaling property is not changed */
4472 return 0;
4473 }
4474 intel_connector->panel.fitting_mode = val;
4475
4476 goto done;
4477 }
4478
f684960e
CW		 4479 return -EINVAL;
4480
4481done:
c0c36b94
CW		 4482 if (intel_encoder->base.crtc)
4483 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4484
4485 return 0;
4486}
4487
a4fc5ed6 4488static void
73845adf 4489intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4490{
1d508706 4491 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4492
10e972d3 4493 kfree(intel_connector->detect_edid);
beb60608 4494
9cd300e0
JN		 4495 if (!IS_ERR_OR_NULL(intel_connector->edid))
4496 kfree(intel_connector->edid);
4497
acd8db10
PZ		 4498 /* Can't call is_edp() since the encoder may have been destroyed
4499 * already. */
4500 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4501 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4502
a4fc5ed6 4503 drm_connector_cleanup(connector);
55f78c43 4504 kfree(connector);
a4fc5ed6
KP		 4505}
4506
00c09d70 4507void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4508{
da63a9f2
PZ		 4509 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4510 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4511
4f71d0cb 4512 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4513 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4514 drm_encoder_cleanup(encoder);
bd943159
KP		 4515 if (is_edp(intel_dp)) {
4516 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4517 /*
4518 * vdd might still be enabled do to the delayed vdd off.
4519 * Make sure vdd is actually turned off here.
4520 */
773538e8 4521 pps_lock(intel_dp);
4be73780 4522 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4523 pps_unlock(intel_dp);
4524
01527b31
CT		 4525 if (intel_dp->edp_notifier.notifier_call) {
4526 unregister_reboot_notifier(&intel_dp->edp_notifier);
4527 intel_dp->edp_notifier.notifier_call = NULL;
4528 }
bd943159 4529 }
da63a9f2 4530 kfree(intel_dig_port);
24d05927
DV		 4531}
4532
07f9cd0b
ID		 4533static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4534{
4535 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4536
4537 if (!is_edp(intel_dp))
4538 return;
4539
951468f3
VS		 4540 /*
4541 * vdd might still be enabled do to the delayed vdd off.
4542 * Make sure vdd is actually turned off here.
4543 */
773538e8 4544 pps_lock(intel_dp);
07f9cd0b 4545 edp_panel_vdd_off_sync(intel_dp);
773538e8 4546 pps_unlock(intel_dp);
07f9cd0b
ID		 4547}
4548
6d93c0c4
ID		 4549static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4550{
4551 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4552}
4553
a4fc5ed6 4554static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4555 .dpms = intel_connector_dpms,
a4fc5ed6 4556 .detect = intel_dp_detect,
beb60608 4557 .force = intel_dp_force,
a4fc5ed6 4558 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4559 .set_property = intel_dp_set_property,
73845adf 4560 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4561};
4562
4563static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4564 .get_modes = intel_dp_get_modes,
4565 .mode_valid = intel_dp_mode_valid,
df0e9248 4566 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4567};
4568
a4fc5ed6 4569static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4570 .reset = intel_dp_encoder_reset,
24d05927 4571 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4572};
4573
0e32b39c 4574void
21d40d37 4575intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4576{
0e32b39c 4577 return;
c8110e52 4578}
6207937d 4579
13cf5504
DA		 4580bool
4581intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4582{
4583 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4584 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4585 struct drm_device *dev = intel_dig_port->base.base.dev;
4586 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4587 enum intel_display_power_domain power_domain;
4588 bool ret = true;
4589
0e32b39c
DA		 4590 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4591 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4592
26fbb774
VS		 4593 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4594 port_name(intel_dig_port->port),
0e32b39c 4595 long_hpd ? "long" : "short");
13cf5504 4596
1c767b33
ID		 4597 power_domain = intel_display_port_power_domain(intel_encoder);
4598 intel_display_power_get(dev_priv, power_domain);
4599
0e32b39c 4600 if (long_hpd) {
2a592bec
DA		 4601
4602 if (HAS_PCH_SPLIT(dev)) {
4603 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4604 goto mst_fail;
4605 } else {
4606 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4607 goto mst_fail;
4608 }
0e32b39c
DA		 4609
4610 if (!intel_dp_get_dpcd(intel_dp)) {
4611 goto mst_fail;
4612 }
4613
4614 intel_dp_probe_oui(intel_dp);
4615
4616 if (!intel_dp_probe_mst(intel_dp))
4617 goto mst_fail;
4618
4619 } else {
4620 if (intel_dp->is_mst) {
1c767b33 4621 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4622 goto mst_fail;
4623 }
4624
4625 if (!intel_dp->is_mst) {
4626 /*
4627 * we'll check the link status via the normal hot plug path later -
4628 * but for short hpds we should check it now
4629 */
5b215bcf 4630 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4631 intel_dp_check_link_status(intel_dp);
5b215bcf 4632 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4633 }
4634 }
1c767b33
ID		 4635 ret = false;
4636 goto put_power;
0e32b39c
DA		 4637mst_fail:
4638 /* if we were in MST mode, and device is not there get out of MST mode */
4639 if (intel_dp->is_mst) {
4640 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4641 intel_dp->is_mst = false;
4642 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4643 }
1c767b33
ID		 4644put_power:
4645 intel_display_power_put(dev_priv, power_domain);
4646
4647 return ret;
13cf5504
DA		 4648}
4649
e3421a18
ZW		 4650/* Return which DP Port should be selected for Transcoder DP control */
4651int
0206e353 4652intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4653{
4654 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4655 struct intel_encoder *intel_encoder;
4656 struct intel_dp *intel_dp;
e3421a18 4657
fa90ecef
PZ		 4658 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4659 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4660
fa90ecef
PZ		 4661 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4662 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4663 return intel_dp->output_reg;
e3421a18 4664 }
ea5b213a 4665
e3421a18
ZW		 4666 return -1;
4667}
4668
36e83a18 4669/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4670bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4671{
4672 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4673 union child_device_config *p_child;
36e83a18 4674 int i;
5d8a7752
VS		 4675 static const short port_mapping[] = {
4676 [PORT_B] = PORT_IDPB,
4677 [PORT_C] = PORT_IDPC,
4678 [PORT_D] = PORT_IDPD,
4679 };
36e83a18 4680
3b32a35b
VS		 4681 if (port == PORT_A)
4682 return true;
4683
41aa3448 4684 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4685 return false;
4686
41aa3448
RV		 4687 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4688 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4689
5d8a7752 4690 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4691 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4692 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4693 return true;
4694 }
4695 return false;
4696}
4697
0e32b39c 4698void
f684960e
CW		 4699intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4700{
53b41837
YN		 4701 struct intel_connector *intel_connector = to_intel_connector(connector);
4702
3f43c48d 4703 intel_attach_force_audio_property(connector);
e953fd7b 4704 intel_attach_broadcast_rgb_property(connector);
55bc60db 4705 intel_dp->color_range_auto = true;
53b41837
YN		 4706
4707 if (is_edp(intel_dp)) {
4708 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4709 drm_object_attach_property(
4710 &connector->base,
53b41837 4711 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4712 DRM_MODE_SCALE_ASPECT);
4713 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4714 }
f684960e
CW		 4715}
4716
dada1a9f
ID		 4717static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4718{
4719 intel_dp->last_power_cycle = jiffies;
4720 intel_dp->last_power_on = jiffies;
4721 intel_dp->last_backlight_off = jiffies;
4722}
4723
67a54566
DV		 4724static void
4725intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4726 struct intel_dp *intel_dp)
67a54566
DV		 4727{
4728 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4729 struct edp_power_seq cur, vbt, spec,
4730 *final = &intel_dp->pps_delays;
67a54566 4731 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4732 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4733
e39b999a
VS		 4734 lockdep_assert_held(&dev_priv->pps_mutex);
4735
453c5420 4736 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4737 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4738 pp_on_reg = PCH_PP_ON_DELAYS;
4739 pp_off_reg = PCH_PP_OFF_DELAYS;
4740 pp_div_reg = PCH_PP_DIVISOR;
4741 } else {
bf13e81b
JN		 4742 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4743
4744 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4745 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4746 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4747 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4748 }
67a54566
DV		 4749
4750 /* Workaround: Need to write PP_CONTROL with the unlock key as
4751 * the very first thing. */
453c5420 4752 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4753 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4754
453c5420
JB		 4755 pp_on = I915_READ(pp_on_reg);
4756 pp_off = I915_READ(pp_off_reg);
4757 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4758
4759 /* Pull timing values out of registers */
4760 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4761 PANEL_POWER_UP_DELAY_SHIFT;
4762
4763 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4764 PANEL_LIGHT_ON_DELAY_SHIFT;
4765
4766 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4767 PANEL_LIGHT_OFF_DELAY_SHIFT;
4768
4769 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4770 PANEL_POWER_DOWN_DELAY_SHIFT;
4771
4772 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4773 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4774
4775 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4776 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4777
41aa3448 4778 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4779
4780 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4781 * our hw here, which are all in 100usec. */
4782 spec.t1_t3 = 210 * 10;
4783 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4784 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4785 spec.t10 = 500 * 10;
4786 /* This one is special and actually in units of 100ms, but zero
4787 * based in the hw (so we need to add 100 ms). But the sw vbt
4788 * table multiplies it with 1000 to make it in units of 100usec,
4789 * too. */
4790 spec.t11_t12 = (510 + 100) * 10;
4791
4792 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4793 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4794
4795 /* Use the max of the register settings and vbt. If both are
4796 * unset, fall back to the spec limits. */
36b5f425 4797#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4798 spec.field : \
4799 max(cur.field, vbt.field))
4800 assign_final(t1_t3);
4801 assign_final(t8);
4802 assign_final(t9);
4803 assign_final(t10);
4804 assign_final(t11_t12);
4805#undef assign_final
4806
36b5f425 4807#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4808 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4809 intel_dp->backlight_on_delay = get_delay(t8);
4810 intel_dp->backlight_off_delay = get_delay(t9);
4811 intel_dp->panel_power_down_delay = get_delay(t10);
4812 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4813#undef get_delay
4814
f30d26e4
JN		 4815 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4816 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4817 intel_dp->panel_power_cycle_delay);
4818
4819 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4820 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 4821}
4822
4823static void
4824intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4825 struct intel_dp *intel_dp)
f30d26e4
JN		 4826{
4827 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4828 u32 pp_on, pp_off, pp_div, port_sel = 0;
4829 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4830 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4831 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4832 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4833
e39b999a 4834 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4835
4836 if (HAS_PCH_SPLIT(dev)) {
4837 pp_on_reg = PCH_PP_ON_DELAYS;
4838 pp_off_reg = PCH_PP_OFF_DELAYS;
4839 pp_div_reg = PCH_PP_DIVISOR;
4840 } else {
bf13e81b
JN		 4841 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4842
4843 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4844 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4845 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4846 }
4847
b2f19d1a
PZ		 4848 /*
4849 * And finally store the new values in the power sequencer. The
4850 * backlight delays are set to 1 because we do manual waits on them. For
4851 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4852 * we'll end up waiting for the backlight off delay twice: once when we
4853 * do the manual sleep, and once when we disable the panel and wait for
4854 * the PP_STATUS bit to become zero.
4855 */
f30d26e4 4856 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4857 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4858 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4859 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4860 /* Compute the divisor for the pp clock, simply match the Bspec
4861 * formula. */
453c5420 4862 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4863 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4864 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4865
4866 /* Haswell doesn't have any port selection bits for the panel
4867 * power sequencer any more. */
bc7d38a4 4868 if (IS_VALLEYVIEW(dev)) {
ad933b56 4869 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4870 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4871 if (port == PORT_A)
a24c144c 4872 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4873 else
a24c144c 4874 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4875 }
4876
453c5420
JB		 4877 pp_on |= port_sel;
4878
4879 I915_WRITE(pp_on_reg, pp_on);
4880 I915_WRITE(pp_off_reg, pp_off);
4881 I915_WRITE(pp_div_reg, pp_div);
67a54566 4882
67a54566 4883 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4884 I915_READ(pp_on_reg),
4885 I915_READ(pp_off_reg),
4886 I915_READ(pp_div_reg));
f684960e
CW		 4887}
4888
439d7ac0
PB		 4889void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4890{
4891 struct drm_i915_private *dev_priv = dev->dev_private;
4892 struct intel_encoder *encoder;
4893 struct intel_dp *intel_dp = NULL;
4894 struct intel_crtc_config *config = NULL;
4895 struct intel_crtc *intel_crtc = NULL;
4896 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4897 u32 reg, val;
4898 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4899
4900 if (refresh_rate <= 0) {
4901 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4902 return;
4903 }
4904
4905 if (intel_connector == NULL) {
4906 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4907 return;
4908 }
4909
1fcc9d1c
DV		 4910 /*
4911 * FIXME: This needs proper synchronization with psr state. But really
4912 * hard to tell without seeing the user of this function of this code.
4913 * Check locking and ordering once that lands.
4914 */
439d7ac0
PB		 4915 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4916 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4917 return;
4918 }
4919
4920 encoder = intel_attached_encoder(&intel_connector->base);
4921 intel_dp = enc_to_intel_dp(&encoder->base);
4922 intel_crtc = encoder->new_crtc;
4923
4924 if (!intel_crtc) {
4925 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4926 return;
4927 }
4928
4929 config = &intel_crtc->config;
4930
4931 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4932 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4933 return;
4934 }
4935
4936 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4937 index = DRRS_LOW_RR;
4938
4939 if (index == intel_dp->drrs_state.refresh_rate_type) {
4940 DRM_DEBUG_KMS(
4941 "DRRS requested for previously set RR...ignoring\n");
4942 return;
4943 }
4944
4945 if (!intel_crtc->active) {
4946 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4947 return;
4948 }
4949
4950 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4951 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4952 val = I915_READ(reg);
4953 if (index > DRRS_HIGH_RR) {
4954 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4955 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4956 } else {
4957 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4958 }
4959 I915_WRITE(reg, val);
4960 }
4961
4962 /*
4963 * mutex taken to ensure that there is no race between differnt
4964 * drrs calls trying to update refresh rate. This scenario may occur
4965 * in future when idleness detection based DRRS in kernel and
4966 * possible calls from user space to set differnt RR are made.
4967 */
4968
4969 mutex_lock(&intel_dp->drrs_state.mutex);
4970
4971 intel_dp->drrs_state.refresh_rate_type = index;
4972
4973 mutex_unlock(&intel_dp->drrs_state.mutex);
4974
4975 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4976}
4977
4f9db5b5
PB		 4978static struct drm_display_mode *
4979intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4980 struct intel_connector *intel_connector,
4981 struct drm_display_mode *fixed_mode)
4982{
4983 struct drm_connector *connector = &intel_connector->base;
4984 struct intel_dp *intel_dp = &intel_dig_port->dp;
4985 struct drm_device *dev = intel_dig_port->base.base.dev;
4986 struct drm_i915_private *dev_priv = dev->dev_private;
4987 struct drm_display_mode *downclock_mode = NULL;
4988
4989 if (INTEL_INFO(dev)->gen <= 6) {
4990 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4991 return NULL;
4992 }
4993
4994 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4995 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4996 return NULL;
4997 }
4998
4999 downclock_mode = intel_find_panel_downclock
5000 (dev, fixed_mode, connector);
5001
5002 if (!downclock_mode) {
4079b8d1 5003 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 5004 return NULL;
5005 }
5006
439d7ac0
PB		 5007 dev_priv->drrs.connector = intel_connector;
5008
5009 mutex_init(&intel_dp->drrs_state.mutex);
5010
4f9db5b5
PB		 5011 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
5012
5013 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5014 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5015 return downclock_mode;
5016}
5017
aba86890
ID		 5018void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
5019{
5020 struct drm_device *dev = intel_encoder->base.dev;
5021 struct drm_i915_private *dev_priv = dev->dev_private;
5022 struct intel_dp *intel_dp;
5023 enum intel_display_power_domain power_domain;
5024
5025 if (intel_encoder->type != INTEL_OUTPUT_EDP)
5026 return;
5027
5028 intel_dp = enc_to_intel_dp(&intel_encoder->base);
773538e8
VS		 5029
5030 pps_lock(intel_dp);
5031
aba86890 5032 if (!edp_have_panel_vdd(intel_dp))
e39b999a 5033 goto out;
aba86890
ID		 5034 /*
5035 * The VDD bit needs a power domain reference, so if the bit is
5036 * already enabled when we boot or resume, grab this reference and
5037 * schedule a vdd off, so we don't hold on to the reference
5038 * indefinitely.
5039 */
5040 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5041 power_domain = intel_display_port_power_domain(intel_encoder);
5042 intel_display_power_get(dev_priv, power_domain);
5043
5044 edp_panel_vdd_schedule_off(intel_dp);
e39b999a 5045 out:
773538e8 5046 pps_unlock(intel_dp);
aba86890
ID		 5047}
5048
ed92f0b2 5049static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5050 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5051{
5052 struct drm_connector *connector = &intel_connector->base;
5053 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5054 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5055 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5056 struct drm_i915_private *dev_priv = dev->dev_private;
5057 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5058 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5059 bool has_dpcd;
5060 struct drm_display_mode *scan;
5061 struct edid *edid;
5062
4f9db5b5
PB		 5063 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
5064
ed92f0b2
PZ		 5065 if (!is_edp(intel_dp))
5066 return true;
5067
aba86890 5068 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 5069
ed92f0b2 5070 /* Cache DPCD and EDID for edp. */
ed92f0b2 5071 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5072
5073 if (has_dpcd) {
5074 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5075 dev_priv->no_aux_handshake =
5076 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5077 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5078 } else {
5079 /* if this fails, presume the device is a ghost */
5080 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5081 return false;
5082 }
5083
5084 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5085 pps_lock(intel_dp);
36b5f425 5086 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5087 pps_unlock(intel_dp);
ed92f0b2 5088
060c8778 5089 mutex_lock(&dev->mode_config.mutex);
0b99836f 5090 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5091 if (edid) {
5092 if (drm_add_edid_modes(connector, edid)) {
5093 drm_mode_connector_update_edid_property(connector,
5094 edid);
5095 drm_edid_to_eld(connector, edid);
5096 } else {
5097 kfree(edid);
5098 edid = ERR_PTR(-EINVAL);
5099 }
5100 } else {
5101 edid = ERR_PTR(-ENOENT);
5102 }
5103 intel_connector->edid = edid;
5104
5105 /* prefer fixed mode from EDID if available */
5106 list_for_each_entry(scan, &connector->probed_modes, head) {
5107 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5108 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 5109 downclock_mode = intel_dp_drrs_init(
5110 intel_dig_port,
5111 intel_connector, fixed_mode);
ed92f0b2
PZ		 5112 break;
5113 }
5114 }
5115
5116 /* fallback to VBT if available for eDP */
5117 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5118 fixed_mode = drm_mode_duplicate(dev,
5119 dev_priv->vbt.lfp_lvds_vbt_mode);
5120 if (fixed_mode)
5121 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5122 }
060c8778 5123 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5124
01527b31
CT		 5125 if (IS_VALLEYVIEW(dev)) {
5126 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5127 register_reboot_notifier(&intel_dp->edp_notifier);
5128 }
5129
4f9db5b5 5130 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5131 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 5132 intel_panel_setup_backlight(connector);
5133
5134 return true;
5135}
5136
16c25533 5137bool
f0fec3f2
PZ		 5138intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5139 struct intel_connector *intel_connector)
a4fc5ed6 5140{
f0fec3f2
PZ		 5141 struct drm_connector *connector = &intel_connector->base;
5142 struct intel_dp *intel_dp = &intel_dig_port->dp;
5143 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5144 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5145 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5146 enum port port = intel_dig_port->port;
0b99836f 5147 int type;
a4fc5ed6 5148
a4a5d2f8
VS		 5149 intel_dp->pps_pipe = INVALID_PIPE;
5150
ec5b01dd 5151 /* intel_dp vfuncs */
b6b5e383
DL		 5152 if (INTEL_INFO(dev)->gen >= 9)
5153 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5154 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5155 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5156 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5157 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5158 else if (HAS_PCH_SPLIT(dev))
5159 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5160 else
5161 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5162
b9ca5fad
DL		 5163 if (INTEL_INFO(dev)->gen >= 9)
5164 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5165 else
5166 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5167
0767935e
DV		 5168 /* Preserve the current hw state. */
5169 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5170 intel_dp->attached_connector = intel_connector;
3d3dc149 5171
3b32a35b 5172 if (intel_dp_is_edp(dev, port))
b329530c 5173 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5174 else
5175 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5176
f7d24902
ID		 5177 /*
5178 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5179 * for DP the encoder type can be set by the caller to
5180 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5181 */
5182 if (type == DRM_MODE_CONNECTOR_eDP)
5183 intel_encoder->type = INTEL_OUTPUT_EDP;
5184
c17ed5b5
VS		 5185 /* eDP only on port B and/or C on vlv/chv */
5186 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5187 port != PORT_B && port != PORT_C))
5188 return false;
5189
e7281eab
ID		 5190 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5191 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5192 port_name(port));
5193
b329530c 5194 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5195 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5196
a4fc5ed6
KP		 5197 connector->interlace_allowed = true;
5198 connector->doublescan_allowed = 0;
5199
f0fec3f2 5200 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5201 edp_panel_vdd_work);
a4fc5ed6 5202
df0e9248 5203 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5204 drm_connector_register(connector);
a4fc5ed6 5205
affa9354 5206 if (HAS_DDI(dev))
bcbc889b
PZ		 5207 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5208 else
5209 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5210 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5211
0b99836f 5212 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5213 switch (port) {
5214 case PORT_A:
1d843f9d 5215 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5216 break;
5217 case PORT_B:
1d843f9d 5218 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5219 break;
5220 case PORT_C:
1d843f9d 5221 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5222 break;
5223 case PORT_D:
1d843f9d 5224 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5225 break;
5226 default:
ad1c0b19 5227 BUG();
5eb08b69
ZW		 5228 }
5229
dada1a9f 5230 if (is_edp(intel_dp)) {
773538e8 5231 pps_lock(intel_dp);
a4a5d2f8
VS		 5232 if (IS_VALLEYVIEW(dev)) {
5233 vlv_initial_power_sequencer_setup(intel_dp);
5234 } else {
5235 intel_dp_init_panel_power_timestamps(intel_dp);
36b5f425 5236 intel_dp_init_panel_power_sequencer(dev, intel_dp);
a4a5d2f8 5237 }
773538e8 5238 pps_unlock(intel_dp);
dada1a9f 5239 }
0095e6dc 5240
9d1a1031 5241 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5242
0e32b39c
DA		 5243 /* init MST on ports that can support it */
5244 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5245 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5246 intel_dp_mst_encoder_init(intel_dig_port,
5247 intel_connector->base.base.id);
0e32b39c
DA		 5248 }
5249 }
5250
36b5f425 5251 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5252 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5253 if (is_edp(intel_dp)) {
5254 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5255 /*
5256 * vdd might still be enabled do to the delayed vdd off.
5257 * Make sure vdd is actually turned off here.
5258 */
773538e8 5259 pps_lock(intel_dp);
4be73780 5260 edp_panel_vdd_off_sync(intel_dp);
773538e8 5261 pps_unlock(intel_dp);
15b1d171 5262 }
34ea3d38 5263 drm_connector_unregister(connector);
b2f246a8 5264 drm_connector_cleanup(connector);
16c25533 5265 return false;
b2f246a8 5266 }
32f9d658 5267
f684960e
CW		 5268 intel_dp_add_properties(intel_dp, connector);
5269
a4fc5ed6
KP		 5270 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5271 * 0xd. Failure to do so will result in spurious interrupts being
5272 * generated on the port when a cable is not attached.
5273 */
5274 if (IS_G4X(dev) && !IS_GM45(dev)) {
5275 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5276 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5277 }
16c25533
PZ		 5278
5279 return true;
a4fc5ed6 5280}
f0fec3f2
PZ		 5281
5282void
5283intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5284{
13cf5504 5285 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5286 struct intel_digital_port *intel_dig_port;
5287 struct intel_encoder *intel_encoder;
5288 struct drm_encoder *encoder;
5289 struct intel_connector *intel_connector;
5290
b14c5679 5291 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5292 if (!intel_dig_port)
5293 return;
5294
b14c5679 5295 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5296 if (!intel_connector) {
5297 kfree(intel_dig_port);
5298 return;
5299 }
5300
5301 intel_encoder = &intel_dig_port->base;
5302 encoder = &intel_encoder->base;
5303
5304 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5305 DRM_MODE_ENCODER_TMDS);
5306
5bfe2ac0 5307 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5308 intel_encoder->disable = intel_disable_dp;
00c09d70 5309 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5310 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5311 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5312 if (IS_CHERRYVIEW(dev)) {
9197c88b 5313 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5314 intel_encoder->pre_enable = chv_pre_enable_dp;
5315 intel_encoder->enable = vlv_enable_dp;
580d3811 5316 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5317 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5318 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5319 intel_encoder->pre_enable = vlv_pre_enable_dp;
5320 intel_encoder->enable = vlv_enable_dp;
49277c31 5321 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5322 } else {
ecff4f3b
JN		 5323 intel_encoder->pre_enable = g4x_pre_enable_dp;
5324 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5325 if (INTEL_INFO(dev)->gen >= 5)
5326 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5327 }
f0fec3f2 5328
174edf1f 5329 intel_dig_port->port = port;
f0fec3f2
PZ		 5330 intel_dig_port->dp.output_reg = output_reg;
5331
00c09d70 5332 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5333 if (IS_CHERRYVIEW(dev)) {
5334 if (port == PORT_D)
5335 intel_encoder->crtc_mask = 1 << 2;
5336 else
5337 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5338 } else {
5339 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5340 }
bc079e8b 5341 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5342 intel_encoder->hot_plug = intel_dp_hot_plug;
5343
13cf5504
DA		 5344 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5345 dev_priv->hpd_irq_port[port] = intel_dig_port;
5346
15b1d171
PZ		 5347 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5348 drm_encoder_cleanup(encoder);
5349 kfree(intel_dig_port);
b2f246a8 5350 kfree(intel_connector);
15b1d171 5351 }
f0fec3f2 5352}
0e32b39c
DA		 5353
5354void intel_dp_mst_suspend(struct drm_device *dev)
5355{
5356 struct drm_i915_private *dev_priv = dev->dev_private;
5357 int i;
5358
5359 /* disable MST */
5360 for (i = 0; i < I915_MAX_PORTS; i++) {
5361 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5362 if (!intel_dig_port)
5363 continue;
5364
5365 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5366 if (!intel_dig_port->dp.can_mst)
5367 continue;
5368 if (intel_dig_port->dp.is_mst)
5369 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5370 }
5371 }
5372}
5373
5374void intel_dp_mst_resume(struct drm_device *dev)
5375{
5376 struct drm_i915_private *dev_priv = dev->dev_private;
5377 int i;
5378
5379 for (i = 0; i < I915_MAX_PORTS; i++) {
5380 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5381 if (!intel_dig_port)
5382 continue;
5383 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5384 int ret;
5385
5386 if (!intel_dig_port->dp.can_mst)
5387 continue;
5388
5389 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5390 if (ret != 0) {
5391 intel_dp_check_mst_status(&intel_dig_port->dp);
5392 }
5393 }
5394 }
5395}
Linux kernel - Deliverables
This page took 0.947028 seconds and 5 git commands to generate.