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drm/i915: De-magic the PSR AUX message
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
5ca476f8 228pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
773538e8
VS		 293static void pps_lock(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct intel_encoder *encoder = &intel_dig_port->base;
297 struct drm_device *dev = encoder->base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
299 enum intel_display_power_domain power_domain;
300
301 /*
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
304 */
305 power_domain = intel_display_port_power_domain(encoder);
306 intel_display_power_get(dev_priv, power_domain);
307
308 mutex_lock(&dev_priv->pps_mutex);
309}
310
311static void pps_unlock(struct intel_dp *intel_dp)
312{
313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
314 struct intel_encoder *encoder = &intel_dig_port->base;
315 struct drm_device *dev = encoder->base.dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 enum intel_display_power_domain power_domain;
318
319 mutex_unlock(&dev_priv->pps_mutex);
320
321 power_domain = intel_display_port_power_domain(encoder);
322 intel_display_power_put(dev_priv, power_domain);
323}
324
bf13e81b
JN		 325static enum pipe
326vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 331 struct intel_encoder *encoder;
332 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
333 struct edp_power_seq power_seq;
bf13e81b 334
e39b999a
VS		 335 lockdep_assert_held(&dev_priv->pps_mutex);
336
a4a5d2f8
VS		 337 if (intel_dp->pps_pipe != INVALID_PIPE)
338 return intel_dp->pps_pipe;
339
340 /*
341 * We don't have power sequencer currently.
342 * Pick one that's not used by other ports.
343 */
344 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
345 base.head) {
346 struct intel_dp *tmp;
347
348 if (encoder->type != INTEL_OUTPUT_EDP)
349 continue;
350
351 tmp = enc_to_intel_dp(&encoder->base);
352
353 if (tmp->pps_pipe != INVALID_PIPE)
354 pipes &= ~(1 << tmp->pps_pipe);
355 }
356
357 /*
358 * Didn't find one. This should not happen since there
359 * are two power sequencers and up to two eDP ports.
360 */
361 if (WARN_ON(pipes == 0))
362 return PIPE_A;
363
364 intel_dp->pps_pipe = ffs(pipes) - 1;
365
366 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
367 pipe_name(intel_dp->pps_pipe),
368 port_name(intel_dig_port->port));
369
370 /* init power sequencer on this pipe and port */
371 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
372 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
373 &power_seq);
374
375 return intel_dp->pps_pipe;
376}
377
6491ab27
VS		 378typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
379 enum pipe pipe);
380
381static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
382 enum pipe pipe)
383{
384 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
385}
386
387static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
388 enum pipe pipe)
389{
390 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
391}
392
393static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
394 enum pipe pipe)
395{
396 return true;
397}
bf13e81b 398
a4a5d2f8 399static enum pipe
6491ab27
VS		 400vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
401 enum port port,
402 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 403{
404 enum pipe pipe;
bf13e81b 405
bf13e81b
JN		 406 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
407 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
408 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 409
410 if (port_sel != PANEL_PORT_SELECT_VLV(port))
411 continue;
412
6491ab27
VS		 413 if (!pipe_check(dev_priv, pipe))
414 continue;
415
a4a5d2f8 416 return pipe;
bf13e81b
JN		 417 }
418
a4a5d2f8
VS		 419 return INVALID_PIPE;
420}
421
422static void
423vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
424{
425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
426 struct drm_device *dev = intel_dig_port->base.base.dev;
427 struct drm_i915_private *dev_priv = dev->dev_private;
428 struct edp_power_seq power_seq;
429 enum port port = intel_dig_port->port;
430
431 lockdep_assert_held(&dev_priv->pps_mutex);
432
433 /* try to find a pipe with this port selected */
6491ab27
VS		 434 /* first pick one where the panel is on */
435 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
436 vlv_pipe_has_pp_on);
437 /* didn't find one? pick one where vdd is on */
438 if (intel_dp->pps_pipe == INVALID_PIPE)
439 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
440 vlv_pipe_has_vdd_on);
441 /* didn't find one? pick one with just the correct port */
442 if (intel_dp->pps_pipe == INVALID_PIPE)
443 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
444 vlv_pipe_any);
a4a5d2f8
VS		 445
446 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
447 if (intel_dp->pps_pipe == INVALID_PIPE) {
448 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
449 port_name(port));
450 return;
bf13e81b
JN		 451 }
452
a4a5d2f8
VS		 453 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
454 port_name(port), pipe_name(intel_dp->pps_pipe));
455
456 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
457 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
458 &power_seq);
bf13e81b
JN		 459}
460
773538e8
VS		 461void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
462{
463 struct drm_device *dev = dev_priv->dev;
464 struct intel_encoder *encoder;
465
466 if (WARN_ON(!IS_VALLEYVIEW(dev)))
467 return;
468
469 /*
470 * We can't grab pps_mutex here due to deadlock with power_domain
471 * mutex when power_domain functions are called while holding pps_mutex.
472 * That also means that in order to use pps_pipe the code needs to
473 * hold both a power domain reference and pps_mutex, and the power domain
474 * reference get/put must be done while _not_ holding pps_mutex.
475 * pps_{lock,unlock}() do these steps in the correct order, so one
476 * should use them always.
477 */
478
479 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
480 struct intel_dp *intel_dp;
481
482 if (encoder->type != INTEL_OUTPUT_EDP)
483 continue;
484
485 intel_dp = enc_to_intel_dp(&encoder->base);
486 intel_dp->pps_pipe = INVALID_PIPE;
487 }
bf13e81b
JN		 488}
489
490static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
491{
492 struct drm_device *dev = intel_dp_to_dev(intel_dp);
493
494 if (HAS_PCH_SPLIT(dev))
495 return PCH_PP_CONTROL;
496 else
497 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
498}
499
500static u32 _pp_stat_reg(struct intel_dp *intel_dp)
501{
502 struct drm_device *dev = intel_dp_to_dev(intel_dp);
503
504 if (HAS_PCH_SPLIT(dev))
505 return PCH_PP_STATUS;
506 else
507 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
508}
509
01527b31
CT		 510/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
511 This function only applicable when panel PM state is not to be tracked */
512static int edp_notify_handler(struct notifier_block *this, unsigned long code,
513 void *unused)
514{
515 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
516 edp_notifier);
517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
518 struct drm_i915_private *dev_priv = dev->dev_private;
519 u32 pp_div;
520 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 521
522 if (!is_edp(intel_dp) || code != SYS_RESTART)
523 return 0;
524
773538e8 525 pps_lock(intel_dp);
e39b999a 526
01527b31 527 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 528 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
529
01527b31
CT		 530 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
531 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
532 pp_div = I915_READ(pp_div_reg);
533 pp_div &= PP_REFERENCE_DIVIDER_MASK;
534
535 /* 0x1F write to PP_DIV_REG sets max cycle delay */
536 I915_WRITE(pp_div_reg, pp_div | 0x1F);
537 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
538 msleep(intel_dp->panel_power_cycle_delay);
539 }
540
773538e8 541 pps_unlock(intel_dp);
e39b999a 542
01527b31
CT		 543 return 0;
544}
545
4be73780 546static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 547{
30add22d 548 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 549 struct drm_i915_private *dev_priv = dev->dev_private;
550
e39b999a
VS		 551 lockdep_assert_held(&dev_priv->pps_mutex);
552
bf13e81b 553 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 554}
555
4be73780 556static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 557{
30add22d 558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 559 struct drm_i915_private *dev_priv = dev->dev_private;
560
e39b999a
VS		 561 lockdep_assert_held(&dev_priv->pps_mutex);
562
773538e8 563 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 564}
565
9b984dae
KP		 566static void
567intel_dp_check_edp(struct intel_dp *intel_dp)
568{
30add22d 569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 570 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 571
9b984dae
KP		 572 if (!is_edp(intel_dp))
573 return;
453c5420 574
4be73780 575 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 576 WARN(1, "eDP powered off while attempting aux channel communication.\n");
577 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 578 I915_READ(_pp_stat_reg(intel_dp)),
579 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 580 }
581}
582
9ee32fea
DV		 583static uint32_t
584intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
585{
586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
587 struct drm_device *dev = intel_dig_port->base.base.dev;
588 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 589 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 590 uint32_t status;
591 bool done;
592
ef04f00d 593#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 594 if (has_aux_irq)
b18ac466 595 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 596 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 597 else
598 done = wait_for_atomic(C, 10) == 0;
599 if (!done)
600 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
601 has_aux_irq);
602#undef C
603
604 return status;
605}
606
ec5b01dd 607static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 608{
174edf1f
PZ		 609 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
610 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 611
ec5b01dd
DL		 612 /*
613 * The clock divider is based off the hrawclk, and would like to run at
614 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 615 */
ec5b01dd
DL		 616 return index ? 0 : intel_hrawclk(dev) / 2;
617}
618
619static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
620{
621 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
622 struct drm_device *dev = intel_dig_port->base.base.dev;
623
624 if (index)
625 return 0;
626
627 if (intel_dig_port->port == PORT_A) {
628 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 629 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 630 else
b84a1cf8 631 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 632 } else {
633 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
634 }
635}
636
637static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
638{
639 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
640 struct drm_device *dev = intel_dig_port->base.base.dev;
641 struct drm_i915_private *dev_priv = dev->dev_private;
642
643 if (intel_dig_port->port == PORT_A) {
644 if (index)
645 return 0;
646 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 647 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
648 /* Workaround for non-ULT HSW */
bc86625a
CW		 649 switch (index) {
650 case 0: return 63;
651 case 1: return 72;
652 default: return 0;
653 }
ec5b01dd 654 } else {
bc86625a 655 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 656 }
b84a1cf8
RV		 657}
658
ec5b01dd
DL		 659static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
660{
661 return index ? 0 : 100;
662}
663
b6b5e383
DL		 664static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
665{
666 /*
667 * SKL doesn't need us to program the AUX clock divider (Hardware will
668 * derive the clock from CDCLK automatically). We still implement the
669 * get_aux_clock_divider vfunc to plug-in into the existing code.
670 */
671 return index ? 0 : 1;
672}
673
5ed12a19
DL		 674static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
675 bool has_aux_irq,
676 int send_bytes,
677 uint32_t aux_clock_divider)
678{
679 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
680 struct drm_device *dev = intel_dig_port->base.base.dev;
681 uint32_t precharge, timeout;
682
683 if (IS_GEN6(dev))
684 precharge = 3;
685 else
686 precharge = 5;
687
688 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
689 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
690 else
691 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
692
693 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 694 DP_AUX_CH_CTL_DONE |
5ed12a19 695 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 696 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 697 timeout |
788d4433 698 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 699 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
700 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 701 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 702}
703
b9ca5fad
DL		 704static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
705 bool has_aux_irq,
706 int send_bytes,
707 uint32_t unused)
708{
709 return DP_AUX_CH_CTL_SEND_BUSY |
710 DP_AUX_CH_CTL_DONE |
711 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
712 DP_AUX_CH_CTL_TIME_OUT_ERROR |
713 DP_AUX_CH_CTL_TIME_OUT_1600us |
714 DP_AUX_CH_CTL_RECEIVE_ERROR |
715 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
716 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
717}
718
b84a1cf8
RV		 719static int
720intel_dp_aux_ch(struct intel_dp *intel_dp,
721 uint8_t *send, int send_bytes,
722 uint8_t *recv, int recv_size)
723{
724 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
725 struct drm_device *dev = intel_dig_port->base.base.dev;
726 struct drm_i915_private *dev_priv = dev->dev_private;
727 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
728 uint32_t ch_data = ch_ctl + 4;
bc86625a 729 uint32_t aux_clock_divider;
b84a1cf8
RV		 730 int i, ret, recv_bytes;
731 uint32_t status;
5ed12a19 732 int try, clock = 0;
4e6b788c 733 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 734 bool vdd;
735
773538e8 736 pps_lock(intel_dp);
e39b999a 737
72c3500a
VS		 738 /*
739 * We will be called with VDD already enabled for dpcd/edid/oui reads.
740 * In such cases we want to leave VDD enabled and it's up to upper layers
741 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
742 * ourselves.
743 */
1e0560e0 744 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 745
746 /* dp aux is extremely sensitive to irq latency, hence request the
747 * lowest possible wakeup latency and so prevent the cpu from going into
748 * deep sleep states.
749 */
750 pm_qos_update_request(&dev_priv->pm_qos, 0);
751
752 intel_dp_check_edp(intel_dp);
5eb08b69 753
c67a470b
PZ		 754 intel_aux_display_runtime_get(dev_priv);
755
11bee43e
JB		 756 /* Try to wait for any previous AUX channel activity */
757 for (try = 0; try < 3; try++) {
ef04f00d 758 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 759 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
760 break;
761 msleep(1);
762 }
763
764 if (try == 3) {
765 WARN(1, "dp_aux_ch not started status 0x%08x\n",
766 I915_READ(ch_ctl));
9ee32fea
DV		 767 ret = -EBUSY;
768 goto out;
4f7f7b7e
CW		 769 }
770
46a5ae9f
PZ		 771 /* Only 5 data registers! */
772 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
773 ret = -E2BIG;
774 goto out;
775 }
776
ec5b01dd 777 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 778 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
779 has_aux_irq,
780 send_bytes,
781 aux_clock_divider);
5ed12a19 782
bc86625a
CW		 783 /* Must try at least 3 times according to DP spec */
784 for (try = 0; try < 5; try++) {
785 /* Load the send data into the aux channel data registers */
786 for (i = 0; i < send_bytes; i += 4)
787 I915_WRITE(ch_data + i,
788 pack_aux(send + i, send_bytes - i));
789
790 /* Send the command and wait for it to complete */
5ed12a19 791 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 792
793 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
794
795 /* Clear done status and any errors */
796 I915_WRITE(ch_ctl,
797 status |
798 DP_AUX_CH_CTL_DONE |
799 DP_AUX_CH_CTL_TIME_OUT_ERROR |
800 DP_AUX_CH_CTL_RECEIVE_ERROR);
801
802 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
803 DP_AUX_CH_CTL_RECEIVE_ERROR))
804 continue;
805 if (status & DP_AUX_CH_CTL_DONE)
806 break;
807 }
4f7f7b7e 808 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 809 break;
810 }
811
a4fc5ed6 812 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 813 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 814 ret = -EBUSY;
815 goto out;
a4fc5ed6
KP		 816 }
817
818 /* Check for timeout or receive error.
819 * Timeouts occur when the sink is not connected
820 */
a5b3da54 821 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 822 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 823 ret = -EIO;
824 goto out;
a5b3da54 825 }
1ae8c0a5
KP		 826
827 /* Timeouts occur when the device isn't connected, so they're
828 * "normal" -- don't fill the kernel log with these */
a5b3da54 829 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 830 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 831 ret = -ETIMEDOUT;
832 goto out;
a4fc5ed6
KP		 833 }
834
835 /* Unload any bytes sent back from the other side */
836 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
837 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 838 if (recv_bytes > recv_size)
839 recv_bytes = recv_size;
0206e353 840
4f7f7b7e
CW		 841 for (i = 0; i < recv_bytes; i += 4)
842 unpack_aux(I915_READ(ch_data + i),
843 recv + i, recv_bytes - i);
a4fc5ed6 844
9ee32fea
DV		 845 ret = recv_bytes;
846out:
847 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 848 intel_aux_display_runtime_put(dev_priv);
9ee32fea 849
884f19e9
JN		 850 if (vdd)
851 edp_panel_vdd_off(intel_dp, false);
852
773538e8 853 pps_unlock(intel_dp);
e39b999a 854
9ee32fea 855 return ret;
a4fc5ed6
KP		 856}
857
a6c8aff0
JN		 858#define BARE_ADDRESS_SIZE 3
859#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 860static ssize_t
861intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 862{
9d1a1031
JN		 863 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
864 uint8_t txbuf[20], rxbuf[20];
865 size_t txsize, rxsize;
a4fc5ed6 866 int ret;
a4fc5ed6 867
9d1a1031
JN		 868 txbuf[0] = msg->request << 4;
869 txbuf[1] = msg->address >> 8;
870 txbuf[2] = msg->address & 0xff;
871 txbuf[3] = msg->size - 1;
46a5ae9f 872
9d1a1031
JN		 873 switch (msg->request & ~DP_AUX_I2C_MOT) {
874 case DP_AUX_NATIVE_WRITE:
875 case DP_AUX_I2C_WRITE:
a6c8aff0 876 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 877 rxsize = 1;
f51a44b9 878
9d1a1031
JN		 879 if (WARN_ON(txsize > 20))
880 return -E2BIG;
a4fc5ed6 881
9d1a1031 882 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 883
9d1a1031
JN		 884 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
885 if (ret > 0) {
886 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 887
9d1a1031
JN		 888 /* Return payload size. */
889 ret = msg->size;
890 }
891 break;
46a5ae9f 892
9d1a1031
JN		 893 case DP_AUX_NATIVE_READ:
894 case DP_AUX_I2C_READ:
a6c8aff0 895 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 896 rxsize = msg->size + 1;
a4fc5ed6 897
9d1a1031
JN		 898 if (WARN_ON(rxsize > 20))
899 return -E2BIG;
a4fc5ed6 900
9d1a1031
JN		 901 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
902 if (ret > 0) {
903 msg->reply = rxbuf[0] >> 4;
904 /*
905 * Assume happy day, and copy the data. The caller is
906 * expected to check msg->reply before touching it.
907 *
908 * Return payload size.
909 */
910 ret--;
911 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 912 }
9d1a1031
JN		 913 break;
914
915 default:
916 ret = -EINVAL;
917 break;
a4fc5ed6 918 }
f51a44b9 919
9d1a1031 920 return ret;
a4fc5ed6
KP		 921}
922
9d1a1031
JN		 923static void
924intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
925{
926 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 927 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
928 enum port port = intel_dig_port->port;
0b99836f 929 const char *name = NULL;
ab2c0672
DA		 930 int ret;
931
33ad6626
JN		 932 switch (port) {
933 case PORT_A:
934 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 935 name = "DPDDC-A";
ab2c0672 936 break;
33ad6626
JN		 937 case PORT_B:
938 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 939 name = "DPDDC-B";
ab2c0672 940 break;
33ad6626
JN		 941 case PORT_C:
942 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 943 name = "DPDDC-C";
ab2c0672 944 break;
33ad6626
JN		 945 case PORT_D:
946 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 947 name = "DPDDC-D";
33ad6626
JN		 948 break;
949 default:
950 BUG();
ab2c0672
DA		 951 }
952
1b1aad75
DL		 953 /*
954 * The AUX_CTL register is usually DP_CTL + 0x10.
955 *
956 * On Haswell and Broadwell though:
957 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
958 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
959 *
960 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
961 */
962 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 963 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 964
0b99836f 965 intel_dp->aux.name = name;
9d1a1031
JN		 966 intel_dp->aux.dev = dev->dev;
967 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 968
0b99836f
JN		 969 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
970 connector->base.kdev->kobj.name);
8316f337 971
4f71d0cb 972 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 973 if (ret < 0) {
4f71d0cb 974 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 975 name, ret);
976 return;
ab2c0672 977 }
8a5e6aeb 978
0b99836f
JN		 979 ret = sysfs_create_link(&connector->base.kdev->kobj,
980 &intel_dp->aux.ddc.dev.kobj,
981 intel_dp->aux.ddc.dev.kobj.name);
982 if (ret < 0) {
983 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 984 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 985 }
a4fc5ed6
KP		 986}
987
80f65de3
ID		 988static void
989intel_dp_connector_unregister(struct intel_connector *intel_connector)
990{
991 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
992
0e32b39c
DA		 993 if (!intel_connector->mst_port)
994 sysfs_remove_link(&intel_connector->base.kdev->kobj,
995 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 996 intel_connector_unregister(intel_connector);
997}
998
0e50338c
DV		 999static void
1000hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
1001{
1002 switch (link_bw) {
1003 case DP_LINK_BW_1_62:
1004 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1005 break;
1006 case DP_LINK_BW_2_7:
1007 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1008 break;
1009 case DP_LINK_BW_5_4:
1010 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1011 break;
1012 }
1013}
1014
c6bb3538
DV		 1015static void
1016intel_dp_set_clock(struct intel_encoder *encoder,
1017 struct intel_crtc_config *pipe_config, int link_bw)
1018{
1019 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1020 const struct dp_link_dpll *divisor = NULL;
1021 int i, count = 0;
c6bb3538
DV		 1022
1023 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1024 divisor = gen4_dpll;
1025 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1026 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1027 divisor = pch_dpll;
1028 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1029 } else if (IS_CHERRYVIEW(dev)) {
1030 divisor = chv_dpll;
1031 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1032 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1033 divisor = vlv_dpll;
1034 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1035 }
9dd4ffdf
CML		 1036
1037 if (divisor && count) {
1038 for (i = 0; i < count; i++) {
1039 if (link_bw == divisor[i].link_bw) {
1040 pipe_config->dpll = divisor[i].dpll;
1041 pipe_config->clock_set = true;
1042 break;
1043 }
1044 }
c6bb3538
DV		 1045 }
1046}
1047
00c09d70 1048bool
5bfe2ac0
DV		 1049intel_dp_compute_config(struct intel_encoder *encoder,
1050 struct intel_crtc_config *pipe_config)
a4fc5ed6 1051{
5bfe2ac0 1052 struct drm_device *dev = encoder->base.dev;
36008365 1053 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1054 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1055 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1056 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1057 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1058 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1059 int lane_count, clock;
56071a20 1060 int min_lane_count = 1;
eeb6324d 1061 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1062 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1063 int min_clock = 0;
06ea66b6 1064 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1065 int bpp, mode_rate;
06ea66b6 1066 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1067 int link_avail, link_clock;
a4fc5ed6 1068
bc7d38a4 1069 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1070 pipe_config->has_pch_encoder = true;
1071
03afc4a2 1072 pipe_config->has_dp_encoder = true;
f769cd24 1073 pipe_config->has_drrs = false;
9ed109a7 1074 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1075
dd06f90e
JN		 1076 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1077 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1078 adjusted_mode);
2dd24552
JB		 1079 if (!HAS_PCH_SPLIT(dev))
1080 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1081 intel_connector->panel.fitting_mode);
1082 else
b074cec8
JB		 1083 intel_pch_panel_fitting(intel_crtc, pipe_config,
1084 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1085 }
1086
cb1793ce 1087 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1088 return false;
1089
083f9560
DV		 1090 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1091 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1092 max_lane_count, bws[max_clock],
1093 adjusted_mode->crtc_clock);
083f9560 1094
36008365
DV		 1095 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1096 * bpc in between. */
3e7ca985 1097 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1098 if (is_edp(intel_dp)) {
1099 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1100 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1101 dev_priv->vbt.edp_bpp);
1102 bpp = dev_priv->vbt.edp_bpp;
1103 }
1104
344c5bbc
JN		 1105 /*
1106 * Use the maximum clock and number of lanes the eDP panel
1107 * advertizes being capable of. The panels are generally
1108 * designed to support only a single clock and lane
1109 * configuration, and typically these values correspond to the
1110 * native resolution of the panel.
1111 */
1112 min_lane_count = max_lane_count;
1113 min_clock = max_clock;
7984211e 1114 }
657445fe 1115
36008365 1116 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1117 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1118 bpp);
36008365 1119
c6930992
DA		 1120 for (clock = min_clock; clock <= max_clock; clock++) {
1121 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1122 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1123 link_avail = intel_dp_max_data_rate(link_clock,
1124 lane_count);
1125
1126 if (mode_rate <= link_avail) {
1127 goto found;
1128 }
1129 }
1130 }
1131 }
c4867936 1132
36008365 1133 return false;
3685a8f3 1134
36008365 1135found:
55bc60db
VS		 1136 if (intel_dp->color_range_auto) {
1137 /*
1138 * See:
1139 * CEA-861-E - 5.1 Default Encoding Parameters
1140 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1141 */
18316c8c 1142 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1143 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1144 else
1145 intel_dp->color_range = 0;
1146 }
1147
3685a8f3 1148 if (intel_dp->color_range)
50f3b016 1149 pipe_config->limited_color_range = true;
a4fc5ed6 1150
36008365
DV		 1151 intel_dp->link_bw = bws[clock];
1152 intel_dp->lane_count = lane_count;
657445fe 1153 pipe_config->pipe_bpp = bpp;
ff9a6750 1154 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1155
36008365
DV		 1156 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1157 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1158 pipe_config->port_clock, bpp);
36008365
DV		 1159 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1160 mode_rate, link_avail);
a4fc5ed6 1161
03afc4a2 1162 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1163 adjusted_mode->crtc_clock,
1164 pipe_config->port_clock,
03afc4a2 1165 &pipe_config->dp_m_n);
9d1a455b 1166
439d7ac0
PB		 1167 if (intel_connector->panel.downclock_mode != NULL &&
1168 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1169 pipe_config->has_drrs = true;
439d7ac0
PB		 1170 intel_link_compute_m_n(bpp, lane_count,
1171 intel_connector->panel.downclock_mode->clock,
1172 pipe_config->port_clock,
1173 &pipe_config->dp_m2_n2);
1174 }
1175
ea155f32 1176 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1177 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1178 else
1179 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1180
03afc4a2 1181 return true;
a4fc5ed6
KP		 1182}
1183
7c62a164 1184static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1185{
7c62a164
DV		 1186 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1187 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1188 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1189 struct drm_i915_private *dev_priv = dev->dev_private;
1190 u32 dpa_ctl;
1191
ff9a6750 1192 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1193 dpa_ctl = I915_READ(DP_A);
1194 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1195
ff9a6750 1196 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1197 /* For a long time we've carried around a ILK-DevA w/a for the
1198 * 160MHz clock. If we're really unlucky, it's still required.
1199 */
1200 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1201 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1202 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1203 } else {
1204 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1205 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1206 }
1ce17038 1207
ea9b6006
DV		 1208 I915_WRITE(DP_A, dpa_ctl);
1209
1210 POSTING_READ(DP_A);
1211 udelay(500);
1212}
1213
8ac33ed3 1214static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1215{
b934223d 1216 struct drm_device *dev = encoder->base.dev;
417e822d 1217 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1218 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1219 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1220 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1221 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1222
417e822d 1223 /*
1a2eb460 1224 * There are four kinds of DP registers:
417e822d
KP		 1225 *
1226 * IBX PCH
1a2eb460
KP		 1227 * SNB CPU
1228 * IVB CPU
417e822d
KP		 1229 * CPT PCH
1230 *
1231 * IBX PCH and CPU are the same for almost everything,
1232 * except that the CPU DP PLL is configured in this
1233 * register
1234 *
1235 * CPT PCH is quite different, having many bits moved
1236 * to the TRANS_DP_CTL register instead. That
1237 * configuration happens (oddly) in ironlake_pch_enable
1238 */
9c9e7927 1239
417e822d
KP		 1240 /* Preserve the BIOS-computed detected bit. This is
1241 * supposed to be read-only.
1242 */
1243 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1244
417e822d 1245 /* Handle DP bits in common between all three register formats */
417e822d 1246 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1247 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1248
9ed109a7 1249 if (crtc->config.has_audio) {
e0dac65e 1250 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1251 pipe_name(crtc->pipe));
ea5b213a 1252 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1253 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1254 }
247d89f6 1255
417e822d 1256 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1257
bc7d38a4 1258 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1259 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1260 intel_dp->DP |= DP_SYNC_HS_HIGH;
1261 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1262 intel_dp->DP |= DP_SYNC_VS_HIGH;
1263 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1264
6aba5b6c 1265 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1266 intel_dp->DP |= DP_ENHANCED_FRAMING;
1267
7c62a164 1268 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1269 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1270 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1271 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1272
1273 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1274 intel_dp->DP |= DP_SYNC_HS_HIGH;
1275 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1276 intel_dp->DP |= DP_SYNC_VS_HIGH;
1277 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1278
6aba5b6c 1279 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1280 intel_dp->DP |= DP_ENHANCED_FRAMING;
1281
44f37d1f
CML		 1282 if (!IS_CHERRYVIEW(dev)) {
1283 if (crtc->pipe == 1)
1284 intel_dp->DP |= DP_PIPEB_SELECT;
1285 } else {
1286 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1287 }
417e822d
KP		 1288 } else {
1289 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1290 }
a4fc5ed6
KP		 1291}
1292
ffd6749d
PZ		 1293#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1294#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1295
1a5ef5b7
PZ		 1296#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1297#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1298
ffd6749d
PZ		 1299#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1300#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1301
4be73780 1302static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1303 u32 mask,
1304 u32 value)
bd943159 1305{
30add22d 1306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1307 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1308 u32 pp_stat_reg, pp_ctrl_reg;
1309
e39b999a
VS		 1310 lockdep_assert_held(&dev_priv->pps_mutex);
1311
bf13e81b
JN		 1312 pp_stat_reg = _pp_stat_reg(intel_dp);
1313 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1314
99ea7127 1315 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1316 mask, value,
1317 I915_READ(pp_stat_reg),
1318 I915_READ(pp_ctrl_reg));
32ce697c 1319
453c5420 1320 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1321 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1322 I915_READ(pp_stat_reg),
1323 I915_READ(pp_ctrl_reg));
32ce697c 1324 }
54c136d4
CW		 1325
1326 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1327}
32ce697c 1328
4be73780 1329static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1330{
1331 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1332 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1333}
1334
4be73780 1335static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1336{
1337 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1338 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1339}
1340
4be73780 1341static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1342{
1343 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1344
1345 /* When we disable the VDD override bit last we have to do the manual
1346 * wait. */
1347 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1348 intel_dp->panel_power_cycle_delay);
1349
4be73780 1350 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1351}
1352
4be73780 1353static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1354{
1355 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1356 intel_dp->backlight_on_delay);
1357}
1358
4be73780 1359static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1360{
1361 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1362 intel_dp->backlight_off_delay);
1363}
99ea7127 1364
832dd3c1
KP		 1365/* Read the current pp_control value, unlocking the register if it
1366 * is locked
1367 */
1368
453c5420 1369static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1370{
453c5420
JB		 1371 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1372 struct drm_i915_private *dev_priv = dev->dev_private;
1373 u32 control;
832dd3c1 1374
e39b999a
VS		 1375 lockdep_assert_held(&dev_priv->pps_mutex);
1376
bf13e81b 1377 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1378 control &= ~PANEL_UNLOCK_MASK;
1379 control |= PANEL_UNLOCK_REGS;
1380 return control;
bd943159
KP		 1381}
1382
951468f3
VS		 1383/*
1384 * Must be paired with edp_panel_vdd_off().
1385 * Must hold pps_mutex around the whole on/off sequence.
1386 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1387 */
1e0560e0 1388static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1389{
30add22d 1390 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1391 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1392 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1393 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1394 enum intel_display_power_domain power_domain;
5d613501 1395 u32 pp;
453c5420 1396 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1397 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1398
e39b999a
VS		 1399 lockdep_assert_held(&dev_priv->pps_mutex);
1400
97af61f5 1401 if (!is_edp(intel_dp))
adddaaf4 1402 return false;
bd943159
KP		 1403
1404 intel_dp->want_panel_vdd = true;
99ea7127 1405
4be73780 1406 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1407 return need_to_disable;
b0665d57 1408
4e6e1a54
ID		 1409 power_domain = intel_display_port_power_domain(intel_encoder);
1410 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1411
b0665d57 1412 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1413
4be73780
DV		 1414 if (!edp_have_panel_power(intel_dp))
1415 wait_panel_power_cycle(intel_dp);
99ea7127 1416
453c5420 1417 pp = ironlake_get_pp_control(intel_dp);
5d613501 1418 pp |= EDP_FORCE_VDD;
ebf33b18 1419
bf13e81b
JN		 1420 pp_stat_reg = _pp_stat_reg(intel_dp);
1421 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1422
1423 I915_WRITE(pp_ctrl_reg, pp);
1424 POSTING_READ(pp_ctrl_reg);
1425 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1426 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1427 /*
1428 * If the panel wasn't on, delay before accessing aux channel
1429 */
4be73780 1430 if (!edp_have_panel_power(intel_dp)) {
bd943159 1431 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1432 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1433 }
adddaaf4
JN		 1434
1435 return need_to_disable;
1436}
1437
951468f3
VS		 1438/*
1439 * Must be paired with intel_edp_panel_vdd_off() or
1440 * intel_edp_panel_off().
1441 * Nested calls to these functions are not allowed since
1442 * we drop the lock. Caller must use some higher level
1443 * locking to prevent nested calls from other threads.
1444 */
b80d6c78 1445void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1446{
c695b6b6 1447 bool vdd;
adddaaf4 1448
c695b6b6
VS		 1449 if (!is_edp(intel_dp))
1450 return;
1451
773538e8 1452 pps_lock(intel_dp);
c695b6b6 1453 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1454 pps_unlock(intel_dp);
c695b6b6
VS		 1455
1456 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1457}
1458
4be73780 1459static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1460{
30add22d 1461 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1462 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1463 struct intel_digital_port *intel_dig_port =
1464 dp_to_dig_port(intel_dp);
1465 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1466 enum intel_display_power_domain power_domain;
5d613501 1467 u32 pp;
453c5420 1468 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1469
e39b999a 1470 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1471
15e899a0 1472 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1473
15e899a0 1474 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1475 return;
b0665d57 1476
be2c9196 1477 DRM_DEBUG_KMS("Turning eDP VDD off\n");
bd943159 1478
be2c9196
VS		 1479 pp = ironlake_get_pp_control(intel_dp);
1480 pp &= ~EDP_FORCE_VDD;
453c5420 1481
be2c9196
VS		 1482 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1483 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420 1484
be2c9196
VS		 1485 I915_WRITE(pp_ctrl_reg, pp);
1486 POSTING_READ(pp_ctrl_reg);
99ea7127 1487
be2c9196
VS		 1488 /* Make sure sequencer is idle before allowing subsequent activity */
1489 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1490 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c 1491
be2c9196
VS		 1492 if ((pp & POWER_TARGET_ON) == 0)
1493 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1494
be2c9196
VS		 1495 power_domain = intel_display_port_power_domain(intel_encoder);
1496 intel_display_power_put(dev_priv, power_domain);
bd943159 1497}
5d613501 1498
4be73780 1499static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1500{
1501 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1502 struct intel_dp, panel_vdd_work);
bd943159 1503
773538e8 1504 pps_lock(intel_dp);
15e899a0
VS		 1505 if (!intel_dp->want_panel_vdd)
1506 edp_panel_vdd_off_sync(intel_dp);
773538e8 1507 pps_unlock(intel_dp);
bd943159
KP		 1508}
1509
aba86890
ID		 1510static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1511{
1512 unsigned long delay;
1513
1514 /*
1515 * Queue the timer to fire a long time from now (relative to the power
1516 * down delay) to keep the panel power up across a sequence of
1517 * operations.
1518 */
1519 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1520 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1521}
1522
951468f3
VS		 1523/*
1524 * Must be paired with edp_panel_vdd_on().
1525 * Must hold pps_mutex around the whole on/off sequence.
1526 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1527 */
4be73780 1528static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1529{
e39b999a
VS		 1530 struct drm_i915_private *dev_priv =
1531 intel_dp_to_dev(intel_dp)->dev_private;
1532
1533 lockdep_assert_held(&dev_priv->pps_mutex);
1534
97af61f5
KP		 1535 if (!is_edp(intel_dp))
1536 return;
5d613501 1537
bd943159 1538 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1539
bd943159
KP		 1540 intel_dp->want_panel_vdd = false;
1541
aba86890 1542 if (sync)
4be73780 1543 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1544 else
1545 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1546}
1547
951468f3
VS		 1548/*
1549 * Must be paired with intel_edp_panel_vdd_on().
1550 * Nested calls to these functions are not allowed since
1551 * we drop the lock. Caller must use some higher level
1552 * locking to prevent nested calls from other threads.
1553 */
1e0560e0
VS		 1554static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1555{
e39b999a
VS		 1556 if (!is_edp(intel_dp))
1557 return;
1558
773538e8 1559 pps_lock(intel_dp);
1e0560e0 1560 edp_panel_vdd_off(intel_dp, sync);
773538e8 1561 pps_unlock(intel_dp);
1e0560e0
VS		 1562}
1563
4be73780 1564void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1565{
30add22d 1566 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1567 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1568 u32 pp;
453c5420 1569 u32 pp_ctrl_reg;
9934c132 1570
97af61f5 1571 if (!is_edp(intel_dp))
bd943159 1572 return;
99ea7127
KP		 1573
1574 DRM_DEBUG_KMS("Turn eDP power on\n");
1575
773538e8 1576 pps_lock(intel_dp);
e39b999a 1577
4be73780 1578 if (edp_have_panel_power(intel_dp)) {
99ea7127 1579 DRM_DEBUG_KMS("eDP power already on\n");
e39b999a 1580 goto out;
99ea7127 1581 }
9934c132 1582
4be73780 1583 wait_panel_power_cycle(intel_dp);
37c6c9b0 1584
bf13e81b 1585 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1586 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1587 if (IS_GEN5(dev)) {
1588 /* ILK workaround: disable reset around power sequence */
1589 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1590 I915_WRITE(pp_ctrl_reg, pp);
1591 POSTING_READ(pp_ctrl_reg);
05ce1a49 1592 }
37c6c9b0 1593
1c0ae80a 1594 pp |= POWER_TARGET_ON;
99ea7127
KP		 1595 if (!IS_GEN5(dev))
1596 pp |= PANEL_POWER_RESET;
1597
453c5420
JB		 1598 I915_WRITE(pp_ctrl_reg, pp);
1599 POSTING_READ(pp_ctrl_reg);
9934c132 1600
4be73780 1601 wait_panel_on(intel_dp);
dce56b3c 1602 intel_dp->last_power_on = jiffies;
9934c132 1603
05ce1a49
KP		 1604 if (IS_GEN5(dev)) {
1605 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1606 I915_WRITE(pp_ctrl_reg, pp);
1607 POSTING_READ(pp_ctrl_reg);
05ce1a49 1608 }
e39b999a
VS		 1609
1610 out:
773538e8 1611 pps_unlock(intel_dp);
9934c132
JB		 1612}
1613
4be73780 1614void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1615{
4e6e1a54
ID		 1616 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1617 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1618 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1619 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1620 enum intel_display_power_domain power_domain;
99ea7127 1621 u32 pp;
453c5420 1622 u32 pp_ctrl_reg;
9934c132 1623
97af61f5
KP		 1624 if (!is_edp(intel_dp))
1625 return;
37c6c9b0 1626
99ea7127 1627 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1628
773538e8 1629 pps_lock(intel_dp);
e39b999a 1630
24f3e092
JN		 1631 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1632
453c5420 1633 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1634 /* We need to switch off panel power _and_ force vdd, for otherwise some
1635 * panels get very unhappy and cease to work. */
b3064154
PJ		 1636 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1637 EDP_BLC_ENABLE);
453c5420 1638
bf13e81b 1639 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1640
849e39f5
PZ		 1641 intel_dp->want_panel_vdd = false;
1642
453c5420
JB		 1643 I915_WRITE(pp_ctrl_reg, pp);
1644 POSTING_READ(pp_ctrl_reg);
9934c132 1645
dce56b3c 1646 intel_dp->last_power_cycle = jiffies;
4be73780 1647 wait_panel_off(intel_dp);
849e39f5
PZ		 1648
1649 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1650 power_domain = intel_display_port_power_domain(intel_encoder);
1651 intel_display_power_put(dev_priv, power_domain);
e39b999a 1652
773538e8 1653 pps_unlock(intel_dp);
9934c132
JB		 1654}
1655
1250d107
JN		 1656/* Enable backlight in the panel power control. */
1657static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1658{
da63a9f2
PZ		 1659 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1660 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1661 struct drm_i915_private *dev_priv = dev->dev_private;
1662 u32 pp;
453c5420 1663 u32 pp_ctrl_reg;
32f9d658 1664
01cb9ea6
JB		 1665 /*
1666 * If we enable the backlight right away following a panel power
1667 * on, we may see slight flicker as the panel syncs with the eDP
1668 * link. So delay a bit to make sure the image is solid before
1669 * allowing it to appear.
1670 */
4be73780 1671 wait_backlight_on(intel_dp);
e39b999a 1672
773538e8 1673 pps_lock(intel_dp);
e39b999a 1674
453c5420 1675 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1676 pp |= EDP_BLC_ENABLE;
453c5420 1677
bf13e81b 1678 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1679
1680 I915_WRITE(pp_ctrl_reg, pp);
1681 POSTING_READ(pp_ctrl_reg);
e39b999a 1682
773538e8 1683 pps_unlock(intel_dp);
32f9d658
ZW		 1684}
1685
1250d107
JN		 1686/* Enable backlight PWM and backlight PP control. */
1687void intel_edp_backlight_on(struct intel_dp *intel_dp)
1688{
1689 if (!is_edp(intel_dp))
1690 return;
1691
1692 DRM_DEBUG_KMS("\n");
1693
1694 intel_panel_enable_backlight(intel_dp->attached_connector);
1695 _intel_edp_backlight_on(intel_dp);
1696}
1697
1698/* Disable backlight in the panel power control. */
1699static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1700{
30add22d 1701 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1702 struct drm_i915_private *dev_priv = dev->dev_private;
1703 u32 pp;
453c5420 1704 u32 pp_ctrl_reg;
32f9d658 1705
f01eca2e
KP		 1706 if (!is_edp(intel_dp))
1707 return;
1708
773538e8 1709 pps_lock(intel_dp);
e39b999a 1710
453c5420 1711 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1712 pp &= ~EDP_BLC_ENABLE;
453c5420 1713
bf13e81b 1714 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1715
1716 I915_WRITE(pp_ctrl_reg, pp);
1717 POSTING_READ(pp_ctrl_reg);
f7d2323c 1718
773538e8 1719 pps_unlock(intel_dp);
e39b999a
VS		 1720
1721 intel_dp->last_backlight_off = jiffies;
f7d2323c 1722 edp_wait_backlight_off(intel_dp);
1250d107 1723}
f7d2323c 1724
1250d107
JN		 1725/* Disable backlight PP control and backlight PWM. */
1726void intel_edp_backlight_off(struct intel_dp *intel_dp)
1727{
1728 if (!is_edp(intel_dp))
1729 return;
1730
1731 DRM_DEBUG_KMS("\n");
f7d2323c 1732
1250d107 1733 _intel_edp_backlight_off(intel_dp);
f7d2323c 1734 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1735}
a4fc5ed6 1736
73580fb7
JN		 1737/*
1738 * Hook for controlling the panel power control backlight through the bl_power
1739 * sysfs attribute. Take care to handle multiple calls.
1740 */
1741static void intel_edp_backlight_power(struct intel_connector *connector,
1742 bool enable)
1743{
1744 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1745 bool is_enabled;
1746
773538e8 1747 pps_lock(intel_dp);
e39b999a 1748 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1749 pps_unlock(intel_dp);
73580fb7
JN		 1750
1751 if (is_enabled == enable)
1752 return;
1753
23ba9373
JN		 1754 DRM_DEBUG_KMS("panel power control backlight %s\n",
1755 enable ? "enable" : "disable");
73580fb7
JN		 1756
1757 if (enable)
1758 _intel_edp_backlight_on(intel_dp);
1759 else
1760 _intel_edp_backlight_off(intel_dp);
1761}
1762
2bd2ad64 1763static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1764{
da63a9f2
PZ		 1765 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1766 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1767 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1768 struct drm_i915_private *dev_priv = dev->dev_private;
1769 u32 dpa_ctl;
1770
2bd2ad64
DV		 1771 assert_pipe_disabled(dev_priv,
1772 to_intel_crtc(crtc)->pipe);
1773
d240f20f
JB		 1774 DRM_DEBUG_KMS("\n");
1775 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1776 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1777 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1778
1779 /* We don't adjust intel_dp->DP while tearing down the link, to
1780 * facilitate link retraining (e.g. after hotplug). Hence clear all
1781 * enable bits here to ensure that we don't enable too much. */
1782 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1783 intel_dp->DP |= DP_PLL_ENABLE;
1784 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1785 POSTING_READ(DP_A);
1786 udelay(200);
d240f20f
JB		 1787}
1788
2bd2ad64 1789static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1790{
da63a9f2
PZ		 1791 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1792 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1793 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1794 struct drm_i915_private *dev_priv = dev->dev_private;
1795 u32 dpa_ctl;
1796
2bd2ad64
DV		 1797 assert_pipe_disabled(dev_priv,
1798 to_intel_crtc(crtc)->pipe);
1799
d240f20f 1800 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1801 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1802 "dp pll off, should be on\n");
1803 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1804
1805 /* We can't rely on the value tracked for the DP register in
1806 * intel_dp->DP because link_down must not change that (otherwise link
1807 * re-training will fail. */
298b0b39 1808 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1809 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1810 POSTING_READ(DP_A);
d240f20f
JB		 1811 udelay(200);
1812}
1813
c7ad3810 1814/* If the sink supports it, try to set the power state appropriately */
c19b0669 1815void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1816{
1817 int ret, i;
1818
1819 /* Should have a valid DPCD by this point */
1820 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1821 return;
1822
1823 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1824 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1825 DP_SET_POWER_D3);
c7ad3810
JB		 1826 } else {
1827 /*
1828 * When turning on, we need to retry for 1ms to give the sink
1829 * time to wake up.
1830 */
1831 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1832 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1833 DP_SET_POWER_D0);
c7ad3810
JB		 1834 if (ret == 1)
1835 break;
1836 msleep(1);
1837 }
1838 }
f9cac721
JN		 1839
1840 if (ret != 1)
1841 DRM_DEBUG_KMS("failed to %s sink power state\n",
1842 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1843}
1844
19d8fe15
DV		 1845static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1846 enum pipe *pipe)
d240f20f 1847{
19d8fe15 1848 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1849 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1850 struct drm_device *dev = encoder->base.dev;
1851 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1852 enum intel_display_power_domain power_domain;
1853 u32 tmp;
1854
1855 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1856 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1857 return false;
1858
1859 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1860
1861 if (!(tmp & DP_PORT_EN))
1862 return false;
1863
bc7d38a4 1864 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1865 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1866 } else if (IS_CHERRYVIEW(dev)) {
1867 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1868 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1869 *pipe = PORT_TO_PIPE(tmp);
1870 } else {
1871 u32 trans_sel;
1872 u32 trans_dp;
1873 int i;
1874
1875 switch (intel_dp->output_reg) {
1876 case PCH_DP_B:
1877 trans_sel = TRANS_DP_PORT_SEL_B;
1878 break;
1879 case PCH_DP_C:
1880 trans_sel = TRANS_DP_PORT_SEL_C;
1881 break;
1882 case PCH_DP_D:
1883 trans_sel = TRANS_DP_PORT_SEL_D;
1884 break;
1885 default:
1886 return true;
1887 }
1888
055e393f 1889 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1890 trans_dp = I915_READ(TRANS_DP_CTL(i));
1891 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1892 *pipe = i;
1893 return true;
1894 }
1895 }
19d8fe15 1896
4a0833ec
DV		 1897 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1898 intel_dp->output_reg);
1899 }
d240f20f 1900
19d8fe15
DV		 1901 return true;
1902}
d240f20f 1903
045ac3b5
JB		 1904static void intel_dp_get_config(struct intel_encoder *encoder,
1905 struct intel_crtc_config *pipe_config)
1906{
1907 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1908 u32 tmp, flags = 0;
63000ef6
XZ		 1909 struct drm_device *dev = encoder->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
1911 enum port port = dp_to_dig_port(intel_dp)->port;
1912 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1913 int dotclock;
045ac3b5 1914
9ed109a7
DV		 1915 tmp = I915_READ(intel_dp->output_reg);
1916 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1917 pipe_config->has_audio = true;
1918
63000ef6 1919 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1920 if (tmp & DP_SYNC_HS_HIGH)
1921 flags |= DRM_MODE_FLAG_PHSYNC;
1922 else
1923 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1924
63000ef6
XZ		 1925 if (tmp & DP_SYNC_VS_HIGH)
1926 flags |= DRM_MODE_FLAG_PVSYNC;
1927 else
1928 flags |= DRM_MODE_FLAG_NVSYNC;
1929 } else {
1930 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1931 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1932 flags |= DRM_MODE_FLAG_PHSYNC;
1933 else
1934 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1935
63000ef6
XZ		 1936 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1937 flags |= DRM_MODE_FLAG_PVSYNC;
1938 else
1939 flags |= DRM_MODE_FLAG_NVSYNC;
1940 }
045ac3b5
JB		 1941
1942 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1943
eb14cb74
VS		 1944 pipe_config->has_dp_encoder = true;
1945
1946 intel_dp_get_m_n(crtc, pipe_config);
1947
18442d08 1948 if (port == PORT_A) {
f1f644dc
JB		 1949 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1950 pipe_config->port_clock = 162000;
1951 else
1952 pipe_config->port_clock = 270000;
1953 }
18442d08
VS		 1954
1955 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1956 &pipe_config->dp_m_n);
1957
1958 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1959 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1960
241bfc38 1961 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1962
c6cd2ee2
JN		 1963 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1964 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1965 /*
1966 * This is a big fat ugly hack.
1967 *
1968 * Some machines in UEFI boot mode provide us a VBT that has 18
1969 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1970 * unknown we fail to light up. Yet the same BIOS boots up with
1971 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1972 * max, not what it tells us to use.
1973 *
1974 * Note: This will still be broken if the eDP panel is not lit
1975 * up by the BIOS, and thus we can't get the mode at module
1976 * load.
1977 */
1978 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1979 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1980 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1981 }
045ac3b5
JB		 1982}
1983
34eb7579 1984static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1985{
34eb7579 1986 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1987}
1988
2b28bb1b
RV		 1989static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1990{
1991 struct drm_i915_private *dev_priv = dev->dev_private;
1992
18b5992c 1993 if (!HAS_PSR(dev))
2b28bb1b
RV		 1994 return false;
1995
18b5992c 1996 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1997}
1998
1999static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
2000 struct edp_vsc_psr *vsc_psr)
2001{
2002 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2003 struct drm_device *dev = dig_port->base.base.dev;
2004 struct drm_i915_private *dev_priv = dev->dev_private;
2005 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
2006 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
2007 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
2008 uint32_t *data = (uint32_t *) vsc_psr;
2009 unsigned int i;
2010
2011 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2012 the video DIP being updated before program video DIP data buffer
2013 registers for DIP being updated. */
2014 I915_WRITE(ctl_reg, 0);
2015 POSTING_READ(ctl_reg);
2016
2017 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
2018 if (i < sizeof(struct edp_vsc_psr))
2019 I915_WRITE(data_reg + i, *data++);
2020 else
2021 I915_WRITE(data_reg + i, 0);
2022 }
2023
2024 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
2025 POSTING_READ(ctl_reg);
2026}
2027
ba80f4d4 2028static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
2b28bb1b 2029{
2b28bb1b
RV		 2030 struct edp_vsc_psr psr_vsc;
2031
2b28bb1b
RV		 2032 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2033 memset(&psr_vsc, 0, sizeof(psr_vsc));
2034 psr_vsc.sdp_header.HB0 = 0;
2035 psr_vsc.sdp_header.HB1 = 0x7;
2036 psr_vsc.sdp_header.HB2 = 0x2;
2037 psr_vsc.sdp_header.HB3 = 0x8;
2038 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2b28bb1b
RV		 2039}
2040
2041static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2042{
0e0ae652
RV		 2043 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2044 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2045 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2046 uint32_t aux_clock_divider;
2b28bb1b 2047 int precharge = 0x3;
0e0ae652 2048 bool only_standby = false;
5ca476f8
VS		 2049 static const uint8_t aux_msg[] = {
2050 [0] = DP_AUX_NATIVE_WRITE << 4,
2051 [1] = DP_SET_POWER >> 8,
2052 [2] = DP_SET_POWER & 0xff,
2053 [3] = 1 - 1,
2054 [4] = DP_SET_POWER_D0,
2055 };
2056 int i;
2057
2058 BUILD_BUG_ON(sizeof(aux_msg) > 20);
2b28bb1b 2059
ec5b01dd
DL		 2060 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2061
0e0ae652
RV		 2062 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2063 only_standby = true;
2064
2b28bb1b 2065 /* Enable PSR in sink */
0e0ae652 2066 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2067 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2068 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2069 else
9d1a1031
JN		 2070 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2071 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2072
2073 /* Setup AUX registers */
5ca476f8
VS		 2074 for (i = 0; i < sizeof(aux_msg); i += 4)
2075 I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
2076 pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
2077
18b5992c 2078 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b 2079 DP_AUX_CH_CTL_TIME_OUT_400us |
5ca476f8 2080 (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2b28bb1b
RV		 2081 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2082 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2083}
2084
2085static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2086{
0e0ae652
RV		 2087 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2088 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2089 struct drm_i915_private *dev_priv = dev->dev_private;
2090 uint32_t max_sleep_time = 0x1f;
2091 uint32_t idle_frames = 1;
2092 uint32_t val = 0x0;
ed8546ac 2093 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2094 bool only_standby = false;
2095
2096 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2097 only_standby = true;
2b28bb1b 2098
0e0ae652 2099 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2100 val |= EDP_PSR_LINK_STANDBY;
2101 val |= EDP_PSR_TP2_TP3_TIME_0us;
2102 val |= EDP_PSR_TP1_TIME_0us;
2103 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2104 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2105 } else
2106 val |= EDP_PSR_LINK_DISABLE;
2107
18b5992c 2108 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2109 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2110 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2111 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2112 EDP_PSR_ENABLE);
2113}
2114
3f51e471
RV		 2115static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2116{
2117 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2118 struct drm_device *dev = dig_port->base.base.dev;
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2120 struct drm_crtc *crtc = dig_port->base.base.crtc;
2121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2122
f0355c4a 2123 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2124 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2125 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2126
a031d709
RV		 2127 dev_priv->psr.source_ok = false;
2128
9ca15301 2129 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2130 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2131 return false;
2132 }
2133
d330a953 2134 if (!i915.enable_psr) {
105b7c11 2135 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2136 return false;
2137 }
2138
4c8c7000
RV		 2139 /* Below limitations aren't valid for Broadwell */
2140 if (IS_BROADWELL(dev))
2141 goto out;
2142
3f51e471
RV		 2143 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2144 S3D_ENABLE) {
2145 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2146 return false;
2147 }
2148
ca73b4f0 2149 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2150 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2151 return false;
2152 }
2153
4c8c7000 2154 out:
a031d709 2155 dev_priv->psr.source_ok = true;
3f51e471
RV		 2156 return true;
2157}
2158
3d739d92 2159static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2160{
7c8f8a70
RV		 2161 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2162 struct drm_device *dev = intel_dig_port->base.base.dev;
2163 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2164
3638379c
DV		 2165 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2166 WARN_ON(dev_priv->psr.active);
f0355c4a 2167 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2168
7ca5a41f 2169 /* Enable/Re-enable PSR on the host */
2b28bb1b 2170 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2171
7c8f8a70 2172 dev_priv->psr.active = true;
2b28bb1b
RV		 2173}
2174
3d739d92
RV		 2175void intel_edp_psr_enable(struct intel_dp *intel_dp)
2176{
2177 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2178 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2179
4704c573
RV		 2180 if (!HAS_PSR(dev)) {
2181 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2182 return;
2183 }
2184
34eb7579
RV		 2185 if (!is_edp_psr(intel_dp)) {
2186 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2187 return;
2188 }
2189
f0355c4a 2190 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2191 if (dev_priv->psr.enabled) {
2192 DRM_DEBUG_KMS("PSR already in use\n");
0aa48783 2193 goto unlock;
109fc2ad
DV		 2194 }
2195
0aa48783
RV		 2196 if (!intel_edp_psr_match_conditions(intel_dp))
2197 goto unlock;
2198
9ca15301
DV		 2199 dev_priv->psr.busy_frontbuffer_bits = 0;
2200
ba80f4d4
RV		 2201 intel_edp_psr_setup_vsc(intel_dp);
2202
2203 /* Avoid continuous PSR exit by masking memup and hpd */
2204 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2205 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
16487254 2206
7ca5a41f
RV		 2207 /* Enable PSR on the panel */
2208 intel_edp_psr_enable_sink(intel_dp);
2209
0aa48783
RV		 2210 dev_priv->psr.enabled = intel_dp;
2211unlock:
f0355c4a 2212 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2213}
2214
2b28bb1b
RV		 2215void intel_edp_psr_disable(struct intel_dp *intel_dp)
2216{
2217 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2218 struct drm_i915_private *dev_priv = dev->dev_private;
2219
f0355c4a
DV		 2220 mutex_lock(&dev_priv->psr.lock);
2221 if (!dev_priv->psr.enabled) {
2222 mutex_unlock(&dev_priv->psr.lock);
2223 return;
2224 }
2225
3638379c
DV		 2226 if (dev_priv->psr.active) {
2227 I915_WRITE(EDP_PSR_CTL(dev),
2228 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2229
2230 /* Wait till PSR is idle */
2231 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2232 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2233 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2234
3638379c
DV		 2235 dev_priv->psr.active = false;
2236 } else {
2237 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2238 }
7c8f8a70 2239
2807cf69 2240 dev_priv->psr.enabled = NULL;
f0355c4a 2241 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2242
2243 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2244}
2245
f02a326e 2246static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2247{
2248 struct drm_i915_private *dev_priv =
2249 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2250 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2251
8d7f4fe9
RV		 2252 /* We have to make sure PSR is ready for re-enable
2253 * otherwise it keeps disabled until next full enable/disable cycle.
2254 * PSR might take some time to get fully disabled
2255 * and be ready for re-enable.
2256 */
2257 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
2258 EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
2259 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
2260 return;
2261 }
2262
f0355c4a
DV		 2263 mutex_lock(&dev_priv->psr.lock);
2264 intel_dp = dev_priv->psr.enabled;
2265
2807cf69 2266 if (!intel_dp)
f0355c4a 2267 goto unlock;
2807cf69 2268
9ca15301
DV		 2269 /*
2270 * The delayed work can race with an invalidate hence we need to
2271 * recheck. Since psr_flush first clears this and then reschedules we
2272 * won't ever miss a flush when bailing out here.
2273 */
2274 if (dev_priv->psr.busy_frontbuffer_bits)
2275 goto unlock;
2276
2277 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2278unlock:
2279 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2280}
2281
9ca15301 2282static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2283{
2284 struct drm_i915_private *dev_priv = dev->dev_private;
2285
3638379c
DV		 2286 if (dev_priv->psr.active) {
2287 u32 val = I915_READ(EDP_PSR_CTL(dev));
2288
2289 WARN_ON(!(val & EDP_PSR_ENABLE));
2290
2291 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2292
2293 dev_priv->psr.active = false;
2294 }
7c8f8a70 2295
9ca15301
DV		 2296}
2297
2298void intel_edp_psr_invalidate(struct drm_device *dev,
2299 unsigned frontbuffer_bits)
2300{
2301 struct drm_i915_private *dev_priv = dev->dev_private;
2302 struct drm_crtc *crtc;
2303 enum pipe pipe;
2304
9ca15301
DV		 2305 mutex_lock(&dev_priv->psr.lock);
2306 if (!dev_priv->psr.enabled) {
2307 mutex_unlock(&dev_priv->psr.lock);
2308 return;
2309 }
2310
2311 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2312 pipe = to_intel_crtc(crtc)->pipe;
2313
2314 intel_edp_psr_do_exit(dev);
2315
2316 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2317
2318 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2319 mutex_unlock(&dev_priv->psr.lock);
2320}
2321
2322void intel_edp_psr_flush(struct drm_device *dev,
2323 unsigned frontbuffer_bits)
2324{
2325 struct drm_i915_private *dev_priv = dev->dev_private;
2326 struct drm_crtc *crtc;
2327 enum pipe pipe;
2328
9ca15301
DV		 2329 mutex_lock(&dev_priv->psr.lock);
2330 if (!dev_priv->psr.enabled) {
2331 mutex_unlock(&dev_priv->psr.lock);
2332 return;
2333 }
2334
2335 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2336 pipe = to_intel_crtc(crtc)->pipe;
2337 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2338
2339 /*
2340 * On Haswell sprite plane updates don't result in a psr invalidating
2341 * signal in the hardware. Which means we need to manually fake this in
2342 * software for all flushes, not just when we've seen a preceding
2343 * invalidation through frontbuffer rendering.
2344 */
2345 if (IS_HASWELL(dev) &&
2346 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2347 intel_edp_psr_do_exit(dev);
2348
2349 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2350 schedule_delayed_work(&dev_priv->psr.work,
2351 msecs_to_jiffies(100));
f0355c4a 2352 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2353}
2354
2355void intel_edp_psr_init(struct drm_device *dev)
2356{
2357 struct drm_i915_private *dev_priv = dev->dev_private;
2358
7c8f8a70 2359 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2360 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2361}
2362
e8cb4558 2363static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2364{
e8cb4558 2365 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2366 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2367
2368 /* Make sure the panel is off before trying to change the mode. But also
2369 * ensure that we have vdd while we switch off the panel. */
24f3e092 2370 intel_edp_panel_vdd_on(intel_dp);
4be73780 2371 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2372 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2373 intel_edp_panel_off(intel_dp);
3739850b 2374
08aff3fe
VS		 2375 /* disable the port before the pipe on g4x */
2376 if (INTEL_INFO(dev)->gen < 5)
3739850b 2377 intel_dp_link_down(intel_dp);
d240f20f
JB		 2378}
2379
08aff3fe 2380static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2381{
2bd2ad64 2382 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2383 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2384
49277c31 2385 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2386 if (port == PORT_A)
2387 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2388}
2389
2390static void vlv_post_disable_dp(struct intel_encoder *encoder)
2391{
2392 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2393
2394 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2395}
2396
580d3811
VS		 2397static void chv_post_disable_dp(struct intel_encoder *encoder)
2398{
2399 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2400 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2401 struct drm_device *dev = encoder->base.dev;
2402 struct drm_i915_private *dev_priv = dev->dev_private;
2403 struct intel_crtc *intel_crtc =
2404 to_intel_crtc(encoder->base.crtc);
2405 enum dpio_channel ch = vlv_dport_to_channel(dport);
2406 enum pipe pipe = intel_crtc->pipe;
2407 u32 val;
2408
2409 intel_dp_link_down(intel_dp);
2410
2411 mutex_lock(&dev_priv->dpio_lock);
2412
2413 /* Propagate soft reset to data lane reset */
97fd4d5c 2414 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2415 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2416 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2417
97fd4d5c
VS		 2418 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2419 val |= CHV_PCS_REQ_SOFTRESET_EN;
2420 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2421
2422 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2423 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2424 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2425
2426 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2427 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2428 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2429
2430 mutex_unlock(&dev_priv->dpio_lock);
2431}
2432
7b13b58a
VS		 2433static void
2434_intel_dp_set_link_train(struct intel_dp *intel_dp,
2435 uint32_t *DP,
2436 uint8_t dp_train_pat)
2437{
2438 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2439 struct drm_device *dev = intel_dig_port->base.base.dev;
2440 struct drm_i915_private *dev_priv = dev->dev_private;
2441 enum port port = intel_dig_port->port;
2442
2443 if (HAS_DDI(dev)) {
2444 uint32_t temp = I915_READ(DP_TP_CTL(port));
2445
2446 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2447 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2448 else
2449 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2450
2451 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2452 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2453 case DP_TRAINING_PATTERN_DISABLE:
2454 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2455
2456 break;
2457 case DP_TRAINING_PATTERN_1:
2458 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2459 break;
2460 case DP_TRAINING_PATTERN_2:
2461 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2462 break;
2463 case DP_TRAINING_PATTERN_3:
2464 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2465 break;
2466 }
2467 I915_WRITE(DP_TP_CTL(port), temp);
2468
2469 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2470 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2471
2472 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2473 case DP_TRAINING_PATTERN_DISABLE:
2474 *DP |= DP_LINK_TRAIN_OFF_CPT;
2475 break;
2476 case DP_TRAINING_PATTERN_1:
2477 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2478 break;
2479 case DP_TRAINING_PATTERN_2:
2480 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2481 break;
2482 case DP_TRAINING_PATTERN_3:
2483 DRM_ERROR("DP training pattern 3 not supported\n");
2484 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2485 break;
2486 }
2487
2488 } else {
2489 if (IS_CHERRYVIEW(dev))
2490 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2491 else
2492 *DP &= ~DP_LINK_TRAIN_MASK;
2493
2494 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2495 case DP_TRAINING_PATTERN_DISABLE:
2496 *DP |= DP_LINK_TRAIN_OFF;
2497 break;
2498 case DP_TRAINING_PATTERN_1:
2499 *DP |= DP_LINK_TRAIN_PAT_1;
2500 break;
2501 case DP_TRAINING_PATTERN_2:
2502 *DP |= DP_LINK_TRAIN_PAT_2;
2503 break;
2504 case DP_TRAINING_PATTERN_3:
2505 if (IS_CHERRYVIEW(dev)) {
2506 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2507 } else {
2508 DRM_ERROR("DP training pattern 3 not supported\n");
2509 *DP |= DP_LINK_TRAIN_PAT_2;
2510 }
2511 break;
2512 }
2513 }
2514}
2515
2516static void intel_dp_enable_port(struct intel_dp *intel_dp)
2517{
2518 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2519 struct drm_i915_private *dev_priv = dev->dev_private;
2520
2521 intel_dp->DP |= DP_PORT_EN;
2522
2523 /* enable with pattern 1 (as per spec) */
2524 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2525 DP_TRAINING_PATTERN_1);
2526
2527 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2528 POSTING_READ(intel_dp->output_reg);
2529}
2530
e8cb4558 2531static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2532{
e8cb4558
DV		 2533 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2534 struct drm_device *dev = encoder->base.dev;
2535 struct drm_i915_private *dev_priv = dev->dev_private;
2536 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2537
0c33d8d7
DV		 2538 if (WARN_ON(dp_reg & DP_PORT_EN))
2539 return;
5d613501 2540
7b13b58a 2541 intel_dp_enable_port(intel_dp);
24f3e092 2542 intel_edp_panel_vdd_on(intel_dp);
4be73780 2543 intel_edp_panel_on(intel_dp);
1e0560e0 2544 intel_edp_panel_vdd_off(intel_dp, true);
f01eca2e 2545 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2546 intel_dp_start_link_train(intel_dp);
33a34e4e 2547 intel_dp_complete_link_train(intel_dp);
3ab9c637 2548 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2549}
89b667f8 2550
ecff4f3b
JN		 2551static void g4x_enable_dp(struct intel_encoder *encoder)
2552{
828f5c6e
JN		 2553 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2554
ecff4f3b 2555 intel_enable_dp(encoder);
4be73780 2556 intel_edp_backlight_on(intel_dp);
ab1f90f9 2557}
89b667f8 2558
ab1f90f9
JN		 2559static void vlv_enable_dp(struct intel_encoder *encoder)
2560{
828f5c6e
JN		 2561 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2562
4be73780 2563 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2564}
2565
ecff4f3b 2566static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2567{
2568 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2569 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2570
8ac33ed3
DV		 2571 intel_dp_prepare(encoder);
2572
d41f1efb
DV		 2573 /* Only ilk+ has port A */
2574 if (dport->port == PORT_A) {
2575 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2576 ironlake_edp_pll_on(intel_dp);
d41f1efb 2577 }
ab1f90f9
JN		 2578}
2579
a4a5d2f8
VS		 2580static void vlv_steal_power_sequencer(struct drm_device *dev,
2581 enum pipe pipe)
2582{
2583 struct drm_i915_private *dev_priv = dev->dev_private;
2584 struct intel_encoder *encoder;
2585
2586 lockdep_assert_held(&dev_priv->pps_mutex);
2587
2588 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2589 base.head) {
2590 struct intel_dp *intel_dp;
773538e8 2591 enum port port;
a4a5d2f8
VS		 2592
2593 if (encoder->type != INTEL_OUTPUT_EDP)
2594 continue;
2595
2596 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2597 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2598
2599 if (intel_dp->pps_pipe != pipe)
2600 continue;
2601
2602 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2603 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 2604
2605 /* make sure vdd is off before we steal it */
2606 edp_panel_vdd_off_sync(intel_dp);
2607
2608 intel_dp->pps_pipe = INVALID_PIPE;
2609 }
2610}
2611
2612static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2613{
2614 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2615 struct intel_encoder *encoder = &intel_dig_port->base;
2616 struct drm_device *dev = encoder->base.dev;
2617 struct drm_i915_private *dev_priv = dev->dev_private;
2618 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2619 struct edp_power_seq power_seq;
2620
2621 lockdep_assert_held(&dev_priv->pps_mutex);
2622
2623 if (intel_dp->pps_pipe == crtc->pipe)
2624 return;
2625
2626 /*
2627 * If another power sequencer was being used on this
2628 * port previously make sure to turn off vdd there while
2629 * we still have control of it.
2630 */
2631 if (intel_dp->pps_pipe != INVALID_PIPE)
2632 edp_panel_vdd_off_sync(intel_dp);
2633
2634 /*
2635 * We may be stealing the power
2636 * sequencer from another port.
2637 */
2638 vlv_steal_power_sequencer(dev, crtc->pipe);
2639
2640 /* now it's all ours */
2641 intel_dp->pps_pipe = crtc->pipe;
2642
2643 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2644 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2645
2646 /* init power sequencer on this pipe and port */
2647 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2648 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2649 &power_seq);
2650}
2651
ab1f90f9 2652static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2653{
2bd2ad64 2654 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2655 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2656 struct drm_device *dev = encoder->base.dev;
89b667f8 2657 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2658 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2659 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2660 int pipe = intel_crtc->pipe;
2661 u32 val;
a4fc5ed6 2662
ab1f90f9 2663 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2664
ab3c759a 2665 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2666 val = 0;
2667 if (pipe)
2668 val |= (1<<21);
2669 else
2670 val &= ~(1<<21);
2671 val |= 0x001000c4;
ab3c759a
CML		 2672 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2673 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2674 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2675
ab1f90f9
JN		 2676 mutex_unlock(&dev_priv->dpio_lock);
2677
2cac613b 2678 if (is_edp(intel_dp)) {
773538e8 2679 pps_lock(intel_dp);
a4a5d2f8 2680 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2681 pps_unlock(intel_dp);
2cac613b 2682 }
bf13e81b 2683
ab1f90f9
JN		 2684 intel_enable_dp(encoder);
2685
e4607fcf 2686 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2687}
2688
ecff4f3b 2689static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2690{
2691 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2692 struct drm_device *dev = encoder->base.dev;
2693 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2694 struct intel_crtc *intel_crtc =
2695 to_intel_crtc(encoder->base.crtc);
e4607fcf 2696 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2697 int pipe = intel_crtc->pipe;
89b667f8 2698
8ac33ed3
DV		 2699 intel_dp_prepare(encoder);
2700
89b667f8 2701 /* Program Tx lane resets to default */
0980a60f 2702 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2703 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2704 DPIO_PCS_TX_LANE2_RESET |
2705 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2706 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2707 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2708 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2709 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2710 DPIO_PCS_CLK_SOFT_RESET);
2711
2712 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2713 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2714 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2715 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2716 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2717}
2718
e4a1d846
CML		 2719static void chv_pre_enable_dp(struct intel_encoder *encoder)
2720{
2721 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2722 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2723 struct drm_device *dev = encoder->base.dev;
2724 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2725 struct intel_crtc *intel_crtc =
2726 to_intel_crtc(encoder->base.crtc);
2727 enum dpio_channel ch = vlv_dport_to_channel(dport);
2728 int pipe = intel_crtc->pipe;
2729 int data, i;
949c1d43 2730 u32 val;
e4a1d846 2731
e4a1d846 2732 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2733
2734 /* Deassert soft data lane reset*/
97fd4d5c 2735 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2736 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2737 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2738
2739 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2740 val |= CHV_PCS_REQ_SOFTRESET_EN;
2741 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2742
2743 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2744 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2745 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2746
97fd4d5c 2747 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2748 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2749 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2750
2751 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2752 for (i = 0; i < 4; i++) {
2753 /* Set the latency optimal bit */
2754 data = (i == 1) ? 0x0 : 0x6;
2755 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2756 data << DPIO_FRC_LATENCY_SHFIT);
2757
2758 /* Set the upar bit */
2759 data = (i == 1) ? 0x0 : 0x1;
2760 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2761 data << DPIO_UPAR_SHIFT);
2762 }
2763
2764 /* Data lane stagger programming */
2765 /* FIXME: Fix up value only after power analysis */
2766
2767 mutex_unlock(&dev_priv->dpio_lock);
2768
2769 if (is_edp(intel_dp)) {
773538e8 2770 pps_lock(intel_dp);
a4a5d2f8 2771 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2772 pps_unlock(intel_dp);
e4a1d846
CML		 2773 }
2774
2775 intel_enable_dp(encoder);
2776
2777 vlv_wait_port_ready(dev_priv, dport);
2778}
2779
9197c88b
VS		 2780static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2781{
2782 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2783 struct drm_device *dev = encoder->base.dev;
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2785 struct intel_crtc *intel_crtc =
2786 to_intel_crtc(encoder->base.crtc);
2787 enum dpio_channel ch = vlv_dport_to_channel(dport);
2788 enum pipe pipe = intel_crtc->pipe;
2789 u32 val;
2790
625695f8
VS		 2791 intel_dp_prepare(encoder);
2792
9197c88b
VS		 2793 mutex_lock(&dev_priv->dpio_lock);
2794
b9e5ac3c
VS		 2795 /* program left/right clock distribution */
2796 if (pipe != PIPE_B) {
2797 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2798 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2799 if (ch == DPIO_CH0)
2800 val |= CHV_BUFLEFTENA1_FORCE;
2801 if (ch == DPIO_CH1)
2802 val |= CHV_BUFRIGHTENA1_FORCE;
2803 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2804 } else {
2805 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2806 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2807 if (ch == DPIO_CH0)
2808 val |= CHV_BUFLEFTENA2_FORCE;
2809 if (ch == DPIO_CH1)
2810 val |= CHV_BUFRIGHTENA2_FORCE;
2811 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2812 }
2813
9197c88b
VS		 2814 /* program clock channel usage */
2815 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2816 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2817 if (pipe != PIPE_B)
2818 val &= ~CHV_PCS_USEDCLKCHANNEL;
2819 else
2820 val |= CHV_PCS_USEDCLKCHANNEL;
2821 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2822
2823 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2824 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2825 if (pipe != PIPE_B)
2826 val &= ~CHV_PCS_USEDCLKCHANNEL;
2827 else
2828 val |= CHV_PCS_USEDCLKCHANNEL;
2829 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2830
2831 /*
2832 * This a a bit weird since generally CL
2833 * matches the pipe, but here we need to
2834 * pick the CL based on the port.
2835 */
2836 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2837 if (pipe != PIPE_B)
2838 val &= ~CHV_CMN_USEDCLKCHANNEL;
2839 else
2840 val |= CHV_CMN_USEDCLKCHANNEL;
2841 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2842
2843 mutex_unlock(&dev_priv->dpio_lock);
2844}
2845
a4fc5ed6 2846/*
df0c237d
JB		 2847 * Native read with retry for link status and receiver capability reads for
2848 * cases where the sink may still be asleep.
9d1a1031
JN		 2849 *
2850 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2851 * supposed to retry 3 times per the spec.
a4fc5ed6 2852 */
9d1a1031
JN		 2853static ssize_t
2854intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2855 void *buffer, size_t size)
a4fc5ed6 2856{
9d1a1031
JN		 2857 ssize_t ret;
2858 int i;
61da5fab 2859
61da5fab 2860 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2861 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2862 if (ret == size)
2863 return ret;
61da5fab
JB		 2864 msleep(1);
2865 }
a4fc5ed6 2866
9d1a1031 2867 return ret;
a4fc5ed6
KP		 2868}
2869
2870/*
2871 * Fetch AUX CH registers 0x202 - 0x207 which contain
2872 * link status information
2873 */
2874static bool
93f62dad 2875intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2876{
9d1a1031
JN		 2877 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2878 DP_LANE0_1_STATUS,
2879 link_status,
2880 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2881}
2882
1100244e 2883/* These are source-specific values. */
a4fc5ed6 2884static uint8_t
1a2eb460 2885intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2886{
30add22d 2887 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2888 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2889
5a9d1f1a
DL		 2890 if (INTEL_INFO(dev)->gen >= 9)
2891 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2892 else if (IS_VALLEYVIEW(dev))
bd60018a 2893 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2894 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2895 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2896 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2897 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2898 else
bd60018a 2899 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2900}
2901
2902static uint8_t
2903intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2904{
30add22d 2905 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2906 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2907
5a9d1f1a
DL		 2908 if (INTEL_INFO(dev)->gen >= 9) {
2909 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2910 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2911 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2912 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2913 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2914 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2915 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2916 default:
2917 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2918 }
2919 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2920 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2921 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2922 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2923 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2924 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2925 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2926 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2927 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2928 default:
bd60018a 2929 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2930 }
e2fa6fba
P		 2931 } else if (IS_VALLEYVIEW(dev)) {
2932 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2934 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2935 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2936 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2938 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2939 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2940 default:
bd60018a 2941 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2942 }
bc7d38a4 2943 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2944 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2945 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2946 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2947 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2949 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2950 default:
bd60018a 2951 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2952 }
2953 } else {
2954 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2955 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2956 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2957 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2958 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2959 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2960 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2961 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2962 default:
bd60018a 2963 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2964 }
a4fc5ed6
KP		 2965 }
2966}
2967
e2fa6fba
P		 2968static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2969{
2970 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2971 struct drm_i915_private *dev_priv = dev->dev_private;
2972 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2973 struct intel_crtc *intel_crtc =
2974 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2975 unsigned long demph_reg_value, preemph_reg_value,
2976 uniqtranscale_reg_value;
2977 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2978 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2979 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2980
2981 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2982 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2983 preemph_reg_value = 0x0004000;
2984 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2985 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2986 demph_reg_value = 0x2B405555;
2987 uniqtranscale_reg_value = 0x552AB83A;
2988 break;
bd60018a 2989 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2990 demph_reg_value = 0x2B404040;
2991 uniqtranscale_reg_value = 0x5548B83A;
2992 break;
bd60018a 2993 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2994 demph_reg_value = 0x2B245555;
2995 uniqtranscale_reg_value = 0x5560B83A;
2996 break;
bd60018a 2997 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2998 demph_reg_value = 0x2B405555;
2999 uniqtranscale_reg_value = 0x5598DA3A;
3000 break;
3001 default:
3002 return 0;
3003 }
3004 break;
bd60018a 3005 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3006 preemph_reg_value = 0x0002000;
3007 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3008 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3009 demph_reg_value = 0x2B404040;
3010 uniqtranscale_reg_value = 0x5552B83A;
3011 break;
bd60018a 3012 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3013 demph_reg_value = 0x2B404848;
3014 uniqtranscale_reg_value = 0x5580B83A;
3015 break;
bd60018a 3016 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3017 demph_reg_value = 0x2B404040;
3018 uniqtranscale_reg_value = 0x55ADDA3A;
3019 break;
3020 default:
3021 return 0;
3022 }
3023 break;
bd60018a 3024 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3025 preemph_reg_value = 0x0000000;
3026 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3027 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3028 demph_reg_value = 0x2B305555;
3029 uniqtranscale_reg_value = 0x5570B83A;
3030 break;
bd60018a 3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3032 demph_reg_value = 0x2B2B4040;
3033 uniqtranscale_reg_value = 0x55ADDA3A;
3034 break;
3035 default:
3036 return 0;
3037 }
3038 break;
bd60018a 3039 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3040 preemph_reg_value = 0x0006000;
3041 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3042 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3043 demph_reg_value = 0x1B405555;
3044 uniqtranscale_reg_value = 0x55ADDA3A;
3045 break;
3046 default:
3047 return 0;
3048 }
3049 break;
3050 default:
3051 return 0;
3052 }
3053
0980a60f 3054 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 3055 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3056 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3057 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3058 uniqtranscale_reg_value);
ab3c759a
CML		 3059 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3060 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3061 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3062 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3063 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3064
3065 return 0;
3066}
3067
e4a1d846
CML		 3068static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3069{
3070 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3071 struct drm_i915_private *dev_priv = dev->dev_private;
3072 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3073 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3074 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3075 uint8_t train_set = intel_dp->train_set[0];
3076 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3077 enum pipe pipe = intel_crtc->pipe;
3078 int i;
e4a1d846
CML		 3079
3080 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3081 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3082 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3083 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3084 deemph_reg_value = 128;
3085 margin_reg_value = 52;
3086 break;
bd60018a 3087 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3088 deemph_reg_value = 128;
3089 margin_reg_value = 77;
3090 break;
bd60018a 3091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3092 deemph_reg_value = 128;
3093 margin_reg_value = 102;
3094 break;
bd60018a 3095 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3096 deemph_reg_value = 128;
3097 margin_reg_value = 154;
3098 /* FIXME extra to set for 1200 */
3099 break;
3100 default:
3101 return 0;
3102 }
3103 break;
bd60018a 3104 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3105 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3106 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3107 deemph_reg_value = 85;
3108 margin_reg_value = 78;
3109 break;
bd60018a 3110 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3111 deemph_reg_value = 85;
3112 margin_reg_value = 116;
3113 break;
bd60018a 3114 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3115 deemph_reg_value = 85;
3116 margin_reg_value = 154;
3117 break;
3118 default:
3119 return 0;
3120 }
3121 break;
bd60018a 3122 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3123 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3124 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3125 deemph_reg_value = 64;
3126 margin_reg_value = 104;
3127 break;
bd60018a 3128 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3129 deemph_reg_value = 64;
3130 margin_reg_value = 154;
3131 break;
3132 default:
3133 return 0;
3134 }
3135 break;
bd60018a 3136 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3137 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3138 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3139 deemph_reg_value = 43;
3140 margin_reg_value = 154;
3141 break;
3142 default:
3143 return 0;
3144 }
3145 break;
3146 default:
3147 return 0;
3148 }
3149
3150 mutex_lock(&dev_priv->dpio_lock);
3151
3152 /* Clear calc init */
1966e59e
VS		 3153 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3154 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3155 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3156
3157 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3158 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3159 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3160
3161 /* Program swing deemph */
f72df8db
VS		 3162 for (i = 0; i < 4; i++) {
3163 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3164 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3165 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3166 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3167 }
e4a1d846
CML		 3168
3169 /* Program swing margin */
f72df8db
VS		 3170 for (i = 0; i < 4; i++) {
3171 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3172 val &= ~DPIO_SWING_MARGIN000_MASK;
3173 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3174 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3175 }
e4a1d846
CML		 3176
3177 /* Disable unique transition scale */
f72df8db
VS		 3178 for (i = 0; i < 4; i++) {
3179 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3180 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3181 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3182 }
e4a1d846
CML		 3183
3184 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3185 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3186 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3187 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3188
3189 /*
3190 * The document said it needs to set bit 27 for ch0 and bit 26
3191 * for ch1. Might be a typo in the doc.
3192 * For now, for this unique transition scale selection, set bit
3193 * 27 for ch0 and ch1.
3194 */
f72df8db
VS		 3195 for (i = 0; i < 4; i++) {
3196 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3197 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3198 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3199 }
e4a1d846 3200
f72df8db
VS		 3201 for (i = 0; i < 4; i++) {
3202 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3203 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3204 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3205 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3206 }
e4a1d846
CML		 3207 }
3208
3209 /* Start swing calculation */
1966e59e
VS		 3210 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3211 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3212 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3213
3214 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3215 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3216 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3217
3218 /* LRC Bypass */
3219 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3220 val |= DPIO_LRC_BYPASS;
3221 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3222
3223 mutex_unlock(&dev_priv->dpio_lock);
3224
3225 return 0;
3226}
3227
a4fc5ed6 3228static void
0301b3ac
JN		 3229intel_get_adjust_train(struct intel_dp *intel_dp,
3230 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3231{
3232 uint8_t v = 0;
3233 uint8_t p = 0;
3234 int lane;
1a2eb460
KP		 3235 uint8_t voltage_max;
3236 uint8_t preemph_max;
a4fc5ed6 3237
33a34e4e 3238 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3239 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3240 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3241
3242 if (this_v > v)
3243 v = this_v;
3244 if (this_p > p)
3245 p = this_p;
3246 }
3247
1a2eb460 3248 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3249 if (v >= voltage_max)
3250 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3251
1a2eb460
KP		 3252 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3253 if (p >= preemph_max)
3254 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3255
3256 for (lane = 0; lane < 4; lane++)
33a34e4e 3257 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3258}
3259
3260static uint32_t
f0a3424e 3261intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3262{
3cf2efb1 3263 uint32_t signal_levels = 0;
a4fc5ed6 3264
3cf2efb1 3265 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3266 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3267 default:
3268 signal_levels |= DP_VOLTAGE_0_4;
3269 break;
bd60018a 3270 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3271 signal_levels |= DP_VOLTAGE_0_6;
3272 break;
bd60018a 3273 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3274 signal_levels |= DP_VOLTAGE_0_8;
3275 break;
bd60018a 3276 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3277 signal_levels |= DP_VOLTAGE_1_2;
3278 break;
3279 }
3cf2efb1 3280 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3281 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3282 default:
3283 signal_levels |= DP_PRE_EMPHASIS_0;
3284 break;
bd60018a 3285 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3286 signal_levels |= DP_PRE_EMPHASIS_3_5;
3287 break;
bd60018a 3288 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3289 signal_levels |= DP_PRE_EMPHASIS_6;
3290 break;
bd60018a 3291 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3292 signal_levels |= DP_PRE_EMPHASIS_9_5;
3293 break;
3294 }
3295 return signal_levels;
3296}
3297
e3421a18
ZW		 3298/* Gen6's DP voltage swing and pre-emphasis control */
3299static uint32_t
3300intel_gen6_edp_signal_levels(uint8_t train_set)
3301{
3c5a62b5
YL		 3302 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3303 DP_TRAIN_PRE_EMPHASIS_MASK);
3304 switch (signal_levels) {
bd60018a
SJ		 3305 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3306 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3307 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3308 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3309 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3310 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3311 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3312 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3313 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3314 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3315 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3316 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3317 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3318 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3319 default:
3c5a62b5
YL		 3320 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3321 "0x%x\n", signal_levels);
3322 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3323 }
3324}
3325
1a2eb460
KP		 3326/* Gen7's DP voltage swing and pre-emphasis control */
3327static uint32_t
3328intel_gen7_edp_signal_levels(uint8_t train_set)
3329{
3330 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3331 DP_TRAIN_PRE_EMPHASIS_MASK);
3332 switch (signal_levels) {
bd60018a 3333 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3334 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3335 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3336 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3337 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3338 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3339
bd60018a 3340 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3341 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3342 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3343 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3344
bd60018a 3345 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3346 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3347 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3348 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3349
3350 default:
3351 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3352 "0x%x\n", signal_levels);
3353 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3354 }
3355}
3356
d6c0d722
PZ		 3357/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3358static uint32_t
f0a3424e 3359intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3360{
d6c0d722
PZ		 3361 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3362 DP_TRAIN_PRE_EMPHASIS_MASK);
3363 switch (signal_levels) {
bd60018a 3364 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3365 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3366 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3367 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3368 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3369 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3370 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3371 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3372
bd60018a 3373 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3374 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3375 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3376 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3377 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3378 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3379
bd60018a 3380 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3381 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3382 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3383 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3384 default:
3385 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3386 "0x%x\n", signal_levels);
c5fe6a06 3387 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3388 }
a4fc5ed6
KP		 3389}
3390
f0a3424e
PZ		 3391/* Properly updates "DP" with the correct signal levels. */
3392static void
3393intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3394{
3395 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3396 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3397 struct drm_device *dev = intel_dig_port->base.base.dev;
3398 uint32_t signal_levels, mask;
3399 uint8_t train_set = intel_dp->train_set[0];
3400
5a9d1f1a 3401 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3402 signal_levels = intel_hsw_signal_levels(train_set);
3403 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3404 } else if (IS_CHERRYVIEW(dev)) {
3405 signal_levels = intel_chv_signal_levels(intel_dp);
3406 mask = 0;
e2fa6fba
P		 3407 } else if (IS_VALLEYVIEW(dev)) {
3408 signal_levels = intel_vlv_signal_levels(intel_dp);
3409 mask = 0;
bc7d38a4 3410 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3411 signal_levels = intel_gen7_edp_signal_levels(train_set);
3412 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3413 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3414 signal_levels = intel_gen6_edp_signal_levels(train_set);
3415 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3416 } else {
3417 signal_levels = intel_gen4_signal_levels(train_set);
3418 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3419 }
3420
3421 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3422
3423 *DP = (*DP & ~mask) | signal_levels;
3424}
3425
a4fc5ed6 3426static bool
ea5b213a 3427intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3428 uint32_t *DP,
58e10eb9 3429 uint8_t dp_train_pat)
a4fc5ed6 3430{
174edf1f
PZ		 3431 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3432 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3433 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3434 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3435 int ret, len;
a4fc5ed6 3436
7b13b58a 3437 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3438
70aff66c 3439 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3440 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3441
2cdfe6c8
JN		 3442 buf[0] = dp_train_pat;
3443 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3444 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3445 /* don't write DP_TRAINING_LANEx_SET on disable */
3446 len = 1;
3447 } else {
3448 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3449 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3450 len = intel_dp->lane_count + 1;
47ea7542 3451 }
a4fc5ed6 3452
9d1a1031
JN		 3453 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3454 buf, len);
2cdfe6c8
JN		 3455
3456 return ret == len;
a4fc5ed6
KP		 3457}
3458
70aff66c
JN		 3459static bool
3460intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3461 uint8_t dp_train_pat)
3462{
953d22e8 3463 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3464 intel_dp_set_signal_levels(intel_dp, DP);
3465 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3466}
3467
3468static bool
3469intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3470 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3471{
3472 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3473 struct drm_device *dev = intel_dig_port->base.base.dev;
3474 struct drm_i915_private *dev_priv = dev->dev_private;
3475 int ret;
3476
3477 intel_get_adjust_train(intel_dp, link_status);
3478 intel_dp_set_signal_levels(intel_dp, DP);
3479
3480 I915_WRITE(intel_dp->output_reg, *DP);
3481 POSTING_READ(intel_dp->output_reg);
3482
9d1a1031
JN		 3483 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3484 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3485
3486 return ret == intel_dp->lane_count;
3487}
3488
3ab9c637
ID		 3489static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3490{
3491 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3492 struct drm_device *dev = intel_dig_port->base.base.dev;
3493 struct drm_i915_private *dev_priv = dev->dev_private;
3494 enum port port = intel_dig_port->port;
3495 uint32_t val;
3496
3497 if (!HAS_DDI(dev))
3498 return;
3499
3500 val = I915_READ(DP_TP_CTL(port));
3501 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3502 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3503 I915_WRITE(DP_TP_CTL(port), val);
3504
3505 /*
3506 * On PORT_A we can have only eDP in SST mode. There the only reason
3507 * we need to set idle transmission mode is to work around a HW issue
3508 * where we enable the pipe while not in idle link-training mode.
3509 * In this case there is requirement to wait for a minimum number of
3510 * idle patterns to be sent.
3511 */
3512 if (port == PORT_A)
3513 return;
3514
3515 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3516 1))
3517 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3518}
3519
33a34e4e 3520/* Enable corresponding port and start training pattern 1 */
c19b0669 3521void
33a34e4e 3522intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3523{
da63a9f2 3524 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3525 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3526 int i;
3527 uint8_t voltage;
cdb0e95b 3528 int voltage_tries, loop_tries;
ea5b213a 3529 uint32_t DP = intel_dp->DP;
6aba5b6c 3530 uint8_t link_config[2];
a4fc5ed6 3531
affa9354 3532 if (HAS_DDI(dev))
c19b0669
PZ		 3533 intel_ddi_prepare_link_retrain(encoder);
3534
3cf2efb1 3535 /* Write the link configuration data */
6aba5b6c
JN		 3536 link_config[0] = intel_dp->link_bw;
3537 link_config[1] = intel_dp->lane_count;
3538 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3539 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3540 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3541
3542 link_config[0] = 0;
3543 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3544 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3545
3546 DP |= DP_PORT_EN;
1a2eb460 3547
70aff66c
JN		 3548 /* clock recovery */
3549 if (!intel_dp_reset_link_train(intel_dp, &DP,
3550 DP_TRAINING_PATTERN_1 |
3551 DP_LINK_SCRAMBLING_DISABLE)) {
3552 DRM_ERROR("failed to enable link training\n");
3553 return;
3554 }
3555
a4fc5ed6 3556 voltage = 0xff;
cdb0e95b
KP		 3557 voltage_tries = 0;
3558 loop_tries = 0;
a4fc5ed6 3559 for (;;) {
70aff66c 3560 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3561
a7c9655f 3562 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3563 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3564 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3565 break;
93f62dad 3566 }
a4fc5ed6 3567
01916270 3568 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3569 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3570 break;
3571 }
3572
3573 /* Check to see if we've tried the max voltage */
3574 for (i = 0; i < intel_dp->lane_count; i++)
3575 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3576 break;
3b4f819d 3577 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3578 ++loop_tries;
3579 if (loop_tries == 5) {
3def84b3 3580 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3581 break;
3582 }
70aff66c
JN		 3583 intel_dp_reset_link_train(intel_dp, &DP,
3584 DP_TRAINING_PATTERN_1 |
3585 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3586 voltage_tries = 0;
3587 continue;
3588 }
a4fc5ed6 3589
3cf2efb1 3590 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3591 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3592 ++voltage_tries;
b06fbda3 3593 if (voltage_tries == 5) {
3def84b3 3594 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3595 break;
3596 }
3597 } else
3598 voltage_tries = 0;
3599 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3600
70aff66c
JN		 3601 /* Update training set as requested by target */
3602 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3603 DRM_ERROR("failed to update link training\n");
3604 break;
3605 }
a4fc5ed6
KP		 3606 }
3607
33a34e4e
JB		 3608 intel_dp->DP = DP;
3609}
3610
c19b0669 3611void
33a34e4e
JB		 3612intel_dp_complete_link_train(struct intel_dp *intel_dp)
3613{
33a34e4e 3614 bool channel_eq = false;
37f80975 3615 int tries, cr_tries;
33a34e4e 3616 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3617 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3618
3619 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3620 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3621 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3622
a4fc5ed6 3623 /* channel equalization */
70aff66c 3624 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3625 training_pattern |
70aff66c
JN		 3626 DP_LINK_SCRAMBLING_DISABLE)) {
3627 DRM_ERROR("failed to start channel equalization\n");
3628 return;
3629 }
3630
a4fc5ed6 3631 tries = 0;
37f80975 3632 cr_tries = 0;
a4fc5ed6
KP		 3633 channel_eq = false;
3634 for (;;) {
70aff66c 3635 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3636
37f80975
JB		 3637 if (cr_tries > 5) {
3638 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3639 break;
3640 }
3641
a7c9655f 3642 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3643 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3644 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3645 break;
70aff66c 3646 }
a4fc5ed6 3647
37f80975 3648 /* Make sure clock is still ok */
01916270 3649 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3650 intel_dp_start_link_train(intel_dp);
70aff66c 3651 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3652 training_pattern |
70aff66c 3653 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3654 cr_tries++;
3655 continue;
3656 }
3657
1ffdff13 3658 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3659 channel_eq = true;
3660 break;
3661 }
a4fc5ed6 3662
37f80975
JB		 3663 /* Try 5 times, then try clock recovery if that fails */
3664 if (tries > 5) {
3665 intel_dp_link_down(intel_dp);
3666 intel_dp_start_link_train(intel_dp);
70aff66c 3667 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3668 training_pattern |
70aff66c 3669 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3670 tries = 0;
3671 cr_tries++;
3672 continue;
3673 }
a4fc5ed6 3674
70aff66c
JN		 3675 /* Update training set as requested by target */
3676 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3677 DRM_ERROR("failed to update link training\n");
3678 break;
3679 }
3cf2efb1 3680 ++tries;
869184a6 3681 }
3cf2efb1 3682
3ab9c637
ID		 3683 intel_dp_set_idle_link_train(intel_dp);
3684
3685 intel_dp->DP = DP;
3686
d6c0d722 3687 if (channel_eq)
07f42258 3688 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3689
3ab9c637
ID		 3690}
3691
3692void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3693{
70aff66c 3694 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3695 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3696}
3697
3698static void
ea5b213a 3699intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3700{
da63a9f2 3701 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3702 enum port port = intel_dig_port->port;
da63a9f2 3703 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3704 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3705 struct intel_crtc *intel_crtc =
3706 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3707 uint32_t DP = intel_dp->DP;
a4fc5ed6 3708
bc76e320 3709 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3710 return;
3711
0c33d8d7 3712 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3713 return;
3714
28c97730 3715 DRM_DEBUG_KMS("\n");
32f9d658 3716
bc7d38a4 3717 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3718 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3719 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3720 } else {
aad3d14d
VS		 3721 if (IS_CHERRYVIEW(dev))
3722 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3723 else
3724 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3725 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3726 }
fe255d00 3727 POSTING_READ(intel_dp->output_reg);
5eb08b69 3728
493a7081 3729 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3730 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3731 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3732
5bddd17f
EA		 3733 /* Hardware workaround: leaving our transcoder select
3734 * set to transcoder B while it's off will prevent the
3735 * corresponding HDMI output on transcoder A.
3736 *
3737 * Combine this with another hardware workaround:
3738 * transcoder select bit can only be cleared while the
3739 * port is enabled.
3740 */
3741 DP &= ~DP_PIPEB_SELECT;
3742 I915_WRITE(intel_dp->output_reg, DP);
3743
3744 /* Changes to enable or select take place the vblank
3745 * after being written.
3746 */
ff50afe9
DV		 3747 if (WARN_ON(crtc == NULL)) {
3748 /* We should never try to disable a port without a crtc
3749 * attached. For paranoia keep the code around for a
3750 * bit. */
31acbcc4
CW		 3751 POSTING_READ(intel_dp->output_reg);
3752 msleep(50);
3753 } else
ab527efc 3754 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3755 }
3756
832afda6 3757 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3758 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3759 POSTING_READ(intel_dp->output_reg);
f01eca2e 3760 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3761}
3762
26d61aad
KP		 3763static bool
3764intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3765{
a031d709
RV		 3766 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3767 struct drm_device *dev = dig_port->base.base.dev;
3768 struct drm_i915_private *dev_priv = dev->dev_private;
3769
9d1a1031
JN		 3770 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3771 sizeof(intel_dp->dpcd)) < 0)
edb39244 3772 return false; /* aux transfer failed */
92fd8fd1 3773
a8e98153 3774 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3775
edb39244
AJ		 3776 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3777 return false; /* DPCD not present */
3778
2293bb5c
SK		 3779 /* Check if the panel supports PSR */
3780 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3781 if (is_edp(intel_dp)) {
9d1a1031
JN		 3782 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3783 intel_dp->psr_dpcd,
3784 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3785 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3786 dev_priv->psr.sink_support = true;
50003939 3787 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3788 }
50003939
JN		 3789 }
3790
06ea66b6
TP		 3791 /* Training Pattern 3 support */
3792 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3793 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3794 intel_dp->use_tps3 = true;
f8d8a672 3795 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3796 } else
3797 intel_dp->use_tps3 = false;
3798
edb39244
AJ		 3799 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3800 DP_DWN_STRM_PORT_PRESENT))
3801 return true; /* native DP sink */
3802
3803 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3804 return true; /* no per-port downstream info */
3805
9d1a1031
JN		 3806 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3807 intel_dp->downstream_ports,
3808 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3809 return false; /* downstream port status fetch failed */
3810
3811 return true;
92fd8fd1
KP		 3812}
3813
0d198328
AJ		 3814static void
3815intel_dp_probe_oui(struct intel_dp *intel_dp)
3816{
3817 u8 buf[3];
3818
3819 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3820 return;
3821
24f3e092 3822 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3823
9d1a1031 3824 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3825 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3826 buf[0], buf[1], buf[2]);
3827
9d1a1031 3828 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3829 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3830 buf[0], buf[1], buf[2]);
351cfc34 3831
1e0560e0 3832 intel_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3833}
3834
0e32b39c
DA		 3835static bool
3836intel_dp_probe_mst(struct intel_dp *intel_dp)
3837{
3838 u8 buf[1];
3839
3840 if (!intel_dp->can_mst)
3841 return false;
3842
3843 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3844 return false;
3845
d337a341 3846 intel_edp_panel_vdd_on(intel_dp);
0e32b39c
DA		 3847 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3848 if (buf[0] & DP_MST_CAP) {
3849 DRM_DEBUG_KMS("Sink is MST capable\n");
3850 intel_dp->is_mst = true;
3851 } else {
3852 DRM_DEBUG_KMS("Sink is not MST capable\n");
3853 intel_dp->is_mst = false;
3854 }
3855 }
1e0560e0 3856 intel_edp_panel_vdd_off(intel_dp, false);
0e32b39c
DA		 3857
3858 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3859 return intel_dp->is_mst;
3860}
3861
d2e216d0
RV		 3862int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3863{
3864 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3865 struct drm_device *dev = intel_dig_port->base.base.dev;
3866 struct intel_crtc *intel_crtc =
3867 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3868 u8 buf;
3869 int test_crc_count;
3870 int attempts = 6;
d2e216d0 3871
ad9dc91b 3872 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3873 return -EIO;
d2e216d0 3874
ad9dc91b 3875 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3876 return -ENOTTY;
3877
ce31d9f4 3878 drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf);
9d1a1031 3879 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3880 buf | DP_TEST_SINK_START) < 0)
bda0381e 3881 return -EIO;
d2e216d0 3882
ad9dc91b
RV		 3883 drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf);
3884 test_crc_count = buf & DP_TEST_COUNT_MASK;
3885
3886 do {
3887 drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf);
3888 intel_wait_for_vblank(dev, intel_crtc->pipe);
3889 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3890
3891 if (attempts == 0) {
3892 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
3893 return -EIO;
3894 }
d2e216d0 3895
9d1a1031 3896 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 3897 return -EIO;
d2e216d0 3898
ce31d9f4
RV		 3899 drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf);
3900 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3901 buf & ~DP_TEST_SINK_START);
3902
d2e216d0
RV		 3903 return 0;
3904}
3905
a60f0e38
JB		 3906static bool
3907intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3908{
9d1a1031
JN		 3909 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3910 DP_DEVICE_SERVICE_IRQ_VECTOR,
3911 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3912}
3913
0e32b39c
DA		 3914static bool
3915intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3916{
3917 int ret;
3918
3919 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3920 DP_SINK_COUNT_ESI,
3921 sink_irq_vector, 14);
3922 if (ret != 14)
3923 return false;
3924
3925 return true;
3926}
3927
a60f0e38
JB		 3928static void
3929intel_dp_handle_test_request(struct intel_dp *intel_dp)
3930{
3931 /* NAK by default */
9d1a1031 3932 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3933}
3934
0e32b39c
DA		 3935static int
3936intel_dp_check_mst_status(struct intel_dp *intel_dp)
3937{
3938 bool bret;
3939
3940 if (intel_dp->is_mst) {
3941 u8 esi[16] = { 0 };
3942 int ret = 0;
3943 int retry;
3944 bool handled;
3945 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3946go_again:
3947 if (bret == true) {
3948
3949 /* check link status - esi[10] = 0x200c */
3950 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3951 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3952 intel_dp_start_link_train(intel_dp);
3953 intel_dp_complete_link_train(intel_dp);
3954 intel_dp_stop_link_train(intel_dp);
3955 }
3956
3957 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3958 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3959
3960 if (handled) {
3961 for (retry = 0; retry < 3; retry++) {
3962 int wret;
3963 wret = drm_dp_dpcd_write(&intel_dp->aux,
3964 DP_SINK_COUNT_ESI+1,
3965 &esi[1], 3);
3966 if (wret == 3) {
3967 break;
3968 }
3969 }
3970
3971 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3972 if (bret == true) {
3973 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3974 goto go_again;
3975 }
3976 } else
3977 ret = 0;
3978
3979 return ret;
3980 } else {
3981 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3982 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3983 intel_dp->is_mst = false;
3984 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3985 /* send a hotplug event */
3986 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3987 }
3988 }
3989 return -EINVAL;
3990}
3991
a4fc5ed6
KP		 3992/*
3993 * According to DP spec
3994 * 5.1.2:
3995 * 1. Read DPCD
3996 * 2. Configure link according to Receiver Capabilities
3997 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3998 * 4. Check link status on receipt of hot-plug interrupt
3999 */
00c09d70 4000void
ea5b213a 4001intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4002{
5b215bcf 4003 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4004 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4005 u8 sink_irq_vector;
93f62dad 4006 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4007
5b215bcf
DA		 4008 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4009
da63a9f2 4010 if (!intel_encoder->connectors_active)
d2b996ac 4011 return;
59cd09e1 4012
da63a9f2 4013 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 4014 return;
4015
1a125d8a
ID		 4016 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4017 return;
4018
92fd8fd1 4019 /* Try to read receiver status if the link appears to be up */
93f62dad 4020 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4021 return;
4022 }
4023
92fd8fd1 4024 /* Now read the DPCD to see if it's actually running */
26d61aad 4025 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4026 return;
4027 }
4028
a60f0e38
JB		 4029 /* Try to read the source of the interrupt */
4030 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4031 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4032 /* Clear interrupt source */
9d1a1031
JN		 4033 drm_dp_dpcd_writeb(&intel_dp->aux,
4034 DP_DEVICE_SERVICE_IRQ_VECTOR,
4035 sink_irq_vector);
a60f0e38
JB		 4036
4037 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4038 intel_dp_handle_test_request(intel_dp);
4039 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4040 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4041 }
4042
1ffdff13 4043 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4044 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4045 intel_encoder->base.name);
33a34e4e
JB		 4046 intel_dp_start_link_train(intel_dp);
4047 intel_dp_complete_link_train(intel_dp);
3ab9c637 4048 intel_dp_stop_link_train(intel_dp);
33a34e4e 4049 }
a4fc5ed6 4050}
a4fc5ed6 4051
caf9ab24 4052/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4053static enum drm_connector_status
26d61aad 4054intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4055{
caf9ab24 4056 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4057 uint8_t type;
4058
4059 if (!intel_dp_get_dpcd(intel_dp))
4060 return connector_status_disconnected;
4061
4062 /* if there's no downstream port, we're done */
4063 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4064 return connector_status_connected;
caf9ab24
AJ		 4065
4066 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4067 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4068 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4069 uint8_t reg;
9d1a1031
JN		 4070
4071 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4072 &reg, 1) < 0)
caf9ab24 4073 return connector_status_unknown;
9d1a1031 4074
23235177
AJ		 4075 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4076 : connector_status_disconnected;
caf9ab24
AJ		 4077 }
4078
4079 /* If no HPD, poke DDC gently */
0b99836f 4080 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4081 return connector_status_connected;
caf9ab24
AJ		 4082
4083 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4084 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4085 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4086 if (type == DP_DS_PORT_TYPE_VGA ||
4087 type == DP_DS_PORT_TYPE_NON_EDID)
4088 return connector_status_unknown;
4089 } else {
4090 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4091 DP_DWN_STRM_PORT_TYPE_MASK;
4092 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4093 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4094 return connector_status_unknown;
4095 }
caf9ab24
AJ		 4096
4097 /* Anything else is out of spec, warn and ignore */
4098 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4099 return connector_status_disconnected;
71ba9000
AJ		 4100}
4101
d410b56d
CW		 4102static enum drm_connector_status
4103edp_detect(struct intel_dp *intel_dp)
4104{
4105 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4106 enum drm_connector_status status;
4107
4108 status = intel_panel_detect(dev);
4109 if (status == connector_status_unknown)
4110 status = connector_status_connected;
4111
4112 return status;
4113}
4114
5eb08b69 4115static enum drm_connector_status
a9756bb5 4116ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4117{
30add22d 4118 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4119 struct drm_i915_private *dev_priv = dev->dev_private;
4120 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4121
1b469639
DL		 4122 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4123 return connector_status_disconnected;
4124
26d61aad 4125 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4126}
4127
2a592bec
DA		 4128static int g4x_digital_port_connected(struct drm_device *dev,
4129 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4130{
a4fc5ed6 4131 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4132 uint32_t bit;
5eb08b69 4133
232a6ee9
TP		 4134 if (IS_VALLEYVIEW(dev)) {
4135 switch (intel_dig_port->port) {
4136 case PORT_B:
4137 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4138 break;
4139 case PORT_C:
4140 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4141 break;
4142 case PORT_D:
4143 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4144 break;
4145 default:
2a592bec 4146 return -EINVAL;
232a6ee9
TP		 4147 }
4148 } else {
4149 switch (intel_dig_port->port) {
4150 case PORT_B:
4151 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4152 break;
4153 case PORT_C:
4154 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4155 break;
4156 case PORT_D:
4157 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4158 break;
4159 default:
2a592bec 4160 return -EINVAL;
232a6ee9 4161 }
a4fc5ed6
KP		 4162 }
4163
10f76a38 4164 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4165 return 0;
4166 return 1;
4167}
4168
4169static enum drm_connector_status
4170g4x_dp_detect(struct intel_dp *intel_dp)
4171{
4172 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4173 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4174 int ret;
4175
4176 /* Can't disconnect eDP, but you can close the lid... */
4177 if (is_edp(intel_dp)) {
4178 enum drm_connector_status status;
4179
4180 status = intel_panel_detect(dev);
4181 if (status == connector_status_unknown)
4182 status = connector_status_connected;
4183 return status;
4184 }
4185
4186 ret = g4x_digital_port_connected(dev, intel_dig_port);
4187 if (ret == -EINVAL)
4188 return connector_status_unknown;
4189 else if (ret == 0)
a4fc5ed6
KP		 4190 return connector_status_disconnected;
4191
26d61aad 4192 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4193}
4194
8c241fef 4195static struct edid *
beb60608 4196intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4197{
beb60608 4198 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4199
9cd300e0
JN		 4200 /* use cached edid if we have one */
4201 if (intel_connector->edid) {
9cd300e0
JN		 4202 /* invalid edid */
4203 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4204 return NULL;
4205
55e9edeb 4206 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4207 } else
4208 return drm_get_edid(&intel_connector->base,
4209 &intel_dp->aux.ddc);
4210}
8c241fef 4211
beb60608
CW		 4212static void
4213intel_dp_set_edid(struct intel_dp *intel_dp)
4214{
4215 struct intel_connector *intel_connector = intel_dp->attached_connector;
4216 struct edid *edid;
8c241fef 4217
beb60608
CW		 4218 edid = intel_dp_get_edid(intel_dp);
4219 intel_connector->detect_edid = edid;
4220
4221 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4222 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4223 else
4224 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4225}
4226
beb60608
CW		 4227static void
4228intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4229{
beb60608 4230 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4231
beb60608
CW		 4232 kfree(intel_connector->detect_edid);
4233 intel_connector->detect_edid = NULL;
9cd300e0 4234
beb60608
CW		 4235 intel_dp->has_audio = false;
4236}
d6f24d0f 4237
beb60608
CW		 4238static enum intel_display_power_domain
4239intel_dp_power_get(struct intel_dp *dp)
4240{
4241 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4242 enum intel_display_power_domain power_domain;
4243
4244 power_domain = intel_display_port_power_domain(encoder);
4245 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4246
4247 return power_domain;
4248}
d6f24d0f 4249
beb60608
CW		 4250static void
4251intel_dp_power_put(struct intel_dp *dp,
4252 enum intel_display_power_domain power_domain)
4253{
4254 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4255 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4256}
4257
a9756bb5
ZW		 4258static enum drm_connector_status
4259intel_dp_detect(struct drm_connector *connector, bool force)
4260{
4261 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4263 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4264 struct drm_device *dev = connector->dev;
a9756bb5 4265 enum drm_connector_status status;
671dedd2 4266 enum intel_display_power_domain power_domain;
0e32b39c 4267 bool ret;
a9756bb5 4268
164c8598 4269 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4270 connector->base.id, connector->name);
beb60608 4271 intel_dp_unset_edid(intel_dp);
164c8598 4272
0e32b39c
DA		 4273 if (intel_dp->is_mst) {
4274 /* MST devices are disconnected from a monitor POV */
4275 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4276 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4277 return connector_status_disconnected;
0e32b39c
DA		 4278 }
4279
beb60608 4280 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4281
d410b56d
CW		 4282 /* Can't disconnect eDP, but you can close the lid... */
4283 if (is_edp(intel_dp))
4284 status = edp_detect(intel_dp);
4285 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4286 status = ironlake_dp_detect(intel_dp);
4287 else
4288 status = g4x_dp_detect(intel_dp);
4289 if (status != connector_status_connected)
c8c8fb33 4290 goto out;
a9756bb5 4291
0d198328
AJ		 4292 intel_dp_probe_oui(intel_dp);
4293
0e32b39c
DA		 4294 ret = intel_dp_probe_mst(intel_dp);
4295 if (ret) {
4296 /* if we are in MST mode then this connector
4297 won't appear connected or have anything with EDID on it */
4298 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4299 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4300 status = connector_status_disconnected;
4301 goto out;
4302 }
4303
beb60608 4304 intel_dp_set_edid(intel_dp);
a9756bb5 4305
d63885da
PZ		 4306 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4307 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4308 status = connector_status_connected;
4309
4310out:
beb60608 4311 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4312 return status;
a4fc5ed6
KP		 4313}
4314
beb60608
CW		 4315static void
4316intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4317{
df0e9248 4318 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4319 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4320 enum intel_display_power_domain power_domain;
a4fc5ed6 4321
beb60608
CW		 4322 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4323 connector->base.id, connector->name);
4324 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4325
beb60608
CW		 4326 if (connector->status != connector_status_connected)
4327 return;
671dedd2 4328
beb60608
CW		 4329 power_domain = intel_dp_power_get(intel_dp);
4330
4331 intel_dp_set_edid(intel_dp);
4332
4333 intel_dp_power_put(intel_dp, power_domain);
4334
4335 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4336 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4337}
4338
4339static int intel_dp_get_modes(struct drm_connector *connector)
4340{
4341 struct intel_connector *intel_connector = to_intel_connector(connector);
4342 struct edid *edid;
4343
4344 edid = intel_connector->detect_edid;
4345 if (edid) {
4346 int ret = intel_connector_update_modes(connector, edid);
4347 if (ret)
4348 return ret;
4349 }
32f9d658 4350
f8779fda 4351 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4352 if (is_edp(intel_attached_dp(connector)) &&
4353 intel_connector->panel.fixed_mode) {
f8779fda 4354 struct drm_display_mode *mode;
beb60608
CW		 4355
4356 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4357 intel_connector->panel.fixed_mode);
f8779fda 4358 if (mode) {
32f9d658
ZW		 4359 drm_mode_probed_add(connector, mode);
4360 return 1;
4361 }
4362 }
beb60608 4363
32f9d658 4364 return 0;
a4fc5ed6
KP		 4365}
4366
1aad7ac0
CW		 4367static bool
4368intel_dp_detect_audio(struct drm_connector *connector)
4369{
1aad7ac0 4370 bool has_audio = false;
beb60608 4371 struct edid *edid;
1aad7ac0 4372
beb60608
CW		 4373 edid = to_intel_connector(connector)->detect_edid;
4374 if (edid)
1aad7ac0 4375 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4376
1aad7ac0
CW		 4377 return has_audio;
4378}
4379
f684960e
CW		 4380static int
4381intel_dp_set_property(struct drm_connector *connector,
4382 struct drm_property *property,
4383 uint64_t val)
4384{
e953fd7b 4385 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4386 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4387 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4388 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4389 int ret;
4390
662595df 4391 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4392 if (ret)
4393 return ret;
4394
3f43c48d 4395 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4396 int i = val;
4397 bool has_audio;
4398
4399 if (i == intel_dp->force_audio)
f684960e
CW		 4400 return 0;
4401
1aad7ac0 4402 intel_dp->force_audio = i;
f684960e 4403
c3e5f67b 4404 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4405 has_audio = intel_dp_detect_audio(connector);
4406 else
c3e5f67b 4407 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4408
4409 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4410 return 0;
4411
1aad7ac0 4412 intel_dp->has_audio = has_audio;
f684960e
CW		 4413 goto done;
4414 }
4415
e953fd7b 4416 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4417 bool old_auto = intel_dp->color_range_auto;
4418 uint32_t old_range = intel_dp->color_range;
4419
55bc60db
VS		 4420 switch (val) {
4421 case INTEL_BROADCAST_RGB_AUTO:
4422 intel_dp->color_range_auto = true;
4423 break;
4424 case INTEL_BROADCAST_RGB_FULL:
4425 intel_dp->color_range_auto = false;
4426 intel_dp->color_range = 0;
4427 break;
4428 case INTEL_BROADCAST_RGB_LIMITED:
4429 intel_dp->color_range_auto = false;
4430 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4431 break;
4432 default:
4433 return -EINVAL;
4434 }
ae4edb80
DV		 4435
4436 if (old_auto == intel_dp->color_range_auto &&
4437 old_range == intel_dp->color_range)
4438 return 0;
4439
e953fd7b
CW		 4440 goto done;
4441 }
4442
53b41837
YN		 4443 if (is_edp(intel_dp) &&
4444 property == connector->dev->mode_config.scaling_mode_property) {
4445 if (val == DRM_MODE_SCALE_NONE) {
4446 DRM_DEBUG_KMS("no scaling not supported\n");
4447 return -EINVAL;
4448 }
4449
4450 if (intel_connector->panel.fitting_mode == val) {
4451 /* the eDP scaling property is not changed */
4452 return 0;
4453 }
4454 intel_connector->panel.fitting_mode = val;
4455
4456 goto done;
4457 }
4458
f684960e
CW		 4459 return -EINVAL;
4460
4461done:
c0c36b94
CW		 4462 if (intel_encoder->base.crtc)
4463 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4464
4465 return 0;
4466}
4467
a4fc5ed6 4468static void
73845adf 4469intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4470{
1d508706 4471 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4472
10e972d3 4473 kfree(intel_connector->detect_edid);
beb60608 4474
9cd300e0
JN		 4475 if (!IS_ERR_OR_NULL(intel_connector->edid))
4476 kfree(intel_connector->edid);
4477
acd8db10
PZ		 4478 /* Can't call is_edp() since the encoder may have been destroyed
4479 * already. */
4480 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4481 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4482
a4fc5ed6 4483 drm_connector_cleanup(connector);
55f78c43 4484 kfree(connector);
a4fc5ed6
KP		 4485}
4486
00c09d70 4487void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4488{
da63a9f2
PZ		 4489 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4490 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4491
4f71d0cb 4492 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4493 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4494 drm_encoder_cleanup(encoder);
bd943159
KP		 4495 if (is_edp(intel_dp)) {
4496 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4497 /*
4498 * vdd might still be enabled do to the delayed vdd off.
4499 * Make sure vdd is actually turned off here.
4500 */
773538e8 4501 pps_lock(intel_dp);
4be73780 4502 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4503 pps_unlock(intel_dp);
4504
01527b31
CT		 4505 if (intel_dp->edp_notifier.notifier_call) {
4506 unregister_reboot_notifier(&intel_dp->edp_notifier);
4507 intel_dp->edp_notifier.notifier_call = NULL;
4508 }
bd943159 4509 }
da63a9f2 4510 kfree(intel_dig_port);
24d05927
DV		 4511}
4512
07f9cd0b
ID		 4513static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4514{
4515 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4516
4517 if (!is_edp(intel_dp))
4518 return;
4519
951468f3
VS		 4520 /*
4521 * vdd might still be enabled do to the delayed vdd off.
4522 * Make sure vdd is actually turned off here.
4523 */
773538e8 4524 pps_lock(intel_dp);
07f9cd0b 4525 edp_panel_vdd_off_sync(intel_dp);
773538e8 4526 pps_unlock(intel_dp);
07f9cd0b
ID		 4527}
4528
6d93c0c4
ID		 4529static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4530{
4531 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4532}
4533
a4fc5ed6 4534static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4535 .dpms = intel_connector_dpms,
a4fc5ed6 4536 .detect = intel_dp_detect,
beb60608 4537 .force = intel_dp_force,
a4fc5ed6 4538 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4539 .set_property = intel_dp_set_property,
73845adf 4540 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4541};
4542
4543static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4544 .get_modes = intel_dp_get_modes,
4545 .mode_valid = intel_dp_mode_valid,
df0e9248 4546 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4547};
4548
a4fc5ed6 4549static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4550 .reset = intel_dp_encoder_reset,
24d05927 4551 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4552};
4553
0e32b39c 4554void
21d40d37 4555intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4556{
0e32b39c 4557 return;
c8110e52 4558}
6207937d 4559
13cf5504
DA		 4560bool
4561intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4562{
4563 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4564 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4565 struct drm_device *dev = intel_dig_port->base.base.dev;
4566 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4567 enum intel_display_power_domain power_domain;
4568 bool ret = true;
4569
0e32b39c
DA		 4570 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4571 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4572
26fbb774
VS		 4573 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4574 port_name(intel_dig_port->port),
0e32b39c 4575 long_hpd ? "long" : "short");
13cf5504 4576
1c767b33
ID		 4577 power_domain = intel_display_port_power_domain(intel_encoder);
4578 intel_display_power_get(dev_priv, power_domain);
4579
0e32b39c 4580 if (long_hpd) {
2a592bec
DA		 4581
4582 if (HAS_PCH_SPLIT(dev)) {
4583 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4584 goto mst_fail;
4585 } else {
4586 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4587 goto mst_fail;
4588 }
0e32b39c
DA		 4589
4590 if (!intel_dp_get_dpcd(intel_dp)) {
4591 goto mst_fail;
4592 }
4593
4594 intel_dp_probe_oui(intel_dp);
4595
4596 if (!intel_dp_probe_mst(intel_dp))
4597 goto mst_fail;
4598
4599 } else {
4600 if (intel_dp->is_mst) {
1c767b33 4601 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4602 goto mst_fail;
4603 }
4604
4605 if (!intel_dp->is_mst) {
4606 /*
4607 * we'll check the link status via the normal hot plug path later -
4608 * but for short hpds we should check it now
4609 */
5b215bcf 4610 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4611 intel_dp_check_link_status(intel_dp);
5b215bcf 4612 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4613 }
4614 }
1c767b33
ID		 4615 ret = false;
4616 goto put_power;
0e32b39c
DA		 4617mst_fail:
4618 /* if we were in MST mode, and device is not there get out of MST mode */
4619 if (intel_dp->is_mst) {
4620 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4621 intel_dp->is_mst = false;
4622 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4623 }
1c767b33
ID		 4624put_power:
4625 intel_display_power_put(dev_priv, power_domain);
4626
4627 return ret;
13cf5504
DA		 4628}
4629
e3421a18
ZW		 4630/* Return which DP Port should be selected for Transcoder DP control */
4631int
0206e353 4632intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4633{
4634 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4635 struct intel_encoder *intel_encoder;
4636 struct intel_dp *intel_dp;
e3421a18 4637
fa90ecef
PZ		 4638 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4639 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4640
fa90ecef
PZ		 4641 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4642 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4643 return intel_dp->output_reg;
e3421a18 4644 }
ea5b213a 4645
e3421a18
ZW		 4646 return -1;
4647}
4648
36e83a18 4649/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4650bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4651{
4652 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4653 union child_device_config *p_child;
36e83a18 4654 int i;
5d8a7752
VS		 4655 static const short port_mapping[] = {
4656 [PORT_B] = PORT_IDPB,
4657 [PORT_C] = PORT_IDPC,
4658 [PORT_D] = PORT_IDPD,
4659 };
36e83a18 4660
3b32a35b
VS		 4661 if (port == PORT_A)
4662 return true;
4663
41aa3448 4664 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4665 return false;
4666
41aa3448
RV		 4667 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4668 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4669
5d8a7752 4670 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4671 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4672 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4673 return true;
4674 }
4675 return false;
4676}
4677
0e32b39c 4678void
f684960e
CW		 4679intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4680{
53b41837
YN		 4681 struct intel_connector *intel_connector = to_intel_connector(connector);
4682
3f43c48d 4683 intel_attach_force_audio_property(connector);
e953fd7b 4684 intel_attach_broadcast_rgb_property(connector);
55bc60db 4685 intel_dp->color_range_auto = true;
53b41837
YN		 4686
4687 if (is_edp(intel_dp)) {
4688 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4689 drm_object_attach_property(
4690 &connector->base,
53b41837 4691 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4692 DRM_MODE_SCALE_ASPECT);
4693 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4694 }
f684960e
CW		 4695}
4696
dada1a9f
ID		 4697static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4698{
4699 intel_dp->last_power_cycle = jiffies;
4700 intel_dp->last_power_on = jiffies;
4701 intel_dp->last_backlight_off = jiffies;
4702}
4703
67a54566
DV		 4704static void
4705intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4706 struct intel_dp *intel_dp,
4707 struct edp_power_seq *out)
67a54566
DV		 4708{
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4710 struct edp_power_seq cur, vbt, spec, final;
4711 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4712 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4713
e39b999a
VS		 4714 lockdep_assert_held(&dev_priv->pps_mutex);
4715
453c5420 4716 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4717 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4718 pp_on_reg = PCH_PP_ON_DELAYS;
4719 pp_off_reg = PCH_PP_OFF_DELAYS;
4720 pp_div_reg = PCH_PP_DIVISOR;
4721 } else {
bf13e81b
JN		 4722 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4723
4724 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4725 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4726 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4727 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4728 }
67a54566
DV		 4729
4730 /* Workaround: Need to write PP_CONTROL with the unlock key as
4731 * the very first thing. */
453c5420 4732 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4733 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4734
453c5420
JB		 4735 pp_on = I915_READ(pp_on_reg);
4736 pp_off = I915_READ(pp_off_reg);
4737 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4738
4739 /* Pull timing values out of registers */
4740 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4741 PANEL_POWER_UP_DELAY_SHIFT;
4742
4743 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4744 PANEL_LIGHT_ON_DELAY_SHIFT;
4745
4746 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4747 PANEL_LIGHT_OFF_DELAY_SHIFT;
4748
4749 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4750 PANEL_POWER_DOWN_DELAY_SHIFT;
4751
4752 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4753 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4754
4755 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4756 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4757
41aa3448 4758 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4759
4760 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4761 * our hw here, which are all in 100usec. */
4762 spec.t1_t3 = 210 * 10;
4763 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4764 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4765 spec.t10 = 500 * 10;
4766 /* This one is special and actually in units of 100ms, but zero
4767 * based in the hw (so we need to add 100 ms). But the sw vbt
4768 * table multiplies it with 1000 to make it in units of 100usec,
4769 * too. */
4770 spec.t11_t12 = (510 + 100) * 10;
4771
4772 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4773 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4774
4775 /* Use the max of the register settings and vbt. If both are
4776 * unset, fall back to the spec limits. */
4777#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4778 spec.field : \
4779 max(cur.field, vbt.field))
4780 assign_final(t1_t3);
4781 assign_final(t8);
4782 assign_final(t9);
4783 assign_final(t10);
4784 assign_final(t11_t12);
4785#undef assign_final
4786
4787#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4788 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4789 intel_dp->backlight_on_delay = get_delay(t8);
4790 intel_dp->backlight_off_delay = get_delay(t9);
4791 intel_dp->panel_power_down_delay = get_delay(t10);
4792 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4793#undef get_delay
4794
f30d26e4
JN		 4795 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4796 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4797 intel_dp->panel_power_cycle_delay);
4798
4799 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4800 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4801
4802 if (out)
4803 *out = final;
4804}
4805
4806static void
4807intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4808 struct intel_dp *intel_dp,
4809 struct edp_power_seq *seq)
4810{
4811 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4812 u32 pp_on, pp_off, pp_div, port_sel = 0;
4813 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4814 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4815 enum port port = dp_to_dig_port(intel_dp)->port;
453c5420 4816
e39b999a 4817 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4818
4819 if (HAS_PCH_SPLIT(dev)) {
4820 pp_on_reg = PCH_PP_ON_DELAYS;
4821 pp_off_reg = PCH_PP_OFF_DELAYS;
4822 pp_div_reg = PCH_PP_DIVISOR;
4823 } else {
bf13e81b
JN		 4824 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4825
4826 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4827 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4828 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4829 }
4830
b2f19d1a
PZ		 4831 /*
4832 * And finally store the new values in the power sequencer. The
4833 * backlight delays are set to 1 because we do manual waits on them. For
4834 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4835 * we'll end up waiting for the backlight off delay twice: once when we
4836 * do the manual sleep, and once when we disable the panel and wait for
4837 * the PP_STATUS bit to become zero.
4838 */
f30d26e4 4839 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4840 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4841 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4842 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4843 /* Compute the divisor for the pp clock, simply match the Bspec
4844 * formula. */
453c5420 4845 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4846 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4847 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4848
4849 /* Haswell doesn't have any port selection bits for the panel
4850 * power sequencer any more. */
bc7d38a4 4851 if (IS_VALLEYVIEW(dev)) {
ad933b56 4852 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4853 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4854 if (port == PORT_A)
a24c144c 4855 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4856 else
a24c144c 4857 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4858 }
4859
453c5420
JB		 4860 pp_on |= port_sel;
4861
4862 I915_WRITE(pp_on_reg, pp_on);
4863 I915_WRITE(pp_off_reg, pp_off);
4864 I915_WRITE(pp_div_reg, pp_div);
67a54566 4865
67a54566 4866 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4867 I915_READ(pp_on_reg),
4868 I915_READ(pp_off_reg),
4869 I915_READ(pp_div_reg));
f684960e
CW		 4870}
4871
439d7ac0
PB		 4872void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4873{
4874 struct drm_i915_private *dev_priv = dev->dev_private;
4875 struct intel_encoder *encoder;
4876 struct intel_dp *intel_dp = NULL;
4877 struct intel_crtc_config *config = NULL;
4878 struct intel_crtc *intel_crtc = NULL;
4879 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4880 u32 reg, val;
4881 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4882
4883 if (refresh_rate <= 0) {
4884 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4885 return;
4886 }
4887
4888 if (intel_connector == NULL) {
4889 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4890 return;
4891 }
4892
1fcc9d1c
DV		 4893 /*
4894 * FIXME: This needs proper synchronization with psr state. But really
4895 * hard to tell without seeing the user of this function of this code.
4896 * Check locking and ordering once that lands.
4897 */
439d7ac0
PB		 4898 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4899 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4900 return;
4901 }
4902
4903 encoder = intel_attached_encoder(&intel_connector->base);
4904 intel_dp = enc_to_intel_dp(&encoder->base);
4905 intel_crtc = encoder->new_crtc;
4906
4907 if (!intel_crtc) {
4908 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4909 return;
4910 }
4911
4912 config = &intel_crtc->config;
4913
4914 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4915 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4916 return;
4917 }
4918
4919 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4920 index = DRRS_LOW_RR;
4921
4922 if (index == intel_dp->drrs_state.refresh_rate_type) {
4923 DRM_DEBUG_KMS(
4924 "DRRS requested for previously set RR...ignoring\n");
4925 return;
4926 }
4927
4928 if (!intel_crtc->active) {
4929 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4930 return;
4931 }
4932
4933 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4934 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4935 val = I915_READ(reg);
4936 if (index > DRRS_HIGH_RR) {
4937 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4938 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4939 } else {
4940 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4941 }
4942 I915_WRITE(reg, val);
4943 }
4944
4945 /*
4946 * mutex taken to ensure that there is no race between differnt
4947 * drrs calls trying to update refresh rate. This scenario may occur
4948 * in future when idleness detection based DRRS in kernel and
4949 * possible calls from user space to set differnt RR are made.
4950 */
4951
4952 mutex_lock(&intel_dp->drrs_state.mutex);
4953
4954 intel_dp->drrs_state.refresh_rate_type = index;
4955
4956 mutex_unlock(&intel_dp->drrs_state.mutex);
4957
4958 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4959}
4960
4f9db5b5
PB		 4961static struct drm_display_mode *
4962intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4963 struct intel_connector *intel_connector,
4964 struct drm_display_mode *fixed_mode)
4965{
4966 struct drm_connector *connector = &intel_connector->base;
4967 struct intel_dp *intel_dp = &intel_dig_port->dp;
4968 struct drm_device *dev = intel_dig_port->base.base.dev;
4969 struct drm_i915_private *dev_priv = dev->dev_private;
4970 struct drm_display_mode *downclock_mode = NULL;
4971
4972 if (INTEL_INFO(dev)->gen <= 6) {
4973 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4974 return NULL;
4975 }
4976
4977 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4978 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4979 return NULL;
4980 }
4981
4982 downclock_mode = intel_find_panel_downclock
4983 (dev, fixed_mode, connector);
4984
4985 if (!downclock_mode) {
4079b8d1 4986 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4987 return NULL;
4988 }
4989
439d7ac0
PB		 4990 dev_priv->drrs.connector = intel_connector;
4991
4992 mutex_init(&intel_dp->drrs_state.mutex);
4993
4f9db5b5
PB		 4994 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4995
4996 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4997 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4998 return downclock_mode;
4999}
5000
aba86890
ID		 5001void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
5002{
5003 struct drm_device *dev = intel_encoder->base.dev;
5004 struct drm_i915_private *dev_priv = dev->dev_private;
5005 struct intel_dp *intel_dp;
5006 enum intel_display_power_domain power_domain;
5007
5008 if (intel_encoder->type != INTEL_OUTPUT_EDP)
5009 return;
5010
5011 intel_dp = enc_to_intel_dp(&intel_encoder->base);
773538e8
VS		 5012
5013 pps_lock(intel_dp);
5014
aba86890 5015 if (!edp_have_panel_vdd(intel_dp))
e39b999a 5016 goto out;
aba86890
ID		 5017 /*
5018 * The VDD bit needs a power domain reference, so if the bit is
5019 * already enabled when we boot or resume, grab this reference and
5020 * schedule a vdd off, so we don't hold on to the reference
5021 * indefinitely.
5022 */
5023 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5024 power_domain = intel_display_port_power_domain(intel_encoder);
5025 intel_display_power_get(dev_priv, power_domain);
5026
5027 edp_panel_vdd_schedule_off(intel_dp);
e39b999a 5028 out:
773538e8 5029 pps_unlock(intel_dp);
aba86890
ID		 5030}
5031
ed92f0b2 5032static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 5033 struct intel_connector *intel_connector,
5034 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 5035{
5036 struct drm_connector *connector = &intel_connector->base;
5037 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5038 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5039 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5040 struct drm_i915_private *dev_priv = dev->dev_private;
5041 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5042 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5043 bool has_dpcd;
5044 struct drm_display_mode *scan;
5045 struct edid *edid;
5046
4f9db5b5
PB		 5047 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
5048
ed92f0b2
PZ		 5049 if (!is_edp(intel_dp))
5050 return true;
5051
aba86890 5052 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 5053
ed92f0b2 5054 /* Cache DPCD and EDID for edp. */
24f3e092 5055 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 5056 has_dpcd = intel_dp_get_dpcd(intel_dp);
1e0560e0 5057 intel_edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 5058
5059 if (has_dpcd) {
5060 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5061 dev_priv->no_aux_handshake =
5062 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5063 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5064 } else {
5065 /* if this fails, presume the device is a ghost */
5066 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5067 return false;
5068 }
5069
5070 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5071 pps_lock(intel_dp);
0095e6dc 5072 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
773538e8 5073 pps_unlock(intel_dp);
ed92f0b2 5074
060c8778 5075 mutex_lock(&dev->mode_config.mutex);
0b99836f 5076 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5077 if (edid) {
5078 if (drm_add_edid_modes(connector, edid)) {
5079 drm_mode_connector_update_edid_property(connector,
5080 edid);
5081 drm_edid_to_eld(connector, edid);
5082 } else {
5083 kfree(edid);
5084 edid = ERR_PTR(-EINVAL);
5085 }
5086 } else {
5087 edid = ERR_PTR(-ENOENT);
5088 }
5089 intel_connector->edid = edid;
5090
5091 /* prefer fixed mode from EDID if available */
5092 list_for_each_entry(scan, &connector->probed_modes, head) {
5093 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5094 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 5095 downclock_mode = intel_dp_drrs_init(
5096 intel_dig_port,
5097 intel_connector, fixed_mode);
ed92f0b2
PZ		 5098 break;
5099 }
5100 }
5101
5102 /* fallback to VBT if available for eDP */
5103 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5104 fixed_mode = drm_mode_duplicate(dev,
5105 dev_priv->vbt.lfp_lvds_vbt_mode);
5106 if (fixed_mode)
5107 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5108 }
060c8778 5109 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5110
01527b31
CT		 5111 if (IS_VALLEYVIEW(dev)) {
5112 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5113 register_reboot_notifier(&intel_dp->edp_notifier);
5114 }
5115
4f9db5b5 5116 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5117 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 5118 intel_panel_setup_backlight(connector);
5119
5120 return true;
5121}
5122
16c25533 5123bool
f0fec3f2
PZ		 5124intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5125 struct intel_connector *intel_connector)
a4fc5ed6 5126{
f0fec3f2
PZ		 5127 struct drm_connector *connector = &intel_connector->base;
5128 struct intel_dp *intel_dp = &intel_dig_port->dp;
5129 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5130 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5131 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5132 enum port port = intel_dig_port->port;
0095e6dc 5133 struct edp_power_seq power_seq = { 0 };
0b99836f 5134 int type;
a4fc5ed6 5135
a4a5d2f8
VS		 5136 intel_dp->pps_pipe = INVALID_PIPE;
5137
ec5b01dd 5138 /* intel_dp vfuncs */
b6b5e383
DL		 5139 if (INTEL_INFO(dev)->gen >= 9)
5140 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5141 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5142 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5143 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5144 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5145 else if (HAS_PCH_SPLIT(dev))
5146 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5147 else
5148 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5149
b9ca5fad
DL		 5150 if (INTEL_INFO(dev)->gen >= 9)
5151 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5152 else
5153 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5154
0767935e
DV		 5155 /* Preserve the current hw state. */
5156 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5157 intel_dp->attached_connector = intel_connector;
3d3dc149 5158
3b32a35b 5159 if (intel_dp_is_edp(dev, port))
b329530c 5160 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5161 else
5162 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5163
f7d24902
ID		 5164 /*
5165 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5166 * for DP the encoder type can be set by the caller to
5167 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5168 */
5169 if (type == DRM_MODE_CONNECTOR_eDP)
5170 intel_encoder->type = INTEL_OUTPUT_EDP;
5171
e7281eab
ID		 5172 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5173 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5174 port_name(port));
5175
b329530c 5176 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5177 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5178
a4fc5ed6
KP		 5179 connector->interlace_allowed = true;
5180 connector->doublescan_allowed = 0;
5181
f0fec3f2 5182 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5183 edp_panel_vdd_work);
a4fc5ed6 5184
df0e9248 5185 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5186 drm_connector_register(connector);
a4fc5ed6 5187
affa9354 5188 if (HAS_DDI(dev))
bcbc889b
PZ		 5189 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5190 else
5191 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5192 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5193
0b99836f 5194 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5195 switch (port) {
5196 case PORT_A:
1d843f9d 5197 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5198 break;
5199 case PORT_B:
1d843f9d 5200 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5201 break;
5202 case PORT_C:
1d843f9d 5203 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5204 break;
5205 case PORT_D:
1d843f9d 5206 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5207 break;
5208 default:
ad1c0b19 5209 BUG();
5eb08b69
ZW		 5210 }
5211
dada1a9f 5212 if (is_edp(intel_dp)) {
773538e8 5213 pps_lock(intel_dp);
a4a5d2f8
VS		 5214 if (IS_VALLEYVIEW(dev)) {
5215 vlv_initial_power_sequencer_setup(intel_dp);
5216 } else {
5217 intel_dp_init_panel_power_timestamps(intel_dp);
5218 intel_dp_init_panel_power_sequencer(dev, intel_dp,
5219 &power_seq);
5220 }
773538e8 5221 pps_unlock(intel_dp);
dada1a9f 5222 }
0095e6dc 5223
9d1a1031 5224 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5225
0e32b39c
DA		 5226 /* init MST on ports that can support it */
5227 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5228 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5229 intel_dp_mst_encoder_init(intel_dig_port,
5230 intel_connector->base.base.id);
0e32b39c
DA		 5231 }
5232 }
5233
0095e6dc 5234 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 5235 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5236 if (is_edp(intel_dp)) {
5237 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5238 /*
5239 * vdd might still be enabled do to the delayed vdd off.
5240 * Make sure vdd is actually turned off here.
5241 */
773538e8 5242 pps_lock(intel_dp);
4be73780 5243 edp_panel_vdd_off_sync(intel_dp);
773538e8 5244 pps_unlock(intel_dp);
15b1d171 5245 }
34ea3d38 5246 drm_connector_unregister(connector);
b2f246a8 5247 drm_connector_cleanup(connector);
16c25533 5248 return false;
b2f246a8 5249 }
32f9d658 5250
f684960e
CW		 5251 intel_dp_add_properties(intel_dp, connector);
5252
a4fc5ed6
KP		 5253 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5254 * 0xd. Failure to do so will result in spurious interrupts being
5255 * generated on the port when a cable is not attached.
5256 */
5257 if (IS_G4X(dev) && !IS_GM45(dev)) {
5258 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5259 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5260 }
16c25533
PZ		 5261
5262 return true;
a4fc5ed6 5263}
f0fec3f2
PZ		 5264
5265void
5266intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5267{
13cf5504 5268 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5269 struct intel_digital_port *intel_dig_port;
5270 struct intel_encoder *intel_encoder;
5271 struct drm_encoder *encoder;
5272 struct intel_connector *intel_connector;
5273
b14c5679 5274 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5275 if (!intel_dig_port)
5276 return;
5277
b14c5679 5278 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5279 if (!intel_connector) {
5280 kfree(intel_dig_port);
5281 return;
5282 }
5283
5284 intel_encoder = &intel_dig_port->base;
5285 encoder = &intel_encoder->base;
5286
5287 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5288 DRM_MODE_ENCODER_TMDS);
5289
5bfe2ac0 5290 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5291 intel_encoder->disable = intel_disable_dp;
00c09d70 5292 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5293 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5294 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5295 if (IS_CHERRYVIEW(dev)) {
9197c88b 5296 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5297 intel_encoder->pre_enable = chv_pre_enable_dp;
5298 intel_encoder->enable = vlv_enable_dp;
580d3811 5299 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5300 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5301 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5302 intel_encoder->pre_enable = vlv_pre_enable_dp;
5303 intel_encoder->enable = vlv_enable_dp;
49277c31 5304 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5305 } else {
ecff4f3b
JN		 5306 intel_encoder->pre_enable = g4x_pre_enable_dp;
5307 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5308 if (INTEL_INFO(dev)->gen >= 5)
5309 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5310 }
f0fec3f2 5311
174edf1f 5312 intel_dig_port->port = port;
f0fec3f2
PZ		 5313 intel_dig_port->dp.output_reg = output_reg;
5314
00c09d70 5315 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5316 if (IS_CHERRYVIEW(dev)) {
5317 if (port == PORT_D)
5318 intel_encoder->crtc_mask = 1 << 2;
5319 else
5320 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5321 } else {
5322 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5323 }
bc079e8b 5324 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5325 intel_encoder->hot_plug = intel_dp_hot_plug;
5326
13cf5504
DA		 5327 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5328 dev_priv->hpd_irq_port[port] = intel_dig_port;
5329
15b1d171
PZ		 5330 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5331 drm_encoder_cleanup(encoder);
5332 kfree(intel_dig_port);
b2f246a8 5333 kfree(intel_connector);
15b1d171 5334 }
f0fec3f2 5335}
0e32b39c
DA		 5336
5337void intel_dp_mst_suspend(struct drm_device *dev)
5338{
5339 struct drm_i915_private *dev_priv = dev->dev_private;
5340 int i;
5341
5342 /* disable MST */
5343 for (i = 0; i < I915_MAX_PORTS; i++) {
5344 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5345 if (!intel_dig_port)
5346 continue;
5347
5348 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5349 if (!intel_dig_port->dp.can_mst)
5350 continue;
5351 if (intel_dig_port->dp.is_mst)
5352 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5353 }
5354 }
5355}
5356
5357void intel_dp_mst_resume(struct drm_device *dev)
5358{
5359 struct drm_i915_private *dev_priv = dev->dev_private;
5360 int i;
5361
5362 for (i = 0; i < I915_MAX_PORTS; i++) {
5363 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5364 if (!intel_dig_port)
5365 continue;
5366 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5367 int ret;
5368
5369 if (!intel_dig_port->dp.can_mst)
5370 continue;
5371
5372 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5373 if (ret != 0) {
5374 intel_dp_check_mst_status(&intel_dig_port->dp);
5375 }
5376 }
5377 }
5378}
Linux kernel - Deliverables
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