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drm/i915: Kick the power sequencer before AUX transactions
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 116static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a4fc5ed6 117
0e32b39c 118int
ea5b213a 119intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 120{
7183dc29 121 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 122 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 123
124 switch (max_link_bw) {
125 case DP_LINK_BW_1_62:
126 case DP_LINK_BW_2_7:
127 break;
d4eead50 128 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 129 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
130 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 131 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
132 max_link_bw = DP_LINK_BW_5_4;
133 else
134 max_link_bw = DP_LINK_BW_2_7;
d4eead50 135 break;
a4fc5ed6 136 default:
d4eead50
ID		 137 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
138 max_link_bw);
a4fc5ed6
KP		 139 max_link_bw = DP_LINK_BW_1_62;
140 break;
141 }
142 return max_link_bw;
143}
144
eeb6324d
PZ		 145static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
146{
147 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
148 struct drm_device *dev = intel_dig_port->base.base.dev;
149 u8 source_max, sink_max;
150
151 source_max = 4;
152 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
153 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
154 source_max = 2;
155
156 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
157
158 return min(source_max, sink_max);
159}
160
cd9dde44
AJ		 161/*
162 * The units on the numbers in the next two are... bizarre. Examples will
163 * make it clearer; this one parallels an example in the eDP spec.
164 *
165 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
166 *
167 * 270000 * 1 * 8 / 10 == 216000
168 *
169 * The actual data capacity of that configuration is 2.16Gbit/s, so the
170 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
171 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
172 * 119000. At 18bpp that's 2142000 kilobits per second.
173 *
174 * Thus the strange-looking division by 10 in intel_dp_link_required, to
175 * get the result in decakilobits instead of kilobits.
176 */
177
a4fc5ed6 178static int
c898261c 179intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 180{
cd9dde44 181 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 182}
183
fe27d53e
DA		 184static int
185intel_dp_max_data_rate(int max_link_clock, int max_lanes)
186{
187 return (max_link_clock * max_lanes * 8) / 10;
188}
189
c19de8eb 190static enum drm_mode_status
a4fc5ed6
KP		 191intel_dp_mode_valid(struct drm_connector *connector,
192 struct drm_display_mode *mode)
193{
df0e9248 194 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 195 struct intel_connector *intel_connector = to_intel_connector(connector);
196 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 197 int target_clock = mode->clock;
198 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 199
dd06f90e
JN		 200 if (is_edp(intel_dp) && fixed_mode) {
201 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 202 return MODE_PANEL;
203
dd06f90e 204 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 205 return MODE_PANEL;
03afc4a2
DV		 206
207 target_clock = fixed_mode->clock;
7de56f43
ZY		 208 }
209
36008365 210 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 211 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 212
213 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
214 mode_rate = intel_dp_link_required(target_clock, 18);
215
216 if (mode_rate > max_rate)
c4867936 217 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 218
219 if (mode->clock < 10000)
220 return MODE_CLOCK_LOW;
221
0af78a2b
DV		 222 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
223 return MODE_H_ILLEGAL;
224
a4fc5ed6
KP		 225 return MODE_OK;
226}
227
228static uint32_t
5ca476f8 229pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 230{
231 int i;
232 uint32_t v = 0;
233
234 if (src_bytes > 4)
235 src_bytes = 4;
236 for (i = 0; i < src_bytes; i++)
237 v |= ((uint32_t) src[i]) << ((3-i) * 8);
238 return v;
239}
240
241static void
242unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
243{
244 int i;
245 if (dst_bytes > 4)
246 dst_bytes = 4;
247 for (i = 0; i < dst_bytes; i++)
248 dst[i] = src >> ((3-i) * 8);
249}
250
fb0f8fbf
KP		 251/* hrawclock is 1/4 the FSB frequency */
252static int
253intel_hrawclk(struct drm_device *dev)
254{
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 uint32_t clkcfg;
257
9473c8f4
VP		 258 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
259 if (IS_VALLEYVIEW(dev))
260 return 200;
261
fb0f8fbf
KP		 262 clkcfg = I915_READ(CLKCFG);
263 switch (clkcfg & CLKCFG_FSB_MASK) {
264 case CLKCFG_FSB_400:
265 return 100;
266 case CLKCFG_FSB_533:
267 return 133;
268 case CLKCFG_FSB_667:
269 return 166;
270 case CLKCFG_FSB_800:
271 return 200;
272 case CLKCFG_FSB_1067:
273 return 266;
274 case CLKCFG_FSB_1333:
275 return 333;
276 /* these two are just a guess; one of them might be right */
277 case CLKCFG_FSB_1600:
278 case CLKCFG_FSB_1600_ALT:
279 return 400;
280 default:
281 return 133;
282 }
283}
284
bf13e81b
JN		 285static void
286intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 287 struct intel_dp *intel_dp);
bf13e81b
JN		 288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 290 struct intel_dp *intel_dp);
bf13e81b 291
773538e8
VS		 292static void pps_lock(struct intel_dp *intel_dp)
293{
294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295 struct intel_encoder *encoder = &intel_dig_port->base;
296 struct drm_device *dev = encoder->base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum intel_display_power_domain power_domain;
299
300 /*
301 * See vlv_power_sequencer_reset() why we need
302 * a power domain reference here.
303 */
304 power_domain = intel_display_port_power_domain(encoder);
305 intel_display_power_get(dev_priv, power_domain);
306
307 mutex_lock(&dev_priv->pps_mutex);
308}
309
310static void pps_unlock(struct intel_dp *intel_dp)
311{
312 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
313 struct intel_encoder *encoder = &intel_dig_port->base;
314 struct drm_device *dev = encoder->base.dev;
315 struct drm_i915_private *dev_priv = dev->dev_private;
316 enum intel_display_power_domain power_domain;
317
318 mutex_unlock(&dev_priv->pps_mutex);
319
320 power_domain = intel_display_port_power_domain(encoder);
321 intel_display_power_put(dev_priv, power_domain);
322}
323
961a0db0
VS		 324static void
325vlv_power_sequencer_kick(struct intel_dp *intel_dp)
326{
327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
328 struct drm_device *dev = intel_dig_port->base.base.dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
330 enum pipe pipe = intel_dp->pps_pipe;
331 uint32_t DP;
332
333 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
334 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
335 pipe_name(pipe), port_name(intel_dig_port->port)))
336 return;
337
338 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
339 pipe_name(pipe), port_name(intel_dig_port->port));
340
341 /* Preserve the BIOS-computed detected bit. This is
342 * supposed to be read-only.
343 */
344 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
345 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
346 DP |= DP_PORT_WIDTH(1);
347 DP |= DP_LINK_TRAIN_PAT_1;
348
349 if (IS_CHERRYVIEW(dev))
350 DP |= DP_PIPE_SELECT_CHV(pipe);
351 else if (pipe == PIPE_B)
352 DP |= DP_PIPEB_SELECT;
353
354 /*
355 * Similar magic as in intel_dp_enable_port().
356 * We _must_ do this port enable + disable trick
357 * to make this power seqeuencer lock onto the port.
358 * Otherwise even VDD force bit won't work.
359 */
360 I915_WRITE(intel_dp->output_reg, DP);
361 POSTING_READ(intel_dp->output_reg);
362
363 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
364 POSTING_READ(intel_dp->output_reg);
365
366 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
367 POSTING_READ(intel_dp->output_reg);
368}
369
bf13e81b
JN		 370static enum pipe
371vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
372{
373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 374 struct drm_device *dev = intel_dig_port->base.base.dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 376 struct intel_encoder *encoder;
377 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
bf13e81b 378
e39b999a 379 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 380
a4a5d2f8
VS		 381 if (intel_dp->pps_pipe != INVALID_PIPE)
382 return intel_dp->pps_pipe;
383
384 /*
385 * We don't have power sequencer currently.
386 * Pick one that's not used by other ports.
387 */
388 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
389 base.head) {
390 struct intel_dp *tmp;
391
392 if (encoder->type != INTEL_OUTPUT_EDP)
393 continue;
394
395 tmp = enc_to_intel_dp(&encoder->base);
396
397 if (tmp->pps_pipe != INVALID_PIPE)
398 pipes &= ~(1 << tmp->pps_pipe);
399 }
400
401 /*
402 * Didn't find one. This should not happen since there
403 * are two power sequencers and up to two eDP ports.
404 */
405 if (WARN_ON(pipes == 0))
406 return PIPE_A;
407
408 intel_dp->pps_pipe = ffs(pipes) - 1;
409
410 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
411 pipe_name(intel_dp->pps_pipe),
412 port_name(intel_dig_port->port));
413
414 /* init power sequencer on this pipe and port */
36b5f425
VS		 415 intel_dp_init_panel_power_sequencer(dev, intel_dp);
416 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 417
961a0db0
VS		 418 /*
419 * Even vdd force doesn't work until we've made
420 * the power sequencer lock in on the port.
421 */
422 vlv_power_sequencer_kick(intel_dp);
423
a4a5d2f8
VS		 424 return intel_dp->pps_pipe;
425}
426
6491ab27
VS		 427typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
428 enum pipe pipe);
429
430static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
431 enum pipe pipe)
432{
433 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
434}
435
436static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
437 enum pipe pipe)
438{
439 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
440}
441
442static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
443 enum pipe pipe)
444{
445 return true;
446}
bf13e81b 447
a4a5d2f8 448static enum pipe
6491ab27
VS		 449vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
450 enum port port,
451 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 452{
453 enum pipe pipe;
bf13e81b 454
bf13e81b
JN		 455 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
456 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
457 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 458
459 if (port_sel != PANEL_PORT_SELECT_VLV(port))
460 continue;
461
6491ab27
VS		 462 if (!pipe_check(dev_priv, pipe))
463 continue;
464
a4a5d2f8 465 return pipe;
bf13e81b
JN		 466 }
467
a4a5d2f8
VS		 468 return INVALID_PIPE;
469}
470
471static void
472vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
473{
474 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
475 struct drm_device *dev = intel_dig_port->base.base.dev;
476 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 477 enum port port = intel_dig_port->port;
478
479 lockdep_assert_held(&dev_priv->pps_mutex);
480
481 /* try to find a pipe with this port selected */
6491ab27
VS		 482 /* first pick one where the panel is on */
483 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
484 vlv_pipe_has_pp_on);
485 /* didn't find one? pick one where vdd is on */
486 if (intel_dp->pps_pipe == INVALID_PIPE)
487 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
488 vlv_pipe_has_vdd_on);
489 /* didn't find one? pick one with just the correct port */
490 if (intel_dp->pps_pipe == INVALID_PIPE)
491 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
492 vlv_pipe_any);
a4a5d2f8
VS		 493
494 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
495 if (intel_dp->pps_pipe == INVALID_PIPE) {
496 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
497 port_name(port));
498 return;
bf13e81b
JN		 499 }
500
a4a5d2f8
VS		 501 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
502 port_name(port), pipe_name(intel_dp->pps_pipe));
503
36b5f425
VS		 504 intel_dp_init_panel_power_sequencer(dev, intel_dp);
505 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 506}
507
773538e8
VS		 508void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
509{
510 struct drm_device *dev = dev_priv->dev;
511 struct intel_encoder *encoder;
512
513 if (WARN_ON(!IS_VALLEYVIEW(dev)))
514 return;
515
516 /*
517 * We can't grab pps_mutex here due to deadlock with power_domain
518 * mutex when power_domain functions are called while holding pps_mutex.
519 * That also means that in order to use pps_pipe the code needs to
520 * hold both a power domain reference and pps_mutex, and the power domain
521 * reference get/put must be done while _not_ holding pps_mutex.
522 * pps_{lock,unlock}() do these steps in the correct order, so one
523 * should use them always.
524 */
525
526 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
527 struct intel_dp *intel_dp;
528
529 if (encoder->type != INTEL_OUTPUT_EDP)
530 continue;
531
532 intel_dp = enc_to_intel_dp(&encoder->base);
533 intel_dp->pps_pipe = INVALID_PIPE;
534 }
bf13e81b
JN		 535}
536
537static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
538{
539 struct drm_device *dev = intel_dp_to_dev(intel_dp);
540
541 if (HAS_PCH_SPLIT(dev))
542 return PCH_PP_CONTROL;
543 else
544 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
545}
546
547static u32 _pp_stat_reg(struct intel_dp *intel_dp)
548{
549 struct drm_device *dev = intel_dp_to_dev(intel_dp);
550
551 if (HAS_PCH_SPLIT(dev))
552 return PCH_PP_STATUS;
553 else
554 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
555}
556
01527b31
CT		 557/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
558 This function only applicable when panel PM state is not to be tracked */
559static int edp_notify_handler(struct notifier_block *this, unsigned long code,
560 void *unused)
561{
562 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
563 edp_notifier);
564 struct drm_device *dev = intel_dp_to_dev(intel_dp);
565 struct drm_i915_private *dev_priv = dev->dev_private;
566 u32 pp_div;
567 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 568
569 if (!is_edp(intel_dp) || code != SYS_RESTART)
570 return 0;
571
773538e8 572 pps_lock(intel_dp);
e39b999a 573
01527b31 574 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 575 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
576
01527b31
CT		 577 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
578 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
579 pp_div = I915_READ(pp_div_reg);
580 pp_div &= PP_REFERENCE_DIVIDER_MASK;
581
582 /* 0x1F write to PP_DIV_REG sets max cycle delay */
583 I915_WRITE(pp_div_reg, pp_div | 0x1F);
584 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
585 msleep(intel_dp->panel_power_cycle_delay);
586 }
587
773538e8 588 pps_unlock(intel_dp);
e39b999a 589
01527b31
CT		 590 return 0;
591}
592
4be73780 593static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 594{
30add22d 595 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 596 struct drm_i915_private *dev_priv = dev->dev_private;
597
e39b999a
VS		 598 lockdep_assert_held(&dev_priv->pps_mutex);
599
bf13e81b 600 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 601}
602
4be73780 603static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 604{
30add22d 605 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 606 struct drm_i915_private *dev_priv = dev->dev_private;
607
e39b999a
VS		 608 lockdep_assert_held(&dev_priv->pps_mutex);
609
773538e8 610 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 611}
612
9b984dae
KP		 613static void
614intel_dp_check_edp(struct intel_dp *intel_dp)
615{
30add22d 616 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 617 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 618
9b984dae
KP		 619 if (!is_edp(intel_dp))
620 return;
453c5420 621
4be73780 622 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 623 WARN(1, "eDP powered off while attempting aux channel communication.\n");
624 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 625 I915_READ(_pp_stat_reg(intel_dp)),
626 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 627 }
628}
629
9ee32fea
DV		 630static uint32_t
631intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
632{
633 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
634 struct drm_device *dev = intel_dig_port->base.base.dev;
635 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 636 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 637 uint32_t status;
638 bool done;
639
ef04f00d 640#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 641 if (has_aux_irq)
b18ac466 642 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 643 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 644 else
645 done = wait_for_atomic(C, 10) == 0;
646 if (!done)
647 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
648 has_aux_irq);
649#undef C
650
651 return status;
652}
653
ec5b01dd 654static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 655{
174edf1f
PZ		 656 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
657 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 658
ec5b01dd
DL		 659 /*
660 * The clock divider is based off the hrawclk, and would like to run at
661 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 662 */
ec5b01dd
DL		 663 return index ? 0 : intel_hrawclk(dev) / 2;
664}
665
666static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
667{
668 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
669 struct drm_device *dev = intel_dig_port->base.base.dev;
670
671 if (index)
672 return 0;
673
674 if (intel_dig_port->port == PORT_A) {
675 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 676 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 677 else
b84a1cf8 678 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 679 } else {
680 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
681 }
682}
683
684static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
685{
686 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
687 struct drm_device *dev = intel_dig_port->base.base.dev;
688 struct drm_i915_private *dev_priv = dev->dev_private;
689
690 if (intel_dig_port->port == PORT_A) {
691 if (index)
692 return 0;
693 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 694 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
695 /* Workaround for non-ULT HSW */
bc86625a
CW		 696 switch (index) {
697 case 0: return 63;
698 case 1: return 72;
699 default: return 0;
700 }
ec5b01dd 701 } else {
bc86625a 702 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 703 }
b84a1cf8
RV		 704}
705
ec5b01dd
DL		 706static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
707{
708 return index ? 0 : 100;
709}
710
b6b5e383
DL		 711static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
712{
713 /*
714 * SKL doesn't need us to program the AUX clock divider (Hardware will
715 * derive the clock from CDCLK automatically). We still implement the
716 * get_aux_clock_divider vfunc to plug-in into the existing code.
717 */
718 return index ? 0 : 1;
719}
720
5ed12a19
DL		 721static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
722 bool has_aux_irq,
723 int send_bytes,
724 uint32_t aux_clock_divider)
725{
726 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
727 struct drm_device *dev = intel_dig_port->base.base.dev;
728 uint32_t precharge, timeout;
729
730 if (IS_GEN6(dev))
731 precharge = 3;
732 else
733 precharge = 5;
734
735 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
736 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
737 else
738 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
739
740 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 741 DP_AUX_CH_CTL_DONE |
5ed12a19 742 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 743 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 744 timeout |
788d4433 745 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 746 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
747 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 748 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 749}
750
b9ca5fad
DL		 751static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
752 bool has_aux_irq,
753 int send_bytes,
754 uint32_t unused)
755{
756 return DP_AUX_CH_CTL_SEND_BUSY |
757 DP_AUX_CH_CTL_DONE |
758 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
759 DP_AUX_CH_CTL_TIME_OUT_ERROR |
760 DP_AUX_CH_CTL_TIME_OUT_1600us |
761 DP_AUX_CH_CTL_RECEIVE_ERROR |
762 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
763 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
764}
765
b84a1cf8
RV		 766static int
767intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 768 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 769 uint8_t *recv, int recv_size)
770{
771 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
772 struct drm_device *dev = intel_dig_port->base.base.dev;
773 struct drm_i915_private *dev_priv = dev->dev_private;
774 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
775 uint32_t ch_data = ch_ctl + 4;
bc86625a 776 uint32_t aux_clock_divider;
b84a1cf8
RV		 777 int i, ret, recv_bytes;
778 uint32_t status;
5ed12a19 779 int try, clock = 0;
4e6b788c 780 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 781 bool vdd;
782
773538e8 783 pps_lock(intel_dp);
e39b999a 784
72c3500a
VS		 785 /*
786 * We will be called with VDD already enabled for dpcd/edid/oui reads.
787 * In such cases we want to leave VDD enabled and it's up to upper layers
788 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
789 * ourselves.
790 */
1e0560e0 791 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 792
793 /* dp aux is extremely sensitive to irq latency, hence request the
794 * lowest possible wakeup latency and so prevent the cpu from going into
795 * deep sleep states.
796 */
797 pm_qos_update_request(&dev_priv->pm_qos, 0);
798
799 intel_dp_check_edp(intel_dp);
5eb08b69 800
c67a470b
PZ		 801 intel_aux_display_runtime_get(dev_priv);
802
11bee43e
JB		 803 /* Try to wait for any previous AUX channel activity */
804 for (try = 0; try < 3; try++) {
ef04f00d 805 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 806 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
807 break;
808 msleep(1);
809 }
810
811 if (try == 3) {
812 WARN(1, "dp_aux_ch not started status 0x%08x\n",
813 I915_READ(ch_ctl));
9ee32fea
DV		 814 ret = -EBUSY;
815 goto out;
4f7f7b7e
CW		 816 }
817
46a5ae9f
PZ		 818 /* Only 5 data registers! */
819 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
820 ret = -E2BIG;
821 goto out;
822 }
823
ec5b01dd 824 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 825 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
826 has_aux_irq,
827 send_bytes,
828 aux_clock_divider);
5ed12a19 829
bc86625a
CW		 830 /* Must try at least 3 times according to DP spec */
831 for (try = 0; try < 5; try++) {
832 /* Load the send data into the aux channel data registers */
833 for (i = 0; i < send_bytes; i += 4)
834 I915_WRITE(ch_data + i,
835 pack_aux(send + i, send_bytes - i));
836
837 /* Send the command and wait for it to complete */
5ed12a19 838 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 839
840 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
841
842 /* Clear done status and any errors */
843 I915_WRITE(ch_ctl,
844 status |
845 DP_AUX_CH_CTL_DONE |
846 DP_AUX_CH_CTL_TIME_OUT_ERROR |
847 DP_AUX_CH_CTL_RECEIVE_ERROR);
848
849 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
850 DP_AUX_CH_CTL_RECEIVE_ERROR))
851 continue;
852 if (status & DP_AUX_CH_CTL_DONE)
853 break;
854 }
4f7f7b7e 855 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 856 break;
857 }
858
a4fc5ed6 859 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 860 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 861 ret = -EBUSY;
862 goto out;
a4fc5ed6
KP		 863 }
864
865 /* Check for timeout or receive error.
866 * Timeouts occur when the sink is not connected
867 */
a5b3da54 868 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 869 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 870 ret = -EIO;
871 goto out;
a5b3da54 872 }
1ae8c0a5
KP		 873
874 /* Timeouts occur when the device isn't connected, so they're
875 * "normal" -- don't fill the kernel log with these */
a5b3da54 876 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 877 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 878 ret = -ETIMEDOUT;
879 goto out;
a4fc5ed6
KP		 880 }
881
882 /* Unload any bytes sent back from the other side */
883 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
884 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 885 if (recv_bytes > recv_size)
886 recv_bytes = recv_size;
0206e353 887
4f7f7b7e
CW		 888 for (i = 0; i < recv_bytes; i += 4)
889 unpack_aux(I915_READ(ch_data + i),
890 recv + i, recv_bytes - i);
a4fc5ed6 891
9ee32fea
DV		 892 ret = recv_bytes;
893out:
894 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 895 intel_aux_display_runtime_put(dev_priv);
9ee32fea 896
884f19e9
JN		 897 if (vdd)
898 edp_panel_vdd_off(intel_dp, false);
899
773538e8 900 pps_unlock(intel_dp);
e39b999a 901
9ee32fea 902 return ret;
a4fc5ed6
KP		 903}
904
a6c8aff0
JN		 905#define BARE_ADDRESS_SIZE 3
906#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 907static ssize_t
908intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 909{
9d1a1031
JN		 910 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
911 uint8_t txbuf[20], rxbuf[20];
912 size_t txsize, rxsize;
a4fc5ed6 913 int ret;
a4fc5ed6 914
9d1a1031
JN		 915 txbuf[0] = msg->request << 4;
916 txbuf[1] = msg->address >> 8;
917 txbuf[2] = msg->address & 0xff;
918 txbuf[3] = msg->size - 1;
46a5ae9f 919
9d1a1031
JN		 920 switch (msg->request & ~DP_AUX_I2C_MOT) {
921 case DP_AUX_NATIVE_WRITE:
922 case DP_AUX_I2C_WRITE:
a6c8aff0 923 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 924 rxsize = 1;
f51a44b9 925
9d1a1031
JN		 926 if (WARN_ON(txsize > 20))
927 return -E2BIG;
a4fc5ed6 928
9d1a1031 929 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 930
9d1a1031
JN		 931 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
932 if (ret > 0) {
933 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 934
9d1a1031
JN		 935 /* Return payload size. */
936 ret = msg->size;
937 }
938 break;
46a5ae9f 939
9d1a1031
JN		 940 case DP_AUX_NATIVE_READ:
941 case DP_AUX_I2C_READ:
a6c8aff0 942 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 943 rxsize = msg->size + 1;
a4fc5ed6 944
9d1a1031
JN		 945 if (WARN_ON(rxsize > 20))
946 return -E2BIG;
a4fc5ed6 947
9d1a1031
JN		 948 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
949 if (ret > 0) {
950 msg->reply = rxbuf[0] >> 4;
951 /*
952 * Assume happy day, and copy the data. The caller is
953 * expected to check msg->reply before touching it.
954 *
955 * Return payload size.
956 */
957 ret--;
958 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 959 }
9d1a1031
JN		 960 break;
961
962 default:
963 ret = -EINVAL;
964 break;
a4fc5ed6 965 }
f51a44b9 966
9d1a1031 967 return ret;
a4fc5ed6
KP		 968}
969
9d1a1031
JN		 970static void
971intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
972{
973 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 974 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
975 enum port port = intel_dig_port->port;
0b99836f 976 const char *name = NULL;
ab2c0672
DA		 977 int ret;
978
33ad6626
JN		 979 switch (port) {
980 case PORT_A:
981 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 982 name = "DPDDC-A";
ab2c0672 983 break;
33ad6626
JN		 984 case PORT_B:
985 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 986 name = "DPDDC-B";
ab2c0672 987 break;
33ad6626
JN		 988 case PORT_C:
989 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 990 name = "DPDDC-C";
ab2c0672 991 break;
33ad6626
JN		 992 case PORT_D:
993 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 994 name = "DPDDC-D";
33ad6626
JN		 995 break;
996 default:
997 BUG();
ab2c0672
DA		 998 }
999
1b1aad75
DL		 1000 /*
1001 * The AUX_CTL register is usually DP_CTL + 0x10.
1002 *
1003 * On Haswell and Broadwell though:
1004 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1005 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1006 *
1007 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1008 */
1009 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 1010 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1011
0b99836f 1012 intel_dp->aux.name = name;
9d1a1031
JN		 1013 intel_dp->aux.dev = dev->dev;
1014 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1015
0b99836f
JN		 1016 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1017 connector->base.kdev->kobj.name);
8316f337 1018
4f71d0cb 1019 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1020 if (ret < 0) {
4f71d0cb 1021 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1022 name, ret);
1023 return;
ab2c0672 1024 }
8a5e6aeb 1025
0b99836f
JN		 1026 ret = sysfs_create_link(&connector->base.kdev->kobj,
1027 &intel_dp->aux.ddc.dev.kobj,
1028 intel_dp->aux.ddc.dev.kobj.name);
1029 if (ret < 0) {
1030 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1031 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1032 }
a4fc5ed6
KP		 1033}
1034
80f65de3
ID		 1035static void
1036intel_dp_connector_unregister(struct intel_connector *intel_connector)
1037{
1038 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1039
0e32b39c
DA		 1040 if (!intel_connector->mst_port)
1041 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1042 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1043 intel_connector_unregister(intel_connector);
1044}
1045
0e50338c
DV		 1046static void
1047hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
1048{
1049 switch (link_bw) {
1050 case DP_LINK_BW_1_62:
1051 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1052 break;
1053 case DP_LINK_BW_2_7:
1054 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1055 break;
1056 case DP_LINK_BW_5_4:
1057 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1058 break;
1059 }
1060}
1061
c6bb3538
DV		 1062static void
1063intel_dp_set_clock(struct intel_encoder *encoder,
1064 struct intel_crtc_config *pipe_config, int link_bw)
1065{
1066 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1067 const struct dp_link_dpll *divisor = NULL;
1068 int i, count = 0;
c6bb3538
DV		 1069
1070 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1071 divisor = gen4_dpll;
1072 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1073 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1074 divisor = pch_dpll;
1075 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1076 } else if (IS_CHERRYVIEW(dev)) {
1077 divisor = chv_dpll;
1078 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1079 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1080 divisor = vlv_dpll;
1081 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1082 }
9dd4ffdf
CML		 1083
1084 if (divisor && count) {
1085 for (i = 0; i < count; i++) {
1086 if (link_bw == divisor[i].link_bw) {
1087 pipe_config->dpll = divisor[i].dpll;
1088 pipe_config->clock_set = true;
1089 break;
1090 }
1091 }
c6bb3538
DV		 1092 }
1093}
1094
00c09d70 1095bool
5bfe2ac0
DV		 1096intel_dp_compute_config(struct intel_encoder *encoder,
1097 struct intel_crtc_config *pipe_config)
a4fc5ed6 1098{
5bfe2ac0 1099 struct drm_device *dev = encoder->base.dev;
36008365 1100 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1101 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1102 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1103 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1104 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1105 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1106 int lane_count, clock;
56071a20 1107 int min_lane_count = 1;
eeb6324d 1108 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1109 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1110 int min_clock = 0;
06ea66b6 1111 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1112 int bpp, mode_rate;
06ea66b6 1113 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1114 int link_avail, link_clock;
a4fc5ed6 1115
bc7d38a4 1116 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1117 pipe_config->has_pch_encoder = true;
1118
03afc4a2 1119 pipe_config->has_dp_encoder = true;
f769cd24 1120 pipe_config->has_drrs = false;
9ed109a7 1121 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1122
dd06f90e
JN		 1123 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1124 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1125 adjusted_mode);
2dd24552
JB		 1126 if (!HAS_PCH_SPLIT(dev))
1127 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1128 intel_connector->panel.fitting_mode);
1129 else
b074cec8
JB		 1130 intel_pch_panel_fitting(intel_crtc, pipe_config,
1131 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1132 }
1133
cb1793ce 1134 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1135 return false;
1136
083f9560
DV		 1137 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1138 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1139 max_lane_count, bws[max_clock],
1140 adjusted_mode->crtc_clock);
083f9560 1141
36008365
DV		 1142 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1143 * bpc in between. */
3e7ca985 1144 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1145 if (is_edp(intel_dp)) {
1146 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1147 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1148 dev_priv->vbt.edp_bpp);
1149 bpp = dev_priv->vbt.edp_bpp;
1150 }
1151
344c5bbc
JN		 1152 /*
1153 * Use the maximum clock and number of lanes the eDP panel
1154 * advertizes being capable of. The panels are generally
1155 * designed to support only a single clock and lane
1156 * configuration, and typically these values correspond to the
1157 * native resolution of the panel.
1158 */
1159 min_lane_count = max_lane_count;
1160 min_clock = max_clock;
7984211e 1161 }
657445fe 1162
36008365 1163 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1164 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1165 bpp);
36008365 1166
c6930992
DA		 1167 for (clock = min_clock; clock <= max_clock; clock++) {
1168 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1169 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1170 link_avail = intel_dp_max_data_rate(link_clock,
1171 lane_count);
1172
1173 if (mode_rate <= link_avail) {
1174 goto found;
1175 }
1176 }
1177 }
1178 }
c4867936 1179
36008365 1180 return false;
3685a8f3 1181
36008365 1182found:
55bc60db
VS		 1183 if (intel_dp->color_range_auto) {
1184 /*
1185 * See:
1186 * CEA-861-E - 5.1 Default Encoding Parameters
1187 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1188 */
18316c8c 1189 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1190 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1191 else
1192 intel_dp->color_range = 0;
1193 }
1194
3685a8f3 1195 if (intel_dp->color_range)
50f3b016 1196 pipe_config->limited_color_range = true;
a4fc5ed6 1197
36008365
DV		 1198 intel_dp->link_bw = bws[clock];
1199 intel_dp->lane_count = lane_count;
657445fe 1200 pipe_config->pipe_bpp = bpp;
ff9a6750 1201 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1202
36008365
DV		 1203 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1204 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1205 pipe_config->port_clock, bpp);
36008365
DV		 1206 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1207 mode_rate, link_avail);
a4fc5ed6 1208
03afc4a2 1209 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1210 adjusted_mode->crtc_clock,
1211 pipe_config->port_clock,
03afc4a2 1212 &pipe_config->dp_m_n);
9d1a455b 1213
439d7ac0
PB		 1214 if (intel_connector->panel.downclock_mode != NULL &&
1215 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1216 pipe_config->has_drrs = true;
439d7ac0
PB		 1217 intel_link_compute_m_n(bpp, lane_count,
1218 intel_connector->panel.downclock_mode->clock,
1219 pipe_config->port_clock,
1220 &pipe_config->dp_m2_n2);
1221 }
1222
ea155f32 1223 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1224 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1225 else
1226 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1227
03afc4a2 1228 return true;
a4fc5ed6
KP		 1229}
1230
7c62a164 1231static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1232{
7c62a164
DV		 1233 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1234 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1235 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1236 struct drm_i915_private *dev_priv = dev->dev_private;
1237 u32 dpa_ctl;
1238
ff9a6750 1239 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1240 dpa_ctl = I915_READ(DP_A);
1241 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1242
ff9a6750 1243 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1244 /* For a long time we've carried around a ILK-DevA w/a for the
1245 * 160MHz clock. If we're really unlucky, it's still required.
1246 */
1247 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1248 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1249 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1250 } else {
1251 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1252 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1253 }
1ce17038 1254
ea9b6006
DV		 1255 I915_WRITE(DP_A, dpa_ctl);
1256
1257 POSTING_READ(DP_A);
1258 udelay(500);
1259}
1260
8ac33ed3 1261static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1262{
b934223d 1263 struct drm_device *dev = encoder->base.dev;
417e822d 1264 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1265 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1266 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1267 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1268 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1269
417e822d 1270 /*
1a2eb460 1271 * There are four kinds of DP registers:
417e822d
KP		 1272 *
1273 * IBX PCH
1a2eb460
KP		 1274 * SNB CPU
1275 * IVB CPU
417e822d
KP		 1276 * CPT PCH
1277 *
1278 * IBX PCH and CPU are the same for almost everything,
1279 * except that the CPU DP PLL is configured in this
1280 * register
1281 *
1282 * CPT PCH is quite different, having many bits moved
1283 * to the TRANS_DP_CTL register instead. That
1284 * configuration happens (oddly) in ironlake_pch_enable
1285 */
9c9e7927 1286
417e822d
KP		 1287 /* Preserve the BIOS-computed detected bit. This is
1288 * supposed to be read-only.
1289 */
1290 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1291
417e822d 1292 /* Handle DP bits in common between all three register formats */
417e822d 1293 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1294 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1295
9ed109a7 1296 if (crtc->config.has_audio) {
e0dac65e 1297 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1298 pipe_name(crtc->pipe));
ea5b213a 1299 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
33d1e7c6 1300 intel_write_eld(encoder);
e0dac65e 1301 }
247d89f6 1302
417e822d 1303 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1304
bc7d38a4 1305 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1306 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1307 intel_dp->DP |= DP_SYNC_HS_HIGH;
1308 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1309 intel_dp->DP |= DP_SYNC_VS_HIGH;
1310 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1311
6aba5b6c 1312 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1313 intel_dp->DP |= DP_ENHANCED_FRAMING;
1314
7c62a164 1315 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1316 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1317 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1318 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1319
1320 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1321 intel_dp->DP |= DP_SYNC_HS_HIGH;
1322 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1323 intel_dp->DP |= DP_SYNC_VS_HIGH;
1324 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1325
6aba5b6c 1326 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1327 intel_dp->DP |= DP_ENHANCED_FRAMING;
1328
44f37d1f
CML		 1329 if (!IS_CHERRYVIEW(dev)) {
1330 if (crtc->pipe == 1)
1331 intel_dp->DP |= DP_PIPEB_SELECT;
1332 } else {
1333 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1334 }
417e822d
KP		 1335 } else {
1336 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1337 }
a4fc5ed6
KP		 1338}
1339
ffd6749d
PZ		 1340#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1341#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1342
1a5ef5b7
PZ		 1343#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1344#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1345
ffd6749d
PZ		 1346#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1347#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1348
4be73780 1349static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1350 u32 mask,
1351 u32 value)
bd943159 1352{
30add22d 1353 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1354 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1355 u32 pp_stat_reg, pp_ctrl_reg;
1356
e39b999a
VS		 1357 lockdep_assert_held(&dev_priv->pps_mutex);
1358
bf13e81b
JN		 1359 pp_stat_reg = _pp_stat_reg(intel_dp);
1360 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1361
99ea7127 1362 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1363 mask, value,
1364 I915_READ(pp_stat_reg),
1365 I915_READ(pp_ctrl_reg));
32ce697c 1366
453c5420 1367 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1368 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1369 I915_READ(pp_stat_reg),
1370 I915_READ(pp_ctrl_reg));
32ce697c 1371 }
54c136d4
CW		 1372
1373 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1374}
32ce697c 1375
4be73780 1376static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1377{
1378 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1379 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1380}
1381
4be73780 1382static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1383{
1384 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1385 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1386}
1387
4be73780 1388static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1389{
1390 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1391
1392 /* When we disable the VDD override bit last we have to do the manual
1393 * wait. */
1394 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1395 intel_dp->panel_power_cycle_delay);
1396
4be73780 1397 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1398}
1399
4be73780 1400static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1401{
1402 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1403 intel_dp->backlight_on_delay);
1404}
1405
4be73780 1406static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1407{
1408 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1409 intel_dp->backlight_off_delay);
1410}
99ea7127 1411
832dd3c1
KP		 1412/* Read the current pp_control value, unlocking the register if it
1413 * is locked
1414 */
1415
453c5420 1416static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1417{
453c5420
JB		 1418 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1419 struct drm_i915_private *dev_priv = dev->dev_private;
1420 u32 control;
832dd3c1 1421
e39b999a
VS		 1422 lockdep_assert_held(&dev_priv->pps_mutex);
1423
bf13e81b 1424 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1425 control &= ~PANEL_UNLOCK_MASK;
1426 control |= PANEL_UNLOCK_REGS;
1427 return control;
bd943159
KP		 1428}
1429
951468f3
VS		 1430/*
1431 * Must be paired with edp_panel_vdd_off().
1432 * Must hold pps_mutex around the whole on/off sequence.
1433 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1434 */
1e0560e0 1435static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1436{
30add22d 1437 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1438 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1439 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1440 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1441 enum intel_display_power_domain power_domain;
5d613501 1442 u32 pp;
453c5420 1443 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1444 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1445
e39b999a
VS		 1446 lockdep_assert_held(&dev_priv->pps_mutex);
1447
97af61f5 1448 if (!is_edp(intel_dp))
adddaaf4 1449 return false;
bd943159
KP		 1450
1451 intel_dp->want_panel_vdd = true;
99ea7127 1452
4be73780 1453 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1454 return need_to_disable;
b0665d57 1455
4e6e1a54
ID		 1456 power_domain = intel_display_port_power_domain(intel_encoder);
1457 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1458
b0665d57 1459 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1460
4be73780
DV		 1461 if (!edp_have_panel_power(intel_dp))
1462 wait_panel_power_cycle(intel_dp);
99ea7127 1463
453c5420 1464 pp = ironlake_get_pp_control(intel_dp);
5d613501 1465 pp |= EDP_FORCE_VDD;
ebf33b18 1466
bf13e81b
JN		 1467 pp_stat_reg = _pp_stat_reg(intel_dp);
1468 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1469
1470 I915_WRITE(pp_ctrl_reg, pp);
1471 POSTING_READ(pp_ctrl_reg);
1472 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1473 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1474 /*
1475 * If the panel wasn't on, delay before accessing aux channel
1476 */
4be73780 1477 if (!edp_have_panel_power(intel_dp)) {
bd943159 1478 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1479 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1480 }
adddaaf4
JN		 1481
1482 return need_to_disable;
1483}
1484
951468f3
VS		 1485/*
1486 * Must be paired with intel_edp_panel_vdd_off() or
1487 * intel_edp_panel_off().
1488 * Nested calls to these functions are not allowed since
1489 * we drop the lock. Caller must use some higher level
1490 * locking to prevent nested calls from other threads.
1491 */
b80d6c78 1492void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1493{
c695b6b6 1494 bool vdd;
adddaaf4 1495
c695b6b6
VS		 1496 if (!is_edp(intel_dp))
1497 return;
1498
773538e8 1499 pps_lock(intel_dp);
c695b6b6 1500 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1501 pps_unlock(intel_dp);
c695b6b6
VS		 1502
1503 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1504}
1505
4be73780 1506static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1507{
30add22d 1508 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1509 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1510 struct intel_digital_port *intel_dig_port =
1511 dp_to_dig_port(intel_dp);
1512 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1513 enum intel_display_power_domain power_domain;
5d613501 1514 u32 pp;
453c5420 1515 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1516
e39b999a 1517 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1518
15e899a0 1519 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1520
15e899a0 1521 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1522 return;
b0665d57 1523
be2c9196 1524 DRM_DEBUG_KMS("Turning eDP VDD off\n");
bd943159 1525
be2c9196
VS		 1526 pp = ironlake_get_pp_control(intel_dp);
1527 pp &= ~EDP_FORCE_VDD;
453c5420 1528
be2c9196
VS		 1529 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1530 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1531
be2c9196
VS		 1532 I915_WRITE(pp_ctrl_reg, pp);
1533 POSTING_READ(pp_ctrl_reg);
90791a5c 1534
be2c9196
VS		 1535 /* Make sure sequencer is idle before allowing subsequent activity */
1536 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1537 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1538
be2c9196
VS		 1539 if ((pp & POWER_TARGET_ON) == 0)
1540 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1541
be2c9196
VS		 1542 power_domain = intel_display_port_power_domain(intel_encoder);
1543 intel_display_power_put(dev_priv, power_domain);
bd943159 1544}
5d613501 1545
4be73780 1546static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1547{
1548 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1549 struct intel_dp, panel_vdd_work);
bd943159 1550
773538e8 1551 pps_lock(intel_dp);
15e899a0
VS		 1552 if (!intel_dp->want_panel_vdd)
1553 edp_panel_vdd_off_sync(intel_dp);
773538e8 1554 pps_unlock(intel_dp);
bd943159
KP		 1555}
1556
aba86890
ID		 1557static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1558{
1559 unsigned long delay;
1560
1561 /*
1562 * Queue the timer to fire a long time from now (relative to the power
1563 * down delay) to keep the panel power up across a sequence of
1564 * operations.
1565 */
1566 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1567 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1568}
1569
951468f3
VS		 1570/*
1571 * Must be paired with edp_panel_vdd_on().
1572 * Must hold pps_mutex around the whole on/off sequence.
1573 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1574 */
4be73780 1575static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1576{
e39b999a
VS		 1577 struct drm_i915_private *dev_priv =
1578 intel_dp_to_dev(intel_dp)->dev_private;
1579
1580 lockdep_assert_held(&dev_priv->pps_mutex);
1581
97af61f5
KP		 1582 if (!is_edp(intel_dp))
1583 return;
5d613501 1584
bd943159 1585 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1586
bd943159
KP		 1587 intel_dp->want_panel_vdd = false;
1588
aba86890 1589 if (sync)
4be73780 1590 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1591 else
1592 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1593}
1594
9f0fb5be 1595static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1596{
30add22d 1597 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1598 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1599 u32 pp;
453c5420 1600 u32 pp_ctrl_reg;
9934c132 1601
9f0fb5be
VS		 1602 lockdep_assert_held(&dev_priv->pps_mutex);
1603
97af61f5 1604 if (!is_edp(intel_dp))
bd943159 1605 return;
99ea7127
KP		 1606
1607 DRM_DEBUG_KMS("Turn eDP power on\n");
1608
4be73780 1609 if (edp_have_panel_power(intel_dp)) {
99ea7127 1610 DRM_DEBUG_KMS("eDP power already on\n");
9f0fb5be 1611 return;
99ea7127 1612 }
9934c132 1613
4be73780 1614 wait_panel_power_cycle(intel_dp);
37c6c9b0 1615
bf13e81b 1616 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1617 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1618 if (IS_GEN5(dev)) {
1619 /* ILK workaround: disable reset around power sequence */
1620 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1621 I915_WRITE(pp_ctrl_reg, pp);
1622 POSTING_READ(pp_ctrl_reg);
05ce1a49 1623 }
37c6c9b0 1624
1c0ae80a 1625 pp |= POWER_TARGET_ON;
99ea7127
KP		 1626 if (!IS_GEN5(dev))
1627 pp |= PANEL_POWER_RESET;
1628
453c5420
JB		 1629 I915_WRITE(pp_ctrl_reg, pp);
1630 POSTING_READ(pp_ctrl_reg);
9934c132 1631
4be73780 1632 wait_panel_on(intel_dp);
dce56b3c 1633 intel_dp->last_power_on = jiffies;
9934c132 1634
05ce1a49
KP		 1635 if (IS_GEN5(dev)) {
1636 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1637 I915_WRITE(pp_ctrl_reg, pp);
1638 POSTING_READ(pp_ctrl_reg);
05ce1a49 1639 }
9f0fb5be 1640}
e39b999a 1641
9f0fb5be
VS		 1642void intel_edp_panel_on(struct intel_dp *intel_dp)
1643{
1644 if (!is_edp(intel_dp))
1645 return;
1646
1647 pps_lock(intel_dp);
1648 edp_panel_on(intel_dp);
773538e8 1649 pps_unlock(intel_dp);
9934c132
JB		 1650}
1651
9f0fb5be
VS		 1652
1653static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1654{
4e6e1a54
ID		 1655 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1656 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1657 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1658 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1659 enum intel_display_power_domain power_domain;
99ea7127 1660 u32 pp;
453c5420 1661 u32 pp_ctrl_reg;
9934c132 1662
9f0fb5be
VS		 1663 lockdep_assert_held(&dev_priv->pps_mutex);
1664
97af61f5
KP		 1665 if (!is_edp(intel_dp))
1666 return;
37c6c9b0 1667
99ea7127 1668 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1669
24f3e092
JN		 1670 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1671
453c5420 1672 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1673 /* We need to switch off panel power _and_ force vdd, for otherwise some
1674 * panels get very unhappy and cease to work. */
b3064154
PJ		 1675 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1676 EDP_BLC_ENABLE);
453c5420 1677
bf13e81b 1678 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1679
849e39f5
PZ		 1680 intel_dp->want_panel_vdd = false;
1681
453c5420
JB		 1682 I915_WRITE(pp_ctrl_reg, pp);
1683 POSTING_READ(pp_ctrl_reg);
9934c132 1684
dce56b3c 1685 intel_dp->last_power_cycle = jiffies;
4be73780 1686 wait_panel_off(intel_dp);
849e39f5
PZ		 1687
1688 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1689 power_domain = intel_display_port_power_domain(intel_encoder);
1690 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1691}
e39b999a 1692
9f0fb5be
VS		 1693void intel_edp_panel_off(struct intel_dp *intel_dp)
1694{
1695 if (!is_edp(intel_dp))
1696 return;
1697
1698 pps_lock(intel_dp);
1699 edp_panel_off(intel_dp);
773538e8 1700 pps_unlock(intel_dp);
9934c132
JB		 1701}
1702
1250d107
JN		 1703/* Enable backlight in the panel power control. */
1704static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1705{
da63a9f2
PZ		 1706 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1707 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1708 struct drm_i915_private *dev_priv = dev->dev_private;
1709 u32 pp;
453c5420 1710 u32 pp_ctrl_reg;
32f9d658 1711
01cb9ea6
JB		 1712 /*
1713 * If we enable the backlight right away following a panel power
1714 * on, we may see slight flicker as the panel syncs with the eDP
1715 * link. So delay a bit to make sure the image is solid before
1716 * allowing it to appear.
1717 */
4be73780 1718 wait_backlight_on(intel_dp);
e39b999a 1719
773538e8 1720 pps_lock(intel_dp);
e39b999a 1721
453c5420 1722 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1723 pp |= EDP_BLC_ENABLE;
453c5420 1724
bf13e81b 1725 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1726
1727 I915_WRITE(pp_ctrl_reg, pp);
1728 POSTING_READ(pp_ctrl_reg);
e39b999a 1729
773538e8 1730 pps_unlock(intel_dp);
32f9d658
ZW		 1731}
1732
1250d107
JN		 1733/* Enable backlight PWM and backlight PP control. */
1734void intel_edp_backlight_on(struct intel_dp *intel_dp)
1735{
1736 if (!is_edp(intel_dp))
1737 return;
1738
1739 DRM_DEBUG_KMS("\n");
1740
1741 intel_panel_enable_backlight(intel_dp->attached_connector);
1742 _intel_edp_backlight_on(intel_dp);
1743}
1744
1745/* Disable backlight in the panel power control. */
1746static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1747{
30add22d 1748 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1749 struct drm_i915_private *dev_priv = dev->dev_private;
1750 u32 pp;
453c5420 1751 u32 pp_ctrl_reg;
32f9d658 1752
f01eca2e
KP		 1753 if (!is_edp(intel_dp))
1754 return;
1755
773538e8 1756 pps_lock(intel_dp);
e39b999a 1757
453c5420 1758 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1759 pp &= ~EDP_BLC_ENABLE;
453c5420 1760
bf13e81b 1761 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1762
1763 I915_WRITE(pp_ctrl_reg, pp);
1764 POSTING_READ(pp_ctrl_reg);
f7d2323c 1765
773538e8 1766 pps_unlock(intel_dp);
e39b999a
VS		 1767
1768 intel_dp->last_backlight_off = jiffies;
f7d2323c 1769 edp_wait_backlight_off(intel_dp);
1250d107 1770}
f7d2323c 1771
1250d107
JN		 1772/* Disable backlight PP control and backlight PWM. */
1773void intel_edp_backlight_off(struct intel_dp *intel_dp)
1774{
1775 if (!is_edp(intel_dp))
1776 return;
1777
1778 DRM_DEBUG_KMS("\n");
f7d2323c 1779
1250d107 1780 _intel_edp_backlight_off(intel_dp);
f7d2323c 1781 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1782}
a4fc5ed6 1783
73580fb7
JN		 1784/*
1785 * Hook for controlling the panel power control backlight through the bl_power
1786 * sysfs attribute. Take care to handle multiple calls.
1787 */
1788static void intel_edp_backlight_power(struct intel_connector *connector,
1789 bool enable)
1790{
1791 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1792 bool is_enabled;
1793
773538e8 1794 pps_lock(intel_dp);
e39b999a 1795 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1796 pps_unlock(intel_dp);
73580fb7
JN		 1797
1798 if (is_enabled == enable)
1799 return;
1800
23ba9373
JN		 1801 DRM_DEBUG_KMS("panel power control backlight %s\n",
1802 enable ? "enable" : "disable");
73580fb7
JN		 1803
1804 if (enable)
1805 _intel_edp_backlight_on(intel_dp);
1806 else
1807 _intel_edp_backlight_off(intel_dp);
1808}
1809
2bd2ad64 1810static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1811{
da63a9f2
PZ		 1812 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1813 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1814 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1815 struct drm_i915_private *dev_priv = dev->dev_private;
1816 u32 dpa_ctl;
1817
2bd2ad64
DV		 1818 assert_pipe_disabled(dev_priv,
1819 to_intel_crtc(crtc)->pipe);
1820
d240f20f
JB		 1821 DRM_DEBUG_KMS("\n");
1822 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1823 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1824 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1825
1826 /* We don't adjust intel_dp->DP while tearing down the link, to
1827 * facilitate link retraining (e.g. after hotplug). Hence clear all
1828 * enable bits here to ensure that we don't enable too much. */
1829 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1830 intel_dp->DP |= DP_PLL_ENABLE;
1831 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1832 POSTING_READ(DP_A);
1833 udelay(200);
d240f20f
JB		 1834}
1835
2bd2ad64 1836static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1837{
da63a9f2
PZ		 1838 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1839 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1840 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1841 struct drm_i915_private *dev_priv = dev->dev_private;
1842 u32 dpa_ctl;
1843
2bd2ad64
DV		 1844 assert_pipe_disabled(dev_priv,
1845 to_intel_crtc(crtc)->pipe);
1846
d240f20f 1847 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1848 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1849 "dp pll off, should be on\n");
1850 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1851
1852 /* We can't rely on the value tracked for the DP register in
1853 * intel_dp->DP because link_down must not change that (otherwise link
1854 * re-training will fail. */
298b0b39 1855 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1856 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1857 POSTING_READ(DP_A);
d240f20f
JB		 1858 udelay(200);
1859}
1860
c7ad3810 1861/* If the sink supports it, try to set the power state appropriately */
c19b0669 1862void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1863{
1864 int ret, i;
1865
1866 /* Should have a valid DPCD by this point */
1867 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1868 return;
1869
1870 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1871 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1872 DP_SET_POWER_D3);
c7ad3810
JB		 1873 } else {
1874 /*
1875 * When turning on, we need to retry for 1ms to give the sink
1876 * time to wake up.
1877 */
1878 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1879 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1880 DP_SET_POWER_D0);
c7ad3810
JB		 1881 if (ret == 1)
1882 break;
1883 msleep(1);
1884 }
1885 }
f9cac721
JN		 1886
1887 if (ret != 1)
1888 DRM_DEBUG_KMS("failed to %s sink power state\n",
1889 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1890}
1891
19d8fe15
DV		 1892static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1893 enum pipe *pipe)
d240f20f 1894{
19d8fe15 1895 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1896 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1897 struct drm_device *dev = encoder->base.dev;
1898 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1899 enum intel_display_power_domain power_domain;
1900 u32 tmp;
1901
1902 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1903 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1904 return false;
1905
1906 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1907
1908 if (!(tmp & DP_PORT_EN))
1909 return false;
1910
bc7d38a4 1911 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1912 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1913 } else if (IS_CHERRYVIEW(dev)) {
1914 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1915 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1916 *pipe = PORT_TO_PIPE(tmp);
1917 } else {
1918 u32 trans_sel;
1919 u32 trans_dp;
1920 int i;
1921
1922 switch (intel_dp->output_reg) {
1923 case PCH_DP_B:
1924 trans_sel = TRANS_DP_PORT_SEL_B;
1925 break;
1926 case PCH_DP_C:
1927 trans_sel = TRANS_DP_PORT_SEL_C;
1928 break;
1929 case PCH_DP_D:
1930 trans_sel = TRANS_DP_PORT_SEL_D;
1931 break;
1932 default:
1933 return true;
1934 }
1935
055e393f 1936 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1937 trans_dp = I915_READ(TRANS_DP_CTL(i));
1938 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1939 *pipe = i;
1940 return true;
1941 }
1942 }
19d8fe15 1943
4a0833ec
DV		 1944 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1945 intel_dp->output_reg);
1946 }
d240f20f 1947
19d8fe15
DV		 1948 return true;
1949}
d240f20f 1950
045ac3b5
JB		 1951static void intel_dp_get_config(struct intel_encoder *encoder,
1952 struct intel_crtc_config *pipe_config)
1953{
1954 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1955 u32 tmp, flags = 0;
63000ef6
XZ		 1956 struct drm_device *dev = encoder->base.dev;
1957 struct drm_i915_private *dev_priv = dev->dev_private;
1958 enum port port = dp_to_dig_port(intel_dp)->port;
1959 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1960 int dotclock;
045ac3b5 1961
9ed109a7
DV		 1962 tmp = I915_READ(intel_dp->output_reg);
1963 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1964 pipe_config->has_audio = true;
1965
63000ef6 1966 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1967 if (tmp & DP_SYNC_HS_HIGH)
1968 flags |= DRM_MODE_FLAG_PHSYNC;
1969 else
1970 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1971
63000ef6
XZ		 1972 if (tmp & DP_SYNC_VS_HIGH)
1973 flags |= DRM_MODE_FLAG_PVSYNC;
1974 else
1975 flags |= DRM_MODE_FLAG_NVSYNC;
1976 } else {
1977 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1978 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1979 flags |= DRM_MODE_FLAG_PHSYNC;
1980 else
1981 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1982
63000ef6
XZ		 1983 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1984 flags |= DRM_MODE_FLAG_PVSYNC;
1985 else
1986 flags |= DRM_MODE_FLAG_NVSYNC;
1987 }
045ac3b5
JB		 1988
1989 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1990
8c875fca
VS		 1991 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1992 tmp & DP_COLOR_RANGE_16_235)
1993 pipe_config->limited_color_range = true;
1994
eb14cb74
VS		 1995 pipe_config->has_dp_encoder = true;
1996
1997 intel_dp_get_m_n(crtc, pipe_config);
1998
18442d08 1999 if (port == PORT_A) {
f1f644dc
JB		 2000 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2001 pipe_config->port_clock = 162000;
2002 else
2003 pipe_config->port_clock = 270000;
2004 }
18442d08
VS		 2005
2006 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2007 &pipe_config->dp_m_n);
2008
2009 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2010 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2011
241bfc38 2012 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2013
c6cd2ee2
JN		 2014 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2015 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2016 /*
2017 * This is a big fat ugly hack.
2018 *
2019 * Some machines in UEFI boot mode provide us a VBT that has 18
2020 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2021 * unknown we fail to light up. Yet the same BIOS boots up with
2022 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2023 * max, not what it tells us to use.
2024 *
2025 * Note: This will still be broken if the eDP panel is not lit
2026 * up by the BIOS, and thus we can't get the mode at module
2027 * load.
2028 */
2029 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2030 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2031 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2032 }
045ac3b5
JB		 2033}
2034
34eb7579 2035static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 2036{
34eb7579 2037 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 2038}
2039
2b28bb1b
RV		 2040static bool intel_edp_is_psr_enabled(struct drm_device *dev)
2041{
2042 struct drm_i915_private *dev_priv = dev->dev_private;
2043
18b5992c 2044 if (!HAS_PSR(dev))
2b28bb1b
RV		 2045 return false;
2046
18b5992c 2047 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 2048}
2049
2050static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
2051 struct edp_vsc_psr *vsc_psr)
2052{
2053 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2054 struct drm_device *dev = dig_port->base.base.dev;
2055 struct drm_i915_private *dev_priv = dev->dev_private;
2056 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
2057 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
2058 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
2059 uint32_t *data = (uint32_t *) vsc_psr;
2060 unsigned int i;
2061
2062 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2063 the video DIP being updated before program video DIP data buffer
2064 registers for DIP being updated. */
2065 I915_WRITE(ctl_reg, 0);
2066 POSTING_READ(ctl_reg);
2067
2068 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
2069 if (i < sizeof(struct edp_vsc_psr))
2070 I915_WRITE(data_reg + i, *data++);
2071 else
2072 I915_WRITE(data_reg + i, 0);
2073 }
2074
2075 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
2076 POSTING_READ(ctl_reg);
2077}
2078
ba80f4d4 2079static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
2b28bb1b 2080{
2b28bb1b
RV		 2081 struct edp_vsc_psr psr_vsc;
2082
2b28bb1b
RV		 2083 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2084 memset(&psr_vsc, 0, sizeof(psr_vsc));
2085 psr_vsc.sdp_header.HB0 = 0;
2086 psr_vsc.sdp_header.HB1 = 0x7;
2087 psr_vsc.sdp_header.HB2 = 0x2;
2088 psr_vsc.sdp_header.HB3 = 0x8;
2089 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2b28bb1b
RV		 2090}
2091
2092static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2093{
0e0ae652
RV		 2094 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2095 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2096 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2097 uint32_t aux_clock_divider;
2b28bb1b 2098 int precharge = 0x3;
0e0ae652 2099 bool only_standby = false;
5ca476f8
VS		 2100 static const uint8_t aux_msg[] = {
2101 [0] = DP_AUX_NATIVE_WRITE << 4,
2102 [1] = DP_SET_POWER >> 8,
2103 [2] = DP_SET_POWER & 0xff,
2104 [3] = 1 - 1,
2105 [4] = DP_SET_POWER_D0,
2106 };
2107 int i;
2108
2109 BUILD_BUG_ON(sizeof(aux_msg) > 20);
2b28bb1b 2110
ec5b01dd
DL		 2111 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2112
0e0ae652
RV		 2113 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2114 only_standby = true;
2115
2b28bb1b 2116 /* Enable PSR in sink */
0e0ae652 2117 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2118 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2119 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2120 else
9d1a1031
JN		 2121 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2122 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2123
2124 /* Setup AUX registers */
5ca476f8
VS		 2125 for (i = 0; i < sizeof(aux_msg); i += 4)
2126 I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
2127 pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
2128
18b5992c 2129 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b 2130 DP_AUX_CH_CTL_TIME_OUT_400us |
5ca476f8 2131 (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2b28bb1b
RV		 2132 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2133 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2134}
2135
2136static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2137{
0e0ae652
RV		 2138 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2139 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2140 struct drm_i915_private *dev_priv = dev->dev_private;
2141 uint32_t max_sleep_time = 0x1f;
2142 uint32_t idle_frames = 1;
2143 uint32_t val = 0x0;
ed8546ac 2144 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2145 bool only_standby = false;
2146
2147 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2148 only_standby = true;
2b28bb1b 2149
0e0ae652 2150 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2151 val |= EDP_PSR_LINK_STANDBY;
2152 val |= EDP_PSR_TP2_TP3_TIME_0us;
2153 val |= EDP_PSR_TP1_TIME_0us;
2154 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2155 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2156 } else
2157 val |= EDP_PSR_LINK_DISABLE;
2158
18b5992c 2159 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2160 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2161 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2162 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2163 EDP_PSR_ENABLE);
2164}
2165
3f51e471
RV		 2166static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2167{
2168 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2169 struct drm_device *dev = dig_port->base.base.dev;
2170 struct drm_i915_private *dev_priv = dev->dev_private;
2171 struct drm_crtc *crtc = dig_port->base.base.crtc;
2172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2173
f0355c4a 2174 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2175 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2176 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2177
a031d709
RV		 2178 dev_priv->psr.source_ok = false;
2179
9ca15301 2180 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2181 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2182 return false;
2183 }
2184
d330a953 2185 if (!i915.enable_psr) {
105b7c11 2186 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2187 return false;
2188 }
2189
4c8c7000
RV		 2190 /* Below limitations aren't valid for Broadwell */
2191 if (IS_BROADWELL(dev))
2192 goto out;
2193
3f51e471
RV		 2194 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2195 S3D_ENABLE) {
2196 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2197 return false;
2198 }
2199
ca73b4f0 2200 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2201 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2202 return false;
2203 }
2204
4c8c7000 2205 out:
a031d709 2206 dev_priv->psr.source_ok = true;
3f51e471
RV		 2207 return true;
2208}
2209
3d739d92 2210static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2211{
7c8f8a70
RV		 2212 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2213 struct drm_device *dev = intel_dig_port->base.base.dev;
2214 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2215
3638379c
DV		 2216 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2217 WARN_ON(dev_priv->psr.active);
f0355c4a 2218 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2219
7ca5a41f 2220 /* Enable/Re-enable PSR on the host */
2b28bb1b 2221 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2222
7c8f8a70 2223 dev_priv->psr.active = true;
2b28bb1b
RV		 2224}
2225
3d739d92
RV		 2226void intel_edp_psr_enable(struct intel_dp *intel_dp)
2227{
2228 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2229 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2230
4704c573
RV		 2231 if (!HAS_PSR(dev)) {
2232 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2233 return;
2234 }
2235
34eb7579
RV		 2236 if (!is_edp_psr(intel_dp)) {
2237 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2238 return;
2239 }
2240
f0355c4a 2241 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2242 if (dev_priv->psr.enabled) {
2243 DRM_DEBUG_KMS("PSR already in use\n");
0aa48783 2244 goto unlock;
109fc2ad
DV		 2245 }
2246
0aa48783
RV		 2247 if (!intel_edp_psr_match_conditions(intel_dp))
2248 goto unlock;
2249
9ca15301
DV		 2250 dev_priv->psr.busy_frontbuffer_bits = 0;
2251
ba80f4d4 2252 intel_edp_psr_setup_vsc(intel_dp);
16487254 2253
ba80f4d4
RV		 2254 /* Avoid continuous PSR exit by masking memup and hpd */
2255 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2256 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
16487254 2257
7ca5a41f
RV		 2258 /* Enable PSR on the panel */
2259 intel_edp_psr_enable_sink(intel_dp);
2260
0aa48783
RV		 2261 dev_priv->psr.enabled = intel_dp;
2262unlock:
f0355c4a 2263 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2264}
2265
2b28bb1b
RV		 2266void intel_edp_psr_disable(struct intel_dp *intel_dp)
2267{
2268 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2269 struct drm_i915_private *dev_priv = dev->dev_private;
2270
f0355c4a
DV		 2271 mutex_lock(&dev_priv->psr.lock);
2272 if (!dev_priv->psr.enabled) {
2273 mutex_unlock(&dev_priv->psr.lock);
2274 return;
2275 }
2276
3638379c
DV		 2277 if (dev_priv->psr.active) {
2278 I915_WRITE(EDP_PSR_CTL(dev),
2279 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2280
2281 /* Wait till PSR is idle */
2282 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2283 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2284 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2285
3638379c
DV		 2286 dev_priv->psr.active = false;
2287 } else {
2288 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2289 }
7c8f8a70 2290
2807cf69 2291 dev_priv->psr.enabled = NULL;
f0355c4a 2292 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2293
2294 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2295}
2296
f02a326e 2297static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2298{
2299 struct drm_i915_private *dev_priv =
2300 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2301 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2302
8d7f4fe9
RV		 2303 /* We have to make sure PSR is ready for re-enable
2304 * otherwise it keeps disabled until next full enable/disable cycle.
2305 * PSR might take some time to get fully disabled
2306 * and be ready for re-enable.
2307 */
2308 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
2309 EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
2310 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
2311 return;
2312 }
2313
f0355c4a
DV		 2314 mutex_lock(&dev_priv->psr.lock);
2315 intel_dp = dev_priv->psr.enabled;
2316
2807cf69 2317 if (!intel_dp)
f0355c4a 2318 goto unlock;
2807cf69 2319
9ca15301
DV		 2320 /*
2321 * The delayed work can race with an invalidate hence we need to
2322 * recheck. Since psr_flush first clears this and then reschedules we
2323 * won't ever miss a flush when bailing out here.
2324 */
2325 if (dev_priv->psr.busy_frontbuffer_bits)
2326 goto unlock;
2327
2328 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2329unlock:
2330 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2331}
2332
9ca15301 2333static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2334{
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336
3638379c
DV		 2337 if (dev_priv->psr.active) {
2338 u32 val = I915_READ(EDP_PSR_CTL(dev));
2339
2340 WARN_ON(!(val & EDP_PSR_ENABLE));
2341
2342 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2343
2344 dev_priv->psr.active = false;
2345 }
7c8f8a70 2346
9ca15301
DV		 2347}
2348
2349void intel_edp_psr_invalidate(struct drm_device *dev,
2350 unsigned frontbuffer_bits)
2351{
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 struct drm_crtc *crtc;
2354 enum pipe pipe;
2355
9ca15301
DV		 2356 mutex_lock(&dev_priv->psr.lock);
2357 if (!dev_priv->psr.enabled) {
2358 mutex_unlock(&dev_priv->psr.lock);
2359 return;
2360 }
2361
2362 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2363 pipe = to_intel_crtc(crtc)->pipe;
2364
2365 intel_edp_psr_do_exit(dev);
2366
2367 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2368
2369 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2370 mutex_unlock(&dev_priv->psr.lock);
2371}
2372
2373void intel_edp_psr_flush(struct drm_device *dev,
2374 unsigned frontbuffer_bits)
2375{
2376 struct drm_i915_private *dev_priv = dev->dev_private;
2377 struct drm_crtc *crtc;
2378 enum pipe pipe;
2379
9ca15301
DV		 2380 mutex_lock(&dev_priv->psr.lock);
2381 if (!dev_priv->psr.enabled) {
2382 mutex_unlock(&dev_priv->psr.lock);
2383 return;
2384 }
2385
2386 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2387 pipe = to_intel_crtc(crtc)->pipe;
2388 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2389
2390 /*
2391 * On Haswell sprite plane updates don't result in a psr invalidating
2392 * signal in the hardware. Which means we need to manually fake this in
2393 * software for all flushes, not just when we've seen a preceding
2394 * invalidation through frontbuffer rendering.
2395 */
2396 if (IS_HASWELL(dev) &&
2397 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2398 intel_edp_psr_do_exit(dev);
2399
2400 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2401 schedule_delayed_work(&dev_priv->psr.work,
2402 msecs_to_jiffies(100));
f0355c4a 2403 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2404}
2405
2406void intel_edp_psr_init(struct drm_device *dev)
2407{
2408 struct drm_i915_private *dev_priv = dev->dev_private;
2409
7c8f8a70 2410 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2411 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2412}
2413
e8cb4558 2414static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2415{
e8cb4558 2416 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2417 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2418
2419 /* Make sure the panel is off before trying to change the mode. But also
2420 * ensure that we have vdd while we switch off the panel. */
24f3e092 2421 intel_edp_panel_vdd_on(intel_dp);
4be73780 2422 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2423 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2424 intel_edp_panel_off(intel_dp);
3739850b 2425
08aff3fe
VS		 2426 /* disable the port before the pipe on g4x */
2427 if (INTEL_INFO(dev)->gen < 5)
3739850b 2428 intel_dp_link_down(intel_dp);
d240f20f
JB		 2429}
2430
08aff3fe 2431static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2432{
2bd2ad64 2433 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2434 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2435
49277c31 2436 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2437 if (port == PORT_A)
2438 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2439}
2440
2441static void vlv_post_disable_dp(struct intel_encoder *encoder)
2442{
2443 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2444
2445 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2446}
2447
580d3811
VS		 2448static void chv_post_disable_dp(struct intel_encoder *encoder)
2449{
2450 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2451 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2452 struct drm_device *dev = encoder->base.dev;
2453 struct drm_i915_private *dev_priv = dev->dev_private;
2454 struct intel_crtc *intel_crtc =
2455 to_intel_crtc(encoder->base.crtc);
2456 enum dpio_channel ch = vlv_dport_to_channel(dport);
2457 enum pipe pipe = intel_crtc->pipe;
2458 u32 val;
2459
2460 intel_dp_link_down(intel_dp);
2461
2462 mutex_lock(&dev_priv->dpio_lock);
2463
2464 /* Propagate soft reset to data lane reset */
97fd4d5c 2465 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2466 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2467 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2468
97fd4d5c
VS		 2469 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2470 val |= CHV_PCS_REQ_SOFTRESET_EN;
2471 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2472
2473 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2474 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2475 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2476
2477 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2478 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2479 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2480
2481 mutex_unlock(&dev_priv->dpio_lock);
2482}
2483
7b13b58a
VS		 2484static void
2485_intel_dp_set_link_train(struct intel_dp *intel_dp,
2486 uint32_t *DP,
2487 uint8_t dp_train_pat)
2488{
2489 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2490 struct drm_device *dev = intel_dig_port->base.base.dev;
2491 struct drm_i915_private *dev_priv = dev->dev_private;
2492 enum port port = intel_dig_port->port;
2493
2494 if (HAS_DDI(dev)) {
2495 uint32_t temp = I915_READ(DP_TP_CTL(port));
2496
2497 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2498 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2499 else
2500 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2501
2502 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2503 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2504 case DP_TRAINING_PATTERN_DISABLE:
2505 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2506
2507 break;
2508 case DP_TRAINING_PATTERN_1:
2509 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2510 break;
2511 case DP_TRAINING_PATTERN_2:
2512 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2513 break;
2514 case DP_TRAINING_PATTERN_3:
2515 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2516 break;
2517 }
2518 I915_WRITE(DP_TP_CTL(port), temp);
2519
2520 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2521 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2522
2523 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2524 case DP_TRAINING_PATTERN_DISABLE:
2525 *DP |= DP_LINK_TRAIN_OFF_CPT;
2526 break;
2527 case DP_TRAINING_PATTERN_1:
2528 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2529 break;
2530 case DP_TRAINING_PATTERN_2:
2531 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2532 break;
2533 case DP_TRAINING_PATTERN_3:
2534 DRM_ERROR("DP training pattern 3 not supported\n");
2535 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2536 break;
2537 }
2538
2539 } else {
2540 if (IS_CHERRYVIEW(dev))
2541 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2542 else
2543 *DP &= ~DP_LINK_TRAIN_MASK;
2544
2545 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2546 case DP_TRAINING_PATTERN_DISABLE:
2547 *DP |= DP_LINK_TRAIN_OFF;
2548 break;
2549 case DP_TRAINING_PATTERN_1:
2550 *DP |= DP_LINK_TRAIN_PAT_1;
2551 break;
2552 case DP_TRAINING_PATTERN_2:
2553 *DP |= DP_LINK_TRAIN_PAT_2;
2554 break;
2555 case DP_TRAINING_PATTERN_3:
2556 if (IS_CHERRYVIEW(dev)) {
2557 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2558 } else {
2559 DRM_ERROR("DP training pattern 3 not supported\n");
2560 *DP |= DP_LINK_TRAIN_PAT_2;
2561 }
2562 break;
2563 }
2564 }
2565}
2566
2567static void intel_dp_enable_port(struct intel_dp *intel_dp)
2568{
2569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2570 struct drm_i915_private *dev_priv = dev->dev_private;
2571
7b13b58a
VS		 2572 /* enable with pattern 1 (as per spec) */
2573 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2574 DP_TRAINING_PATTERN_1);
2575
2576 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2577 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2578
2579 /*
2580 * Magic for VLV/CHV. We _must_ first set up the register
2581 * without actually enabling the port, and then do another
2582 * write to enable the port. Otherwise link training will
2583 * fail when the power sequencer is freshly used for this port.
2584 */
2585 intel_dp->DP |= DP_PORT_EN;
2586
2587 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2588 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2589}
2590
e8cb4558 2591static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2592{
e8cb4558
DV		 2593 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2594 struct drm_device *dev = encoder->base.dev;
2595 struct drm_i915_private *dev_priv = dev->dev_private;
2596 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2597
0c33d8d7
DV		 2598 if (WARN_ON(dp_reg & DP_PORT_EN))
2599 return;
5d613501 2600
093e3f13
VS		 2601 pps_lock(intel_dp);
2602
2603 if (IS_VALLEYVIEW(dev))
2604 vlv_init_panel_power_sequencer(intel_dp);
2605
7b13b58a 2606 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2607
2608 edp_panel_vdd_on(intel_dp);
2609 edp_panel_on(intel_dp);
2610 edp_panel_vdd_off(intel_dp, true);
2611
2612 pps_unlock(intel_dp);
2613
61234fa5
VS		 2614 if (IS_VALLEYVIEW(dev))
2615 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2616
f01eca2e 2617 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2618 intel_dp_start_link_train(intel_dp);
33a34e4e 2619 intel_dp_complete_link_train(intel_dp);
3ab9c637 2620 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2621}
89b667f8 2622
ecff4f3b
JN		 2623static void g4x_enable_dp(struct intel_encoder *encoder)
2624{
828f5c6e
JN		 2625 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2626
ecff4f3b 2627 intel_enable_dp(encoder);
4be73780 2628 intel_edp_backlight_on(intel_dp);
ab1f90f9 2629}
89b667f8 2630
ab1f90f9
JN		 2631static void vlv_enable_dp(struct intel_encoder *encoder)
2632{
828f5c6e
JN		 2633 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2634
4be73780 2635 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2636}
2637
ecff4f3b 2638static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2639{
2640 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2641 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2642
8ac33ed3
DV		 2643 intel_dp_prepare(encoder);
2644
d41f1efb
DV		 2645 /* Only ilk+ has port A */
2646 if (dport->port == PORT_A) {
2647 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2648 ironlake_edp_pll_on(intel_dp);
d41f1efb 2649 }
ab1f90f9
JN		 2650}
2651
a4a5d2f8
VS		 2652static void vlv_steal_power_sequencer(struct drm_device *dev,
2653 enum pipe pipe)
2654{
2655 struct drm_i915_private *dev_priv = dev->dev_private;
2656 struct intel_encoder *encoder;
2657
2658 lockdep_assert_held(&dev_priv->pps_mutex);
2659
2660 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2661 base.head) {
2662 struct intel_dp *intel_dp;
773538e8 2663 enum port port;
a4a5d2f8
VS		 2664
2665 if (encoder->type != INTEL_OUTPUT_EDP)
2666 continue;
2667
2668 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2669 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2670
2671 if (intel_dp->pps_pipe != pipe)
2672 continue;
2673
2674 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2675 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 2676
2677 /* make sure vdd is off before we steal it */
2678 edp_panel_vdd_off_sync(intel_dp);
2679
2680 intel_dp->pps_pipe = INVALID_PIPE;
2681 }
2682}
2683
2684static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2685{
2686 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2687 struct intel_encoder *encoder = &intel_dig_port->base;
2688 struct drm_device *dev = encoder->base.dev;
2689 struct drm_i915_private *dev_priv = dev->dev_private;
2690 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2691
2692 lockdep_assert_held(&dev_priv->pps_mutex);
2693
093e3f13
VS		 2694 if (!is_edp(intel_dp))
2695 return;
2696
a4a5d2f8
VS		 2697 if (intel_dp->pps_pipe == crtc->pipe)
2698 return;
2699
2700 /*
2701 * If another power sequencer was being used on this
2702 * port previously make sure to turn off vdd there while
2703 * we still have control of it.
2704 */
2705 if (intel_dp->pps_pipe != INVALID_PIPE)
2706 edp_panel_vdd_off_sync(intel_dp);
2707
2708 /*
2709 * We may be stealing the power
2710 * sequencer from another port.
2711 */
2712 vlv_steal_power_sequencer(dev, crtc->pipe);
2713
2714 /* now it's all ours */
2715 intel_dp->pps_pipe = crtc->pipe;
2716
2717 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2718 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2719
2720 /* init power sequencer on this pipe and port */
36b5f425
VS		 2721 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2722 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2723}
2724
ab1f90f9 2725static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2726{
2bd2ad64 2727 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2728 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2729 struct drm_device *dev = encoder->base.dev;
89b667f8 2730 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2731 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2732 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2733 int pipe = intel_crtc->pipe;
2734 u32 val;
a4fc5ed6 2735
ab1f90f9 2736 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2737
ab3c759a 2738 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2739 val = 0;
2740 if (pipe)
2741 val |= (1<<21);
2742 else
2743 val &= ~(1<<21);
2744 val |= 0x001000c4;
ab3c759a
CML		 2745 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2746 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2747 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2748
ab1f90f9
JN		 2749 mutex_unlock(&dev_priv->dpio_lock);
2750
2751 intel_enable_dp(encoder);
89b667f8
JB		 2752}
2753
ecff4f3b 2754static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2755{
2756 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2757 struct drm_device *dev = encoder->base.dev;
2758 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2759 struct intel_crtc *intel_crtc =
2760 to_intel_crtc(encoder->base.crtc);
e4607fcf 2761 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2762 int pipe = intel_crtc->pipe;
89b667f8 2763
8ac33ed3
DV		 2764 intel_dp_prepare(encoder);
2765
89b667f8 2766 /* Program Tx lane resets to default */
0980a60f 2767 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2768 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2769 DPIO_PCS_TX_LANE2_RESET |
2770 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2771 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2772 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2773 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2774 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2775 DPIO_PCS_CLK_SOFT_RESET);
2776
2777 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2778 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2779 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2780 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2781 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2782}
2783
e4a1d846
CML		 2784static void chv_pre_enable_dp(struct intel_encoder *encoder)
2785{
2786 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2787 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2788 struct drm_device *dev = encoder->base.dev;
2789 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2790 struct intel_crtc *intel_crtc =
2791 to_intel_crtc(encoder->base.crtc);
2792 enum dpio_channel ch = vlv_dport_to_channel(dport);
2793 int pipe = intel_crtc->pipe;
2794 int data, i;
949c1d43 2795 u32 val;
e4a1d846 2796
e4a1d846 2797 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2798
570e2a74
VS		 2799 /* allow hardware to manage TX FIFO reset source */
2800 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2801 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2802 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2803
2804 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2805 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2806 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2807
949c1d43 2808 /* Deassert soft data lane reset*/
97fd4d5c 2809 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2810 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2811 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2812
2813 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2814 val |= CHV_PCS_REQ_SOFTRESET_EN;
2815 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2816
2817 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2818 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2819 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2820
97fd4d5c 2821 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2822 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2823 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2824
2825 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2826 for (i = 0; i < 4; i++) {
2827 /* Set the latency optimal bit */
2828 data = (i == 1) ? 0x0 : 0x6;
2829 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2830 data << DPIO_FRC_LATENCY_SHFIT);
2831
2832 /* Set the upar bit */
2833 data = (i == 1) ? 0x0 : 0x1;
2834 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2835 data << DPIO_UPAR_SHIFT);
2836 }
2837
2838 /* Data lane stagger programming */
2839 /* FIXME: Fix up value only after power analysis */
2840
2841 mutex_unlock(&dev_priv->dpio_lock);
2842
e4a1d846 2843 intel_enable_dp(encoder);
e4a1d846
CML		 2844}
2845
9197c88b
VS		 2846static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2847{
2848 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2849 struct drm_device *dev = encoder->base.dev;
2850 struct drm_i915_private *dev_priv = dev->dev_private;
2851 struct intel_crtc *intel_crtc =
2852 to_intel_crtc(encoder->base.crtc);
2853 enum dpio_channel ch = vlv_dport_to_channel(dport);
2854 enum pipe pipe = intel_crtc->pipe;
2855 u32 val;
2856
625695f8
VS		 2857 intel_dp_prepare(encoder);
2858
9197c88b
VS		 2859 mutex_lock(&dev_priv->dpio_lock);
2860
b9e5ac3c
VS		 2861 /* program left/right clock distribution */
2862 if (pipe != PIPE_B) {
2863 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2864 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2865 if (ch == DPIO_CH0)
2866 val |= CHV_BUFLEFTENA1_FORCE;
2867 if (ch == DPIO_CH1)
2868 val |= CHV_BUFRIGHTENA1_FORCE;
2869 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2870 } else {
2871 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2872 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2873 if (ch == DPIO_CH0)
2874 val |= CHV_BUFLEFTENA2_FORCE;
2875 if (ch == DPIO_CH1)
2876 val |= CHV_BUFRIGHTENA2_FORCE;
2877 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2878 }
2879
9197c88b
VS		 2880 /* program clock channel usage */
2881 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2882 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2883 if (pipe != PIPE_B)
2884 val &= ~CHV_PCS_USEDCLKCHANNEL;
2885 else
2886 val |= CHV_PCS_USEDCLKCHANNEL;
2887 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2888
2889 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2890 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2891 if (pipe != PIPE_B)
2892 val &= ~CHV_PCS_USEDCLKCHANNEL;
2893 else
2894 val |= CHV_PCS_USEDCLKCHANNEL;
2895 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2896
2897 /*
2898 * This a a bit weird since generally CL
2899 * matches the pipe, but here we need to
2900 * pick the CL based on the port.
2901 */
2902 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2903 if (pipe != PIPE_B)
2904 val &= ~CHV_CMN_USEDCLKCHANNEL;
2905 else
2906 val |= CHV_CMN_USEDCLKCHANNEL;
2907 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2908
2909 mutex_unlock(&dev_priv->dpio_lock);
2910}
2911
a4fc5ed6 2912/*
df0c237d
JB		 2913 * Native read with retry for link status and receiver capability reads for
2914 * cases where the sink may still be asleep.
9d1a1031
JN		 2915 *
2916 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2917 * supposed to retry 3 times per the spec.
a4fc5ed6 2918 */
9d1a1031
JN		 2919static ssize_t
2920intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2921 void *buffer, size_t size)
a4fc5ed6 2922{
9d1a1031
JN		 2923 ssize_t ret;
2924 int i;
61da5fab 2925
61da5fab 2926 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2927 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2928 if (ret == size)
2929 return ret;
61da5fab
JB		 2930 msleep(1);
2931 }
a4fc5ed6 2932
9d1a1031 2933 return ret;
a4fc5ed6
KP		 2934}
2935
2936/*
2937 * Fetch AUX CH registers 0x202 - 0x207 which contain
2938 * link status information
2939 */
2940static bool
93f62dad 2941intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2942{
9d1a1031
JN		 2943 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2944 DP_LANE0_1_STATUS,
2945 link_status,
2946 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2947}
2948
1100244e 2949/* These are source-specific values. */
a4fc5ed6 2950static uint8_t
1a2eb460 2951intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2952{
30add22d 2953 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2954 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2955
5a9d1f1a
DL		 2956 if (INTEL_INFO(dev)->gen >= 9)
2957 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2958 else if (IS_VALLEYVIEW(dev))
bd60018a 2959 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2960 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2961 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2962 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2963 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2964 else
bd60018a 2965 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2966}
2967
2968static uint8_t
2969intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2970{
30add22d 2971 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2972 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2973
5a9d1f1a
DL		 2974 if (INTEL_INFO(dev)->gen >= 9) {
2975 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2976 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2977 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2978 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2979 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2980 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2981 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2982 default:
2983 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2984 }
2985 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2986 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2987 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2988 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2989 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2990 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2991 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2992 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2993 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2994 default:
bd60018a 2995 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2996 }
e2fa6fba
P		 2997 } else if (IS_VALLEYVIEW(dev)) {
2998 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2999 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3000 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3001 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3002 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3003 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3004 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3005 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 3006 default:
bd60018a 3007 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 3008 }
bc7d38a4 3009 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 3010 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3011 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3012 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3014 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3015 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 3016 default:
bd60018a 3017 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 3018 }
3019 } else {
3020 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3021 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3022 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3024 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3025 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3026 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3027 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 3028 default:
bd60018a 3029 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 3030 }
a4fc5ed6
KP		 3031 }
3032}
3033
e2fa6fba
P		 3034static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
3035{
3036 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3037 struct drm_i915_private *dev_priv = dev->dev_private;
3038 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 3039 struct intel_crtc *intel_crtc =
3040 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 3041 unsigned long demph_reg_value, preemph_reg_value,
3042 uniqtranscale_reg_value;
3043 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 3044 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 3045 int pipe = intel_crtc->pipe;
e2fa6fba
P		 3046
3047 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3048 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3049 preemph_reg_value = 0x0004000;
3050 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3051 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3052 demph_reg_value = 0x2B405555;
3053 uniqtranscale_reg_value = 0x552AB83A;
3054 break;
bd60018a 3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3056 demph_reg_value = 0x2B404040;
3057 uniqtranscale_reg_value = 0x5548B83A;
3058 break;
bd60018a 3059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3060 demph_reg_value = 0x2B245555;
3061 uniqtranscale_reg_value = 0x5560B83A;
3062 break;
bd60018a 3063 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3064 demph_reg_value = 0x2B405555;
3065 uniqtranscale_reg_value = 0x5598DA3A;
3066 break;
3067 default:
3068 return 0;
3069 }
3070 break;
bd60018a 3071 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3072 preemph_reg_value = 0x0002000;
3073 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3074 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3075 demph_reg_value = 0x2B404040;
3076 uniqtranscale_reg_value = 0x5552B83A;
3077 break;
bd60018a 3078 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3079 demph_reg_value = 0x2B404848;
3080 uniqtranscale_reg_value = 0x5580B83A;
3081 break;
bd60018a 3082 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3083 demph_reg_value = 0x2B404040;
3084 uniqtranscale_reg_value = 0x55ADDA3A;
3085 break;
3086 default:
3087 return 0;
3088 }
3089 break;
bd60018a 3090 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3091 preemph_reg_value = 0x0000000;
3092 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3094 demph_reg_value = 0x2B305555;
3095 uniqtranscale_reg_value = 0x5570B83A;
3096 break;
bd60018a 3097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3098 demph_reg_value = 0x2B2B4040;
3099 uniqtranscale_reg_value = 0x55ADDA3A;
3100 break;
3101 default:
3102 return 0;
3103 }
3104 break;
bd60018a 3105 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3106 preemph_reg_value = 0x0006000;
3107 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3108 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3109 demph_reg_value = 0x1B405555;
3110 uniqtranscale_reg_value = 0x55ADDA3A;
3111 break;
3112 default:
3113 return 0;
3114 }
3115 break;
3116 default:
3117 return 0;
3118 }
3119
0980a60f 3120 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 3121 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3122 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3123 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3124 uniqtranscale_reg_value);
ab3c759a
CML		 3125 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3126 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3127 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3128 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3129 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3130
3131 return 0;
3132}
3133
e4a1d846
CML		 3134static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3135{
3136 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3137 struct drm_i915_private *dev_priv = dev->dev_private;
3138 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3139 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3140 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3141 uint8_t train_set = intel_dp->train_set[0];
3142 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3143 enum pipe pipe = intel_crtc->pipe;
3144 int i;
e4a1d846
CML		 3145
3146 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3147 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3148 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3149 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3150 deemph_reg_value = 128;
3151 margin_reg_value = 52;
3152 break;
bd60018a 3153 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3154 deemph_reg_value = 128;
3155 margin_reg_value = 77;
3156 break;
bd60018a 3157 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3158 deemph_reg_value = 128;
3159 margin_reg_value = 102;
3160 break;
bd60018a 3161 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3162 deemph_reg_value = 128;
3163 margin_reg_value = 154;
3164 /* FIXME extra to set for 1200 */
3165 break;
3166 default:
3167 return 0;
3168 }
3169 break;
bd60018a 3170 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3171 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3172 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3173 deemph_reg_value = 85;
3174 margin_reg_value = 78;
3175 break;
bd60018a 3176 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3177 deemph_reg_value = 85;
3178 margin_reg_value = 116;
3179 break;
bd60018a 3180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3181 deemph_reg_value = 85;
3182 margin_reg_value = 154;
3183 break;
3184 default:
3185 return 0;
3186 }
3187 break;
bd60018a 3188 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3189 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3190 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3191 deemph_reg_value = 64;
3192 margin_reg_value = 104;
3193 break;
bd60018a 3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3195 deemph_reg_value = 64;
3196 margin_reg_value = 154;
3197 break;
3198 default:
3199 return 0;
3200 }
3201 break;
bd60018a 3202 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3203 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3205 deemph_reg_value = 43;
3206 margin_reg_value = 154;
3207 break;
3208 default:
3209 return 0;
3210 }
3211 break;
3212 default:
3213 return 0;
3214 }
3215
3216 mutex_lock(&dev_priv->dpio_lock);
3217
3218 /* Clear calc init */
1966e59e
VS		 3219 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3220 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3221 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3222 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3223 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3224
3225 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3226 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3227 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3228 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 3229 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 3230
a02ef3c7
VS		 3231 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3232 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3233 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3234 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3235
3236 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3237 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3238 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3239 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3240
e4a1d846 3241 /* Program swing deemph */
f72df8db
VS		 3242 for (i = 0; i < 4; i++) {
3243 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3244 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3245 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3246 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3247 }
e4a1d846
CML		 3248
3249 /* Program swing margin */
f72df8db
VS		 3250 for (i = 0; i < 4; i++) {
3251 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3252 val &= ~DPIO_SWING_MARGIN000_MASK;
3253 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3254 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3255 }
e4a1d846
CML		 3256
3257 /* Disable unique transition scale */
f72df8db
VS		 3258 for (i = 0; i < 4; i++) {
3259 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3260 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3261 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3262 }
e4a1d846
CML		 3263
3264 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3265 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3266 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3267 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3268
3269 /*
3270 * The document said it needs to set bit 27 for ch0 and bit 26
3271 * for ch1. Might be a typo in the doc.
3272 * For now, for this unique transition scale selection, set bit
3273 * 27 for ch0 and ch1.
3274 */
f72df8db
VS		 3275 for (i = 0; i < 4; i++) {
3276 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3277 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3278 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3279 }
e4a1d846 3280
f72df8db
VS		 3281 for (i = 0; i < 4; i++) {
3282 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3283 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3284 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3285 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3286 }
e4a1d846
CML		 3287 }
3288
3289 /* Start swing calculation */
1966e59e
VS		 3290 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3291 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3292 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3293
3294 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3295 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3296 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3297
3298 /* LRC Bypass */
3299 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3300 val |= DPIO_LRC_BYPASS;
3301 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3302
3303 mutex_unlock(&dev_priv->dpio_lock);
3304
3305 return 0;
3306}
3307
a4fc5ed6 3308static void
0301b3ac
JN		 3309intel_get_adjust_train(struct intel_dp *intel_dp,
3310 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3311{
3312 uint8_t v = 0;
3313 uint8_t p = 0;
3314 int lane;
1a2eb460
KP		 3315 uint8_t voltage_max;
3316 uint8_t preemph_max;
a4fc5ed6 3317
33a34e4e 3318 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3319 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3320 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3321
3322 if (this_v > v)
3323 v = this_v;
3324 if (this_p > p)
3325 p = this_p;
3326 }
3327
1a2eb460 3328 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3329 if (v >= voltage_max)
3330 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3331
1a2eb460
KP		 3332 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3333 if (p >= preemph_max)
3334 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3335
3336 for (lane = 0; lane < 4; lane++)
33a34e4e 3337 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3338}
3339
3340static uint32_t
f0a3424e 3341intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3342{
3cf2efb1 3343 uint32_t signal_levels = 0;
a4fc5ed6 3344
3cf2efb1 3345 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3346 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3347 default:
3348 signal_levels |= DP_VOLTAGE_0_4;
3349 break;
bd60018a 3350 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3351 signal_levels |= DP_VOLTAGE_0_6;
3352 break;
bd60018a 3353 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3354 signal_levels |= DP_VOLTAGE_0_8;
3355 break;
bd60018a 3356 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3357 signal_levels |= DP_VOLTAGE_1_2;
3358 break;
3359 }
3cf2efb1 3360 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3361 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3362 default:
3363 signal_levels |= DP_PRE_EMPHASIS_0;
3364 break;
bd60018a 3365 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3366 signal_levels |= DP_PRE_EMPHASIS_3_5;
3367 break;
bd60018a 3368 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3369 signal_levels |= DP_PRE_EMPHASIS_6;
3370 break;
bd60018a 3371 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3372 signal_levels |= DP_PRE_EMPHASIS_9_5;
3373 break;
3374 }
3375 return signal_levels;
3376}
3377
e3421a18
ZW		 3378/* Gen6's DP voltage swing and pre-emphasis control */
3379static uint32_t
3380intel_gen6_edp_signal_levels(uint8_t train_set)
3381{
3c5a62b5
YL		 3382 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3383 DP_TRAIN_PRE_EMPHASIS_MASK);
3384 switch (signal_levels) {
bd60018a
SJ		 3385 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3386 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3387 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3388 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3389 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3390 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3391 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3392 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3393 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3394 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3395 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3396 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3397 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3398 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3399 default:
3c5a62b5
YL		 3400 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3401 "0x%x\n", signal_levels);
3402 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3403 }
3404}
3405
1a2eb460
KP		 3406/* Gen7's DP voltage swing and pre-emphasis control */
3407static uint32_t
3408intel_gen7_edp_signal_levels(uint8_t train_set)
3409{
3410 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3411 DP_TRAIN_PRE_EMPHASIS_MASK);
3412 switch (signal_levels) {
bd60018a 3413 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3414 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3415 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3416 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3417 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3418 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3419
bd60018a 3420 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3421 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3422 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3423 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3424
bd60018a 3425 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3426 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3427 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3428 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3429
3430 default:
3431 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3432 "0x%x\n", signal_levels);
3433 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3434 }
3435}
3436
d6c0d722
PZ		 3437/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3438static uint32_t
f0a3424e 3439intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3440{
d6c0d722
PZ		 3441 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3442 DP_TRAIN_PRE_EMPHASIS_MASK);
3443 switch (signal_levels) {
bd60018a 3444 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3445 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3446 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3447 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3448 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3449 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3450 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3451 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3452
bd60018a 3453 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3454 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3455 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3456 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3457 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3458 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3459
bd60018a 3460 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3461 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3462 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3463 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3464 default:
3465 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3466 "0x%x\n", signal_levels);
c5fe6a06 3467 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3468 }
a4fc5ed6
KP		 3469}
3470
f0a3424e
PZ		 3471/* Properly updates "DP" with the correct signal levels. */
3472static void
3473intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3474{
3475 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3476 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3477 struct drm_device *dev = intel_dig_port->base.base.dev;
3478 uint32_t signal_levels, mask;
3479 uint8_t train_set = intel_dp->train_set[0];
3480
5a9d1f1a 3481 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3482 signal_levels = intel_hsw_signal_levels(train_set);
3483 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3484 } else if (IS_CHERRYVIEW(dev)) {
3485 signal_levels = intel_chv_signal_levels(intel_dp);
3486 mask = 0;
e2fa6fba
P		 3487 } else if (IS_VALLEYVIEW(dev)) {
3488 signal_levels = intel_vlv_signal_levels(intel_dp);
3489 mask = 0;
bc7d38a4 3490 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3491 signal_levels = intel_gen7_edp_signal_levels(train_set);
3492 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3493 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3494 signal_levels = intel_gen6_edp_signal_levels(train_set);
3495 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3496 } else {
3497 signal_levels = intel_gen4_signal_levels(train_set);
3498 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3499 }
3500
3501 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3502
3503 *DP = (*DP & ~mask) | signal_levels;
3504}
3505
a4fc5ed6 3506static bool
ea5b213a 3507intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3508 uint32_t *DP,
58e10eb9 3509 uint8_t dp_train_pat)
a4fc5ed6 3510{
174edf1f
PZ		 3511 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3512 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3513 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3514 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3515 int ret, len;
a4fc5ed6 3516
7b13b58a 3517 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3518
70aff66c 3519 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3520 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3521
2cdfe6c8
JN		 3522 buf[0] = dp_train_pat;
3523 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3524 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3525 /* don't write DP_TRAINING_LANEx_SET on disable */
3526 len = 1;
3527 } else {
3528 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3529 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3530 len = intel_dp->lane_count + 1;
47ea7542 3531 }
a4fc5ed6 3532
9d1a1031
JN		 3533 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3534 buf, len);
2cdfe6c8
JN		 3535
3536 return ret == len;
a4fc5ed6
KP		 3537}
3538
70aff66c
JN		 3539static bool
3540intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3541 uint8_t dp_train_pat)
3542{
953d22e8 3543 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3544 intel_dp_set_signal_levels(intel_dp, DP);
3545 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3546}
3547
3548static bool
3549intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3550 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3551{
3552 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3553 struct drm_device *dev = intel_dig_port->base.base.dev;
3554 struct drm_i915_private *dev_priv = dev->dev_private;
3555 int ret;
3556
3557 intel_get_adjust_train(intel_dp, link_status);
3558 intel_dp_set_signal_levels(intel_dp, DP);
3559
3560 I915_WRITE(intel_dp->output_reg, *DP);
3561 POSTING_READ(intel_dp->output_reg);
3562
9d1a1031
JN		 3563 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3564 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3565
3566 return ret == intel_dp->lane_count;
3567}
3568
3ab9c637
ID		 3569static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3570{
3571 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3572 struct drm_device *dev = intel_dig_port->base.base.dev;
3573 struct drm_i915_private *dev_priv = dev->dev_private;
3574 enum port port = intel_dig_port->port;
3575 uint32_t val;
3576
3577 if (!HAS_DDI(dev))
3578 return;
3579
3580 val = I915_READ(DP_TP_CTL(port));
3581 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3582 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3583 I915_WRITE(DP_TP_CTL(port), val);
3584
3585 /*
3586 * On PORT_A we can have only eDP in SST mode. There the only reason
3587 * we need to set idle transmission mode is to work around a HW issue
3588 * where we enable the pipe while not in idle link-training mode.
3589 * In this case there is requirement to wait for a minimum number of
3590 * idle patterns to be sent.
3591 */
3592 if (port == PORT_A)
3593 return;
3594
3595 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3596 1))
3597 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3598}
3599
33a34e4e 3600/* Enable corresponding port and start training pattern 1 */
c19b0669 3601void
33a34e4e 3602intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3603{
da63a9f2 3604 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3605 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3606 int i;
3607 uint8_t voltage;
cdb0e95b 3608 int voltage_tries, loop_tries;
ea5b213a 3609 uint32_t DP = intel_dp->DP;
6aba5b6c 3610 uint8_t link_config[2];
a4fc5ed6 3611
affa9354 3612 if (HAS_DDI(dev))
c19b0669
PZ		 3613 intel_ddi_prepare_link_retrain(encoder);
3614
3cf2efb1 3615 /* Write the link configuration data */
6aba5b6c
JN		 3616 link_config[0] = intel_dp->link_bw;
3617 link_config[1] = intel_dp->lane_count;
3618 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3619 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3620 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3621
3622 link_config[0] = 0;
3623 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3624 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3625
3626 DP |= DP_PORT_EN;
1a2eb460 3627
70aff66c
JN		 3628 /* clock recovery */
3629 if (!intel_dp_reset_link_train(intel_dp, &DP,
3630 DP_TRAINING_PATTERN_1 |
3631 DP_LINK_SCRAMBLING_DISABLE)) {
3632 DRM_ERROR("failed to enable link training\n");
3633 return;
3634 }
3635
a4fc5ed6 3636 voltage = 0xff;
cdb0e95b
KP		 3637 voltage_tries = 0;
3638 loop_tries = 0;
a4fc5ed6 3639 for (;;) {
70aff66c 3640 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3641
a7c9655f 3642 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3643 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3644 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3645 break;
93f62dad 3646 }
a4fc5ed6 3647
01916270 3648 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3649 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3650 break;
3651 }
3652
3653 /* Check to see if we've tried the max voltage */
3654 for (i = 0; i < intel_dp->lane_count; i++)
3655 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3656 break;
3b4f819d 3657 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3658 ++loop_tries;
3659 if (loop_tries == 5) {
3def84b3 3660 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3661 break;
3662 }
70aff66c
JN		 3663 intel_dp_reset_link_train(intel_dp, &DP,
3664 DP_TRAINING_PATTERN_1 |
3665 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3666 voltage_tries = 0;
3667 continue;
3668 }
a4fc5ed6 3669
3cf2efb1 3670 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3671 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3672 ++voltage_tries;
b06fbda3 3673 if (voltage_tries == 5) {
3def84b3 3674 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3675 break;
3676 }
3677 } else
3678 voltage_tries = 0;
3679 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3680
70aff66c
JN		 3681 /* Update training set as requested by target */
3682 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3683 DRM_ERROR("failed to update link training\n");
3684 break;
3685 }
a4fc5ed6
KP		 3686 }
3687
33a34e4e
JB		 3688 intel_dp->DP = DP;
3689}
3690
c19b0669 3691void
33a34e4e
JB		 3692intel_dp_complete_link_train(struct intel_dp *intel_dp)
3693{
33a34e4e 3694 bool channel_eq = false;
37f80975 3695 int tries, cr_tries;
33a34e4e 3696 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3697 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3698
3699 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3700 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3701 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3702
a4fc5ed6 3703 /* channel equalization */
70aff66c 3704 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3705 training_pattern |
70aff66c
JN		 3706 DP_LINK_SCRAMBLING_DISABLE)) {
3707 DRM_ERROR("failed to start channel equalization\n");
3708 return;
3709 }
3710
a4fc5ed6 3711 tries = 0;
37f80975 3712 cr_tries = 0;
a4fc5ed6
KP		 3713 channel_eq = false;
3714 for (;;) {
70aff66c 3715 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3716
37f80975
JB		 3717 if (cr_tries > 5) {
3718 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3719 break;
3720 }
3721
a7c9655f 3722 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3723 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3724 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3725 break;
70aff66c 3726 }
a4fc5ed6 3727
37f80975 3728 /* Make sure clock is still ok */
01916270 3729 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3730 intel_dp_start_link_train(intel_dp);
70aff66c 3731 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3732 training_pattern |
70aff66c 3733 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3734 cr_tries++;
3735 continue;
3736 }
3737
1ffdff13 3738 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3739 channel_eq = true;
3740 break;
3741 }
a4fc5ed6 3742
37f80975
JB		 3743 /* Try 5 times, then try clock recovery if that fails */
3744 if (tries > 5) {
3745 intel_dp_link_down(intel_dp);
3746 intel_dp_start_link_train(intel_dp);
70aff66c 3747 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3748 training_pattern |
70aff66c 3749 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3750 tries = 0;
3751 cr_tries++;
3752 continue;
3753 }
a4fc5ed6 3754
70aff66c
JN		 3755 /* Update training set as requested by target */
3756 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3757 DRM_ERROR("failed to update link training\n");
3758 break;
3759 }
3cf2efb1 3760 ++tries;
869184a6 3761 }
3cf2efb1 3762
3ab9c637
ID		 3763 intel_dp_set_idle_link_train(intel_dp);
3764
3765 intel_dp->DP = DP;
3766
d6c0d722 3767 if (channel_eq)
07f42258 3768 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3769
3ab9c637
ID		 3770}
3771
3772void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3773{
70aff66c 3774 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3775 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3776}
3777
3778static void
ea5b213a 3779intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3780{
da63a9f2 3781 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3782 enum port port = intel_dig_port->port;
da63a9f2 3783 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3784 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3785 struct intel_crtc *intel_crtc =
3786 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3787 uint32_t DP = intel_dp->DP;
a4fc5ed6 3788
bc76e320 3789 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3790 return;
3791
0c33d8d7 3792 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3793 return;
3794
28c97730 3795 DRM_DEBUG_KMS("\n");
32f9d658 3796
bc7d38a4 3797 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3798 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3799 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3800 } else {
aad3d14d
VS		 3801 if (IS_CHERRYVIEW(dev))
3802 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3803 else
3804 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3805 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3806 }
fe255d00 3807 POSTING_READ(intel_dp->output_reg);
5eb08b69 3808
493a7081 3809 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3810 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3811 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3812
5bddd17f
EA		 3813 /* Hardware workaround: leaving our transcoder select
3814 * set to transcoder B while it's off will prevent the
3815 * corresponding HDMI output on transcoder A.
3816 *
3817 * Combine this with another hardware workaround:
3818 * transcoder select bit can only be cleared while the
3819 * port is enabled.
3820 */
3821 DP &= ~DP_PIPEB_SELECT;
3822 I915_WRITE(intel_dp->output_reg, DP);
3823
3824 /* Changes to enable or select take place the vblank
3825 * after being written.
3826 */
ff50afe9
DV		 3827 if (WARN_ON(crtc == NULL)) {
3828 /* We should never try to disable a port without a crtc
3829 * attached. For paranoia keep the code around for a
3830 * bit. */
31acbcc4
CW		 3831 POSTING_READ(intel_dp->output_reg);
3832 msleep(50);
3833 } else
ab527efc 3834 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3835 }
3836
832afda6 3837 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3838 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3839 POSTING_READ(intel_dp->output_reg);
f01eca2e 3840 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3841}
3842
26d61aad
KP		 3843static bool
3844intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3845{
a031d709
RV		 3846 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3847 struct drm_device *dev = dig_port->base.base.dev;
3848 struct drm_i915_private *dev_priv = dev->dev_private;
3849
9d1a1031
JN		 3850 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3851 sizeof(intel_dp->dpcd)) < 0)
edb39244 3852 return false; /* aux transfer failed */
92fd8fd1 3853
a8e98153 3854 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3855
edb39244
AJ		 3856 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3857 return false; /* DPCD not present */
3858
2293bb5c
SK		 3859 /* Check if the panel supports PSR */
3860 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3861 if (is_edp(intel_dp)) {
9d1a1031
JN		 3862 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3863 intel_dp->psr_dpcd,
3864 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3865 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3866 dev_priv->psr.sink_support = true;
50003939 3867 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3868 }
50003939
JN		 3869 }
3870
06ea66b6
TP		 3871 /* Training Pattern 3 support */
3872 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3873 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3874 intel_dp->use_tps3 = true;
f8d8a672 3875 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3876 } else
3877 intel_dp->use_tps3 = false;
3878
edb39244
AJ		 3879 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3880 DP_DWN_STRM_PORT_PRESENT))
3881 return true; /* native DP sink */
3882
3883 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3884 return true; /* no per-port downstream info */
3885
9d1a1031
JN		 3886 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3887 intel_dp->downstream_ports,
3888 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3889 return false; /* downstream port status fetch failed */
3890
3891 return true;
92fd8fd1
KP		 3892}
3893
0d198328
AJ		 3894static void
3895intel_dp_probe_oui(struct intel_dp *intel_dp)
3896{
3897 u8 buf[3];
3898
3899 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3900 return;
3901
9d1a1031 3902 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3903 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3904 buf[0], buf[1], buf[2]);
3905
9d1a1031 3906 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3907 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3908 buf[0], buf[1], buf[2]);
3909}
3910
0e32b39c
DA		 3911static bool
3912intel_dp_probe_mst(struct intel_dp *intel_dp)
3913{
3914 u8 buf[1];
3915
3916 if (!intel_dp->can_mst)
3917 return false;
3918
3919 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3920 return false;
3921
0e32b39c
DA		 3922 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3923 if (buf[0] & DP_MST_CAP) {
3924 DRM_DEBUG_KMS("Sink is MST capable\n");
3925 intel_dp->is_mst = true;
3926 } else {
3927 DRM_DEBUG_KMS("Sink is not MST capable\n");
3928 intel_dp->is_mst = false;
3929 }
3930 }
0e32b39c
DA		 3931
3932 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3933 return intel_dp->is_mst;
3934}
3935
d2e216d0
RV		 3936int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3937{
3938 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3939 struct drm_device *dev = intel_dig_port->base.base.dev;
3940 struct intel_crtc *intel_crtc =
3941 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3942 u8 buf;
3943 int test_crc_count;
3944 int attempts = 6;
d2e216d0 3945
ad9dc91b 3946 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3947 return -EIO;
d2e216d0 3948
ad9dc91b 3949 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3950 return -ENOTTY;
3951
1dda5f93
RV		 3952 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3953 return -EIO;
3954
9d1a1031 3955 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3956 buf | DP_TEST_SINK_START) < 0)
bda0381e 3957 return -EIO;
d2e216d0 3958
1dda5f93 3959 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3960 return -EIO;
ad9dc91b 3961 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 3962
ad9dc91b 3963 do {
1dda5f93
RV		 3964 if (drm_dp_dpcd_readb(&intel_dp->aux,
3965 DP_TEST_SINK_MISC, &buf) < 0)
3966 return -EIO;
ad9dc91b
RV		 3967 intel_wait_for_vblank(dev, intel_crtc->pipe);
3968 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3969
3970 if (attempts == 0) {
3971 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
3972 return -EIO;
3973 }
d2e216d0 3974
9d1a1031 3975 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 3976 return -EIO;
d2e216d0 3977
1dda5f93
RV		 3978 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3979 return -EIO;
3980 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3981 buf & ~DP_TEST_SINK_START) < 0)
3982 return -EIO;
ce31d9f4 3983
d2e216d0
RV		 3984 return 0;
3985}
3986
a60f0e38
JB		 3987static bool
3988intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3989{
9d1a1031
JN		 3990 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3991 DP_DEVICE_SERVICE_IRQ_VECTOR,
3992 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3993}
3994
0e32b39c
DA		 3995static bool
3996intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3997{
3998 int ret;
3999
4000 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4001 DP_SINK_COUNT_ESI,
4002 sink_irq_vector, 14);
4003 if (ret != 14)
4004 return false;
4005
4006 return true;
4007}
4008
a60f0e38
JB		 4009static void
4010intel_dp_handle_test_request(struct intel_dp *intel_dp)
4011{
4012 /* NAK by default */
9d1a1031 4013 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 4014}
4015
0e32b39c
DA		 4016static int
4017intel_dp_check_mst_status(struct intel_dp *intel_dp)
4018{
4019 bool bret;
4020
4021 if (intel_dp->is_mst) {
4022 u8 esi[16] = { 0 };
4023 int ret = 0;
4024 int retry;
4025 bool handled;
4026 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4027go_again:
4028 if (bret == true) {
4029
4030 /* check link status - esi[10] = 0x200c */
4031 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4032 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4033 intel_dp_start_link_train(intel_dp);
4034 intel_dp_complete_link_train(intel_dp);
4035 intel_dp_stop_link_train(intel_dp);
4036 }
4037
4038 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4039 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4040
4041 if (handled) {
4042 for (retry = 0; retry < 3; retry++) {
4043 int wret;
4044 wret = drm_dp_dpcd_write(&intel_dp->aux,
4045 DP_SINK_COUNT_ESI+1,
4046 &esi[1], 3);
4047 if (wret == 3) {
4048 break;
4049 }
4050 }
4051
4052 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4053 if (bret == true) {
4054 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4055 goto go_again;
4056 }
4057 } else
4058 ret = 0;
4059
4060 return ret;
4061 } else {
4062 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4063 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4064 intel_dp->is_mst = false;
4065 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4066 /* send a hotplug event */
4067 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4068 }
4069 }
4070 return -EINVAL;
4071}
4072
a4fc5ed6
KP		 4073/*
4074 * According to DP spec
4075 * 5.1.2:
4076 * 1. Read DPCD
4077 * 2. Configure link according to Receiver Capabilities
4078 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4079 * 4. Check link status on receipt of hot-plug interrupt
4080 */
00c09d70 4081void
ea5b213a 4082intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4083{
5b215bcf 4084 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4085 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4086 u8 sink_irq_vector;
93f62dad 4087 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4088
5b215bcf
DA		 4089 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4090
da63a9f2 4091 if (!intel_encoder->connectors_active)
d2b996ac 4092 return;
59cd09e1 4093
da63a9f2 4094 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 4095 return;
4096
1a125d8a
ID		 4097 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4098 return;
4099
92fd8fd1 4100 /* Try to read receiver status if the link appears to be up */
93f62dad 4101 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4102 return;
4103 }
4104
92fd8fd1 4105 /* Now read the DPCD to see if it's actually running */
26d61aad 4106 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4107 return;
4108 }
4109
a60f0e38
JB		 4110 /* Try to read the source of the interrupt */
4111 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4112 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4113 /* Clear interrupt source */
9d1a1031
JN		 4114 drm_dp_dpcd_writeb(&intel_dp->aux,
4115 DP_DEVICE_SERVICE_IRQ_VECTOR,
4116 sink_irq_vector);
a60f0e38
JB		 4117
4118 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4119 intel_dp_handle_test_request(intel_dp);
4120 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4121 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4122 }
4123
1ffdff13 4124 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4125 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4126 intel_encoder->base.name);
33a34e4e
JB		 4127 intel_dp_start_link_train(intel_dp);
4128 intel_dp_complete_link_train(intel_dp);
3ab9c637 4129 intel_dp_stop_link_train(intel_dp);
33a34e4e 4130 }
a4fc5ed6 4131}
a4fc5ed6 4132
caf9ab24 4133/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4134static enum drm_connector_status
26d61aad 4135intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4136{
caf9ab24 4137 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4138 uint8_t type;
4139
4140 if (!intel_dp_get_dpcd(intel_dp))
4141 return connector_status_disconnected;
4142
4143 /* if there's no downstream port, we're done */
4144 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4145 return connector_status_connected;
caf9ab24
AJ		 4146
4147 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4148 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4149 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4150 uint8_t reg;
9d1a1031
JN		 4151
4152 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4153 &reg, 1) < 0)
caf9ab24 4154 return connector_status_unknown;
9d1a1031 4155
23235177
AJ		 4156 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4157 : connector_status_disconnected;
caf9ab24
AJ		 4158 }
4159
4160 /* If no HPD, poke DDC gently */
0b99836f 4161 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4162 return connector_status_connected;
caf9ab24
AJ		 4163
4164 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4165 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4166 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4167 if (type == DP_DS_PORT_TYPE_VGA ||
4168 type == DP_DS_PORT_TYPE_NON_EDID)
4169 return connector_status_unknown;
4170 } else {
4171 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4172 DP_DWN_STRM_PORT_TYPE_MASK;
4173 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4174 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4175 return connector_status_unknown;
4176 }
caf9ab24
AJ		 4177
4178 /* Anything else is out of spec, warn and ignore */
4179 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4180 return connector_status_disconnected;
71ba9000
AJ		 4181}
4182
d410b56d
CW		 4183static enum drm_connector_status
4184edp_detect(struct intel_dp *intel_dp)
4185{
4186 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4187 enum drm_connector_status status;
4188
4189 status = intel_panel_detect(dev);
4190 if (status == connector_status_unknown)
4191 status = connector_status_connected;
4192
4193 return status;
4194}
4195
5eb08b69 4196static enum drm_connector_status
a9756bb5 4197ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4198{
30add22d 4199 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4200 struct drm_i915_private *dev_priv = dev->dev_private;
4201 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4202
1b469639
DL		 4203 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4204 return connector_status_disconnected;
4205
26d61aad 4206 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4207}
4208
2a592bec
DA		 4209static int g4x_digital_port_connected(struct drm_device *dev,
4210 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4211{
a4fc5ed6 4212 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4213 uint32_t bit;
5eb08b69 4214
232a6ee9
TP		 4215 if (IS_VALLEYVIEW(dev)) {
4216 switch (intel_dig_port->port) {
4217 case PORT_B:
4218 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4219 break;
4220 case PORT_C:
4221 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4222 break;
4223 case PORT_D:
4224 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4225 break;
4226 default:
2a592bec 4227 return -EINVAL;
232a6ee9
TP		 4228 }
4229 } else {
4230 switch (intel_dig_port->port) {
4231 case PORT_B:
4232 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4233 break;
4234 case PORT_C:
4235 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4236 break;
4237 case PORT_D:
4238 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4239 break;
4240 default:
2a592bec 4241 return -EINVAL;
232a6ee9 4242 }
a4fc5ed6
KP		 4243 }
4244
10f76a38 4245 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4246 return 0;
4247 return 1;
4248}
4249
4250static enum drm_connector_status
4251g4x_dp_detect(struct intel_dp *intel_dp)
4252{
4253 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4254 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4255 int ret;
4256
4257 /* Can't disconnect eDP, but you can close the lid... */
4258 if (is_edp(intel_dp)) {
4259 enum drm_connector_status status;
4260
4261 status = intel_panel_detect(dev);
4262 if (status == connector_status_unknown)
4263 status = connector_status_connected;
4264 return status;
4265 }
4266
4267 ret = g4x_digital_port_connected(dev, intel_dig_port);
4268 if (ret == -EINVAL)
4269 return connector_status_unknown;
4270 else if (ret == 0)
a4fc5ed6
KP		 4271 return connector_status_disconnected;
4272
26d61aad 4273 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4274}
4275
8c241fef 4276static struct edid *
beb60608 4277intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4278{
beb60608 4279 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4280
9cd300e0
JN		 4281 /* use cached edid if we have one */
4282 if (intel_connector->edid) {
9cd300e0
JN		 4283 /* invalid edid */
4284 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4285 return NULL;
4286
55e9edeb 4287 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4288 } else
4289 return drm_get_edid(&intel_connector->base,
4290 &intel_dp->aux.ddc);
4291}
8c241fef 4292
beb60608
CW		 4293static void
4294intel_dp_set_edid(struct intel_dp *intel_dp)
4295{
4296 struct intel_connector *intel_connector = intel_dp->attached_connector;
4297 struct edid *edid;
8c241fef 4298
beb60608
CW		 4299 edid = intel_dp_get_edid(intel_dp);
4300 intel_connector->detect_edid = edid;
4301
4302 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4303 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4304 else
4305 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4306}
4307
beb60608
CW		 4308static void
4309intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4310{
beb60608 4311 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4312
beb60608
CW		 4313 kfree(intel_connector->detect_edid);
4314 intel_connector->detect_edid = NULL;
9cd300e0 4315
beb60608
CW		 4316 intel_dp->has_audio = false;
4317}
d6f24d0f 4318
beb60608
CW		 4319static enum intel_display_power_domain
4320intel_dp_power_get(struct intel_dp *dp)
4321{
4322 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4323 enum intel_display_power_domain power_domain;
4324
4325 power_domain = intel_display_port_power_domain(encoder);
4326 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4327
4328 return power_domain;
4329}
d6f24d0f 4330
beb60608
CW		 4331static void
4332intel_dp_power_put(struct intel_dp *dp,
4333 enum intel_display_power_domain power_domain)
4334{
4335 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4336 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4337}
4338
a9756bb5
ZW		 4339static enum drm_connector_status
4340intel_dp_detect(struct drm_connector *connector, bool force)
4341{
4342 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4343 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4344 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4345 struct drm_device *dev = connector->dev;
a9756bb5 4346 enum drm_connector_status status;
671dedd2 4347 enum intel_display_power_domain power_domain;
0e32b39c 4348 bool ret;
a9756bb5 4349
164c8598 4350 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4351 connector->base.id, connector->name);
beb60608 4352 intel_dp_unset_edid(intel_dp);
164c8598 4353
0e32b39c
DA		 4354 if (intel_dp->is_mst) {
4355 /* MST devices are disconnected from a monitor POV */
4356 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4357 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4358 return connector_status_disconnected;
0e32b39c
DA		 4359 }
4360
beb60608 4361 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4362
d410b56d
CW		 4363 /* Can't disconnect eDP, but you can close the lid... */
4364 if (is_edp(intel_dp))
4365 status = edp_detect(intel_dp);
4366 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4367 status = ironlake_dp_detect(intel_dp);
4368 else
4369 status = g4x_dp_detect(intel_dp);
4370 if (status != connector_status_connected)
c8c8fb33 4371 goto out;
a9756bb5 4372
0d198328
AJ		 4373 intel_dp_probe_oui(intel_dp);
4374
0e32b39c
DA		 4375 ret = intel_dp_probe_mst(intel_dp);
4376 if (ret) {
4377 /* if we are in MST mode then this connector
4378 won't appear connected or have anything with EDID on it */
4379 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4380 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4381 status = connector_status_disconnected;
4382 goto out;
4383 }
4384
beb60608 4385 intel_dp_set_edid(intel_dp);
a9756bb5 4386
d63885da
PZ		 4387 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4388 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4389 status = connector_status_connected;
4390
4391out:
beb60608 4392 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4393 return status;
a4fc5ed6
KP		 4394}
4395
beb60608
CW		 4396static void
4397intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4398{
df0e9248 4399 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4400 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4401 enum intel_display_power_domain power_domain;
a4fc5ed6 4402
beb60608
CW		 4403 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4404 connector->base.id, connector->name);
4405 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4406
beb60608
CW		 4407 if (connector->status != connector_status_connected)
4408 return;
671dedd2 4409
beb60608
CW		 4410 power_domain = intel_dp_power_get(intel_dp);
4411
4412 intel_dp_set_edid(intel_dp);
4413
4414 intel_dp_power_put(intel_dp, power_domain);
4415
4416 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4417 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4418}
4419
4420static int intel_dp_get_modes(struct drm_connector *connector)
4421{
4422 struct intel_connector *intel_connector = to_intel_connector(connector);
4423 struct edid *edid;
4424
4425 edid = intel_connector->detect_edid;
4426 if (edid) {
4427 int ret = intel_connector_update_modes(connector, edid);
4428 if (ret)
4429 return ret;
4430 }
32f9d658 4431
f8779fda 4432 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4433 if (is_edp(intel_attached_dp(connector)) &&
4434 intel_connector->panel.fixed_mode) {
f8779fda 4435 struct drm_display_mode *mode;
beb60608
CW		 4436
4437 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4438 intel_connector->panel.fixed_mode);
f8779fda 4439 if (mode) {
32f9d658
ZW		 4440 drm_mode_probed_add(connector, mode);
4441 return 1;
4442 }
4443 }
beb60608 4444
32f9d658 4445 return 0;
a4fc5ed6
KP		 4446}
4447
1aad7ac0
CW		 4448static bool
4449intel_dp_detect_audio(struct drm_connector *connector)
4450{
1aad7ac0 4451 bool has_audio = false;
beb60608 4452 struct edid *edid;
1aad7ac0 4453
beb60608
CW		 4454 edid = to_intel_connector(connector)->detect_edid;
4455 if (edid)
1aad7ac0 4456 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4457
1aad7ac0
CW		 4458 return has_audio;
4459}
4460
f684960e
CW		 4461static int
4462intel_dp_set_property(struct drm_connector *connector,
4463 struct drm_property *property,
4464 uint64_t val)
4465{
e953fd7b 4466 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4467 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4468 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4469 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4470 int ret;
4471
662595df 4472 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4473 if (ret)
4474 return ret;
4475
3f43c48d 4476 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4477 int i = val;
4478 bool has_audio;
4479
4480 if (i == intel_dp->force_audio)
f684960e
CW		 4481 return 0;
4482
1aad7ac0 4483 intel_dp->force_audio = i;
f684960e 4484
c3e5f67b 4485 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4486 has_audio = intel_dp_detect_audio(connector);
4487 else
c3e5f67b 4488 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4489
4490 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4491 return 0;
4492
1aad7ac0 4493 intel_dp->has_audio = has_audio;
f684960e
CW		 4494 goto done;
4495 }
4496
e953fd7b 4497 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4498 bool old_auto = intel_dp->color_range_auto;
4499 uint32_t old_range = intel_dp->color_range;
4500
55bc60db
VS		 4501 switch (val) {
4502 case INTEL_BROADCAST_RGB_AUTO:
4503 intel_dp->color_range_auto = true;
4504 break;
4505 case INTEL_BROADCAST_RGB_FULL:
4506 intel_dp->color_range_auto = false;
4507 intel_dp->color_range = 0;
4508 break;
4509 case INTEL_BROADCAST_RGB_LIMITED:
4510 intel_dp->color_range_auto = false;
4511 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4512 break;
4513 default:
4514 return -EINVAL;
4515 }
ae4edb80
DV		 4516
4517 if (old_auto == intel_dp->color_range_auto &&
4518 old_range == intel_dp->color_range)
4519 return 0;
4520
e953fd7b
CW		 4521 goto done;
4522 }
4523
53b41837
YN		 4524 if (is_edp(intel_dp) &&
4525 property == connector->dev->mode_config.scaling_mode_property) {
4526 if (val == DRM_MODE_SCALE_NONE) {
4527 DRM_DEBUG_KMS("no scaling not supported\n");
4528 return -EINVAL;
4529 }
4530
4531 if (intel_connector->panel.fitting_mode == val) {
4532 /* the eDP scaling property is not changed */
4533 return 0;
4534 }
4535 intel_connector->panel.fitting_mode = val;
4536
4537 goto done;
4538 }
4539
f684960e
CW		 4540 return -EINVAL;
4541
4542done:
c0c36b94
CW		 4543 if (intel_encoder->base.crtc)
4544 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4545
4546 return 0;
4547}
4548
a4fc5ed6 4549static void
73845adf 4550intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4551{
1d508706 4552 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4553
10e972d3 4554 kfree(intel_connector->detect_edid);
beb60608 4555
9cd300e0
JN		 4556 if (!IS_ERR_OR_NULL(intel_connector->edid))
4557 kfree(intel_connector->edid);
4558
acd8db10
PZ		 4559 /* Can't call is_edp() since the encoder may have been destroyed
4560 * already. */
4561 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4562 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4563
a4fc5ed6 4564 drm_connector_cleanup(connector);
55f78c43 4565 kfree(connector);
a4fc5ed6
KP		 4566}
4567
00c09d70 4568void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4569{
da63a9f2
PZ		 4570 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4571 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4572
4f71d0cb 4573 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4574 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4575 drm_encoder_cleanup(encoder);
bd943159
KP		 4576 if (is_edp(intel_dp)) {
4577 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4578 /*
4579 * vdd might still be enabled do to the delayed vdd off.
4580 * Make sure vdd is actually turned off here.
4581 */
773538e8 4582 pps_lock(intel_dp);
4be73780 4583 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4584 pps_unlock(intel_dp);
4585
01527b31
CT		 4586 if (intel_dp->edp_notifier.notifier_call) {
4587 unregister_reboot_notifier(&intel_dp->edp_notifier);
4588 intel_dp->edp_notifier.notifier_call = NULL;
4589 }
bd943159 4590 }
da63a9f2 4591 kfree(intel_dig_port);
24d05927
DV		 4592}
4593
07f9cd0b
ID		 4594static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4595{
4596 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4597
4598 if (!is_edp(intel_dp))
4599 return;
4600
951468f3
VS		 4601 /*
4602 * vdd might still be enabled do to the delayed vdd off.
4603 * Make sure vdd is actually turned off here.
4604 */
773538e8 4605 pps_lock(intel_dp);
07f9cd0b 4606 edp_panel_vdd_off_sync(intel_dp);
773538e8 4607 pps_unlock(intel_dp);
07f9cd0b
ID		 4608}
4609
6d93c0c4
ID		 4610static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4611{
4612 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4613}
4614
a4fc5ed6 4615static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4616 .dpms = intel_connector_dpms,
a4fc5ed6 4617 .detect = intel_dp_detect,
beb60608 4618 .force = intel_dp_force,
a4fc5ed6 4619 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4620 .set_property = intel_dp_set_property,
73845adf 4621 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4622};
4623
4624static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4625 .get_modes = intel_dp_get_modes,
4626 .mode_valid = intel_dp_mode_valid,
df0e9248 4627 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4628};
4629
a4fc5ed6 4630static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4631 .reset = intel_dp_encoder_reset,
24d05927 4632 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4633};
4634
0e32b39c 4635void
21d40d37 4636intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4637{
0e32b39c 4638 return;
c8110e52 4639}
6207937d 4640
13cf5504
DA		 4641bool
4642intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4643{
4644 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4645 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4646 struct drm_device *dev = intel_dig_port->base.base.dev;
4647 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4648 enum intel_display_power_domain power_domain;
4649 bool ret = true;
4650
0e32b39c
DA		 4651 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4652 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4653
26fbb774
VS		 4654 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4655 port_name(intel_dig_port->port),
0e32b39c 4656 long_hpd ? "long" : "short");
13cf5504 4657
1c767b33
ID		 4658 power_domain = intel_display_port_power_domain(intel_encoder);
4659 intel_display_power_get(dev_priv, power_domain);
4660
0e32b39c 4661 if (long_hpd) {
2a592bec
DA		 4662
4663 if (HAS_PCH_SPLIT(dev)) {
4664 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4665 goto mst_fail;
4666 } else {
4667 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4668 goto mst_fail;
4669 }
0e32b39c
DA		 4670
4671 if (!intel_dp_get_dpcd(intel_dp)) {
4672 goto mst_fail;
4673 }
4674
4675 intel_dp_probe_oui(intel_dp);
4676
4677 if (!intel_dp_probe_mst(intel_dp))
4678 goto mst_fail;
4679
4680 } else {
4681 if (intel_dp->is_mst) {
1c767b33 4682 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4683 goto mst_fail;
4684 }
4685
4686 if (!intel_dp->is_mst) {
4687 /*
4688 * we'll check the link status via the normal hot plug path later -
4689 * but for short hpds we should check it now
4690 */
5b215bcf 4691 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4692 intel_dp_check_link_status(intel_dp);
5b215bcf 4693 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4694 }
4695 }
1c767b33
ID		 4696 ret = false;
4697 goto put_power;
0e32b39c
DA		 4698mst_fail:
4699 /* if we were in MST mode, and device is not there get out of MST mode */
4700 if (intel_dp->is_mst) {
4701 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4702 intel_dp->is_mst = false;
4703 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4704 }
1c767b33
ID		 4705put_power:
4706 intel_display_power_put(dev_priv, power_domain);
4707
4708 return ret;
13cf5504
DA		 4709}
4710
e3421a18
ZW		 4711/* Return which DP Port should be selected for Transcoder DP control */
4712int
0206e353 4713intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4714{
4715 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4716 struct intel_encoder *intel_encoder;
4717 struct intel_dp *intel_dp;
e3421a18 4718
fa90ecef
PZ		 4719 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4720 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4721
fa90ecef
PZ		 4722 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4723 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4724 return intel_dp->output_reg;
e3421a18 4725 }
ea5b213a 4726
e3421a18
ZW		 4727 return -1;
4728}
4729
36e83a18 4730/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4731bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4732{
4733 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4734 union child_device_config *p_child;
36e83a18 4735 int i;
5d8a7752
VS		 4736 static const short port_mapping[] = {
4737 [PORT_B] = PORT_IDPB,
4738 [PORT_C] = PORT_IDPC,
4739 [PORT_D] = PORT_IDPD,
4740 };
36e83a18 4741
3b32a35b
VS		 4742 if (port == PORT_A)
4743 return true;
4744
41aa3448 4745 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4746 return false;
4747
41aa3448
RV		 4748 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4749 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4750
5d8a7752 4751 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4752 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4753 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4754 return true;
4755 }
4756 return false;
4757}
4758
0e32b39c 4759void
f684960e
CW		 4760intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4761{
53b41837
YN		 4762 struct intel_connector *intel_connector = to_intel_connector(connector);
4763
3f43c48d 4764 intel_attach_force_audio_property(connector);
e953fd7b 4765 intel_attach_broadcast_rgb_property(connector);
55bc60db 4766 intel_dp->color_range_auto = true;
53b41837
YN		 4767
4768 if (is_edp(intel_dp)) {
4769 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4770 drm_object_attach_property(
4771 &connector->base,
53b41837 4772 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4773 DRM_MODE_SCALE_ASPECT);
4774 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4775 }
f684960e
CW		 4776}
4777
dada1a9f
ID		 4778static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4779{
4780 intel_dp->last_power_cycle = jiffies;
4781 intel_dp->last_power_on = jiffies;
4782 intel_dp->last_backlight_off = jiffies;
4783}
4784
67a54566
DV		 4785static void
4786intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4787 struct intel_dp *intel_dp)
67a54566
DV		 4788{
4789 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4790 struct edp_power_seq cur, vbt, spec,
4791 *final = &intel_dp->pps_delays;
67a54566 4792 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4793 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4794
e39b999a
VS		 4795 lockdep_assert_held(&dev_priv->pps_mutex);
4796
81ddbc69
VS		 4797 /* already initialized? */
4798 if (final->t11_t12 != 0)
4799 return;
4800
453c5420 4801 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4802 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4803 pp_on_reg = PCH_PP_ON_DELAYS;
4804 pp_off_reg = PCH_PP_OFF_DELAYS;
4805 pp_div_reg = PCH_PP_DIVISOR;
4806 } else {
bf13e81b
JN		 4807 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4808
4809 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4810 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4811 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4812 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4813 }
67a54566
DV		 4814
4815 /* Workaround: Need to write PP_CONTROL with the unlock key as
4816 * the very first thing. */
453c5420 4817 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4818 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4819
453c5420
JB		 4820 pp_on = I915_READ(pp_on_reg);
4821 pp_off = I915_READ(pp_off_reg);
4822 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4823
4824 /* Pull timing values out of registers */
4825 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4826 PANEL_POWER_UP_DELAY_SHIFT;
4827
4828 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4829 PANEL_LIGHT_ON_DELAY_SHIFT;
4830
4831 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4832 PANEL_LIGHT_OFF_DELAY_SHIFT;
4833
4834 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4835 PANEL_POWER_DOWN_DELAY_SHIFT;
4836
4837 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4838 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4839
4840 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4841 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4842
41aa3448 4843 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4844
4845 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4846 * our hw here, which are all in 100usec. */
4847 spec.t1_t3 = 210 * 10;
4848 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4849 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4850 spec.t10 = 500 * 10;
4851 /* This one is special and actually in units of 100ms, but zero
4852 * based in the hw (so we need to add 100 ms). But the sw vbt
4853 * table multiplies it with 1000 to make it in units of 100usec,
4854 * too. */
4855 spec.t11_t12 = (510 + 100) * 10;
4856
4857 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4858 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4859
4860 /* Use the max of the register settings and vbt. If both are
4861 * unset, fall back to the spec limits. */
36b5f425 4862#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4863 spec.field : \
4864 max(cur.field, vbt.field))
4865 assign_final(t1_t3);
4866 assign_final(t8);
4867 assign_final(t9);
4868 assign_final(t10);
4869 assign_final(t11_t12);
4870#undef assign_final
4871
36b5f425 4872#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4873 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4874 intel_dp->backlight_on_delay = get_delay(t8);
4875 intel_dp->backlight_off_delay = get_delay(t9);
4876 intel_dp->panel_power_down_delay = get_delay(t10);
4877 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4878#undef get_delay
4879
f30d26e4
JN		 4880 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4881 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4882 intel_dp->panel_power_cycle_delay);
4883
4884 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4885 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 4886}
4887
4888static void
4889intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4890 struct intel_dp *intel_dp)
f30d26e4
JN		 4891{
4892 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4893 u32 pp_on, pp_off, pp_div, port_sel = 0;
4894 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4895 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4896 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4897 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4898
e39b999a 4899 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4900
4901 if (HAS_PCH_SPLIT(dev)) {
4902 pp_on_reg = PCH_PP_ON_DELAYS;
4903 pp_off_reg = PCH_PP_OFF_DELAYS;
4904 pp_div_reg = PCH_PP_DIVISOR;
4905 } else {
bf13e81b
JN		 4906 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4907
4908 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4909 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4910 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4911 }
4912
b2f19d1a
PZ		 4913 /*
4914 * And finally store the new values in the power sequencer. The
4915 * backlight delays are set to 1 because we do manual waits on them. For
4916 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4917 * we'll end up waiting for the backlight off delay twice: once when we
4918 * do the manual sleep, and once when we disable the panel and wait for
4919 * the PP_STATUS bit to become zero.
4920 */
f30d26e4 4921 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4922 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4923 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4924 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4925 /* Compute the divisor for the pp clock, simply match the Bspec
4926 * formula. */
453c5420 4927 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4928 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4929 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4930
4931 /* Haswell doesn't have any port selection bits for the panel
4932 * power sequencer any more. */
bc7d38a4 4933 if (IS_VALLEYVIEW(dev)) {
ad933b56 4934 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4935 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4936 if (port == PORT_A)
a24c144c 4937 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4938 else
a24c144c 4939 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4940 }
4941
453c5420
JB		 4942 pp_on |= port_sel;
4943
4944 I915_WRITE(pp_on_reg, pp_on);
4945 I915_WRITE(pp_off_reg, pp_off);
4946 I915_WRITE(pp_div_reg, pp_div);
67a54566 4947
67a54566 4948 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4949 I915_READ(pp_on_reg),
4950 I915_READ(pp_off_reg),
4951 I915_READ(pp_div_reg));
f684960e
CW		 4952}
4953
439d7ac0
PB		 4954void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4955{
4956 struct drm_i915_private *dev_priv = dev->dev_private;
4957 struct intel_encoder *encoder;
4958 struct intel_dp *intel_dp = NULL;
4959 struct intel_crtc_config *config = NULL;
4960 struct intel_crtc *intel_crtc = NULL;
4961 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4962 u32 reg, val;
4963 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4964
4965 if (refresh_rate <= 0) {
4966 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4967 return;
4968 }
4969
4970 if (intel_connector == NULL) {
4971 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4972 return;
4973 }
4974
1fcc9d1c
DV		 4975 /*
4976 * FIXME: This needs proper synchronization with psr state. But really
4977 * hard to tell without seeing the user of this function of this code.
4978 * Check locking and ordering once that lands.
4979 */
439d7ac0
PB		 4980 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4981 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4982 return;
4983 }
4984
4985 encoder = intel_attached_encoder(&intel_connector->base);
4986 intel_dp = enc_to_intel_dp(&encoder->base);
4987 intel_crtc = encoder->new_crtc;
4988
4989 if (!intel_crtc) {
4990 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4991 return;
4992 }
4993
4994 config = &intel_crtc->config;
4995
4996 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4997 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4998 return;
4999 }
5000
5001 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
5002 index = DRRS_LOW_RR;
5003
5004 if (index == intel_dp->drrs_state.refresh_rate_type) {
5005 DRM_DEBUG_KMS(
5006 "DRRS requested for previously set RR...ignoring\n");
5007 return;
5008 }
5009
5010 if (!intel_crtc->active) {
5011 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5012 return;
5013 }
5014
5015 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
5016 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
5017 val = I915_READ(reg);
5018 if (index > DRRS_HIGH_RR) {
5019 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 5020 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 5021 } else {
5022 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5023 }
5024 I915_WRITE(reg, val);
5025 }
5026
5027 /*
5028 * mutex taken to ensure that there is no race between differnt
5029 * drrs calls trying to update refresh rate. This scenario may occur
5030 * in future when idleness detection based DRRS in kernel and
5031 * possible calls from user space to set differnt RR are made.
5032 */
5033
5034 mutex_lock(&intel_dp->drrs_state.mutex);
5035
5036 intel_dp->drrs_state.refresh_rate_type = index;
5037
5038 mutex_unlock(&intel_dp->drrs_state.mutex);
5039
5040 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5041}
5042
4f9db5b5
PB		 5043static struct drm_display_mode *
5044intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
5045 struct intel_connector *intel_connector,
5046 struct drm_display_mode *fixed_mode)
5047{
5048 struct drm_connector *connector = &intel_connector->base;
5049 struct intel_dp *intel_dp = &intel_dig_port->dp;
5050 struct drm_device *dev = intel_dig_port->base.base.dev;
5051 struct drm_i915_private *dev_priv = dev->dev_private;
5052 struct drm_display_mode *downclock_mode = NULL;
5053
5054 if (INTEL_INFO(dev)->gen <= 6) {
5055 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5056 return NULL;
5057 }
5058
5059 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5060 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5061 return NULL;
5062 }
5063
5064 downclock_mode = intel_find_panel_downclock
5065 (dev, fixed_mode, connector);
5066
5067 if (!downclock_mode) {
4079b8d1 5068 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 5069 return NULL;
5070 }
5071
439d7ac0
PB		 5072 dev_priv->drrs.connector = intel_connector;
5073
5074 mutex_init(&intel_dp->drrs_state.mutex);
5075
4f9db5b5
PB		 5076 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
5077
5078 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5079 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5080 return downclock_mode;
5081}
5082
aba86890
ID		 5083void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
5084{
5085 struct drm_device *dev = intel_encoder->base.dev;
5086 struct drm_i915_private *dev_priv = dev->dev_private;
5087 struct intel_dp *intel_dp;
5088 enum intel_display_power_domain power_domain;
5089
5090 if (intel_encoder->type != INTEL_OUTPUT_EDP)
5091 return;
5092
5093 intel_dp = enc_to_intel_dp(&intel_encoder->base);
773538e8
VS		 5094
5095 pps_lock(intel_dp);
5096
aba86890 5097 if (!edp_have_panel_vdd(intel_dp))
e39b999a 5098 goto out;
aba86890
ID		 5099 /*
5100 * The VDD bit needs a power domain reference, so if the bit is
5101 * already enabled when we boot or resume, grab this reference and
5102 * schedule a vdd off, so we don't hold on to the reference
5103 * indefinitely.
5104 */
5105 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5106 power_domain = intel_display_port_power_domain(intel_encoder);
5107 intel_display_power_get(dev_priv, power_domain);
5108
5109 edp_panel_vdd_schedule_off(intel_dp);
e39b999a 5110 out:
773538e8 5111 pps_unlock(intel_dp);
aba86890
ID		 5112}
5113
ed92f0b2 5114static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5115 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5116{
5117 struct drm_connector *connector = &intel_connector->base;
5118 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5119 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5120 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5121 struct drm_i915_private *dev_priv = dev->dev_private;
5122 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5123 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5124 bool has_dpcd;
5125 struct drm_display_mode *scan;
5126 struct edid *edid;
5127
4f9db5b5
PB		 5128 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
5129
ed92f0b2
PZ		 5130 if (!is_edp(intel_dp))
5131 return true;
5132
aba86890 5133 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 5134
ed92f0b2 5135 /* Cache DPCD and EDID for edp. */
ed92f0b2 5136 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5137
5138 if (has_dpcd) {
5139 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5140 dev_priv->no_aux_handshake =
5141 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5142 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5143 } else {
5144 /* if this fails, presume the device is a ghost */
5145 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5146 return false;
5147 }
5148
5149 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5150 pps_lock(intel_dp);
36b5f425 5151 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5152 pps_unlock(intel_dp);
ed92f0b2 5153
060c8778 5154 mutex_lock(&dev->mode_config.mutex);
0b99836f 5155 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5156 if (edid) {
5157 if (drm_add_edid_modes(connector, edid)) {
5158 drm_mode_connector_update_edid_property(connector,
5159 edid);
5160 drm_edid_to_eld(connector, edid);
5161 } else {
5162 kfree(edid);
5163 edid = ERR_PTR(-EINVAL);
5164 }
5165 } else {
5166 edid = ERR_PTR(-ENOENT);
5167 }
5168 intel_connector->edid = edid;
5169
5170 /* prefer fixed mode from EDID if available */
5171 list_for_each_entry(scan, &connector->probed_modes, head) {
5172 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5173 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 5174 downclock_mode = intel_dp_drrs_init(
5175 intel_dig_port,
5176 intel_connector, fixed_mode);
ed92f0b2
PZ		 5177 break;
5178 }
5179 }
5180
5181 /* fallback to VBT if available for eDP */
5182 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5183 fixed_mode = drm_mode_duplicate(dev,
5184 dev_priv->vbt.lfp_lvds_vbt_mode);
5185 if (fixed_mode)
5186 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5187 }
060c8778 5188 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5189
01527b31
CT		 5190 if (IS_VALLEYVIEW(dev)) {
5191 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5192 register_reboot_notifier(&intel_dp->edp_notifier);
5193 }
5194
4f9db5b5 5195 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5196 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 5197 intel_panel_setup_backlight(connector);
5198
5199 return true;
5200}
5201
16c25533 5202bool
f0fec3f2
PZ		 5203intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5204 struct intel_connector *intel_connector)
a4fc5ed6 5205{
f0fec3f2
PZ		 5206 struct drm_connector *connector = &intel_connector->base;
5207 struct intel_dp *intel_dp = &intel_dig_port->dp;
5208 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5209 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5210 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5211 enum port port = intel_dig_port->port;
0b99836f 5212 int type;
a4fc5ed6 5213
a4a5d2f8
VS		 5214 intel_dp->pps_pipe = INVALID_PIPE;
5215
ec5b01dd 5216 /* intel_dp vfuncs */
b6b5e383
DL		 5217 if (INTEL_INFO(dev)->gen >= 9)
5218 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5219 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5220 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5221 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5222 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5223 else if (HAS_PCH_SPLIT(dev))
5224 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5225 else
5226 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5227
b9ca5fad
DL		 5228 if (INTEL_INFO(dev)->gen >= 9)
5229 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5230 else
5231 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5232
0767935e
DV		 5233 /* Preserve the current hw state. */
5234 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5235 intel_dp->attached_connector = intel_connector;
3d3dc149 5236
3b32a35b 5237 if (intel_dp_is_edp(dev, port))
b329530c 5238 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5239 else
5240 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5241
f7d24902
ID		 5242 /*
5243 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5244 * for DP the encoder type can be set by the caller to
5245 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5246 */
5247 if (type == DRM_MODE_CONNECTOR_eDP)
5248 intel_encoder->type = INTEL_OUTPUT_EDP;
5249
c17ed5b5
VS		 5250 /* eDP only on port B and/or C on vlv/chv */
5251 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5252 port != PORT_B && port != PORT_C))
5253 return false;
5254
e7281eab
ID		 5255 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5256 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5257 port_name(port));
5258
b329530c 5259 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5260 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5261
a4fc5ed6
KP		 5262 connector->interlace_allowed = true;
5263 connector->doublescan_allowed = 0;
5264
f0fec3f2 5265 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5266 edp_panel_vdd_work);
a4fc5ed6 5267
df0e9248 5268 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5269 drm_connector_register(connector);
a4fc5ed6 5270
affa9354 5271 if (HAS_DDI(dev))
bcbc889b
PZ		 5272 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5273 else
5274 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5275 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5276
0b99836f 5277 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5278 switch (port) {
5279 case PORT_A:
1d843f9d 5280 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5281 break;
5282 case PORT_B:
1d843f9d 5283 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5284 break;
5285 case PORT_C:
1d843f9d 5286 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5287 break;
5288 case PORT_D:
1d843f9d 5289 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5290 break;
5291 default:
ad1c0b19 5292 BUG();
5eb08b69
ZW		 5293 }
5294
dada1a9f 5295 if (is_edp(intel_dp)) {
773538e8 5296 pps_lock(intel_dp);
a4a5d2f8
VS		 5297 if (IS_VALLEYVIEW(dev)) {
5298 vlv_initial_power_sequencer_setup(intel_dp);
5299 } else {
5300 intel_dp_init_panel_power_timestamps(intel_dp);
36b5f425 5301 intel_dp_init_panel_power_sequencer(dev, intel_dp);
a4a5d2f8 5302 }
773538e8 5303 pps_unlock(intel_dp);
dada1a9f 5304 }
0095e6dc 5305
9d1a1031 5306 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5307
0e32b39c
DA		 5308 /* init MST on ports that can support it */
5309 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5310 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5311 intel_dp_mst_encoder_init(intel_dig_port,
5312 intel_connector->base.base.id);
0e32b39c
DA		 5313 }
5314 }
5315
36b5f425 5316 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5317 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5318 if (is_edp(intel_dp)) {
5319 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5320 /*
5321 * vdd might still be enabled do to the delayed vdd off.
5322 * Make sure vdd is actually turned off here.
5323 */
773538e8 5324 pps_lock(intel_dp);
4be73780 5325 edp_panel_vdd_off_sync(intel_dp);
773538e8 5326 pps_unlock(intel_dp);
15b1d171 5327 }
34ea3d38 5328 drm_connector_unregister(connector);
b2f246a8 5329 drm_connector_cleanup(connector);
16c25533 5330 return false;
b2f246a8 5331 }
32f9d658 5332
f684960e
CW		 5333 intel_dp_add_properties(intel_dp, connector);
5334
a4fc5ed6
KP		 5335 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5336 * 0xd. Failure to do so will result in spurious interrupts being
5337 * generated on the port when a cable is not attached.
5338 */
5339 if (IS_G4X(dev) && !IS_GM45(dev)) {
5340 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5341 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5342 }
16c25533
PZ		 5343
5344 return true;
a4fc5ed6 5345}
f0fec3f2
PZ		 5346
5347void
5348intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5349{
13cf5504 5350 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5351 struct intel_digital_port *intel_dig_port;
5352 struct intel_encoder *intel_encoder;
5353 struct drm_encoder *encoder;
5354 struct intel_connector *intel_connector;
5355
b14c5679 5356 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5357 if (!intel_dig_port)
5358 return;
5359
b14c5679 5360 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5361 if (!intel_connector) {
5362 kfree(intel_dig_port);
5363 return;
5364 }
5365
5366 intel_encoder = &intel_dig_port->base;
5367 encoder = &intel_encoder->base;
5368
5369 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5370 DRM_MODE_ENCODER_TMDS);
5371
5bfe2ac0 5372 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5373 intel_encoder->disable = intel_disable_dp;
00c09d70 5374 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5375 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5376 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5377 if (IS_CHERRYVIEW(dev)) {
9197c88b 5378 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5379 intel_encoder->pre_enable = chv_pre_enable_dp;
5380 intel_encoder->enable = vlv_enable_dp;
580d3811 5381 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5382 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5383 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5384 intel_encoder->pre_enable = vlv_pre_enable_dp;
5385 intel_encoder->enable = vlv_enable_dp;
49277c31 5386 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5387 } else {
ecff4f3b
JN		 5388 intel_encoder->pre_enable = g4x_pre_enable_dp;
5389 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5390 if (INTEL_INFO(dev)->gen >= 5)
5391 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5392 }
f0fec3f2 5393
174edf1f 5394 intel_dig_port->port = port;
f0fec3f2
PZ		 5395 intel_dig_port->dp.output_reg = output_reg;
5396
00c09d70 5397 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5398 if (IS_CHERRYVIEW(dev)) {
5399 if (port == PORT_D)
5400 intel_encoder->crtc_mask = 1 << 2;
5401 else
5402 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5403 } else {
5404 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5405 }
bc079e8b 5406 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5407 intel_encoder->hot_plug = intel_dp_hot_plug;
5408
13cf5504
DA		 5409 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5410 dev_priv->hpd_irq_port[port] = intel_dig_port;
5411
15b1d171
PZ		 5412 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5413 drm_encoder_cleanup(encoder);
5414 kfree(intel_dig_port);
b2f246a8 5415 kfree(intel_connector);
15b1d171 5416 }
f0fec3f2 5417}
0e32b39c
DA		 5418
5419void intel_dp_mst_suspend(struct drm_device *dev)
5420{
5421 struct drm_i915_private *dev_priv = dev->dev_private;
5422 int i;
5423
5424 /* disable MST */
5425 for (i = 0; i < I915_MAX_PORTS; i++) {
5426 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5427 if (!intel_dig_port)
5428 continue;
5429
5430 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5431 if (!intel_dig_port->dp.can_mst)
5432 continue;
5433 if (intel_dig_port->dp.is_mst)
5434 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5435 }
5436 }
5437}
5438
5439void intel_dp_mst_resume(struct drm_device *dev)
5440{
5441 struct drm_i915_private *dev_priv = dev->dev_private;
5442 int i;
5443
5444 for (i = 0; i < I915_MAX_PORTS; i++) {
5445 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5446 if (!intel_dig_port)
5447 continue;
5448 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5449 int ret;
5450
5451 if (!intel_dig_port->dp.can_mst)
5452 continue;
5453
5454 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5455 if (ret != 0) {
5456 intel_dp_check_mst_status(&intel_dig_port->dp);
5457 }
5458 }
5459 }
5460}
Linux kernel - Deliverables
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