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drm/i915: Split power sequencer panel on/off functions to locked and unlocked variants
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
5ca476f8 228pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 286 struct intel_dp *intel_dp);
bf13e81b
JN		 287static void
288intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 289 struct intel_dp *intel_dp);
bf13e81b 290
773538e8
VS		 291static void pps_lock(struct intel_dp *intel_dp)
292{
293 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
294 struct intel_encoder *encoder = &intel_dig_port->base;
295 struct drm_device *dev = encoder->base.dev;
296 struct drm_i915_private *dev_priv = dev->dev_private;
297 enum intel_display_power_domain power_domain;
298
299 /*
300 * See vlv_power_sequencer_reset() why we need
301 * a power domain reference here.
302 */
303 power_domain = intel_display_port_power_domain(encoder);
304 intel_display_power_get(dev_priv, power_domain);
305
306 mutex_lock(&dev_priv->pps_mutex);
307}
308
309static void pps_unlock(struct intel_dp *intel_dp)
310{
311 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
312 struct intel_encoder *encoder = &intel_dig_port->base;
313 struct drm_device *dev = encoder->base.dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315 enum intel_display_power_domain power_domain;
316
317 mutex_unlock(&dev_priv->pps_mutex);
318
319 power_domain = intel_display_port_power_domain(encoder);
320 intel_display_power_put(dev_priv, power_domain);
321}
322
bf13e81b
JN		 323static enum pipe
324vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
325{
326 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 327 struct drm_device *dev = intel_dig_port->base.base.dev;
328 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 329 struct intel_encoder *encoder;
330 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
bf13e81b 331
e39b999a 332 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 333
a4a5d2f8
VS		 334 if (intel_dp->pps_pipe != INVALID_PIPE)
335 return intel_dp->pps_pipe;
336
337 /*
338 * We don't have power sequencer currently.
339 * Pick one that's not used by other ports.
340 */
341 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
342 base.head) {
343 struct intel_dp *tmp;
344
345 if (encoder->type != INTEL_OUTPUT_EDP)
346 continue;
347
348 tmp = enc_to_intel_dp(&encoder->base);
349
350 if (tmp->pps_pipe != INVALID_PIPE)
351 pipes &= ~(1 << tmp->pps_pipe);
352 }
353
354 /*
355 * Didn't find one. This should not happen since there
356 * are two power sequencers and up to two eDP ports.
357 */
358 if (WARN_ON(pipes == 0))
359 return PIPE_A;
360
361 intel_dp->pps_pipe = ffs(pipes) - 1;
362
363 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
364 pipe_name(intel_dp->pps_pipe),
365 port_name(intel_dig_port->port));
366
367 /* init power sequencer on this pipe and port */
36b5f425
VS		 368 intel_dp_init_panel_power_sequencer(dev, intel_dp);
369 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 370
371 return intel_dp->pps_pipe;
372}
373
6491ab27
VS		 374typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
375 enum pipe pipe);
376
377static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
378 enum pipe pipe)
379{
380 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
381}
382
383static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
384 enum pipe pipe)
385{
386 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
387}
388
389static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
390 enum pipe pipe)
391{
392 return true;
393}
bf13e81b 394
a4a5d2f8 395static enum pipe
6491ab27
VS		 396vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
397 enum port port,
398 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 399{
400 enum pipe pipe;
bf13e81b 401
bf13e81b
JN		 402 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
403 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
404 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 405
406 if (port_sel != PANEL_PORT_SELECT_VLV(port))
407 continue;
408
6491ab27
VS		 409 if (!pipe_check(dev_priv, pipe))
410 continue;
411
a4a5d2f8 412 return pipe;
bf13e81b
JN		 413 }
414
a4a5d2f8
VS		 415 return INVALID_PIPE;
416}
417
418static void
419vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
420{
421 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
422 struct drm_device *dev = intel_dig_port->base.base.dev;
423 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 424 enum port port = intel_dig_port->port;
425
426 lockdep_assert_held(&dev_priv->pps_mutex);
427
428 /* try to find a pipe with this port selected */
6491ab27
VS		 429 /* first pick one where the panel is on */
430 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
431 vlv_pipe_has_pp_on);
432 /* didn't find one? pick one where vdd is on */
433 if (intel_dp->pps_pipe == INVALID_PIPE)
434 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
435 vlv_pipe_has_vdd_on);
436 /* didn't find one? pick one with just the correct port */
437 if (intel_dp->pps_pipe == INVALID_PIPE)
438 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
439 vlv_pipe_any);
a4a5d2f8
VS		 440
441 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
442 if (intel_dp->pps_pipe == INVALID_PIPE) {
443 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
444 port_name(port));
445 return;
bf13e81b
JN		 446 }
447
a4a5d2f8
VS		 448 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
449 port_name(port), pipe_name(intel_dp->pps_pipe));
450
36b5f425
VS		 451 intel_dp_init_panel_power_sequencer(dev, intel_dp);
452 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 453}
454
773538e8
VS		 455void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
456{
457 struct drm_device *dev = dev_priv->dev;
458 struct intel_encoder *encoder;
459
460 if (WARN_ON(!IS_VALLEYVIEW(dev)))
461 return;
462
463 /*
464 * We can't grab pps_mutex here due to deadlock with power_domain
465 * mutex when power_domain functions are called while holding pps_mutex.
466 * That also means that in order to use pps_pipe the code needs to
467 * hold both a power domain reference and pps_mutex, and the power domain
468 * reference get/put must be done while _not_ holding pps_mutex.
469 * pps_{lock,unlock}() do these steps in the correct order, so one
470 * should use them always.
471 */
472
473 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
474 struct intel_dp *intel_dp;
475
476 if (encoder->type != INTEL_OUTPUT_EDP)
477 continue;
478
479 intel_dp = enc_to_intel_dp(&encoder->base);
480 intel_dp->pps_pipe = INVALID_PIPE;
481 }
bf13e81b
JN		 482}
483
484static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
485{
486 struct drm_device *dev = intel_dp_to_dev(intel_dp);
487
488 if (HAS_PCH_SPLIT(dev))
489 return PCH_PP_CONTROL;
490 else
491 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
492}
493
494static u32 _pp_stat_reg(struct intel_dp *intel_dp)
495{
496 struct drm_device *dev = intel_dp_to_dev(intel_dp);
497
498 if (HAS_PCH_SPLIT(dev))
499 return PCH_PP_STATUS;
500 else
501 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
502}
503
01527b31
CT		 504/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
505 This function only applicable when panel PM state is not to be tracked */
506static int edp_notify_handler(struct notifier_block *this, unsigned long code,
507 void *unused)
508{
509 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
510 edp_notifier);
511 struct drm_device *dev = intel_dp_to_dev(intel_dp);
512 struct drm_i915_private *dev_priv = dev->dev_private;
513 u32 pp_div;
514 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 515
516 if (!is_edp(intel_dp) || code != SYS_RESTART)
517 return 0;
518
773538e8 519 pps_lock(intel_dp);
e39b999a 520
01527b31 521 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 522 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
523
01527b31
CT		 524 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
525 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
526 pp_div = I915_READ(pp_div_reg);
527 pp_div &= PP_REFERENCE_DIVIDER_MASK;
528
529 /* 0x1F write to PP_DIV_REG sets max cycle delay */
530 I915_WRITE(pp_div_reg, pp_div | 0x1F);
531 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
532 msleep(intel_dp->panel_power_cycle_delay);
533 }
534
773538e8 535 pps_unlock(intel_dp);
e39b999a 536
01527b31
CT		 537 return 0;
538}
539
4be73780 540static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 541{
30add22d 542 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 543 struct drm_i915_private *dev_priv = dev->dev_private;
544
e39b999a
VS		 545 lockdep_assert_held(&dev_priv->pps_mutex);
546
bf13e81b 547 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 548}
549
4be73780 550static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 551{
30add22d 552 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 553 struct drm_i915_private *dev_priv = dev->dev_private;
554
e39b999a
VS		 555 lockdep_assert_held(&dev_priv->pps_mutex);
556
773538e8 557 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 558}
559
9b984dae
KP		 560static void
561intel_dp_check_edp(struct intel_dp *intel_dp)
562{
30add22d 563 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 564 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 565
9b984dae
KP		 566 if (!is_edp(intel_dp))
567 return;
453c5420 568
4be73780 569 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 570 WARN(1, "eDP powered off while attempting aux channel communication.\n");
571 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 572 I915_READ(_pp_stat_reg(intel_dp)),
573 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 574 }
575}
576
9ee32fea
DV		 577static uint32_t
578intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
579{
580 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
581 struct drm_device *dev = intel_dig_port->base.base.dev;
582 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 583 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 584 uint32_t status;
585 bool done;
586
ef04f00d 587#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 588 if (has_aux_irq)
b18ac466 589 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 590 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 591 else
592 done = wait_for_atomic(C, 10) == 0;
593 if (!done)
594 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
595 has_aux_irq);
596#undef C
597
598 return status;
599}
600
ec5b01dd 601static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 602{
174edf1f
PZ		 603 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
604 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 605
ec5b01dd
DL		 606 /*
607 * The clock divider is based off the hrawclk, and would like to run at
608 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 609 */
ec5b01dd
DL		 610 return index ? 0 : intel_hrawclk(dev) / 2;
611}
612
613static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
614{
615 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
616 struct drm_device *dev = intel_dig_port->base.base.dev;
617
618 if (index)
619 return 0;
620
621 if (intel_dig_port->port == PORT_A) {
622 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 623 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 624 else
b84a1cf8 625 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 626 } else {
627 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
628 }
629}
630
631static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
632{
633 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
634 struct drm_device *dev = intel_dig_port->base.base.dev;
635 struct drm_i915_private *dev_priv = dev->dev_private;
636
637 if (intel_dig_port->port == PORT_A) {
638 if (index)
639 return 0;
640 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 641 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
642 /* Workaround for non-ULT HSW */
bc86625a
CW		 643 switch (index) {
644 case 0: return 63;
645 case 1: return 72;
646 default: return 0;
647 }
ec5b01dd 648 } else {
bc86625a 649 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 650 }
b84a1cf8
RV		 651}
652
ec5b01dd
DL		 653static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
654{
655 return index ? 0 : 100;
656}
657
b6b5e383
DL		 658static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
659{
660 /*
661 * SKL doesn't need us to program the AUX clock divider (Hardware will
662 * derive the clock from CDCLK automatically). We still implement the
663 * get_aux_clock_divider vfunc to plug-in into the existing code.
664 */
665 return index ? 0 : 1;
666}
667
5ed12a19
DL		 668static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
669 bool has_aux_irq,
670 int send_bytes,
671 uint32_t aux_clock_divider)
672{
673 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
674 struct drm_device *dev = intel_dig_port->base.base.dev;
675 uint32_t precharge, timeout;
676
677 if (IS_GEN6(dev))
678 precharge = 3;
679 else
680 precharge = 5;
681
682 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
683 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
684 else
685 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
686
687 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 688 DP_AUX_CH_CTL_DONE |
5ed12a19 689 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 690 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 691 timeout |
788d4433 692 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 693 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
694 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 695 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 696}
697
b9ca5fad
DL		 698static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
699 bool has_aux_irq,
700 int send_bytes,
701 uint32_t unused)
702{
703 return DP_AUX_CH_CTL_SEND_BUSY |
704 DP_AUX_CH_CTL_DONE |
705 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
706 DP_AUX_CH_CTL_TIME_OUT_ERROR |
707 DP_AUX_CH_CTL_TIME_OUT_1600us |
708 DP_AUX_CH_CTL_RECEIVE_ERROR |
709 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
710 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
711}
712
b84a1cf8
RV		 713static int
714intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 715 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 716 uint8_t *recv, int recv_size)
717{
718 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
719 struct drm_device *dev = intel_dig_port->base.base.dev;
720 struct drm_i915_private *dev_priv = dev->dev_private;
721 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
722 uint32_t ch_data = ch_ctl + 4;
bc86625a 723 uint32_t aux_clock_divider;
b84a1cf8
RV		 724 int i, ret, recv_bytes;
725 uint32_t status;
5ed12a19 726 int try, clock = 0;
4e6b788c 727 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 728 bool vdd;
729
773538e8 730 pps_lock(intel_dp);
e39b999a 731
72c3500a
VS		 732 /*
733 * We will be called with VDD already enabled for dpcd/edid/oui reads.
734 * In such cases we want to leave VDD enabled and it's up to upper layers
735 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
736 * ourselves.
737 */
1e0560e0 738 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 739
740 /* dp aux is extremely sensitive to irq latency, hence request the
741 * lowest possible wakeup latency and so prevent the cpu from going into
742 * deep sleep states.
743 */
744 pm_qos_update_request(&dev_priv->pm_qos, 0);
745
746 intel_dp_check_edp(intel_dp);
5eb08b69 747
c67a470b
PZ		 748 intel_aux_display_runtime_get(dev_priv);
749
11bee43e
JB		 750 /* Try to wait for any previous AUX channel activity */
751 for (try = 0; try < 3; try++) {
ef04f00d 752 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 753 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
754 break;
755 msleep(1);
756 }
757
758 if (try == 3) {
759 WARN(1, "dp_aux_ch not started status 0x%08x\n",
760 I915_READ(ch_ctl));
9ee32fea
DV		 761 ret = -EBUSY;
762 goto out;
4f7f7b7e
CW		 763 }
764
46a5ae9f
PZ		 765 /* Only 5 data registers! */
766 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
767 ret = -E2BIG;
768 goto out;
769 }
770
ec5b01dd 771 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 772 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
773 has_aux_irq,
774 send_bytes,
775 aux_clock_divider);
5ed12a19 776
bc86625a
CW		 777 /* Must try at least 3 times according to DP spec */
778 for (try = 0; try < 5; try++) {
779 /* Load the send data into the aux channel data registers */
780 for (i = 0; i < send_bytes; i += 4)
781 I915_WRITE(ch_data + i,
782 pack_aux(send + i, send_bytes - i));
783
784 /* Send the command and wait for it to complete */
5ed12a19 785 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 786
787 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
788
789 /* Clear done status and any errors */
790 I915_WRITE(ch_ctl,
791 status |
792 DP_AUX_CH_CTL_DONE |
793 DP_AUX_CH_CTL_TIME_OUT_ERROR |
794 DP_AUX_CH_CTL_RECEIVE_ERROR);
795
796 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
797 DP_AUX_CH_CTL_RECEIVE_ERROR))
798 continue;
799 if (status & DP_AUX_CH_CTL_DONE)
800 break;
801 }
4f7f7b7e 802 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 803 break;
804 }
805
a4fc5ed6 806 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 807 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 808 ret = -EBUSY;
809 goto out;
a4fc5ed6
KP		 810 }
811
812 /* Check for timeout or receive error.
813 * Timeouts occur when the sink is not connected
814 */
a5b3da54 815 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 816 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 817 ret = -EIO;
818 goto out;
a5b3da54 819 }
1ae8c0a5
KP		 820
821 /* Timeouts occur when the device isn't connected, so they're
822 * "normal" -- don't fill the kernel log with these */
a5b3da54 823 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 824 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 825 ret = -ETIMEDOUT;
826 goto out;
a4fc5ed6
KP		 827 }
828
829 /* Unload any bytes sent back from the other side */
830 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
831 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 832 if (recv_bytes > recv_size)
833 recv_bytes = recv_size;
0206e353 834
4f7f7b7e
CW		 835 for (i = 0; i < recv_bytes; i += 4)
836 unpack_aux(I915_READ(ch_data + i),
837 recv + i, recv_bytes - i);
a4fc5ed6 838
9ee32fea
DV		 839 ret = recv_bytes;
840out:
841 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 842 intel_aux_display_runtime_put(dev_priv);
9ee32fea 843
884f19e9
JN		 844 if (vdd)
845 edp_panel_vdd_off(intel_dp, false);
846
773538e8 847 pps_unlock(intel_dp);
e39b999a 848
9ee32fea 849 return ret;
a4fc5ed6
KP		 850}
851
a6c8aff0
JN		 852#define BARE_ADDRESS_SIZE 3
853#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 854static ssize_t
855intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 856{
9d1a1031
JN		 857 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
858 uint8_t txbuf[20], rxbuf[20];
859 size_t txsize, rxsize;
a4fc5ed6 860 int ret;
a4fc5ed6 861
9d1a1031
JN		 862 txbuf[0] = msg->request << 4;
863 txbuf[1] = msg->address >> 8;
864 txbuf[2] = msg->address & 0xff;
865 txbuf[3] = msg->size - 1;
46a5ae9f 866
9d1a1031
JN		 867 switch (msg->request & ~DP_AUX_I2C_MOT) {
868 case DP_AUX_NATIVE_WRITE:
869 case DP_AUX_I2C_WRITE:
a6c8aff0 870 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 871 rxsize = 1;
f51a44b9 872
9d1a1031
JN		 873 if (WARN_ON(txsize > 20))
874 return -E2BIG;
a4fc5ed6 875
9d1a1031 876 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 877
9d1a1031
JN		 878 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
879 if (ret > 0) {
880 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 881
9d1a1031
JN		 882 /* Return payload size. */
883 ret = msg->size;
884 }
885 break;
46a5ae9f 886
9d1a1031
JN		 887 case DP_AUX_NATIVE_READ:
888 case DP_AUX_I2C_READ:
a6c8aff0 889 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 890 rxsize = msg->size + 1;
a4fc5ed6 891
9d1a1031
JN		 892 if (WARN_ON(rxsize > 20))
893 return -E2BIG;
a4fc5ed6 894
9d1a1031
JN		 895 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
896 if (ret > 0) {
897 msg->reply = rxbuf[0] >> 4;
898 /*
899 * Assume happy day, and copy the data. The caller is
900 * expected to check msg->reply before touching it.
901 *
902 * Return payload size.
903 */
904 ret--;
905 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 906 }
9d1a1031
JN		 907 break;
908
909 default:
910 ret = -EINVAL;
911 break;
a4fc5ed6 912 }
f51a44b9 913
9d1a1031 914 return ret;
a4fc5ed6
KP		 915}
916
9d1a1031
JN		 917static void
918intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
919{
920 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 921 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
922 enum port port = intel_dig_port->port;
0b99836f 923 const char *name = NULL;
ab2c0672
DA		 924 int ret;
925
33ad6626
JN		 926 switch (port) {
927 case PORT_A:
928 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 929 name = "DPDDC-A";
ab2c0672 930 break;
33ad6626
JN		 931 case PORT_B:
932 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 933 name = "DPDDC-B";
ab2c0672 934 break;
33ad6626
JN		 935 case PORT_C:
936 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 937 name = "DPDDC-C";
ab2c0672 938 break;
33ad6626
JN		 939 case PORT_D:
940 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 941 name = "DPDDC-D";
33ad6626
JN		 942 break;
943 default:
944 BUG();
ab2c0672
DA		 945 }
946
1b1aad75
DL		 947 /*
948 * The AUX_CTL register is usually DP_CTL + 0x10.
949 *
950 * On Haswell and Broadwell though:
951 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
952 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
953 *
954 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
955 */
956 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 957 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 958
0b99836f 959 intel_dp->aux.name = name;
9d1a1031
JN		 960 intel_dp->aux.dev = dev->dev;
961 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 962
0b99836f
JN		 963 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
964 connector->base.kdev->kobj.name);
8316f337 965
4f71d0cb 966 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 967 if (ret < 0) {
4f71d0cb 968 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 969 name, ret);
970 return;
ab2c0672 971 }
8a5e6aeb 972
0b99836f
JN		 973 ret = sysfs_create_link(&connector->base.kdev->kobj,
974 &intel_dp->aux.ddc.dev.kobj,
975 intel_dp->aux.ddc.dev.kobj.name);
976 if (ret < 0) {
977 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 978 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 979 }
a4fc5ed6
KP		 980}
981
80f65de3
ID		 982static void
983intel_dp_connector_unregister(struct intel_connector *intel_connector)
984{
985 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
986
0e32b39c
DA		 987 if (!intel_connector->mst_port)
988 sysfs_remove_link(&intel_connector->base.kdev->kobj,
989 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 990 intel_connector_unregister(intel_connector);
991}
992
0e50338c
DV		 993static void
994hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
995{
996 switch (link_bw) {
997 case DP_LINK_BW_1_62:
998 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
999 break;
1000 case DP_LINK_BW_2_7:
1001 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1002 break;
1003 case DP_LINK_BW_5_4:
1004 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1005 break;
1006 }
1007}
1008
c6bb3538
DV		 1009static void
1010intel_dp_set_clock(struct intel_encoder *encoder,
1011 struct intel_crtc_config *pipe_config, int link_bw)
1012{
1013 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1014 const struct dp_link_dpll *divisor = NULL;
1015 int i, count = 0;
c6bb3538
DV		 1016
1017 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1018 divisor = gen4_dpll;
1019 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1020 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1021 divisor = pch_dpll;
1022 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1023 } else if (IS_CHERRYVIEW(dev)) {
1024 divisor = chv_dpll;
1025 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1026 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1027 divisor = vlv_dpll;
1028 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1029 }
9dd4ffdf
CML		 1030
1031 if (divisor && count) {
1032 for (i = 0; i < count; i++) {
1033 if (link_bw == divisor[i].link_bw) {
1034 pipe_config->dpll = divisor[i].dpll;
1035 pipe_config->clock_set = true;
1036 break;
1037 }
1038 }
c6bb3538
DV		 1039 }
1040}
1041
00c09d70 1042bool
5bfe2ac0
DV		 1043intel_dp_compute_config(struct intel_encoder *encoder,
1044 struct intel_crtc_config *pipe_config)
a4fc5ed6 1045{
5bfe2ac0 1046 struct drm_device *dev = encoder->base.dev;
36008365 1047 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1048 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1049 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1050 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1051 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1052 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1053 int lane_count, clock;
56071a20 1054 int min_lane_count = 1;
eeb6324d 1055 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1056 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1057 int min_clock = 0;
06ea66b6 1058 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1059 int bpp, mode_rate;
06ea66b6 1060 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1061 int link_avail, link_clock;
a4fc5ed6 1062
bc7d38a4 1063 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1064 pipe_config->has_pch_encoder = true;
1065
03afc4a2 1066 pipe_config->has_dp_encoder = true;
f769cd24 1067 pipe_config->has_drrs = false;
9ed109a7 1068 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1069
dd06f90e
JN		 1070 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1071 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1072 adjusted_mode);
2dd24552
JB		 1073 if (!HAS_PCH_SPLIT(dev))
1074 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1075 intel_connector->panel.fitting_mode);
1076 else
b074cec8
JB		 1077 intel_pch_panel_fitting(intel_crtc, pipe_config,
1078 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1079 }
1080
cb1793ce 1081 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1082 return false;
1083
083f9560
DV		 1084 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1085 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1086 max_lane_count, bws[max_clock],
1087 adjusted_mode->crtc_clock);
083f9560 1088
36008365
DV		 1089 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1090 * bpc in between. */
3e7ca985 1091 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1092 if (is_edp(intel_dp)) {
1093 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1094 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1095 dev_priv->vbt.edp_bpp);
1096 bpp = dev_priv->vbt.edp_bpp;
1097 }
1098
344c5bbc
JN		 1099 /*
1100 * Use the maximum clock and number of lanes the eDP panel
1101 * advertizes being capable of. The panels are generally
1102 * designed to support only a single clock and lane
1103 * configuration, and typically these values correspond to the
1104 * native resolution of the panel.
1105 */
1106 min_lane_count = max_lane_count;
1107 min_clock = max_clock;
7984211e 1108 }
657445fe 1109
36008365 1110 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1111 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1112 bpp);
36008365 1113
c6930992
DA		 1114 for (clock = min_clock; clock <= max_clock; clock++) {
1115 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1116 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1117 link_avail = intel_dp_max_data_rate(link_clock,
1118 lane_count);
1119
1120 if (mode_rate <= link_avail) {
1121 goto found;
1122 }
1123 }
1124 }
1125 }
c4867936 1126
36008365 1127 return false;
3685a8f3 1128
36008365 1129found:
55bc60db
VS		 1130 if (intel_dp->color_range_auto) {
1131 /*
1132 * See:
1133 * CEA-861-E - 5.1 Default Encoding Parameters
1134 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1135 */
18316c8c 1136 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1137 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1138 else
1139 intel_dp->color_range = 0;
1140 }
1141
3685a8f3 1142 if (intel_dp->color_range)
50f3b016 1143 pipe_config->limited_color_range = true;
a4fc5ed6 1144
36008365
DV		 1145 intel_dp->link_bw = bws[clock];
1146 intel_dp->lane_count = lane_count;
657445fe 1147 pipe_config->pipe_bpp = bpp;
ff9a6750 1148 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1149
36008365
DV		 1150 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1151 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1152 pipe_config->port_clock, bpp);
36008365
DV		 1153 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1154 mode_rate, link_avail);
a4fc5ed6 1155
03afc4a2 1156 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1157 adjusted_mode->crtc_clock,
1158 pipe_config->port_clock,
03afc4a2 1159 &pipe_config->dp_m_n);
9d1a455b 1160
439d7ac0
PB		 1161 if (intel_connector->panel.downclock_mode != NULL &&
1162 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1163 pipe_config->has_drrs = true;
439d7ac0
PB		 1164 intel_link_compute_m_n(bpp, lane_count,
1165 intel_connector->panel.downclock_mode->clock,
1166 pipe_config->port_clock,
1167 &pipe_config->dp_m2_n2);
1168 }
1169
ea155f32 1170 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1171 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1172 else
1173 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1174
03afc4a2 1175 return true;
a4fc5ed6
KP		 1176}
1177
7c62a164 1178static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1179{
7c62a164
DV		 1180 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1181 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1182 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1183 struct drm_i915_private *dev_priv = dev->dev_private;
1184 u32 dpa_ctl;
1185
ff9a6750 1186 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1187 dpa_ctl = I915_READ(DP_A);
1188 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1189
ff9a6750 1190 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1191 /* For a long time we've carried around a ILK-DevA w/a for the
1192 * 160MHz clock. If we're really unlucky, it's still required.
1193 */
1194 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1195 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1196 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1197 } else {
1198 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1199 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1200 }
1ce17038 1201
ea9b6006
DV		 1202 I915_WRITE(DP_A, dpa_ctl);
1203
1204 POSTING_READ(DP_A);
1205 udelay(500);
1206}
1207
8ac33ed3 1208static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1209{
b934223d 1210 struct drm_device *dev = encoder->base.dev;
417e822d 1211 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1212 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1213 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1214 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1215 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1216
417e822d 1217 /*
1a2eb460 1218 * There are four kinds of DP registers:
417e822d
KP		 1219 *
1220 * IBX PCH
1a2eb460
KP		 1221 * SNB CPU
1222 * IVB CPU
417e822d
KP		 1223 * CPT PCH
1224 *
1225 * IBX PCH and CPU are the same for almost everything,
1226 * except that the CPU DP PLL is configured in this
1227 * register
1228 *
1229 * CPT PCH is quite different, having many bits moved
1230 * to the TRANS_DP_CTL register instead. That
1231 * configuration happens (oddly) in ironlake_pch_enable
1232 */
9c9e7927 1233
417e822d
KP		 1234 /* Preserve the BIOS-computed detected bit. This is
1235 * supposed to be read-only.
1236 */
1237 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1238
417e822d 1239 /* Handle DP bits in common between all three register formats */
417e822d 1240 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1241 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1242
9ed109a7 1243 if (crtc->config.has_audio) {
e0dac65e 1244 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1245 pipe_name(crtc->pipe));
ea5b213a 1246 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
33d1e7c6 1247 intel_write_eld(encoder);
e0dac65e 1248 }
247d89f6 1249
417e822d 1250 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1251
bc7d38a4 1252 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1253 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1254 intel_dp->DP |= DP_SYNC_HS_HIGH;
1255 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1256 intel_dp->DP |= DP_SYNC_VS_HIGH;
1257 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1258
6aba5b6c 1259 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1260 intel_dp->DP |= DP_ENHANCED_FRAMING;
1261
7c62a164 1262 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1263 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1264 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1265 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1266
1267 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1268 intel_dp->DP |= DP_SYNC_HS_HIGH;
1269 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1270 intel_dp->DP |= DP_SYNC_VS_HIGH;
1271 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1272
6aba5b6c 1273 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1274 intel_dp->DP |= DP_ENHANCED_FRAMING;
1275
44f37d1f
CML		 1276 if (!IS_CHERRYVIEW(dev)) {
1277 if (crtc->pipe == 1)
1278 intel_dp->DP |= DP_PIPEB_SELECT;
1279 } else {
1280 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1281 }
417e822d
KP		 1282 } else {
1283 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1284 }
a4fc5ed6
KP		 1285}
1286
ffd6749d
PZ		 1287#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1288#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1289
1a5ef5b7
PZ		 1290#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1291#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1292
ffd6749d
PZ		 1293#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1294#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1295
4be73780 1296static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1297 u32 mask,
1298 u32 value)
bd943159 1299{
30add22d 1300 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1301 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1302 u32 pp_stat_reg, pp_ctrl_reg;
1303
e39b999a
VS		 1304 lockdep_assert_held(&dev_priv->pps_mutex);
1305
bf13e81b
JN		 1306 pp_stat_reg = _pp_stat_reg(intel_dp);
1307 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1308
99ea7127 1309 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1310 mask, value,
1311 I915_READ(pp_stat_reg),
1312 I915_READ(pp_ctrl_reg));
32ce697c 1313
453c5420 1314 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1315 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1316 I915_READ(pp_stat_reg),
1317 I915_READ(pp_ctrl_reg));
32ce697c 1318 }
54c136d4
CW		 1319
1320 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1321}
32ce697c 1322
4be73780 1323static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1324{
1325 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1326 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1327}
1328
4be73780 1329static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1330{
1331 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1332 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1333}
1334
4be73780 1335static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1336{
1337 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1338
1339 /* When we disable the VDD override bit last we have to do the manual
1340 * wait. */
1341 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1342 intel_dp->panel_power_cycle_delay);
1343
4be73780 1344 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1345}
1346
4be73780 1347static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1348{
1349 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1350 intel_dp->backlight_on_delay);
1351}
1352
4be73780 1353static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1354{
1355 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1356 intel_dp->backlight_off_delay);
1357}
99ea7127 1358
832dd3c1
KP		 1359/* Read the current pp_control value, unlocking the register if it
1360 * is locked
1361 */
1362
453c5420 1363static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1364{
453c5420
JB		 1365 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 u32 control;
832dd3c1 1368
e39b999a
VS		 1369 lockdep_assert_held(&dev_priv->pps_mutex);
1370
bf13e81b 1371 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1372 control &= ~PANEL_UNLOCK_MASK;
1373 control |= PANEL_UNLOCK_REGS;
1374 return control;
bd943159
KP		 1375}
1376
951468f3
VS		 1377/*
1378 * Must be paired with edp_panel_vdd_off().
1379 * Must hold pps_mutex around the whole on/off sequence.
1380 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1381 */
1e0560e0 1382static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1383{
30add22d 1384 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1385 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1386 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1387 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1388 enum intel_display_power_domain power_domain;
5d613501 1389 u32 pp;
453c5420 1390 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1391 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1392
e39b999a
VS		 1393 lockdep_assert_held(&dev_priv->pps_mutex);
1394
97af61f5 1395 if (!is_edp(intel_dp))
adddaaf4 1396 return false;
bd943159
KP		 1397
1398 intel_dp->want_panel_vdd = true;
99ea7127 1399
4be73780 1400 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1401 return need_to_disable;
b0665d57 1402
4e6e1a54
ID		 1403 power_domain = intel_display_port_power_domain(intel_encoder);
1404 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1405
b0665d57 1406 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1407
4be73780
DV		 1408 if (!edp_have_panel_power(intel_dp))
1409 wait_panel_power_cycle(intel_dp);
99ea7127 1410
453c5420 1411 pp = ironlake_get_pp_control(intel_dp);
5d613501 1412 pp |= EDP_FORCE_VDD;
ebf33b18 1413
bf13e81b
JN		 1414 pp_stat_reg = _pp_stat_reg(intel_dp);
1415 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1416
1417 I915_WRITE(pp_ctrl_reg, pp);
1418 POSTING_READ(pp_ctrl_reg);
1419 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1420 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1421 /*
1422 * If the panel wasn't on, delay before accessing aux channel
1423 */
4be73780 1424 if (!edp_have_panel_power(intel_dp)) {
bd943159 1425 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1426 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1427 }
adddaaf4
JN		 1428
1429 return need_to_disable;
1430}
1431
951468f3
VS		 1432/*
1433 * Must be paired with intel_edp_panel_vdd_off() or
1434 * intel_edp_panel_off().
1435 * Nested calls to these functions are not allowed since
1436 * we drop the lock. Caller must use some higher level
1437 * locking to prevent nested calls from other threads.
1438 */
b80d6c78 1439void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1440{
c695b6b6 1441 bool vdd;
adddaaf4 1442
c695b6b6
VS		 1443 if (!is_edp(intel_dp))
1444 return;
1445
773538e8 1446 pps_lock(intel_dp);
c695b6b6 1447 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1448 pps_unlock(intel_dp);
c695b6b6
VS		 1449
1450 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1451}
1452
4be73780 1453static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1454{
30add22d 1455 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1456 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1457 struct intel_digital_port *intel_dig_port =
1458 dp_to_dig_port(intel_dp);
1459 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1460 enum intel_display_power_domain power_domain;
5d613501 1461 u32 pp;
453c5420 1462 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1463
e39b999a 1464 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1465
15e899a0 1466 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1467
15e899a0 1468 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1469 return;
b0665d57 1470
be2c9196 1471 DRM_DEBUG_KMS("Turning eDP VDD off\n");
bd943159 1472
be2c9196
VS		 1473 pp = ironlake_get_pp_control(intel_dp);
1474 pp &= ~EDP_FORCE_VDD;
453c5420 1475
be2c9196
VS		 1476 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1477 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1478
be2c9196
VS		 1479 I915_WRITE(pp_ctrl_reg, pp);
1480 POSTING_READ(pp_ctrl_reg);
90791a5c 1481
be2c9196
VS		 1482 /* Make sure sequencer is idle before allowing subsequent activity */
1483 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1484 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1485
be2c9196
VS		 1486 if ((pp & POWER_TARGET_ON) == 0)
1487 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1488
be2c9196
VS		 1489 power_domain = intel_display_port_power_domain(intel_encoder);
1490 intel_display_power_put(dev_priv, power_domain);
bd943159 1491}
5d613501 1492
4be73780 1493static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1494{
1495 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1496 struct intel_dp, panel_vdd_work);
bd943159 1497
773538e8 1498 pps_lock(intel_dp);
15e899a0
VS		 1499 if (!intel_dp->want_panel_vdd)
1500 edp_panel_vdd_off_sync(intel_dp);
773538e8 1501 pps_unlock(intel_dp);
bd943159
KP		 1502}
1503
aba86890
ID		 1504static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1505{
1506 unsigned long delay;
1507
1508 /*
1509 * Queue the timer to fire a long time from now (relative to the power
1510 * down delay) to keep the panel power up across a sequence of
1511 * operations.
1512 */
1513 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1514 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1515}
1516
951468f3
VS		 1517/*
1518 * Must be paired with edp_panel_vdd_on().
1519 * Must hold pps_mutex around the whole on/off sequence.
1520 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1521 */
4be73780 1522static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1523{
e39b999a
VS		 1524 struct drm_i915_private *dev_priv =
1525 intel_dp_to_dev(intel_dp)->dev_private;
1526
1527 lockdep_assert_held(&dev_priv->pps_mutex);
1528
97af61f5
KP		 1529 if (!is_edp(intel_dp))
1530 return;
5d613501 1531
bd943159 1532 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1533
bd943159
KP		 1534 intel_dp->want_panel_vdd = false;
1535
aba86890 1536 if (sync)
4be73780 1537 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1538 else
1539 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1540}
1541
951468f3
VS		 1542/*
1543 * Must be paired with intel_edp_panel_vdd_on().
1544 * Nested calls to these functions are not allowed since
1545 * we drop the lock. Caller must use some higher level
1546 * locking to prevent nested calls from other threads.
1547 */
1e0560e0
VS		 1548static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1549{
e39b999a
VS		 1550 if (!is_edp(intel_dp))
1551 return;
1552
773538e8 1553 pps_lock(intel_dp);
1e0560e0 1554 edp_panel_vdd_off(intel_dp, sync);
773538e8 1555 pps_unlock(intel_dp);
1e0560e0
VS		 1556}
1557
9f0fb5be 1558static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1559{
30add22d 1560 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1561 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1562 u32 pp;
453c5420 1563 u32 pp_ctrl_reg;
9934c132 1564
9f0fb5be
VS		 1565 lockdep_assert_held(&dev_priv->pps_mutex);
1566
97af61f5 1567 if (!is_edp(intel_dp))
bd943159 1568 return;
99ea7127
KP		 1569
1570 DRM_DEBUG_KMS("Turn eDP power on\n");
1571
4be73780 1572 if (edp_have_panel_power(intel_dp)) {
99ea7127 1573 DRM_DEBUG_KMS("eDP power already on\n");
9f0fb5be 1574 return;
99ea7127 1575 }
9934c132 1576
4be73780 1577 wait_panel_power_cycle(intel_dp);
37c6c9b0 1578
bf13e81b 1579 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1580 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1581 if (IS_GEN5(dev)) {
1582 /* ILK workaround: disable reset around power sequence */
1583 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1584 I915_WRITE(pp_ctrl_reg, pp);
1585 POSTING_READ(pp_ctrl_reg);
05ce1a49 1586 }
37c6c9b0 1587
1c0ae80a 1588 pp |= POWER_TARGET_ON;
99ea7127
KP		 1589 if (!IS_GEN5(dev))
1590 pp |= PANEL_POWER_RESET;
1591
453c5420
JB		 1592 I915_WRITE(pp_ctrl_reg, pp);
1593 POSTING_READ(pp_ctrl_reg);
9934c132 1594
4be73780 1595 wait_panel_on(intel_dp);
dce56b3c 1596 intel_dp->last_power_on = jiffies;
9934c132 1597
05ce1a49
KP		 1598 if (IS_GEN5(dev)) {
1599 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1600 I915_WRITE(pp_ctrl_reg, pp);
1601 POSTING_READ(pp_ctrl_reg);
05ce1a49 1602 }
9f0fb5be 1603}
e39b999a 1604
9f0fb5be
VS		 1605void intel_edp_panel_on(struct intel_dp *intel_dp)
1606{
1607 if (!is_edp(intel_dp))
1608 return;
1609
1610 pps_lock(intel_dp);
1611 edp_panel_on(intel_dp);
773538e8 1612 pps_unlock(intel_dp);
9934c132
JB		 1613}
1614
9f0fb5be
VS		 1615
1616static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1617{
4e6e1a54
ID		 1618 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1619 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1620 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1621 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1622 enum intel_display_power_domain power_domain;
99ea7127 1623 u32 pp;
453c5420 1624 u32 pp_ctrl_reg;
9934c132 1625
9f0fb5be
VS		 1626 lockdep_assert_held(&dev_priv->pps_mutex);
1627
97af61f5
KP		 1628 if (!is_edp(intel_dp))
1629 return;
37c6c9b0 1630
99ea7127 1631 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1632
24f3e092
JN		 1633 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1634
453c5420 1635 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1636 /* We need to switch off panel power _and_ force vdd, for otherwise some
1637 * panels get very unhappy and cease to work. */
b3064154
PJ		 1638 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1639 EDP_BLC_ENABLE);
453c5420 1640
bf13e81b 1641 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1642
849e39f5
PZ		 1643 intel_dp->want_panel_vdd = false;
1644
453c5420
JB		 1645 I915_WRITE(pp_ctrl_reg, pp);
1646 POSTING_READ(pp_ctrl_reg);
9934c132 1647
dce56b3c 1648 intel_dp->last_power_cycle = jiffies;
4be73780 1649 wait_panel_off(intel_dp);
849e39f5
PZ		 1650
1651 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1652 power_domain = intel_display_port_power_domain(intel_encoder);
1653 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1654}
e39b999a 1655
9f0fb5be
VS		 1656void intel_edp_panel_off(struct intel_dp *intel_dp)
1657{
1658 if (!is_edp(intel_dp))
1659 return;
1660
1661 pps_lock(intel_dp);
1662 edp_panel_off(intel_dp);
773538e8 1663 pps_unlock(intel_dp);
9934c132
JB		 1664}
1665
1250d107
JN		 1666/* Enable backlight in the panel power control. */
1667static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1668{
da63a9f2
PZ		 1669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1670 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1671 struct drm_i915_private *dev_priv = dev->dev_private;
1672 u32 pp;
453c5420 1673 u32 pp_ctrl_reg;
32f9d658 1674
01cb9ea6
JB		 1675 /*
1676 * If we enable the backlight right away following a panel power
1677 * on, we may see slight flicker as the panel syncs with the eDP
1678 * link. So delay a bit to make sure the image is solid before
1679 * allowing it to appear.
1680 */
4be73780 1681 wait_backlight_on(intel_dp);
e39b999a 1682
773538e8 1683 pps_lock(intel_dp);
e39b999a 1684
453c5420 1685 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1686 pp |= EDP_BLC_ENABLE;
453c5420 1687
bf13e81b 1688 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1689
1690 I915_WRITE(pp_ctrl_reg, pp);
1691 POSTING_READ(pp_ctrl_reg);
e39b999a 1692
773538e8 1693 pps_unlock(intel_dp);
32f9d658
ZW		 1694}
1695
1250d107
JN		 1696/* Enable backlight PWM and backlight PP control. */
1697void intel_edp_backlight_on(struct intel_dp *intel_dp)
1698{
1699 if (!is_edp(intel_dp))
1700 return;
1701
1702 DRM_DEBUG_KMS("\n");
1703
1704 intel_panel_enable_backlight(intel_dp->attached_connector);
1705 _intel_edp_backlight_on(intel_dp);
1706}
1707
1708/* Disable backlight in the panel power control. */
1709static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1710{
30add22d 1711 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1712 struct drm_i915_private *dev_priv = dev->dev_private;
1713 u32 pp;
453c5420 1714 u32 pp_ctrl_reg;
32f9d658 1715
f01eca2e
KP		 1716 if (!is_edp(intel_dp))
1717 return;
1718
773538e8 1719 pps_lock(intel_dp);
e39b999a 1720
453c5420 1721 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1722 pp &= ~EDP_BLC_ENABLE;
453c5420 1723
bf13e81b 1724 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1725
1726 I915_WRITE(pp_ctrl_reg, pp);
1727 POSTING_READ(pp_ctrl_reg);
f7d2323c 1728
773538e8 1729 pps_unlock(intel_dp);
e39b999a
VS		 1730
1731 intel_dp->last_backlight_off = jiffies;
f7d2323c 1732 edp_wait_backlight_off(intel_dp);
1250d107 1733}
f7d2323c 1734
1250d107
JN		 1735/* Disable backlight PP control and backlight PWM. */
1736void intel_edp_backlight_off(struct intel_dp *intel_dp)
1737{
1738 if (!is_edp(intel_dp))
1739 return;
1740
1741 DRM_DEBUG_KMS("\n");
f7d2323c 1742
1250d107 1743 _intel_edp_backlight_off(intel_dp);
f7d2323c 1744 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1745}
a4fc5ed6 1746
73580fb7
JN		 1747/*
1748 * Hook for controlling the panel power control backlight through the bl_power
1749 * sysfs attribute. Take care to handle multiple calls.
1750 */
1751static void intel_edp_backlight_power(struct intel_connector *connector,
1752 bool enable)
1753{
1754 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1755 bool is_enabled;
1756
773538e8 1757 pps_lock(intel_dp);
e39b999a 1758 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1759 pps_unlock(intel_dp);
73580fb7
JN		 1760
1761 if (is_enabled == enable)
1762 return;
1763
23ba9373
JN		 1764 DRM_DEBUG_KMS("panel power control backlight %s\n",
1765 enable ? "enable" : "disable");
73580fb7
JN		 1766
1767 if (enable)
1768 _intel_edp_backlight_on(intel_dp);
1769 else
1770 _intel_edp_backlight_off(intel_dp);
1771}
1772
2bd2ad64 1773static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1774{
da63a9f2
PZ		 1775 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1776 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1777 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1778 struct drm_i915_private *dev_priv = dev->dev_private;
1779 u32 dpa_ctl;
1780
2bd2ad64
DV		 1781 assert_pipe_disabled(dev_priv,
1782 to_intel_crtc(crtc)->pipe);
1783
d240f20f
JB		 1784 DRM_DEBUG_KMS("\n");
1785 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1786 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1787 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1788
1789 /* We don't adjust intel_dp->DP while tearing down the link, to
1790 * facilitate link retraining (e.g. after hotplug). Hence clear all
1791 * enable bits here to ensure that we don't enable too much. */
1792 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1793 intel_dp->DP |= DP_PLL_ENABLE;
1794 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1795 POSTING_READ(DP_A);
1796 udelay(200);
d240f20f
JB		 1797}
1798
2bd2ad64 1799static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1800{
da63a9f2
PZ		 1801 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1802 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1803 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1804 struct drm_i915_private *dev_priv = dev->dev_private;
1805 u32 dpa_ctl;
1806
2bd2ad64
DV		 1807 assert_pipe_disabled(dev_priv,
1808 to_intel_crtc(crtc)->pipe);
1809
d240f20f 1810 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1811 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1812 "dp pll off, should be on\n");
1813 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1814
1815 /* We can't rely on the value tracked for the DP register in
1816 * intel_dp->DP because link_down must not change that (otherwise link
1817 * re-training will fail. */
298b0b39 1818 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1819 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1820 POSTING_READ(DP_A);
d240f20f
JB		 1821 udelay(200);
1822}
1823
c7ad3810 1824/* If the sink supports it, try to set the power state appropriately */
c19b0669 1825void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1826{
1827 int ret, i;
1828
1829 /* Should have a valid DPCD by this point */
1830 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1831 return;
1832
1833 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1834 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1835 DP_SET_POWER_D3);
c7ad3810
JB		 1836 } else {
1837 /*
1838 * When turning on, we need to retry for 1ms to give the sink
1839 * time to wake up.
1840 */
1841 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1842 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1843 DP_SET_POWER_D0);
c7ad3810
JB		 1844 if (ret == 1)
1845 break;
1846 msleep(1);
1847 }
1848 }
f9cac721
JN		 1849
1850 if (ret != 1)
1851 DRM_DEBUG_KMS("failed to %s sink power state\n",
1852 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1853}
1854
19d8fe15
DV		 1855static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1856 enum pipe *pipe)
d240f20f 1857{
19d8fe15 1858 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1859 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1860 struct drm_device *dev = encoder->base.dev;
1861 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1862 enum intel_display_power_domain power_domain;
1863 u32 tmp;
1864
1865 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1866 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1867 return false;
1868
1869 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1870
1871 if (!(tmp & DP_PORT_EN))
1872 return false;
1873
bc7d38a4 1874 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1875 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1876 } else if (IS_CHERRYVIEW(dev)) {
1877 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1878 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1879 *pipe = PORT_TO_PIPE(tmp);
1880 } else {
1881 u32 trans_sel;
1882 u32 trans_dp;
1883 int i;
1884
1885 switch (intel_dp->output_reg) {
1886 case PCH_DP_B:
1887 trans_sel = TRANS_DP_PORT_SEL_B;
1888 break;
1889 case PCH_DP_C:
1890 trans_sel = TRANS_DP_PORT_SEL_C;
1891 break;
1892 case PCH_DP_D:
1893 trans_sel = TRANS_DP_PORT_SEL_D;
1894 break;
1895 default:
1896 return true;
1897 }
1898
055e393f 1899 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1900 trans_dp = I915_READ(TRANS_DP_CTL(i));
1901 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1902 *pipe = i;
1903 return true;
1904 }
1905 }
19d8fe15 1906
4a0833ec
DV		 1907 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1908 intel_dp->output_reg);
1909 }
d240f20f 1910
19d8fe15
DV		 1911 return true;
1912}
d240f20f 1913
045ac3b5
JB		 1914static void intel_dp_get_config(struct intel_encoder *encoder,
1915 struct intel_crtc_config *pipe_config)
1916{
1917 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1918 u32 tmp, flags = 0;
63000ef6
XZ		 1919 struct drm_device *dev = encoder->base.dev;
1920 struct drm_i915_private *dev_priv = dev->dev_private;
1921 enum port port = dp_to_dig_port(intel_dp)->port;
1922 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1923 int dotclock;
045ac3b5 1924
9ed109a7
DV		 1925 tmp = I915_READ(intel_dp->output_reg);
1926 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1927 pipe_config->has_audio = true;
1928
63000ef6 1929 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1930 if (tmp & DP_SYNC_HS_HIGH)
1931 flags |= DRM_MODE_FLAG_PHSYNC;
1932 else
1933 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1934
63000ef6
XZ		 1935 if (tmp & DP_SYNC_VS_HIGH)
1936 flags |= DRM_MODE_FLAG_PVSYNC;
1937 else
1938 flags |= DRM_MODE_FLAG_NVSYNC;
1939 } else {
1940 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1941 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1942 flags |= DRM_MODE_FLAG_PHSYNC;
1943 else
1944 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1945
63000ef6
XZ		 1946 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1947 flags |= DRM_MODE_FLAG_PVSYNC;
1948 else
1949 flags |= DRM_MODE_FLAG_NVSYNC;
1950 }
045ac3b5
JB		 1951
1952 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1953
8c875fca
VS		 1954 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1955 tmp & DP_COLOR_RANGE_16_235)
1956 pipe_config->limited_color_range = true;
1957
eb14cb74
VS		 1958 pipe_config->has_dp_encoder = true;
1959
1960 intel_dp_get_m_n(crtc, pipe_config);
1961
18442d08 1962 if (port == PORT_A) {
f1f644dc
JB		 1963 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1964 pipe_config->port_clock = 162000;
1965 else
1966 pipe_config->port_clock = 270000;
1967 }
18442d08
VS		 1968
1969 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1970 &pipe_config->dp_m_n);
1971
1972 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1973 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1974
241bfc38 1975 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1976
c6cd2ee2
JN		 1977 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1978 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1979 /*
1980 * This is a big fat ugly hack.
1981 *
1982 * Some machines in UEFI boot mode provide us a VBT that has 18
1983 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1984 * unknown we fail to light up. Yet the same BIOS boots up with
1985 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1986 * max, not what it tells us to use.
1987 *
1988 * Note: This will still be broken if the eDP panel is not lit
1989 * up by the BIOS, and thus we can't get the mode at module
1990 * load.
1991 */
1992 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1993 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1994 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1995 }
045ac3b5
JB		 1996}
1997
34eb7579 1998static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1999{
34eb7579 2000 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 2001}
2002
2b28bb1b
RV		 2003static bool intel_edp_is_psr_enabled(struct drm_device *dev)
2004{
2005 struct drm_i915_private *dev_priv = dev->dev_private;
2006
18b5992c 2007 if (!HAS_PSR(dev))
2b28bb1b
RV		 2008 return false;
2009
18b5992c 2010 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 2011}
2012
2013static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
2014 struct edp_vsc_psr *vsc_psr)
2015{
2016 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2017 struct drm_device *dev = dig_port->base.base.dev;
2018 struct drm_i915_private *dev_priv = dev->dev_private;
2019 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
2020 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
2021 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
2022 uint32_t *data = (uint32_t *) vsc_psr;
2023 unsigned int i;
2024
2025 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2026 the video DIP being updated before program video DIP data buffer
2027 registers for DIP being updated. */
2028 I915_WRITE(ctl_reg, 0);
2029 POSTING_READ(ctl_reg);
2030
2031 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
2032 if (i < sizeof(struct edp_vsc_psr))
2033 I915_WRITE(data_reg + i, *data++);
2034 else
2035 I915_WRITE(data_reg + i, 0);
2036 }
2037
2038 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
2039 POSTING_READ(ctl_reg);
2040}
2041
ba80f4d4 2042static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
2b28bb1b 2043{
2b28bb1b
RV		 2044 struct edp_vsc_psr psr_vsc;
2045
2b28bb1b
RV		 2046 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2047 memset(&psr_vsc, 0, sizeof(psr_vsc));
2048 psr_vsc.sdp_header.HB0 = 0;
2049 psr_vsc.sdp_header.HB1 = 0x7;
2050 psr_vsc.sdp_header.HB2 = 0x2;
2051 psr_vsc.sdp_header.HB3 = 0x8;
2052 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2b28bb1b
RV		 2053}
2054
2055static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2056{
0e0ae652
RV		 2057 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2058 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2059 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2060 uint32_t aux_clock_divider;
2b28bb1b 2061 int precharge = 0x3;
0e0ae652 2062 bool only_standby = false;
5ca476f8
VS		 2063 static const uint8_t aux_msg[] = {
2064 [0] = DP_AUX_NATIVE_WRITE << 4,
2065 [1] = DP_SET_POWER >> 8,
2066 [2] = DP_SET_POWER & 0xff,
2067 [3] = 1 - 1,
2068 [4] = DP_SET_POWER_D0,
2069 };
2070 int i;
2071
2072 BUILD_BUG_ON(sizeof(aux_msg) > 20);
2b28bb1b 2073
ec5b01dd
DL		 2074 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2075
0e0ae652
RV		 2076 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2077 only_standby = true;
2078
2b28bb1b 2079 /* Enable PSR in sink */
0e0ae652 2080 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2081 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2082 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2083 else
9d1a1031
JN		 2084 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2085 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2086
2087 /* Setup AUX registers */
5ca476f8
VS		 2088 for (i = 0; i < sizeof(aux_msg); i += 4)
2089 I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
2090 pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
2091
18b5992c 2092 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b 2093 DP_AUX_CH_CTL_TIME_OUT_400us |
5ca476f8 2094 (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2b28bb1b
RV		 2095 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2096 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2097}
2098
2099static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2100{
0e0ae652
RV		 2101 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2102 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2103 struct drm_i915_private *dev_priv = dev->dev_private;
2104 uint32_t max_sleep_time = 0x1f;
2105 uint32_t idle_frames = 1;
2106 uint32_t val = 0x0;
ed8546ac 2107 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2108 bool only_standby = false;
2109
2110 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2111 only_standby = true;
2b28bb1b 2112
0e0ae652 2113 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2114 val |= EDP_PSR_LINK_STANDBY;
2115 val |= EDP_PSR_TP2_TP3_TIME_0us;
2116 val |= EDP_PSR_TP1_TIME_0us;
2117 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2118 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2119 } else
2120 val |= EDP_PSR_LINK_DISABLE;
2121
18b5992c 2122 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2123 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2124 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2125 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2126 EDP_PSR_ENABLE);
2127}
2128
3f51e471
RV		 2129static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2130{
2131 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2132 struct drm_device *dev = dig_port->base.base.dev;
2133 struct drm_i915_private *dev_priv = dev->dev_private;
2134 struct drm_crtc *crtc = dig_port->base.base.crtc;
2135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2136
f0355c4a 2137 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2138 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2139 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2140
a031d709
RV		 2141 dev_priv->psr.source_ok = false;
2142
9ca15301 2143 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2144 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2145 return false;
2146 }
2147
d330a953 2148 if (!i915.enable_psr) {
105b7c11 2149 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2150 return false;
2151 }
2152
4c8c7000
RV		 2153 /* Below limitations aren't valid for Broadwell */
2154 if (IS_BROADWELL(dev))
2155 goto out;
2156
3f51e471
RV		 2157 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2158 S3D_ENABLE) {
2159 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2160 return false;
2161 }
2162
ca73b4f0 2163 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2164 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2165 return false;
2166 }
2167
4c8c7000 2168 out:
a031d709 2169 dev_priv->psr.source_ok = true;
3f51e471
RV		 2170 return true;
2171}
2172
3d739d92 2173static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2174{
7c8f8a70
RV		 2175 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2176 struct drm_device *dev = intel_dig_port->base.base.dev;
2177 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2178
3638379c
DV		 2179 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2180 WARN_ON(dev_priv->psr.active);
f0355c4a 2181 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2182
7ca5a41f 2183 /* Enable/Re-enable PSR on the host */
2b28bb1b 2184 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2185
7c8f8a70 2186 dev_priv->psr.active = true;
2b28bb1b
RV		 2187}
2188
3d739d92
RV		 2189void intel_edp_psr_enable(struct intel_dp *intel_dp)
2190{
2191 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2192 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2193
4704c573
RV		 2194 if (!HAS_PSR(dev)) {
2195 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2196 return;
2197 }
2198
34eb7579
RV		 2199 if (!is_edp_psr(intel_dp)) {
2200 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2201 return;
2202 }
2203
f0355c4a 2204 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2205 if (dev_priv->psr.enabled) {
2206 DRM_DEBUG_KMS("PSR already in use\n");
0aa48783 2207 goto unlock;
109fc2ad
DV		 2208 }
2209
0aa48783
RV		 2210 if (!intel_edp_psr_match_conditions(intel_dp))
2211 goto unlock;
2212
9ca15301
DV		 2213 dev_priv->psr.busy_frontbuffer_bits = 0;
2214
ba80f4d4 2215 intel_edp_psr_setup_vsc(intel_dp);
16487254 2216
ba80f4d4
RV		 2217 /* Avoid continuous PSR exit by masking memup and hpd */
2218 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2219 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
16487254 2220
7ca5a41f
RV		 2221 /* Enable PSR on the panel */
2222 intel_edp_psr_enable_sink(intel_dp);
2223
0aa48783
RV		 2224 dev_priv->psr.enabled = intel_dp;
2225unlock:
f0355c4a 2226 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2227}
2228
2b28bb1b
RV		 2229void intel_edp_psr_disable(struct intel_dp *intel_dp)
2230{
2231 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2232 struct drm_i915_private *dev_priv = dev->dev_private;
2233
f0355c4a
DV		 2234 mutex_lock(&dev_priv->psr.lock);
2235 if (!dev_priv->psr.enabled) {
2236 mutex_unlock(&dev_priv->psr.lock);
2237 return;
2238 }
2239
3638379c
DV		 2240 if (dev_priv->psr.active) {
2241 I915_WRITE(EDP_PSR_CTL(dev),
2242 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2243
2244 /* Wait till PSR is idle */
2245 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2246 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2247 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2248
3638379c
DV		 2249 dev_priv->psr.active = false;
2250 } else {
2251 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2252 }
7c8f8a70 2253
2807cf69 2254 dev_priv->psr.enabled = NULL;
f0355c4a 2255 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2256
2257 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2258}
2259
f02a326e 2260static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2261{
2262 struct drm_i915_private *dev_priv =
2263 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2264 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2265
8d7f4fe9
RV		 2266 /* We have to make sure PSR is ready for re-enable
2267 * otherwise it keeps disabled until next full enable/disable cycle.
2268 * PSR might take some time to get fully disabled
2269 * and be ready for re-enable.
2270 */
2271 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
2272 EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
2273 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
2274 return;
2275 }
2276
f0355c4a
DV		 2277 mutex_lock(&dev_priv->psr.lock);
2278 intel_dp = dev_priv->psr.enabled;
2279
2807cf69 2280 if (!intel_dp)
f0355c4a 2281 goto unlock;
2807cf69 2282
9ca15301
DV		 2283 /*
2284 * The delayed work can race with an invalidate hence we need to
2285 * recheck. Since psr_flush first clears this and then reschedules we
2286 * won't ever miss a flush when bailing out here.
2287 */
2288 if (dev_priv->psr.busy_frontbuffer_bits)
2289 goto unlock;
2290
2291 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2292unlock:
2293 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2294}
2295
9ca15301 2296static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2297{
2298 struct drm_i915_private *dev_priv = dev->dev_private;
2299
3638379c
DV		 2300 if (dev_priv->psr.active) {
2301 u32 val = I915_READ(EDP_PSR_CTL(dev));
2302
2303 WARN_ON(!(val & EDP_PSR_ENABLE));
2304
2305 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2306
2307 dev_priv->psr.active = false;
2308 }
7c8f8a70 2309
9ca15301
DV		 2310}
2311
2312void intel_edp_psr_invalidate(struct drm_device *dev,
2313 unsigned frontbuffer_bits)
2314{
2315 struct drm_i915_private *dev_priv = dev->dev_private;
2316 struct drm_crtc *crtc;
2317 enum pipe pipe;
2318
9ca15301
DV		 2319 mutex_lock(&dev_priv->psr.lock);
2320 if (!dev_priv->psr.enabled) {
2321 mutex_unlock(&dev_priv->psr.lock);
2322 return;
2323 }
2324
2325 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2326 pipe = to_intel_crtc(crtc)->pipe;
2327
2328 intel_edp_psr_do_exit(dev);
2329
2330 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2331
2332 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2333 mutex_unlock(&dev_priv->psr.lock);
2334}
2335
2336void intel_edp_psr_flush(struct drm_device *dev,
2337 unsigned frontbuffer_bits)
2338{
2339 struct drm_i915_private *dev_priv = dev->dev_private;
2340 struct drm_crtc *crtc;
2341 enum pipe pipe;
2342
9ca15301
DV		 2343 mutex_lock(&dev_priv->psr.lock);
2344 if (!dev_priv->psr.enabled) {
2345 mutex_unlock(&dev_priv->psr.lock);
2346 return;
2347 }
2348
2349 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2350 pipe = to_intel_crtc(crtc)->pipe;
2351 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2352
2353 /*
2354 * On Haswell sprite plane updates don't result in a psr invalidating
2355 * signal in the hardware. Which means we need to manually fake this in
2356 * software for all flushes, not just when we've seen a preceding
2357 * invalidation through frontbuffer rendering.
2358 */
2359 if (IS_HASWELL(dev) &&
2360 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2361 intel_edp_psr_do_exit(dev);
2362
2363 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2364 schedule_delayed_work(&dev_priv->psr.work,
2365 msecs_to_jiffies(100));
f0355c4a 2366 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2367}
2368
2369void intel_edp_psr_init(struct drm_device *dev)
2370{
2371 struct drm_i915_private *dev_priv = dev->dev_private;
2372
7c8f8a70 2373 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2374 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2375}
2376
e8cb4558 2377static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2378{
e8cb4558 2379 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2380 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2381
2382 /* Make sure the panel is off before trying to change the mode. But also
2383 * ensure that we have vdd while we switch off the panel. */
24f3e092 2384 intel_edp_panel_vdd_on(intel_dp);
4be73780 2385 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2386 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2387 intel_edp_panel_off(intel_dp);
3739850b 2388
08aff3fe
VS		 2389 /* disable the port before the pipe on g4x */
2390 if (INTEL_INFO(dev)->gen < 5)
3739850b 2391 intel_dp_link_down(intel_dp);
d240f20f
JB		 2392}
2393
08aff3fe 2394static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2395{
2bd2ad64 2396 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2397 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2398
49277c31 2399 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2400 if (port == PORT_A)
2401 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2402}
2403
2404static void vlv_post_disable_dp(struct intel_encoder *encoder)
2405{
2406 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2407
2408 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2409}
2410
580d3811
VS		 2411static void chv_post_disable_dp(struct intel_encoder *encoder)
2412{
2413 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2414 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2415 struct drm_device *dev = encoder->base.dev;
2416 struct drm_i915_private *dev_priv = dev->dev_private;
2417 struct intel_crtc *intel_crtc =
2418 to_intel_crtc(encoder->base.crtc);
2419 enum dpio_channel ch = vlv_dport_to_channel(dport);
2420 enum pipe pipe = intel_crtc->pipe;
2421 u32 val;
2422
2423 intel_dp_link_down(intel_dp);
2424
2425 mutex_lock(&dev_priv->dpio_lock);
2426
2427 /* Propagate soft reset to data lane reset */
97fd4d5c 2428 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2429 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2430 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2431
97fd4d5c
VS		 2432 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2433 val |= CHV_PCS_REQ_SOFTRESET_EN;
2434 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2435
2436 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2437 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2438 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2439
2440 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2441 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2442 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2443
2444 mutex_unlock(&dev_priv->dpio_lock);
2445}
2446
7b13b58a
VS		 2447static void
2448_intel_dp_set_link_train(struct intel_dp *intel_dp,
2449 uint32_t *DP,
2450 uint8_t dp_train_pat)
2451{
2452 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2453 struct drm_device *dev = intel_dig_port->base.base.dev;
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2455 enum port port = intel_dig_port->port;
2456
2457 if (HAS_DDI(dev)) {
2458 uint32_t temp = I915_READ(DP_TP_CTL(port));
2459
2460 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2461 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2462 else
2463 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2464
2465 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2466 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2467 case DP_TRAINING_PATTERN_DISABLE:
2468 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2469
2470 break;
2471 case DP_TRAINING_PATTERN_1:
2472 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2473 break;
2474 case DP_TRAINING_PATTERN_2:
2475 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2476 break;
2477 case DP_TRAINING_PATTERN_3:
2478 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2479 break;
2480 }
2481 I915_WRITE(DP_TP_CTL(port), temp);
2482
2483 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2484 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2485
2486 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2487 case DP_TRAINING_PATTERN_DISABLE:
2488 *DP |= DP_LINK_TRAIN_OFF_CPT;
2489 break;
2490 case DP_TRAINING_PATTERN_1:
2491 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2492 break;
2493 case DP_TRAINING_PATTERN_2:
2494 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2495 break;
2496 case DP_TRAINING_PATTERN_3:
2497 DRM_ERROR("DP training pattern 3 not supported\n");
2498 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2499 break;
2500 }
2501
2502 } else {
2503 if (IS_CHERRYVIEW(dev))
2504 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2505 else
2506 *DP &= ~DP_LINK_TRAIN_MASK;
2507
2508 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2509 case DP_TRAINING_PATTERN_DISABLE:
2510 *DP |= DP_LINK_TRAIN_OFF;
2511 break;
2512 case DP_TRAINING_PATTERN_1:
2513 *DP |= DP_LINK_TRAIN_PAT_1;
2514 break;
2515 case DP_TRAINING_PATTERN_2:
2516 *DP |= DP_LINK_TRAIN_PAT_2;
2517 break;
2518 case DP_TRAINING_PATTERN_3:
2519 if (IS_CHERRYVIEW(dev)) {
2520 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2521 } else {
2522 DRM_ERROR("DP training pattern 3 not supported\n");
2523 *DP |= DP_LINK_TRAIN_PAT_2;
2524 }
2525 break;
2526 }
2527 }
2528}
2529
2530static void intel_dp_enable_port(struct intel_dp *intel_dp)
2531{
2532 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2533 struct drm_i915_private *dev_priv = dev->dev_private;
2534
2535 intel_dp->DP |= DP_PORT_EN;
2536
2537 /* enable with pattern 1 (as per spec) */
2538 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2539 DP_TRAINING_PATTERN_1);
2540
2541 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2542 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2543}
2544
e8cb4558 2545static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2546{
e8cb4558
DV		 2547 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2548 struct drm_device *dev = encoder->base.dev;
2549 struct drm_i915_private *dev_priv = dev->dev_private;
2550 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2551
0c33d8d7
DV		 2552 if (WARN_ON(dp_reg & DP_PORT_EN))
2553 return;
5d613501 2554
7b13b58a 2555 intel_dp_enable_port(intel_dp);
24f3e092 2556 intel_edp_panel_vdd_on(intel_dp);
4be73780 2557 intel_edp_panel_on(intel_dp);
1e0560e0 2558 intel_edp_panel_vdd_off(intel_dp, true);
f01eca2e 2559 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2560 intel_dp_start_link_train(intel_dp);
33a34e4e 2561 intel_dp_complete_link_train(intel_dp);
3ab9c637 2562 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2563}
89b667f8 2564
ecff4f3b
JN		 2565static void g4x_enable_dp(struct intel_encoder *encoder)
2566{
828f5c6e
JN		 2567 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2568
ecff4f3b 2569 intel_enable_dp(encoder);
4be73780 2570 intel_edp_backlight_on(intel_dp);
ab1f90f9 2571}
89b667f8 2572
ab1f90f9
JN		 2573static void vlv_enable_dp(struct intel_encoder *encoder)
2574{
828f5c6e
JN		 2575 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2576
4be73780 2577 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2578}
2579
ecff4f3b 2580static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2581{
2582 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2583 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2584
8ac33ed3
DV		 2585 intel_dp_prepare(encoder);
2586
d41f1efb
DV		 2587 /* Only ilk+ has port A */
2588 if (dport->port == PORT_A) {
2589 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2590 ironlake_edp_pll_on(intel_dp);
d41f1efb 2591 }
ab1f90f9
JN		 2592}
2593
a4a5d2f8
VS		 2594static void vlv_steal_power_sequencer(struct drm_device *dev,
2595 enum pipe pipe)
2596{
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 struct intel_encoder *encoder;
2599
2600 lockdep_assert_held(&dev_priv->pps_mutex);
2601
2602 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2603 base.head) {
2604 struct intel_dp *intel_dp;
773538e8 2605 enum port port;
a4a5d2f8
VS		 2606
2607 if (encoder->type != INTEL_OUTPUT_EDP)
2608 continue;
2609
2610 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2611 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2612
2613 if (intel_dp->pps_pipe != pipe)
2614 continue;
2615
2616 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2617 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 2618
2619 /* make sure vdd is off before we steal it */
2620 edp_panel_vdd_off_sync(intel_dp);
2621
2622 intel_dp->pps_pipe = INVALID_PIPE;
2623 }
2624}
2625
2626static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2627{
2628 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2629 struct intel_encoder *encoder = &intel_dig_port->base;
2630 struct drm_device *dev = encoder->base.dev;
2631 struct drm_i915_private *dev_priv = dev->dev_private;
2632 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2633
2634 lockdep_assert_held(&dev_priv->pps_mutex);
2635
2636 if (intel_dp->pps_pipe == crtc->pipe)
2637 return;
2638
2639 /*
2640 * If another power sequencer was being used on this
2641 * port previously make sure to turn off vdd there while
2642 * we still have control of it.
2643 */
2644 if (intel_dp->pps_pipe != INVALID_PIPE)
2645 edp_panel_vdd_off_sync(intel_dp);
2646
2647 /*
2648 * We may be stealing the power
2649 * sequencer from another port.
2650 */
2651 vlv_steal_power_sequencer(dev, crtc->pipe);
2652
2653 /* now it's all ours */
2654 intel_dp->pps_pipe = crtc->pipe;
2655
2656 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2657 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2658
2659 /* init power sequencer on this pipe and port */
36b5f425
VS		 2660 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2661 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2662}
2663
ab1f90f9 2664static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2665{
2bd2ad64 2666 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2667 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2668 struct drm_device *dev = encoder->base.dev;
89b667f8 2669 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2670 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2671 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2672 int pipe = intel_crtc->pipe;
2673 u32 val;
a4fc5ed6 2674
ab1f90f9 2675 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2676
ab3c759a 2677 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2678 val = 0;
2679 if (pipe)
2680 val |= (1<<21);
2681 else
2682 val &= ~(1<<21);
2683 val |= 0x001000c4;
ab3c759a
CML		 2684 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2685 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2686 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2687
ab1f90f9
JN		 2688 mutex_unlock(&dev_priv->dpio_lock);
2689
2cac613b 2690 if (is_edp(intel_dp)) {
773538e8 2691 pps_lock(intel_dp);
a4a5d2f8 2692 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2693 pps_unlock(intel_dp);
2cac613b 2694 }
bf13e81b 2695
ab1f90f9
JN		 2696 intel_enable_dp(encoder);
2697
e4607fcf 2698 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2699}
2700
ecff4f3b 2701static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2702{
2703 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2704 struct drm_device *dev = encoder->base.dev;
2705 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2706 struct intel_crtc *intel_crtc =
2707 to_intel_crtc(encoder->base.crtc);
e4607fcf 2708 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2709 int pipe = intel_crtc->pipe;
89b667f8 2710
8ac33ed3
DV		 2711 intel_dp_prepare(encoder);
2712
89b667f8 2713 /* Program Tx lane resets to default */
0980a60f 2714 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2715 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2716 DPIO_PCS_TX_LANE2_RESET |
2717 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2718 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2719 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2720 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2721 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2722 DPIO_PCS_CLK_SOFT_RESET);
2723
2724 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2725 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2726 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2727 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2728 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2729}
2730
e4a1d846
CML		 2731static void chv_pre_enable_dp(struct intel_encoder *encoder)
2732{
2733 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2734 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2735 struct drm_device *dev = encoder->base.dev;
2736 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2737 struct intel_crtc *intel_crtc =
2738 to_intel_crtc(encoder->base.crtc);
2739 enum dpio_channel ch = vlv_dport_to_channel(dport);
2740 int pipe = intel_crtc->pipe;
2741 int data, i;
949c1d43 2742 u32 val;
e4a1d846 2743
e4a1d846 2744 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2745
570e2a74
VS		 2746 /* allow hardware to manage TX FIFO reset source */
2747 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2748 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2749 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2750
2751 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2752 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2753 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2754
949c1d43 2755 /* Deassert soft data lane reset*/
97fd4d5c 2756 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2757 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2758 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2759
2760 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2761 val |= CHV_PCS_REQ_SOFTRESET_EN;
2762 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2763
2764 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2765 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2766 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2767
97fd4d5c 2768 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2769 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2770 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2771
2772 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2773 for (i = 0; i < 4; i++) {
2774 /* Set the latency optimal bit */
2775 data = (i == 1) ? 0x0 : 0x6;
2776 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2777 data << DPIO_FRC_LATENCY_SHFIT);
2778
2779 /* Set the upar bit */
2780 data = (i == 1) ? 0x0 : 0x1;
2781 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2782 data << DPIO_UPAR_SHIFT);
2783 }
2784
2785 /* Data lane stagger programming */
2786 /* FIXME: Fix up value only after power analysis */
2787
2788 mutex_unlock(&dev_priv->dpio_lock);
2789
2790 if (is_edp(intel_dp)) {
773538e8 2791 pps_lock(intel_dp);
a4a5d2f8 2792 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2793 pps_unlock(intel_dp);
e4a1d846
CML		 2794 }
2795
2796 intel_enable_dp(encoder);
2797
2798 vlv_wait_port_ready(dev_priv, dport);
2799}
2800
9197c88b
VS		 2801static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2802{
2803 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2804 struct drm_device *dev = encoder->base.dev;
2805 struct drm_i915_private *dev_priv = dev->dev_private;
2806 struct intel_crtc *intel_crtc =
2807 to_intel_crtc(encoder->base.crtc);
2808 enum dpio_channel ch = vlv_dport_to_channel(dport);
2809 enum pipe pipe = intel_crtc->pipe;
2810 u32 val;
2811
625695f8
VS		 2812 intel_dp_prepare(encoder);
2813
9197c88b
VS		 2814 mutex_lock(&dev_priv->dpio_lock);
2815
b9e5ac3c
VS		 2816 /* program left/right clock distribution */
2817 if (pipe != PIPE_B) {
2818 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2819 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2820 if (ch == DPIO_CH0)
2821 val |= CHV_BUFLEFTENA1_FORCE;
2822 if (ch == DPIO_CH1)
2823 val |= CHV_BUFRIGHTENA1_FORCE;
2824 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2825 } else {
2826 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2827 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2828 if (ch == DPIO_CH0)
2829 val |= CHV_BUFLEFTENA2_FORCE;
2830 if (ch == DPIO_CH1)
2831 val |= CHV_BUFRIGHTENA2_FORCE;
2832 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2833 }
2834
9197c88b
VS		 2835 /* program clock channel usage */
2836 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2837 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2838 if (pipe != PIPE_B)
2839 val &= ~CHV_PCS_USEDCLKCHANNEL;
2840 else
2841 val |= CHV_PCS_USEDCLKCHANNEL;
2842 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2843
2844 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2845 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2846 if (pipe != PIPE_B)
2847 val &= ~CHV_PCS_USEDCLKCHANNEL;
2848 else
2849 val |= CHV_PCS_USEDCLKCHANNEL;
2850 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2851
2852 /*
2853 * This a a bit weird since generally CL
2854 * matches the pipe, but here we need to
2855 * pick the CL based on the port.
2856 */
2857 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2858 if (pipe != PIPE_B)
2859 val &= ~CHV_CMN_USEDCLKCHANNEL;
2860 else
2861 val |= CHV_CMN_USEDCLKCHANNEL;
2862 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2863
2864 mutex_unlock(&dev_priv->dpio_lock);
2865}
2866
a4fc5ed6 2867/*
df0c237d
JB		 2868 * Native read with retry for link status and receiver capability reads for
2869 * cases where the sink may still be asleep.
9d1a1031
JN		 2870 *
2871 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2872 * supposed to retry 3 times per the spec.
a4fc5ed6 2873 */
9d1a1031
JN		 2874static ssize_t
2875intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2876 void *buffer, size_t size)
a4fc5ed6 2877{
9d1a1031
JN		 2878 ssize_t ret;
2879 int i;
61da5fab 2880
61da5fab 2881 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2882 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2883 if (ret == size)
2884 return ret;
61da5fab
JB		 2885 msleep(1);
2886 }
a4fc5ed6 2887
9d1a1031 2888 return ret;
a4fc5ed6
KP		 2889}
2890
2891/*
2892 * Fetch AUX CH registers 0x202 - 0x207 which contain
2893 * link status information
2894 */
2895static bool
93f62dad 2896intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2897{
9d1a1031
JN		 2898 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2899 DP_LANE0_1_STATUS,
2900 link_status,
2901 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2902}
2903
1100244e 2904/* These are source-specific values. */
a4fc5ed6 2905static uint8_t
1a2eb460 2906intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2907{
30add22d 2908 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2909 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2910
5a9d1f1a
DL		 2911 if (INTEL_INFO(dev)->gen >= 9)
2912 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2913 else if (IS_VALLEYVIEW(dev))
bd60018a 2914 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2915 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2916 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2917 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2918 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2919 else
bd60018a 2920 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2921}
2922
2923static uint8_t
2924intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2925{
30add22d 2926 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2927 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2928
5a9d1f1a
DL		 2929 if (INTEL_INFO(dev)->gen >= 9) {
2930 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2931 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2932 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2934 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2935 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2936 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2937 default:
2938 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2939 }
2940 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2941 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2942 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2943 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2944 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2945 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2946 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2947 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2949 default:
bd60018a 2950 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2951 }
e2fa6fba
P		 2952 } else if (IS_VALLEYVIEW(dev)) {
2953 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2954 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2955 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2956 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2957 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2958 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2959 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2960 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2961 default:
bd60018a 2962 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2963 }
bc7d38a4 2964 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2965 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2966 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2967 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2968 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2969 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2970 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2971 default:
bd60018a 2972 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2973 }
2974 } else {
2975 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2976 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2977 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2978 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2979 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2980 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2981 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2982 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2983 default:
bd60018a 2984 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2985 }
a4fc5ed6
KP		 2986 }
2987}
2988
e2fa6fba
P		 2989static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2990{
2991 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2992 struct drm_i915_private *dev_priv = dev->dev_private;
2993 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2994 struct intel_crtc *intel_crtc =
2995 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2996 unsigned long demph_reg_value, preemph_reg_value,
2997 uniqtranscale_reg_value;
2998 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2999 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 3000 int pipe = intel_crtc->pipe;
e2fa6fba
P		 3001
3002 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3003 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3004 preemph_reg_value = 0x0004000;
3005 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3006 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3007 demph_reg_value = 0x2B405555;
3008 uniqtranscale_reg_value = 0x552AB83A;
3009 break;
bd60018a 3010 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3011 demph_reg_value = 0x2B404040;
3012 uniqtranscale_reg_value = 0x5548B83A;
3013 break;
bd60018a 3014 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3015 demph_reg_value = 0x2B245555;
3016 uniqtranscale_reg_value = 0x5560B83A;
3017 break;
bd60018a 3018 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3019 demph_reg_value = 0x2B405555;
3020 uniqtranscale_reg_value = 0x5598DA3A;
3021 break;
3022 default:
3023 return 0;
3024 }
3025 break;
bd60018a 3026 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3027 preemph_reg_value = 0x0002000;
3028 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3029 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3030 demph_reg_value = 0x2B404040;
3031 uniqtranscale_reg_value = 0x5552B83A;
3032 break;
bd60018a 3033 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3034 demph_reg_value = 0x2B404848;
3035 uniqtranscale_reg_value = 0x5580B83A;
3036 break;
bd60018a 3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3038 demph_reg_value = 0x2B404040;
3039 uniqtranscale_reg_value = 0x55ADDA3A;
3040 break;
3041 default:
3042 return 0;
3043 }
3044 break;
bd60018a 3045 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3046 preemph_reg_value = 0x0000000;
3047 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3048 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3049 demph_reg_value = 0x2B305555;
3050 uniqtranscale_reg_value = 0x5570B83A;
3051 break;
bd60018a 3052 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3053 demph_reg_value = 0x2B2B4040;
3054 uniqtranscale_reg_value = 0x55ADDA3A;
3055 break;
3056 default:
3057 return 0;
3058 }
3059 break;
bd60018a 3060 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3061 preemph_reg_value = 0x0006000;
3062 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3063 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3064 demph_reg_value = 0x1B405555;
3065 uniqtranscale_reg_value = 0x55ADDA3A;
3066 break;
3067 default:
3068 return 0;
3069 }
3070 break;
3071 default:
3072 return 0;
3073 }
3074
0980a60f 3075 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 3076 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3077 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3078 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3079 uniqtranscale_reg_value);
ab3c759a
CML		 3080 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3081 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3082 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3083 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3084 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3085
3086 return 0;
3087}
3088
e4a1d846
CML		 3089static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3090{
3091 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3092 struct drm_i915_private *dev_priv = dev->dev_private;
3093 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3094 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3095 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3096 uint8_t train_set = intel_dp->train_set[0];
3097 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3098 enum pipe pipe = intel_crtc->pipe;
3099 int i;
e4a1d846
CML		 3100
3101 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3102 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3103 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3104 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3105 deemph_reg_value = 128;
3106 margin_reg_value = 52;
3107 break;
bd60018a 3108 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3109 deemph_reg_value = 128;
3110 margin_reg_value = 77;
3111 break;
bd60018a 3112 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3113 deemph_reg_value = 128;
3114 margin_reg_value = 102;
3115 break;
bd60018a 3116 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3117 deemph_reg_value = 128;
3118 margin_reg_value = 154;
3119 /* FIXME extra to set for 1200 */
3120 break;
3121 default:
3122 return 0;
3123 }
3124 break;
bd60018a 3125 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3126 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3127 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3128 deemph_reg_value = 85;
3129 margin_reg_value = 78;
3130 break;
bd60018a 3131 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3132 deemph_reg_value = 85;
3133 margin_reg_value = 116;
3134 break;
bd60018a 3135 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3136 deemph_reg_value = 85;
3137 margin_reg_value = 154;
3138 break;
3139 default:
3140 return 0;
3141 }
3142 break;
bd60018a 3143 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3144 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3145 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3146 deemph_reg_value = 64;
3147 margin_reg_value = 104;
3148 break;
bd60018a 3149 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3150 deemph_reg_value = 64;
3151 margin_reg_value = 154;
3152 break;
3153 default:
3154 return 0;
3155 }
3156 break;
bd60018a 3157 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3158 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3159 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3160 deemph_reg_value = 43;
3161 margin_reg_value = 154;
3162 break;
3163 default:
3164 return 0;
3165 }
3166 break;
3167 default:
3168 return 0;
3169 }
3170
3171 mutex_lock(&dev_priv->dpio_lock);
3172
3173 /* Clear calc init */
1966e59e
VS		 3174 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3175 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3176 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3177 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3178 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3179
3180 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3181 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3182 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3183 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 3184 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 3185
a02ef3c7
VS		 3186 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3187 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3188 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3189 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3190
3191 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3192 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3193 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3194 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3195
e4a1d846 3196 /* Program swing deemph */
f72df8db
VS		 3197 for (i = 0; i < 4; i++) {
3198 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3199 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3200 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3201 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3202 }
e4a1d846
CML		 3203
3204 /* Program swing margin */
f72df8db
VS		 3205 for (i = 0; i < 4; i++) {
3206 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3207 val &= ~DPIO_SWING_MARGIN000_MASK;
3208 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3209 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3210 }
e4a1d846
CML		 3211
3212 /* Disable unique transition scale */
f72df8db
VS		 3213 for (i = 0; i < 4; i++) {
3214 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3215 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3216 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3217 }
e4a1d846
CML		 3218
3219 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3220 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3221 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3222 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3223
3224 /*
3225 * The document said it needs to set bit 27 for ch0 and bit 26
3226 * for ch1. Might be a typo in the doc.
3227 * For now, for this unique transition scale selection, set bit
3228 * 27 for ch0 and ch1.
3229 */
f72df8db
VS		 3230 for (i = 0; i < 4; i++) {
3231 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3232 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3233 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3234 }
e4a1d846 3235
f72df8db
VS		 3236 for (i = 0; i < 4; i++) {
3237 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3238 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3239 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3240 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3241 }
e4a1d846
CML		 3242 }
3243
3244 /* Start swing calculation */
1966e59e
VS		 3245 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3246 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3247 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3248
3249 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3250 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3251 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3252
3253 /* LRC Bypass */
3254 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3255 val |= DPIO_LRC_BYPASS;
3256 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3257
3258 mutex_unlock(&dev_priv->dpio_lock);
3259
3260 return 0;
3261}
3262
a4fc5ed6 3263static void
0301b3ac
JN		 3264intel_get_adjust_train(struct intel_dp *intel_dp,
3265 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3266{
3267 uint8_t v = 0;
3268 uint8_t p = 0;
3269 int lane;
1a2eb460
KP		 3270 uint8_t voltage_max;
3271 uint8_t preemph_max;
a4fc5ed6 3272
33a34e4e 3273 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3274 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3275 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3276
3277 if (this_v > v)
3278 v = this_v;
3279 if (this_p > p)
3280 p = this_p;
3281 }
3282
1a2eb460 3283 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3284 if (v >= voltage_max)
3285 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3286
1a2eb460
KP		 3287 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3288 if (p >= preemph_max)
3289 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3290
3291 for (lane = 0; lane < 4; lane++)
33a34e4e 3292 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3293}
3294
3295static uint32_t
f0a3424e 3296intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3297{
3cf2efb1 3298 uint32_t signal_levels = 0;
a4fc5ed6 3299
3cf2efb1 3300 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3301 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3302 default:
3303 signal_levels |= DP_VOLTAGE_0_4;
3304 break;
bd60018a 3305 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3306 signal_levels |= DP_VOLTAGE_0_6;
3307 break;
bd60018a 3308 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3309 signal_levels |= DP_VOLTAGE_0_8;
3310 break;
bd60018a 3311 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3312 signal_levels |= DP_VOLTAGE_1_2;
3313 break;
3314 }
3cf2efb1 3315 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3316 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3317 default:
3318 signal_levels |= DP_PRE_EMPHASIS_0;
3319 break;
bd60018a 3320 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3321 signal_levels |= DP_PRE_EMPHASIS_3_5;
3322 break;
bd60018a 3323 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3324 signal_levels |= DP_PRE_EMPHASIS_6;
3325 break;
bd60018a 3326 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3327 signal_levels |= DP_PRE_EMPHASIS_9_5;
3328 break;
3329 }
3330 return signal_levels;
3331}
3332
e3421a18
ZW		 3333/* Gen6's DP voltage swing and pre-emphasis control */
3334static uint32_t
3335intel_gen6_edp_signal_levels(uint8_t train_set)
3336{
3c5a62b5
YL		 3337 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3338 DP_TRAIN_PRE_EMPHASIS_MASK);
3339 switch (signal_levels) {
bd60018a
SJ		 3340 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3341 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3342 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3343 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3344 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3345 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3346 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3347 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3348 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3349 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3350 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3351 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3352 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3353 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3354 default:
3c5a62b5
YL		 3355 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3356 "0x%x\n", signal_levels);
3357 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3358 }
3359}
3360
1a2eb460
KP		 3361/* Gen7's DP voltage swing and pre-emphasis control */
3362static uint32_t
3363intel_gen7_edp_signal_levels(uint8_t train_set)
3364{
3365 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3366 DP_TRAIN_PRE_EMPHASIS_MASK);
3367 switch (signal_levels) {
bd60018a 3368 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3369 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3370 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3371 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3372 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3373 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3374
bd60018a 3375 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3376 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3377 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3378 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3379
bd60018a 3380 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3381 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3382 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3383 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3384
3385 default:
3386 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3387 "0x%x\n", signal_levels);
3388 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3389 }
3390}
3391
d6c0d722
PZ		 3392/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3393static uint32_t
f0a3424e 3394intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3395{
d6c0d722
PZ		 3396 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3397 DP_TRAIN_PRE_EMPHASIS_MASK);
3398 switch (signal_levels) {
bd60018a 3399 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3400 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3401 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3402 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3403 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3404 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3405 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3406 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3407
bd60018a 3408 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3409 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3410 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3411 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3412 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3413 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3414
bd60018a 3415 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3416 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3417 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3418 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3419 default:
3420 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3421 "0x%x\n", signal_levels);
c5fe6a06 3422 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3423 }
a4fc5ed6
KP		 3424}
3425
f0a3424e
PZ		 3426/* Properly updates "DP" with the correct signal levels. */
3427static void
3428intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3429{
3430 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3431 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3432 struct drm_device *dev = intel_dig_port->base.base.dev;
3433 uint32_t signal_levels, mask;
3434 uint8_t train_set = intel_dp->train_set[0];
3435
5a9d1f1a 3436 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3437 signal_levels = intel_hsw_signal_levels(train_set);
3438 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3439 } else if (IS_CHERRYVIEW(dev)) {
3440 signal_levels = intel_chv_signal_levels(intel_dp);
3441 mask = 0;
e2fa6fba
P		 3442 } else if (IS_VALLEYVIEW(dev)) {
3443 signal_levels = intel_vlv_signal_levels(intel_dp);
3444 mask = 0;
bc7d38a4 3445 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3446 signal_levels = intel_gen7_edp_signal_levels(train_set);
3447 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3448 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3449 signal_levels = intel_gen6_edp_signal_levels(train_set);
3450 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3451 } else {
3452 signal_levels = intel_gen4_signal_levels(train_set);
3453 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3454 }
3455
3456 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3457
3458 *DP = (*DP & ~mask) | signal_levels;
3459}
3460
a4fc5ed6 3461static bool
ea5b213a 3462intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3463 uint32_t *DP,
58e10eb9 3464 uint8_t dp_train_pat)
a4fc5ed6 3465{
174edf1f
PZ		 3466 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3467 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3468 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3469 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3470 int ret, len;
a4fc5ed6 3471
7b13b58a 3472 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3473
70aff66c 3474 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3475 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3476
2cdfe6c8
JN		 3477 buf[0] = dp_train_pat;
3478 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3479 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3480 /* don't write DP_TRAINING_LANEx_SET on disable */
3481 len = 1;
3482 } else {
3483 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3484 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3485 len = intel_dp->lane_count + 1;
47ea7542 3486 }
a4fc5ed6 3487
9d1a1031
JN		 3488 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3489 buf, len);
2cdfe6c8
JN		 3490
3491 return ret == len;
a4fc5ed6
KP		 3492}
3493
70aff66c
JN		 3494static bool
3495intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3496 uint8_t dp_train_pat)
3497{
953d22e8 3498 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3499 intel_dp_set_signal_levels(intel_dp, DP);
3500 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3501}
3502
3503static bool
3504intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3505 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3506{
3507 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3508 struct drm_device *dev = intel_dig_port->base.base.dev;
3509 struct drm_i915_private *dev_priv = dev->dev_private;
3510 int ret;
3511
3512 intel_get_adjust_train(intel_dp, link_status);
3513 intel_dp_set_signal_levels(intel_dp, DP);
3514
3515 I915_WRITE(intel_dp->output_reg, *DP);
3516 POSTING_READ(intel_dp->output_reg);
3517
9d1a1031
JN		 3518 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3519 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3520
3521 return ret == intel_dp->lane_count;
3522}
3523
3ab9c637
ID		 3524static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3525{
3526 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3527 struct drm_device *dev = intel_dig_port->base.base.dev;
3528 struct drm_i915_private *dev_priv = dev->dev_private;
3529 enum port port = intel_dig_port->port;
3530 uint32_t val;
3531
3532 if (!HAS_DDI(dev))
3533 return;
3534
3535 val = I915_READ(DP_TP_CTL(port));
3536 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3537 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3538 I915_WRITE(DP_TP_CTL(port), val);
3539
3540 /*
3541 * On PORT_A we can have only eDP in SST mode. There the only reason
3542 * we need to set idle transmission mode is to work around a HW issue
3543 * where we enable the pipe while not in idle link-training mode.
3544 * In this case there is requirement to wait for a minimum number of
3545 * idle patterns to be sent.
3546 */
3547 if (port == PORT_A)
3548 return;
3549
3550 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3551 1))
3552 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3553}
3554
33a34e4e 3555/* Enable corresponding port and start training pattern 1 */
c19b0669 3556void
33a34e4e 3557intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3558{
da63a9f2 3559 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3560 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3561 int i;
3562 uint8_t voltage;
cdb0e95b 3563 int voltage_tries, loop_tries;
ea5b213a 3564 uint32_t DP = intel_dp->DP;
6aba5b6c 3565 uint8_t link_config[2];
a4fc5ed6 3566
affa9354 3567 if (HAS_DDI(dev))
c19b0669
PZ		 3568 intel_ddi_prepare_link_retrain(encoder);
3569
3cf2efb1 3570 /* Write the link configuration data */
6aba5b6c
JN		 3571 link_config[0] = intel_dp->link_bw;
3572 link_config[1] = intel_dp->lane_count;
3573 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3574 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3575 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3576
3577 link_config[0] = 0;
3578 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3579 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3580
3581 DP |= DP_PORT_EN;
1a2eb460 3582
70aff66c
JN		 3583 /* clock recovery */
3584 if (!intel_dp_reset_link_train(intel_dp, &DP,
3585 DP_TRAINING_PATTERN_1 |
3586 DP_LINK_SCRAMBLING_DISABLE)) {
3587 DRM_ERROR("failed to enable link training\n");
3588 return;
3589 }
3590
a4fc5ed6 3591 voltage = 0xff;
cdb0e95b
KP		 3592 voltage_tries = 0;
3593 loop_tries = 0;
a4fc5ed6 3594 for (;;) {
70aff66c 3595 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3596
a7c9655f 3597 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3598 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3599 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3600 break;
93f62dad 3601 }
a4fc5ed6 3602
01916270 3603 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3604 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3605 break;
3606 }
3607
3608 /* Check to see if we've tried the max voltage */
3609 for (i = 0; i < intel_dp->lane_count; i++)
3610 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3611 break;
3b4f819d 3612 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3613 ++loop_tries;
3614 if (loop_tries == 5) {
3def84b3 3615 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3616 break;
3617 }
70aff66c
JN		 3618 intel_dp_reset_link_train(intel_dp, &DP,
3619 DP_TRAINING_PATTERN_1 |
3620 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3621 voltage_tries = 0;
3622 continue;
3623 }
a4fc5ed6 3624
3cf2efb1 3625 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3626 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3627 ++voltage_tries;
b06fbda3 3628 if (voltage_tries == 5) {
3def84b3 3629 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3630 break;
3631 }
3632 } else
3633 voltage_tries = 0;
3634 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3635
70aff66c
JN		 3636 /* Update training set as requested by target */
3637 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3638 DRM_ERROR("failed to update link training\n");
3639 break;
3640 }
a4fc5ed6
KP		 3641 }
3642
33a34e4e
JB		 3643 intel_dp->DP = DP;
3644}
3645
c19b0669 3646void
33a34e4e
JB		 3647intel_dp_complete_link_train(struct intel_dp *intel_dp)
3648{
33a34e4e 3649 bool channel_eq = false;
37f80975 3650 int tries, cr_tries;
33a34e4e 3651 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3652 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3653
3654 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3655 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3656 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3657
a4fc5ed6 3658 /* channel equalization */
70aff66c 3659 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3660 training_pattern |
70aff66c
JN		 3661 DP_LINK_SCRAMBLING_DISABLE)) {
3662 DRM_ERROR("failed to start channel equalization\n");
3663 return;
3664 }
3665
a4fc5ed6 3666 tries = 0;
37f80975 3667 cr_tries = 0;
a4fc5ed6
KP		 3668 channel_eq = false;
3669 for (;;) {
70aff66c 3670 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3671
37f80975
JB		 3672 if (cr_tries > 5) {
3673 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3674 break;
3675 }
3676
a7c9655f 3677 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3678 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3679 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3680 break;
70aff66c 3681 }
a4fc5ed6 3682
37f80975 3683 /* Make sure clock is still ok */
01916270 3684 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3685 intel_dp_start_link_train(intel_dp);
70aff66c 3686 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3687 training_pattern |
70aff66c 3688 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3689 cr_tries++;
3690 continue;
3691 }
3692
1ffdff13 3693 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3694 channel_eq = true;
3695 break;
3696 }
a4fc5ed6 3697
37f80975
JB		 3698 /* Try 5 times, then try clock recovery if that fails */
3699 if (tries > 5) {
3700 intel_dp_link_down(intel_dp);
3701 intel_dp_start_link_train(intel_dp);
70aff66c 3702 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3703 training_pattern |
70aff66c 3704 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3705 tries = 0;
3706 cr_tries++;
3707 continue;
3708 }
a4fc5ed6 3709
70aff66c
JN		 3710 /* Update training set as requested by target */
3711 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3712 DRM_ERROR("failed to update link training\n");
3713 break;
3714 }
3cf2efb1 3715 ++tries;
869184a6 3716 }
3cf2efb1 3717
3ab9c637
ID		 3718 intel_dp_set_idle_link_train(intel_dp);
3719
3720 intel_dp->DP = DP;
3721
d6c0d722 3722 if (channel_eq)
07f42258 3723 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3724
3ab9c637
ID		 3725}
3726
3727void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3728{
70aff66c 3729 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3730 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3731}
3732
3733static void
ea5b213a 3734intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3735{
da63a9f2 3736 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3737 enum port port = intel_dig_port->port;
da63a9f2 3738 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3739 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3740 struct intel_crtc *intel_crtc =
3741 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3742 uint32_t DP = intel_dp->DP;
a4fc5ed6 3743
bc76e320 3744 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3745 return;
3746
0c33d8d7 3747 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3748 return;
3749
28c97730 3750 DRM_DEBUG_KMS("\n");
32f9d658 3751
bc7d38a4 3752 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3753 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3754 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3755 } else {
aad3d14d
VS		 3756 if (IS_CHERRYVIEW(dev))
3757 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3758 else
3759 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3760 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3761 }
fe255d00 3762 POSTING_READ(intel_dp->output_reg);
5eb08b69 3763
493a7081 3764 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3765 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3766 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3767
5bddd17f
EA		 3768 /* Hardware workaround: leaving our transcoder select
3769 * set to transcoder B while it's off will prevent the
3770 * corresponding HDMI output on transcoder A.
3771 *
3772 * Combine this with another hardware workaround:
3773 * transcoder select bit can only be cleared while the
3774 * port is enabled.
3775 */
3776 DP &= ~DP_PIPEB_SELECT;
3777 I915_WRITE(intel_dp->output_reg, DP);
3778
3779 /* Changes to enable or select take place the vblank
3780 * after being written.
3781 */
ff50afe9
DV		 3782 if (WARN_ON(crtc == NULL)) {
3783 /* We should never try to disable a port without a crtc
3784 * attached. For paranoia keep the code around for a
3785 * bit. */
31acbcc4
CW		 3786 POSTING_READ(intel_dp->output_reg);
3787 msleep(50);
3788 } else
ab527efc 3789 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3790 }
3791
832afda6 3792 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3793 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3794 POSTING_READ(intel_dp->output_reg);
f01eca2e 3795 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3796}
3797
26d61aad
KP		 3798static bool
3799intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3800{
a031d709
RV		 3801 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3802 struct drm_device *dev = dig_port->base.base.dev;
3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804
9d1a1031
JN		 3805 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3806 sizeof(intel_dp->dpcd)) < 0)
edb39244 3807 return false; /* aux transfer failed */
92fd8fd1 3808
a8e98153 3809 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3810
edb39244
AJ		 3811 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3812 return false; /* DPCD not present */
3813
2293bb5c
SK		 3814 /* Check if the panel supports PSR */
3815 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3816 if (is_edp(intel_dp)) {
9d1a1031
JN		 3817 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3818 intel_dp->psr_dpcd,
3819 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3820 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3821 dev_priv->psr.sink_support = true;
50003939 3822 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3823 }
50003939
JN		 3824 }
3825
06ea66b6
TP		 3826 /* Training Pattern 3 support */
3827 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3828 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3829 intel_dp->use_tps3 = true;
f8d8a672 3830 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3831 } else
3832 intel_dp->use_tps3 = false;
3833
edb39244
AJ		 3834 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3835 DP_DWN_STRM_PORT_PRESENT))
3836 return true; /* native DP sink */
3837
3838 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3839 return true; /* no per-port downstream info */
3840
9d1a1031
JN		 3841 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3842 intel_dp->downstream_ports,
3843 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3844 return false; /* downstream port status fetch failed */
3845
3846 return true;
92fd8fd1
KP		 3847}
3848
0d198328
AJ		 3849static void
3850intel_dp_probe_oui(struct intel_dp *intel_dp)
3851{
3852 u8 buf[3];
3853
3854 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3855 return;
3856
9d1a1031 3857 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3858 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3859 buf[0], buf[1], buf[2]);
3860
9d1a1031 3861 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3862 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3863 buf[0], buf[1], buf[2]);
3864}
3865
0e32b39c
DA		 3866static bool
3867intel_dp_probe_mst(struct intel_dp *intel_dp)
3868{
3869 u8 buf[1];
3870
3871 if (!intel_dp->can_mst)
3872 return false;
3873
3874 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3875 return false;
3876
0e32b39c
DA		 3877 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3878 if (buf[0] & DP_MST_CAP) {
3879 DRM_DEBUG_KMS("Sink is MST capable\n");
3880 intel_dp->is_mst = true;
3881 } else {
3882 DRM_DEBUG_KMS("Sink is not MST capable\n");
3883 intel_dp->is_mst = false;
3884 }
3885 }
0e32b39c
DA		 3886
3887 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3888 return intel_dp->is_mst;
3889}
3890
d2e216d0
RV		 3891int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3892{
3893 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3894 struct drm_device *dev = intel_dig_port->base.base.dev;
3895 struct intel_crtc *intel_crtc =
3896 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3897 u8 buf;
3898 int test_crc_count;
3899 int attempts = 6;
d2e216d0 3900
ad9dc91b 3901 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3902 return -EIO;
d2e216d0 3903
ad9dc91b 3904 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3905 return -ENOTTY;
3906
1dda5f93
RV		 3907 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3908 return -EIO;
3909
9d1a1031 3910 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3911 buf | DP_TEST_SINK_START) < 0)
bda0381e 3912 return -EIO;
d2e216d0 3913
1dda5f93 3914 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3915 return -EIO;
ad9dc91b 3916 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 3917
ad9dc91b 3918 do {
1dda5f93
RV		 3919 if (drm_dp_dpcd_readb(&intel_dp->aux,
3920 DP_TEST_SINK_MISC, &buf) < 0)
3921 return -EIO;
ad9dc91b
RV		 3922 intel_wait_for_vblank(dev, intel_crtc->pipe);
3923 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3924
3925 if (attempts == 0) {
3926 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
3927 return -EIO;
3928 }
d2e216d0 3929
9d1a1031 3930 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 3931 return -EIO;
d2e216d0 3932
1dda5f93
RV		 3933 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3934 return -EIO;
3935 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3936 buf & ~DP_TEST_SINK_START) < 0)
3937 return -EIO;
ce31d9f4 3938
d2e216d0
RV		 3939 return 0;
3940}
3941
a60f0e38
JB		 3942static bool
3943intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3944{
9d1a1031
JN		 3945 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3946 DP_DEVICE_SERVICE_IRQ_VECTOR,
3947 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3948}
3949
0e32b39c
DA		 3950static bool
3951intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3952{
3953 int ret;
3954
3955 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3956 DP_SINK_COUNT_ESI,
3957 sink_irq_vector, 14);
3958 if (ret != 14)
3959 return false;
3960
3961 return true;
3962}
3963
a60f0e38
JB		 3964static void
3965intel_dp_handle_test_request(struct intel_dp *intel_dp)
3966{
3967 /* NAK by default */
9d1a1031 3968 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3969}
3970
0e32b39c
DA		 3971static int
3972intel_dp_check_mst_status(struct intel_dp *intel_dp)
3973{
3974 bool bret;
3975
3976 if (intel_dp->is_mst) {
3977 u8 esi[16] = { 0 };
3978 int ret = 0;
3979 int retry;
3980 bool handled;
3981 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3982go_again:
3983 if (bret == true) {
3984
3985 /* check link status - esi[10] = 0x200c */
3986 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3987 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3988 intel_dp_start_link_train(intel_dp);
3989 intel_dp_complete_link_train(intel_dp);
3990 intel_dp_stop_link_train(intel_dp);
3991 }
3992
3993 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3994 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3995
3996 if (handled) {
3997 for (retry = 0; retry < 3; retry++) {
3998 int wret;
3999 wret = drm_dp_dpcd_write(&intel_dp->aux,
4000 DP_SINK_COUNT_ESI+1,
4001 &esi[1], 3);
4002 if (wret == 3) {
4003 break;
4004 }
4005 }
4006
4007 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4008 if (bret == true) {
4009 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4010 goto go_again;
4011 }
4012 } else
4013 ret = 0;
4014
4015 return ret;
4016 } else {
4017 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4018 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4019 intel_dp->is_mst = false;
4020 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4021 /* send a hotplug event */
4022 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4023 }
4024 }
4025 return -EINVAL;
4026}
4027
a4fc5ed6
KP		 4028/*
4029 * According to DP spec
4030 * 5.1.2:
4031 * 1. Read DPCD
4032 * 2. Configure link according to Receiver Capabilities
4033 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4034 * 4. Check link status on receipt of hot-plug interrupt
4035 */
00c09d70 4036void
ea5b213a 4037intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4038{
5b215bcf 4039 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4040 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4041 u8 sink_irq_vector;
93f62dad 4042 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4043
5b215bcf
DA		 4044 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4045
da63a9f2 4046 if (!intel_encoder->connectors_active)
d2b996ac 4047 return;
59cd09e1 4048
da63a9f2 4049 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 4050 return;
4051
1a125d8a
ID		 4052 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4053 return;
4054
92fd8fd1 4055 /* Try to read receiver status if the link appears to be up */
93f62dad 4056 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4057 return;
4058 }
4059
92fd8fd1 4060 /* Now read the DPCD to see if it's actually running */
26d61aad 4061 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4062 return;
4063 }
4064
a60f0e38
JB		 4065 /* Try to read the source of the interrupt */
4066 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4067 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4068 /* Clear interrupt source */
9d1a1031
JN		 4069 drm_dp_dpcd_writeb(&intel_dp->aux,
4070 DP_DEVICE_SERVICE_IRQ_VECTOR,
4071 sink_irq_vector);
a60f0e38
JB		 4072
4073 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4074 intel_dp_handle_test_request(intel_dp);
4075 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4076 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4077 }
4078
1ffdff13 4079 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4080 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4081 intel_encoder->base.name);
33a34e4e
JB		 4082 intel_dp_start_link_train(intel_dp);
4083 intel_dp_complete_link_train(intel_dp);
3ab9c637 4084 intel_dp_stop_link_train(intel_dp);
33a34e4e 4085 }
a4fc5ed6 4086}
a4fc5ed6 4087
caf9ab24 4088/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4089static enum drm_connector_status
26d61aad 4090intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4091{
caf9ab24 4092 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4093 uint8_t type;
4094
4095 if (!intel_dp_get_dpcd(intel_dp))
4096 return connector_status_disconnected;
4097
4098 /* if there's no downstream port, we're done */
4099 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4100 return connector_status_connected;
caf9ab24
AJ		 4101
4102 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4103 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4104 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4105 uint8_t reg;
9d1a1031
JN		 4106
4107 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4108 &reg, 1) < 0)
caf9ab24 4109 return connector_status_unknown;
9d1a1031 4110
23235177
AJ		 4111 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4112 : connector_status_disconnected;
caf9ab24
AJ		 4113 }
4114
4115 /* If no HPD, poke DDC gently */
0b99836f 4116 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4117 return connector_status_connected;
caf9ab24
AJ		 4118
4119 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4120 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4121 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4122 if (type == DP_DS_PORT_TYPE_VGA ||
4123 type == DP_DS_PORT_TYPE_NON_EDID)
4124 return connector_status_unknown;
4125 } else {
4126 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4127 DP_DWN_STRM_PORT_TYPE_MASK;
4128 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4129 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4130 return connector_status_unknown;
4131 }
caf9ab24
AJ		 4132
4133 /* Anything else is out of spec, warn and ignore */
4134 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4135 return connector_status_disconnected;
71ba9000
AJ		 4136}
4137
d410b56d
CW		 4138static enum drm_connector_status
4139edp_detect(struct intel_dp *intel_dp)
4140{
4141 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4142 enum drm_connector_status status;
4143
4144 status = intel_panel_detect(dev);
4145 if (status == connector_status_unknown)
4146 status = connector_status_connected;
4147
4148 return status;
4149}
4150
5eb08b69 4151static enum drm_connector_status
a9756bb5 4152ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4153{
30add22d 4154 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4155 struct drm_i915_private *dev_priv = dev->dev_private;
4156 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4157
1b469639
DL		 4158 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4159 return connector_status_disconnected;
4160
26d61aad 4161 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4162}
4163
2a592bec
DA		 4164static int g4x_digital_port_connected(struct drm_device *dev,
4165 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4166{
a4fc5ed6 4167 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4168 uint32_t bit;
5eb08b69 4169
232a6ee9
TP		 4170 if (IS_VALLEYVIEW(dev)) {
4171 switch (intel_dig_port->port) {
4172 case PORT_B:
4173 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4174 break;
4175 case PORT_C:
4176 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4177 break;
4178 case PORT_D:
4179 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4180 break;
4181 default:
2a592bec 4182 return -EINVAL;
232a6ee9
TP		 4183 }
4184 } else {
4185 switch (intel_dig_port->port) {
4186 case PORT_B:
4187 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4188 break;
4189 case PORT_C:
4190 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4191 break;
4192 case PORT_D:
4193 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4194 break;
4195 default:
2a592bec 4196 return -EINVAL;
232a6ee9 4197 }
a4fc5ed6
KP		 4198 }
4199
10f76a38 4200 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4201 return 0;
4202 return 1;
4203}
4204
4205static enum drm_connector_status
4206g4x_dp_detect(struct intel_dp *intel_dp)
4207{
4208 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4209 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4210 int ret;
4211
4212 /* Can't disconnect eDP, but you can close the lid... */
4213 if (is_edp(intel_dp)) {
4214 enum drm_connector_status status;
4215
4216 status = intel_panel_detect(dev);
4217 if (status == connector_status_unknown)
4218 status = connector_status_connected;
4219 return status;
4220 }
4221
4222 ret = g4x_digital_port_connected(dev, intel_dig_port);
4223 if (ret == -EINVAL)
4224 return connector_status_unknown;
4225 else if (ret == 0)
a4fc5ed6
KP		 4226 return connector_status_disconnected;
4227
26d61aad 4228 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4229}
4230
8c241fef 4231static struct edid *
beb60608 4232intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4233{
beb60608 4234 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4235
9cd300e0
JN		 4236 /* use cached edid if we have one */
4237 if (intel_connector->edid) {
9cd300e0
JN		 4238 /* invalid edid */
4239 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4240 return NULL;
4241
55e9edeb 4242 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4243 } else
4244 return drm_get_edid(&intel_connector->base,
4245 &intel_dp->aux.ddc);
4246}
8c241fef 4247
beb60608
CW		 4248static void
4249intel_dp_set_edid(struct intel_dp *intel_dp)
4250{
4251 struct intel_connector *intel_connector = intel_dp->attached_connector;
4252 struct edid *edid;
8c241fef 4253
beb60608
CW		 4254 edid = intel_dp_get_edid(intel_dp);
4255 intel_connector->detect_edid = edid;
4256
4257 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4258 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4259 else
4260 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4261}
4262
beb60608
CW		 4263static void
4264intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4265{
beb60608 4266 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4267
beb60608
CW		 4268 kfree(intel_connector->detect_edid);
4269 intel_connector->detect_edid = NULL;
9cd300e0 4270
beb60608
CW		 4271 intel_dp->has_audio = false;
4272}
d6f24d0f 4273
beb60608
CW		 4274static enum intel_display_power_domain
4275intel_dp_power_get(struct intel_dp *dp)
4276{
4277 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4278 enum intel_display_power_domain power_domain;
4279
4280 power_domain = intel_display_port_power_domain(encoder);
4281 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4282
4283 return power_domain;
4284}
d6f24d0f 4285
beb60608
CW		 4286static void
4287intel_dp_power_put(struct intel_dp *dp,
4288 enum intel_display_power_domain power_domain)
4289{
4290 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4291 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4292}
4293
a9756bb5
ZW		 4294static enum drm_connector_status
4295intel_dp_detect(struct drm_connector *connector, bool force)
4296{
4297 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4298 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4299 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4300 struct drm_device *dev = connector->dev;
a9756bb5 4301 enum drm_connector_status status;
671dedd2 4302 enum intel_display_power_domain power_domain;
0e32b39c 4303 bool ret;
a9756bb5 4304
164c8598 4305 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4306 connector->base.id, connector->name);
beb60608 4307 intel_dp_unset_edid(intel_dp);
164c8598 4308
0e32b39c
DA		 4309 if (intel_dp->is_mst) {
4310 /* MST devices are disconnected from a monitor POV */
4311 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4312 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4313 return connector_status_disconnected;
0e32b39c
DA		 4314 }
4315
beb60608 4316 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4317
d410b56d
CW		 4318 /* Can't disconnect eDP, but you can close the lid... */
4319 if (is_edp(intel_dp))
4320 status = edp_detect(intel_dp);
4321 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4322 status = ironlake_dp_detect(intel_dp);
4323 else
4324 status = g4x_dp_detect(intel_dp);
4325 if (status != connector_status_connected)
c8c8fb33 4326 goto out;
a9756bb5 4327
0d198328
AJ		 4328 intel_dp_probe_oui(intel_dp);
4329
0e32b39c
DA		 4330 ret = intel_dp_probe_mst(intel_dp);
4331 if (ret) {
4332 /* if we are in MST mode then this connector
4333 won't appear connected or have anything with EDID on it */
4334 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4335 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4336 status = connector_status_disconnected;
4337 goto out;
4338 }
4339
beb60608 4340 intel_dp_set_edid(intel_dp);
a9756bb5 4341
d63885da
PZ		 4342 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4343 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4344 status = connector_status_connected;
4345
4346out:
beb60608 4347 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4348 return status;
a4fc5ed6
KP		 4349}
4350
beb60608
CW		 4351static void
4352intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4353{
df0e9248 4354 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4355 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4356 enum intel_display_power_domain power_domain;
a4fc5ed6 4357
beb60608
CW		 4358 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4359 connector->base.id, connector->name);
4360 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4361
beb60608
CW		 4362 if (connector->status != connector_status_connected)
4363 return;
671dedd2 4364
beb60608
CW		 4365 power_domain = intel_dp_power_get(intel_dp);
4366
4367 intel_dp_set_edid(intel_dp);
4368
4369 intel_dp_power_put(intel_dp, power_domain);
4370
4371 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4372 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4373}
4374
4375static int intel_dp_get_modes(struct drm_connector *connector)
4376{
4377 struct intel_connector *intel_connector = to_intel_connector(connector);
4378 struct edid *edid;
4379
4380 edid = intel_connector->detect_edid;
4381 if (edid) {
4382 int ret = intel_connector_update_modes(connector, edid);
4383 if (ret)
4384 return ret;
4385 }
32f9d658 4386
f8779fda 4387 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4388 if (is_edp(intel_attached_dp(connector)) &&
4389 intel_connector->panel.fixed_mode) {
f8779fda 4390 struct drm_display_mode *mode;
beb60608
CW		 4391
4392 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4393 intel_connector->panel.fixed_mode);
f8779fda 4394 if (mode) {
32f9d658
ZW		 4395 drm_mode_probed_add(connector, mode);
4396 return 1;
4397 }
4398 }
beb60608 4399
32f9d658 4400 return 0;
a4fc5ed6
KP		 4401}
4402
1aad7ac0
CW		 4403static bool
4404intel_dp_detect_audio(struct drm_connector *connector)
4405{
1aad7ac0 4406 bool has_audio = false;
beb60608 4407 struct edid *edid;
1aad7ac0 4408
beb60608
CW		 4409 edid = to_intel_connector(connector)->detect_edid;
4410 if (edid)
1aad7ac0 4411 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4412
1aad7ac0
CW		 4413 return has_audio;
4414}
4415
f684960e
CW		 4416static int
4417intel_dp_set_property(struct drm_connector *connector,
4418 struct drm_property *property,
4419 uint64_t val)
4420{
e953fd7b 4421 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4422 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4423 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4424 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4425 int ret;
4426
662595df 4427 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4428 if (ret)
4429 return ret;
4430
3f43c48d 4431 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4432 int i = val;
4433 bool has_audio;
4434
4435 if (i == intel_dp->force_audio)
f684960e
CW		 4436 return 0;
4437
1aad7ac0 4438 intel_dp->force_audio = i;
f684960e 4439
c3e5f67b 4440 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4441 has_audio = intel_dp_detect_audio(connector);
4442 else
c3e5f67b 4443 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4444
4445 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4446 return 0;
4447
1aad7ac0 4448 intel_dp->has_audio = has_audio;
f684960e
CW		 4449 goto done;
4450 }
4451
e953fd7b 4452 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4453 bool old_auto = intel_dp->color_range_auto;
4454 uint32_t old_range = intel_dp->color_range;
4455
55bc60db
VS		 4456 switch (val) {
4457 case INTEL_BROADCAST_RGB_AUTO:
4458 intel_dp->color_range_auto = true;
4459 break;
4460 case INTEL_BROADCAST_RGB_FULL:
4461 intel_dp->color_range_auto = false;
4462 intel_dp->color_range = 0;
4463 break;
4464 case INTEL_BROADCAST_RGB_LIMITED:
4465 intel_dp->color_range_auto = false;
4466 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4467 break;
4468 default:
4469 return -EINVAL;
4470 }
ae4edb80
DV		 4471
4472 if (old_auto == intel_dp->color_range_auto &&
4473 old_range == intel_dp->color_range)
4474 return 0;
4475
e953fd7b
CW		 4476 goto done;
4477 }
4478
53b41837
YN		 4479 if (is_edp(intel_dp) &&
4480 property == connector->dev->mode_config.scaling_mode_property) {
4481 if (val == DRM_MODE_SCALE_NONE) {
4482 DRM_DEBUG_KMS("no scaling not supported\n");
4483 return -EINVAL;
4484 }
4485
4486 if (intel_connector->panel.fitting_mode == val) {
4487 /* the eDP scaling property is not changed */
4488 return 0;
4489 }
4490 intel_connector->panel.fitting_mode = val;
4491
4492 goto done;
4493 }
4494
f684960e
CW		 4495 return -EINVAL;
4496
4497done:
c0c36b94
CW		 4498 if (intel_encoder->base.crtc)
4499 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4500
4501 return 0;
4502}
4503
a4fc5ed6 4504static void
73845adf 4505intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4506{
1d508706 4507 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4508
10e972d3 4509 kfree(intel_connector->detect_edid);
beb60608 4510
9cd300e0
JN		 4511 if (!IS_ERR_OR_NULL(intel_connector->edid))
4512 kfree(intel_connector->edid);
4513
acd8db10
PZ		 4514 /* Can't call is_edp() since the encoder may have been destroyed
4515 * already. */
4516 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4517 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4518
a4fc5ed6 4519 drm_connector_cleanup(connector);
55f78c43 4520 kfree(connector);
a4fc5ed6
KP		 4521}
4522
00c09d70 4523void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4524{
da63a9f2
PZ		 4525 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4526 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4527
4f71d0cb 4528 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4529 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4530 drm_encoder_cleanup(encoder);
bd943159
KP		 4531 if (is_edp(intel_dp)) {
4532 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4533 /*
4534 * vdd might still be enabled do to the delayed vdd off.
4535 * Make sure vdd is actually turned off here.
4536 */
773538e8 4537 pps_lock(intel_dp);
4be73780 4538 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4539 pps_unlock(intel_dp);
4540
01527b31
CT		 4541 if (intel_dp->edp_notifier.notifier_call) {
4542 unregister_reboot_notifier(&intel_dp->edp_notifier);
4543 intel_dp->edp_notifier.notifier_call = NULL;
4544 }
bd943159 4545 }
da63a9f2 4546 kfree(intel_dig_port);
24d05927
DV		 4547}
4548
07f9cd0b
ID		 4549static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4550{
4551 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4552
4553 if (!is_edp(intel_dp))
4554 return;
4555
951468f3
VS		 4556 /*
4557 * vdd might still be enabled do to the delayed vdd off.
4558 * Make sure vdd is actually turned off here.
4559 */
773538e8 4560 pps_lock(intel_dp);
07f9cd0b 4561 edp_panel_vdd_off_sync(intel_dp);
773538e8 4562 pps_unlock(intel_dp);
07f9cd0b
ID		 4563}
4564
6d93c0c4
ID		 4565static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4566{
4567 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4568}
4569
a4fc5ed6 4570static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4571 .dpms = intel_connector_dpms,
a4fc5ed6 4572 .detect = intel_dp_detect,
beb60608 4573 .force = intel_dp_force,
a4fc5ed6 4574 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4575 .set_property = intel_dp_set_property,
73845adf 4576 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4577};
4578
4579static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4580 .get_modes = intel_dp_get_modes,
4581 .mode_valid = intel_dp_mode_valid,
df0e9248 4582 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4583};
4584
a4fc5ed6 4585static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4586 .reset = intel_dp_encoder_reset,
24d05927 4587 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4588};
4589
0e32b39c 4590void
21d40d37 4591intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4592{
0e32b39c 4593 return;
c8110e52 4594}
6207937d 4595
13cf5504
DA		 4596bool
4597intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4598{
4599 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4600 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4601 struct drm_device *dev = intel_dig_port->base.base.dev;
4602 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4603 enum intel_display_power_domain power_domain;
4604 bool ret = true;
4605
0e32b39c
DA		 4606 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4607 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4608
26fbb774
VS		 4609 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4610 port_name(intel_dig_port->port),
0e32b39c 4611 long_hpd ? "long" : "short");
13cf5504 4612
1c767b33
ID		 4613 power_domain = intel_display_port_power_domain(intel_encoder);
4614 intel_display_power_get(dev_priv, power_domain);
4615
0e32b39c 4616 if (long_hpd) {
2a592bec
DA		 4617
4618 if (HAS_PCH_SPLIT(dev)) {
4619 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4620 goto mst_fail;
4621 } else {
4622 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4623 goto mst_fail;
4624 }
0e32b39c
DA		 4625
4626 if (!intel_dp_get_dpcd(intel_dp)) {
4627 goto mst_fail;
4628 }
4629
4630 intel_dp_probe_oui(intel_dp);
4631
4632 if (!intel_dp_probe_mst(intel_dp))
4633 goto mst_fail;
4634
4635 } else {
4636 if (intel_dp->is_mst) {
1c767b33 4637 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4638 goto mst_fail;
4639 }
4640
4641 if (!intel_dp->is_mst) {
4642 /*
4643 * we'll check the link status via the normal hot plug path later -
4644 * but for short hpds we should check it now
4645 */
5b215bcf 4646 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4647 intel_dp_check_link_status(intel_dp);
5b215bcf 4648 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4649 }
4650 }
1c767b33
ID		 4651 ret = false;
4652 goto put_power;
0e32b39c
DA		 4653mst_fail:
4654 /* if we were in MST mode, and device is not there get out of MST mode */
4655 if (intel_dp->is_mst) {
4656 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4657 intel_dp->is_mst = false;
4658 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4659 }
1c767b33
ID		 4660put_power:
4661 intel_display_power_put(dev_priv, power_domain);
4662
4663 return ret;
13cf5504
DA		 4664}
4665
e3421a18
ZW		 4666/* Return which DP Port should be selected for Transcoder DP control */
4667int
0206e353 4668intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4669{
4670 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4671 struct intel_encoder *intel_encoder;
4672 struct intel_dp *intel_dp;
e3421a18 4673
fa90ecef
PZ		 4674 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4675 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4676
fa90ecef
PZ		 4677 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4678 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4679 return intel_dp->output_reg;
e3421a18 4680 }
ea5b213a 4681
e3421a18
ZW		 4682 return -1;
4683}
4684
36e83a18 4685/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4686bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4687{
4688 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4689 union child_device_config *p_child;
36e83a18 4690 int i;
5d8a7752
VS		 4691 static const short port_mapping[] = {
4692 [PORT_B] = PORT_IDPB,
4693 [PORT_C] = PORT_IDPC,
4694 [PORT_D] = PORT_IDPD,
4695 };
36e83a18 4696
3b32a35b
VS		 4697 if (port == PORT_A)
4698 return true;
4699
41aa3448 4700 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4701 return false;
4702
41aa3448
RV		 4703 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4704 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4705
5d8a7752 4706 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4707 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4708 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4709 return true;
4710 }
4711 return false;
4712}
4713
0e32b39c 4714void
f684960e
CW		 4715intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4716{
53b41837
YN		 4717 struct intel_connector *intel_connector = to_intel_connector(connector);
4718
3f43c48d 4719 intel_attach_force_audio_property(connector);
e953fd7b 4720 intel_attach_broadcast_rgb_property(connector);
55bc60db 4721 intel_dp->color_range_auto = true;
53b41837
YN		 4722
4723 if (is_edp(intel_dp)) {
4724 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4725 drm_object_attach_property(
4726 &connector->base,
53b41837 4727 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4728 DRM_MODE_SCALE_ASPECT);
4729 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4730 }
f684960e
CW		 4731}
4732
dada1a9f
ID		 4733static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4734{
4735 intel_dp->last_power_cycle = jiffies;
4736 intel_dp->last_power_on = jiffies;
4737 intel_dp->last_backlight_off = jiffies;
4738}
4739
67a54566
DV		 4740static void
4741intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4742 struct intel_dp *intel_dp)
67a54566
DV		 4743{
4744 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4745 struct edp_power_seq cur, vbt, spec,
4746 *final = &intel_dp->pps_delays;
67a54566 4747 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4748 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4749
e39b999a
VS		 4750 lockdep_assert_held(&dev_priv->pps_mutex);
4751
81ddbc69
VS		 4752 /* already initialized? */
4753 if (final->t11_t12 != 0)
4754 return;
4755
453c5420 4756 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4757 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4758 pp_on_reg = PCH_PP_ON_DELAYS;
4759 pp_off_reg = PCH_PP_OFF_DELAYS;
4760 pp_div_reg = PCH_PP_DIVISOR;
4761 } else {
bf13e81b
JN		 4762 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4763
4764 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4765 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4766 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4767 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4768 }
67a54566
DV		 4769
4770 /* Workaround: Need to write PP_CONTROL with the unlock key as
4771 * the very first thing. */
453c5420 4772 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4773 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4774
453c5420
JB		 4775 pp_on = I915_READ(pp_on_reg);
4776 pp_off = I915_READ(pp_off_reg);
4777 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4778
4779 /* Pull timing values out of registers */
4780 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4781 PANEL_POWER_UP_DELAY_SHIFT;
4782
4783 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4784 PANEL_LIGHT_ON_DELAY_SHIFT;
4785
4786 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4787 PANEL_LIGHT_OFF_DELAY_SHIFT;
4788
4789 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4790 PANEL_POWER_DOWN_DELAY_SHIFT;
4791
4792 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4793 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4794
4795 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4796 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4797
41aa3448 4798 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4799
4800 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4801 * our hw here, which are all in 100usec. */
4802 spec.t1_t3 = 210 * 10;
4803 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4804 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4805 spec.t10 = 500 * 10;
4806 /* This one is special and actually in units of 100ms, but zero
4807 * based in the hw (so we need to add 100 ms). But the sw vbt
4808 * table multiplies it with 1000 to make it in units of 100usec,
4809 * too. */
4810 spec.t11_t12 = (510 + 100) * 10;
4811
4812 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4813 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4814
4815 /* Use the max of the register settings and vbt. If both are
4816 * unset, fall back to the spec limits. */
36b5f425 4817#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4818 spec.field : \
4819 max(cur.field, vbt.field))
4820 assign_final(t1_t3);
4821 assign_final(t8);
4822 assign_final(t9);
4823 assign_final(t10);
4824 assign_final(t11_t12);
4825#undef assign_final
4826
36b5f425 4827#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4828 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4829 intel_dp->backlight_on_delay = get_delay(t8);
4830 intel_dp->backlight_off_delay = get_delay(t9);
4831 intel_dp->panel_power_down_delay = get_delay(t10);
4832 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4833#undef get_delay
4834
f30d26e4
JN		 4835 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4836 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4837 intel_dp->panel_power_cycle_delay);
4838
4839 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4840 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 4841}
4842
4843static void
4844intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4845 struct intel_dp *intel_dp)
f30d26e4
JN		 4846{
4847 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4848 u32 pp_on, pp_off, pp_div, port_sel = 0;
4849 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4850 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4851 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4852 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4853
e39b999a 4854 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4855
4856 if (HAS_PCH_SPLIT(dev)) {
4857 pp_on_reg = PCH_PP_ON_DELAYS;
4858 pp_off_reg = PCH_PP_OFF_DELAYS;
4859 pp_div_reg = PCH_PP_DIVISOR;
4860 } else {
bf13e81b
JN		 4861 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4862
4863 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4864 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4865 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4866 }
4867
b2f19d1a
PZ		 4868 /*
4869 * And finally store the new values in the power sequencer. The
4870 * backlight delays are set to 1 because we do manual waits on them. For
4871 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4872 * we'll end up waiting for the backlight off delay twice: once when we
4873 * do the manual sleep, and once when we disable the panel and wait for
4874 * the PP_STATUS bit to become zero.
4875 */
f30d26e4 4876 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4877 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4878 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4879 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4880 /* Compute the divisor for the pp clock, simply match the Bspec
4881 * formula. */
453c5420 4882 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4883 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4884 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4885
4886 /* Haswell doesn't have any port selection bits for the panel
4887 * power sequencer any more. */
bc7d38a4 4888 if (IS_VALLEYVIEW(dev)) {
ad933b56 4889 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4890 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4891 if (port == PORT_A)
a24c144c 4892 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4893 else
a24c144c 4894 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4895 }
4896
453c5420
JB		 4897 pp_on |= port_sel;
4898
4899 I915_WRITE(pp_on_reg, pp_on);
4900 I915_WRITE(pp_off_reg, pp_off);
4901 I915_WRITE(pp_div_reg, pp_div);
67a54566 4902
67a54566 4903 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4904 I915_READ(pp_on_reg),
4905 I915_READ(pp_off_reg),
4906 I915_READ(pp_div_reg));
f684960e
CW		 4907}
4908
439d7ac0
PB		 4909void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4910{
4911 struct drm_i915_private *dev_priv = dev->dev_private;
4912 struct intel_encoder *encoder;
4913 struct intel_dp *intel_dp = NULL;
4914 struct intel_crtc_config *config = NULL;
4915 struct intel_crtc *intel_crtc = NULL;
4916 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4917 u32 reg, val;
4918 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4919
4920 if (refresh_rate <= 0) {
4921 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4922 return;
4923 }
4924
4925 if (intel_connector == NULL) {
4926 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4927 return;
4928 }
4929
1fcc9d1c
DV		 4930 /*
4931 * FIXME: This needs proper synchronization with psr state. But really
4932 * hard to tell without seeing the user of this function of this code.
4933 * Check locking and ordering once that lands.
4934 */
439d7ac0
PB		 4935 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4936 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4937 return;
4938 }
4939
4940 encoder = intel_attached_encoder(&intel_connector->base);
4941 intel_dp = enc_to_intel_dp(&encoder->base);
4942 intel_crtc = encoder->new_crtc;
4943
4944 if (!intel_crtc) {
4945 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4946 return;
4947 }
4948
4949 config = &intel_crtc->config;
4950
4951 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4952 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4953 return;
4954 }
4955
4956 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4957 index = DRRS_LOW_RR;
4958
4959 if (index == intel_dp->drrs_state.refresh_rate_type) {
4960 DRM_DEBUG_KMS(
4961 "DRRS requested for previously set RR...ignoring\n");
4962 return;
4963 }
4964
4965 if (!intel_crtc->active) {
4966 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4967 return;
4968 }
4969
4970 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4971 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4972 val = I915_READ(reg);
4973 if (index > DRRS_HIGH_RR) {
4974 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4975 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4976 } else {
4977 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4978 }
4979 I915_WRITE(reg, val);
4980 }
4981
4982 /*
4983 * mutex taken to ensure that there is no race between differnt
4984 * drrs calls trying to update refresh rate. This scenario may occur
4985 * in future when idleness detection based DRRS in kernel and
4986 * possible calls from user space to set differnt RR are made.
4987 */
4988
4989 mutex_lock(&intel_dp->drrs_state.mutex);
4990
4991 intel_dp->drrs_state.refresh_rate_type = index;
4992
4993 mutex_unlock(&intel_dp->drrs_state.mutex);
4994
4995 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4996}
4997
4f9db5b5
PB		 4998static struct drm_display_mode *
4999intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
5000 struct intel_connector *intel_connector,
5001 struct drm_display_mode *fixed_mode)
5002{
5003 struct drm_connector *connector = &intel_connector->base;
5004 struct intel_dp *intel_dp = &intel_dig_port->dp;
5005 struct drm_device *dev = intel_dig_port->base.base.dev;
5006 struct drm_i915_private *dev_priv = dev->dev_private;
5007 struct drm_display_mode *downclock_mode = NULL;
5008
5009 if (INTEL_INFO(dev)->gen <= 6) {
5010 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5011 return NULL;
5012 }
5013
5014 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5015 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5016 return NULL;
5017 }
5018
5019 downclock_mode = intel_find_panel_downclock
5020 (dev, fixed_mode, connector);
5021
5022 if (!downclock_mode) {
4079b8d1 5023 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 5024 return NULL;
5025 }
5026
439d7ac0
PB		 5027 dev_priv->drrs.connector = intel_connector;
5028
5029 mutex_init(&intel_dp->drrs_state.mutex);
5030
4f9db5b5
PB		 5031 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
5032
5033 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5034 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5035 return downclock_mode;
5036}
5037
aba86890
ID		 5038void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
5039{
5040 struct drm_device *dev = intel_encoder->base.dev;
5041 struct drm_i915_private *dev_priv = dev->dev_private;
5042 struct intel_dp *intel_dp;
5043 enum intel_display_power_domain power_domain;
5044
5045 if (intel_encoder->type != INTEL_OUTPUT_EDP)
5046 return;
5047
5048 intel_dp = enc_to_intel_dp(&intel_encoder->base);
773538e8
VS		 5049
5050 pps_lock(intel_dp);
5051
aba86890 5052 if (!edp_have_panel_vdd(intel_dp))
e39b999a 5053 goto out;
aba86890
ID		 5054 /*
5055 * The VDD bit needs a power domain reference, so if the bit is
5056 * already enabled when we boot or resume, grab this reference and
5057 * schedule a vdd off, so we don't hold on to the reference
5058 * indefinitely.
5059 */
5060 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5061 power_domain = intel_display_port_power_domain(intel_encoder);
5062 intel_display_power_get(dev_priv, power_domain);
5063
5064 edp_panel_vdd_schedule_off(intel_dp);
e39b999a 5065 out:
773538e8 5066 pps_unlock(intel_dp);
aba86890
ID		 5067}
5068
ed92f0b2 5069static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5070 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5071{
5072 struct drm_connector *connector = &intel_connector->base;
5073 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5074 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5075 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5076 struct drm_i915_private *dev_priv = dev->dev_private;
5077 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5078 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5079 bool has_dpcd;
5080 struct drm_display_mode *scan;
5081 struct edid *edid;
5082
4f9db5b5
PB		 5083 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
5084
ed92f0b2
PZ		 5085 if (!is_edp(intel_dp))
5086 return true;
5087
aba86890 5088 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 5089
ed92f0b2 5090 /* Cache DPCD and EDID for edp. */
ed92f0b2 5091 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5092
5093 if (has_dpcd) {
5094 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5095 dev_priv->no_aux_handshake =
5096 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5097 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5098 } else {
5099 /* if this fails, presume the device is a ghost */
5100 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5101 return false;
5102 }
5103
5104 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5105 pps_lock(intel_dp);
36b5f425 5106 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5107 pps_unlock(intel_dp);
ed92f0b2 5108
060c8778 5109 mutex_lock(&dev->mode_config.mutex);
0b99836f 5110 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5111 if (edid) {
5112 if (drm_add_edid_modes(connector, edid)) {
5113 drm_mode_connector_update_edid_property(connector,
5114 edid);
5115 drm_edid_to_eld(connector, edid);
5116 } else {
5117 kfree(edid);
5118 edid = ERR_PTR(-EINVAL);
5119 }
5120 } else {
5121 edid = ERR_PTR(-ENOENT);
5122 }
5123 intel_connector->edid = edid;
5124
5125 /* prefer fixed mode from EDID if available */
5126 list_for_each_entry(scan, &connector->probed_modes, head) {
5127 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5128 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 5129 downclock_mode = intel_dp_drrs_init(
5130 intel_dig_port,
5131 intel_connector, fixed_mode);
ed92f0b2
PZ		 5132 break;
5133 }
5134 }
5135
5136 /* fallback to VBT if available for eDP */
5137 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5138 fixed_mode = drm_mode_duplicate(dev,
5139 dev_priv->vbt.lfp_lvds_vbt_mode);
5140 if (fixed_mode)
5141 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5142 }
060c8778 5143 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5144
01527b31
CT		 5145 if (IS_VALLEYVIEW(dev)) {
5146 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5147 register_reboot_notifier(&intel_dp->edp_notifier);
5148 }
5149
4f9db5b5 5150 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5151 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 5152 intel_panel_setup_backlight(connector);
5153
5154 return true;
5155}
5156
16c25533 5157bool
f0fec3f2
PZ		 5158intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5159 struct intel_connector *intel_connector)
a4fc5ed6 5160{
f0fec3f2
PZ		 5161 struct drm_connector *connector = &intel_connector->base;
5162 struct intel_dp *intel_dp = &intel_dig_port->dp;
5163 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5164 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5165 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5166 enum port port = intel_dig_port->port;
0b99836f 5167 int type;
a4fc5ed6 5168
a4a5d2f8
VS		 5169 intel_dp->pps_pipe = INVALID_PIPE;
5170
ec5b01dd 5171 /* intel_dp vfuncs */
b6b5e383
DL		 5172 if (INTEL_INFO(dev)->gen >= 9)
5173 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5174 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5175 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5176 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5177 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5178 else if (HAS_PCH_SPLIT(dev))
5179 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5180 else
5181 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5182
b9ca5fad
DL		 5183 if (INTEL_INFO(dev)->gen >= 9)
5184 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5185 else
5186 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5187
0767935e
DV		 5188 /* Preserve the current hw state. */
5189 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5190 intel_dp->attached_connector = intel_connector;
3d3dc149 5191
3b32a35b 5192 if (intel_dp_is_edp(dev, port))
b329530c 5193 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5194 else
5195 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5196
f7d24902
ID		 5197 /*
5198 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5199 * for DP the encoder type can be set by the caller to
5200 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5201 */
5202 if (type == DRM_MODE_CONNECTOR_eDP)
5203 intel_encoder->type = INTEL_OUTPUT_EDP;
5204
c17ed5b5
VS		 5205 /* eDP only on port B and/or C on vlv/chv */
5206 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5207 port != PORT_B && port != PORT_C))
5208 return false;
5209
e7281eab
ID		 5210 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5211 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5212 port_name(port));
5213
b329530c 5214 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5215 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5216
a4fc5ed6
KP		 5217 connector->interlace_allowed = true;
5218 connector->doublescan_allowed = 0;
5219
f0fec3f2 5220 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5221 edp_panel_vdd_work);
a4fc5ed6 5222
df0e9248 5223 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5224 drm_connector_register(connector);
a4fc5ed6 5225
affa9354 5226 if (HAS_DDI(dev))
bcbc889b
PZ		 5227 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5228 else
5229 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5230 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5231
0b99836f 5232 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5233 switch (port) {
5234 case PORT_A:
1d843f9d 5235 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5236 break;
5237 case PORT_B:
1d843f9d 5238 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5239 break;
5240 case PORT_C:
1d843f9d 5241 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5242 break;
5243 case PORT_D:
1d843f9d 5244 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5245 break;
5246 default:
ad1c0b19 5247 BUG();
5eb08b69
ZW		 5248 }
5249
dada1a9f 5250 if (is_edp(intel_dp)) {
773538e8 5251 pps_lock(intel_dp);
a4a5d2f8
VS		 5252 if (IS_VALLEYVIEW(dev)) {
5253 vlv_initial_power_sequencer_setup(intel_dp);
5254 } else {
5255 intel_dp_init_panel_power_timestamps(intel_dp);
36b5f425 5256 intel_dp_init_panel_power_sequencer(dev, intel_dp);
a4a5d2f8 5257 }
773538e8 5258 pps_unlock(intel_dp);
dada1a9f 5259 }
0095e6dc 5260
9d1a1031 5261 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5262
0e32b39c
DA		 5263 /* init MST on ports that can support it */
5264 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5265 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5266 intel_dp_mst_encoder_init(intel_dig_port,
5267 intel_connector->base.base.id);
0e32b39c
DA		 5268 }
5269 }
5270
36b5f425 5271 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5272 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5273 if (is_edp(intel_dp)) {
5274 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5275 /*
5276 * vdd might still be enabled do to the delayed vdd off.
5277 * Make sure vdd is actually turned off here.
5278 */
773538e8 5279 pps_lock(intel_dp);
4be73780 5280 edp_panel_vdd_off_sync(intel_dp);
773538e8 5281 pps_unlock(intel_dp);
15b1d171 5282 }
34ea3d38 5283 drm_connector_unregister(connector);
b2f246a8 5284 drm_connector_cleanup(connector);
16c25533 5285 return false;
b2f246a8 5286 }
32f9d658 5287
f684960e
CW		 5288 intel_dp_add_properties(intel_dp, connector);
5289
a4fc5ed6
KP		 5290 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5291 * 0xd. Failure to do so will result in spurious interrupts being
5292 * generated on the port when a cable is not attached.
5293 */
5294 if (IS_G4X(dev) && !IS_GM45(dev)) {
5295 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5296 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5297 }
16c25533
PZ		 5298
5299 return true;
a4fc5ed6 5300}
f0fec3f2
PZ		 5301
5302void
5303intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5304{
13cf5504 5305 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5306 struct intel_digital_port *intel_dig_port;
5307 struct intel_encoder *intel_encoder;
5308 struct drm_encoder *encoder;
5309 struct intel_connector *intel_connector;
5310
b14c5679 5311 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5312 if (!intel_dig_port)
5313 return;
5314
b14c5679 5315 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5316 if (!intel_connector) {
5317 kfree(intel_dig_port);
5318 return;
5319 }
5320
5321 intel_encoder = &intel_dig_port->base;
5322 encoder = &intel_encoder->base;
5323
5324 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5325 DRM_MODE_ENCODER_TMDS);
5326
5bfe2ac0 5327 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5328 intel_encoder->disable = intel_disable_dp;
00c09d70 5329 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5330 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5331 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5332 if (IS_CHERRYVIEW(dev)) {
9197c88b 5333 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5334 intel_encoder->pre_enable = chv_pre_enable_dp;
5335 intel_encoder->enable = vlv_enable_dp;
580d3811 5336 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5337 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5338 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5339 intel_encoder->pre_enable = vlv_pre_enable_dp;
5340 intel_encoder->enable = vlv_enable_dp;
49277c31 5341 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5342 } else {
ecff4f3b
JN		 5343 intel_encoder->pre_enable = g4x_pre_enable_dp;
5344 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5345 if (INTEL_INFO(dev)->gen >= 5)
5346 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5347 }
f0fec3f2 5348
174edf1f 5349 intel_dig_port->port = port;
f0fec3f2
PZ		 5350 intel_dig_port->dp.output_reg = output_reg;
5351
00c09d70 5352 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5353 if (IS_CHERRYVIEW(dev)) {
5354 if (port == PORT_D)
5355 intel_encoder->crtc_mask = 1 << 2;
5356 else
5357 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5358 } else {
5359 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5360 }
bc079e8b 5361 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5362 intel_encoder->hot_plug = intel_dp_hot_plug;
5363
13cf5504
DA		 5364 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5365 dev_priv->hpd_irq_port[port] = intel_dig_port;
5366
15b1d171
PZ		 5367 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5368 drm_encoder_cleanup(encoder);
5369 kfree(intel_dig_port);
b2f246a8 5370 kfree(intel_connector);
15b1d171 5371 }
f0fec3f2 5372}
0e32b39c
DA		 5373
5374void intel_dp_mst_suspend(struct drm_device *dev)
5375{
5376 struct drm_i915_private *dev_priv = dev->dev_private;
5377 int i;
5378
5379 /* disable MST */
5380 for (i = 0; i < I915_MAX_PORTS; i++) {
5381 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5382 if (!intel_dig_port)
5383 continue;
5384
5385 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5386 if (!intel_dig_port->dp.can_mst)
5387 continue;
5388 if (intel_dig_port->dp.is_mst)
5389 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5390 }
5391 }
5392}
5393
5394void intel_dp_mst_resume(struct drm_device *dev)
5395{
5396 struct drm_i915_private *dev_priv = dev->dev_private;
5397 int i;
5398
5399 for (i = 0; i < I915_MAX_PORTS; i++) {
5400 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5401 if (!intel_dig_port)
5402 continue;
5403 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5404 int ret;
5405
5406 if (!intel_dig_port->dp.can_mst)
5407 continue;
5408
5409 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5410 if (ret != 0) {
5411 intel_dp_check_mst_status(&intel_dig_port->dp);
5412 }
5413 }
5414 }
5415}
Linux kernel - Deliverables
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