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drm/i915: Add PSR docbook
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 116static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 117static void vlv_steal_power_sequencer(struct drm_device *dev,
118 enum pipe pipe);
a4fc5ed6 119
0e32b39c 120int
ea5b213a 121intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 122{
7183dc29 123 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 124 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 125
126 switch (max_link_bw) {
127 case DP_LINK_BW_1_62:
128 case DP_LINK_BW_2_7:
129 break;
d4eead50 130 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 131 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
132 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 133 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
134 max_link_bw = DP_LINK_BW_5_4;
135 else
136 max_link_bw = DP_LINK_BW_2_7;
d4eead50 137 break;
a4fc5ed6 138 default:
d4eead50
ID		 139 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
140 max_link_bw);
a4fc5ed6
KP		 141 max_link_bw = DP_LINK_BW_1_62;
142 break;
143 }
144 return max_link_bw;
145}
146
eeb6324d
PZ		 147static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
148{
149 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
150 struct drm_device *dev = intel_dig_port->base.base.dev;
151 u8 source_max, sink_max;
152
153 source_max = 4;
154 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
155 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
156 source_max = 2;
157
158 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
159
160 return min(source_max, sink_max);
161}
162
cd9dde44
AJ		 163/*
164 * The units on the numbers in the next two are... bizarre. Examples will
165 * make it clearer; this one parallels an example in the eDP spec.
166 *
167 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
168 *
169 * 270000 * 1 * 8 / 10 == 216000
170 *
171 * The actual data capacity of that configuration is 2.16Gbit/s, so the
172 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
173 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
174 * 119000. At 18bpp that's 2142000 kilobits per second.
175 *
176 * Thus the strange-looking division by 10 in intel_dp_link_required, to
177 * get the result in decakilobits instead of kilobits.
178 */
179
a4fc5ed6 180static int
c898261c 181intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 182{
cd9dde44 183 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 184}
185
fe27d53e
DA		 186static int
187intel_dp_max_data_rate(int max_link_clock, int max_lanes)
188{
189 return (max_link_clock * max_lanes * 8) / 10;
190}
191
c19de8eb 192static enum drm_mode_status
a4fc5ed6
KP		 193intel_dp_mode_valid(struct drm_connector *connector,
194 struct drm_display_mode *mode)
195{
df0e9248 196 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 197 struct intel_connector *intel_connector = to_intel_connector(connector);
198 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 199 int target_clock = mode->clock;
200 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 201
dd06f90e
JN		 202 if (is_edp(intel_dp) && fixed_mode) {
203 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 204 return MODE_PANEL;
205
dd06f90e 206 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 207 return MODE_PANEL;
03afc4a2
DV		 208
209 target_clock = fixed_mode->clock;
7de56f43
ZY		 210 }
211
36008365 212 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 213 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 214
215 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
216 mode_rate = intel_dp_link_required(target_clock, 18);
217
218 if (mode_rate > max_rate)
c4867936 219 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 220
221 if (mode->clock < 10000)
222 return MODE_CLOCK_LOW;
223
0af78a2b
DV		 224 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
225 return MODE_H_ILLEGAL;
226
a4fc5ed6
KP		 227 return MODE_OK;
228}
229
a4f1289e 230uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 231{
232 int i;
233 uint32_t v = 0;
234
235 if (src_bytes > 4)
236 src_bytes = 4;
237 for (i = 0; i < src_bytes; i++)
238 v |= ((uint32_t) src[i]) << ((3-i) * 8);
239 return v;
240}
241
a4f1289e 242void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 243{
244 int i;
245 if (dst_bytes > 4)
246 dst_bytes = 4;
247 for (i = 0; i < dst_bytes; i++)
248 dst[i] = src >> ((3-i) * 8);
249}
250
fb0f8fbf
KP		 251/* hrawclock is 1/4 the FSB frequency */
252static int
253intel_hrawclk(struct drm_device *dev)
254{
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 uint32_t clkcfg;
257
9473c8f4
VP		 258 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
259 if (IS_VALLEYVIEW(dev))
260 return 200;
261
fb0f8fbf
KP		 262 clkcfg = I915_READ(CLKCFG);
263 switch (clkcfg & CLKCFG_FSB_MASK) {
264 case CLKCFG_FSB_400:
265 return 100;
266 case CLKCFG_FSB_533:
267 return 133;
268 case CLKCFG_FSB_667:
269 return 166;
270 case CLKCFG_FSB_800:
271 return 200;
272 case CLKCFG_FSB_1067:
273 return 266;
274 case CLKCFG_FSB_1333:
275 return 333;
276 /* these two are just a guess; one of them might be right */
277 case CLKCFG_FSB_1600:
278 case CLKCFG_FSB_1600_ALT:
279 return 400;
280 default:
281 return 133;
282 }
283}
284
bf13e81b
JN		 285static void
286intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 287 struct intel_dp *intel_dp);
bf13e81b
JN		 288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 290 struct intel_dp *intel_dp);
bf13e81b 291
773538e8
VS		 292static void pps_lock(struct intel_dp *intel_dp)
293{
294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295 struct intel_encoder *encoder = &intel_dig_port->base;
296 struct drm_device *dev = encoder->base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum intel_display_power_domain power_domain;
299
300 /*
301 * See vlv_power_sequencer_reset() why we need
302 * a power domain reference here.
303 */
304 power_domain = intel_display_port_power_domain(encoder);
305 intel_display_power_get(dev_priv, power_domain);
306
307 mutex_lock(&dev_priv->pps_mutex);
308}
309
310static void pps_unlock(struct intel_dp *intel_dp)
311{
312 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
313 struct intel_encoder *encoder = &intel_dig_port->base;
314 struct drm_device *dev = encoder->base.dev;
315 struct drm_i915_private *dev_priv = dev->dev_private;
316 enum intel_display_power_domain power_domain;
317
318 mutex_unlock(&dev_priv->pps_mutex);
319
320 power_domain = intel_display_port_power_domain(encoder);
321 intel_display_power_put(dev_priv, power_domain);
322}
323
961a0db0
VS		 324static void
325vlv_power_sequencer_kick(struct intel_dp *intel_dp)
326{
327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
328 struct drm_device *dev = intel_dig_port->base.base.dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
330 enum pipe pipe = intel_dp->pps_pipe;
d288f65f 331 bool pll_enabled;
961a0db0
VS		 332 uint32_t DP;
333
334 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
335 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
336 pipe_name(pipe), port_name(intel_dig_port->port)))
337 return;
338
339 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
340 pipe_name(pipe), port_name(intel_dig_port->port));
341
342 /* Preserve the BIOS-computed detected bit. This is
343 * supposed to be read-only.
344 */
345 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
346 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
347 DP |= DP_PORT_WIDTH(1);
348 DP |= DP_LINK_TRAIN_PAT_1;
349
350 if (IS_CHERRYVIEW(dev))
351 DP |= DP_PIPE_SELECT_CHV(pipe);
352 else if (pipe == PIPE_B)
353 DP |= DP_PIPEB_SELECT;
354
d288f65f
VS		 355 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
356
357 /*
358 * The DPLL for the pipe must be enabled for this to work.
359 * So enable temporarily it if it's not already enabled.
360 */
361 if (!pll_enabled)
362 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
363 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
364
961a0db0
VS		 365 /*
366 * Similar magic as in intel_dp_enable_port().
367 * We _must_ do this port enable + disable trick
368 * to make this power seqeuencer lock onto the port.
369 * Otherwise even VDD force bit won't work.
370 */
371 I915_WRITE(intel_dp->output_reg, DP);
372 POSTING_READ(intel_dp->output_reg);
373
374 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
375 POSTING_READ(intel_dp->output_reg);
376
377 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
378 POSTING_READ(intel_dp->output_reg);
d288f65f
VS		 379
380 if (!pll_enabled)
381 vlv_force_pll_off(dev, pipe);
961a0db0
VS		 382}
383
bf13e81b
JN		 384static enum pipe
385vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
386{
387 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 388 struct drm_device *dev = intel_dig_port->base.base.dev;
389 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 390 struct intel_encoder *encoder;
391 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 392 enum pipe pipe;
bf13e81b 393
e39b999a 394 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 395
a8c3344e
VS		 396 /* We should never land here with regular DP ports */
397 WARN_ON(!is_edp(intel_dp));
398
a4a5d2f8
VS		 399 if (intel_dp->pps_pipe != INVALID_PIPE)
400 return intel_dp->pps_pipe;
401
402 /*
403 * We don't have power sequencer currently.
404 * Pick one that's not used by other ports.
405 */
406 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
407 base.head) {
408 struct intel_dp *tmp;
409
410 if (encoder->type != INTEL_OUTPUT_EDP)
411 continue;
412
413 tmp = enc_to_intel_dp(&encoder->base);
414
415 if (tmp->pps_pipe != INVALID_PIPE)
416 pipes &= ~(1 << tmp->pps_pipe);
417 }
418
419 /*
420 * Didn't find one. This should not happen since there
421 * are two power sequencers and up to two eDP ports.
422 */
423 if (WARN_ON(pipes == 0))
a8c3344e
VS		 424 pipe = PIPE_A;
425 else
426 pipe = ffs(pipes) - 1;
a4a5d2f8 427
a8c3344e
VS		 428 vlv_steal_power_sequencer(dev, pipe);
429 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 430
431 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
432 pipe_name(intel_dp->pps_pipe),
433 port_name(intel_dig_port->port));
434
435 /* init power sequencer on this pipe and port */
36b5f425
VS		 436 intel_dp_init_panel_power_sequencer(dev, intel_dp);
437 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 438
961a0db0
VS		 439 /*
440 * Even vdd force doesn't work until we've made
441 * the power sequencer lock in on the port.
442 */
443 vlv_power_sequencer_kick(intel_dp);
444
a4a5d2f8
VS		 445 return intel_dp->pps_pipe;
446}
447
6491ab27
VS		 448typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
449 enum pipe pipe);
450
451static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
452 enum pipe pipe)
453{
454 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
455}
456
457static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
458 enum pipe pipe)
459{
460 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
461}
462
463static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
464 enum pipe pipe)
465{
466 return true;
467}
bf13e81b 468
a4a5d2f8 469static enum pipe
6491ab27
VS		 470vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
471 enum port port,
472 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 473{
474 enum pipe pipe;
bf13e81b 475
bf13e81b
JN		 476 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
477 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
478 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 479
480 if (port_sel != PANEL_PORT_SELECT_VLV(port))
481 continue;
482
6491ab27
VS		 483 if (!pipe_check(dev_priv, pipe))
484 continue;
485
a4a5d2f8 486 return pipe;
bf13e81b
JN		 487 }
488
a4a5d2f8
VS		 489 return INVALID_PIPE;
490}
491
492static void
493vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
494{
495 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
496 struct drm_device *dev = intel_dig_port->base.base.dev;
497 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 498 enum port port = intel_dig_port->port;
499
500 lockdep_assert_held(&dev_priv->pps_mutex);
501
502 /* try to find a pipe with this port selected */
6491ab27
VS		 503 /* first pick one where the panel is on */
504 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
505 vlv_pipe_has_pp_on);
506 /* didn't find one? pick one where vdd is on */
507 if (intel_dp->pps_pipe == INVALID_PIPE)
508 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
509 vlv_pipe_has_vdd_on);
510 /* didn't find one? pick one with just the correct port */
511 if (intel_dp->pps_pipe == INVALID_PIPE)
512 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
513 vlv_pipe_any);
a4a5d2f8
VS		 514
515 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
516 if (intel_dp->pps_pipe == INVALID_PIPE) {
517 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
518 port_name(port));
519 return;
bf13e81b
JN		 520 }
521
a4a5d2f8
VS		 522 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
523 port_name(port), pipe_name(intel_dp->pps_pipe));
524
36b5f425
VS		 525 intel_dp_init_panel_power_sequencer(dev, intel_dp);
526 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 527}
528
773538e8
VS		 529void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
530{
531 struct drm_device *dev = dev_priv->dev;
532 struct intel_encoder *encoder;
533
534 if (WARN_ON(!IS_VALLEYVIEW(dev)))
535 return;
536
537 /*
538 * We can't grab pps_mutex here due to deadlock with power_domain
539 * mutex when power_domain functions are called while holding pps_mutex.
540 * That also means that in order to use pps_pipe the code needs to
541 * hold both a power domain reference and pps_mutex, and the power domain
542 * reference get/put must be done while _not_ holding pps_mutex.
543 * pps_{lock,unlock}() do these steps in the correct order, so one
544 * should use them always.
545 */
546
547 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
548 struct intel_dp *intel_dp;
549
550 if (encoder->type != INTEL_OUTPUT_EDP)
551 continue;
552
553 intel_dp = enc_to_intel_dp(&encoder->base);
554 intel_dp->pps_pipe = INVALID_PIPE;
555 }
bf13e81b
JN		 556}
557
558static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
559{
560 struct drm_device *dev = intel_dp_to_dev(intel_dp);
561
562 if (HAS_PCH_SPLIT(dev))
563 return PCH_PP_CONTROL;
564 else
565 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
566}
567
568static u32 _pp_stat_reg(struct intel_dp *intel_dp)
569{
570 struct drm_device *dev = intel_dp_to_dev(intel_dp);
571
572 if (HAS_PCH_SPLIT(dev))
573 return PCH_PP_STATUS;
574 else
575 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
576}
577
01527b31
CT		 578/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
579 This function only applicable when panel PM state is not to be tracked */
580static int edp_notify_handler(struct notifier_block *this, unsigned long code,
581 void *unused)
582{
583 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
584 edp_notifier);
585 struct drm_device *dev = intel_dp_to_dev(intel_dp);
586 struct drm_i915_private *dev_priv = dev->dev_private;
587 u32 pp_div;
588 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 589
590 if (!is_edp(intel_dp) || code != SYS_RESTART)
591 return 0;
592
773538e8 593 pps_lock(intel_dp);
e39b999a 594
01527b31 595 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 596 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
597
01527b31
CT		 598 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
599 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
600 pp_div = I915_READ(pp_div_reg);
601 pp_div &= PP_REFERENCE_DIVIDER_MASK;
602
603 /* 0x1F write to PP_DIV_REG sets max cycle delay */
604 I915_WRITE(pp_div_reg, pp_div | 0x1F);
605 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
606 msleep(intel_dp->panel_power_cycle_delay);
607 }
608
773538e8 609 pps_unlock(intel_dp);
e39b999a 610
01527b31
CT		 611 return 0;
612}
613
4be73780 614static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 615{
30add22d 616 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 617 struct drm_i915_private *dev_priv = dev->dev_private;
618
e39b999a
VS		 619 lockdep_assert_held(&dev_priv->pps_mutex);
620
9a42356b
VS		 621 if (IS_VALLEYVIEW(dev) &&
622 intel_dp->pps_pipe == INVALID_PIPE)
623 return false;
624
bf13e81b 625 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 626}
627
4be73780 628static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 629{
30add22d 630 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 631 struct drm_i915_private *dev_priv = dev->dev_private;
632
e39b999a
VS		 633 lockdep_assert_held(&dev_priv->pps_mutex);
634
9a42356b
VS		 635 if (IS_VALLEYVIEW(dev) &&
636 intel_dp->pps_pipe == INVALID_PIPE)
637 return false;
638
773538e8 639 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 640}
641
9b984dae
KP		 642static void
643intel_dp_check_edp(struct intel_dp *intel_dp)
644{
30add22d 645 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 646 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 647
9b984dae
KP		 648 if (!is_edp(intel_dp))
649 return;
453c5420 650
4be73780 651 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 652 WARN(1, "eDP powered off while attempting aux channel communication.\n");
653 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 654 I915_READ(_pp_stat_reg(intel_dp)),
655 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 656 }
657}
658
9ee32fea
DV		 659static uint32_t
660intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
661{
662 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
663 struct drm_device *dev = intel_dig_port->base.base.dev;
664 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 665 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 666 uint32_t status;
667 bool done;
668
ef04f00d 669#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 670 if (has_aux_irq)
b18ac466 671 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 672 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 673 else
674 done = wait_for_atomic(C, 10) == 0;
675 if (!done)
676 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
677 has_aux_irq);
678#undef C
679
680 return status;
681}
682
ec5b01dd 683static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 684{
174edf1f
PZ		 685 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
686 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 687
ec5b01dd
DL		 688 /*
689 * The clock divider is based off the hrawclk, and would like to run at
690 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 691 */
ec5b01dd
DL		 692 return index ? 0 : intel_hrawclk(dev) / 2;
693}
694
695static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
696{
697 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
698 struct drm_device *dev = intel_dig_port->base.base.dev;
699
700 if (index)
701 return 0;
702
703 if (intel_dig_port->port == PORT_A) {
704 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 705 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 706 else
b84a1cf8 707 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 708 } else {
709 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
710 }
711}
712
713static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
714{
715 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
716 struct drm_device *dev = intel_dig_port->base.base.dev;
717 struct drm_i915_private *dev_priv = dev->dev_private;
718
719 if (intel_dig_port->port == PORT_A) {
720 if (index)
721 return 0;
722 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 723 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
724 /* Workaround for non-ULT HSW */
bc86625a
CW		 725 switch (index) {
726 case 0: return 63;
727 case 1: return 72;
728 default: return 0;
729 }
ec5b01dd 730 } else {
bc86625a 731 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 732 }
b84a1cf8
RV		 733}
734
ec5b01dd
DL		 735static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
736{
737 return index ? 0 : 100;
738}
739
b6b5e383
DL		 740static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
741{
742 /*
743 * SKL doesn't need us to program the AUX clock divider (Hardware will
744 * derive the clock from CDCLK automatically). We still implement the
745 * get_aux_clock_divider vfunc to plug-in into the existing code.
746 */
747 return index ? 0 : 1;
748}
749
5ed12a19
DL		 750static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
751 bool has_aux_irq,
752 int send_bytes,
753 uint32_t aux_clock_divider)
754{
755 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
756 struct drm_device *dev = intel_dig_port->base.base.dev;
757 uint32_t precharge, timeout;
758
759 if (IS_GEN6(dev))
760 precharge = 3;
761 else
762 precharge = 5;
763
764 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
765 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
766 else
767 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
768
769 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 770 DP_AUX_CH_CTL_DONE |
5ed12a19 771 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 772 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 773 timeout |
788d4433 774 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 775 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
776 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 777 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 778}
779
b9ca5fad
DL		 780static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
781 bool has_aux_irq,
782 int send_bytes,
783 uint32_t unused)
784{
785 return DP_AUX_CH_CTL_SEND_BUSY |
786 DP_AUX_CH_CTL_DONE |
787 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788 DP_AUX_CH_CTL_TIME_OUT_ERROR |
789 DP_AUX_CH_CTL_TIME_OUT_1600us |
790 DP_AUX_CH_CTL_RECEIVE_ERROR |
791 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
792 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
793}
794
b84a1cf8
RV		 795static int
796intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 797 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 798 uint8_t *recv, int recv_size)
799{
800 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
801 struct drm_device *dev = intel_dig_port->base.base.dev;
802 struct drm_i915_private *dev_priv = dev->dev_private;
803 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
804 uint32_t ch_data = ch_ctl + 4;
bc86625a 805 uint32_t aux_clock_divider;
b84a1cf8
RV		 806 int i, ret, recv_bytes;
807 uint32_t status;
5ed12a19 808 int try, clock = 0;
4e6b788c 809 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 810 bool vdd;
811
773538e8 812 pps_lock(intel_dp);
e39b999a 813
72c3500a
VS		 814 /*
815 * We will be called with VDD already enabled for dpcd/edid/oui reads.
816 * In such cases we want to leave VDD enabled and it's up to upper layers
817 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
818 * ourselves.
819 */
1e0560e0 820 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 821
822 /* dp aux is extremely sensitive to irq latency, hence request the
823 * lowest possible wakeup latency and so prevent the cpu from going into
824 * deep sleep states.
825 */
826 pm_qos_update_request(&dev_priv->pm_qos, 0);
827
828 intel_dp_check_edp(intel_dp);
5eb08b69 829
c67a470b
PZ		 830 intel_aux_display_runtime_get(dev_priv);
831
11bee43e
JB		 832 /* Try to wait for any previous AUX channel activity */
833 for (try = 0; try < 3; try++) {
ef04f00d 834 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 835 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
836 break;
837 msleep(1);
838 }
839
840 if (try == 3) {
841 WARN(1, "dp_aux_ch not started status 0x%08x\n",
842 I915_READ(ch_ctl));
9ee32fea
DV		 843 ret = -EBUSY;
844 goto out;
4f7f7b7e
CW		 845 }
846
46a5ae9f
PZ		 847 /* Only 5 data registers! */
848 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
849 ret = -E2BIG;
850 goto out;
851 }
852
ec5b01dd 853 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 854 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
855 has_aux_irq,
856 send_bytes,
857 aux_clock_divider);
5ed12a19 858
bc86625a
CW		 859 /* Must try at least 3 times according to DP spec */
860 for (try = 0; try < 5; try++) {
861 /* Load the send data into the aux channel data registers */
862 for (i = 0; i < send_bytes; i += 4)
863 I915_WRITE(ch_data + i,
a4f1289e
RV		 864 intel_dp_pack_aux(send + i,
865 send_bytes - i));
bc86625a
CW		 866
867 /* Send the command and wait for it to complete */
5ed12a19 868 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 869
870 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
871
872 /* Clear done status and any errors */
873 I915_WRITE(ch_ctl,
874 status |
875 DP_AUX_CH_CTL_DONE |
876 DP_AUX_CH_CTL_TIME_OUT_ERROR |
877 DP_AUX_CH_CTL_RECEIVE_ERROR);
878
879 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
880 DP_AUX_CH_CTL_RECEIVE_ERROR))
881 continue;
882 if (status & DP_AUX_CH_CTL_DONE)
883 break;
884 }
4f7f7b7e 885 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 886 break;
887 }
888
a4fc5ed6 889 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 890 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 891 ret = -EBUSY;
892 goto out;
a4fc5ed6
KP		 893 }
894
895 /* Check for timeout or receive error.
896 * Timeouts occur when the sink is not connected
897 */
a5b3da54 898 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 899 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 900 ret = -EIO;
901 goto out;
a5b3da54 902 }
1ae8c0a5
KP		 903
904 /* Timeouts occur when the device isn't connected, so they're
905 * "normal" -- don't fill the kernel log with these */
a5b3da54 906 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 907 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 908 ret = -ETIMEDOUT;
909 goto out;
a4fc5ed6
KP		 910 }
911
912 /* Unload any bytes sent back from the other side */
913 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
914 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 915 if (recv_bytes > recv_size)
916 recv_bytes = recv_size;
0206e353 917
4f7f7b7e 918 for (i = 0; i < recv_bytes; i += 4)
a4f1289e
RV		 919 intel_dp_unpack_aux(I915_READ(ch_data + i),
920 recv + i, recv_bytes - i);
a4fc5ed6 921
9ee32fea
DV		 922 ret = recv_bytes;
923out:
924 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 925 intel_aux_display_runtime_put(dev_priv);
9ee32fea 926
884f19e9
JN		 927 if (vdd)
928 edp_panel_vdd_off(intel_dp, false);
929
773538e8 930 pps_unlock(intel_dp);
e39b999a 931
9ee32fea 932 return ret;
a4fc5ed6
KP		 933}
934
a6c8aff0
JN		 935#define BARE_ADDRESS_SIZE 3
936#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 937static ssize_t
938intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 939{
9d1a1031
JN		 940 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
941 uint8_t txbuf[20], rxbuf[20];
942 size_t txsize, rxsize;
a4fc5ed6 943 int ret;
a4fc5ed6 944
9d1a1031
JN		 945 txbuf[0] = msg->request << 4;
946 txbuf[1] = msg->address >> 8;
947 txbuf[2] = msg->address & 0xff;
948 txbuf[3] = msg->size - 1;
46a5ae9f 949
9d1a1031
JN		 950 switch (msg->request & ~DP_AUX_I2C_MOT) {
951 case DP_AUX_NATIVE_WRITE:
952 case DP_AUX_I2C_WRITE:
a6c8aff0 953 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 954 rxsize = 1;
f51a44b9 955
9d1a1031
JN		 956 if (WARN_ON(txsize > 20))
957 return -E2BIG;
a4fc5ed6 958
9d1a1031 959 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 960
9d1a1031
JN		 961 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
962 if (ret > 0) {
963 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 964
9d1a1031
JN		 965 /* Return payload size. */
966 ret = msg->size;
967 }
968 break;
46a5ae9f 969
9d1a1031
JN		 970 case DP_AUX_NATIVE_READ:
971 case DP_AUX_I2C_READ:
a6c8aff0 972 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 973 rxsize = msg->size + 1;
a4fc5ed6 974
9d1a1031
JN		 975 if (WARN_ON(rxsize > 20))
976 return -E2BIG;
a4fc5ed6 977
9d1a1031
JN		 978 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
979 if (ret > 0) {
980 msg->reply = rxbuf[0] >> 4;
981 /*
982 * Assume happy day, and copy the data. The caller is
983 * expected to check msg->reply before touching it.
984 *
985 * Return payload size.
986 */
987 ret--;
988 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 989 }
9d1a1031
JN		 990 break;
991
992 default:
993 ret = -EINVAL;
994 break;
a4fc5ed6 995 }
f51a44b9 996
9d1a1031 997 return ret;
a4fc5ed6
KP		 998}
999
9d1a1031
JN		 1000static void
1001intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1002{
1003 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 1004 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1005 enum port port = intel_dig_port->port;
0b99836f 1006 const char *name = NULL;
ab2c0672
DA		 1007 int ret;
1008
33ad6626
JN		 1009 switch (port) {
1010 case PORT_A:
1011 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 1012 name = "DPDDC-A";
ab2c0672 1013 break;
33ad6626
JN		 1014 case PORT_B:
1015 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 1016 name = "DPDDC-B";
ab2c0672 1017 break;
33ad6626
JN		 1018 case PORT_C:
1019 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 1020 name = "DPDDC-C";
ab2c0672 1021 break;
33ad6626
JN		 1022 case PORT_D:
1023 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1024 name = "DPDDC-D";
33ad6626
JN		 1025 break;
1026 default:
1027 BUG();
ab2c0672
DA		 1028 }
1029
1b1aad75
DL		 1030 /*
1031 * The AUX_CTL register is usually DP_CTL + 0x10.
1032 *
1033 * On Haswell and Broadwell though:
1034 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1035 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1036 *
1037 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1038 */
1039 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 1040 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1041
0b99836f 1042 intel_dp->aux.name = name;
9d1a1031
JN		 1043 intel_dp->aux.dev = dev->dev;
1044 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1045
0b99836f
JN		 1046 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1047 connector->base.kdev->kobj.name);
8316f337 1048
4f71d0cb 1049 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1050 if (ret < 0) {
4f71d0cb 1051 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1052 name, ret);
1053 return;
ab2c0672 1054 }
8a5e6aeb 1055
0b99836f
JN		 1056 ret = sysfs_create_link(&connector->base.kdev->kobj,
1057 &intel_dp->aux.ddc.dev.kobj,
1058 intel_dp->aux.ddc.dev.kobj.name);
1059 if (ret < 0) {
1060 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1061 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1062 }
a4fc5ed6
KP		 1063}
1064
80f65de3
ID		 1065static void
1066intel_dp_connector_unregister(struct intel_connector *intel_connector)
1067{
1068 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1069
0e32b39c
DA		 1070 if (!intel_connector->mst_port)
1071 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1072 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1073 intel_connector_unregister(intel_connector);
1074}
1075
0e50338c
DV		 1076static void
1077hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
1078{
1079 switch (link_bw) {
1080 case DP_LINK_BW_1_62:
1081 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1082 break;
1083 case DP_LINK_BW_2_7:
1084 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1085 break;
1086 case DP_LINK_BW_5_4:
1087 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1088 break;
1089 }
1090}
1091
c6bb3538
DV		 1092static void
1093intel_dp_set_clock(struct intel_encoder *encoder,
1094 struct intel_crtc_config *pipe_config, int link_bw)
1095{
1096 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1097 const struct dp_link_dpll *divisor = NULL;
1098 int i, count = 0;
c6bb3538
DV		 1099
1100 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1101 divisor = gen4_dpll;
1102 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1103 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1104 divisor = pch_dpll;
1105 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1106 } else if (IS_CHERRYVIEW(dev)) {
1107 divisor = chv_dpll;
1108 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1109 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1110 divisor = vlv_dpll;
1111 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1112 }
9dd4ffdf
CML		 1113
1114 if (divisor && count) {
1115 for (i = 0; i < count; i++) {
1116 if (link_bw == divisor[i].link_bw) {
1117 pipe_config->dpll = divisor[i].dpll;
1118 pipe_config->clock_set = true;
1119 break;
1120 }
1121 }
c6bb3538
DV		 1122 }
1123}
1124
00c09d70 1125bool
5bfe2ac0
DV		 1126intel_dp_compute_config(struct intel_encoder *encoder,
1127 struct intel_crtc_config *pipe_config)
a4fc5ed6 1128{
5bfe2ac0 1129 struct drm_device *dev = encoder->base.dev;
36008365 1130 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1131 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1132 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1133 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1134 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1135 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1136 int lane_count, clock;
56071a20 1137 int min_lane_count = 1;
eeb6324d 1138 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1139 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1140 int min_clock = 0;
06ea66b6 1141 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1142 int bpp, mode_rate;
06ea66b6 1143 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1144 int link_avail, link_clock;
a4fc5ed6 1145
bc7d38a4 1146 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1147 pipe_config->has_pch_encoder = true;
1148
03afc4a2 1149 pipe_config->has_dp_encoder = true;
f769cd24 1150 pipe_config->has_drrs = false;
9ed109a7 1151 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1152
dd06f90e
JN		 1153 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1154 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1155 adjusted_mode);
2dd24552
JB		 1156 if (!HAS_PCH_SPLIT(dev))
1157 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1158 intel_connector->panel.fitting_mode);
1159 else
b074cec8
JB		 1160 intel_pch_panel_fitting(intel_crtc, pipe_config,
1161 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1162 }
1163
cb1793ce 1164 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1165 return false;
1166
083f9560
DV		 1167 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1168 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1169 max_lane_count, bws[max_clock],
1170 adjusted_mode->crtc_clock);
083f9560 1171
36008365
DV		 1172 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1173 * bpc in between. */
3e7ca985 1174 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1175 if (is_edp(intel_dp)) {
1176 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1177 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1178 dev_priv->vbt.edp_bpp);
1179 bpp = dev_priv->vbt.edp_bpp;
1180 }
1181
344c5bbc
JN		 1182 /*
1183 * Use the maximum clock and number of lanes the eDP panel
1184 * advertizes being capable of. The panels are generally
1185 * designed to support only a single clock and lane
1186 * configuration, and typically these values correspond to the
1187 * native resolution of the panel.
1188 */
1189 min_lane_count = max_lane_count;
1190 min_clock = max_clock;
7984211e 1191 }
657445fe 1192
36008365 1193 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1194 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1195 bpp);
36008365 1196
c6930992
DA		 1197 for (clock = min_clock; clock <= max_clock; clock++) {
1198 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1199 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1200 link_avail = intel_dp_max_data_rate(link_clock,
1201 lane_count);
1202
1203 if (mode_rate <= link_avail) {
1204 goto found;
1205 }
1206 }
1207 }
1208 }
c4867936 1209
36008365 1210 return false;
3685a8f3 1211
36008365 1212found:
55bc60db
VS		 1213 if (intel_dp->color_range_auto) {
1214 /*
1215 * See:
1216 * CEA-861-E - 5.1 Default Encoding Parameters
1217 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1218 */
18316c8c 1219 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1220 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1221 else
1222 intel_dp->color_range = 0;
1223 }
1224
3685a8f3 1225 if (intel_dp->color_range)
50f3b016 1226 pipe_config->limited_color_range = true;
a4fc5ed6 1227
36008365
DV		 1228 intel_dp->link_bw = bws[clock];
1229 intel_dp->lane_count = lane_count;
657445fe 1230 pipe_config->pipe_bpp = bpp;
ff9a6750 1231 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1232
36008365
DV		 1233 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1234 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1235 pipe_config->port_clock, bpp);
36008365
DV		 1236 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1237 mode_rate, link_avail);
a4fc5ed6 1238
03afc4a2 1239 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1240 adjusted_mode->crtc_clock,
1241 pipe_config->port_clock,
03afc4a2 1242 &pipe_config->dp_m_n);
9d1a455b 1243
439d7ac0
PB		 1244 if (intel_connector->panel.downclock_mode != NULL &&
1245 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1246 pipe_config->has_drrs = true;
439d7ac0
PB		 1247 intel_link_compute_m_n(bpp, lane_count,
1248 intel_connector->panel.downclock_mode->clock,
1249 pipe_config->port_clock,
1250 &pipe_config->dp_m2_n2);
1251 }
1252
ea155f32 1253 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1254 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1255 else
1256 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1257
03afc4a2 1258 return true;
a4fc5ed6
KP		 1259}
1260
7c62a164 1261static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1262{
7c62a164
DV		 1263 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1264 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1265 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1266 struct drm_i915_private *dev_priv = dev->dev_private;
1267 u32 dpa_ctl;
1268
ff9a6750 1269 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1270 dpa_ctl = I915_READ(DP_A);
1271 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1272
ff9a6750 1273 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1274 /* For a long time we've carried around a ILK-DevA w/a for the
1275 * 160MHz clock. If we're really unlucky, it's still required.
1276 */
1277 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1278 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1279 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1280 } else {
1281 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1282 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1283 }
1ce17038 1284
ea9b6006
DV		 1285 I915_WRITE(DP_A, dpa_ctl);
1286
1287 POSTING_READ(DP_A);
1288 udelay(500);
1289}
1290
8ac33ed3 1291static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1292{
b934223d 1293 struct drm_device *dev = encoder->base.dev;
417e822d 1294 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1295 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1296 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1297 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1298 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1299
417e822d 1300 /*
1a2eb460 1301 * There are four kinds of DP registers:
417e822d
KP		 1302 *
1303 * IBX PCH
1a2eb460
KP		 1304 * SNB CPU
1305 * IVB CPU
417e822d
KP		 1306 * CPT PCH
1307 *
1308 * IBX PCH and CPU are the same for almost everything,
1309 * except that the CPU DP PLL is configured in this
1310 * register
1311 *
1312 * CPT PCH is quite different, having many bits moved
1313 * to the TRANS_DP_CTL register instead. That
1314 * configuration happens (oddly) in ironlake_pch_enable
1315 */
9c9e7927 1316
417e822d
KP		 1317 /* Preserve the BIOS-computed detected bit. This is
1318 * supposed to be read-only.
1319 */
1320 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1321
417e822d 1322 /* Handle DP bits in common between all three register formats */
417e822d 1323 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1324 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1325
c1dec79a 1326 if (crtc->config.has_audio)
ea5b213a 1327 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
247d89f6 1328
417e822d 1329 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1330
bc7d38a4 1331 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1332 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1333 intel_dp->DP |= DP_SYNC_HS_HIGH;
1334 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1335 intel_dp->DP |= DP_SYNC_VS_HIGH;
1336 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1337
6aba5b6c 1338 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1339 intel_dp->DP |= DP_ENHANCED_FRAMING;
1340
7c62a164 1341 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1342 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1343 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1344 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1345
1346 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1347 intel_dp->DP |= DP_SYNC_HS_HIGH;
1348 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1349 intel_dp->DP |= DP_SYNC_VS_HIGH;
1350 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1351
6aba5b6c 1352 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1353 intel_dp->DP |= DP_ENHANCED_FRAMING;
1354
44f37d1f
CML		 1355 if (!IS_CHERRYVIEW(dev)) {
1356 if (crtc->pipe == 1)
1357 intel_dp->DP |= DP_PIPEB_SELECT;
1358 } else {
1359 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1360 }
417e822d
KP		 1361 } else {
1362 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1363 }
a4fc5ed6
KP		 1364}
1365
ffd6749d
PZ		 1366#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1367#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1368
1a5ef5b7
PZ		 1369#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1370#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1371
ffd6749d
PZ		 1372#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1373#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1374
4be73780 1375static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1376 u32 mask,
1377 u32 value)
bd943159 1378{
30add22d 1379 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1380 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1381 u32 pp_stat_reg, pp_ctrl_reg;
1382
e39b999a
VS		 1383 lockdep_assert_held(&dev_priv->pps_mutex);
1384
bf13e81b
JN		 1385 pp_stat_reg = _pp_stat_reg(intel_dp);
1386 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1387
99ea7127 1388 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1389 mask, value,
1390 I915_READ(pp_stat_reg),
1391 I915_READ(pp_ctrl_reg));
32ce697c 1392
453c5420 1393 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1394 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1395 I915_READ(pp_stat_reg),
1396 I915_READ(pp_ctrl_reg));
32ce697c 1397 }
54c136d4
CW		 1398
1399 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1400}
32ce697c 1401
4be73780 1402static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1403{
1404 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1405 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1406}
1407
4be73780 1408static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1409{
1410 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1411 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1412}
1413
4be73780 1414static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1415{
1416 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1417
1418 /* When we disable the VDD override bit last we have to do the manual
1419 * wait. */
1420 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1421 intel_dp->panel_power_cycle_delay);
1422
4be73780 1423 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1424}
1425
4be73780 1426static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1427{
1428 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1429 intel_dp->backlight_on_delay);
1430}
1431
4be73780 1432static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1433{
1434 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1435 intel_dp->backlight_off_delay);
1436}
99ea7127 1437
832dd3c1
KP		 1438/* Read the current pp_control value, unlocking the register if it
1439 * is locked
1440 */
1441
453c5420 1442static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1443{
453c5420
JB		 1444 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1445 struct drm_i915_private *dev_priv = dev->dev_private;
1446 u32 control;
832dd3c1 1447
e39b999a
VS		 1448 lockdep_assert_held(&dev_priv->pps_mutex);
1449
bf13e81b 1450 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1451 control &= ~PANEL_UNLOCK_MASK;
1452 control |= PANEL_UNLOCK_REGS;
1453 return control;
bd943159
KP		 1454}
1455
951468f3
VS		 1456/*
1457 * Must be paired with edp_panel_vdd_off().
1458 * Must hold pps_mutex around the whole on/off sequence.
1459 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1460 */
1e0560e0 1461static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1462{
30add22d 1463 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1464 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1465 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1466 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1467 enum intel_display_power_domain power_domain;
5d613501 1468 u32 pp;
453c5420 1469 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1470 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1471
e39b999a
VS		 1472 lockdep_assert_held(&dev_priv->pps_mutex);
1473
97af61f5 1474 if (!is_edp(intel_dp))
adddaaf4 1475 return false;
bd943159
KP		 1476
1477 intel_dp->want_panel_vdd = true;
99ea7127 1478
4be73780 1479 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1480 return need_to_disable;
b0665d57 1481
4e6e1a54
ID		 1482 power_domain = intel_display_port_power_domain(intel_encoder);
1483 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1484
3936fcf4
VS		 1485 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1486 port_name(intel_dig_port->port));
bd943159 1487
4be73780
DV		 1488 if (!edp_have_panel_power(intel_dp))
1489 wait_panel_power_cycle(intel_dp);
99ea7127 1490
453c5420 1491 pp = ironlake_get_pp_control(intel_dp);
5d613501 1492 pp |= EDP_FORCE_VDD;
ebf33b18 1493
bf13e81b
JN		 1494 pp_stat_reg = _pp_stat_reg(intel_dp);
1495 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1496
1497 I915_WRITE(pp_ctrl_reg, pp);
1498 POSTING_READ(pp_ctrl_reg);
1499 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1500 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1501 /*
1502 * If the panel wasn't on, delay before accessing aux channel
1503 */
4be73780 1504 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1505 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1506 port_name(intel_dig_port->port));
f01eca2e 1507 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1508 }
adddaaf4
JN		 1509
1510 return need_to_disable;
1511}
1512
951468f3
VS		 1513/*
1514 * Must be paired with intel_edp_panel_vdd_off() or
1515 * intel_edp_panel_off().
1516 * Nested calls to these functions are not allowed since
1517 * we drop the lock. Caller must use some higher level
1518 * locking to prevent nested calls from other threads.
1519 */
b80d6c78 1520void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1521{
c695b6b6 1522 bool vdd;
adddaaf4 1523
c695b6b6
VS		 1524 if (!is_edp(intel_dp))
1525 return;
1526
773538e8 1527 pps_lock(intel_dp);
c695b6b6 1528 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1529 pps_unlock(intel_dp);
c695b6b6 1530
3936fcf4
VS		 1531 WARN(!vdd, "eDP port %c VDD already requested on\n",
1532 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1533}
1534
4be73780 1535static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1536{
30add22d 1537 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1538 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1539 struct intel_digital_port *intel_dig_port =
1540 dp_to_dig_port(intel_dp);
1541 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1542 enum intel_display_power_domain power_domain;
5d613501 1543 u32 pp;
453c5420 1544 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1545
e39b999a 1546 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1547
15e899a0 1548 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1549
15e899a0 1550 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1551 return;
b0665d57 1552
3936fcf4
VS		 1553 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1554 port_name(intel_dig_port->port));
bd943159 1555
be2c9196
VS		 1556 pp = ironlake_get_pp_control(intel_dp);
1557 pp &= ~EDP_FORCE_VDD;
453c5420 1558
be2c9196
VS		 1559 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1560 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1561
be2c9196
VS		 1562 I915_WRITE(pp_ctrl_reg, pp);
1563 POSTING_READ(pp_ctrl_reg);
90791a5c 1564
be2c9196
VS		 1565 /* Make sure sequencer is idle before allowing subsequent activity */
1566 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1567 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1568
be2c9196
VS		 1569 if ((pp & POWER_TARGET_ON) == 0)
1570 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1571
be2c9196
VS		 1572 power_domain = intel_display_port_power_domain(intel_encoder);
1573 intel_display_power_put(dev_priv, power_domain);
bd943159 1574}
5d613501 1575
4be73780 1576static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1577{
1578 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1579 struct intel_dp, panel_vdd_work);
bd943159 1580
773538e8 1581 pps_lock(intel_dp);
15e899a0
VS		 1582 if (!intel_dp->want_panel_vdd)
1583 edp_panel_vdd_off_sync(intel_dp);
773538e8 1584 pps_unlock(intel_dp);
bd943159
KP		 1585}
1586
aba86890
ID		 1587static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1588{
1589 unsigned long delay;
1590
1591 /*
1592 * Queue the timer to fire a long time from now (relative to the power
1593 * down delay) to keep the panel power up across a sequence of
1594 * operations.
1595 */
1596 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1597 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1598}
1599
951468f3
VS		 1600/*
1601 * Must be paired with edp_panel_vdd_on().
1602 * Must hold pps_mutex around the whole on/off sequence.
1603 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1604 */
4be73780 1605static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1606{
e39b999a
VS		 1607 struct drm_i915_private *dev_priv =
1608 intel_dp_to_dev(intel_dp)->dev_private;
1609
1610 lockdep_assert_held(&dev_priv->pps_mutex);
1611
97af61f5
KP		 1612 if (!is_edp(intel_dp))
1613 return;
5d613501 1614
3936fcf4
VS		 1615 WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1616 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1617
bd943159
KP		 1618 intel_dp->want_panel_vdd = false;
1619
aba86890 1620 if (sync)
4be73780 1621 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1622 else
1623 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1624}
1625
9f0fb5be 1626static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1627{
30add22d 1628 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1629 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1630 u32 pp;
453c5420 1631 u32 pp_ctrl_reg;
9934c132 1632
9f0fb5be
VS		 1633 lockdep_assert_held(&dev_priv->pps_mutex);
1634
97af61f5 1635 if (!is_edp(intel_dp))
bd943159 1636 return;
99ea7127 1637
3936fcf4
VS		 1638 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1639 port_name(dp_to_dig_port(intel_dp)->port));
99ea7127 1640
e7a89ace
VS		 1641 if (WARN(edp_have_panel_power(intel_dp),
1642 "eDP port %c panel power already on\n",
1643 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1644 return;
9934c132 1645
4be73780 1646 wait_panel_power_cycle(intel_dp);
37c6c9b0 1647
bf13e81b 1648 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1649 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1650 if (IS_GEN5(dev)) {
1651 /* ILK workaround: disable reset around power sequence */
1652 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1653 I915_WRITE(pp_ctrl_reg, pp);
1654 POSTING_READ(pp_ctrl_reg);
05ce1a49 1655 }
37c6c9b0 1656
1c0ae80a 1657 pp |= POWER_TARGET_ON;
99ea7127
KP		 1658 if (!IS_GEN5(dev))
1659 pp |= PANEL_POWER_RESET;
1660
453c5420
JB		 1661 I915_WRITE(pp_ctrl_reg, pp);
1662 POSTING_READ(pp_ctrl_reg);
9934c132 1663
4be73780 1664 wait_panel_on(intel_dp);
dce56b3c 1665 intel_dp->last_power_on = jiffies;
9934c132 1666
05ce1a49
KP		 1667 if (IS_GEN5(dev)) {
1668 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1669 I915_WRITE(pp_ctrl_reg, pp);
1670 POSTING_READ(pp_ctrl_reg);
05ce1a49 1671 }
9f0fb5be 1672}
e39b999a 1673
9f0fb5be
VS		 1674void intel_edp_panel_on(struct intel_dp *intel_dp)
1675{
1676 if (!is_edp(intel_dp))
1677 return;
1678
1679 pps_lock(intel_dp);
1680 edp_panel_on(intel_dp);
773538e8 1681 pps_unlock(intel_dp);
9934c132
JB		 1682}
1683
9f0fb5be
VS		 1684
1685static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1686{
4e6e1a54
ID		 1687 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1688 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1689 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1690 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1691 enum intel_display_power_domain power_domain;
99ea7127 1692 u32 pp;
453c5420 1693 u32 pp_ctrl_reg;
9934c132 1694
9f0fb5be
VS		 1695 lockdep_assert_held(&dev_priv->pps_mutex);
1696
97af61f5
KP		 1697 if (!is_edp(intel_dp))
1698 return;
37c6c9b0 1699
3936fcf4
VS		 1700 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1701 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 1702
3936fcf4
VS		 1703 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1704 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 1705
453c5420 1706 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1707 /* We need to switch off panel power _and_ force vdd, for otherwise some
1708 * panels get very unhappy and cease to work. */
b3064154
PJ		 1709 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1710 EDP_BLC_ENABLE);
453c5420 1711
bf13e81b 1712 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1713
849e39f5
PZ		 1714 intel_dp->want_panel_vdd = false;
1715
453c5420
JB		 1716 I915_WRITE(pp_ctrl_reg, pp);
1717 POSTING_READ(pp_ctrl_reg);
9934c132 1718
dce56b3c 1719 intel_dp->last_power_cycle = jiffies;
4be73780 1720 wait_panel_off(intel_dp);
849e39f5
PZ		 1721
1722 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1723 power_domain = intel_display_port_power_domain(intel_encoder);
1724 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1725}
e39b999a 1726
9f0fb5be
VS		 1727void intel_edp_panel_off(struct intel_dp *intel_dp)
1728{
1729 if (!is_edp(intel_dp))
1730 return;
1731
1732 pps_lock(intel_dp);
1733 edp_panel_off(intel_dp);
773538e8 1734 pps_unlock(intel_dp);
9934c132
JB		 1735}
1736
1250d107
JN		 1737/* Enable backlight in the panel power control. */
1738static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1739{
da63a9f2
PZ		 1740 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1741 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1742 struct drm_i915_private *dev_priv = dev->dev_private;
1743 u32 pp;
453c5420 1744 u32 pp_ctrl_reg;
32f9d658 1745
01cb9ea6
JB		 1746 /*
1747 * If we enable the backlight right away following a panel power
1748 * on, we may see slight flicker as the panel syncs with the eDP
1749 * link. So delay a bit to make sure the image is solid before
1750 * allowing it to appear.
1751 */
4be73780 1752 wait_backlight_on(intel_dp);
e39b999a 1753
773538e8 1754 pps_lock(intel_dp);
e39b999a 1755
453c5420 1756 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1757 pp |= EDP_BLC_ENABLE;
453c5420 1758
bf13e81b 1759 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1760
1761 I915_WRITE(pp_ctrl_reg, pp);
1762 POSTING_READ(pp_ctrl_reg);
e39b999a 1763
773538e8 1764 pps_unlock(intel_dp);
32f9d658
ZW		 1765}
1766
1250d107
JN		 1767/* Enable backlight PWM and backlight PP control. */
1768void intel_edp_backlight_on(struct intel_dp *intel_dp)
1769{
1770 if (!is_edp(intel_dp))
1771 return;
1772
1773 DRM_DEBUG_KMS("\n");
1774
1775 intel_panel_enable_backlight(intel_dp->attached_connector);
1776 _intel_edp_backlight_on(intel_dp);
1777}
1778
1779/* Disable backlight in the panel power control. */
1780static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1781{
30add22d 1782 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1783 struct drm_i915_private *dev_priv = dev->dev_private;
1784 u32 pp;
453c5420 1785 u32 pp_ctrl_reg;
32f9d658 1786
f01eca2e
KP		 1787 if (!is_edp(intel_dp))
1788 return;
1789
773538e8 1790 pps_lock(intel_dp);
e39b999a 1791
453c5420 1792 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1793 pp &= ~EDP_BLC_ENABLE;
453c5420 1794
bf13e81b 1795 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1796
1797 I915_WRITE(pp_ctrl_reg, pp);
1798 POSTING_READ(pp_ctrl_reg);
f7d2323c 1799
773538e8 1800 pps_unlock(intel_dp);
e39b999a
VS		 1801
1802 intel_dp->last_backlight_off = jiffies;
f7d2323c 1803 edp_wait_backlight_off(intel_dp);
1250d107 1804}
f7d2323c 1805
1250d107
JN		 1806/* Disable backlight PP control and backlight PWM. */
1807void intel_edp_backlight_off(struct intel_dp *intel_dp)
1808{
1809 if (!is_edp(intel_dp))
1810 return;
1811
1812 DRM_DEBUG_KMS("\n");
f7d2323c 1813
1250d107 1814 _intel_edp_backlight_off(intel_dp);
f7d2323c 1815 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1816}
a4fc5ed6 1817
73580fb7
JN		 1818/*
1819 * Hook for controlling the panel power control backlight through the bl_power
1820 * sysfs attribute. Take care to handle multiple calls.
1821 */
1822static void intel_edp_backlight_power(struct intel_connector *connector,
1823 bool enable)
1824{
1825 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1826 bool is_enabled;
1827
773538e8 1828 pps_lock(intel_dp);
e39b999a 1829 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1830 pps_unlock(intel_dp);
73580fb7
JN		 1831
1832 if (is_enabled == enable)
1833 return;
1834
23ba9373
JN		 1835 DRM_DEBUG_KMS("panel power control backlight %s\n",
1836 enable ? "enable" : "disable");
73580fb7
JN		 1837
1838 if (enable)
1839 _intel_edp_backlight_on(intel_dp);
1840 else
1841 _intel_edp_backlight_off(intel_dp);
1842}
1843
2bd2ad64 1844static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1845{
da63a9f2
PZ		 1846 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1847 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1848 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1849 struct drm_i915_private *dev_priv = dev->dev_private;
1850 u32 dpa_ctl;
1851
2bd2ad64
DV		 1852 assert_pipe_disabled(dev_priv,
1853 to_intel_crtc(crtc)->pipe);
1854
d240f20f
JB		 1855 DRM_DEBUG_KMS("\n");
1856 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1857 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1858 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1859
1860 /* We don't adjust intel_dp->DP while tearing down the link, to
1861 * facilitate link retraining (e.g. after hotplug). Hence clear all
1862 * enable bits here to ensure that we don't enable too much. */
1863 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1864 intel_dp->DP |= DP_PLL_ENABLE;
1865 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1866 POSTING_READ(DP_A);
1867 udelay(200);
d240f20f
JB		 1868}
1869
2bd2ad64 1870static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1871{
da63a9f2
PZ		 1872 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1873 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1874 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1875 struct drm_i915_private *dev_priv = dev->dev_private;
1876 u32 dpa_ctl;
1877
2bd2ad64
DV		 1878 assert_pipe_disabled(dev_priv,
1879 to_intel_crtc(crtc)->pipe);
1880
d240f20f 1881 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1882 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1883 "dp pll off, should be on\n");
1884 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1885
1886 /* We can't rely on the value tracked for the DP register in
1887 * intel_dp->DP because link_down must not change that (otherwise link
1888 * re-training will fail. */
298b0b39 1889 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1890 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1891 POSTING_READ(DP_A);
d240f20f
JB		 1892 udelay(200);
1893}
1894
c7ad3810 1895/* If the sink supports it, try to set the power state appropriately */
c19b0669 1896void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1897{
1898 int ret, i;
1899
1900 /* Should have a valid DPCD by this point */
1901 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1902 return;
1903
1904 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1905 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1906 DP_SET_POWER_D3);
c7ad3810
JB		 1907 } else {
1908 /*
1909 * When turning on, we need to retry for 1ms to give the sink
1910 * time to wake up.
1911 */
1912 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1913 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1914 DP_SET_POWER_D0);
c7ad3810
JB		 1915 if (ret == 1)
1916 break;
1917 msleep(1);
1918 }
1919 }
f9cac721
JN		 1920
1921 if (ret != 1)
1922 DRM_DEBUG_KMS("failed to %s sink power state\n",
1923 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1924}
1925
19d8fe15
DV		 1926static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1927 enum pipe *pipe)
d240f20f 1928{
19d8fe15 1929 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1930 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1931 struct drm_device *dev = encoder->base.dev;
1932 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1933 enum intel_display_power_domain power_domain;
1934 u32 tmp;
1935
1936 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1937 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1938 return false;
1939
1940 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1941
1942 if (!(tmp & DP_PORT_EN))
1943 return false;
1944
bc7d38a4 1945 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1946 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1947 } else if (IS_CHERRYVIEW(dev)) {
1948 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1949 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1950 *pipe = PORT_TO_PIPE(tmp);
1951 } else {
1952 u32 trans_sel;
1953 u32 trans_dp;
1954 int i;
1955
1956 switch (intel_dp->output_reg) {
1957 case PCH_DP_B:
1958 trans_sel = TRANS_DP_PORT_SEL_B;
1959 break;
1960 case PCH_DP_C:
1961 trans_sel = TRANS_DP_PORT_SEL_C;
1962 break;
1963 case PCH_DP_D:
1964 trans_sel = TRANS_DP_PORT_SEL_D;
1965 break;
1966 default:
1967 return true;
1968 }
1969
055e393f 1970 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1971 trans_dp = I915_READ(TRANS_DP_CTL(i));
1972 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1973 *pipe = i;
1974 return true;
1975 }
1976 }
19d8fe15 1977
4a0833ec
DV		 1978 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1979 intel_dp->output_reg);
1980 }
d240f20f 1981
19d8fe15
DV		 1982 return true;
1983}
d240f20f 1984
045ac3b5
JB		 1985static void intel_dp_get_config(struct intel_encoder *encoder,
1986 struct intel_crtc_config *pipe_config)
1987{
1988 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1989 u32 tmp, flags = 0;
63000ef6
XZ		 1990 struct drm_device *dev = encoder->base.dev;
1991 struct drm_i915_private *dev_priv = dev->dev_private;
1992 enum port port = dp_to_dig_port(intel_dp)->port;
1993 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1994 int dotclock;
045ac3b5 1995
9ed109a7
DV		 1996 tmp = I915_READ(intel_dp->output_reg);
1997 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1998 pipe_config->has_audio = true;
1999
63000ef6 2000 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 2001 if (tmp & DP_SYNC_HS_HIGH)
2002 flags |= DRM_MODE_FLAG_PHSYNC;
2003 else
2004 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2005
63000ef6
XZ		 2006 if (tmp & DP_SYNC_VS_HIGH)
2007 flags |= DRM_MODE_FLAG_PVSYNC;
2008 else
2009 flags |= DRM_MODE_FLAG_NVSYNC;
2010 } else {
2011 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2012 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2013 flags |= DRM_MODE_FLAG_PHSYNC;
2014 else
2015 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2016
63000ef6
XZ		 2017 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2018 flags |= DRM_MODE_FLAG_PVSYNC;
2019 else
2020 flags |= DRM_MODE_FLAG_NVSYNC;
2021 }
045ac3b5
JB		 2022
2023 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 2024
8c875fca
VS		 2025 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2026 tmp & DP_COLOR_RANGE_16_235)
2027 pipe_config->limited_color_range = true;
2028
eb14cb74
VS		 2029 pipe_config->has_dp_encoder = true;
2030
2031 intel_dp_get_m_n(crtc, pipe_config);
2032
18442d08 2033 if (port == PORT_A) {
f1f644dc
JB		 2034 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2035 pipe_config->port_clock = 162000;
2036 else
2037 pipe_config->port_clock = 270000;
2038 }
18442d08
VS		 2039
2040 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2041 &pipe_config->dp_m_n);
2042
2043 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2044 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2045
241bfc38 2046 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2047
c6cd2ee2
JN		 2048 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2049 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2050 /*
2051 * This is a big fat ugly hack.
2052 *
2053 * Some machines in UEFI boot mode provide us a VBT that has 18
2054 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2055 * unknown we fail to light up. Yet the same BIOS boots up with
2056 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2057 * max, not what it tells us to use.
2058 *
2059 * Note: This will still be broken if the eDP panel is not lit
2060 * up by the BIOS, and thus we can't get the mode at module
2061 * load.
2062 */
2063 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2064 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2065 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2066 }
045ac3b5
JB		 2067}
2068
e8cb4558 2069static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2070{
e8cb4558 2071 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2072 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2073 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2074
2075 if (crtc->config.has_audio)
2076 intel_audio_codec_disable(encoder);
6cb49835
DV		 2077
2078 /* Make sure the panel is off before trying to change the mode. But also
2079 * ensure that we have vdd while we switch off the panel. */
24f3e092 2080 intel_edp_panel_vdd_on(intel_dp);
4be73780 2081 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2082 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2083 intel_edp_panel_off(intel_dp);
3739850b 2084
08aff3fe
VS		 2085 /* disable the port before the pipe on g4x */
2086 if (INTEL_INFO(dev)->gen < 5)
3739850b 2087 intel_dp_link_down(intel_dp);
d240f20f
JB		 2088}
2089
08aff3fe 2090static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2091{
2bd2ad64 2092 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2093 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2094
49277c31 2095 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2096 if (port == PORT_A)
2097 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2098}
2099
2100static void vlv_post_disable_dp(struct intel_encoder *encoder)
2101{
2102 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2103
2104 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2105}
2106
580d3811
VS		 2107static void chv_post_disable_dp(struct intel_encoder *encoder)
2108{
2109 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2110 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2111 struct drm_device *dev = encoder->base.dev;
2112 struct drm_i915_private *dev_priv = dev->dev_private;
2113 struct intel_crtc *intel_crtc =
2114 to_intel_crtc(encoder->base.crtc);
2115 enum dpio_channel ch = vlv_dport_to_channel(dport);
2116 enum pipe pipe = intel_crtc->pipe;
2117 u32 val;
2118
2119 intel_dp_link_down(intel_dp);
2120
2121 mutex_lock(&dev_priv->dpio_lock);
2122
2123 /* Propagate soft reset to data lane reset */
97fd4d5c 2124 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2125 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2126 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2127
97fd4d5c
VS		 2128 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2129 val |= CHV_PCS_REQ_SOFTRESET_EN;
2130 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2131
2132 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2133 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2134 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2135
2136 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2137 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2138 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2139
2140 mutex_unlock(&dev_priv->dpio_lock);
2141}
2142
7b13b58a
VS		 2143static void
2144_intel_dp_set_link_train(struct intel_dp *intel_dp,
2145 uint32_t *DP,
2146 uint8_t dp_train_pat)
2147{
2148 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2149 struct drm_device *dev = intel_dig_port->base.base.dev;
2150 struct drm_i915_private *dev_priv = dev->dev_private;
2151 enum port port = intel_dig_port->port;
2152
2153 if (HAS_DDI(dev)) {
2154 uint32_t temp = I915_READ(DP_TP_CTL(port));
2155
2156 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2157 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2158 else
2159 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2160
2161 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2162 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2163 case DP_TRAINING_PATTERN_DISABLE:
2164 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2165
2166 break;
2167 case DP_TRAINING_PATTERN_1:
2168 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2169 break;
2170 case DP_TRAINING_PATTERN_2:
2171 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2172 break;
2173 case DP_TRAINING_PATTERN_3:
2174 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2175 break;
2176 }
2177 I915_WRITE(DP_TP_CTL(port), temp);
2178
2179 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2180 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2181
2182 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2183 case DP_TRAINING_PATTERN_DISABLE:
2184 *DP |= DP_LINK_TRAIN_OFF_CPT;
2185 break;
2186 case DP_TRAINING_PATTERN_1:
2187 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2188 break;
2189 case DP_TRAINING_PATTERN_2:
2190 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2191 break;
2192 case DP_TRAINING_PATTERN_3:
2193 DRM_ERROR("DP training pattern 3 not supported\n");
2194 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2195 break;
2196 }
2197
2198 } else {
2199 if (IS_CHERRYVIEW(dev))
2200 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2201 else
2202 *DP &= ~DP_LINK_TRAIN_MASK;
2203
2204 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2205 case DP_TRAINING_PATTERN_DISABLE:
2206 *DP |= DP_LINK_TRAIN_OFF;
2207 break;
2208 case DP_TRAINING_PATTERN_1:
2209 *DP |= DP_LINK_TRAIN_PAT_1;
2210 break;
2211 case DP_TRAINING_PATTERN_2:
2212 *DP |= DP_LINK_TRAIN_PAT_2;
2213 break;
2214 case DP_TRAINING_PATTERN_3:
2215 if (IS_CHERRYVIEW(dev)) {
2216 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2217 } else {
2218 DRM_ERROR("DP training pattern 3 not supported\n");
2219 *DP |= DP_LINK_TRAIN_PAT_2;
2220 }
2221 break;
2222 }
2223 }
2224}
2225
2226static void intel_dp_enable_port(struct intel_dp *intel_dp)
2227{
2228 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2229 struct drm_i915_private *dev_priv = dev->dev_private;
2230
7b13b58a
VS		 2231 /* enable with pattern 1 (as per spec) */
2232 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2233 DP_TRAINING_PATTERN_1);
2234
2235 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2236 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2237
2238 /*
2239 * Magic for VLV/CHV. We _must_ first set up the register
2240 * without actually enabling the port, and then do another
2241 * write to enable the port. Otherwise link training will
2242 * fail when the power sequencer is freshly used for this port.
2243 */
2244 intel_dp->DP |= DP_PORT_EN;
2245
2246 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2247 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2248}
2249
e8cb4558 2250static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2251{
e8cb4558
DV		 2252 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2253 struct drm_device *dev = encoder->base.dev;
2254 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2255 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2256 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2257
0c33d8d7
DV		 2258 if (WARN_ON(dp_reg & DP_PORT_EN))
2259 return;
5d613501 2260
093e3f13
VS		 2261 pps_lock(intel_dp);
2262
2263 if (IS_VALLEYVIEW(dev))
2264 vlv_init_panel_power_sequencer(intel_dp);
2265
7b13b58a 2266 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2267
2268 edp_panel_vdd_on(intel_dp);
2269 edp_panel_on(intel_dp);
2270 edp_panel_vdd_off(intel_dp, true);
2271
2272 pps_unlock(intel_dp);
2273
61234fa5
VS		 2274 if (IS_VALLEYVIEW(dev))
2275 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2276
f01eca2e 2277 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2278 intel_dp_start_link_train(intel_dp);
33a34e4e 2279 intel_dp_complete_link_train(intel_dp);
3ab9c637 2280 intel_dp_stop_link_train(intel_dp);
c1dec79a
JN		 2281
2282 if (crtc->config.has_audio) {
2283 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2284 pipe_name(crtc->pipe));
2285 intel_audio_codec_enable(encoder);
2286 }
ab1f90f9 2287}
89b667f8 2288
ecff4f3b
JN		 2289static void g4x_enable_dp(struct intel_encoder *encoder)
2290{
828f5c6e
JN		 2291 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2292
ecff4f3b 2293 intel_enable_dp(encoder);
4be73780 2294 intel_edp_backlight_on(intel_dp);
ab1f90f9 2295}
89b667f8 2296
ab1f90f9
JN		 2297static void vlv_enable_dp(struct intel_encoder *encoder)
2298{
828f5c6e
JN		 2299 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2300
4be73780 2301 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2302}
2303
ecff4f3b 2304static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2305{
2306 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2307 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2308
8ac33ed3
DV		 2309 intel_dp_prepare(encoder);
2310
d41f1efb
DV		 2311 /* Only ilk+ has port A */
2312 if (dport->port == PORT_A) {
2313 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2314 ironlake_edp_pll_on(intel_dp);
d41f1efb 2315 }
ab1f90f9
JN		 2316}
2317
83b84597
VS		 2318static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2319{
2320 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2321 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2322 enum pipe pipe = intel_dp->pps_pipe;
2323 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2324
2325 edp_panel_vdd_off_sync(intel_dp);
2326
2327 /*
2328 * VLV seems to get confused when multiple power seqeuencers
2329 * have the same port selected (even if only one has power/vdd
2330 * enabled). The failure manifests as vlv_wait_port_ready() failing
2331 * CHV on the other hand doesn't seem to mind having the same port
2332 * selected in multiple power seqeuencers, but let's clear the
2333 * port select always when logically disconnecting a power sequencer
2334 * from a port.
2335 */
2336 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2337 pipe_name(pipe), port_name(intel_dig_port->port));
2338 I915_WRITE(pp_on_reg, 0);
2339 POSTING_READ(pp_on_reg);
2340
2341 intel_dp->pps_pipe = INVALID_PIPE;
2342}
2343
a4a5d2f8
VS		 2344static void vlv_steal_power_sequencer(struct drm_device *dev,
2345 enum pipe pipe)
2346{
2347 struct drm_i915_private *dev_priv = dev->dev_private;
2348 struct intel_encoder *encoder;
2349
2350 lockdep_assert_held(&dev_priv->pps_mutex);
2351
ac3c12e4
VS		 2352 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2353 return;
2354
a4a5d2f8
VS		 2355 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2356 base.head) {
2357 struct intel_dp *intel_dp;
773538e8 2358 enum port port;
a4a5d2f8
VS		 2359
2360 if (encoder->type != INTEL_OUTPUT_EDP)
2361 continue;
2362
2363 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2364 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2365
2366 if (intel_dp->pps_pipe != pipe)
2367 continue;
2368
2369 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2370 pipe_name(pipe), port_name(port));
a4a5d2f8 2371
034e43c6
VS		 2372 WARN(encoder->connectors_active,
2373 "stealing pipe %c power sequencer from active eDP port %c\n",
2374 pipe_name(pipe), port_name(port));
2375
a4a5d2f8 2376 /* make sure vdd is off before we steal it */
83b84597 2377 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2378 }
2379}
2380
2381static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2382{
2383 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2384 struct intel_encoder *encoder = &intel_dig_port->base;
2385 struct drm_device *dev = encoder->base.dev;
2386 struct drm_i915_private *dev_priv = dev->dev_private;
2387 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2388
2389 lockdep_assert_held(&dev_priv->pps_mutex);
2390
093e3f13
VS		 2391 if (!is_edp(intel_dp))
2392 return;
2393
a4a5d2f8
VS		 2394 if (intel_dp->pps_pipe == crtc->pipe)
2395 return;
2396
2397 /*
2398 * If another power sequencer was being used on this
2399 * port previously make sure to turn off vdd there while
2400 * we still have control of it.
2401 */
2402 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2403 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2404
2405 /*
2406 * We may be stealing the power
2407 * sequencer from another port.
2408 */
2409 vlv_steal_power_sequencer(dev, crtc->pipe);
2410
2411 /* now it's all ours */
2412 intel_dp->pps_pipe = crtc->pipe;
2413
2414 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2415 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2416
2417 /* init power sequencer on this pipe and port */
36b5f425
VS		 2418 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2419 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2420}
2421
ab1f90f9 2422static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2423{
2bd2ad64 2424 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2425 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2426 struct drm_device *dev = encoder->base.dev;
89b667f8 2427 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2428 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2429 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2430 int pipe = intel_crtc->pipe;
2431 u32 val;
a4fc5ed6 2432
ab1f90f9 2433 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2434
ab3c759a 2435 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2436 val = 0;
2437 if (pipe)
2438 val |= (1<<21);
2439 else
2440 val &= ~(1<<21);
2441 val |= 0x001000c4;
ab3c759a
CML		 2442 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2443 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2444 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2445
ab1f90f9
JN		 2446 mutex_unlock(&dev_priv->dpio_lock);
2447
2448 intel_enable_dp(encoder);
89b667f8
JB		 2449}
2450
ecff4f3b 2451static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2452{
2453 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2454 struct drm_device *dev = encoder->base.dev;
2455 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2456 struct intel_crtc *intel_crtc =
2457 to_intel_crtc(encoder->base.crtc);
e4607fcf 2458 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2459 int pipe = intel_crtc->pipe;
89b667f8 2460
8ac33ed3
DV		 2461 intel_dp_prepare(encoder);
2462
89b667f8 2463 /* Program Tx lane resets to default */
0980a60f 2464 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2465 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2466 DPIO_PCS_TX_LANE2_RESET |
2467 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2468 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2469 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2470 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2471 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2472 DPIO_PCS_CLK_SOFT_RESET);
2473
2474 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2475 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2476 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2477 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2478 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2479}
2480
e4a1d846
CML		 2481static void chv_pre_enable_dp(struct intel_encoder *encoder)
2482{
2483 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2484 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2485 struct drm_device *dev = encoder->base.dev;
2486 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2487 struct intel_crtc *intel_crtc =
2488 to_intel_crtc(encoder->base.crtc);
2489 enum dpio_channel ch = vlv_dport_to_channel(dport);
2490 int pipe = intel_crtc->pipe;
2491 int data, i;
949c1d43 2492 u32 val;
e4a1d846 2493
e4a1d846 2494 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2495
570e2a74
VS		 2496 /* allow hardware to manage TX FIFO reset source */
2497 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2498 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2499 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2500
2501 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2502 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2503 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2504
949c1d43 2505 /* Deassert soft data lane reset*/
97fd4d5c 2506 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2507 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2508 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2509
2510 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2511 val |= CHV_PCS_REQ_SOFTRESET_EN;
2512 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2513
2514 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2515 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2516 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2517
97fd4d5c 2518 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2519 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2520 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2521
2522 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2523 for (i = 0; i < 4; i++) {
2524 /* Set the latency optimal bit */
2525 data = (i == 1) ? 0x0 : 0x6;
2526 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2527 data << DPIO_FRC_LATENCY_SHFIT);
2528
2529 /* Set the upar bit */
2530 data = (i == 1) ? 0x0 : 0x1;
2531 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2532 data << DPIO_UPAR_SHIFT);
2533 }
2534
2535 /* Data lane stagger programming */
2536 /* FIXME: Fix up value only after power analysis */
2537
2538 mutex_unlock(&dev_priv->dpio_lock);
2539
e4a1d846 2540 intel_enable_dp(encoder);
e4a1d846
CML		 2541}
2542
9197c88b
VS		 2543static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2544{
2545 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2546 struct drm_device *dev = encoder->base.dev;
2547 struct drm_i915_private *dev_priv = dev->dev_private;
2548 struct intel_crtc *intel_crtc =
2549 to_intel_crtc(encoder->base.crtc);
2550 enum dpio_channel ch = vlv_dport_to_channel(dport);
2551 enum pipe pipe = intel_crtc->pipe;
2552 u32 val;
2553
625695f8
VS		 2554 intel_dp_prepare(encoder);
2555
9197c88b
VS		 2556 mutex_lock(&dev_priv->dpio_lock);
2557
b9e5ac3c
VS		 2558 /* program left/right clock distribution */
2559 if (pipe != PIPE_B) {
2560 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2561 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2562 if (ch == DPIO_CH0)
2563 val |= CHV_BUFLEFTENA1_FORCE;
2564 if (ch == DPIO_CH1)
2565 val |= CHV_BUFRIGHTENA1_FORCE;
2566 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2567 } else {
2568 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2569 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2570 if (ch == DPIO_CH0)
2571 val |= CHV_BUFLEFTENA2_FORCE;
2572 if (ch == DPIO_CH1)
2573 val |= CHV_BUFRIGHTENA2_FORCE;
2574 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2575 }
2576
9197c88b
VS		 2577 /* program clock channel usage */
2578 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2579 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2580 if (pipe != PIPE_B)
2581 val &= ~CHV_PCS_USEDCLKCHANNEL;
2582 else
2583 val |= CHV_PCS_USEDCLKCHANNEL;
2584 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2585
2586 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2587 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2588 if (pipe != PIPE_B)
2589 val &= ~CHV_PCS_USEDCLKCHANNEL;
2590 else
2591 val |= CHV_PCS_USEDCLKCHANNEL;
2592 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2593
2594 /*
2595 * This a a bit weird since generally CL
2596 * matches the pipe, but here we need to
2597 * pick the CL based on the port.
2598 */
2599 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2600 if (pipe != PIPE_B)
2601 val &= ~CHV_CMN_USEDCLKCHANNEL;
2602 else
2603 val |= CHV_CMN_USEDCLKCHANNEL;
2604 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2605
2606 mutex_unlock(&dev_priv->dpio_lock);
2607}
2608
a4fc5ed6 2609/*
df0c237d
JB		 2610 * Native read with retry for link status and receiver capability reads for
2611 * cases where the sink may still be asleep.
9d1a1031
JN		 2612 *
2613 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2614 * supposed to retry 3 times per the spec.
a4fc5ed6 2615 */
9d1a1031
JN		 2616static ssize_t
2617intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2618 void *buffer, size_t size)
a4fc5ed6 2619{
9d1a1031
JN		 2620 ssize_t ret;
2621 int i;
61da5fab 2622
61da5fab 2623 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2624 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2625 if (ret == size)
2626 return ret;
61da5fab
JB		 2627 msleep(1);
2628 }
a4fc5ed6 2629
9d1a1031 2630 return ret;
a4fc5ed6
KP		 2631}
2632
2633/*
2634 * Fetch AUX CH registers 0x202 - 0x207 which contain
2635 * link status information
2636 */
2637static bool
93f62dad 2638intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2639{
9d1a1031
JN		 2640 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2641 DP_LANE0_1_STATUS,
2642 link_status,
2643 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2644}
2645
1100244e 2646/* These are source-specific values. */
a4fc5ed6 2647static uint8_t
1a2eb460 2648intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2649{
30add22d 2650 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2651 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2652
5a9d1f1a
DL		 2653 if (INTEL_INFO(dev)->gen >= 9)
2654 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2655 else if (IS_VALLEYVIEW(dev))
bd60018a 2656 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2657 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2658 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2659 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2660 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2661 else
bd60018a 2662 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2663}
2664
2665static uint8_t
2666intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2667{
30add22d 2668 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2669 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2670
5a9d1f1a
DL		 2671 if (INTEL_INFO(dev)->gen >= 9) {
2672 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2673 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2674 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2675 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2676 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2677 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2678 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2679 default:
2680 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2681 }
2682 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2683 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2684 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2685 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2686 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2687 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2688 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2689 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2690 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2691 default:
bd60018a 2692 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2693 }
e2fa6fba
P		 2694 } else if (IS_VALLEYVIEW(dev)) {
2695 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2696 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2697 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2698 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2699 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2700 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2701 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2702 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2703 default:
bd60018a 2704 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2705 }
bc7d38a4 2706 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2707 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2708 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2709 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2710 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2711 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2712 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2713 default:
bd60018a 2714 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2715 }
2716 } else {
2717 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2718 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2719 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2720 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2721 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2722 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2723 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2724 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2725 default:
bd60018a 2726 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2727 }
a4fc5ed6
KP		 2728 }
2729}
2730
e2fa6fba
P		 2731static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2732{
2733 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2734 struct drm_i915_private *dev_priv = dev->dev_private;
2735 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2736 struct intel_crtc *intel_crtc =
2737 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2738 unsigned long demph_reg_value, preemph_reg_value,
2739 uniqtranscale_reg_value;
2740 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2741 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2742 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2743
2744 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2745 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2746 preemph_reg_value = 0x0004000;
2747 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2748 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2749 demph_reg_value = 0x2B405555;
2750 uniqtranscale_reg_value = 0x552AB83A;
2751 break;
bd60018a 2752 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2753 demph_reg_value = 0x2B404040;
2754 uniqtranscale_reg_value = 0x5548B83A;
2755 break;
bd60018a 2756 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2757 demph_reg_value = 0x2B245555;
2758 uniqtranscale_reg_value = 0x5560B83A;
2759 break;
bd60018a 2760 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2761 demph_reg_value = 0x2B405555;
2762 uniqtranscale_reg_value = 0x5598DA3A;
2763 break;
2764 default:
2765 return 0;
2766 }
2767 break;
bd60018a 2768 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2769 preemph_reg_value = 0x0002000;
2770 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2771 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2772 demph_reg_value = 0x2B404040;
2773 uniqtranscale_reg_value = 0x5552B83A;
2774 break;
bd60018a 2775 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2776 demph_reg_value = 0x2B404848;
2777 uniqtranscale_reg_value = 0x5580B83A;
2778 break;
bd60018a 2779 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2780 demph_reg_value = 0x2B404040;
2781 uniqtranscale_reg_value = 0x55ADDA3A;
2782 break;
2783 default:
2784 return 0;
2785 }
2786 break;
bd60018a 2787 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 2788 preemph_reg_value = 0x0000000;
2789 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2790 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2791 demph_reg_value = 0x2B305555;
2792 uniqtranscale_reg_value = 0x5570B83A;
2793 break;
bd60018a 2794 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2795 demph_reg_value = 0x2B2B4040;
2796 uniqtranscale_reg_value = 0x55ADDA3A;
2797 break;
2798 default:
2799 return 0;
2800 }
2801 break;
bd60018a 2802 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 2803 preemph_reg_value = 0x0006000;
2804 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2805 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2806 demph_reg_value = 0x1B405555;
2807 uniqtranscale_reg_value = 0x55ADDA3A;
2808 break;
2809 default:
2810 return 0;
2811 }
2812 break;
2813 default:
2814 return 0;
2815 }
2816
0980a60f 2817 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2818 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2819 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2820 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2821 uniqtranscale_reg_value);
ab3c759a
CML		 2822 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2823 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2824 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2825 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2826 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2827
2828 return 0;
2829}
2830
e4a1d846
CML		 2831static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2832{
2833 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2834 struct drm_i915_private *dev_priv = dev->dev_private;
2835 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2836 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2837 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2838 uint8_t train_set = intel_dp->train_set[0];
2839 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2840 enum pipe pipe = intel_crtc->pipe;
2841 int i;
e4a1d846
CML		 2842
2843 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2844 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 2845 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2846 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2847 deemph_reg_value = 128;
2848 margin_reg_value = 52;
2849 break;
bd60018a 2850 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2851 deemph_reg_value = 128;
2852 margin_reg_value = 77;
2853 break;
bd60018a 2854 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2855 deemph_reg_value = 128;
2856 margin_reg_value = 102;
2857 break;
bd60018a 2858 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 2859 deemph_reg_value = 128;
2860 margin_reg_value = 154;
2861 /* FIXME extra to set for 1200 */
2862 break;
2863 default:
2864 return 0;
2865 }
2866 break;
bd60018a 2867 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 2868 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2869 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2870 deemph_reg_value = 85;
2871 margin_reg_value = 78;
2872 break;
bd60018a 2873 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2874 deemph_reg_value = 85;
2875 margin_reg_value = 116;
2876 break;
bd60018a 2877 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2878 deemph_reg_value = 85;
2879 margin_reg_value = 154;
2880 break;
2881 default:
2882 return 0;
2883 }
2884 break;
bd60018a 2885 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 2886 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2887 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2888 deemph_reg_value = 64;
2889 margin_reg_value = 104;
2890 break;
bd60018a 2891 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2892 deemph_reg_value = 64;
2893 margin_reg_value = 154;
2894 break;
2895 default:
2896 return 0;
2897 }
2898 break;
bd60018a 2899 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 2900 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2901 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2902 deemph_reg_value = 43;
2903 margin_reg_value = 154;
2904 break;
2905 default:
2906 return 0;
2907 }
2908 break;
2909 default:
2910 return 0;
2911 }
2912
2913 mutex_lock(&dev_priv->dpio_lock);
2914
2915 /* Clear calc init */
1966e59e
VS		 2916 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2917 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 2918 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2919 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 2920 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2921
2922 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2923 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 2924 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2925 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 2926 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 2927
a02ef3c7
VS		 2928 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
2929 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2930 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2931 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
2932
2933 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
2934 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2935 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2936 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
2937
e4a1d846 2938 /* Program swing deemph */
f72df8db
VS		 2939 for (i = 0; i < 4; i++) {
2940 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2941 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2942 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2943 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2944 }
e4a1d846
CML		 2945
2946 /* Program swing margin */
f72df8db
VS		 2947 for (i = 0; i < 4; i++) {
2948 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 2949 val &= ~DPIO_SWING_MARGIN000_MASK;
2950 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 2951 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2952 }
e4a1d846
CML		 2953
2954 /* Disable unique transition scale */
f72df8db
VS		 2955 for (i = 0; i < 4; i++) {
2956 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2957 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2958 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2959 }
e4a1d846
CML		 2960
2961 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 2962 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 2963 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 2964 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 2965
2966 /*
2967 * The document said it needs to set bit 27 for ch0 and bit 26
2968 * for ch1. Might be a typo in the doc.
2969 * For now, for this unique transition scale selection, set bit
2970 * 27 for ch0 and ch1.
2971 */
f72df8db
VS		 2972 for (i = 0; i < 4; i++) {
2973 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2974 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2975 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2976 }
e4a1d846 2977
f72df8db
VS		 2978 for (i = 0; i < 4; i++) {
2979 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2980 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2981 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2982 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2983 }
e4a1d846
CML		 2984 }
2985
2986 /* Start swing calculation */
1966e59e
VS		 2987 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2988 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2989 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2990
2991 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2992 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2993 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2994
2995 /* LRC Bypass */
2996 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2997 val |= DPIO_LRC_BYPASS;
2998 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2999
3000 mutex_unlock(&dev_priv->dpio_lock);
3001
3002 return 0;
3003}
3004
a4fc5ed6 3005static void
0301b3ac
JN		 3006intel_get_adjust_train(struct intel_dp *intel_dp,
3007 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3008{
3009 uint8_t v = 0;
3010 uint8_t p = 0;
3011 int lane;
1a2eb460
KP		 3012 uint8_t voltage_max;
3013 uint8_t preemph_max;
a4fc5ed6 3014
33a34e4e 3015 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3016 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3017 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3018
3019 if (this_v > v)
3020 v = this_v;
3021 if (this_p > p)
3022 p = this_p;
3023 }
3024
1a2eb460 3025 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3026 if (v >= voltage_max)
3027 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3028
1a2eb460
KP		 3029 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3030 if (p >= preemph_max)
3031 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3032
3033 for (lane = 0; lane < 4; lane++)
33a34e4e 3034 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3035}
3036
3037static uint32_t
f0a3424e 3038intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3039{
3cf2efb1 3040 uint32_t signal_levels = 0;
a4fc5ed6 3041
3cf2efb1 3042 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3043 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3044 default:
3045 signal_levels |= DP_VOLTAGE_0_4;
3046 break;
bd60018a 3047 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3048 signal_levels |= DP_VOLTAGE_0_6;
3049 break;
bd60018a 3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3051 signal_levels |= DP_VOLTAGE_0_8;
3052 break;
bd60018a 3053 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3054 signal_levels |= DP_VOLTAGE_1_2;
3055 break;
3056 }
3cf2efb1 3057 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3058 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3059 default:
3060 signal_levels |= DP_PRE_EMPHASIS_0;
3061 break;
bd60018a 3062 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3063 signal_levels |= DP_PRE_EMPHASIS_3_5;
3064 break;
bd60018a 3065 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3066 signal_levels |= DP_PRE_EMPHASIS_6;
3067 break;
bd60018a 3068 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3069 signal_levels |= DP_PRE_EMPHASIS_9_5;
3070 break;
3071 }
3072 return signal_levels;
3073}
3074
e3421a18
ZW		 3075/* Gen6's DP voltage swing and pre-emphasis control */
3076static uint32_t
3077intel_gen6_edp_signal_levels(uint8_t train_set)
3078{
3c5a62b5
YL		 3079 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3080 DP_TRAIN_PRE_EMPHASIS_MASK);
3081 switch (signal_levels) {
bd60018a
SJ		 3082 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3083 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3084 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3085 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3086 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3087 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3088 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3089 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3090 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3092 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3094 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3095 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3096 default:
3c5a62b5
YL		 3097 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3098 "0x%x\n", signal_levels);
3099 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3100 }
3101}
3102
1a2eb460
KP		 3103/* Gen7's DP voltage swing and pre-emphasis control */
3104static uint32_t
3105intel_gen7_edp_signal_levels(uint8_t train_set)
3106{
3107 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3108 DP_TRAIN_PRE_EMPHASIS_MASK);
3109 switch (signal_levels) {
bd60018a 3110 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3111 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3112 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3113 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3114 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3115 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3116
bd60018a 3117 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3118 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3119 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3120 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3121
bd60018a 3122 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3123 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3124 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3125 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3126
3127 default:
3128 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3129 "0x%x\n", signal_levels);
3130 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3131 }
3132}
3133
d6c0d722
PZ		 3134/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3135static uint32_t
f0a3424e 3136intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3137{
d6c0d722
PZ		 3138 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3139 DP_TRAIN_PRE_EMPHASIS_MASK);
3140 switch (signal_levels) {
bd60018a 3141 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3142 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3143 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3144 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3145 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3146 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3147 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3148 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3149
bd60018a 3150 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3151 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3152 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3153 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3154 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3155 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3156
bd60018a 3157 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3158 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3159 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3160 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3161 default:
3162 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3163 "0x%x\n", signal_levels);
c5fe6a06 3164 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3165 }
a4fc5ed6
KP		 3166}
3167
f0a3424e
PZ		 3168/* Properly updates "DP" with the correct signal levels. */
3169static void
3170intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3171{
3172 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3173 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3174 struct drm_device *dev = intel_dig_port->base.base.dev;
3175 uint32_t signal_levels, mask;
3176 uint8_t train_set = intel_dp->train_set[0];
3177
5a9d1f1a 3178 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3179 signal_levels = intel_hsw_signal_levels(train_set);
3180 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3181 } else if (IS_CHERRYVIEW(dev)) {
3182 signal_levels = intel_chv_signal_levels(intel_dp);
3183 mask = 0;
e2fa6fba
P		 3184 } else if (IS_VALLEYVIEW(dev)) {
3185 signal_levels = intel_vlv_signal_levels(intel_dp);
3186 mask = 0;
bc7d38a4 3187 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3188 signal_levels = intel_gen7_edp_signal_levels(train_set);
3189 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3190 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3191 signal_levels = intel_gen6_edp_signal_levels(train_set);
3192 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3193 } else {
3194 signal_levels = intel_gen4_signal_levels(train_set);
3195 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3196 }
3197
3198 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3199
3200 *DP = (*DP & ~mask) | signal_levels;
3201}
3202
a4fc5ed6 3203static bool
ea5b213a 3204intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3205 uint32_t *DP,
58e10eb9 3206 uint8_t dp_train_pat)
a4fc5ed6 3207{
174edf1f
PZ		 3208 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3209 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3210 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3211 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3212 int ret, len;
a4fc5ed6 3213
7b13b58a 3214 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3215
70aff66c 3216 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3217 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3218
2cdfe6c8
JN		 3219 buf[0] = dp_train_pat;
3220 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3221 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3222 /* don't write DP_TRAINING_LANEx_SET on disable */
3223 len = 1;
3224 } else {
3225 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3226 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3227 len = intel_dp->lane_count + 1;
47ea7542 3228 }
a4fc5ed6 3229
9d1a1031
JN		 3230 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3231 buf, len);
2cdfe6c8
JN		 3232
3233 return ret == len;
a4fc5ed6
KP		 3234}
3235
70aff66c
JN		 3236static bool
3237intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3238 uint8_t dp_train_pat)
3239{
953d22e8 3240 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3241 intel_dp_set_signal_levels(intel_dp, DP);
3242 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3243}
3244
3245static bool
3246intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3247 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3248{
3249 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3250 struct drm_device *dev = intel_dig_port->base.base.dev;
3251 struct drm_i915_private *dev_priv = dev->dev_private;
3252 int ret;
3253
3254 intel_get_adjust_train(intel_dp, link_status);
3255 intel_dp_set_signal_levels(intel_dp, DP);
3256
3257 I915_WRITE(intel_dp->output_reg, *DP);
3258 POSTING_READ(intel_dp->output_reg);
3259
9d1a1031
JN		 3260 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3261 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3262
3263 return ret == intel_dp->lane_count;
3264}
3265
3ab9c637
ID		 3266static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3267{
3268 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3269 struct drm_device *dev = intel_dig_port->base.base.dev;
3270 struct drm_i915_private *dev_priv = dev->dev_private;
3271 enum port port = intel_dig_port->port;
3272 uint32_t val;
3273
3274 if (!HAS_DDI(dev))
3275 return;
3276
3277 val = I915_READ(DP_TP_CTL(port));
3278 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3279 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3280 I915_WRITE(DP_TP_CTL(port), val);
3281
3282 /*
3283 * On PORT_A we can have only eDP in SST mode. There the only reason
3284 * we need to set idle transmission mode is to work around a HW issue
3285 * where we enable the pipe while not in idle link-training mode.
3286 * In this case there is requirement to wait for a minimum number of
3287 * idle patterns to be sent.
3288 */
3289 if (port == PORT_A)
3290 return;
3291
3292 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3293 1))
3294 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3295}
3296
33a34e4e 3297/* Enable corresponding port and start training pattern 1 */
c19b0669 3298void
33a34e4e 3299intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3300{
da63a9f2 3301 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3302 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3303 int i;
3304 uint8_t voltage;
cdb0e95b 3305 int voltage_tries, loop_tries;
ea5b213a 3306 uint32_t DP = intel_dp->DP;
6aba5b6c 3307 uint8_t link_config[2];
a4fc5ed6 3308
affa9354 3309 if (HAS_DDI(dev))
c19b0669
PZ		 3310 intel_ddi_prepare_link_retrain(encoder);
3311
3cf2efb1 3312 /* Write the link configuration data */
6aba5b6c
JN		 3313 link_config[0] = intel_dp->link_bw;
3314 link_config[1] = intel_dp->lane_count;
3315 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3316 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3317 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3318
3319 link_config[0] = 0;
3320 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3321 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3322
3323 DP |= DP_PORT_EN;
1a2eb460 3324
70aff66c
JN		 3325 /* clock recovery */
3326 if (!intel_dp_reset_link_train(intel_dp, &DP,
3327 DP_TRAINING_PATTERN_1 |
3328 DP_LINK_SCRAMBLING_DISABLE)) {
3329 DRM_ERROR("failed to enable link training\n");
3330 return;
3331 }
3332
a4fc5ed6 3333 voltage = 0xff;
cdb0e95b
KP		 3334 voltage_tries = 0;
3335 loop_tries = 0;
a4fc5ed6 3336 for (;;) {
70aff66c 3337 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3338
a7c9655f 3339 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3340 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3341 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3342 break;
93f62dad 3343 }
a4fc5ed6 3344
01916270 3345 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3346 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3347 break;
3348 }
3349
3350 /* Check to see if we've tried the max voltage */
3351 for (i = 0; i < intel_dp->lane_count; i++)
3352 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3353 break;
3b4f819d 3354 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3355 ++loop_tries;
3356 if (loop_tries == 5) {
3def84b3 3357 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3358 break;
3359 }
70aff66c
JN		 3360 intel_dp_reset_link_train(intel_dp, &DP,
3361 DP_TRAINING_PATTERN_1 |
3362 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3363 voltage_tries = 0;
3364 continue;
3365 }
a4fc5ed6 3366
3cf2efb1 3367 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3368 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3369 ++voltage_tries;
b06fbda3 3370 if (voltage_tries == 5) {
3def84b3 3371 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3372 break;
3373 }
3374 } else
3375 voltage_tries = 0;
3376 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3377
70aff66c
JN		 3378 /* Update training set as requested by target */
3379 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3380 DRM_ERROR("failed to update link training\n");
3381 break;
3382 }
a4fc5ed6
KP		 3383 }
3384
33a34e4e
JB		 3385 intel_dp->DP = DP;
3386}
3387
c19b0669 3388void
33a34e4e
JB		 3389intel_dp_complete_link_train(struct intel_dp *intel_dp)
3390{
33a34e4e 3391 bool channel_eq = false;
37f80975 3392 int tries, cr_tries;
33a34e4e 3393 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3394 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3395
3396 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3397 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3398 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3399
a4fc5ed6 3400 /* channel equalization */
70aff66c 3401 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3402 training_pattern |
70aff66c
JN		 3403 DP_LINK_SCRAMBLING_DISABLE)) {
3404 DRM_ERROR("failed to start channel equalization\n");
3405 return;
3406 }
3407
a4fc5ed6 3408 tries = 0;
37f80975 3409 cr_tries = 0;
a4fc5ed6
KP		 3410 channel_eq = false;
3411 for (;;) {
70aff66c 3412 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3413
37f80975
JB		 3414 if (cr_tries > 5) {
3415 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3416 break;
3417 }
3418
a7c9655f 3419 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3420 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3421 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3422 break;
70aff66c 3423 }
a4fc5ed6 3424
37f80975 3425 /* Make sure clock is still ok */
01916270 3426 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3427 intel_dp_start_link_train(intel_dp);
70aff66c 3428 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3429 training_pattern |
70aff66c 3430 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3431 cr_tries++;
3432 continue;
3433 }
3434
1ffdff13 3435 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3436 channel_eq = true;
3437 break;
3438 }
a4fc5ed6 3439
37f80975
JB		 3440 /* Try 5 times, then try clock recovery if that fails */
3441 if (tries > 5) {
37f80975 3442 intel_dp_start_link_train(intel_dp);
70aff66c 3443 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3444 training_pattern |
70aff66c 3445 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3446 tries = 0;
3447 cr_tries++;
3448 continue;
3449 }
a4fc5ed6 3450
70aff66c
JN		 3451 /* Update training set as requested by target */
3452 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3453 DRM_ERROR("failed to update link training\n");
3454 break;
3455 }
3cf2efb1 3456 ++tries;
869184a6 3457 }
3cf2efb1 3458
3ab9c637
ID		 3459 intel_dp_set_idle_link_train(intel_dp);
3460
3461 intel_dp->DP = DP;
3462
d6c0d722 3463 if (channel_eq)
07f42258 3464 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3465
3ab9c637
ID		 3466}
3467
3468void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3469{
70aff66c 3470 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3471 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3472}
3473
3474static void
ea5b213a 3475intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3476{
da63a9f2 3477 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3478 enum port port = intel_dig_port->port;
da63a9f2 3479 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3480 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3481 struct intel_crtc *intel_crtc =
3482 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3483 uint32_t DP = intel_dp->DP;
a4fc5ed6 3484
bc76e320 3485 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3486 return;
3487
0c33d8d7 3488 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3489 return;
3490
28c97730 3491 DRM_DEBUG_KMS("\n");
32f9d658 3492
bc7d38a4 3493 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3494 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3495 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3496 } else {
aad3d14d
VS		 3497 if (IS_CHERRYVIEW(dev))
3498 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3499 else
3500 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3501 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3502 }
fe255d00 3503 POSTING_READ(intel_dp->output_reg);
5eb08b69 3504
493a7081 3505 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3506 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3507 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3508
5bddd17f
EA		 3509 /* Hardware workaround: leaving our transcoder select
3510 * set to transcoder B while it's off will prevent the
3511 * corresponding HDMI output on transcoder A.
3512 *
3513 * Combine this with another hardware workaround:
3514 * transcoder select bit can only be cleared while the
3515 * port is enabled.
3516 */
3517 DP &= ~DP_PIPEB_SELECT;
3518 I915_WRITE(intel_dp->output_reg, DP);
3519
3520 /* Changes to enable or select take place the vblank
3521 * after being written.
3522 */
ff50afe9
DV		 3523 if (WARN_ON(crtc == NULL)) {
3524 /* We should never try to disable a port without a crtc
3525 * attached. For paranoia keep the code around for a
3526 * bit. */
31acbcc4
CW		 3527 POSTING_READ(intel_dp->output_reg);
3528 msleep(50);
3529 } else
ab527efc 3530 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3531 }
3532
832afda6 3533 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3534 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3535 POSTING_READ(intel_dp->output_reg);
f01eca2e 3536 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3537}
3538
26d61aad
KP		 3539static bool
3540intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3541{
a031d709
RV		 3542 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3543 struct drm_device *dev = dig_port->base.base.dev;
3544 struct drm_i915_private *dev_priv = dev->dev_private;
3545
9d1a1031
JN		 3546 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3547 sizeof(intel_dp->dpcd)) < 0)
edb39244 3548 return false; /* aux transfer failed */
92fd8fd1 3549
a8e98153 3550 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3551
edb39244
AJ		 3552 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3553 return false; /* DPCD not present */
3554
2293bb5c
SK		 3555 /* Check if the panel supports PSR */
3556 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3557 if (is_edp(intel_dp)) {
9d1a1031
JN		 3558 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3559 intel_dp->psr_dpcd,
3560 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3561 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3562 dev_priv->psr.sink_support = true;
50003939 3563 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3564 }
50003939
JN		 3565 }
3566
06ea66b6
TP		 3567 /* Training Pattern 3 support */
3568 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3569 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3570 intel_dp->use_tps3 = true;
f8d8a672 3571 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3572 } else
3573 intel_dp->use_tps3 = false;
3574
edb39244
AJ		 3575 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3576 DP_DWN_STRM_PORT_PRESENT))
3577 return true; /* native DP sink */
3578
3579 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3580 return true; /* no per-port downstream info */
3581
9d1a1031
JN		 3582 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3583 intel_dp->downstream_ports,
3584 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3585 return false; /* downstream port status fetch failed */
3586
3587 return true;
92fd8fd1
KP		 3588}
3589
0d198328
AJ		 3590static void
3591intel_dp_probe_oui(struct intel_dp *intel_dp)
3592{
3593 u8 buf[3];
3594
3595 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3596 return;
3597
9d1a1031 3598 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3599 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3600 buf[0], buf[1], buf[2]);
3601
9d1a1031 3602 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3603 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3604 buf[0], buf[1], buf[2]);
3605}
3606
0e32b39c
DA		 3607static bool
3608intel_dp_probe_mst(struct intel_dp *intel_dp)
3609{
3610 u8 buf[1];
3611
3612 if (!intel_dp->can_mst)
3613 return false;
3614
3615 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3616 return false;
3617
0e32b39c
DA		 3618 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3619 if (buf[0] & DP_MST_CAP) {
3620 DRM_DEBUG_KMS("Sink is MST capable\n");
3621 intel_dp->is_mst = true;
3622 } else {
3623 DRM_DEBUG_KMS("Sink is not MST capable\n");
3624 intel_dp->is_mst = false;
3625 }
3626 }
0e32b39c
DA		 3627
3628 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3629 return intel_dp->is_mst;
3630}
3631
d2e216d0
RV		 3632int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3633{
3634 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3635 struct drm_device *dev = intel_dig_port->base.base.dev;
3636 struct intel_crtc *intel_crtc =
3637 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3638 u8 buf;
3639 int test_crc_count;
3640 int attempts = 6;
d2e216d0 3641
ad9dc91b 3642 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3643 return -EIO;
d2e216d0 3644
ad9dc91b 3645 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3646 return -ENOTTY;
3647
1dda5f93
RV		 3648 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3649 return -EIO;
3650
9d1a1031 3651 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3652 buf | DP_TEST_SINK_START) < 0)
bda0381e 3653 return -EIO;
d2e216d0 3654
1dda5f93 3655 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3656 return -EIO;
ad9dc91b 3657 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 3658
ad9dc91b 3659 do {
1dda5f93
RV		 3660 if (drm_dp_dpcd_readb(&intel_dp->aux,
3661 DP_TEST_SINK_MISC, &buf) < 0)
3662 return -EIO;
ad9dc91b
RV		 3663 intel_wait_for_vblank(dev, intel_crtc->pipe);
3664 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3665
3666 if (attempts == 0) {
3667 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
3668 return -EIO;
3669 }
d2e216d0 3670
9d1a1031 3671 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 3672 return -EIO;
d2e216d0 3673
1dda5f93
RV		 3674 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3675 return -EIO;
3676 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3677 buf & ~DP_TEST_SINK_START) < 0)
3678 return -EIO;
ce31d9f4 3679
d2e216d0
RV		 3680 return 0;
3681}
3682
a60f0e38
JB		 3683static bool
3684intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3685{
9d1a1031
JN		 3686 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3687 DP_DEVICE_SERVICE_IRQ_VECTOR,
3688 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3689}
3690
0e32b39c
DA		 3691static bool
3692intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3693{
3694 int ret;
3695
3696 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3697 DP_SINK_COUNT_ESI,
3698 sink_irq_vector, 14);
3699 if (ret != 14)
3700 return false;
3701
3702 return true;
3703}
3704
a60f0e38
JB		 3705static void
3706intel_dp_handle_test_request(struct intel_dp *intel_dp)
3707{
3708 /* NAK by default */
9d1a1031 3709 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3710}
3711
0e32b39c
DA		 3712static int
3713intel_dp_check_mst_status(struct intel_dp *intel_dp)
3714{
3715 bool bret;
3716
3717 if (intel_dp->is_mst) {
3718 u8 esi[16] = { 0 };
3719 int ret = 0;
3720 int retry;
3721 bool handled;
3722 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3723go_again:
3724 if (bret == true) {
3725
3726 /* check link status - esi[10] = 0x200c */
3727 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3728 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3729 intel_dp_start_link_train(intel_dp);
3730 intel_dp_complete_link_train(intel_dp);
3731 intel_dp_stop_link_train(intel_dp);
3732 }
3733
3734 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3735 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3736
3737 if (handled) {
3738 for (retry = 0; retry < 3; retry++) {
3739 int wret;
3740 wret = drm_dp_dpcd_write(&intel_dp->aux,
3741 DP_SINK_COUNT_ESI+1,
3742 &esi[1], 3);
3743 if (wret == 3) {
3744 break;
3745 }
3746 }
3747
3748 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3749 if (bret == true) {
3750 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3751 goto go_again;
3752 }
3753 } else
3754 ret = 0;
3755
3756 return ret;
3757 } else {
3758 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3759 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3760 intel_dp->is_mst = false;
3761 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3762 /* send a hotplug event */
3763 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3764 }
3765 }
3766 return -EINVAL;
3767}
3768
a4fc5ed6
KP		 3769/*
3770 * According to DP spec
3771 * 5.1.2:
3772 * 1. Read DPCD
3773 * 2. Configure link according to Receiver Capabilities
3774 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3775 * 4. Check link status on receipt of hot-plug interrupt
3776 */
00c09d70 3777void
ea5b213a 3778intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3779{
5b215bcf 3780 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3781 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3782 u8 sink_irq_vector;
93f62dad 3783 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3784
5b215bcf
DA		 3785 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3786
da63a9f2 3787 if (!intel_encoder->connectors_active)
d2b996ac 3788 return;
59cd09e1 3789
da63a9f2 3790 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3791 return;
3792
1a125d8a
ID		 3793 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3794 return;
3795
92fd8fd1 3796 /* Try to read receiver status if the link appears to be up */
93f62dad 3797 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3798 return;
3799 }
3800
92fd8fd1 3801 /* Now read the DPCD to see if it's actually running */
26d61aad 3802 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3803 return;
3804 }
3805
a60f0e38
JB		 3806 /* Try to read the source of the interrupt */
3807 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3808 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3809 /* Clear interrupt source */
9d1a1031
JN		 3810 drm_dp_dpcd_writeb(&intel_dp->aux,
3811 DP_DEVICE_SERVICE_IRQ_VECTOR,
3812 sink_irq_vector);
a60f0e38
JB		 3813
3814 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3815 intel_dp_handle_test_request(intel_dp);
3816 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3817 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3818 }
3819
1ffdff13 3820 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3821 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3822 intel_encoder->base.name);
33a34e4e
JB		 3823 intel_dp_start_link_train(intel_dp);
3824 intel_dp_complete_link_train(intel_dp);
3ab9c637 3825 intel_dp_stop_link_train(intel_dp);
33a34e4e 3826 }
a4fc5ed6 3827}
a4fc5ed6 3828
caf9ab24 3829/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3830static enum drm_connector_status
26d61aad 3831intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3832{
caf9ab24 3833 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3834 uint8_t type;
3835
3836 if (!intel_dp_get_dpcd(intel_dp))
3837 return connector_status_disconnected;
3838
3839 /* if there's no downstream port, we're done */
3840 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3841 return connector_status_connected;
caf9ab24
AJ		 3842
3843 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3844 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3845 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3846 uint8_t reg;
9d1a1031
JN		 3847
3848 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3849 &reg, 1) < 0)
caf9ab24 3850 return connector_status_unknown;
9d1a1031 3851
23235177
AJ		 3852 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3853 : connector_status_disconnected;
caf9ab24
AJ		 3854 }
3855
3856 /* If no HPD, poke DDC gently */
0b99836f 3857 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3858 return connector_status_connected;
caf9ab24
AJ		 3859
3860 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3861 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3862 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3863 if (type == DP_DS_PORT_TYPE_VGA ||
3864 type == DP_DS_PORT_TYPE_NON_EDID)
3865 return connector_status_unknown;
3866 } else {
3867 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3868 DP_DWN_STRM_PORT_TYPE_MASK;
3869 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3870 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3871 return connector_status_unknown;
3872 }
caf9ab24
AJ		 3873
3874 /* Anything else is out of spec, warn and ignore */
3875 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3876 return connector_status_disconnected;
71ba9000
AJ		 3877}
3878
d410b56d
CW		 3879static enum drm_connector_status
3880edp_detect(struct intel_dp *intel_dp)
3881{
3882 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3883 enum drm_connector_status status;
3884
3885 status = intel_panel_detect(dev);
3886 if (status == connector_status_unknown)
3887 status = connector_status_connected;
3888
3889 return status;
3890}
3891
5eb08b69 3892static enum drm_connector_status
a9756bb5 3893ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3894{
30add22d 3895 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3896 struct drm_i915_private *dev_priv = dev->dev_private;
3897 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 3898
1b469639
DL		 3899 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3900 return connector_status_disconnected;
3901
26d61aad 3902 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3903}
3904
2a592bec
DA		 3905static int g4x_digital_port_connected(struct drm_device *dev,
3906 struct intel_digital_port *intel_dig_port)
a4fc5ed6 3907{
a4fc5ed6 3908 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 3909 uint32_t bit;
5eb08b69 3910
232a6ee9
TP		 3911 if (IS_VALLEYVIEW(dev)) {
3912 switch (intel_dig_port->port) {
3913 case PORT_B:
3914 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3915 break;
3916 case PORT_C:
3917 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3918 break;
3919 case PORT_D:
3920 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3921 break;
3922 default:
2a592bec 3923 return -EINVAL;
232a6ee9
TP		 3924 }
3925 } else {
3926 switch (intel_dig_port->port) {
3927 case PORT_B:
3928 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3929 break;
3930 case PORT_C:
3931 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3932 break;
3933 case PORT_D:
3934 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3935 break;
3936 default:
2a592bec 3937 return -EINVAL;
232a6ee9 3938 }
a4fc5ed6
KP		 3939 }
3940
10f76a38 3941 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 3942 return 0;
3943 return 1;
3944}
3945
3946static enum drm_connector_status
3947g4x_dp_detect(struct intel_dp *intel_dp)
3948{
3949 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3950 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3951 int ret;
3952
3953 /* Can't disconnect eDP, but you can close the lid... */
3954 if (is_edp(intel_dp)) {
3955 enum drm_connector_status status;
3956
3957 status = intel_panel_detect(dev);
3958 if (status == connector_status_unknown)
3959 status = connector_status_connected;
3960 return status;
3961 }
3962
3963 ret = g4x_digital_port_connected(dev, intel_dig_port);
3964 if (ret == -EINVAL)
3965 return connector_status_unknown;
3966 else if (ret == 0)
a4fc5ed6
KP		 3967 return connector_status_disconnected;
3968
26d61aad 3969 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3970}
3971
8c241fef 3972static struct edid *
beb60608 3973intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 3974{
beb60608 3975 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 3976
9cd300e0
JN		 3977 /* use cached edid if we have one */
3978 if (intel_connector->edid) {
9cd300e0
JN		 3979 /* invalid edid */
3980 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3981 return NULL;
3982
55e9edeb 3983 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 3984 } else
3985 return drm_get_edid(&intel_connector->base,
3986 &intel_dp->aux.ddc);
3987}
8c241fef 3988
beb60608
CW		 3989static void
3990intel_dp_set_edid(struct intel_dp *intel_dp)
3991{
3992 struct intel_connector *intel_connector = intel_dp->attached_connector;
3993 struct edid *edid;
8c241fef 3994
beb60608
CW		 3995 edid = intel_dp_get_edid(intel_dp);
3996 intel_connector->detect_edid = edid;
3997
3998 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
3999 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4000 else
4001 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4002}
4003
beb60608
CW		 4004static void
4005intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4006{
beb60608 4007 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4008
beb60608
CW		 4009 kfree(intel_connector->detect_edid);
4010 intel_connector->detect_edid = NULL;
9cd300e0 4011
beb60608
CW		 4012 intel_dp->has_audio = false;
4013}
d6f24d0f 4014
beb60608
CW		 4015static enum intel_display_power_domain
4016intel_dp_power_get(struct intel_dp *dp)
4017{
4018 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4019 enum intel_display_power_domain power_domain;
4020
4021 power_domain = intel_display_port_power_domain(encoder);
4022 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4023
4024 return power_domain;
4025}
d6f24d0f 4026
beb60608
CW		 4027static void
4028intel_dp_power_put(struct intel_dp *dp,
4029 enum intel_display_power_domain power_domain)
4030{
4031 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4032 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4033}
4034
a9756bb5
ZW		 4035static enum drm_connector_status
4036intel_dp_detect(struct drm_connector *connector, bool force)
4037{
4038 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4039 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4040 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4041 struct drm_device *dev = connector->dev;
a9756bb5 4042 enum drm_connector_status status;
671dedd2 4043 enum intel_display_power_domain power_domain;
0e32b39c 4044 bool ret;
a9756bb5 4045
164c8598 4046 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4047 connector->base.id, connector->name);
beb60608 4048 intel_dp_unset_edid(intel_dp);
164c8598 4049
0e32b39c
DA		 4050 if (intel_dp->is_mst) {
4051 /* MST devices are disconnected from a monitor POV */
4052 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4053 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4054 return connector_status_disconnected;
0e32b39c
DA		 4055 }
4056
beb60608 4057 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4058
d410b56d
CW		 4059 /* Can't disconnect eDP, but you can close the lid... */
4060 if (is_edp(intel_dp))
4061 status = edp_detect(intel_dp);
4062 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4063 status = ironlake_dp_detect(intel_dp);
4064 else
4065 status = g4x_dp_detect(intel_dp);
4066 if (status != connector_status_connected)
c8c8fb33 4067 goto out;
a9756bb5 4068
0d198328
AJ		 4069 intel_dp_probe_oui(intel_dp);
4070
0e32b39c
DA		 4071 ret = intel_dp_probe_mst(intel_dp);
4072 if (ret) {
4073 /* if we are in MST mode then this connector
4074 won't appear connected or have anything with EDID on it */
4075 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4076 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4077 status = connector_status_disconnected;
4078 goto out;
4079 }
4080
beb60608 4081 intel_dp_set_edid(intel_dp);
a9756bb5 4082
d63885da
PZ		 4083 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4084 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4085 status = connector_status_connected;
4086
4087out:
beb60608 4088 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4089 return status;
a4fc5ed6
KP		 4090}
4091
beb60608
CW		 4092static void
4093intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4094{
df0e9248 4095 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4096 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4097 enum intel_display_power_domain power_domain;
a4fc5ed6 4098
beb60608
CW		 4099 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4100 connector->base.id, connector->name);
4101 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4102
beb60608
CW		 4103 if (connector->status != connector_status_connected)
4104 return;
671dedd2 4105
beb60608
CW		 4106 power_domain = intel_dp_power_get(intel_dp);
4107
4108 intel_dp_set_edid(intel_dp);
4109
4110 intel_dp_power_put(intel_dp, power_domain);
4111
4112 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4113 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4114}
4115
4116static int intel_dp_get_modes(struct drm_connector *connector)
4117{
4118 struct intel_connector *intel_connector = to_intel_connector(connector);
4119 struct edid *edid;
4120
4121 edid = intel_connector->detect_edid;
4122 if (edid) {
4123 int ret = intel_connector_update_modes(connector, edid);
4124 if (ret)
4125 return ret;
4126 }
32f9d658 4127
f8779fda 4128 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4129 if (is_edp(intel_attached_dp(connector)) &&
4130 intel_connector->panel.fixed_mode) {
f8779fda 4131 struct drm_display_mode *mode;
beb60608
CW		 4132
4133 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4134 intel_connector->panel.fixed_mode);
f8779fda 4135 if (mode) {
32f9d658
ZW		 4136 drm_mode_probed_add(connector, mode);
4137 return 1;
4138 }
4139 }
beb60608 4140
32f9d658 4141 return 0;
a4fc5ed6
KP		 4142}
4143
1aad7ac0
CW		 4144static bool
4145intel_dp_detect_audio(struct drm_connector *connector)
4146{
1aad7ac0 4147 bool has_audio = false;
beb60608 4148 struct edid *edid;
1aad7ac0 4149
beb60608
CW		 4150 edid = to_intel_connector(connector)->detect_edid;
4151 if (edid)
1aad7ac0 4152 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4153
1aad7ac0
CW		 4154 return has_audio;
4155}
4156
f684960e
CW		 4157static int
4158intel_dp_set_property(struct drm_connector *connector,
4159 struct drm_property *property,
4160 uint64_t val)
4161{
e953fd7b 4162 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4163 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4164 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4165 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4166 int ret;
4167
662595df 4168 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4169 if (ret)
4170 return ret;
4171
3f43c48d 4172 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4173 int i = val;
4174 bool has_audio;
4175
4176 if (i == intel_dp->force_audio)
f684960e
CW		 4177 return 0;
4178
1aad7ac0 4179 intel_dp->force_audio = i;
f684960e 4180
c3e5f67b 4181 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4182 has_audio = intel_dp_detect_audio(connector);
4183 else
c3e5f67b 4184 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4185
4186 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4187 return 0;
4188
1aad7ac0 4189 intel_dp->has_audio = has_audio;
f684960e
CW		 4190 goto done;
4191 }
4192
e953fd7b 4193 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4194 bool old_auto = intel_dp->color_range_auto;
4195 uint32_t old_range = intel_dp->color_range;
4196
55bc60db
VS		 4197 switch (val) {
4198 case INTEL_BROADCAST_RGB_AUTO:
4199 intel_dp->color_range_auto = true;
4200 break;
4201 case INTEL_BROADCAST_RGB_FULL:
4202 intel_dp->color_range_auto = false;
4203 intel_dp->color_range = 0;
4204 break;
4205 case INTEL_BROADCAST_RGB_LIMITED:
4206 intel_dp->color_range_auto = false;
4207 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4208 break;
4209 default:
4210 return -EINVAL;
4211 }
ae4edb80
DV		 4212
4213 if (old_auto == intel_dp->color_range_auto &&
4214 old_range == intel_dp->color_range)
4215 return 0;
4216
e953fd7b
CW		 4217 goto done;
4218 }
4219
53b41837
YN		 4220 if (is_edp(intel_dp) &&
4221 property == connector->dev->mode_config.scaling_mode_property) {
4222 if (val == DRM_MODE_SCALE_NONE) {
4223 DRM_DEBUG_KMS("no scaling not supported\n");
4224 return -EINVAL;
4225 }
4226
4227 if (intel_connector->panel.fitting_mode == val) {
4228 /* the eDP scaling property is not changed */
4229 return 0;
4230 }
4231 intel_connector->panel.fitting_mode = val;
4232
4233 goto done;
4234 }
4235
f684960e
CW		 4236 return -EINVAL;
4237
4238done:
c0c36b94
CW		 4239 if (intel_encoder->base.crtc)
4240 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4241
4242 return 0;
4243}
4244
a4fc5ed6 4245static void
73845adf 4246intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4247{
1d508706 4248 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4249
10e972d3 4250 kfree(intel_connector->detect_edid);
beb60608 4251
9cd300e0
JN		 4252 if (!IS_ERR_OR_NULL(intel_connector->edid))
4253 kfree(intel_connector->edid);
4254
acd8db10
PZ		 4255 /* Can't call is_edp() since the encoder may have been destroyed
4256 * already. */
4257 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4258 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4259
a4fc5ed6 4260 drm_connector_cleanup(connector);
55f78c43 4261 kfree(connector);
a4fc5ed6
KP		 4262}
4263
00c09d70 4264void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4265{
da63a9f2
PZ		 4266 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4267 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4268
4f71d0cb 4269 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4270 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4271 drm_encoder_cleanup(encoder);
bd943159
KP		 4272 if (is_edp(intel_dp)) {
4273 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4274 /*
4275 * vdd might still be enabled do to the delayed vdd off.
4276 * Make sure vdd is actually turned off here.
4277 */
773538e8 4278 pps_lock(intel_dp);
4be73780 4279 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4280 pps_unlock(intel_dp);
4281
01527b31
CT		 4282 if (intel_dp->edp_notifier.notifier_call) {
4283 unregister_reboot_notifier(&intel_dp->edp_notifier);
4284 intel_dp->edp_notifier.notifier_call = NULL;
4285 }
bd943159 4286 }
da63a9f2 4287 kfree(intel_dig_port);
24d05927
DV		 4288}
4289
07f9cd0b
ID		 4290static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4291{
4292 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4293
4294 if (!is_edp(intel_dp))
4295 return;
4296
951468f3
VS		 4297 /*
4298 * vdd might still be enabled do to the delayed vdd off.
4299 * Make sure vdd is actually turned off here.
4300 */
773538e8 4301 pps_lock(intel_dp);
07f9cd0b 4302 edp_panel_vdd_off_sync(intel_dp);
773538e8 4303 pps_unlock(intel_dp);
07f9cd0b
ID		 4304}
4305
49e6bc51
VS		 4306static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4307{
4308 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4309 struct drm_device *dev = intel_dig_port->base.base.dev;
4310 struct drm_i915_private *dev_priv = dev->dev_private;
4311 enum intel_display_power_domain power_domain;
4312
4313 lockdep_assert_held(&dev_priv->pps_mutex);
4314
4315 if (!edp_have_panel_vdd(intel_dp))
4316 return;
4317
4318 /*
4319 * The VDD bit needs a power domain reference, so if the bit is
4320 * already enabled when we boot or resume, grab this reference and
4321 * schedule a vdd off, so we don't hold on to the reference
4322 * indefinitely.
4323 */
4324 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4325 power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4326 intel_display_power_get(dev_priv, power_domain);
4327
4328 edp_panel_vdd_schedule_off(intel_dp);
4329}
4330
6d93c0c4
ID		 4331static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4332{
49e6bc51
VS		 4333 struct intel_dp *intel_dp;
4334
4335 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4336 return;
4337
4338 intel_dp = enc_to_intel_dp(encoder);
4339
4340 pps_lock(intel_dp);
4341
4342 /*
4343 * Read out the current power sequencer assignment,
4344 * in case the BIOS did something with it.
4345 */
4346 if (IS_VALLEYVIEW(encoder->dev))
4347 vlv_initial_power_sequencer_setup(intel_dp);
4348
4349 intel_edp_panel_vdd_sanitize(intel_dp);
4350
4351 pps_unlock(intel_dp);
6d93c0c4
ID		 4352}
4353
a4fc5ed6 4354static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4355 .dpms = intel_connector_dpms,
a4fc5ed6 4356 .detect = intel_dp_detect,
beb60608 4357 .force = intel_dp_force,
a4fc5ed6 4358 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4359 .set_property = intel_dp_set_property,
73845adf 4360 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4361};
4362
4363static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4364 .get_modes = intel_dp_get_modes,
4365 .mode_valid = intel_dp_mode_valid,
df0e9248 4366 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4367};
4368
a4fc5ed6 4369static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4370 .reset = intel_dp_encoder_reset,
24d05927 4371 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4372};
4373
0e32b39c 4374void
21d40d37 4375intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4376{
0e32b39c 4377 return;
c8110e52 4378}
6207937d 4379
13cf5504
DA		 4380bool
4381intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4382{
4383 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4384 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4385 struct drm_device *dev = intel_dig_port->base.base.dev;
4386 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4387 enum intel_display_power_domain power_domain;
4388 bool ret = true;
4389
0e32b39c
DA		 4390 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4391 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4392
26fbb774
VS		 4393 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4394 port_name(intel_dig_port->port),
0e32b39c 4395 long_hpd ? "long" : "short");
13cf5504 4396
1c767b33
ID		 4397 power_domain = intel_display_port_power_domain(intel_encoder);
4398 intel_display_power_get(dev_priv, power_domain);
4399
0e32b39c 4400 if (long_hpd) {
2a592bec
DA		 4401
4402 if (HAS_PCH_SPLIT(dev)) {
4403 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4404 goto mst_fail;
4405 } else {
4406 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4407 goto mst_fail;
4408 }
0e32b39c
DA		 4409
4410 if (!intel_dp_get_dpcd(intel_dp)) {
4411 goto mst_fail;
4412 }
4413
4414 intel_dp_probe_oui(intel_dp);
4415
4416 if (!intel_dp_probe_mst(intel_dp))
4417 goto mst_fail;
4418
4419 } else {
4420 if (intel_dp->is_mst) {
1c767b33 4421 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4422 goto mst_fail;
4423 }
4424
4425 if (!intel_dp->is_mst) {
4426 /*
4427 * we'll check the link status via the normal hot plug path later -
4428 * but for short hpds we should check it now
4429 */
5b215bcf 4430 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4431 intel_dp_check_link_status(intel_dp);
5b215bcf 4432 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4433 }
4434 }
1c767b33
ID		 4435 ret = false;
4436 goto put_power;
0e32b39c
DA		 4437mst_fail:
4438 /* if we were in MST mode, and device is not there get out of MST mode */
4439 if (intel_dp->is_mst) {
4440 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4441 intel_dp->is_mst = false;
4442 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4443 }
1c767b33
ID		 4444put_power:
4445 intel_display_power_put(dev_priv, power_domain);
4446
4447 return ret;
13cf5504
DA		 4448}
4449
e3421a18
ZW		 4450/* Return which DP Port should be selected for Transcoder DP control */
4451int
0206e353 4452intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4453{
4454 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4455 struct intel_encoder *intel_encoder;
4456 struct intel_dp *intel_dp;
e3421a18 4457
fa90ecef
PZ		 4458 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4459 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4460
fa90ecef
PZ		 4461 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4462 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4463 return intel_dp->output_reg;
e3421a18 4464 }
ea5b213a 4465
e3421a18
ZW		 4466 return -1;
4467}
4468
36e83a18 4469/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4470bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4471{
4472 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4473 union child_device_config *p_child;
36e83a18 4474 int i;
5d8a7752
VS		 4475 static const short port_mapping[] = {
4476 [PORT_B] = PORT_IDPB,
4477 [PORT_C] = PORT_IDPC,
4478 [PORT_D] = PORT_IDPD,
4479 };
36e83a18 4480
3b32a35b
VS		 4481 if (port == PORT_A)
4482 return true;
4483
41aa3448 4484 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4485 return false;
4486
41aa3448
RV		 4487 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4488 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4489
5d8a7752 4490 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4491 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4492 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4493 return true;
4494 }
4495 return false;
4496}
4497
0e32b39c 4498void
f684960e
CW		 4499intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4500{
53b41837
YN		 4501 struct intel_connector *intel_connector = to_intel_connector(connector);
4502
3f43c48d 4503 intel_attach_force_audio_property(connector);
e953fd7b 4504 intel_attach_broadcast_rgb_property(connector);
55bc60db 4505 intel_dp->color_range_auto = true;
53b41837
YN		 4506
4507 if (is_edp(intel_dp)) {
4508 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4509 drm_object_attach_property(
4510 &connector->base,
53b41837 4511 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4512 DRM_MODE_SCALE_ASPECT);
4513 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4514 }
f684960e
CW		 4515}
4516
dada1a9f
ID		 4517static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4518{
4519 intel_dp->last_power_cycle = jiffies;
4520 intel_dp->last_power_on = jiffies;
4521 intel_dp->last_backlight_off = jiffies;
4522}
4523
67a54566
DV		 4524static void
4525intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4526 struct intel_dp *intel_dp)
67a54566
DV		 4527{
4528 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4529 struct edp_power_seq cur, vbt, spec,
4530 *final = &intel_dp->pps_delays;
67a54566 4531 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4532 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4533
e39b999a
VS		 4534 lockdep_assert_held(&dev_priv->pps_mutex);
4535
81ddbc69
VS		 4536 /* already initialized? */
4537 if (final->t11_t12 != 0)
4538 return;
4539
453c5420 4540 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4541 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4542 pp_on_reg = PCH_PP_ON_DELAYS;
4543 pp_off_reg = PCH_PP_OFF_DELAYS;
4544 pp_div_reg = PCH_PP_DIVISOR;
4545 } else {
bf13e81b
JN		 4546 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4547
4548 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4549 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4550 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4551 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4552 }
67a54566
DV		 4553
4554 /* Workaround: Need to write PP_CONTROL with the unlock key as
4555 * the very first thing. */
453c5420 4556 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4557 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4558
453c5420
JB		 4559 pp_on = I915_READ(pp_on_reg);
4560 pp_off = I915_READ(pp_off_reg);
4561 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4562
4563 /* Pull timing values out of registers */
4564 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4565 PANEL_POWER_UP_DELAY_SHIFT;
4566
4567 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4568 PANEL_LIGHT_ON_DELAY_SHIFT;
4569
4570 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4571 PANEL_LIGHT_OFF_DELAY_SHIFT;
4572
4573 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4574 PANEL_POWER_DOWN_DELAY_SHIFT;
4575
4576 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4577 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4578
4579 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4580 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4581
41aa3448 4582 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4583
4584 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4585 * our hw here, which are all in 100usec. */
4586 spec.t1_t3 = 210 * 10;
4587 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4588 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4589 spec.t10 = 500 * 10;
4590 /* This one is special and actually in units of 100ms, but zero
4591 * based in the hw (so we need to add 100 ms). But the sw vbt
4592 * table multiplies it with 1000 to make it in units of 100usec,
4593 * too. */
4594 spec.t11_t12 = (510 + 100) * 10;
4595
4596 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4597 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4598
4599 /* Use the max of the register settings and vbt. If both are
4600 * unset, fall back to the spec limits. */
36b5f425 4601#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4602 spec.field : \
4603 max(cur.field, vbt.field))
4604 assign_final(t1_t3);
4605 assign_final(t8);
4606 assign_final(t9);
4607 assign_final(t10);
4608 assign_final(t11_t12);
4609#undef assign_final
4610
36b5f425 4611#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4612 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4613 intel_dp->backlight_on_delay = get_delay(t8);
4614 intel_dp->backlight_off_delay = get_delay(t9);
4615 intel_dp->panel_power_down_delay = get_delay(t10);
4616 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4617#undef get_delay
4618
f30d26e4
JN		 4619 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4620 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4621 intel_dp->panel_power_cycle_delay);
4622
4623 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4624 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 4625}
4626
4627static void
4628intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4629 struct intel_dp *intel_dp)
f30d26e4
JN		 4630{
4631 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4632 u32 pp_on, pp_off, pp_div, port_sel = 0;
4633 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4634 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4635 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4636 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4637
e39b999a 4638 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4639
4640 if (HAS_PCH_SPLIT(dev)) {
4641 pp_on_reg = PCH_PP_ON_DELAYS;
4642 pp_off_reg = PCH_PP_OFF_DELAYS;
4643 pp_div_reg = PCH_PP_DIVISOR;
4644 } else {
bf13e81b
JN		 4645 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4646
4647 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4648 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4649 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4650 }
4651
b2f19d1a
PZ		 4652 /*
4653 * And finally store the new values in the power sequencer. The
4654 * backlight delays are set to 1 because we do manual waits on them. For
4655 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4656 * we'll end up waiting for the backlight off delay twice: once when we
4657 * do the manual sleep, and once when we disable the panel and wait for
4658 * the PP_STATUS bit to become zero.
4659 */
f30d26e4 4660 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4661 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4662 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4663 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4664 /* Compute the divisor for the pp clock, simply match the Bspec
4665 * formula. */
453c5420 4666 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4667 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4668 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4669
4670 /* Haswell doesn't have any port selection bits for the panel
4671 * power sequencer any more. */
bc7d38a4 4672 if (IS_VALLEYVIEW(dev)) {
ad933b56 4673 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4674 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4675 if (port == PORT_A)
a24c144c 4676 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4677 else
a24c144c 4678 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4679 }
4680
453c5420
JB		 4681 pp_on |= port_sel;
4682
4683 I915_WRITE(pp_on_reg, pp_on);
4684 I915_WRITE(pp_off_reg, pp_off);
4685 I915_WRITE(pp_div_reg, pp_div);
67a54566 4686
67a54566 4687 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4688 I915_READ(pp_on_reg),
4689 I915_READ(pp_off_reg),
4690 I915_READ(pp_div_reg));
f684960e
CW		 4691}
4692
439d7ac0
PB		 4693void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4694{
4695 struct drm_i915_private *dev_priv = dev->dev_private;
4696 struct intel_encoder *encoder;
4697 struct intel_dp *intel_dp = NULL;
4698 struct intel_crtc_config *config = NULL;
4699 struct intel_crtc *intel_crtc = NULL;
4700 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4701 u32 reg, val;
4702 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4703
4704 if (refresh_rate <= 0) {
4705 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4706 return;
4707 }
4708
4709 if (intel_connector == NULL) {
4710 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4711 return;
4712 }
4713
1fcc9d1c
DV		 4714 /*
4715 * FIXME: This needs proper synchronization with psr state. But really
4716 * hard to tell without seeing the user of this function of this code.
4717 * Check locking and ordering once that lands.
4718 */
0bc12bcb 4719 if (INTEL_INFO(dev)->gen < 8 && intel_psr_is_enabled(dev)) {
439d7ac0
PB		 4720 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4721 return;
4722 }
4723
4724 encoder = intel_attached_encoder(&intel_connector->base);
4725 intel_dp = enc_to_intel_dp(&encoder->base);
4726 intel_crtc = encoder->new_crtc;
4727
4728 if (!intel_crtc) {
4729 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4730 return;
4731 }
4732
4733 config = &intel_crtc->config;
4734
4735 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4736 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4737 return;
4738 }
4739
4740 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4741 index = DRRS_LOW_RR;
4742
4743 if (index == intel_dp->drrs_state.refresh_rate_type) {
4744 DRM_DEBUG_KMS(
4745 "DRRS requested for previously set RR...ignoring\n");
4746 return;
4747 }
4748
4749 if (!intel_crtc->active) {
4750 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4751 return;
4752 }
4753
4754 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4755 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4756 val = I915_READ(reg);
4757 if (index > DRRS_HIGH_RR) {
4758 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4759 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4760 } else {
4761 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4762 }
4763 I915_WRITE(reg, val);
4764 }
4765
4766 /*
4767 * mutex taken to ensure that there is no race between differnt
4768 * drrs calls trying to update refresh rate. This scenario may occur
4769 * in future when idleness detection based DRRS in kernel and
4770 * possible calls from user space to set differnt RR are made.
4771 */
4772
4773 mutex_lock(&intel_dp->drrs_state.mutex);
4774
4775 intel_dp->drrs_state.refresh_rate_type = index;
4776
4777 mutex_unlock(&intel_dp->drrs_state.mutex);
4778
4779 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4780}
4781
4f9db5b5
PB		 4782static struct drm_display_mode *
4783intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4784 struct intel_connector *intel_connector,
4785 struct drm_display_mode *fixed_mode)
4786{
4787 struct drm_connector *connector = &intel_connector->base;
4788 struct intel_dp *intel_dp = &intel_dig_port->dp;
4789 struct drm_device *dev = intel_dig_port->base.base.dev;
4790 struct drm_i915_private *dev_priv = dev->dev_private;
4791 struct drm_display_mode *downclock_mode = NULL;
4792
4793 if (INTEL_INFO(dev)->gen <= 6) {
4794 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4795 return NULL;
4796 }
4797
4798 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4799 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4800 return NULL;
4801 }
4802
4803 downclock_mode = intel_find_panel_downclock
4804 (dev, fixed_mode, connector);
4805
4806 if (!downclock_mode) {
4079b8d1 4807 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4808 return NULL;
4809 }
4810
439d7ac0
PB		 4811 dev_priv->drrs.connector = intel_connector;
4812
4813 mutex_init(&intel_dp->drrs_state.mutex);
4814
4f9db5b5
PB		 4815 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4816
4817 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4818 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4819 return downclock_mode;
4820}
4821
ed92f0b2 4822static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 4823 struct intel_connector *intel_connector)
ed92f0b2
PZ		 4824{
4825 struct drm_connector *connector = &intel_connector->base;
4826 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4827 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4828 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4829 struct drm_i915_private *dev_priv = dev->dev_private;
4830 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4831 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4832 bool has_dpcd;
4833 struct drm_display_mode *scan;
4834 struct edid *edid;
6517d273 4835 enum pipe pipe = INVALID_PIPE;
ed92f0b2 4836
4f9db5b5
PB		 4837 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4838
ed92f0b2
PZ		 4839 if (!is_edp(intel_dp))
4840 return true;
4841
49e6bc51
VS		 4842 pps_lock(intel_dp);
4843 intel_edp_panel_vdd_sanitize(intel_dp);
4844 pps_unlock(intel_dp);
63635217 4845
ed92f0b2 4846 /* Cache DPCD and EDID for edp. */
ed92f0b2 4847 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 4848
4849 if (has_dpcd) {
4850 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4851 dev_priv->no_aux_handshake =
4852 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4853 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4854 } else {
4855 /* if this fails, presume the device is a ghost */
4856 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4857 return false;
4858 }
4859
4860 /* We now know it's not a ghost, init power sequence regs. */
773538e8 4861 pps_lock(intel_dp);
36b5f425 4862 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 4863 pps_unlock(intel_dp);
ed92f0b2 4864
060c8778 4865 mutex_lock(&dev->mode_config.mutex);
0b99836f 4866 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4867 if (edid) {
4868 if (drm_add_edid_modes(connector, edid)) {
4869 drm_mode_connector_update_edid_property(connector,
4870 edid);
4871 drm_edid_to_eld(connector, edid);
4872 } else {
4873 kfree(edid);
4874 edid = ERR_PTR(-EINVAL);
4875 }
4876 } else {
4877 edid = ERR_PTR(-ENOENT);
4878 }
4879 intel_connector->edid = edid;
4880
4881 /* prefer fixed mode from EDID if available */
4882 list_for_each_entry(scan, &connector->probed_modes, head) {
4883 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4884 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4885 downclock_mode = intel_dp_drrs_init(
4886 intel_dig_port,
4887 intel_connector, fixed_mode);
ed92f0b2
PZ		 4888 break;
4889 }
4890 }
4891
4892 /* fallback to VBT if available for eDP */
4893 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4894 fixed_mode = drm_mode_duplicate(dev,
4895 dev_priv->vbt.lfp_lvds_vbt_mode);
4896 if (fixed_mode)
4897 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4898 }
060c8778 4899 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4900
01527b31
CT		 4901 if (IS_VALLEYVIEW(dev)) {
4902 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4903 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 4904
4905 /*
4906 * Figure out the current pipe for the initial backlight setup.
4907 * If the current pipe isn't valid, try the PPS pipe, and if that
4908 * fails just assume pipe A.
4909 */
4910 if (IS_CHERRYVIEW(dev))
4911 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
4912 else
4913 pipe = PORT_TO_PIPE(intel_dp->DP);
4914
4915 if (pipe != PIPE_A && pipe != PIPE_B)
4916 pipe = intel_dp->pps_pipe;
4917
4918 if (pipe != PIPE_A && pipe != PIPE_B)
4919 pipe = PIPE_A;
4920
4921 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
4922 pipe_name(pipe));
01527b31
CT		 4923 }
4924
4f9db5b5 4925 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 4926 intel_connector->panel.backlight_power = intel_edp_backlight_power;
6517d273 4927 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 4928
4929 return true;
4930}
4931
16c25533 4932bool
f0fec3f2
PZ		 4933intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4934 struct intel_connector *intel_connector)
a4fc5ed6 4935{
f0fec3f2
PZ		 4936 struct drm_connector *connector = &intel_connector->base;
4937 struct intel_dp *intel_dp = &intel_dig_port->dp;
4938 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4939 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4940 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4941 enum port port = intel_dig_port->port;
0b99836f 4942 int type;
a4fc5ed6 4943
a4a5d2f8
VS		 4944 intel_dp->pps_pipe = INVALID_PIPE;
4945
ec5b01dd 4946 /* intel_dp vfuncs */
b6b5e383
DL		 4947 if (INTEL_INFO(dev)->gen >= 9)
4948 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
4949 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 4950 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4951 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4952 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4953 else if (HAS_PCH_SPLIT(dev))
4954 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4955 else
4956 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4957
b9ca5fad
DL		 4958 if (INTEL_INFO(dev)->gen >= 9)
4959 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
4960 else
4961 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 4962
0767935e
DV		 4963 /* Preserve the current hw state. */
4964 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4965 intel_dp->attached_connector = intel_connector;
3d3dc149 4966
3b32a35b 4967 if (intel_dp_is_edp(dev, port))
b329530c 4968 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4969 else
4970 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4971
f7d24902
ID		 4972 /*
4973 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4974 * for DP the encoder type can be set by the caller to
4975 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4976 */
4977 if (type == DRM_MODE_CONNECTOR_eDP)
4978 intel_encoder->type = INTEL_OUTPUT_EDP;
4979
c17ed5b5
VS		 4980 /* eDP only on port B and/or C on vlv/chv */
4981 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
4982 port != PORT_B && port != PORT_C))
4983 return false;
4984
e7281eab
ID		 4985 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4986 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4987 port_name(port));
4988
b329530c 4989 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4990 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4991
a4fc5ed6
KP		 4992 connector->interlace_allowed = true;
4993 connector->doublescan_allowed = 0;
4994
f0fec3f2 4995 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4996 edp_panel_vdd_work);
a4fc5ed6 4997
df0e9248 4998 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 4999 drm_connector_register(connector);
a4fc5ed6 5000
affa9354 5001 if (HAS_DDI(dev))
bcbc889b
PZ		 5002 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5003 else
5004 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5005 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5006
0b99836f 5007 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5008 switch (port) {
5009 case PORT_A:
1d843f9d 5010 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5011 break;
5012 case PORT_B:
1d843f9d 5013 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5014 break;
5015 case PORT_C:
1d843f9d 5016 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5017 break;
5018 case PORT_D:
1d843f9d 5019 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5020 break;
5021 default:
ad1c0b19 5022 BUG();
5eb08b69
ZW		 5023 }
5024
dada1a9f 5025 if (is_edp(intel_dp)) {
773538e8 5026 pps_lock(intel_dp);
1e74a324
VS		 5027 intel_dp_init_panel_power_timestamps(intel_dp);
5028 if (IS_VALLEYVIEW(dev))
a4a5d2f8 5029 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5030 else
36b5f425 5031 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5032 pps_unlock(intel_dp);
dada1a9f 5033 }
0095e6dc 5034
9d1a1031 5035 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5036
0e32b39c
DA		 5037 /* init MST on ports that can support it */
5038 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5039 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5040 intel_dp_mst_encoder_init(intel_dig_port,
5041 intel_connector->base.base.id);
0e32b39c
DA		 5042 }
5043 }
5044
36b5f425 5045 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5046 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5047 if (is_edp(intel_dp)) {
5048 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5049 /*
5050 * vdd might still be enabled do to the delayed vdd off.
5051 * Make sure vdd is actually turned off here.
5052 */
773538e8 5053 pps_lock(intel_dp);
4be73780 5054 edp_panel_vdd_off_sync(intel_dp);
773538e8 5055 pps_unlock(intel_dp);
15b1d171 5056 }
34ea3d38 5057 drm_connector_unregister(connector);
b2f246a8 5058 drm_connector_cleanup(connector);
16c25533 5059 return false;
b2f246a8 5060 }
32f9d658 5061
f684960e
CW		 5062 intel_dp_add_properties(intel_dp, connector);
5063
a4fc5ed6
KP		 5064 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5065 * 0xd. Failure to do so will result in spurious interrupts being
5066 * generated on the port when a cable is not attached.
5067 */
5068 if (IS_G4X(dev) && !IS_GM45(dev)) {
5069 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5070 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5071 }
16c25533
PZ		 5072
5073 return true;
a4fc5ed6 5074}
f0fec3f2
PZ		 5075
5076void
5077intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5078{
13cf5504 5079 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5080 struct intel_digital_port *intel_dig_port;
5081 struct intel_encoder *intel_encoder;
5082 struct drm_encoder *encoder;
5083 struct intel_connector *intel_connector;
5084
b14c5679 5085 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5086 if (!intel_dig_port)
5087 return;
5088
b14c5679 5089 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5090 if (!intel_connector) {
5091 kfree(intel_dig_port);
5092 return;
5093 }
5094
5095 intel_encoder = &intel_dig_port->base;
5096 encoder = &intel_encoder->base;
5097
5098 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5099 DRM_MODE_ENCODER_TMDS);
5100
5bfe2ac0 5101 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5102 intel_encoder->disable = intel_disable_dp;
00c09d70 5103 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5104 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5105 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5106 if (IS_CHERRYVIEW(dev)) {
9197c88b 5107 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5108 intel_encoder->pre_enable = chv_pre_enable_dp;
5109 intel_encoder->enable = vlv_enable_dp;
580d3811 5110 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5111 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5112 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5113 intel_encoder->pre_enable = vlv_pre_enable_dp;
5114 intel_encoder->enable = vlv_enable_dp;
49277c31 5115 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5116 } else {
ecff4f3b
JN		 5117 intel_encoder->pre_enable = g4x_pre_enable_dp;
5118 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5119 if (INTEL_INFO(dev)->gen >= 5)
5120 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5121 }
f0fec3f2 5122
174edf1f 5123 intel_dig_port->port = port;
f0fec3f2
PZ		 5124 intel_dig_port->dp.output_reg = output_reg;
5125
00c09d70 5126 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5127 if (IS_CHERRYVIEW(dev)) {
5128 if (port == PORT_D)
5129 intel_encoder->crtc_mask = 1 << 2;
5130 else
5131 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5132 } else {
5133 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5134 }
bc079e8b 5135 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5136 intel_encoder->hot_plug = intel_dp_hot_plug;
5137
13cf5504
DA		 5138 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5139 dev_priv->hpd_irq_port[port] = intel_dig_port;
5140
15b1d171
PZ		 5141 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5142 drm_encoder_cleanup(encoder);
5143 kfree(intel_dig_port);
b2f246a8 5144 kfree(intel_connector);
15b1d171 5145 }
f0fec3f2 5146}
0e32b39c
DA		 5147
5148void intel_dp_mst_suspend(struct drm_device *dev)
5149{
5150 struct drm_i915_private *dev_priv = dev->dev_private;
5151 int i;
5152
5153 /* disable MST */
5154 for (i = 0; i < I915_MAX_PORTS; i++) {
5155 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5156 if (!intel_dig_port)
5157 continue;
5158
5159 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5160 if (!intel_dig_port->dp.can_mst)
5161 continue;
5162 if (intel_dig_port->dp.is_mst)
5163 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5164 }
5165 }
5166}
5167
5168void intel_dp_mst_resume(struct drm_device *dev)
5169{
5170 struct drm_i915_private *dev_priv = dev->dev_private;
5171 int i;
5172
5173 for (i = 0; i < I915_MAX_PORTS; i++) {
5174 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5175 if (!intel_dig_port)
5176 continue;
5177 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5178 int ret;
5179
5180 if (!intel_dig_port->dp.can_mst)
5181 continue;
5182
5183 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5184 if (ret != 0) {
5185 intel_dp_check_mst_status(&intel_dig_port->dp);
5186 }
5187 }
5188 }
5189}
Linux kernel - Deliverables
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