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drm/i915: enable power wells on Haswell init
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
021357ac
CW		 101static inline u32 /* units of 100MHz */
102intel_fdi_link_freq(struct drm_device *dev)
103{
8b99e68c
CW		 104 if (IS_GEN5(dev)) {
105 struct drm_i915_private *dev_priv = dev->dev_private;
106 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
107 } else
108 return 27;
021357ac
CW		 109}
110
e4b36699 111static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 112 .dot = { .min = 25000, .max = 350000 },
113 .vco = { .min = 930000, .max = 1400000 },
114 .n = { .min = 3, .max = 16 },
115 .m = { .min = 96, .max = 140 },
116 .m1 = { .min = 18, .max = 26 },
117 .m2 = { .min = 6, .max = 16 },
118 .p = { .min = 4, .max = 128 },
119 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 120 .p2 = { .dot_limit = 165000,
121 .p2_slow = 4, .p2_fast = 2 },
d4906093 122 .find_pll = intel_find_best_PLL,
e4b36699
KP		 123};
124
125static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 126 .dot = { .min = 25000, .max = 350000 },
127 .vco = { .min = 930000, .max = 1400000 },
128 .n = { .min = 3, .max = 16 },
129 .m = { .min = 96, .max = 140 },
130 .m1 = { .min = 18, .max = 26 },
131 .m2 = { .min = 6, .max = 16 },
132 .p = { .min = 4, .max = 128 },
133 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 134 .p2 = { .dot_limit = 165000,
135 .p2_slow = 14, .p2_fast = 7 },
d4906093 136 .find_pll = intel_find_best_PLL,
e4b36699 137};
273e27ca 138
e4b36699 139static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 140 .dot = { .min = 20000, .max = 400000 },
141 .vco = { .min = 1400000, .max = 2800000 },
142 .n = { .min = 1, .max = 6 },
143 .m = { .min = 70, .max = 120 },
144 .m1 = { .min = 10, .max = 22 },
145 .m2 = { .min = 5, .max = 9 },
146 .p = { .min = 5, .max = 80 },
147 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 148 .p2 = { .dot_limit = 200000,
149 .p2_slow = 10, .p2_fast = 5 },
d4906093 150 .find_pll = intel_find_best_PLL,
e4b36699
KP		 151};
152
153static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 154 .dot = { .min = 20000, .max = 400000 },
155 .vco = { .min = 1400000, .max = 2800000 },
156 .n = { .min = 1, .max = 6 },
157 .m = { .min = 70, .max = 120 },
158 .m1 = { .min = 10, .max = 22 },
159 .m2 = { .min = 5, .max = 9 },
160 .p = { .min = 7, .max = 98 },
161 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 162 .p2 = { .dot_limit = 112000,
163 .p2_slow = 14, .p2_fast = 7 },
d4906093 164 .find_pll = intel_find_best_PLL,
e4b36699
KP		 165};
166
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 169 .dot = { .min = 25000, .max = 270000 },
170 .vco = { .min = 1750000, .max = 3500000},
171 .n = { .min = 1, .max = 4 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 10, .max = 30 },
176 .p1 = { .min = 1, .max = 3},
177 .p2 = { .dot_limit = 270000,
178 .p2_slow = 10,
179 .p2_fast = 10
044c7c41 180 },
d4906093 181 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 182};
183
184static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 185 .dot = { .min = 22000, .max = 400000 },
186 .vco = { .min = 1750000, .max = 3500000},
187 .n = { .min = 1, .max = 4 },
188 .m = { .min = 104, .max = 138 },
189 .m1 = { .min = 16, .max = 23 },
190 .m2 = { .min = 5, .max = 11 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8},
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 10, .p2_fast = 5 },
d4906093 195 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 196};
197
198static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 199 .dot = { .min = 20000, .max = 115000 },
200 .vco = { .min = 1750000, .max = 3500000 },
201 .n = { .min = 1, .max = 3 },
202 .m = { .min = 104, .max = 138 },
203 .m1 = { .min = 17, .max = 23 },
204 .m2 = { .min = 5, .max = 11 },
205 .p = { .min = 28, .max = 112 },
206 .p1 = { .min = 2, .max = 8 },
207 .p2 = { .dot_limit = 0,
208 .p2_slow = 14, .p2_fast = 14
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 80000, .max = 224000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 14, .max = 42 },
221 .p1 = { .min = 2, .max = 6 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 7, .p2_fast = 7
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 229 .dot = { .min = 161670, .max = 227000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 2 },
232 .m = { .min = 97, .max = 108 },
233 .m1 = { .min = 0x10, .max = 0x12 },
234 .m2 = { .min = 0x05, .max = 0x06 },
235 .p = { .min = 10, .max = 20 },
236 .p1 = { .min = 1, .max = 2},
237 .p2 = { .dot_limit = 0,
273e27ca 238 .p2_slow = 10, .p2_fast = 10 },
0206e353 239 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 240};
241
f2b115e6 242static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 243 .dot = { .min = 20000, .max = 400000},
244 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 245 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
273e27ca 248 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 249 .m1 = { .min = 0, .max = 0 },
250 .m2 = { .min = 0, .max = 254 },
251 .p = { .min = 5, .max = 80 },
252 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 253 .p2 = { .dot_limit = 200000,
254 .p2_slow = 10, .p2_fast = 5 },
6115707b 255 .find_pll = intel_find_best_PLL,
e4b36699
KP		 256};
257
f2b115e6 258static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 259 .dot = { .min = 20000, .max = 400000 },
260 .vco = { .min = 1700000, .max = 3500000 },
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 .m1 = { .min = 0, .max = 0 },
264 .m2 = { .min = 0, .max = 254 },
265 .p = { .min = 7, .max = 112 },
266 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 267 .p2 = { .dot_limit = 112000,
268 .p2_slow = 14, .p2_fast = 14 },
6115707b 269 .find_pll = intel_find_best_PLL,
e4b36699
KP		 270};
271
273e27ca
EA		 272/* Ironlake / Sandybridge
273 *
274 * We calculate clock using (register_value + 2) for N/M1/M2, so here
275 * the range value for them is (actual_value - 2).
276 */
b91ad0ec 277static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 278 .dot = { .min = 25000, .max = 350000 },
279 .vco = { .min = 1760000, .max = 3510000 },
280 .n = { .min = 1, .max = 5 },
281 .m = { .min = 79, .max = 127 },
282 .m1 = { .min = 12, .max = 22 },
283 .m2 = { .min = 5, .max = 9 },
284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
286 .p2 = { .dot_limit = 225000,
287 .p2_slow = 10, .p2_fast = 5 },
4547668a 288 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 289};
290
b91ad0ec 291static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 292 .dot = { .min = 25000, .max = 350000 },
293 .vco = { .min = 1760000, .max = 3510000 },
294 .n = { .min = 1, .max = 3 },
295 .m = { .min = 79, .max = 118 },
296 .m1 = { .min = 12, .max = 22 },
297 .m2 = { .min = 5, .max = 9 },
298 .p = { .min = 28, .max = 112 },
299 .p1 = { .min = 2, .max = 8 },
300 .p2 = { .dot_limit = 225000,
301 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 302 .find_pll = intel_g4x_find_best_PLL,
303};
304
305static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 3 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 14, .max = 56 },
313 .p1 = { .min = 2, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 316 .find_pll = intel_g4x_find_best_PLL,
317};
318
273e27ca 319/* LVDS 100mhz refclk limits. */
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 2 },
324 .m = { .min = 79, .max = 126 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
0206e353 328 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 42 },
0206e353 342 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
348static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 349 .dot = { .min = 25000, .max = 350000 },
350 .vco = { .min = 1760000, .max = 3510000},
351 .n = { .min = 1, .max = 2 },
352 .m = { .min = 81, .max = 90 },
353 .m1 = { .min = 12, .max = 22 },
354 .m2 = { .min = 5, .max = 9 },
355 .p = { .min = 10, .max = 20 },
356 .p1 = { .min = 1, .max = 2},
357 .p2 = { .dot_limit = 0,
273e27ca 358 .p2_slow = 10, .p2_fast = 10 },
0206e353 359 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 360};
361
57f350b6
JB		 362u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
363{
364 unsigned long flags;
365 u32 val = 0;
366
367 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
368 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
369 DRM_ERROR("DPIO idle wait timed out\n");
370 goto out_unlock;
371 }
372
373 I915_WRITE(DPIO_REG, reg);
374 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
375 DPIO_BYTE);
376 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
377 DRM_ERROR("DPIO read wait timed out\n");
378 goto out_unlock;
379 }
380 val = I915_READ(DPIO_DATA);
381
382out_unlock:
383 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
384 return val;
385}
386
57f350b6
JB		 387static void vlv_init_dpio(struct drm_device *dev)
388{
389 struct drm_i915_private *dev_priv = dev->dev_private;
390
391 /* Reset the DPIO config */
392 I915_WRITE(DPIO_CTL, 0);
393 POSTING_READ(DPIO_CTL);
394 I915_WRITE(DPIO_CTL, 1);
395 POSTING_READ(DPIO_CTL);
396}
397
618563e3
DV		 398static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
399{
400 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
401 return 1;
402}
403
404static const struct dmi_system_id intel_dual_link_lvds[] = {
405 {
406 .callback = intel_dual_link_lvds_callback,
407 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
408 .matches = {
409 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
410 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
411 },
412 },
413 { } /* terminating entry */
414};
415
b0354385
TI		 416static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
417 unsigned int reg)
418{
419 unsigned int val;
420
121d527a
TI		 421 /* use the module option value if specified */
422 if (i915_lvds_channel_mode > 0)
423 return i915_lvds_channel_mode == 2;
424
618563e3
DV		 425 if (dmi_check_system(intel_dual_link_lvds))
426 return true;
427
b0354385
TI		 428 if (dev_priv->lvds_val)
429 val = dev_priv->lvds_val;
430 else {
431 /* BIOS should set the proper LVDS register value at boot, but
432 * in reality, it doesn't set the value when the lid is closed;
433 * we need to check "the value to be set" in VBT when LVDS
434 * register is uninitialized.
435 */
436 val = I915_READ(reg);
437 if (!(val & ~LVDS_DETECTED))
438 val = dev_priv->bios_lvds_val;
439 dev_priv->lvds_val = val;
440 }
441 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
442}
443
1b894b59
CW		 444static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
445 int refclk)
2c07245f 446{
b91ad0ec
ZW		 447 struct drm_device *dev = crtc->dev;
448 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 449 const intel_limit_t *limit;
b91ad0ec
ZW		 450
451 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 452 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 453 /* LVDS dual channel */
1b894b59 454 if (refclk == 100000)
b91ad0ec
ZW		 455 limit = &intel_limits_ironlake_dual_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_dual_lvds;
458 } else {
1b894b59 459 if (refclk == 100000)
b91ad0ec
ZW		 460 limit = &intel_limits_ironlake_single_lvds_100m;
461 else
462 limit = &intel_limits_ironlake_single_lvds;
463 }
464 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 465 HAS_eDP)
466 limit = &intel_limits_ironlake_display_port;
2c07245f 467 else
b91ad0ec 468 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 469
470 return limit;
471}
472
044c7c41
ML		 473static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
474{
475 struct drm_device *dev = crtc->dev;
476 struct drm_i915_private *dev_priv = dev->dev_private;
477 const intel_limit_t *limit;
478
479 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 480 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 481 /* LVDS with dual channel */
e4b36699 482 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 483 else
484 /* LVDS with dual channel */
e4b36699 485 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 486 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
487 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 488 limit = &intel_limits_g4x_hdmi;
044c7c41 489 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 490 limit = &intel_limits_g4x_sdvo;
0206e353 491 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 492 limit = &intel_limits_g4x_display_port;
044c7c41 493 } else /* The option is for other outputs */
e4b36699 494 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 495
496 return limit;
497}
498
1b894b59 499static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 500{
501 struct drm_device *dev = crtc->dev;
502 const intel_limit_t *limit;
503
bad720ff 504 if (HAS_PCH_SPLIT(dev))
1b894b59 505 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 506 else if (IS_G4X(dev)) {
044c7c41 507 limit = intel_g4x_limit(crtc);
f2b115e6 508 } else if (IS_PINEVIEW(dev)) {
2177832f 509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 510 limit = &intel_limits_pineview_lvds;
2177832f 511 else
f2b115e6 512 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 513 } else if (!IS_GEN2(dev)) {
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i9xx_lvds;
516 else
517 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 518 } else {
519 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 520 limit = &intel_limits_i8xx_lvds;
79e53945 521 else
e4b36699 522 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 523 }
524 return limit;
525}
526
f2b115e6
AJ		 527/* m1 is reserved as 0 in Pineview, n is a ring counter */
528static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 529{
2177832f
SL		 530 clock->m = clock->m2 + 2;
531 clock->p = clock->p1 * clock->p2;
532 clock->vco = refclk * clock->m / clock->n;
533 clock->dot = clock->vco / clock->p;
534}
535
536static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
537{
f2b115e6
AJ		 538 if (IS_PINEVIEW(dev)) {
539 pineview_clock(refclk, clock);
2177832f
SL		 540 return;
541 }
79e53945
JB		 542 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
543 clock->p = clock->p1 * clock->p2;
544 clock->vco = refclk * clock->m / (clock->n + 2);
545 clock->dot = clock->vco / clock->p;
546}
547
79e53945
JB		 548/**
549 * Returns whether any output on the specified pipe is of the specified type
550 */
4ef69c7a 551bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 552{
4ef69c7a
CW		 553 struct drm_device *dev = crtc->dev;
554 struct drm_mode_config *mode_config = &dev->mode_config;
555 struct intel_encoder *encoder;
556
557 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
558 if (encoder->base.crtc == crtc && encoder->type == type)
559 return true;
560
561 return false;
79e53945
JB		 562}
563
7c04d1d9 564#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 565/**
566 * Returns whether the given set of divisors are valid for a given refclk with
567 * the given connectors.
568 */
569
1b894b59
CW		 570static bool intel_PLL_is_valid(struct drm_device *dev,
571 const intel_limit_t *limit,
572 const intel_clock_t *clock)
79e53945 573{
79e53945 574 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 575 INTELPllInvalid("p1 out of range\n");
79e53945 576 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 577 INTELPllInvalid("p out of range\n");
79e53945 578 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 579 INTELPllInvalid("m2 out of range\n");
79e53945 580 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 581 INTELPllInvalid("m1 out of range\n");
f2b115e6 582 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 583 INTELPllInvalid("m1 <= m2\n");
79e53945 584 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 585 INTELPllInvalid("m out of range\n");
79e53945 586 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 587 INTELPllInvalid("n out of range\n");
79e53945 588 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 589 INTELPllInvalid("vco out of range\n");
79e53945
JB		 590 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
591 * connector, etc., rather than just a single range.
592 */
593 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 594 INTELPllInvalid("dot out of range\n");
79e53945
JB		 595
596 return true;
597}
598
d4906093
ML		 599static bool
600intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 601 int target, int refclk, intel_clock_t *match_clock,
602 intel_clock_t *best_clock)
d4906093 603
79e53945
JB		 604{
605 struct drm_device *dev = crtc->dev;
606 struct drm_i915_private *dev_priv = dev->dev_private;
607 intel_clock_t clock;
79e53945
JB		 608 int err = target;
609
bc5e5718 610 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 611 (I915_READ(LVDS)) != 0) {
79e53945
JB		 612 /*
613 * For LVDS, if the panel is on, just rely on its current
614 * settings for dual-channel. We haven't figured out how to
615 * reliably set up different single/dual channel state, if we
616 * even can.
617 */
b0354385 618 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 619 clock.p2 = limit->p2.p2_fast;
620 else
621 clock.p2 = limit->p2.p2_slow;
622 } else {
623 if (target < limit->p2.dot_limit)
624 clock.p2 = limit->p2.p2_slow;
625 else
626 clock.p2 = limit->p2.p2_fast;
627 }
628
0206e353 629 memset(best_clock, 0, sizeof(*best_clock));
79e53945 630
42158660
ZY		 631 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
632 clock.m1++) {
633 for (clock.m2 = limit->m2.min;
634 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 635 /* m1 is always 0 in Pineview */
636 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 637 break;
638 for (clock.n = limit->n.min;
639 clock.n <= limit->n.max; clock.n++) {
640 for (clock.p1 = limit->p1.min;
641 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 642 int this_err;
643
2177832f 644 intel_clock(dev, refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
79e53945 647 continue;
cec2f356
SP		 648 if (match_clock &&
649 clock.p != match_clock->p)
650 continue;
79e53945
JB		 651
652 this_err = abs(clock.dot - target);
653 if (this_err < err) {
654 *best_clock = clock;
655 err = this_err;
656 }
657 }
658 }
659 }
660 }
661
662 return (err != target);
663}
664
d4906093
ML		 665static bool
666intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 667 int target, int refclk, intel_clock_t *match_clock,
668 intel_clock_t *best_clock)
d4906093
ML		 669{
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 intel_clock_t clock;
673 int max_n;
674 bool found;
6ba770dc
AJ		 675 /* approximately equals target * 0.00585 */
676 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 677 found = false;
678
679 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 680 int lvds_reg;
681
c619eed4 682 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 683 lvds_reg = PCH_LVDS;
684 else
685 lvds_reg = LVDS;
686 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 687 LVDS_CLKB_POWER_UP)
688 clock.p2 = limit->p2.p2_fast;
689 else
690 clock.p2 = limit->p2.p2_slow;
691 } else {
692 if (target < limit->p2.dot_limit)
693 clock.p2 = limit->p2.p2_slow;
694 else
695 clock.p2 = limit->p2.p2_fast;
696 }
697
698 memset(best_clock, 0, sizeof(*best_clock));
699 max_n = limit->n.max;
f77f13e2 700 /* based on hardware requirement, prefer smaller n to precision */
d4906093 701 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 702 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 703 for (clock.m1 = limit->m1.max;
704 clock.m1 >= limit->m1.min; clock.m1--) {
705 for (clock.m2 = limit->m2.max;
706 clock.m2 >= limit->m2.min; clock.m2--) {
707 for (clock.p1 = limit->p1.max;
708 clock.p1 >= limit->p1.min; clock.p1--) {
709 int this_err;
710
2177832f 711 intel_clock(dev, refclk, &clock);
1b894b59
CW		 712 if (!intel_PLL_is_valid(dev, limit,
713 &clock))
d4906093 714 continue;
cec2f356
SP		 715 if (match_clock &&
716 clock.p != match_clock->p)
717 continue;
1b894b59
CW		 718
719 this_err = abs(clock.dot - target);
d4906093
ML		 720 if (this_err < err_most) {
721 *best_clock = clock;
722 err_most = this_err;
723 max_n = clock.n;
724 found = true;
725 }
726 }
727 }
728 }
729 }
2c07245f
ZW		 730 return found;
731}
732
5eb08b69 733static bool
f2b115e6 734intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 735 int target, int refclk, intel_clock_t *match_clock,
736 intel_clock_t *best_clock)
5eb08b69
ZW		 737{
738 struct drm_device *dev = crtc->dev;
739 intel_clock_t clock;
4547668a 740
5eb08b69
ZW		 741 if (target < 200000) {
742 clock.n = 1;
743 clock.p1 = 2;
744 clock.p2 = 10;
745 clock.m1 = 12;
746 clock.m2 = 9;
747 } else {
748 clock.n = 2;
749 clock.p1 = 1;
750 clock.p2 = 10;
751 clock.m1 = 14;
752 clock.m2 = 8;
753 }
754 intel_clock(dev, refclk, &clock);
755 memcpy(best_clock, &clock, sizeof(intel_clock_t));
756 return true;
757}
758
a4fc5ed6
KP		 759/* DisplayPort has only two frequencies, 162MHz and 270MHz */
760static bool
761intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
a4fc5ed6 764{
5eddb70b
CW		 765 intel_clock_t clock;
766 if (target < 200000) {
767 clock.p1 = 2;
768 clock.p2 = 10;
769 clock.n = 2;
770 clock.m1 = 23;
771 clock.m2 = 8;
772 } else {
773 clock.p1 = 1;
774 clock.p2 = 10;
775 clock.n = 1;
776 clock.m1 = 14;
777 clock.m2 = 2;
778 }
779 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
780 clock.p = (clock.p1 * clock.p2);
781 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
782 clock.vco = 0;
783 memcpy(best_clock, &clock, sizeof(intel_clock_t));
784 return true;
a4fc5ed6
KP		 785}
786
a928d536
PZ		 787static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
788{
789 struct drm_i915_private *dev_priv = dev->dev_private;
790 u32 frame, frame_reg = PIPEFRAME(pipe);
791
792 frame = I915_READ(frame_reg);
793
794 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
795 DRM_DEBUG_KMS("vblank wait timed out\n");
796}
797
9d0498a2
JB		 798/**
799 * intel_wait_for_vblank - wait for vblank on a given pipe
800 * @dev: drm device
801 * @pipe: pipe to wait for
802 *
803 * Wait for vblank to occur on a given pipe. Needed for various bits of
804 * mode setting code.
805 */
806void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 807{
9d0498a2 808 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 809 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 810
a928d536
PZ		 811 if (INTEL_INFO(dev)->gen >= 5) {
812 ironlake_wait_for_vblank(dev, pipe);
813 return;
814 }
815
300387c0
CW		 816 /* Clear existing vblank status. Note this will clear any other
817 * sticky status fields as well.
818 *
819 * This races with i915_driver_irq_handler() with the result
820 * that either function could miss a vblank event. Here it is not
821 * fatal, as we will either wait upon the next vblank interrupt or
822 * timeout. Generally speaking intel_wait_for_vblank() is only
823 * called during modeset at which time the GPU should be idle and
824 * should *not* be performing page flips and thus not waiting on
825 * vblanks...
826 * Currently, the result of us stealing a vblank from the irq
827 * handler is that a single frame will be skipped during swapbuffers.
828 */
829 I915_WRITE(pipestat_reg,
830 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
831
9d0498a2 832 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 833 if (wait_for(I915_READ(pipestat_reg) &
834 PIPE_VBLANK_INTERRUPT_STATUS,
835 50))
9d0498a2
JB		 836 DRM_DEBUG_KMS("vblank wait timed out\n");
837}
838
ab7ad7f6
KP		 839/*
840 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 841 * @dev: drm device
842 * @pipe: pipe to wait for
843 *
844 * After disabling a pipe, we can't wait for vblank in the usual way,
845 * spinning on the vblank interrupt status bit, since we won't actually
846 * see an interrupt when the pipe is disabled.
847 *
ab7ad7f6
KP		 848 * On Gen4 and above:
849 * wait for the pipe register state bit to turn off
850 *
851 * Otherwise:
852 * wait for the display line value to settle (it usually
853 * ends up stopping at the start of the next frame).
58e10eb9 854 *
9d0498a2 855 */
58e10eb9 856void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 857{
858 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 859
860 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 861 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 862
863 /* Wait for the Pipe State to go off */
58e10eb9
CW		 864 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
865 100))
ab7ad7f6
KP		 866 DRM_DEBUG_KMS("pipe_off wait timed out\n");
867 } else {
837ba00f 868 u32 last_line, line_mask;
58e10eb9 869 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 870 unsigned long timeout = jiffies + msecs_to_jiffies(100);
871
837ba00f
PZ		 872 if (IS_GEN2(dev))
873 line_mask = DSL_LINEMASK_GEN2;
874 else
875 line_mask = DSL_LINEMASK_GEN3;
876
ab7ad7f6
KP		 877 /* Wait for the display line to settle */
878 do {
837ba00f 879 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 880 mdelay(5);
837ba00f 881 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 882 time_after(timeout, jiffies));
883 if (time_after(jiffies, timeout))
884 DRM_DEBUG_KMS("pipe_off wait timed out\n");
885 }
79e53945
JB		 886}
887
b24e7179
JB		 888static const char *state_string(bool enabled)
889{
890 return enabled ? "on" : "off";
891}
892
893/* Only for pre-ILK configs */
894static void assert_pll(struct drm_i915_private *dev_priv,
895 enum pipe pipe, bool state)
896{
897 int reg;
898 u32 val;
899 bool cur_state;
900
901 reg = DPLL(pipe);
902 val = I915_READ(reg);
903 cur_state = !!(val & DPLL_VCO_ENABLE);
904 WARN(cur_state != state,
905 "PLL state assertion failure (expected %s, current %s)\n",
906 state_string(state), state_string(cur_state));
907}
908#define assert_pll_enabled(d, p) assert_pll(d, p, true)
909#define assert_pll_disabled(d, p) assert_pll(d, p, false)
910
040484af
JB		 911/* For ILK+ */
912static void assert_pch_pll(struct drm_i915_private *dev_priv,
ee7b9f93 913 struct intel_crtc *intel_crtc, bool state)
040484af
JB		 914{
915 int reg;
916 u32 val;
917 bool cur_state;
918
ee7b9f93
JB		 919 if (!intel_crtc->pch_pll) {
920 WARN(1, "asserting PCH PLL enabled with no PLL\n");
921 return;
922 }
923
d3ccbe86
JB		 924 if (HAS_PCH_CPT(dev_priv->dev)) {
925 u32 pch_dpll;
926
927 pch_dpll = I915_READ(PCH_DPLL_SEL);
928
929 /* Make sure the selected PLL is enabled to the transcoder */
ee7b9f93
JB		 930 WARN(!((pch_dpll >> (4 * intel_crtc->pipe)) & 8),
931 "transcoder %d PLL not enabled\n", intel_crtc->pipe);
d3ccbe86
JB		 932 }
933
ee7b9f93 934 reg = intel_crtc->pch_pll->pll_reg;
040484af
JB		 935 val = I915_READ(reg);
936 cur_state = !!(val & DPLL_VCO_ENABLE);
937 WARN(cur_state != state,
938 "PCH PLL state assertion failure (expected %s, current %s)\n",
939 state_string(state), state_string(cur_state));
940}
941#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
942#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
943
944static void assert_fdi_tx(struct drm_i915_private *dev_priv,
945 enum pipe pipe, bool state)
946{
947 int reg;
948 u32 val;
949 bool cur_state;
950
951 reg = FDI_TX_CTL(pipe);
952 val = I915_READ(reg);
953 cur_state = !!(val & FDI_TX_ENABLE);
954 WARN(cur_state != state,
955 "FDI TX state assertion failure (expected %s, current %s)\n",
956 state_string(state), state_string(cur_state));
957}
958#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
959#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
960
961static void assert_fdi_rx(struct drm_i915_private *dev_priv,
962 enum pipe pipe, bool state)
963{
964 int reg;
965 u32 val;
966 bool cur_state;
967
968 reg = FDI_RX_CTL(pipe);
969 val = I915_READ(reg);
970 cur_state = !!(val & FDI_RX_ENABLE);
971 WARN(cur_state != state,
972 "FDI RX state assertion failure (expected %s, current %s)\n",
973 state_string(state), state_string(cur_state));
974}
975#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
976#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
977
978static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
979 enum pipe pipe)
980{
981 int reg;
982 u32 val;
983
984 /* ILK FDI PLL is always enabled */
985 if (dev_priv->info->gen == 5)
986 return;
987
988 reg = FDI_TX_CTL(pipe);
989 val = I915_READ(reg);
990 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
991}
992
993static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
994 enum pipe pipe)
995{
996 int reg;
997 u32 val;
998
999 reg = FDI_RX_CTL(pipe);
1000 val = I915_READ(reg);
1001 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1002}
1003
ea0760cf
JB		 1004static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1005 enum pipe pipe)
1006{
1007 int pp_reg, lvds_reg;
1008 u32 val;
1009 enum pipe panel_pipe = PIPE_A;
0de3b485 1010 bool locked = true;
ea0760cf
JB		 1011
1012 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1013 pp_reg = PCH_PP_CONTROL;
1014 lvds_reg = PCH_LVDS;
1015 } else {
1016 pp_reg = PP_CONTROL;
1017 lvds_reg = LVDS;
1018 }
1019
1020 val = I915_READ(pp_reg);
1021 if (!(val & PANEL_POWER_ON) ||
1022 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1023 locked = false;
1024
1025 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1026 panel_pipe = PIPE_B;
1027
1028 WARN(panel_pipe == pipe && locked,
1029 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1030 pipe_name(pipe));
ea0760cf
JB		 1031}
1032
b840d907
JB		 1033void assert_pipe(struct drm_i915_private *dev_priv,
1034 enum pipe pipe, bool state)
b24e7179
JB		 1035{
1036 int reg;
1037 u32 val;
63d7bbe9 1038 bool cur_state;
b24e7179 1039
8e636784
DV		 1040 /* if we need the pipe A quirk it must be always on */
1041 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1042 state = true;
1043
b24e7179
JB		 1044 reg = PIPECONF(pipe);
1045 val = I915_READ(reg);
63d7bbe9
JB		 1046 cur_state = !!(val & PIPECONF_ENABLE);
1047 WARN(cur_state != state,
1048 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1049 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1050}
1051
931872fc
CW		 1052static void assert_plane(struct drm_i915_private *dev_priv,
1053 enum plane plane, bool state)
b24e7179
JB		 1054{
1055 int reg;
1056 u32 val;
931872fc 1057 bool cur_state;
b24e7179
JB		 1058
1059 reg = DSPCNTR(plane);
1060 val = I915_READ(reg);
931872fc
CW		 1061 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1062 WARN(cur_state != state,
1063 "plane %c assertion failure (expected %s, current %s)\n",
1064 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1065}
1066
931872fc
CW		 1067#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1068#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1069
b24e7179
JB		 1070static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1071 enum pipe pipe)
1072{
1073 int reg, i;
1074 u32 val;
1075 int cur_pipe;
1076
19ec1358 1077 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1078 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1079 reg = DSPCNTR(pipe);
1080 val = I915_READ(reg);
1081 WARN((val & DISPLAY_PLANE_ENABLE),
1082 "plane %c assertion failure, should be disabled but not\n",
1083 plane_name(pipe));
19ec1358 1084 return;
28c05794 1085 }
19ec1358 1086
b24e7179
JB		 1087 /* Need to check both planes against the pipe */
1088 for (i = 0; i < 2; i++) {
1089 reg = DSPCNTR(i);
1090 val = I915_READ(reg);
1091 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1092 DISPPLANE_SEL_PIPE_SHIFT;
1093 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1094 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1095 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1096 }
1097}
1098
92f2584a
JB		 1099static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1100{
1101 u32 val;
1102 bool enabled;
1103
1104 val = I915_READ(PCH_DREF_CONTROL);
1105 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1106 DREF_SUPERSPREAD_SOURCE_MASK));
1107 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1108}
1109
1110static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1111 enum pipe pipe)
1112{
1113 int reg;
1114 u32 val;
1115 bool enabled;
1116
1117 reg = TRANSCONF(pipe);
1118 val = I915_READ(reg);
1119 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1120 WARN(enabled,
1121 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1122 pipe_name(pipe));
92f2584a
JB		 1123}
1124
4e634389
KP		 1125static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1127{
1128 if ((val & DP_PORT_EN) == 0)
1129 return false;
1130
1131 if (HAS_PCH_CPT(dev_priv->dev)) {
1132 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1133 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1134 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1135 return false;
1136 } else {
1137 if ((val & DP_PIPE_MASK) != (pipe << 30))
1138 return false;
1139 }
1140 return true;
1141}
1142
1519b995
KP		 1143static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1144 enum pipe pipe, u32 val)
1145{
1146 if ((val & PORT_ENABLE) == 0)
1147 return false;
1148
1149 if (HAS_PCH_CPT(dev_priv->dev)) {
1150 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1151 return false;
1152 } else {
1153 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1154 return false;
1155 }
1156 return true;
1157}
1158
1159static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1160 enum pipe pipe, u32 val)
1161{
1162 if ((val & LVDS_PORT_EN) == 0)
1163 return false;
1164
1165 if (HAS_PCH_CPT(dev_priv->dev)) {
1166 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1167 return false;
1168 } else {
1169 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1170 return false;
1171 }
1172 return true;
1173}
1174
1175static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1176 enum pipe pipe, u32 val)
1177{
1178 if ((val & ADPA_DAC_ENABLE) == 0)
1179 return false;
1180 if (HAS_PCH_CPT(dev_priv->dev)) {
1181 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1182 return false;
1183 } else {
1184 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1185 return false;
1186 }
1187 return true;
1188}
1189
291906f1 1190static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1191 enum pipe pipe, int reg, u32 port_sel)
291906f1 1192{
47a05eca 1193 u32 val = I915_READ(reg);
4e634389 1194 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1195 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1196 reg, pipe_name(pipe));
291906f1
JB		 1197}
1198
1199static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1200 enum pipe pipe, int reg)
1201{
47a05eca 1202 u32 val = I915_READ(reg);
1519b995 1203 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1204 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1205 reg, pipe_name(pipe));
291906f1
JB		 1206}
1207
1208static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1209 enum pipe pipe)
1210{
1211 int reg;
1212 u32 val;
291906f1 1213
f0575e92
KP		 1214 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1215 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1216 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1217
1218 reg = PCH_ADPA;
1219 val = I915_READ(reg);
1519b995 1220 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1221 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1222 pipe_name(pipe));
291906f1
JB		 1223
1224 reg = PCH_LVDS;
1225 val = I915_READ(reg);
1519b995 1226 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1227 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1228 pipe_name(pipe));
291906f1
JB		 1229
1230 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1231 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1232 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1233}
1234
63d7bbe9
JB		 1235/**
1236 * intel_enable_pll - enable a PLL
1237 * @dev_priv: i915 private structure
1238 * @pipe: pipe PLL to enable
1239 *
1240 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1241 * make sure the PLL reg is writable first though, since the panel write
1242 * protect mechanism may be enabled.
1243 *
1244 * Note! This is for pre-ILK only.
1245 */
1246static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1247{
1248 int reg;
1249 u32 val;
1250
1251 /* No really, not for ILK+ */
1252 BUG_ON(dev_priv->info->gen >= 5);
1253
1254 /* PLL is protected by panel, make sure we can write it */
1255 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1256 assert_panel_unlocked(dev_priv, pipe);
1257
1258 reg = DPLL(pipe);
1259 val = I915_READ(reg);
1260 val |= DPLL_VCO_ENABLE;
1261
1262 /* We do this three times for luck */
1263 I915_WRITE(reg, val);
1264 POSTING_READ(reg);
1265 udelay(150); /* wait for warmup */
1266 I915_WRITE(reg, val);
1267 POSTING_READ(reg);
1268 udelay(150); /* wait for warmup */
1269 I915_WRITE(reg, val);
1270 POSTING_READ(reg);
1271 udelay(150); /* wait for warmup */
1272}
1273
1274/**
1275 * intel_disable_pll - disable a PLL
1276 * @dev_priv: i915 private structure
1277 * @pipe: pipe PLL to disable
1278 *
1279 * Disable the PLL for @pipe, making sure the pipe is off first.
1280 *
1281 * Note! This is for pre-ILK only.
1282 */
1283static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1284{
1285 int reg;
1286 u32 val;
1287
1288 /* Don't disable pipe A or pipe A PLLs if needed */
1289 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1290 return;
1291
1292 /* Make sure the pipe isn't still relying on us */
1293 assert_pipe_disabled(dev_priv, pipe);
1294
1295 reg = DPLL(pipe);
1296 val = I915_READ(reg);
1297 val &= ~DPLL_VCO_ENABLE;
1298 I915_WRITE(reg, val);
1299 POSTING_READ(reg);
1300}
1301
a416edef
ED		 1302/* SBI access */
1303static void
1304intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1305{
1306 unsigned long flags;
1307
1308 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1309 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1310 100)) {
1311 DRM_ERROR("timeout waiting for SBI to become ready\n");
1312 goto out_unlock;
1313 }
1314
1315 I915_WRITE(SBI_ADDR,
1316 (reg << 16));
1317 I915_WRITE(SBI_DATA,
1318 value);
1319 I915_WRITE(SBI_CTL_STAT,
1320 SBI_BUSY |
1321 SBI_CTL_OP_CRWR);
1322
1323 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1324 100)) {
1325 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1326 goto out_unlock;
1327 }
1328
1329out_unlock:
1330 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1331}
1332
1333static u32
1334intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1335{
1336 unsigned long flags;
1337 u32 value;
1338
1339 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1340 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1341 100)) {
1342 DRM_ERROR("timeout waiting for SBI to become ready\n");
1343 goto out_unlock;
1344 }
1345
1346 I915_WRITE(SBI_ADDR,
1347 (reg << 16));
1348 I915_WRITE(SBI_CTL_STAT,
1349 SBI_BUSY |
1350 SBI_CTL_OP_CRRD);
1351
1352 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1353 100)) {
1354 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1355 goto out_unlock;
1356 }
1357
1358 value = I915_READ(SBI_DATA);
1359
1360out_unlock:
1361 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1362 return value;
1363}
1364
92f2584a
JB		 1365/**
1366 * intel_enable_pch_pll - enable PCH PLL
1367 * @dev_priv: i915 private structure
1368 * @pipe: pipe PLL to enable
1369 *
1370 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1371 * drives the transcoder clock.
1372 */
ee7b9f93 1373static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1374{
ee7b9f93
JB		 1375 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1376 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a
JB		 1377 int reg;
1378 u32 val;
1379
1380 /* PCH only available on ILK+ */
1381 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1382 BUG_ON(pll == NULL);
1383 BUG_ON(pll->refcount == 0);
1384
1385 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1386 pll->pll_reg, pll->active, pll->on,
1387 intel_crtc->base.base.id);
92f2584a
JB		 1388
1389 /* PCH refclock must be enabled first */
1390 assert_pch_refclk_enabled(dev_priv);
1391
ee7b9f93
JB		 1392 if (pll->active++ && pll->on) {
1393 assert_pch_pll_enabled(dev_priv, intel_crtc);
1394 return;
1395 }
1396
1397 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1398
1399 reg = pll->pll_reg;
92f2584a
JB		 1400 val = I915_READ(reg);
1401 val |= DPLL_VCO_ENABLE;
1402 I915_WRITE(reg, val);
1403 POSTING_READ(reg);
1404 udelay(200);
ee7b9f93
JB		 1405
1406 pll->on = true;
92f2584a
JB		 1407}
1408
ee7b9f93 1409static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1410{
ee7b9f93
JB		 1411 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1412 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1413 int reg;
ee7b9f93 1414 u32 val;
4c609cb8 1415
92f2584a
JB		 1416 /* PCH only available on ILK+ */
1417 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1418 if (pll == NULL)
1419 return;
92f2584a 1420
ee7b9f93 1421 BUG_ON(pll->refcount == 0);
7a419866 1422
ee7b9f93
JB		 1423 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1424 pll->pll_reg, pll->active, pll->on,
1425 intel_crtc->base.base.id);
7a419866 1426
ee7b9f93
JB		 1427 BUG_ON(pll->active == 0);
1428 if (--pll->active) {
1429 assert_pch_pll_enabled(dev_priv, intel_crtc);
7a419866 1430 return;
ee7b9f93
JB		 1431 }
1432
1433 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1434
1435 /* Make sure transcoder isn't still depending on us */
1436 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1437
ee7b9f93 1438 reg = pll->pll_reg;
92f2584a
JB		 1439 val = I915_READ(reg);
1440 val &= ~DPLL_VCO_ENABLE;
1441 I915_WRITE(reg, val);
1442 POSTING_READ(reg);
1443 udelay(200);
ee7b9f93
JB		 1444
1445 pll->on = false;
92f2584a
JB		 1446}
1447
040484af
JB		 1448static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1449 enum pipe pipe)
1450{
1451 int reg;
5f7f726d 1452 u32 val, pipeconf_val;
7c26e5c6 1453 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1454
1455 /* PCH only available on ILK+ */
1456 BUG_ON(dev_priv->info->gen < 5);
1457
1458 /* Make sure PCH DPLL is enabled */
ee7b9f93 1459 assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
040484af
JB		 1460
1461 /* FDI must be feeding us bits for PCH ports */
1462 assert_fdi_tx_enabled(dev_priv, pipe);
1463 assert_fdi_rx_enabled(dev_priv, pipe);
1464
1465 reg = TRANSCONF(pipe);
1466 val = I915_READ(reg);
5f7f726d 1467 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1468
1469 if (HAS_PCH_IBX(dev_priv->dev)) {
1470 /*
1471 * make the BPC in transcoder be consistent with
1472 * that in pipeconf reg.
1473 */
1474 val &= ~PIPE_BPC_MASK;
5f7f726d 1475 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1476 }
5f7f726d
PZ		 1477
1478 val &= ~TRANS_INTERLACE_MASK;
1479 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1480 if (HAS_PCH_IBX(dev_priv->dev) &&
1481 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1482 val |= TRANS_LEGACY_INTERLACED_ILK;
1483 else
1484 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1485 else
1486 val |= TRANS_PROGRESSIVE;
1487
040484af
JB		 1488 I915_WRITE(reg, val | TRANS_ENABLE);
1489 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1490 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1491}
1492
1493static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1494 enum pipe pipe)
1495{
1496 int reg;
1497 u32 val;
1498
1499 /* FDI relies on the transcoder */
1500 assert_fdi_tx_disabled(dev_priv, pipe);
1501 assert_fdi_rx_disabled(dev_priv, pipe);
1502
291906f1
JB		 1503 /* Ports must be off as well */
1504 assert_pch_ports_disabled(dev_priv, pipe);
1505
040484af
JB		 1506 reg = TRANSCONF(pipe);
1507 val = I915_READ(reg);
1508 val &= ~TRANS_ENABLE;
1509 I915_WRITE(reg, val);
1510 /* wait for PCH transcoder off, transcoder state */
1511 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1512 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1513}
1514
b24e7179 1515/**
309cfea8 1516 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1517 * @dev_priv: i915 private structure
1518 * @pipe: pipe to enable
040484af 1519 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1520 *
1521 * Enable @pipe, making sure that various hardware specific requirements
1522 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1523 *
1524 * @pipe should be %PIPE_A or %PIPE_B.
1525 *
1526 * Will wait until the pipe is actually running (i.e. first vblank) before
1527 * returning.
1528 */
040484af
JB		 1529static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1530 bool pch_port)
b24e7179
JB		 1531{
1532 int reg;
1533 u32 val;
1534
1535 /*
1536 * A pipe without a PLL won't actually be able to drive bits from
1537 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1538 * need the check.
1539 */
1540 if (!HAS_PCH_SPLIT(dev_priv->dev))
1541 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1542 else {
1543 if (pch_port) {
1544 /* if driving the PCH, we need FDI enabled */
1545 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1546 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1547 }
1548 /* FIXME: assert CPU port conditions for SNB+ */
1549 }
b24e7179
JB		 1550
1551 reg = PIPECONF(pipe);
1552 val = I915_READ(reg);
00d70b15
CW		 1553 if (val & PIPECONF_ENABLE)
1554 return;
1555
1556 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1557 intel_wait_for_vblank(dev_priv->dev, pipe);
1558}
1559
1560/**
309cfea8 1561 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1562 * @dev_priv: i915 private structure
1563 * @pipe: pipe to disable
1564 *
1565 * Disable @pipe, making sure that various hardware specific requirements
1566 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1567 *
1568 * @pipe should be %PIPE_A or %PIPE_B.
1569 *
1570 * Will wait until the pipe has shut down before returning.
1571 */
1572static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1573 enum pipe pipe)
1574{
1575 int reg;
1576 u32 val;
1577
1578 /*
1579 * Make sure planes won't keep trying to pump pixels to us,
1580 * or we might hang the display.
1581 */
1582 assert_planes_disabled(dev_priv, pipe);
1583
1584 /* Don't disable pipe A or pipe A PLLs if needed */
1585 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1586 return;
1587
1588 reg = PIPECONF(pipe);
1589 val = I915_READ(reg);
00d70b15
CW		 1590 if ((val & PIPECONF_ENABLE) == 0)
1591 return;
1592
1593 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1594 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1595}
1596
d74362c9
KP		 1597/*
1598 * Plane regs are double buffered, going from enabled->disabled needs a
1599 * trigger in order to latch. The display address reg provides this.
1600 */
6f1d69b0 1601void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1602 enum plane plane)
1603{
1604 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1605 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1606}
1607
b24e7179
JB		 1608/**
1609 * intel_enable_plane - enable a display plane on a given pipe
1610 * @dev_priv: i915 private structure
1611 * @plane: plane to enable
1612 * @pipe: pipe being fed
1613 *
1614 * Enable @plane on @pipe, making sure that @pipe is running first.
1615 */
1616static void intel_enable_plane(struct drm_i915_private *dev_priv,
1617 enum plane plane, enum pipe pipe)
1618{
1619 int reg;
1620 u32 val;
1621
1622 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1623 assert_pipe_enabled(dev_priv, pipe);
1624
1625 reg = DSPCNTR(plane);
1626 val = I915_READ(reg);
00d70b15
CW		 1627 if (val & DISPLAY_PLANE_ENABLE)
1628 return;
1629
1630 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1631 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1632 intel_wait_for_vblank(dev_priv->dev, pipe);
1633}
1634
b24e7179
JB		 1635/**
1636 * intel_disable_plane - disable a display plane
1637 * @dev_priv: i915 private structure
1638 * @plane: plane to disable
1639 * @pipe: pipe consuming the data
1640 *
1641 * Disable @plane; should be an independent operation.
1642 */
1643static void intel_disable_plane(struct drm_i915_private *dev_priv,
1644 enum plane plane, enum pipe pipe)
1645{
1646 int reg;
1647 u32 val;
1648
1649 reg = DSPCNTR(plane);
1650 val = I915_READ(reg);
00d70b15
CW		 1651 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1652 return;
1653
1654 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1655 intel_flush_display_plane(dev_priv, plane);
1656 intel_wait_for_vblank(dev_priv->dev, pipe);
1657}
1658
47a05eca 1659static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1660 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1661{
1662 u32 val = I915_READ(reg);
4e634389 1663 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1664 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1665 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1666 }
47a05eca
JB		 1667}
1668
1669static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1670 enum pipe pipe, int reg)
1671{
1672 u32 val = I915_READ(reg);
1519b995 1673 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1674 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1675 reg, pipe);
47a05eca 1676 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1677 }
47a05eca
JB		 1678}
1679
1680/* Disable any ports connected to this transcoder */
1681static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1682 enum pipe pipe)
1683{
1684 u32 reg, val;
1685
1686 val = I915_READ(PCH_PP_CONTROL);
1687 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1688
f0575e92
KP		 1689 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1690 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1691 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1692
1693 reg = PCH_ADPA;
1694 val = I915_READ(reg);
1519b995 1695 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1696 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1697
1698 reg = PCH_LVDS;
1699 val = I915_READ(reg);
1519b995
KP		 1700 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1701 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1702 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1703 POSTING_READ(reg);
1704 udelay(100);
1705 }
1706
1707 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1708 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1709 disable_pch_hdmi(dev_priv, pipe, HDMID);
1710}
1711
127bd2ac 1712int
48b956c5 1713intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1714 struct drm_i915_gem_object *obj,
919926ae 1715 struct intel_ring_buffer *pipelined)
6b95a207 1716{
ce453d81 1717 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1718 u32 alignment;
1719 int ret;
1720
05394f39 1721 switch (obj->tiling_mode) {
6b95a207 1722 case I915_TILING_NONE:
534843da
CW		 1723 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1724 alignment = 128 * 1024;
a6c45cf0 1725 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1726 alignment = 4 * 1024;
1727 else
1728 alignment = 64 * 1024;
6b95a207
KH		 1729 break;
1730 case I915_TILING_X:
1731 /* pin() will align the object as required by fence */
1732 alignment = 0;
1733 break;
1734 case I915_TILING_Y:
1735 /* FIXME: Is this true? */
1736 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1737 return -EINVAL;
1738 default:
1739 BUG();
1740 }
1741
ce453d81 1742 dev_priv->mm.interruptible = false;
2da3b9b9 1743 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1744 if (ret)
ce453d81 1745 goto err_interruptible;
6b95a207
KH		 1746
1747 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1748 * fence, whereas 965+ only requires a fence if using
1749 * framebuffer compression. For simplicity, we always install
1750 * a fence as the cost is not that onerous.
1751 */
06d98131 1752 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1753 if (ret)
1754 goto err_unpin;
1690e1eb 1755
9a5a53b3 1756 i915_gem_object_pin_fence(obj);
6b95a207 1757
ce453d81 1758 dev_priv->mm.interruptible = true;
6b95a207 1759 return 0;
48b956c5
CW		 1760
1761err_unpin:
1762 i915_gem_object_unpin(obj);
ce453d81
CW		 1763err_interruptible:
1764 dev_priv->mm.interruptible = true;
48b956c5 1765 return ret;
6b95a207
KH		 1766}
1767
1690e1eb
CW		 1768void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1769{
1770 i915_gem_object_unpin_fence(obj);
1771 i915_gem_object_unpin(obj);
1772}
1773
17638cd6
JB		 1774static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1775 int x, int y)
81255565
JB		 1776{
1777 struct drm_device *dev = crtc->dev;
1778 struct drm_i915_private *dev_priv = dev->dev_private;
1779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1780 struct intel_framebuffer *intel_fb;
05394f39 1781 struct drm_i915_gem_object *obj;
81255565
JB		 1782 int plane = intel_crtc->plane;
1783 unsigned long Start, Offset;
81255565 1784 u32 dspcntr;
5eddb70b 1785 u32 reg;
81255565
JB		 1786
1787 switch (plane) {
1788 case 0:
1789 case 1:
1790 break;
1791 default:
1792 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1793 return -EINVAL;
1794 }
1795
1796 intel_fb = to_intel_framebuffer(fb);
1797 obj = intel_fb->obj;
81255565 1798
5eddb70b
CW		 1799 reg = DSPCNTR(plane);
1800 dspcntr = I915_READ(reg);
81255565
JB		 1801 /* Mask out pixel format bits in case we change it */
1802 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1803 switch (fb->bits_per_pixel) {
1804 case 8:
1805 dspcntr |= DISPPLANE_8BPP;
1806 break;
1807 case 16:
1808 if (fb->depth == 15)
1809 dspcntr |= DISPPLANE_15_16BPP;
1810 else
1811 dspcntr |= DISPPLANE_16BPP;
1812 break;
1813 case 24:
1814 case 32:
1815 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1816 break;
1817 default:
17638cd6 1818 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 1819 return -EINVAL;
1820 }
a6c45cf0 1821 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1822 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1823 dspcntr |= DISPPLANE_TILED;
1824 else
1825 dspcntr &= ~DISPPLANE_TILED;
1826 }
1827
5eddb70b 1828 I915_WRITE(reg, dspcntr);
81255565 1829
05394f39 1830 Start = obj->gtt_offset;
01f2c773 1831 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1832
4e6cfefc 1833 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 1834 Start, Offset, x, y, fb->pitches[0]);
1835 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1836 if (INTEL_INFO(dev)->gen >= 4) {
446f2545 1837 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
5eddb70b
CW		 1838 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1839 I915_WRITE(DSPADDR(plane), Offset);
1840 } else
1841 I915_WRITE(DSPADDR(plane), Start + Offset);
1842 POSTING_READ(reg);
81255565 1843
17638cd6
JB		 1844 return 0;
1845}
1846
1847static int ironlake_update_plane(struct drm_crtc *crtc,
1848 struct drm_framebuffer *fb, int x, int y)
1849{
1850 struct drm_device *dev = crtc->dev;
1851 struct drm_i915_private *dev_priv = dev->dev_private;
1852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1853 struct intel_framebuffer *intel_fb;
1854 struct drm_i915_gem_object *obj;
1855 int plane = intel_crtc->plane;
1856 unsigned long Start, Offset;
1857 u32 dspcntr;
1858 u32 reg;
1859
1860 switch (plane) {
1861 case 0:
1862 case 1:
27f8227b 1863 case 2:
17638cd6
JB		 1864 break;
1865 default:
1866 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1867 return -EINVAL;
1868 }
1869
1870 intel_fb = to_intel_framebuffer(fb);
1871 obj = intel_fb->obj;
1872
1873 reg = DSPCNTR(plane);
1874 dspcntr = I915_READ(reg);
1875 /* Mask out pixel format bits in case we change it */
1876 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1877 switch (fb->bits_per_pixel) {
1878 case 8:
1879 dspcntr |= DISPPLANE_8BPP;
1880 break;
1881 case 16:
1882 if (fb->depth != 16)
1883 return -EINVAL;
1884
1885 dspcntr |= DISPPLANE_16BPP;
1886 break;
1887 case 24:
1888 case 32:
1889 if (fb->depth == 24)
1890 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1891 else if (fb->depth == 30)
1892 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1893 else
1894 return -EINVAL;
1895 break;
1896 default:
1897 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1898 return -EINVAL;
1899 }
1900
1901 if (obj->tiling_mode != I915_TILING_NONE)
1902 dspcntr |= DISPPLANE_TILED;
1903 else
1904 dspcntr &= ~DISPPLANE_TILED;
1905
1906 /* must disable */
1907 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1908
1909 I915_WRITE(reg, dspcntr);
1910
1911 Start = obj->gtt_offset;
01f2c773 1912 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 1913
1914 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 1915 Start, Offset, x, y, fb->pitches[0]);
1916 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
446f2545 1917 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
17638cd6
JB		 1918 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1919 I915_WRITE(DSPADDR(plane), Offset);
1920 POSTING_READ(reg);
1921
1922 return 0;
1923}
1924
1925/* Assume fb object is pinned & idle & fenced and just update base pointers */
1926static int
1927intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1928 int x, int y, enum mode_set_atomic state)
1929{
1930 struct drm_device *dev = crtc->dev;
1931 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 1932
6b8e6ed0
CW		 1933 if (dev_priv->display.disable_fbc)
1934 dev_priv->display.disable_fbc(dev);
3dec0095 1935 intel_increase_pllclock(crtc);
81255565 1936
6b8e6ed0 1937 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 1938}
1939
14667a4b
CW		 1940static int
1941intel_finish_fb(struct drm_framebuffer *old_fb)
1942{
1943 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1944 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1945 bool was_interruptible = dev_priv->mm.interruptible;
1946 int ret;
1947
1948 wait_event(dev_priv->pending_flip_queue,
1949 atomic_read(&dev_priv->mm.wedged) ||
1950 atomic_read(&obj->pending_flip) == 0);
1951
1952 /* Big Hammer, we also need to ensure that any pending
1953 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1954 * current scanout is retired before unpinning the old
1955 * framebuffer.
1956 *
1957 * This should only fail upon a hung GPU, in which case we
1958 * can safely continue.
1959 */
1960 dev_priv->mm.interruptible = false;
1961 ret = i915_gem_object_finish_gpu(obj);
1962 dev_priv->mm.interruptible = was_interruptible;
1963
1964 return ret;
1965}
1966
5c3b82e2 1967static int
3c4fdcfb
KH		 1968intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1969 struct drm_framebuffer *old_fb)
79e53945
JB		 1970{
1971 struct drm_device *dev = crtc->dev;
6b8e6ed0 1972 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 1973 struct drm_i915_master_private *master_priv;
1974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 1975 int ret;
79e53945
JB		 1976
1977 /* no fb bound */
1978 if (!crtc->fb) {
a5071c2f 1979 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 1980 return 0;
1981 }
1982
5826eca5
ED		 1983 if(intel_crtc->plane > dev_priv->num_pipe) {
1984 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
1985 intel_crtc->plane,
1986 dev_priv->num_pipe);
5c3b82e2 1987 return -EINVAL;
79e53945
JB		 1988 }
1989
5c3b82e2 1990 mutex_lock(&dev->struct_mutex);
265db958
CW		 1991 ret = intel_pin_and_fence_fb_obj(dev,
1992 to_intel_framebuffer(crtc->fb)->obj,
919926ae 1993 NULL);
5c3b82e2
CW		 1994 if (ret != 0) {
1995 mutex_unlock(&dev->struct_mutex);
a5071c2f 1996 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 1997 return ret;
1998 }
79e53945 1999
14667a4b
CW		 2000 if (old_fb)
2001 intel_finish_fb(old_fb);
265db958 2002
6b8e6ed0 2003 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
4e6cfefc 2004 if (ret) {
1690e1eb 2005 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2006 mutex_unlock(&dev->struct_mutex);
a5071c2f 2007 DRM_ERROR("failed to update base address\n");
4e6cfefc 2008 return ret;
79e53945 2009 }
3c4fdcfb 2010
b7f1de28
CW		 2011 if (old_fb) {
2012 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2013 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2014 }
652c393a 2015
6b8e6ed0 2016 intel_update_fbc(dev);
5c3b82e2 2017 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2018
2019 if (!dev->primary->master)
5c3b82e2 2020 return 0;
79e53945
JB		 2021
2022 master_priv = dev->primary->master->driver_priv;
2023 if (!master_priv->sarea_priv)
5c3b82e2 2024 return 0;
79e53945 2025
265db958 2026 if (intel_crtc->pipe) {
79e53945
JB		 2027 master_priv->sarea_priv->pipeB_x = x;
2028 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2029 } else {
2030 master_priv->sarea_priv->pipeA_x = x;
2031 master_priv->sarea_priv->pipeA_y = y;
79e53945 2032 }
5c3b82e2
CW		 2033
2034 return 0;
79e53945
JB		 2035}
2036
5eddb70b 2037static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2038{
2039 struct drm_device *dev = crtc->dev;
2040 struct drm_i915_private *dev_priv = dev->dev_private;
2041 u32 dpa_ctl;
2042
28c97730 2043 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2044 dpa_ctl = I915_READ(DP_A);
2045 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2046
2047 if (clock < 200000) {
2048 u32 temp;
2049 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2050 /* workaround for 160Mhz:
2051 1) program 0x4600c bits 15:0 = 0x8124
2052 2) program 0x46010 bit 0 = 1
2053 3) program 0x46034 bit 24 = 1
2054 4) program 0x64000 bit 14 = 1
2055 */
2056 temp = I915_READ(0x4600c);
2057 temp &= 0xffff0000;
2058 I915_WRITE(0x4600c, temp | 0x8124);
2059
2060 temp = I915_READ(0x46010);
2061 I915_WRITE(0x46010, temp | 1);
2062
2063 temp = I915_READ(0x46034);
2064 I915_WRITE(0x46034, temp | (1 << 24));
2065 } else {
2066 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2067 }
2068 I915_WRITE(DP_A, dpa_ctl);
2069
5eddb70b 2070 POSTING_READ(DP_A);
32f9d658
ZW		 2071 udelay(500);
2072}
2073
5e84e1a4
ZW		 2074static void intel_fdi_normal_train(struct drm_crtc *crtc)
2075{
2076 struct drm_device *dev = crtc->dev;
2077 struct drm_i915_private *dev_priv = dev->dev_private;
2078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2079 int pipe = intel_crtc->pipe;
2080 u32 reg, temp;
2081
2082 /* enable normal train */
2083 reg = FDI_TX_CTL(pipe);
2084 temp = I915_READ(reg);
61e499bf 2085 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2086 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2087 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2088 } else {
2089 temp &= ~FDI_LINK_TRAIN_NONE;
2090 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2091 }
5e84e1a4
ZW		 2092 I915_WRITE(reg, temp);
2093
2094 reg = FDI_RX_CTL(pipe);
2095 temp = I915_READ(reg);
2096 if (HAS_PCH_CPT(dev)) {
2097 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2098 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2099 } else {
2100 temp &= ~FDI_LINK_TRAIN_NONE;
2101 temp |= FDI_LINK_TRAIN_NONE;
2102 }
2103 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2104
2105 /* wait one idle pattern time */
2106 POSTING_READ(reg);
2107 udelay(1000);
357555c0
JB		 2108
2109 /* IVB wants error correction enabled */
2110 if (IS_IVYBRIDGE(dev))
2111 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2112 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2113}
2114
291427f5
JB		 2115static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2116{
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2118 u32 flags = I915_READ(SOUTH_CHICKEN1);
2119
2120 flags |= FDI_PHASE_SYNC_OVR(pipe);
2121 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2122 flags |= FDI_PHASE_SYNC_EN(pipe);
2123 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2124 POSTING_READ(SOUTH_CHICKEN1);
2125}
2126
8db9d77b
ZW		 2127/* The FDI link training functions for ILK/Ibexpeak. */
2128static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2129{
2130 struct drm_device *dev = crtc->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133 int pipe = intel_crtc->pipe;
0fc932b8 2134 int plane = intel_crtc->plane;
5eddb70b 2135 u32 reg, temp, tries;
8db9d77b 2136
0fc932b8
JB		 2137 /* FDI needs bits from pipe & plane first */
2138 assert_pipe_enabled(dev_priv, pipe);
2139 assert_plane_enabled(dev_priv, plane);
2140
e1a44743
AJ		 2141 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2142 for train result */
5eddb70b
CW		 2143 reg = FDI_RX_IMR(pipe);
2144 temp = I915_READ(reg);
e1a44743
AJ		 2145 temp &= ~FDI_RX_SYMBOL_LOCK;
2146 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2147 I915_WRITE(reg, temp);
2148 I915_READ(reg);
e1a44743
AJ		 2149 udelay(150);
2150
8db9d77b 2151 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2152 reg = FDI_TX_CTL(pipe);
2153 temp = I915_READ(reg);
77ffb597
AJ		 2154 temp &= ~(7 << 19);
2155 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2156 temp &= ~FDI_LINK_TRAIN_NONE;
2157 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2158 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2159
5eddb70b
CW		 2160 reg = FDI_RX_CTL(pipe);
2161 temp = I915_READ(reg);
8db9d77b
ZW		 2162 temp &= ~FDI_LINK_TRAIN_NONE;
2163 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2164 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2165
2166 POSTING_READ(reg);
8db9d77b
ZW		 2167 udelay(150);
2168
5b2adf89 2169 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2170 if (HAS_PCH_IBX(dev)) {
2171 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2172 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2173 FDI_RX_PHASE_SYNC_POINTER_EN);
2174 }
5b2adf89 2175
5eddb70b 2176 reg = FDI_RX_IIR(pipe);
e1a44743 2177 for (tries = 0; tries < 5; tries++) {
5eddb70b 2178 temp = I915_READ(reg);
8db9d77b
ZW		 2179 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2180
2181 if ((temp & FDI_RX_BIT_LOCK)) {
2182 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2183 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2184 break;
2185 }
8db9d77b 2186 }
e1a44743 2187 if (tries == 5)
5eddb70b 2188 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2189
2190 /* Train 2 */
5eddb70b
CW		 2191 reg = FDI_TX_CTL(pipe);
2192 temp = I915_READ(reg);
8db9d77b
ZW		 2193 temp &= ~FDI_LINK_TRAIN_NONE;
2194 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2195 I915_WRITE(reg, temp);
8db9d77b 2196
5eddb70b
CW		 2197 reg = FDI_RX_CTL(pipe);
2198 temp = I915_READ(reg);
8db9d77b
ZW		 2199 temp &= ~FDI_LINK_TRAIN_NONE;
2200 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2201 I915_WRITE(reg, temp);
8db9d77b 2202
5eddb70b
CW		 2203 POSTING_READ(reg);
2204 udelay(150);
8db9d77b 2205
5eddb70b 2206 reg = FDI_RX_IIR(pipe);
e1a44743 2207 for (tries = 0; tries < 5; tries++) {
5eddb70b 2208 temp = I915_READ(reg);
8db9d77b
ZW		 2209 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2210
2211 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2212 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2213 DRM_DEBUG_KMS("FDI train 2 done.\n");
2214 break;
2215 }
8db9d77b 2216 }
e1a44743 2217 if (tries == 5)
5eddb70b 2218 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2219
2220 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2221
8db9d77b
ZW		 2222}
2223
0206e353 2224static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2225 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2226 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2227 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2228 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2229};
2230
2231/* The FDI link training functions for SNB/Cougarpoint. */
2232static void gen6_fdi_link_train(struct drm_crtc *crtc)
2233{
2234 struct drm_device *dev = crtc->dev;
2235 struct drm_i915_private *dev_priv = dev->dev_private;
2236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2237 int pipe = intel_crtc->pipe;
fa37d39e 2238 u32 reg, temp, i, retry;
8db9d77b 2239
e1a44743
AJ		 2240 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2241 for train result */
5eddb70b
CW		 2242 reg = FDI_RX_IMR(pipe);
2243 temp = I915_READ(reg);
e1a44743
AJ		 2244 temp &= ~FDI_RX_SYMBOL_LOCK;
2245 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2246 I915_WRITE(reg, temp);
2247
2248 POSTING_READ(reg);
e1a44743
AJ		 2249 udelay(150);
2250
8db9d77b 2251 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2252 reg = FDI_TX_CTL(pipe);
2253 temp = I915_READ(reg);
77ffb597
AJ		 2254 temp &= ~(7 << 19);
2255 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2256 temp &= ~FDI_LINK_TRAIN_NONE;
2257 temp |= FDI_LINK_TRAIN_PATTERN_1;
2258 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2259 /* SNB-B */
2260 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2261 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2262
5eddb70b
CW		 2263 reg = FDI_RX_CTL(pipe);
2264 temp = I915_READ(reg);
8db9d77b
ZW		 2265 if (HAS_PCH_CPT(dev)) {
2266 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2267 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2268 } else {
2269 temp &= ~FDI_LINK_TRAIN_NONE;
2270 temp |= FDI_LINK_TRAIN_PATTERN_1;
2271 }
5eddb70b
CW		 2272 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2273
2274 POSTING_READ(reg);
8db9d77b
ZW		 2275 udelay(150);
2276
291427f5
JB		 2277 if (HAS_PCH_CPT(dev))
2278 cpt_phase_pointer_enable(dev, pipe);
2279
0206e353 2280 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2281 reg = FDI_TX_CTL(pipe);
2282 temp = I915_READ(reg);
8db9d77b
ZW		 2283 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2284 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2285 I915_WRITE(reg, temp);
2286
2287 POSTING_READ(reg);
8db9d77b
ZW		 2288 udelay(500);
2289
fa37d39e
SP		 2290 for (retry = 0; retry < 5; retry++) {
2291 reg = FDI_RX_IIR(pipe);
2292 temp = I915_READ(reg);
2293 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2294 if (temp & FDI_RX_BIT_LOCK) {
2295 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2296 DRM_DEBUG_KMS("FDI train 1 done.\n");
2297 break;
2298 }
2299 udelay(50);
8db9d77b 2300 }
fa37d39e
SP		 2301 if (retry < 5)
2302 break;
8db9d77b
ZW		 2303 }
2304 if (i == 4)
5eddb70b 2305 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2306
2307 /* Train 2 */
5eddb70b
CW		 2308 reg = FDI_TX_CTL(pipe);
2309 temp = I915_READ(reg);
8db9d77b
ZW		 2310 temp &= ~FDI_LINK_TRAIN_NONE;
2311 temp |= FDI_LINK_TRAIN_PATTERN_2;
2312 if (IS_GEN6(dev)) {
2313 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2314 /* SNB-B */
2315 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2316 }
5eddb70b 2317 I915_WRITE(reg, temp);
8db9d77b 2318
5eddb70b
CW		 2319 reg = FDI_RX_CTL(pipe);
2320 temp = I915_READ(reg);
8db9d77b
ZW		 2321 if (HAS_PCH_CPT(dev)) {
2322 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2323 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2324 } else {
2325 temp &= ~FDI_LINK_TRAIN_NONE;
2326 temp |= FDI_LINK_TRAIN_PATTERN_2;
2327 }
5eddb70b
CW		 2328 I915_WRITE(reg, temp);
2329
2330 POSTING_READ(reg);
8db9d77b
ZW		 2331 udelay(150);
2332
0206e353 2333 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2334 reg = FDI_TX_CTL(pipe);
2335 temp = I915_READ(reg);
8db9d77b
ZW		 2336 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2337 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2338 I915_WRITE(reg, temp);
2339
2340 POSTING_READ(reg);
8db9d77b
ZW		 2341 udelay(500);
2342
fa37d39e
SP		 2343 for (retry = 0; retry < 5; retry++) {
2344 reg = FDI_RX_IIR(pipe);
2345 temp = I915_READ(reg);
2346 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2347 if (temp & FDI_RX_SYMBOL_LOCK) {
2348 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2349 DRM_DEBUG_KMS("FDI train 2 done.\n");
2350 break;
2351 }
2352 udelay(50);
8db9d77b 2353 }
fa37d39e
SP		 2354 if (retry < 5)
2355 break;
8db9d77b
ZW		 2356 }
2357 if (i == 4)
5eddb70b 2358 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2359
2360 DRM_DEBUG_KMS("FDI train done.\n");
2361}
2362
357555c0
JB		 2363/* Manual link training for Ivy Bridge A0 parts */
2364static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2365{
2366 struct drm_device *dev = crtc->dev;
2367 struct drm_i915_private *dev_priv = dev->dev_private;
2368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2369 int pipe = intel_crtc->pipe;
2370 u32 reg, temp, i;
2371
2372 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2373 for train result */
2374 reg = FDI_RX_IMR(pipe);
2375 temp = I915_READ(reg);
2376 temp &= ~FDI_RX_SYMBOL_LOCK;
2377 temp &= ~FDI_RX_BIT_LOCK;
2378 I915_WRITE(reg, temp);
2379
2380 POSTING_READ(reg);
2381 udelay(150);
2382
2383 /* enable CPU FDI TX and PCH FDI RX */
2384 reg = FDI_TX_CTL(pipe);
2385 temp = I915_READ(reg);
2386 temp &= ~(7 << 19);
2387 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2388 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2389 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2390 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2391 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2392 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2393 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2394
2395 reg = FDI_RX_CTL(pipe);
2396 temp = I915_READ(reg);
2397 temp &= ~FDI_LINK_TRAIN_AUTO;
2398 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2399 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2400 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2401 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2402
2403 POSTING_READ(reg);
2404 udelay(150);
2405
291427f5
JB		 2406 if (HAS_PCH_CPT(dev))
2407 cpt_phase_pointer_enable(dev, pipe);
2408
0206e353 2409 for (i = 0; i < 4; i++) {
357555c0
JB		 2410 reg = FDI_TX_CTL(pipe);
2411 temp = I915_READ(reg);
2412 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2413 temp |= snb_b_fdi_train_param[i];
2414 I915_WRITE(reg, temp);
2415
2416 POSTING_READ(reg);
2417 udelay(500);
2418
2419 reg = FDI_RX_IIR(pipe);
2420 temp = I915_READ(reg);
2421 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2422
2423 if (temp & FDI_RX_BIT_LOCK ||
2424 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2425 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2426 DRM_DEBUG_KMS("FDI train 1 done.\n");
2427 break;
2428 }
2429 }
2430 if (i == 4)
2431 DRM_ERROR("FDI train 1 fail!\n");
2432
2433 /* Train 2 */
2434 reg = FDI_TX_CTL(pipe);
2435 temp = I915_READ(reg);
2436 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2437 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2438 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2439 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2440 I915_WRITE(reg, temp);
2441
2442 reg = FDI_RX_CTL(pipe);
2443 temp = I915_READ(reg);
2444 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2445 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2446 I915_WRITE(reg, temp);
2447
2448 POSTING_READ(reg);
2449 udelay(150);
2450
0206e353 2451 for (i = 0; i < 4; i++) {
357555c0
JB		 2452 reg = FDI_TX_CTL(pipe);
2453 temp = I915_READ(reg);
2454 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2455 temp |= snb_b_fdi_train_param[i];
2456 I915_WRITE(reg, temp);
2457
2458 POSTING_READ(reg);
2459 udelay(500);
2460
2461 reg = FDI_RX_IIR(pipe);
2462 temp = I915_READ(reg);
2463 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2464
2465 if (temp & FDI_RX_SYMBOL_LOCK) {
2466 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2467 DRM_DEBUG_KMS("FDI train 2 done.\n");
2468 break;
2469 }
2470 }
2471 if (i == 4)
2472 DRM_ERROR("FDI train 2 fail!\n");
2473
2474 DRM_DEBUG_KMS("FDI train done.\n");
2475}
2476
2477static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2478{
2479 struct drm_device *dev = crtc->dev;
2480 struct drm_i915_private *dev_priv = dev->dev_private;
2481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2482 int pipe = intel_crtc->pipe;
5eddb70b 2483 u32 reg, temp;
79e53945 2484
c64e311e 2485 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2486 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2487 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2488
c98e9dcf 2489 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2490 reg = FDI_RX_CTL(pipe);
2491 temp = I915_READ(reg);
2492 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2493 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2494 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2495 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2496
2497 POSTING_READ(reg);
c98e9dcf
JB		 2498 udelay(200);
2499
2500 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2501 temp = I915_READ(reg);
2502 I915_WRITE(reg, temp | FDI_PCDCLK);
2503
2504 POSTING_READ(reg);
c98e9dcf
JB		 2505 udelay(200);
2506
2507 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2508 reg = FDI_TX_CTL(pipe);
2509 temp = I915_READ(reg);
c98e9dcf 2510 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2511 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2512
2513 POSTING_READ(reg);
c98e9dcf 2514 udelay(100);
6be4a607 2515 }
0e23b99d
JB		 2516}
2517
291427f5
JB		 2518static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2519{
2520 struct drm_i915_private *dev_priv = dev->dev_private;
2521 u32 flags = I915_READ(SOUTH_CHICKEN1);
2522
2523 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2524 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2525 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2526 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2527 POSTING_READ(SOUTH_CHICKEN1);
2528}
0fc932b8
JB		 2529static void ironlake_fdi_disable(struct drm_crtc *crtc)
2530{
2531 struct drm_device *dev = crtc->dev;
2532 struct drm_i915_private *dev_priv = dev->dev_private;
2533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2534 int pipe = intel_crtc->pipe;
2535 u32 reg, temp;
2536
2537 /* disable CPU FDI tx and PCH FDI rx */
2538 reg = FDI_TX_CTL(pipe);
2539 temp = I915_READ(reg);
2540 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2541 POSTING_READ(reg);
2542
2543 reg = FDI_RX_CTL(pipe);
2544 temp = I915_READ(reg);
2545 temp &= ~(0x7 << 16);
2546 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2547 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2548
2549 POSTING_READ(reg);
2550 udelay(100);
2551
2552 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2553 if (HAS_PCH_IBX(dev)) {
2554 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2555 I915_WRITE(FDI_RX_CHICKEN(pipe),
2556 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2557 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2558 } else if (HAS_PCH_CPT(dev)) {
2559 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2560 }
0fc932b8
JB		 2561
2562 /* still set train pattern 1 */
2563 reg = FDI_TX_CTL(pipe);
2564 temp = I915_READ(reg);
2565 temp &= ~FDI_LINK_TRAIN_NONE;
2566 temp |= FDI_LINK_TRAIN_PATTERN_1;
2567 I915_WRITE(reg, temp);
2568
2569 reg = FDI_RX_CTL(pipe);
2570 temp = I915_READ(reg);
2571 if (HAS_PCH_CPT(dev)) {
2572 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2573 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2574 } else {
2575 temp &= ~FDI_LINK_TRAIN_NONE;
2576 temp |= FDI_LINK_TRAIN_PATTERN_1;
2577 }
2578 /* BPC in FDI rx is consistent with that in PIPECONF */
2579 temp &= ~(0x07 << 16);
2580 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2581 I915_WRITE(reg, temp);
2582
2583 POSTING_READ(reg);
2584 udelay(100);
2585}
2586
e6c3a2a6
CW		 2587static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2588{
0f91128d 2589 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2590
2591 if (crtc->fb == NULL)
2592 return;
2593
0f91128d
CW		 2594 mutex_lock(&dev->struct_mutex);
2595 intel_finish_fb(crtc->fb);
2596 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2597}
2598
040484af
JB		 2599static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2600{
2601 struct drm_device *dev = crtc->dev;
2602 struct drm_mode_config *mode_config = &dev->mode_config;
2603 struct intel_encoder *encoder;
2604
2605 /*
2606 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2607 * must be driven by its own crtc; no sharing is possible.
2608 */
2609 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2610 if (encoder->base.crtc != crtc)
2611 continue;
2612
6ee8bab0
ED		 2613 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2614 * CPU handles all others */
2615 if (IS_HASWELL(dev)) {
2616 /* It is still unclear how this will work on PPT, so throw up a warning */
2617 WARN_ON(!HAS_PCH_LPT(dev));
2618
2619 if (encoder->type == DRM_MODE_ENCODER_DAC) {
2620 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2621 return true;
2622 } else {
2623 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2624 encoder->type);
2625 return false;
2626 }
2627 }
2628
040484af
JB		 2629 switch (encoder->type) {
2630 case INTEL_OUTPUT_EDP:
2631 if (!intel_encoder_is_pch_edp(&encoder->base))
2632 return false;
2633 continue;
2634 }
2635 }
2636
2637 return true;
2638}
2639
f67a559d
JB		 2640/*
2641 * Enable PCH resources required for PCH ports:
2642 * - PCH PLLs
2643 * - FDI training & RX/TX
2644 * - update transcoder timings
2645 * - DP transcoding bits
2646 * - transcoder
2647 */
2648static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2649{
2650 struct drm_device *dev = crtc->dev;
2651 struct drm_i915_private *dev_priv = dev->dev_private;
2652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2653 int pipe = intel_crtc->pipe;
ee7b9f93 2654 u32 reg, temp;
2c07245f 2655
c98e9dcf 2656 /* For PCH output, training FDI link */
674cf967 2657 dev_priv->display.fdi_link_train(crtc);
2c07245f 2658
ee7b9f93 2659 intel_enable_pch_pll(intel_crtc);
8db9d77b 2660
c98e9dcf 2661 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2662 u32 sel;
4b645f14 2663
c98e9dcf 2664 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2665 switch (pipe) {
2666 default:
2667 case 0:
2668 temp |= TRANSA_DPLL_ENABLE;
2669 sel = TRANSA_DPLLB_SEL;
2670 break;
2671 case 1:
2672 temp |= TRANSB_DPLL_ENABLE;
2673 sel = TRANSB_DPLLB_SEL;
2674 break;
2675 case 2:
2676 temp |= TRANSC_DPLL_ENABLE;
2677 sel = TRANSC_DPLLB_SEL;
2678 break;
d64311ab 2679 }
ee7b9f93
JB		 2680 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2681 temp |= sel;
2682 else
2683 temp &= ~sel;
c98e9dcf 2684 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2685 }
5eddb70b 2686
d9b6cb56
JB		 2687 /* set transcoder timing, panel must allow it */
2688 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2689 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2690 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2691 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2692
5eddb70b
CW		 2693 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2694 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2695 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 2696 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 2697
f57e1e3a
ED		 2698 if (!IS_HASWELL(dev))
2699 intel_fdi_normal_train(crtc);
5e84e1a4 2700
c98e9dcf
JB		 2701 /* For PCH DP, enable TRANS_DP_CTL */
2702 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2703 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2704 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 2705 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2706 reg = TRANS_DP_CTL(pipe);
2707 temp = I915_READ(reg);
2708 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2709 TRANS_DP_SYNC_MASK |
2710 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2711 temp |= (TRANS_DP_OUTPUT_ENABLE |
2712 TRANS_DP_ENH_FRAMING);
9325c9f0 2713 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2714
2715 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2716 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2717 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2718 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2719
2720 switch (intel_trans_dp_port_sel(crtc)) {
2721 case PCH_DP_B:
5eddb70b 2722 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2723 break;
2724 case PCH_DP_C:
5eddb70b 2725 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2726 break;
2727 case PCH_DP_D:
5eddb70b 2728 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2729 break;
2730 default:
2731 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2732 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2733 break;
32f9d658 2734 }
2c07245f 2735
5eddb70b 2736 I915_WRITE(reg, temp);
6be4a607 2737 }
b52eb4dc 2738
040484af 2739 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2740}
2741
ee7b9f93
JB		 2742static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2743{
2744 struct intel_pch_pll *pll = intel_crtc->pch_pll;
2745
2746 if (pll == NULL)
2747 return;
2748
2749 if (pll->refcount == 0) {
2750 WARN(1, "bad PCH PLL refcount\n");
2751 return;
2752 }
2753
2754 --pll->refcount;
2755 intel_crtc->pch_pll = NULL;
2756}
2757
2758static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2759{
2760 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2761 struct intel_pch_pll *pll;
2762 int i;
2763
2764 pll = intel_crtc->pch_pll;
2765 if (pll) {
2766 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2767 intel_crtc->base.base.id, pll->pll_reg);
2768 goto prepare;
2769 }
2770
2771 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2772 pll = &dev_priv->pch_plls[i];
2773
2774 /* Only want to check enabled timings first */
2775 if (pll->refcount == 0)
2776 continue;
2777
2778 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2779 fp == I915_READ(pll->fp0_reg)) {
2780 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2781 intel_crtc->base.base.id,
2782 pll->pll_reg, pll->refcount, pll->active);
2783
2784 goto found;
2785 }
2786 }
2787
2788 /* Ok no matching timings, maybe there's a free one? */
2789 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2790 pll = &dev_priv->pch_plls[i];
2791 if (pll->refcount == 0) {
2792 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2793 intel_crtc->base.base.id, pll->pll_reg);
2794 goto found;
2795 }
2796 }
2797
2798 return NULL;
2799
2800found:
2801 intel_crtc->pch_pll = pll;
2802 pll->refcount++;
2803 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2804prepare: /* separate function? */
2805 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 2806
e04c7350
CW		 2807 /* Wait for the clocks to stabilize before rewriting the regs */
2808 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 2809 POSTING_READ(pll->pll_reg);
2810 udelay(150);
e04c7350
CW		 2811
2812 I915_WRITE(pll->fp0_reg, fp);
2813 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 2814 pll->on = false;
2815 return pll;
2816}
2817
d4270e57
JB		 2818void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2819{
2820 struct drm_i915_private *dev_priv = dev->dev_private;
2821 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2822 u32 temp;
2823
2824 temp = I915_READ(dslreg);
2825 udelay(500);
2826 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2827 /* Without this, mode sets may fail silently on FDI */
2828 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2829 udelay(250);
2830 I915_WRITE(tc2reg, 0);
2831 if (wait_for(I915_READ(dslreg) != temp, 5))
2832 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2833 }
2834}
2835
f67a559d
JB		 2836static void ironlake_crtc_enable(struct drm_crtc *crtc)
2837{
2838 struct drm_device *dev = crtc->dev;
2839 struct drm_i915_private *dev_priv = dev->dev_private;
2840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2841 int pipe = intel_crtc->pipe;
2842 int plane = intel_crtc->plane;
2843 u32 temp;
2844 bool is_pch_port;
2845
2846 if (intel_crtc->active)
2847 return;
2848
2849 intel_crtc->active = true;
2850 intel_update_watermarks(dev);
2851
2852 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2853 temp = I915_READ(PCH_LVDS);
2854 if ((temp & LVDS_PORT_EN) == 0)
2855 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2856 }
2857
2858 is_pch_port = intel_crtc_driving_pch(crtc);
2859
2860 if (is_pch_port)
357555c0 2861 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2862 else
2863 ironlake_fdi_disable(crtc);
2864
2865 /* Enable panel fitting for LVDS */
2866 if (dev_priv->pch_pf_size &&
2867 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2868 /* Force use of hard-coded filter coefficients
2869 * as some pre-programmed values are broken,
2870 * e.g. x201.
2871 */
9db4a9c7
JB		 2872 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2873 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2874 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2875 }
2876
9c54c0dd
JB		 2877 /*
2878 * On ILK+ LUT must be loaded before the pipe is running but with
2879 * clocks enabled
2880 */
2881 intel_crtc_load_lut(crtc);
2882
f67a559d
JB		 2883 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2884 intel_enable_plane(dev_priv, plane, pipe);
2885
2886 if (is_pch_port)
2887 ironlake_pch_enable(crtc);
c98e9dcf 2888
d1ebd816 2889 mutex_lock(&dev->struct_mutex);
bed4a673 2890 intel_update_fbc(dev);
d1ebd816
BW		 2891 mutex_unlock(&dev->struct_mutex);
2892
6b383a7f 2893 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2894}
2895
2896static void ironlake_crtc_disable(struct drm_crtc *crtc)
2897{
2898 struct drm_device *dev = crtc->dev;
2899 struct drm_i915_private *dev_priv = dev->dev_private;
2900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2901 int pipe = intel_crtc->pipe;
2902 int plane = intel_crtc->plane;
5eddb70b 2903 u32 reg, temp;
b52eb4dc 2904
f7abfe8b
CW		 2905 if (!intel_crtc->active)
2906 return;
2907
e6c3a2a6 2908 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 2909 drm_vblank_off(dev, pipe);
6b383a7f 2910 intel_crtc_update_cursor(crtc, false);
5eddb70b 2911
b24e7179 2912 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 2913
973d04f9
CW		 2914 if (dev_priv->cfb_plane == plane)
2915 intel_disable_fbc(dev);
2c07245f 2916
b24e7179 2917 intel_disable_pipe(dev_priv, pipe);
32f9d658 2918
6be4a607 2919 /* Disable PF */
9db4a9c7
JB		 2920 I915_WRITE(PF_CTL(pipe), 0);
2921 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 2922
0fc932b8 2923 ironlake_fdi_disable(crtc);
2c07245f 2924
47a05eca
JB		 2925 /* This is a horrible layering violation; we should be doing this in
2926 * the connector/encoder ->prepare instead, but we don't always have
2927 * enough information there about the config to know whether it will
2928 * actually be necessary or just cause undesired flicker.
2929 */
2930 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 2931
040484af 2932 intel_disable_transcoder(dev_priv, pipe);
913d8d11 2933
6be4a607
JB		 2934 if (HAS_PCH_CPT(dev)) {
2935 /* disable TRANS_DP_CTL */
5eddb70b
CW		 2936 reg = TRANS_DP_CTL(pipe);
2937 temp = I915_READ(reg);
2938 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 2939 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 2940 I915_WRITE(reg, temp);
6be4a607
JB		 2941
2942 /* disable DPLL_SEL */
2943 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 2944 switch (pipe) {
2945 case 0:
d64311ab 2946 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 2947 break;
2948 case 1:
6be4a607 2949 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 2950 break;
2951 case 2:
4b645f14 2952 /* C shares PLL A or B */
d64311ab 2953 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 2954 break;
2955 default:
2956 BUG(); /* wtf */
2957 }
6be4a607 2958 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 2959 }
e3421a18 2960
6be4a607 2961 /* disable PCH DPLL */
ee7b9f93 2962 intel_disable_pch_pll(intel_crtc);
8db9d77b 2963
6be4a607 2964 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 2965 reg = FDI_RX_CTL(pipe);
2966 temp = I915_READ(reg);
2967 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 2968
6be4a607 2969 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 2970 reg = FDI_TX_CTL(pipe);
2971 temp = I915_READ(reg);
2972 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2973
2974 POSTING_READ(reg);
6be4a607 2975 udelay(100);
8db9d77b 2976
5eddb70b
CW		 2977 reg = FDI_RX_CTL(pipe);
2978 temp = I915_READ(reg);
2979 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 2980
6be4a607 2981 /* Wait for the clocks to turn off. */
5eddb70b 2982 POSTING_READ(reg);
6be4a607 2983 udelay(100);
6b383a7f 2984
f7abfe8b 2985 intel_crtc->active = false;
6b383a7f 2986 intel_update_watermarks(dev);
d1ebd816
BW		 2987
2988 mutex_lock(&dev->struct_mutex);
6b383a7f 2989 intel_update_fbc(dev);
d1ebd816 2990 mutex_unlock(&dev->struct_mutex);
6be4a607 2991}
1b3c7a47 2992
6be4a607
JB		 2993static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2994{
2995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2996 int pipe = intel_crtc->pipe;
2997 int plane = intel_crtc->plane;
8db9d77b 2998
6be4a607
JB		 2999 /* XXX: When our outputs are all unaware of DPMS modes other than off
3000 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3001 */
3002 switch (mode) {
3003 case DRM_MODE_DPMS_ON:
3004 case DRM_MODE_DPMS_STANDBY:
3005 case DRM_MODE_DPMS_SUSPEND:
3006 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3007 ironlake_crtc_enable(crtc);
3008 break;
1b3c7a47 3009
6be4a607
JB		 3010 case DRM_MODE_DPMS_OFF:
3011 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3012 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3013 break;
3014 }
3015}
3016
ee7b9f93
JB		 3017static void ironlake_crtc_off(struct drm_crtc *crtc)
3018{
3019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3020 intel_put_pch_pll(intel_crtc);
3021}
3022
02e792fb
DV		 3023static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3024{
02e792fb 3025 if (!enable && intel_crtc->overlay) {
23f09ce3 3026 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3027 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3028
23f09ce3 3029 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3030 dev_priv->mm.interruptible = false;
3031 (void) intel_overlay_switch_off(intel_crtc->overlay);
3032 dev_priv->mm.interruptible = true;
23f09ce3 3033 mutex_unlock(&dev->struct_mutex);
02e792fb 3034 }
02e792fb 3035
5dcdbcb0
CW		 3036 /* Let userspace switch the overlay on again. In most cases userspace
3037 * has to recompute where to put it anyway.
3038 */
02e792fb
DV		 3039}
3040
0b8765c6 3041static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3042{
3043 struct drm_device *dev = crtc->dev;
79e53945
JB		 3044 struct drm_i915_private *dev_priv = dev->dev_private;
3045 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3046 int pipe = intel_crtc->pipe;
80824003 3047 int plane = intel_crtc->plane;
79e53945 3048
f7abfe8b
CW		 3049 if (intel_crtc->active)
3050 return;
3051
3052 intel_crtc->active = true;
6b383a7f
CW		 3053 intel_update_watermarks(dev);
3054
63d7bbe9 3055 intel_enable_pll(dev_priv, pipe);
040484af 3056 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3057 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3058
0b8765c6 3059 intel_crtc_load_lut(crtc);
bed4a673 3060 intel_update_fbc(dev);
79e53945 3061
0b8765c6
JB		 3062 /* Give the overlay scaler a chance to enable if it's on this pipe */
3063 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3064 intel_crtc_update_cursor(crtc, true);
0b8765c6 3065}
79e53945 3066
0b8765c6
JB		 3067static void i9xx_crtc_disable(struct drm_crtc *crtc)
3068{
3069 struct drm_device *dev = crtc->dev;
3070 struct drm_i915_private *dev_priv = dev->dev_private;
3071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3072 int pipe = intel_crtc->pipe;
3073 int plane = intel_crtc->plane;
b690e96c 3074
f7abfe8b
CW		 3075 if (!intel_crtc->active)
3076 return;
3077
0b8765c6 3078 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3079 intel_crtc_wait_for_pending_flips(crtc);
3080 drm_vblank_off(dev, pipe);
0b8765c6 3081 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3082 intel_crtc_update_cursor(crtc, false);
0b8765c6 3083
973d04f9
CW		 3084 if (dev_priv->cfb_plane == plane)
3085 intel_disable_fbc(dev);
79e53945 3086
b24e7179 3087 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3088 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3089 intel_disable_pll(dev_priv, pipe);
0b8765c6 3090
f7abfe8b 3091 intel_crtc->active = false;
6b383a7f
CW		 3092 intel_update_fbc(dev);
3093 intel_update_watermarks(dev);
0b8765c6
JB		 3094}
3095
3096static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3097{
3098 /* XXX: When our outputs are all unaware of DPMS modes other than off
3099 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3100 */
3101 switch (mode) {
3102 case DRM_MODE_DPMS_ON:
3103 case DRM_MODE_DPMS_STANDBY:
3104 case DRM_MODE_DPMS_SUSPEND:
3105 i9xx_crtc_enable(crtc);
3106 break;
3107 case DRM_MODE_DPMS_OFF:
3108 i9xx_crtc_disable(crtc);
79e53945
JB		 3109 break;
3110 }
2c07245f
ZW		 3111}
3112
ee7b9f93
JB		 3113static void i9xx_crtc_off(struct drm_crtc *crtc)
3114{
3115}
3116
2c07245f
ZW		 3117/**
3118 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3119 */
3120static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3121{
3122 struct drm_device *dev = crtc->dev;
e70236a8 3123 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3124 struct drm_i915_master_private *master_priv;
3125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3126 int pipe = intel_crtc->pipe;
3127 bool enabled;
3128
032d2a0d
CW		 3129 if (intel_crtc->dpms_mode == mode)
3130 return;
3131
65655d4a 3132 intel_crtc->dpms_mode = mode;
debcaddc 3133
e70236a8 3134 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3135
3136 if (!dev->primary->master)
3137 return;
3138
3139 master_priv = dev->primary->master->driver_priv;
3140 if (!master_priv->sarea_priv)
3141 return;
3142
3143 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3144
3145 switch (pipe) {
3146 case 0:
3147 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3148 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3149 break;
3150 case 1:
3151 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3152 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3153 break;
3154 default:
9db4a9c7 3155 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3156 break;
3157 }
79e53945
JB		 3158}
3159
cdd59983
CW		 3160static void intel_crtc_disable(struct drm_crtc *crtc)
3161{
3162 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3163 struct drm_device *dev = crtc->dev;
ee7b9f93 3164 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983
CW		 3165
3166 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
ee7b9f93
JB		 3167 dev_priv->display.off(crtc);
3168
931872fc
CW		 3169 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3170 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3171
3172 if (crtc->fb) {
3173 mutex_lock(&dev->struct_mutex);
1690e1eb 3174 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3175 mutex_unlock(&dev->struct_mutex);
3176 }
3177}
3178
7e7d76c3
JB		 3179/* Prepare for a mode set.
3180 *
3181 * Note we could be a lot smarter here. We need to figure out which outputs
3182 * will be enabled, which disabled (in short, how the config will changes)
3183 * and perform the minimum necessary steps to accomplish that, e.g. updating
3184 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3185 * panel fitting is in the proper state, etc.
3186 */
3187static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3188{
7e7d76c3 3189 i9xx_crtc_disable(crtc);
79e53945
JB		 3190}
3191
7e7d76c3 3192static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3193{
7e7d76c3 3194 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3195}
3196
3197static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3198{
7e7d76c3 3199 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3200}
3201
3202static void ironlake_crtc_commit(struct drm_crtc *crtc)
3203{
7e7d76c3 3204 ironlake_crtc_enable(crtc);
79e53945
JB		 3205}
3206
0206e353 3207void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3208{
3209 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3210 /* lvds has its own version of prepare see intel_lvds_prepare */
3211 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3212}
3213
0206e353 3214void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3215{
3216 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57 3217 struct drm_device *dev = encoder->dev;
d47d7cb8 3218 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
d4270e57 3219
79e53945
JB		 3220 /* lvds has its own version of commit see intel_lvds_commit */
3221 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3222
3223 if (HAS_PCH_CPT(dev))
3224 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3225}
3226
ea5b213a
CW		 3227void intel_encoder_destroy(struct drm_encoder *encoder)
3228{
4ef69c7a 3229 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3230
ea5b213a
CW		 3231 drm_encoder_cleanup(encoder);
3232 kfree(intel_encoder);
3233}
3234
79e53945
JB		 3235static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3236 struct drm_display_mode *mode,
3237 struct drm_display_mode *adjusted_mode)
3238{
2c07245f 3239 struct drm_device *dev = crtc->dev;
89749350 3240
bad720ff 3241 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3242 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3243 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3244 return false;
2c07245f 3245 }
89749350 3246
f9bef081
DV		 3247 /* All interlaced capable intel hw wants timings in frames. Note though
3248 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3249 * timings, so we need to be careful not to clobber these.*/
3250 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3251 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3252
79e53945
JB		 3253 return true;
3254}
3255
25eb05fc
JB		 3256static int valleyview_get_display_clock_speed(struct drm_device *dev)
3257{
3258 return 400000; /* FIXME */
3259}
3260
e70236a8
JB		 3261static int i945_get_display_clock_speed(struct drm_device *dev)
3262{
3263 return 400000;
3264}
79e53945 3265
e70236a8 3266static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3267{
e70236a8
JB		 3268 return 333000;
3269}
79e53945 3270
e70236a8
JB		 3271static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3272{
3273 return 200000;
3274}
79e53945 3275
e70236a8
JB		 3276static int i915gm_get_display_clock_speed(struct drm_device *dev)
3277{
3278 u16 gcfgc = 0;
79e53945 3279
e70236a8
JB		 3280 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3281
3282 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3283 return 133000;
3284 else {
3285 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3286 case GC_DISPLAY_CLOCK_333_MHZ:
3287 return 333000;
3288 default:
3289 case GC_DISPLAY_CLOCK_190_200_MHZ:
3290 return 190000;
79e53945 3291 }
e70236a8
JB		 3292 }
3293}
3294
3295static int i865_get_display_clock_speed(struct drm_device *dev)
3296{
3297 return 266000;
3298}
3299
3300static int i855_get_display_clock_speed(struct drm_device *dev)
3301{
3302 u16 hpllcc = 0;
3303 /* Assume that the hardware is in the high speed state. This
3304 * should be the default.
3305 */
3306 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3307 case GC_CLOCK_133_200:
3308 case GC_CLOCK_100_200:
3309 return 200000;
3310 case GC_CLOCK_166_250:
3311 return 250000;
3312 case GC_CLOCK_100_133:
79e53945 3313 return 133000;
e70236a8 3314 }
79e53945 3315
e70236a8
JB		 3316 /* Shouldn't happen */
3317 return 0;
3318}
79e53945 3319
e70236a8
JB		 3320static int i830_get_display_clock_speed(struct drm_device *dev)
3321{
3322 return 133000;
79e53945
JB		 3323}
3324
2c07245f
ZW		 3325struct fdi_m_n {
3326 u32 tu;
3327 u32 gmch_m;
3328 u32 gmch_n;
3329 u32 link_m;
3330 u32 link_n;
3331};
3332
3333static void
3334fdi_reduce_ratio(u32 *num, u32 *den)
3335{
3336 while (*num > 0xffffff || *den > 0xffffff) {
3337 *num >>= 1;
3338 *den >>= 1;
3339 }
3340}
3341
2c07245f 3342static void
f2b115e6
AJ		 3343ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3344 int link_clock, struct fdi_m_n *m_n)
2c07245f 3345{
2c07245f
ZW		 3346 m_n->tu = 64; /* default size */
3347
22ed1113
CW		 3348 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3349 m_n->gmch_m = bits_per_pixel * pixel_clock;
3350 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3351 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3352
22ed1113
CW		 3353 m_n->link_m = pixel_clock;
3354 m_n->link_n = link_clock;
2c07245f
ZW		 3355 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3356}
3357
a7615030
CW		 3358static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3359{
72bbe58c
KP		 3360 if (i915_panel_use_ssc >= 0)
3361 return i915_panel_use_ssc != 0;
3362 return dev_priv->lvds_use_ssc
435793df 3363 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3364}
3365
5a354204
JB		 3366/**
3367 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3368 * @crtc: CRTC structure
3b5c78a3 3369 * @mode: requested mode
5a354204
JB		 3370 *
3371 * A pipe may be connected to one or more outputs. Based on the depth of the
3372 * attached framebuffer, choose a good color depth to use on the pipe.
3373 *
3374 * If possible, match the pipe depth to the fb depth. In some cases, this
3375 * isn't ideal, because the connected output supports a lesser or restricted
3376 * set of depths. Resolve that here:
3377 * LVDS typically supports only 6bpc, so clamp down in that case
3378 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3379 * Displays may support a restricted set as well, check EDID and clamp as
3380 * appropriate.
3b5c78a3 3381 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3382 *
3383 * RETURNS:
3384 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3385 * true if they don't match).
3386 */
3387static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 3388 unsigned int *pipe_bpp,
3389 struct drm_display_mode *mode)
5a354204
JB		 3390{
3391 struct drm_device *dev = crtc->dev;
3392 struct drm_i915_private *dev_priv = dev->dev_private;
3393 struct drm_encoder *encoder;
3394 struct drm_connector *connector;
3395 unsigned int display_bpc = UINT_MAX, bpc;
3396
3397 /* Walk the encoders & connectors on this crtc, get min bpc */
3398 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3399 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3400
3401 if (encoder->crtc != crtc)
3402 continue;
3403
3404 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3405 unsigned int lvds_bpc;
3406
3407 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3408 LVDS_A3_POWER_UP)
3409 lvds_bpc = 8;
3410 else
3411 lvds_bpc = 6;
3412
3413 if (lvds_bpc < display_bpc) {
82820490 3414 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3415 display_bpc = lvds_bpc;
3416 }
3417 continue;
3418 }
3419
3420 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3421 /* Use VBT settings if we have an eDP panel */
3422 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3423
3424 if (edp_bpc < display_bpc) {
82820490 3425 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 3426 display_bpc = edp_bpc;
3427 }
3428 continue;
3429 }
3430
3431 /* Not one of the known troublemakers, check the EDID */
3432 list_for_each_entry(connector, &dev->mode_config.connector_list,
3433 head) {
3434 if (connector->encoder != encoder)
3435 continue;
3436
62ac41a6
JB		 3437 /* Don't use an invalid EDID bpc value */
3438 if (connector->display_info.bpc &&
3439 connector->display_info.bpc < display_bpc) {
82820490 3440 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3441 display_bpc = connector->display_info.bpc;
3442 }
3443 }
3444
3445 /*
3446 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3447 * through, clamp it down. (Note: >12bpc will be caught below.)
3448 */
3449 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3450 if (display_bpc > 8 && display_bpc < 12) {
82820490 3451 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3452 display_bpc = 12;
3453 } else {
82820490 3454 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3455 display_bpc = 8;
3456 }
3457 }
3458 }
3459
3b5c78a3
AJ		 3460 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3461 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3462 display_bpc = 6;
3463 }
3464
5a354204
JB		 3465 /*
3466 * We could just drive the pipe at the highest bpc all the time and
3467 * enable dithering as needed, but that costs bandwidth. So choose
3468 * the minimum value that expresses the full color range of the fb but
3469 * also stays within the max display bpc discovered above.
3470 */
3471
3472 switch (crtc->fb->depth) {
3473 case 8:
3474 bpc = 8; /* since we go through a colormap */
3475 break;
3476 case 15:
3477 case 16:
3478 bpc = 6; /* min is 18bpp */
3479 break;
3480 case 24:
578393cd 3481 bpc = 8;
5a354204
JB		 3482 break;
3483 case 30:
578393cd 3484 bpc = 10;
5a354204
JB		 3485 break;
3486 case 48:
578393cd 3487 bpc = 12;
5a354204
JB		 3488 break;
3489 default:
3490 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3491 bpc = min((unsigned int)8, display_bpc);
3492 break;
3493 }
3494
578393cd
KP		 3495 display_bpc = min(display_bpc, bpc);
3496
82820490
AJ		 3497 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3498 bpc, display_bpc);
5a354204 3499
578393cd 3500 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3501
3502 return display_bpc != bpc;
3503}
3504
c65d77d8
JB		 3505static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3506{
3507 struct drm_device *dev = crtc->dev;
3508 struct drm_i915_private *dev_priv = dev->dev_private;
3509 int refclk;
3510
3511 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3512 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3513 refclk = dev_priv->lvds_ssc_freq * 1000;
3514 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3515 refclk / 1000);
3516 } else if (!IS_GEN2(dev)) {
3517 refclk = 96000;
3518 } else {
3519 refclk = 48000;
3520 }
3521
3522 return refclk;
3523}
3524
3525static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3526 intel_clock_t *clock)
3527{
3528 /* SDVO TV has fixed PLL values depend on its clock range,
3529 this mirrors vbios setting. */
3530 if (adjusted_mode->clock >= 100000
3531 && adjusted_mode->clock < 140500) {
3532 clock->p1 = 2;
3533 clock->p2 = 10;
3534 clock->n = 3;
3535 clock->m1 = 16;
3536 clock->m2 = 8;
3537 } else if (adjusted_mode->clock >= 140500
3538 && adjusted_mode->clock <= 200000) {
3539 clock->p1 = 1;
3540 clock->p2 = 10;
3541 clock->n = 6;
3542 clock->m1 = 12;
3543 clock->m2 = 8;
3544 }
3545}
3546
a7516a05
JB		 3547static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3548 intel_clock_t *clock,
3549 intel_clock_t *reduced_clock)
3550{
3551 struct drm_device *dev = crtc->dev;
3552 struct drm_i915_private *dev_priv = dev->dev_private;
3553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3554 int pipe = intel_crtc->pipe;
3555 u32 fp, fp2 = 0;
3556
3557 if (IS_PINEVIEW(dev)) {
3558 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3559 if (reduced_clock)
3560 fp2 = (1 << reduced_clock->n) << 16 |
3561 reduced_clock->m1 << 8 | reduced_clock->m2;
3562 } else {
3563 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3564 if (reduced_clock)
3565 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3566 reduced_clock->m2;
3567 }
3568
3569 I915_WRITE(FP0(pipe), fp);
3570
3571 intel_crtc->lowfreq_avail = false;
3572 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3573 reduced_clock && i915_powersave) {
3574 I915_WRITE(FP1(pipe), fp2);
3575 intel_crtc->lowfreq_avail = true;
3576 } else {
3577 I915_WRITE(FP1(pipe), fp);
3578 }
3579}
3580
93e537a1
DV		 3581static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3582 struct drm_display_mode *adjusted_mode)
3583{
3584 struct drm_device *dev = crtc->dev;
3585 struct drm_i915_private *dev_priv = dev->dev_private;
3586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3587 int pipe = intel_crtc->pipe;
284d5df5 3588 u32 temp;
93e537a1
DV		 3589
3590 temp = I915_READ(LVDS);
3591 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3592 if (pipe == 1) {
3593 temp |= LVDS_PIPEB_SELECT;
3594 } else {
3595 temp &= ~LVDS_PIPEB_SELECT;
3596 }
3597 /* set the corresponsding LVDS_BORDER bit */
3598 temp |= dev_priv->lvds_border_bits;
3599 /* Set the B0-B3 data pairs corresponding to whether we're going to
3600 * set the DPLLs for dual-channel mode or not.
3601 */
3602 if (clock->p2 == 7)
3603 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3604 else
3605 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3606
3607 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3608 * appropriately here, but we need to look more thoroughly into how
3609 * panels behave in the two modes.
3610 */
3611 /* set the dithering flag on LVDS as needed */
3612 if (INTEL_INFO(dev)->gen >= 4) {
3613 if (dev_priv->lvds_dither)
3614 temp |= LVDS_ENABLE_DITHER;
3615 else
3616 temp &= ~LVDS_ENABLE_DITHER;
3617 }
284d5df5 3618 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 3619 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 3620 temp |= LVDS_HSYNC_POLARITY;
93e537a1 3621 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 3622 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 3623 I915_WRITE(LVDS, temp);
3624}
3625
eb1cbe48
DV		 3626static void i9xx_update_pll(struct drm_crtc *crtc,
3627 struct drm_display_mode *mode,
3628 struct drm_display_mode *adjusted_mode,
3629 intel_clock_t *clock, intel_clock_t *reduced_clock,
3630 int num_connectors)
3631{
3632 struct drm_device *dev = crtc->dev;
3633 struct drm_i915_private *dev_priv = dev->dev_private;
3634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3635 int pipe = intel_crtc->pipe;
3636 u32 dpll;
3637 bool is_sdvo;
3638
3639 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3640 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3641
3642 dpll = DPLL_VGA_MODE_DIS;
3643
3644 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3645 dpll |= DPLLB_MODE_LVDS;
3646 else
3647 dpll |= DPLLB_MODE_DAC_SERIAL;
3648 if (is_sdvo) {
3649 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3650 if (pixel_multiplier > 1) {
3651 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3652 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3653 }
3654 dpll |= DPLL_DVO_HIGH_SPEED;
3655 }
3656 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3657 dpll |= DPLL_DVO_HIGH_SPEED;
3658
3659 /* compute bitmask from p1 value */
3660 if (IS_PINEVIEW(dev))
3661 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3662 else {
3663 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3664 if (IS_G4X(dev) && reduced_clock)
3665 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3666 }
3667 switch (clock->p2) {
3668 case 5:
3669 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3670 break;
3671 case 7:
3672 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3673 break;
3674 case 10:
3675 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3676 break;
3677 case 14:
3678 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3679 break;
3680 }
3681 if (INTEL_INFO(dev)->gen >= 4)
3682 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3683
3684 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3685 dpll |= PLL_REF_INPUT_TVCLKINBC;
3686 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3687 /* XXX: just matching BIOS for now */
3688 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3689 dpll |= 3;
3690 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3691 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3692 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3693 else
3694 dpll |= PLL_REF_INPUT_DREFCLK;
3695
3696 dpll |= DPLL_VCO_ENABLE;
3697 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3698 POSTING_READ(DPLL(pipe));
3699 udelay(150);
3700
3701 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3702 * This is an exception to the general rule that mode_set doesn't turn
3703 * things on.
3704 */
3705 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3706 intel_update_lvds(crtc, clock, adjusted_mode);
3707
3708 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3709 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3710
3711 I915_WRITE(DPLL(pipe), dpll);
3712
3713 /* Wait for the clocks to stabilize. */
3714 POSTING_READ(DPLL(pipe));
3715 udelay(150);
3716
3717 if (INTEL_INFO(dev)->gen >= 4) {
3718 u32 temp = 0;
3719 if (is_sdvo) {
3720 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3721 if (temp > 1)
3722 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3723 else
3724 temp = 0;
3725 }
3726 I915_WRITE(DPLL_MD(pipe), temp);
3727 } else {
3728 /* The pixel multiplier can only be updated once the
3729 * DPLL is enabled and the clocks are stable.
3730 *
3731 * So write it again.
3732 */
3733 I915_WRITE(DPLL(pipe), dpll);
3734 }
3735}
3736
3737static void i8xx_update_pll(struct drm_crtc *crtc,
3738 struct drm_display_mode *adjusted_mode,
3739 intel_clock_t *clock,
3740 int num_connectors)
3741{
3742 struct drm_device *dev = crtc->dev;
3743 struct drm_i915_private *dev_priv = dev->dev_private;
3744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3745 int pipe = intel_crtc->pipe;
3746 u32 dpll;
3747
3748 dpll = DPLL_VGA_MODE_DIS;
3749
3750 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3751 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3752 } else {
3753 if (clock->p1 == 2)
3754 dpll |= PLL_P1_DIVIDE_BY_TWO;
3755 else
3756 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3757 if (clock->p2 == 4)
3758 dpll |= PLL_P2_DIVIDE_BY_4;
3759 }
3760
3761 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3762 /* XXX: just matching BIOS for now */
3763 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3764 dpll |= 3;
3765 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3766 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3767 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3768 else
3769 dpll |= PLL_REF_INPUT_DREFCLK;
3770
3771 dpll |= DPLL_VCO_ENABLE;
3772 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3773 POSTING_READ(DPLL(pipe));
3774 udelay(150);
3775
3776 I915_WRITE(DPLL(pipe), dpll);
3777
3778 /* Wait for the clocks to stabilize. */
3779 POSTING_READ(DPLL(pipe));
3780 udelay(150);
3781
3782 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3783 * This is an exception to the general rule that mode_set doesn't turn
3784 * things on.
3785 */
3786 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3787 intel_update_lvds(crtc, clock, adjusted_mode);
3788
3789 /* The pixel multiplier can only be updated once the
3790 * DPLL is enabled and the clocks are stable.
3791 *
3792 * So write it again.
3793 */
3794 I915_WRITE(DPLL(pipe), dpll);
3795}
3796
f564048e
EA		 3797static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3798 struct drm_display_mode *mode,
3799 struct drm_display_mode *adjusted_mode,
3800 int x, int y,
3801 struct drm_framebuffer *old_fb)
79e53945
JB		 3802{
3803 struct drm_device *dev = crtc->dev;
3804 struct drm_i915_private *dev_priv = dev->dev_private;
3805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3806 int pipe = intel_crtc->pipe;
80824003 3807 int plane = intel_crtc->plane;
c751ce4f 3808 int refclk, num_connectors = 0;
652c393a 3809 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 3810 u32 dspcntr, pipeconf, vsyncshift;
3811 bool ok, has_reduced_clock = false, is_sdvo = false;
3812 bool is_lvds = false, is_tv = false, is_dp = false;
79e53945 3813 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 3814 struct intel_encoder *encoder;
d4906093 3815 const intel_limit_t *limit;
5c3b82e2 3816 int ret;
79e53945 3817
5eddb70b
CW		 3818 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3819 if (encoder->base.crtc != crtc)
79e53945
JB		 3820 continue;
3821
5eddb70b 3822 switch (encoder->type) {
79e53945
JB		 3823 case INTEL_OUTPUT_LVDS:
3824 is_lvds = true;
3825 break;
3826 case INTEL_OUTPUT_SDVO:
7d57382e 3827 case INTEL_OUTPUT_HDMI:
79e53945 3828 is_sdvo = true;
5eddb70b 3829 if (encoder->needs_tv_clock)
e2f0ba97 3830 is_tv = true;
79e53945 3831 break;
79e53945
JB		 3832 case INTEL_OUTPUT_TVOUT:
3833 is_tv = true;
3834 break;
a4fc5ed6
KP		 3835 case INTEL_OUTPUT_DISPLAYPORT:
3836 is_dp = true;
3837 break;
79e53945 3838 }
43565a06 3839
c751ce4f 3840 num_connectors++;
79e53945
JB		 3841 }
3842
c65d77d8 3843 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 3844
d4906093
ML		 3845 /*
3846 * Returns a set of divisors for the desired target clock with the given
3847 * refclk, or FALSE. The returned values represent the clock equation:
3848 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3849 */
1b894b59 3850 limit = intel_limit(crtc, refclk);
cec2f356
SP		 3851 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3852 &clock);
79e53945
JB		 3853 if (!ok) {
3854 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 3855 return -EINVAL;
79e53945
JB		 3856 }
3857
cda4b7d3 3858 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 3859 intel_crtc_update_cursor(crtc, true);
cda4b7d3 3860
ddc9003c 3861 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 3862 /*
3863 * Ensure we match the reduced clock's P to the target clock.
3864 * If the clocks don't match, we can't switch the display clock
3865 * by using the FP0/FP1. In such case we will disable the LVDS
3866 * downclock feature.
3867 */
ddc9003c 3868 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 3869 dev_priv->lvds_downclock,
3870 refclk,
cec2f356 3871 &clock,
5eddb70b 3872 &reduced_clock);
7026d4ac
ZW		 3873 }
3874
c65d77d8
JB		 3875 if (is_sdvo && is_tv)
3876 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 3877
a7516a05
JB		 3878 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
3879 &reduced_clock : NULL);
79e53945 3880
eb1cbe48
DV		 3881 if (IS_GEN2(dev))
3882 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
79e53945 3883 else
eb1cbe48
DV		 3884 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
3885 has_reduced_clock ? &reduced_clock : NULL,
3886 num_connectors);
79e53945
JB		 3887
3888 /* setup pipeconf */
5eddb70b 3889 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 3890
3891 /* Set up the display plane register */
3892 dspcntr = DISPPLANE_GAMMA_ENABLE;
3893
929c77fb
EA		 3894 if (pipe == 0)
3895 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3896 else
3897 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 3898
a6c45cf0 3899 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 3900 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3901 * core speed.
3902 *
3903 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3904 * pipe == 0 check?
3905 */
e70236a8
JB		 3906 if (mode->clock >
3907 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 3908 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 3909 else
5eddb70b 3910 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 3911 }
3912
3b5c78a3
AJ		 3913 /* default to 8bpc */
3914 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
3915 if (is_dp) {
3916 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3917 pipeconf |= PIPECONF_BPP_6 |
3918 PIPECONF_DITHER_EN |
3919 PIPECONF_DITHER_TYPE_SP;
3920 }
3921 }
3922
28c97730 3923 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 3924 drm_mode_debug_printmodeline(mode);
3925
a7516a05
JB		 3926 if (HAS_PIPE_CXSR(dev)) {
3927 if (intel_crtc->lowfreq_avail) {
28c97730 3928 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 3929 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 3930 } else {
28c97730 3931 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 3932 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3933 }
3934 }
3935
617cf884 3936 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 3937 if (!IS_GEN2(dev) &&
3938 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 3939 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3940 /* the chip adds 2 halflines automatically */
734b4157 3941 adjusted_mode->crtc_vtotal -= 1;
734b4157 3942 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 3943 vsyncshift = adjusted_mode->crtc_hsync_start
3944 - adjusted_mode->crtc_htotal/2;
3945 } else {
617cf884 3946 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 3947 vsyncshift = 0;
3948 }
3949
3950 if (!IS_GEN3(dev))
3951 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 3952
5eddb70b
CW		 3953 I915_WRITE(HTOTAL(pipe),
3954 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 3955 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 3956 I915_WRITE(HBLANK(pipe),
3957 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 3958 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 3959 I915_WRITE(HSYNC(pipe),
3960 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 3961 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 3962
3963 I915_WRITE(VTOTAL(pipe),
3964 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 3965 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 3966 I915_WRITE(VBLANK(pipe),
3967 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 3968 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 3969 I915_WRITE(VSYNC(pipe),
3970 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 3971 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 3972
3973 /* pipesrc and dspsize control the size that is scaled from,
3974 * which should always be the user's requested size.
79e53945 3975 */
929c77fb
EA		 3976 I915_WRITE(DSPSIZE(plane),
3977 ((mode->vdisplay - 1) << 16) |
3978 (mode->hdisplay - 1));
3979 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 3980 I915_WRITE(PIPESRC(pipe),
3981 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 3982
f564048e
EA		 3983 I915_WRITE(PIPECONF(pipe), pipeconf);
3984 POSTING_READ(PIPECONF(pipe));
929c77fb 3985 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 3986
3987 intel_wait_for_vblank(dev, pipe);
3988
f564048e
EA		 3989 I915_WRITE(DSPCNTR(plane), dspcntr);
3990 POSTING_READ(DSPCNTR(plane));
3991
3992 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3993
3994 intel_update_watermarks(dev);
3995
f564048e
EA		 3996 return ret;
3997}
3998
9fb526db
KP		 3999/*
4000 * Initialize reference clocks when the driver loads
4001 */
4002void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4003{
4004 struct drm_i915_private *dev_priv = dev->dev_private;
4005 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4006 struct intel_encoder *encoder;
13d83a67
JB		 4007 u32 temp;
4008 bool has_lvds = false;
199e5d79
KP		 4009 bool has_cpu_edp = false;
4010 bool has_pch_edp = false;
4011 bool has_panel = false;
99eb6a01
KP		 4012 bool has_ck505 = false;
4013 bool can_ssc = false;
13d83a67
JB		 4014
4015 /* We need to take the global config into account */
199e5d79
KP		 4016 list_for_each_entry(encoder, &mode_config->encoder_list,
4017 base.head) {
4018 switch (encoder->type) {
4019 case INTEL_OUTPUT_LVDS:
4020 has_panel = true;
4021 has_lvds = true;
4022 break;
4023 case INTEL_OUTPUT_EDP:
4024 has_panel = true;
4025 if (intel_encoder_is_pch_edp(&encoder->base))
4026 has_pch_edp = true;
4027 else
4028 has_cpu_edp = true;
4029 break;
13d83a67
JB		 4030 }
4031 }
4032
99eb6a01
KP		 4033 if (HAS_PCH_IBX(dev)) {
4034 has_ck505 = dev_priv->display_clock_mode;
4035 can_ssc = has_ck505;
4036 } else {
4037 has_ck505 = false;
4038 can_ssc = true;
4039 }
4040
4041 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4042 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4043 has_ck505);
13d83a67
JB		 4044
4045 /* Ironlake: try to setup display ref clock before DPLL
4046 * enabling. This is only under driver's control after
4047 * PCH B stepping, previous chipset stepping should be
4048 * ignoring this setting.
4049 */
4050 temp = I915_READ(PCH_DREF_CONTROL);
4051 /* Always enable nonspread source */
4052 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4053
99eb6a01
KP		 4054 if (has_ck505)
4055 temp |= DREF_NONSPREAD_CK505_ENABLE;
4056 else
4057 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4058
199e5d79
KP		 4059 if (has_panel) {
4060 temp &= ~DREF_SSC_SOURCE_MASK;
4061 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4062
199e5d79 4063 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4064 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4065 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4066 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4067 } else
4068 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4069
4070 /* Get SSC going before enabling the outputs */
4071 I915_WRITE(PCH_DREF_CONTROL, temp);
4072 POSTING_READ(PCH_DREF_CONTROL);
4073 udelay(200);
4074
13d83a67
JB		 4075 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4076
4077 /* Enable CPU source on CPU attached eDP */
199e5d79 4078 if (has_cpu_edp) {
99eb6a01 4079 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4080 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4081 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4082 }
13d83a67
JB		 4083 else
4084 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4085 } else
4086 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4087
4088 I915_WRITE(PCH_DREF_CONTROL, temp);
4089 POSTING_READ(PCH_DREF_CONTROL);
4090 udelay(200);
4091 } else {
4092 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4093
4094 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4095
4096 /* Turn off CPU output */
4097 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4098
4099 I915_WRITE(PCH_DREF_CONTROL, temp);
4100 POSTING_READ(PCH_DREF_CONTROL);
4101 udelay(200);
4102
4103 /* Turn off the SSC source */
4104 temp &= ~DREF_SSC_SOURCE_MASK;
4105 temp |= DREF_SSC_SOURCE_DISABLE;
4106
4107 /* Turn off SSC1 */
4108 temp &= ~ DREF_SSC1_ENABLE;
4109
13d83a67
JB		 4110 I915_WRITE(PCH_DREF_CONTROL, temp);
4111 POSTING_READ(PCH_DREF_CONTROL);
4112 udelay(200);
4113 }
4114}
4115
d9d444cb
JB		 4116static int ironlake_get_refclk(struct drm_crtc *crtc)
4117{
4118 struct drm_device *dev = crtc->dev;
4119 struct drm_i915_private *dev_priv = dev->dev_private;
4120 struct intel_encoder *encoder;
4121 struct drm_mode_config *mode_config = &dev->mode_config;
4122 struct intel_encoder *edp_encoder = NULL;
4123 int num_connectors = 0;
4124 bool is_lvds = false;
4125
4126 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4127 if (encoder->base.crtc != crtc)
4128 continue;
4129
4130 switch (encoder->type) {
4131 case INTEL_OUTPUT_LVDS:
4132 is_lvds = true;
4133 break;
4134 case INTEL_OUTPUT_EDP:
4135 edp_encoder = encoder;
4136 break;
4137 }
4138 num_connectors++;
4139 }
4140
4141 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4142 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4143 dev_priv->lvds_ssc_freq);
4144 return dev_priv->lvds_ssc_freq * 1000;
4145 }
4146
4147 return 120000;
4148}
4149
f564048e
EA		 4150static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4151 struct drm_display_mode *mode,
4152 struct drm_display_mode *adjusted_mode,
4153 int x, int y,
4154 struct drm_framebuffer *old_fb)
79e53945
JB		 4155{
4156 struct drm_device *dev = crtc->dev;
4157 struct drm_i915_private *dev_priv = dev->dev_private;
4158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4159 int pipe = intel_crtc->pipe;
80824003 4160 int plane = intel_crtc->plane;
c751ce4f 4161 int refclk, num_connectors = 0;
652c393a 4162 intel_clock_t clock, reduced_clock;
5eddb70b 4163 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4164 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4165 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4166 struct drm_mode_config *mode_config = &dev->mode_config;
e3aef172 4167 struct intel_encoder *encoder, *edp_encoder = NULL;
d4906093 4168 const intel_limit_t *limit;
5c3b82e2 4169 int ret;
2c07245f 4170 struct fdi_m_n m_n = {0};
fae14981 4171 u32 temp;
5a354204
JB		 4172 int target_clock, pixel_multiplier, lane, link_bw, factor;
4173 unsigned int pipe_bpp;
4174 bool dither;
e3aef172 4175 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4176
5eddb70b
CW		 4177 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4178 if (encoder->base.crtc != crtc)
79e53945
JB		 4179 continue;
4180
5eddb70b 4181 switch (encoder->type) {
79e53945
JB		 4182 case INTEL_OUTPUT_LVDS:
4183 is_lvds = true;
4184 break;
4185 case INTEL_OUTPUT_SDVO:
7d57382e 4186 case INTEL_OUTPUT_HDMI:
79e53945 4187 is_sdvo = true;
5eddb70b 4188 if (encoder->needs_tv_clock)
e2f0ba97 4189 is_tv = true;
79e53945 4190 break;
79e53945
JB		 4191 case INTEL_OUTPUT_TVOUT:
4192 is_tv = true;
4193 break;
4194 case INTEL_OUTPUT_ANALOG:
4195 is_crt = true;
4196 break;
a4fc5ed6
KP		 4197 case INTEL_OUTPUT_DISPLAYPORT:
4198 is_dp = true;
4199 break;
32f9d658 4200 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4201 is_dp = true;
4202 if (intel_encoder_is_pch_edp(&encoder->base))
4203 is_pch_edp = true;
4204 else
4205 is_cpu_edp = true;
4206 edp_encoder = encoder;
32f9d658 4207 break;
79e53945 4208 }
43565a06 4209
c751ce4f 4210 num_connectors++;
79e53945
JB		 4211 }
4212
d9d444cb 4213 refclk = ironlake_get_refclk(crtc);
79e53945 4214
d4906093
ML		 4215 /*
4216 * Returns a set of divisors for the desired target clock with the given
4217 * refclk, or FALSE. The returned values represent the clock equation:
4218 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4219 */
1b894b59 4220 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4221 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4222 &clock);
79e53945
JB		 4223 if (!ok) {
4224 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4225 return -EINVAL;
79e53945
JB		 4226 }
4227
cda4b7d3 4228 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4229 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4230
ddc9003c 4231 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4232 /*
4233 * Ensure we match the reduced clock's P to the target clock.
4234 * If the clocks don't match, we can't switch the display clock
4235 * by using the FP0/FP1. In such case we will disable the LVDS
4236 * downclock feature.
4237 */
ddc9003c 4238 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4239 dev_priv->lvds_downclock,
4240 refclk,
cec2f356 4241 &clock,
5eddb70b 4242 &reduced_clock);
652c393a 4243 }
7026d4ac
ZW		 4244 /* SDVO TV has fixed PLL values depend on its clock range,
4245 this mirrors vbios setting. */
4246 if (is_sdvo && is_tv) {
4247 if (adjusted_mode->clock >= 100000
5eddb70b 4248 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4249 clock.p1 = 2;
4250 clock.p2 = 10;
4251 clock.n = 3;
4252 clock.m1 = 16;
4253 clock.m2 = 8;
4254 } else if (adjusted_mode->clock >= 140500
5eddb70b 4255 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4256 clock.p1 = 1;
4257 clock.p2 = 10;
4258 clock.n = 6;
4259 clock.m1 = 12;
4260 clock.m2 = 8;
4261 }
4262 }
4263
2c07245f 4264 /* FDI link */
8febb297
EA		 4265 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4266 lane = 0;
4267 /* CPU eDP doesn't require FDI link, so just set DP M/N
4268 according to current link config */
e3aef172 4269 if (is_cpu_edp) {
8febb297 4270 target_clock = mode->clock;
e3aef172 4271 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297
EA		 4272 } else {
4273 /* [e]DP over FDI requires target mode clock
4274 instead of link clock */
e3aef172 4275 if (is_dp)
5eb08b69 4276 target_clock = mode->clock;
8febb297
EA		 4277 else
4278 target_clock = adjusted_mode->clock;
4279
4280 /* FDI is a binary signal running at ~2.7GHz, encoding
4281 * each output octet as 10 bits. The actual frequency
4282 * is stored as a divider into a 100MHz clock, and the
4283 * mode pixel clock is stored in units of 1KHz.
4284 * Hence the bw of each lane in terms of the mode signal
4285 * is:
4286 */
4287 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4288 }
58a27471 4289
8febb297
EA		 4290 /* determine panel color depth */
4291 temp = I915_READ(PIPECONF(pipe));
4292 temp &= ~PIPE_BPC_MASK;
3b5c78a3 4293 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 4294 switch (pipe_bpp) {
4295 case 18:
4296 temp |= PIPE_6BPC;
8febb297 4297 break;
5a354204
JB		 4298 case 24:
4299 temp |= PIPE_8BPC;
8febb297 4300 break;
5a354204
JB		 4301 case 30:
4302 temp |= PIPE_10BPC;
8febb297 4303 break;
5a354204
JB		 4304 case 36:
4305 temp |= PIPE_12BPC;
8febb297
EA		 4306 break;
4307 default:
62ac41a6
JB		 4308 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4309 pipe_bpp);
5a354204
JB		 4310 temp |= PIPE_8BPC;
4311 pipe_bpp = 24;
4312 break;
8febb297 4313 }
77ffb597 4314
5a354204
JB		 4315 intel_crtc->bpp = pipe_bpp;
4316 I915_WRITE(PIPECONF(pipe), temp);
4317
8febb297
EA		 4318 if (!lane) {
4319 /*
4320 * Account for spread spectrum to avoid
4321 * oversubscribing the link. Max center spread
4322 * is 2.5%; use 5% for safety's sake.
4323 */
5a354204 4324 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4325 lane = bps / (link_bw * 8) + 1;
5eb08b69 4326 }
2c07245f 4327
8febb297
EA		 4328 intel_crtc->fdi_lanes = lane;
4329
4330 if (pixel_multiplier > 1)
4331 link_bw *= pixel_multiplier;
5a354204
JB		 4332 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4333 &m_n);
8febb297 4334
a07d6787
EA		 4335 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4336 if (has_reduced_clock)
4337 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4338 reduced_clock.m2;
79e53945 4339
c1858123 4340 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4341 factor = 21;
4342 if (is_lvds) {
4343 if ((intel_panel_use_ssc(dev_priv) &&
4344 dev_priv->lvds_ssc_freq == 100) ||
4345 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4346 factor = 25;
4347 } else if (is_sdvo && is_tv)
4348 factor = 20;
c1858123 4349
cb0e0931 4350 if (clock.m < factor * clock.n)
8febb297 4351 fp |= FP_CB_TUNE;
2c07245f 4352
5eddb70b 4353 dpll = 0;
2c07245f 4354
a07d6787
EA		 4355 if (is_lvds)
4356 dpll |= DPLLB_MODE_LVDS;
4357 else
4358 dpll |= DPLLB_MODE_DAC_SERIAL;
4359 if (is_sdvo) {
4360 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4361 if (pixel_multiplier > 1) {
4362 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4363 }
a07d6787
EA		 4364 dpll |= DPLL_DVO_HIGH_SPEED;
4365 }
e3aef172 4366 if (is_dp && !is_cpu_edp)
a07d6787 4367 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4368
a07d6787
EA		 4369 /* compute bitmask from p1 value */
4370 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4371 /* also FPA1 */
4372 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4373
4374 switch (clock.p2) {
4375 case 5:
4376 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4377 break;
4378 case 7:
4379 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4380 break;
4381 case 10:
4382 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4383 break;
4384 case 14:
4385 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4386 break;
79e53945
JB		 4387 }
4388
43565a06
KH		 4389 if (is_sdvo && is_tv)
4390 dpll |= PLL_REF_INPUT_TVCLKINBC;
4391 else if (is_tv)
79e53945 4392 /* XXX: just matching BIOS for now */
43565a06 4393 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4394 dpll |= 3;
a7615030 4395 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4396 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4397 else
4398 dpll |= PLL_REF_INPUT_DREFCLK;
4399
4400 /* setup pipeconf */
5eddb70b 4401 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4402
4403 /* Set up the display plane register */
4404 dspcntr = DISPPLANE_GAMMA_ENABLE;
4405
f7cb34d4 4406 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4407 drm_mode_debug_printmodeline(mode);
4408
ee7b9f93
JB		 4409 /* CPU eDP is the only output that doesn't need a PCH PLL of its own */
4410 if (!is_cpu_edp) {
4411 struct intel_pch_pll *pll;
4b645f14 4412
ee7b9f93
JB		 4413 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4414 if (pll == NULL) {
4415 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4416 pipe);
4b645f14
JB		 4417 return -EINVAL;
4418 }
ee7b9f93
JB		 4419 } else
4420 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4421
4422 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4423 * This is an exception to the general rule that mode_set doesn't turn
4424 * things on.
4425 */
4426 if (is_lvds) {
fae14981 4427 temp = I915_READ(PCH_LVDS);
5eddb70b 4428 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4429 if (HAS_PCH_CPT(dev)) {
4430 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4431 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4432 } else {
4433 if (pipe == 1)
4434 temp |= LVDS_PIPEB_SELECT;
4435 else
4436 temp &= ~LVDS_PIPEB_SELECT;
4437 }
4b645f14 4438
a3e17eb8 4439 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4440 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4441 /* Set the B0-B3 data pairs corresponding to whether we're going to
4442 * set the DPLLs for dual-channel mode or not.
4443 */
4444 if (clock.p2 == 7)
5eddb70b 4445 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4446 else
5eddb70b 4447 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4448
4449 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4450 * appropriately here, but we need to look more thoroughly into how
4451 * panels behave in the two modes.
4452 */
284d5df5 4453 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4454 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4455 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4456 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4457 temp |= LVDS_VSYNC_POLARITY;
fae14981 4458 I915_WRITE(PCH_LVDS, temp);
79e53945 4459 }
434ed097 4460
8febb297
EA		 4461 pipeconf &= ~PIPECONF_DITHER_EN;
4462 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 4463 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 4464 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 4465 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 4466 }
e3aef172 4467 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4468 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4469 } else {
8db9d77b 4470 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4471 I915_WRITE(TRANSDATA_M1(pipe), 0);
4472 I915_WRITE(TRANSDATA_N1(pipe), 0);
4473 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4474 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4475 }
79e53945 4476
ee7b9f93
JB		 4477 if (intel_crtc->pch_pll) {
4478 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4479
32f9d658 4480 /* Wait for the clocks to stabilize. */
ee7b9f93 4481 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4482 udelay(150);
4483
8febb297
EA		 4484 /* The pixel multiplier can only be updated once the
4485 * DPLL is enabled and the clocks are stable.
4486 *
4487 * So write it again.
4488 */
ee7b9f93 4489 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 4490 }
79e53945 4491
5eddb70b 4492 intel_crtc->lowfreq_avail = false;
ee7b9f93 4493 if (intel_crtc->pch_pll) {
4b645f14 4494 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 4495 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14
JB		 4496 intel_crtc->lowfreq_avail = true;
4497 if (HAS_PIPE_CXSR(dev)) {
4498 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4499 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4500 }
4501 } else {
ee7b9f93 4502 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4b645f14
JB		 4503 if (HAS_PIPE_CXSR(dev)) {
4504 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4505 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4506 }
652c393a
JB		 4507 }
4508 }
4509
617cf884 4510 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 4511 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 4512 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 4513 /* the chip adds 2 halflines automatically */
734b4157 4514 adjusted_mode->crtc_vtotal -= 1;
734b4157 4515 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4516 I915_WRITE(VSYNCSHIFT(pipe),
4517 adjusted_mode->crtc_hsync_start
4518 - adjusted_mode->crtc_htotal/2);
4519 } else {
617cf884 4520 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4521 I915_WRITE(VSYNCSHIFT(pipe), 0);
4522 }
734b4157 4523
5eddb70b
CW		 4524 I915_WRITE(HTOTAL(pipe),
4525 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4526 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4527 I915_WRITE(HBLANK(pipe),
4528 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4529 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4530 I915_WRITE(HSYNC(pipe),
4531 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4532 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4533
4534 I915_WRITE(VTOTAL(pipe),
4535 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4536 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4537 I915_WRITE(VBLANK(pipe),
4538 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4539 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4540 I915_WRITE(VSYNC(pipe),
4541 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4542 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 4543
8febb297
EA		 4544 /* pipesrc controls the size that is scaled from, which should
4545 * always be the user's requested size.
79e53945 4546 */
5eddb70b
CW		 4547 I915_WRITE(PIPESRC(pipe),
4548 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4549
8febb297
EA		 4550 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4551 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4552 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4553 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 4554
e3aef172 4555 if (is_cpu_edp)
8febb297 4556 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 4557
5eddb70b
CW		 4558 I915_WRITE(PIPECONF(pipe), pipeconf);
4559 POSTING_READ(PIPECONF(pipe));
79e53945 4560
9d0498a2 4561 intel_wait_for_vblank(dev, pipe);
79e53945 4562
5eddb70b 4563 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 4564 POSTING_READ(DSPCNTR(plane));
79e53945 4565
5c3b82e2 4566 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 4567
4568 intel_update_watermarks(dev);
4569
1f803ee5 4570 return ret;
79e53945
JB		 4571}
4572
f564048e
EA		 4573static int intel_crtc_mode_set(struct drm_crtc *crtc,
4574 struct drm_display_mode *mode,
4575 struct drm_display_mode *adjusted_mode,
4576 int x, int y,
4577 struct drm_framebuffer *old_fb)
4578{
4579 struct drm_device *dev = crtc->dev;
4580 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 4581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4582 int pipe = intel_crtc->pipe;
f564048e
EA		 4583 int ret;
4584
0b701d27 4585 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 4586
f564048e
EA		 4587 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4588 x, y, old_fb);
79e53945 4589 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 4590
d8e70a25
JB		 4591 if (ret)
4592 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4593 else
4594 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 4595
1f803ee5 4596 return ret;
79e53945
JB		 4597}
4598
3a9627f4
WF		 4599static bool intel_eld_uptodate(struct drm_connector *connector,
4600 int reg_eldv, uint32_t bits_eldv,
4601 int reg_elda, uint32_t bits_elda,
4602 int reg_edid)
4603{
4604 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4605 uint8_t *eld = connector->eld;
4606 uint32_t i;
4607
4608 i = I915_READ(reg_eldv);
4609 i &= bits_eldv;
4610
4611 if (!eld[0])
4612 return !i;
4613
4614 if (!i)
4615 return false;
4616
4617 i = I915_READ(reg_elda);
4618 i &= ~bits_elda;
4619 I915_WRITE(reg_elda, i);
4620
4621 for (i = 0; i < eld[2]; i++)
4622 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4623 return false;
4624
4625 return true;
4626}
4627
e0dac65e
WF		 4628static void g4x_write_eld(struct drm_connector *connector,
4629 struct drm_crtc *crtc)
4630{
4631 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4632 uint8_t *eld = connector->eld;
4633 uint32_t eldv;
4634 uint32_t len;
4635 uint32_t i;
4636
4637 i = I915_READ(G4X_AUD_VID_DID);
4638
4639 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4640 eldv = G4X_ELDV_DEVCL_DEVBLC;
4641 else
4642 eldv = G4X_ELDV_DEVCTG;
4643
3a9627f4
WF		 4644 if (intel_eld_uptodate(connector,
4645 G4X_AUD_CNTL_ST, eldv,
4646 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4647 G4X_HDMIW_HDMIEDID))
4648 return;
4649
e0dac65e
WF		 4650 i = I915_READ(G4X_AUD_CNTL_ST);
4651 i &= ~(eldv | G4X_ELD_ADDR);
4652 len = (i >> 9) & 0x1f; /* ELD buffer size */
4653 I915_WRITE(G4X_AUD_CNTL_ST, i);
4654
4655 if (!eld[0])
4656 return;
4657
4658 len = min_t(uint8_t, eld[2], len);
4659 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4660 for (i = 0; i < len; i++)
4661 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4662
4663 i = I915_READ(G4X_AUD_CNTL_ST);
4664 i |= eldv;
4665 I915_WRITE(G4X_AUD_CNTL_ST, i);
4666}
4667
4668static void ironlake_write_eld(struct drm_connector *connector,
4669 struct drm_crtc *crtc)
4670{
4671 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4672 uint8_t *eld = connector->eld;
4673 uint32_t eldv;
4674 uint32_t i;
4675 int len;
4676 int hdmiw_hdmiedid;
b6daa025 4677 int aud_config;
e0dac65e
WF		 4678 int aud_cntl_st;
4679 int aud_cntrl_st2;
4680
b3f33cbf 4681 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6 4682 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
b6daa025 4683 aud_config = IBX_AUD_CONFIG_A;
1202b4c6
WF		 4684 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4685 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 4686 } else {
1202b4c6 4687 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
b6daa025 4688 aud_config = CPT_AUD_CONFIG_A;
1202b4c6
WF		 4689 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4690 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 4691 }
4692
4693 i = to_intel_crtc(crtc)->pipe;
4694 hdmiw_hdmiedid += i * 0x100;
4695 aud_cntl_st += i * 0x100;
b6daa025 4696 aud_config += i * 0x100;
e0dac65e
WF		 4697
4698 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4699
4700 i = I915_READ(aud_cntl_st);
4701 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4702 if (!i) {
4703 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4704 /* operate blindly on all ports */
1202b4c6
WF		 4705 eldv = IBX_ELD_VALIDB;
4706 eldv |= IBX_ELD_VALIDB << 4;
4707 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 4708 } else {
4709 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 4710 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 4711 }
4712
3a9627f4
WF		 4713 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4714 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4715 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 4716 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4717 } else
4718 I915_WRITE(aud_config, 0);
e0dac65e 4719
3a9627f4
WF		 4720 if (intel_eld_uptodate(connector,
4721 aud_cntrl_st2, eldv,
4722 aud_cntl_st, IBX_ELD_ADDRESS,
4723 hdmiw_hdmiedid))
4724 return;
4725
e0dac65e
WF		 4726 i = I915_READ(aud_cntrl_st2);
4727 i &= ~eldv;
4728 I915_WRITE(aud_cntrl_st2, i);
4729
4730 if (!eld[0])
4731 return;
4732
e0dac65e 4733 i = I915_READ(aud_cntl_st);
1202b4c6 4734 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 4735 I915_WRITE(aud_cntl_st, i);
4736
4737 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
4738 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4739 for (i = 0; i < len; i++)
4740 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4741
4742 i = I915_READ(aud_cntrl_st2);
4743 i |= eldv;
4744 I915_WRITE(aud_cntrl_st2, i);
4745}
4746
4747void intel_write_eld(struct drm_encoder *encoder,
4748 struct drm_display_mode *mode)
4749{
4750 struct drm_crtc *crtc = encoder->crtc;
4751 struct drm_connector *connector;
4752 struct drm_device *dev = encoder->dev;
4753 struct drm_i915_private *dev_priv = dev->dev_private;
4754
4755 connector = drm_select_eld(encoder, mode);
4756 if (!connector)
4757 return;
4758
4759 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4760 connector->base.id,
4761 drm_get_connector_name(connector),
4762 connector->encoder->base.id,
4763 drm_get_encoder_name(connector->encoder));
4764
4765 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4766
4767 if (dev_priv->display.write_eld)
4768 dev_priv->display.write_eld(connector, crtc);
4769}
4770
79e53945
JB		 4771/** Loads the palette/gamma unit for the CRTC with the prepared values */
4772void intel_crtc_load_lut(struct drm_crtc *crtc)
4773{
4774 struct drm_device *dev = crtc->dev;
4775 struct drm_i915_private *dev_priv = dev->dev_private;
4776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 4777 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 4778 int i;
4779
4780 /* The clocks have to be on to load the palette. */
aed3f09d 4781 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 4782 return;
4783
f2b115e6 4784 /* use legacy palette for Ironlake */
bad720ff 4785 if (HAS_PCH_SPLIT(dev))
9db4a9c7 4786 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 4787
79e53945
JB		 4788 for (i = 0; i < 256; i++) {
4789 I915_WRITE(palreg + 4 * i,
4790 (intel_crtc->lut_r[i] << 16) |
4791 (intel_crtc->lut_g[i] << 8) |
4792 intel_crtc->lut_b[i]);
4793 }
4794}
4795
560b85bb
CW		 4796static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4797{
4798 struct drm_device *dev = crtc->dev;
4799 struct drm_i915_private *dev_priv = dev->dev_private;
4800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4801 bool visible = base != 0;
4802 u32 cntl;
4803
4804 if (intel_crtc->cursor_visible == visible)
4805 return;
4806
9db4a9c7 4807 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 4808 if (visible) {
4809 /* On these chipsets we can only modify the base whilst
4810 * the cursor is disabled.
4811 */
9db4a9c7 4812 I915_WRITE(_CURABASE, base);
560b85bb
CW		 4813
4814 cntl &= ~(CURSOR_FORMAT_MASK);
4815 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4816 cntl |= CURSOR_ENABLE |
4817 CURSOR_GAMMA_ENABLE |
4818 CURSOR_FORMAT_ARGB;
4819 } else
4820 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 4821 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 4822
4823 intel_crtc->cursor_visible = visible;
4824}
4825
4826static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4827{
4828 struct drm_device *dev = crtc->dev;
4829 struct drm_i915_private *dev_priv = dev->dev_private;
4830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4831 int pipe = intel_crtc->pipe;
4832 bool visible = base != 0;
4833
4834 if (intel_crtc->cursor_visible != visible) {
548f245b 4835 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 4836 if (base) {
4837 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4838 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4839 cntl |= pipe << 28; /* Connect to correct pipe */
4840 } else {
4841 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4842 cntl |= CURSOR_MODE_DISABLE;
4843 }
9db4a9c7 4844 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 4845
4846 intel_crtc->cursor_visible = visible;
4847 }
4848 /* and commit changes on next vblank */
9db4a9c7 4849 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 4850}
4851
65a21cd6
JB		 4852static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4853{
4854 struct drm_device *dev = crtc->dev;
4855 struct drm_i915_private *dev_priv = dev->dev_private;
4856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4857 int pipe = intel_crtc->pipe;
4858 bool visible = base != 0;
4859
4860 if (intel_crtc->cursor_visible != visible) {
4861 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
4862 if (base) {
4863 cntl &= ~CURSOR_MODE;
4864 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4865 } else {
4866 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4867 cntl |= CURSOR_MODE_DISABLE;
4868 }
4869 I915_WRITE(CURCNTR_IVB(pipe), cntl);
4870
4871 intel_crtc->cursor_visible = visible;
4872 }
4873 /* and commit changes on next vblank */
4874 I915_WRITE(CURBASE_IVB(pipe), base);
4875}
4876
cda4b7d3 4877/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 4878static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4879 bool on)
cda4b7d3
CW		 4880{
4881 struct drm_device *dev = crtc->dev;
4882 struct drm_i915_private *dev_priv = dev->dev_private;
4883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4884 int pipe = intel_crtc->pipe;
4885 int x = intel_crtc->cursor_x;
4886 int y = intel_crtc->cursor_y;
560b85bb 4887 u32 base, pos;
cda4b7d3
CW		 4888 bool visible;
4889
4890 pos = 0;
4891
6b383a7f 4892 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 4893 base = intel_crtc->cursor_addr;
4894 if (x > (int) crtc->fb->width)
4895 base = 0;
4896
4897 if (y > (int) crtc->fb->height)
4898 base = 0;
4899 } else
4900 base = 0;
4901
4902 if (x < 0) {
4903 if (x + intel_crtc->cursor_width < 0)
4904 base = 0;
4905
4906 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4907 x = -x;
4908 }
4909 pos |= x << CURSOR_X_SHIFT;
4910
4911 if (y < 0) {
4912 if (y + intel_crtc->cursor_height < 0)
4913 base = 0;
4914
4915 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4916 y = -y;
4917 }
4918 pos |= y << CURSOR_Y_SHIFT;
4919
4920 visible = base != 0;
560b85bb 4921 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 4922 return;
4923
0cd83aa9 4924 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 4925 I915_WRITE(CURPOS_IVB(pipe), pos);
4926 ivb_update_cursor(crtc, base);
4927 } else {
4928 I915_WRITE(CURPOS(pipe), pos);
4929 if (IS_845G(dev) || IS_I865G(dev))
4930 i845_update_cursor(crtc, base);
4931 else
4932 i9xx_update_cursor(crtc, base);
4933 }
cda4b7d3
CW		 4934}
4935
79e53945 4936static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 4937 struct drm_file *file,
79e53945
JB		 4938 uint32_t handle,
4939 uint32_t width, uint32_t height)
4940{
4941 struct drm_device *dev = crtc->dev;
4942 struct drm_i915_private *dev_priv = dev->dev_private;
4943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 4944 struct drm_i915_gem_object *obj;
cda4b7d3 4945 uint32_t addr;
3f8bc370 4946 int ret;
79e53945 4947
28c97730 4948 DRM_DEBUG_KMS("\n");
79e53945
JB		 4949
4950 /* if we want to turn off the cursor ignore width and height */
4951 if (!handle) {
28c97730 4952 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 4953 addr = 0;
05394f39 4954 obj = NULL;
5004417d 4955 mutex_lock(&dev->struct_mutex);
3f8bc370 4956 goto finish;
79e53945
JB		 4957 }
4958
4959 /* Currently we only support 64x64 cursors */
4960 if (width != 64 || height != 64) {
4961 DRM_ERROR("we currently only support 64x64 cursors\n");
4962 return -EINVAL;
4963 }
4964
05394f39 4965 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 4966 if (&obj->base == NULL)
79e53945
JB		 4967 return -ENOENT;
4968
05394f39 4969 if (obj->base.size < width * height * 4) {
79e53945 4970 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 4971 ret = -ENOMEM;
4972 goto fail;
79e53945
JB		 4973 }
4974
71acb5eb 4975 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 4976 mutex_lock(&dev->struct_mutex);
b295d1b6 4977 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 4978 if (obj->tiling_mode) {
4979 DRM_ERROR("cursor cannot be tiled\n");
4980 ret = -EINVAL;
4981 goto fail_locked;
4982 }
4983
2da3b9b9 4984 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 4985 if (ret) {
4986 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 4987 goto fail_locked;
e7b526bb
CW		 4988 }
4989
d9e86c0e
CW		 4990 ret = i915_gem_object_put_fence(obj);
4991 if (ret) {
2da3b9b9 4992 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 4993 goto fail_unpin;
4994 }
4995
05394f39 4996 addr = obj->gtt_offset;
71acb5eb 4997 } else {
6eeefaf3 4998 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 4999 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5000 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5001 align);
71acb5eb
DA		 5002 if (ret) {
5003 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5004 goto fail_locked;
71acb5eb 5005 }
05394f39 5006 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5007 }
5008
a6c45cf0 5009 if (IS_GEN2(dev))
14b60391
JB		 5010 I915_WRITE(CURSIZE, (height << 12) | width);
5011
3f8bc370 5012 finish:
3f8bc370 5013 if (intel_crtc->cursor_bo) {
b295d1b6 5014 if (dev_priv->info->cursor_needs_physical) {
05394f39 5015 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5016 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5017 } else
5018 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5019 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5020 }
80824003 5021
7f9872e0 5022 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5023
5024 intel_crtc->cursor_addr = addr;
05394f39 5025 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5026 intel_crtc->cursor_width = width;
5027 intel_crtc->cursor_height = height;
5028
6b383a7f 5029 intel_crtc_update_cursor(crtc, true);
3f8bc370 5030
79e53945 5031 return 0;
e7b526bb 5032fail_unpin:
05394f39 5033 i915_gem_object_unpin(obj);
7f9872e0 5034fail_locked:
34b8686e 5035 mutex_unlock(&dev->struct_mutex);
bc9025bd 5036fail:
05394f39 5037 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5038 return ret;
79e53945
JB		 5039}
5040
5041static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5042{
79e53945 5043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5044
cda4b7d3
CW		 5045 intel_crtc->cursor_x = x;
5046 intel_crtc->cursor_y = y;
652c393a 5047
6b383a7f 5048 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5049
5050 return 0;
5051}
5052
5053/** Sets the color ramps on behalf of RandR */
5054void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5055 u16 blue, int regno)
5056{
5057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5058
5059 intel_crtc->lut_r[regno] = red >> 8;
5060 intel_crtc->lut_g[regno] = green >> 8;
5061 intel_crtc->lut_b[regno] = blue >> 8;
5062}
5063
b8c00ac5
DA		 5064void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5065 u16 *blue, int regno)
5066{
5067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5068
5069 *red = intel_crtc->lut_r[regno] << 8;
5070 *green = intel_crtc->lut_g[regno] << 8;
5071 *blue = intel_crtc->lut_b[regno] << 8;
5072}
5073
79e53945 5074static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5075 u16 *blue, uint32_t start, uint32_t size)
79e53945 5076{
7203425a 5077 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5079
7203425a 5080 for (i = start; i < end; i++) {
79e53945
JB		 5081 intel_crtc->lut_r[i] = red[i] >> 8;
5082 intel_crtc->lut_g[i] = green[i] >> 8;
5083 intel_crtc->lut_b[i] = blue[i] >> 8;
5084 }
5085
5086 intel_crtc_load_lut(crtc);
5087}
5088
5089/**
5090 * Get a pipe with a simple mode set on it for doing load-based monitor
5091 * detection.
5092 *
5093 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5094 * its requirements. The pipe will be connected to no other encoders.
79e53945 5095 *
c751ce4f 5096 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5097 * configured for it. In the future, it could choose to temporarily disable
5098 * some outputs to free up a pipe for its use.
5099 *
5100 * \return crtc, or NULL if no pipes are available.
5101 */
5102
5103/* VESA 640x480x72Hz mode to set on the pipe */
5104static struct drm_display_mode load_detect_mode = {
5105 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5106 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5107};
5108
d2dff872
CW		 5109static struct drm_framebuffer *
5110intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5111 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5112 struct drm_i915_gem_object *obj)
5113{
5114 struct intel_framebuffer *intel_fb;
5115 int ret;
5116
5117 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5118 if (!intel_fb) {
5119 drm_gem_object_unreference_unlocked(&obj->base);
5120 return ERR_PTR(-ENOMEM);
5121 }
5122
5123 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5124 if (ret) {
5125 drm_gem_object_unreference_unlocked(&obj->base);
5126 kfree(intel_fb);
5127 return ERR_PTR(ret);
5128 }
5129
5130 return &intel_fb->base;
5131}
5132
5133static u32
5134intel_framebuffer_pitch_for_width(int width, int bpp)
5135{
5136 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5137 return ALIGN(pitch, 64);
5138}
5139
5140static u32
5141intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5142{
5143 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5144 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5145}
5146
5147static struct drm_framebuffer *
5148intel_framebuffer_create_for_mode(struct drm_device *dev,
5149 struct drm_display_mode *mode,
5150 int depth, int bpp)
5151{
5152 struct drm_i915_gem_object *obj;
308e5bcb 5153 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5154
5155 obj = i915_gem_alloc_object(dev,
5156 intel_framebuffer_size_for_mode(mode, bpp));
5157 if (obj == NULL)
5158 return ERR_PTR(-ENOMEM);
5159
5160 mode_cmd.width = mode->hdisplay;
5161 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5162 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5163 bpp);
5ca0c34a 5164 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5165
5166 return intel_framebuffer_create(dev, &mode_cmd, obj);
5167}
5168
5169static struct drm_framebuffer *
5170mode_fits_in_fbdev(struct drm_device *dev,
5171 struct drm_display_mode *mode)
5172{
5173 struct drm_i915_private *dev_priv = dev->dev_private;
5174 struct drm_i915_gem_object *obj;
5175 struct drm_framebuffer *fb;
5176
5177 if (dev_priv->fbdev == NULL)
5178 return NULL;
5179
5180 obj = dev_priv->fbdev->ifb.obj;
5181 if (obj == NULL)
5182 return NULL;
5183
5184 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5185 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5186 fb->bits_per_pixel))
d2dff872
CW		 5187 return NULL;
5188
01f2c773 5189 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5190 return NULL;
5191
5192 return fb;
5193}
5194
7173188d
CW		 5195bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5196 struct drm_connector *connector,
5197 struct drm_display_mode *mode,
8261b191 5198 struct intel_load_detect_pipe *old)
79e53945
JB		 5199{
5200 struct intel_crtc *intel_crtc;
5201 struct drm_crtc *possible_crtc;
4ef69c7a 5202 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5203 struct drm_crtc *crtc = NULL;
5204 struct drm_device *dev = encoder->dev;
d2dff872 5205 struct drm_framebuffer *old_fb;
79e53945
JB		 5206 int i = -1;
5207
d2dff872
CW		 5208 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5209 connector->base.id, drm_get_connector_name(connector),
5210 encoder->base.id, drm_get_encoder_name(encoder));
5211
79e53945
JB		 5212 /*
5213 * Algorithm gets a little messy:
7a5e4805 5214 *
79e53945
JB		 5215 * - if the connector already has an assigned crtc, use it (but make
5216 * sure it's on first)
7a5e4805 5217 *
79e53945
JB		 5218 * - try to find the first unused crtc that can drive this connector,
5219 * and use that if we find one
79e53945
JB		 5220 */
5221
5222 /* See if we already have a CRTC for this connector */
5223 if (encoder->crtc) {
5224 crtc = encoder->crtc;
8261b191 5225
79e53945 5226 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5227 old->dpms_mode = intel_crtc->dpms_mode;
5228 old->load_detect_temp = false;
5229
5230 /* Make sure the crtc and connector are running */
79e53945 5231 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5232 struct drm_encoder_helper_funcs *encoder_funcs;
5233 struct drm_crtc_helper_funcs *crtc_funcs;
5234
79e53945
JB		 5235 crtc_funcs = crtc->helper_private;
5236 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5237
5238 encoder_funcs = encoder->helper_private;
79e53945
JB		 5239 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5240 }
8261b191 5241
7173188d 5242 return true;
79e53945
JB		 5243 }
5244
5245 /* Find an unused one (if possible) */
5246 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5247 i++;
5248 if (!(encoder->possible_crtcs & (1 << i)))
5249 continue;
5250 if (!possible_crtc->enabled) {
5251 crtc = possible_crtc;
5252 break;
5253 }
79e53945
JB		 5254 }
5255
5256 /*
5257 * If we didn't find an unused CRTC, don't use any.
5258 */
5259 if (!crtc) {
7173188d
CW		 5260 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5261 return false;
79e53945
JB		 5262 }
5263
5264 encoder->crtc = crtc;
c1c43977 5265 connector->encoder = encoder;
79e53945
JB		 5266
5267 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5268 old->dpms_mode = intel_crtc->dpms_mode;
5269 old->load_detect_temp = true;
d2dff872 5270 old->release_fb = NULL;
79e53945 5271
6492711d
CW		 5272 if (!mode)
5273 mode = &load_detect_mode;
79e53945 5274
d2dff872
CW		 5275 old_fb = crtc->fb;
5276
5277 /* We need a framebuffer large enough to accommodate all accesses
5278 * that the plane may generate whilst we perform load detection.
5279 * We can not rely on the fbcon either being present (we get called
5280 * during its initialisation to detect all boot displays, or it may
5281 * not even exist) or that it is large enough to satisfy the
5282 * requested mode.
5283 */
5284 crtc->fb = mode_fits_in_fbdev(dev, mode);
5285 if (crtc->fb == NULL) {
5286 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5287 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5288 old->release_fb = crtc->fb;
5289 } else
5290 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5291 if (IS_ERR(crtc->fb)) {
5292 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5293 crtc->fb = old_fb;
5294 return false;
79e53945 5295 }
79e53945 5296
d2dff872 5297 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5298 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5299 if (old->release_fb)
5300 old->release_fb->funcs->destroy(old->release_fb);
5301 crtc->fb = old_fb;
6492711d 5302 return false;
79e53945 5303 }
7173188d 5304
79e53945 5305 /* let the connector get through one full cycle before testing */
9d0498a2 5306 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5307
7173188d 5308 return true;
79e53945
JB		 5309}
5310
c1c43977 5311void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5312 struct drm_connector *connector,
5313 struct intel_load_detect_pipe *old)
79e53945 5314{
4ef69c7a 5315 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5316 struct drm_device *dev = encoder->dev;
5317 struct drm_crtc *crtc = encoder->crtc;
5318 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5319 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5320
d2dff872
CW		 5321 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5322 connector->base.id, drm_get_connector_name(connector),
5323 encoder->base.id, drm_get_encoder_name(encoder));
5324
8261b191 5325 if (old->load_detect_temp) {
c1c43977 5326 connector->encoder = NULL;
79e53945 5327 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5328
5329 if (old->release_fb)
5330 old->release_fb->funcs->destroy(old->release_fb);
5331
0622a53c 5332 return;
79e53945
JB		 5333 }
5334
c751ce4f 5335 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5336 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5337 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5338 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5339 }
5340}
5341
5342/* Returns the clock of the currently programmed mode of the given pipe. */
5343static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5344{
5345 struct drm_i915_private *dev_priv = dev->dev_private;
5346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5347 int pipe = intel_crtc->pipe;
548f245b 5348 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5349 u32 fp;
5350 intel_clock_t clock;
5351
5352 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5353 fp = I915_READ(FP0(pipe));
79e53945 5354 else
39adb7a5 5355 fp = I915_READ(FP1(pipe));
79e53945
JB		 5356
5357 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5358 if (IS_PINEVIEW(dev)) {
5359 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5360 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5361 } else {
5362 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5363 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5364 }
5365
a6c45cf0 5366 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5367 if (IS_PINEVIEW(dev))
5368 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5369 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5370 else
5371 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5372 DPLL_FPA01_P1_POST_DIV_SHIFT);
5373
5374 switch (dpll & DPLL_MODE_MASK) {
5375 case DPLLB_MODE_DAC_SERIAL:
5376 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5377 5 : 10;
5378 break;
5379 case DPLLB_MODE_LVDS:
5380 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5381 7 : 14;
5382 break;
5383 default:
28c97730 5384 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5385 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5386 return 0;
5387 }
5388
5389 /* XXX: Handle the 100Mhz refclk */
2177832f 5390 intel_clock(dev, 96000, &clock);
79e53945
JB		 5391 } else {
5392 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5393
5394 if (is_lvds) {
5395 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5396 DPLL_FPA01_P1_POST_DIV_SHIFT);
5397 clock.p2 = 14;
5398
5399 if ((dpll & PLL_REF_INPUT_MASK) ==
5400 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5401 /* XXX: might not be 66MHz */
2177832f 5402 intel_clock(dev, 66000, &clock);
79e53945 5403 } else
2177832f 5404 intel_clock(dev, 48000, &clock);
79e53945
JB		 5405 } else {
5406 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5407 clock.p1 = 2;
5408 else {
5409 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5410 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5411 }
5412 if (dpll & PLL_P2_DIVIDE_BY_4)
5413 clock.p2 = 4;
5414 else
5415 clock.p2 = 2;
5416
2177832f 5417 intel_clock(dev, 48000, &clock);
79e53945
JB		 5418 }
5419 }
5420
5421 /* XXX: It would be nice to validate the clocks, but we can't reuse
5422 * i830PllIsValid() because it relies on the xf86_config connector
5423 * configuration being accurate, which it isn't necessarily.
5424 */
5425
5426 return clock.dot;
5427}
5428
5429/** Returns the currently programmed mode of the given pipe. */
5430struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5431 struct drm_crtc *crtc)
5432{
548f245b 5433 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5435 int pipe = intel_crtc->pipe;
5436 struct drm_display_mode *mode;
548f245b
JB		 5437 int htot = I915_READ(HTOTAL(pipe));
5438 int hsync = I915_READ(HSYNC(pipe));
5439 int vtot = I915_READ(VTOTAL(pipe));
5440 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5441
5442 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5443 if (!mode)
5444 return NULL;
5445
5446 mode->clock = intel_crtc_clock_get(dev, crtc);
5447 mode->hdisplay = (htot & 0xffff) + 1;
5448 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5449 mode->hsync_start = (hsync & 0xffff) + 1;
5450 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5451 mode->vdisplay = (vtot & 0xffff) + 1;
5452 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5453 mode->vsync_start = (vsync & 0xffff) + 1;
5454 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5455
5456 drm_mode_set_name(mode);
79e53945
JB		 5457
5458 return mode;
5459}
5460
652c393a
JB		 5461#define GPU_IDLE_TIMEOUT 500 /* ms */
5462
5463/* When this timer fires, we've been idle for awhile */
5464static void intel_gpu_idle_timer(unsigned long arg)
5465{
5466 struct drm_device *dev = (struct drm_device *)arg;
5467 drm_i915_private_t *dev_priv = dev->dev_private;
5468
ff7ea4c0
CW		 5469 if (!list_empty(&dev_priv->mm.active_list)) {
5470 /* Still processing requests, so just re-arm the timer. */
5471 mod_timer(&dev_priv->idle_timer, jiffies +
5472 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5473 return;
5474 }
652c393a 5475
ff7ea4c0 5476 dev_priv->busy = false;
01dfba93 5477 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5478}
5479
652c393a
JB		 5480#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5481
5482static void intel_crtc_idle_timer(unsigned long arg)
5483{
5484 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5485 struct drm_crtc *crtc = &intel_crtc->base;
5486 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5487 struct intel_framebuffer *intel_fb;
652c393a 5488
ff7ea4c0
CW		 5489 intel_fb = to_intel_framebuffer(crtc->fb);
5490 if (intel_fb && intel_fb->obj->active) {
5491 /* The framebuffer is still being accessed by the GPU. */
5492 mod_timer(&intel_crtc->idle_timer, jiffies +
5493 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5494 return;
5495 }
652c393a 5496
ff7ea4c0 5497 intel_crtc->busy = false;
01dfba93 5498 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5499}
5500
3dec0095 5501static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5502{
5503 struct drm_device *dev = crtc->dev;
5504 drm_i915_private_t *dev_priv = dev->dev_private;
5505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5506 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5507 int dpll_reg = DPLL(pipe);
5508 int dpll;
652c393a 5509
bad720ff 5510 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5511 return;
5512
5513 if (!dev_priv->lvds_downclock_avail)
5514 return;
5515
dbdc6479 5516 dpll = I915_READ(dpll_reg);
652c393a 5517 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5518 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 5519
8ac5a6d5 5520 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 5521
5522 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5523 I915_WRITE(dpll_reg, dpll);
9d0498a2 5524 intel_wait_for_vblank(dev, pipe);
dbdc6479 5525
652c393a
JB		 5526 dpll = I915_READ(dpll_reg);
5527 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5528 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 5529 }
5530
5531 /* Schedule downclock */
3dec0095
DV		 5532 mod_timer(&intel_crtc->idle_timer, jiffies +
5533 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 5534}
5535
5536static void intel_decrease_pllclock(struct drm_crtc *crtc)
5537{
5538 struct drm_device *dev = crtc->dev;
5539 drm_i915_private_t *dev_priv = dev->dev_private;
5540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 5541
bad720ff 5542 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5543 return;
5544
5545 if (!dev_priv->lvds_downclock_avail)
5546 return;
5547
5548 /*
5549 * Since this is called by a timer, we should never get here in
5550 * the manual case.
5551 */
5552 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 5553 int pipe = intel_crtc->pipe;
5554 int dpll_reg = DPLL(pipe);
5555 int dpll;
f6e5b160 5556
44d98a61 5557 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 5558
8ac5a6d5 5559 assert_panel_unlocked(dev_priv, pipe);
652c393a 5560
dc257cf1 5561 dpll = I915_READ(dpll_reg);
652c393a
JB		 5562 dpll |= DISPLAY_RATE_SELECT_FPA1;
5563 I915_WRITE(dpll_reg, dpll);
9d0498a2 5564 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 5565 dpll = I915_READ(dpll_reg);
5566 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 5567 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 5568 }
5569
5570}
5571
5572/**
5573 * intel_idle_update - adjust clocks for idleness
5574 * @work: work struct
5575 *
5576 * Either the GPU or display (or both) went idle. Check the busy status
5577 * here and adjust the CRTC and GPU clocks as necessary.
5578 */
5579static void intel_idle_update(struct work_struct *work)
5580{
5581 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5582 idle_work);
5583 struct drm_device *dev = dev_priv->dev;
5584 struct drm_crtc *crtc;
5585 struct intel_crtc *intel_crtc;
5586
5587 if (!i915_powersave)
5588 return;
5589
5590 mutex_lock(&dev->struct_mutex);
5591
7648fa99
JB		 5592 i915_update_gfx_val(dev_priv);
5593
652c393a
JB		 5594 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5595 /* Skip inactive CRTCs */
5596 if (!crtc->fb)
5597 continue;
5598
5599 intel_crtc = to_intel_crtc(crtc);
5600 if (!intel_crtc->busy)
5601 intel_decrease_pllclock(crtc);
5602 }
5603
45ac22c8 5604
652c393a
JB		 5605 mutex_unlock(&dev->struct_mutex);
5606}
5607
5608/**
5609 * intel_mark_busy - mark the GPU and possibly the display busy
5610 * @dev: drm device
5611 * @obj: object we're operating on
5612 *
5613 * Callers can use this function to indicate that the GPU is busy processing
5614 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5615 * buffer), we'll also mark the display as busy, so we know to increase its
5616 * clock frequency.
5617 */
05394f39 5618void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 5619{
5620 drm_i915_private_t *dev_priv = dev->dev_private;
5621 struct drm_crtc *crtc = NULL;
5622 struct intel_framebuffer *intel_fb;
5623 struct intel_crtc *intel_crtc;
5624
5e17ee74
ZW		 5625 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5626 return;
5627
9104183d
CW		 5628 if (!dev_priv->busy) {
5629 intel_sanitize_pm(dev);
28cf798f 5630 dev_priv->busy = true;
9104183d 5631 } else
28cf798f
CW		 5632 mod_timer(&dev_priv->idle_timer, jiffies +
5633 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a 5634
acb87dfb
CW		 5635 if (obj == NULL)
5636 return;
5637
652c393a
JB		 5638 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5639 if (!crtc->fb)
5640 continue;
5641
5642 intel_crtc = to_intel_crtc(crtc);
5643 intel_fb = to_intel_framebuffer(crtc->fb);
5644 if (intel_fb->obj == obj) {
5645 if (!intel_crtc->busy) {
5646 /* Non-busy -> busy, upclock */
3dec0095 5647 intel_increase_pllclock(crtc);
652c393a
JB		 5648 intel_crtc->busy = true;
5649 } else {
5650 /* Busy -> busy, put off timer */
5651 mod_timer(&intel_crtc->idle_timer, jiffies +
5652 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5653 }
5654 }
5655 }
5656}
5657
79e53945
JB		 5658static void intel_crtc_destroy(struct drm_crtc *crtc)
5659{
5660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 5661 struct drm_device *dev = crtc->dev;
5662 struct intel_unpin_work *work;
5663 unsigned long flags;
5664
5665 spin_lock_irqsave(&dev->event_lock, flags);
5666 work = intel_crtc->unpin_work;
5667 intel_crtc->unpin_work = NULL;
5668 spin_unlock_irqrestore(&dev->event_lock, flags);
5669
5670 if (work) {
5671 cancel_work_sync(&work->work);
5672 kfree(work);
5673 }
79e53945
JB		 5674
5675 drm_crtc_cleanup(crtc);
67e77c5a 5676
79e53945
JB		 5677 kfree(intel_crtc);
5678}
5679
6b95a207
KH		 5680static void intel_unpin_work_fn(struct work_struct *__work)
5681{
5682 struct intel_unpin_work *work =
5683 container_of(__work, struct intel_unpin_work, work);
5684
5685 mutex_lock(&work->dev->struct_mutex);
1690e1eb 5686 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 5687 drm_gem_object_unreference(&work->pending_flip_obj->base);
5688 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 5689
7782de3b 5690 intel_update_fbc(work->dev);
6b95a207
KH		 5691 mutex_unlock(&work->dev->struct_mutex);
5692 kfree(work);
5693}
5694
1afe3e9d 5695static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 5696 struct drm_crtc *crtc)
6b95a207
KH		 5697{
5698 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 5699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5700 struct intel_unpin_work *work;
05394f39 5701 struct drm_i915_gem_object *obj;
6b95a207 5702 struct drm_pending_vblank_event *e;
49b14a5c 5703 struct timeval tnow, tvbl;
6b95a207
KH		 5704 unsigned long flags;
5705
5706 /* Ignore early vblank irqs */
5707 if (intel_crtc == NULL)
5708 return;
5709
49b14a5c
MK		 5710 do_gettimeofday(&tnow);
5711
6b95a207
KH		 5712 spin_lock_irqsave(&dev->event_lock, flags);
5713 work = intel_crtc->unpin_work;
5714 if (work == NULL || !work->pending) {
5715 spin_unlock_irqrestore(&dev->event_lock, flags);
5716 return;
5717 }
5718
5719 intel_crtc->unpin_work = NULL;
6b95a207
KH		 5720
5721 if (work->event) {
5722 e = work->event;
49b14a5c 5723 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 5724
5725 /* Called before vblank count and timestamps have
5726 * been updated for the vblank interval of flip
5727 * completion? Need to increment vblank count and
5728 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 5729 * to account for this. We assume this happened if we
5730 * get called over 0.9 frame durations after the last
5731 * timestamped vblank.
5732 *
5733 * This calculation can not be used with vrefresh rates
5734 * below 5Hz (10Hz to be on the safe side) without
5735 * promoting to 64 integers.
0af7e4df 5736 */
49b14a5c
MK		 5737 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5738 9 * crtc->framedur_ns) {
0af7e4df 5739 e->event.sequence++;
49b14a5c
MK		 5740 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5741 crtc->framedur_ns);
0af7e4df
MK		 5742 }
5743
49b14a5c
MK		 5744 e->event.tv_sec = tvbl.tv_sec;
5745 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 5746
6b95a207
KH		 5747 list_add_tail(&e->base.link,
5748 &e->base.file_priv->event_list);
5749 wake_up_interruptible(&e->base.file_priv->event_wait);
5750 }
5751
0af7e4df
MK		 5752 drm_vblank_put(dev, intel_crtc->pipe);
5753
6b95a207
KH		 5754 spin_unlock_irqrestore(&dev->event_lock, flags);
5755
05394f39 5756 obj = work->old_fb_obj;
d9e86c0e 5757
e59f2bac 5758 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 5759 &obj->pending_flip.counter);
5760 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 5761 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 5762
6b95a207 5763 schedule_work(&work->work);
e5510fac
JB		 5764
5765 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 5766}
5767
1afe3e9d
JB		 5768void intel_finish_page_flip(struct drm_device *dev, int pipe)
5769{
5770 drm_i915_private_t *dev_priv = dev->dev_private;
5771 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5772
49b14a5c 5773 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 5774}
5775
5776void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5777{
5778 drm_i915_private_t *dev_priv = dev->dev_private;
5779 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5780
49b14a5c 5781 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 5782}
5783
6b95a207
KH		 5784void intel_prepare_page_flip(struct drm_device *dev, int plane)
5785{
5786 drm_i915_private_t *dev_priv = dev->dev_private;
5787 struct intel_crtc *intel_crtc =
5788 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5789 unsigned long flags;
5790
5791 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 5792 if (intel_crtc->unpin_work) {
4e5359cd
SF		 5793 if ((++intel_crtc->unpin_work->pending) > 1)
5794 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 5795 } else {
5796 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5797 }
6b95a207
KH		 5798 spin_unlock_irqrestore(&dev->event_lock, flags);
5799}
5800
8c9f3aaf
JB		 5801static int intel_gen2_queue_flip(struct drm_device *dev,
5802 struct drm_crtc *crtc,
5803 struct drm_framebuffer *fb,
5804 struct drm_i915_gem_object *obj)
5805{
5806 struct drm_i915_private *dev_priv = dev->dev_private;
5807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5808 unsigned long offset;
5809 u32 flip_mask;
6d90c952 5810 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5811 int ret;
5812
6d90c952 5813 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5814 if (ret)
83d4092b 5815 goto err;
8c9f3aaf
JB		 5816
5817 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 5818 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf 5819
6d90c952 5820 ret = intel_ring_begin(ring, 6);
8c9f3aaf 5821 if (ret)
83d4092b 5822 goto err_unpin;
8c9f3aaf
JB		 5823
5824 /* Can't queue multiple flips, so wait for the previous
5825 * one to finish before executing the next.
5826 */
5827 if (intel_crtc->plane)
5828 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5829 else
5830 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 5831 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5832 intel_ring_emit(ring, MI_NOOP);
5833 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5834 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5835 intel_ring_emit(ring, fb->pitches[0]);
5836 intel_ring_emit(ring, obj->gtt_offset + offset);
5837 intel_ring_emit(ring, 0); /* aux display base address, unused */
5838 intel_ring_advance(ring);
83d4092b
CW		 5839 return 0;
5840
5841err_unpin:
5842 intel_unpin_fb_obj(obj);
5843err:
8c9f3aaf
JB		 5844 return ret;
5845}
5846
5847static int intel_gen3_queue_flip(struct drm_device *dev,
5848 struct drm_crtc *crtc,
5849 struct drm_framebuffer *fb,
5850 struct drm_i915_gem_object *obj)
5851{
5852 struct drm_i915_private *dev_priv = dev->dev_private;
5853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5854 unsigned long offset;
5855 u32 flip_mask;
6d90c952 5856 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5857 int ret;
5858
6d90c952 5859 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5860 if (ret)
83d4092b 5861 goto err;
8c9f3aaf
JB		 5862
5863 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 5864 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf 5865
6d90c952 5866 ret = intel_ring_begin(ring, 6);
8c9f3aaf 5867 if (ret)
83d4092b 5868 goto err_unpin;
8c9f3aaf
JB		 5869
5870 if (intel_crtc->plane)
5871 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5872 else
5873 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 5874 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5875 intel_ring_emit(ring, MI_NOOP);
5876 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
5877 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5878 intel_ring_emit(ring, fb->pitches[0]);
5879 intel_ring_emit(ring, obj->gtt_offset + offset);
5880 intel_ring_emit(ring, MI_NOOP);
5881
5882 intel_ring_advance(ring);
83d4092b
CW		 5883 return 0;
5884
5885err_unpin:
5886 intel_unpin_fb_obj(obj);
5887err:
8c9f3aaf
JB		 5888 return ret;
5889}
5890
5891static int intel_gen4_queue_flip(struct drm_device *dev,
5892 struct drm_crtc *crtc,
5893 struct drm_framebuffer *fb,
5894 struct drm_i915_gem_object *obj)
5895{
5896 struct drm_i915_private *dev_priv = dev->dev_private;
5897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5898 uint32_t pf, pipesrc;
6d90c952 5899 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5900 int ret;
5901
6d90c952 5902 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5903 if (ret)
83d4092b 5904 goto err;
8c9f3aaf 5905
6d90c952 5906 ret = intel_ring_begin(ring, 4);
8c9f3aaf 5907 if (ret)
83d4092b 5908 goto err_unpin;
8c9f3aaf
JB		 5909
5910 /* i965+ uses the linear or tiled offsets from the
5911 * Display Registers (which do not change across a page-flip)
5912 * so we need only reprogram the base address.
5913 */
6d90c952
DV		 5914 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5915 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5916 intel_ring_emit(ring, fb->pitches[0]);
5917 intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
8c9f3aaf
JB		 5918
5919 /* XXX Enabling the panel-fitter across page-flip is so far
5920 * untested on non-native modes, so ignore it for now.
5921 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5922 */
5923 pf = 0;
5924 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 5925 intel_ring_emit(ring, pf | pipesrc);
5926 intel_ring_advance(ring);
83d4092b
CW		 5927 return 0;
5928
5929err_unpin:
5930 intel_unpin_fb_obj(obj);
5931err:
8c9f3aaf
JB		 5932 return ret;
5933}
5934
5935static int intel_gen6_queue_flip(struct drm_device *dev,
5936 struct drm_crtc *crtc,
5937 struct drm_framebuffer *fb,
5938 struct drm_i915_gem_object *obj)
5939{
5940 struct drm_i915_private *dev_priv = dev->dev_private;
5941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 5942 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5943 uint32_t pf, pipesrc;
5944 int ret;
5945
6d90c952 5946 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5947 if (ret)
83d4092b 5948 goto err;
8c9f3aaf 5949
6d90c952 5950 ret = intel_ring_begin(ring, 4);
8c9f3aaf 5951 if (ret)
83d4092b 5952 goto err_unpin;
8c9f3aaf 5953
6d90c952
DV		 5954 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5955 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5956 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
5957 intel_ring_emit(ring, obj->gtt_offset);
8c9f3aaf 5958
dc257cf1
DV		 5959 /* Contrary to the suggestions in the documentation,
5960 * "Enable Panel Fitter" does not seem to be required when page
5961 * flipping with a non-native mode, and worse causes a normal
5962 * modeset to fail.
5963 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
5964 */
5965 pf = 0;
8c9f3aaf 5966 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 5967 intel_ring_emit(ring, pf | pipesrc);
5968 intel_ring_advance(ring);
83d4092b
CW		 5969 return 0;
5970
5971err_unpin:
5972 intel_unpin_fb_obj(obj);
5973err:
8c9f3aaf
JB		 5974 return ret;
5975}
5976
7c9017e5
JB		 5977/*
5978 * On gen7 we currently use the blit ring because (in early silicon at least)
5979 * the render ring doesn't give us interrpts for page flip completion, which
5980 * means clients will hang after the first flip is queued. Fortunately the
5981 * blit ring generates interrupts properly, so use it instead.
5982 */
5983static int intel_gen7_queue_flip(struct drm_device *dev,
5984 struct drm_crtc *crtc,
5985 struct drm_framebuffer *fb,
5986 struct drm_i915_gem_object *obj)
5987{
5988 struct drm_i915_private *dev_priv = dev->dev_private;
5989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5990 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
5991 int ret;
5992
5993 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5994 if (ret)
83d4092b 5995 goto err;
7c9017e5
JB		 5996
5997 ret = intel_ring_begin(ring, 4);
5998 if (ret)
83d4092b 5999 goto err_unpin;
7c9017e5
JB		 6000
6001 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 6002 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 6003 intel_ring_emit(ring, (obj->gtt_offset));
6004 intel_ring_emit(ring, (MI_NOOP));
6005 intel_ring_advance(ring);
83d4092b
CW		 6006 return 0;
6007
6008err_unpin:
6009 intel_unpin_fb_obj(obj);
6010err:
7c9017e5
JB		 6011 return ret;
6012}
6013
8c9f3aaf
JB		 6014static int intel_default_queue_flip(struct drm_device *dev,
6015 struct drm_crtc *crtc,
6016 struct drm_framebuffer *fb,
6017 struct drm_i915_gem_object *obj)
6018{
6019 return -ENODEV;
6020}
6021
6b95a207
KH		 6022static int intel_crtc_page_flip(struct drm_crtc *crtc,
6023 struct drm_framebuffer *fb,
6024 struct drm_pending_vblank_event *event)
6025{
6026 struct drm_device *dev = crtc->dev;
6027 struct drm_i915_private *dev_priv = dev->dev_private;
6028 struct intel_framebuffer *intel_fb;
05394f39 6029 struct drm_i915_gem_object *obj;
6b95a207
KH		 6030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6031 struct intel_unpin_work *work;
8c9f3aaf 6032 unsigned long flags;
52e68630 6033 int ret;
6b95a207
KH		 6034
6035 work = kzalloc(sizeof *work, GFP_KERNEL);
6036 if (work == NULL)
6037 return -ENOMEM;
6038
6b95a207
KH		 6039 work->event = event;
6040 work->dev = crtc->dev;
6041 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6042 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6043 INIT_WORK(&work->work, intel_unpin_work_fn);
6044
7317c75e
JB		 6045 ret = drm_vblank_get(dev, intel_crtc->pipe);
6046 if (ret)
6047 goto free_work;
6048
6b95a207
KH		 6049 /* We borrow the event spin lock for protecting unpin_work */
6050 spin_lock_irqsave(&dev->event_lock, flags);
6051 if (intel_crtc->unpin_work) {
6052 spin_unlock_irqrestore(&dev->event_lock, flags);
6053 kfree(work);
7317c75e 6054 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6055
6056 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6057 return -EBUSY;
6058 }
6059 intel_crtc->unpin_work = work;
6060 spin_unlock_irqrestore(&dev->event_lock, flags);
6061
6062 intel_fb = to_intel_framebuffer(fb);
6063 obj = intel_fb->obj;
6064
468f0b44 6065 mutex_lock(&dev->struct_mutex);
6b95a207 6066
75dfca80 6067 /* Reference the objects for the scheduled work. */
05394f39
CW		 6068 drm_gem_object_reference(&work->old_fb_obj->base);
6069 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6070
6071 crtc->fb = fb;
96b099fd 6072
e1f99ce6 6073 work->pending_flip_obj = obj;
e1f99ce6 6074
4e5359cd
SF		 6075 work->enable_stall_check = true;
6076
e1f99ce6
CW		 6077 /* Block clients from rendering to the new back buffer until
6078 * the flip occurs and the object is no longer visible.
6079 */
05394f39 6080 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6081
8c9f3aaf
JB		 6082 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6083 if (ret)
6084 goto cleanup_pending;
6b95a207 6085
7782de3b 6086 intel_disable_fbc(dev);
acb87dfb 6087 intel_mark_busy(dev, obj);
6b95a207
KH		 6088 mutex_unlock(&dev->struct_mutex);
6089
e5510fac
JB		 6090 trace_i915_flip_request(intel_crtc->plane, obj);
6091
6b95a207 6092 return 0;
96b099fd 6093
8c9f3aaf
JB		 6094cleanup_pending:
6095 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6096 drm_gem_object_unreference(&work->old_fb_obj->base);
6097 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6098 mutex_unlock(&dev->struct_mutex);
6099
6100 spin_lock_irqsave(&dev->event_lock, flags);
6101 intel_crtc->unpin_work = NULL;
6102 spin_unlock_irqrestore(&dev->event_lock, flags);
6103
7317c75e
JB		 6104 drm_vblank_put(dev, intel_crtc->pipe);
6105free_work:
96b099fd
CW		 6106 kfree(work);
6107
6108 return ret;
6b95a207
KH		 6109}
6110
47f1c6c9
CW		 6111static void intel_sanitize_modesetting(struct drm_device *dev,
6112 int pipe, int plane)
6113{
6114 struct drm_i915_private *dev_priv = dev->dev_private;
6115 u32 reg, val;
6116
f47166d2
CW		 6117 /* Clear any frame start delays used for debugging left by the BIOS */
6118 for_each_pipe(pipe) {
6119 reg = PIPECONF(pipe);
6120 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6121 }
6122
47f1c6c9
CW		 6123 if (HAS_PCH_SPLIT(dev))
6124 return;
6125
6126 /* Who knows what state these registers were left in by the BIOS or
6127 * grub?
6128 *
6129 * If we leave the registers in a conflicting state (e.g. with the
6130 * display plane reading from the other pipe than the one we intend
6131 * to use) then when we attempt to teardown the active mode, we will
6132 * not disable the pipes and planes in the correct order -- leaving
6133 * a plane reading from a disabled pipe and possibly leading to
6134 * undefined behaviour.
6135 */
6136
6137 reg = DSPCNTR(plane);
6138 val = I915_READ(reg);
6139
6140 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6141 return;
6142 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6143 return;
6144
6145 /* This display plane is active and attached to the other CPU pipe. */
6146 pipe = !pipe;
6147
6148 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6149 intel_disable_plane(dev_priv, plane, pipe);
6150 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6151}
79e53945 6152
f6e5b160
CW		 6153static void intel_crtc_reset(struct drm_crtc *crtc)
6154{
6155 struct drm_device *dev = crtc->dev;
6156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6157
6158 /* Reset flags back to the 'unknown' status so that they
6159 * will be correctly set on the initial modeset.
6160 */
6161 intel_crtc->dpms_mode = -1;
6162
6163 /* We need to fix up any BIOS configuration that conflicts with
6164 * our expectations.
6165 */
6166 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6167}
6168
6169static struct drm_crtc_helper_funcs intel_helper_funcs = {
6170 .dpms = intel_crtc_dpms,
6171 .mode_fixup = intel_crtc_mode_fixup,
6172 .mode_set = intel_crtc_mode_set,
6173 .mode_set_base = intel_pipe_set_base,
6174 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6175 .load_lut = intel_crtc_load_lut,
6176 .disable = intel_crtc_disable,
6177};
6178
6179static const struct drm_crtc_funcs intel_crtc_funcs = {
6180 .reset = intel_crtc_reset,
6181 .cursor_set = intel_crtc_cursor_set,
6182 .cursor_move = intel_crtc_cursor_move,
6183 .gamma_set = intel_crtc_gamma_set,
6184 .set_config = drm_crtc_helper_set_config,
6185 .destroy = intel_crtc_destroy,
6186 .page_flip = intel_crtc_page_flip,
6187};
6188
ee7b9f93
JB		 6189static void intel_pch_pll_init(struct drm_device *dev)
6190{
6191 drm_i915_private_t *dev_priv = dev->dev_private;
6192 int i;
6193
6194 if (dev_priv->num_pch_pll == 0) {
6195 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6196 return;
6197 }
6198
6199 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6200 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6201 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6202 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6203 }
6204}
6205
b358d0a6 6206static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6207{
22fd0fab 6208 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6209 struct intel_crtc *intel_crtc;
6210 int i;
6211
6212 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6213 if (intel_crtc == NULL)
6214 return;
6215
6216 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6217
6218 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6219 for (i = 0; i < 256; i++) {
6220 intel_crtc->lut_r[i] = i;
6221 intel_crtc->lut_g[i] = i;
6222 intel_crtc->lut_b[i] = i;
6223 }
6224
80824003
JB		 6225 /* Swap pipes & planes for FBC on pre-965 */
6226 intel_crtc->pipe = pipe;
6227 intel_crtc->plane = pipe;
e2e767ab 6228 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6229 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6230 intel_crtc->plane = !pipe;
80824003
JB		 6231 }
6232
22fd0fab
JB		 6233 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6234 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6235 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6236 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6237
5d1d0cc8 6238 intel_crtc_reset(&intel_crtc->base);
04dbff52 6239 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 6240 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 6241
6242 if (HAS_PCH_SPLIT(dev)) {
6243 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6244 intel_helper_funcs.commit = ironlake_crtc_commit;
6245 } else {
6246 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6247 intel_helper_funcs.commit = i9xx_crtc_commit;
6248 }
6249
79e53945
JB		 6250 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6251
652c393a
JB		 6252 intel_crtc->busy = false;
6253
6254 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6255 (unsigned long)intel_crtc);
79e53945
JB		 6256}
6257
08d7b3d1 6258int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6259 struct drm_file *file)
08d7b3d1 6260{
08d7b3d1 6261 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6262 struct drm_mode_object *drmmode_obj;
6263 struct intel_crtc *crtc;
08d7b3d1 6264
1cff8f6b
DV		 6265 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6266 return -ENODEV;
08d7b3d1 6267
c05422d5
DV		 6268 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6269 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6270
c05422d5 6271 if (!drmmode_obj) {
08d7b3d1
CW		 6272 DRM_ERROR("no such CRTC id\n");
6273 return -EINVAL;
6274 }
6275
c05422d5
DV		 6276 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6277 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6278
c05422d5 6279 return 0;
08d7b3d1
CW		 6280}
6281
c5e4df33 6282static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6283{
4ef69c7a 6284 struct intel_encoder *encoder;
79e53945 6285 int index_mask = 0;
79e53945
JB		 6286 int entry = 0;
6287
4ef69c7a
CW		 6288 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6289 if (type_mask & encoder->clone_mask)
79e53945
JB		 6290 index_mask |= (1 << entry);
6291 entry++;
6292 }
4ef69c7a 6293
79e53945
JB		 6294 return index_mask;
6295}
6296
4d302442
CW		 6297static bool has_edp_a(struct drm_device *dev)
6298{
6299 struct drm_i915_private *dev_priv = dev->dev_private;
6300
6301 if (!IS_MOBILE(dev))
6302 return false;
6303
6304 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6305 return false;
6306
6307 if (IS_GEN5(dev) &&
6308 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6309 return false;
6310
6311 return true;
6312}
6313
79e53945
JB		 6314static void intel_setup_outputs(struct drm_device *dev)
6315{
725e30ad 6316 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6317 struct intel_encoder *encoder;
cb0953d7 6318 bool dpd_is_edp = false;
f3cfcba6 6319 bool has_lvds;
79e53945 6320
f3cfcba6 6321 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 6322 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6323 /* disable the panel fitter on everything but LVDS */
6324 I915_WRITE(PFIT_CONTROL, 0);
6325 }
79e53945 6326
bad720ff 6327 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6328 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6329
4d302442 6330 if (has_edp_a(dev))
32f9d658
ZW		 6331 intel_dp_init(dev, DP_A);
6332
cb0953d7
AJ		 6333 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6334 intel_dp_init(dev, PCH_DP_D);
6335 }
6336
6337 intel_crt_init(dev);
6338
6339 if (HAS_PCH_SPLIT(dev)) {
6340 int found;
6341
30ad48b7 6342 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 6343 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 6344 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7
ZW		 6345 if (!found)
6346 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6347 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6348 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6349 }
6350
6351 if (I915_READ(HDMIC) & PORT_DETECTED)
6352 intel_hdmi_init(dev, HDMIC);
6353
6354 if (I915_READ(HDMID) & PORT_DETECTED)
6355 intel_hdmi_init(dev, HDMID);
6356
5eb08b69
ZW		 6357 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6358 intel_dp_init(dev, PCH_DP_C);
6359
cb0953d7 6360 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6361 intel_dp_init(dev, PCH_DP_D);
6362
103a196f 6363 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6364 bool found = false;
7d57382e 6365
725e30ad 6366 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6367 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 6368 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 6369 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6370 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6371 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6372 }
27185ae1 6373
b01f2c3a
JB		 6374 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6375 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6376 intel_dp_init(dev, DP_B);
b01f2c3a 6377 }
725e30ad 6378 }
13520b05
KH		 6379
6380 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6381
b01f2c3a
JB		 6382 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6383 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 6384 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 6385 }
27185ae1
ML		 6386
6387 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6388
b01f2c3a
JB		 6389 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6390 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6391 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6392 }
6393 if (SUPPORTS_INTEGRATED_DP(dev)) {
6394 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6395 intel_dp_init(dev, DP_C);
b01f2c3a 6396 }
725e30ad 6397 }
27185ae1 6398
b01f2c3a
JB		 6399 if (SUPPORTS_INTEGRATED_DP(dev) &&
6400 (I915_READ(DP_D) & DP_DETECTED)) {
6401 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6402 intel_dp_init(dev, DP_D);
b01f2c3a 6403 }
bad720ff 6404 } else if (IS_GEN2(dev))
79e53945
JB		 6405 intel_dvo_init(dev);
6406
103a196f 6407 if (SUPPORTS_TV(dev))
79e53945
JB		 6408 intel_tv_init(dev);
6409
4ef69c7a
CW		 6410 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6411 encoder->base.possible_crtcs = encoder->crtc_mask;
6412 encoder->base.possible_clones =
6413 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6414 }
47356eb6 6415
2c7111db
CW		 6416 /* disable all the possible outputs/crtcs before entering KMS mode */
6417 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 6418
6419 if (HAS_PCH_SPLIT(dev))
6420 ironlake_init_pch_refclk(dev);
79e53945
JB		 6421}
6422
6423static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6424{
6425 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6426
6427 drm_framebuffer_cleanup(fb);
05394f39 6428 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6429
6430 kfree(intel_fb);
6431}
6432
6433static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6434 struct drm_file *file,
79e53945
JB		 6435 unsigned int *handle)
6436{
6437 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6438 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6439
05394f39 6440 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6441}
6442
6443static const struct drm_framebuffer_funcs intel_fb_funcs = {
6444 .destroy = intel_user_framebuffer_destroy,
6445 .create_handle = intel_user_framebuffer_create_handle,
6446};
6447
38651674
DA		 6448int intel_framebuffer_init(struct drm_device *dev,
6449 struct intel_framebuffer *intel_fb,
308e5bcb 6450 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 6451 struct drm_i915_gem_object *obj)
79e53945 6452{
79e53945
JB		 6453 int ret;
6454
05394f39 6455 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6456 return -EINVAL;
6457
308e5bcb 6458 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 6459 return -EINVAL;
6460
308e5bcb 6461 switch (mode_cmd->pixel_format) {
04b3924d
VS		 6462 case DRM_FORMAT_RGB332:
6463 case DRM_FORMAT_RGB565:
6464 case DRM_FORMAT_XRGB8888:
b250da79 6465 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 6466 case DRM_FORMAT_ARGB8888:
6467 case DRM_FORMAT_XRGB2101010:
6468 case DRM_FORMAT_ARGB2101010:
308e5bcb 6469 /* RGB formats are common across chipsets */
b5626747 6470 break;
04b3924d
VS		 6471 case DRM_FORMAT_YUYV:
6472 case DRM_FORMAT_UYVY:
6473 case DRM_FORMAT_YVYU:
6474 case DRM_FORMAT_VYUY:
57cd6508
CW		 6475 break;
6476 default:
aca25848
ED		 6477 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6478 mode_cmd->pixel_format);
57cd6508
CW		 6479 return -EINVAL;
6480 }
6481
79e53945
JB		 6482 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6483 if (ret) {
6484 DRM_ERROR("framebuffer init failed %d\n", ret);
6485 return ret;
6486 }
6487
6488 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6489 intel_fb->obj = obj;
79e53945
JB		 6490 return 0;
6491}
6492
79e53945
JB		 6493static struct drm_framebuffer *
6494intel_user_framebuffer_create(struct drm_device *dev,
6495 struct drm_file *filp,
308e5bcb 6496 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 6497{
05394f39 6498 struct drm_i915_gem_object *obj;
79e53945 6499
308e5bcb
JB		 6500 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6501 mode_cmd->handles[0]));
c8725226 6502 if (&obj->base == NULL)
cce13ff7 6503 return ERR_PTR(-ENOENT);
79e53945 6504
d2dff872 6505 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6506}
6507
79e53945 6508static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6509 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6510 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6511};
6512
e70236a8
JB		 6513/* Set up chip specific display functions */
6514static void intel_init_display(struct drm_device *dev)
6515{
6516 struct drm_i915_private *dev_priv = dev->dev_private;
6517
6518 /* We always want a DPMS function */
f564048e 6519 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 6520 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 6521 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
ee7b9f93 6522 dev_priv->display.off = ironlake_crtc_off;
17638cd6 6523 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 6524 } else {
e70236a8 6525 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 6526 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
ee7b9f93 6527 dev_priv->display.off = i9xx_crtc_off;
17638cd6 6528 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 6529 }
e70236a8 6530
e70236a8 6531 /* Returns the core display clock speed */
25eb05fc
JB		 6532 if (IS_VALLEYVIEW(dev))
6533 dev_priv->display.get_display_clock_speed =
6534 valleyview_get_display_clock_speed;
6535 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 6536 dev_priv->display.get_display_clock_speed =
6537 i945_get_display_clock_speed;
6538 else if (IS_I915G(dev))
6539 dev_priv->display.get_display_clock_speed =
6540 i915_get_display_clock_speed;
f2b115e6 6541 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 6542 dev_priv->display.get_display_clock_speed =
6543 i9xx_misc_get_display_clock_speed;
6544 else if (IS_I915GM(dev))
6545 dev_priv->display.get_display_clock_speed =
6546 i915gm_get_display_clock_speed;
6547 else if (IS_I865G(dev))
6548 dev_priv->display.get_display_clock_speed =
6549 i865_get_display_clock_speed;
f0f8a9ce 6550 else if (IS_I85X(dev))
e70236a8
JB		 6551 dev_priv->display.get_display_clock_speed =
6552 i855_get_display_clock_speed;
6553 else /* 852, 830 */
6554 dev_priv->display.get_display_clock_speed =
6555 i830_get_display_clock_speed;
6556
7f8a8569 6557 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 6558 if (IS_GEN5(dev)) {
674cf967 6559 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 6560 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 6561 } else if (IS_GEN6(dev)) {
674cf967 6562 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 6563 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 6564 } else if (IS_IVYBRIDGE(dev)) {
6565 /* FIXME: detect B0+ stepping and use auto training */
6566 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 6567 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 6568 } else
6569 dev_priv->display.update_wm = NULL;
ceb04246 6570 } else if (IS_VALLEYVIEW(dev)) {
575155a9
JB		 6571 dev_priv->display.force_wake_get = vlv_force_wake_get;
6572 dev_priv->display.force_wake_put = vlv_force_wake_put;
6067aaea 6573 } else if (IS_G4X(dev)) {
e0dac65e 6574 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 6575 }
8c9f3aaf
JB		 6576
6577 /* Default just returns -ENODEV to indicate unsupported */
6578 dev_priv->display.queue_flip = intel_default_queue_flip;
6579
6580 switch (INTEL_INFO(dev)->gen) {
6581 case 2:
6582 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6583 break;
6584
6585 case 3:
6586 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6587 break;
6588
6589 case 4:
6590 case 5:
6591 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6592 break;
6593
6594 case 6:
6595 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6596 break;
7c9017e5
JB		 6597 case 7:
6598 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6599 break;
8c9f3aaf 6600 }
e70236a8
JB		 6601}
6602
b690e96c
JB		 6603/*
6604 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6605 * resume, or other times. This quirk makes sure that's the case for
6606 * affected systems.
6607 */
0206e353 6608static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 6609{
6610 struct drm_i915_private *dev_priv = dev->dev_private;
6611
6612 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 6613 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 6614}
6615
435793df
KP		 6616/*
6617 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6618 */
6619static void quirk_ssc_force_disable(struct drm_device *dev)
6620{
6621 struct drm_i915_private *dev_priv = dev->dev_private;
6622 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 6623 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 6624}
6625
4dca20ef 6626/*
5a15ab5b
CE		 6627 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6628 * brightness value
4dca20ef
CE		 6629 */
6630static void quirk_invert_brightness(struct drm_device *dev)
6631{
6632 struct drm_i915_private *dev_priv = dev->dev_private;
6633 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 6634 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 6635}
6636
b690e96c
JB		 6637struct intel_quirk {
6638 int device;
6639 int subsystem_vendor;
6640 int subsystem_device;
6641 void (*hook)(struct drm_device *dev);
6642};
6643
c43b5634 6644static struct intel_quirk intel_quirks[] = {
b690e96c 6645 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 6646 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 6647
6648 /* Thinkpad R31 needs pipe A force quirk */
6649 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6650 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6651 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6652
6653 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6654 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6655 /* ThinkPad X40 needs pipe A force quirk */
6656
6657 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6658 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6659
6660 /* 855 & before need to leave pipe A & dpll A up */
6661 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6662 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 6663
6664 /* Lenovo U160 cannot use SSC on LVDS */
6665 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 6666
6667 /* Sony Vaio Y cannot use SSC on LVDS */
6668 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 6669
6670 /* Acer Aspire 5734Z must invert backlight brightness */
6671 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 6672};
6673
6674static void intel_init_quirks(struct drm_device *dev)
6675{
6676 struct pci_dev *d = dev->pdev;
6677 int i;
6678
6679 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6680 struct intel_quirk *q = &intel_quirks[i];
6681
6682 if (d->device == q->device &&
6683 (d->subsystem_vendor == q->subsystem_vendor ||
6684 q->subsystem_vendor == PCI_ANY_ID) &&
6685 (d->subsystem_device == q->subsystem_device ||
6686 q->subsystem_device == PCI_ANY_ID))
6687 q->hook(dev);
6688 }
6689}
6690
9cce37f4
JB		 6691/* Disable the VGA plane that we never use */
6692static void i915_disable_vga(struct drm_device *dev)
6693{
6694 struct drm_i915_private *dev_priv = dev->dev_private;
6695 u8 sr1;
6696 u32 vga_reg;
6697
6698 if (HAS_PCH_SPLIT(dev))
6699 vga_reg = CPU_VGACNTRL;
6700 else
6701 vga_reg = VGACNTRL;
6702
6703 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 6704 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 6705 sr1 = inb(VGA_SR_DATA);
6706 outb(sr1 | 1<<5, VGA_SR_DATA);
6707 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6708 udelay(300);
6709
6710 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6711 POSTING_READ(vga_reg);
6712}
6713
f82cfb6b
JB		 6714static void ivb_pch_pwm_override(struct drm_device *dev)
6715{
6716 struct drm_i915_private *dev_priv = dev->dev_private;
6717
6718 /*
6719 * IVB has CPU eDP backlight regs too, set things up to let the
6720 * PCH regs control the backlight
6721 */
6722 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6723 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6724 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6725}
6726
f817586c
DV		 6727void intel_modeset_init_hw(struct drm_device *dev)
6728{
6729 struct drm_i915_private *dev_priv = dev->dev_private;
6730
6731 intel_init_clock_gating(dev);
6732
6733 if (IS_IRONLAKE_M(dev)) {
6734 ironlake_enable_drps(dev);
1833b134 6735 ironlake_enable_rc6(dev);
f817586c
DV		 6736 intel_init_emon(dev);
6737 }
6738
b6834bd6 6739 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
f817586c
DV		 6740 gen6_enable_rps(dev_priv);
6741 gen6_update_ring_freq(dev_priv);
6742 }
f82cfb6b
JB		 6743
6744 if (IS_IVYBRIDGE(dev))
6745 ivb_pch_pwm_override(dev);
f817586c
DV		 6746}
6747
79e53945
JB		 6748void intel_modeset_init(struct drm_device *dev)
6749{
652c393a 6750 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 6751 int i, ret;
79e53945
JB		 6752
6753 drm_mode_config_init(dev);
6754
6755 dev->mode_config.min_width = 0;
6756 dev->mode_config.min_height = 0;
6757
019d96cb
DA		 6758 dev->mode_config.preferred_depth = 24;
6759 dev->mode_config.prefer_shadow = 1;
6760
79e53945
JB		 6761 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6762
b690e96c
JB		 6763 intel_init_quirks(dev);
6764
1fa61106
ED		 6765 intel_init_pm(dev);
6766
e70236a8
JB		 6767 intel_init_display(dev);
6768
a6c45cf0
CW		 6769 if (IS_GEN2(dev)) {
6770 dev->mode_config.max_width = 2048;
6771 dev->mode_config.max_height = 2048;
6772 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 6773 dev->mode_config.max_width = 4096;
6774 dev->mode_config.max_height = 4096;
79e53945 6775 } else {
a6c45cf0
CW		 6776 dev->mode_config.max_width = 8192;
6777 dev->mode_config.max_height = 8192;
79e53945 6778 }
35c3047a 6779 dev->mode_config.fb_base = dev->agp->base;
79e53945 6780
28c97730 6781 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 6782 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 6783
a3524f1b 6784 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 6785 intel_crtc_init(dev, i);
00c2064b
JB		 6786 ret = intel_plane_init(dev, i);
6787 if (ret)
6788 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 6789 }
6790
ee7b9f93
JB		 6791 intel_pch_pll_init(dev);
6792
9cce37f4
JB		 6793 /* Just disable it once at startup */
6794 i915_disable_vga(dev);
79e53945 6795 intel_setup_outputs(dev);
652c393a 6796
652c393a
JB		 6797 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6798 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6799 (unsigned long)dev);
2c7111db
CW		 6800}
6801
6802void intel_modeset_gem_init(struct drm_device *dev)
6803{
1833b134 6804 intel_modeset_init_hw(dev);
02e792fb
DV		 6805
6806 intel_setup_overlay(dev);
79e53945
JB		 6807}
6808
6809void intel_modeset_cleanup(struct drm_device *dev)
6810{
652c393a
JB		 6811 struct drm_i915_private *dev_priv = dev->dev_private;
6812 struct drm_crtc *crtc;
6813 struct intel_crtc *intel_crtc;
6814
f87ea761 6815 drm_kms_helper_poll_fini(dev);
652c393a
JB		 6816 mutex_lock(&dev->struct_mutex);
6817
723bfd70
JB		 6818 intel_unregister_dsm_handler();
6819
6820
652c393a
JB		 6821 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6822 /* Skip inactive CRTCs */
6823 if (!crtc->fb)
6824 continue;
6825
6826 intel_crtc = to_intel_crtc(crtc);
3dec0095 6827 intel_increase_pllclock(crtc);
652c393a
JB		 6828 }
6829
973d04f9 6830 intel_disable_fbc(dev);
e70236a8 6831
f97108d1
JB		 6832 if (IS_IRONLAKE_M(dev))
6833 ironlake_disable_drps(dev);
b6834bd6 6834 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
3b8d8d91 6835 gen6_disable_rps(dev);
f97108d1 6836
d5bb081b
JB		 6837 if (IS_IRONLAKE_M(dev))
6838 ironlake_disable_rc6(dev);
0cdab21f 6839
57f350b6
JB		 6840 if (IS_VALLEYVIEW(dev))
6841 vlv_init_dpio(dev);
6842
69341a5e
KH		 6843 mutex_unlock(&dev->struct_mutex);
6844
6c0d9350
DV		 6845 /* Disable the irq before mode object teardown, for the irq might
6846 * enqueue unpin/hotplug work. */
6847 drm_irq_uninstall(dev);
6848 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 6849 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 6850
1630fe75
CW		 6851 /* flush any delayed tasks or pending work */
6852 flush_scheduled_work();
6853
3dec0095
DV		 6854 /* Shut off idle work before the crtcs get freed. */
6855 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6856 intel_crtc = to_intel_crtc(crtc);
6857 del_timer_sync(&intel_crtc->idle_timer);
6858 }
6859 del_timer_sync(&dev_priv->idle_timer);
6860 cancel_work_sync(&dev_priv->idle_work);
6861
79e53945
JB		 6862 drm_mode_config_cleanup(dev);
6863}
6864
f1c79df3
ZW		 6865/*
6866 * Return which encoder is currently attached for connector.
6867 */
df0e9248 6868struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 6869{
df0e9248
CW		 6870 return &intel_attached_encoder(connector)->base;
6871}
f1c79df3 6872
df0e9248
CW		 6873void intel_connector_attach_encoder(struct intel_connector *connector,
6874 struct intel_encoder *encoder)
6875{
6876 connector->encoder = encoder;
6877 drm_mode_connector_attach_encoder(&connector->base,
6878 &encoder->base);
79e53945 6879}
28d52043
DA		 6880
6881/*
6882 * set vga decode state - true == enable VGA decode
6883 */
6884int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6885{
6886 struct drm_i915_private *dev_priv = dev->dev_private;
6887 u16 gmch_ctrl;
6888
6889 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6890 if (state)
6891 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6892 else
6893 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6894 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6895 return 0;
6896}
c4a1d9e4
CW		 6897
6898#ifdef CONFIG_DEBUG_FS
6899#include <linux/seq_file.h>
6900
6901struct intel_display_error_state {
6902 struct intel_cursor_error_state {
6903 u32 control;
6904 u32 position;
6905 u32 base;
6906 u32 size;
6907 } cursor[2];
6908
6909 struct intel_pipe_error_state {
6910 u32 conf;
6911 u32 source;
6912
6913 u32 htotal;
6914 u32 hblank;
6915 u32 hsync;
6916 u32 vtotal;
6917 u32 vblank;
6918 u32 vsync;
6919 } pipe[2];
6920
6921 struct intel_plane_error_state {
6922 u32 control;
6923 u32 stride;
6924 u32 size;
6925 u32 pos;
6926 u32 addr;
6927 u32 surface;
6928 u32 tile_offset;
6929 } plane[2];
6930};
6931
6932struct intel_display_error_state *
6933intel_display_capture_error_state(struct drm_device *dev)
6934{
0206e353 6935 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 6936 struct intel_display_error_state *error;
6937 int i;
6938
6939 error = kmalloc(sizeof(*error), GFP_ATOMIC);
6940 if (error == NULL)
6941 return NULL;
6942
6943 for (i = 0; i < 2; i++) {
6944 error->cursor[i].control = I915_READ(CURCNTR(i));
6945 error->cursor[i].position = I915_READ(CURPOS(i));
6946 error->cursor[i].base = I915_READ(CURBASE(i));
6947
6948 error->plane[i].control = I915_READ(DSPCNTR(i));
6949 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6950 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 6951 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 6952 error->plane[i].addr = I915_READ(DSPADDR(i));
6953 if (INTEL_INFO(dev)->gen >= 4) {
6954 error->plane[i].surface = I915_READ(DSPSURF(i));
6955 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6956 }
6957
6958 error->pipe[i].conf = I915_READ(PIPECONF(i));
6959 error->pipe[i].source = I915_READ(PIPESRC(i));
6960 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6961 error->pipe[i].hblank = I915_READ(HBLANK(i));
6962 error->pipe[i].hsync = I915_READ(HSYNC(i));
6963 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6964 error->pipe[i].vblank = I915_READ(VBLANK(i));
6965 error->pipe[i].vsync = I915_READ(VSYNC(i));
6966 }
6967
6968 return error;
6969}
6970
6971void
6972intel_display_print_error_state(struct seq_file *m,
6973 struct drm_device *dev,
6974 struct intel_display_error_state *error)
6975{
6976 int i;
6977
6978 for (i = 0; i < 2; i++) {
6979 seq_printf(m, "Pipe [%d]:\n", i);
6980 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
6981 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
6982 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
6983 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
6984 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
6985 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
6986 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
6987 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
6988
6989 seq_printf(m, "Plane [%d]:\n", i);
6990 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
6991 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
6992 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
6993 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
6994 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
6995 if (INTEL_INFO(dev)->gen >= 4) {
6996 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
6997 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
6998 }
6999
7000 seq_printf(m, "Cursor [%d]:\n", i);
7001 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7002 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7003 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7004 }
7005}
7006#endif
Linux kernel - Deliverables
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