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drm/i915: Do a dummy DPCD read before the actual read
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
773538e8
VS		 293static void pps_lock(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct intel_encoder *encoder = &intel_dig_port->base;
297 struct drm_device *dev = encoder->base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
299 enum intel_display_power_domain power_domain;
300
301 /*
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
304 */
305 power_domain = intel_display_port_power_domain(encoder);
306 intel_display_power_get(dev_priv, power_domain);
307
308 mutex_lock(&dev_priv->pps_mutex);
309}
310
311static void pps_unlock(struct intel_dp *intel_dp)
312{
313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
314 struct intel_encoder *encoder = &intel_dig_port->base;
315 struct drm_device *dev = encoder->base.dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 enum intel_display_power_domain power_domain;
318
319 mutex_unlock(&dev_priv->pps_mutex);
320
321 power_domain = intel_display_port_power_domain(encoder);
322 intel_display_power_put(dev_priv, power_domain);
323}
324
bf13e81b
JN		 325static enum pipe
326vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 331 struct intel_encoder *encoder;
332 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
333 struct edp_power_seq power_seq;
bf13e81b 334
e39b999a 335 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 336
a4a5d2f8
VS		 337 if (intel_dp->pps_pipe != INVALID_PIPE)
338 return intel_dp->pps_pipe;
339
340 /*
341 * We don't have power sequencer currently.
342 * Pick one that's not used by other ports.
343 */
344 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
345 base.head) {
346 struct intel_dp *tmp;
347
348 if (encoder->type != INTEL_OUTPUT_EDP)
349 continue;
350
351 tmp = enc_to_intel_dp(&encoder->base);
352
353 if (tmp->pps_pipe != INVALID_PIPE)
354 pipes &= ~(1 << tmp->pps_pipe);
355 }
356
357 /*
358 * Didn't find one. This should not happen since there
359 * are two power sequencers and up to two eDP ports.
360 */
361 if (WARN_ON(pipes == 0))
362 return PIPE_A;
363
364 intel_dp->pps_pipe = ffs(pipes) - 1;
365
366 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
367 pipe_name(intel_dp->pps_pipe),
368 port_name(intel_dig_port->port));
369
370 /* init power sequencer on this pipe and port */
371 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
372 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
373 &power_seq);
374
375 return intel_dp->pps_pipe;
376}
377
6491ab27
VS		 378typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
379 enum pipe pipe);
380
381static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
382 enum pipe pipe)
383{
384 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
385}
386
387static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
388 enum pipe pipe)
389{
390 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
391}
392
393static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
394 enum pipe pipe)
395{
396 return true;
397}
bf13e81b 398
a4a5d2f8 399static enum pipe
6491ab27
VS		 400vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
401 enum port port,
402 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 403{
404 enum pipe pipe;
bf13e81b 405
bf13e81b
JN		 406 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
407 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
408 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 409
410 if (port_sel != PANEL_PORT_SELECT_VLV(port))
411 continue;
412
6491ab27
VS		 413 if (!pipe_check(dev_priv, pipe))
414 continue;
415
a4a5d2f8 416 return pipe;
bf13e81b
JN		 417 }
418
a4a5d2f8
VS		 419 return INVALID_PIPE;
420}
421
422static void
423vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
424{
425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
426 struct drm_device *dev = intel_dig_port->base.base.dev;
427 struct drm_i915_private *dev_priv = dev->dev_private;
428 struct edp_power_seq power_seq;
429 enum port port = intel_dig_port->port;
430
431 lockdep_assert_held(&dev_priv->pps_mutex);
432
433 /* try to find a pipe with this port selected */
6491ab27
VS		 434 /* first pick one where the panel is on */
435 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
436 vlv_pipe_has_pp_on);
437 /* didn't find one? pick one where vdd is on */
438 if (intel_dp->pps_pipe == INVALID_PIPE)
439 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
440 vlv_pipe_has_vdd_on);
441 /* didn't find one? pick one with just the correct port */
442 if (intel_dp->pps_pipe == INVALID_PIPE)
443 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
444 vlv_pipe_any);
a4a5d2f8
VS		 445
446 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
447 if (intel_dp->pps_pipe == INVALID_PIPE) {
448 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
449 port_name(port));
450 return;
bf13e81b
JN		 451 }
452
a4a5d2f8
VS		 453 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
454 port_name(port), pipe_name(intel_dp->pps_pipe));
455
456 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
457 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
458 &power_seq);
bf13e81b
JN		 459}
460
773538e8
VS		 461void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
462{
463 struct drm_device *dev = dev_priv->dev;
464 struct intel_encoder *encoder;
465
466 if (WARN_ON(!IS_VALLEYVIEW(dev)))
467 return;
468
469 /*
470 * We can't grab pps_mutex here due to deadlock with power_domain
471 * mutex when power_domain functions are called while holding pps_mutex.
472 * That also means that in order to use pps_pipe the code needs to
473 * hold both a power domain reference and pps_mutex, and the power domain
474 * reference get/put must be done while _not_ holding pps_mutex.
475 * pps_{lock,unlock}() do these steps in the correct order, so one
476 * should use them always.
477 */
478
479 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
480 struct intel_dp *intel_dp;
481
482 if (encoder->type != INTEL_OUTPUT_EDP)
483 continue;
484
485 intel_dp = enc_to_intel_dp(&encoder->base);
486 intel_dp->pps_pipe = INVALID_PIPE;
487 }
bf13e81b
JN		 488}
489
490static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
491{
492 struct drm_device *dev = intel_dp_to_dev(intel_dp);
493
494 if (HAS_PCH_SPLIT(dev))
495 return PCH_PP_CONTROL;
496 else
497 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
498}
499
500static u32 _pp_stat_reg(struct intel_dp *intel_dp)
501{
502 struct drm_device *dev = intel_dp_to_dev(intel_dp);
503
504 if (HAS_PCH_SPLIT(dev))
505 return PCH_PP_STATUS;
506 else
507 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
508}
509
01527b31
CT		 510/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
511 This function only applicable when panel PM state is not to be tracked */
512static int edp_notify_handler(struct notifier_block *this, unsigned long code,
513 void *unused)
514{
515 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
516 edp_notifier);
517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
518 struct drm_i915_private *dev_priv = dev->dev_private;
519 u32 pp_div;
520 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 521
522 if (!is_edp(intel_dp) || code != SYS_RESTART)
523 return 0;
524
773538e8 525 pps_lock(intel_dp);
e39b999a 526
01527b31 527 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 528 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
529
01527b31
CT		 530 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
531 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
532 pp_div = I915_READ(pp_div_reg);
533 pp_div &= PP_REFERENCE_DIVIDER_MASK;
534
535 /* 0x1F write to PP_DIV_REG sets max cycle delay */
536 I915_WRITE(pp_div_reg, pp_div | 0x1F);
537 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
538 msleep(intel_dp->panel_power_cycle_delay);
539 }
540
773538e8 541 pps_unlock(intel_dp);
e39b999a 542
01527b31
CT		 543 return 0;
544}
545
4be73780 546static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 547{
30add22d 548 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 549 struct drm_i915_private *dev_priv = dev->dev_private;
550
e39b999a
VS		 551 lockdep_assert_held(&dev_priv->pps_mutex);
552
bf13e81b 553 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 554}
555
4be73780 556static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 557{
30add22d 558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 559 struct drm_i915_private *dev_priv = dev->dev_private;
560
e39b999a
VS		 561 lockdep_assert_held(&dev_priv->pps_mutex);
562
773538e8 563 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 564}
565
9b984dae
KP		 566static void
567intel_dp_check_edp(struct intel_dp *intel_dp)
568{
30add22d 569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 570 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 571
9b984dae
KP		 572 if (!is_edp(intel_dp))
573 return;
453c5420 574
4be73780 575 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 576 WARN(1, "eDP powered off while attempting aux channel communication.\n");
577 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 578 I915_READ(_pp_stat_reg(intel_dp)),
579 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 580 }
581}
582
9ee32fea
DV		 583static uint32_t
584intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
585{
586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
587 struct drm_device *dev = intel_dig_port->base.base.dev;
588 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 589 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 590 uint32_t status;
591 bool done;
592
ef04f00d 593#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 594 if (has_aux_irq)
b18ac466 595 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 596 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 597 else
598 done = wait_for_atomic(C, 10) == 0;
599 if (!done)
600 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
601 has_aux_irq);
602#undef C
603
604 return status;
605}
606
ec5b01dd 607static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 608{
174edf1f
PZ		 609 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
610 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 611
ec5b01dd
DL		 612 /*
613 * The clock divider is based off the hrawclk, and would like to run at
614 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 615 */
ec5b01dd
DL		 616 return index ? 0 : intel_hrawclk(dev) / 2;
617}
618
619static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
620{
621 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
622 struct drm_device *dev = intel_dig_port->base.base.dev;
623
624 if (index)
625 return 0;
626
627 if (intel_dig_port->port == PORT_A) {
628 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 629 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 630 else
b84a1cf8 631 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 632 } else {
633 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
634 }
635}
636
637static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
638{
639 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
640 struct drm_device *dev = intel_dig_port->base.base.dev;
641 struct drm_i915_private *dev_priv = dev->dev_private;
642
643 if (intel_dig_port->port == PORT_A) {
644 if (index)
645 return 0;
646 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 647 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
648 /* Workaround for non-ULT HSW */
bc86625a
CW		 649 switch (index) {
650 case 0: return 63;
651 case 1: return 72;
652 default: return 0;
653 }
ec5b01dd 654 } else {
bc86625a 655 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 656 }
b84a1cf8
RV		 657}
658
ec5b01dd
DL		 659static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
660{
661 return index ? 0 : 100;
662}
663
5ed12a19
DL		 664static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
665 bool has_aux_irq,
666 int send_bytes,
667 uint32_t aux_clock_divider)
668{
669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
670 struct drm_device *dev = intel_dig_port->base.base.dev;
671 uint32_t precharge, timeout;
672
673 if (IS_GEN6(dev))
674 precharge = 3;
675 else
676 precharge = 5;
677
678 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
679 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
680 else
681 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
682
683 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 684 DP_AUX_CH_CTL_DONE |
5ed12a19 685 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 686 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 687 timeout |
788d4433 688 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 689 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
690 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 691 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 692}
693
b84a1cf8
RV		 694static int
695intel_dp_aux_ch(struct intel_dp *intel_dp,
696 uint8_t *send, int send_bytes,
697 uint8_t *recv, int recv_size)
698{
699 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
700 struct drm_device *dev = intel_dig_port->base.base.dev;
701 struct drm_i915_private *dev_priv = dev->dev_private;
702 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
703 uint32_t ch_data = ch_ctl + 4;
bc86625a 704 uint32_t aux_clock_divider;
b84a1cf8
RV		 705 int i, ret, recv_bytes;
706 uint32_t status;
5ed12a19 707 int try, clock = 0;
4e6b788c 708 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 709 bool vdd;
710
773538e8 711 pps_lock(intel_dp);
e39b999a 712
72c3500a
VS		 713 /*
714 * We will be called with VDD already enabled for dpcd/edid/oui reads.
715 * In such cases we want to leave VDD enabled and it's up to upper layers
716 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
717 * ourselves.
718 */
1e0560e0 719 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 720
721 /* dp aux is extremely sensitive to irq latency, hence request the
722 * lowest possible wakeup latency and so prevent the cpu from going into
723 * deep sleep states.
724 */
725 pm_qos_update_request(&dev_priv->pm_qos, 0);
726
727 intel_dp_check_edp(intel_dp);
5eb08b69 728
c67a470b
PZ		 729 intel_aux_display_runtime_get(dev_priv);
730
11bee43e
JB		 731 /* Try to wait for any previous AUX channel activity */
732 for (try = 0; try < 3; try++) {
ef04f00d 733 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 734 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
735 break;
736 msleep(1);
737 }
738
739 if (try == 3) {
740 WARN(1, "dp_aux_ch not started status 0x%08x\n",
741 I915_READ(ch_ctl));
9ee32fea
DV		 742 ret = -EBUSY;
743 goto out;
4f7f7b7e
CW		 744 }
745
46a5ae9f
PZ		 746 /* Only 5 data registers! */
747 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
748 ret = -E2BIG;
749 goto out;
750 }
751
ec5b01dd 752 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 753 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
754 has_aux_irq,
755 send_bytes,
756 aux_clock_divider);
5ed12a19 757
bc86625a
CW		 758 /* Must try at least 3 times according to DP spec */
759 for (try = 0; try < 5; try++) {
760 /* Load the send data into the aux channel data registers */
761 for (i = 0; i < send_bytes; i += 4)
762 I915_WRITE(ch_data + i,
763 pack_aux(send + i, send_bytes - i));
764
765 /* Send the command and wait for it to complete */
5ed12a19 766 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 767
768 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
769
770 /* Clear done status and any errors */
771 I915_WRITE(ch_ctl,
772 status |
773 DP_AUX_CH_CTL_DONE |
774 DP_AUX_CH_CTL_TIME_OUT_ERROR |
775 DP_AUX_CH_CTL_RECEIVE_ERROR);
776
777 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
778 DP_AUX_CH_CTL_RECEIVE_ERROR))
779 continue;
780 if (status & DP_AUX_CH_CTL_DONE)
781 break;
782 }
4f7f7b7e 783 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 784 break;
785 }
786
a4fc5ed6 787 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 788 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 789 ret = -EBUSY;
790 goto out;
a4fc5ed6
KP		 791 }
792
793 /* Check for timeout or receive error.
794 * Timeouts occur when the sink is not connected
795 */
a5b3da54 796 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 797 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 798 ret = -EIO;
799 goto out;
a5b3da54 800 }
1ae8c0a5
KP		 801
802 /* Timeouts occur when the device isn't connected, so they're
803 * "normal" -- don't fill the kernel log with these */
a5b3da54 804 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 805 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 806 ret = -ETIMEDOUT;
807 goto out;
a4fc5ed6
KP		 808 }
809
810 /* Unload any bytes sent back from the other side */
811 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
812 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 813 if (recv_bytes > recv_size)
814 recv_bytes = recv_size;
0206e353 815
4f7f7b7e
CW		 816 for (i = 0; i < recv_bytes; i += 4)
817 unpack_aux(I915_READ(ch_data + i),
818 recv + i, recv_bytes - i);
a4fc5ed6 819
9ee32fea
DV		 820 ret = recv_bytes;
821out:
822 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 823 intel_aux_display_runtime_put(dev_priv);
9ee32fea 824
884f19e9
JN		 825 if (vdd)
826 edp_panel_vdd_off(intel_dp, false);
827
773538e8 828 pps_unlock(intel_dp);
e39b999a 829
9ee32fea 830 return ret;
a4fc5ed6
KP		 831}
832
a6c8aff0
JN		 833#define BARE_ADDRESS_SIZE 3
834#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 835static ssize_t
836intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 837{
9d1a1031
JN		 838 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
839 uint8_t txbuf[20], rxbuf[20];
840 size_t txsize, rxsize;
a4fc5ed6 841 int ret;
a4fc5ed6 842
9d1a1031
JN		 843 txbuf[0] = msg->request << 4;
844 txbuf[1] = msg->address >> 8;
845 txbuf[2] = msg->address & 0xff;
846 txbuf[3] = msg->size - 1;
46a5ae9f 847
9d1a1031
JN		 848 switch (msg->request & ~DP_AUX_I2C_MOT) {
849 case DP_AUX_NATIVE_WRITE:
850 case DP_AUX_I2C_WRITE:
a6c8aff0 851 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 852 rxsize = 1;
f51a44b9 853
9d1a1031
JN		 854 if (WARN_ON(txsize > 20))
855 return -E2BIG;
a4fc5ed6 856
9d1a1031 857 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 858
9d1a1031
JN		 859 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
860 if (ret > 0) {
861 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 862
9d1a1031
JN		 863 /* Return payload size. */
864 ret = msg->size;
865 }
866 break;
46a5ae9f 867
9d1a1031
JN		 868 case DP_AUX_NATIVE_READ:
869 case DP_AUX_I2C_READ:
a6c8aff0 870 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 871 rxsize = msg->size + 1;
a4fc5ed6 872
9d1a1031
JN		 873 if (WARN_ON(rxsize > 20))
874 return -E2BIG;
a4fc5ed6 875
9d1a1031
JN		 876 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
877 if (ret > 0) {
878 msg->reply = rxbuf[0] >> 4;
879 /*
880 * Assume happy day, and copy the data. The caller is
881 * expected to check msg->reply before touching it.
882 *
883 * Return payload size.
884 */
885 ret--;
886 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 887 }
9d1a1031
JN		 888 break;
889
890 default:
891 ret = -EINVAL;
892 break;
a4fc5ed6 893 }
f51a44b9 894
9d1a1031 895 return ret;
a4fc5ed6
KP		 896}
897
9d1a1031
JN		 898static void
899intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
900{
901 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 902 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
903 enum port port = intel_dig_port->port;
0b99836f 904 const char *name = NULL;
ab2c0672
DA		 905 int ret;
906
33ad6626
JN		 907 switch (port) {
908 case PORT_A:
909 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 910 name = "DPDDC-A";
ab2c0672 911 break;
33ad6626
JN		 912 case PORT_B:
913 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 914 name = "DPDDC-B";
ab2c0672 915 break;
33ad6626
JN		 916 case PORT_C:
917 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 918 name = "DPDDC-C";
ab2c0672 919 break;
33ad6626
JN		 920 case PORT_D:
921 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 922 name = "DPDDC-D";
33ad6626
JN		 923 break;
924 default:
925 BUG();
ab2c0672
DA		 926 }
927
33ad6626
JN		 928 if (!HAS_DDI(dev))
929 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 930
0b99836f 931 intel_dp->aux.name = name;
9d1a1031
JN		 932 intel_dp->aux.dev = dev->dev;
933 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 934
0b99836f
JN		 935 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
936 connector->base.kdev->kobj.name);
8316f337 937
4f71d0cb 938 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 939 if (ret < 0) {
4f71d0cb 940 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 941 name, ret);
942 return;
ab2c0672 943 }
8a5e6aeb 944
0b99836f
JN		 945 ret = sysfs_create_link(&connector->base.kdev->kobj,
946 &intel_dp->aux.ddc.dev.kobj,
947 intel_dp->aux.ddc.dev.kobj.name);
948 if (ret < 0) {
949 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 950 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 951 }
a4fc5ed6
KP		 952}
953
80f65de3
ID		 954static void
955intel_dp_connector_unregister(struct intel_connector *intel_connector)
956{
957 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
958
0e32b39c
DA		 959 if (!intel_connector->mst_port)
960 sysfs_remove_link(&intel_connector->base.kdev->kobj,
961 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 962 intel_connector_unregister(intel_connector);
963}
964
0e50338c
DV		 965static void
966hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
967{
968 switch (link_bw) {
969 case DP_LINK_BW_1_62:
970 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
971 break;
972 case DP_LINK_BW_2_7:
973 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
974 break;
975 case DP_LINK_BW_5_4:
976 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
977 break;
978 }
979}
980
c6bb3538
DV		 981static void
982intel_dp_set_clock(struct intel_encoder *encoder,
983 struct intel_crtc_config *pipe_config, int link_bw)
984{
985 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 986 const struct dp_link_dpll *divisor = NULL;
987 int i, count = 0;
c6bb3538
DV		 988
989 if (IS_G4X(dev)) {
9dd4ffdf
CML		 990 divisor = gen4_dpll;
991 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 992 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 993 divisor = pch_dpll;
994 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 995 } else if (IS_CHERRYVIEW(dev)) {
996 divisor = chv_dpll;
997 count = ARRAY_SIZE(chv_dpll);
c6bb3538 998 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 999 divisor = vlv_dpll;
1000 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1001 }
9dd4ffdf
CML		 1002
1003 if (divisor && count) {
1004 for (i = 0; i < count; i++) {
1005 if (link_bw == divisor[i].link_bw) {
1006 pipe_config->dpll = divisor[i].dpll;
1007 pipe_config->clock_set = true;
1008 break;
1009 }
1010 }
c6bb3538
DV		 1011 }
1012}
1013
00c09d70 1014bool
5bfe2ac0
DV		 1015intel_dp_compute_config(struct intel_encoder *encoder,
1016 struct intel_crtc_config *pipe_config)
a4fc5ed6 1017{
5bfe2ac0 1018 struct drm_device *dev = encoder->base.dev;
36008365 1019 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1020 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1021 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1022 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1023 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1024 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1025 int lane_count, clock;
56071a20 1026 int min_lane_count = 1;
eeb6324d 1027 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1028 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1029 int min_clock = 0;
06ea66b6 1030 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1031 int bpp, mode_rate;
06ea66b6 1032 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1033 int link_avail, link_clock;
a4fc5ed6 1034
bc7d38a4 1035 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1036 pipe_config->has_pch_encoder = true;
1037
03afc4a2 1038 pipe_config->has_dp_encoder = true;
f769cd24 1039 pipe_config->has_drrs = false;
9ed109a7 1040 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1041
dd06f90e
JN		 1042 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1043 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1044 adjusted_mode);
2dd24552
JB		 1045 if (!HAS_PCH_SPLIT(dev))
1046 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1047 intel_connector->panel.fitting_mode);
1048 else
b074cec8
JB		 1049 intel_pch_panel_fitting(intel_crtc, pipe_config,
1050 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1051 }
1052
cb1793ce 1053 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1054 return false;
1055
083f9560
DV		 1056 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1057 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1058 max_lane_count, bws[max_clock],
1059 adjusted_mode->crtc_clock);
083f9560 1060
36008365
DV		 1061 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1062 * bpc in between. */
3e7ca985 1063 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1064 if (is_edp(intel_dp)) {
1065 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1066 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1067 dev_priv->vbt.edp_bpp);
1068 bpp = dev_priv->vbt.edp_bpp;
1069 }
1070
344c5bbc
JN		 1071 /*
1072 * Use the maximum clock and number of lanes the eDP panel
1073 * advertizes being capable of. The panels are generally
1074 * designed to support only a single clock and lane
1075 * configuration, and typically these values correspond to the
1076 * native resolution of the panel.
1077 */
1078 min_lane_count = max_lane_count;
1079 min_clock = max_clock;
7984211e 1080 }
657445fe 1081
36008365 1082 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1083 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1084 bpp);
36008365 1085
c6930992
DA		 1086 for (clock = min_clock; clock <= max_clock; clock++) {
1087 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1088 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1089 link_avail = intel_dp_max_data_rate(link_clock,
1090 lane_count);
1091
1092 if (mode_rate <= link_avail) {
1093 goto found;
1094 }
1095 }
1096 }
1097 }
c4867936 1098
36008365 1099 return false;
3685a8f3 1100
36008365 1101found:
55bc60db
VS		 1102 if (intel_dp->color_range_auto) {
1103 /*
1104 * See:
1105 * CEA-861-E - 5.1 Default Encoding Parameters
1106 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1107 */
18316c8c 1108 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1109 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1110 else
1111 intel_dp->color_range = 0;
1112 }
1113
3685a8f3 1114 if (intel_dp->color_range)
50f3b016 1115 pipe_config->limited_color_range = true;
a4fc5ed6 1116
36008365
DV		 1117 intel_dp->link_bw = bws[clock];
1118 intel_dp->lane_count = lane_count;
657445fe 1119 pipe_config->pipe_bpp = bpp;
ff9a6750 1120 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1121
36008365
DV		 1122 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1123 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1124 pipe_config->port_clock, bpp);
36008365
DV		 1125 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1126 mode_rate, link_avail);
a4fc5ed6 1127
03afc4a2 1128 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1129 adjusted_mode->crtc_clock,
1130 pipe_config->port_clock,
03afc4a2 1131 &pipe_config->dp_m_n);
9d1a455b 1132
439d7ac0
PB		 1133 if (intel_connector->panel.downclock_mode != NULL &&
1134 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1135 pipe_config->has_drrs = true;
439d7ac0
PB		 1136 intel_link_compute_m_n(bpp, lane_count,
1137 intel_connector->panel.downclock_mode->clock,
1138 pipe_config->port_clock,
1139 &pipe_config->dp_m2_n2);
1140 }
1141
ea155f32 1142 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1143 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1144 else
1145 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1146
03afc4a2 1147 return true;
a4fc5ed6
KP		 1148}
1149
7c62a164 1150static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1151{
7c62a164
DV		 1152 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1153 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1154 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1155 struct drm_i915_private *dev_priv = dev->dev_private;
1156 u32 dpa_ctl;
1157
ff9a6750 1158 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1159 dpa_ctl = I915_READ(DP_A);
1160 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1161
ff9a6750 1162 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1163 /* For a long time we've carried around a ILK-DevA w/a for the
1164 * 160MHz clock. If we're really unlucky, it's still required.
1165 */
1166 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1167 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1168 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1169 } else {
1170 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1171 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1172 }
1ce17038 1173
ea9b6006
DV		 1174 I915_WRITE(DP_A, dpa_ctl);
1175
1176 POSTING_READ(DP_A);
1177 udelay(500);
1178}
1179
8ac33ed3 1180static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1181{
b934223d 1182 struct drm_device *dev = encoder->base.dev;
417e822d 1183 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1184 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1185 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1186 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1187 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1188
417e822d 1189 /*
1a2eb460 1190 * There are four kinds of DP registers:
417e822d
KP		 1191 *
1192 * IBX PCH
1a2eb460
KP		 1193 * SNB CPU
1194 * IVB CPU
417e822d
KP		 1195 * CPT PCH
1196 *
1197 * IBX PCH and CPU are the same for almost everything,
1198 * except that the CPU DP PLL is configured in this
1199 * register
1200 *
1201 * CPT PCH is quite different, having many bits moved
1202 * to the TRANS_DP_CTL register instead. That
1203 * configuration happens (oddly) in ironlake_pch_enable
1204 */
9c9e7927 1205
417e822d
KP		 1206 /* Preserve the BIOS-computed detected bit. This is
1207 * supposed to be read-only.
1208 */
1209 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1210
417e822d 1211 /* Handle DP bits in common between all three register formats */
417e822d 1212 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1213 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1214
9ed109a7 1215 if (crtc->config.has_audio) {
e0dac65e 1216 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1217 pipe_name(crtc->pipe));
ea5b213a 1218 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1219 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1220 }
247d89f6 1221
417e822d 1222 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1223
bc7d38a4 1224 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1225 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1226 intel_dp->DP |= DP_SYNC_HS_HIGH;
1227 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1228 intel_dp->DP |= DP_SYNC_VS_HIGH;
1229 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1230
6aba5b6c 1231 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1232 intel_dp->DP |= DP_ENHANCED_FRAMING;
1233
7c62a164 1234 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1235 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1236 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1237 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1238
1239 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1240 intel_dp->DP |= DP_SYNC_HS_HIGH;
1241 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1242 intel_dp->DP |= DP_SYNC_VS_HIGH;
1243 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1244
6aba5b6c 1245 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1246 intel_dp->DP |= DP_ENHANCED_FRAMING;
1247
44f37d1f
CML		 1248 if (!IS_CHERRYVIEW(dev)) {
1249 if (crtc->pipe == 1)
1250 intel_dp->DP |= DP_PIPEB_SELECT;
1251 } else {
1252 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1253 }
417e822d
KP		 1254 } else {
1255 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1256 }
a4fc5ed6
KP		 1257}
1258
ffd6749d
PZ		 1259#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1260#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1261
1a5ef5b7
PZ		 1262#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1263#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1264
ffd6749d
PZ		 1265#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1266#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1267
4be73780 1268static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1269 u32 mask,
1270 u32 value)
bd943159 1271{
30add22d 1272 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1273 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1274 u32 pp_stat_reg, pp_ctrl_reg;
1275
e39b999a
VS		 1276 lockdep_assert_held(&dev_priv->pps_mutex);
1277
bf13e81b
JN		 1278 pp_stat_reg = _pp_stat_reg(intel_dp);
1279 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1280
99ea7127 1281 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1282 mask, value,
1283 I915_READ(pp_stat_reg),
1284 I915_READ(pp_ctrl_reg));
32ce697c 1285
453c5420 1286 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1287 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1288 I915_READ(pp_stat_reg),
1289 I915_READ(pp_ctrl_reg));
32ce697c 1290 }
54c136d4
CW		 1291
1292 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1293}
32ce697c 1294
4be73780 1295static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1296{
1297 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1298 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1299}
1300
4be73780 1301static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1302{
1303 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1304 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1305}
1306
4be73780 1307static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1308{
1309 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1310
1311 /* When we disable the VDD override bit last we have to do the manual
1312 * wait. */
1313 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1314 intel_dp->panel_power_cycle_delay);
1315
4be73780 1316 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1317}
1318
4be73780 1319static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1320{
1321 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1322 intel_dp->backlight_on_delay);
1323}
1324
4be73780 1325static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1326{
1327 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1328 intel_dp->backlight_off_delay);
1329}
99ea7127 1330
832dd3c1
KP		 1331/* Read the current pp_control value, unlocking the register if it
1332 * is locked
1333 */
1334
453c5420 1335static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1336{
453c5420
JB		 1337 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1338 struct drm_i915_private *dev_priv = dev->dev_private;
1339 u32 control;
832dd3c1 1340
e39b999a
VS		 1341 lockdep_assert_held(&dev_priv->pps_mutex);
1342
bf13e81b 1343 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1344 control &= ~PANEL_UNLOCK_MASK;
1345 control |= PANEL_UNLOCK_REGS;
1346 return control;
bd943159
KP		 1347}
1348
951468f3
VS		 1349/*
1350 * Must be paired with edp_panel_vdd_off().
1351 * Must hold pps_mutex around the whole on/off sequence.
1352 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1353 */
1e0560e0 1354static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1355{
30add22d 1356 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1358 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1359 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1360 enum intel_display_power_domain power_domain;
5d613501 1361 u32 pp;
453c5420 1362 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1363 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1364
e39b999a
VS		 1365 lockdep_assert_held(&dev_priv->pps_mutex);
1366
97af61f5 1367 if (!is_edp(intel_dp))
adddaaf4 1368 return false;
bd943159
KP		 1369
1370 intel_dp->want_panel_vdd = true;
99ea7127 1371
4be73780 1372 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1373 return need_to_disable;
b0665d57 1374
4e6e1a54
ID		 1375 power_domain = intel_display_port_power_domain(intel_encoder);
1376 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1377
b0665d57 1378 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1379
4be73780
DV		 1380 if (!edp_have_panel_power(intel_dp))
1381 wait_panel_power_cycle(intel_dp);
99ea7127 1382
453c5420 1383 pp = ironlake_get_pp_control(intel_dp);
5d613501 1384 pp |= EDP_FORCE_VDD;
ebf33b18 1385
bf13e81b
JN		 1386 pp_stat_reg = _pp_stat_reg(intel_dp);
1387 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1388
1389 I915_WRITE(pp_ctrl_reg, pp);
1390 POSTING_READ(pp_ctrl_reg);
1391 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1392 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1393 /*
1394 * If the panel wasn't on, delay before accessing aux channel
1395 */
4be73780 1396 if (!edp_have_panel_power(intel_dp)) {
bd943159 1397 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1398 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1399 }
adddaaf4
JN		 1400
1401 return need_to_disable;
1402}
1403
951468f3
VS		 1404/*
1405 * Must be paired with intel_edp_panel_vdd_off() or
1406 * intel_edp_panel_off().
1407 * Nested calls to these functions are not allowed since
1408 * we drop the lock. Caller must use some higher level
1409 * locking to prevent nested calls from other threads.
1410 */
b80d6c78 1411void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1412{
c695b6b6 1413 bool vdd;
adddaaf4 1414
c695b6b6
VS		 1415 if (!is_edp(intel_dp))
1416 return;
1417
773538e8 1418 pps_lock(intel_dp);
c695b6b6 1419 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1420 pps_unlock(intel_dp);
c695b6b6
VS		 1421
1422 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1423}
1424
4be73780 1425static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1426{
30add22d 1427 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1428 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1429 struct intel_digital_port *intel_dig_port =
1430 dp_to_dig_port(intel_dp);
1431 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1432 enum intel_display_power_domain power_domain;
5d613501 1433 u32 pp;
453c5420 1434 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1435
e39b999a 1436 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1437
15e899a0 1438 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1439
15e899a0 1440 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1441 return;
b0665d57 1442
be2c9196 1443 DRM_DEBUG_KMS("Turning eDP VDD off\n");
bd943159 1444
be2c9196
VS		 1445 pp = ironlake_get_pp_control(intel_dp);
1446 pp &= ~EDP_FORCE_VDD;
453c5420 1447
be2c9196
VS		 1448 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1449 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1450
be2c9196
VS		 1451 I915_WRITE(pp_ctrl_reg, pp);
1452 POSTING_READ(pp_ctrl_reg);
90791a5c 1453
be2c9196
VS		 1454 /* Make sure sequencer is idle before allowing subsequent activity */
1455 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1456 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1457
be2c9196
VS		 1458 if ((pp & POWER_TARGET_ON) == 0)
1459 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1460
be2c9196
VS		 1461 power_domain = intel_display_port_power_domain(intel_encoder);
1462 intel_display_power_put(dev_priv, power_domain);
bd943159 1463}
5d613501 1464
4be73780 1465static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1466{
1467 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1468 struct intel_dp, panel_vdd_work);
bd943159 1469
773538e8 1470 pps_lock(intel_dp);
15e899a0
VS		 1471 if (!intel_dp->want_panel_vdd)
1472 edp_panel_vdd_off_sync(intel_dp);
773538e8 1473 pps_unlock(intel_dp);
bd943159
KP		 1474}
1475
aba86890
ID		 1476static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1477{
1478 unsigned long delay;
1479
1480 /*
1481 * Queue the timer to fire a long time from now (relative to the power
1482 * down delay) to keep the panel power up across a sequence of
1483 * operations.
1484 */
1485 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1486 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1487}
1488
951468f3
VS		 1489/*
1490 * Must be paired with edp_panel_vdd_on().
1491 * Must hold pps_mutex around the whole on/off sequence.
1492 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1493 */
4be73780 1494static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1495{
e39b999a
VS		 1496 struct drm_i915_private *dev_priv =
1497 intel_dp_to_dev(intel_dp)->dev_private;
1498
1499 lockdep_assert_held(&dev_priv->pps_mutex);
1500
97af61f5
KP		 1501 if (!is_edp(intel_dp))
1502 return;
5d613501 1503
bd943159 1504 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1505
bd943159
KP		 1506 intel_dp->want_panel_vdd = false;
1507
aba86890 1508 if (sync)
4be73780 1509 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1510 else
1511 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1512}
1513
951468f3
VS		 1514/*
1515 * Must be paired with intel_edp_panel_vdd_on().
1516 * Nested calls to these functions are not allowed since
1517 * we drop the lock. Caller must use some higher level
1518 * locking to prevent nested calls from other threads.
1519 */
1e0560e0
VS		 1520static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1521{
e39b999a
VS		 1522 if (!is_edp(intel_dp))
1523 return;
1524
773538e8 1525 pps_lock(intel_dp);
1e0560e0 1526 edp_panel_vdd_off(intel_dp, sync);
773538e8 1527 pps_unlock(intel_dp);
1e0560e0
VS		 1528}
1529
4be73780 1530void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1531{
30add22d 1532 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1533 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1534 u32 pp;
453c5420 1535 u32 pp_ctrl_reg;
9934c132 1536
97af61f5 1537 if (!is_edp(intel_dp))
bd943159 1538 return;
99ea7127
KP		 1539
1540 DRM_DEBUG_KMS("Turn eDP power on\n");
1541
773538e8 1542 pps_lock(intel_dp);
e39b999a 1543
4be73780 1544 if (edp_have_panel_power(intel_dp)) {
99ea7127 1545 DRM_DEBUG_KMS("eDP power already on\n");
e39b999a 1546 goto out;
99ea7127 1547 }
9934c132 1548
4be73780 1549 wait_panel_power_cycle(intel_dp);
37c6c9b0 1550
bf13e81b 1551 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1552 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1553 if (IS_GEN5(dev)) {
1554 /* ILK workaround: disable reset around power sequence */
1555 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1556 I915_WRITE(pp_ctrl_reg, pp);
1557 POSTING_READ(pp_ctrl_reg);
05ce1a49 1558 }
37c6c9b0 1559
1c0ae80a 1560 pp |= POWER_TARGET_ON;
99ea7127
KP		 1561 if (!IS_GEN5(dev))
1562 pp |= PANEL_POWER_RESET;
1563
453c5420
JB		 1564 I915_WRITE(pp_ctrl_reg, pp);
1565 POSTING_READ(pp_ctrl_reg);
9934c132 1566
4be73780 1567 wait_panel_on(intel_dp);
dce56b3c 1568 intel_dp->last_power_on = jiffies;
9934c132 1569
05ce1a49
KP		 1570 if (IS_GEN5(dev)) {
1571 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1572 I915_WRITE(pp_ctrl_reg, pp);
1573 POSTING_READ(pp_ctrl_reg);
05ce1a49 1574 }
e39b999a
VS		 1575
1576 out:
773538e8 1577 pps_unlock(intel_dp);
9934c132
JB		 1578}
1579
4be73780 1580void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1581{
4e6e1a54
ID		 1582 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1583 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1584 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1585 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1586 enum intel_display_power_domain power_domain;
99ea7127 1587 u32 pp;
453c5420 1588 u32 pp_ctrl_reg;
9934c132 1589
97af61f5
KP		 1590 if (!is_edp(intel_dp))
1591 return;
37c6c9b0 1592
99ea7127 1593 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1594
773538e8 1595 pps_lock(intel_dp);
e39b999a 1596
24f3e092
JN		 1597 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1598
453c5420 1599 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1600 /* We need to switch off panel power _and_ force vdd, for otherwise some
1601 * panels get very unhappy and cease to work. */
b3064154
PJ		 1602 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1603 EDP_BLC_ENABLE);
453c5420 1604
bf13e81b 1605 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1606
849e39f5
PZ		 1607 intel_dp->want_panel_vdd = false;
1608
453c5420
JB		 1609 I915_WRITE(pp_ctrl_reg, pp);
1610 POSTING_READ(pp_ctrl_reg);
9934c132 1611
dce56b3c 1612 intel_dp->last_power_cycle = jiffies;
4be73780 1613 wait_panel_off(intel_dp);
849e39f5
PZ		 1614
1615 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1616 power_domain = intel_display_port_power_domain(intel_encoder);
1617 intel_display_power_put(dev_priv, power_domain);
e39b999a 1618
773538e8 1619 pps_unlock(intel_dp);
9934c132
JB		 1620}
1621
1250d107
JN		 1622/* Enable backlight in the panel power control. */
1623static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1624{
da63a9f2
PZ		 1625 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1626 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1627 struct drm_i915_private *dev_priv = dev->dev_private;
1628 u32 pp;
453c5420 1629 u32 pp_ctrl_reg;
32f9d658 1630
01cb9ea6
JB		 1631 /*
1632 * If we enable the backlight right away following a panel power
1633 * on, we may see slight flicker as the panel syncs with the eDP
1634 * link. So delay a bit to make sure the image is solid before
1635 * allowing it to appear.
1636 */
4be73780 1637 wait_backlight_on(intel_dp);
e39b999a 1638
773538e8 1639 pps_lock(intel_dp);
e39b999a 1640
453c5420 1641 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1642 pp |= EDP_BLC_ENABLE;
453c5420 1643
bf13e81b 1644 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1645
1646 I915_WRITE(pp_ctrl_reg, pp);
1647 POSTING_READ(pp_ctrl_reg);
e39b999a 1648
773538e8 1649 pps_unlock(intel_dp);
32f9d658
ZW		 1650}
1651
1250d107
JN		 1652/* Enable backlight PWM and backlight PP control. */
1653void intel_edp_backlight_on(struct intel_dp *intel_dp)
1654{
1655 if (!is_edp(intel_dp))
1656 return;
1657
1658 DRM_DEBUG_KMS("\n");
1659
1660 intel_panel_enable_backlight(intel_dp->attached_connector);
1661 _intel_edp_backlight_on(intel_dp);
1662}
1663
1664/* Disable backlight in the panel power control. */
1665static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1666{
30add22d 1667 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 u32 pp;
453c5420 1670 u32 pp_ctrl_reg;
32f9d658 1671
f01eca2e
KP		 1672 if (!is_edp(intel_dp))
1673 return;
1674
773538e8 1675 pps_lock(intel_dp);
e39b999a 1676
453c5420 1677 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1678 pp &= ~EDP_BLC_ENABLE;
453c5420 1679
bf13e81b 1680 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1681
1682 I915_WRITE(pp_ctrl_reg, pp);
1683 POSTING_READ(pp_ctrl_reg);
f7d2323c 1684
773538e8 1685 pps_unlock(intel_dp);
e39b999a
VS		 1686
1687 intel_dp->last_backlight_off = jiffies;
f7d2323c 1688 edp_wait_backlight_off(intel_dp);
1250d107 1689}
f7d2323c 1690
1250d107
JN		 1691/* Disable backlight PP control and backlight PWM. */
1692void intel_edp_backlight_off(struct intel_dp *intel_dp)
1693{
1694 if (!is_edp(intel_dp))
1695 return;
1696
1697 DRM_DEBUG_KMS("\n");
f7d2323c 1698
1250d107 1699 _intel_edp_backlight_off(intel_dp);
f7d2323c 1700 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1701}
a4fc5ed6 1702
73580fb7
JN		 1703/*
1704 * Hook for controlling the panel power control backlight through the bl_power
1705 * sysfs attribute. Take care to handle multiple calls.
1706 */
1707static void intel_edp_backlight_power(struct intel_connector *connector,
1708 bool enable)
1709{
1710 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1711 bool is_enabled;
1712
773538e8 1713 pps_lock(intel_dp);
e39b999a 1714 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1715 pps_unlock(intel_dp);
73580fb7
JN		 1716
1717 if (is_enabled == enable)
1718 return;
1719
23ba9373
JN		 1720 DRM_DEBUG_KMS("panel power control backlight %s\n",
1721 enable ? "enable" : "disable");
73580fb7
JN		 1722
1723 if (enable)
1724 _intel_edp_backlight_on(intel_dp);
1725 else
1726 _intel_edp_backlight_off(intel_dp);
1727}
1728
2bd2ad64 1729static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1730{
da63a9f2
PZ		 1731 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1732 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1733 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1734 struct drm_i915_private *dev_priv = dev->dev_private;
1735 u32 dpa_ctl;
1736
2bd2ad64
DV		 1737 assert_pipe_disabled(dev_priv,
1738 to_intel_crtc(crtc)->pipe);
1739
d240f20f
JB		 1740 DRM_DEBUG_KMS("\n");
1741 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1742 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1743 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1744
1745 /* We don't adjust intel_dp->DP while tearing down the link, to
1746 * facilitate link retraining (e.g. after hotplug). Hence clear all
1747 * enable bits here to ensure that we don't enable too much. */
1748 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1749 intel_dp->DP |= DP_PLL_ENABLE;
1750 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1751 POSTING_READ(DP_A);
1752 udelay(200);
d240f20f
JB		 1753}
1754
2bd2ad64 1755static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1756{
da63a9f2
PZ		 1757 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1758 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1759 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1760 struct drm_i915_private *dev_priv = dev->dev_private;
1761 u32 dpa_ctl;
1762
2bd2ad64
DV		 1763 assert_pipe_disabled(dev_priv,
1764 to_intel_crtc(crtc)->pipe);
1765
d240f20f 1766 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1767 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1768 "dp pll off, should be on\n");
1769 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1770
1771 /* We can't rely on the value tracked for the DP register in
1772 * intel_dp->DP because link_down must not change that (otherwise link
1773 * re-training will fail. */
298b0b39 1774 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1775 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1776 POSTING_READ(DP_A);
d240f20f
JB		 1777 udelay(200);
1778}
1779
c7ad3810 1780/* If the sink supports it, try to set the power state appropriately */
c19b0669 1781void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1782{
1783 int ret, i;
1784
1785 /* Should have a valid DPCD by this point */
1786 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1787 return;
1788
1789 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1790 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1791 DP_SET_POWER_D3);
c7ad3810
JB		 1792 } else {
1793 /*
1794 * When turning on, we need to retry for 1ms to give the sink
1795 * time to wake up.
1796 */
1797 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1798 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1799 DP_SET_POWER_D0);
c7ad3810
JB		 1800 if (ret == 1)
1801 break;
1802 msleep(1);
1803 }
1804 }
f9cac721
JN		 1805
1806 if (ret != 1)
1807 DRM_DEBUG_KMS("failed to %s sink power state\n",
1808 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1809}
1810
19d8fe15
DV		 1811static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1812 enum pipe *pipe)
d240f20f 1813{
19d8fe15 1814 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1815 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1816 struct drm_device *dev = encoder->base.dev;
1817 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1818 enum intel_display_power_domain power_domain;
1819 u32 tmp;
1820
1821 power_domain = intel_display_port_power_domain(encoder);
1822 if (!intel_display_power_enabled(dev_priv, power_domain))
1823 return false;
1824
1825 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1826
1827 if (!(tmp & DP_PORT_EN))
1828 return false;
1829
bc7d38a4 1830 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1831 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1832 } else if (IS_CHERRYVIEW(dev)) {
1833 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1834 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1835 *pipe = PORT_TO_PIPE(tmp);
1836 } else {
1837 u32 trans_sel;
1838 u32 trans_dp;
1839 int i;
1840
1841 switch (intel_dp->output_reg) {
1842 case PCH_DP_B:
1843 trans_sel = TRANS_DP_PORT_SEL_B;
1844 break;
1845 case PCH_DP_C:
1846 trans_sel = TRANS_DP_PORT_SEL_C;
1847 break;
1848 case PCH_DP_D:
1849 trans_sel = TRANS_DP_PORT_SEL_D;
1850 break;
1851 default:
1852 return true;
1853 }
1854
055e393f 1855 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1856 trans_dp = I915_READ(TRANS_DP_CTL(i));
1857 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1858 *pipe = i;
1859 return true;
1860 }
1861 }
19d8fe15 1862
4a0833ec
DV		 1863 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1864 intel_dp->output_reg);
1865 }
d240f20f 1866
19d8fe15
DV		 1867 return true;
1868}
d240f20f 1869
045ac3b5
JB		 1870static void intel_dp_get_config(struct intel_encoder *encoder,
1871 struct intel_crtc_config *pipe_config)
1872{
1873 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1874 u32 tmp, flags = 0;
63000ef6
XZ		 1875 struct drm_device *dev = encoder->base.dev;
1876 struct drm_i915_private *dev_priv = dev->dev_private;
1877 enum port port = dp_to_dig_port(intel_dp)->port;
1878 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1879 int dotclock;
045ac3b5 1880
9ed109a7
DV		 1881 tmp = I915_READ(intel_dp->output_reg);
1882 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1883 pipe_config->has_audio = true;
1884
63000ef6 1885 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1886 if (tmp & DP_SYNC_HS_HIGH)
1887 flags |= DRM_MODE_FLAG_PHSYNC;
1888 else
1889 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1890
63000ef6
XZ		 1891 if (tmp & DP_SYNC_VS_HIGH)
1892 flags |= DRM_MODE_FLAG_PVSYNC;
1893 else
1894 flags |= DRM_MODE_FLAG_NVSYNC;
1895 } else {
1896 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1897 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1898 flags |= DRM_MODE_FLAG_PHSYNC;
1899 else
1900 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1901
63000ef6
XZ		 1902 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1903 flags |= DRM_MODE_FLAG_PVSYNC;
1904 else
1905 flags |= DRM_MODE_FLAG_NVSYNC;
1906 }
045ac3b5
JB		 1907
1908 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1909
8c875fca
VS		 1910 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1911 tmp & DP_COLOR_RANGE_16_235)
1912 pipe_config->limited_color_range = true;
1913
eb14cb74
VS		 1914 pipe_config->has_dp_encoder = true;
1915
1916 intel_dp_get_m_n(crtc, pipe_config);
1917
18442d08 1918 if (port == PORT_A) {
f1f644dc
JB		 1919 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1920 pipe_config->port_clock = 162000;
1921 else
1922 pipe_config->port_clock = 270000;
1923 }
18442d08
VS		 1924
1925 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1926 &pipe_config->dp_m_n);
1927
1928 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1929 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1930
241bfc38 1931 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1932
c6cd2ee2
JN		 1933 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1934 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1935 /*
1936 * This is a big fat ugly hack.
1937 *
1938 * Some machines in UEFI boot mode provide us a VBT that has 18
1939 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1940 * unknown we fail to light up. Yet the same BIOS boots up with
1941 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1942 * max, not what it tells us to use.
1943 *
1944 * Note: This will still be broken if the eDP panel is not lit
1945 * up by the BIOS, and thus we can't get the mode at module
1946 * load.
1947 */
1948 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1949 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1950 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1951 }
045ac3b5
JB		 1952}
1953
34eb7579 1954static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1955{
34eb7579 1956 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1957}
1958
2b28bb1b
RV		 1959static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1960{
1961 struct drm_i915_private *dev_priv = dev->dev_private;
1962
18b5992c 1963 if (!HAS_PSR(dev))
2b28bb1b
RV		 1964 return false;
1965
18b5992c 1966 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1967}
1968
1969static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1970 struct edp_vsc_psr *vsc_psr)
1971{
1972 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1973 struct drm_device *dev = dig_port->base.base.dev;
1974 struct drm_i915_private *dev_priv = dev->dev_private;
1975 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1976 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1977 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1978 uint32_t *data = (uint32_t *) vsc_psr;
1979 unsigned int i;
1980
1981 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1982 the video DIP being updated before program video DIP data buffer
1983 registers for DIP being updated. */
1984 I915_WRITE(ctl_reg, 0);
1985 POSTING_READ(ctl_reg);
1986
1987 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1988 if (i < sizeof(struct edp_vsc_psr))
1989 I915_WRITE(data_reg + i, *data++);
1990 else
1991 I915_WRITE(data_reg + i, 0);
1992 }
1993
1994 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1995 POSTING_READ(ctl_reg);
1996}
1997
1998static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1999{
2000 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2002 struct edp_vsc_psr psr_vsc;
2003
2b28bb1b
RV		 2004 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2005 memset(&psr_vsc, 0, sizeof(psr_vsc));
2006 psr_vsc.sdp_header.HB0 = 0;
2007 psr_vsc.sdp_header.HB1 = 0x7;
2008 psr_vsc.sdp_header.HB2 = 0x2;
2009 psr_vsc.sdp_header.HB3 = 0x8;
2010 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2011
2012 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 2013 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 2014 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 2015}
2016
2017static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2018{
0e0ae652
RV		 2019 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2020 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2021 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2022 uint32_t aux_clock_divider;
2b28bb1b
RV		 2023 int precharge = 0x3;
2024 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 2025 bool only_standby = false;
2b28bb1b 2026
ec5b01dd
DL		 2027 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2028
0e0ae652
RV		 2029 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2030 only_standby = true;
2031
2b28bb1b 2032 /* Enable PSR in sink */
0e0ae652 2033 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2034 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2035 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2036 else
9d1a1031
JN		 2037 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2038 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2039
2040 /* Setup AUX registers */
18b5992c
BW		 2041 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
2042 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
2043 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 2044 DP_AUX_CH_CTL_TIME_OUT_400us |
2045 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2046 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2047 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2048}
2049
2050static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2051{
0e0ae652
RV		 2052 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2053 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2054 struct drm_i915_private *dev_priv = dev->dev_private;
2055 uint32_t max_sleep_time = 0x1f;
2056 uint32_t idle_frames = 1;
2057 uint32_t val = 0x0;
ed8546ac 2058 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2059 bool only_standby = false;
2060
2061 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2062 only_standby = true;
2b28bb1b 2063
0e0ae652 2064 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2065 val |= EDP_PSR_LINK_STANDBY;
2066 val |= EDP_PSR_TP2_TP3_TIME_0us;
2067 val |= EDP_PSR_TP1_TIME_0us;
2068 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2069 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2070 } else
2071 val |= EDP_PSR_LINK_DISABLE;
2072
18b5992c 2073 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2074 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2075 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2076 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2077 EDP_PSR_ENABLE);
2078}
2079
3f51e471
RV		 2080static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2081{
2082 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2083 struct drm_device *dev = dig_port->base.base.dev;
2084 struct drm_i915_private *dev_priv = dev->dev_private;
2085 struct drm_crtc *crtc = dig_port->base.base.crtc;
2086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2087
f0355c4a 2088 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2089 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2090 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2091
a031d709
RV		 2092 dev_priv->psr.source_ok = false;
2093
9ca15301 2094 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2095 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2096 return false;
2097 }
2098
d330a953 2099 if (!i915.enable_psr) {
105b7c11 2100 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2101 return false;
2102 }
2103
4c8c7000
RV		 2104 /* Below limitations aren't valid for Broadwell */
2105 if (IS_BROADWELL(dev))
2106 goto out;
2107
3f51e471
RV		 2108 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2109 S3D_ENABLE) {
2110 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2111 return false;
2112 }
2113
ca73b4f0 2114 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2115 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2116 return false;
2117 }
2118
4c8c7000 2119 out:
a031d709 2120 dev_priv->psr.source_ok = true;
3f51e471
RV		 2121 return true;
2122}
2123
3d739d92 2124static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2125{
7c8f8a70
RV		 2126 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2127 struct drm_device *dev = intel_dig_port->base.base.dev;
2128 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2129
3638379c
DV		 2130 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2131 WARN_ON(dev_priv->psr.active);
f0355c4a 2132 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2133
2b28bb1b
RV		 2134 /* Enable PSR on the panel */
2135 intel_edp_psr_enable_sink(intel_dp);
2136
2137 /* Enable PSR on the host */
2138 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2139
7c8f8a70 2140 dev_priv->psr.active = true;
2b28bb1b
RV		 2141}
2142
3d739d92
RV		 2143void intel_edp_psr_enable(struct intel_dp *intel_dp)
2144{
2145 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2146 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2147
4704c573
RV		 2148 if (!HAS_PSR(dev)) {
2149 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2150 return;
2151 }
2152
34eb7579
RV		 2153 if (!is_edp_psr(intel_dp)) {
2154 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2155 return;
2156 }
2157
f0355c4a 2158 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2159 if (dev_priv->psr.enabled) {
2160 DRM_DEBUG_KMS("PSR already in use\n");
f0355c4a 2161 mutex_unlock(&dev_priv->psr.lock);
109fc2ad
DV		 2162 return;
2163 }
2164
9ca15301
DV		 2165 dev_priv->psr.busy_frontbuffer_bits = 0;
2166
16487254
RV		 2167 /* Setup PSR once */
2168 intel_edp_psr_setup(intel_dp);
2169
7c8f8a70 2170 if (intel_edp_psr_match_conditions(intel_dp))
9ca15301 2171 dev_priv->psr.enabled = intel_dp;
f0355c4a 2172 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2173}
2174
2b28bb1b
RV		 2175void intel_edp_psr_disable(struct intel_dp *intel_dp)
2176{
2177 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2178 struct drm_i915_private *dev_priv = dev->dev_private;
2179
f0355c4a
DV		 2180 mutex_lock(&dev_priv->psr.lock);
2181 if (!dev_priv->psr.enabled) {
2182 mutex_unlock(&dev_priv->psr.lock);
2183 return;
2184 }
2185
3638379c
DV		 2186 if (dev_priv->psr.active) {
2187 I915_WRITE(EDP_PSR_CTL(dev),
2188 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2189
2190 /* Wait till PSR is idle */
2191 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2192 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2193 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2194
3638379c
DV		 2195 dev_priv->psr.active = false;
2196 } else {
2197 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2198 }
7c8f8a70 2199
2807cf69 2200 dev_priv->psr.enabled = NULL;
f0355c4a 2201 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2202
2203 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2204}
2205
f02a326e 2206static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2207{
2208 struct drm_i915_private *dev_priv =
2209 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2210 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2211
f0355c4a
DV		 2212 mutex_lock(&dev_priv->psr.lock);
2213 intel_dp = dev_priv->psr.enabled;
2214
2807cf69 2215 if (!intel_dp)
f0355c4a 2216 goto unlock;
2807cf69 2217
9ca15301
DV		 2218 /*
2219 * The delayed work can race with an invalidate hence we need to
2220 * recheck. Since psr_flush first clears this and then reschedules we
2221 * won't ever miss a flush when bailing out here.
2222 */
2223 if (dev_priv->psr.busy_frontbuffer_bits)
2224 goto unlock;
2225
2226 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2227unlock:
2228 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2229}
2230
9ca15301 2231static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2232{
2233 struct drm_i915_private *dev_priv = dev->dev_private;
2234
3638379c
DV		 2235 if (dev_priv->psr.active) {
2236 u32 val = I915_READ(EDP_PSR_CTL(dev));
2237
2238 WARN_ON(!(val & EDP_PSR_ENABLE));
2239
2240 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2241
2242 dev_priv->psr.active = false;
2243 }
7c8f8a70 2244
9ca15301
DV		 2245}
2246
2247void intel_edp_psr_invalidate(struct drm_device *dev,
2248 unsigned frontbuffer_bits)
2249{
2250 struct drm_i915_private *dev_priv = dev->dev_private;
2251 struct drm_crtc *crtc;
2252 enum pipe pipe;
2253
9ca15301
DV		 2254 mutex_lock(&dev_priv->psr.lock);
2255 if (!dev_priv->psr.enabled) {
2256 mutex_unlock(&dev_priv->psr.lock);
2257 return;
2258 }
2259
2260 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2261 pipe = to_intel_crtc(crtc)->pipe;
2262
2263 intel_edp_psr_do_exit(dev);
2264
2265 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2266
2267 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2268 mutex_unlock(&dev_priv->psr.lock);
2269}
2270
2271void intel_edp_psr_flush(struct drm_device *dev,
2272 unsigned frontbuffer_bits)
2273{
2274 struct drm_i915_private *dev_priv = dev->dev_private;
2275 struct drm_crtc *crtc;
2276 enum pipe pipe;
2277
9ca15301
DV		 2278 mutex_lock(&dev_priv->psr.lock);
2279 if (!dev_priv->psr.enabled) {
2280 mutex_unlock(&dev_priv->psr.lock);
2281 return;
2282 }
2283
2284 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2285 pipe = to_intel_crtc(crtc)->pipe;
2286 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2287
2288 /*
2289 * On Haswell sprite plane updates don't result in a psr invalidating
2290 * signal in the hardware. Which means we need to manually fake this in
2291 * software for all flushes, not just when we've seen a preceding
2292 * invalidation through frontbuffer rendering.
2293 */
2294 if (IS_HASWELL(dev) &&
2295 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2296 intel_edp_psr_do_exit(dev);
2297
2298 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2299 schedule_delayed_work(&dev_priv->psr.work,
2300 msecs_to_jiffies(100));
f0355c4a 2301 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2302}
2303
2304void intel_edp_psr_init(struct drm_device *dev)
2305{
2306 struct drm_i915_private *dev_priv = dev->dev_private;
2307
7c8f8a70 2308 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2309 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2310}
2311
e8cb4558 2312static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2313{
e8cb4558 2314 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2315 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2316
2317 /* Make sure the panel is off before trying to change the mode. But also
2318 * ensure that we have vdd while we switch off the panel. */
24f3e092 2319 intel_edp_panel_vdd_on(intel_dp);
4be73780 2320 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2321 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2322 intel_edp_panel_off(intel_dp);
3739850b 2323
08aff3fe
VS		 2324 /* disable the port before the pipe on g4x */
2325 if (INTEL_INFO(dev)->gen < 5)
3739850b 2326 intel_dp_link_down(intel_dp);
d240f20f
JB		 2327}
2328
08aff3fe 2329static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2330{
2bd2ad64 2331 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2332 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2333
49277c31 2334 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2335 if (port == PORT_A)
2336 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2337}
2338
2339static void vlv_post_disable_dp(struct intel_encoder *encoder)
2340{
2341 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2342
2343 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2344}
2345
580d3811
VS		 2346static void chv_post_disable_dp(struct intel_encoder *encoder)
2347{
2348 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2349 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2350 struct drm_device *dev = encoder->base.dev;
2351 struct drm_i915_private *dev_priv = dev->dev_private;
2352 struct intel_crtc *intel_crtc =
2353 to_intel_crtc(encoder->base.crtc);
2354 enum dpio_channel ch = vlv_dport_to_channel(dport);
2355 enum pipe pipe = intel_crtc->pipe;
2356 u32 val;
2357
2358 intel_dp_link_down(intel_dp);
2359
2360 mutex_lock(&dev_priv->dpio_lock);
2361
2362 /* Propagate soft reset to data lane reset */
97fd4d5c 2363 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2364 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2365 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2366
97fd4d5c
VS		 2367 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2368 val |= CHV_PCS_REQ_SOFTRESET_EN;
2369 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2370
2371 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2372 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2373 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2374
2375 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2376 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2377 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2378
2379 mutex_unlock(&dev_priv->dpio_lock);
2380}
2381
7b13b58a
VS		 2382static void
2383_intel_dp_set_link_train(struct intel_dp *intel_dp,
2384 uint32_t *DP,
2385 uint8_t dp_train_pat)
2386{
2387 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2388 struct drm_device *dev = intel_dig_port->base.base.dev;
2389 struct drm_i915_private *dev_priv = dev->dev_private;
2390 enum port port = intel_dig_port->port;
2391
2392 if (HAS_DDI(dev)) {
2393 uint32_t temp = I915_READ(DP_TP_CTL(port));
2394
2395 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2396 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2397 else
2398 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2399
2400 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2401 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2402 case DP_TRAINING_PATTERN_DISABLE:
2403 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2404
2405 break;
2406 case DP_TRAINING_PATTERN_1:
2407 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2408 break;
2409 case DP_TRAINING_PATTERN_2:
2410 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2411 break;
2412 case DP_TRAINING_PATTERN_3:
2413 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2414 break;
2415 }
2416 I915_WRITE(DP_TP_CTL(port), temp);
2417
2418 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2419 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2420
2421 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2422 case DP_TRAINING_PATTERN_DISABLE:
2423 *DP |= DP_LINK_TRAIN_OFF_CPT;
2424 break;
2425 case DP_TRAINING_PATTERN_1:
2426 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2427 break;
2428 case DP_TRAINING_PATTERN_2:
2429 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2430 break;
2431 case DP_TRAINING_PATTERN_3:
2432 DRM_ERROR("DP training pattern 3 not supported\n");
2433 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2434 break;
2435 }
2436
2437 } else {
2438 if (IS_CHERRYVIEW(dev))
2439 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2440 else
2441 *DP &= ~DP_LINK_TRAIN_MASK;
2442
2443 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2444 case DP_TRAINING_PATTERN_DISABLE:
2445 *DP |= DP_LINK_TRAIN_OFF;
2446 break;
2447 case DP_TRAINING_PATTERN_1:
2448 *DP |= DP_LINK_TRAIN_PAT_1;
2449 break;
2450 case DP_TRAINING_PATTERN_2:
2451 *DP |= DP_LINK_TRAIN_PAT_2;
2452 break;
2453 case DP_TRAINING_PATTERN_3:
2454 if (IS_CHERRYVIEW(dev)) {
2455 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2456 } else {
2457 DRM_ERROR("DP training pattern 3 not supported\n");
2458 *DP |= DP_LINK_TRAIN_PAT_2;
2459 }
2460 break;
2461 }
2462 }
2463}
2464
2465static void intel_dp_enable_port(struct intel_dp *intel_dp)
2466{
2467 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2468 struct drm_i915_private *dev_priv = dev->dev_private;
2469
2470 intel_dp->DP |= DP_PORT_EN;
2471
2472 /* enable with pattern 1 (as per spec) */
2473 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2474 DP_TRAINING_PATTERN_1);
2475
2476 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2477 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2478}
2479
e8cb4558 2480static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2481{
e8cb4558
DV		 2482 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2483 struct drm_device *dev = encoder->base.dev;
2484 struct drm_i915_private *dev_priv = dev->dev_private;
2485 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2486
0c33d8d7
DV		 2487 if (WARN_ON(dp_reg & DP_PORT_EN))
2488 return;
5d613501 2489
7b13b58a 2490 intel_dp_enable_port(intel_dp);
24f3e092 2491 intel_edp_panel_vdd_on(intel_dp);
4be73780 2492 intel_edp_panel_on(intel_dp);
1e0560e0 2493 intel_edp_panel_vdd_off(intel_dp, true);
f01eca2e 2494 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2495 intel_dp_start_link_train(intel_dp);
33a34e4e 2496 intel_dp_complete_link_train(intel_dp);
3ab9c637 2497 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2498}
89b667f8 2499
ecff4f3b
JN		 2500static void g4x_enable_dp(struct intel_encoder *encoder)
2501{
828f5c6e
JN		 2502 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2503
ecff4f3b 2504 intel_enable_dp(encoder);
4be73780 2505 intel_edp_backlight_on(intel_dp);
ab1f90f9 2506}
89b667f8 2507
ab1f90f9
JN		 2508static void vlv_enable_dp(struct intel_encoder *encoder)
2509{
828f5c6e
JN		 2510 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2511
4be73780 2512 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2513}
2514
ecff4f3b 2515static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2516{
2517 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2518 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2519
8ac33ed3
DV		 2520 intel_dp_prepare(encoder);
2521
d41f1efb
DV		 2522 /* Only ilk+ has port A */
2523 if (dport->port == PORT_A) {
2524 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2525 ironlake_edp_pll_on(intel_dp);
d41f1efb 2526 }
ab1f90f9
JN		 2527}
2528
a4a5d2f8
VS		 2529static void vlv_steal_power_sequencer(struct drm_device *dev,
2530 enum pipe pipe)
2531{
2532 struct drm_i915_private *dev_priv = dev->dev_private;
2533 struct intel_encoder *encoder;
2534
2535 lockdep_assert_held(&dev_priv->pps_mutex);
2536
2537 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2538 base.head) {
2539 struct intel_dp *intel_dp;
773538e8 2540 enum port port;
a4a5d2f8
VS		 2541
2542 if (encoder->type != INTEL_OUTPUT_EDP)
2543 continue;
2544
2545 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2546 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2547
2548 if (intel_dp->pps_pipe != pipe)
2549 continue;
2550
2551 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2552 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 2553
2554 /* make sure vdd is off before we steal it */
2555 edp_panel_vdd_off_sync(intel_dp);
2556
2557 intel_dp->pps_pipe = INVALID_PIPE;
2558 }
2559}
2560
2561static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2562{
2563 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2564 struct intel_encoder *encoder = &intel_dig_port->base;
2565 struct drm_device *dev = encoder->base.dev;
2566 struct drm_i915_private *dev_priv = dev->dev_private;
2567 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2568 struct edp_power_seq power_seq;
2569
2570 lockdep_assert_held(&dev_priv->pps_mutex);
2571
2572 if (intel_dp->pps_pipe == crtc->pipe)
2573 return;
2574
2575 /*
2576 * If another power sequencer was being used on this
2577 * port previously make sure to turn off vdd there while
2578 * we still have control of it.
2579 */
2580 if (intel_dp->pps_pipe != INVALID_PIPE)
2581 edp_panel_vdd_off_sync(intel_dp);
2582
2583 /*
2584 * We may be stealing the power
2585 * sequencer from another port.
2586 */
2587 vlv_steal_power_sequencer(dev, crtc->pipe);
2588
2589 /* now it's all ours */
2590 intel_dp->pps_pipe = crtc->pipe;
2591
2592 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2593 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2594
2595 /* init power sequencer on this pipe and port */
2596 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2597 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2598 &power_seq);
2599}
2600
ab1f90f9 2601static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2602{
2bd2ad64 2603 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2604 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2605 struct drm_device *dev = encoder->base.dev;
89b667f8 2606 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2607 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2608 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2609 int pipe = intel_crtc->pipe;
2610 u32 val;
a4fc5ed6 2611
ab1f90f9 2612 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2613
ab3c759a 2614 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2615 val = 0;
2616 if (pipe)
2617 val |= (1<<21);
2618 else
2619 val &= ~(1<<21);
2620 val |= 0x001000c4;
ab3c759a
CML		 2621 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2622 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2623 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2624
ab1f90f9
JN		 2625 mutex_unlock(&dev_priv->dpio_lock);
2626
2cac613b 2627 if (is_edp(intel_dp)) {
773538e8 2628 pps_lock(intel_dp);
a4a5d2f8 2629 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2630 pps_unlock(intel_dp);
2cac613b 2631 }
bf13e81b 2632
ab1f90f9
JN		 2633 intel_enable_dp(encoder);
2634
e4607fcf 2635 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2636}
2637
ecff4f3b 2638static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2639{
2640 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2641 struct drm_device *dev = encoder->base.dev;
2642 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2643 struct intel_crtc *intel_crtc =
2644 to_intel_crtc(encoder->base.crtc);
e4607fcf 2645 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2646 int pipe = intel_crtc->pipe;
89b667f8 2647
8ac33ed3
DV		 2648 intel_dp_prepare(encoder);
2649
89b667f8 2650 /* Program Tx lane resets to default */
0980a60f 2651 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2652 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2653 DPIO_PCS_TX_LANE2_RESET |
2654 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2655 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2656 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2657 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2658 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2659 DPIO_PCS_CLK_SOFT_RESET);
2660
2661 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2662 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2663 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2664 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2665 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2666}
2667
e4a1d846
CML		 2668static void chv_pre_enable_dp(struct intel_encoder *encoder)
2669{
2670 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2671 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2672 struct drm_device *dev = encoder->base.dev;
2673 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2674 struct intel_crtc *intel_crtc =
2675 to_intel_crtc(encoder->base.crtc);
2676 enum dpio_channel ch = vlv_dport_to_channel(dport);
2677 int pipe = intel_crtc->pipe;
2678 int data, i;
949c1d43 2679 u32 val;
e4a1d846 2680
e4a1d846 2681 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2682
2683 /* Deassert soft data lane reset*/
97fd4d5c 2684 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2685 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2686 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2687
2688 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2689 val |= CHV_PCS_REQ_SOFTRESET_EN;
2690 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2691
2692 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2693 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2694 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2695
97fd4d5c 2696 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2697 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2698 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2699
2700 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2701 for (i = 0; i < 4; i++) {
2702 /* Set the latency optimal bit */
2703 data = (i == 1) ? 0x0 : 0x6;
2704 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2705 data << DPIO_FRC_LATENCY_SHFIT);
2706
2707 /* Set the upar bit */
2708 data = (i == 1) ? 0x0 : 0x1;
2709 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2710 data << DPIO_UPAR_SHIFT);
2711 }
2712
2713 /* Data lane stagger programming */
2714 /* FIXME: Fix up value only after power analysis */
2715
2716 mutex_unlock(&dev_priv->dpio_lock);
2717
2718 if (is_edp(intel_dp)) {
773538e8 2719 pps_lock(intel_dp);
a4a5d2f8 2720 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2721 pps_unlock(intel_dp);
e4a1d846
CML		 2722 }
2723
2724 intel_enable_dp(encoder);
2725
2726 vlv_wait_port_ready(dev_priv, dport);
2727}
2728
9197c88b
VS		 2729static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2730{
2731 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2732 struct drm_device *dev = encoder->base.dev;
2733 struct drm_i915_private *dev_priv = dev->dev_private;
2734 struct intel_crtc *intel_crtc =
2735 to_intel_crtc(encoder->base.crtc);
2736 enum dpio_channel ch = vlv_dport_to_channel(dport);
2737 enum pipe pipe = intel_crtc->pipe;
2738 u32 val;
2739
625695f8
VS		 2740 intel_dp_prepare(encoder);
2741
9197c88b
VS		 2742 mutex_lock(&dev_priv->dpio_lock);
2743
b9e5ac3c
VS		 2744 /* program left/right clock distribution */
2745 if (pipe != PIPE_B) {
2746 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2747 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2748 if (ch == DPIO_CH0)
2749 val |= CHV_BUFLEFTENA1_FORCE;
2750 if (ch == DPIO_CH1)
2751 val |= CHV_BUFRIGHTENA1_FORCE;
2752 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2753 } else {
2754 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2755 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2756 if (ch == DPIO_CH0)
2757 val |= CHV_BUFLEFTENA2_FORCE;
2758 if (ch == DPIO_CH1)
2759 val |= CHV_BUFRIGHTENA2_FORCE;
2760 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2761 }
2762
9197c88b
VS		 2763 /* program clock channel usage */
2764 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2765 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2766 if (pipe != PIPE_B)
2767 val &= ~CHV_PCS_USEDCLKCHANNEL;
2768 else
2769 val |= CHV_PCS_USEDCLKCHANNEL;
2770 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2771
2772 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2773 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2774 if (pipe != PIPE_B)
2775 val &= ~CHV_PCS_USEDCLKCHANNEL;
2776 else
2777 val |= CHV_PCS_USEDCLKCHANNEL;
2778 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2779
2780 /*
2781 * This a a bit weird since generally CL
2782 * matches the pipe, but here we need to
2783 * pick the CL based on the port.
2784 */
2785 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2786 if (pipe != PIPE_B)
2787 val &= ~CHV_CMN_USEDCLKCHANNEL;
2788 else
2789 val |= CHV_CMN_USEDCLKCHANNEL;
2790 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2791
2792 mutex_unlock(&dev_priv->dpio_lock);
2793}
2794
a4fc5ed6 2795/*
df0c237d
JB		 2796 * Native read with retry for link status and receiver capability reads for
2797 * cases where the sink may still be asleep.
9d1a1031
JN		 2798 *
2799 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2800 * supposed to retry 3 times per the spec.
a4fc5ed6 2801 */
9d1a1031
JN		 2802static ssize_t
2803intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2804 void *buffer, size_t size)
a4fc5ed6 2805{
9d1a1031
JN		 2806 ssize_t ret;
2807 int i;
61da5fab 2808
f6a19066
VS		 2809 /*
2810 * Sometime we just get the same incorrect byte repeated
2811 * over the entire buffer. Doing just one throw away read
2812 * initially seems to "solve" it.
2813 */
2814 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2815
61da5fab 2816 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2817 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2818 if (ret == size)
2819 return ret;
61da5fab
JB		 2820 msleep(1);
2821 }
a4fc5ed6 2822
9d1a1031 2823 return ret;
a4fc5ed6
KP		 2824}
2825
2826/*
2827 * Fetch AUX CH registers 0x202 - 0x207 which contain
2828 * link status information
2829 */
2830static bool
93f62dad 2831intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2832{
9d1a1031
JN		 2833 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2834 DP_LANE0_1_STATUS,
2835 link_status,
2836 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2837}
2838
1100244e 2839/* These are source-specific values. */
a4fc5ed6 2840static uint8_t
1a2eb460 2841intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2842{
30add22d 2843 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2844 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2845
9576c27f 2846 if (IS_VALLEYVIEW(dev))
bd60018a 2847 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2848 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2849 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2850 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2851 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2852 else
bd60018a 2853 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2854}
2855
2856static uint8_t
2857intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2858{
30add22d 2859 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2860 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2861
9576c27f 2862 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2863 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2864 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2865 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2866 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2867 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2868 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2869 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2870 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2871 default:
bd60018a 2872 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2873 }
e2fa6fba
P		 2874 } else if (IS_VALLEYVIEW(dev)) {
2875 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2876 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2877 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2878 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2879 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2880 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2881 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2882 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2883 default:
bd60018a 2884 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2885 }
bc7d38a4 2886 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2887 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2888 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2889 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2890 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2891 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2892 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2893 default:
bd60018a 2894 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2895 }
2896 } else {
2897 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2898 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2899 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2900 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2901 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2902 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2903 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2904 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2905 default:
bd60018a 2906 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2907 }
a4fc5ed6
KP		 2908 }
2909}
2910
e2fa6fba
P		 2911static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2912{
2913 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2914 struct drm_i915_private *dev_priv = dev->dev_private;
2915 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2916 struct intel_crtc *intel_crtc =
2917 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2918 unsigned long demph_reg_value, preemph_reg_value,
2919 uniqtranscale_reg_value;
2920 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2921 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2922 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2923
2924 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2925 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2926 preemph_reg_value = 0x0004000;
2927 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2928 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2929 demph_reg_value = 0x2B405555;
2930 uniqtranscale_reg_value = 0x552AB83A;
2931 break;
bd60018a 2932 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2933 demph_reg_value = 0x2B404040;
2934 uniqtranscale_reg_value = 0x5548B83A;
2935 break;
bd60018a 2936 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2937 demph_reg_value = 0x2B245555;
2938 uniqtranscale_reg_value = 0x5560B83A;
2939 break;
bd60018a 2940 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2941 demph_reg_value = 0x2B405555;
2942 uniqtranscale_reg_value = 0x5598DA3A;
2943 break;
2944 default:
2945 return 0;
2946 }
2947 break;
bd60018a 2948 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2949 preemph_reg_value = 0x0002000;
2950 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2951 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2952 demph_reg_value = 0x2B404040;
2953 uniqtranscale_reg_value = 0x5552B83A;
2954 break;
bd60018a 2955 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2956 demph_reg_value = 0x2B404848;
2957 uniqtranscale_reg_value = 0x5580B83A;
2958 break;
bd60018a 2959 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2960 demph_reg_value = 0x2B404040;
2961 uniqtranscale_reg_value = 0x55ADDA3A;
2962 break;
2963 default:
2964 return 0;
2965 }
2966 break;
bd60018a 2967 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 2968 preemph_reg_value = 0x0000000;
2969 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2970 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2971 demph_reg_value = 0x2B305555;
2972 uniqtranscale_reg_value = 0x5570B83A;
2973 break;
bd60018a 2974 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2975 demph_reg_value = 0x2B2B4040;
2976 uniqtranscale_reg_value = 0x55ADDA3A;
2977 break;
2978 default:
2979 return 0;
2980 }
2981 break;
bd60018a 2982 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 2983 preemph_reg_value = 0x0006000;
2984 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2985 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2986 demph_reg_value = 0x1B405555;
2987 uniqtranscale_reg_value = 0x55ADDA3A;
2988 break;
2989 default:
2990 return 0;
2991 }
2992 break;
2993 default:
2994 return 0;
2995 }
2996
0980a60f 2997 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2998 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2999 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3000 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3001 uniqtranscale_reg_value);
ab3c759a
CML		 3002 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3003 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3004 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3005 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3006 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3007
3008 return 0;
3009}
3010
e4a1d846
CML		 3011static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3012{
3013 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3014 struct drm_i915_private *dev_priv = dev->dev_private;
3015 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3016 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3017 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3018 uint8_t train_set = intel_dp->train_set[0];
3019 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3020 enum pipe pipe = intel_crtc->pipe;
3021 int i;
e4a1d846
CML		 3022
3023 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3024 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3025 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3026 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3027 deemph_reg_value = 128;
3028 margin_reg_value = 52;
3029 break;
bd60018a 3030 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3031 deemph_reg_value = 128;
3032 margin_reg_value = 77;
3033 break;
bd60018a 3034 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3035 deemph_reg_value = 128;
3036 margin_reg_value = 102;
3037 break;
bd60018a 3038 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3039 deemph_reg_value = 128;
3040 margin_reg_value = 154;
3041 /* FIXME extra to set for 1200 */
3042 break;
3043 default:
3044 return 0;
3045 }
3046 break;
bd60018a 3047 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3048 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3049 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3050 deemph_reg_value = 85;
3051 margin_reg_value = 78;
3052 break;
bd60018a 3053 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3054 deemph_reg_value = 85;
3055 margin_reg_value = 116;
3056 break;
bd60018a 3057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3058 deemph_reg_value = 85;
3059 margin_reg_value = 154;
3060 break;
3061 default:
3062 return 0;
3063 }
3064 break;
bd60018a 3065 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3066 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3067 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3068 deemph_reg_value = 64;
3069 margin_reg_value = 104;
3070 break;
bd60018a 3071 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3072 deemph_reg_value = 64;
3073 margin_reg_value = 154;
3074 break;
3075 default:
3076 return 0;
3077 }
3078 break;
bd60018a 3079 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3080 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3081 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3082 deemph_reg_value = 43;
3083 margin_reg_value = 154;
3084 break;
3085 default:
3086 return 0;
3087 }
3088 break;
3089 default:
3090 return 0;
3091 }
3092
3093 mutex_lock(&dev_priv->dpio_lock);
3094
3095 /* Clear calc init */
1966e59e
VS		 3096 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3097 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3098 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3099
3100 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3101 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3102 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3103
3104 /* Program swing deemph */
f72df8db
VS		 3105 for (i = 0; i < 4; i++) {
3106 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3107 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3108 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3109 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3110 }
e4a1d846
CML		 3111
3112 /* Program swing margin */
f72df8db
VS		 3113 for (i = 0; i < 4; i++) {
3114 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3115 val &= ~DPIO_SWING_MARGIN000_MASK;
3116 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3117 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3118 }
e4a1d846
CML		 3119
3120 /* Disable unique transition scale */
f72df8db
VS		 3121 for (i = 0; i < 4; i++) {
3122 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3123 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3124 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3125 }
e4a1d846
CML		 3126
3127 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3128 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3129 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3130 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3131
3132 /*
3133 * The document said it needs to set bit 27 for ch0 and bit 26
3134 * for ch1. Might be a typo in the doc.
3135 * For now, for this unique transition scale selection, set bit
3136 * 27 for ch0 and ch1.
3137 */
f72df8db
VS		 3138 for (i = 0; i < 4; i++) {
3139 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3140 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3141 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3142 }
e4a1d846 3143
f72df8db
VS		 3144 for (i = 0; i < 4; i++) {
3145 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3146 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3147 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3148 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3149 }
e4a1d846
CML		 3150 }
3151
3152 /* Start swing calculation */
1966e59e
VS		 3153 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3154 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3155 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3156
3157 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3158 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3159 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3160
3161 /* LRC Bypass */
3162 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3163 val |= DPIO_LRC_BYPASS;
3164 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3165
3166 mutex_unlock(&dev_priv->dpio_lock);
3167
3168 return 0;
3169}
3170
a4fc5ed6 3171static void
0301b3ac
JN		 3172intel_get_adjust_train(struct intel_dp *intel_dp,
3173 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3174{
3175 uint8_t v = 0;
3176 uint8_t p = 0;
3177 int lane;
1a2eb460
KP		 3178 uint8_t voltage_max;
3179 uint8_t preemph_max;
a4fc5ed6 3180
33a34e4e 3181 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3182 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3183 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3184
3185 if (this_v > v)
3186 v = this_v;
3187 if (this_p > p)
3188 p = this_p;
3189 }
3190
1a2eb460 3191 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3192 if (v >= voltage_max)
3193 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3194
1a2eb460
KP		 3195 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3196 if (p >= preemph_max)
3197 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3198
3199 for (lane = 0; lane < 4; lane++)
33a34e4e 3200 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3201}
3202
3203static uint32_t
f0a3424e 3204intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3205{
3cf2efb1 3206 uint32_t signal_levels = 0;
a4fc5ed6 3207
3cf2efb1 3208 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3209 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3210 default:
3211 signal_levels |= DP_VOLTAGE_0_4;
3212 break;
bd60018a 3213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3214 signal_levels |= DP_VOLTAGE_0_6;
3215 break;
bd60018a 3216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3217 signal_levels |= DP_VOLTAGE_0_8;
3218 break;
bd60018a 3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3220 signal_levels |= DP_VOLTAGE_1_2;
3221 break;
3222 }
3cf2efb1 3223 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3224 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3225 default:
3226 signal_levels |= DP_PRE_EMPHASIS_0;
3227 break;
bd60018a 3228 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3229 signal_levels |= DP_PRE_EMPHASIS_3_5;
3230 break;
bd60018a 3231 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3232 signal_levels |= DP_PRE_EMPHASIS_6;
3233 break;
bd60018a 3234 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3235 signal_levels |= DP_PRE_EMPHASIS_9_5;
3236 break;
3237 }
3238 return signal_levels;
3239}
3240
e3421a18
ZW		 3241/* Gen6's DP voltage swing and pre-emphasis control */
3242static uint32_t
3243intel_gen6_edp_signal_levels(uint8_t train_set)
3244{
3c5a62b5
YL		 3245 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3246 DP_TRAIN_PRE_EMPHASIS_MASK);
3247 switch (signal_levels) {
bd60018a
SJ		 3248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3249 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3250 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3251 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3252 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3253 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3254 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3255 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3256 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3257 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3258 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3259 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3260 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3261 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3262 default:
3c5a62b5
YL		 3263 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3264 "0x%x\n", signal_levels);
3265 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3266 }
3267}
3268
1a2eb460
KP		 3269/* Gen7's DP voltage swing and pre-emphasis control */
3270static uint32_t
3271intel_gen7_edp_signal_levels(uint8_t train_set)
3272{
3273 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3274 DP_TRAIN_PRE_EMPHASIS_MASK);
3275 switch (signal_levels) {
bd60018a 3276 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3277 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3278 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3279 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3280 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3281 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3282
bd60018a 3283 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3284 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3286 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3287
bd60018a 3288 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3289 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3291 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3292
3293 default:
3294 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3295 "0x%x\n", signal_levels);
3296 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3297 }
3298}
3299
d6c0d722
PZ		 3300/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3301static uint32_t
f0a3424e 3302intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3303{
d6c0d722
PZ		 3304 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3305 DP_TRAIN_PRE_EMPHASIS_MASK);
3306 switch (signal_levels) {
bd60018a 3307 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3308 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3309 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3310 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3311 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3312 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3313 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3314 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3315
bd60018a 3316 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3317 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3318 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3319 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3320 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3321 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3322
bd60018a 3323 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3324 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3325 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3326 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3327 default:
3328 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3329 "0x%x\n", signal_levels);
c5fe6a06 3330 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3331 }
a4fc5ed6
KP		 3332}
3333
f0a3424e
PZ		 3334/* Properly updates "DP" with the correct signal levels. */
3335static void
3336intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3337{
3338 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3339 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3340 struct drm_device *dev = intel_dig_port->base.base.dev;
3341 uint32_t signal_levels, mask;
3342 uint8_t train_set = intel_dp->train_set[0];
3343
9576c27f 3344 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 3345 signal_levels = intel_hsw_signal_levels(train_set);
3346 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3347 } else if (IS_CHERRYVIEW(dev)) {
3348 signal_levels = intel_chv_signal_levels(intel_dp);
3349 mask = 0;
e2fa6fba
P		 3350 } else if (IS_VALLEYVIEW(dev)) {
3351 signal_levels = intel_vlv_signal_levels(intel_dp);
3352 mask = 0;
bc7d38a4 3353 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3354 signal_levels = intel_gen7_edp_signal_levels(train_set);
3355 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3356 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3357 signal_levels = intel_gen6_edp_signal_levels(train_set);
3358 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3359 } else {
3360 signal_levels = intel_gen4_signal_levels(train_set);
3361 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3362 }
3363
3364 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3365
3366 *DP = (*DP & ~mask) | signal_levels;
3367}
3368
a4fc5ed6 3369static bool
ea5b213a 3370intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3371 uint32_t *DP,
58e10eb9 3372 uint8_t dp_train_pat)
a4fc5ed6 3373{
174edf1f
PZ		 3374 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3375 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3376 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3377 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3378 int ret, len;
a4fc5ed6 3379
7b13b58a 3380 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3381
70aff66c 3382 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3383 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3384
2cdfe6c8
JN		 3385 buf[0] = dp_train_pat;
3386 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3387 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3388 /* don't write DP_TRAINING_LANEx_SET on disable */
3389 len = 1;
3390 } else {
3391 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3392 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3393 len = intel_dp->lane_count + 1;
47ea7542 3394 }
a4fc5ed6 3395
9d1a1031
JN		 3396 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3397 buf, len);
2cdfe6c8
JN		 3398
3399 return ret == len;
a4fc5ed6
KP		 3400}
3401
70aff66c
JN		 3402static bool
3403intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3404 uint8_t dp_train_pat)
3405{
953d22e8 3406 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3407 intel_dp_set_signal_levels(intel_dp, DP);
3408 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3409}
3410
3411static bool
3412intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3413 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3414{
3415 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3416 struct drm_device *dev = intel_dig_port->base.base.dev;
3417 struct drm_i915_private *dev_priv = dev->dev_private;
3418 int ret;
3419
3420 intel_get_adjust_train(intel_dp, link_status);
3421 intel_dp_set_signal_levels(intel_dp, DP);
3422
3423 I915_WRITE(intel_dp->output_reg, *DP);
3424 POSTING_READ(intel_dp->output_reg);
3425
9d1a1031
JN		 3426 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3427 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3428
3429 return ret == intel_dp->lane_count;
3430}
3431
3ab9c637
ID		 3432static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3433{
3434 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3435 struct drm_device *dev = intel_dig_port->base.base.dev;
3436 struct drm_i915_private *dev_priv = dev->dev_private;
3437 enum port port = intel_dig_port->port;
3438 uint32_t val;
3439
3440 if (!HAS_DDI(dev))
3441 return;
3442
3443 val = I915_READ(DP_TP_CTL(port));
3444 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3445 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3446 I915_WRITE(DP_TP_CTL(port), val);
3447
3448 /*
3449 * On PORT_A we can have only eDP in SST mode. There the only reason
3450 * we need to set idle transmission mode is to work around a HW issue
3451 * where we enable the pipe while not in idle link-training mode.
3452 * In this case there is requirement to wait for a minimum number of
3453 * idle patterns to be sent.
3454 */
3455 if (port == PORT_A)
3456 return;
3457
3458 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3459 1))
3460 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3461}
3462
33a34e4e 3463/* Enable corresponding port and start training pattern 1 */
c19b0669 3464void
33a34e4e 3465intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3466{
da63a9f2 3467 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3468 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3469 int i;
3470 uint8_t voltage;
cdb0e95b 3471 int voltage_tries, loop_tries;
ea5b213a 3472 uint32_t DP = intel_dp->DP;
6aba5b6c 3473 uint8_t link_config[2];
a4fc5ed6 3474
affa9354 3475 if (HAS_DDI(dev))
c19b0669
PZ		 3476 intel_ddi_prepare_link_retrain(encoder);
3477
3cf2efb1 3478 /* Write the link configuration data */
6aba5b6c
JN		 3479 link_config[0] = intel_dp->link_bw;
3480 link_config[1] = intel_dp->lane_count;
3481 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3482 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3483 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3484
3485 link_config[0] = 0;
3486 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3487 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3488
3489 DP |= DP_PORT_EN;
1a2eb460 3490
70aff66c
JN		 3491 /* clock recovery */
3492 if (!intel_dp_reset_link_train(intel_dp, &DP,
3493 DP_TRAINING_PATTERN_1 |
3494 DP_LINK_SCRAMBLING_DISABLE)) {
3495 DRM_ERROR("failed to enable link training\n");
3496 return;
3497 }
3498
a4fc5ed6 3499 voltage = 0xff;
cdb0e95b
KP		 3500 voltage_tries = 0;
3501 loop_tries = 0;
a4fc5ed6 3502 for (;;) {
70aff66c 3503 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3504
a7c9655f 3505 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3506 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3507 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3508 break;
93f62dad 3509 }
a4fc5ed6 3510
01916270 3511 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3512 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3513 break;
3514 }
3515
3516 /* Check to see if we've tried the max voltage */
3517 for (i = 0; i < intel_dp->lane_count; i++)
3518 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3519 break;
3b4f819d 3520 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3521 ++loop_tries;
3522 if (loop_tries == 5) {
3def84b3 3523 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3524 break;
3525 }
70aff66c
JN		 3526 intel_dp_reset_link_train(intel_dp, &DP,
3527 DP_TRAINING_PATTERN_1 |
3528 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3529 voltage_tries = 0;
3530 continue;
3531 }
a4fc5ed6 3532
3cf2efb1 3533 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3534 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3535 ++voltage_tries;
b06fbda3 3536 if (voltage_tries == 5) {
3def84b3 3537 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3538 break;
3539 }
3540 } else
3541 voltage_tries = 0;
3542 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3543
70aff66c
JN		 3544 /* Update training set as requested by target */
3545 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3546 DRM_ERROR("failed to update link training\n");
3547 break;
3548 }
a4fc5ed6
KP		 3549 }
3550
33a34e4e
JB		 3551 intel_dp->DP = DP;
3552}
3553
c19b0669 3554void
33a34e4e
JB		 3555intel_dp_complete_link_train(struct intel_dp *intel_dp)
3556{
33a34e4e 3557 bool channel_eq = false;
37f80975 3558 int tries, cr_tries;
33a34e4e 3559 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3560 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3561
3562 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3563 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3564 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3565
a4fc5ed6 3566 /* channel equalization */
70aff66c 3567 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3568 training_pattern |
70aff66c
JN		 3569 DP_LINK_SCRAMBLING_DISABLE)) {
3570 DRM_ERROR("failed to start channel equalization\n");
3571 return;
3572 }
3573
a4fc5ed6 3574 tries = 0;
37f80975 3575 cr_tries = 0;
a4fc5ed6
KP		 3576 channel_eq = false;
3577 for (;;) {
70aff66c 3578 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3579
37f80975
JB		 3580 if (cr_tries > 5) {
3581 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3582 break;
3583 }
3584
a7c9655f 3585 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3586 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3587 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3588 break;
70aff66c 3589 }
a4fc5ed6 3590
37f80975 3591 /* Make sure clock is still ok */
01916270 3592 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3593 intel_dp_start_link_train(intel_dp);
70aff66c 3594 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3595 training_pattern |
70aff66c 3596 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3597 cr_tries++;
3598 continue;
3599 }
3600
1ffdff13 3601 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3602 channel_eq = true;
3603 break;
3604 }
a4fc5ed6 3605
37f80975
JB		 3606 /* Try 5 times, then try clock recovery if that fails */
3607 if (tries > 5) {
3608 intel_dp_link_down(intel_dp);
3609 intel_dp_start_link_train(intel_dp);
70aff66c 3610 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3611 training_pattern |
70aff66c 3612 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3613 tries = 0;
3614 cr_tries++;
3615 continue;
3616 }
a4fc5ed6 3617
70aff66c
JN		 3618 /* Update training set as requested by target */
3619 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3620 DRM_ERROR("failed to update link training\n");
3621 break;
3622 }
3cf2efb1 3623 ++tries;
869184a6 3624 }
3cf2efb1 3625
3ab9c637
ID		 3626 intel_dp_set_idle_link_train(intel_dp);
3627
3628 intel_dp->DP = DP;
3629
d6c0d722 3630 if (channel_eq)
07f42258 3631 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3632
3ab9c637
ID		 3633}
3634
3635void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3636{
70aff66c 3637 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3638 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3639}
3640
3641static void
ea5b213a 3642intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3643{
da63a9f2 3644 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3645 enum port port = intel_dig_port->port;
da63a9f2 3646 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3647 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3648 struct intel_crtc *intel_crtc =
3649 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3650 uint32_t DP = intel_dp->DP;
a4fc5ed6 3651
bc76e320 3652 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3653 return;
3654
0c33d8d7 3655 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3656 return;
3657
28c97730 3658 DRM_DEBUG_KMS("\n");
32f9d658 3659
bc7d38a4 3660 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3661 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3662 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3663 } else {
aad3d14d
VS		 3664 if (IS_CHERRYVIEW(dev))
3665 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3666 else
3667 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3668 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3669 }
fe255d00 3670 POSTING_READ(intel_dp->output_reg);
5eb08b69 3671
493a7081 3672 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3673 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3674 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3675
5bddd17f
EA		 3676 /* Hardware workaround: leaving our transcoder select
3677 * set to transcoder B while it's off will prevent the
3678 * corresponding HDMI output on transcoder A.
3679 *
3680 * Combine this with another hardware workaround:
3681 * transcoder select bit can only be cleared while the
3682 * port is enabled.
3683 */
3684 DP &= ~DP_PIPEB_SELECT;
3685 I915_WRITE(intel_dp->output_reg, DP);
3686
3687 /* Changes to enable or select take place the vblank
3688 * after being written.
3689 */
ff50afe9
DV		 3690 if (WARN_ON(crtc == NULL)) {
3691 /* We should never try to disable a port without a crtc
3692 * attached. For paranoia keep the code around for a
3693 * bit. */
31acbcc4
CW		 3694 POSTING_READ(intel_dp->output_reg);
3695 msleep(50);
3696 } else
ab527efc 3697 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3698 }
3699
832afda6 3700 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3701 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3702 POSTING_READ(intel_dp->output_reg);
f01eca2e 3703 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3704}
3705
26d61aad
KP		 3706static bool
3707intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3708{
a031d709
RV		 3709 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3710 struct drm_device *dev = dig_port->base.base.dev;
3711 struct drm_i915_private *dev_priv = dev->dev_private;
3712
9d1a1031
JN		 3713 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3714 sizeof(intel_dp->dpcd)) < 0)
edb39244 3715 return false; /* aux transfer failed */
92fd8fd1 3716
a8e98153 3717 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3718
edb39244
AJ		 3719 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3720 return false; /* DPCD not present */
3721
2293bb5c
SK		 3722 /* Check if the panel supports PSR */
3723 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3724 if (is_edp(intel_dp)) {
9d1a1031
JN		 3725 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3726 intel_dp->psr_dpcd,
3727 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3728 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3729 dev_priv->psr.sink_support = true;
50003939 3730 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3731 }
50003939
JN		 3732 }
3733
06ea66b6
TP		 3734 /* Training Pattern 3 support */
3735 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3736 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3737 intel_dp->use_tps3 = true;
f8d8a672 3738 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3739 } else
3740 intel_dp->use_tps3 = false;
3741
edb39244
AJ		 3742 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3743 DP_DWN_STRM_PORT_PRESENT))
3744 return true; /* native DP sink */
3745
3746 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3747 return true; /* no per-port downstream info */
3748
9d1a1031
JN		 3749 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3750 intel_dp->downstream_ports,
3751 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3752 return false; /* downstream port status fetch failed */
3753
3754 return true;
92fd8fd1
KP		 3755}
3756
0d198328
AJ		 3757static void
3758intel_dp_probe_oui(struct intel_dp *intel_dp)
3759{
3760 u8 buf[3];
3761
3762 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3763 return;
3764
24f3e092 3765 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3766
9d1a1031 3767 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3768 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3769 buf[0], buf[1], buf[2]);
3770
9d1a1031 3771 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3772 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3773 buf[0], buf[1], buf[2]);
351cfc34 3774
1e0560e0 3775 intel_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3776}
3777
0e32b39c
DA		 3778static bool
3779intel_dp_probe_mst(struct intel_dp *intel_dp)
3780{
3781 u8 buf[1];
3782
3783 if (!intel_dp->can_mst)
3784 return false;
3785
3786 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3787 return false;
3788
d337a341 3789 intel_edp_panel_vdd_on(intel_dp);
0e32b39c
DA		 3790 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3791 if (buf[0] & DP_MST_CAP) {
3792 DRM_DEBUG_KMS("Sink is MST capable\n");
3793 intel_dp->is_mst = true;
3794 } else {
3795 DRM_DEBUG_KMS("Sink is not MST capable\n");
3796 intel_dp->is_mst = false;
3797 }
3798 }
1e0560e0 3799 intel_edp_panel_vdd_off(intel_dp, false);
0e32b39c
DA		 3800
3801 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3802 return intel_dp->is_mst;
3803}
3804
d2e216d0
RV		 3805int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3806{
3807 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3808 struct drm_device *dev = intel_dig_port->base.base.dev;
3809 struct intel_crtc *intel_crtc =
3810 to_intel_crtc(intel_dig_port->base.base.crtc);
3811 u8 buf[1];
3812
9d1a1031 3813 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
bda0381e 3814 return -EIO;
d2e216d0
RV		 3815
3816 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3817 return -ENOTTY;
3818
9d1a1031
JN		 3819 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3820 DP_TEST_SINK_START) < 0)
bda0381e 3821 return -EIO;
d2e216d0
RV		 3822
3823 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3824 intel_wait_for_vblank(dev, intel_crtc->pipe);
3825 intel_wait_for_vblank(dev, intel_crtc->pipe);
3826
9d1a1031 3827 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 3828 return -EIO;
d2e216d0 3829
9d1a1031 3830 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3831 return 0;
3832}
3833
a60f0e38
JB		 3834static bool
3835intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3836{
9d1a1031
JN		 3837 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3838 DP_DEVICE_SERVICE_IRQ_VECTOR,
3839 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3840}
3841
0e32b39c
DA		 3842static bool
3843intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3844{
3845 int ret;
3846
3847 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3848 DP_SINK_COUNT_ESI,
3849 sink_irq_vector, 14);
3850 if (ret != 14)
3851 return false;
3852
3853 return true;
3854}
3855
a60f0e38
JB		 3856static void
3857intel_dp_handle_test_request(struct intel_dp *intel_dp)
3858{
3859 /* NAK by default */
9d1a1031 3860 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3861}
3862
0e32b39c
DA		 3863static int
3864intel_dp_check_mst_status(struct intel_dp *intel_dp)
3865{
3866 bool bret;
3867
3868 if (intel_dp->is_mst) {
3869 u8 esi[16] = { 0 };
3870 int ret = 0;
3871 int retry;
3872 bool handled;
3873 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3874go_again:
3875 if (bret == true) {
3876
3877 /* check link status - esi[10] = 0x200c */
3878 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3879 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3880 intel_dp_start_link_train(intel_dp);
3881 intel_dp_complete_link_train(intel_dp);
3882 intel_dp_stop_link_train(intel_dp);
3883 }
3884
3885 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3886 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3887
3888 if (handled) {
3889 for (retry = 0; retry < 3; retry++) {
3890 int wret;
3891 wret = drm_dp_dpcd_write(&intel_dp->aux,
3892 DP_SINK_COUNT_ESI+1,
3893 &esi[1], 3);
3894 if (wret == 3) {
3895 break;
3896 }
3897 }
3898
3899 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3900 if (bret == true) {
3901 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3902 goto go_again;
3903 }
3904 } else
3905 ret = 0;
3906
3907 return ret;
3908 } else {
3909 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3910 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3911 intel_dp->is_mst = false;
3912 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3913 /* send a hotplug event */
3914 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3915 }
3916 }
3917 return -EINVAL;
3918}
3919
a4fc5ed6
KP		 3920/*
3921 * According to DP spec
3922 * 5.1.2:
3923 * 1. Read DPCD
3924 * 2. Configure link according to Receiver Capabilities
3925 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3926 * 4. Check link status on receipt of hot-plug interrupt
3927 */
00c09d70 3928void
ea5b213a 3929intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3930{
5b215bcf 3931 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3932 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3933 u8 sink_irq_vector;
93f62dad 3934 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3935
5b215bcf
DA		 3936 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3937
da63a9f2 3938 if (!intel_encoder->connectors_active)
d2b996ac 3939 return;
59cd09e1 3940
da63a9f2 3941 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3942 return;
3943
1a125d8a
ID		 3944 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3945 return;
3946
92fd8fd1 3947 /* Try to read receiver status if the link appears to be up */
93f62dad 3948 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3949 return;
3950 }
3951
92fd8fd1 3952 /* Now read the DPCD to see if it's actually running */
26d61aad 3953 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3954 return;
3955 }
3956
a60f0e38
JB		 3957 /* Try to read the source of the interrupt */
3958 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3959 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3960 /* Clear interrupt source */
9d1a1031
JN		 3961 drm_dp_dpcd_writeb(&intel_dp->aux,
3962 DP_DEVICE_SERVICE_IRQ_VECTOR,
3963 sink_irq_vector);
a60f0e38
JB		 3964
3965 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3966 intel_dp_handle_test_request(intel_dp);
3967 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3968 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3969 }
3970
1ffdff13 3971 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3972 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3973 intel_encoder->base.name);
33a34e4e
JB		 3974 intel_dp_start_link_train(intel_dp);
3975 intel_dp_complete_link_train(intel_dp);
3ab9c637 3976 intel_dp_stop_link_train(intel_dp);
33a34e4e 3977 }
a4fc5ed6 3978}
a4fc5ed6 3979
caf9ab24 3980/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3981static enum drm_connector_status
26d61aad 3982intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3983{
caf9ab24 3984 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3985 uint8_t type;
3986
3987 if (!intel_dp_get_dpcd(intel_dp))
3988 return connector_status_disconnected;
3989
3990 /* if there's no downstream port, we're done */
3991 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3992 return connector_status_connected;
caf9ab24
AJ		 3993
3994 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3995 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3996 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3997 uint8_t reg;
9d1a1031
JN		 3998
3999 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4000 &reg, 1) < 0)
caf9ab24 4001 return connector_status_unknown;
9d1a1031 4002
23235177
AJ		 4003 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4004 : connector_status_disconnected;
caf9ab24
AJ		 4005 }
4006
4007 /* If no HPD, poke DDC gently */
0b99836f 4008 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4009 return connector_status_connected;
caf9ab24
AJ		 4010
4011 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4012 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4013 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4014 if (type == DP_DS_PORT_TYPE_VGA ||
4015 type == DP_DS_PORT_TYPE_NON_EDID)
4016 return connector_status_unknown;
4017 } else {
4018 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4019 DP_DWN_STRM_PORT_TYPE_MASK;
4020 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4021 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4022 return connector_status_unknown;
4023 }
caf9ab24
AJ		 4024
4025 /* Anything else is out of spec, warn and ignore */
4026 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4027 return connector_status_disconnected;
71ba9000
AJ		 4028}
4029
d410b56d
CW		 4030static enum drm_connector_status
4031edp_detect(struct intel_dp *intel_dp)
4032{
4033 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4034 enum drm_connector_status status;
4035
4036 status = intel_panel_detect(dev);
4037 if (status == connector_status_unknown)
4038 status = connector_status_connected;
4039
4040 return status;
4041}
4042
5eb08b69 4043static enum drm_connector_status
a9756bb5 4044ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4045{
30add22d 4046 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4047 struct drm_i915_private *dev_priv = dev->dev_private;
4048 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4049
1b469639
DL		 4050 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4051 return connector_status_disconnected;
4052
26d61aad 4053 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4054}
4055
2a592bec
DA		 4056static int g4x_digital_port_connected(struct drm_device *dev,
4057 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4058{
a4fc5ed6 4059 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4060 uint32_t bit;
5eb08b69 4061
232a6ee9
TP		 4062 if (IS_VALLEYVIEW(dev)) {
4063 switch (intel_dig_port->port) {
4064 case PORT_B:
4065 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4066 break;
4067 case PORT_C:
4068 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4069 break;
4070 case PORT_D:
4071 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4072 break;
4073 default:
2a592bec 4074 return -EINVAL;
232a6ee9
TP		 4075 }
4076 } else {
4077 switch (intel_dig_port->port) {
4078 case PORT_B:
4079 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4080 break;
4081 case PORT_C:
4082 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4083 break;
4084 case PORT_D:
4085 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4086 break;
4087 default:
2a592bec 4088 return -EINVAL;
232a6ee9 4089 }
a4fc5ed6
KP		 4090 }
4091
10f76a38 4092 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4093 return 0;
4094 return 1;
4095}
4096
4097static enum drm_connector_status
4098g4x_dp_detect(struct intel_dp *intel_dp)
4099{
4100 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4102 int ret;
4103
4104 /* Can't disconnect eDP, but you can close the lid... */
4105 if (is_edp(intel_dp)) {
4106 enum drm_connector_status status;
4107
4108 status = intel_panel_detect(dev);
4109 if (status == connector_status_unknown)
4110 status = connector_status_connected;
4111 return status;
4112 }
4113
4114 ret = g4x_digital_port_connected(dev, intel_dig_port);
4115 if (ret == -EINVAL)
4116 return connector_status_unknown;
4117 else if (ret == 0)
a4fc5ed6
KP		 4118 return connector_status_disconnected;
4119
26d61aad 4120 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4121}
4122
8c241fef 4123static struct edid *
beb60608 4124intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4125{
beb60608 4126 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4127
9cd300e0
JN		 4128 /* use cached edid if we have one */
4129 if (intel_connector->edid) {
9cd300e0
JN		 4130 /* invalid edid */
4131 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4132 return NULL;
4133
55e9edeb 4134 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4135 } else
4136 return drm_get_edid(&intel_connector->base,
4137 &intel_dp->aux.ddc);
4138}
8c241fef 4139
beb60608
CW		 4140static void
4141intel_dp_set_edid(struct intel_dp *intel_dp)
4142{
4143 struct intel_connector *intel_connector = intel_dp->attached_connector;
4144 struct edid *edid;
8c241fef 4145
beb60608
CW		 4146 edid = intel_dp_get_edid(intel_dp);
4147 intel_connector->detect_edid = edid;
4148
4149 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4150 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4151 else
4152 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4153}
4154
beb60608
CW		 4155static void
4156intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4157{
beb60608 4158 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4159
beb60608
CW		 4160 kfree(intel_connector->detect_edid);
4161 intel_connector->detect_edid = NULL;
9cd300e0 4162
beb60608
CW		 4163 intel_dp->has_audio = false;
4164}
d6f24d0f 4165
beb60608
CW		 4166static enum intel_display_power_domain
4167intel_dp_power_get(struct intel_dp *dp)
4168{
4169 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4170 enum intel_display_power_domain power_domain;
4171
4172 power_domain = intel_display_port_power_domain(encoder);
4173 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4174
4175 return power_domain;
4176}
d6f24d0f 4177
beb60608
CW		 4178static void
4179intel_dp_power_put(struct intel_dp *dp,
4180 enum intel_display_power_domain power_domain)
4181{
4182 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4183 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4184}
4185
a9756bb5
ZW		 4186static enum drm_connector_status
4187intel_dp_detect(struct drm_connector *connector, bool force)
4188{
4189 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4190 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4191 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4192 struct drm_device *dev = connector->dev;
a9756bb5 4193 enum drm_connector_status status;
671dedd2 4194 enum intel_display_power_domain power_domain;
0e32b39c 4195 bool ret;
a9756bb5 4196
164c8598 4197 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4198 connector->base.id, connector->name);
beb60608 4199 intel_dp_unset_edid(intel_dp);
164c8598 4200
0e32b39c
DA		 4201 if (intel_dp->is_mst) {
4202 /* MST devices are disconnected from a monitor POV */
4203 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4204 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4205 return connector_status_disconnected;
0e32b39c
DA		 4206 }
4207
beb60608 4208 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4209
d410b56d
CW		 4210 /* Can't disconnect eDP, but you can close the lid... */
4211 if (is_edp(intel_dp))
4212 status = edp_detect(intel_dp);
4213 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4214 status = ironlake_dp_detect(intel_dp);
4215 else
4216 status = g4x_dp_detect(intel_dp);
4217 if (status != connector_status_connected)
c8c8fb33 4218 goto out;
a9756bb5 4219
0d198328
AJ		 4220 intel_dp_probe_oui(intel_dp);
4221
0e32b39c
DA		 4222 ret = intel_dp_probe_mst(intel_dp);
4223 if (ret) {
4224 /* if we are in MST mode then this connector
4225 won't appear connected or have anything with EDID on it */
4226 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4227 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4228 status = connector_status_disconnected;
4229 goto out;
4230 }
4231
beb60608 4232 intel_dp_set_edid(intel_dp);
a9756bb5 4233
d63885da
PZ		 4234 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4235 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4236 status = connector_status_connected;
4237
4238out:
beb60608 4239 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4240 return status;
a4fc5ed6
KP		 4241}
4242
beb60608
CW		 4243static void
4244intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4245{
df0e9248 4246 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4247 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4248 enum intel_display_power_domain power_domain;
a4fc5ed6 4249
beb60608
CW		 4250 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4251 connector->base.id, connector->name);
4252 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4253
beb60608
CW		 4254 if (connector->status != connector_status_connected)
4255 return;
671dedd2 4256
beb60608
CW		 4257 power_domain = intel_dp_power_get(intel_dp);
4258
4259 intel_dp_set_edid(intel_dp);
4260
4261 intel_dp_power_put(intel_dp, power_domain);
4262
4263 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4264 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4265}
4266
4267static int intel_dp_get_modes(struct drm_connector *connector)
4268{
4269 struct intel_connector *intel_connector = to_intel_connector(connector);
4270 struct edid *edid;
4271
4272 edid = intel_connector->detect_edid;
4273 if (edid) {
4274 int ret = intel_connector_update_modes(connector, edid);
4275 if (ret)
4276 return ret;
4277 }
32f9d658 4278
f8779fda 4279 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4280 if (is_edp(intel_attached_dp(connector)) &&
4281 intel_connector->panel.fixed_mode) {
f8779fda 4282 struct drm_display_mode *mode;
beb60608
CW		 4283
4284 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4285 intel_connector->panel.fixed_mode);
f8779fda 4286 if (mode) {
32f9d658
ZW		 4287 drm_mode_probed_add(connector, mode);
4288 return 1;
4289 }
4290 }
beb60608 4291
32f9d658 4292 return 0;
a4fc5ed6
KP		 4293}
4294
1aad7ac0
CW		 4295static bool
4296intel_dp_detect_audio(struct drm_connector *connector)
4297{
1aad7ac0 4298 bool has_audio = false;
beb60608 4299 struct edid *edid;
1aad7ac0 4300
beb60608
CW		 4301 edid = to_intel_connector(connector)->detect_edid;
4302 if (edid)
1aad7ac0 4303 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4304
1aad7ac0
CW		 4305 return has_audio;
4306}
4307
f684960e
CW		 4308static int
4309intel_dp_set_property(struct drm_connector *connector,
4310 struct drm_property *property,
4311 uint64_t val)
4312{
e953fd7b 4313 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4314 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4315 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4316 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4317 int ret;
4318
662595df 4319 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4320 if (ret)
4321 return ret;
4322
3f43c48d 4323 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4324 int i = val;
4325 bool has_audio;
4326
4327 if (i == intel_dp->force_audio)
f684960e
CW		 4328 return 0;
4329
1aad7ac0 4330 intel_dp->force_audio = i;
f684960e 4331
c3e5f67b 4332 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4333 has_audio = intel_dp_detect_audio(connector);
4334 else
c3e5f67b 4335 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4336
4337 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4338 return 0;
4339
1aad7ac0 4340 intel_dp->has_audio = has_audio;
f684960e
CW		 4341 goto done;
4342 }
4343
e953fd7b 4344 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4345 bool old_auto = intel_dp->color_range_auto;
4346 uint32_t old_range = intel_dp->color_range;
4347
55bc60db
VS		 4348 switch (val) {
4349 case INTEL_BROADCAST_RGB_AUTO:
4350 intel_dp->color_range_auto = true;
4351 break;
4352 case INTEL_BROADCAST_RGB_FULL:
4353 intel_dp->color_range_auto = false;
4354 intel_dp->color_range = 0;
4355 break;
4356 case INTEL_BROADCAST_RGB_LIMITED:
4357 intel_dp->color_range_auto = false;
4358 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4359 break;
4360 default:
4361 return -EINVAL;
4362 }
ae4edb80
DV		 4363
4364 if (old_auto == intel_dp->color_range_auto &&
4365 old_range == intel_dp->color_range)
4366 return 0;
4367
e953fd7b
CW		 4368 goto done;
4369 }
4370
53b41837
YN		 4371 if (is_edp(intel_dp) &&
4372 property == connector->dev->mode_config.scaling_mode_property) {
4373 if (val == DRM_MODE_SCALE_NONE) {
4374 DRM_DEBUG_KMS("no scaling not supported\n");
4375 return -EINVAL;
4376 }
4377
4378 if (intel_connector->panel.fitting_mode == val) {
4379 /* the eDP scaling property is not changed */
4380 return 0;
4381 }
4382 intel_connector->panel.fitting_mode = val;
4383
4384 goto done;
4385 }
4386
f684960e
CW		 4387 return -EINVAL;
4388
4389done:
c0c36b94
CW		 4390 if (intel_encoder->base.crtc)
4391 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4392
4393 return 0;
4394}
4395
a4fc5ed6 4396static void
73845adf 4397intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4398{
1d508706 4399 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4400
10e972d3 4401 kfree(intel_connector->detect_edid);
beb60608 4402
9cd300e0
JN		 4403 if (!IS_ERR_OR_NULL(intel_connector->edid))
4404 kfree(intel_connector->edid);
4405
acd8db10
PZ		 4406 /* Can't call is_edp() since the encoder may have been destroyed
4407 * already. */
4408 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4409 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4410
a4fc5ed6 4411 drm_connector_cleanup(connector);
55f78c43 4412 kfree(connector);
a4fc5ed6
KP		 4413}
4414
00c09d70 4415void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4416{
da63a9f2
PZ		 4417 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4418 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4419
4f71d0cb 4420 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4421 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4422 drm_encoder_cleanup(encoder);
bd943159
KP		 4423 if (is_edp(intel_dp)) {
4424 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4425 /*
4426 * vdd might still be enabled do to the delayed vdd off.
4427 * Make sure vdd is actually turned off here.
4428 */
773538e8 4429 pps_lock(intel_dp);
4be73780 4430 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4431 pps_unlock(intel_dp);
4432
01527b31
CT		 4433 if (intel_dp->edp_notifier.notifier_call) {
4434 unregister_reboot_notifier(&intel_dp->edp_notifier);
4435 intel_dp->edp_notifier.notifier_call = NULL;
4436 }
bd943159 4437 }
da63a9f2 4438 kfree(intel_dig_port);
24d05927
DV		 4439}
4440
07f9cd0b
ID		 4441static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4442{
4443 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4444
4445 if (!is_edp(intel_dp))
4446 return;
4447
951468f3
VS		 4448 /*
4449 * vdd might still be enabled do to the delayed vdd off.
4450 * Make sure vdd is actually turned off here.
4451 */
773538e8 4452 pps_lock(intel_dp);
07f9cd0b 4453 edp_panel_vdd_off_sync(intel_dp);
773538e8 4454 pps_unlock(intel_dp);
07f9cd0b
ID		 4455}
4456
6d93c0c4
ID		 4457static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4458{
4459 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4460}
4461
a4fc5ed6 4462static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4463 .dpms = intel_connector_dpms,
a4fc5ed6 4464 .detect = intel_dp_detect,
beb60608 4465 .force = intel_dp_force,
a4fc5ed6 4466 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4467 .set_property = intel_dp_set_property,
73845adf 4468 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4469};
4470
4471static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4472 .get_modes = intel_dp_get_modes,
4473 .mode_valid = intel_dp_mode_valid,
df0e9248 4474 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4475};
4476
a4fc5ed6 4477static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4478 .reset = intel_dp_encoder_reset,
24d05927 4479 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4480};
4481
0e32b39c 4482void
21d40d37 4483intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4484{
0e32b39c 4485 return;
c8110e52 4486}
6207937d 4487
13cf5504
DA		 4488bool
4489intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4490{
4491 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4492 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4493 struct drm_device *dev = intel_dig_port->base.base.dev;
4494 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4495 enum intel_display_power_domain power_domain;
4496 bool ret = true;
4497
0e32b39c
DA		 4498 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4499 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4500
26fbb774
VS		 4501 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4502 port_name(intel_dig_port->port),
0e32b39c 4503 long_hpd ? "long" : "short");
13cf5504 4504
1c767b33
ID		 4505 power_domain = intel_display_port_power_domain(intel_encoder);
4506 intel_display_power_get(dev_priv, power_domain);
4507
0e32b39c 4508 if (long_hpd) {
2a592bec
DA		 4509
4510 if (HAS_PCH_SPLIT(dev)) {
4511 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4512 goto mst_fail;
4513 } else {
4514 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4515 goto mst_fail;
4516 }
0e32b39c
DA		 4517
4518 if (!intel_dp_get_dpcd(intel_dp)) {
4519 goto mst_fail;
4520 }
4521
4522 intel_dp_probe_oui(intel_dp);
4523
4524 if (!intel_dp_probe_mst(intel_dp))
4525 goto mst_fail;
4526
4527 } else {
4528 if (intel_dp->is_mst) {
1c767b33 4529 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4530 goto mst_fail;
4531 }
4532
4533 if (!intel_dp->is_mst) {
4534 /*
4535 * we'll check the link status via the normal hot plug path later -
4536 * but for short hpds we should check it now
4537 */
5b215bcf 4538 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4539 intel_dp_check_link_status(intel_dp);
5b215bcf 4540 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4541 }
4542 }
1c767b33
ID		 4543 ret = false;
4544 goto put_power;
0e32b39c
DA		 4545mst_fail:
4546 /* if we were in MST mode, and device is not there get out of MST mode */
4547 if (intel_dp->is_mst) {
4548 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4549 intel_dp->is_mst = false;
4550 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4551 }
1c767b33
ID		 4552put_power:
4553 intel_display_power_put(dev_priv, power_domain);
4554
4555 return ret;
13cf5504
DA		 4556}
4557
e3421a18
ZW		 4558/* Return which DP Port should be selected for Transcoder DP control */
4559int
0206e353 4560intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4561{
4562 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4563 struct intel_encoder *intel_encoder;
4564 struct intel_dp *intel_dp;
e3421a18 4565
fa90ecef
PZ		 4566 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4567 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4568
fa90ecef
PZ		 4569 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4570 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4571 return intel_dp->output_reg;
e3421a18 4572 }
ea5b213a 4573
e3421a18
ZW		 4574 return -1;
4575}
4576
36e83a18 4577/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4578bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4579{
4580 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4581 union child_device_config *p_child;
36e83a18 4582 int i;
5d8a7752
VS		 4583 static const short port_mapping[] = {
4584 [PORT_B] = PORT_IDPB,
4585 [PORT_C] = PORT_IDPC,
4586 [PORT_D] = PORT_IDPD,
4587 };
36e83a18 4588
3b32a35b
VS		 4589 if (port == PORT_A)
4590 return true;
4591
41aa3448 4592 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4593 return false;
4594
41aa3448
RV		 4595 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4596 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4597
5d8a7752 4598 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4599 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4600 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4601 return true;
4602 }
4603 return false;
4604}
4605
0e32b39c 4606void
f684960e
CW		 4607intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4608{
53b41837
YN		 4609 struct intel_connector *intel_connector = to_intel_connector(connector);
4610
3f43c48d 4611 intel_attach_force_audio_property(connector);
e953fd7b 4612 intel_attach_broadcast_rgb_property(connector);
55bc60db 4613 intel_dp->color_range_auto = true;
53b41837
YN		 4614
4615 if (is_edp(intel_dp)) {
4616 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4617 drm_object_attach_property(
4618 &connector->base,
53b41837 4619 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4620 DRM_MODE_SCALE_ASPECT);
4621 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4622 }
f684960e
CW		 4623}
4624
dada1a9f
ID		 4625static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4626{
4627 intel_dp->last_power_cycle = jiffies;
4628 intel_dp->last_power_on = jiffies;
4629 intel_dp->last_backlight_off = jiffies;
4630}
4631
67a54566
DV		 4632static void
4633intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4634 struct intel_dp *intel_dp,
4635 struct edp_power_seq *out)
67a54566
DV		 4636{
4637 struct drm_i915_private *dev_priv = dev->dev_private;
4638 struct edp_power_seq cur, vbt, spec, final;
4639 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4640 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4641
e39b999a
VS		 4642 lockdep_assert_held(&dev_priv->pps_mutex);
4643
453c5420 4644 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4645 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4646 pp_on_reg = PCH_PP_ON_DELAYS;
4647 pp_off_reg = PCH_PP_OFF_DELAYS;
4648 pp_div_reg = PCH_PP_DIVISOR;
4649 } else {
bf13e81b
JN		 4650 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4651
4652 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4653 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4654 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4655 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4656 }
67a54566
DV		 4657
4658 /* Workaround: Need to write PP_CONTROL with the unlock key as
4659 * the very first thing. */
453c5420 4660 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4661 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4662
453c5420
JB		 4663 pp_on = I915_READ(pp_on_reg);
4664 pp_off = I915_READ(pp_off_reg);
4665 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4666
4667 /* Pull timing values out of registers */
4668 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4669 PANEL_POWER_UP_DELAY_SHIFT;
4670
4671 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4672 PANEL_LIGHT_ON_DELAY_SHIFT;
4673
4674 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4675 PANEL_LIGHT_OFF_DELAY_SHIFT;
4676
4677 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4678 PANEL_POWER_DOWN_DELAY_SHIFT;
4679
4680 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4681 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4682
4683 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4684 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4685
41aa3448 4686 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4687
4688 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4689 * our hw here, which are all in 100usec. */
4690 spec.t1_t3 = 210 * 10;
4691 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4692 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4693 spec.t10 = 500 * 10;
4694 /* This one is special and actually in units of 100ms, but zero
4695 * based in the hw (so we need to add 100 ms). But the sw vbt
4696 * table multiplies it with 1000 to make it in units of 100usec,
4697 * too. */
4698 spec.t11_t12 = (510 + 100) * 10;
4699
4700 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4701 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4702
4703 /* Use the max of the register settings and vbt. If both are
4704 * unset, fall back to the spec limits. */
4705#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4706 spec.field : \
4707 max(cur.field, vbt.field))
4708 assign_final(t1_t3);
4709 assign_final(t8);
4710 assign_final(t9);
4711 assign_final(t10);
4712 assign_final(t11_t12);
4713#undef assign_final
4714
4715#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4716 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4717 intel_dp->backlight_on_delay = get_delay(t8);
4718 intel_dp->backlight_off_delay = get_delay(t9);
4719 intel_dp->panel_power_down_delay = get_delay(t10);
4720 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4721#undef get_delay
4722
f30d26e4
JN		 4723 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4724 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4725 intel_dp->panel_power_cycle_delay);
4726
4727 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4728 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4729
4730 if (out)
4731 *out = final;
4732}
4733
4734static void
4735intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4736 struct intel_dp *intel_dp,
4737 struct edp_power_seq *seq)
4738{
4739 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4740 u32 pp_on, pp_off, pp_div, port_sel = 0;
4741 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4742 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4743 enum port port = dp_to_dig_port(intel_dp)->port;
453c5420 4744
e39b999a 4745 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4746
4747 if (HAS_PCH_SPLIT(dev)) {
4748 pp_on_reg = PCH_PP_ON_DELAYS;
4749 pp_off_reg = PCH_PP_OFF_DELAYS;
4750 pp_div_reg = PCH_PP_DIVISOR;
4751 } else {
bf13e81b
JN		 4752 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4753
4754 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4755 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4756 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4757 }
4758
b2f19d1a
PZ		 4759 /*
4760 * And finally store the new values in the power sequencer. The
4761 * backlight delays are set to 1 because we do manual waits on them. For
4762 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4763 * we'll end up waiting for the backlight off delay twice: once when we
4764 * do the manual sleep, and once when we disable the panel and wait for
4765 * the PP_STATUS bit to become zero.
4766 */
f30d26e4 4767 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4768 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4769 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4770 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4771 /* Compute the divisor for the pp clock, simply match the Bspec
4772 * formula. */
453c5420 4773 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4774 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4775 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4776
4777 /* Haswell doesn't have any port selection bits for the panel
4778 * power sequencer any more. */
bc7d38a4 4779 if (IS_VALLEYVIEW(dev)) {
ad933b56 4780 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4781 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4782 if (port == PORT_A)
a24c144c 4783 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4784 else
a24c144c 4785 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4786 }
4787
453c5420
JB		 4788 pp_on |= port_sel;
4789
4790 I915_WRITE(pp_on_reg, pp_on);
4791 I915_WRITE(pp_off_reg, pp_off);
4792 I915_WRITE(pp_div_reg, pp_div);
67a54566 4793
67a54566 4794 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4795 I915_READ(pp_on_reg),
4796 I915_READ(pp_off_reg),
4797 I915_READ(pp_div_reg));
f684960e
CW		 4798}
4799
439d7ac0
PB		 4800void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4801{
4802 struct drm_i915_private *dev_priv = dev->dev_private;
4803 struct intel_encoder *encoder;
4804 struct intel_dp *intel_dp = NULL;
4805 struct intel_crtc_config *config = NULL;
4806 struct intel_crtc *intel_crtc = NULL;
4807 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4808 u32 reg, val;
4809 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4810
4811 if (refresh_rate <= 0) {
4812 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4813 return;
4814 }
4815
4816 if (intel_connector == NULL) {
4817 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4818 return;
4819 }
4820
1fcc9d1c
DV		 4821 /*
4822 * FIXME: This needs proper synchronization with psr state. But really
4823 * hard to tell without seeing the user of this function of this code.
4824 * Check locking and ordering once that lands.
4825 */
439d7ac0
PB		 4826 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4827 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4828 return;
4829 }
4830
4831 encoder = intel_attached_encoder(&intel_connector->base);
4832 intel_dp = enc_to_intel_dp(&encoder->base);
4833 intel_crtc = encoder->new_crtc;
4834
4835 if (!intel_crtc) {
4836 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4837 return;
4838 }
4839
4840 config = &intel_crtc->config;
4841
4842 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4843 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4844 return;
4845 }
4846
4847 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4848 index = DRRS_LOW_RR;
4849
4850 if (index == intel_dp->drrs_state.refresh_rate_type) {
4851 DRM_DEBUG_KMS(
4852 "DRRS requested for previously set RR...ignoring\n");
4853 return;
4854 }
4855
4856 if (!intel_crtc->active) {
4857 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4858 return;
4859 }
4860
4861 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4862 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4863 val = I915_READ(reg);
4864 if (index > DRRS_HIGH_RR) {
4865 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4866 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4867 } else {
4868 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4869 }
4870 I915_WRITE(reg, val);
4871 }
4872
4873 /*
4874 * mutex taken to ensure that there is no race between differnt
4875 * drrs calls trying to update refresh rate. This scenario may occur
4876 * in future when idleness detection based DRRS in kernel and
4877 * possible calls from user space to set differnt RR are made.
4878 */
4879
4880 mutex_lock(&intel_dp->drrs_state.mutex);
4881
4882 intel_dp->drrs_state.refresh_rate_type = index;
4883
4884 mutex_unlock(&intel_dp->drrs_state.mutex);
4885
4886 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4887}
4888
4f9db5b5
PB		 4889static struct drm_display_mode *
4890intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4891 struct intel_connector *intel_connector,
4892 struct drm_display_mode *fixed_mode)
4893{
4894 struct drm_connector *connector = &intel_connector->base;
4895 struct intel_dp *intel_dp = &intel_dig_port->dp;
4896 struct drm_device *dev = intel_dig_port->base.base.dev;
4897 struct drm_i915_private *dev_priv = dev->dev_private;
4898 struct drm_display_mode *downclock_mode = NULL;
4899
4900 if (INTEL_INFO(dev)->gen <= 6) {
4901 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4902 return NULL;
4903 }
4904
4905 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4906 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4907 return NULL;
4908 }
4909
4910 downclock_mode = intel_find_panel_downclock
4911 (dev, fixed_mode, connector);
4912
4913 if (!downclock_mode) {
4079b8d1 4914 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4915 return NULL;
4916 }
4917
439d7ac0
PB		 4918 dev_priv->drrs.connector = intel_connector;
4919
4920 mutex_init(&intel_dp->drrs_state.mutex);
4921
4f9db5b5
PB		 4922 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4923
4924 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4925 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4926 return downclock_mode;
4927}
4928
aba86890
ID		 4929void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4930{
4931 struct drm_device *dev = intel_encoder->base.dev;
4932 struct drm_i915_private *dev_priv = dev->dev_private;
4933 struct intel_dp *intel_dp;
4934 enum intel_display_power_domain power_domain;
4935
4936 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4937 return;
4938
4939 intel_dp = enc_to_intel_dp(&intel_encoder->base);
773538e8
VS		 4940
4941 pps_lock(intel_dp);
4942
aba86890 4943 if (!edp_have_panel_vdd(intel_dp))
e39b999a 4944 goto out;
aba86890
ID		 4945 /*
4946 * The VDD bit needs a power domain reference, so if the bit is
4947 * already enabled when we boot or resume, grab this reference and
4948 * schedule a vdd off, so we don't hold on to the reference
4949 * indefinitely.
4950 */
4951 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4952 power_domain = intel_display_port_power_domain(intel_encoder);
4953 intel_display_power_get(dev_priv, power_domain);
4954
4955 edp_panel_vdd_schedule_off(intel_dp);
e39b999a 4956 out:
773538e8 4957 pps_unlock(intel_dp);
aba86890
ID		 4958}
4959
ed92f0b2 4960static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4961 struct intel_connector *intel_connector,
4962 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4963{
4964 struct drm_connector *connector = &intel_connector->base;
4965 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4966 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4967 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4968 struct drm_i915_private *dev_priv = dev->dev_private;
4969 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4970 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4971 bool has_dpcd;
4972 struct drm_display_mode *scan;
4973 struct edid *edid;
4974
4f9db5b5
PB		 4975 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4976
ed92f0b2
PZ		 4977 if (!is_edp(intel_dp))
4978 return true;
4979
aba86890 4980 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 4981
ed92f0b2 4982 /* Cache DPCD and EDID for edp. */
24f3e092 4983 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4984 has_dpcd = intel_dp_get_dpcd(intel_dp);
1e0560e0 4985 intel_edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4986
4987 if (has_dpcd) {
4988 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4989 dev_priv->no_aux_handshake =
4990 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4991 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4992 } else {
4993 /* if this fails, presume the device is a ghost */
4994 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4995 return false;
4996 }
4997
4998 /* We now know it's not a ghost, init power sequence regs. */
773538e8 4999 pps_lock(intel_dp);
0095e6dc 5000 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
773538e8 5001 pps_unlock(intel_dp);
ed92f0b2 5002
060c8778 5003 mutex_lock(&dev->mode_config.mutex);
0b99836f 5004 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5005 if (edid) {
5006 if (drm_add_edid_modes(connector, edid)) {
5007 drm_mode_connector_update_edid_property(connector,
5008 edid);
5009 drm_edid_to_eld(connector, edid);
5010 } else {
5011 kfree(edid);
5012 edid = ERR_PTR(-EINVAL);
5013 }
5014 } else {
5015 edid = ERR_PTR(-ENOENT);
5016 }
5017 intel_connector->edid = edid;
5018
5019 /* prefer fixed mode from EDID if available */
5020 list_for_each_entry(scan, &connector->probed_modes, head) {
5021 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5022 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 5023 downclock_mode = intel_dp_drrs_init(
5024 intel_dig_port,
5025 intel_connector, fixed_mode);
ed92f0b2
PZ		 5026 break;
5027 }
5028 }
5029
5030 /* fallback to VBT if available for eDP */
5031 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5032 fixed_mode = drm_mode_duplicate(dev,
5033 dev_priv->vbt.lfp_lvds_vbt_mode);
5034 if (fixed_mode)
5035 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5036 }
060c8778 5037 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5038
01527b31
CT		 5039 if (IS_VALLEYVIEW(dev)) {
5040 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5041 register_reboot_notifier(&intel_dp->edp_notifier);
5042 }
5043
4f9db5b5 5044 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5045 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 5046 intel_panel_setup_backlight(connector);
5047
5048 return true;
5049}
5050
16c25533 5051bool
f0fec3f2
PZ		 5052intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5053 struct intel_connector *intel_connector)
a4fc5ed6 5054{
f0fec3f2
PZ		 5055 struct drm_connector *connector = &intel_connector->base;
5056 struct intel_dp *intel_dp = &intel_dig_port->dp;
5057 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5058 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5059 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5060 enum port port = intel_dig_port->port;
0095e6dc 5061 struct edp_power_seq power_seq = { 0 };
0b99836f 5062 int type;
a4fc5ed6 5063
a4a5d2f8
VS		 5064 intel_dp->pps_pipe = INVALID_PIPE;
5065
ec5b01dd
DL		 5066 /* intel_dp vfuncs */
5067 if (IS_VALLEYVIEW(dev))
5068 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5069 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5070 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5071 else if (HAS_PCH_SPLIT(dev))
5072 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5073 else
5074 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5075
153b1100
DL		 5076 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5077
0767935e
DV		 5078 /* Preserve the current hw state. */
5079 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5080 intel_dp->attached_connector = intel_connector;
3d3dc149 5081
3b32a35b 5082 if (intel_dp_is_edp(dev, port))
b329530c 5083 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5084 else
5085 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5086
f7d24902
ID		 5087 /*
5088 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5089 * for DP the encoder type can be set by the caller to
5090 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5091 */
5092 if (type == DRM_MODE_CONNECTOR_eDP)
5093 intel_encoder->type = INTEL_OUTPUT_EDP;
5094
e7281eab
ID		 5095 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5096 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5097 port_name(port));
5098
b329530c 5099 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5100 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5101
a4fc5ed6
KP		 5102 connector->interlace_allowed = true;
5103 connector->doublescan_allowed = 0;
5104
f0fec3f2 5105 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5106 edp_panel_vdd_work);
a4fc5ed6 5107
df0e9248 5108 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5109 drm_connector_register(connector);
a4fc5ed6 5110
affa9354 5111 if (HAS_DDI(dev))
bcbc889b
PZ		 5112 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5113 else
5114 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5115 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5116
0b99836f 5117 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5118 switch (port) {
5119 case PORT_A:
1d843f9d 5120 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5121 break;
5122 case PORT_B:
1d843f9d 5123 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5124 break;
5125 case PORT_C:
1d843f9d 5126 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5127 break;
5128 case PORT_D:
1d843f9d 5129 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5130 break;
5131 default:
ad1c0b19 5132 BUG();
5eb08b69
ZW		 5133 }
5134
dada1a9f 5135 if (is_edp(intel_dp)) {
773538e8 5136 pps_lock(intel_dp);
a4a5d2f8
VS		 5137 if (IS_VALLEYVIEW(dev)) {
5138 vlv_initial_power_sequencer_setup(intel_dp);
5139 } else {
5140 intel_dp_init_panel_power_timestamps(intel_dp);
5141 intel_dp_init_panel_power_sequencer(dev, intel_dp,
5142 &power_seq);
5143 }
773538e8 5144 pps_unlock(intel_dp);
dada1a9f 5145 }
0095e6dc 5146
9d1a1031 5147 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5148
0e32b39c
DA		 5149 /* init MST on ports that can support it */
5150 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5151 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5152 intel_dp_mst_encoder_init(intel_dig_port,
5153 intel_connector->base.base.id);
0e32b39c
DA		 5154 }
5155 }
5156
0095e6dc 5157 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 5158 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5159 if (is_edp(intel_dp)) {
5160 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5161 /*
5162 * vdd might still be enabled do to the delayed vdd off.
5163 * Make sure vdd is actually turned off here.
5164 */
773538e8 5165 pps_lock(intel_dp);
4be73780 5166 edp_panel_vdd_off_sync(intel_dp);
773538e8 5167 pps_unlock(intel_dp);
15b1d171 5168 }
34ea3d38 5169 drm_connector_unregister(connector);
b2f246a8 5170 drm_connector_cleanup(connector);
16c25533 5171 return false;
b2f246a8 5172 }
32f9d658 5173
f684960e
CW		 5174 intel_dp_add_properties(intel_dp, connector);
5175
a4fc5ed6
KP		 5176 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5177 * 0xd. Failure to do so will result in spurious interrupts being
5178 * generated on the port when a cable is not attached.
5179 */
5180 if (IS_G4X(dev) && !IS_GM45(dev)) {
5181 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5182 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5183 }
16c25533
PZ		 5184
5185 return true;
a4fc5ed6 5186}
f0fec3f2
PZ		 5187
5188void
5189intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5190{
13cf5504 5191 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5192 struct intel_digital_port *intel_dig_port;
5193 struct intel_encoder *intel_encoder;
5194 struct drm_encoder *encoder;
5195 struct intel_connector *intel_connector;
5196
b14c5679 5197 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5198 if (!intel_dig_port)
5199 return;
5200
b14c5679 5201 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5202 if (!intel_connector) {
5203 kfree(intel_dig_port);
5204 return;
5205 }
5206
5207 intel_encoder = &intel_dig_port->base;
5208 encoder = &intel_encoder->base;
5209
5210 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5211 DRM_MODE_ENCODER_TMDS);
5212
5bfe2ac0 5213 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5214 intel_encoder->disable = intel_disable_dp;
00c09d70 5215 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5216 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5217 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5218 if (IS_CHERRYVIEW(dev)) {
9197c88b 5219 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5220 intel_encoder->pre_enable = chv_pre_enable_dp;
5221 intel_encoder->enable = vlv_enable_dp;
580d3811 5222 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5223 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5224 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5225 intel_encoder->pre_enable = vlv_pre_enable_dp;
5226 intel_encoder->enable = vlv_enable_dp;
49277c31 5227 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5228 } else {
ecff4f3b
JN		 5229 intel_encoder->pre_enable = g4x_pre_enable_dp;
5230 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5231 if (INTEL_INFO(dev)->gen >= 5)
5232 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5233 }
f0fec3f2 5234
174edf1f 5235 intel_dig_port->port = port;
f0fec3f2
PZ		 5236 intel_dig_port->dp.output_reg = output_reg;
5237
00c09d70 5238 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5239 if (IS_CHERRYVIEW(dev)) {
5240 if (port == PORT_D)
5241 intel_encoder->crtc_mask = 1 << 2;
5242 else
5243 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5244 } else {
5245 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5246 }
bc079e8b 5247 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5248 intel_encoder->hot_plug = intel_dp_hot_plug;
5249
13cf5504
DA		 5250 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5251 dev_priv->hpd_irq_port[port] = intel_dig_port;
5252
15b1d171
PZ		 5253 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5254 drm_encoder_cleanup(encoder);
5255 kfree(intel_dig_port);
b2f246a8 5256 kfree(intel_connector);
15b1d171 5257 }
f0fec3f2 5258}
0e32b39c
DA		 5259
5260void intel_dp_mst_suspend(struct drm_device *dev)
5261{
5262 struct drm_i915_private *dev_priv = dev->dev_private;
5263 int i;
5264
5265 /* disable MST */
5266 for (i = 0; i < I915_MAX_PORTS; i++) {
5267 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5268 if (!intel_dig_port)
5269 continue;
5270
5271 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5272 if (!intel_dig_port->dp.can_mst)
5273 continue;
5274 if (intel_dig_port->dp.is_mst)
5275 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5276 }
5277 }
5278}
5279
5280void intel_dp_mst_resume(struct drm_device *dev)
5281{
5282 struct drm_i915_private *dev_priv = dev->dev_private;
5283 int i;
5284
5285 for (i = 0; i < I915_MAX_PORTS; i++) {
5286 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5287 if (!intel_dig_port)
5288 continue;
5289 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5290 int ret;
5291
5292 if (!intel_dig_port->dp.can_mst)
5293 continue;
5294
5295 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5296 if (ret != 0) {
5297 intel_dp_check_mst_status(&intel_dig_port->dp);
5298 }
5299 }
5300 }
5301}
Linux kernel - Deliverables
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