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Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same register
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
91802f3c
JB		 12019-11-11 Jan Beulich <jbeulich@suse.com>
2
3 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
4 smaxp/sminp entries' "tied_operand" field to 2.
5
4f5fc85d
JB		 62019-11-11 Jan Beulich <jbeulich@suse.com>
7
8 * aarch64-opc.c (operand_general_constraint_met_p): Replace
9 "index" local variable by that of the already existing "num".
10
dc2be329
L		 112019-11-08 H.J. Lu <hongjiu.lu@intel.com>
12
13 PR gas/25167
14 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
15 * i386-tbl.h: Regenerated.
16
f74a6307
JB		 172019-11-08 Jan Beulich <jbeulich@suse.com>
18
19 * i386-gen.c (operand_type_init): Add Class= to
20 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
21 OPERAND_TYPE_REGBND entry.
22 (operand_classes): Add RegMask and RegBND entries.
23 (operand_types): Drop RegMask and RegBND entry.
24 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
25 (RegMask, RegBND): Delete.
26 (union i386_operand_type): Remove regmask and regbnd fields.
27 * i386-opc.tbl (RegMask, RegBND): Define.
28 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
29 Class=RegBND.
30 * i386-init.h, i386-tbl.h: Re-generate.
31
3528c362
JB		 322019-11-08 Jan Beulich <jbeulich@suse.com>
33
34 * i386-gen.c (operand_type_init): Add Class= to
35 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
36 OPERAND_TYPE_REGZMM entries.
37 (operand_classes): Add RegMMX and RegSIMD entries.
38 (operand_types): Drop RegMMX and RegSIMD entries.
39 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
40 (RegMMX, RegSIMD): Delete.
41 (union i386_operand_type): Remove regmmx and regsimd fields.
42 * i386-opc.tbl (RegMMX): Define.
43 (RegXMM, RegYMM, RegZMM): Add Class=.
44 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
45 Class=RegSIMD.
46 * i386-init.h, i386-tbl.h: Re-generate.
47
4a5c67ed
JB		 482019-11-08 Jan Beulich <jbeulich@suse.com>
49
50 * i386-gen.c (operand_type_init): Add Class= to
51 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
52 entries.
53 (operand_classes): Add RegCR, RegDR, and RegTR entries.
54 (operand_types): Drop Control, Debug, and Test entries.
55 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
56 (Control, Debug, Test): Delete.
57 (union i386_operand_type): Remove control, debug, and test
58 fields.
59 * i386-opc.tbl (Control, Debug, Test): Define.
60 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
61 Class=RegDR, and Test by Class=RegTR.
62 * i386-init.h, i386-tbl.h: Re-generate.
63
00cee14f
JB		 642019-11-08 Jan Beulich <jbeulich@suse.com>
65
66 * i386-gen.c (operand_type_init): Add Class= to
67 OPERAND_TYPE_SREG entry.
68 (operand_classes): Add SReg entry.
69 (operand_types): Drop SReg entry.
70 * i386-opc.h (enum operand_class): Add SReg.
71 (SReg): Delete.
72 (union i386_operand_type): Remove sreg field.
73 * i386-opc.tbl (SReg): Define.
74 * i386-reg.tbl: Replace SReg by Class=SReg.
75 * i386-init.h, i386-tbl.h: Re-generate.
76
bab6aec1
JB		 772019-11-08 Jan Beulich <jbeulich@suse.com>
78
79 * i386-gen.c (operand_type_init): Add Class=. New
80 OPERAND_TYPE_ANYIMM entry.
81 (operand_classes): New.
82 (operand_types): Drop Reg entry.
83 (output_operand_type): New parameter "class". Process it.
84 (process_i386_operand_type): New local variable "class".
85 (main): Adjust static assertions.
86 * i386-opc.h (CLASS_WIDTH): Define.
87 (enum operand_class): New.
88 (Reg): Replace by Class. Adjust comment.
89 (union i386_operand_type): Replace reg by class.
90 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
91 Class=.
92 * i386-reg.tbl: Replace Reg by Class=Reg.
93 * i386-init.h: Re-generate.
94
1f4cd317
MM		 952019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
96
97 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
98 (aarch64_opcode_table): Add data gathering hint mnemonic.
99 * opcodes/aarch64-dis-2.c: Account for new instruction.
100
616ce08e
MM		 1012019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
102
103 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
104
105
8382113f
MM		 1062019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
107
108 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
109 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
110 aarch64_feature_f64mm): New feature sets.
111 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
112 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
113 instructions.
114 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
115 macros.
116 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
117 (OP_SVE_QQQ): New qualifier.
118 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
119 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
120 the movprfx constraint.
121 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
122 (aarch64_opcode_table): Define new instructions smmla,
123 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
124 uzip{1/2}, trn{1/2}.
125 * aarch64-opc.c (operand_general_constraint_met_p): Handle
126 AARCH64_OPND_SVE_ADDR_RI_S4x32.
127 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
128 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
129 Account for new instructions.
130 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
131 S4x32 operand.
132 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
133
aab2c27d
MM		 1342019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
1352019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
136
137 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
138 Armv8.6-A.
139 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
140 (neon_opcodes): Add bfloat SIMD instructions.
141 (print_insn_coprocessor): Add new control character %b to print
142 condition code without checking cp_num.
143 (print_insn_neon): Account for BFloat16 instructions that have no
144 special top-byte handling.
145
33593eaf
MM		 1462019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
1472019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
148
149 * arm-dis.c (print_insn_coprocessor,
150 print_insn_generic_coprocessor): Create wrapper functions around
151 the implementation of the print_insn_coprocessor control codes.
152 (print_insn_coprocessor_1): Original print_insn_coprocessor
153 function that now takes which array to look at as an argument.
154 (print_insn_arm): Use both print_insn_coprocessor and
155 print_insn_generic_coprocessor.
156 (print_insn_thumb32): As above.
157
df678013
MM		 1582019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
1592019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
160
161 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
162 in reglane special case.
163 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
164 aarch64_find_next_opcode): Account for new instructions.
165 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
166 in reglane special case.
167 * aarch64-opc.c (struct operand_qualifier_data): Add data for
168 new AARCH64_OPND_QLF_S_2H qualifier.
169 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
170 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
171 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
172 sets.
173 (BFLOAT_SVE, BFLOAT): New feature set macros.
174 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
175 instructions.
176 (aarch64_opcode_table): Define new instructions bfdot,
177 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
178 bfcvtn2, bfcvt.
179
8ae2d3d9
MM		 1802019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
1812019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
182
183 * aarch64-tbl.h (ARMV8_6): New macro.
184
142861df
JB		 1852019-11-07 Jan Beulich <jbeulich@suse.com>
186
187 * i386-dis.c (prefix_table): Add mcommit.
188 (rm_table): Add rdpru.
189 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
190 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
191 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
192 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
193 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
194 * i386-opc.tbl (mcommit, rdpru): New.
195 * i386-init.h, i386-tbl.h: Re-generate.
196
081e283f
JB		 1972019-11-07 Jan Beulich <jbeulich@suse.com>
198
199 * i386-dis.c (OP_Mwait): Drop local variable "names", use
200 "names32" instead.
201 (OP_Monitor): Drop local variable "op1_names", re-purpose
202 "names" for it instead, and replace former "names" uses by
203 "names32" ones.
204
c050c89a
JB		 2052019-11-07 Jan Beulich <jbeulich@suse.com>
206
207 PR/gas 25167
208 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
209 operand-less forms.
210 * opcodes/i386-tbl.h: Re-generate.
211
7abb8d81
JB		 2122019-11-05 Jan Beulich <jbeulich@suse.com>
213
214 * i386-dis.c (OP_Mwaitx): Delete.
215 (prefix_table): Use OP_Mwait for mwaitx entry.
216 (OP_Mwait): Also handle mwaitx.
217
267b8516
JB		 2182019-11-05 Jan Beulich <jbeulich@suse.com>
219
220 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
221 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
222 (prefix_table): Add respective entries.
223 (rm_table): Link to those entries.
224
f8687e93
JB		 2252019-11-05 Jan Beulich <jbeulich@suse.com>
226
227 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
228 (REG_0F1C_P_0_MOD_0): ... this.
229 (REG_0F1E_MOD_3): Rename to ...
230 (REG_0F1E_P_1_MOD_3): ... this.
231 (RM_0F01_REG_5): Rename to ...
232 (RM_0F01_REG_5_MOD_3): ... this.
233 (RM_0F01_REG_7): Rename to ...
234 (RM_0F01_REG_7_MOD_3): ... this.
235 (RM_0F1E_MOD_3_REG_7): Rename to ...
236 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
237 (RM_0FAE_REG_6): Rename to ...
238 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
239 (RM_0FAE_REG_7): Rename to ...
240 (RM_0FAE_REG_7_MOD_3): ... this.
241 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
242 (PREFIX_0F01_REG_5_MOD_0): ... this.
243 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
244 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
245 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
246 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
247 (PREFIX_0FAE_REG_0): Rename to ...
248 (PREFIX_0FAE_REG_0_MOD_3): ... this.
249 (PREFIX_0FAE_REG_1): Rename to ...
250 (PREFIX_0FAE_REG_1_MOD_3): ... this.
251 (PREFIX_0FAE_REG_2): Rename to ...
252 (PREFIX_0FAE_REG_2_MOD_3): ... this.
253 (PREFIX_0FAE_REG_3): Rename to ...
254 (PREFIX_0FAE_REG_3_MOD_3): ... this.
255 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
256 (PREFIX_0FAE_REG_4_MOD_0): ... this.
257 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
258 (PREFIX_0FAE_REG_4_MOD_3): ... this.
259 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
260 (PREFIX_0FAE_REG_5_MOD_0): ... this.
261 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
262 (PREFIX_0FAE_REG_5_MOD_3): ... this.
263 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
264 (PREFIX_0FAE_REG_6_MOD_0): ... this.
265 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
266 (PREFIX_0FAE_REG_6_MOD_3): ... this.
267 (PREFIX_0FAE_REG_7): Rename to ...
268 (PREFIX_0FAE_REG_7_MOD_0): ... this.
269 (PREFIX_MOD_0_0FC3): Rename to ...
270 (PREFIX_0FC3_MOD_0): ... this.
271 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
272 (PREFIX_0FC7_REG_6_MOD_0): ... this.
273 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
274 (PREFIX_0FC7_REG_6_MOD_3): ... this.
275 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
276 (PREFIX_0FC7_REG_7_MOD_3): ... this.
277 (reg_table, prefix_table, mod_table, rm_table): Adjust
278 accordingly.
279
5103274f
NC		 2802019-11-04 Nick Clifton <nickc@redhat.com>
281
282 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
283 of a v850 system register. Move the v850_sreg_names array into
284 this function.
285 (get_v850_reg_name): Likewise for ordinary register names.
286 (get_v850_vreg_name): Likewise for vector register names.
287 (get_v850_cc_name): Likewise for condition codes.
288 * get_v850_float_cc_name): Likewise for floating point condition
289 codes.
290 (get_v850_cacheop_name): Likewise for cache-ops.
291 (get_v850_prefop_name): Likewise for pref-ops.
292 (disassemble): Use the new accessor functions.
293
1820262b
DB		 2942019-10-30 Delia Burduv <delia.burduv@arm.com>
295
296 * aarch64-opc.c (print_immediate_offset_address): Don't print the
297 immediate for the writeback form of ldraa/ldrab if it is 0.
298 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
299 * aarch64-opc-2.c: Regenerated.
300
3cc17af5
JB		 3012019-10-30 Jan Beulich <jbeulich@suse.com>
302
303 * i386-gen.c (operand_type_shorthands): Delete.
304 (operand_type_init): Expand previous shorthands.
305 (set_bitfield_from_shorthand): Rename back to ...
306 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
307 of operand_type_init[].
308 (set_bitfield): Adjust call to the above function.
309 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
310 RegXMM, RegYMM, RegZMM): Define.
311 * i386-reg.tbl: Expand prior shorthands.
312
a2cebd03
JB		 3132019-10-30 Jan Beulich <jbeulich@suse.com>
314
315 * i386-gen.c (output_i386_opcode): Change order of fields
316 emitted to output.
317 * i386-opc.h (struct insn_template): Move operands field.
318 Convert extension_opcode field to unsigned short.
319 * i386-tbl.h: Re-generate.
320
507916b8
JB		 3212019-10-30 Jan Beulich <jbeulich@suse.com>
322
323 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
324 of W.
325 * i386-opc.h (W): Extend comment.
326 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
327 general purpose variants not allowing for byte operands.
328 * i386-tbl.h: Re-generate.
329
efea62b4
NC		 3302019-10-29 Nick Clifton <nickc@redhat.com>
331
332 * tic30-dis.c (print_branch): Correct size of operand array.
333
9adb2591
NC		 3342019-10-29 Nick Clifton <nickc@redhat.com>
335
336 * d30v-dis.c (print_insn): Check that operand index is valid
337 before attempting to access the operands array.
338
993a00a9
NC		 3392019-10-29 Nick Clifton <nickc@redhat.com>
340
341 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
342 locating the bit to be tested.
343
66a66a17
NC		 3442019-10-29 Nick Clifton <nickc@redhat.com>
345
346 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
347 values.
348 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
349 (print_insn_s12z): Check for illegal size values.
350
1ee3542c
NC		 3512019-10-28 Nick Clifton <nickc@redhat.com>
352
353 * csky-dis.c (csky_chars_to_number): Check for a negative
354 count. Use an unsigned integer to construct the return value.
355
bbf9a0b5
NC		 3562019-10-28 Nick Clifton <nickc@redhat.com>
357
358 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
359 operand buffer. Set value to 15 not 13.
360 (get_register_operand): Use OPERAND_BUFFER_LEN.
361 (get_indirect_operand): Likewise.
362 (print_two_operand): Likewise.
363 (print_three_operand): Likewise.
364 (print_oar_insn): Likewise.
365
d1e304bc
NC		 3662019-10-28 Nick Clifton <nickc@redhat.com>
367
368 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
369 (bit_extract_simple): Likewise.
370 (bit_copy): Likewise.
371 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
372 index_offset array are not accessed.
373
dee33451
NC		 3742019-10-28 Nick Clifton <nickc@redhat.com>
375
376 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
377 operand.
378
27cee81d
NC		 3792019-10-25 Nick Clifton <nickc@redhat.com>
380
381 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
382 access to opcodes.op array element.
383
de6d8dc2
NC		 3842019-10-23 Nick Clifton <nickc@redhat.com>
385
386 * rx-dis.c (get_register_name): Fix spelling typo in error
387 message.
388 (get_condition_name, get_flag_name, get_double_register_name)
389 (get_double_register_high_name, get_double_register_low_name)
390 (get_double_control_register_name, get_double_condition_name)
391 (get_opsize_name, get_size_name): Likewise.
392
6207ed28
NC		 3932019-10-22 Nick Clifton <nickc@redhat.com>
394
395 * rx-dis.c (get_size_name): New function. Provides safe
396 access to name array.
397 (get_opsize_name): Likewise.
398 (print_insn_rx): Use the accessor functions.
399
12234dfd
NC		 4002019-10-16 Nick Clifton <nickc@redhat.com>
401
402 * rx-dis.c (get_register_name): New function. Provides safe
403 access to name array.
404 (get_condition_name, get_flag_name, get_double_register_name)
405 (get_double_register_high_name, get_double_register_low_name)
406 (get_double_control_register_name, get_double_condition_name):
407 Likewise.
408 (print_insn_rx): Use the accessor functions.
409
1d378749
NC		 4102019-10-09 Nick Clifton <nickc@redhat.com>
411
412 PR 25041
413 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
414 instructions.
415
d241b910
JB		 4162019-10-07 Jan Beulich <jbeulich@suse.com>
417
418 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
419 (cmpsd): Likewise. Move EsSeg to other operand.
420 * opcodes/i386-tbl.h: Re-generate.
421
f5c5b7c1
AM		 4222019-09-23 Alan Modra <amodra@gmail.com>
423
424 * m68k-dis.c: Include cpu-m68k.h
425
7beeaeb8
AM		 4262019-09-23 Alan Modra <amodra@gmail.com>
427
428 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
429 "elf/mips.h" earlier.
430
3f9aad11
JB		 4312018-09-20 Jan Beulich <jbeulich@suse.com>
432
433 PR gas/25012
434 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
435 with SReg operand.
436 * i386-tbl.h: Re-generate.
437
fd361982
AM		 4382019-09-18 Alan Modra <amodra@gmail.com>
439
440 * arc-ext.c: Update throughout for bfd section macro changes.
441
e0b2a78c
SM		 4422019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
443
444 * Makefile.in: Re-generate.
445 * configure: Re-generate.
446
7e9ad3a3
JW		 4472019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
448
449 * riscv-opc.c (riscv_opcodes): Change subset field
450 to insn_class field for all instructions.
451 (riscv_insn_types): Likewise.
452
bb695960
PB		 4532019-09-16 Phil Blundell <pb@pbcl.net>
454
455 * configure: Regenerated.
456
8063ab7e
MV		 4572019-09-10 Miod Vallat <miod@online.fr>
458
459 PR 24982
460 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
461
60391a25
PB		 4622019-09-09 Phil Blundell <pb@pbcl.net>
463
464 binutils 2.33 branch created.
465
f44b758d
NC		 4662019-09-03 Nick Clifton <nickc@redhat.com>
467
468 PR 24961
469 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
470 greater than zero before indexing via (bufcnt -1).
471
1e4b5e7d
NC		 4722019-09-03 Nick Clifton <nickc@redhat.com>
473
474 PR 24958
475 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
476 (MAX_SPEC_REG_NAME_LEN): Define.
477 (struct mmix_dis_info): Use defined constants for array lengths.
478 (get_reg_name): New function.
479 (get_sprec_reg_name): New function.
480 (print_insn_mmix): Use new functions.
481
c4a23bf8
SP		 4822019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
483
484 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
485 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
486 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
487
a051e2f3
KT		 4882019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
489
490 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
491 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
492 (aarch64_sys_reg_supported_p): Update checks for the above.
493
08132bdd
SP		 4942019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
495
496 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
497 cases MVE_SQRSHRL and MVE_UQRSHLL.
498 (print_insn_mve): Add case for specifier 'k' to check
499 specific bit of the instruction.
500
d88bdcb4
PA		 5012019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
502
503 PR 24854
504 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
505 encountering an unknown machine type.
506 (print_insn_arc): Handle arc_insn_length returning 0. In error
507 cases return -1 rather than calling abort.
508
bc750500
JB		 5092019-08-07 Jan Beulich <jbeulich@suse.com>
510
511 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
512 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
513 IgnoreSize.
514 * i386-tbl.h: Re-generate.
515
23d188c7
BW		 5162019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
517
518 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
519 instructions.
520
c0d6f62f
JW		 5212019-07-30 Mel Chen <mel.chen@sifive.com>
522
523 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
524 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
525
526 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
527 fscsr.
528
0f3f7167
CZ		 5292019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
530
531 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
532 and MPY class instructions.
533 (parse_option): Add nps400 option.
534 (print_arc_disassembler_options): Add nps400 info.
535
7e126ba3
CZ		 5362019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
537
538 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
539 (bspop): Likewise.
540 (modapp): Likewise.
541 * arc-opc.c (RAD_CHK): Add.
542 * arc-tbl.h: Regenerate.
543
a028026d
KT		 5442019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
545
546 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
547 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
548
ac79ff9e
NC		 5492019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
550
551 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
552 instructions as UNPREDICTABLE.
553
231097b0
JM		 5542019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
555
556 * bpf-desc.c: Regenerated.
557
1d942ae9
JB		 5582019-07-17 Jan Beulich <jbeulich@suse.com>
559
560 * i386-gen.c (static_assert): Define.
561 (main): Use it.
562 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
563 (Opcode_Modifier_Num): ... this.
564 (Mem): Delete.
565
dfd69174
JB		 5662019-07-16 Jan Beulich <jbeulich@suse.com>
567
568 * i386-gen.c (operand_types): Move RegMem ...
569 (opcode_modifiers): ... here.
570 * i386-opc.h (RegMem): Move to opcode modifer enum.
571 (union i386_operand_type): Move regmem field ...
572 (struct i386_opcode_modifier): ... here.
573 * i386-opc.tbl (RegMem): Define.
574 (mov, movq): Move RegMem on segment, control, debug, and test
575 register flavors.
576 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
577 to non-SSE2AVX flavor.
578 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
579 Move RegMem on register only flavors. Drop IgnoreSize from
580 legacy encoding flavors.
581 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
582 flavors.
583 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
584 register only flavors.
585 (vmovd): Move RegMem and drop IgnoreSize on register only
586 flavor. Change opcode and operand order to store form.
587 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
588
21df382b
JB		 5892019-07-16 Jan Beulich <jbeulich@suse.com>
590
591 * i386-gen.c (operand_type_init, operand_types): Replace SReg
592 entries.
593 * i386-opc.h (SReg2, SReg3): Replace by ...
594 (SReg): ... this.
595 (union i386_operand_type): Replace sreg fields.
596 * i386-opc.tbl (mov, ): Use SReg.
597 (push, pop): Likewies. Drop i386 and x86-64 specific segment
598 register flavors.
599 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
600 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
601
3719fd55
JM		 6022019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
603
604 * bpf-desc.c: Regenerate.
605 * bpf-opc.c: Likewise.
606 * bpf-opc.h: Likewise.
607
92434a14
JM		 6082019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
609
610 * bpf-desc.c: Regenerate.
611 * bpf-opc.c: Likewise.
612
43dd7626
HPN		 6132019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
614
615 * arm-dis.c (print_insn_coprocessor): Rename index to
616 index_operand.
617
98602811
JW		 6182019-07-05 Kito Cheng <kito.cheng@sifive.com>
619
620 * riscv-opc.c (riscv_insn_types): Add r4 type.
621
622 * riscv-opc.c (riscv_insn_types): Add b and j type.
623
624 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
625 format for sb type and correct s type.
626
01c1ee4a
RS		 6272019-07-02 Richard Sandiford <richard.sandiford@arm.com>
628
629 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
630 SVE FMOV alias of FCPY.
631
83adff69
RS		 6322019-07-02 Richard Sandiford <richard.sandiford@arm.com>
633
634 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
635 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
636
89418844
RS		 6372019-07-02 Richard Sandiford <richard.sandiford@arm.com>
638
639 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
640 registers in an instruction prefixed by MOVPRFX.
641
41be57ca
MM		 6422019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
643
644 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
645 sve_size_13 icode to account for variant behaviour of
646 pmull{t,b}.
647 * aarch64-dis-2.c: Regenerate.
648 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
649 sve_size_13 icode to account for variant behaviour of
650 pmull{t,b}.
651 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
652 (OP_SVE_VVV_Q_D): Add new qualifier.
653 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
654 (struct aarch64_opcode): Split pmull{t,b} into those requiring
655 AES and those not.
656
9d3bf266
JB		 6572019-07-01 Jan Beulich <jbeulich@suse.com>
658
659 * opcodes/i386-gen.c (operand_type_init): Remove
660 OPERAND_TYPE_VEC_IMM4 entry.
661 (operand_types): Remove Vec_Imm4.
662 * opcodes/i386-opc.h (Vec_Imm4): Delete.
663 (union i386_operand_type): Remove vec_imm4.
664 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
665 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
666
c3949f43
JB		 6672019-07-01 Jan Beulich <jbeulich@suse.com>
668
669 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
670 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
671 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
672 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
673 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
674 monitorx, mwaitx): Drop ImmExt from operand-less forms.
675 * i386-tbl.h: Re-generate.
676
5641ec01
JB		 6772019-07-01 Jan Beulich <jbeulich@suse.com>
678
679 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
680 register operands.
681 * i386-tbl.h: Re-generate.
682
79dec6b7
JB		 6832019-07-01 Jan Beulich <jbeulich@suse.com>
684
685 * i386-opc.tbl (C): New.
686 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
687 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
688 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
689 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
690 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
691 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
692 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
693 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
694 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
695 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
696 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
697 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
698 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
699 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
700 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
701 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
702 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
703 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
704 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
705 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
706 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
707 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
708 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
709 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
710 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
711 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
712 flavors.
713 * i386-tbl.h: Re-generate.
714
a0a1771e
JB		 7152019-07-01 Jan Beulich <jbeulich@suse.com>
716
717 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
718 register operands.
719 * i386-tbl.h: Re-generate.
720
cd546e7b
JB		 7212019-07-01 Jan Beulich <jbeulich@suse.com>
722
723 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
724 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
725 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
726 * i386-tbl.h: Re-generate.
727
e3bba3fc
JB		 7282019-07-01 Jan Beulich <jbeulich@suse.com>
729
730 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
731 Disp8MemShift from register only templates.
732 * i386-tbl.h: Re-generate.
733
36cc073e
JB		 7342019-07-01 Jan Beulich <jbeulich@suse.com>
735
736 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
737 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
738 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
739 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
740 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
741 EVEX_W_0F11_P_3_M_1): Delete.
742 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
743 EVEX_W_0F11_P_3): New.
744 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
745 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
746 MOD_EVEX_0F11_PREFIX_3 table entries.
747 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
748 PREFIX_EVEX_0F11 table entries.
749 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
750 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
751 EVEX_W_0F11_P_3_M_{0,1} table entries.
752
219920a7
JB		 7532019-07-01 Jan Beulich <jbeulich@suse.com>
754
755 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
756 Delete.
757
e395f487
L		 7582019-06-27 H.J. Lu <hongjiu.lu@intel.com>
759
760 PR binutils/24719
761 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
762 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
763 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
764 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
765 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
766 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
767 EVEX_LEN_0F38C7_R_6_P_2_W_1.
768 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
769 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
770 PREFIX_EVEX_0F38C6_REG_6 entries.
771 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
772 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
773 EVEX_W_0F38C7_R_6_P_2 entries.
774 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
775 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
776 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
777 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
778 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
779 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
780 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
781
2b7bcc87
JB		 7822019-06-27 Jan Beulich <jbeulich@suse.com>
783
784 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
785 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
786 VEX_LEN_0F2D_P_3): Delete.
787 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
788 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
789 (prefix_table): ... here.
790
c1dc7af5
JB		 7912019-06-27 Jan Beulich <jbeulich@suse.com>
792
793 * i386-dis.c (Iq): Delete.
794 (Id): New.
795 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
796 TBM insns.
797 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
798 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
799 (OP_E_memory): Also honor needindex when deciding whether an
800 address size prefix needs printing.
801 (OP_I): Remove handling of q_mode. Add handling of d_mode.
802
d7560e2d
JW		 8032019-06-26 Jim Wilson <jimw@sifive.com>
804
805 PR binutils/24739
806 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
807 Set info->display_endian to info->endian_code.
808
2c703856
JB		 8092019-06-25 Jan Beulich <jbeulich@suse.com>
810
811 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
812 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
813 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
814 OPERAND_TYPE_ACC64 entries.
815 * i386-init.h: Re-generate.
816
54fbadc0
JB		 8172019-06-25 Jan Beulich <jbeulich@suse.com>
818
819 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
820 Delete.
821 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
822 of dqa_mode.
823 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
824 entries here.
825 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
826 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
827
a280ab8e
JB		 8282019-06-25 Jan Beulich <jbeulich@suse.com>
829
830 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
831 variables.
832
e1a1babd
JB		 8332019-06-25 Jan Beulich <jbeulich@suse.com>
834
835 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
836 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
837 movnti.
d7560e2d 838 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 839 * i386-tbl.h: Re-generate.
840
b8364fa7
JB		 8412019-06-25 Jan Beulich <jbeulich@suse.com>
842
843 * i386-opc.tbl (and): Mark Imm8S form for optimization.
844 * i386-tbl.h: Re-generate.
845
ad692897
L		 8462019-06-21 H.J. Lu <hongjiu.lu@intel.com>
847
848 * i386-dis-evex.h: Break into ...
849 * i386-dis-evex-len.h: New file.
850 * i386-dis-evex-mod.h: Likewise.
851 * i386-dis-evex-prefix.h: Likewise.
852 * i386-dis-evex-reg.h: Likewise.
853 * i386-dis-evex-w.h: Likewise.
854 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
855 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
856 i386-dis-evex-mod.h.
857
f0a6222e
L		 8582019-06-19 H.J. Lu <hongjiu.lu@intel.com>
859
860 PR binutils/24700
861 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
862 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
863 EVEX_W_0F385B_P_2.
864 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
865 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
866 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
867 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
868 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
869 EVEX_LEN_0F385B_P_2_W_1.
870 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
871 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
872 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
873 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
874 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
875 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
876 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
877 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
878 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
879 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
880
6e1c90b7
L		 8812019-06-17 H.J. Lu <hongjiu.lu@intel.com>
882
883 PR binutils/24691
884 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
885 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
886 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
887 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
888 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
889 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
890 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
891 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
892 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
893 EVEX_LEN_0F3A43_P_2_W_1.
894 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
895 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
896 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
897 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
898 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
899 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
900 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
901 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
902 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
903 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
904 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
905 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
906
bcc5a6eb
NC		 9072019-06-14 Nick Clifton <nickc@redhat.com>
908
909 * po/fr.po; Updated French translation.
910
e4c4ac46
SH		 9112019-06-13 Stafford Horne <shorne@gmail.com>
912
913 * or1k-asm.c: Regenerated.
914 * or1k-desc.c: Regenerated.
915 * or1k-desc.h: Regenerated.
916 * or1k-dis.c: Regenerated.
917 * or1k-ibld.c: Regenerated.
918 * or1k-opc.c: Regenerated.
919 * or1k-opc.h: Regenerated.
920 * or1k-opinst.c: Regenerated.
921
a0e44ef5
PB		 9222019-06-12 Peter Bergner <bergner@linux.ibm.com>
923
924 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
925
12efd68d
L		 9262019-06-05 H.J. Lu <hongjiu.lu@intel.com>
927
928 PR binutils/24633
929 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
930 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
931 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
932 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
933 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
934 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
935 EVEX_LEN_0F3A1B_P_2_W_1.
936 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
937 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
938 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
939 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
940 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
941 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
942 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
943 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
944
63c6fc6c
L		 9452019-06-04 H.J. Lu <hongjiu.lu@intel.com>
946
947 PR binutils/24626
948 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
949 EVEX.vvvv when disassembling VEX and EVEX instructions.
950 (OP_VEX): Set vex.register_specifier to 0 after readding
951 vex.register_specifier.
952 (OP_Vex_2src_1): Likewise.
953 (OP_Vex_2src_2): Likewise.
954 (OP_LWP_E): Likewise.
955 (OP_EX_Vex): Don't check vex.register_specifier.
956 (OP_XMM_Vex): Likewise.
957
9186c494
L		 9582019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
959 Lili Cui <lili.cui@intel.com>
960
961 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
962 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
963 instructions.
964 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
965 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
966 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
967 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
968 (i386_cpu_flags): Add cpuavx512_vp2intersect.
969 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
970 * i386-init.h: Regenerated.
971 * i386-tbl.h: Likewise.
972
5d79adc4
L		 9732019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
974 Lili Cui <lili.cui@intel.com>
975
976 * doc/c-i386.texi: Document enqcmd.
977 * testsuite/gas/i386/enqcmd-intel.d: New file.
978 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
979 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
980 * testsuite/gas/i386/enqcmd.d: Likewise.
981 * testsuite/gas/i386/enqcmd.s: Likewise.
982 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
983 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
984 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
985 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
986 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
987 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
988 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
989 and x86-64-enqcmd.
990
a9d96ab9
AH		 9912019-06-04 Alan Hayward <alan.hayward@arm.com>
992
993 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
994
4f6d070a
AM		 9952019-06-03 Alan Modra <amodra@gmail.com>
996
997 * ppc-dis.c (prefix_opcd_indices): Correct size.
998
a2f4b66c
L		 9992019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1000
1001 PR gas/24625
1002 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1003 Disp8ShiftVL.
1004 * i386-tbl.h: Regenerated.
1005
405b5bd8
AM		 10062019-05-24 Alan Modra <amodra@gmail.com>
1007
1008 * po/POTFILES.in: Regenerate.
1009
8acf1435
PB		 10102019-05-24 Peter Bergner <bergner@linux.ibm.com>
1011 Alan Modra <amodra@gmail.com>
1012
1013 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1014 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1015 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1016 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1017 XTOP>): Define and add entries.
1018 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1019 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1020 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1021 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1022
dd7efa79
PB		 10232019-05-24 Peter Bergner <bergner@linux.ibm.com>
1024 Alan Modra <amodra@gmail.com>
1025
1026 * ppc-dis.c (ppc_opts): Add "future" entry.
1027 (PREFIX_OPCD_SEGS): Define.
1028 (prefix_opcd_indices): New array.
1029 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1030 (lookup_prefix): New function.
1031 (print_insn_powerpc): Handle 64-bit prefix instructions.
1032 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1033 (PMRR, POWERXX): Define.
1034 (prefix_opcodes): New instruction table.
1035 (prefix_num_opcodes): New constant.
1036
79472b45
JM		 10372019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1038
1039 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1040 * configure: Regenerated.
1041 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1042 and cpu/bpf.opc.
1043 (HFILES): Add bpf-desc.h and bpf-opc.h.
1044 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1045 bpf-ibld.c and bpf-opc.c.
1046 (BPF_DEPS): Define.
1047 * Makefile.in: Regenerated.
1048 * disassemble.c (ARCH_bpf): Define.
1049 (disassembler): Add case for bfd_arch_bpf.
1050 (disassemble_init_for_target): Likewise.
1051 (enum epbf_isa_attr): Define.
1052 * disassemble.h: extern print_insn_bpf.
1053 * bpf-asm.c: Generated.
1054 * bpf-opc.h: Likewise.
1055 * bpf-opc.c: Likewise.
1056 * bpf-ibld.c: Likewise.
1057 * bpf-dis.c: Likewise.
1058 * bpf-desc.h: Likewise.
1059 * bpf-desc.c: Likewise.
1060
ba6cd17f
SD		 10612019-05-21 Sudakshina Das <sudi.das@arm.com>
1062
1063 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1064 and VMSR with the new operands.
1065
e39c1607
SD		 10662019-05-21 Sudakshina Das <sudi.das@arm.com>
1067
1068 * arm-dis.c (enum mve_instructions): New enum
1069 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1070 and cneg.
1071 (mve_opcodes): New instructions as above.
1072 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1073 csneg and csel.
1074 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1075
23d00a41
SD		 10762019-05-21 Sudakshina Das <sudi.das@arm.com>
1077
1078 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1079 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1080 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1081 uqshl, urshrl and urshr.
1082 (is_mve_okay_in_it): Add new instructions to TRUE list.
1083 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1084 (print_insn_mve): Updated to accept new %j,
1085 %<bitfield>m and %<bitfield>n patterns.
1086
cd4797ee
FS		 10872019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1088
1089 * mips-opc.c (mips_builtin_opcodes): Change source register
1090 constraint for DAUI.
1091
999b073b
NC		 10922019-05-20 Nick Clifton <nickc@redhat.com>
1093
1094 * po/fr.po: Updated French translation.
1095
14b456f2
AV		 10962019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1097 Michael Collison <michael.collison@arm.com>
1098
1099 * arm-dis.c (thumb32_opcodes): Add new instructions.
1100 (enum mve_instructions): Likewise.
1101 (enum mve_undefined): Add new reasons.
1102 (is_mve_encoding_conflict): Handle new instructions.
1103 (is_mve_undefined): Likewise.
1104 (is_mve_unpredictable): Likewise.
1105 (print_mve_undefined): Likewise.
1106 (print_mve_size): Likewise.
1107
f49bb598
AV		 11082019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1109 Michael Collison <michael.collison@arm.com>
1110
1111 * arm-dis.c (thumb32_opcodes): Add new instructions.
1112 (enum mve_instructions): Likewise.
1113 (is_mve_encoding_conflict): Handle new instructions.
1114 (is_mve_undefined): Likewise.
1115 (is_mve_unpredictable): Likewise.
1116 (print_mve_size): Likewise.
1117
56858bea
AV		 11182019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1119 Michael Collison <michael.collison@arm.com>
1120
1121 * arm-dis.c (thumb32_opcodes): Add new instructions.
1122 (enum mve_instructions): Likewise.
1123 (is_mve_encoding_conflict): Likewise.
1124 (is_mve_unpredictable): Likewise.
1125 (print_mve_size): Likewise.
1126
e523f101
AV		 11272019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1128 Michael Collison <michael.collison@arm.com>
1129
1130 * arm-dis.c (thumb32_opcodes): Add new instructions.
1131 (enum mve_instructions): Likewise.
1132 (is_mve_encoding_conflict): Handle new instructions.
1133 (is_mve_undefined): Likewise.
1134 (is_mve_unpredictable): Likewise.
1135 (print_mve_size): Likewise.
1136
66dcaa5d
AV		 11372019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1138 Michael Collison <michael.collison@arm.com>
1139
1140 * arm-dis.c (thumb32_opcodes): Add new instructions.
1141 (enum mve_instructions): Likewise.
1142 (is_mve_encoding_conflict): Handle new instructions.
1143 (is_mve_undefined): Likewise.
1144 (is_mve_unpredictable): Likewise.
1145 (print_mve_size): Likewise.
1146 (print_insn_mve): Likewise.
1147
d052b9b7
AV		 11482019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1149 Michael Collison <michael.collison@arm.com>
1150
1151 * arm-dis.c (thumb32_opcodes): Add new instructions.
1152 (print_insn_thumb32): Handle new instructions.
1153
ed63aa17
AV		 11542019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1155 Michael Collison <michael.collison@arm.com>
1156
1157 * arm-dis.c (enum mve_instructions): Add new instructions.
1158 (enum mve_undefined): Add new reasons.
1159 (is_mve_encoding_conflict): Handle new instructions.
1160 (is_mve_undefined): Likewise.
1161 (is_mve_unpredictable): Likewise.
1162 (print_mve_undefined): Likewise.
1163 (print_mve_size): Likewise.
1164 (print_mve_shift_n): Likewise.
1165 (print_insn_mve): Likewise.
1166
897b9bbc
AV		 11672019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1168 Michael Collison <michael.collison@arm.com>
1169
1170 * arm-dis.c (enum mve_instructions): Add new instructions.
1171 (is_mve_encoding_conflict): Handle new instructions.
1172 (is_mve_unpredictable): Likewise.
1173 (print_mve_rotate): Likewise.
1174 (print_mve_size): Likewise.
1175 (print_insn_mve): Likewise.
1176
1c8f2df8
AV		 11772019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1178 Michael Collison <michael.collison@arm.com>
1179
1180 * arm-dis.c (enum mve_instructions): Add new instructions.
1181 (is_mve_encoding_conflict): Handle new instructions.
1182 (is_mve_unpredictable): Likewise.
1183 (print_mve_size): Likewise.
1184 (print_insn_mve): Likewise.
1185
d3b63143
AV		 11862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1187 Michael Collison <michael.collison@arm.com>
1188
1189 * arm-dis.c (enum mve_instructions): Add new instructions.
1190 (enum mve_undefined): Add new reasons.
1191 (is_mve_encoding_conflict): Handle new instructions.
1192 (is_mve_undefined): Likewise.
1193 (is_mve_unpredictable): Likewise.
1194 (print_mve_undefined): Likewise.
1195 (print_mve_size): Likewise.
1196 (print_insn_mve): Likewise.
1197
14925797
AV		 11982019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1199 Michael Collison <michael.collison@arm.com>
1200
1201 * arm-dis.c (enum mve_instructions): Add new instructions.
1202 (is_mve_encoding_conflict): Handle new instructions.
1203 (is_mve_undefined): Likewise.
1204 (is_mve_unpredictable): Likewise.
1205 (print_mve_size): Likewise.
1206 (print_insn_mve): Likewise.
1207
c507f10b
AV		 12082019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1209 Michael Collison <michael.collison@arm.com>
1210
1211 * arm-dis.c (enum mve_instructions): Add new instructions.
1212 (enum mve_unpredictable): Add new reasons.
1213 (enum mve_undefined): Likewise.
1214 (is_mve_okay_in_it): Handle new isntructions.
1215 (is_mve_encoding_conflict): Likewise.
1216 (is_mve_undefined): Likewise.
1217 (is_mve_unpredictable): Likewise.
1218 (print_mve_vmov_index): Likewise.
1219 (print_simd_imm8): Likewise.
1220 (print_mve_undefined): Likewise.
1221 (print_mve_unpredictable): Likewise.
1222 (print_mve_size): Likewise.
1223 (print_insn_mve): Likewise.
1224
bf0b396d
AV		 12252019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1226 Michael Collison <michael.collison@arm.com>
1227
1228 * arm-dis.c (enum mve_instructions): Add new instructions.
1229 (enum mve_unpredictable): Add new reasons.
1230 (enum mve_undefined): Likewise.
1231 (is_mve_encoding_conflict): Handle new instructions.
1232 (is_mve_undefined): Likewise.
1233 (is_mve_unpredictable): Likewise.
1234 (print_mve_undefined): Likewise.
1235 (print_mve_unpredictable): Likewise.
1236 (print_mve_rounding_mode): Likewise.
1237 (print_mve_vcvt_size): Likewise.
1238 (print_mve_size): Likewise.
1239 (print_insn_mve): Likewise.
1240
ef1576a1
AV		 12412019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1242 Michael Collison <michael.collison@arm.com>
1243
1244 * arm-dis.c (enum mve_instructions): Add new instructions.
1245 (enum mve_unpredictable): Add new reasons.
1246 (enum mve_undefined): Likewise.
1247 (is_mve_undefined): Handle new instructions.
1248 (is_mve_unpredictable): Likewise.
1249 (print_mve_undefined): Likewise.
1250 (print_mve_unpredictable): Likewise.
1251 (print_mve_size): Likewise.
1252 (print_insn_mve): Likewise.
1253
aef6d006
AV		 12542019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1255 Michael Collison <michael.collison@arm.com>
1256
1257 * arm-dis.c (enum mve_instructions): Add new instructions.
1258 (enum mve_undefined): Add new reasons.
1259 (insns): Add new instructions.
1260 (is_mve_encoding_conflict):
1261 (print_mve_vld_str_addr): New print function.
1262 (is_mve_undefined): Handle new instructions.
1263 (is_mve_unpredictable): Likewise.
1264 (print_mve_undefined): Likewise.
1265 (print_mve_size): Likewise.
1266 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1267 (print_insn_mve): Handle new operands.
1268
04d54ace
AV		 12692019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1270 Michael Collison <michael.collison@arm.com>
1271
1272 * arm-dis.c (enum mve_instructions): Add new instructions.
1273 (enum mve_unpredictable): Add new reasons.
1274 (is_mve_encoding_conflict): Handle new instructions.
1275 (is_mve_unpredictable): Likewise.
1276 (mve_opcodes): Add new instructions.
1277 (print_mve_unpredictable): Handle new reasons.
1278 (print_mve_register_blocks): New print function.
1279 (print_mve_size): Handle new instructions.
1280 (print_insn_mve): Likewise.
1281
9743db03
AV		 12822019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1283 Michael Collison <michael.collison@arm.com>
1284
1285 * arm-dis.c (enum mve_instructions): Add new instructions.
1286 (enum mve_unpredictable): Add new reasons.
1287 (enum mve_undefined): Likewise.
1288 (is_mve_encoding_conflict): Handle new instructions.
1289 (is_mve_undefined): Likewise.
1290 (is_mve_unpredictable): Likewise.
1291 (coprocessor_opcodes): Move NEON VDUP from here...
1292 (neon_opcodes): ... to here.
1293 (mve_opcodes): Add new instructions.
1294 (print_mve_undefined): Handle new reasons.
1295 (print_mve_unpredictable): Likewise.
1296 (print_mve_size): Handle new instructions.
1297 (print_insn_neon): Handle vdup.
1298 (print_insn_mve): Handle new operands.
1299
143275ea
AV		 13002019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1301 Michael Collison <michael.collison@arm.com>
1302
1303 * arm-dis.c (enum mve_instructions): Add new instructions.
1304 (enum mve_unpredictable): Add new values.
1305 (mve_opcodes): Add new instructions.
1306 (vec_condnames): New array with vector conditions.
1307 (mve_predicatenames): New array with predicate suffixes.
1308 (mve_vec_sizename): New array with vector sizes.
1309 (enum vpt_pred_state): New enum with vector predication states.
1310 (struct vpt_block): New struct type for vpt blocks.
1311 (vpt_block_state): Global struct to keep track of state.
1312 (mve_extract_pred_mask): New helper function.
1313 (num_instructions_vpt_block): Likewise.
1314 (mark_outside_vpt_block): Likewise.
1315 (mark_inside_vpt_block): Likewise.
1316 (invert_next_predicate_state): Likewise.
1317 (update_next_predicate_state): Likewise.
1318 (update_vpt_block_state): Likewise.
1319 (is_vpt_instruction): Likewise.
1320 (is_mve_encoding_conflict): Add entries for new instructions.
1321 (is_mve_unpredictable): Likewise.
1322 (print_mve_unpredictable): Handle new cases.
1323 (print_instruction_predicate): Likewise.
1324 (print_mve_size): New function.
1325 (print_vec_condition): New function.
1326 (print_insn_mve): Handle vpt blocks and new print operands.
1327
f08d8ce3
AV		 13282019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1329
1330 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1331 8, 14 and 15 for Armv8.1-M Mainline.
1332
73cd51e5
AV		 13332019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1334 Michael Collison <michael.collison@arm.com>
1335
1336 * arm-dis.c (enum mve_instructions): New enum.
1337 (enum mve_unpredictable): Likewise.
1338 (enum mve_undefined): Likewise.
1339 (struct mopcode32): New struct.
1340 (is_mve_okay_in_it): New function.
1341 (is_mve_architecture): Likewise.
1342 (arm_decode_field): Likewise.
1343 (arm_decode_field_multiple): Likewise.
1344 (is_mve_encoding_conflict): Likewise.
1345 (is_mve_undefined): Likewise.
1346 (is_mve_unpredictable): Likewise.
1347 (print_mve_undefined): Likewise.
1348 (print_mve_unpredictable): Likewise.
1349 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1350 (print_insn_mve): New function.
1351 (print_insn_thumb32): Handle MVE architecture.
1352 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1353
3076e594
NC		 13542019-05-10 Nick Clifton <nickc@redhat.com>
1355
1356 PR 24538
1357 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1358 end of the table prematurely.
1359
387e7624
FS		 13602019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1361
1362 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1363 macros for R6.
1364
0067be51
AM		 13652019-05-11 Alan Modra <amodra@gmail.com>
1366
1367 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1368 when -Mraw is in effect.
1369
42e6288f
MM		 13702019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1371
1372 * aarch64-dis-2.c: Regenerate.
1373 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1374 (OP_SVE_BBB): New variant set.
1375 (OP_SVE_DDDD): New variant set.
1376 (OP_SVE_HHH): New variant set.
1377 (OP_SVE_HHHU): New variant set.
1378 (OP_SVE_SSS): New variant set.
1379 (OP_SVE_SSSU): New variant set.
1380 (OP_SVE_SHH): New variant set.
1381 (OP_SVE_SBBU): New variant set.
1382 (OP_SVE_DSS): New variant set.
1383 (OP_SVE_DHHU): New variant set.
1384 (OP_SVE_VMV_HSD_BHS): New variant set.
1385 (OP_SVE_VVU_HSD_BHS): New variant set.
1386 (OP_SVE_VVVU_SD_BH): New variant set.
1387 (OP_SVE_VVVU_BHSD): New variant set.
1388 (OP_SVE_VVV_QHD_DBS): New variant set.
1389 (OP_SVE_VVV_HSD_BHS): New variant set.
1390 (OP_SVE_VVV_HSD_BHS2): New variant set.
1391 (OP_SVE_VVV_BHS_HSD): New variant set.
1392 (OP_SVE_VV_BHS_HSD): New variant set.
1393 (OP_SVE_VVV_SD): New variant set.
1394 (OP_SVE_VVU_BHS_HSD): New variant set.
1395 (OP_SVE_VZVV_SD): New variant set.
1396 (OP_SVE_VZVV_BH): New variant set.
1397 (OP_SVE_VZV_SD): New variant set.
1398 (aarch64_opcode_table): Add sve2 instructions.
1399
28ed815a
MM		 14002019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1401
1402 * aarch64-asm-2.c: Regenerated.
1403 * aarch64-dis-2.c: Regenerated.
1404 * aarch64-opc-2.c: Regenerated.
1405 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1406 for SVE_SHLIMM_UNPRED_22.
1407 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1408 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1409 operand.
1410
fd1dc4a0
MM		 14112019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1412
1413 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1414 sve_size_tsz_bhs iclass encode.
1415 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1416 sve_size_tsz_bhs iclass decode.
1417
31e36ab3
MM		 14182019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1419
1420 * aarch64-asm-2.c: Regenerated.
1421 * aarch64-dis-2.c: Regenerated.
1422 * aarch64-opc-2.c: Regenerated.
1423 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1424 for SVE_Zm4_11_INDEX.
1425 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1426 (fields): Handle SVE_i2h field.
1427 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1428 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1429
1be5f94f
MM		 14302019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1431
1432 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1433 sve_shift_tsz_bhsd iclass encode.
1434 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1435 sve_shift_tsz_bhsd iclass decode.
1436
3c17238b
MM		 14372019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1438
1439 * aarch64-asm-2.c: Regenerated.
1440 * aarch64-dis-2.c: Regenerated.
1441 * aarch64-opc-2.c: Regenerated.
1442 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1443 (aarch64_encode_variant_using_iclass): Handle
1444 sve_shift_tsz_hsd iclass encode.
1445 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1446 sve_shift_tsz_hsd iclass decode.
1447 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1448 for SVE_SHRIMM_UNPRED_22.
1449 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1450 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1451 operand.
1452
cd50a87a
MM		 14532019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1454
1455 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1456 sve_size_013 iclass encode.
1457 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1458 sve_size_013 iclass decode.
1459
3c705960
MM		 14602019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1461
1462 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1463 sve_size_bh iclass encode.
1464 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1465 sve_size_bh iclass decode.
1466
0a57e14f
MM		 14672019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1468
1469 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1470 sve_size_sd2 iclass encode.
1471 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1472 sve_size_sd2 iclass decode.
1473 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1474 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1475
c469c864
MM		 14762019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1477
1478 * aarch64-asm-2.c: Regenerated.
1479 * aarch64-dis-2.c: Regenerated.
1480 * aarch64-opc-2.c: Regenerated.
1481 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1482 for SVE_ADDR_ZX.
1483 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1484 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1485
116adc27
MM		 14862019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1487
1488 * aarch64-asm-2.c: Regenerated.
1489 * aarch64-dis-2.c: Regenerated.
1490 * aarch64-opc-2.c: Regenerated.
1491 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1492 for SVE_Zm3_11_INDEX.
1493 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1494 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1495 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1496 fields.
1497 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1498
3bd82c86
MM		 14992019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1500
1501 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1502 sve_size_hsd2 iclass encode.
1503 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1504 sve_size_hsd2 iclass decode.
1505 * aarch64-opc.c (fields): Handle SVE_size field.
1506 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1507
adccc507
MM		 15082019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1509
1510 * aarch64-asm-2.c: Regenerated.
1511 * aarch64-dis-2.c: Regenerated.
1512 * aarch64-opc-2.c: Regenerated.
1513 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1514 for SVE_IMM_ROT3.
1515 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1516 (fields): Handle SVE_rot3 field.
1517 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1518 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1519
5cd99750
MM		 15202019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1521
1522 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1523 instructions.
1524
7ce2460a
MM		 15252019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1526
1527 * aarch64-tbl.h
1528 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1529 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1530 aarch64_feature_sve2bitperm): New feature sets.
1531 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1532 for feature set addresses.
1533 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1534 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1535
41cee089
FS		 15362019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1537 Faraz Shahbazker <fshahbazker@wavecomp.com>
1538
1539 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1540 argument and set ASE_EVA_R6 appropriately.
1541 (set_default_mips_dis_options): Pass ISA to above.
1542 (parse_mips_dis_option): Likewise.
1543 * mips-opc.c (EVAR6): New macro.
1544 (mips_builtin_opcodes): Add llwpe, scwpe.
1545
b83b4b13
SD		 15462019-05-01 Sudakshina Das <sudi.das@arm.com>
1547
1548 * aarch64-asm-2.c: Regenerated.
1549 * aarch64-dis-2.c: Regenerated.
1550 * aarch64-opc-2.c: Regenerated.
1551 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1552 AARCH64_OPND_TME_UIMM16.
1553 (aarch64_print_operand): Likewise.
1554 * aarch64-tbl.h (QL_IMM_NIL): New.
1555 (TME): New.
1556 (_TME_INSN): New.
1557 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1558
4a90ce95
JD		 15592019-04-29 John Darrington <john@darrington.wattle.id.au>
1560
1561 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1562
a45328b9
AB		 15632019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1564 Faraz Shahbazker <fshahbazker@wavecomp.com>
1565
1566 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1567
d10be0cb
JD		 15682019-04-24 John Darrington <john@darrington.wattle.id.au>
1569
1570 * s12z-opc.h: Add extern "C" bracketing to help
1571 users who wish to use this interface in c++ code.
1572
a679f24e
JD		 15732019-04-24 John Darrington <john@darrington.wattle.id.au>
1574
1575 * s12z-opc.c (bm_decode): Handle bit map operations with the
1576 "reserved0" mode.
1577
32c36c3c
AV		 15782019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1579
1580 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1581 specifier. Add entries for VLDR and VSTR of system registers.
1582 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1583 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1584 of %J and %K format specifier.
1585
efd6b359
AV		 15862019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1587
1588 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1589 Add new entries for VSCCLRM instruction.
1590 (print_insn_coprocessor): Handle new %C format control code.
1591
6b0dd094
AV		 15922019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1593
1594 * arm-dis.c (enum isa): New enum.
1595 (struct sopcode32): New structure.
1596 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1597 set isa field of all current entries to ANY.
1598 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1599 Only match an entry if its isa field allows the current mode.
1600
4b5a202f
AV		 16012019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1602
1603 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1604 CLRM.
1605 (print_insn_thumb32): Add logic to print %n CLRM register list.
1606
60f993ce
AV		 16072019-04-15 Sudakshina Das <sudi.das@arm.com>
1608
1609 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1610 and %Q patterns.
1611
f6b2b12d
AV		 16122019-04-15 Sudakshina Das <sudi.das@arm.com>
1613
1614 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1615 (print_insn_thumb32): Edit the switch case for %Z.
1616
1889da70
AV		 16172019-04-15 Sudakshina Das <sudi.das@arm.com>
1618
1619 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1620
65d1bc05
AV		 16212019-04-15 Sudakshina Das <sudi.das@arm.com>
1622
1623 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1624
1caf72a5
AV		 16252019-04-15 Sudakshina Das <sudi.das@arm.com>
1626
1627 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1628
f1c7f421
AV		 16292019-04-15 Sudakshina Das <sudi.das@arm.com>
1630
1631 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1632 Arm register with r13 and r15 unpredictable.
1633 (thumb32_opcodes): New instructions for bfx and bflx.
1634
4389b29a
AV		 16352019-04-15 Sudakshina Das <sudi.das@arm.com>
1636
1637 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1638
e5d6e09e
AV		 16392019-04-15 Sudakshina Das <sudi.das@arm.com>
1640
1641 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1642
e12437dc
AV		 16432019-04-15 Sudakshina Das <sudi.das@arm.com>
1644
1645 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1646
031254f2
AV		 16472019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1648
1649 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1650
e5a557ac
JD		 16512019-04-12 John Darrington <john@darrington.wattle.id.au>
1652
1653 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1654 "optr". ("operator" is a reserved word in c++).
1655
bd7ceb8d
SD		 16562019-04-11 Sudakshina Das <sudi.das@arm.com>
1657
1658 * aarch64-opc.c (aarch64_print_operand): Add case for
1659 AARCH64_OPND_Rt_SP.
1660 (verify_constraints): Likewise.
1661 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1662 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1663 to accept Rt|SP as first operand.
1664 (AARCH64_OPERANDS): Add new Rt_SP.
1665 * aarch64-asm-2.c: Regenerated.
1666 * aarch64-dis-2.c: Regenerated.
1667 * aarch64-opc-2.c: Regenerated.
1668
e54010f1
SD		 16692019-04-11 Sudakshina Das <sudi.das@arm.com>
1670
1671 * aarch64-asm-2.c: Regenerated.
1672 * aarch64-dis-2.c: Likewise.
1673 * aarch64-opc-2.c: Likewise.
1674 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1675
7e96e219
RS		 16762019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1677
1678 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1679
6f2791d5
L		 16802019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1681
1682 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1683 * i386-init.h: Regenerated.
1684
e392bad3
AM		 16852019-04-07 Alan Modra <amodra@gmail.com>
1686
1687 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1688 op_separator to control printing of spaces, comma and parens
1689 rather than need_comma, need_paren and spaces vars.
1690
dffaa15c
AM		 16912019-04-07 Alan Modra <amodra@gmail.com>
1692
1693 PR 24421
1694 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1695 (print_insn_neon, print_insn_arm): Likewise.
1696
d6aab7a1
XG		 16972019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1698
1699 * i386-dis-evex.h (evex_table): Updated to support BF16
1700 instructions.
1701 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1702 and EVEX_W_0F3872_P_3.
1703 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1704 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1705 * i386-opc.h (enum): Add CpuAVX512_BF16.
1706 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1707 * i386-opc.tbl: Add AVX512 BF16 instructions.
1708 * i386-init.h: Regenerated.
1709 * i386-tbl.h: Likewise.
1710
66e85460
AM		 17112019-04-05 Alan Modra <amodra@gmail.com>
1712
1713 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1714 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1715 to favour printing of "-" branch hint when using the "y" bit.
1716 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1717
c2b1c275
AM		 17182019-04-05 Alan Modra <amodra@gmail.com>
1719
1720 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1721 opcode until first operand is output.
1722
aae9718e
PB		 17232019-04-04 Peter Bergner <bergner@linux.ibm.com>
1724
1725 PR gas/24349
1726 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1727 (valid_bo_post_v2): Add support for 'at' branch hints.
1728 (insert_bo): Only error on branch on ctr.
1729 (get_bo_hint_mask): New function.
1730 (insert_boe): Add new 'branch_taken' formal argument. Add support
1731 for inserting 'at' branch hints.
1732 (extract_boe): Add new 'branch_taken' formal argument. Add support
1733 for extracting 'at' branch hints.
1734 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1735 (BOE): Delete operand.
1736 (BOM, BOP): New operands.
1737 (RM): Update value.
1738 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1739 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1740 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1741 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1742 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1743 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1744 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1745 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1746 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1747 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1748 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1749 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1750 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1751 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1752 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1753 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1754 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1755 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1756 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1757 bttarl+>: New extended mnemonics.
1758
96a86c01
AM		 17592019-03-28 Alan Modra <amodra@gmail.com>
1760
1761 PR 24390
1762 * ppc-opc.c (BTF): Define.
1763 (powerpc_opcodes): Use for mtfsb*.
1764 * ppc-dis.c (print_insn_powerpc): Print fields with both
1765 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1766
796d6298
TC		 17672019-03-25 Tamar Christina <tamar.christina@arm.com>
1768
1769 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1770 (mapping_symbol_for_insn): Implement new algorithm.
1771 (print_insn): Remove duplicate code.
1772
60df3720
TC		 17732019-03-25 Tamar Christina <tamar.christina@arm.com>
1774
1775 * aarch64-dis.c (print_insn_aarch64):
1776 Implement override.
1777
51457761
TC		 17782019-03-25 Tamar Christina <tamar.christina@arm.com>
1779
1780 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1781 order.
1782
53b2f36b
TC		 17832019-03-25 Tamar Christina <tamar.christina@arm.com>
1784
1785 * aarch64-dis.c (last_stop_offset): New.
1786 (print_insn_aarch64): Use stop_offset.
1787
89199bb5
L		 17882019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1789
1790 PR gas/24359
1791 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1792 CPU_ANY_AVX2_FLAGS.
1793 * i386-init.h: Regenerated.
1794
97ed31ae
L		 17952019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1796
1797 PR gas/24348
1798 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1799 vmovdqu16, vmovdqu32 and vmovdqu64.
1800 * i386-tbl.h: Regenerated.
1801
0919bfe9
AK		 18022019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1803
1804 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1805 from vstrszb, vstrszh, and vstrszf.
1806
18072019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1808
1809 * s390-opc.txt: Add instruction descriptions.
1810
21820ebe
JW		 18112019-02-08 Jim Wilson <jimw@sifive.com>
1812
1813 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1814 <bne>: Likewise.
1815
f7dd2fb2
TC		 18162019-02-07 Tamar Christina <tamar.christina@arm.com>
1817
1818 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1819
6456d318
TC		 18202019-02-07 Tamar Christina <tamar.christina@arm.com>
1821
1822 PR binutils/23212
1823 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1824 * aarch64-opc.c (verify_elem_sd): New.
1825 (fields): Add FLD_sz entr.
1826 * aarch64-tbl.h (_SIMD_INSN): New.
1827 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1828 fmulx scalar and vector by element isns.
1829
4a83b610
NC		 18302019-02-07 Nick Clifton <nickc@redhat.com>
1831
1832 * po/sv.po: Updated Swedish translation.
1833
fc60b8c8
AK		 18342019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1835
1836 * s390-mkopc.c (main): Accept arch13 as cpu string.
1837 * s390-opc.c: Add new instruction formats and instruction opcode
1838 masks.
1839 * s390-opc.txt: Add new arch13 instructions.
1840
e10620d3
TC		 18412019-01-25 Sudakshina Das <sudi.das@arm.com>
1842
1843 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1844 (aarch64_opcode): Change encoding for stg, stzg
1845 st2g and st2zg.
1846 * aarch64-asm-2.c: Regenerated.
1847 * aarch64-dis-2.c: Regenerated.
1848 * aarch64-opc-2.c: Regenerated.
1849
20a4ca55
SD		 18502019-01-25 Sudakshina Das <sudi.das@arm.com>
1851
1852 * aarch64-asm-2.c: Regenerated.
1853 * aarch64-dis-2.c: Likewise.
1854 * aarch64-opc-2.c: Likewise.
1855 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1856
550fd7bf
SD		 18572019-01-25 Sudakshina Das <sudi.das@arm.com>
1858 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1859
1860 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1861 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1862 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1863 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1864 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1865 case for ldstgv_indexed.
1866 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1867 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1868 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1869 * aarch64-asm-2.c: Regenerated.
1870 * aarch64-dis-2.c: Regenerated.
1871 * aarch64-opc-2.c: Regenerated.
1872
d9938630
NC		 18732019-01-23 Nick Clifton <nickc@redhat.com>
1874
1875 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1876
375cd423
NC		 18772019-01-21 Nick Clifton <nickc@redhat.com>
1878
1879 * po/de.po: Updated German translation.
1880 * po/uk.po: Updated Ukranian translation.
1881
57299f48
CX		 18822019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1883 * mips-dis.c (mips_arch_choices): Fix typo in
1884 gs464, gs464e and gs264e descriptors.
1885
f48dfe41
NC		 18862019-01-19 Nick Clifton <nickc@redhat.com>
1887
1888 * configure: Regenerate.
1889 * po/opcodes.pot: Regenerate.
1890
f974f26c
NC		 18912018-06-24 Nick Clifton <nickc@redhat.com>
1892
1893 2.32 branch created.
1894
39f286cd
JD		 18952019-01-09 John Darrington <john@darrington.wattle.id.au>
1896
448b8ca8
JD		 1897 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1898 if it is null.
1899 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1900 zero.
1901
3107326d
AP		 19022019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1903
1904 * configure: Regenerate.
1905
7e9ca91e
AM		 19062019-01-07 Alan Modra <amodra@gmail.com>
1907
1908 * configure: Regenerate.
1909 * po/POTFILES.in: Regenerate.
1910
ef1ad42b
JD		 19112019-01-03 John Darrington <john@darrington.wattle.id.au>
1912
1913 * s12z-opc.c: New file.
1914 * s12z-opc.h: New file.
1915 * s12z-dis.c: Removed all code not directly related to display
1916 of instructions. Used the interface provided by the new files
1917 instead.
1918 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1919 * Makefile.in: Regenerate.
ef1ad42b 1920 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1921 * configure: Regenerate.
ef1ad42b 1922
82704155
AM		 19232019-01-01 Alan Modra <amodra@gmail.com>
1924
1925 Update year range in copyright notice of all files.
1926
d5c04e1b 1927For older changes see ChangeLog-2018
3499769a 1928\f
d5c04e1b 1929Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1930
1931Copying and distribution of this file, with or without modification,
1932are permitted in any medium without royalty provided the copyright
1933notice and this notice are preserved.
1934
1935Local Variables:
1936mode: change-log
1937left-margin: 8
1938fill-column: 74
1939version-control: never
1940End:
GDB Binutils - Deliverables
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