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ubsan: crx: left shift cannot be represented in type 'int'
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
36bd8ea7
AM		 12019-12-16 Alan Modra <amodra@gmail.com>
2
3 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
4 (get_number_of_operands, getargtype, getbits, getregname),
5 (getcopregname, getprocregname, gettrapstring, getcinvstring),
6 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
7 (powerof2, match_opcode, make_instruction, print_arguments),
8 (print_arg): Delete forward declarations, moving static to..
9 (getregname, getcopregname, getregliststring): ..these definitions.
10 (build_mask): Return unsigned int mask.
11 (match_opcode): Use unsigned int vars.
12
cedfc774
AM		 132019-12-16 Alan Modra <amodra@gmail.com>
14
15 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
16
4bdb25fe
AM		 172019-12-16 Alan Modra <amodra@gmail.com>
18
19 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
20 (struct objdump_disasm_info): Delete.
21 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
22 N32_IMMS to unsigned before shifting left.
23
cf950fd4
AM		 242019-12-16 Alan Modra <amodra@gmail.com>
25
26 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
27 (print_insn_moxie): Remove unnecessary cast.
28
967354c3
AM		 292019-12-12 Alan Modra <amodra@gmail.com>
30
31 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
32 mask.
33
1d61b032
AM		 342019-12-11 Alan Modra <amodra@gmail.com>
35
36 * arc-dis.c (BITS): Don't truncate high bits with shifts.
37 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
38 * tic54x-dis.c (print_instruction): Likewise.
39 * tilegx-opc.c (parse_insn_tilegx): Likewise.
40 * tilepro-opc.c (parse_insn_tilepro): Likewise.
41 * visium-dis.c (disassem_class0): Likewise.
42 * pdp11-dis.c (sign_extend): Likewise.
43 (SIGN_BITS): Delete.
44 * epiphany-ibld.c: Regenerate.
45 * lm32-ibld.c: Regenerate.
46 * m32c-ibld.c: Regenerate.
47
5afa80e9
AM		 482019-12-11 Alan Modra <amodra@gmail.com>
49
50 * ns32k-dis.c (sign_extend): Correct last patch.
51
5c05618a
AM		 522019-12-11 Alan Modra <amodra@gmail.com>
53
54 * vax-dis.c (NEXTLONG): Avoid signed overflow.
55
2a81ccbb
AM		 562019-12-11 Alan Modra <amodra@gmail.com>
57
58 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
59 sign extend using shifts.
60
b84f6152
AM		 612019-12-11 Alan Modra <amodra@gmail.com>
62
63 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
64
66152f16
AM		 652019-12-11 Alan Modra <amodra@gmail.com>
66
67 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
68 on NULL registertable entry.
69 (tic4x_hash_opcode): Use unsigned arithmetic.
70
205c426a
AM		 712019-12-11 Alan Modra <amodra@gmail.com>
72
73 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
74
fb4cb4e2
AM		 752019-12-11 Alan Modra <amodra@gmail.com>
76
77 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
78 (bit_extract_simple, sign_extend): Likewise.
79
96f1f604
AM		 802019-12-11 Alan Modra <amodra@gmail.com>
81
82 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
83
8c9b4171
AM		 842019-12-11 Alan Modra <amodra@gmail.com>
85
86 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
87
334175b6
AM		 882019-12-11 Alan Modra <amodra@gmail.com>
89
90 * m68k-dis.c (COERCE32): Cast value first.
91 (NEXTLONG, NEXTULONG): Avoid signed overflow.
92
f8a87c78
AM		 932019-12-11 Alan Modra <amodra@gmail.com>
94
95 * h8300-dis.c (extract_immediate): Avoid signed overflow.
96 (bfd_h8_disassemble): Likewise.
97
159653d8
AM		 982019-12-11 Alan Modra <amodra@gmail.com>
99
100 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
101 past end of operands array.
102
d93bba9e
AM		 1032019-12-11 Alan Modra <amodra@gmail.com>
104
105 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
106 overflow when collecting bytes of a number.
107
c202f69e
AM		 1082019-12-11 Alan Modra <amodra@gmail.com>
109
110 * cris-dis.c (print_with_operands): Avoid signed integer
111 overflow when collecting bytes of a 32-bit integer.
112
0ef562a4
AM		 1132019-12-11 Alan Modra <amodra@gmail.com>
114
115 * cr16-dis.c (EXTRACT, SBM): Rewrite.
116 (cr16_match_opcode): Delete duplicate bcond test.
117
2fd2b153
AM		 1182019-12-11 Alan Modra <amodra@gmail.com>
119
120 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
121 (SIGNBIT): New.
122 (MASKBITS, SIGNEXTEND): Rewrite.
123 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
124 unsigned arithmetic, instead assign result of SIGNEXTEND back
125 to x.
126 (fmtconst_val): Use 1u in shift expression.
127
a11db3e9
AM		 1282019-12-11 Alan Modra <amodra@gmail.com>
129
130 * arc-dis.c (find_format_from_table): Use ull constant when
131 shifting by up to 32.
132
9d48687b
AM		 1332019-12-11 Alan Modra <amodra@gmail.com>
134
135 PR 25270
136 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
137 false when field is zero for sve_size_tsz_bhs.
138
b8e61daa
AM		 1392019-12-11 Alan Modra <amodra@gmail.com>
140
141 * epiphany-ibld.c: Regenerate.
142
20135676
AM		 1432019-12-10 Alan Modra <amodra@gmail.com>
144
145 PR 24960
146 * disassemble.c (disassemble_free_target): New function.
147
103ebbc3
AM		 1482019-12-10 Alan Modra <amodra@gmail.com>
149
150 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
151 * disassemble.c (disassemble_init_for_target): Likewise.
152 * bpf-dis.c: Regenerate.
153 * epiphany-dis.c: Regenerate.
154 * fr30-dis.c: Regenerate.
155 * frv-dis.c: Regenerate.
156 * ip2k-dis.c: Regenerate.
157 * iq2000-dis.c: Regenerate.
158 * lm32-dis.c: Regenerate.
159 * m32c-dis.c: Regenerate.
160 * m32r-dis.c: Regenerate.
161 * mep-dis.c: Regenerate.
162 * mt-dis.c: Regenerate.
163 * or1k-dis.c: Regenerate.
164 * xc16x-dis.c: Regenerate.
165 * xstormy16-dis.c: Regenerate.
166
6f0e0752
AM		 1672019-12-10 Alan Modra <amodra@gmail.com>
168
169 * ppc-dis.c (private): Delete variable.
170 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
171 (powerpc_init_dialect): Don't use global private.
172
e7c22a69
AM		 1732019-12-10 Alan Modra <amodra@gmail.com>
174
175 * s12z-opc.c: Formatting.
176
0a6aef6b
AM		 1772019-12-08 Alan Modra <amodra@gmail.com>
178
179 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
180 registers.
181
2dc4b12f
JB		 1822019-12-05 Jan Beulich <jbeulich@suse.com>
183
184 * aarch64-tbl.h (aarch64_feature_crypto,
185 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
186 CRYPTO_V8_2_INSN): Delete.
187
378fd436
AM		 1882019-12-05 Alan Modra <amodra@gmail.com>
189
190 PR 25249
191 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
192 (struct string_buf): New.
193 (strbuf): New function.
194 (get_field): Use strbuf rather than strdup of local temp.
195 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
196 (get_field_rfsl, get_field_imm15): Likewise.
197 (get_field_rd, get_field_r1, get_field_r2): Update macros.
198 (get_field_special): Likewise. Don't strcpy spr. Formatting.
199 (print_insn_microblaze): Formatting. Init and pass string_buf to
200 get_field functions.
201
0ba59a29
JB		 2022019-12-04 Jan Beulich <jbeulich@suse.com>
203
204 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
205 * i386-tbl.h: Re-generate.
206
77ad8092
JB		 2072019-12-04 Jan Beulich <jbeulich@suse.com>
208
209 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
210
3036c899
JB		 2112019-12-04 Jan Beulich <jbeulich@suse.com>
212
213 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
214 forms.
215 (xbegin): Drop DefaultSize.
216 * i386-tbl.h: Re-generate.
217
8b301fbb
MI		 2182019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
219
220 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
221 Change the coproc CRC conditions to use the extension
222 feature set, second word, base on ARM_EXT2_CRC.
223
6aa385b9
JB		 2242019-11-14 Jan Beulich <jbeulich@suse.com>
225
226 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
227 * i386-tbl.h: Re-generate.
228
0cfa3eb3
JB		 2292019-11-14 Jan Beulich <jbeulich@suse.com>
230
231 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
232 JumpInterSegment, and JumpAbsolute entries.
233 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
234 JUMP_ABSOLUTE): Define.
235 (struct i386_opcode_modifier): Extend jump field to 3 bits.
236 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
237 fields.
238 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
239 JumpInterSegment): Define.
240 * i386-tbl.h: Re-generate.
241
6f2f06be
JB		 2422019-11-14 Jan Beulich <jbeulich@suse.com>
243
244 * i386-gen.c (operand_type_init): Remove
245 OPERAND_TYPE_JUMPABSOLUTE entry.
246 (opcode_modifiers): Add JumpAbsolute entry.
247 (operand_types): Remove JumpAbsolute entry.
248 * i386-opc.h (JumpAbsolute): Move between enums.
249 (struct i386_opcode_modifier): Add jumpabsolute field.
250 (union i386_operand_type): Remove jumpabsolute field.
251 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
252 * i386-init.h, i386-tbl.h: Re-generate.
253
601e8564
JB		 2542019-11-14 Jan Beulich <jbeulich@suse.com>
255
256 * i386-gen.c (opcode_modifiers): Add AnySize entry.
257 (operand_types): Remove AnySize entry.
258 * i386-opc.h (AnySize): Move between enums.
259 (struct i386_opcode_modifier): Add anysize field.
260 (OTUnused): Un-comment.
261 (union i386_operand_type): Remove anysize field.
262 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
263 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
264 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
265 AnySize.
266 * i386-tbl.h: Re-generate.
267
7722d40a
JW		 2682019-11-12 Nelson Chu <nelson.chu@sifive.com>
269
270 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
271 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
272 use the floating point register (FPR).
273
ce760a76
MI		 2742019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
275
276 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
277 cmode 1101.
278 (is_mve_encoding_conflict): Update cmode conflict checks for
279 MVE_VMVN_IMM.
280
51c8edf6
JB		 2812019-11-12 Jan Beulich <jbeulich@suse.com>
282
283 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
284 entry.
285 (operand_types): Remove EsSeg entry.
286 (main): Replace stale use of OTMax.
287 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
288 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
289 (EsSeg): Delete.
290 (OTUnused): Comment out.
291 (union i386_operand_type): Remove esseg field.
292 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
293 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
294 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
295 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
296 * i386-init.h, i386-tbl.h: Re-generate.
297
474da251
JB		 2982019-11-12 Jan Beulich <jbeulich@suse.com>
299
300 * i386-gen.c (operand_instances): Add RegB entry.
301 * i386-opc.h (enum operand_instance): Add RegB.
302 * i386-opc.tbl (RegC, RegD, RegB): Define.
303 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
304 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
305 monitorx, mwaitx): Drop ImmExt and convert encodings
306 accordingly.
307 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
308 (edx, rdx): Add Instance=RegD.
309 (ebx, rbx): Add Instance=RegB.
310 * i386-tbl.h: Re-generate.
311
75e5731b
JB		 3122019-11-12 Jan Beulich <jbeulich@suse.com>
313
314 * i386-gen.c (operand_type_init): Adjust
315 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
316 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
317 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
318 (operand_instances): New.
319 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
320 (output_operand_type): New parameter "instance". Process it.
321 (process_i386_operand_type): New local variable "instance".
322 (main): Adjust static assertions.
323 * i386-opc.h (INSTANCE_WIDTH): Define.
324 (enum operand_instance): New.
325 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
326 (union i386_operand_type): Replace acc, inoutportreg, and
327 shiftcount by instance.
328 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
329 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
330 Add Instance=.
331 * i386-init.h, i386-tbl.h: Re-generate.
332
91802f3c
JB		 3332019-11-11 Jan Beulich <jbeulich@suse.com>
334
335 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
336 smaxp/sminp entries' "tied_operand" field to 2.
337
4f5fc85d
JB		 3382019-11-11 Jan Beulich <jbeulich@suse.com>
339
340 * aarch64-opc.c (operand_general_constraint_met_p): Replace
341 "index" local variable by that of the already existing "num".
342
dc2be329
L		 3432019-11-08 H.J. Lu <hongjiu.lu@intel.com>
344
345 PR gas/25167
346 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
347 * i386-tbl.h: Regenerated.
348
f74a6307
JB		 3492019-11-08 Jan Beulich <jbeulich@suse.com>
350
351 * i386-gen.c (operand_type_init): Add Class= to
352 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
353 OPERAND_TYPE_REGBND entry.
354 (operand_classes): Add RegMask and RegBND entries.
355 (operand_types): Drop RegMask and RegBND entry.
356 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
357 (RegMask, RegBND): Delete.
358 (union i386_operand_type): Remove regmask and regbnd fields.
359 * i386-opc.tbl (RegMask, RegBND): Define.
360 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
361 Class=RegBND.
362 * i386-init.h, i386-tbl.h: Re-generate.
363
3528c362
JB		 3642019-11-08 Jan Beulich <jbeulich@suse.com>
365
366 * i386-gen.c (operand_type_init): Add Class= to
367 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
368 OPERAND_TYPE_REGZMM entries.
369 (operand_classes): Add RegMMX and RegSIMD entries.
370 (operand_types): Drop RegMMX and RegSIMD entries.
371 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
372 (RegMMX, RegSIMD): Delete.
373 (union i386_operand_type): Remove regmmx and regsimd fields.
374 * i386-opc.tbl (RegMMX): Define.
375 (RegXMM, RegYMM, RegZMM): Add Class=.
376 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
377 Class=RegSIMD.
378 * i386-init.h, i386-tbl.h: Re-generate.
379
4a5c67ed
JB		 3802019-11-08 Jan Beulich <jbeulich@suse.com>
381
382 * i386-gen.c (operand_type_init): Add Class= to
383 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
384 entries.
385 (operand_classes): Add RegCR, RegDR, and RegTR entries.
386 (operand_types): Drop Control, Debug, and Test entries.
387 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
388 (Control, Debug, Test): Delete.
389 (union i386_operand_type): Remove control, debug, and test
390 fields.
391 * i386-opc.tbl (Control, Debug, Test): Define.
392 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
393 Class=RegDR, and Test by Class=RegTR.
394 * i386-init.h, i386-tbl.h: Re-generate.
395
00cee14f
JB		 3962019-11-08 Jan Beulich <jbeulich@suse.com>
397
398 * i386-gen.c (operand_type_init): Add Class= to
399 OPERAND_TYPE_SREG entry.
400 (operand_classes): Add SReg entry.
401 (operand_types): Drop SReg entry.
402 * i386-opc.h (enum operand_class): Add SReg.
403 (SReg): Delete.
404 (union i386_operand_type): Remove sreg field.
405 * i386-opc.tbl (SReg): Define.
406 * i386-reg.tbl: Replace SReg by Class=SReg.
407 * i386-init.h, i386-tbl.h: Re-generate.
408
bab6aec1
JB		 4092019-11-08 Jan Beulich <jbeulich@suse.com>
410
411 * i386-gen.c (operand_type_init): Add Class=. New
412 OPERAND_TYPE_ANYIMM entry.
413 (operand_classes): New.
414 (operand_types): Drop Reg entry.
415 (output_operand_type): New parameter "class". Process it.
416 (process_i386_operand_type): New local variable "class".
417 (main): Adjust static assertions.
418 * i386-opc.h (CLASS_WIDTH): Define.
419 (enum operand_class): New.
420 (Reg): Replace by Class. Adjust comment.
421 (union i386_operand_type): Replace reg by class.
422 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
423 Class=.
424 * i386-reg.tbl: Replace Reg by Class=Reg.
425 * i386-init.h: Re-generate.
426
1f4cd317
MM		 4272019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
428
429 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
430 (aarch64_opcode_table): Add data gathering hint mnemonic.
431 * opcodes/aarch64-dis-2.c: Account for new instruction.
432
616ce08e
MM		 4332019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
434
435 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
436
437
8382113f
MM		 4382019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
439
440 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
441 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
442 aarch64_feature_f64mm): New feature sets.
443 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
444 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
445 instructions.
446 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
447 macros.
448 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
449 (OP_SVE_QQQ): New qualifier.
450 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
451 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
452 the movprfx constraint.
453 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
454 (aarch64_opcode_table): Define new instructions smmla,
455 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
456 uzip{1/2}, trn{1/2}.
457 * aarch64-opc.c (operand_general_constraint_met_p): Handle
458 AARCH64_OPND_SVE_ADDR_RI_S4x32.
459 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
460 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
461 Account for new instructions.
462 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
463 S4x32 operand.
464 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
465
aab2c27d
MM		 4662019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4672019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
468
469 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
470 Armv8.6-A.
471 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
472 (neon_opcodes): Add bfloat SIMD instructions.
473 (print_insn_coprocessor): Add new control character %b to print
474 condition code without checking cp_num.
475 (print_insn_neon): Account for BFloat16 instructions that have no
476 special top-byte handling.
477
33593eaf
MM		 4782019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4792019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
480
481 * arm-dis.c (print_insn_coprocessor,
482 print_insn_generic_coprocessor): Create wrapper functions around
483 the implementation of the print_insn_coprocessor control codes.
484 (print_insn_coprocessor_1): Original print_insn_coprocessor
485 function that now takes which array to look at as an argument.
486 (print_insn_arm): Use both print_insn_coprocessor and
487 print_insn_generic_coprocessor.
488 (print_insn_thumb32): As above.
489
df678013
MM		 4902019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4912019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
492
493 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
494 in reglane special case.
495 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
496 aarch64_find_next_opcode): Account for new instructions.
497 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
498 in reglane special case.
499 * aarch64-opc.c (struct operand_qualifier_data): Add data for
500 new AARCH64_OPND_QLF_S_2H qualifier.
501 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
502 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
503 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
504 sets.
505 (BFLOAT_SVE, BFLOAT): New feature set macros.
506 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
507 instructions.
508 (aarch64_opcode_table): Define new instructions bfdot,
509 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
510 bfcvtn2, bfcvt.
511
8ae2d3d9
MM		 5122019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5132019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
514
515 * aarch64-tbl.h (ARMV8_6): New macro.
516
142861df
JB		 5172019-11-07 Jan Beulich <jbeulich@suse.com>
518
519 * i386-dis.c (prefix_table): Add mcommit.
520 (rm_table): Add rdpru.
521 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
522 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
523 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
524 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
525 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
526 * i386-opc.tbl (mcommit, rdpru): New.
527 * i386-init.h, i386-tbl.h: Re-generate.
528
081e283f
JB		 5292019-11-07 Jan Beulich <jbeulich@suse.com>
530
531 * i386-dis.c (OP_Mwait): Drop local variable "names", use
532 "names32" instead.
533 (OP_Monitor): Drop local variable "op1_names", re-purpose
534 "names" for it instead, and replace former "names" uses by
535 "names32" ones.
536
c050c89a
JB		 5372019-11-07 Jan Beulich <jbeulich@suse.com>
538
539 PR/gas 25167
540 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
541 operand-less forms.
542 * opcodes/i386-tbl.h: Re-generate.
543
7abb8d81
JB		 5442019-11-05 Jan Beulich <jbeulich@suse.com>
545
546 * i386-dis.c (OP_Mwaitx): Delete.
547 (prefix_table): Use OP_Mwait for mwaitx entry.
548 (OP_Mwait): Also handle mwaitx.
549
267b8516
JB		 5502019-11-05 Jan Beulich <jbeulich@suse.com>
551
552 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
553 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
554 (prefix_table): Add respective entries.
555 (rm_table): Link to those entries.
556
f8687e93
JB		 5572019-11-05 Jan Beulich <jbeulich@suse.com>
558
559 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
560 (REG_0F1C_P_0_MOD_0): ... this.
561 (REG_0F1E_MOD_3): Rename to ...
562 (REG_0F1E_P_1_MOD_3): ... this.
563 (RM_0F01_REG_5): Rename to ...
564 (RM_0F01_REG_5_MOD_3): ... this.
565 (RM_0F01_REG_7): Rename to ...
566 (RM_0F01_REG_7_MOD_3): ... this.
567 (RM_0F1E_MOD_3_REG_7): Rename to ...
568 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
569 (RM_0FAE_REG_6): Rename to ...
570 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
571 (RM_0FAE_REG_7): Rename to ...
572 (RM_0FAE_REG_7_MOD_3): ... this.
573 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
574 (PREFIX_0F01_REG_5_MOD_0): ... this.
575 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
576 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
577 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
578 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
579 (PREFIX_0FAE_REG_0): Rename to ...
580 (PREFIX_0FAE_REG_0_MOD_3): ... this.
581 (PREFIX_0FAE_REG_1): Rename to ...
582 (PREFIX_0FAE_REG_1_MOD_3): ... this.
583 (PREFIX_0FAE_REG_2): Rename to ...
584 (PREFIX_0FAE_REG_2_MOD_3): ... this.
585 (PREFIX_0FAE_REG_3): Rename to ...
586 (PREFIX_0FAE_REG_3_MOD_3): ... this.
587 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
588 (PREFIX_0FAE_REG_4_MOD_0): ... this.
589 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
590 (PREFIX_0FAE_REG_4_MOD_3): ... this.
591 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
592 (PREFIX_0FAE_REG_5_MOD_0): ... this.
593 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
594 (PREFIX_0FAE_REG_5_MOD_3): ... this.
595 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
596 (PREFIX_0FAE_REG_6_MOD_0): ... this.
597 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
598 (PREFIX_0FAE_REG_6_MOD_3): ... this.
599 (PREFIX_0FAE_REG_7): Rename to ...
600 (PREFIX_0FAE_REG_7_MOD_0): ... this.
601 (PREFIX_MOD_0_0FC3): Rename to ...
602 (PREFIX_0FC3_MOD_0): ... this.
603 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
604 (PREFIX_0FC7_REG_6_MOD_0): ... this.
605 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
606 (PREFIX_0FC7_REG_6_MOD_3): ... this.
607 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
608 (PREFIX_0FC7_REG_7_MOD_3): ... this.
609 (reg_table, prefix_table, mod_table, rm_table): Adjust
610 accordingly.
611
5103274f
NC		 6122019-11-04 Nick Clifton <nickc@redhat.com>
613
614 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
615 of a v850 system register. Move the v850_sreg_names array into
616 this function.
617 (get_v850_reg_name): Likewise for ordinary register names.
618 (get_v850_vreg_name): Likewise for vector register names.
619 (get_v850_cc_name): Likewise for condition codes.
620 * get_v850_float_cc_name): Likewise for floating point condition
621 codes.
622 (get_v850_cacheop_name): Likewise for cache-ops.
623 (get_v850_prefop_name): Likewise for pref-ops.
624 (disassemble): Use the new accessor functions.
625
1820262b
DB		 6262019-10-30 Delia Burduv <delia.burduv@arm.com>
627
628 * aarch64-opc.c (print_immediate_offset_address): Don't print the
629 immediate for the writeback form of ldraa/ldrab if it is 0.
630 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
631 * aarch64-opc-2.c: Regenerated.
632
3cc17af5
JB		 6332019-10-30 Jan Beulich <jbeulich@suse.com>
634
635 * i386-gen.c (operand_type_shorthands): Delete.
636 (operand_type_init): Expand previous shorthands.
637 (set_bitfield_from_shorthand): Rename back to ...
638 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
639 of operand_type_init[].
640 (set_bitfield): Adjust call to the above function.
641 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
642 RegXMM, RegYMM, RegZMM): Define.
643 * i386-reg.tbl: Expand prior shorthands.
644
a2cebd03
JB		 6452019-10-30 Jan Beulich <jbeulich@suse.com>
646
647 * i386-gen.c (output_i386_opcode): Change order of fields
648 emitted to output.
649 * i386-opc.h (struct insn_template): Move operands field.
650 Convert extension_opcode field to unsigned short.
651 * i386-tbl.h: Re-generate.
652
507916b8
JB		 6532019-10-30 Jan Beulich <jbeulich@suse.com>
654
655 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
656 of W.
657 * i386-opc.h (W): Extend comment.
658 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
659 general purpose variants not allowing for byte operands.
660 * i386-tbl.h: Re-generate.
661
efea62b4
NC		 6622019-10-29 Nick Clifton <nickc@redhat.com>
663
664 * tic30-dis.c (print_branch): Correct size of operand array.
665
9adb2591
NC		 6662019-10-29 Nick Clifton <nickc@redhat.com>
667
668 * d30v-dis.c (print_insn): Check that operand index is valid
669 before attempting to access the operands array.
670
993a00a9
NC		 6712019-10-29 Nick Clifton <nickc@redhat.com>
672
673 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
674 locating the bit to be tested.
675
66a66a17
NC		 6762019-10-29 Nick Clifton <nickc@redhat.com>
677
678 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
679 values.
680 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
681 (print_insn_s12z): Check for illegal size values.
682
1ee3542c
NC		 6832019-10-28 Nick Clifton <nickc@redhat.com>
684
685 * csky-dis.c (csky_chars_to_number): Check for a negative
686 count. Use an unsigned integer to construct the return value.
687
bbf9a0b5
NC		 6882019-10-28 Nick Clifton <nickc@redhat.com>
689
690 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
691 operand buffer. Set value to 15 not 13.
692 (get_register_operand): Use OPERAND_BUFFER_LEN.
693 (get_indirect_operand): Likewise.
694 (print_two_operand): Likewise.
695 (print_three_operand): Likewise.
696 (print_oar_insn): Likewise.
697
d1e304bc
NC		 6982019-10-28 Nick Clifton <nickc@redhat.com>
699
700 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
701 (bit_extract_simple): Likewise.
702 (bit_copy): Likewise.
703 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
704 index_offset array are not accessed.
705
dee33451
NC		 7062019-10-28 Nick Clifton <nickc@redhat.com>
707
708 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
709 operand.
710
27cee81d
NC		 7112019-10-25 Nick Clifton <nickc@redhat.com>
712
713 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
714 access to opcodes.op array element.
715
de6d8dc2
NC		 7162019-10-23 Nick Clifton <nickc@redhat.com>
717
718 * rx-dis.c (get_register_name): Fix spelling typo in error
719 message.
720 (get_condition_name, get_flag_name, get_double_register_name)
721 (get_double_register_high_name, get_double_register_low_name)
722 (get_double_control_register_name, get_double_condition_name)
723 (get_opsize_name, get_size_name): Likewise.
724
6207ed28
NC		 7252019-10-22 Nick Clifton <nickc@redhat.com>
726
727 * rx-dis.c (get_size_name): New function. Provides safe
728 access to name array.
729 (get_opsize_name): Likewise.
730 (print_insn_rx): Use the accessor functions.
731
12234dfd
NC		 7322019-10-16 Nick Clifton <nickc@redhat.com>
733
734 * rx-dis.c (get_register_name): New function. Provides safe
735 access to name array.
736 (get_condition_name, get_flag_name, get_double_register_name)
737 (get_double_register_high_name, get_double_register_low_name)
738 (get_double_control_register_name, get_double_condition_name):
739 Likewise.
740 (print_insn_rx): Use the accessor functions.
741
1d378749
NC		 7422019-10-09 Nick Clifton <nickc@redhat.com>
743
744 PR 25041
745 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
746 instructions.
747
d241b910
JB		 7482019-10-07 Jan Beulich <jbeulich@suse.com>
749
750 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
751 (cmpsd): Likewise. Move EsSeg to other operand.
752 * opcodes/i386-tbl.h: Re-generate.
753
f5c5b7c1
AM		 7542019-09-23 Alan Modra <amodra@gmail.com>
755
756 * m68k-dis.c: Include cpu-m68k.h
757
7beeaeb8
AM		 7582019-09-23 Alan Modra <amodra@gmail.com>
759
760 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
761 "elf/mips.h" earlier.
762
3f9aad11
JB		 7632018-09-20 Jan Beulich <jbeulich@suse.com>
764
765 PR gas/25012
766 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
767 with SReg operand.
768 * i386-tbl.h: Re-generate.
769
fd361982
AM		 7702019-09-18 Alan Modra <amodra@gmail.com>
771
772 * arc-ext.c: Update throughout for bfd section macro changes.
773
e0b2a78c
SM		 7742019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
775
776 * Makefile.in: Re-generate.
777 * configure: Re-generate.
778
7e9ad3a3
JW		 7792019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
780
781 * riscv-opc.c (riscv_opcodes): Change subset field
782 to insn_class field for all instructions.
783 (riscv_insn_types): Likewise.
784
bb695960
PB		 7852019-09-16 Phil Blundell <pb@pbcl.net>
786
787 * configure: Regenerated.
788
8063ab7e
MV		 7892019-09-10 Miod Vallat <miod@online.fr>
790
791 PR 24982
792 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
793
60391a25
PB		 7942019-09-09 Phil Blundell <pb@pbcl.net>
795
796 binutils 2.33 branch created.
797
f44b758d
NC		 7982019-09-03 Nick Clifton <nickc@redhat.com>
799
800 PR 24961
801 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
802 greater than zero before indexing via (bufcnt -1).
803
1e4b5e7d
NC		 8042019-09-03 Nick Clifton <nickc@redhat.com>
805
806 PR 24958
807 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
808 (MAX_SPEC_REG_NAME_LEN): Define.
809 (struct mmix_dis_info): Use defined constants for array lengths.
810 (get_reg_name): New function.
811 (get_sprec_reg_name): New function.
812 (print_insn_mmix): Use new functions.
813
c4a23bf8
SP		 8142019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
815
816 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
817 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
818 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
819
a051e2f3
KT		 8202019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
821
822 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
823 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
824 (aarch64_sys_reg_supported_p): Update checks for the above.
825
08132bdd
SP		 8262019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
827
828 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
829 cases MVE_SQRSHRL and MVE_UQRSHLL.
830 (print_insn_mve): Add case for specifier 'k' to check
831 specific bit of the instruction.
832
d88bdcb4
PA		 8332019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
834
835 PR 24854
836 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
837 encountering an unknown machine type.
838 (print_insn_arc): Handle arc_insn_length returning 0. In error
839 cases return -1 rather than calling abort.
840
bc750500
JB		 8412019-08-07 Jan Beulich <jbeulich@suse.com>
842
843 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
844 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
845 IgnoreSize.
846 * i386-tbl.h: Re-generate.
847
23d188c7
BW		 8482019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
849
850 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
851 instructions.
852
c0d6f62f
JW		 8532019-07-30 Mel Chen <mel.chen@sifive.com>
854
855 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
856 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
857
858 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
859 fscsr.
860
0f3f7167
CZ		 8612019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
862
863 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
864 and MPY class instructions.
865 (parse_option): Add nps400 option.
866 (print_arc_disassembler_options): Add nps400 info.
867
7e126ba3
CZ		 8682019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
869
870 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
871 (bspop): Likewise.
872 (modapp): Likewise.
873 * arc-opc.c (RAD_CHK): Add.
874 * arc-tbl.h: Regenerate.
875
a028026d
KT		 8762019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
877
878 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
879 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
880
ac79ff9e
NC		 8812019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
882
883 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
884 instructions as UNPREDICTABLE.
885
231097b0
JM		 8862019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
887
888 * bpf-desc.c: Regenerated.
889
1d942ae9
JB		 8902019-07-17 Jan Beulich <jbeulich@suse.com>
891
892 * i386-gen.c (static_assert): Define.
893 (main): Use it.
894 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
895 (Opcode_Modifier_Num): ... this.
896 (Mem): Delete.
897
dfd69174
JB		 8982019-07-16 Jan Beulich <jbeulich@suse.com>
899
900 * i386-gen.c (operand_types): Move RegMem ...
901 (opcode_modifiers): ... here.
902 * i386-opc.h (RegMem): Move to opcode modifer enum.
903 (union i386_operand_type): Move regmem field ...
904 (struct i386_opcode_modifier): ... here.
905 * i386-opc.tbl (RegMem): Define.
906 (mov, movq): Move RegMem on segment, control, debug, and test
907 register flavors.
908 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
909 to non-SSE2AVX flavor.
910 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
911 Move RegMem on register only flavors. Drop IgnoreSize from
912 legacy encoding flavors.
913 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
914 flavors.
915 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
916 register only flavors.
917 (vmovd): Move RegMem and drop IgnoreSize on register only
918 flavor. Change opcode and operand order to store form.
919 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
920
21df382b
JB		 9212019-07-16 Jan Beulich <jbeulich@suse.com>
922
923 * i386-gen.c (operand_type_init, operand_types): Replace SReg
924 entries.
925 * i386-opc.h (SReg2, SReg3): Replace by ...
926 (SReg): ... this.
927 (union i386_operand_type): Replace sreg fields.
928 * i386-opc.tbl (mov, ): Use SReg.
929 (push, pop): Likewies. Drop i386 and x86-64 specific segment
930 register flavors.
931 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
932 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
933
3719fd55
JM		 9342019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
935
936 * bpf-desc.c: Regenerate.
937 * bpf-opc.c: Likewise.
938 * bpf-opc.h: Likewise.
939
92434a14
JM		 9402019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
941
942 * bpf-desc.c: Regenerate.
943 * bpf-opc.c: Likewise.
944
43dd7626
HPN		 9452019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
946
947 * arm-dis.c (print_insn_coprocessor): Rename index to
948 index_operand.
949
98602811
JW		 9502019-07-05 Kito Cheng <kito.cheng@sifive.com>
951
952 * riscv-opc.c (riscv_insn_types): Add r4 type.
953
954 * riscv-opc.c (riscv_insn_types): Add b and j type.
955
956 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
957 format for sb type and correct s type.
958
01c1ee4a
RS		 9592019-07-02 Richard Sandiford <richard.sandiford@arm.com>
960
961 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
962 SVE FMOV alias of FCPY.
963
83adff69
RS		 9642019-07-02 Richard Sandiford <richard.sandiford@arm.com>
965
966 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
967 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
968
89418844
RS		 9692019-07-02 Richard Sandiford <richard.sandiford@arm.com>
970
971 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
972 registers in an instruction prefixed by MOVPRFX.
973
41be57ca
MM		 9742019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
975
976 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
977 sve_size_13 icode to account for variant behaviour of
978 pmull{t,b}.
979 * aarch64-dis-2.c: Regenerate.
980 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
981 sve_size_13 icode to account for variant behaviour of
982 pmull{t,b}.
983 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
984 (OP_SVE_VVV_Q_D): Add new qualifier.
985 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
986 (struct aarch64_opcode): Split pmull{t,b} into those requiring
987 AES and those not.
988
9d3bf266
JB		 9892019-07-01 Jan Beulich <jbeulich@suse.com>
990
991 * opcodes/i386-gen.c (operand_type_init): Remove
992 OPERAND_TYPE_VEC_IMM4 entry.
993 (operand_types): Remove Vec_Imm4.
994 * opcodes/i386-opc.h (Vec_Imm4): Delete.
995 (union i386_operand_type): Remove vec_imm4.
996 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
997 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
998
c3949f43
JB		 9992019-07-01 Jan Beulich <jbeulich@suse.com>
1000
1001 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1002 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1003 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1004 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1005 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1006 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1007 * i386-tbl.h: Re-generate.
1008
5641ec01
JB		 10092019-07-01 Jan Beulich <jbeulich@suse.com>
1010
1011 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1012 register operands.
1013 * i386-tbl.h: Re-generate.
1014
79dec6b7
JB		 10152019-07-01 Jan Beulich <jbeulich@suse.com>
1016
1017 * i386-opc.tbl (C): New.
1018 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1019 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1020 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1021 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1022 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1023 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1024 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1025 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1026 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1027 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1028 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1029 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1030 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1031 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1032 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1033 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1034 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1035 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1036 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1037 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1038 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1039 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1040 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1041 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1042 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1043 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1044 flavors.
1045 * i386-tbl.h: Re-generate.
1046
a0a1771e
JB		 10472019-07-01 Jan Beulich <jbeulich@suse.com>
1048
1049 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1050 register operands.
1051 * i386-tbl.h: Re-generate.
1052
cd546e7b
JB		 10532019-07-01 Jan Beulich <jbeulich@suse.com>
1054
1055 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1056 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1057 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1058 * i386-tbl.h: Re-generate.
1059
e3bba3fc
JB		 10602019-07-01 Jan Beulich <jbeulich@suse.com>
1061
1062 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1063 Disp8MemShift from register only templates.
1064 * i386-tbl.h: Re-generate.
1065
36cc073e
JB		 10662019-07-01 Jan Beulich <jbeulich@suse.com>
1067
1068 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1069 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1070 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1071 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1072 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1073 EVEX_W_0F11_P_3_M_1): Delete.
1074 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1075 EVEX_W_0F11_P_3): New.
1076 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1077 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1078 MOD_EVEX_0F11_PREFIX_3 table entries.
1079 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1080 PREFIX_EVEX_0F11 table entries.
1081 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1082 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1083 EVEX_W_0F11_P_3_M_{0,1} table entries.
1084
219920a7
JB		 10852019-07-01 Jan Beulich <jbeulich@suse.com>
1086
1087 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1088 Delete.
1089
e395f487
L		 10902019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1091
1092 PR binutils/24719
1093 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1094 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1095 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1096 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1097 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1098 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1099 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1100 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1101 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1102 PREFIX_EVEX_0F38C6_REG_6 entries.
1103 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1104 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1105 EVEX_W_0F38C7_R_6_P_2 entries.
1106 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1107 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1108 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1109 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1110 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1111 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1112 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1113
2b7bcc87
JB		 11142019-06-27 Jan Beulich <jbeulich@suse.com>
1115
1116 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1117 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1118 VEX_LEN_0F2D_P_3): Delete.
1119 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1120 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1121 (prefix_table): ... here.
1122
c1dc7af5
JB		 11232019-06-27 Jan Beulich <jbeulich@suse.com>
1124
1125 * i386-dis.c (Iq): Delete.
1126 (Id): New.
1127 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1128 TBM insns.
1129 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1130 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1131 (OP_E_memory): Also honor needindex when deciding whether an
1132 address size prefix needs printing.
1133 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1134
d7560e2d
JW		 11352019-06-26 Jim Wilson <jimw@sifive.com>
1136
1137 PR binutils/24739
1138 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1139 Set info->display_endian to info->endian_code.
1140
2c703856
JB		 11412019-06-25 Jan Beulich <jbeulich@suse.com>
1142
1143 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1144 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1145 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1146 OPERAND_TYPE_ACC64 entries.
1147 * i386-init.h: Re-generate.
1148
54fbadc0
JB		 11492019-06-25 Jan Beulich <jbeulich@suse.com>
1150
1151 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1152 Delete.
1153 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1154 of dqa_mode.
1155 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1156 entries here.
1157 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1158 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1159
a280ab8e
JB		 11602019-06-25 Jan Beulich <jbeulich@suse.com>
1161
1162 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1163 variables.
1164
e1a1babd
JB		 11652019-06-25 Jan Beulich <jbeulich@suse.com>
1166
1167 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1168 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1169 movnti.
d7560e2d 1170 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1171 * i386-tbl.h: Re-generate.
1172
b8364fa7
JB		 11732019-06-25 Jan Beulich <jbeulich@suse.com>
1174
1175 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1176 * i386-tbl.h: Re-generate.
1177
ad692897
L		 11782019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1179
1180 * i386-dis-evex.h: Break into ...
1181 * i386-dis-evex-len.h: New file.
1182 * i386-dis-evex-mod.h: Likewise.
1183 * i386-dis-evex-prefix.h: Likewise.
1184 * i386-dis-evex-reg.h: Likewise.
1185 * i386-dis-evex-w.h: Likewise.
1186 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1187 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1188 i386-dis-evex-mod.h.
1189
f0a6222e
L		 11902019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1191
1192 PR binutils/24700
1193 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1194 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1195 EVEX_W_0F385B_P_2.
1196 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1197 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1198 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1199 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1200 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1201 EVEX_LEN_0F385B_P_2_W_1.
1202 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1203 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1204 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1205 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1206 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1207 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1208 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1209 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1210 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1211 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1212
6e1c90b7
L		 12132019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1214
1215 PR binutils/24691
1216 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1217 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1218 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1219 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1220 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1221 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1222 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1223 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1224 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1225 EVEX_LEN_0F3A43_P_2_W_1.
1226 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1227 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1228 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1229 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1230 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1231 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1232 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1233 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1234 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1235 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1236 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1237 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1238
bcc5a6eb
NC		 12392019-06-14 Nick Clifton <nickc@redhat.com>
1240
1241 * po/fr.po; Updated French translation.
1242
e4c4ac46
SH		 12432019-06-13 Stafford Horne <shorne@gmail.com>
1244
1245 * or1k-asm.c: Regenerated.
1246 * or1k-desc.c: Regenerated.
1247 * or1k-desc.h: Regenerated.
1248 * or1k-dis.c: Regenerated.
1249 * or1k-ibld.c: Regenerated.
1250 * or1k-opc.c: Regenerated.
1251 * or1k-opc.h: Regenerated.
1252 * or1k-opinst.c: Regenerated.
1253
a0e44ef5
PB		 12542019-06-12 Peter Bergner <bergner@linux.ibm.com>
1255
1256 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1257
12efd68d
L		 12582019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1259
1260 PR binutils/24633
1261 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1262 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1263 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1264 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1265 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1266 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1267 EVEX_LEN_0F3A1B_P_2_W_1.
1268 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1269 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1270 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1271 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1272 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1273 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1274 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1275 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1276
63c6fc6c
L		 12772019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1278
1279 PR binutils/24626
1280 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1281 EVEX.vvvv when disassembling VEX and EVEX instructions.
1282 (OP_VEX): Set vex.register_specifier to 0 after readding
1283 vex.register_specifier.
1284 (OP_Vex_2src_1): Likewise.
1285 (OP_Vex_2src_2): Likewise.
1286 (OP_LWP_E): Likewise.
1287 (OP_EX_Vex): Don't check vex.register_specifier.
1288 (OP_XMM_Vex): Likewise.
1289
9186c494
L		 12902019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1291 Lili Cui <lili.cui@intel.com>
1292
1293 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1294 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1295 instructions.
1296 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1297 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1298 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1299 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1300 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1301 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1302 * i386-init.h: Regenerated.
1303 * i386-tbl.h: Likewise.
1304
5d79adc4
L		 13052019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1306 Lili Cui <lili.cui@intel.com>
1307
1308 * doc/c-i386.texi: Document enqcmd.
1309 * testsuite/gas/i386/enqcmd-intel.d: New file.
1310 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1311 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1312 * testsuite/gas/i386/enqcmd.d: Likewise.
1313 * testsuite/gas/i386/enqcmd.s: Likewise.
1314 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1315 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1316 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1317 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1318 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1319 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1320 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1321 and x86-64-enqcmd.
1322
a9d96ab9
AH		 13232019-06-04 Alan Hayward <alan.hayward@arm.com>
1324
1325 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1326
4f6d070a
AM		 13272019-06-03 Alan Modra <amodra@gmail.com>
1328
1329 * ppc-dis.c (prefix_opcd_indices): Correct size.
1330
a2f4b66c
L		 13312019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1332
1333 PR gas/24625
1334 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1335 Disp8ShiftVL.
1336 * i386-tbl.h: Regenerated.
1337
405b5bd8
AM		 13382019-05-24 Alan Modra <amodra@gmail.com>
1339
1340 * po/POTFILES.in: Regenerate.
1341
8acf1435
PB		 13422019-05-24 Peter Bergner <bergner@linux.ibm.com>
1343 Alan Modra <amodra@gmail.com>
1344
1345 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1346 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1347 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1348 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1349 XTOP>): Define and add entries.
1350 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1351 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1352 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1353 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1354
dd7efa79
PB		 13552019-05-24 Peter Bergner <bergner@linux.ibm.com>
1356 Alan Modra <amodra@gmail.com>
1357
1358 * ppc-dis.c (ppc_opts): Add "future" entry.
1359 (PREFIX_OPCD_SEGS): Define.
1360 (prefix_opcd_indices): New array.
1361 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1362 (lookup_prefix): New function.
1363 (print_insn_powerpc): Handle 64-bit prefix instructions.
1364 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1365 (PMRR, POWERXX): Define.
1366 (prefix_opcodes): New instruction table.
1367 (prefix_num_opcodes): New constant.
1368
79472b45
JM		 13692019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1370
1371 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1372 * configure: Regenerated.
1373 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1374 and cpu/bpf.opc.
1375 (HFILES): Add bpf-desc.h and bpf-opc.h.
1376 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1377 bpf-ibld.c and bpf-opc.c.
1378 (BPF_DEPS): Define.
1379 * Makefile.in: Regenerated.
1380 * disassemble.c (ARCH_bpf): Define.
1381 (disassembler): Add case for bfd_arch_bpf.
1382 (disassemble_init_for_target): Likewise.
1383 (enum epbf_isa_attr): Define.
1384 * disassemble.h: extern print_insn_bpf.
1385 * bpf-asm.c: Generated.
1386 * bpf-opc.h: Likewise.
1387 * bpf-opc.c: Likewise.
1388 * bpf-ibld.c: Likewise.
1389 * bpf-dis.c: Likewise.
1390 * bpf-desc.h: Likewise.
1391 * bpf-desc.c: Likewise.
1392
ba6cd17f
SD		 13932019-05-21 Sudakshina Das <sudi.das@arm.com>
1394
1395 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1396 and VMSR with the new operands.
1397
e39c1607
SD		 13982019-05-21 Sudakshina Das <sudi.das@arm.com>
1399
1400 * arm-dis.c (enum mve_instructions): New enum
1401 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1402 and cneg.
1403 (mve_opcodes): New instructions as above.
1404 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1405 csneg and csel.
1406 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1407
23d00a41
SD		 14082019-05-21 Sudakshina Das <sudi.das@arm.com>
1409
1410 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1411 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1412 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1413 uqshl, urshrl and urshr.
1414 (is_mve_okay_in_it): Add new instructions to TRUE list.
1415 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1416 (print_insn_mve): Updated to accept new %j,
1417 %<bitfield>m and %<bitfield>n patterns.
1418
cd4797ee
FS		 14192019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1420
1421 * mips-opc.c (mips_builtin_opcodes): Change source register
1422 constraint for DAUI.
1423
999b073b
NC		 14242019-05-20 Nick Clifton <nickc@redhat.com>
1425
1426 * po/fr.po: Updated French translation.
1427
14b456f2
AV		 14282019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1429 Michael Collison <michael.collison@arm.com>
1430
1431 * arm-dis.c (thumb32_opcodes): Add new instructions.
1432 (enum mve_instructions): Likewise.
1433 (enum mve_undefined): Add new reasons.
1434 (is_mve_encoding_conflict): Handle new instructions.
1435 (is_mve_undefined): Likewise.
1436 (is_mve_unpredictable): Likewise.
1437 (print_mve_undefined): Likewise.
1438 (print_mve_size): Likewise.
1439
f49bb598
AV		 14402019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1441 Michael Collison <michael.collison@arm.com>
1442
1443 * arm-dis.c (thumb32_opcodes): Add new instructions.
1444 (enum mve_instructions): Likewise.
1445 (is_mve_encoding_conflict): Handle new instructions.
1446 (is_mve_undefined): Likewise.
1447 (is_mve_unpredictable): Likewise.
1448 (print_mve_size): Likewise.
1449
56858bea
AV		 14502019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1451 Michael Collison <michael.collison@arm.com>
1452
1453 * arm-dis.c (thumb32_opcodes): Add new instructions.
1454 (enum mve_instructions): Likewise.
1455 (is_mve_encoding_conflict): Likewise.
1456 (is_mve_unpredictable): Likewise.
1457 (print_mve_size): Likewise.
1458
e523f101
AV		 14592019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1460 Michael Collison <michael.collison@arm.com>
1461
1462 * arm-dis.c (thumb32_opcodes): Add new instructions.
1463 (enum mve_instructions): Likewise.
1464 (is_mve_encoding_conflict): Handle new instructions.
1465 (is_mve_undefined): Likewise.
1466 (is_mve_unpredictable): Likewise.
1467 (print_mve_size): Likewise.
1468
66dcaa5d
AV		 14692019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1470 Michael Collison <michael.collison@arm.com>
1471
1472 * arm-dis.c (thumb32_opcodes): Add new instructions.
1473 (enum mve_instructions): Likewise.
1474 (is_mve_encoding_conflict): Handle new instructions.
1475 (is_mve_undefined): Likewise.
1476 (is_mve_unpredictable): Likewise.
1477 (print_mve_size): Likewise.
1478 (print_insn_mve): Likewise.
1479
d052b9b7
AV		 14802019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1481 Michael Collison <michael.collison@arm.com>
1482
1483 * arm-dis.c (thumb32_opcodes): Add new instructions.
1484 (print_insn_thumb32): Handle new instructions.
1485
ed63aa17
AV		 14862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1487 Michael Collison <michael.collison@arm.com>
1488
1489 * arm-dis.c (enum mve_instructions): Add new instructions.
1490 (enum mve_undefined): Add new reasons.
1491 (is_mve_encoding_conflict): Handle new instructions.
1492 (is_mve_undefined): Likewise.
1493 (is_mve_unpredictable): Likewise.
1494 (print_mve_undefined): Likewise.
1495 (print_mve_size): Likewise.
1496 (print_mve_shift_n): Likewise.
1497 (print_insn_mve): Likewise.
1498
897b9bbc
AV		 14992019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1500 Michael Collison <michael.collison@arm.com>
1501
1502 * arm-dis.c (enum mve_instructions): Add new instructions.
1503 (is_mve_encoding_conflict): Handle new instructions.
1504 (is_mve_unpredictable): Likewise.
1505 (print_mve_rotate): Likewise.
1506 (print_mve_size): Likewise.
1507 (print_insn_mve): Likewise.
1508
1c8f2df8
AV		 15092019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1510 Michael Collison <michael.collison@arm.com>
1511
1512 * arm-dis.c (enum mve_instructions): Add new instructions.
1513 (is_mve_encoding_conflict): Handle new instructions.
1514 (is_mve_unpredictable): Likewise.
1515 (print_mve_size): Likewise.
1516 (print_insn_mve): Likewise.
1517
d3b63143
AV		 15182019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1519 Michael Collison <michael.collison@arm.com>
1520
1521 * arm-dis.c (enum mve_instructions): Add new instructions.
1522 (enum mve_undefined): Add new reasons.
1523 (is_mve_encoding_conflict): Handle new instructions.
1524 (is_mve_undefined): Likewise.
1525 (is_mve_unpredictable): Likewise.
1526 (print_mve_undefined): Likewise.
1527 (print_mve_size): Likewise.
1528 (print_insn_mve): Likewise.
1529
14925797
AV		 15302019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1531 Michael Collison <michael.collison@arm.com>
1532
1533 * arm-dis.c (enum mve_instructions): Add new instructions.
1534 (is_mve_encoding_conflict): Handle new instructions.
1535 (is_mve_undefined): Likewise.
1536 (is_mve_unpredictable): Likewise.
1537 (print_mve_size): Likewise.
1538 (print_insn_mve): Likewise.
1539
c507f10b
AV		 15402019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1541 Michael Collison <michael.collison@arm.com>
1542
1543 * arm-dis.c (enum mve_instructions): Add new instructions.
1544 (enum mve_unpredictable): Add new reasons.
1545 (enum mve_undefined): Likewise.
1546 (is_mve_okay_in_it): Handle new isntructions.
1547 (is_mve_encoding_conflict): Likewise.
1548 (is_mve_undefined): Likewise.
1549 (is_mve_unpredictable): Likewise.
1550 (print_mve_vmov_index): Likewise.
1551 (print_simd_imm8): Likewise.
1552 (print_mve_undefined): Likewise.
1553 (print_mve_unpredictable): Likewise.
1554 (print_mve_size): Likewise.
1555 (print_insn_mve): Likewise.
1556
bf0b396d
AV		 15572019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1558 Michael Collison <michael.collison@arm.com>
1559
1560 * arm-dis.c (enum mve_instructions): Add new instructions.
1561 (enum mve_unpredictable): Add new reasons.
1562 (enum mve_undefined): Likewise.
1563 (is_mve_encoding_conflict): Handle new instructions.
1564 (is_mve_undefined): Likewise.
1565 (is_mve_unpredictable): Likewise.
1566 (print_mve_undefined): Likewise.
1567 (print_mve_unpredictable): Likewise.
1568 (print_mve_rounding_mode): Likewise.
1569 (print_mve_vcvt_size): Likewise.
1570 (print_mve_size): Likewise.
1571 (print_insn_mve): Likewise.
1572
ef1576a1
AV		 15732019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1574 Michael Collison <michael.collison@arm.com>
1575
1576 * arm-dis.c (enum mve_instructions): Add new instructions.
1577 (enum mve_unpredictable): Add new reasons.
1578 (enum mve_undefined): Likewise.
1579 (is_mve_undefined): Handle new instructions.
1580 (is_mve_unpredictable): Likewise.
1581 (print_mve_undefined): Likewise.
1582 (print_mve_unpredictable): Likewise.
1583 (print_mve_size): Likewise.
1584 (print_insn_mve): Likewise.
1585
aef6d006
AV		 15862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1587 Michael Collison <michael.collison@arm.com>
1588
1589 * arm-dis.c (enum mve_instructions): Add new instructions.
1590 (enum mve_undefined): Add new reasons.
1591 (insns): Add new instructions.
1592 (is_mve_encoding_conflict):
1593 (print_mve_vld_str_addr): New print function.
1594 (is_mve_undefined): Handle new instructions.
1595 (is_mve_unpredictable): Likewise.
1596 (print_mve_undefined): Likewise.
1597 (print_mve_size): Likewise.
1598 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1599 (print_insn_mve): Handle new operands.
1600
04d54ace
AV		 16012019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1602 Michael Collison <michael.collison@arm.com>
1603
1604 * arm-dis.c (enum mve_instructions): Add new instructions.
1605 (enum mve_unpredictable): Add new reasons.
1606 (is_mve_encoding_conflict): Handle new instructions.
1607 (is_mve_unpredictable): Likewise.
1608 (mve_opcodes): Add new instructions.
1609 (print_mve_unpredictable): Handle new reasons.
1610 (print_mve_register_blocks): New print function.
1611 (print_mve_size): Handle new instructions.
1612 (print_insn_mve): Likewise.
1613
9743db03
AV		 16142019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1615 Michael Collison <michael.collison@arm.com>
1616
1617 * arm-dis.c (enum mve_instructions): Add new instructions.
1618 (enum mve_unpredictable): Add new reasons.
1619 (enum mve_undefined): Likewise.
1620 (is_mve_encoding_conflict): Handle new instructions.
1621 (is_mve_undefined): Likewise.
1622 (is_mve_unpredictable): Likewise.
1623 (coprocessor_opcodes): Move NEON VDUP from here...
1624 (neon_opcodes): ... to here.
1625 (mve_opcodes): Add new instructions.
1626 (print_mve_undefined): Handle new reasons.
1627 (print_mve_unpredictable): Likewise.
1628 (print_mve_size): Handle new instructions.
1629 (print_insn_neon): Handle vdup.
1630 (print_insn_mve): Handle new operands.
1631
143275ea
AV		 16322019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1633 Michael Collison <michael.collison@arm.com>
1634
1635 * arm-dis.c (enum mve_instructions): Add new instructions.
1636 (enum mve_unpredictable): Add new values.
1637 (mve_opcodes): Add new instructions.
1638 (vec_condnames): New array with vector conditions.
1639 (mve_predicatenames): New array with predicate suffixes.
1640 (mve_vec_sizename): New array with vector sizes.
1641 (enum vpt_pred_state): New enum with vector predication states.
1642 (struct vpt_block): New struct type for vpt blocks.
1643 (vpt_block_state): Global struct to keep track of state.
1644 (mve_extract_pred_mask): New helper function.
1645 (num_instructions_vpt_block): Likewise.
1646 (mark_outside_vpt_block): Likewise.
1647 (mark_inside_vpt_block): Likewise.
1648 (invert_next_predicate_state): Likewise.
1649 (update_next_predicate_state): Likewise.
1650 (update_vpt_block_state): Likewise.
1651 (is_vpt_instruction): Likewise.
1652 (is_mve_encoding_conflict): Add entries for new instructions.
1653 (is_mve_unpredictable): Likewise.
1654 (print_mve_unpredictable): Handle new cases.
1655 (print_instruction_predicate): Likewise.
1656 (print_mve_size): New function.
1657 (print_vec_condition): New function.
1658 (print_insn_mve): Handle vpt blocks and new print operands.
1659
f08d8ce3
AV		 16602019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1661
1662 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1663 8, 14 and 15 for Armv8.1-M Mainline.
1664
73cd51e5
AV		 16652019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1666 Michael Collison <michael.collison@arm.com>
1667
1668 * arm-dis.c (enum mve_instructions): New enum.
1669 (enum mve_unpredictable): Likewise.
1670 (enum mve_undefined): Likewise.
1671 (struct mopcode32): New struct.
1672 (is_mve_okay_in_it): New function.
1673 (is_mve_architecture): Likewise.
1674 (arm_decode_field): Likewise.
1675 (arm_decode_field_multiple): Likewise.
1676 (is_mve_encoding_conflict): Likewise.
1677 (is_mve_undefined): Likewise.
1678 (is_mve_unpredictable): Likewise.
1679 (print_mve_undefined): Likewise.
1680 (print_mve_unpredictable): Likewise.
1681 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1682 (print_insn_mve): New function.
1683 (print_insn_thumb32): Handle MVE architecture.
1684 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1685
3076e594
NC		 16862019-05-10 Nick Clifton <nickc@redhat.com>
1687
1688 PR 24538
1689 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1690 end of the table prematurely.
1691
387e7624
FS		 16922019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1693
1694 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1695 macros for R6.
1696
0067be51
AM		 16972019-05-11 Alan Modra <amodra@gmail.com>
1698
1699 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1700 when -Mraw is in effect.
1701
42e6288f
MM		 17022019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1703
1704 * aarch64-dis-2.c: Regenerate.
1705 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1706 (OP_SVE_BBB): New variant set.
1707 (OP_SVE_DDDD): New variant set.
1708 (OP_SVE_HHH): New variant set.
1709 (OP_SVE_HHHU): New variant set.
1710 (OP_SVE_SSS): New variant set.
1711 (OP_SVE_SSSU): New variant set.
1712 (OP_SVE_SHH): New variant set.
1713 (OP_SVE_SBBU): New variant set.
1714 (OP_SVE_DSS): New variant set.
1715 (OP_SVE_DHHU): New variant set.
1716 (OP_SVE_VMV_HSD_BHS): New variant set.
1717 (OP_SVE_VVU_HSD_BHS): New variant set.
1718 (OP_SVE_VVVU_SD_BH): New variant set.
1719 (OP_SVE_VVVU_BHSD): New variant set.
1720 (OP_SVE_VVV_QHD_DBS): New variant set.
1721 (OP_SVE_VVV_HSD_BHS): New variant set.
1722 (OP_SVE_VVV_HSD_BHS2): New variant set.
1723 (OP_SVE_VVV_BHS_HSD): New variant set.
1724 (OP_SVE_VV_BHS_HSD): New variant set.
1725 (OP_SVE_VVV_SD): New variant set.
1726 (OP_SVE_VVU_BHS_HSD): New variant set.
1727 (OP_SVE_VZVV_SD): New variant set.
1728 (OP_SVE_VZVV_BH): New variant set.
1729 (OP_SVE_VZV_SD): New variant set.
1730 (aarch64_opcode_table): Add sve2 instructions.
1731
28ed815a
MM		 17322019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1733
1734 * aarch64-asm-2.c: Regenerated.
1735 * aarch64-dis-2.c: Regenerated.
1736 * aarch64-opc-2.c: Regenerated.
1737 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1738 for SVE_SHLIMM_UNPRED_22.
1739 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1740 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1741 operand.
1742
fd1dc4a0
MM		 17432019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1744
1745 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1746 sve_size_tsz_bhs iclass encode.
1747 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1748 sve_size_tsz_bhs iclass decode.
1749
31e36ab3
MM		 17502019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1751
1752 * aarch64-asm-2.c: Regenerated.
1753 * aarch64-dis-2.c: Regenerated.
1754 * aarch64-opc-2.c: Regenerated.
1755 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1756 for SVE_Zm4_11_INDEX.
1757 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1758 (fields): Handle SVE_i2h field.
1759 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1760 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1761
1be5f94f
MM		 17622019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1763
1764 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1765 sve_shift_tsz_bhsd iclass encode.
1766 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1767 sve_shift_tsz_bhsd iclass decode.
1768
3c17238b
MM		 17692019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1770
1771 * aarch64-asm-2.c: Regenerated.
1772 * aarch64-dis-2.c: Regenerated.
1773 * aarch64-opc-2.c: Regenerated.
1774 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1775 (aarch64_encode_variant_using_iclass): Handle
1776 sve_shift_tsz_hsd iclass encode.
1777 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1778 sve_shift_tsz_hsd iclass decode.
1779 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1780 for SVE_SHRIMM_UNPRED_22.
1781 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1782 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1783 operand.
1784
cd50a87a
MM		 17852019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1786
1787 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1788 sve_size_013 iclass encode.
1789 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1790 sve_size_013 iclass decode.
1791
3c705960
MM		 17922019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1793
1794 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1795 sve_size_bh iclass encode.
1796 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1797 sve_size_bh iclass decode.
1798
0a57e14f
MM		 17992019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1800
1801 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1802 sve_size_sd2 iclass encode.
1803 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1804 sve_size_sd2 iclass decode.
1805 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1806 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1807
c469c864
MM		 18082019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1809
1810 * aarch64-asm-2.c: Regenerated.
1811 * aarch64-dis-2.c: Regenerated.
1812 * aarch64-opc-2.c: Regenerated.
1813 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1814 for SVE_ADDR_ZX.
1815 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1816 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1817
116adc27
MM		 18182019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1819
1820 * aarch64-asm-2.c: Regenerated.
1821 * aarch64-dis-2.c: Regenerated.
1822 * aarch64-opc-2.c: Regenerated.
1823 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1824 for SVE_Zm3_11_INDEX.
1825 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1826 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1827 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1828 fields.
1829 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1830
3bd82c86
MM		 18312019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1832
1833 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1834 sve_size_hsd2 iclass encode.
1835 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1836 sve_size_hsd2 iclass decode.
1837 * aarch64-opc.c (fields): Handle SVE_size field.
1838 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1839
adccc507
MM		 18402019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1841
1842 * aarch64-asm-2.c: Regenerated.
1843 * aarch64-dis-2.c: Regenerated.
1844 * aarch64-opc-2.c: Regenerated.
1845 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1846 for SVE_IMM_ROT3.
1847 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1848 (fields): Handle SVE_rot3 field.
1849 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1850 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1851
5cd99750
MM		 18522019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1853
1854 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1855 instructions.
1856
7ce2460a
MM		 18572019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1858
1859 * aarch64-tbl.h
1860 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1861 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1862 aarch64_feature_sve2bitperm): New feature sets.
1863 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1864 for feature set addresses.
1865 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1866 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1867
41cee089
FS		 18682019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1869 Faraz Shahbazker <fshahbazker@wavecomp.com>
1870
1871 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1872 argument and set ASE_EVA_R6 appropriately.
1873 (set_default_mips_dis_options): Pass ISA to above.
1874 (parse_mips_dis_option): Likewise.
1875 * mips-opc.c (EVAR6): New macro.
1876 (mips_builtin_opcodes): Add llwpe, scwpe.
1877
b83b4b13
SD		 18782019-05-01 Sudakshina Das <sudi.das@arm.com>
1879
1880 * aarch64-asm-2.c: Regenerated.
1881 * aarch64-dis-2.c: Regenerated.
1882 * aarch64-opc-2.c: Regenerated.
1883 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1884 AARCH64_OPND_TME_UIMM16.
1885 (aarch64_print_operand): Likewise.
1886 * aarch64-tbl.h (QL_IMM_NIL): New.
1887 (TME): New.
1888 (_TME_INSN): New.
1889 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1890
4a90ce95
JD		 18912019-04-29 John Darrington <john@darrington.wattle.id.au>
1892
1893 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1894
a45328b9
AB		 18952019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1896 Faraz Shahbazker <fshahbazker@wavecomp.com>
1897
1898 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1899
d10be0cb
JD		 19002019-04-24 John Darrington <john@darrington.wattle.id.au>
1901
1902 * s12z-opc.h: Add extern "C" bracketing to help
1903 users who wish to use this interface in c++ code.
1904
a679f24e
JD		 19052019-04-24 John Darrington <john@darrington.wattle.id.au>
1906
1907 * s12z-opc.c (bm_decode): Handle bit map operations with the
1908 "reserved0" mode.
1909
32c36c3c
AV		 19102019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1911
1912 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1913 specifier. Add entries for VLDR and VSTR of system registers.
1914 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1915 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1916 of %J and %K format specifier.
1917
efd6b359
AV		 19182019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1919
1920 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1921 Add new entries for VSCCLRM instruction.
1922 (print_insn_coprocessor): Handle new %C format control code.
1923
6b0dd094
AV		 19242019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1925
1926 * arm-dis.c (enum isa): New enum.
1927 (struct sopcode32): New structure.
1928 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1929 set isa field of all current entries to ANY.
1930 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1931 Only match an entry if its isa field allows the current mode.
1932
4b5a202f
AV		 19332019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1934
1935 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1936 CLRM.
1937 (print_insn_thumb32): Add logic to print %n CLRM register list.
1938
60f993ce
AV		 19392019-04-15 Sudakshina Das <sudi.das@arm.com>
1940
1941 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1942 and %Q patterns.
1943
f6b2b12d
AV		 19442019-04-15 Sudakshina Das <sudi.das@arm.com>
1945
1946 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1947 (print_insn_thumb32): Edit the switch case for %Z.
1948
1889da70
AV		 19492019-04-15 Sudakshina Das <sudi.das@arm.com>
1950
1951 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1952
65d1bc05
AV		 19532019-04-15 Sudakshina Das <sudi.das@arm.com>
1954
1955 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1956
1caf72a5
AV		 19572019-04-15 Sudakshina Das <sudi.das@arm.com>
1958
1959 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1960
f1c7f421
AV		 19612019-04-15 Sudakshina Das <sudi.das@arm.com>
1962
1963 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1964 Arm register with r13 and r15 unpredictable.
1965 (thumb32_opcodes): New instructions for bfx and bflx.
1966
4389b29a
AV		 19672019-04-15 Sudakshina Das <sudi.das@arm.com>
1968
1969 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1970
e5d6e09e
AV		 19712019-04-15 Sudakshina Das <sudi.das@arm.com>
1972
1973 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1974
e12437dc
AV		 19752019-04-15 Sudakshina Das <sudi.das@arm.com>
1976
1977 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1978
031254f2
AV		 19792019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1980
1981 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1982
e5a557ac
JD		 19832019-04-12 John Darrington <john@darrington.wattle.id.au>
1984
1985 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1986 "optr". ("operator" is a reserved word in c++).
1987
bd7ceb8d
SD		 19882019-04-11 Sudakshina Das <sudi.das@arm.com>
1989
1990 * aarch64-opc.c (aarch64_print_operand): Add case for
1991 AARCH64_OPND_Rt_SP.
1992 (verify_constraints): Likewise.
1993 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1994 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1995 to accept Rt|SP as first operand.
1996 (AARCH64_OPERANDS): Add new Rt_SP.
1997 * aarch64-asm-2.c: Regenerated.
1998 * aarch64-dis-2.c: Regenerated.
1999 * aarch64-opc-2.c: Regenerated.
2000
e54010f1
SD		 20012019-04-11 Sudakshina Das <sudi.das@arm.com>
2002
2003 * aarch64-asm-2.c: Regenerated.
2004 * aarch64-dis-2.c: Likewise.
2005 * aarch64-opc-2.c: Likewise.
2006 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2007
7e96e219
RS		 20082019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2009
2010 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2011
6f2791d5
L		 20122019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2013
2014 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2015 * i386-init.h: Regenerated.
2016
e392bad3
AM		 20172019-04-07 Alan Modra <amodra@gmail.com>
2018
2019 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2020 op_separator to control printing of spaces, comma and parens
2021 rather than need_comma, need_paren and spaces vars.
2022
dffaa15c
AM		 20232019-04-07 Alan Modra <amodra@gmail.com>
2024
2025 PR 24421
2026 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2027 (print_insn_neon, print_insn_arm): Likewise.
2028
d6aab7a1
XG		 20292019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2030
2031 * i386-dis-evex.h (evex_table): Updated to support BF16
2032 instructions.
2033 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2034 and EVEX_W_0F3872_P_3.
2035 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2036 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2037 * i386-opc.h (enum): Add CpuAVX512_BF16.
2038 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2039 * i386-opc.tbl: Add AVX512 BF16 instructions.
2040 * i386-init.h: Regenerated.
2041 * i386-tbl.h: Likewise.
2042
66e85460
AM		 20432019-04-05 Alan Modra <amodra@gmail.com>
2044
2045 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2046 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2047 to favour printing of "-" branch hint when using the "y" bit.
2048 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2049
c2b1c275
AM		 20502019-04-05 Alan Modra <amodra@gmail.com>
2051
2052 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2053 opcode until first operand is output.
2054
aae9718e
PB		 20552019-04-04 Peter Bergner <bergner@linux.ibm.com>
2056
2057 PR gas/24349
2058 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2059 (valid_bo_post_v2): Add support for 'at' branch hints.
2060 (insert_bo): Only error on branch on ctr.
2061 (get_bo_hint_mask): New function.
2062 (insert_boe): Add new 'branch_taken' formal argument. Add support
2063 for inserting 'at' branch hints.
2064 (extract_boe): Add new 'branch_taken' formal argument. Add support
2065 for extracting 'at' branch hints.
2066 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2067 (BOE): Delete operand.
2068 (BOM, BOP): New operands.
2069 (RM): Update value.
2070 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2071 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2072 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2073 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2074 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2075 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2076 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2077 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2078 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2079 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2080 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2081 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2082 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2083 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2084 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2085 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2086 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2087 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2088 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2089 bttarl+>: New extended mnemonics.
2090
96a86c01
AM		 20912019-03-28 Alan Modra <amodra@gmail.com>
2092
2093 PR 24390
2094 * ppc-opc.c (BTF): Define.
2095 (powerpc_opcodes): Use for mtfsb*.
2096 * ppc-dis.c (print_insn_powerpc): Print fields with both
2097 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2098
796d6298
TC		 20992019-03-25 Tamar Christina <tamar.christina@arm.com>
2100
2101 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2102 (mapping_symbol_for_insn): Implement new algorithm.
2103 (print_insn): Remove duplicate code.
2104
60df3720
TC		 21052019-03-25 Tamar Christina <tamar.christina@arm.com>
2106
2107 * aarch64-dis.c (print_insn_aarch64):
2108 Implement override.
2109
51457761
TC		 21102019-03-25 Tamar Christina <tamar.christina@arm.com>
2111
2112 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2113 order.
2114
53b2f36b
TC		 21152019-03-25 Tamar Christina <tamar.christina@arm.com>
2116
2117 * aarch64-dis.c (last_stop_offset): New.
2118 (print_insn_aarch64): Use stop_offset.
2119
89199bb5
L		 21202019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2121
2122 PR gas/24359
2123 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2124 CPU_ANY_AVX2_FLAGS.
2125 * i386-init.h: Regenerated.
2126
97ed31ae
L		 21272019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2128
2129 PR gas/24348
2130 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2131 vmovdqu16, vmovdqu32 and vmovdqu64.
2132 * i386-tbl.h: Regenerated.
2133
0919bfe9
AK		 21342019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2135
2136 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2137 from vstrszb, vstrszh, and vstrszf.
2138
21392019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2140
2141 * s390-opc.txt: Add instruction descriptions.
2142
21820ebe
JW		 21432019-02-08 Jim Wilson <jimw@sifive.com>
2144
2145 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2146 <bne>: Likewise.
2147
f7dd2fb2
TC		 21482019-02-07 Tamar Christina <tamar.christina@arm.com>
2149
2150 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2151
6456d318
TC		 21522019-02-07 Tamar Christina <tamar.christina@arm.com>
2153
2154 PR binutils/23212
2155 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2156 * aarch64-opc.c (verify_elem_sd): New.
2157 (fields): Add FLD_sz entr.
2158 * aarch64-tbl.h (_SIMD_INSN): New.
2159 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2160 fmulx scalar and vector by element isns.
2161
4a83b610
NC		 21622019-02-07 Nick Clifton <nickc@redhat.com>
2163
2164 * po/sv.po: Updated Swedish translation.
2165
fc60b8c8
AK		 21662019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2167
2168 * s390-mkopc.c (main): Accept arch13 as cpu string.
2169 * s390-opc.c: Add new instruction formats and instruction opcode
2170 masks.
2171 * s390-opc.txt: Add new arch13 instructions.
2172
e10620d3
TC		 21732019-01-25 Sudakshina Das <sudi.das@arm.com>
2174
2175 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2176 (aarch64_opcode): Change encoding for stg, stzg
2177 st2g and st2zg.
2178 * aarch64-asm-2.c: Regenerated.
2179 * aarch64-dis-2.c: Regenerated.
2180 * aarch64-opc-2.c: Regenerated.
2181
20a4ca55
SD		 21822019-01-25 Sudakshina Das <sudi.das@arm.com>
2183
2184 * aarch64-asm-2.c: Regenerated.
2185 * aarch64-dis-2.c: Likewise.
2186 * aarch64-opc-2.c: Likewise.
2187 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2188
550fd7bf
SD		 21892019-01-25 Sudakshina Das <sudi.das@arm.com>
2190 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2191
2192 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2193 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2194 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2195 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2196 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2197 case for ldstgv_indexed.
2198 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2199 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2200 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2201 * aarch64-asm-2.c: Regenerated.
2202 * aarch64-dis-2.c: Regenerated.
2203 * aarch64-opc-2.c: Regenerated.
2204
d9938630
NC		 22052019-01-23 Nick Clifton <nickc@redhat.com>
2206
2207 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2208
375cd423
NC		 22092019-01-21 Nick Clifton <nickc@redhat.com>
2210
2211 * po/de.po: Updated German translation.
2212 * po/uk.po: Updated Ukranian translation.
2213
57299f48
CX		 22142019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2215 * mips-dis.c (mips_arch_choices): Fix typo in
2216 gs464, gs464e and gs264e descriptors.
2217
f48dfe41
NC		 22182019-01-19 Nick Clifton <nickc@redhat.com>
2219
2220 * configure: Regenerate.
2221 * po/opcodes.pot: Regenerate.
2222
f974f26c
NC		 22232018-06-24 Nick Clifton <nickc@redhat.com>
2224
2225 2.32 branch created.
2226
39f286cd
JD		 22272019-01-09 John Darrington <john@darrington.wattle.id.au>
2228
448b8ca8
JD		 2229 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2230 if it is null.
2231 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2232 zero.
2233
3107326d
AP		 22342019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2235
2236 * configure: Regenerate.
2237
7e9ca91e
AM		 22382019-01-07 Alan Modra <amodra@gmail.com>
2239
2240 * configure: Regenerate.
2241 * po/POTFILES.in: Regenerate.
2242
ef1ad42b
JD		 22432019-01-03 John Darrington <john@darrington.wattle.id.au>
2244
2245 * s12z-opc.c: New file.
2246 * s12z-opc.h: New file.
2247 * s12z-dis.c: Removed all code not directly related to display
2248 of instructions. Used the interface provided by the new files
2249 instead.
2250 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2251 * Makefile.in: Regenerate.
ef1ad42b 2252 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2253 * configure: Regenerate.
ef1ad42b 2254
82704155
AM		 22552019-01-01 Alan Modra <amodra@gmail.com>
2256
2257 Update year range in copyright notice of all files.
2258
d5c04e1b 2259For older changes see ChangeLog-2018
3499769a 2260\f
d5c04e1b 2261Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2262
2263Copying and distribution of this file, with or without modification,
2264are permitted in any medium without royalty provided the copyright
2265notice and this notice are preserved.
2266
2267Local Variables:
2268mode: change-log
2269left-margin: 8
2270fill-column: 74
2271version-control: never
2272End:
GDB Binutils - Deliverables
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