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drm/i915: rip out intel_disable_pch_ports
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
a0c4da24
JB		 101static bool
102intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
021357ac
CW		 106static inline u32 /* units of 100MHz */
107intel_fdi_link_freq(struct drm_device *dev)
108{
8b99e68c
CW		 109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
021357ac
CW		 114}
115
e4b36699 116static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
d4906093 127 .find_pll = intel_find_best_PLL,
e4b36699
KP		 128};
129
130static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
d4906093 141 .find_pll = intel_find_best_PLL,
e4b36699 142};
273e27ca 143
e4b36699 144static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
d4906093 155 .find_pll = intel_find_best_PLL,
e4b36699
KP		 156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
d4906093 169 .find_pll = intel_find_best_PLL,
e4b36699
KP		 170};
171
273e27ca 172
e4b36699 173static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
044c7c41 185 },
d4906093 186 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 187};
188
189static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
d4906093 200 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 201};
202
203static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
044c7c41 214 },
d4906093 215 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 216};
217
218static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
044c7c41 229 },
d4906093 230 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 231};
232
233static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
273e27ca 243 .p2_slow = 10, .p2_fast = 10 },
0206e353 244 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 245};
246
f2b115e6 247static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 250 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
273e27ca 253 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
6115707b 260 .find_pll = intel_find_best_PLL,
e4b36699
KP		 261};
262
f2b115e6 263static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
6115707b 274 .find_pll = intel_find_best_PLL,
e4b36699
KP		 275};
276
273e27ca
EA		 277/* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
b91ad0ec 282static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
4547668a 293 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 294};
295
b91ad0ec 296static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 307 .find_pll = intel_g4x_find_best_PLL,
308};
309
310static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 321 .find_pll = intel_g4x_find_best_PLL,
322};
323
273e27ca 324/* LVDS 100mhz refclk limits. */
b91ad0ec 325static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
0206e353 333 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 336 .find_pll = intel_g4x_find_best_PLL,
337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
0206e353 347 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 350 .find_pll = intel_g4x_find_best_PLL,
351};
352
353static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
273e27ca 363 .p2_slow = 10, .p2_fast = 10 },
0206e353 364 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 365};
366
a0c4da24
JB		 367static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379};
380
381static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393};
394
395static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407};
408
57f350b6
JB		 409u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410{
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432}
433
a0c4da24
JB		 434static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436{
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454}
455
57f350b6
JB		 456static void vlv_init_dpio(struct drm_device *dev)
457{
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465}
466
618563e3
DV		 467static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468{
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471}
472
473static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483};
484
b0354385
TI		 485static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487{
488 unsigned int val;
489
121d527a
TI		 490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
618563e3
DV		 494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
b0354385
TI		 497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
14d94a3d 506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511}
512
1b894b59
CW		 513static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
2c07245f 515{
b91ad0ec
ZW		 516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 518 const intel_limit_t *limit;
b91ad0ec
ZW		 519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 522 /* LVDS dual channel */
1b894b59 523 if (refclk == 100000)
b91ad0ec
ZW		 524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
1b894b59 528 if (refclk == 100000)
b91ad0ec
ZW		 529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
2c07245f 536 else
b91ad0ec 537 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 538
539 return limit;
540}
541
044c7c41
ML		 542static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543{
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 549 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 550 /* LVDS with dual channel */
e4b36699 551 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 552 else
553 /* LVDS with dual channel */
e4b36699 554 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 557 limit = &intel_limits_g4x_hdmi;
044c7c41 558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 559 limit = &intel_limits_g4x_sdvo;
0206e353 560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 561 limit = &intel_limits_g4x_display_port;
044c7c41 562 } else /* The option is for other outputs */
e4b36699 563 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 564
565 return limit;
566}
567
1b894b59 568static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 569{
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
bad720ff 573 if (HAS_PCH_SPLIT(dev))
1b894b59 574 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 575 else if (IS_G4X(dev)) {
044c7c41 576 limit = intel_g4x_limit(crtc);
f2b115e6 577 } else if (IS_PINEVIEW(dev)) {
2177832f 578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 579 limit = &intel_limits_pineview_lvds;
2177832f 580 else
f2b115e6 581 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 596 limit = &intel_limits_i8xx_lvds;
79e53945 597 else
e4b36699 598 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 599 }
600 return limit;
601}
602
f2b115e6
AJ		 603/* m1 is reserved as 0 in Pineview, n is a ring counter */
604static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 605{
2177832f
SL		 606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610}
611
612static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613{
f2b115e6
AJ		 614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
2177832f
SL		 616 return;
617 }
79e53945
JB		 618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622}
623
79e53945
JB		 624/**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
4ef69c7a 627bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 628{
4ef69c7a 629 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 630 struct intel_encoder *encoder;
631
6c2b7c12
DV		 632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
4ef69c7a
CW		 634 return true;
635
636 return false;
79e53945
JB		 637}
638
7c04d1d9 639#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 640/**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
1b894b59
CW		 645static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
79e53945 648{
79e53945 649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 650 INTELPllInvalid("p1 out of range\n");
79e53945 651 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 652 INTELPllInvalid("p out of range\n");
79e53945 653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 654 INTELPllInvalid("m2 out of range\n");
79e53945 655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 656 INTELPllInvalid("m1 out of range\n");
f2b115e6 657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 658 INTELPllInvalid("m1 <= m2\n");
79e53945 659 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 660 INTELPllInvalid("m out of range\n");
79e53945 661 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 662 INTELPllInvalid("n out of range\n");
79e53945 663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 664 INTELPllInvalid("vco out of range\n");
79e53945
JB		 665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 669 INTELPllInvalid("dot out of range\n");
79e53945
JB		 670
671 return true;
672}
673
d4906093
ML		 674static bool
675intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
d4906093 678
79e53945
JB		 679{
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
79e53945
JB		 683 int err = target;
684
bc5e5718 685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 686 (I915_READ(LVDS)) != 0) {
79e53945
JB		 687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
b0354385 693 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
0206e353 704 memset(best_clock, 0, sizeof(*best_clock));
79e53945 705
42158660
ZY		 706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 717 int this_err;
718
2177832f 719 intel_clock(dev, refclk, &clock);
1b894b59
CW		 720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
79e53945 722 continue;
cec2f356
SP		 723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
79e53945
JB		 726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738}
739
d4906093
ML		 740static bool
741intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
d4906093
ML		 744{
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
6ba770dc
AJ		 750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 755 int lvds_reg;
756
c619eed4 757 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
f77f13e2 775 /* based on hardware requirement, prefer smaller n to precision */
d4906093 776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 777 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
2177832f 786 intel_clock(dev, refclk, &clock);
1b894b59
CW		 787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
d4906093 789 continue;
cec2f356
SP		 790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
1b894b59
CW		 793
794 this_err = abs(clock.dot - target);
d4906093
ML		 795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
2c07245f
ZW		 805 return found;
806}
807
5eb08b69 808static bool
f2b115e6 809intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
5eb08b69
ZW		 812{
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
4547668a 815
5eb08b69
ZW		 816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832}
833
a4fc5ed6
KP		 834/* DisplayPort has only two frequencies, 162MHz and 270MHz */
835static bool
836intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
a4fc5ed6 839{
5eddb70b
CW		 840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
a4fc5ed6 860}
a0c4da24
JB		 861static bool
862intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865{
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
af447bd3 872 flag = 0;
a0c4da24
JB		 873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928}
a4fc5ed6 929
a928d536
PZ		 930static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931{
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939}
940
9d0498a2
JB		 941/**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 950{
9d0498a2 951 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 952 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 953
a928d536
PZ		 954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
300387c0
CW		 959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
9d0498a2 975 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
9d0498a2
JB		 979 DRM_DEBUG_KMS("vblank wait timed out\n");
980}
981
ab7ad7f6
KP		 982/*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
ab7ad7f6
KP		 991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
58e10eb9 997 *
9d0498a2 998 */
58e10eb9 999void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1000{
1001 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 1002
1003 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 1004 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 1005
1006 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
284637d9 1009 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1010 } else {
837ba00f 1011 u32 last_line, line_mask;
58e10eb9 1012 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
837ba00f
PZ		 1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
ab7ad7f6
KP		 1020 /* Wait for the display line to settle */
1021 do {
837ba00f 1022 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1023 mdelay(5);
837ba00f 1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
284637d9 1027 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1028 }
79e53945
JB		 1029}
1030
b24e7179
JB		 1031static const char *state_string(bool enabled)
1032{
1033 return enabled ? "on" : "off";
1034}
1035
1036/* Only for pre-ILK configs */
1037static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039{
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050}
1051#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
040484af
JB		 1054/* For ILK+ */
1055static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
040484af 1059{
040484af
JB		 1060 u32 val;
1061 bool cur_state;
1062
9d82aa17
ED		 1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
92b27b08
CW		 1068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1070 return;
ee7b9f93 1071
92b27b08
CW		 1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
d3ccbe86 1095 }
040484af 1096}
92b27b08
CW		 1097#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1099
1100static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102{
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
bf507ef7
ED		 1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
040484af
JB		 1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
1121#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126{
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
59c859d6
ED		 1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
040484af
JB		 1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142}
1143#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
bf507ef7
ED		 1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
040484af
JB		 1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163}
1164
1165static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
1168 int reg;
1169 u32 val;
1170
59c859d6
ED		 1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
040484af
JB		 1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178}
1179
ea0760cf
JB		 1180static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182{
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
0de3b485 1186 bool locked = true;
ea0760cf
JB		 1187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1206 pipe_name(pipe));
ea0760cf
JB		 1207}
1208
b840d907
JB		 1209void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
b24e7179
JB		 1211{
1212 int reg;
1213 u32 val;
63d7bbe9 1214 bool cur_state;
b24e7179 1215
8e636784
DV		 1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
b24e7179
JB		 1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
63d7bbe9
JB		 1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1225 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1226}
1227
931872fc
CW		 1228static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
b24e7179
JB		 1230{
1231 int reg;
1232 u32 val;
931872fc 1233 bool cur_state;
b24e7179
JB		 1234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
931872fc
CW		 1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1241}
1242
931872fc
CW		 1243#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
b24e7179
JB		 1246static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248{
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
19ec1358 1253 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
19ec1358 1260 return;
28c05794 1261 }
19ec1358 1262
b24e7179
JB		 1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1272 }
1273}
1274
92f2584a
JB		 1275static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276{
1277 u32 val;
1278 bool enabled;
1279
9d82aa17
ED		 1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
92f2584a
JB		 1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289}
1290
1291static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
92f2584a
JB		 1304}
1305
4e634389
KP		 1306static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1308{
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322}
1323
1519b995
KP		 1324static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326{
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338}
1339
1340static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369}
1370
291906f1 1371static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1372 enum pipe pipe, int reg, u32 port_sel)
291906f1 1373{
47a05eca 1374 u32 val = I915_READ(reg);
4e634389 1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1377 reg, pipe_name(pipe));
de9a35ab
DV		 1378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1381}
1382
1383static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, int reg)
1385{
47a05eca 1386 u32 val = I915_READ(reg);
e9a851ed 1387 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1389 reg, pipe_name(pipe));
de9a35ab
DV		 1390
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1393}
1394
1395static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397{
1398 int reg;
1399 u32 val;
291906f1 1400
f0575e92
KP		 1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1404
1405 reg = PCH_ADPA;
1406 val = I915_READ(reg);
e9a851ed 1407 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1408 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1409 pipe_name(pipe));
291906f1
JB		 1410
1411 reg = PCH_LVDS;
1412 val = I915_READ(reg);
e9a851ed 1413 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 pipe_name(pipe));
291906f1
JB		 1416
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420}
1421
63d7bbe9
JB		 1422/**
1423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1426 *
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1430 *
1431 * Note! This is for pre-ILK only.
7434a255
TR		 1432 *
1433 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1434 */
a37b9b34 1435static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1436{
1437 int reg;
1438 u32 val;
1439
1440 /* No really, not for ILK+ */
a0c4da24 1441 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1442
1443 /* PLL is protected by panel, make sure we can write it */
1444 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445 assert_panel_unlocked(dev_priv, pipe);
1446
1447 reg = DPLL(pipe);
1448 val = I915_READ(reg);
1449 val |= DPLL_VCO_ENABLE;
1450
1451 /* We do this three times for luck */
1452 I915_WRITE(reg, val);
1453 POSTING_READ(reg);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg, val);
1456 POSTING_READ(reg);
1457 udelay(150); /* wait for warmup */
1458 I915_WRITE(reg, val);
1459 POSTING_READ(reg);
1460 udelay(150); /* wait for warmup */
1461}
1462
1463/**
1464 * intel_disable_pll - disable a PLL
1465 * @dev_priv: i915 private structure
1466 * @pipe: pipe PLL to disable
1467 *
1468 * Disable the PLL for @pipe, making sure the pipe is off first.
1469 *
1470 * Note! This is for pre-ILK only.
1471 */
1472static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473{
1474 int reg;
1475 u32 val;
1476
1477 /* Don't disable pipe A or pipe A PLLs if needed */
1478 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479 return;
1480
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val &= ~DPLL_VCO_ENABLE;
1487 I915_WRITE(reg, val);
1488 POSTING_READ(reg);
1489}
1490
a416edef
ED		 1491/* SBI access */
1492static void
1493intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494{
1495 unsigned long flags;
1496
1497 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1498 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1499 100)) {
1500 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501 goto out_unlock;
1502 }
1503
1504 I915_WRITE(SBI_ADDR,
1505 (reg << 16));
1506 I915_WRITE(SBI_DATA,
1507 value);
1508 I915_WRITE(SBI_CTL_STAT,
1509 SBI_BUSY |
1510 SBI_CTL_OP_CRWR);
1511
39fb50f6 1512 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1513 100)) {
1514 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515 goto out_unlock;
1516 }
1517
1518out_unlock:
1519 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520}
1521
1522static u32
1523intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524{
1525 unsigned long flags;
39fb50f6 1526 u32 value = 0;
a416edef
ED		 1527
1528 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1529 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1530 100)) {
1531 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532 goto out_unlock;
1533 }
1534
1535 I915_WRITE(SBI_ADDR,
1536 (reg << 16));
1537 I915_WRITE(SBI_CTL_STAT,
1538 SBI_BUSY |
1539 SBI_CTL_OP_CRRD);
1540
39fb50f6 1541 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1542 100)) {
1543 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544 goto out_unlock;
1545 }
1546
1547 value = I915_READ(SBI_DATA);
1548
1549out_unlock:
1550 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551 return value;
1552}
1553
92f2584a
JB		 1554/**
1555 * intel_enable_pch_pll - enable PCH PLL
1556 * @dev_priv: i915 private structure
1557 * @pipe: pipe PLL to enable
1558 *
1559 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560 * drives the transcoder clock.
1561 */
ee7b9f93 1562static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1563{
ee7b9f93 1564 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1565 struct intel_pch_pll *pll;
92f2584a
JB		 1566 int reg;
1567 u32 val;
1568
48da64a8 1569 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1570 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1571 pll = intel_crtc->pch_pll;
1572 if (pll == NULL)
1573 return;
1574
1575 if (WARN_ON(pll->refcount == 0))
1576 return;
ee7b9f93
JB		 1577
1578 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579 pll->pll_reg, pll->active, pll->on,
1580 intel_crtc->base.base.id);
92f2584a
JB		 1581
1582 /* PCH refclock must be enabled first */
1583 assert_pch_refclk_enabled(dev_priv);
1584
ee7b9f93 1585 if (pll->active++ && pll->on) {
92b27b08 1586 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1587 return;
1588 }
1589
1590 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592 reg = pll->pll_reg;
92f2584a
JB		 1593 val = I915_READ(reg);
1594 val |= DPLL_VCO_ENABLE;
1595 I915_WRITE(reg, val);
1596 POSTING_READ(reg);
1597 udelay(200);
ee7b9f93
JB		 1598
1599 pll->on = true;
92f2584a
JB		 1600}
1601
ee7b9f93 1602static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1603{
ee7b9f93
JB		 1604 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1606 int reg;
ee7b9f93 1607 u32 val;
4c609cb8 1608
92f2584a
JB		 1609 /* PCH only available on ILK+ */
1610 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1611 if (pll == NULL)
1612 return;
92f2584a 1613
48da64a8
CW		 1614 if (WARN_ON(pll->refcount == 0))
1615 return;
7a419866 1616
ee7b9f93
JB		 1617 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618 pll->pll_reg, pll->active, pll->on,
1619 intel_crtc->base.base.id);
7a419866 1620
48da64a8 1621 if (WARN_ON(pll->active == 0)) {
92b27b08 1622 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1623 return;
1624 }
1625
ee7b9f93 1626 if (--pll->active) {
92b27b08 1627 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1628 return;
ee7b9f93
JB		 1629 }
1630
1631 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1632
1633 /* Make sure transcoder isn't still depending on us */
1634 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1635
ee7b9f93 1636 reg = pll->pll_reg;
92f2584a
JB		 1637 val = I915_READ(reg);
1638 val &= ~DPLL_VCO_ENABLE;
1639 I915_WRITE(reg, val);
1640 POSTING_READ(reg);
1641 udelay(200);
ee7b9f93
JB		 1642
1643 pll->on = false;
92f2584a
JB		 1644}
1645
040484af
JB		 1646static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647 enum pipe pipe)
1648{
1649 int reg;
5f7f726d 1650 u32 val, pipeconf_val;
7c26e5c6 1651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1652
1653 /* PCH only available on ILK+ */
1654 BUG_ON(dev_priv->info->gen < 5);
1655
1656 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1657 assert_pch_pll_enabled(dev_priv,
1658 to_intel_crtc(crtc)->pch_pll,
1659 to_intel_crtc(crtc));
040484af
JB		 1660
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1664
59c859d6
ED		 1665 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667 return;
1668 }
040484af
JB		 1669 reg = TRANSCONF(pipe);
1670 val = I915_READ(reg);
5f7f726d 1671 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1672
1673 if (HAS_PCH_IBX(dev_priv->dev)) {
1674 /*
1675 * make the BPC in transcoder be consistent with
1676 * that in pipeconf reg.
1677 */
1678 val &= ~PIPE_BPC_MASK;
5f7f726d 1679 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1680 }
5f7f726d
PZ		 1681
1682 val &= ~TRANS_INTERLACE_MASK;
1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1684 if (HAS_PCH_IBX(dev_priv->dev) &&
1685 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686 val |= TRANS_LEGACY_INTERLACED_ILK;
1687 else
1688 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1689 else
1690 val |= TRANS_PROGRESSIVE;
1691
040484af
JB		 1692 I915_WRITE(reg, val | TRANS_ENABLE);
1693 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695}
1696
1697static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698 enum pipe pipe)
1699{
1700 int reg;
1701 u32 val;
1702
1703 /* FDI relies on the transcoder */
1704 assert_fdi_tx_disabled(dev_priv, pipe);
1705 assert_fdi_rx_disabled(dev_priv, pipe);
1706
291906f1
JB		 1707 /* Ports must be off as well */
1708 assert_pch_ports_disabled(dev_priv, pipe);
1709
040484af
JB		 1710 reg = TRANSCONF(pipe);
1711 val = I915_READ(reg);
1712 val &= ~TRANS_ENABLE;
1713 I915_WRITE(reg, val);
1714 /* wait for PCH transcoder off, transcoder state */
1715 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1716 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1717}
1718
b24e7179 1719/**
309cfea8 1720 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1721 * @dev_priv: i915 private structure
1722 * @pipe: pipe to enable
040484af 1723 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1724 *
1725 * Enable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727 *
1728 * @pipe should be %PIPE_A or %PIPE_B.
1729 *
1730 * Will wait until the pipe is actually running (i.e. first vblank) before
1731 * returning.
1732 */
040484af
JB		 1733static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734 bool pch_port)
b24e7179
JB		 1735{
1736 int reg;
1737 u32 val;
1738
1739 /*
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 * need the check.
1743 */
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1746 else {
1747 if (pch_port) {
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751 }
1752 /* FIXME: assert CPU port conditions for SNB+ */
1753 }
b24e7179
JB		 1754
1755 reg = PIPECONF(pipe);
1756 val = I915_READ(reg);
00d70b15
CW		 1757 if (val & PIPECONF_ENABLE)
1758 return;
1759
1760 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1761 intel_wait_for_vblank(dev_priv->dev, pipe);
1762}
1763
1764/**
309cfea8 1765 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe to disable
1768 *
1769 * Disable @pipe, making sure that various hardware specific requirements
1770 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771 *
1772 * @pipe should be %PIPE_A or %PIPE_B.
1773 *
1774 * Will wait until the pipe has shut down before returning.
1775 */
1776static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777 enum pipe pipe)
1778{
1779 int reg;
1780 u32 val;
1781
1782 /*
1783 * Make sure planes won't keep trying to pump pixels to us,
1784 * or we might hang the display.
1785 */
1786 assert_planes_disabled(dev_priv, pipe);
1787
1788 /* Don't disable pipe A or pipe A PLLs if needed */
1789 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790 return;
1791
1792 reg = PIPECONF(pipe);
1793 val = I915_READ(reg);
00d70b15
CW		 1794 if ((val & PIPECONF_ENABLE) == 0)
1795 return;
1796
1797 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1798 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799}
1800
d74362c9
KP		 1801/*
1802 * Plane regs are double buffered, going from enabled->disabled needs a
1803 * trigger in order to latch. The display address reg provides this.
1804 */
6f1d69b0 1805void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1806 enum plane plane)
1807{
1808 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810}
1811
b24e7179
JB		 1812/**
1813 * intel_enable_plane - enable a display plane on a given pipe
1814 * @dev_priv: i915 private structure
1815 * @plane: plane to enable
1816 * @pipe: pipe being fed
1817 *
1818 * Enable @plane on @pipe, making sure that @pipe is running first.
1819 */
1820static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane, enum pipe pipe)
1822{
1823 int reg;
1824 u32 val;
1825
1826 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827 assert_pipe_enabled(dev_priv, pipe);
1828
1829 reg = DSPCNTR(plane);
1830 val = I915_READ(reg);
00d70b15
CW		 1831 if (val & DISPLAY_PLANE_ENABLE)
1832 return;
1833
1834 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1835 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1836 intel_wait_for_vblank(dev_priv->dev, pipe);
1837}
1838
b24e7179
JB		 1839/**
1840 * intel_disable_plane - disable a display plane
1841 * @dev_priv: i915 private structure
1842 * @plane: plane to disable
1843 * @pipe: pipe consuming the data
1844 *
1845 * Disable @plane; should be an independent operation.
1846 */
1847static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848 enum plane plane, enum pipe pipe)
1849{
1850 int reg;
1851 u32 val;
1852
1853 reg = DSPCNTR(plane);
1854 val = I915_READ(reg);
00d70b15
CW		 1855 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856 return;
1857
1858 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1859 intel_flush_display_plane(dev_priv, plane);
1860 intel_wait_for_vblank(dev_priv->dev, pipe);
1861}
1862
127bd2ac 1863int
48b956c5 1864intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1865 struct drm_i915_gem_object *obj,
919926ae 1866 struct intel_ring_buffer *pipelined)
6b95a207 1867{
ce453d81 1868 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1869 u32 alignment;
1870 int ret;
1871
05394f39 1872 switch (obj->tiling_mode) {
6b95a207 1873 case I915_TILING_NONE:
534843da
CW		 1874 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1875 alignment = 128 * 1024;
a6c45cf0 1876 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1877 alignment = 4 * 1024;
1878 else
1879 alignment = 64 * 1024;
6b95a207
KH		 1880 break;
1881 case I915_TILING_X:
1882 /* pin() will align the object as required by fence */
1883 alignment = 0;
1884 break;
1885 case I915_TILING_Y:
1886 /* FIXME: Is this true? */
1887 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1888 return -EINVAL;
1889 default:
1890 BUG();
1891 }
1892
ce453d81 1893 dev_priv->mm.interruptible = false;
2da3b9b9 1894 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1895 if (ret)
ce453d81 1896 goto err_interruptible;
6b95a207
KH		 1897
1898 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1899 * fence, whereas 965+ only requires a fence if using
1900 * framebuffer compression. For simplicity, we always install
1901 * a fence as the cost is not that onerous.
1902 */
06d98131 1903 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1904 if (ret)
1905 goto err_unpin;
1690e1eb 1906
9a5a53b3 1907 i915_gem_object_pin_fence(obj);
6b95a207 1908
ce453d81 1909 dev_priv->mm.interruptible = true;
6b95a207 1910 return 0;
48b956c5
CW		 1911
1912err_unpin:
1913 i915_gem_object_unpin(obj);
ce453d81
CW		 1914err_interruptible:
1915 dev_priv->mm.interruptible = true;
48b956c5 1916 return ret;
6b95a207
KH		 1917}
1918
1690e1eb
CW		 1919void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1920{
1921 i915_gem_object_unpin_fence(obj);
1922 i915_gem_object_unpin(obj);
1923}
1924
c2c75131
DV		 1925/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1926 * is assumed to be a power-of-two. */
1927static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1928 unsigned int bpp,
1929 unsigned int pitch)
1930{
1931 int tile_rows, tiles;
1932
1933 tile_rows = *y / 8;
1934 *y %= 8;
1935 tiles = *x / (512/bpp);
1936 *x %= 512/bpp;
1937
1938 return tile_rows * pitch * 8 + tiles * 4096;
1939}
1940
17638cd6
JB		 1941static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1942 int x, int y)
81255565
JB		 1943{
1944 struct drm_device *dev = crtc->dev;
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1947 struct intel_framebuffer *intel_fb;
05394f39 1948 struct drm_i915_gem_object *obj;
81255565 1949 int plane = intel_crtc->plane;
e506a0c6 1950 unsigned long linear_offset;
81255565 1951 u32 dspcntr;
5eddb70b 1952 u32 reg;
81255565
JB		 1953
1954 switch (plane) {
1955 case 0:
1956 case 1:
1957 break;
1958 default:
1959 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1960 return -EINVAL;
1961 }
1962
1963 intel_fb = to_intel_framebuffer(fb);
1964 obj = intel_fb->obj;
81255565 1965
5eddb70b
CW		 1966 reg = DSPCNTR(plane);
1967 dspcntr = I915_READ(reg);
81255565
JB		 1968 /* Mask out pixel format bits in case we change it */
1969 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1970 switch (fb->bits_per_pixel) {
1971 case 8:
1972 dspcntr |= DISPPLANE_8BPP;
1973 break;
1974 case 16:
1975 if (fb->depth == 15)
1976 dspcntr |= DISPPLANE_15_16BPP;
1977 else
1978 dspcntr |= DISPPLANE_16BPP;
1979 break;
1980 case 24:
1981 case 32:
1982 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1983 break;
1984 default:
17638cd6 1985 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 1986 return -EINVAL;
1987 }
a6c45cf0 1988 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1989 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1990 dspcntr |= DISPPLANE_TILED;
1991 else
1992 dspcntr &= ~DISPPLANE_TILED;
1993 }
1994
5eddb70b 1995 I915_WRITE(reg, dspcntr);
81255565 1996
e506a0c6 1997 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1998
c2c75131
DV		 1999 if (INTEL_INFO(dev)->gen >= 4) {
2000 intel_crtc->dspaddr_offset =
2001 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2002 fb->bits_per_pixel / 8,
2003 fb->pitches[0]);
2004 linear_offset -= intel_crtc->dspaddr_offset;
2005 } else {
e506a0c6 2006 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2007 }
e506a0c6
DV		 2008
2009 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2010 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2011 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2012 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2013 I915_MODIFY_DISPBASE(DSPSURF(plane),
2014 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2015 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2016 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2017 } else
e506a0c6 2018 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2019 POSTING_READ(reg);
81255565 2020
17638cd6
JB		 2021 return 0;
2022}
2023
2024static int ironlake_update_plane(struct drm_crtc *crtc,
2025 struct drm_framebuffer *fb, int x, int y)
2026{
2027 struct drm_device *dev = crtc->dev;
2028 struct drm_i915_private *dev_priv = dev->dev_private;
2029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2030 struct intel_framebuffer *intel_fb;
2031 struct drm_i915_gem_object *obj;
2032 int plane = intel_crtc->plane;
e506a0c6 2033 unsigned long linear_offset;
17638cd6
JB		 2034 u32 dspcntr;
2035 u32 reg;
2036
2037 switch (plane) {
2038 case 0:
2039 case 1:
27f8227b 2040 case 2:
17638cd6
JB		 2041 break;
2042 default:
2043 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2044 return -EINVAL;
2045 }
2046
2047 intel_fb = to_intel_framebuffer(fb);
2048 obj = intel_fb->obj;
2049
2050 reg = DSPCNTR(plane);
2051 dspcntr = I915_READ(reg);
2052 /* Mask out pixel format bits in case we change it */
2053 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2054 switch (fb->bits_per_pixel) {
2055 case 8:
2056 dspcntr |= DISPPLANE_8BPP;
2057 break;
2058 case 16:
2059 if (fb->depth != 16)
2060 return -EINVAL;
2061
2062 dspcntr |= DISPPLANE_16BPP;
2063 break;
2064 case 24:
2065 case 32:
2066 if (fb->depth == 24)
2067 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2068 else if (fb->depth == 30)
2069 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2070 else
2071 return -EINVAL;
2072 break;
2073 default:
2074 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2075 return -EINVAL;
2076 }
2077
2078 if (obj->tiling_mode != I915_TILING_NONE)
2079 dspcntr |= DISPPLANE_TILED;
2080 else
2081 dspcntr &= ~DISPPLANE_TILED;
2082
2083 /* must disable */
2084 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2085
2086 I915_WRITE(reg, dspcntr);
2087
e506a0c6 2088 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131
DV		 2089 intel_crtc->dspaddr_offset =
2090 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2091 fb->bits_per_pixel / 8,
2092 fb->pitches[0]);
2093 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2094
e506a0c6
DV		 2095 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2096 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2097 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2098 I915_MODIFY_DISPBASE(DSPSURF(plane),
2099 obj->gtt_offset + intel_crtc->dspaddr_offset);
17638cd6 2100 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2101 I915_WRITE(DSPLINOFF(plane), linear_offset);
17638cd6
JB		 2102 POSTING_READ(reg);
2103
2104 return 0;
2105}
2106
2107/* Assume fb object is pinned & idle & fenced and just update base pointers */
2108static int
2109intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2110 int x, int y, enum mode_set_atomic state)
2111{
2112 struct drm_device *dev = crtc->dev;
2113 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2114
6b8e6ed0
CW		 2115 if (dev_priv->display.disable_fbc)
2116 dev_priv->display.disable_fbc(dev);
3dec0095 2117 intel_increase_pllclock(crtc);
81255565 2118
6b8e6ed0 2119 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2120}
2121
14667a4b
CW		 2122static int
2123intel_finish_fb(struct drm_framebuffer *old_fb)
2124{
2125 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2126 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2127 bool was_interruptible = dev_priv->mm.interruptible;
2128 int ret;
2129
2130 wait_event(dev_priv->pending_flip_queue,
2131 atomic_read(&dev_priv->mm.wedged) ||
2132 atomic_read(&obj->pending_flip) == 0);
2133
2134 /* Big Hammer, we also need to ensure that any pending
2135 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2136 * current scanout is retired before unpinning the old
2137 * framebuffer.
2138 *
2139 * This should only fail upon a hung GPU, in which case we
2140 * can safely continue.
2141 */
2142 dev_priv->mm.interruptible = false;
2143 ret = i915_gem_object_finish_gpu(obj);
2144 dev_priv->mm.interruptible = was_interruptible;
2145
2146 return ret;
2147}
2148
5c3b82e2 2149static int
3c4fdcfb 2150intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2151 struct drm_framebuffer *fb)
79e53945
JB		 2152{
2153 struct drm_device *dev = crtc->dev;
6b8e6ed0 2154 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2155 struct drm_i915_master_private *master_priv;
2156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2157 struct drm_framebuffer *old_fb;
5c3b82e2 2158 int ret;
79e53945
JB		 2159
2160 /* no fb bound */
94352cf9 2161 if (!fb) {
a5071c2f 2162 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2163 return 0;
2164 }
2165
5826eca5
ED		 2166 if(intel_crtc->plane > dev_priv->num_pipe) {
2167 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2168 intel_crtc->plane,
2169 dev_priv->num_pipe);
5c3b82e2 2170 return -EINVAL;
79e53945
JB		 2171 }
2172
5c3b82e2 2173 mutex_lock(&dev->struct_mutex);
265db958 2174 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2175 to_intel_framebuffer(fb)->obj,
919926ae 2176 NULL);
5c3b82e2
CW		 2177 if (ret != 0) {
2178 mutex_unlock(&dev->struct_mutex);
a5071c2f 2179 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2180 return ret;
2181 }
79e53945 2182
94352cf9
DV		 2183 if (crtc->fb)
2184 intel_finish_fb(crtc->fb);
265db958 2185
94352cf9 2186 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2187 if (ret) {
94352cf9 2188 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2189 mutex_unlock(&dev->struct_mutex);
a5071c2f 2190 DRM_ERROR("failed to update base address\n");
4e6cfefc 2191 return ret;
79e53945 2192 }
3c4fdcfb 2193
94352cf9
DV		 2194 old_fb = crtc->fb;
2195 crtc->fb = fb;
6c4c86f5
DV		 2196 crtc->x = x;
2197 crtc->y = y;
94352cf9 2198
b7f1de28
CW		 2199 if (old_fb) {
2200 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2201 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2202 }
652c393a 2203
6b8e6ed0 2204 intel_update_fbc(dev);
5c3b82e2 2205 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2206
2207 if (!dev->primary->master)
5c3b82e2 2208 return 0;
79e53945
JB		 2209
2210 master_priv = dev->primary->master->driver_priv;
2211 if (!master_priv->sarea_priv)
5c3b82e2 2212 return 0;
79e53945 2213
265db958 2214 if (intel_crtc->pipe) {
79e53945
JB		 2215 master_priv->sarea_priv->pipeB_x = x;
2216 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2217 } else {
2218 master_priv->sarea_priv->pipeA_x = x;
2219 master_priv->sarea_priv->pipeA_y = y;
79e53945 2220 }
5c3b82e2
CW		 2221
2222 return 0;
79e53945
JB		 2223}
2224
5eddb70b 2225static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2226{
2227 struct drm_device *dev = crtc->dev;
2228 struct drm_i915_private *dev_priv = dev->dev_private;
2229 u32 dpa_ctl;
2230
28c97730 2231 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2232 dpa_ctl = I915_READ(DP_A);
2233 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2234
2235 if (clock < 200000) {
2236 u32 temp;
2237 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2238 /* workaround for 160Mhz:
2239 1) program 0x4600c bits 15:0 = 0x8124
2240 2) program 0x46010 bit 0 = 1
2241 3) program 0x46034 bit 24 = 1
2242 4) program 0x64000 bit 14 = 1
2243 */
2244 temp = I915_READ(0x4600c);
2245 temp &= 0xffff0000;
2246 I915_WRITE(0x4600c, temp | 0x8124);
2247
2248 temp = I915_READ(0x46010);
2249 I915_WRITE(0x46010, temp | 1);
2250
2251 temp = I915_READ(0x46034);
2252 I915_WRITE(0x46034, temp | (1 << 24));
2253 } else {
2254 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2255 }
2256 I915_WRITE(DP_A, dpa_ctl);
2257
5eddb70b 2258 POSTING_READ(DP_A);
32f9d658
ZW		 2259 udelay(500);
2260}
2261
5e84e1a4
ZW		 2262static void intel_fdi_normal_train(struct drm_crtc *crtc)
2263{
2264 struct drm_device *dev = crtc->dev;
2265 struct drm_i915_private *dev_priv = dev->dev_private;
2266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2267 int pipe = intel_crtc->pipe;
2268 u32 reg, temp;
2269
2270 /* enable normal train */
2271 reg = FDI_TX_CTL(pipe);
2272 temp = I915_READ(reg);
61e499bf 2273 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2274 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2275 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2276 } else {
2277 temp &= ~FDI_LINK_TRAIN_NONE;
2278 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2279 }
5e84e1a4
ZW		 2280 I915_WRITE(reg, temp);
2281
2282 reg = FDI_RX_CTL(pipe);
2283 temp = I915_READ(reg);
2284 if (HAS_PCH_CPT(dev)) {
2285 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2286 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2287 } else {
2288 temp &= ~FDI_LINK_TRAIN_NONE;
2289 temp |= FDI_LINK_TRAIN_NONE;
2290 }
2291 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2292
2293 /* wait one idle pattern time */
2294 POSTING_READ(reg);
2295 udelay(1000);
357555c0
JB		 2296
2297 /* IVB wants error correction enabled */
2298 if (IS_IVYBRIDGE(dev))
2299 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2300 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2301}
2302
291427f5
JB		 2303static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2304{
2305 struct drm_i915_private *dev_priv = dev->dev_private;
2306 u32 flags = I915_READ(SOUTH_CHICKEN1);
2307
2308 flags |= FDI_PHASE_SYNC_OVR(pipe);
2309 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2310 flags |= FDI_PHASE_SYNC_EN(pipe);
2311 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2312 POSTING_READ(SOUTH_CHICKEN1);
2313}
2314
8db9d77b
ZW		 2315/* The FDI link training functions for ILK/Ibexpeak. */
2316static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2317{
2318 struct drm_device *dev = crtc->dev;
2319 struct drm_i915_private *dev_priv = dev->dev_private;
2320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2321 int pipe = intel_crtc->pipe;
0fc932b8 2322 int plane = intel_crtc->plane;
5eddb70b 2323 u32 reg, temp, tries;
8db9d77b 2324
0fc932b8
JB		 2325 /* FDI needs bits from pipe & plane first */
2326 assert_pipe_enabled(dev_priv, pipe);
2327 assert_plane_enabled(dev_priv, plane);
2328
e1a44743
AJ		 2329 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2330 for train result */
5eddb70b
CW		 2331 reg = FDI_RX_IMR(pipe);
2332 temp = I915_READ(reg);
e1a44743
AJ		 2333 temp &= ~FDI_RX_SYMBOL_LOCK;
2334 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2335 I915_WRITE(reg, temp);
2336 I915_READ(reg);
e1a44743
AJ		 2337 udelay(150);
2338
8db9d77b 2339 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
77ffb597
AJ		 2342 temp &= ~(7 << 19);
2343 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2344 temp &= ~FDI_LINK_TRAIN_NONE;
2345 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2346 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2347
5eddb70b
CW		 2348 reg = FDI_RX_CTL(pipe);
2349 temp = I915_READ(reg);
8db9d77b
ZW		 2350 temp &= ~FDI_LINK_TRAIN_NONE;
2351 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2352 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2353
2354 POSTING_READ(reg);
8db9d77b
ZW		 2355 udelay(150);
2356
5b2adf89 2357 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2358 if (HAS_PCH_IBX(dev)) {
2359 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2360 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2361 FDI_RX_PHASE_SYNC_POINTER_EN);
2362 }
5b2adf89 2363
5eddb70b 2364 reg = FDI_RX_IIR(pipe);
e1a44743 2365 for (tries = 0; tries < 5; tries++) {
5eddb70b 2366 temp = I915_READ(reg);
8db9d77b
ZW		 2367 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2368
2369 if ((temp & FDI_RX_BIT_LOCK)) {
2370 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2371 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2372 break;
2373 }
8db9d77b 2374 }
e1a44743 2375 if (tries == 5)
5eddb70b 2376 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2377
2378 /* Train 2 */
5eddb70b
CW		 2379 reg = FDI_TX_CTL(pipe);
2380 temp = I915_READ(reg);
8db9d77b
ZW		 2381 temp &= ~FDI_LINK_TRAIN_NONE;
2382 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2383 I915_WRITE(reg, temp);
8db9d77b 2384
5eddb70b
CW		 2385 reg = FDI_RX_CTL(pipe);
2386 temp = I915_READ(reg);
8db9d77b
ZW		 2387 temp &= ~FDI_LINK_TRAIN_NONE;
2388 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2389 I915_WRITE(reg, temp);
8db9d77b 2390
5eddb70b
CW		 2391 POSTING_READ(reg);
2392 udelay(150);
8db9d77b 2393
5eddb70b 2394 reg = FDI_RX_IIR(pipe);
e1a44743 2395 for (tries = 0; tries < 5; tries++) {
5eddb70b 2396 temp = I915_READ(reg);
8db9d77b
ZW		 2397 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2398
2399 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2400 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2401 DRM_DEBUG_KMS("FDI train 2 done.\n");
2402 break;
2403 }
8db9d77b 2404 }
e1a44743 2405 if (tries == 5)
5eddb70b 2406 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2407
2408 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2409
8db9d77b
ZW		 2410}
2411
0206e353 2412static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2413 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2414 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2415 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2416 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2417};
2418
2419/* The FDI link training functions for SNB/Cougarpoint. */
2420static void gen6_fdi_link_train(struct drm_crtc *crtc)
2421{
2422 struct drm_device *dev = crtc->dev;
2423 struct drm_i915_private *dev_priv = dev->dev_private;
2424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2425 int pipe = intel_crtc->pipe;
fa37d39e 2426 u32 reg, temp, i, retry;
8db9d77b 2427
e1a44743
AJ		 2428 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2429 for train result */
5eddb70b
CW		 2430 reg = FDI_RX_IMR(pipe);
2431 temp = I915_READ(reg);
e1a44743
AJ		 2432 temp &= ~FDI_RX_SYMBOL_LOCK;
2433 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2434 I915_WRITE(reg, temp);
2435
2436 POSTING_READ(reg);
e1a44743
AJ		 2437 udelay(150);
2438
8db9d77b 2439 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2440 reg = FDI_TX_CTL(pipe);
2441 temp = I915_READ(reg);
77ffb597
AJ		 2442 temp &= ~(7 << 19);
2443 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2444 temp &= ~FDI_LINK_TRAIN_NONE;
2445 temp |= FDI_LINK_TRAIN_PATTERN_1;
2446 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2447 /* SNB-B */
2448 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2449 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2450
5eddb70b
CW		 2451 reg = FDI_RX_CTL(pipe);
2452 temp = I915_READ(reg);
8db9d77b
ZW		 2453 if (HAS_PCH_CPT(dev)) {
2454 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2455 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2456 } else {
2457 temp &= ~FDI_LINK_TRAIN_NONE;
2458 temp |= FDI_LINK_TRAIN_PATTERN_1;
2459 }
5eddb70b
CW		 2460 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2461
2462 POSTING_READ(reg);
8db9d77b
ZW		 2463 udelay(150);
2464
291427f5
JB		 2465 if (HAS_PCH_CPT(dev))
2466 cpt_phase_pointer_enable(dev, pipe);
2467
0206e353 2468 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2469 reg = FDI_TX_CTL(pipe);
2470 temp = I915_READ(reg);
8db9d77b
ZW		 2471 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2472 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2473 I915_WRITE(reg, temp);
2474
2475 POSTING_READ(reg);
8db9d77b
ZW		 2476 udelay(500);
2477
fa37d39e
SP		 2478 for (retry = 0; retry < 5; retry++) {
2479 reg = FDI_RX_IIR(pipe);
2480 temp = I915_READ(reg);
2481 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2482 if (temp & FDI_RX_BIT_LOCK) {
2483 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2484 DRM_DEBUG_KMS("FDI train 1 done.\n");
2485 break;
2486 }
2487 udelay(50);
8db9d77b 2488 }
fa37d39e
SP		 2489 if (retry < 5)
2490 break;
8db9d77b
ZW		 2491 }
2492 if (i == 4)
5eddb70b 2493 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2494
2495 /* Train 2 */
5eddb70b
CW		 2496 reg = FDI_TX_CTL(pipe);
2497 temp = I915_READ(reg);
8db9d77b
ZW		 2498 temp &= ~FDI_LINK_TRAIN_NONE;
2499 temp |= FDI_LINK_TRAIN_PATTERN_2;
2500 if (IS_GEN6(dev)) {
2501 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2502 /* SNB-B */
2503 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2504 }
5eddb70b 2505 I915_WRITE(reg, temp);
8db9d77b 2506
5eddb70b
CW		 2507 reg = FDI_RX_CTL(pipe);
2508 temp = I915_READ(reg);
8db9d77b
ZW		 2509 if (HAS_PCH_CPT(dev)) {
2510 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2511 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2512 } else {
2513 temp &= ~FDI_LINK_TRAIN_NONE;
2514 temp |= FDI_LINK_TRAIN_PATTERN_2;
2515 }
5eddb70b
CW		 2516 I915_WRITE(reg, temp);
2517
2518 POSTING_READ(reg);
8db9d77b
ZW		 2519 udelay(150);
2520
0206e353 2521 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2522 reg = FDI_TX_CTL(pipe);
2523 temp = I915_READ(reg);
8db9d77b
ZW		 2524 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2525 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2526 I915_WRITE(reg, temp);
2527
2528 POSTING_READ(reg);
8db9d77b
ZW		 2529 udelay(500);
2530
fa37d39e
SP		 2531 for (retry = 0; retry < 5; retry++) {
2532 reg = FDI_RX_IIR(pipe);
2533 temp = I915_READ(reg);
2534 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2535 if (temp & FDI_RX_SYMBOL_LOCK) {
2536 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2537 DRM_DEBUG_KMS("FDI train 2 done.\n");
2538 break;
2539 }
2540 udelay(50);
8db9d77b 2541 }
fa37d39e
SP		 2542 if (retry < 5)
2543 break;
8db9d77b
ZW		 2544 }
2545 if (i == 4)
5eddb70b 2546 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2547
2548 DRM_DEBUG_KMS("FDI train done.\n");
2549}
2550
357555c0
JB		 2551/* Manual link training for Ivy Bridge A0 parts */
2552static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2553{
2554 struct drm_device *dev = crtc->dev;
2555 struct drm_i915_private *dev_priv = dev->dev_private;
2556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2557 int pipe = intel_crtc->pipe;
2558 u32 reg, temp, i;
2559
2560 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2561 for train result */
2562 reg = FDI_RX_IMR(pipe);
2563 temp = I915_READ(reg);
2564 temp &= ~FDI_RX_SYMBOL_LOCK;
2565 temp &= ~FDI_RX_BIT_LOCK;
2566 I915_WRITE(reg, temp);
2567
2568 POSTING_READ(reg);
2569 udelay(150);
2570
2571 /* enable CPU FDI TX and PCH FDI RX */
2572 reg = FDI_TX_CTL(pipe);
2573 temp = I915_READ(reg);
2574 temp &= ~(7 << 19);
2575 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2576 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2577 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2578 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2579 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2580 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2581 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2582
2583 reg = FDI_RX_CTL(pipe);
2584 temp = I915_READ(reg);
2585 temp &= ~FDI_LINK_TRAIN_AUTO;
2586 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2587 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2588 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2589 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2590
2591 POSTING_READ(reg);
2592 udelay(150);
2593
291427f5
JB		 2594 if (HAS_PCH_CPT(dev))
2595 cpt_phase_pointer_enable(dev, pipe);
2596
0206e353 2597 for (i = 0; i < 4; i++) {
357555c0
JB		 2598 reg = FDI_TX_CTL(pipe);
2599 temp = I915_READ(reg);
2600 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2601 temp |= snb_b_fdi_train_param[i];
2602 I915_WRITE(reg, temp);
2603
2604 POSTING_READ(reg);
2605 udelay(500);
2606
2607 reg = FDI_RX_IIR(pipe);
2608 temp = I915_READ(reg);
2609 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2610
2611 if (temp & FDI_RX_BIT_LOCK ||
2612 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2613 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2614 DRM_DEBUG_KMS("FDI train 1 done.\n");
2615 break;
2616 }
2617 }
2618 if (i == 4)
2619 DRM_ERROR("FDI train 1 fail!\n");
2620
2621 /* Train 2 */
2622 reg = FDI_TX_CTL(pipe);
2623 temp = I915_READ(reg);
2624 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2625 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2626 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2627 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2628 I915_WRITE(reg, temp);
2629
2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
2632 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2633 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2634 I915_WRITE(reg, temp);
2635
2636 POSTING_READ(reg);
2637 udelay(150);
2638
0206e353 2639 for (i = 0; i < 4; i++) {
357555c0
JB		 2640 reg = FDI_TX_CTL(pipe);
2641 temp = I915_READ(reg);
2642 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2643 temp |= snb_b_fdi_train_param[i];
2644 I915_WRITE(reg, temp);
2645
2646 POSTING_READ(reg);
2647 udelay(500);
2648
2649 reg = FDI_RX_IIR(pipe);
2650 temp = I915_READ(reg);
2651 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2652
2653 if (temp & FDI_RX_SYMBOL_LOCK) {
2654 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2655 DRM_DEBUG_KMS("FDI train 2 done.\n");
2656 break;
2657 }
2658 }
2659 if (i == 4)
2660 DRM_ERROR("FDI train 2 fail!\n");
2661
2662 DRM_DEBUG_KMS("FDI train done.\n");
2663}
2664
88cefb6c 2665static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2666{
88cefb6c 2667 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2668 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2669 int pipe = intel_crtc->pipe;
5eddb70b 2670 u32 reg, temp;
79e53945 2671
c64e311e 2672 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2673 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2674 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2675
c98e9dcf 2676 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2677 reg = FDI_RX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2680 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2681 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2682 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2683
2684 POSTING_READ(reg);
c98e9dcf
JB		 2685 udelay(200);
2686
2687 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2688 temp = I915_READ(reg);
2689 I915_WRITE(reg, temp | FDI_PCDCLK);
2690
2691 POSTING_READ(reg);
c98e9dcf
JB		 2692 udelay(200);
2693
bf507ef7
ED		 2694 /* On Haswell, the PLL configuration for ports and pipes is handled
2695 * separately, as part of DDI setup */
2696 if (!IS_HASWELL(dev)) {
2697 /* Enable CPU FDI TX PLL, always on for Ironlake */
2698 reg = FDI_TX_CTL(pipe);
2699 temp = I915_READ(reg);
2700 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2701 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2702
bf507ef7
ED		 2703 POSTING_READ(reg);
2704 udelay(100);
2705 }
6be4a607 2706 }
0e23b99d
JB		 2707}
2708
88cefb6c
DV		 2709static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2710{
2711 struct drm_device *dev = intel_crtc->base.dev;
2712 struct drm_i915_private *dev_priv = dev->dev_private;
2713 int pipe = intel_crtc->pipe;
2714 u32 reg, temp;
2715
2716 /* Switch from PCDclk to Rawclk */
2717 reg = FDI_RX_CTL(pipe);
2718 temp = I915_READ(reg);
2719 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2720
2721 /* Disable CPU FDI TX PLL */
2722 reg = FDI_TX_CTL(pipe);
2723 temp = I915_READ(reg);
2724 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2725
2726 POSTING_READ(reg);
2727 udelay(100);
2728
2729 reg = FDI_RX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2732
2733 /* Wait for the clocks to turn off. */
2734 POSTING_READ(reg);
2735 udelay(100);
2736}
2737
291427f5
JB		 2738static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2739{
2740 struct drm_i915_private *dev_priv = dev->dev_private;
2741 u32 flags = I915_READ(SOUTH_CHICKEN1);
2742
2743 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2744 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2745 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2746 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2747 POSTING_READ(SOUTH_CHICKEN1);
2748}
0fc932b8
JB		 2749static void ironlake_fdi_disable(struct drm_crtc *crtc)
2750{
2751 struct drm_device *dev = crtc->dev;
2752 struct drm_i915_private *dev_priv = dev->dev_private;
2753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2754 int pipe = intel_crtc->pipe;
2755 u32 reg, temp;
2756
2757 /* disable CPU FDI tx and PCH FDI rx */
2758 reg = FDI_TX_CTL(pipe);
2759 temp = I915_READ(reg);
2760 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2761 POSTING_READ(reg);
2762
2763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
2765 temp &= ~(0x7 << 16);
2766 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2767 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2768
2769 POSTING_READ(reg);
2770 udelay(100);
2771
2772 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2773 if (HAS_PCH_IBX(dev)) {
2774 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2775 I915_WRITE(FDI_RX_CHICKEN(pipe),
2776 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2777 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2778 } else if (HAS_PCH_CPT(dev)) {
2779 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2780 }
0fc932b8
JB		 2781
2782 /* still set train pattern 1 */
2783 reg = FDI_TX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 temp &= ~FDI_LINK_TRAIN_NONE;
2786 temp |= FDI_LINK_TRAIN_PATTERN_1;
2787 I915_WRITE(reg, temp);
2788
2789 reg = FDI_RX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 if (HAS_PCH_CPT(dev)) {
2792 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2793 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2794 } else {
2795 temp &= ~FDI_LINK_TRAIN_NONE;
2796 temp |= FDI_LINK_TRAIN_PATTERN_1;
2797 }
2798 /* BPC in FDI rx is consistent with that in PIPECONF */
2799 temp &= ~(0x07 << 16);
2800 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2801 I915_WRITE(reg, temp);
2802
2803 POSTING_READ(reg);
2804 udelay(100);
2805}
2806
e6c3a2a6
CW		 2807static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2808{
0f91128d 2809 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2810
2811 if (crtc->fb == NULL)
2812 return;
2813
0f91128d
CW		 2814 mutex_lock(&dev->struct_mutex);
2815 intel_finish_fb(crtc->fb);
2816 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2817}
2818
040484af
JB		 2819static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2820{
2821 struct drm_device *dev = crtc->dev;
228d3e36 2822 struct intel_encoder *intel_encoder;
040484af
JB		 2823
2824 /*
2825 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2826 * must be driven by its own crtc; no sharing is possible.
2827 */
228d3e36 2828 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
040484af 2829
6ee8bab0
ED		 2830 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2831 * CPU handles all others */
2832 if (IS_HASWELL(dev)) {
2833 /* It is still unclear how this will work on PPT, so throw up a warning */
2834 WARN_ON(!HAS_PCH_LPT(dev));
2835
228d3e36 2836 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
6ee8bab0
ED		 2837 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2838 return true;
2839 } else {
2840 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
228d3e36 2841 intel_encoder->type);
6ee8bab0
ED		 2842 return false;
2843 }
2844 }
2845
228d3e36 2846 switch (intel_encoder->type) {
040484af 2847 case INTEL_OUTPUT_EDP:
228d3e36 2848 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2849 return false;
2850 continue;
2851 }
2852 }
2853
2854 return true;
2855}
2856
e615efe4
ED		 2857/* Program iCLKIP clock to the desired frequency */
2858static void lpt_program_iclkip(struct drm_crtc *crtc)
2859{
2860 struct drm_device *dev = crtc->dev;
2861 struct drm_i915_private *dev_priv = dev->dev_private;
2862 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2863 u32 temp;
2864
2865 /* It is necessary to ungate the pixclk gate prior to programming
2866 * the divisors, and gate it back when it is done.
2867 */
2868 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2869
2870 /* Disable SSCCTL */
2871 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2872 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2873 SBI_SSCCTL_DISABLE);
2874
2875 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2876 if (crtc->mode.clock == 20000) {
2877 auxdiv = 1;
2878 divsel = 0x41;
2879 phaseinc = 0x20;
2880 } else {
2881 /* The iCLK virtual clock root frequency is in MHz,
2882 * but the crtc->mode.clock in in KHz. To get the divisors,
2883 * it is necessary to divide one by another, so we
2884 * convert the virtual clock precision to KHz here for higher
2885 * precision.
2886 */
2887 u32 iclk_virtual_root_freq = 172800 * 1000;
2888 u32 iclk_pi_range = 64;
2889 u32 desired_divisor, msb_divisor_value, pi_value;
2890
2891 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2892 msb_divisor_value = desired_divisor / iclk_pi_range;
2893 pi_value = desired_divisor % iclk_pi_range;
2894
2895 auxdiv = 0;
2896 divsel = msb_divisor_value - 2;
2897 phaseinc = pi_value;
2898 }
2899
2900 /* This should not happen with any sane values */
2901 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2902 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2903 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2904 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2905
2906 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2907 crtc->mode.clock,
2908 auxdiv,
2909 divsel,
2910 phasedir,
2911 phaseinc);
2912
2913 /* Program SSCDIVINTPHASE6 */
2914 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2915 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2916 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2917 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2918 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2919 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2920 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2921
2922 intel_sbi_write(dev_priv,
2923 SBI_SSCDIVINTPHASE6,
2924 temp);
2925
2926 /* Program SSCAUXDIV */
2927 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2928 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2929 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2930 intel_sbi_write(dev_priv,
2931 SBI_SSCAUXDIV6,
2932 temp);
2933
2934
2935 /* Enable modulator and associated divider */
2936 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2937 temp &= ~SBI_SSCCTL_DISABLE;
2938 intel_sbi_write(dev_priv,
2939 SBI_SSCCTL6,
2940 temp);
2941
2942 /* Wait for initialization time */
2943 udelay(24);
2944
2945 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2946}
2947
f67a559d
JB		 2948/*
2949 * Enable PCH resources required for PCH ports:
2950 * - PCH PLLs
2951 * - FDI training & RX/TX
2952 * - update transcoder timings
2953 * - DP transcoding bits
2954 * - transcoder
2955 */
2956static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2957{
2958 struct drm_device *dev = crtc->dev;
2959 struct drm_i915_private *dev_priv = dev->dev_private;
2960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2961 int pipe = intel_crtc->pipe;
ee7b9f93 2962 u32 reg, temp;
2c07245f 2963
e7e164db
CW		 2964 assert_transcoder_disabled(dev_priv, pipe);
2965
c98e9dcf 2966 /* For PCH output, training FDI link */
674cf967 2967 dev_priv->display.fdi_link_train(crtc);
2c07245f 2968
6f13b7b5
CW		 2969 intel_enable_pch_pll(intel_crtc);
2970
e615efe4
ED		 2971 if (HAS_PCH_LPT(dev)) {
2972 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2973 lpt_program_iclkip(crtc);
2974 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 2975 u32 sel;
4b645f14 2976
c98e9dcf 2977 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2978 switch (pipe) {
2979 default:
2980 case 0:
2981 temp |= TRANSA_DPLL_ENABLE;
2982 sel = TRANSA_DPLLB_SEL;
2983 break;
2984 case 1:
2985 temp |= TRANSB_DPLL_ENABLE;
2986 sel = TRANSB_DPLLB_SEL;
2987 break;
2988 case 2:
2989 temp |= TRANSC_DPLL_ENABLE;
2990 sel = TRANSC_DPLLB_SEL;
2991 break;
d64311ab 2992 }
ee7b9f93
JB		 2993 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2994 temp |= sel;
2995 else
2996 temp &= ~sel;
c98e9dcf 2997 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2998 }
5eddb70b 2999
d9b6cb56
JB		 3000 /* set transcoder timing, panel must allow it */
3001 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3002 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3003 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3004 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3005
5eddb70b
CW		 3006 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3007 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3008 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3009 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3010
f57e1e3a
ED		 3011 if (!IS_HASWELL(dev))
3012 intel_fdi_normal_train(crtc);
5e84e1a4 3013
c98e9dcf
JB		 3014 /* For PCH DP, enable TRANS_DP_CTL */
3015 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3016 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3017 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3018 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3019 reg = TRANS_DP_CTL(pipe);
3020 temp = I915_READ(reg);
3021 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3022 TRANS_DP_SYNC_MASK |
3023 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3024 temp |= (TRANS_DP_OUTPUT_ENABLE |
3025 TRANS_DP_ENH_FRAMING);
9325c9f0 3026 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3027
3028 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3029 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3030 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3031 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3032
3033 switch (intel_trans_dp_port_sel(crtc)) {
3034 case PCH_DP_B:
5eddb70b 3035 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3036 break;
3037 case PCH_DP_C:
5eddb70b 3038 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3039 break;
3040 case PCH_DP_D:
5eddb70b 3041 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3042 break;
3043 default:
3044 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3045 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3046 break;
32f9d658 3047 }
2c07245f 3048
5eddb70b 3049 I915_WRITE(reg, temp);
6be4a607 3050 }
b52eb4dc 3051
040484af 3052 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3053}
3054
ee7b9f93
JB		 3055static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3056{
3057 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3058
3059 if (pll == NULL)
3060 return;
3061
3062 if (pll->refcount == 0) {
3063 WARN(1, "bad PCH PLL refcount\n");
3064 return;
3065 }
3066
3067 --pll->refcount;
3068 intel_crtc->pch_pll = NULL;
3069}
3070
3071static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3072{
3073 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3074 struct intel_pch_pll *pll;
3075 int i;
3076
3077 pll = intel_crtc->pch_pll;
3078 if (pll) {
3079 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3080 intel_crtc->base.base.id, pll->pll_reg);
3081 goto prepare;
3082 }
3083
98b6bd99
DV		 3084 if (HAS_PCH_IBX(dev_priv->dev)) {
3085 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3086 i = intel_crtc->pipe;
3087 pll = &dev_priv->pch_plls[i];
3088
3089 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3090 intel_crtc->base.base.id, pll->pll_reg);
3091
3092 goto found;
3093 }
3094
ee7b9f93
JB		 3095 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3096 pll = &dev_priv->pch_plls[i];
3097
3098 /* Only want to check enabled timings first */
3099 if (pll->refcount == 0)
3100 continue;
3101
3102 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3103 fp == I915_READ(pll->fp0_reg)) {
3104 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3105 intel_crtc->base.base.id,
3106 pll->pll_reg, pll->refcount, pll->active);
3107
3108 goto found;
3109 }
3110 }
3111
3112 /* Ok no matching timings, maybe there's a free one? */
3113 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3114 pll = &dev_priv->pch_plls[i];
3115 if (pll->refcount == 0) {
3116 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3117 intel_crtc->base.base.id, pll->pll_reg);
3118 goto found;
3119 }
3120 }
3121
3122 return NULL;
3123
3124found:
3125 intel_crtc->pch_pll = pll;
3126 pll->refcount++;
3127 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3128prepare: /* separate function? */
3129 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3130
e04c7350
CW		 3131 /* Wait for the clocks to stabilize before rewriting the regs */
3132 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3133 POSTING_READ(pll->pll_reg);
3134 udelay(150);
e04c7350
CW		 3135
3136 I915_WRITE(pll->fp0_reg, fp);
3137 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3138 pll->on = false;
3139 return pll;
3140}
3141
d4270e57
JB		 3142void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3143{
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3146 u32 temp;
3147
3148 temp = I915_READ(dslreg);
3149 udelay(500);
3150 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3151 /* Without this, mode sets may fail silently on FDI */
3152 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3153 udelay(250);
3154 I915_WRITE(tc2reg, 0);
3155 if (wait_for(I915_READ(dslreg) != temp, 5))
3156 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3157 }
3158}
3159
f67a559d
JB		 3160static void ironlake_crtc_enable(struct drm_crtc *crtc)
3161{
3162 struct drm_device *dev = crtc->dev;
3163 struct drm_i915_private *dev_priv = dev->dev_private;
3164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3165 struct intel_encoder *encoder;
f67a559d
JB		 3166 int pipe = intel_crtc->pipe;
3167 int plane = intel_crtc->plane;
3168 u32 temp;
3169 bool is_pch_port;
3170
08a48469
DV		 3171 WARN_ON(!crtc->enabled);
3172
f67a559d
JB		 3173 if (intel_crtc->active)
3174 return;
3175
3176 intel_crtc->active = true;
3177 intel_update_watermarks(dev);
3178
3179 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3180 temp = I915_READ(PCH_LVDS);
3181 if ((temp & LVDS_PORT_EN) == 0)
3182 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3183 }
3184
3185 is_pch_port = intel_crtc_driving_pch(crtc);
3186
3187 if (is_pch_port)
88cefb6c 3188 ironlake_fdi_pll_enable(intel_crtc);
f67a559d
JB		 3189 else
3190 ironlake_fdi_disable(crtc);
3191
bf49ec8c
DV		 3192 for_each_encoder_on_crtc(dev, crtc, encoder)
3193 if (encoder->pre_enable)
3194 encoder->pre_enable(encoder);
3195
f67a559d
JB		 3196 /* Enable panel fitting for LVDS */
3197 if (dev_priv->pch_pf_size &&
3198 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3199 /* Force use of hard-coded filter coefficients
3200 * as some pre-programmed values are broken,
3201 * e.g. x201.
3202 */
9db4a9c7
JB		 3203 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3204 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3205 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3206 }
3207
9c54c0dd
JB		 3208 /*
3209 * On ILK+ LUT must be loaded before the pipe is running but with
3210 * clocks enabled
3211 */
3212 intel_crtc_load_lut(crtc);
3213
f67a559d
JB		 3214 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3215 intel_enable_plane(dev_priv, plane, pipe);
3216
3217 if (is_pch_port)
3218 ironlake_pch_enable(crtc);
c98e9dcf 3219
d1ebd816 3220 mutex_lock(&dev->struct_mutex);
bed4a673 3221 intel_update_fbc(dev);
d1ebd816
BW		 3222 mutex_unlock(&dev->struct_mutex);
3223
6b383a7f 3224 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3225
fa5c73b1
DV		 3226 for_each_encoder_on_crtc(dev, crtc, encoder)
3227 encoder->enable(encoder);
61b77ddd
DV		 3228
3229 if (HAS_PCH_CPT(dev))
3230 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 3231}
3232
3233static void ironlake_crtc_disable(struct drm_crtc *crtc)
3234{
3235 struct drm_device *dev = crtc->dev;
3236 struct drm_i915_private *dev_priv = dev->dev_private;
3237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3238 struct intel_encoder *encoder;
6be4a607
JB		 3239 int pipe = intel_crtc->pipe;
3240 int plane = intel_crtc->plane;
5eddb70b 3241 u32 reg, temp;
b52eb4dc 3242
ef9c3aee 3243
f7abfe8b
CW		 3244 if (!intel_crtc->active)
3245 return;
3246
ea9d758d
DV		 3247 for_each_encoder_on_crtc(dev, crtc, encoder)
3248 encoder->disable(encoder);
3249
e6c3a2a6 3250 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3251 drm_vblank_off(dev, pipe);
6b383a7f 3252 intel_crtc_update_cursor(crtc, false);
5eddb70b 3253
b24e7179 3254 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3255
973d04f9
CW		 3256 if (dev_priv->cfb_plane == plane)
3257 intel_disable_fbc(dev);
2c07245f 3258
b24e7179 3259 intel_disable_pipe(dev_priv, pipe);
32f9d658 3260
6be4a607 3261 /* Disable PF */
9db4a9c7
JB		 3262 I915_WRITE(PF_CTL(pipe), 0);
3263 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3264
bf49ec8c
DV		 3265 for_each_encoder_on_crtc(dev, crtc, encoder)
3266 if (encoder->post_disable)
3267 encoder->post_disable(encoder);
3268
0fc932b8 3269 ironlake_fdi_disable(crtc);
2c07245f 3270
040484af 3271 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3272
6be4a607
JB		 3273 if (HAS_PCH_CPT(dev)) {
3274 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3275 reg = TRANS_DP_CTL(pipe);
3276 temp = I915_READ(reg);
3277 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3278 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3279 I915_WRITE(reg, temp);
6be4a607
JB		 3280
3281 /* disable DPLL_SEL */
3282 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3283 switch (pipe) {
3284 case 0:
d64311ab 3285 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3286 break;
3287 case 1:
6be4a607 3288 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3289 break;
3290 case 2:
4b645f14 3291 /* C shares PLL A or B */
d64311ab 3292 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3293 break;
3294 default:
3295 BUG(); /* wtf */
3296 }
6be4a607 3297 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3298 }
e3421a18 3299
6be4a607 3300 /* disable PCH DPLL */
ee7b9f93 3301 intel_disable_pch_pll(intel_crtc);
8db9d77b 3302
88cefb6c 3303 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3304
f7abfe8b 3305 intel_crtc->active = false;
6b383a7f 3306 intel_update_watermarks(dev);
d1ebd816
BW		 3307
3308 mutex_lock(&dev->struct_mutex);
6b383a7f 3309 intel_update_fbc(dev);
d1ebd816 3310 mutex_unlock(&dev->struct_mutex);
6be4a607 3311}
1b3c7a47 3312
ee7b9f93
JB		 3313static void ironlake_crtc_off(struct drm_crtc *crtc)
3314{
3315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3316 intel_put_pch_pll(intel_crtc);
3317}
3318
02e792fb
DV		 3319static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3320{
02e792fb 3321 if (!enable && intel_crtc->overlay) {
23f09ce3 3322 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3323 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3324
23f09ce3 3325 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3326 dev_priv->mm.interruptible = false;
3327 (void) intel_overlay_switch_off(intel_crtc->overlay);
3328 dev_priv->mm.interruptible = true;
23f09ce3 3329 mutex_unlock(&dev->struct_mutex);
02e792fb 3330 }
02e792fb 3331
5dcdbcb0
CW		 3332 /* Let userspace switch the overlay on again. In most cases userspace
3333 * has to recompute where to put it anyway.
3334 */
02e792fb
DV		 3335}
3336
0b8765c6 3337static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3338{
3339 struct drm_device *dev = crtc->dev;
79e53945
JB		 3340 struct drm_i915_private *dev_priv = dev->dev_private;
3341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3342 struct intel_encoder *encoder;
79e53945 3343 int pipe = intel_crtc->pipe;
80824003 3344 int plane = intel_crtc->plane;
79e53945 3345
08a48469
DV		 3346 WARN_ON(!crtc->enabled);
3347
f7abfe8b
CW		 3348 if (intel_crtc->active)
3349 return;
3350
3351 intel_crtc->active = true;
6b383a7f
CW		 3352 intel_update_watermarks(dev);
3353
63d7bbe9 3354 intel_enable_pll(dev_priv, pipe);
040484af 3355 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3356 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3357
0b8765c6 3358 intel_crtc_load_lut(crtc);
bed4a673 3359 intel_update_fbc(dev);
79e53945 3360
0b8765c6
JB		 3361 /* Give the overlay scaler a chance to enable if it's on this pipe */
3362 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3363 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3364
fa5c73b1
DV		 3365 for_each_encoder_on_crtc(dev, crtc, encoder)
3366 encoder->enable(encoder);
0b8765c6 3367}
79e53945 3368
0b8765c6
JB		 3369static void i9xx_crtc_disable(struct drm_crtc *crtc)
3370{
3371 struct drm_device *dev = crtc->dev;
3372 struct drm_i915_private *dev_priv = dev->dev_private;
3373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3374 struct intel_encoder *encoder;
0b8765c6
JB		 3375 int pipe = intel_crtc->pipe;
3376 int plane = intel_crtc->plane;
b690e96c 3377
ef9c3aee 3378
f7abfe8b
CW		 3379 if (!intel_crtc->active)
3380 return;
3381
ea9d758d
DV		 3382 for_each_encoder_on_crtc(dev, crtc, encoder)
3383 encoder->disable(encoder);
3384
0b8765c6 3385 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3386 intel_crtc_wait_for_pending_flips(crtc);
3387 drm_vblank_off(dev, pipe);
0b8765c6 3388 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3389 intel_crtc_update_cursor(crtc, false);
0b8765c6 3390
973d04f9
CW		 3391 if (dev_priv->cfb_plane == plane)
3392 intel_disable_fbc(dev);
79e53945 3393
b24e7179 3394 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3395 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3396 intel_disable_pll(dev_priv, pipe);
0b8765c6 3397
f7abfe8b 3398 intel_crtc->active = false;
6b383a7f
CW		 3399 intel_update_fbc(dev);
3400 intel_update_watermarks(dev);
0b8765c6
JB		 3401}
3402
ee7b9f93
JB		 3403static void i9xx_crtc_off(struct drm_crtc *crtc)
3404{
3405}
3406
976f8a20
DV		 3407static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3408 bool enabled)
2c07245f
ZW		 3409{
3410 struct drm_device *dev = crtc->dev;
3411 struct drm_i915_master_private *master_priv;
3412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3413 int pipe = intel_crtc->pipe;
79e53945
JB		 3414
3415 if (!dev->primary->master)
3416 return;
3417
3418 master_priv = dev->primary->master->driver_priv;
3419 if (!master_priv->sarea_priv)
3420 return;
3421
79e53945
JB		 3422 switch (pipe) {
3423 case 0:
3424 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3425 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3426 break;
3427 case 1:
3428 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3429 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3430 break;
3431 default:
9db4a9c7 3432 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3433 break;
3434 }
79e53945
JB		 3435}
3436
976f8a20
DV		 3437/**
3438 * Sets the power management mode of the pipe and plane.
3439 */
3440void intel_crtc_update_dpms(struct drm_crtc *crtc)
3441{
3442 struct drm_device *dev = crtc->dev;
3443 struct drm_i915_private *dev_priv = dev->dev_private;
3444 struct intel_encoder *intel_encoder;
3445 bool enable = false;
3446
3447 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3448 enable |= intel_encoder->connectors_active;
3449
3450 if (enable)
3451 dev_priv->display.crtc_enable(crtc);
3452 else
3453 dev_priv->display.crtc_disable(crtc);
3454
3455 intel_crtc_update_sarea(crtc, enable);
3456}
3457
3458static void intel_crtc_noop(struct drm_crtc *crtc)
3459{
3460}
3461
cdd59983
CW		 3462static void intel_crtc_disable(struct drm_crtc *crtc)
3463{
cdd59983 3464 struct drm_device *dev = crtc->dev;
976f8a20 3465 struct drm_connector *connector;
ee7b9f93 3466 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3467
976f8a20
DV		 3468 /* crtc should still be enabled when we disable it. */
3469 WARN_ON(!crtc->enabled);
3470
3471 dev_priv->display.crtc_disable(crtc);
3472 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3473 dev_priv->display.off(crtc);
3474
931872fc
CW		 3475 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3476 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3477
3478 if (crtc->fb) {
3479 mutex_lock(&dev->struct_mutex);
1690e1eb 3480 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3481 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3482 crtc->fb = NULL;
3483 }
3484
3485 /* Update computed state. */
3486 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3487 if (!connector->encoder || !connector->encoder->crtc)
3488 continue;
3489
3490 if (connector->encoder->crtc != crtc)
3491 continue;
3492
3493 connector->dpms = DRM_MODE_DPMS_OFF;
3494 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3495 }
3496}
3497
a261b246 3498void intel_modeset_disable(struct drm_device *dev)
79e53945 3499{
a261b246
DV		 3500 struct drm_crtc *crtc;
3501
3502 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3503 if (crtc->enabled)
3504 intel_crtc_disable(crtc);
3505 }
79e53945
JB		 3506}
3507
1f703855 3508void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3509{
7e7d76c3
JB		 3510}
3511
ea5b213a 3512void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3513{
4ef69c7a 3514 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3515
ea5b213a
CW		 3516 drm_encoder_cleanup(encoder);
3517 kfree(intel_encoder);
7e7d76c3
JB		 3518}
3519
5ab432ef
DV		 3520/* Simple dpms helper for encodres with just one connector, no cloning and only
3521 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3522 * state of the entire output pipe. */
3523void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3524{
5ab432ef
DV		 3525 if (mode == DRM_MODE_DPMS_ON) {
3526 encoder->connectors_active = true;
3527
b2cabb0e 3528 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3529 } else {
3530 encoder->connectors_active = false;
3531
b2cabb0e 3532 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3533 }
79e53945
JB		 3534}
3535
0a91ca29
DV		 3536/* Cross check the actual hw state with our own modeset state tracking (and it's
3537 * internal consistency). */
b980514c 3538static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3539{
0a91ca29
DV		 3540 if (connector->get_hw_state(connector)) {
3541 struct intel_encoder *encoder = connector->encoder;
3542 struct drm_crtc *crtc;
3543 bool encoder_enabled;
3544 enum pipe pipe;
3545
3546 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3547 connector->base.base.id,
3548 drm_get_connector_name(&connector->base));
3549
3550 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3551 "wrong connector dpms state\n");
3552 WARN(connector->base.encoder != &encoder->base,
3553 "active connector not linked to encoder\n");
3554 WARN(!encoder->connectors_active,
3555 "encoder->connectors_active not set\n");
3556
3557 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3558 WARN(!encoder_enabled, "encoder not enabled\n");
3559 if (WARN_ON(!encoder->base.crtc))
3560 return;
3561
3562 crtc = encoder->base.crtc;
3563
3564 WARN(!crtc->enabled, "crtc not enabled\n");
3565 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3566 WARN(pipe != to_intel_crtc(crtc)->pipe,
3567 "encoder active on the wrong pipe\n");
3568 }
79e53945
JB		 3569}
3570
5ab432ef
DV		 3571/* Even simpler default implementation, if there's really no special case to
3572 * consider. */
3573void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3574{
5ab432ef 3575 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3576
5ab432ef
DV		 3577 /* All the simple cases only support two dpms states. */
3578 if (mode != DRM_MODE_DPMS_ON)
3579 mode = DRM_MODE_DPMS_OFF;
d4270e57 3580
5ab432ef
DV		 3581 if (mode == connector->dpms)
3582 return;
3583
3584 connector->dpms = mode;
3585
3586 /* Only need to change hw state when actually enabled */
3587 if (encoder->base.crtc)
3588 intel_encoder_dpms(encoder, mode);
3589 else
8af6cf88 3590 WARN_ON(encoder->connectors_active != false);
0a91ca29 3591
b980514c 3592 intel_modeset_check_state(connector->dev);
79e53945
JB		 3593}
3594
f0947c37
DV		 3595/* Simple connector->get_hw_state implementation for encoders that support only
3596 * one connector and no cloning and hence the encoder state determines the state
3597 * of the connector. */
3598bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3599{
24929352 3600 enum pipe pipe = 0;
f0947c37 3601 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3602
f0947c37 3603 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3604}
3605
79e53945 3606static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3607 const struct drm_display_mode *mode,
79e53945
JB		 3608 struct drm_display_mode *adjusted_mode)
3609{
2c07245f 3610 struct drm_device *dev = crtc->dev;
89749350 3611
bad720ff 3612 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3613 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3614 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3615 return false;
2c07245f 3616 }
89749350 3617
f9bef081
DV		 3618 /* All interlaced capable intel hw wants timings in frames. Note though
3619 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3620 * timings, so we need to be careful not to clobber these.*/
3621 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3622 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3623
44f46b42
CW		 3624 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3625 * with a hsync front porch of 0.
3626 */
3627 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3628 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3629 return false;
3630
79e53945
JB		 3631 return true;
3632}
3633
25eb05fc
JB		 3634static int valleyview_get_display_clock_speed(struct drm_device *dev)
3635{
3636 return 400000; /* FIXME */
3637}
3638
e70236a8
JB		 3639static int i945_get_display_clock_speed(struct drm_device *dev)
3640{
3641 return 400000;
3642}
79e53945 3643
e70236a8 3644static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3645{
e70236a8
JB		 3646 return 333000;
3647}
79e53945 3648
e70236a8
JB		 3649static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3650{
3651 return 200000;
3652}
79e53945 3653
e70236a8
JB		 3654static int i915gm_get_display_clock_speed(struct drm_device *dev)
3655{
3656 u16 gcfgc = 0;
79e53945 3657
e70236a8
JB		 3658 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3659
3660 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3661 return 133000;
3662 else {
3663 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3664 case GC_DISPLAY_CLOCK_333_MHZ:
3665 return 333000;
3666 default:
3667 case GC_DISPLAY_CLOCK_190_200_MHZ:
3668 return 190000;
79e53945 3669 }
e70236a8
JB		 3670 }
3671}
3672
3673static int i865_get_display_clock_speed(struct drm_device *dev)
3674{
3675 return 266000;
3676}
3677
3678static int i855_get_display_clock_speed(struct drm_device *dev)
3679{
3680 u16 hpllcc = 0;
3681 /* Assume that the hardware is in the high speed state. This
3682 * should be the default.
3683 */
3684 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3685 case GC_CLOCK_133_200:
3686 case GC_CLOCK_100_200:
3687 return 200000;
3688 case GC_CLOCK_166_250:
3689 return 250000;
3690 case GC_CLOCK_100_133:
79e53945 3691 return 133000;
e70236a8 3692 }
79e53945 3693
e70236a8
JB		 3694 /* Shouldn't happen */
3695 return 0;
3696}
79e53945 3697
e70236a8
JB		 3698static int i830_get_display_clock_speed(struct drm_device *dev)
3699{
3700 return 133000;
79e53945
JB		 3701}
3702
2c07245f
ZW		 3703struct fdi_m_n {
3704 u32 tu;
3705 u32 gmch_m;
3706 u32 gmch_n;
3707 u32 link_m;
3708 u32 link_n;
3709};
3710
3711static void
3712fdi_reduce_ratio(u32 *num, u32 *den)
3713{
3714 while (*num > 0xffffff || *den > 0xffffff) {
3715 *num >>= 1;
3716 *den >>= 1;
3717 }
3718}
3719
2c07245f 3720static void
f2b115e6
AJ		 3721ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3722 int link_clock, struct fdi_m_n *m_n)
2c07245f 3723{
2c07245f
ZW		 3724 m_n->tu = 64; /* default size */
3725
22ed1113
CW		 3726 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3727 m_n->gmch_m = bits_per_pixel * pixel_clock;
3728 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3729 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3730
22ed1113
CW		 3731 m_n->link_m = pixel_clock;
3732 m_n->link_n = link_clock;
2c07245f
ZW		 3733 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3734}
3735
a7615030
CW		 3736static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3737{
72bbe58c
KP		 3738 if (i915_panel_use_ssc >= 0)
3739 return i915_panel_use_ssc != 0;
3740 return dev_priv->lvds_use_ssc
435793df 3741 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3742}
3743
5a354204
JB		 3744/**
3745 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3746 * @crtc: CRTC structure
3b5c78a3 3747 * @mode: requested mode
5a354204
JB		 3748 *
3749 * A pipe may be connected to one or more outputs. Based on the depth of the
3750 * attached framebuffer, choose a good color depth to use on the pipe.
3751 *
3752 * If possible, match the pipe depth to the fb depth. In some cases, this
3753 * isn't ideal, because the connected output supports a lesser or restricted
3754 * set of depths. Resolve that here:
3755 * LVDS typically supports only 6bpc, so clamp down in that case
3756 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3757 * Displays may support a restricted set as well, check EDID and clamp as
3758 * appropriate.
3b5c78a3 3759 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3760 *
3761 * RETURNS:
3762 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3763 * true if they don't match).
3764 */
3765static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 3766 struct drm_framebuffer *fb,
3b5c78a3
AJ		 3767 unsigned int *pipe_bpp,
3768 struct drm_display_mode *mode)
5a354204
JB		 3769{
3770 struct drm_device *dev = crtc->dev;
3771 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 3772 struct drm_connector *connector;
6c2b7c12 3773 struct intel_encoder *intel_encoder;
5a354204
JB		 3774 unsigned int display_bpc = UINT_MAX, bpc;
3775
3776 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 3777 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 3778
3779 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3780 unsigned int lvds_bpc;
3781
3782 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3783 LVDS_A3_POWER_UP)
3784 lvds_bpc = 8;
3785 else
3786 lvds_bpc = 6;
3787
3788 if (lvds_bpc < display_bpc) {
82820490 3789 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3790 display_bpc = lvds_bpc;
3791 }
3792 continue;
3793 }
3794
5a354204
JB		 3795 /* Not one of the known troublemakers, check the EDID */
3796 list_for_each_entry(connector, &dev->mode_config.connector_list,
3797 head) {
6c2b7c12 3798 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 3799 continue;
3800
62ac41a6
JB		 3801 /* Don't use an invalid EDID bpc value */
3802 if (connector->display_info.bpc &&
3803 connector->display_info.bpc < display_bpc) {
82820490 3804 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3805 display_bpc = connector->display_info.bpc;
3806 }
3807 }
3808
3809 /*
3810 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3811 * through, clamp it down. (Note: >12bpc will be caught below.)
3812 */
3813 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3814 if (display_bpc > 8 && display_bpc < 12) {
82820490 3815 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3816 display_bpc = 12;
3817 } else {
82820490 3818 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3819 display_bpc = 8;
3820 }
3821 }
3822 }
3823
3b5c78a3
AJ		 3824 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3825 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3826 display_bpc = 6;
3827 }
3828
5a354204
JB		 3829 /*
3830 * We could just drive the pipe at the highest bpc all the time and
3831 * enable dithering as needed, but that costs bandwidth. So choose
3832 * the minimum value that expresses the full color range of the fb but
3833 * also stays within the max display bpc discovered above.
3834 */
3835
94352cf9 3836 switch (fb->depth) {
5a354204
JB		 3837 case 8:
3838 bpc = 8; /* since we go through a colormap */
3839 break;
3840 case 15:
3841 case 16:
3842 bpc = 6; /* min is 18bpp */
3843 break;
3844 case 24:
578393cd 3845 bpc = 8;
5a354204
JB		 3846 break;
3847 case 30:
578393cd 3848 bpc = 10;
5a354204
JB		 3849 break;
3850 case 48:
578393cd 3851 bpc = 12;
5a354204
JB		 3852 break;
3853 default:
3854 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3855 bpc = min((unsigned int)8, display_bpc);
3856 break;
3857 }
3858
578393cd
KP		 3859 display_bpc = min(display_bpc, bpc);
3860
82820490
AJ		 3861 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3862 bpc, display_bpc);
5a354204 3863
578393cd 3864 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3865
3866 return display_bpc != bpc;
3867}
3868
a0c4da24
JB		 3869static int vlv_get_refclk(struct drm_crtc *crtc)
3870{
3871 struct drm_device *dev = crtc->dev;
3872 struct drm_i915_private *dev_priv = dev->dev_private;
3873 int refclk = 27000; /* for DP & HDMI */
3874
3875 return 100000; /* only one validated so far */
3876
3877 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3878 refclk = 96000;
3879 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3880 if (intel_panel_use_ssc(dev_priv))
3881 refclk = 100000;
3882 else
3883 refclk = 96000;
3884 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3885 refclk = 100000;
3886 }
3887
3888 return refclk;
3889}
3890
c65d77d8
JB		 3891static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3892{
3893 struct drm_device *dev = crtc->dev;
3894 struct drm_i915_private *dev_priv = dev->dev_private;
3895 int refclk;
3896
a0c4da24
JB		 3897 if (IS_VALLEYVIEW(dev)) {
3898 refclk = vlv_get_refclk(crtc);
3899 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 3900 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3901 refclk = dev_priv->lvds_ssc_freq * 1000;
3902 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3903 refclk / 1000);
3904 } else if (!IS_GEN2(dev)) {
3905 refclk = 96000;
3906 } else {
3907 refclk = 48000;
3908 }
3909
3910 return refclk;
3911}
3912
3913static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3914 intel_clock_t *clock)
3915{
3916 /* SDVO TV has fixed PLL values depend on its clock range,
3917 this mirrors vbios setting. */
3918 if (adjusted_mode->clock >= 100000
3919 && adjusted_mode->clock < 140500) {
3920 clock->p1 = 2;
3921 clock->p2 = 10;
3922 clock->n = 3;
3923 clock->m1 = 16;
3924 clock->m2 = 8;
3925 } else if (adjusted_mode->clock >= 140500
3926 && adjusted_mode->clock <= 200000) {
3927 clock->p1 = 1;
3928 clock->p2 = 10;
3929 clock->n = 6;
3930 clock->m1 = 12;
3931 clock->m2 = 8;
3932 }
3933}
3934
a7516a05
JB		 3935static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3936 intel_clock_t *clock,
3937 intel_clock_t *reduced_clock)
3938{
3939 struct drm_device *dev = crtc->dev;
3940 struct drm_i915_private *dev_priv = dev->dev_private;
3941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3942 int pipe = intel_crtc->pipe;
3943 u32 fp, fp2 = 0;
3944
3945 if (IS_PINEVIEW(dev)) {
3946 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3947 if (reduced_clock)
3948 fp2 = (1 << reduced_clock->n) << 16 |
3949 reduced_clock->m1 << 8 | reduced_clock->m2;
3950 } else {
3951 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3952 if (reduced_clock)
3953 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3954 reduced_clock->m2;
3955 }
3956
3957 I915_WRITE(FP0(pipe), fp);
3958
3959 intel_crtc->lowfreq_avail = false;
3960 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3961 reduced_clock && i915_powersave) {
3962 I915_WRITE(FP1(pipe), fp2);
3963 intel_crtc->lowfreq_avail = true;
3964 } else {
3965 I915_WRITE(FP1(pipe), fp);
3966 }
3967}
3968
93e537a1
DV		 3969static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3970 struct drm_display_mode *adjusted_mode)
3971{
3972 struct drm_device *dev = crtc->dev;
3973 struct drm_i915_private *dev_priv = dev->dev_private;
3974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3975 int pipe = intel_crtc->pipe;
284d5df5 3976 u32 temp;
93e537a1
DV		 3977
3978 temp = I915_READ(LVDS);
3979 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3980 if (pipe == 1) {
3981 temp |= LVDS_PIPEB_SELECT;
3982 } else {
3983 temp &= ~LVDS_PIPEB_SELECT;
3984 }
3985 /* set the corresponsding LVDS_BORDER bit */
3986 temp |= dev_priv->lvds_border_bits;
3987 /* Set the B0-B3 data pairs corresponding to whether we're going to
3988 * set the DPLLs for dual-channel mode or not.
3989 */
3990 if (clock->p2 == 7)
3991 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3992 else
3993 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3994
3995 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3996 * appropriately here, but we need to look more thoroughly into how
3997 * panels behave in the two modes.
3998 */
3999 /* set the dithering flag on LVDS as needed */
4000 if (INTEL_INFO(dev)->gen >= 4) {
4001 if (dev_priv->lvds_dither)
4002 temp |= LVDS_ENABLE_DITHER;
4003 else
4004 temp &= ~LVDS_ENABLE_DITHER;
4005 }
284d5df5 4006 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4007 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4008 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4009 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4010 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4011 I915_WRITE(LVDS, temp);
4012}
4013
a0c4da24
JB		 4014static void vlv_update_pll(struct drm_crtc *crtc,
4015 struct drm_display_mode *mode,
4016 struct drm_display_mode *adjusted_mode,
4017 intel_clock_t *clock, intel_clock_t *reduced_clock,
4018 int refclk, int num_connectors)
4019{
4020 struct drm_device *dev = crtc->dev;
4021 struct drm_i915_private *dev_priv = dev->dev_private;
4022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4023 int pipe = intel_crtc->pipe;
4024 u32 dpll, mdiv, pdiv;
4025 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4026 bool is_hdmi;
4027
4028 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4029
4030 bestn = clock->n;
4031 bestm1 = clock->m1;
4032 bestm2 = clock->m2;
4033 bestp1 = clock->p1;
4034 bestp2 = clock->p2;
4035
4036 /* Enable DPIO clock input */
4037 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4038 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4039 I915_WRITE(DPLL(pipe), dpll);
4040 POSTING_READ(DPLL(pipe));
4041
4042 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4043 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4044 mdiv |= ((bestn << DPIO_N_SHIFT));
4045 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4046 mdiv |= (1 << DPIO_K_SHIFT);
4047 mdiv |= DPIO_ENABLE_CALIBRATION;
4048 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4049
4050 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4051
4052 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4053 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4054 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4055 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4056
4057 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4058
4059 dpll |= DPLL_VCO_ENABLE;
4060 I915_WRITE(DPLL(pipe), dpll);
4061 POSTING_READ(DPLL(pipe));
4062 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4063 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4064
4065 if (is_hdmi) {
4066 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4067
4068 if (temp > 1)
4069 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4070 else
4071 temp = 0;
4072
4073 I915_WRITE(DPLL_MD(pipe), temp);
4074 POSTING_READ(DPLL_MD(pipe));
4075 }
4076
4077 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4078}
4079
eb1cbe48
DV		 4080static void i9xx_update_pll(struct drm_crtc *crtc,
4081 struct drm_display_mode *mode,
4082 struct drm_display_mode *adjusted_mode,
4083 intel_clock_t *clock, intel_clock_t *reduced_clock,
4084 int num_connectors)
4085{
4086 struct drm_device *dev = crtc->dev;
4087 struct drm_i915_private *dev_priv = dev->dev_private;
4088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4089 int pipe = intel_crtc->pipe;
4090 u32 dpll;
4091 bool is_sdvo;
4092
4093 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4094 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4095
4096 dpll = DPLL_VGA_MODE_DIS;
4097
4098 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4099 dpll |= DPLLB_MODE_LVDS;
4100 else
4101 dpll |= DPLLB_MODE_DAC_SERIAL;
4102 if (is_sdvo) {
4103 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4104 if (pixel_multiplier > 1) {
4105 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4106 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4107 }
4108 dpll |= DPLL_DVO_HIGH_SPEED;
4109 }
4110 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4111 dpll |= DPLL_DVO_HIGH_SPEED;
4112
4113 /* compute bitmask from p1 value */
4114 if (IS_PINEVIEW(dev))
4115 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4116 else {
4117 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4118 if (IS_G4X(dev) && reduced_clock)
4119 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4120 }
4121 switch (clock->p2) {
4122 case 5:
4123 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4124 break;
4125 case 7:
4126 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4127 break;
4128 case 10:
4129 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4130 break;
4131 case 14:
4132 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4133 break;
4134 }
4135 if (INTEL_INFO(dev)->gen >= 4)
4136 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4137
4138 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4139 dpll |= PLL_REF_INPUT_TVCLKINBC;
4140 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4141 /* XXX: just matching BIOS for now */
4142 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4143 dpll |= 3;
4144 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4145 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4146 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4147 else
4148 dpll |= PLL_REF_INPUT_DREFCLK;
4149
4150 dpll |= DPLL_VCO_ENABLE;
4151 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4152 POSTING_READ(DPLL(pipe));
4153 udelay(150);
4154
4155 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4156 * This is an exception to the general rule that mode_set doesn't turn
4157 * things on.
4158 */
4159 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4160 intel_update_lvds(crtc, clock, adjusted_mode);
4161
4162 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4163 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4164
4165 I915_WRITE(DPLL(pipe), dpll);
4166
4167 /* Wait for the clocks to stabilize. */
4168 POSTING_READ(DPLL(pipe));
4169 udelay(150);
4170
4171 if (INTEL_INFO(dev)->gen >= 4) {
4172 u32 temp = 0;
4173 if (is_sdvo) {
4174 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4175 if (temp > 1)
4176 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4177 else
4178 temp = 0;
4179 }
4180 I915_WRITE(DPLL_MD(pipe), temp);
4181 } else {
4182 /* The pixel multiplier can only be updated once the
4183 * DPLL is enabled and the clocks are stable.
4184 *
4185 * So write it again.
4186 */
4187 I915_WRITE(DPLL(pipe), dpll);
4188 }
4189}
4190
4191static void i8xx_update_pll(struct drm_crtc *crtc,
4192 struct drm_display_mode *adjusted_mode,
4193 intel_clock_t *clock,
4194 int num_connectors)
4195{
4196 struct drm_device *dev = crtc->dev;
4197 struct drm_i915_private *dev_priv = dev->dev_private;
4198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4199 int pipe = intel_crtc->pipe;
4200 u32 dpll;
4201
4202 dpll = DPLL_VGA_MODE_DIS;
4203
4204 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4205 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4206 } else {
4207 if (clock->p1 == 2)
4208 dpll |= PLL_P1_DIVIDE_BY_TWO;
4209 else
4210 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4211 if (clock->p2 == 4)
4212 dpll |= PLL_P2_DIVIDE_BY_4;
4213 }
4214
4215 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4216 /* XXX: just matching BIOS for now */
4217 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4218 dpll |= 3;
4219 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4220 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4221 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4222 else
4223 dpll |= PLL_REF_INPUT_DREFCLK;
4224
4225 dpll |= DPLL_VCO_ENABLE;
4226 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4227 POSTING_READ(DPLL(pipe));
4228 udelay(150);
4229
4230 I915_WRITE(DPLL(pipe), dpll);
4231
4232 /* Wait for the clocks to stabilize. */
4233 POSTING_READ(DPLL(pipe));
4234 udelay(150);
4235
4236 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4237 * This is an exception to the general rule that mode_set doesn't turn
4238 * things on.
4239 */
4240 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4241 intel_update_lvds(crtc, clock, adjusted_mode);
4242
4243 /* The pixel multiplier can only be updated once the
4244 * DPLL is enabled and the clocks are stable.
4245 *
4246 * So write it again.
4247 */
4248 I915_WRITE(DPLL(pipe), dpll);
4249}
4250
f564048e
EA		 4251static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4252 struct drm_display_mode *mode,
4253 struct drm_display_mode *adjusted_mode,
4254 int x, int y,
94352cf9 4255 struct drm_framebuffer *fb)
79e53945
JB		 4256{
4257 struct drm_device *dev = crtc->dev;
4258 struct drm_i915_private *dev_priv = dev->dev_private;
4259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4260 int pipe = intel_crtc->pipe;
80824003 4261 int plane = intel_crtc->plane;
c751ce4f 4262 int refclk, num_connectors = 0;
652c393a 4263 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 4264 u32 dspcntr, pipeconf, vsyncshift;
4265 bool ok, has_reduced_clock = false, is_sdvo = false;
4266 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4267 struct intel_encoder *encoder;
d4906093 4268 const intel_limit_t *limit;
5c3b82e2 4269 int ret;
79e53945 4270
6c2b7c12 4271 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4272 switch (encoder->type) {
79e53945
JB		 4273 case INTEL_OUTPUT_LVDS:
4274 is_lvds = true;
4275 break;
4276 case INTEL_OUTPUT_SDVO:
7d57382e 4277 case INTEL_OUTPUT_HDMI:
79e53945 4278 is_sdvo = true;
5eddb70b 4279 if (encoder->needs_tv_clock)
e2f0ba97 4280 is_tv = true;
79e53945 4281 break;
79e53945
JB		 4282 case INTEL_OUTPUT_TVOUT:
4283 is_tv = true;
4284 break;
a4fc5ed6
KP		 4285 case INTEL_OUTPUT_DISPLAYPORT:
4286 is_dp = true;
4287 break;
79e53945 4288 }
43565a06 4289
c751ce4f 4290 num_connectors++;
79e53945
JB		 4291 }
4292
c65d77d8 4293 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4294
d4906093
ML		 4295 /*
4296 * Returns a set of divisors for the desired target clock with the given
4297 * refclk, or FALSE. The returned values represent the clock equation:
4298 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4299 */
1b894b59 4300 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4301 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4302 &clock);
79e53945
JB		 4303 if (!ok) {
4304 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4305 return -EINVAL;
79e53945
JB		 4306 }
4307
cda4b7d3 4308 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4309 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4310
ddc9003c 4311 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4312 /*
4313 * Ensure we match the reduced clock's P to the target clock.
4314 * If the clocks don't match, we can't switch the display clock
4315 * by using the FP0/FP1. In such case we will disable the LVDS
4316 * downclock feature.
4317 */
ddc9003c 4318 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4319 dev_priv->lvds_downclock,
4320 refclk,
cec2f356 4321 &clock,
5eddb70b 4322 &reduced_clock);
7026d4ac
ZW		 4323 }
4324
c65d77d8
JB		 4325 if (is_sdvo && is_tv)
4326 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4327
a7516a05
JB		 4328 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4329 &reduced_clock : NULL);
79e53945 4330
eb1cbe48
DV		 4331 if (IS_GEN2(dev))
4332 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
a0c4da24
JB		 4333 else if (IS_VALLEYVIEW(dev))
4334 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4335 refclk, num_connectors);
79e53945 4336 else
eb1cbe48
DV		 4337 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4338 has_reduced_clock ? &reduced_clock : NULL,
4339 num_connectors);
79e53945
JB		 4340
4341 /* setup pipeconf */
5eddb70b 4342 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4343
4344 /* Set up the display plane register */
4345 dspcntr = DISPPLANE_GAMMA_ENABLE;
4346
929c77fb
EA		 4347 if (pipe == 0)
4348 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4349 else
4350 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4351
a6c45cf0 4352 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4353 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4354 * core speed.
4355 *
4356 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4357 * pipe == 0 check?
4358 */
e70236a8
JB		 4359 if (mode->clock >
4360 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4361 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4362 else
5eddb70b 4363 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4364 }
4365
3b5c78a3
AJ		 4366 /* default to 8bpc */
4367 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4368 if (is_dp) {
4369 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4370 pipeconf |= PIPECONF_BPP_6 |
4371 PIPECONF_DITHER_EN |
4372 PIPECONF_DITHER_TYPE_SP;
4373 }
4374 }
4375
28c97730 4376 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4377 drm_mode_debug_printmodeline(mode);
4378
a7516a05
JB		 4379 if (HAS_PIPE_CXSR(dev)) {
4380 if (intel_crtc->lowfreq_avail) {
28c97730 4381 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4382 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4383 } else {
28c97730 4384 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4385 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4386 }
4387 }
4388
617cf884 4389 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 4390 if (!IS_GEN2(dev) &&
4391 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 4392 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4393 /* the chip adds 2 halflines automatically */
734b4157 4394 adjusted_mode->crtc_vtotal -= 1;
734b4157 4395 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4396 vsyncshift = adjusted_mode->crtc_hsync_start
4397 - adjusted_mode->crtc_htotal/2;
4398 } else {
617cf884 4399 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4400 vsyncshift = 0;
4401 }
4402
4403 if (!IS_GEN3(dev))
4404 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 4405
5eddb70b
CW		 4406 I915_WRITE(HTOTAL(pipe),
4407 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4408 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4409 I915_WRITE(HBLANK(pipe),
4410 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4411 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4412 I915_WRITE(HSYNC(pipe),
4413 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4414 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4415
4416 I915_WRITE(VTOTAL(pipe),
4417 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4418 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4419 I915_WRITE(VBLANK(pipe),
4420 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4421 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4422 I915_WRITE(VSYNC(pipe),
4423 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4424 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4425
4426 /* pipesrc and dspsize control the size that is scaled from,
4427 * which should always be the user's requested size.
79e53945 4428 */
929c77fb
EA		 4429 I915_WRITE(DSPSIZE(plane),
4430 ((mode->vdisplay - 1) << 16) |
4431 (mode->hdisplay - 1));
4432 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4433 I915_WRITE(PIPESRC(pipe),
4434 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4435
f564048e
EA		 4436 I915_WRITE(PIPECONF(pipe), pipeconf);
4437 POSTING_READ(PIPECONF(pipe));
929c77fb 4438 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4439
4440 intel_wait_for_vblank(dev, pipe);
4441
f564048e
EA		 4442 I915_WRITE(DSPCNTR(plane), dspcntr);
4443 POSTING_READ(DSPCNTR(plane));
4444
94352cf9 4445 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4446
4447 intel_update_watermarks(dev);
4448
f564048e
EA		 4449 return ret;
4450}
4451
9fb526db
KP		 4452/*
4453 * Initialize reference clocks when the driver loads
4454 */
4455void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4456{
4457 struct drm_i915_private *dev_priv = dev->dev_private;
4458 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4459 struct intel_encoder *encoder;
13d83a67
JB		 4460 u32 temp;
4461 bool has_lvds = false;
199e5d79
KP		 4462 bool has_cpu_edp = false;
4463 bool has_pch_edp = false;
4464 bool has_panel = false;
99eb6a01
KP		 4465 bool has_ck505 = false;
4466 bool can_ssc = false;
13d83a67
JB		 4467
4468 /* We need to take the global config into account */
199e5d79
KP		 4469 list_for_each_entry(encoder, &mode_config->encoder_list,
4470 base.head) {
4471 switch (encoder->type) {
4472 case INTEL_OUTPUT_LVDS:
4473 has_panel = true;
4474 has_lvds = true;
4475 break;
4476 case INTEL_OUTPUT_EDP:
4477 has_panel = true;
4478 if (intel_encoder_is_pch_edp(&encoder->base))
4479 has_pch_edp = true;
4480 else
4481 has_cpu_edp = true;
4482 break;
13d83a67
JB		 4483 }
4484 }
4485
99eb6a01
KP		 4486 if (HAS_PCH_IBX(dev)) {
4487 has_ck505 = dev_priv->display_clock_mode;
4488 can_ssc = has_ck505;
4489 } else {
4490 has_ck505 = false;
4491 can_ssc = true;
4492 }
4493
4494 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4495 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4496 has_ck505);
13d83a67
JB		 4497
4498 /* Ironlake: try to setup display ref clock before DPLL
4499 * enabling. This is only under driver's control after
4500 * PCH B stepping, previous chipset stepping should be
4501 * ignoring this setting.
4502 */
4503 temp = I915_READ(PCH_DREF_CONTROL);
4504 /* Always enable nonspread source */
4505 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4506
99eb6a01
KP		 4507 if (has_ck505)
4508 temp |= DREF_NONSPREAD_CK505_ENABLE;
4509 else
4510 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4511
199e5d79
KP		 4512 if (has_panel) {
4513 temp &= ~DREF_SSC_SOURCE_MASK;
4514 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4515
199e5d79 4516 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4517 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4518 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4519 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4520 } else
4521 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4522
4523 /* Get SSC going before enabling the outputs */
4524 I915_WRITE(PCH_DREF_CONTROL, temp);
4525 POSTING_READ(PCH_DREF_CONTROL);
4526 udelay(200);
4527
13d83a67
JB		 4528 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4529
4530 /* Enable CPU source on CPU attached eDP */
199e5d79 4531 if (has_cpu_edp) {
99eb6a01 4532 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4533 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4534 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4535 }
13d83a67
JB		 4536 else
4537 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4538 } else
4539 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4540
4541 I915_WRITE(PCH_DREF_CONTROL, temp);
4542 POSTING_READ(PCH_DREF_CONTROL);
4543 udelay(200);
4544 } else {
4545 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4546
4547 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4548
4549 /* Turn off CPU output */
4550 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4551
4552 I915_WRITE(PCH_DREF_CONTROL, temp);
4553 POSTING_READ(PCH_DREF_CONTROL);
4554 udelay(200);
4555
4556 /* Turn off the SSC source */
4557 temp &= ~DREF_SSC_SOURCE_MASK;
4558 temp |= DREF_SSC_SOURCE_DISABLE;
4559
4560 /* Turn off SSC1 */
4561 temp &= ~ DREF_SSC1_ENABLE;
4562
13d83a67
JB		 4563 I915_WRITE(PCH_DREF_CONTROL, temp);
4564 POSTING_READ(PCH_DREF_CONTROL);
4565 udelay(200);
4566 }
4567}
4568
d9d444cb
JB		 4569static int ironlake_get_refclk(struct drm_crtc *crtc)
4570{
4571 struct drm_device *dev = crtc->dev;
4572 struct drm_i915_private *dev_priv = dev->dev_private;
4573 struct intel_encoder *encoder;
d9d444cb
JB		 4574 struct intel_encoder *edp_encoder = NULL;
4575 int num_connectors = 0;
4576 bool is_lvds = false;
4577
6c2b7c12 4578 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4579 switch (encoder->type) {
4580 case INTEL_OUTPUT_LVDS:
4581 is_lvds = true;
4582 break;
4583 case INTEL_OUTPUT_EDP:
4584 edp_encoder = encoder;
4585 break;
4586 }
4587 num_connectors++;
4588 }
4589
4590 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4591 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4592 dev_priv->lvds_ssc_freq);
4593 return dev_priv->lvds_ssc_freq * 1000;
4594 }
4595
4596 return 120000;
4597}
4598
c8203565
PZ		 4599static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4600 struct drm_display_mode *adjusted_mode,
4601 bool dither)
4602{
4603 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4605 int pipe = intel_crtc->pipe;
4606 uint32_t val;
4607
4608 val = I915_READ(PIPECONF(pipe));
4609
4610 val &= ~PIPE_BPC_MASK;
4611 switch (intel_crtc->bpp) {
4612 case 18:
4613 val |= PIPE_6BPC;
4614 break;
4615 case 24:
4616 val |= PIPE_8BPC;
4617 break;
4618 case 30:
4619 val |= PIPE_10BPC;
4620 break;
4621 case 36:
4622 val |= PIPE_12BPC;
4623 break;
4624 default:
4625 val |= PIPE_8BPC;
4626 break;
4627 }
4628
4629 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4630 if (dither)
4631 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4632
4633 val &= ~PIPECONF_INTERLACE_MASK;
4634 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4635 val |= PIPECONF_INTERLACED_ILK;
4636 else
4637 val |= PIPECONF_PROGRESSIVE;
4638
4639 I915_WRITE(PIPECONF(pipe), val);
4640 POSTING_READ(PIPECONF(pipe));
4641}
4642
6591c6e4
PZ		 4643static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4644 struct drm_display_mode *adjusted_mode,
4645 intel_clock_t *clock,
4646 bool *has_reduced_clock,
4647 intel_clock_t *reduced_clock)
4648{
4649 struct drm_device *dev = crtc->dev;
4650 struct drm_i915_private *dev_priv = dev->dev_private;
4651 struct intel_encoder *intel_encoder;
4652 int refclk;
4653 const intel_limit_t *limit;
4654 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4655
4656 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4657 switch (intel_encoder->type) {
4658 case INTEL_OUTPUT_LVDS:
4659 is_lvds = true;
4660 break;
4661 case INTEL_OUTPUT_SDVO:
4662 case INTEL_OUTPUT_HDMI:
4663 is_sdvo = true;
4664 if (intel_encoder->needs_tv_clock)
4665 is_tv = true;
4666 break;
4667 case INTEL_OUTPUT_TVOUT:
4668 is_tv = true;
4669 break;
4670 }
4671 }
4672
4673 refclk = ironlake_get_refclk(crtc);
4674
4675 /*
4676 * Returns a set of divisors for the desired target clock with the given
4677 * refclk, or FALSE. The returned values represent the clock equation:
4678 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4679 */
4680 limit = intel_limit(crtc, refclk);
4681 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4682 clock);
4683 if (!ret)
4684 return false;
4685
4686 if (is_lvds && dev_priv->lvds_downclock_avail) {
4687 /*
4688 * Ensure we match the reduced clock's P to the target clock.
4689 * If the clocks don't match, we can't switch the display clock
4690 * by using the FP0/FP1. In such case we will disable the LVDS
4691 * downclock feature.
4692 */
4693 *has_reduced_clock = limit->find_pll(limit, crtc,
4694 dev_priv->lvds_downclock,
4695 refclk,
4696 clock,
4697 reduced_clock);
4698 }
4699
4700 if (is_sdvo && is_tv)
4701 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4702
4703 return true;
4704}
4705
f564048e
EA		 4706static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4707 struct drm_display_mode *mode,
4708 struct drm_display_mode *adjusted_mode,
4709 int x, int y,
94352cf9 4710 struct drm_framebuffer *fb)
79e53945
JB		 4711{
4712 struct drm_device *dev = crtc->dev;
4713 struct drm_i915_private *dev_priv = dev->dev_private;
4714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4715 int pipe = intel_crtc->pipe;
80824003 4716 int plane = intel_crtc->plane;
6591c6e4 4717 int num_connectors = 0;
652c393a 4718 intel_clock_t clock, reduced_clock;
a1f9e77e 4719 u32 dpll, fp = 0, fp2 = 0;
a07d6787 4720 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4721 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
e3aef172 4722 struct intel_encoder *encoder, *edp_encoder = NULL;
5c3b82e2 4723 int ret;
2c07245f 4724 struct fdi_m_n m_n = {0};
fae14981 4725 u32 temp;
5a354204
JB		 4726 int target_clock, pixel_multiplier, lane, link_bw, factor;
4727 unsigned int pipe_bpp;
4728 bool dither;
e3aef172 4729 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4730
6c2b7c12 4731 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4732 switch (encoder->type) {
79e53945
JB		 4733 case INTEL_OUTPUT_LVDS:
4734 is_lvds = true;
4735 break;
4736 case INTEL_OUTPUT_SDVO:
7d57382e 4737 case INTEL_OUTPUT_HDMI:
79e53945 4738 is_sdvo = true;
5eddb70b 4739 if (encoder->needs_tv_clock)
e2f0ba97 4740 is_tv = true;
79e53945 4741 break;
79e53945
JB		 4742 case INTEL_OUTPUT_TVOUT:
4743 is_tv = true;
4744 break;
4745 case INTEL_OUTPUT_ANALOG:
4746 is_crt = true;
4747 break;
a4fc5ed6
KP		 4748 case INTEL_OUTPUT_DISPLAYPORT:
4749 is_dp = true;
4750 break;
32f9d658 4751 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4752 is_dp = true;
4753 if (intel_encoder_is_pch_edp(&encoder->base))
4754 is_pch_edp = true;
4755 else
4756 is_cpu_edp = true;
4757 edp_encoder = encoder;
32f9d658 4758 break;
79e53945 4759 }
43565a06 4760
c751ce4f 4761 num_connectors++;
79e53945
JB		 4762 }
4763
6591c6e4
PZ		 4764 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
4765 &has_reduced_clock, &reduced_clock);
79e53945
JB		 4766 if (!ok) {
4767 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4768 return -EINVAL;
79e53945
JB		 4769 }
4770
cda4b7d3 4771 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4772 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4773
2c07245f 4774 /* FDI link */
8febb297
EA		 4775 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4776 lane = 0;
4777 /* CPU eDP doesn't require FDI link, so just set DP M/N
4778 according to current link config */
e3aef172 4779 if (is_cpu_edp) {
e3aef172 4780 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 4781 } else {
8febb297
EA		 4782 /* FDI is a binary signal running at ~2.7GHz, encoding
4783 * each output octet as 10 bits. The actual frequency
4784 * is stored as a divider into a 100MHz clock, and the
4785 * mode pixel clock is stored in units of 1KHz.
4786 * Hence the bw of each lane in terms of the mode signal
4787 * is:
4788 */
4789 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4790 }
58a27471 4791
94bf2ced
DV		 4792 /* [e]DP over FDI requires target mode clock instead of link clock. */
4793 if (edp_encoder)
4794 target_clock = intel_edp_target_clock(edp_encoder, mode);
4795 else if (is_dp)
4796 target_clock = mode->clock;
4797 else
4798 target_clock = adjusted_mode->clock;
4799
8febb297 4800 /* determine panel color depth */
94352cf9 4801 dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp, mode);
c8203565
PZ		 4802 if (is_lvds && dev_priv->lvds_dither)
4803 dither = true;
4804
4805 if (pipe_bpp != 18 && pipe_bpp != 24 && pipe_bpp != 30 &&
4806 pipe_bpp != 36) {
62ac41a6 4807 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
c8203565 4808 pipe_bpp);
5a354204 4809 pipe_bpp = 24;
8febb297 4810 }
5a354204 4811 intel_crtc->bpp = pipe_bpp;
5a354204 4812
8febb297
EA		 4813 if (!lane) {
4814 /*
4815 * Account for spread spectrum to avoid
4816 * oversubscribing the link. Max center spread
4817 * is 2.5%; use 5% for safety's sake.
4818 */
5a354204 4819 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4820 lane = bps / (link_bw * 8) + 1;
5eb08b69 4821 }
2c07245f 4822
8febb297
EA		 4823 intel_crtc->fdi_lanes = lane;
4824
4825 if (pixel_multiplier > 1)
4826 link_bw *= pixel_multiplier;
5a354204
JB		 4827 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4828 &m_n);
8febb297 4829
a07d6787
EA		 4830 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4831 if (has_reduced_clock)
4832 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4833 reduced_clock.m2;
79e53945 4834
c1858123 4835 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4836 factor = 21;
4837 if (is_lvds) {
4838 if ((intel_panel_use_ssc(dev_priv) &&
4839 dev_priv->lvds_ssc_freq == 100) ||
4840 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4841 factor = 25;
4842 } else if (is_sdvo && is_tv)
4843 factor = 20;
c1858123 4844
cb0e0931 4845 if (clock.m < factor * clock.n)
8febb297 4846 fp |= FP_CB_TUNE;
2c07245f 4847
5eddb70b 4848 dpll = 0;
2c07245f 4849
a07d6787
EA		 4850 if (is_lvds)
4851 dpll |= DPLLB_MODE_LVDS;
4852 else
4853 dpll |= DPLLB_MODE_DAC_SERIAL;
4854 if (is_sdvo) {
4855 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4856 if (pixel_multiplier > 1) {
4857 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4858 }
a07d6787
EA		 4859 dpll |= DPLL_DVO_HIGH_SPEED;
4860 }
e3aef172 4861 if (is_dp && !is_cpu_edp)
a07d6787 4862 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4863
a07d6787
EA		 4864 /* compute bitmask from p1 value */
4865 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4866 /* also FPA1 */
4867 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4868
4869 switch (clock.p2) {
4870 case 5:
4871 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4872 break;
4873 case 7:
4874 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4875 break;
4876 case 10:
4877 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4878 break;
4879 case 14:
4880 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4881 break;
79e53945
JB		 4882 }
4883
43565a06
KH		 4884 if (is_sdvo && is_tv)
4885 dpll |= PLL_REF_INPUT_TVCLKINBC;
4886 else if (is_tv)
79e53945 4887 /* XXX: just matching BIOS for now */
43565a06 4888 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4889 dpll |= 3;
a7615030 4890 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4891 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4892 else
4893 dpll |= PLL_REF_INPUT_DREFCLK;
4894
f7cb34d4 4895 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4896 drm_mode_debug_printmodeline(mode);
4897
9d82aa17
ED		 4898 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4899 * pre-Haswell/LPT generation */
4900 if (HAS_PCH_LPT(dev)) {
4901 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4902 pipe);
4903 } else if (!is_cpu_edp) {
ee7b9f93 4904 struct intel_pch_pll *pll;
4b645f14 4905
ee7b9f93
JB		 4906 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4907 if (pll == NULL) {
4908 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4909 pipe);
4b645f14
JB		 4910 return -EINVAL;
4911 }
ee7b9f93
JB		 4912 } else
4913 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4914
4915 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4916 * This is an exception to the general rule that mode_set doesn't turn
4917 * things on.
4918 */
4919 if (is_lvds) {
fae14981 4920 temp = I915_READ(PCH_LVDS);
5eddb70b 4921 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4922 if (HAS_PCH_CPT(dev)) {
4923 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4924 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4925 } else {
4926 if (pipe == 1)
4927 temp |= LVDS_PIPEB_SELECT;
4928 else
4929 temp &= ~LVDS_PIPEB_SELECT;
4930 }
4b645f14 4931
a3e17eb8 4932 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4933 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4934 /* Set the B0-B3 data pairs corresponding to whether we're going to
4935 * set the DPLLs for dual-channel mode or not.
4936 */
4937 if (clock.p2 == 7)
5eddb70b 4938 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4939 else
5eddb70b 4940 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4941
4942 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4943 * appropriately here, but we need to look more thoroughly into how
4944 * panels behave in the two modes.
4945 */
284d5df5 4946 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4947 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4948 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4949 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4950 temp |= LVDS_VSYNC_POLARITY;
fae14981 4951 I915_WRITE(PCH_LVDS, temp);
79e53945 4952 }
434ed097 4953
e3aef172 4954 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4955 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4956 } else {
8db9d77b 4957 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4958 I915_WRITE(TRANSDATA_M1(pipe), 0);
4959 I915_WRITE(TRANSDATA_N1(pipe), 0);
4960 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4961 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4962 }
79e53945 4963
ee7b9f93
JB		 4964 if (intel_crtc->pch_pll) {
4965 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4966
32f9d658 4967 /* Wait for the clocks to stabilize. */
ee7b9f93 4968 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4969 udelay(150);
4970
8febb297
EA		 4971 /* The pixel multiplier can only be updated once the
4972 * DPLL is enabled and the clocks are stable.
4973 *
4974 * So write it again.
4975 */
ee7b9f93 4976 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 4977 }
79e53945 4978
5eddb70b 4979 intel_crtc->lowfreq_avail = false;
ee7b9f93 4980 if (intel_crtc->pch_pll) {
4b645f14 4981 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 4982 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 4983 intel_crtc->lowfreq_avail = true;
4b645f14 4984 } else {
ee7b9f93 4985 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 4986 }
4987 }
4988
734b4157 4989 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157 4990 /* the chip adds 2 halflines automatically */
734b4157 4991 adjusted_mode->crtc_vtotal -= 1;
734b4157 4992 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4993 I915_WRITE(VSYNCSHIFT(pipe),
4994 adjusted_mode->crtc_hsync_start
4995 - adjusted_mode->crtc_htotal/2);
4996 } else {
0529a0d9
DV		 4997 I915_WRITE(VSYNCSHIFT(pipe), 0);
4998 }
734b4157 4999
5eddb70b
CW		 5000 I915_WRITE(HTOTAL(pipe),
5001 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5002 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5003 I915_WRITE(HBLANK(pipe),
5004 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5005 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5006 I915_WRITE(HSYNC(pipe),
5007 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5008 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5009
5010 I915_WRITE(VTOTAL(pipe),
5011 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5012 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5013 I915_WRITE(VBLANK(pipe),
5014 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5015 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5016 I915_WRITE(VSYNC(pipe),
5017 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5018 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5019
8febb297
EA		 5020 /* pipesrc controls the size that is scaled from, which should
5021 * always be the user's requested size.
79e53945 5022 */
5eddb70b
CW		 5023 I915_WRITE(PIPESRC(pipe),
5024 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5025
8febb297
EA		 5026 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5027 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5028 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5029 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5030
e3aef172 5031 if (is_cpu_edp)
8febb297 5032 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5033
c8203565 5034 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5035
9d0498a2 5036 intel_wait_for_vblank(dev, pipe);
79e53945 5037
a1f9e77e
PZ		 5038 /* Set up the display plane register */
5039 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5040 POSTING_READ(DSPCNTR(plane));
79e53945 5041
94352cf9 5042 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5043
5044 intel_update_watermarks(dev);
5045
1f8eeabf
ED		 5046 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5047
1f803ee5 5048 return ret;
79e53945
JB		 5049}
5050
f564048e
EA		 5051static int intel_crtc_mode_set(struct drm_crtc *crtc,
5052 struct drm_display_mode *mode,
5053 struct drm_display_mode *adjusted_mode,
5054 int x, int y,
94352cf9 5055 struct drm_framebuffer *fb)
f564048e
EA		 5056{
5057 struct drm_device *dev = crtc->dev;
5058 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5060 int pipe = intel_crtc->pipe;
f564048e
EA		 5061 int ret;
5062
0b701d27 5063 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5064
f564048e 5065 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5066 x, y, fb);
79e53945 5067 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5068
1f803ee5 5069 return ret;
79e53945
JB		 5070}
5071
3a9627f4
WF		 5072static bool intel_eld_uptodate(struct drm_connector *connector,
5073 int reg_eldv, uint32_t bits_eldv,
5074 int reg_elda, uint32_t bits_elda,
5075 int reg_edid)
5076{
5077 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5078 uint8_t *eld = connector->eld;
5079 uint32_t i;
5080
5081 i = I915_READ(reg_eldv);
5082 i &= bits_eldv;
5083
5084 if (!eld[0])
5085 return !i;
5086
5087 if (!i)
5088 return false;
5089
5090 i = I915_READ(reg_elda);
5091 i &= ~bits_elda;
5092 I915_WRITE(reg_elda, i);
5093
5094 for (i = 0; i < eld[2]; i++)
5095 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5096 return false;
5097
5098 return true;
5099}
5100
e0dac65e
WF		 5101static void g4x_write_eld(struct drm_connector *connector,
5102 struct drm_crtc *crtc)
5103{
5104 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5105 uint8_t *eld = connector->eld;
5106 uint32_t eldv;
5107 uint32_t len;
5108 uint32_t i;
5109
5110 i = I915_READ(G4X_AUD_VID_DID);
5111
5112 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5113 eldv = G4X_ELDV_DEVCL_DEVBLC;
5114 else
5115 eldv = G4X_ELDV_DEVCTG;
5116
3a9627f4
WF		 5117 if (intel_eld_uptodate(connector,
5118 G4X_AUD_CNTL_ST, eldv,
5119 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5120 G4X_HDMIW_HDMIEDID))
5121 return;
5122
e0dac65e
WF		 5123 i = I915_READ(G4X_AUD_CNTL_ST);
5124 i &= ~(eldv | G4X_ELD_ADDR);
5125 len = (i >> 9) & 0x1f; /* ELD buffer size */
5126 I915_WRITE(G4X_AUD_CNTL_ST, i);
5127
5128 if (!eld[0])
5129 return;
5130
5131 len = min_t(uint8_t, eld[2], len);
5132 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5133 for (i = 0; i < len; i++)
5134 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5135
5136 i = I915_READ(G4X_AUD_CNTL_ST);
5137 i |= eldv;
5138 I915_WRITE(G4X_AUD_CNTL_ST, i);
5139}
5140
83358c85
WX		 5141static void haswell_write_eld(struct drm_connector *connector,
5142 struct drm_crtc *crtc)
5143{
5144 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5145 uint8_t *eld = connector->eld;
5146 struct drm_device *dev = crtc->dev;
5147 uint32_t eldv;
5148 uint32_t i;
5149 int len;
5150 int pipe = to_intel_crtc(crtc)->pipe;
5151 int tmp;
5152
5153 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5154 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5155 int aud_config = HSW_AUD_CFG(pipe);
5156 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5157
5158
5159 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5160
5161 /* Audio output enable */
5162 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5163 tmp = I915_READ(aud_cntrl_st2);
5164 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5165 I915_WRITE(aud_cntrl_st2, tmp);
5166
5167 /* Wait for 1 vertical blank */
5168 intel_wait_for_vblank(dev, pipe);
5169
5170 /* Set ELD valid state */
5171 tmp = I915_READ(aud_cntrl_st2);
5172 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5173 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5174 I915_WRITE(aud_cntrl_st2, tmp);
5175 tmp = I915_READ(aud_cntrl_st2);
5176 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5177
5178 /* Enable HDMI mode */
5179 tmp = I915_READ(aud_config);
5180 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5181 /* clear N_programing_enable and N_value_index */
5182 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5183 I915_WRITE(aud_config, tmp);
5184
5185 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5186
5187 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5188
5189 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5190 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5191 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5192 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5193 } else
5194 I915_WRITE(aud_config, 0);
5195
5196 if (intel_eld_uptodate(connector,
5197 aud_cntrl_st2, eldv,
5198 aud_cntl_st, IBX_ELD_ADDRESS,
5199 hdmiw_hdmiedid))
5200 return;
5201
5202 i = I915_READ(aud_cntrl_st2);
5203 i &= ~eldv;
5204 I915_WRITE(aud_cntrl_st2, i);
5205
5206 if (!eld[0])
5207 return;
5208
5209 i = I915_READ(aud_cntl_st);
5210 i &= ~IBX_ELD_ADDRESS;
5211 I915_WRITE(aud_cntl_st, i);
5212 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5213 DRM_DEBUG_DRIVER("port num:%d\n", i);
5214
5215 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5216 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5217 for (i = 0; i < len; i++)
5218 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5219
5220 i = I915_READ(aud_cntrl_st2);
5221 i |= eldv;
5222 I915_WRITE(aud_cntrl_st2, i);
5223
5224}
5225
e0dac65e
WF		 5226static void ironlake_write_eld(struct drm_connector *connector,
5227 struct drm_crtc *crtc)
5228{
5229 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5230 uint8_t *eld = connector->eld;
5231 uint32_t eldv;
5232 uint32_t i;
5233 int len;
5234 int hdmiw_hdmiedid;
b6daa025 5235 int aud_config;
e0dac65e
WF		 5236 int aud_cntl_st;
5237 int aud_cntrl_st2;
9b138a83 5238 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5239
b3f33cbf 5240 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5241 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5242 aud_config = IBX_AUD_CFG(pipe);
5243 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5244 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5245 } else {
9b138a83
WX		 5246 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5247 aud_config = CPT_AUD_CFG(pipe);
5248 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5249 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5250 }
5251
9b138a83 5252 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5253
5254 i = I915_READ(aud_cntl_st);
9b138a83 5255 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5256 if (!i) {
5257 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5258 /* operate blindly on all ports */
1202b4c6
WF		 5259 eldv = IBX_ELD_VALIDB;
5260 eldv |= IBX_ELD_VALIDB << 4;
5261 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5262 } else {
5263 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5264 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5265 }
5266
3a9627f4
WF		 5267 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5268 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5269 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5270 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5271 } else
5272 I915_WRITE(aud_config, 0);
e0dac65e 5273
3a9627f4
WF		 5274 if (intel_eld_uptodate(connector,
5275 aud_cntrl_st2, eldv,
5276 aud_cntl_st, IBX_ELD_ADDRESS,
5277 hdmiw_hdmiedid))
5278 return;
5279
e0dac65e
WF		 5280 i = I915_READ(aud_cntrl_st2);
5281 i &= ~eldv;
5282 I915_WRITE(aud_cntrl_st2, i);
5283
5284 if (!eld[0])
5285 return;
5286
e0dac65e 5287 i = I915_READ(aud_cntl_st);
1202b4c6 5288 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5289 I915_WRITE(aud_cntl_st, i);
5290
5291 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5292 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5293 for (i = 0; i < len; i++)
5294 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5295
5296 i = I915_READ(aud_cntrl_st2);
5297 i |= eldv;
5298 I915_WRITE(aud_cntrl_st2, i);
5299}
5300
5301void intel_write_eld(struct drm_encoder *encoder,
5302 struct drm_display_mode *mode)
5303{
5304 struct drm_crtc *crtc = encoder->crtc;
5305 struct drm_connector *connector;
5306 struct drm_device *dev = encoder->dev;
5307 struct drm_i915_private *dev_priv = dev->dev_private;
5308
5309 connector = drm_select_eld(encoder, mode);
5310 if (!connector)
5311 return;
5312
5313 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5314 connector->base.id,
5315 drm_get_connector_name(connector),
5316 connector->encoder->base.id,
5317 drm_get_encoder_name(connector->encoder));
5318
5319 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5320
5321 if (dev_priv->display.write_eld)
5322 dev_priv->display.write_eld(connector, crtc);
5323}
5324
79e53945
JB		 5325/** Loads the palette/gamma unit for the CRTC with the prepared values */
5326void intel_crtc_load_lut(struct drm_crtc *crtc)
5327{
5328 struct drm_device *dev = crtc->dev;
5329 struct drm_i915_private *dev_priv = dev->dev_private;
5330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5331 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5332 int i;
5333
5334 /* The clocks have to be on to load the palette. */
aed3f09d 5335 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5336 return;
5337
f2b115e6 5338 /* use legacy palette for Ironlake */
bad720ff 5339 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5340 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5341
79e53945
JB		 5342 for (i = 0; i < 256; i++) {
5343 I915_WRITE(palreg + 4 * i,
5344 (intel_crtc->lut_r[i] << 16) |
5345 (intel_crtc->lut_g[i] << 8) |
5346 intel_crtc->lut_b[i]);
5347 }
5348}
5349
560b85bb
CW		 5350static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5351{
5352 struct drm_device *dev = crtc->dev;
5353 struct drm_i915_private *dev_priv = dev->dev_private;
5354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5355 bool visible = base != 0;
5356 u32 cntl;
5357
5358 if (intel_crtc->cursor_visible == visible)
5359 return;
5360
9db4a9c7 5361 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5362 if (visible) {
5363 /* On these chipsets we can only modify the base whilst
5364 * the cursor is disabled.
5365 */
9db4a9c7 5366 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5367
5368 cntl &= ~(CURSOR_FORMAT_MASK);
5369 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5370 cntl |= CURSOR_ENABLE |
5371 CURSOR_GAMMA_ENABLE |
5372 CURSOR_FORMAT_ARGB;
5373 } else
5374 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5375 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5376
5377 intel_crtc->cursor_visible = visible;
5378}
5379
5380static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5381{
5382 struct drm_device *dev = crtc->dev;
5383 struct drm_i915_private *dev_priv = dev->dev_private;
5384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5385 int pipe = intel_crtc->pipe;
5386 bool visible = base != 0;
5387
5388 if (intel_crtc->cursor_visible != visible) {
548f245b 5389 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5390 if (base) {
5391 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5392 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5393 cntl |= pipe << 28; /* Connect to correct pipe */
5394 } else {
5395 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5396 cntl |= CURSOR_MODE_DISABLE;
5397 }
9db4a9c7 5398 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5399
5400 intel_crtc->cursor_visible = visible;
5401 }
5402 /* and commit changes on next vblank */
9db4a9c7 5403 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5404}
5405
65a21cd6
JB		 5406static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5407{
5408 struct drm_device *dev = crtc->dev;
5409 struct drm_i915_private *dev_priv = dev->dev_private;
5410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5411 int pipe = intel_crtc->pipe;
5412 bool visible = base != 0;
5413
5414 if (intel_crtc->cursor_visible != visible) {
5415 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5416 if (base) {
5417 cntl &= ~CURSOR_MODE;
5418 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5419 } else {
5420 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5421 cntl |= CURSOR_MODE_DISABLE;
5422 }
5423 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5424
5425 intel_crtc->cursor_visible = visible;
5426 }
5427 /* and commit changes on next vblank */
5428 I915_WRITE(CURBASE_IVB(pipe), base);
5429}
5430
cda4b7d3 5431/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5432static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5433 bool on)
cda4b7d3
CW		 5434{
5435 struct drm_device *dev = crtc->dev;
5436 struct drm_i915_private *dev_priv = dev->dev_private;
5437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5438 int pipe = intel_crtc->pipe;
5439 int x = intel_crtc->cursor_x;
5440 int y = intel_crtc->cursor_y;
560b85bb 5441 u32 base, pos;
cda4b7d3
CW		 5442 bool visible;
5443
5444 pos = 0;
5445
6b383a7f 5446 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5447 base = intel_crtc->cursor_addr;
5448 if (x > (int) crtc->fb->width)
5449 base = 0;
5450
5451 if (y > (int) crtc->fb->height)
5452 base = 0;
5453 } else
5454 base = 0;
5455
5456 if (x < 0) {
5457 if (x + intel_crtc->cursor_width < 0)
5458 base = 0;
5459
5460 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5461 x = -x;
5462 }
5463 pos |= x << CURSOR_X_SHIFT;
5464
5465 if (y < 0) {
5466 if (y + intel_crtc->cursor_height < 0)
5467 base = 0;
5468
5469 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5470 y = -y;
5471 }
5472 pos |= y << CURSOR_Y_SHIFT;
5473
5474 visible = base != 0;
560b85bb 5475 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5476 return;
5477
0cd83aa9 5478 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5479 I915_WRITE(CURPOS_IVB(pipe), pos);
5480 ivb_update_cursor(crtc, base);
5481 } else {
5482 I915_WRITE(CURPOS(pipe), pos);
5483 if (IS_845G(dev) || IS_I865G(dev))
5484 i845_update_cursor(crtc, base);
5485 else
5486 i9xx_update_cursor(crtc, base);
5487 }
cda4b7d3
CW		 5488}
5489
79e53945 5490static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5491 struct drm_file *file,
79e53945
JB		 5492 uint32_t handle,
5493 uint32_t width, uint32_t height)
5494{
5495 struct drm_device *dev = crtc->dev;
5496 struct drm_i915_private *dev_priv = dev->dev_private;
5497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5498 struct drm_i915_gem_object *obj;
cda4b7d3 5499 uint32_t addr;
3f8bc370 5500 int ret;
79e53945 5501
79e53945
JB		 5502 /* if we want to turn off the cursor ignore width and height */
5503 if (!handle) {
28c97730 5504 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5505 addr = 0;
05394f39 5506 obj = NULL;
5004417d 5507 mutex_lock(&dev->struct_mutex);
3f8bc370 5508 goto finish;
79e53945
JB		 5509 }
5510
5511 /* Currently we only support 64x64 cursors */
5512 if (width != 64 || height != 64) {
5513 DRM_ERROR("we currently only support 64x64 cursors\n");
5514 return -EINVAL;
5515 }
5516
05394f39 5517 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5518 if (&obj->base == NULL)
79e53945
JB		 5519 return -ENOENT;
5520
05394f39 5521 if (obj->base.size < width * height * 4) {
79e53945 5522 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5523 ret = -ENOMEM;
5524 goto fail;
79e53945
JB		 5525 }
5526
71acb5eb 5527 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5528 mutex_lock(&dev->struct_mutex);
b295d1b6 5529 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5530 if (obj->tiling_mode) {
5531 DRM_ERROR("cursor cannot be tiled\n");
5532 ret = -EINVAL;
5533 goto fail_locked;
5534 }
5535
2da3b9b9 5536 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5537 if (ret) {
5538 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5539 goto fail_locked;
e7b526bb
CW		 5540 }
5541
d9e86c0e
CW		 5542 ret = i915_gem_object_put_fence(obj);
5543 if (ret) {
2da3b9b9 5544 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5545 goto fail_unpin;
5546 }
5547
05394f39 5548 addr = obj->gtt_offset;
71acb5eb 5549 } else {
6eeefaf3 5550 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5551 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5552 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5553 align);
71acb5eb
DA		 5554 if (ret) {
5555 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5556 goto fail_locked;
71acb5eb 5557 }
05394f39 5558 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5559 }
5560
a6c45cf0 5561 if (IS_GEN2(dev))
14b60391
JB		 5562 I915_WRITE(CURSIZE, (height << 12) | width);
5563
3f8bc370 5564 finish:
3f8bc370 5565 if (intel_crtc->cursor_bo) {
b295d1b6 5566 if (dev_priv->info->cursor_needs_physical) {
05394f39 5567 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5568 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5569 } else
5570 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5571 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5572 }
80824003 5573
7f9872e0 5574 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5575
5576 intel_crtc->cursor_addr = addr;
05394f39 5577 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5578 intel_crtc->cursor_width = width;
5579 intel_crtc->cursor_height = height;
5580
6b383a7f 5581 intel_crtc_update_cursor(crtc, true);
3f8bc370 5582
79e53945 5583 return 0;
e7b526bb 5584fail_unpin:
05394f39 5585 i915_gem_object_unpin(obj);
7f9872e0 5586fail_locked:
34b8686e 5587 mutex_unlock(&dev->struct_mutex);
bc9025bd 5588fail:
05394f39 5589 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5590 return ret;
79e53945
JB		 5591}
5592
5593static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5594{
79e53945 5595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5596
cda4b7d3
CW		 5597 intel_crtc->cursor_x = x;
5598 intel_crtc->cursor_y = y;
652c393a 5599
6b383a7f 5600 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5601
5602 return 0;
5603}
5604
5605/** Sets the color ramps on behalf of RandR */
5606void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5607 u16 blue, int regno)
5608{
5609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5610
5611 intel_crtc->lut_r[regno] = red >> 8;
5612 intel_crtc->lut_g[regno] = green >> 8;
5613 intel_crtc->lut_b[regno] = blue >> 8;
5614}
5615
b8c00ac5
DA		 5616void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5617 u16 *blue, int regno)
5618{
5619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5620
5621 *red = intel_crtc->lut_r[regno] << 8;
5622 *green = intel_crtc->lut_g[regno] << 8;
5623 *blue = intel_crtc->lut_b[regno] << 8;
5624}
5625
79e53945 5626static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5627 u16 *blue, uint32_t start, uint32_t size)
79e53945 5628{
7203425a 5629 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5631
7203425a 5632 for (i = start; i < end; i++) {
79e53945
JB		 5633 intel_crtc->lut_r[i] = red[i] >> 8;
5634 intel_crtc->lut_g[i] = green[i] >> 8;
5635 intel_crtc->lut_b[i] = blue[i] >> 8;
5636 }
5637
5638 intel_crtc_load_lut(crtc);
5639}
5640
5641/**
5642 * Get a pipe with a simple mode set on it for doing load-based monitor
5643 * detection.
5644 *
5645 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5646 * its requirements. The pipe will be connected to no other encoders.
79e53945 5647 *
c751ce4f 5648 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5649 * configured for it. In the future, it could choose to temporarily disable
5650 * some outputs to free up a pipe for its use.
5651 *
5652 * \return crtc, or NULL if no pipes are available.
5653 */
5654
5655/* VESA 640x480x72Hz mode to set on the pipe */
5656static struct drm_display_mode load_detect_mode = {
5657 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5658 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5659};
5660
d2dff872
CW		 5661static struct drm_framebuffer *
5662intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5663 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5664 struct drm_i915_gem_object *obj)
5665{
5666 struct intel_framebuffer *intel_fb;
5667 int ret;
5668
5669 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5670 if (!intel_fb) {
5671 drm_gem_object_unreference_unlocked(&obj->base);
5672 return ERR_PTR(-ENOMEM);
5673 }
5674
5675 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5676 if (ret) {
5677 drm_gem_object_unreference_unlocked(&obj->base);
5678 kfree(intel_fb);
5679 return ERR_PTR(ret);
5680 }
5681
5682 return &intel_fb->base;
5683}
5684
5685static u32
5686intel_framebuffer_pitch_for_width(int width, int bpp)
5687{
5688 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5689 return ALIGN(pitch, 64);
5690}
5691
5692static u32
5693intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5694{
5695 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5696 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5697}
5698
5699static struct drm_framebuffer *
5700intel_framebuffer_create_for_mode(struct drm_device *dev,
5701 struct drm_display_mode *mode,
5702 int depth, int bpp)
5703{
5704 struct drm_i915_gem_object *obj;
308e5bcb 5705 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5706
5707 obj = i915_gem_alloc_object(dev,
5708 intel_framebuffer_size_for_mode(mode, bpp));
5709 if (obj == NULL)
5710 return ERR_PTR(-ENOMEM);
5711
5712 mode_cmd.width = mode->hdisplay;
5713 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5714 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5715 bpp);
5ca0c34a 5716 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5717
5718 return intel_framebuffer_create(dev, &mode_cmd, obj);
5719}
5720
5721static struct drm_framebuffer *
5722mode_fits_in_fbdev(struct drm_device *dev,
5723 struct drm_display_mode *mode)
5724{
5725 struct drm_i915_private *dev_priv = dev->dev_private;
5726 struct drm_i915_gem_object *obj;
5727 struct drm_framebuffer *fb;
5728
5729 if (dev_priv->fbdev == NULL)
5730 return NULL;
5731
5732 obj = dev_priv->fbdev->ifb.obj;
5733 if (obj == NULL)
5734 return NULL;
5735
5736 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5737 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5738 fb->bits_per_pixel))
d2dff872
CW		 5739 return NULL;
5740
01f2c773 5741 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5742 return NULL;
5743
5744 return fb;
5745}
5746
d2434ab7 5747bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 5748 struct drm_display_mode *mode,
8261b191 5749 struct intel_load_detect_pipe *old)
79e53945
JB		 5750{
5751 struct intel_crtc *intel_crtc;
d2434ab7
DV		 5752 struct intel_encoder *intel_encoder =
5753 intel_attached_encoder(connector);
79e53945 5754 struct drm_crtc *possible_crtc;
4ef69c7a 5755 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5756 struct drm_crtc *crtc = NULL;
5757 struct drm_device *dev = encoder->dev;
94352cf9 5758 struct drm_framebuffer *fb;
79e53945
JB		 5759 int i = -1;
5760
d2dff872
CW		 5761 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5762 connector->base.id, drm_get_connector_name(connector),
5763 encoder->base.id, drm_get_encoder_name(encoder));
5764
79e53945
JB		 5765 /*
5766 * Algorithm gets a little messy:
7a5e4805 5767 *
79e53945
JB		 5768 * - if the connector already has an assigned crtc, use it (but make
5769 * sure it's on first)
7a5e4805 5770 *
79e53945
JB		 5771 * - try to find the first unused crtc that can drive this connector,
5772 * and use that if we find one
79e53945
JB		 5773 */
5774
5775 /* See if we already have a CRTC for this connector */
5776 if (encoder->crtc) {
5777 crtc = encoder->crtc;
8261b191 5778
24218aac 5779 old->dpms_mode = connector->dpms;
8261b191
CW		 5780 old->load_detect_temp = false;
5781
5782 /* Make sure the crtc and connector are running */
24218aac
DV		 5783 if (connector->dpms != DRM_MODE_DPMS_ON)
5784 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 5785
7173188d 5786 return true;
79e53945
JB		 5787 }
5788
5789 /* Find an unused one (if possible) */
5790 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5791 i++;
5792 if (!(encoder->possible_crtcs & (1 << i)))
5793 continue;
5794 if (!possible_crtc->enabled) {
5795 crtc = possible_crtc;
5796 break;
5797 }
79e53945
JB		 5798 }
5799
5800 /*
5801 * If we didn't find an unused CRTC, don't use any.
5802 */
5803 if (!crtc) {
7173188d
CW		 5804 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5805 return false;
79e53945
JB		 5806 }
5807
fc303101
DV		 5808 intel_encoder->new_crtc = to_intel_crtc(crtc);
5809 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 5810
5811 intel_crtc = to_intel_crtc(crtc);
24218aac 5812 old->dpms_mode = connector->dpms;
8261b191 5813 old->load_detect_temp = true;
d2dff872 5814 old->release_fb = NULL;
79e53945 5815
6492711d
CW		 5816 if (!mode)
5817 mode = &load_detect_mode;
79e53945 5818
d2dff872
CW		 5819 /* We need a framebuffer large enough to accommodate all accesses
5820 * that the plane may generate whilst we perform load detection.
5821 * We can not rely on the fbcon either being present (we get called
5822 * during its initialisation to detect all boot displays, or it may
5823 * not even exist) or that it is large enough to satisfy the
5824 * requested mode.
5825 */
94352cf9
DV		 5826 fb = mode_fits_in_fbdev(dev, mode);
5827 if (fb == NULL) {
d2dff872 5828 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 5829 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5830 old->release_fb = fb;
d2dff872
CW		 5831 } else
5832 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 5833 if (IS_ERR(fb)) {
d2dff872 5834 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 5835 goto fail;
79e53945 5836 }
79e53945 5837
94352cf9 5838 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 5839 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5840 if (old->release_fb)
5841 old->release_fb->funcs->destroy(old->release_fb);
24218aac 5842 goto fail;
79e53945 5843 }
7173188d 5844
79e53945 5845 /* let the connector get through one full cycle before testing */
9d0498a2 5846 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5847
7173188d 5848 return true;
24218aac
DV		 5849fail:
5850 connector->encoder = NULL;
5851 encoder->crtc = NULL;
24218aac 5852 return false;
79e53945
JB		 5853}
5854
d2434ab7 5855void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 5856 struct intel_load_detect_pipe *old)
79e53945 5857{
d2434ab7
DV		 5858 struct intel_encoder *intel_encoder =
5859 intel_attached_encoder(connector);
4ef69c7a 5860 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 5861
d2dff872
CW		 5862 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5863 connector->base.id, drm_get_connector_name(connector),
5864 encoder->base.id, drm_get_encoder_name(encoder));
5865
8261b191 5866 if (old->load_detect_temp) {
fc303101
DV		 5867 struct drm_crtc *crtc = encoder->crtc;
5868
5869 to_intel_connector(connector)->new_encoder = NULL;
5870 intel_encoder->new_crtc = NULL;
5871 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 5872
5873 if (old->release_fb)
5874 old->release_fb->funcs->destroy(old->release_fb);
5875
0622a53c 5876 return;
79e53945
JB		 5877 }
5878
c751ce4f 5879 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 5880 if (old->dpms_mode != DRM_MODE_DPMS_ON)
5881 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 5882}
5883
5884/* Returns the clock of the currently programmed mode of the given pipe. */
5885static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5886{
5887 struct drm_i915_private *dev_priv = dev->dev_private;
5888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5889 int pipe = intel_crtc->pipe;
548f245b 5890 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5891 u32 fp;
5892 intel_clock_t clock;
5893
5894 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5895 fp = I915_READ(FP0(pipe));
79e53945 5896 else
39adb7a5 5897 fp = I915_READ(FP1(pipe));
79e53945
JB		 5898
5899 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5900 if (IS_PINEVIEW(dev)) {
5901 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5902 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5903 } else {
5904 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5905 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5906 }
5907
a6c45cf0 5908 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5909 if (IS_PINEVIEW(dev))
5910 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5911 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5912 else
5913 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5914 DPLL_FPA01_P1_POST_DIV_SHIFT);
5915
5916 switch (dpll & DPLL_MODE_MASK) {
5917 case DPLLB_MODE_DAC_SERIAL:
5918 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5919 5 : 10;
5920 break;
5921 case DPLLB_MODE_LVDS:
5922 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5923 7 : 14;
5924 break;
5925 default:
28c97730 5926 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5927 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5928 return 0;
5929 }
5930
5931 /* XXX: Handle the 100Mhz refclk */
2177832f 5932 intel_clock(dev, 96000, &clock);
79e53945
JB		 5933 } else {
5934 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5935
5936 if (is_lvds) {
5937 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5938 DPLL_FPA01_P1_POST_DIV_SHIFT);
5939 clock.p2 = 14;
5940
5941 if ((dpll & PLL_REF_INPUT_MASK) ==
5942 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5943 /* XXX: might not be 66MHz */
2177832f 5944 intel_clock(dev, 66000, &clock);
79e53945 5945 } else
2177832f 5946 intel_clock(dev, 48000, &clock);
79e53945
JB		 5947 } else {
5948 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5949 clock.p1 = 2;
5950 else {
5951 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5952 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5953 }
5954 if (dpll & PLL_P2_DIVIDE_BY_4)
5955 clock.p2 = 4;
5956 else
5957 clock.p2 = 2;
5958
2177832f 5959 intel_clock(dev, 48000, &clock);
79e53945
JB		 5960 }
5961 }
5962
5963 /* XXX: It would be nice to validate the clocks, but we can't reuse
5964 * i830PllIsValid() because it relies on the xf86_config connector
5965 * configuration being accurate, which it isn't necessarily.
5966 */
5967
5968 return clock.dot;
5969}
5970
5971/** Returns the currently programmed mode of the given pipe. */
5972struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5973 struct drm_crtc *crtc)
5974{
548f245b 5975 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5977 int pipe = intel_crtc->pipe;
5978 struct drm_display_mode *mode;
548f245b
JB		 5979 int htot = I915_READ(HTOTAL(pipe));
5980 int hsync = I915_READ(HSYNC(pipe));
5981 int vtot = I915_READ(VTOTAL(pipe));
5982 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5983
5984 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5985 if (!mode)
5986 return NULL;
5987
5988 mode->clock = intel_crtc_clock_get(dev, crtc);
5989 mode->hdisplay = (htot & 0xffff) + 1;
5990 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5991 mode->hsync_start = (hsync & 0xffff) + 1;
5992 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5993 mode->vdisplay = (vtot & 0xffff) + 1;
5994 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5995 mode->vsync_start = (vsync & 0xffff) + 1;
5996 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5997
5998 drm_mode_set_name(mode);
79e53945
JB		 5999
6000 return mode;
6001}
6002
3dec0095 6003static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6004{
6005 struct drm_device *dev = crtc->dev;
6006 drm_i915_private_t *dev_priv = dev->dev_private;
6007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6008 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6009 int dpll_reg = DPLL(pipe);
6010 int dpll;
652c393a 6011
bad720ff 6012 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6013 return;
6014
6015 if (!dev_priv->lvds_downclock_avail)
6016 return;
6017
dbdc6479 6018 dpll = I915_READ(dpll_reg);
652c393a 6019 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6020 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6021
8ac5a6d5 6022 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6023
6024 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6025 I915_WRITE(dpll_reg, dpll);
9d0498a2 6026 intel_wait_for_vblank(dev, pipe);
dbdc6479 6027
652c393a
JB		 6028 dpll = I915_READ(dpll_reg);
6029 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6030 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6031 }
652c393a
JB		 6032}
6033
6034static void intel_decrease_pllclock(struct drm_crtc *crtc)
6035{
6036 struct drm_device *dev = crtc->dev;
6037 drm_i915_private_t *dev_priv = dev->dev_private;
6038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6039
bad720ff 6040 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6041 return;
6042
6043 if (!dev_priv->lvds_downclock_avail)
6044 return;
6045
6046 /*
6047 * Since this is called by a timer, we should never get here in
6048 * the manual case.
6049 */
6050 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6051 int pipe = intel_crtc->pipe;
6052 int dpll_reg = DPLL(pipe);
6053 int dpll;
f6e5b160 6054
44d98a61 6055 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6056
8ac5a6d5 6057 assert_panel_unlocked(dev_priv, pipe);
652c393a 6058
dc257cf1 6059 dpll = I915_READ(dpll_reg);
652c393a
JB		 6060 dpll |= DISPLAY_RATE_SELECT_FPA1;
6061 I915_WRITE(dpll_reg, dpll);
9d0498a2 6062 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6063 dpll = I915_READ(dpll_reg);
6064 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6065 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6066 }
6067
6068}
6069
f047e395
CW		 6070void intel_mark_busy(struct drm_device *dev)
6071{
f047e395
CW		 6072 i915_update_gfx_val(dev->dev_private);
6073}
6074
6075void intel_mark_idle(struct drm_device *dev)
652c393a 6076{
f047e395
CW		 6077}
6078
6079void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6080{
6081 struct drm_device *dev = obj->base.dev;
652c393a 6082 struct drm_crtc *crtc;
652c393a
JB		 6083
6084 if (!i915_powersave)
6085 return;
6086
652c393a 6087 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6088 if (!crtc->fb)
6089 continue;
6090
f047e395
CW		 6091 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6092 intel_increase_pllclock(crtc);
652c393a 6093 }
652c393a
JB		 6094}
6095
f047e395 6096void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6097{
f047e395
CW		 6098 struct drm_device *dev = obj->base.dev;
6099 struct drm_crtc *crtc;
652c393a 6100
f047e395 6101 if (!i915_powersave)
acb87dfb
CW		 6102 return;
6103
652c393a
JB		 6104 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6105 if (!crtc->fb)
6106 continue;
6107
f047e395
CW		 6108 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6109 intel_decrease_pllclock(crtc);
652c393a
JB		 6110 }
6111}
6112
79e53945
JB		 6113static void intel_crtc_destroy(struct drm_crtc *crtc)
6114{
6115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6116 struct drm_device *dev = crtc->dev;
6117 struct intel_unpin_work *work;
6118 unsigned long flags;
6119
6120 spin_lock_irqsave(&dev->event_lock, flags);
6121 work = intel_crtc->unpin_work;
6122 intel_crtc->unpin_work = NULL;
6123 spin_unlock_irqrestore(&dev->event_lock, flags);
6124
6125 if (work) {
6126 cancel_work_sync(&work->work);
6127 kfree(work);
6128 }
79e53945
JB		 6129
6130 drm_crtc_cleanup(crtc);
67e77c5a 6131
79e53945
JB		 6132 kfree(intel_crtc);
6133}
6134
6b95a207
KH		 6135static void intel_unpin_work_fn(struct work_struct *__work)
6136{
6137 struct intel_unpin_work *work =
6138 container_of(__work, struct intel_unpin_work, work);
6139
6140 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6141 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6142 drm_gem_object_unreference(&work->pending_flip_obj->base);
6143 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6144
7782de3b 6145 intel_update_fbc(work->dev);
6b95a207
KH		 6146 mutex_unlock(&work->dev->struct_mutex);
6147 kfree(work);
6148}
6149
1afe3e9d 6150static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6151 struct drm_crtc *crtc)
6b95a207
KH		 6152{
6153 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6155 struct intel_unpin_work *work;
05394f39 6156 struct drm_i915_gem_object *obj;
6b95a207 6157 struct drm_pending_vblank_event *e;
49b14a5c 6158 struct timeval tnow, tvbl;
6b95a207
KH		 6159 unsigned long flags;
6160
6161 /* Ignore early vblank irqs */
6162 if (intel_crtc == NULL)
6163 return;
6164
49b14a5c
MK		 6165 do_gettimeofday(&tnow);
6166
6b95a207
KH		 6167 spin_lock_irqsave(&dev->event_lock, flags);
6168 work = intel_crtc->unpin_work;
6169 if (work == NULL || !work->pending) {
6170 spin_unlock_irqrestore(&dev->event_lock, flags);
6171 return;
6172 }
6173
6174 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6175
6176 if (work->event) {
6177 e = work->event;
49b14a5c 6178 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6179
6180 /* Called before vblank count and timestamps have
6181 * been updated for the vblank interval of flip
6182 * completion? Need to increment vblank count and
6183 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6184 * to account for this. We assume this happened if we
6185 * get called over 0.9 frame durations after the last
6186 * timestamped vblank.
6187 *
6188 * This calculation can not be used with vrefresh rates
6189 * below 5Hz (10Hz to be on the safe side) without
6190 * promoting to 64 integers.
0af7e4df 6191 */
49b14a5c
MK		 6192 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6193 9 * crtc->framedur_ns) {
0af7e4df 6194 e->event.sequence++;
49b14a5c
MK		 6195 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6196 crtc->framedur_ns);
0af7e4df
MK		 6197 }
6198
49b14a5c
MK		 6199 e->event.tv_sec = tvbl.tv_sec;
6200 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6201
6b95a207
KH		 6202 list_add_tail(&e->base.link,
6203 &e->base.file_priv->event_list);
6204 wake_up_interruptible(&e->base.file_priv->event_wait);
6205 }
6206
0af7e4df
MK		 6207 drm_vblank_put(dev, intel_crtc->pipe);
6208
6b95a207
KH		 6209 spin_unlock_irqrestore(&dev->event_lock, flags);
6210
05394f39 6211 obj = work->old_fb_obj;
d9e86c0e 6212
e59f2bac 6213 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6214 &obj->pending_flip.counter);
6215 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6216 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6217
6b95a207 6218 schedule_work(&work->work);
e5510fac
JB		 6219
6220 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6221}
6222
1afe3e9d
JB		 6223void intel_finish_page_flip(struct drm_device *dev, int pipe)
6224{
6225 drm_i915_private_t *dev_priv = dev->dev_private;
6226 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6227
49b14a5c 6228 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6229}
6230
6231void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6232{
6233 drm_i915_private_t *dev_priv = dev->dev_private;
6234 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6235
49b14a5c 6236 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6237}
6238
6b95a207
KH		 6239void intel_prepare_page_flip(struct drm_device *dev, int plane)
6240{
6241 drm_i915_private_t *dev_priv = dev->dev_private;
6242 struct intel_crtc *intel_crtc =
6243 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6244 unsigned long flags;
6245
6246 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6247 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6248 if ((++intel_crtc->unpin_work->pending) > 1)
6249 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6250 } else {
6251 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6252 }
6b95a207
KH		 6253 spin_unlock_irqrestore(&dev->event_lock, flags);
6254}
6255
8c9f3aaf
JB		 6256static int intel_gen2_queue_flip(struct drm_device *dev,
6257 struct drm_crtc *crtc,
6258 struct drm_framebuffer *fb,
6259 struct drm_i915_gem_object *obj)
6260{
6261 struct drm_i915_private *dev_priv = dev->dev_private;
6262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6263 u32 flip_mask;
6d90c952 6264 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6265 int ret;
6266
6d90c952 6267 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6268 if (ret)
83d4092b 6269 goto err;
8c9f3aaf 6270
6d90c952 6271 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6272 if (ret)
83d4092b 6273 goto err_unpin;
8c9f3aaf
JB		 6274
6275 /* Can't queue multiple flips, so wait for the previous
6276 * one to finish before executing the next.
6277 */
6278 if (intel_crtc->plane)
6279 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6280 else
6281 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6282 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6283 intel_ring_emit(ring, MI_NOOP);
6284 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6285 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6286 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6287 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6288 intel_ring_emit(ring, 0); /* aux display base address, unused */
6289 intel_ring_advance(ring);
83d4092b
CW		 6290 return 0;
6291
6292err_unpin:
6293 intel_unpin_fb_obj(obj);
6294err:
8c9f3aaf
JB		 6295 return ret;
6296}
6297
6298static int intel_gen3_queue_flip(struct drm_device *dev,
6299 struct drm_crtc *crtc,
6300 struct drm_framebuffer *fb,
6301 struct drm_i915_gem_object *obj)
6302{
6303 struct drm_i915_private *dev_priv = dev->dev_private;
6304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6305 u32 flip_mask;
6d90c952 6306 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6307 int ret;
6308
6d90c952 6309 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6310 if (ret)
83d4092b 6311 goto err;
8c9f3aaf 6312
6d90c952 6313 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6314 if (ret)
83d4092b 6315 goto err_unpin;
8c9f3aaf
JB		 6316
6317 if (intel_crtc->plane)
6318 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6319 else
6320 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6321 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6322 intel_ring_emit(ring, MI_NOOP);
6323 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6324 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6325 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6326 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6327 intel_ring_emit(ring, MI_NOOP);
6328
6329 intel_ring_advance(ring);
83d4092b
CW		 6330 return 0;
6331
6332err_unpin:
6333 intel_unpin_fb_obj(obj);
6334err:
8c9f3aaf
JB		 6335 return ret;
6336}
6337
6338static int intel_gen4_queue_flip(struct drm_device *dev,
6339 struct drm_crtc *crtc,
6340 struct drm_framebuffer *fb,
6341 struct drm_i915_gem_object *obj)
6342{
6343 struct drm_i915_private *dev_priv = dev->dev_private;
6344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6345 uint32_t pf, pipesrc;
6d90c952 6346 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6347 int ret;
6348
6d90c952 6349 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6350 if (ret)
83d4092b 6351 goto err;
8c9f3aaf 6352
6d90c952 6353 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6354 if (ret)
83d4092b 6355 goto err_unpin;
8c9f3aaf
JB		 6356
6357 /* i965+ uses the linear or tiled offsets from the
6358 * Display Registers (which do not change across a page-flip)
6359 * so we need only reprogram the base address.
6360 */
6d90c952
DV		 6361 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6362 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6363 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6364 intel_ring_emit(ring,
6365 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6366 obj->tiling_mode);
8c9f3aaf
JB		 6367
6368 /* XXX Enabling the panel-fitter across page-flip is so far
6369 * untested on non-native modes, so ignore it for now.
6370 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6371 */
6372 pf = 0;
6373 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6374 intel_ring_emit(ring, pf | pipesrc);
6375 intel_ring_advance(ring);
83d4092b
CW		 6376 return 0;
6377
6378err_unpin:
6379 intel_unpin_fb_obj(obj);
6380err:
8c9f3aaf
JB		 6381 return ret;
6382}
6383
6384static int intel_gen6_queue_flip(struct drm_device *dev,
6385 struct drm_crtc *crtc,
6386 struct drm_framebuffer *fb,
6387 struct drm_i915_gem_object *obj)
6388{
6389 struct drm_i915_private *dev_priv = dev->dev_private;
6390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6391 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6392 uint32_t pf, pipesrc;
6393 int ret;
6394
6d90c952 6395 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6396 if (ret)
83d4092b 6397 goto err;
8c9f3aaf 6398
6d90c952 6399 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6400 if (ret)
83d4092b 6401 goto err_unpin;
8c9f3aaf 6402
6d90c952
DV		 6403 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6404 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6405 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 6406 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 6407
dc257cf1
DV		 6408 /* Contrary to the suggestions in the documentation,
6409 * "Enable Panel Fitter" does not seem to be required when page
6410 * flipping with a non-native mode, and worse causes a normal
6411 * modeset to fail.
6412 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6413 */
6414 pf = 0;
8c9f3aaf 6415 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6416 intel_ring_emit(ring, pf | pipesrc);
6417 intel_ring_advance(ring);
83d4092b
CW		 6418 return 0;
6419
6420err_unpin:
6421 intel_unpin_fb_obj(obj);
6422err:
8c9f3aaf
JB		 6423 return ret;
6424}
6425
7c9017e5
JB		 6426/*
6427 * On gen7 we currently use the blit ring because (in early silicon at least)
6428 * the render ring doesn't give us interrpts for page flip completion, which
6429 * means clients will hang after the first flip is queued. Fortunately the
6430 * blit ring generates interrupts properly, so use it instead.
6431 */
6432static int intel_gen7_queue_flip(struct drm_device *dev,
6433 struct drm_crtc *crtc,
6434 struct drm_framebuffer *fb,
6435 struct drm_i915_gem_object *obj)
6436{
6437 struct drm_i915_private *dev_priv = dev->dev_private;
6438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6439 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 6440 uint32_t plane_bit = 0;
7c9017e5
JB		 6441 int ret;
6442
6443 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6444 if (ret)
83d4092b 6445 goto err;
7c9017e5 6446
cb05d8de
DV		 6447 switch(intel_crtc->plane) {
6448 case PLANE_A:
6449 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6450 break;
6451 case PLANE_B:
6452 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6453 break;
6454 case PLANE_C:
6455 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6456 break;
6457 default:
6458 WARN_ONCE(1, "unknown plane in flip command\n");
6459 ret = -ENODEV;
ab3951eb 6460 goto err_unpin;
cb05d8de
DV		 6461 }
6462
7c9017e5
JB		 6463 ret = intel_ring_begin(ring, 4);
6464 if (ret)
83d4092b 6465 goto err_unpin;
7c9017e5 6466
cb05d8de 6467 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 6468 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 6469 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 6470 intel_ring_emit(ring, (MI_NOOP));
6471 intel_ring_advance(ring);
83d4092b
CW		 6472 return 0;
6473
6474err_unpin:
6475 intel_unpin_fb_obj(obj);
6476err:
7c9017e5
JB		 6477 return ret;
6478}
6479
8c9f3aaf
JB		 6480static int intel_default_queue_flip(struct drm_device *dev,
6481 struct drm_crtc *crtc,
6482 struct drm_framebuffer *fb,
6483 struct drm_i915_gem_object *obj)
6484{
6485 return -ENODEV;
6486}
6487
6b95a207
KH		 6488static int intel_crtc_page_flip(struct drm_crtc *crtc,
6489 struct drm_framebuffer *fb,
6490 struct drm_pending_vblank_event *event)
6491{
6492 struct drm_device *dev = crtc->dev;
6493 struct drm_i915_private *dev_priv = dev->dev_private;
6494 struct intel_framebuffer *intel_fb;
05394f39 6495 struct drm_i915_gem_object *obj;
6b95a207
KH		 6496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6497 struct intel_unpin_work *work;
8c9f3aaf 6498 unsigned long flags;
52e68630 6499 int ret;
6b95a207 6500
e6a595d2
VS		 6501 /* Can't change pixel format via MI display flips. */
6502 if (fb->pixel_format != crtc->fb->pixel_format)
6503 return -EINVAL;
6504
6505 /*
6506 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6507 * Note that pitch changes could also affect these register.
6508 */
6509 if (INTEL_INFO(dev)->gen > 3 &&
6510 (fb->offsets[0] != crtc->fb->offsets[0] ||
6511 fb->pitches[0] != crtc->fb->pitches[0]))
6512 return -EINVAL;
6513
6b95a207
KH		 6514 work = kzalloc(sizeof *work, GFP_KERNEL);
6515 if (work == NULL)
6516 return -ENOMEM;
6517
6b95a207
KH		 6518 work->event = event;
6519 work->dev = crtc->dev;
6520 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6521 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6522 INIT_WORK(&work->work, intel_unpin_work_fn);
6523
7317c75e
JB		 6524 ret = drm_vblank_get(dev, intel_crtc->pipe);
6525 if (ret)
6526 goto free_work;
6527
6b95a207
KH		 6528 /* We borrow the event spin lock for protecting unpin_work */
6529 spin_lock_irqsave(&dev->event_lock, flags);
6530 if (intel_crtc->unpin_work) {
6531 spin_unlock_irqrestore(&dev->event_lock, flags);
6532 kfree(work);
7317c75e 6533 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6534
6535 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6536 return -EBUSY;
6537 }
6538 intel_crtc->unpin_work = work;
6539 spin_unlock_irqrestore(&dev->event_lock, flags);
6540
6541 intel_fb = to_intel_framebuffer(fb);
6542 obj = intel_fb->obj;
6543
79158103
CW		 6544 ret = i915_mutex_lock_interruptible(dev);
6545 if (ret)
6546 goto cleanup;
6b95a207 6547
75dfca80 6548 /* Reference the objects for the scheduled work. */
05394f39
CW		 6549 drm_gem_object_reference(&work->old_fb_obj->base);
6550 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6551
6552 crtc->fb = fb;
96b099fd 6553
e1f99ce6 6554 work->pending_flip_obj = obj;
e1f99ce6 6555
4e5359cd
SF		 6556 work->enable_stall_check = true;
6557
e1f99ce6
CW		 6558 /* Block clients from rendering to the new back buffer until
6559 * the flip occurs and the object is no longer visible.
6560 */
05394f39 6561 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6562
8c9f3aaf
JB		 6563 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6564 if (ret)
6565 goto cleanup_pending;
6b95a207 6566
7782de3b 6567 intel_disable_fbc(dev);
f047e395 6568 intel_mark_fb_busy(obj);
6b95a207
KH		 6569 mutex_unlock(&dev->struct_mutex);
6570
e5510fac
JB		 6571 trace_i915_flip_request(intel_crtc->plane, obj);
6572
6b95a207 6573 return 0;
96b099fd 6574
8c9f3aaf
JB		 6575cleanup_pending:
6576 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6577 drm_gem_object_unreference(&work->old_fb_obj->base);
6578 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6579 mutex_unlock(&dev->struct_mutex);
6580
79158103 6581cleanup:
96b099fd
CW		 6582 spin_lock_irqsave(&dev->event_lock, flags);
6583 intel_crtc->unpin_work = NULL;
6584 spin_unlock_irqrestore(&dev->event_lock, flags);
6585
7317c75e
JB		 6586 drm_vblank_put(dev, intel_crtc->pipe);
6587free_work:
96b099fd
CW		 6588 kfree(work);
6589
6590 return ret;
6b95a207
KH		 6591}
6592
f6e5b160 6593static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 6594 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6595 .load_lut = intel_crtc_load_lut,
976f8a20 6596 .disable = intel_crtc_noop,
f6e5b160
CW		 6597};
6598
6ed0f796 6599bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 6600{
6ed0f796
DV		 6601 struct intel_encoder *other_encoder;
6602 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 6603
6ed0f796
DV		 6604 if (WARN_ON(!crtc))
6605 return false;
6606
6607 list_for_each_entry(other_encoder,
6608 &crtc->dev->mode_config.encoder_list,
6609 base.head) {
6610
6611 if (&other_encoder->new_crtc->base != crtc ||
6612 encoder == other_encoder)
6613 continue;
6614 else
6615 return true;
f47166d2
CW		 6616 }
6617
6ed0f796
DV		 6618 return false;
6619}
47f1c6c9 6620
50f56119
DV		 6621static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6622 struct drm_crtc *crtc)
6623{
6624 struct drm_device *dev;
6625 struct drm_crtc *tmp;
6626 int crtc_mask = 1;
47f1c6c9 6627
50f56119 6628 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 6629
50f56119 6630 dev = crtc->dev;
47f1c6c9 6631
50f56119
DV		 6632 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6633 if (tmp == crtc)
6634 break;
6635 crtc_mask <<= 1;
6636 }
47f1c6c9 6637
50f56119
DV		 6638 if (encoder->possible_crtcs & crtc_mask)
6639 return true;
6640 return false;
47f1c6c9 6641}
79e53945 6642
9a935856
DV		 6643/**
6644 * intel_modeset_update_staged_output_state
6645 *
6646 * Updates the staged output configuration state, e.g. after we've read out the
6647 * current hw state.
6648 */
6649static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 6650{
9a935856
DV		 6651 struct intel_encoder *encoder;
6652 struct intel_connector *connector;
f6e5b160 6653
9a935856
DV		 6654 list_for_each_entry(connector, &dev->mode_config.connector_list,
6655 base.head) {
6656 connector->new_encoder =
6657 to_intel_encoder(connector->base.encoder);
6658 }
f6e5b160 6659
9a935856
DV		 6660 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6661 base.head) {
6662 encoder->new_crtc =
6663 to_intel_crtc(encoder->base.crtc);
6664 }
f6e5b160
CW		 6665}
6666
9a935856
DV		 6667/**
6668 * intel_modeset_commit_output_state
6669 *
6670 * This function copies the stage display pipe configuration to the real one.
6671 */
6672static void intel_modeset_commit_output_state(struct drm_device *dev)
6673{
6674 struct intel_encoder *encoder;
6675 struct intel_connector *connector;
f6e5b160 6676
9a935856
DV		 6677 list_for_each_entry(connector, &dev->mode_config.connector_list,
6678 base.head) {
6679 connector->base.encoder = &connector->new_encoder->base;
6680 }
f6e5b160 6681
9a935856
DV		 6682 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6683 base.head) {
6684 encoder->base.crtc = &encoder->new_crtc->base;
6685 }
6686}
6687
7758a113
DV		 6688static struct drm_display_mode *
6689intel_modeset_adjusted_mode(struct drm_crtc *crtc,
6690 struct drm_display_mode *mode)
ee7b9f93 6691{
7758a113
DV		 6692 struct drm_device *dev = crtc->dev;
6693 struct drm_display_mode *adjusted_mode;
6694 struct drm_encoder_helper_funcs *encoder_funcs;
6695 struct intel_encoder *encoder;
ee7b9f93 6696
7758a113
DV		 6697 adjusted_mode = drm_mode_duplicate(dev, mode);
6698 if (!adjusted_mode)
6699 return ERR_PTR(-ENOMEM);
6700
6701 /* Pass our mode to the connectors and the CRTC to give them a chance to
6702 * adjust it according to limitations or connector properties, and also
6703 * a chance to reject the mode entirely.
6704 */
6705 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6706 base.head) {
6707
6708 if (&encoder->new_crtc->base != crtc)
6709 continue;
6710 encoder_funcs = encoder->base.helper_private;
6711 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
6712 adjusted_mode))) {
6713 DRM_DEBUG_KMS("Encoder fixup failed\n");
6714 goto fail;
6715 }
ee7b9f93
JB		 6716 }
6717
7758a113
DV		 6718 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
6719 DRM_DEBUG_KMS("CRTC fixup failed\n");
6720 goto fail;
ee7b9f93 6721 }
7758a113
DV		 6722 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6723
6724 return adjusted_mode;
6725fail:
6726 drm_mode_destroy(dev, adjusted_mode);
6727 return ERR_PTR(-EINVAL);
ee7b9f93
JB		 6728}
6729
e2e1ed41
DV		 6730/* Computes which crtcs are affected and sets the relevant bits in the mask. For
6731 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
6732static void
6733intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
6734 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 6735{
6736 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 6737 struct drm_device *dev = crtc->dev;
6738 struct intel_encoder *encoder;
6739 struct intel_connector *connector;
6740 struct drm_crtc *tmp_crtc;
79e53945 6741
e2e1ed41 6742 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 6743
e2e1ed41
DV		 6744 /* Check which crtcs have changed outputs connected to them, these need
6745 * to be part of the prepare_pipes mask. We don't (yet) support global
6746 * modeset across multiple crtcs, so modeset_pipes will only have one
6747 * bit set at most. */
6748 list_for_each_entry(connector, &dev->mode_config.connector_list,
6749 base.head) {
6750 if (connector->base.encoder == &connector->new_encoder->base)
6751 continue;
79e53945 6752
e2e1ed41
DV		 6753 if (connector->base.encoder) {
6754 tmp_crtc = connector->base.encoder->crtc;
6755
6756 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6757 }
6758
6759 if (connector->new_encoder)
6760 *prepare_pipes |=
6761 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 6762 }
6763
e2e1ed41
DV		 6764 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6765 base.head) {
6766 if (encoder->base.crtc == &encoder->new_crtc->base)
6767 continue;
6768
6769 if (encoder->base.crtc) {
6770 tmp_crtc = encoder->base.crtc;
6771
6772 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6773 }
6774
6775 if (encoder->new_crtc)
6776 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 6777 }
6778
e2e1ed41
DV		 6779 /* Check for any pipes that will be fully disabled ... */
6780 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6781 base.head) {
6782 bool used = false;
22fd0fab 6783
e2e1ed41
DV		 6784 /* Don't try to disable disabled crtcs. */
6785 if (!intel_crtc->base.enabled)
6786 continue;
7e7d76c3 6787
e2e1ed41
DV		 6788 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6789 base.head) {
6790 if (encoder->new_crtc == intel_crtc)
6791 used = true;
6792 }
6793
6794 if (!used)
6795 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 6796 }
6797
e2e1ed41
DV		 6798
6799 /* set_mode is also used to update properties on life display pipes. */
6800 intel_crtc = to_intel_crtc(crtc);
6801 if (crtc->enabled)
6802 *prepare_pipes |= 1 << intel_crtc->pipe;
6803
6804 /* We only support modeset on one single crtc, hence we need to do that
6805 * only for the passed in crtc iff we change anything else than just
6806 * disable crtcs.
6807 *
6808 * This is actually not true, to be fully compatible with the old crtc
6809 * helper we automatically disable _any_ output (i.e. doesn't need to be
6810 * connected to the crtc we're modesetting on) if it's disconnected.
6811 * Which is a rather nutty api (since changed the output configuration
6812 * without userspace's explicit request can lead to confusion), but
6813 * alas. Hence we currently need to modeset on all pipes we prepare. */
6814 if (*prepare_pipes)
6815 *modeset_pipes = *prepare_pipes;
6816
6817 /* ... and mask these out. */
6818 *modeset_pipes &= ~(*disable_pipes);
6819 *prepare_pipes &= ~(*disable_pipes);
6820}
6821
ea9d758d
DV		 6822static bool intel_crtc_in_use(struct drm_crtc *crtc)
6823{
6824 struct drm_encoder *encoder;
6825 struct drm_device *dev = crtc->dev;
6826
6827 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
6828 if (encoder->crtc == crtc)
6829 return true;
6830
6831 return false;
6832}
6833
6834static void
6835intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
6836{
6837 struct intel_encoder *intel_encoder;
6838 struct intel_crtc *intel_crtc;
6839 struct drm_connector *connector;
6840
6841 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
6842 base.head) {
6843 if (!intel_encoder->base.crtc)
6844 continue;
6845
6846 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
6847
6848 if (prepare_pipes & (1 << intel_crtc->pipe))
6849 intel_encoder->connectors_active = false;
6850 }
6851
6852 intel_modeset_commit_output_state(dev);
6853
6854 /* Update computed state. */
6855 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6856 base.head) {
6857 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
6858 }
6859
6860 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6861 if (!connector->encoder || !connector->encoder->crtc)
6862 continue;
6863
6864 intel_crtc = to_intel_crtc(connector->encoder->crtc);
6865
6866 if (prepare_pipes & (1 << intel_crtc->pipe)) {
6867 connector->dpms = DRM_MODE_DPMS_ON;
6868
6869 intel_encoder = to_intel_encoder(connector->encoder);
6870 intel_encoder->connectors_active = true;
6871 }
6872 }
6873
6874}
6875
25c5b266
DV		 6876#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
6877 list_for_each_entry((intel_crtc), \
6878 &(dev)->mode_config.crtc_list, \
6879 base.head) \
6880 if (mask & (1 <<(intel_crtc)->pipe)) \
6881
b980514c 6882void
8af6cf88
DV		 6883intel_modeset_check_state(struct drm_device *dev)
6884{
6885 struct intel_crtc *crtc;
6886 struct intel_encoder *encoder;
6887 struct intel_connector *connector;
6888
6889 list_for_each_entry(connector, &dev->mode_config.connector_list,
6890 base.head) {
6891 /* This also checks the encoder/connector hw state with the
6892 * ->get_hw_state callbacks. */
6893 intel_connector_check_state(connector);
6894
6895 WARN(&connector->new_encoder->base != connector->base.encoder,
6896 "connector's staged encoder doesn't match current encoder\n");
6897 }
6898
6899 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6900 base.head) {
6901 bool enabled = false;
6902 bool active = false;
6903 enum pipe pipe, tracked_pipe;
6904
6905 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
6906 encoder->base.base.id,
6907 drm_get_encoder_name(&encoder->base));
6908
6909 WARN(&encoder->new_crtc->base != encoder->base.crtc,
6910 "encoder's stage crtc doesn't match current crtc\n");
6911 WARN(encoder->connectors_active && !encoder->base.crtc,
6912 "encoder's active_connectors set, but no crtc\n");
6913
6914 list_for_each_entry(connector, &dev->mode_config.connector_list,
6915 base.head) {
6916 if (connector->base.encoder != &encoder->base)
6917 continue;
6918 enabled = true;
6919 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
6920 active = true;
6921 }
6922 WARN(!!encoder->base.crtc != enabled,
6923 "encoder's enabled state mismatch "
6924 "(expected %i, found %i)\n",
6925 !!encoder->base.crtc, enabled);
6926 WARN(active && !encoder->base.crtc,
6927 "active encoder with no crtc\n");
6928
6929 WARN(encoder->connectors_active != active,
6930 "encoder's computed active state doesn't match tracked active state "
6931 "(expected %i, found %i)\n", active, encoder->connectors_active);
6932
6933 active = encoder->get_hw_state(encoder, &pipe);
6934 WARN(active != encoder->connectors_active,
6935 "encoder's hw state doesn't match sw tracking "
6936 "(expected %i, found %i)\n",
6937 encoder->connectors_active, active);
6938
6939 if (!encoder->base.crtc)
6940 continue;
6941
6942 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
6943 WARN(active && pipe != tracked_pipe,
6944 "active encoder's pipe doesn't match"
6945 "(expected %i, found %i)\n",
6946 tracked_pipe, pipe);
6947
6948 }
6949
6950 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
6951 base.head) {
6952 bool enabled = false;
6953 bool active = false;
6954
6955 DRM_DEBUG_KMS("[CRTC:%d]\n",
6956 crtc->base.base.id);
6957
6958 WARN(crtc->active && !crtc->base.enabled,
6959 "active crtc, but not enabled in sw tracking\n");
6960
6961 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6962 base.head) {
6963 if (encoder->base.crtc != &crtc->base)
6964 continue;
6965 enabled = true;
6966 if (encoder->connectors_active)
6967 active = true;
6968 }
6969 WARN(active != crtc->active,
6970 "crtc's computed active state doesn't match tracked active state "
6971 "(expected %i, found %i)\n", active, crtc->active);
6972 WARN(enabled != crtc->base.enabled,
6973 "crtc's computed enabled state doesn't match tracked enabled state "
6974 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
6975
6976 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
6977 }
6978}
6979
a6778b3c
DV		 6980bool intel_set_mode(struct drm_crtc *crtc,
6981 struct drm_display_mode *mode,
94352cf9 6982 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 6983{
6984 struct drm_device *dev = crtc->dev;
dbf2b54e 6985 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 6986 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
a6778b3c 6987 struct drm_encoder_helper_funcs *encoder_funcs;
a6778b3c 6988 struct drm_encoder *encoder;
25c5b266
DV		 6989 struct intel_crtc *intel_crtc;
6990 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 6991 bool ret = true;
6992
e2e1ed41 6993 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 6994 &prepare_pipes, &disable_pipes);
6995
6996 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
6997 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 6998
976f8a20
DV		 6999 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7000 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7001
a6778b3c
DV		 7002 saved_hwmode = crtc->hwmode;
7003 saved_mode = crtc->mode;
a6778b3c 7004
25c5b266
DV		 7005 /* Hack: Because we don't (yet) support global modeset on multiple
7006 * crtcs, we don't keep track of the new mode for more than one crtc.
7007 * Hence simply check whether any bit is set in modeset_pipes in all the
7008 * pieces of code that are not yet converted to deal with mutliple crtcs
7009 * changing their mode at the same time. */
7010 adjusted_mode = NULL;
7011 if (modeset_pipes) {
7012 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7013 if (IS_ERR(adjusted_mode)) {
7014 return false;
7015 }
25c5b266 7016 }
a6778b3c 7017
ea9d758d
DV		 7018 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7019 if (intel_crtc->base.enabled)
7020 dev_priv->display.crtc_disable(&intel_crtc->base);
7021 }
a6778b3c 7022
6c4c86f5
DV		 7023 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7024 * to set it here already despite that we pass it down the callchain.
7025 */
7026 if (modeset_pipes)
25c5b266 7027 crtc->mode = *mode;
7758a113 7028
ea9d758d
DV		 7029 /* Only after disabling all output pipelines that will be changed can we
7030 * update the the output configuration. */
7031 intel_modeset_update_state(dev, prepare_pipes);
7032
a6778b3c
DV		 7033 /* Set up the DPLL and any encoders state that needs to adjust or depend
7034 * on the DPLL.
7035 */
25c5b266
DV		 7036 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7037 ret = !intel_crtc_mode_set(&intel_crtc->base,
7038 mode, adjusted_mode,
7039 x, y, fb);
7040 if (!ret)
7041 goto done;
a6778b3c 7042
25c5b266 7043 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
a6778b3c 7044
25c5b266
DV		 7045 if (encoder->crtc != &intel_crtc->base)
7046 continue;
a6778b3c 7047
25c5b266
DV		 7048 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7049 encoder->base.id, drm_get_encoder_name(encoder),
7050 mode->base.id, mode->name);
7051 encoder_funcs = encoder->helper_private;
7052 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7053 }
a6778b3c
DV		 7054 }
7055
7056 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7057 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7058 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7059
25c5b266
DV		 7060 if (modeset_pipes) {
7061 /* Store real post-adjustment hardware mode. */
7062 crtc->hwmode = *adjusted_mode;
a6778b3c 7063
25c5b266
DV		 7064 /* Calculate and store various constants which
7065 * are later needed by vblank and swap-completion
7066 * timestamping. They are derived from true hwmode.
7067 */
7068 drm_calc_timestamping_constants(crtc);
7069 }
a6778b3c
DV		 7070
7071 /* FIXME: add subpixel order */
7072done:
7073 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7074 if (!ret && crtc->enabled) {
a6778b3c
DV		 7075 crtc->hwmode = saved_hwmode;
7076 crtc->mode = saved_mode;
8af6cf88
DV		 7077 } else {
7078 intel_modeset_check_state(dev);
a6778b3c
DV		 7079 }
7080
7081 return ret;
7082}
7083
25c5b266
DV		 7084#undef for_each_intel_crtc_masked
7085
d9e55608
DV		 7086static void intel_set_config_free(struct intel_set_config *config)
7087{
7088 if (!config)
7089 return;
7090
1aa4b628
DV		 7091 kfree(config->save_connector_encoders);
7092 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7093 kfree(config);
7094}
7095
85f9eb71
DV		 7096static int intel_set_config_save_state(struct drm_device *dev,
7097 struct intel_set_config *config)
7098{
85f9eb71
DV		 7099 struct drm_encoder *encoder;
7100 struct drm_connector *connector;
7101 int count;
7102
1aa4b628
DV		 7103 config->save_encoder_crtcs =
7104 kcalloc(dev->mode_config.num_encoder,
7105 sizeof(struct drm_crtc *), GFP_KERNEL);
7106 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7107 return -ENOMEM;
7108
1aa4b628
DV		 7109 config->save_connector_encoders =
7110 kcalloc(dev->mode_config.num_connector,
7111 sizeof(struct drm_encoder *), GFP_KERNEL);
7112 if (!config->save_connector_encoders)
85f9eb71
DV		 7113 return -ENOMEM;
7114
7115 /* Copy data. Note that driver private data is not affected.
7116 * Should anything bad happen only the expected state is
7117 * restored, not the drivers personal bookkeeping.
7118 */
85f9eb71
DV		 7119 count = 0;
7120 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7121 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7122 }
7123
7124 count = 0;
7125 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7126 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7127 }
7128
7129 return 0;
7130}
7131
7132static void intel_set_config_restore_state(struct drm_device *dev,
7133 struct intel_set_config *config)
7134{
9a935856
DV		 7135 struct intel_encoder *encoder;
7136 struct intel_connector *connector;
85f9eb71
DV		 7137 int count;
7138
85f9eb71 7139 count = 0;
9a935856
DV		 7140 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7141 encoder->new_crtc =
7142 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7143 }
7144
7145 count = 0;
9a935856
DV		 7146 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7147 connector->new_encoder =
7148 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7149 }
7150}
7151
5e2b584e
DV		 7152static void
7153intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7154 struct intel_set_config *config)
7155{
7156
7157 /* We should be able to check here if the fb has the same properties
7158 * and then just flip_or_move it */
7159 if (set->crtc->fb != set->fb) {
7160 /* If we have no fb then treat it as a full mode set */
7161 if (set->crtc->fb == NULL) {
7162 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7163 config->mode_changed = true;
7164 } else if (set->fb == NULL) {
7165 config->mode_changed = true;
7166 } else if (set->fb->depth != set->crtc->fb->depth) {
7167 config->mode_changed = true;
7168 } else if (set->fb->bits_per_pixel !=
7169 set->crtc->fb->bits_per_pixel) {
7170 config->mode_changed = true;
7171 } else
7172 config->fb_changed = true;
7173 }
7174
835c5873 7175 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7176 config->fb_changed = true;
7177
7178 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7179 DRM_DEBUG_KMS("modes are different, full mode set\n");
7180 drm_mode_debug_printmodeline(&set->crtc->mode);
7181 drm_mode_debug_printmodeline(set->mode);
7182 config->mode_changed = true;
7183 }
7184}
7185
2e431051 7186static int
9a935856
DV		 7187intel_modeset_stage_output_state(struct drm_device *dev,
7188 struct drm_mode_set *set,
7189 struct intel_set_config *config)
50f56119 7190{
85f9eb71 7191 struct drm_crtc *new_crtc;
9a935856
DV		 7192 struct intel_connector *connector;
7193 struct intel_encoder *encoder;
2e431051 7194 int count, ro;
50f56119 7195
9a935856
DV		 7196 /* The upper layers ensure that we either disabl a crtc or have a list
7197 * of connectors. For paranoia, double-check this. */
7198 WARN_ON(!set->fb && (set->num_connectors != 0));
7199 WARN_ON(set->fb && (set->num_connectors == 0));
7200
50f56119 7201 count = 0;
9a935856
DV		 7202 list_for_each_entry(connector, &dev->mode_config.connector_list,
7203 base.head) {
7204 /* Otherwise traverse passed in connector list and get encoders
7205 * for them. */
50f56119 7206 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7207 if (set->connectors[ro] == &connector->base) {
7208 connector->new_encoder = connector->encoder;
50f56119
DV		 7209 break;
7210 }
7211 }
7212
9a935856
DV		 7213 /* If we disable the crtc, disable all its connectors. Also, if
7214 * the connector is on the changing crtc but not on the new
7215 * connector list, disable it. */
7216 if ((!set->fb || ro == set->num_connectors) &&
7217 connector->base.encoder &&
7218 connector->base.encoder->crtc == set->crtc) {
7219 connector->new_encoder = NULL;
7220
7221 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7222 connector->base.base.id,
7223 drm_get_connector_name(&connector->base));
7224 }
7225
7226
7227 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7228 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7229 config->mode_changed = true;
50f56119 7230 }
9a935856
DV		 7231
7232 /* Disable all disconnected encoders. */
7233 if (connector->base.status == connector_status_disconnected)
7234 connector->new_encoder = NULL;
50f56119 7235 }
9a935856 7236 /* connector->new_encoder is now updated for all connectors. */
50f56119 7237
9a935856 7238 /* Update crtc of enabled connectors. */
50f56119 7239 count = 0;
9a935856
DV		 7240 list_for_each_entry(connector, &dev->mode_config.connector_list,
7241 base.head) {
7242 if (!connector->new_encoder)
50f56119
DV		 7243 continue;
7244
9a935856 7245 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7246
7247 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7248 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7249 new_crtc = set->crtc;
7250 }
7251
7252 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7253 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7254 new_crtc)) {
5e2b584e 7255 return -EINVAL;
50f56119 7256 }
9a935856
DV		 7257 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7258
7259 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7260 connector->base.base.id,
7261 drm_get_connector_name(&connector->base),
7262 new_crtc->base.id);
7263 }
7264
7265 /* Check for any encoders that needs to be disabled. */
7266 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7267 base.head) {
7268 list_for_each_entry(connector,
7269 &dev->mode_config.connector_list,
7270 base.head) {
7271 if (connector->new_encoder == encoder) {
7272 WARN_ON(!connector->new_encoder->new_crtc);
7273
7274 goto next_encoder;
7275 }
7276 }
7277 encoder->new_crtc = NULL;
7278next_encoder:
7279 /* Only now check for crtc changes so we don't miss encoders
7280 * that will be disabled. */
7281 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7282 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7283 config->mode_changed = true;
50f56119
DV		 7284 }
7285 }
9a935856 7286 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7287
2e431051
DV		 7288 return 0;
7289}
7290
7291static int intel_crtc_set_config(struct drm_mode_set *set)
7292{
7293 struct drm_device *dev;
2e431051
DV		 7294 struct drm_mode_set save_set;
7295 struct intel_set_config *config;
7296 int ret;
7297 int i;
7298
8d3e375e
DV		 7299 BUG_ON(!set);
7300 BUG_ON(!set->crtc);
7301 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 7302
7303 if (!set->mode)
7304 set->fb = NULL;
7305
431e50f7
DV		 7306 /* The fb helper likes to play gross jokes with ->mode_set_config.
7307 * Unfortunately the crtc helper doesn't do much at all for this case,
7308 * so we have to cope with this madness until the fb helper is fixed up. */
7309 if (set->fb && set->num_connectors == 0)
7310 return 0;
7311
2e431051
DV		 7312 if (set->fb) {
7313 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7314 set->crtc->base.id, set->fb->base.id,
7315 (int)set->num_connectors, set->x, set->y);
7316 } else {
7317 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 7318 }
7319
7320 dev = set->crtc->dev;
7321
7322 ret = -ENOMEM;
7323 config = kzalloc(sizeof(*config), GFP_KERNEL);
7324 if (!config)
7325 goto out_config;
7326
7327 ret = intel_set_config_save_state(dev, config);
7328 if (ret)
7329 goto out_config;
7330
7331 save_set.crtc = set->crtc;
7332 save_set.mode = &set->crtc->mode;
7333 save_set.x = set->crtc->x;
7334 save_set.y = set->crtc->y;
7335 save_set.fb = set->crtc->fb;
7336
7337 /* Compute whether we need a full modeset, only an fb base update or no
7338 * change at all. In the future we might also check whether only the
7339 * mode changed, e.g. for LVDS where we only change the panel fitter in
7340 * such cases. */
7341 intel_set_config_compute_mode_changes(set, config);
7342
9a935856 7343 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 7344 if (ret)
7345 goto fail;
7346
5e2b584e 7347 if (config->mode_changed) {
87f1faa6 7348 if (set->mode) {
50f56119
DV		 7349 DRM_DEBUG_KMS("attempting to set mode from"
7350 " userspace\n");
7351 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 7352 }
7353
7354 if (!intel_set_mode(set->crtc, set->mode,
7355 set->x, set->y, set->fb)) {
7356 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7357 set->crtc->base.id);
7358 ret = -EINVAL;
7359 goto fail;
7360 }
7361
7362 if (set->crtc->enabled) {
50f56119
DV		 7363 DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
7364 for (i = 0; i < set->num_connectors; i++) {
7365 DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id,
7366 drm_get_connector_name(set->connectors[i]));
7367 set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON);
7368 }
7369 }
5e2b584e 7370 } else if (config->fb_changed) {
4f660f49 7371 ret = intel_pipe_set_base(set->crtc,
94352cf9 7372 set->x, set->y, set->fb);
50f56119
DV		 7373 }
7374
d9e55608
DV		 7375 intel_set_config_free(config);
7376
50f56119
DV		 7377 return 0;
7378
7379fail:
85f9eb71 7380 intel_set_config_restore_state(dev, config);
50f56119
DV		 7381
7382 /* Try to restore the config */
5e2b584e 7383 if (config->mode_changed &&
a6778b3c
DV		 7384 !intel_set_mode(save_set.crtc, save_set.mode,
7385 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 7386 DRM_ERROR("failed to restore config after modeset failure\n");
7387
d9e55608
DV		 7388out_config:
7389 intel_set_config_free(config);
50f56119
DV		 7390 return ret;
7391}
7392
f6e5b160 7393static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 7394 .cursor_set = intel_crtc_cursor_set,
7395 .cursor_move = intel_crtc_cursor_move,
7396 .gamma_set = intel_crtc_gamma_set,
50f56119 7397 .set_config = intel_crtc_set_config,
f6e5b160
CW		 7398 .destroy = intel_crtc_destroy,
7399 .page_flip = intel_crtc_page_flip,
7400};
7401
ee7b9f93
JB		 7402static void intel_pch_pll_init(struct drm_device *dev)
7403{
7404 drm_i915_private_t *dev_priv = dev->dev_private;
7405 int i;
7406
7407 if (dev_priv->num_pch_pll == 0) {
7408 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7409 return;
7410 }
7411
7412 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7413 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7414 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7415 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7416 }
7417}
7418
b358d0a6 7419static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7420{
22fd0fab 7421 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7422 struct intel_crtc *intel_crtc;
7423 int i;
7424
7425 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7426 if (intel_crtc == NULL)
7427 return;
7428
7429 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7430
7431 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7432 for (i = 0; i < 256; i++) {
7433 intel_crtc->lut_r[i] = i;
7434 intel_crtc->lut_g[i] = i;
7435 intel_crtc->lut_b[i] = i;
7436 }
7437
80824003
JB		 7438 /* Swap pipes & planes for FBC on pre-965 */
7439 intel_crtc->pipe = pipe;
7440 intel_crtc->plane = pipe;
e2e767ab 7441 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7442 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7443 intel_crtc->plane = !pipe;
80824003
JB		 7444 }
7445
22fd0fab
JB		 7446 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7447 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7448 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7449 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7450
5a354204 7451 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 7452
79e53945 7453 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 7454}
7455
08d7b3d1 7456int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7457 struct drm_file *file)
08d7b3d1 7458{
08d7b3d1 7459 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7460 struct drm_mode_object *drmmode_obj;
7461 struct intel_crtc *crtc;
08d7b3d1 7462
1cff8f6b
DV		 7463 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7464 return -ENODEV;
08d7b3d1 7465
c05422d5
DV		 7466 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7467 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7468
c05422d5 7469 if (!drmmode_obj) {
08d7b3d1
CW		 7470 DRM_ERROR("no such CRTC id\n");
7471 return -EINVAL;
7472 }
7473
c05422d5
DV		 7474 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7475 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7476
c05422d5 7477 return 0;
08d7b3d1
CW		 7478}
7479
66a9278e 7480static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 7481{
66a9278e
DV		 7482 struct drm_device *dev = encoder->base.dev;
7483 struct intel_encoder *source_encoder;
79e53945 7484 int index_mask = 0;
79e53945
JB		 7485 int entry = 0;
7486
66a9278e
DV		 7487 list_for_each_entry(source_encoder,
7488 &dev->mode_config.encoder_list, base.head) {
7489
7490 if (encoder == source_encoder)
79e53945 7491 index_mask |= (1 << entry);
66a9278e
DV		 7492
7493 /* Intel hw has only one MUX where enocoders could be cloned. */
7494 if (encoder->cloneable && source_encoder->cloneable)
7495 index_mask |= (1 << entry);
7496
79e53945
JB		 7497 entry++;
7498 }
4ef69c7a 7499
79e53945
JB		 7500 return index_mask;
7501}
7502
4d302442
CW		 7503static bool has_edp_a(struct drm_device *dev)
7504{
7505 struct drm_i915_private *dev_priv = dev->dev_private;
7506
7507 if (!IS_MOBILE(dev))
7508 return false;
7509
7510 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7511 return false;
7512
7513 if (IS_GEN5(dev) &&
7514 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7515 return false;
7516
7517 return true;
7518}
7519
79e53945
JB		 7520static void intel_setup_outputs(struct drm_device *dev)
7521{
725e30ad 7522 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7523 struct intel_encoder *encoder;
cb0953d7 7524 bool dpd_is_edp = false;
f3cfcba6 7525 bool has_lvds;
79e53945 7526
f3cfcba6 7527 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 7528 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7529 /* disable the panel fitter on everything but LVDS */
7530 I915_WRITE(PFIT_CONTROL, 0);
7531 }
79e53945 7532
bad720ff 7533 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7534 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7535
4d302442 7536 if (has_edp_a(dev))
ab9d7c30 7537 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 7538
cb0953d7 7539 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 7540 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 7541 }
7542
7543 intel_crt_init(dev);
7544
0e72a5b5
ED		 7545 if (IS_HASWELL(dev)) {
7546 int found;
7547
7548 /* Haswell uses DDI functions to detect digital outputs */
7549 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7550 /* DDI A only supports eDP */
7551 if (found)
7552 intel_ddi_init(dev, PORT_A);
7553
7554 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7555 * register */
7556 found = I915_READ(SFUSE_STRAP);
7557
7558 if (found & SFUSE_STRAP_DDIB_DETECTED)
7559 intel_ddi_init(dev, PORT_B);
7560 if (found & SFUSE_STRAP_DDIC_DETECTED)
7561 intel_ddi_init(dev, PORT_C);
7562 if (found & SFUSE_STRAP_DDID_DETECTED)
7563 intel_ddi_init(dev, PORT_D);
7564 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 7565 int found;
7566
30ad48b7 7567 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 7568 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 7569 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 7570 if (!found)
08d644ad 7571 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 7572 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 7573 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 7574 }
7575
7576 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 7577 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 7578
b708a1d5 7579 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 7580 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 7581
5eb08b69 7582 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 7583 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 7584
cb0953d7 7585 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 7586 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 7587 } else if (IS_VALLEYVIEW(dev)) {
7588 int found;
7589
7590 if (I915_READ(SDVOB) & PORT_DETECTED) {
7591 /* SDVOB multiplex with HDMIB */
7592 found = intel_sdvo_init(dev, SDVOB, true);
7593 if (!found)
08d644ad 7594 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 7595 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 7596 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 7597 }
7598
7599 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 7600 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 7601
4a87d65d
JB		 7602 /* Shares lanes with HDMI on SDVOC */
7603 if (I915_READ(DP_C) & DP_DETECTED)
ab9d7c30 7604 intel_dp_init(dev, DP_C, PORT_C);
103a196f 7605 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7606 bool found = false;
7d57382e 7607
725e30ad 7608 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7609 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 7610 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 7611 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7612 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 7613 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 7614 }
27185ae1 7615
b01f2c3a
JB		 7616 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7617 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 7618 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 7619 }
725e30ad 7620 }
13520b05
KH		 7621
7622 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7623
b01f2c3a
JB		 7624 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7625 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 7626 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 7627 }
27185ae1
ML		 7628
7629 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7630
b01f2c3a
JB		 7631 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7632 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 7633 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 7634 }
7635 if (SUPPORTS_INTEGRATED_DP(dev)) {
7636 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 7637 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 7638 }
725e30ad 7639 }
27185ae1 7640
b01f2c3a
JB		 7641 if (SUPPORTS_INTEGRATED_DP(dev) &&
7642 (I915_READ(DP_D) & DP_DETECTED)) {
7643 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 7644 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 7645 }
bad720ff 7646 } else if (IS_GEN2(dev))
79e53945
JB		 7647 intel_dvo_init(dev);
7648
103a196f 7649 if (SUPPORTS_TV(dev))
79e53945
JB		 7650 intel_tv_init(dev);
7651
4ef69c7a
CW		 7652 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7653 encoder->base.possible_crtcs = encoder->crtc_mask;
7654 encoder->base.possible_clones =
66a9278e 7655 intel_encoder_clones(encoder);
79e53945 7656 }
47356eb6 7657
40579abe 7658 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 7659 ironlake_init_pch_refclk(dev);
79e53945
JB		 7660}
7661
7662static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7663{
7664 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7665
7666 drm_framebuffer_cleanup(fb);
05394f39 7667 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7668
7669 kfree(intel_fb);
7670}
7671
7672static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7673 struct drm_file *file,
79e53945
JB		 7674 unsigned int *handle)
7675{
7676 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7677 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7678
05394f39 7679 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7680}
7681
7682static const struct drm_framebuffer_funcs intel_fb_funcs = {
7683 .destroy = intel_user_framebuffer_destroy,
7684 .create_handle = intel_user_framebuffer_create_handle,
7685};
7686
38651674
DA		 7687int intel_framebuffer_init(struct drm_device *dev,
7688 struct intel_framebuffer *intel_fb,
308e5bcb 7689 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 7690 struct drm_i915_gem_object *obj)
79e53945 7691{
79e53945
JB		 7692 int ret;
7693
05394f39 7694 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7695 return -EINVAL;
7696
308e5bcb 7697 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 7698 return -EINVAL;
7699
308e5bcb 7700 switch (mode_cmd->pixel_format) {
04b3924d
VS		 7701 case DRM_FORMAT_RGB332:
7702 case DRM_FORMAT_RGB565:
7703 case DRM_FORMAT_XRGB8888:
b250da79 7704 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 7705 case DRM_FORMAT_ARGB8888:
7706 case DRM_FORMAT_XRGB2101010:
7707 case DRM_FORMAT_ARGB2101010:
308e5bcb 7708 /* RGB formats are common across chipsets */
b5626747 7709 break;
04b3924d
VS		 7710 case DRM_FORMAT_YUYV:
7711 case DRM_FORMAT_UYVY:
7712 case DRM_FORMAT_YVYU:
7713 case DRM_FORMAT_VYUY:
57cd6508
CW		 7714 break;
7715 default:
aca25848
ED		 7716 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7717 mode_cmd->pixel_format);
57cd6508
CW		 7718 return -EINVAL;
7719 }
7720
79e53945
JB		 7721 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7722 if (ret) {
7723 DRM_ERROR("framebuffer init failed %d\n", ret);
7724 return ret;
7725 }
7726
7727 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7728 intel_fb->obj = obj;
79e53945
JB		 7729 return 0;
7730}
7731
79e53945
JB		 7732static struct drm_framebuffer *
7733intel_user_framebuffer_create(struct drm_device *dev,
7734 struct drm_file *filp,
308e5bcb 7735 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 7736{
05394f39 7737 struct drm_i915_gem_object *obj;
79e53945 7738
308e5bcb
JB		 7739 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7740 mode_cmd->handles[0]));
c8725226 7741 if (&obj->base == NULL)
cce13ff7 7742 return ERR_PTR(-ENOENT);
79e53945 7743
d2dff872 7744 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7745}
7746
79e53945 7747static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7748 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7749 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7750};
7751
e70236a8
JB		 7752/* Set up chip specific display functions */
7753static void intel_init_display(struct drm_device *dev)
7754{
7755 struct drm_i915_private *dev_priv = dev->dev_private;
7756
7757 /* We always want a DPMS function */
f564048e 7758 if (HAS_PCH_SPLIT(dev)) {
f564048e 7759 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 7760 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7761 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 7762 dev_priv->display.off = ironlake_crtc_off;
17638cd6 7763 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 7764 } else {
f564048e 7765 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 7766 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7767 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 7768 dev_priv->display.off = i9xx_crtc_off;
17638cd6 7769 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 7770 }
e70236a8 7771
e70236a8 7772 /* Returns the core display clock speed */
25eb05fc
JB		 7773 if (IS_VALLEYVIEW(dev))
7774 dev_priv->display.get_display_clock_speed =
7775 valleyview_get_display_clock_speed;
7776 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 7777 dev_priv->display.get_display_clock_speed =
7778 i945_get_display_clock_speed;
7779 else if (IS_I915G(dev))
7780 dev_priv->display.get_display_clock_speed =
7781 i915_get_display_clock_speed;
f2b115e6 7782 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7783 dev_priv->display.get_display_clock_speed =
7784 i9xx_misc_get_display_clock_speed;
7785 else if (IS_I915GM(dev))
7786 dev_priv->display.get_display_clock_speed =
7787 i915gm_get_display_clock_speed;
7788 else if (IS_I865G(dev))
7789 dev_priv->display.get_display_clock_speed =
7790 i865_get_display_clock_speed;
f0f8a9ce 7791 else if (IS_I85X(dev))
e70236a8
JB		 7792 dev_priv->display.get_display_clock_speed =
7793 i855_get_display_clock_speed;
7794 else /* 852, 830 */
7795 dev_priv->display.get_display_clock_speed =
7796 i830_get_display_clock_speed;
7797
7f8a8569 7798 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 7799 if (IS_GEN5(dev)) {
674cf967 7800 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 7801 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 7802 } else if (IS_GEN6(dev)) {
674cf967 7803 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 7804 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 7805 } else if (IS_IVYBRIDGE(dev)) {
7806 /* FIXME: detect B0+ stepping and use auto training */
7807 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 7808 dev_priv->display.write_eld = ironlake_write_eld;
c82e4d26
ED		 7809 } else if (IS_HASWELL(dev)) {
7810 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 7811 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 7812 } else
7813 dev_priv->display.update_wm = NULL;
6067aaea 7814 } else if (IS_G4X(dev)) {
e0dac65e 7815 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 7816 }
8c9f3aaf
JB		 7817
7818 /* Default just returns -ENODEV to indicate unsupported */
7819 dev_priv->display.queue_flip = intel_default_queue_flip;
7820
7821 switch (INTEL_INFO(dev)->gen) {
7822 case 2:
7823 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7824 break;
7825
7826 case 3:
7827 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7828 break;
7829
7830 case 4:
7831 case 5:
7832 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7833 break;
7834
7835 case 6:
7836 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7837 break;
7c9017e5
JB		 7838 case 7:
7839 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7840 break;
8c9f3aaf 7841 }
e70236a8
JB		 7842}
7843
b690e96c
JB		 7844/*
7845 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7846 * resume, or other times. This quirk makes sure that's the case for
7847 * affected systems.
7848 */
0206e353 7849static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 7850{
7851 struct drm_i915_private *dev_priv = dev->dev_private;
7852
7853 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 7854 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 7855}
7856
435793df
KP		 7857/*
7858 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7859 */
7860static void quirk_ssc_force_disable(struct drm_device *dev)
7861{
7862 struct drm_i915_private *dev_priv = dev->dev_private;
7863 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 7864 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 7865}
7866
4dca20ef 7867/*
5a15ab5b
CE		 7868 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7869 * brightness value
4dca20ef
CE		 7870 */
7871static void quirk_invert_brightness(struct drm_device *dev)
7872{
7873 struct drm_i915_private *dev_priv = dev->dev_private;
7874 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 7875 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 7876}
7877
b690e96c
JB		 7878struct intel_quirk {
7879 int device;
7880 int subsystem_vendor;
7881 int subsystem_device;
7882 void (*hook)(struct drm_device *dev);
7883};
7884
c43b5634 7885static struct intel_quirk intel_quirks[] = {
b690e96c 7886 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 7887 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 7888
b690e96c
JB		 7889 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7890 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7891
b690e96c
JB		 7892 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7893 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7894
7895 /* 855 & before need to leave pipe A & dpll A up */
7896 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7897 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 7898 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 7899
7900 /* Lenovo U160 cannot use SSC on LVDS */
7901 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 7902
7903 /* Sony Vaio Y cannot use SSC on LVDS */
7904 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 7905
7906 /* Acer Aspire 5734Z must invert backlight brightness */
7907 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 7908};
7909
7910static void intel_init_quirks(struct drm_device *dev)
7911{
7912 struct pci_dev *d = dev->pdev;
7913 int i;
7914
7915 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7916 struct intel_quirk *q = &intel_quirks[i];
7917
7918 if (d->device == q->device &&
7919 (d->subsystem_vendor == q->subsystem_vendor ||
7920 q->subsystem_vendor == PCI_ANY_ID) &&
7921 (d->subsystem_device == q->subsystem_device ||
7922 q->subsystem_device == PCI_ANY_ID))
7923 q->hook(dev);
7924 }
7925}
7926
9cce37f4
JB		 7927/* Disable the VGA plane that we never use */
7928static void i915_disable_vga(struct drm_device *dev)
7929{
7930 struct drm_i915_private *dev_priv = dev->dev_private;
7931 u8 sr1;
7932 u32 vga_reg;
7933
7934 if (HAS_PCH_SPLIT(dev))
7935 vga_reg = CPU_VGACNTRL;
7936 else
7937 vga_reg = VGACNTRL;
7938
7939 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 7940 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 7941 sr1 = inb(VGA_SR_DATA);
7942 outb(sr1 | 1<<5, VGA_SR_DATA);
7943 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7944 udelay(300);
7945
7946 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7947 POSTING_READ(vga_reg);
7948}
7949
f817586c
DV		 7950void intel_modeset_init_hw(struct drm_device *dev)
7951{
0232e927
ED		 7952 /* We attempt to init the necessary power wells early in the initialization
7953 * time, so the subsystems that expect power to be enabled can work.
7954 */
7955 intel_init_power_wells(dev);
7956
a8f78b58
ED		 7957 intel_prepare_ddi(dev);
7958
f817586c
DV		 7959 intel_init_clock_gating(dev);
7960
79f5b2c7 7961 mutex_lock(&dev->struct_mutex);
8090c6b9 7962 intel_enable_gt_powersave(dev);
79f5b2c7 7963 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 7964}
7965
79e53945
JB		 7966void intel_modeset_init(struct drm_device *dev)
7967{
652c393a 7968 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 7969 int i, ret;
79e53945
JB		 7970
7971 drm_mode_config_init(dev);
7972
7973 dev->mode_config.min_width = 0;
7974 dev->mode_config.min_height = 0;
7975
019d96cb
DA		 7976 dev->mode_config.preferred_depth = 24;
7977 dev->mode_config.prefer_shadow = 1;
7978
e6ecefaa 7979 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 7980
b690e96c
JB		 7981 intel_init_quirks(dev);
7982
1fa61106
ED		 7983 intel_init_pm(dev);
7984
e70236a8
JB		 7985 intel_init_display(dev);
7986
a6c45cf0
CW		 7987 if (IS_GEN2(dev)) {
7988 dev->mode_config.max_width = 2048;
7989 dev->mode_config.max_height = 2048;
7990 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 7991 dev->mode_config.max_width = 4096;
7992 dev->mode_config.max_height = 4096;
79e53945 7993 } else {
a6c45cf0
CW		 7994 dev->mode_config.max_width = 8192;
7995 dev->mode_config.max_height = 8192;
79e53945 7996 }
dd2757f8 7997 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 7998
28c97730 7999 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8000 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8001
a3524f1b 8002 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8003 intel_crtc_init(dev, i);
00c2064b
JB		 8004 ret = intel_plane_init(dev, i);
8005 if (ret)
8006 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8007 }
8008
ee7b9f93
JB		 8009 intel_pch_pll_init(dev);
8010
9cce37f4
JB		 8011 /* Just disable it once at startup */
8012 i915_disable_vga(dev);
79e53945 8013 intel_setup_outputs(dev);
2c7111db
CW		 8014}
8015
24929352
DV		 8016static void
8017intel_connector_break_all_links(struct intel_connector *connector)
8018{
8019 connector->base.dpms = DRM_MODE_DPMS_OFF;
8020 connector->base.encoder = NULL;
8021 connector->encoder->connectors_active = false;
8022 connector->encoder->base.crtc = NULL;
8023}
8024
7fad798e
DV		 8025static void intel_enable_pipe_a(struct drm_device *dev)
8026{
8027 struct intel_connector *connector;
8028 struct drm_connector *crt = NULL;
8029 struct intel_load_detect_pipe load_detect_temp;
8030
8031 /* We can't just switch on the pipe A, we need to set things up with a
8032 * proper mode and output configuration. As a gross hack, enable pipe A
8033 * by enabling the load detect pipe once. */
8034 list_for_each_entry(connector,
8035 &dev->mode_config.connector_list,
8036 base.head) {
8037 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8038 crt = &connector->base;
8039 break;
8040 }
8041 }
8042
8043 if (!crt)
8044 return;
8045
8046 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8047 intel_release_load_detect_pipe(crt, &load_detect_temp);
8048
8049
8050}
8051
24929352
DV		 8052static void intel_sanitize_crtc(struct intel_crtc *crtc)
8053{
8054 struct drm_device *dev = crtc->base.dev;
8055 struct drm_i915_private *dev_priv = dev->dev_private;
8056 u32 reg, val;
8057
24929352
DV		 8058 /* Clear any frame start delays used for debugging left by the BIOS */
8059 reg = PIPECONF(crtc->pipe);
8060 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8061
8062 /* We need to sanitize the plane -> pipe mapping first because this will
8063 * disable the crtc (and hence change the state) if it is wrong. */
8064 if (!HAS_PCH_SPLIT(dev)) {
8065 struct intel_connector *connector;
8066 bool plane;
8067
8068 reg = DSPCNTR(crtc->plane);
8069 val = I915_READ(reg);
8070
8071 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
8072 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8073 goto ok;
8074
8075 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8076 crtc->base.base.id);
8077
8078 /* Pipe has the wrong plane attached and the plane is active.
8079 * Temporarily change the plane mapping and disable everything
8080 * ... */
8081 plane = crtc->plane;
8082 crtc->plane = !plane;
8083 dev_priv->display.crtc_disable(&crtc->base);
8084 crtc->plane = plane;
8085
8086 /* ... and break all links. */
8087 list_for_each_entry(connector, &dev->mode_config.connector_list,
8088 base.head) {
8089 if (connector->encoder->base.crtc != &crtc->base)
8090 continue;
8091
8092 intel_connector_break_all_links(connector);
8093 }
8094
8095 WARN_ON(crtc->active);
8096 crtc->base.enabled = false;
8097 }
8098ok:
8099
7fad798e
DV		 8100 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8101 crtc->pipe == PIPE_A && !crtc->active) {
8102 /* BIOS forgot to enable pipe A, this mostly happens after
8103 * resume. Force-enable the pipe to fix this, the update_dpms
8104 * call below we restore the pipe to the right state, but leave
8105 * the required bits on. */
8106 intel_enable_pipe_a(dev);
8107 }
8108
24929352
DV		 8109 /* Adjust the state of the output pipe according to whether we
8110 * have active connectors/encoders. */
8111 intel_crtc_update_dpms(&crtc->base);
8112
8113 if (crtc->active != crtc->base.enabled) {
8114 struct intel_encoder *encoder;
8115
8116 /* This can happen either due to bugs in the get_hw_state
8117 * functions or because the pipe is force-enabled due to the
8118 * pipe A quirk. */
8119 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8120 crtc->base.base.id,
8121 crtc->base.enabled ? "enabled" : "disabled",
8122 crtc->active ? "enabled" : "disabled");
8123
8124 crtc->base.enabled = crtc->active;
8125
8126 /* Because we only establish the connector -> encoder ->
8127 * crtc links if something is active, this means the
8128 * crtc is now deactivated. Break the links. connector
8129 * -> encoder links are only establish when things are
8130 * actually up, hence no need to break them. */
8131 WARN_ON(crtc->active);
8132
8133 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8134 WARN_ON(encoder->connectors_active);
8135 encoder->base.crtc = NULL;
8136 }
8137 }
8138}
8139
8140static void intel_sanitize_encoder(struct intel_encoder *encoder)
8141{
8142 struct intel_connector *connector;
8143 struct drm_device *dev = encoder->base.dev;
8144
8145 /* We need to check both for a crtc link (meaning that the
8146 * encoder is active and trying to read from a pipe) and the
8147 * pipe itself being active. */
8148 bool has_active_crtc = encoder->base.crtc &&
8149 to_intel_crtc(encoder->base.crtc)->active;
8150
8151 if (encoder->connectors_active && !has_active_crtc) {
8152 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8153 encoder->base.base.id,
8154 drm_get_encoder_name(&encoder->base));
8155
8156 /* Connector is active, but has no active pipe. This is
8157 * fallout from our resume register restoring. Disable
8158 * the encoder manually again. */
8159 if (encoder->base.crtc) {
8160 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8161 encoder->base.base.id,
8162 drm_get_encoder_name(&encoder->base));
8163 encoder->disable(encoder);
8164 }
8165
8166 /* Inconsistent output/port/pipe state happens presumably due to
8167 * a bug in one of the get_hw_state functions. Or someplace else
8168 * in our code, like the register restore mess on resume. Clamp
8169 * things to off as a safer default. */
8170 list_for_each_entry(connector,
8171 &dev->mode_config.connector_list,
8172 base.head) {
8173 if (connector->encoder != encoder)
8174 continue;
8175
8176 intel_connector_break_all_links(connector);
8177 }
8178 }
8179 /* Enabled encoders without active connectors will be fixed in
8180 * the crtc fixup. */
8181}
8182
8183/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8184 * and i915 state tracking structures. */
8185void intel_modeset_setup_hw_state(struct drm_device *dev)
8186{
8187 struct drm_i915_private *dev_priv = dev->dev_private;
8188 enum pipe pipe;
8189 u32 tmp;
8190 struct intel_crtc *crtc;
8191 struct intel_encoder *encoder;
8192 struct intel_connector *connector;
8193
8194 for_each_pipe(pipe) {
8195 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8196
8197 tmp = I915_READ(PIPECONF(pipe));
8198 if (tmp & PIPECONF_ENABLE)
8199 crtc->active = true;
8200 else
8201 crtc->active = false;
8202
8203 crtc->base.enabled = crtc->active;
8204
8205 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8206 crtc->base.base.id,
8207 crtc->active ? "enabled" : "disabled");
8208 }
8209
8210 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8211 base.head) {
8212 pipe = 0;
8213
8214 if (encoder->get_hw_state(encoder, &pipe)) {
8215 encoder->base.crtc =
8216 dev_priv->pipe_to_crtc_mapping[pipe];
8217 } else {
8218 encoder->base.crtc = NULL;
8219 }
8220
8221 encoder->connectors_active = false;
8222 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8223 encoder->base.base.id,
8224 drm_get_encoder_name(&encoder->base),
8225 encoder->base.crtc ? "enabled" : "disabled",
8226 pipe);
8227 }
8228
8229 list_for_each_entry(connector, &dev->mode_config.connector_list,
8230 base.head) {
8231 if (connector->get_hw_state(connector)) {
8232 connector->base.dpms = DRM_MODE_DPMS_ON;
8233 connector->encoder->connectors_active = true;
8234 connector->base.encoder = &connector->encoder->base;
8235 } else {
8236 connector->base.dpms = DRM_MODE_DPMS_OFF;
8237 connector->base.encoder = NULL;
8238 }
8239 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8240 connector->base.base.id,
8241 drm_get_connector_name(&connector->base),
8242 connector->base.encoder ? "enabled" : "disabled");
8243 }
8244
8245 /* HW state is read out, now we need to sanitize this mess. */
8246 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8247 base.head) {
8248 intel_sanitize_encoder(encoder);
8249 }
8250
8251 for_each_pipe(pipe) {
8252 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8253 intel_sanitize_crtc(crtc);
8254 }
9a935856
DV		 8255
8256 intel_modeset_update_staged_output_state(dev);
8af6cf88
DV		 8257
8258 intel_modeset_check_state(dev);
24929352
DV		 8259}
8260
2c7111db
CW		 8261void intel_modeset_gem_init(struct drm_device *dev)
8262{
1833b134 8263 intel_modeset_init_hw(dev);
02e792fb
DV		 8264
8265 intel_setup_overlay(dev);
24929352
DV		 8266
8267 intel_modeset_setup_hw_state(dev);
79e53945
JB		 8268}
8269
8270void intel_modeset_cleanup(struct drm_device *dev)
8271{
652c393a
JB		 8272 struct drm_i915_private *dev_priv = dev->dev_private;
8273 struct drm_crtc *crtc;
8274 struct intel_crtc *intel_crtc;
8275
f87ea761 8276 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8277 mutex_lock(&dev->struct_mutex);
8278
723bfd70
JB		 8279 intel_unregister_dsm_handler();
8280
8281
652c393a
JB		 8282 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8283 /* Skip inactive CRTCs */
8284 if (!crtc->fb)
8285 continue;
8286
8287 intel_crtc = to_intel_crtc(crtc);
3dec0095 8288 intel_increase_pllclock(crtc);
652c393a
JB		 8289 }
8290
973d04f9 8291 intel_disable_fbc(dev);
e70236a8 8292
8090c6b9 8293 intel_disable_gt_powersave(dev);
0cdab21f 8294
930ebb46
DV		 8295 ironlake_teardown_rc6(dev);
8296
57f350b6
JB		 8297 if (IS_VALLEYVIEW(dev))
8298 vlv_init_dpio(dev);
8299
69341a5e
KH		 8300 mutex_unlock(&dev->struct_mutex);
8301
6c0d9350
DV		 8302 /* Disable the irq before mode object teardown, for the irq might
8303 * enqueue unpin/hotplug work. */
8304 drm_irq_uninstall(dev);
8305 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 8306 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 8307
1630fe75
CW		 8308 /* flush any delayed tasks or pending work */
8309 flush_scheduled_work();
8310
79e53945
JB		 8311 drm_mode_config_cleanup(dev);
8312}
8313
f1c79df3
ZW		 8314/*
8315 * Return which encoder is currently attached for connector.
8316 */
df0e9248 8317struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8318{
df0e9248
CW		 8319 return &intel_attached_encoder(connector)->base;
8320}
f1c79df3 8321
df0e9248
CW		 8322void intel_connector_attach_encoder(struct intel_connector *connector,
8323 struct intel_encoder *encoder)
8324{
8325 connector->encoder = encoder;
8326 drm_mode_connector_attach_encoder(&connector->base,
8327 &encoder->base);
79e53945 8328}
28d52043
DA		 8329
8330/*
8331 * set vga decode state - true == enable VGA decode
8332 */
8333int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8334{
8335 struct drm_i915_private *dev_priv = dev->dev_private;
8336 u16 gmch_ctrl;
8337
8338 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8339 if (state)
8340 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8341 else
8342 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8343 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8344 return 0;
8345}
c4a1d9e4
CW		 8346
8347#ifdef CONFIG_DEBUG_FS
8348#include <linux/seq_file.h>
8349
8350struct intel_display_error_state {
8351 struct intel_cursor_error_state {
8352 u32 control;
8353 u32 position;
8354 u32 base;
8355 u32 size;
52331309 8356 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 8357
8358 struct intel_pipe_error_state {
8359 u32 conf;
8360 u32 source;
8361
8362 u32 htotal;
8363 u32 hblank;
8364 u32 hsync;
8365 u32 vtotal;
8366 u32 vblank;
8367 u32 vsync;
52331309 8368 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 8369
8370 struct intel_plane_error_state {
8371 u32 control;
8372 u32 stride;
8373 u32 size;
8374 u32 pos;
8375 u32 addr;
8376 u32 surface;
8377 u32 tile_offset;
52331309 8378 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 8379};
8380
8381struct intel_display_error_state *
8382intel_display_capture_error_state(struct drm_device *dev)
8383{
0206e353 8384 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8385 struct intel_display_error_state *error;
8386 int i;
8387
8388 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8389 if (error == NULL)
8390 return NULL;
8391
52331309 8392 for_each_pipe(i) {
c4a1d9e4
CW		 8393 error->cursor[i].control = I915_READ(CURCNTR(i));
8394 error->cursor[i].position = I915_READ(CURPOS(i));
8395 error->cursor[i].base = I915_READ(CURBASE(i));
8396
8397 error->plane[i].control = I915_READ(DSPCNTR(i));
8398 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8399 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 8400 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 8401 error->plane[i].addr = I915_READ(DSPADDR(i));
8402 if (INTEL_INFO(dev)->gen >= 4) {
8403 error->plane[i].surface = I915_READ(DSPSURF(i));
8404 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8405 }
8406
8407 error->pipe[i].conf = I915_READ(PIPECONF(i));
8408 error->pipe[i].source = I915_READ(PIPESRC(i));
8409 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8410 error->pipe[i].hblank = I915_READ(HBLANK(i));
8411 error->pipe[i].hsync = I915_READ(HSYNC(i));
8412 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8413 error->pipe[i].vblank = I915_READ(VBLANK(i));
8414 error->pipe[i].vsync = I915_READ(VSYNC(i));
8415 }
8416
8417 return error;
8418}
8419
8420void
8421intel_display_print_error_state(struct seq_file *m,
8422 struct drm_device *dev,
8423 struct intel_display_error_state *error)
8424{
52331309 8425 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8426 int i;
8427
52331309
DL		 8428 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8429 for_each_pipe(i) {
c4a1d9e4
CW		 8430 seq_printf(m, "Pipe [%d]:\n", i);
8431 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8432 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8433 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8434 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8435 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8436 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8437 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8438 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8439
8440 seq_printf(m, "Plane [%d]:\n", i);
8441 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8442 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8443 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8444 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8445 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8446 if (INTEL_INFO(dev)->gen >= 4) {
8447 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8448 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8449 }
8450
8451 seq_printf(m, "Cursor [%d]:\n", i);
8452 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8453 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8454 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8455 }
8456}
8457#endif
Linux kernel - Deliverables
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