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drm/i915/crt: Do not rely upon the HPD presence pin
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
021357ac
CW		 101static inline u32 /* units of 100MHz */
102intel_fdi_link_freq(struct drm_device *dev)
103{
8b99e68c
CW		 104 if (IS_GEN5(dev)) {
105 struct drm_i915_private *dev_priv = dev->dev_private;
106 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
107 } else
108 return 27;
021357ac
CW		 109}
110
e4b36699 111static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 112 .dot = { .min = 25000, .max = 350000 },
113 .vco = { .min = 930000, .max = 1400000 },
114 .n = { .min = 3, .max = 16 },
115 .m = { .min = 96, .max = 140 },
116 .m1 = { .min = 18, .max = 26 },
117 .m2 = { .min = 6, .max = 16 },
118 .p = { .min = 4, .max = 128 },
119 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 120 .p2 = { .dot_limit = 165000,
121 .p2_slow = 4, .p2_fast = 2 },
d4906093 122 .find_pll = intel_find_best_PLL,
e4b36699
KP		 123};
124
125static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 126 .dot = { .min = 25000, .max = 350000 },
127 .vco = { .min = 930000, .max = 1400000 },
128 .n = { .min = 3, .max = 16 },
129 .m = { .min = 96, .max = 140 },
130 .m1 = { .min = 18, .max = 26 },
131 .m2 = { .min = 6, .max = 16 },
132 .p = { .min = 4, .max = 128 },
133 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 134 .p2 = { .dot_limit = 165000,
135 .p2_slow = 14, .p2_fast = 7 },
d4906093 136 .find_pll = intel_find_best_PLL,
e4b36699 137};
273e27ca 138
e4b36699 139static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 140 .dot = { .min = 20000, .max = 400000 },
141 .vco = { .min = 1400000, .max = 2800000 },
142 .n = { .min = 1, .max = 6 },
143 .m = { .min = 70, .max = 120 },
144 .m1 = { .min = 10, .max = 22 },
145 .m2 = { .min = 5, .max = 9 },
146 .p = { .min = 5, .max = 80 },
147 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 148 .p2 = { .dot_limit = 200000,
149 .p2_slow = 10, .p2_fast = 5 },
d4906093 150 .find_pll = intel_find_best_PLL,
e4b36699
KP		 151};
152
153static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 154 .dot = { .min = 20000, .max = 400000 },
155 .vco = { .min = 1400000, .max = 2800000 },
156 .n = { .min = 1, .max = 6 },
157 .m = { .min = 70, .max = 120 },
158 .m1 = { .min = 10, .max = 22 },
159 .m2 = { .min = 5, .max = 9 },
160 .p = { .min = 7, .max = 98 },
161 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 162 .p2 = { .dot_limit = 112000,
163 .p2_slow = 14, .p2_fast = 7 },
d4906093 164 .find_pll = intel_find_best_PLL,
e4b36699
KP		 165};
166
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 169 .dot = { .min = 25000, .max = 270000 },
170 .vco = { .min = 1750000, .max = 3500000},
171 .n = { .min = 1, .max = 4 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 10, .max = 30 },
176 .p1 = { .min = 1, .max = 3},
177 .p2 = { .dot_limit = 270000,
178 .p2_slow = 10,
179 .p2_fast = 10
044c7c41 180 },
d4906093 181 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 182};
183
184static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 185 .dot = { .min = 22000, .max = 400000 },
186 .vco = { .min = 1750000, .max = 3500000},
187 .n = { .min = 1, .max = 4 },
188 .m = { .min = 104, .max = 138 },
189 .m1 = { .min = 16, .max = 23 },
190 .m2 = { .min = 5, .max = 11 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8},
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 10, .p2_fast = 5 },
d4906093 195 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 196};
197
198static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 199 .dot = { .min = 20000, .max = 115000 },
200 .vco = { .min = 1750000, .max = 3500000 },
201 .n = { .min = 1, .max = 3 },
202 .m = { .min = 104, .max = 138 },
203 .m1 = { .min = 17, .max = 23 },
204 .m2 = { .min = 5, .max = 11 },
205 .p = { .min = 28, .max = 112 },
206 .p1 = { .min = 2, .max = 8 },
207 .p2 = { .dot_limit = 0,
208 .p2_slow = 14, .p2_fast = 14
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 80000, .max = 224000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 14, .max = 42 },
221 .p1 = { .min = 2, .max = 6 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 7, .p2_fast = 7
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 229 .dot = { .min = 161670, .max = 227000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 2 },
232 .m = { .min = 97, .max = 108 },
233 .m1 = { .min = 0x10, .max = 0x12 },
234 .m2 = { .min = 0x05, .max = 0x06 },
235 .p = { .min = 10, .max = 20 },
236 .p1 = { .min = 1, .max = 2},
237 .p2 = { .dot_limit = 0,
273e27ca 238 .p2_slow = 10, .p2_fast = 10 },
0206e353 239 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 240};
241
f2b115e6 242static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 243 .dot = { .min = 20000, .max = 400000},
244 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 245 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
273e27ca 248 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 249 .m1 = { .min = 0, .max = 0 },
250 .m2 = { .min = 0, .max = 254 },
251 .p = { .min = 5, .max = 80 },
252 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 253 .p2 = { .dot_limit = 200000,
254 .p2_slow = 10, .p2_fast = 5 },
6115707b 255 .find_pll = intel_find_best_PLL,
e4b36699
KP		 256};
257
f2b115e6 258static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 259 .dot = { .min = 20000, .max = 400000 },
260 .vco = { .min = 1700000, .max = 3500000 },
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 .m1 = { .min = 0, .max = 0 },
264 .m2 = { .min = 0, .max = 254 },
265 .p = { .min = 7, .max = 112 },
266 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 267 .p2 = { .dot_limit = 112000,
268 .p2_slow = 14, .p2_fast = 14 },
6115707b 269 .find_pll = intel_find_best_PLL,
e4b36699
KP		 270};
271
273e27ca
EA		 272/* Ironlake / Sandybridge
273 *
274 * We calculate clock using (register_value + 2) for N/M1/M2, so here
275 * the range value for them is (actual_value - 2).
276 */
b91ad0ec 277static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 278 .dot = { .min = 25000, .max = 350000 },
279 .vco = { .min = 1760000, .max = 3510000 },
280 .n = { .min = 1, .max = 5 },
281 .m = { .min = 79, .max = 127 },
282 .m1 = { .min = 12, .max = 22 },
283 .m2 = { .min = 5, .max = 9 },
284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
286 .p2 = { .dot_limit = 225000,
287 .p2_slow = 10, .p2_fast = 5 },
4547668a 288 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 289};
290
b91ad0ec 291static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 292 .dot = { .min = 25000, .max = 350000 },
293 .vco = { .min = 1760000, .max = 3510000 },
294 .n = { .min = 1, .max = 3 },
295 .m = { .min = 79, .max = 118 },
296 .m1 = { .min = 12, .max = 22 },
297 .m2 = { .min = 5, .max = 9 },
298 .p = { .min = 28, .max = 112 },
299 .p1 = { .min = 2, .max = 8 },
300 .p2 = { .dot_limit = 225000,
301 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 302 .find_pll = intel_g4x_find_best_PLL,
303};
304
305static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 3 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 14, .max = 56 },
313 .p1 = { .min = 2, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 316 .find_pll = intel_g4x_find_best_PLL,
317};
318
273e27ca 319/* LVDS 100mhz refclk limits. */
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 2 },
324 .m = { .min = 79, .max = 126 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
0206e353 328 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 42 },
0206e353 342 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
348static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 349 .dot = { .min = 25000, .max = 350000 },
350 .vco = { .min = 1760000, .max = 3510000},
351 .n = { .min = 1, .max = 2 },
352 .m = { .min = 81, .max = 90 },
353 .m1 = { .min = 12, .max = 22 },
354 .m2 = { .min = 5, .max = 9 },
355 .p = { .min = 10, .max = 20 },
356 .p1 = { .min = 1, .max = 2},
357 .p2 = { .dot_limit = 0,
273e27ca 358 .p2_slow = 10, .p2_fast = 10 },
0206e353 359 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 360};
361
57f350b6
JB		 362u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
363{
364 unsigned long flags;
365 u32 val = 0;
366
367 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
368 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
369 DRM_ERROR("DPIO idle wait timed out\n");
370 goto out_unlock;
371 }
372
373 I915_WRITE(DPIO_REG, reg);
374 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
375 DPIO_BYTE);
376 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
377 DRM_ERROR("DPIO read wait timed out\n");
378 goto out_unlock;
379 }
380 val = I915_READ(DPIO_DATA);
381
382out_unlock:
383 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
384 return val;
385}
386
57f350b6
JB		 387static void vlv_init_dpio(struct drm_device *dev)
388{
389 struct drm_i915_private *dev_priv = dev->dev_private;
390
391 /* Reset the DPIO config */
392 I915_WRITE(DPIO_CTL, 0);
393 POSTING_READ(DPIO_CTL);
394 I915_WRITE(DPIO_CTL, 1);
395 POSTING_READ(DPIO_CTL);
396}
397
618563e3
DV		 398static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
399{
400 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
401 return 1;
402}
403
404static const struct dmi_system_id intel_dual_link_lvds[] = {
405 {
406 .callback = intel_dual_link_lvds_callback,
407 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
408 .matches = {
409 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
410 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
411 },
412 },
413 { } /* terminating entry */
414};
415
b0354385
TI		 416static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
417 unsigned int reg)
418{
419 unsigned int val;
420
121d527a
TI		 421 /* use the module option value if specified */
422 if (i915_lvds_channel_mode > 0)
423 return i915_lvds_channel_mode == 2;
424
618563e3
DV		 425 if (dmi_check_system(intel_dual_link_lvds))
426 return true;
427
b0354385
TI		 428 if (dev_priv->lvds_val)
429 val = dev_priv->lvds_val;
430 else {
431 /* BIOS should set the proper LVDS register value at boot, but
432 * in reality, it doesn't set the value when the lid is closed;
433 * we need to check "the value to be set" in VBT when LVDS
434 * register is uninitialized.
435 */
436 val = I915_READ(reg);
14d94a3d 437 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 438 val = dev_priv->bios_lvds_val;
439 dev_priv->lvds_val = val;
440 }
441 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
442}
443
1b894b59
CW		 444static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
445 int refclk)
2c07245f 446{
b91ad0ec
ZW		 447 struct drm_device *dev = crtc->dev;
448 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 449 const intel_limit_t *limit;
b91ad0ec
ZW		 450
451 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 452 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 453 /* LVDS dual channel */
1b894b59 454 if (refclk == 100000)
b91ad0ec
ZW		 455 limit = &intel_limits_ironlake_dual_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_dual_lvds;
458 } else {
1b894b59 459 if (refclk == 100000)
b91ad0ec
ZW		 460 limit = &intel_limits_ironlake_single_lvds_100m;
461 else
462 limit = &intel_limits_ironlake_single_lvds;
463 }
464 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 465 HAS_eDP)
466 limit = &intel_limits_ironlake_display_port;
2c07245f 467 else
b91ad0ec 468 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 469
470 return limit;
471}
472
044c7c41
ML		 473static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
474{
475 struct drm_device *dev = crtc->dev;
476 struct drm_i915_private *dev_priv = dev->dev_private;
477 const intel_limit_t *limit;
478
479 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 480 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 481 /* LVDS with dual channel */
e4b36699 482 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 483 else
484 /* LVDS with dual channel */
e4b36699 485 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 486 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
487 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 488 limit = &intel_limits_g4x_hdmi;
044c7c41 489 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 490 limit = &intel_limits_g4x_sdvo;
0206e353 491 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 492 limit = &intel_limits_g4x_display_port;
044c7c41 493 } else /* The option is for other outputs */
e4b36699 494 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 495
496 return limit;
497}
498
1b894b59 499static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 500{
501 struct drm_device *dev = crtc->dev;
502 const intel_limit_t *limit;
503
bad720ff 504 if (HAS_PCH_SPLIT(dev))
1b894b59 505 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 506 else if (IS_G4X(dev)) {
044c7c41 507 limit = intel_g4x_limit(crtc);
f2b115e6 508 } else if (IS_PINEVIEW(dev)) {
2177832f 509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 510 limit = &intel_limits_pineview_lvds;
2177832f 511 else
f2b115e6 512 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 513 } else if (!IS_GEN2(dev)) {
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i9xx_lvds;
516 else
517 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 518 } else {
519 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 520 limit = &intel_limits_i8xx_lvds;
79e53945 521 else
e4b36699 522 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 523 }
524 return limit;
525}
526
f2b115e6
AJ		 527/* m1 is reserved as 0 in Pineview, n is a ring counter */
528static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 529{
2177832f
SL		 530 clock->m = clock->m2 + 2;
531 clock->p = clock->p1 * clock->p2;
532 clock->vco = refclk * clock->m / clock->n;
533 clock->dot = clock->vco / clock->p;
534}
535
536static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
537{
f2b115e6
AJ		 538 if (IS_PINEVIEW(dev)) {
539 pineview_clock(refclk, clock);
2177832f
SL		 540 return;
541 }
79e53945
JB		 542 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
543 clock->p = clock->p1 * clock->p2;
544 clock->vco = refclk * clock->m / (clock->n + 2);
545 clock->dot = clock->vco / clock->p;
546}
547
79e53945
JB		 548/**
549 * Returns whether any output on the specified pipe is of the specified type
550 */
4ef69c7a 551bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 552{
4ef69c7a
CW		 553 struct drm_device *dev = crtc->dev;
554 struct drm_mode_config *mode_config = &dev->mode_config;
555 struct intel_encoder *encoder;
556
557 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
558 if (encoder->base.crtc == crtc && encoder->type == type)
559 return true;
560
561 return false;
79e53945
JB		 562}
563
7c04d1d9 564#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 565/**
566 * Returns whether the given set of divisors are valid for a given refclk with
567 * the given connectors.
568 */
569
1b894b59
CW		 570static bool intel_PLL_is_valid(struct drm_device *dev,
571 const intel_limit_t *limit,
572 const intel_clock_t *clock)
79e53945 573{
79e53945 574 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 575 INTELPllInvalid("p1 out of range\n");
79e53945 576 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 577 INTELPllInvalid("p out of range\n");
79e53945 578 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 579 INTELPllInvalid("m2 out of range\n");
79e53945 580 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 581 INTELPllInvalid("m1 out of range\n");
f2b115e6 582 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 583 INTELPllInvalid("m1 <= m2\n");
79e53945 584 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 585 INTELPllInvalid("m out of range\n");
79e53945 586 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 587 INTELPllInvalid("n out of range\n");
79e53945 588 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 589 INTELPllInvalid("vco out of range\n");
79e53945
JB		 590 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
591 * connector, etc., rather than just a single range.
592 */
593 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 594 INTELPllInvalid("dot out of range\n");
79e53945
JB		 595
596 return true;
597}
598
d4906093
ML		 599static bool
600intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 601 int target, int refclk, intel_clock_t *match_clock,
602 intel_clock_t *best_clock)
d4906093 603
79e53945
JB		 604{
605 struct drm_device *dev = crtc->dev;
606 struct drm_i915_private *dev_priv = dev->dev_private;
607 intel_clock_t clock;
79e53945
JB		 608 int err = target;
609
bc5e5718 610 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 611 (I915_READ(LVDS)) != 0) {
79e53945
JB		 612 /*
613 * For LVDS, if the panel is on, just rely on its current
614 * settings for dual-channel. We haven't figured out how to
615 * reliably set up different single/dual channel state, if we
616 * even can.
617 */
b0354385 618 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 619 clock.p2 = limit->p2.p2_fast;
620 else
621 clock.p2 = limit->p2.p2_slow;
622 } else {
623 if (target < limit->p2.dot_limit)
624 clock.p2 = limit->p2.p2_slow;
625 else
626 clock.p2 = limit->p2.p2_fast;
627 }
628
0206e353 629 memset(best_clock, 0, sizeof(*best_clock));
79e53945 630
42158660
ZY		 631 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
632 clock.m1++) {
633 for (clock.m2 = limit->m2.min;
634 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 635 /* m1 is always 0 in Pineview */
636 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 637 break;
638 for (clock.n = limit->n.min;
639 clock.n <= limit->n.max; clock.n++) {
640 for (clock.p1 = limit->p1.min;
641 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 642 int this_err;
643
2177832f 644 intel_clock(dev, refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
79e53945 647 continue;
cec2f356
SP		 648 if (match_clock &&
649 clock.p != match_clock->p)
650 continue;
79e53945
JB		 651
652 this_err = abs(clock.dot - target);
653 if (this_err < err) {
654 *best_clock = clock;
655 err = this_err;
656 }
657 }
658 }
659 }
660 }
661
662 return (err != target);
663}
664
d4906093
ML		 665static bool
666intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 667 int target, int refclk, intel_clock_t *match_clock,
668 intel_clock_t *best_clock)
d4906093
ML		 669{
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 intel_clock_t clock;
673 int max_n;
674 bool found;
6ba770dc
AJ		 675 /* approximately equals target * 0.00585 */
676 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 677 found = false;
678
679 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 680 int lvds_reg;
681
c619eed4 682 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 683 lvds_reg = PCH_LVDS;
684 else
685 lvds_reg = LVDS;
686 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 687 LVDS_CLKB_POWER_UP)
688 clock.p2 = limit->p2.p2_fast;
689 else
690 clock.p2 = limit->p2.p2_slow;
691 } else {
692 if (target < limit->p2.dot_limit)
693 clock.p2 = limit->p2.p2_slow;
694 else
695 clock.p2 = limit->p2.p2_fast;
696 }
697
698 memset(best_clock, 0, sizeof(*best_clock));
699 max_n = limit->n.max;
f77f13e2 700 /* based on hardware requirement, prefer smaller n to precision */
d4906093 701 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 702 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 703 for (clock.m1 = limit->m1.max;
704 clock.m1 >= limit->m1.min; clock.m1--) {
705 for (clock.m2 = limit->m2.max;
706 clock.m2 >= limit->m2.min; clock.m2--) {
707 for (clock.p1 = limit->p1.max;
708 clock.p1 >= limit->p1.min; clock.p1--) {
709 int this_err;
710
2177832f 711 intel_clock(dev, refclk, &clock);
1b894b59
CW		 712 if (!intel_PLL_is_valid(dev, limit,
713 &clock))
d4906093 714 continue;
cec2f356
SP		 715 if (match_clock &&
716 clock.p != match_clock->p)
717 continue;
1b894b59
CW		 718
719 this_err = abs(clock.dot - target);
d4906093
ML		 720 if (this_err < err_most) {
721 *best_clock = clock;
722 err_most = this_err;
723 max_n = clock.n;
724 found = true;
725 }
726 }
727 }
728 }
729 }
2c07245f
ZW		 730 return found;
731}
732
5eb08b69 733static bool
f2b115e6 734intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 735 int target, int refclk, intel_clock_t *match_clock,
736 intel_clock_t *best_clock)
5eb08b69
ZW		 737{
738 struct drm_device *dev = crtc->dev;
739 intel_clock_t clock;
4547668a 740
5eb08b69
ZW		 741 if (target < 200000) {
742 clock.n = 1;
743 clock.p1 = 2;
744 clock.p2 = 10;
745 clock.m1 = 12;
746 clock.m2 = 9;
747 } else {
748 clock.n = 2;
749 clock.p1 = 1;
750 clock.p2 = 10;
751 clock.m1 = 14;
752 clock.m2 = 8;
753 }
754 intel_clock(dev, refclk, &clock);
755 memcpy(best_clock, &clock, sizeof(intel_clock_t));
756 return true;
757}
758
a4fc5ed6
KP		 759/* DisplayPort has only two frequencies, 162MHz and 270MHz */
760static bool
761intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
a4fc5ed6 764{
5eddb70b
CW		 765 intel_clock_t clock;
766 if (target < 200000) {
767 clock.p1 = 2;
768 clock.p2 = 10;
769 clock.n = 2;
770 clock.m1 = 23;
771 clock.m2 = 8;
772 } else {
773 clock.p1 = 1;
774 clock.p2 = 10;
775 clock.n = 1;
776 clock.m1 = 14;
777 clock.m2 = 2;
778 }
779 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
780 clock.p = (clock.p1 * clock.p2);
781 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
782 clock.vco = 0;
783 memcpy(best_clock, &clock, sizeof(intel_clock_t));
784 return true;
a4fc5ed6
KP		 785}
786
a928d536
PZ		 787static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
788{
789 struct drm_i915_private *dev_priv = dev->dev_private;
790 u32 frame, frame_reg = PIPEFRAME(pipe);
791
792 frame = I915_READ(frame_reg);
793
794 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
795 DRM_DEBUG_KMS("vblank wait timed out\n");
796}
797
9d0498a2
JB		 798/**
799 * intel_wait_for_vblank - wait for vblank on a given pipe
800 * @dev: drm device
801 * @pipe: pipe to wait for
802 *
803 * Wait for vblank to occur on a given pipe. Needed for various bits of
804 * mode setting code.
805 */
806void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 807{
9d0498a2 808 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 809 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 810
a928d536
PZ		 811 if (INTEL_INFO(dev)->gen >= 5) {
812 ironlake_wait_for_vblank(dev, pipe);
813 return;
814 }
815
300387c0
CW		 816 /* Clear existing vblank status. Note this will clear any other
817 * sticky status fields as well.
818 *
819 * This races with i915_driver_irq_handler() with the result
820 * that either function could miss a vblank event. Here it is not
821 * fatal, as we will either wait upon the next vblank interrupt or
822 * timeout. Generally speaking intel_wait_for_vblank() is only
823 * called during modeset at which time the GPU should be idle and
824 * should *not* be performing page flips and thus not waiting on
825 * vblanks...
826 * Currently, the result of us stealing a vblank from the irq
827 * handler is that a single frame will be skipped during swapbuffers.
828 */
829 I915_WRITE(pipestat_reg,
830 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
831
9d0498a2 832 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 833 if (wait_for(I915_READ(pipestat_reg) &
834 PIPE_VBLANK_INTERRUPT_STATUS,
835 50))
9d0498a2
JB		 836 DRM_DEBUG_KMS("vblank wait timed out\n");
837}
838
ab7ad7f6
KP		 839/*
840 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 841 * @dev: drm device
842 * @pipe: pipe to wait for
843 *
844 * After disabling a pipe, we can't wait for vblank in the usual way,
845 * spinning on the vblank interrupt status bit, since we won't actually
846 * see an interrupt when the pipe is disabled.
847 *
ab7ad7f6
KP		 848 * On Gen4 and above:
849 * wait for the pipe register state bit to turn off
850 *
851 * Otherwise:
852 * wait for the display line value to settle (it usually
853 * ends up stopping at the start of the next frame).
58e10eb9 854 *
9d0498a2 855 */
58e10eb9 856void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 857{
858 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 859
860 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 861 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 862
863 /* Wait for the Pipe State to go off */
58e10eb9
CW		 864 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
865 100))
ab7ad7f6
KP		 866 DRM_DEBUG_KMS("pipe_off wait timed out\n");
867 } else {
837ba00f 868 u32 last_line, line_mask;
58e10eb9 869 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 870 unsigned long timeout = jiffies + msecs_to_jiffies(100);
871
837ba00f
PZ		 872 if (IS_GEN2(dev))
873 line_mask = DSL_LINEMASK_GEN2;
874 else
875 line_mask = DSL_LINEMASK_GEN3;
876
ab7ad7f6
KP		 877 /* Wait for the display line to settle */
878 do {
837ba00f 879 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 880 mdelay(5);
837ba00f 881 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 882 time_after(timeout, jiffies));
883 if (time_after(jiffies, timeout))
884 DRM_DEBUG_KMS("pipe_off wait timed out\n");
885 }
79e53945
JB		 886}
887
b24e7179
JB		 888static const char *state_string(bool enabled)
889{
890 return enabled ? "on" : "off";
891}
892
893/* Only for pre-ILK configs */
894static void assert_pll(struct drm_i915_private *dev_priv,
895 enum pipe pipe, bool state)
896{
897 int reg;
898 u32 val;
899 bool cur_state;
900
901 reg = DPLL(pipe);
902 val = I915_READ(reg);
903 cur_state = !!(val & DPLL_VCO_ENABLE);
904 WARN(cur_state != state,
905 "PLL state assertion failure (expected %s, current %s)\n",
906 state_string(state), state_string(cur_state));
907}
908#define assert_pll_enabled(d, p) assert_pll(d, p, true)
909#define assert_pll_disabled(d, p) assert_pll(d, p, false)
910
040484af
JB		 911/* For ILK+ */
912static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 913 struct intel_pch_pll *pll,
914 struct intel_crtc *crtc,
915 bool state)
040484af 916{
040484af
JB		 917 u32 val;
918 bool cur_state;
919
9d82aa17
ED		 920 if (HAS_PCH_LPT(dev_priv->dev)) {
921 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
922 return;
923 }
924
92b27b08
CW		 925 if (WARN (!pll,
926 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 927 return;
ee7b9f93 928
92b27b08
CW		 929 val = I915_READ(pll->pll_reg);
930 cur_state = !!(val & DPLL_VCO_ENABLE);
931 WARN(cur_state != state,
932 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
933 pll->pll_reg, state_string(state), state_string(cur_state), val);
934
935 /* Make sure the selected PLL is correctly attached to the transcoder */
936 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 937 u32 pch_dpll;
938
939 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 940 cur_state = pll->pll_reg == _PCH_DPLL_B;
941 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
942 "PLL[%d] not attached to this transcoder %d: %08x\n",
943 cur_state, crtc->pipe, pch_dpll)) {
944 cur_state = !!(val >> (4*crtc->pipe + 3));
945 WARN(cur_state != state,
946 "PLL[%d] not %s on this transcoder %d: %08x\n",
947 pll->pll_reg == _PCH_DPLL_B,
948 state_string(state),
949 crtc->pipe,
950 val);
951 }
d3ccbe86 952 }
040484af 953}
92b27b08
CW		 954#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
955#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 956
957static void assert_fdi_tx(struct drm_i915_private *dev_priv,
958 enum pipe pipe, bool state)
959{
960 int reg;
961 u32 val;
962 bool cur_state;
963
bf507ef7
ED		 964 if (IS_HASWELL(dev_priv->dev)) {
965 /* On Haswell, DDI is used instead of FDI_TX_CTL */
966 reg = DDI_FUNC_CTL(pipe);
967 val = I915_READ(reg);
968 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
969 } else {
970 reg = FDI_TX_CTL(pipe);
971 val = I915_READ(reg);
972 cur_state = !!(val & FDI_TX_ENABLE);
973 }
040484af
JB		 974 WARN(cur_state != state,
975 "FDI TX state assertion failure (expected %s, current %s)\n",
976 state_string(state), state_string(cur_state));
977}
978#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
979#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
980
981static void assert_fdi_rx(struct drm_i915_private *dev_priv,
982 enum pipe pipe, bool state)
983{
984 int reg;
985 u32 val;
986 bool cur_state;
987
59c859d6
ED		 988 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
989 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
990 return;
991 } else {
992 reg = FDI_RX_CTL(pipe);
993 val = I915_READ(reg);
994 cur_state = !!(val & FDI_RX_ENABLE);
995 }
040484af
JB		 996 WARN(cur_state != state,
997 "FDI RX state assertion failure (expected %s, current %s)\n",
998 state_string(state), state_string(cur_state));
999}
1000#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1001#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1002
1003static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1004 enum pipe pipe)
1005{
1006 int reg;
1007 u32 val;
1008
1009 /* ILK FDI PLL is always enabled */
1010 if (dev_priv->info->gen == 5)
1011 return;
1012
bf507ef7
ED		 1013 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1014 if (IS_HASWELL(dev_priv->dev))
1015 return;
1016
040484af
JB		 1017 reg = FDI_TX_CTL(pipe);
1018 val = I915_READ(reg);
1019 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1020}
1021
1022static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1023 enum pipe pipe)
1024{
1025 int reg;
1026 u32 val;
1027
59c859d6
ED		 1028 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1029 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1030 return;
1031 }
040484af
JB		 1032 reg = FDI_RX_CTL(pipe);
1033 val = I915_READ(reg);
1034 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1035}
1036
ea0760cf
JB		 1037static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1038 enum pipe pipe)
1039{
1040 int pp_reg, lvds_reg;
1041 u32 val;
1042 enum pipe panel_pipe = PIPE_A;
0de3b485 1043 bool locked = true;
ea0760cf
JB		 1044
1045 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1046 pp_reg = PCH_PP_CONTROL;
1047 lvds_reg = PCH_LVDS;
1048 } else {
1049 pp_reg = PP_CONTROL;
1050 lvds_reg = LVDS;
1051 }
1052
1053 val = I915_READ(pp_reg);
1054 if (!(val & PANEL_POWER_ON) ||
1055 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1056 locked = false;
1057
1058 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1059 panel_pipe = PIPE_B;
1060
1061 WARN(panel_pipe == pipe && locked,
1062 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1063 pipe_name(pipe));
ea0760cf
JB		 1064}
1065
b840d907
JB		 1066void assert_pipe(struct drm_i915_private *dev_priv,
1067 enum pipe pipe, bool state)
b24e7179
JB		 1068{
1069 int reg;
1070 u32 val;
63d7bbe9 1071 bool cur_state;
b24e7179 1072
8e636784
DV		 1073 /* if we need the pipe A quirk it must be always on */
1074 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1075 state = true;
1076
b24e7179
JB		 1077 reg = PIPECONF(pipe);
1078 val = I915_READ(reg);
63d7bbe9
JB		 1079 cur_state = !!(val & PIPECONF_ENABLE);
1080 WARN(cur_state != state,
1081 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1082 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1083}
1084
931872fc
CW		 1085static void assert_plane(struct drm_i915_private *dev_priv,
1086 enum plane plane, bool state)
b24e7179
JB		 1087{
1088 int reg;
1089 u32 val;
931872fc 1090 bool cur_state;
b24e7179
JB		 1091
1092 reg = DSPCNTR(plane);
1093 val = I915_READ(reg);
931872fc
CW		 1094 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1095 WARN(cur_state != state,
1096 "plane %c assertion failure (expected %s, current %s)\n",
1097 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1098}
1099
931872fc
CW		 1100#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1101#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1102
b24e7179
JB		 1103static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1104 enum pipe pipe)
1105{
1106 int reg, i;
1107 u32 val;
1108 int cur_pipe;
1109
19ec1358 1110 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1111 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1112 reg = DSPCNTR(pipe);
1113 val = I915_READ(reg);
1114 WARN((val & DISPLAY_PLANE_ENABLE),
1115 "plane %c assertion failure, should be disabled but not\n",
1116 plane_name(pipe));
19ec1358 1117 return;
28c05794 1118 }
19ec1358 1119
b24e7179
JB		 1120 /* Need to check both planes against the pipe */
1121 for (i = 0; i < 2; i++) {
1122 reg = DSPCNTR(i);
1123 val = I915_READ(reg);
1124 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1125 DISPPLANE_SEL_PIPE_SHIFT;
1126 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1127 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1128 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1129 }
1130}
1131
92f2584a
JB		 1132static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1133{
1134 u32 val;
1135 bool enabled;
1136
9d82aa17
ED		 1137 if (HAS_PCH_LPT(dev_priv->dev)) {
1138 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1139 return;
1140 }
1141
92f2584a
JB		 1142 val = I915_READ(PCH_DREF_CONTROL);
1143 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1144 DREF_SUPERSPREAD_SOURCE_MASK));
1145 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1146}
1147
1148static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1149 enum pipe pipe)
1150{
1151 int reg;
1152 u32 val;
1153 bool enabled;
1154
1155 reg = TRANSCONF(pipe);
1156 val = I915_READ(reg);
1157 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1158 WARN(enabled,
1159 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1160 pipe_name(pipe));
92f2584a
JB		 1161}
1162
4e634389
KP		 1163static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1164 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1165{
1166 if ((val & DP_PORT_EN) == 0)
1167 return false;
1168
1169 if (HAS_PCH_CPT(dev_priv->dev)) {
1170 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1171 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1172 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1173 return false;
1174 } else {
1175 if ((val & DP_PIPE_MASK) != (pipe << 30))
1176 return false;
1177 }
1178 return true;
1179}
1180
1519b995
KP		 1181static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1182 enum pipe pipe, u32 val)
1183{
1184 if ((val & PORT_ENABLE) == 0)
1185 return false;
1186
1187 if (HAS_PCH_CPT(dev_priv->dev)) {
1188 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1189 return false;
1190 } else {
1191 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1192 return false;
1193 }
1194 return true;
1195}
1196
1197static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1198 enum pipe pipe, u32 val)
1199{
1200 if ((val & LVDS_PORT_EN) == 0)
1201 return false;
1202
1203 if (HAS_PCH_CPT(dev_priv->dev)) {
1204 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1205 return false;
1206 } else {
1207 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1208 return false;
1209 }
1210 return true;
1211}
1212
1213static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1214 enum pipe pipe, u32 val)
1215{
1216 if ((val & ADPA_DAC_ENABLE) == 0)
1217 return false;
1218 if (HAS_PCH_CPT(dev_priv->dev)) {
1219 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1220 return false;
1221 } else {
1222 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1223 return false;
1224 }
1225 return true;
1226}
1227
291906f1 1228static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1229 enum pipe pipe, int reg, u32 port_sel)
291906f1 1230{
47a05eca 1231 u32 val = I915_READ(reg);
4e634389 1232 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1233 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1234 reg, pipe_name(pipe));
de9a35ab
DV		 1235
1236 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1237 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1238}
1239
1240static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1241 enum pipe pipe, int reg)
1242{
47a05eca 1243 u32 val = I915_READ(reg);
1519b995 1244 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1245 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1246 reg, pipe_name(pipe));
de9a35ab
DV		 1247
1248 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1249 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1250}
1251
1252static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1253 enum pipe pipe)
1254{
1255 int reg;
1256 u32 val;
291906f1 1257
f0575e92
KP		 1258 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1259 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1260 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1261
1262 reg = PCH_ADPA;
1263 val = I915_READ(reg);
1519b995 1264 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1265 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1266 pipe_name(pipe));
291906f1
JB		 1267
1268 reg = PCH_LVDS;
1269 val = I915_READ(reg);
1519b995 1270 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1271 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1272 pipe_name(pipe));
291906f1
JB		 1273
1274 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1275 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1276 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1277}
1278
63d7bbe9
JB		 1279/**
1280 * intel_enable_pll - enable a PLL
1281 * @dev_priv: i915 private structure
1282 * @pipe: pipe PLL to enable
1283 *
1284 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1285 * make sure the PLL reg is writable first though, since the panel write
1286 * protect mechanism may be enabled.
1287 *
1288 * Note! This is for pre-ILK only.
1289 */
1290static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1291{
1292 int reg;
1293 u32 val;
1294
1295 /* No really, not for ILK+ */
1296 BUG_ON(dev_priv->info->gen >= 5);
1297
1298 /* PLL is protected by panel, make sure we can write it */
1299 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1300 assert_panel_unlocked(dev_priv, pipe);
1301
1302 reg = DPLL(pipe);
1303 val = I915_READ(reg);
1304 val |= DPLL_VCO_ENABLE;
1305
1306 /* We do this three times for luck */
1307 I915_WRITE(reg, val);
1308 POSTING_READ(reg);
1309 udelay(150); /* wait for warmup */
1310 I915_WRITE(reg, val);
1311 POSTING_READ(reg);
1312 udelay(150); /* wait for warmup */
1313 I915_WRITE(reg, val);
1314 POSTING_READ(reg);
1315 udelay(150); /* wait for warmup */
1316}
1317
1318/**
1319 * intel_disable_pll - disable a PLL
1320 * @dev_priv: i915 private structure
1321 * @pipe: pipe PLL to disable
1322 *
1323 * Disable the PLL for @pipe, making sure the pipe is off first.
1324 *
1325 * Note! This is for pre-ILK only.
1326 */
1327static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1328{
1329 int reg;
1330 u32 val;
1331
1332 /* Don't disable pipe A or pipe A PLLs if needed */
1333 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1334 return;
1335
1336 /* Make sure the pipe isn't still relying on us */
1337 assert_pipe_disabled(dev_priv, pipe);
1338
1339 reg = DPLL(pipe);
1340 val = I915_READ(reg);
1341 val &= ~DPLL_VCO_ENABLE;
1342 I915_WRITE(reg, val);
1343 POSTING_READ(reg);
1344}
1345
a416edef
ED		 1346/* SBI access */
1347static void
1348intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1349{
1350 unsigned long flags;
1351
1352 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1353 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1354 100)) {
1355 DRM_ERROR("timeout waiting for SBI to become ready\n");
1356 goto out_unlock;
1357 }
1358
1359 I915_WRITE(SBI_ADDR,
1360 (reg << 16));
1361 I915_WRITE(SBI_DATA,
1362 value);
1363 I915_WRITE(SBI_CTL_STAT,
1364 SBI_BUSY |
1365 SBI_CTL_OP_CRWR);
1366
1367 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1368 100)) {
1369 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1370 goto out_unlock;
1371 }
1372
1373out_unlock:
1374 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1375}
1376
1377static u32
1378intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1379{
1380 unsigned long flags;
1381 u32 value;
1382
1383 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1384 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1385 100)) {
1386 DRM_ERROR("timeout waiting for SBI to become ready\n");
1387 goto out_unlock;
1388 }
1389
1390 I915_WRITE(SBI_ADDR,
1391 (reg << 16));
1392 I915_WRITE(SBI_CTL_STAT,
1393 SBI_BUSY |
1394 SBI_CTL_OP_CRRD);
1395
1396 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1397 100)) {
1398 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1399 goto out_unlock;
1400 }
1401
1402 value = I915_READ(SBI_DATA);
1403
1404out_unlock:
1405 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1406 return value;
1407}
1408
92f2584a
JB		 1409/**
1410 * intel_enable_pch_pll - enable PCH PLL
1411 * @dev_priv: i915 private structure
1412 * @pipe: pipe PLL to enable
1413 *
1414 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1415 * drives the transcoder clock.
1416 */
ee7b9f93 1417static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1418{
ee7b9f93 1419 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1420 struct intel_pch_pll *pll;
92f2584a
JB		 1421 int reg;
1422 u32 val;
1423
48da64a8 1424 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1425 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1426 pll = intel_crtc->pch_pll;
1427 if (pll == NULL)
1428 return;
1429
1430 if (WARN_ON(pll->refcount == 0))
1431 return;
ee7b9f93
JB		 1432
1433 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1434 pll->pll_reg, pll->active, pll->on,
1435 intel_crtc->base.base.id);
92f2584a
JB		 1436
1437 /* PCH refclock must be enabled first */
1438 assert_pch_refclk_enabled(dev_priv);
1439
ee7b9f93 1440 if (pll->active++ && pll->on) {
92b27b08 1441 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1442 return;
1443 }
1444
1445 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1446
1447 reg = pll->pll_reg;
92f2584a
JB		 1448 val = I915_READ(reg);
1449 val |= DPLL_VCO_ENABLE;
1450 I915_WRITE(reg, val);
1451 POSTING_READ(reg);
1452 udelay(200);
ee7b9f93
JB		 1453
1454 pll->on = true;
92f2584a
JB		 1455}
1456
ee7b9f93 1457static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1458{
ee7b9f93
JB		 1459 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1460 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1461 int reg;
ee7b9f93 1462 u32 val;
4c609cb8 1463
92f2584a
JB		 1464 /* PCH only available on ILK+ */
1465 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1466 if (pll == NULL)
1467 return;
92f2584a 1468
48da64a8
CW		 1469 if (WARN_ON(pll->refcount == 0))
1470 return;
7a419866 1471
ee7b9f93
JB		 1472 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1473 pll->pll_reg, pll->active, pll->on,
1474 intel_crtc->base.base.id);
7a419866 1475
48da64a8 1476 if (WARN_ON(pll->active == 0)) {
92b27b08 1477 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1478 return;
1479 }
1480
ee7b9f93 1481 if (--pll->active) {
92b27b08 1482 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1483 return;
ee7b9f93
JB		 1484 }
1485
1486 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1487
1488 /* Make sure transcoder isn't still depending on us */
1489 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1490
ee7b9f93 1491 reg = pll->pll_reg;
92f2584a
JB		 1492 val = I915_READ(reg);
1493 val &= ~DPLL_VCO_ENABLE;
1494 I915_WRITE(reg, val);
1495 POSTING_READ(reg);
1496 udelay(200);
ee7b9f93
JB		 1497
1498 pll->on = false;
92f2584a
JB		 1499}
1500
040484af
JB		 1501static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1502 enum pipe pipe)
1503{
1504 int reg;
5f7f726d 1505 u32 val, pipeconf_val;
7c26e5c6 1506 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1507
1508 /* PCH only available on ILK+ */
1509 BUG_ON(dev_priv->info->gen < 5);
1510
1511 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1512 assert_pch_pll_enabled(dev_priv,
1513 to_intel_crtc(crtc)->pch_pll,
1514 to_intel_crtc(crtc));
040484af
JB		 1515
1516 /* FDI must be feeding us bits for PCH ports */
1517 assert_fdi_tx_enabled(dev_priv, pipe);
1518 assert_fdi_rx_enabled(dev_priv, pipe);
1519
59c859d6
ED		 1520 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1521 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1522 return;
1523 }
040484af
JB		 1524 reg = TRANSCONF(pipe);
1525 val = I915_READ(reg);
5f7f726d 1526 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1527
1528 if (HAS_PCH_IBX(dev_priv->dev)) {
1529 /*
1530 * make the BPC in transcoder be consistent with
1531 * that in pipeconf reg.
1532 */
1533 val &= ~PIPE_BPC_MASK;
5f7f726d 1534 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1535 }
5f7f726d
PZ		 1536
1537 val &= ~TRANS_INTERLACE_MASK;
1538 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1539 if (HAS_PCH_IBX(dev_priv->dev) &&
1540 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1541 val |= TRANS_LEGACY_INTERLACED_ILK;
1542 else
1543 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1544 else
1545 val |= TRANS_PROGRESSIVE;
1546
040484af
JB		 1547 I915_WRITE(reg, val | TRANS_ENABLE);
1548 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1549 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1550}
1551
1552static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1553 enum pipe pipe)
1554{
1555 int reg;
1556 u32 val;
1557
1558 /* FDI relies on the transcoder */
1559 assert_fdi_tx_disabled(dev_priv, pipe);
1560 assert_fdi_rx_disabled(dev_priv, pipe);
1561
291906f1
JB		 1562 /* Ports must be off as well */
1563 assert_pch_ports_disabled(dev_priv, pipe);
1564
040484af
JB		 1565 reg = TRANSCONF(pipe);
1566 val = I915_READ(reg);
1567 val &= ~TRANS_ENABLE;
1568 I915_WRITE(reg, val);
1569 /* wait for PCH transcoder off, transcoder state */
1570 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1571 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1572}
1573
b24e7179 1574/**
309cfea8 1575 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1576 * @dev_priv: i915 private structure
1577 * @pipe: pipe to enable
040484af 1578 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1579 *
1580 * Enable @pipe, making sure that various hardware specific requirements
1581 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1582 *
1583 * @pipe should be %PIPE_A or %PIPE_B.
1584 *
1585 * Will wait until the pipe is actually running (i.e. first vblank) before
1586 * returning.
1587 */
040484af
JB		 1588static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1589 bool pch_port)
b24e7179
JB		 1590{
1591 int reg;
1592 u32 val;
1593
1594 /*
1595 * A pipe without a PLL won't actually be able to drive bits from
1596 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1597 * need the check.
1598 */
1599 if (!HAS_PCH_SPLIT(dev_priv->dev))
1600 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1601 else {
1602 if (pch_port) {
1603 /* if driving the PCH, we need FDI enabled */
1604 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1605 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1606 }
1607 /* FIXME: assert CPU port conditions for SNB+ */
1608 }
b24e7179
JB		 1609
1610 reg = PIPECONF(pipe);
1611 val = I915_READ(reg);
00d70b15
CW		 1612 if (val & PIPECONF_ENABLE)
1613 return;
1614
1615 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1616 intel_wait_for_vblank(dev_priv->dev, pipe);
1617}
1618
1619/**
309cfea8 1620 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1621 * @dev_priv: i915 private structure
1622 * @pipe: pipe to disable
1623 *
1624 * Disable @pipe, making sure that various hardware specific requirements
1625 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1626 *
1627 * @pipe should be %PIPE_A or %PIPE_B.
1628 *
1629 * Will wait until the pipe has shut down before returning.
1630 */
1631static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1632 enum pipe pipe)
1633{
1634 int reg;
1635 u32 val;
1636
1637 /*
1638 * Make sure planes won't keep trying to pump pixels to us,
1639 * or we might hang the display.
1640 */
1641 assert_planes_disabled(dev_priv, pipe);
1642
1643 /* Don't disable pipe A or pipe A PLLs if needed */
1644 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1645 return;
1646
1647 reg = PIPECONF(pipe);
1648 val = I915_READ(reg);
00d70b15
CW		 1649 if ((val & PIPECONF_ENABLE) == 0)
1650 return;
1651
1652 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1653 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1654}
1655
d74362c9
KP		 1656/*
1657 * Plane regs are double buffered, going from enabled->disabled needs a
1658 * trigger in order to latch. The display address reg provides this.
1659 */
6f1d69b0 1660void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1661 enum plane plane)
1662{
1663 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1664 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1665}
1666
b24e7179
JB		 1667/**
1668 * intel_enable_plane - enable a display plane on a given pipe
1669 * @dev_priv: i915 private structure
1670 * @plane: plane to enable
1671 * @pipe: pipe being fed
1672 *
1673 * Enable @plane on @pipe, making sure that @pipe is running first.
1674 */
1675static void intel_enable_plane(struct drm_i915_private *dev_priv,
1676 enum plane plane, enum pipe pipe)
1677{
1678 int reg;
1679 u32 val;
1680
1681 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1682 assert_pipe_enabled(dev_priv, pipe);
1683
1684 reg = DSPCNTR(plane);
1685 val = I915_READ(reg);
00d70b15
CW		 1686 if (val & DISPLAY_PLANE_ENABLE)
1687 return;
1688
1689 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1690 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1691 intel_wait_for_vblank(dev_priv->dev, pipe);
1692}
1693
b24e7179
JB		 1694/**
1695 * intel_disable_plane - disable a display plane
1696 * @dev_priv: i915 private structure
1697 * @plane: plane to disable
1698 * @pipe: pipe consuming the data
1699 *
1700 * Disable @plane; should be an independent operation.
1701 */
1702static void intel_disable_plane(struct drm_i915_private *dev_priv,
1703 enum plane plane, enum pipe pipe)
1704{
1705 int reg;
1706 u32 val;
1707
1708 reg = DSPCNTR(plane);
1709 val = I915_READ(reg);
00d70b15
CW		 1710 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1711 return;
1712
1713 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1714 intel_flush_display_plane(dev_priv, plane);
1715 intel_wait_for_vblank(dev_priv->dev, pipe);
1716}
1717
47a05eca 1718static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1719 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1720{
1721 u32 val = I915_READ(reg);
4e634389 1722 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1723 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1724 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1725 }
47a05eca
JB		 1726}
1727
1728static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1729 enum pipe pipe, int reg)
1730{
1731 u32 val = I915_READ(reg);
1519b995 1732 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1733 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1734 reg, pipe);
47a05eca 1735 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1736 }
47a05eca
JB		 1737}
1738
1739/* Disable any ports connected to this transcoder */
1740static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1741 enum pipe pipe)
1742{
1743 u32 reg, val;
1744
1745 val = I915_READ(PCH_PP_CONTROL);
1746 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1747
f0575e92
KP		 1748 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1749 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1750 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1751
1752 reg = PCH_ADPA;
1753 val = I915_READ(reg);
1519b995 1754 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1755 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1756
1757 reg = PCH_LVDS;
1758 val = I915_READ(reg);
1519b995
KP		 1759 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1760 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1761 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1762 POSTING_READ(reg);
1763 udelay(100);
1764 }
1765
1766 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1767 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1768 disable_pch_hdmi(dev_priv, pipe, HDMID);
1769}
1770
127bd2ac 1771int
48b956c5 1772intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1773 struct drm_i915_gem_object *obj,
919926ae 1774 struct intel_ring_buffer *pipelined)
6b95a207 1775{
ce453d81 1776 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1777 u32 alignment;
1778 int ret;
1779
05394f39 1780 switch (obj->tiling_mode) {
6b95a207 1781 case I915_TILING_NONE:
534843da
CW		 1782 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1783 alignment = 128 * 1024;
a6c45cf0 1784 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1785 alignment = 4 * 1024;
1786 else
1787 alignment = 64 * 1024;
6b95a207
KH		 1788 break;
1789 case I915_TILING_X:
1790 /* pin() will align the object as required by fence */
1791 alignment = 0;
1792 break;
1793 case I915_TILING_Y:
1794 /* FIXME: Is this true? */
1795 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1796 return -EINVAL;
1797 default:
1798 BUG();
1799 }
1800
ce453d81 1801 dev_priv->mm.interruptible = false;
2da3b9b9 1802 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1803 if (ret)
ce453d81 1804 goto err_interruptible;
6b95a207
KH		 1805
1806 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1807 * fence, whereas 965+ only requires a fence if using
1808 * framebuffer compression. For simplicity, we always install
1809 * a fence as the cost is not that onerous.
1810 */
06d98131 1811 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1812 if (ret)
1813 goto err_unpin;
1690e1eb 1814
9a5a53b3 1815 i915_gem_object_pin_fence(obj);
6b95a207 1816
ce453d81 1817 dev_priv->mm.interruptible = true;
6b95a207 1818 return 0;
48b956c5
CW		 1819
1820err_unpin:
1821 i915_gem_object_unpin(obj);
ce453d81
CW		 1822err_interruptible:
1823 dev_priv->mm.interruptible = true;
48b956c5 1824 return ret;
6b95a207
KH		 1825}
1826
1690e1eb
CW		 1827void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1828{
1829 i915_gem_object_unpin_fence(obj);
1830 i915_gem_object_unpin(obj);
1831}
1832
17638cd6
JB		 1833static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1834 int x, int y)
81255565
JB		 1835{
1836 struct drm_device *dev = crtc->dev;
1837 struct drm_i915_private *dev_priv = dev->dev_private;
1838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1839 struct intel_framebuffer *intel_fb;
05394f39 1840 struct drm_i915_gem_object *obj;
81255565
JB		 1841 int plane = intel_crtc->plane;
1842 unsigned long Start, Offset;
81255565 1843 u32 dspcntr;
5eddb70b 1844 u32 reg;
81255565
JB		 1845
1846 switch (plane) {
1847 case 0:
1848 case 1:
1849 break;
1850 default:
1851 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1852 return -EINVAL;
1853 }
1854
1855 intel_fb = to_intel_framebuffer(fb);
1856 obj = intel_fb->obj;
81255565 1857
5eddb70b
CW		 1858 reg = DSPCNTR(plane);
1859 dspcntr = I915_READ(reg);
81255565
JB		 1860 /* Mask out pixel format bits in case we change it */
1861 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1862 switch (fb->bits_per_pixel) {
1863 case 8:
1864 dspcntr |= DISPPLANE_8BPP;
1865 break;
1866 case 16:
1867 if (fb->depth == 15)
1868 dspcntr |= DISPPLANE_15_16BPP;
1869 else
1870 dspcntr |= DISPPLANE_16BPP;
1871 break;
1872 case 24:
1873 case 32:
1874 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1875 break;
1876 default:
17638cd6 1877 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 1878 return -EINVAL;
1879 }
a6c45cf0 1880 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1881 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1882 dspcntr |= DISPPLANE_TILED;
1883 else
1884 dspcntr &= ~DISPPLANE_TILED;
1885 }
1886
5eddb70b 1887 I915_WRITE(reg, dspcntr);
81255565 1888
05394f39 1889 Start = obj->gtt_offset;
01f2c773 1890 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1891
4e6cfefc 1892 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 1893 Start, Offset, x, y, fb->pitches[0]);
1894 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1895 if (INTEL_INFO(dev)->gen >= 4) {
446f2545 1896 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
5eddb70b
CW		 1897 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1898 I915_WRITE(DSPADDR(plane), Offset);
1899 } else
1900 I915_WRITE(DSPADDR(plane), Start + Offset);
1901 POSTING_READ(reg);
81255565 1902
17638cd6
JB		 1903 return 0;
1904}
1905
1906static int ironlake_update_plane(struct drm_crtc *crtc,
1907 struct drm_framebuffer *fb, int x, int y)
1908{
1909 struct drm_device *dev = crtc->dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
1911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1912 struct intel_framebuffer *intel_fb;
1913 struct drm_i915_gem_object *obj;
1914 int plane = intel_crtc->plane;
1915 unsigned long Start, Offset;
1916 u32 dspcntr;
1917 u32 reg;
1918
1919 switch (plane) {
1920 case 0:
1921 case 1:
27f8227b 1922 case 2:
17638cd6
JB		 1923 break;
1924 default:
1925 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1926 return -EINVAL;
1927 }
1928
1929 intel_fb = to_intel_framebuffer(fb);
1930 obj = intel_fb->obj;
1931
1932 reg = DSPCNTR(plane);
1933 dspcntr = I915_READ(reg);
1934 /* Mask out pixel format bits in case we change it */
1935 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1936 switch (fb->bits_per_pixel) {
1937 case 8:
1938 dspcntr |= DISPPLANE_8BPP;
1939 break;
1940 case 16:
1941 if (fb->depth != 16)
1942 return -EINVAL;
1943
1944 dspcntr |= DISPPLANE_16BPP;
1945 break;
1946 case 24:
1947 case 32:
1948 if (fb->depth == 24)
1949 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1950 else if (fb->depth == 30)
1951 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1952 else
1953 return -EINVAL;
1954 break;
1955 default:
1956 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1957 return -EINVAL;
1958 }
1959
1960 if (obj->tiling_mode != I915_TILING_NONE)
1961 dspcntr |= DISPPLANE_TILED;
1962 else
1963 dspcntr &= ~DISPPLANE_TILED;
1964
1965 /* must disable */
1966 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1967
1968 I915_WRITE(reg, dspcntr);
1969
1970 Start = obj->gtt_offset;
01f2c773 1971 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 1972
1973 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 1974 Start, Offset, x, y, fb->pitches[0]);
1975 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
446f2545 1976 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
17638cd6
JB		 1977 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1978 I915_WRITE(DSPADDR(plane), Offset);
1979 POSTING_READ(reg);
1980
1981 return 0;
1982}
1983
1984/* Assume fb object is pinned & idle & fenced and just update base pointers */
1985static int
1986intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1987 int x, int y, enum mode_set_atomic state)
1988{
1989 struct drm_device *dev = crtc->dev;
1990 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 1991
6b8e6ed0
CW		 1992 if (dev_priv->display.disable_fbc)
1993 dev_priv->display.disable_fbc(dev);
3dec0095 1994 intel_increase_pllclock(crtc);
81255565 1995
6b8e6ed0 1996 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 1997}
1998
14667a4b
CW		 1999static int
2000intel_finish_fb(struct drm_framebuffer *old_fb)
2001{
2002 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2003 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2004 bool was_interruptible = dev_priv->mm.interruptible;
2005 int ret;
2006
2007 wait_event(dev_priv->pending_flip_queue,
2008 atomic_read(&dev_priv->mm.wedged) ||
2009 atomic_read(&obj->pending_flip) == 0);
2010
2011 /* Big Hammer, we also need to ensure that any pending
2012 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2013 * current scanout is retired before unpinning the old
2014 * framebuffer.
2015 *
2016 * This should only fail upon a hung GPU, in which case we
2017 * can safely continue.
2018 */
2019 dev_priv->mm.interruptible = false;
2020 ret = i915_gem_object_finish_gpu(obj);
2021 dev_priv->mm.interruptible = was_interruptible;
2022
2023 return ret;
2024}
2025
5c3b82e2 2026static int
3c4fdcfb
KH		 2027intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2028 struct drm_framebuffer *old_fb)
79e53945
JB		 2029{
2030 struct drm_device *dev = crtc->dev;
6b8e6ed0 2031 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2032 struct drm_i915_master_private *master_priv;
2033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2034 int ret;
79e53945
JB		 2035
2036 /* no fb bound */
2037 if (!crtc->fb) {
a5071c2f 2038 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2039 return 0;
2040 }
2041
5826eca5
ED		 2042 if(intel_crtc->plane > dev_priv->num_pipe) {
2043 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2044 intel_crtc->plane,
2045 dev_priv->num_pipe);
5c3b82e2 2046 return -EINVAL;
79e53945
JB		 2047 }
2048
5c3b82e2 2049 mutex_lock(&dev->struct_mutex);
265db958
CW		 2050 ret = intel_pin_and_fence_fb_obj(dev,
2051 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2052 NULL);
5c3b82e2
CW		 2053 if (ret != 0) {
2054 mutex_unlock(&dev->struct_mutex);
a5071c2f 2055 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2056 return ret;
2057 }
79e53945 2058
14667a4b
CW		 2059 if (old_fb)
2060 intel_finish_fb(old_fb);
265db958 2061
6b8e6ed0 2062 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
4e6cfefc 2063 if (ret) {
1690e1eb 2064 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2065 mutex_unlock(&dev->struct_mutex);
a5071c2f 2066 DRM_ERROR("failed to update base address\n");
4e6cfefc 2067 return ret;
79e53945 2068 }
3c4fdcfb 2069
b7f1de28
CW		 2070 if (old_fb) {
2071 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2072 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2073 }
652c393a 2074
6b8e6ed0 2075 intel_update_fbc(dev);
5c3b82e2 2076 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2077
2078 if (!dev->primary->master)
5c3b82e2 2079 return 0;
79e53945
JB		 2080
2081 master_priv = dev->primary->master->driver_priv;
2082 if (!master_priv->sarea_priv)
5c3b82e2 2083 return 0;
79e53945 2084
265db958 2085 if (intel_crtc->pipe) {
79e53945
JB		 2086 master_priv->sarea_priv->pipeB_x = x;
2087 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2088 } else {
2089 master_priv->sarea_priv->pipeA_x = x;
2090 master_priv->sarea_priv->pipeA_y = y;
79e53945 2091 }
5c3b82e2
CW		 2092
2093 return 0;
79e53945
JB		 2094}
2095
5eddb70b 2096static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2097{
2098 struct drm_device *dev = crtc->dev;
2099 struct drm_i915_private *dev_priv = dev->dev_private;
2100 u32 dpa_ctl;
2101
28c97730 2102 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2103 dpa_ctl = I915_READ(DP_A);
2104 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2105
2106 if (clock < 200000) {
2107 u32 temp;
2108 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2109 /* workaround for 160Mhz:
2110 1) program 0x4600c bits 15:0 = 0x8124
2111 2) program 0x46010 bit 0 = 1
2112 3) program 0x46034 bit 24 = 1
2113 4) program 0x64000 bit 14 = 1
2114 */
2115 temp = I915_READ(0x4600c);
2116 temp &= 0xffff0000;
2117 I915_WRITE(0x4600c, temp | 0x8124);
2118
2119 temp = I915_READ(0x46010);
2120 I915_WRITE(0x46010, temp | 1);
2121
2122 temp = I915_READ(0x46034);
2123 I915_WRITE(0x46034, temp | (1 << 24));
2124 } else {
2125 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2126 }
2127 I915_WRITE(DP_A, dpa_ctl);
2128
5eddb70b 2129 POSTING_READ(DP_A);
32f9d658
ZW		 2130 udelay(500);
2131}
2132
5e84e1a4
ZW		 2133static void intel_fdi_normal_train(struct drm_crtc *crtc)
2134{
2135 struct drm_device *dev = crtc->dev;
2136 struct drm_i915_private *dev_priv = dev->dev_private;
2137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2138 int pipe = intel_crtc->pipe;
2139 u32 reg, temp;
2140
2141 /* enable normal train */
2142 reg = FDI_TX_CTL(pipe);
2143 temp = I915_READ(reg);
61e499bf 2144 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2145 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2146 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2147 } else {
2148 temp &= ~FDI_LINK_TRAIN_NONE;
2149 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2150 }
5e84e1a4
ZW		 2151 I915_WRITE(reg, temp);
2152
2153 reg = FDI_RX_CTL(pipe);
2154 temp = I915_READ(reg);
2155 if (HAS_PCH_CPT(dev)) {
2156 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2157 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2158 } else {
2159 temp &= ~FDI_LINK_TRAIN_NONE;
2160 temp |= FDI_LINK_TRAIN_NONE;
2161 }
2162 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2163
2164 /* wait one idle pattern time */
2165 POSTING_READ(reg);
2166 udelay(1000);
357555c0
JB		 2167
2168 /* IVB wants error correction enabled */
2169 if (IS_IVYBRIDGE(dev))
2170 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2171 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2172}
2173
291427f5
JB		 2174static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2175{
2176 struct drm_i915_private *dev_priv = dev->dev_private;
2177 u32 flags = I915_READ(SOUTH_CHICKEN1);
2178
2179 flags |= FDI_PHASE_SYNC_OVR(pipe);
2180 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2181 flags |= FDI_PHASE_SYNC_EN(pipe);
2182 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2183 POSTING_READ(SOUTH_CHICKEN1);
2184}
2185
8db9d77b
ZW		 2186/* The FDI link training functions for ILK/Ibexpeak. */
2187static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2188{
2189 struct drm_device *dev = crtc->dev;
2190 struct drm_i915_private *dev_priv = dev->dev_private;
2191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2192 int pipe = intel_crtc->pipe;
0fc932b8 2193 int plane = intel_crtc->plane;
5eddb70b 2194 u32 reg, temp, tries;
8db9d77b 2195
0fc932b8
JB		 2196 /* FDI needs bits from pipe & plane first */
2197 assert_pipe_enabled(dev_priv, pipe);
2198 assert_plane_enabled(dev_priv, plane);
2199
e1a44743
AJ		 2200 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2201 for train result */
5eddb70b
CW		 2202 reg = FDI_RX_IMR(pipe);
2203 temp = I915_READ(reg);
e1a44743
AJ		 2204 temp &= ~FDI_RX_SYMBOL_LOCK;
2205 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2206 I915_WRITE(reg, temp);
2207 I915_READ(reg);
e1a44743
AJ		 2208 udelay(150);
2209
8db9d77b 2210 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2211 reg = FDI_TX_CTL(pipe);
2212 temp = I915_READ(reg);
77ffb597
AJ		 2213 temp &= ~(7 << 19);
2214 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2215 temp &= ~FDI_LINK_TRAIN_NONE;
2216 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2217 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2218
5eddb70b
CW		 2219 reg = FDI_RX_CTL(pipe);
2220 temp = I915_READ(reg);
8db9d77b
ZW		 2221 temp &= ~FDI_LINK_TRAIN_NONE;
2222 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2223 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2224
2225 POSTING_READ(reg);
8db9d77b
ZW		 2226 udelay(150);
2227
5b2adf89 2228 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2229 if (HAS_PCH_IBX(dev)) {
2230 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2231 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2232 FDI_RX_PHASE_SYNC_POINTER_EN);
2233 }
5b2adf89 2234
5eddb70b 2235 reg = FDI_RX_IIR(pipe);
e1a44743 2236 for (tries = 0; tries < 5; tries++) {
5eddb70b 2237 temp = I915_READ(reg);
8db9d77b
ZW		 2238 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2239
2240 if ((temp & FDI_RX_BIT_LOCK)) {
2241 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2242 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2243 break;
2244 }
8db9d77b 2245 }
e1a44743 2246 if (tries == 5)
5eddb70b 2247 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2248
2249 /* Train 2 */
5eddb70b
CW		 2250 reg = FDI_TX_CTL(pipe);
2251 temp = I915_READ(reg);
8db9d77b
ZW		 2252 temp &= ~FDI_LINK_TRAIN_NONE;
2253 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2254 I915_WRITE(reg, temp);
8db9d77b 2255
5eddb70b
CW		 2256 reg = FDI_RX_CTL(pipe);
2257 temp = I915_READ(reg);
8db9d77b
ZW		 2258 temp &= ~FDI_LINK_TRAIN_NONE;
2259 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2260 I915_WRITE(reg, temp);
8db9d77b 2261
5eddb70b
CW		 2262 POSTING_READ(reg);
2263 udelay(150);
8db9d77b 2264
5eddb70b 2265 reg = FDI_RX_IIR(pipe);
e1a44743 2266 for (tries = 0; tries < 5; tries++) {
5eddb70b 2267 temp = I915_READ(reg);
8db9d77b
ZW		 2268 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2269
2270 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2271 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2272 DRM_DEBUG_KMS("FDI train 2 done.\n");
2273 break;
2274 }
8db9d77b 2275 }
e1a44743 2276 if (tries == 5)
5eddb70b 2277 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2278
2279 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2280
8db9d77b
ZW		 2281}
2282
0206e353 2283static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2284 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2285 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2286 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2287 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2288};
2289
2290/* The FDI link training functions for SNB/Cougarpoint. */
2291static void gen6_fdi_link_train(struct drm_crtc *crtc)
2292{
2293 struct drm_device *dev = crtc->dev;
2294 struct drm_i915_private *dev_priv = dev->dev_private;
2295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2296 int pipe = intel_crtc->pipe;
fa37d39e 2297 u32 reg, temp, i, retry;
8db9d77b 2298
e1a44743
AJ		 2299 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2300 for train result */
5eddb70b
CW		 2301 reg = FDI_RX_IMR(pipe);
2302 temp = I915_READ(reg);
e1a44743
AJ		 2303 temp &= ~FDI_RX_SYMBOL_LOCK;
2304 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2305 I915_WRITE(reg, temp);
2306
2307 POSTING_READ(reg);
e1a44743
AJ		 2308 udelay(150);
2309
8db9d77b 2310 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2311 reg = FDI_TX_CTL(pipe);
2312 temp = I915_READ(reg);
77ffb597
AJ		 2313 temp &= ~(7 << 19);
2314 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2315 temp &= ~FDI_LINK_TRAIN_NONE;
2316 temp |= FDI_LINK_TRAIN_PATTERN_1;
2317 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2318 /* SNB-B */
2319 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2320 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2321
5eddb70b
CW		 2322 reg = FDI_RX_CTL(pipe);
2323 temp = I915_READ(reg);
8db9d77b
ZW		 2324 if (HAS_PCH_CPT(dev)) {
2325 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2326 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2327 } else {
2328 temp &= ~FDI_LINK_TRAIN_NONE;
2329 temp |= FDI_LINK_TRAIN_PATTERN_1;
2330 }
5eddb70b
CW		 2331 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2332
2333 POSTING_READ(reg);
8db9d77b
ZW		 2334 udelay(150);
2335
291427f5
JB		 2336 if (HAS_PCH_CPT(dev))
2337 cpt_phase_pointer_enable(dev, pipe);
2338
0206e353 2339 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
8db9d77b
ZW		 2342 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2343 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2344 I915_WRITE(reg, temp);
2345
2346 POSTING_READ(reg);
8db9d77b
ZW		 2347 udelay(500);
2348
fa37d39e
SP		 2349 for (retry = 0; retry < 5; retry++) {
2350 reg = FDI_RX_IIR(pipe);
2351 temp = I915_READ(reg);
2352 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2353 if (temp & FDI_RX_BIT_LOCK) {
2354 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2355 DRM_DEBUG_KMS("FDI train 1 done.\n");
2356 break;
2357 }
2358 udelay(50);
8db9d77b 2359 }
fa37d39e
SP		 2360 if (retry < 5)
2361 break;
8db9d77b
ZW		 2362 }
2363 if (i == 4)
5eddb70b 2364 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2365
2366 /* Train 2 */
5eddb70b
CW		 2367 reg = FDI_TX_CTL(pipe);
2368 temp = I915_READ(reg);
8db9d77b
ZW		 2369 temp &= ~FDI_LINK_TRAIN_NONE;
2370 temp |= FDI_LINK_TRAIN_PATTERN_2;
2371 if (IS_GEN6(dev)) {
2372 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2373 /* SNB-B */
2374 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2375 }
5eddb70b 2376 I915_WRITE(reg, temp);
8db9d77b 2377
5eddb70b
CW		 2378 reg = FDI_RX_CTL(pipe);
2379 temp = I915_READ(reg);
8db9d77b
ZW		 2380 if (HAS_PCH_CPT(dev)) {
2381 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2382 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2383 } else {
2384 temp &= ~FDI_LINK_TRAIN_NONE;
2385 temp |= FDI_LINK_TRAIN_PATTERN_2;
2386 }
5eddb70b
CW		 2387 I915_WRITE(reg, temp);
2388
2389 POSTING_READ(reg);
8db9d77b
ZW		 2390 udelay(150);
2391
0206e353 2392 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2393 reg = FDI_TX_CTL(pipe);
2394 temp = I915_READ(reg);
8db9d77b
ZW		 2395 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2396 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2397 I915_WRITE(reg, temp);
2398
2399 POSTING_READ(reg);
8db9d77b
ZW		 2400 udelay(500);
2401
fa37d39e
SP		 2402 for (retry = 0; retry < 5; retry++) {
2403 reg = FDI_RX_IIR(pipe);
2404 temp = I915_READ(reg);
2405 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2406 if (temp & FDI_RX_SYMBOL_LOCK) {
2407 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2408 DRM_DEBUG_KMS("FDI train 2 done.\n");
2409 break;
2410 }
2411 udelay(50);
8db9d77b 2412 }
fa37d39e
SP		 2413 if (retry < 5)
2414 break;
8db9d77b
ZW		 2415 }
2416 if (i == 4)
5eddb70b 2417 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2418
2419 DRM_DEBUG_KMS("FDI train done.\n");
2420}
2421
357555c0
JB		 2422/* Manual link training for Ivy Bridge A0 parts */
2423static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2424{
2425 struct drm_device *dev = crtc->dev;
2426 struct drm_i915_private *dev_priv = dev->dev_private;
2427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2428 int pipe = intel_crtc->pipe;
2429 u32 reg, temp, i;
2430
2431 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2432 for train result */
2433 reg = FDI_RX_IMR(pipe);
2434 temp = I915_READ(reg);
2435 temp &= ~FDI_RX_SYMBOL_LOCK;
2436 temp &= ~FDI_RX_BIT_LOCK;
2437 I915_WRITE(reg, temp);
2438
2439 POSTING_READ(reg);
2440 udelay(150);
2441
2442 /* enable CPU FDI TX and PCH FDI RX */
2443 reg = FDI_TX_CTL(pipe);
2444 temp = I915_READ(reg);
2445 temp &= ~(7 << 19);
2446 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2447 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2448 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2449 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2450 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2451 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2452 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2453
2454 reg = FDI_RX_CTL(pipe);
2455 temp = I915_READ(reg);
2456 temp &= ~FDI_LINK_TRAIN_AUTO;
2457 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2458 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2459 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2460 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2461
2462 POSTING_READ(reg);
2463 udelay(150);
2464
291427f5
JB		 2465 if (HAS_PCH_CPT(dev))
2466 cpt_phase_pointer_enable(dev, pipe);
2467
0206e353 2468 for (i = 0; i < 4; i++) {
357555c0
JB		 2469 reg = FDI_TX_CTL(pipe);
2470 temp = I915_READ(reg);
2471 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2472 temp |= snb_b_fdi_train_param[i];
2473 I915_WRITE(reg, temp);
2474
2475 POSTING_READ(reg);
2476 udelay(500);
2477
2478 reg = FDI_RX_IIR(pipe);
2479 temp = I915_READ(reg);
2480 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2481
2482 if (temp & FDI_RX_BIT_LOCK ||
2483 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2484 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2485 DRM_DEBUG_KMS("FDI train 1 done.\n");
2486 break;
2487 }
2488 }
2489 if (i == 4)
2490 DRM_ERROR("FDI train 1 fail!\n");
2491
2492 /* Train 2 */
2493 reg = FDI_TX_CTL(pipe);
2494 temp = I915_READ(reg);
2495 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2496 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2497 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2498 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2499 I915_WRITE(reg, temp);
2500
2501 reg = FDI_RX_CTL(pipe);
2502 temp = I915_READ(reg);
2503 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2504 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2505 I915_WRITE(reg, temp);
2506
2507 POSTING_READ(reg);
2508 udelay(150);
2509
0206e353 2510 for (i = 0; i < 4; i++) {
357555c0
JB		 2511 reg = FDI_TX_CTL(pipe);
2512 temp = I915_READ(reg);
2513 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2514 temp |= snb_b_fdi_train_param[i];
2515 I915_WRITE(reg, temp);
2516
2517 POSTING_READ(reg);
2518 udelay(500);
2519
2520 reg = FDI_RX_IIR(pipe);
2521 temp = I915_READ(reg);
2522 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2523
2524 if (temp & FDI_RX_SYMBOL_LOCK) {
2525 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2526 DRM_DEBUG_KMS("FDI train 2 done.\n");
2527 break;
2528 }
2529 }
2530 if (i == 4)
2531 DRM_ERROR("FDI train 2 fail!\n");
2532
2533 DRM_DEBUG_KMS("FDI train done.\n");
2534}
2535
2536static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2537{
2538 struct drm_device *dev = crtc->dev;
2539 struct drm_i915_private *dev_priv = dev->dev_private;
2540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2541 int pipe = intel_crtc->pipe;
5eddb70b 2542 u32 reg, temp;
79e53945 2543
c64e311e 2544 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2545 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2546 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2547
c98e9dcf 2548 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2549 reg = FDI_RX_CTL(pipe);
2550 temp = I915_READ(reg);
2551 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2552 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2553 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2554 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2555
2556 POSTING_READ(reg);
c98e9dcf
JB		 2557 udelay(200);
2558
2559 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2560 temp = I915_READ(reg);
2561 I915_WRITE(reg, temp | FDI_PCDCLK);
2562
2563 POSTING_READ(reg);
c98e9dcf
JB		 2564 udelay(200);
2565
bf507ef7
ED		 2566 /* On Haswell, the PLL configuration for ports and pipes is handled
2567 * separately, as part of DDI setup */
2568 if (!IS_HASWELL(dev)) {
2569 /* Enable CPU FDI TX PLL, always on for Ironlake */
2570 reg = FDI_TX_CTL(pipe);
2571 temp = I915_READ(reg);
2572 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2573 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2574
bf507ef7
ED		 2575 POSTING_READ(reg);
2576 udelay(100);
2577 }
6be4a607 2578 }
0e23b99d
JB		 2579}
2580
291427f5
JB		 2581static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2582{
2583 struct drm_i915_private *dev_priv = dev->dev_private;
2584 u32 flags = I915_READ(SOUTH_CHICKEN1);
2585
2586 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2587 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2588 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2589 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2590 POSTING_READ(SOUTH_CHICKEN1);
2591}
0fc932b8
JB		 2592static void ironlake_fdi_disable(struct drm_crtc *crtc)
2593{
2594 struct drm_device *dev = crtc->dev;
2595 struct drm_i915_private *dev_priv = dev->dev_private;
2596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2597 int pipe = intel_crtc->pipe;
2598 u32 reg, temp;
2599
2600 /* disable CPU FDI tx and PCH FDI rx */
2601 reg = FDI_TX_CTL(pipe);
2602 temp = I915_READ(reg);
2603 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2604 POSTING_READ(reg);
2605
2606 reg = FDI_RX_CTL(pipe);
2607 temp = I915_READ(reg);
2608 temp &= ~(0x7 << 16);
2609 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2610 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2611
2612 POSTING_READ(reg);
2613 udelay(100);
2614
2615 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2616 if (HAS_PCH_IBX(dev)) {
2617 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2618 I915_WRITE(FDI_RX_CHICKEN(pipe),
2619 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2620 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2621 } else if (HAS_PCH_CPT(dev)) {
2622 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2623 }
0fc932b8
JB		 2624
2625 /* still set train pattern 1 */
2626 reg = FDI_TX_CTL(pipe);
2627 temp = I915_READ(reg);
2628 temp &= ~FDI_LINK_TRAIN_NONE;
2629 temp |= FDI_LINK_TRAIN_PATTERN_1;
2630 I915_WRITE(reg, temp);
2631
2632 reg = FDI_RX_CTL(pipe);
2633 temp = I915_READ(reg);
2634 if (HAS_PCH_CPT(dev)) {
2635 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2636 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2637 } else {
2638 temp &= ~FDI_LINK_TRAIN_NONE;
2639 temp |= FDI_LINK_TRAIN_PATTERN_1;
2640 }
2641 /* BPC in FDI rx is consistent with that in PIPECONF */
2642 temp &= ~(0x07 << 16);
2643 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2644 I915_WRITE(reg, temp);
2645
2646 POSTING_READ(reg);
2647 udelay(100);
2648}
2649
e6c3a2a6
CW		 2650static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2651{
0f91128d 2652 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2653
2654 if (crtc->fb == NULL)
2655 return;
2656
0f91128d
CW		 2657 mutex_lock(&dev->struct_mutex);
2658 intel_finish_fb(crtc->fb);
2659 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2660}
2661
040484af
JB		 2662static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2663{
2664 struct drm_device *dev = crtc->dev;
2665 struct drm_mode_config *mode_config = &dev->mode_config;
2666 struct intel_encoder *encoder;
2667
2668 /*
2669 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2670 * must be driven by its own crtc; no sharing is possible.
2671 */
2672 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2673 if (encoder->base.crtc != crtc)
2674 continue;
2675
6ee8bab0
ED		 2676 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2677 * CPU handles all others */
2678 if (IS_HASWELL(dev)) {
2679 /* It is still unclear how this will work on PPT, so throw up a warning */
2680 WARN_ON(!HAS_PCH_LPT(dev));
2681
2682 if (encoder->type == DRM_MODE_ENCODER_DAC) {
2683 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2684 return true;
2685 } else {
2686 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2687 encoder->type);
2688 return false;
2689 }
2690 }
2691
040484af
JB		 2692 switch (encoder->type) {
2693 case INTEL_OUTPUT_EDP:
2694 if (!intel_encoder_is_pch_edp(&encoder->base))
2695 return false;
2696 continue;
2697 }
2698 }
2699
2700 return true;
2701}
2702
e615efe4
ED		 2703/* Program iCLKIP clock to the desired frequency */
2704static void lpt_program_iclkip(struct drm_crtc *crtc)
2705{
2706 struct drm_device *dev = crtc->dev;
2707 struct drm_i915_private *dev_priv = dev->dev_private;
2708 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2709 u32 temp;
2710
2711 /* It is necessary to ungate the pixclk gate prior to programming
2712 * the divisors, and gate it back when it is done.
2713 */
2714 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2715
2716 /* Disable SSCCTL */
2717 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2718 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2719 SBI_SSCCTL_DISABLE);
2720
2721 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2722 if (crtc->mode.clock == 20000) {
2723 auxdiv = 1;
2724 divsel = 0x41;
2725 phaseinc = 0x20;
2726 } else {
2727 /* The iCLK virtual clock root frequency is in MHz,
2728 * but the crtc->mode.clock in in KHz. To get the divisors,
2729 * it is necessary to divide one by another, so we
2730 * convert the virtual clock precision to KHz here for higher
2731 * precision.
2732 */
2733 u32 iclk_virtual_root_freq = 172800 * 1000;
2734 u32 iclk_pi_range = 64;
2735 u32 desired_divisor, msb_divisor_value, pi_value;
2736
2737 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2738 msb_divisor_value = desired_divisor / iclk_pi_range;
2739 pi_value = desired_divisor % iclk_pi_range;
2740
2741 auxdiv = 0;
2742 divsel = msb_divisor_value - 2;
2743 phaseinc = pi_value;
2744 }
2745
2746 /* This should not happen with any sane values */
2747 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2748 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2749 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2750 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2751
2752 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2753 crtc->mode.clock,
2754 auxdiv,
2755 divsel,
2756 phasedir,
2757 phaseinc);
2758
2759 /* Program SSCDIVINTPHASE6 */
2760 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2761 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2762 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2763 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2764 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2765 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2766 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2767
2768 intel_sbi_write(dev_priv,
2769 SBI_SSCDIVINTPHASE6,
2770 temp);
2771
2772 /* Program SSCAUXDIV */
2773 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2774 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2775 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2776 intel_sbi_write(dev_priv,
2777 SBI_SSCAUXDIV6,
2778 temp);
2779
2780
2781 /* Enable modulator and associated divider */
2782 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2783 temp &= ~SBI_SSCCTL_DISABLE;
2784 intel_sbi_write(dev_priv,
2785 SBI_SSCCTL6,
2786 temp);
2787
2788 /* Wait for initialization time */
2789 udelay(24);
2790
2791 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2792}
2793
f67a559d
JB		 2794/*
2795 * Enable PCH resources required for PCH ports:
2796 * - PCH PLLs
2797 * - FDI training & RX/TX
2798 * - update transcoder timings
2799 * - DP transcoding bits
2800 * - transcoder
2801 */
2802static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2803{
2804 struct drm_device *dev = crtc->dev;
2805 struct drm_i915_private *dev_priv = dev->dev_private;
2806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2807 int pipe = intel_crtc->pipe;
ee7b9f93 2808 u32 reg, temp;
2c07245f 2809
e7e164db
CW		 2810 assert_transcoder_disabled(dev_priv, pipe);
2811
c98e9dcf 2812 /* For PCH output, training FDI link */
674cf967 2813 dev_priv->display.fdi_link_train(crtc);
2c07245f 2814
6f13b7b5
CW		 2815 intel_enable_pch_pll(intel_crtc);
2816
e615efe4
ED		 2817 if (HAS_PCH_LPT(dev)) {
2818 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2819 lpt_program_iclkip(crtc);
2820 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 2821 u32 sel;
4b645f14 2822
c98e9dcf 2823 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2824 switch (pipe) {
2825 default:
2826 case 0:
2827 temp |= TRANSA_DPLL_ENABLE;
2828 sel = TRANSA_DPLLB_SEL;
2829 break;
2830 case 1:
2831 temp |= TRANSB_DPLL_ENABLE;
2832 sel = TRANSB_DPLLB_SEL;
2833 break;
2834 case 2:
2835 temp |= TRANSC_DPLL_ENABLE;
2836 sel = TRANSC_DPLLB_SEL;
2837 break;
d64311ab 2838 }
ee7b9f93
JB		 2839 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2840 temp |= sel;
2841 else
2842 temp &= ~sel;
c98e9dcf 2843 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2844 }
5eddb70b 2845
d9b6cb56
JB		 2846 /* set transcoder timing, panel must allow it */
2847 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2848 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2849 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2850 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2851
5eddb70b
CW		 2852 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2853 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2854 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 2855 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 2856
f57e1e3a
ED		 2857 if (!IS_HASWELL(dev))
2858 intel_fdi_normal_train(crtc);
5e84e1a4 2859
c98e9dcf
JB		 2860 /* For PCH DP, enable TRANS_DP_CTL */
2861 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2862 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2863 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 2864 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2865 reg = TRANS_DP_CTL(pipe);
2866 temp = I915_READ(reg);
2867 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2868 TRANS_DP_SYNC_MASK |
2869 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2870 temp |= (TRANS_DP_OUTPUT_ENABLE |
2871 TRANS_DP_ENH_FRAMING);
9325c9f0 2872 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2873
2874 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2875 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2876 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2877 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2878
2879 switch (intel_trans_dp_port_sel(crtc)) {
2880 case PCH_DP_B:
5eddb70b 2881 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2882 break;
2883 case PCH_DP_C:
5eddb70b 2884 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2885 break;
2886 case PCH_DP_D:
5eddb70b 2887 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2888 break;
2889 default:
2890 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2891 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2892 break;
32f9d658 2893 }
2c07245f 2894
5eddb70b 2895 I915_WRITE(reg, temp);
6be4a607 2896 }
b52eb4dc 2897
040484af 2898 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2899}
2900
ee7b9f93
JB		 2901static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2902{
2903 struct intel_pch_pll *pll = intel_crtc->pch_pll;
2904
2905 if (pll == NULL)
2906 return;
2907
2908 if (pll->refcount == 0) {
2909 WARN(1, "bad PCH PLL refcount\n");
2910 return;
2911 }
2912
2913 --pll->refcount;
2914 intel_crtc->pch_pll = NULL;
2915}
2916
2917static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2918{
2919 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2920 struct intel_pch_pll *pll;
2921 int i;
2922
2923 pll = intel_crtc->pch_pll;
2924 if (pll) {
2925 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2926 intel_crtc->base.base.id, pll->pll_reg);
2927 goto prepare;
2928 }
2929
98b6bd99
DV		 2930 if (HAS_PCH_IBX(dev_priv->dev)) {
2931 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
2932 i = intel_crtc->pipe;
2933 pll = &dev_priv->pch_plls[i];
2934
2935 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
2936 intel_crtc->base.base.id, pll->pll_reg);
2937
2938 goto found;
2939 }
2940
ee7b9f93
JB		 2941 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2942 pll = &dev_priv->pch_plls[i];
2943
2944 /* Only want to check enabled timings first */
2945 if (pll->refcount == 0)
2946 continue;
2947
2948 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2949 fp == I915_READ(pll->fp0_reg)) {
2950 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2951 intel_crtc->base.base.id,
2952 pll->pll_reg, pll->refcount, pll->active);
2953
2954 goto found;
2955 }
2956 }
2957
2958 /* Ok no matching timings, maybe there's a free one? */
2959 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2960 pll = &dev_priv->pch_plls[i];
2961 if (pll->refcount == 0) {
2962 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2963 intel_crtc->base.base.id, pll->pll_reg);
2964 goto found;
2965 }
2966 }
2967
2968 return NULL;
2969
2970found:
2971 intel_crtc->pch_pll = pll;
2972 pll->refcount++;
2973 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2974prepare: /* separate function? */
2975 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 2976
e04c7350
CW		 2977 /* Wait for the clocks to stabilize before rewriting the regs */
2978 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 2979 POSTING_READ(pll->pll_reg);
2980 udelay(150);
e04c7350
CW		 2981
2982 I915_WRITE(pll->fp0_reg, fp);
2983 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 2984 pll->on = false;
2985 return pll;
2986}
2987
d4270e57
JB		 2988void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2989{
2990 struct drm_i915_private *dev_priv = dev->dev_private;
2991 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2992 u32 temp;
2993
2994 temp = I915_READ(dslreg);
2995 udelay(500);
2996 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2997 /* Without this, mode sets may fail silently on FDI */
2998 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2999 udelay(250);
3000 I915_WRITE(tc2reg, 0);
3001 if (wait_for(I915_READ(dslreg) != temp, 5))
3002 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3003 }
3004}
3005
f67a559d
JB		 3006static void ironlake_crtc_enable(struct drm_crtc *crtc)
3007{
3008 struct drm_device *dev = crtc->dev;
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3011 int pipe = intel_crtc->pipe;
3012 int plane = intel_crtc->plane;
3013 u32 temp;
3014 bool is_pch_port;
3015
3016 if (intel_crtc->active)
3017 return;
3018
3019 intel_crtc->active = true;
3020 intel_update_watermarks(dev);
3021
3022 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3023 temp = I915_READ(PCH_LVDS);
3024 if ((temp & LVDS_PORT_EN) == 0)
3025 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3026 }
3027
3028 is_pch_port = intel_crtc_driving_pch(crtc);
3029
3030 if (is_pch_port)
357555c0 3031 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 3032 else
3033 ironlake_fdi_disable(crtc);
3034
3035 /* Enable panel fitting for LVDS */
3036 if (dev_priv->pch_pf_size &&
3037 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3038 /* Force use of hard-coded filter coefficients
3039 * as some pre-programmed values are broken,
3040 * e.g. x201.
3041 */
9db4a9c7
JB		 3042 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3043 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3044 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3045 }
3046
9c54c0dd
JB		 3047 /*
3048 * On ILK+ LUT must be loaded before the pipe is running but with
3049 * clocks enabled
3050 */
3051 intel_crtc_load_lut(crtc);
3052
f67a559d
JB		 3053 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3054 intel_enable_plane(dev_priv, plane, pipe);
3055
3056 if (is_pch_port)
3057 ironlake_pch_enable(crtc);
c98e9dcf 3058
d1ebd816 3059 mutex_lock(&dev->struct_mutex);
bed4a673 3060 intel_update_fbc(dev);
d1ebd816
BW		 3061 mutex_unlock(&dev->struct_mutex);
3062
6b383a7f 3063 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3064}
3065
3066static void ironlake_crtc_disable(struct drm_crtc *crtc)
3067{
3068 struct drm_device *dev = crtc->dev;
3069 struct drm_i915_private *dev_priv = dev->dev_private;
3070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3071 int pipe = intel_crtc->pipe;
3072 int plane = intel_crtc->plane;
5eddb70b 3073 u32 reg, temp;
b52eb4dc 3074
f7abfe8b
CW		 3075 if (!intel_crtc->active)
3076 return;
3077
e6c3a2a6 3078 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3079 drm_vblank_off(dev, pipe);
6b383a7f 3080 intel_crtc_update_cursor(crtc, false);
5eddb70b 3081
b24e7179 3082 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3083
973d04f9
CW		 3084 if (dev_priv->cfb_plane == plane)
3085 intel_disable_fbc(dev);
2c07245f 3086
b24e7179 3087 intel_disable_pipe(dev_priv, pipe);
32f9d658 3088
6be4a607 3089 /* Disable PF */
9db4a9c7
JB		 3090 I915_WRITE(PF_CTL(pipe), 0);
3091 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3092
0fc932b8 3093 ironlake_fdi_disable(crtc);
2c07245f 3094
47a05eca
JB		 3095 /* This is a horrible layering violation; we should be doing this in
3096 * the connector/encoder ->prepare instead, but we don't always have
3097 * enough information there about the config to know whether it will
3098 * actually be necessary or just cause undesired flicker.
3099 */
3100 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3101
040484af 3102 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3103
6be4a607
JB		 3104 if (HAS_PCH_CPT(dev)) {
3105 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3106 reg = TRANS_DP_CTL(pipe);
3107 temp = I915_READ(reg);
3108 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3109 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3110 I915_WRITE(reg, temp);
6be4a607
JB		 3111
3112 /* disable DPLL_SEL */
3113 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3114 switch (pipe) {
3115 case 0:
d64311ab 3116 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3117 break;
3118 case 1:
6be4a607 3119 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3120 break;
3121 case 2:
4b645f14 3122 /* C shares PLL A or B */
d64311ab 3123 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3124 break;
3125 default:
3126 BUG(); /* wtf */
3127 }
6be4a607 3128 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3129 }
e3421a18 3130
6be4a607 3131 /* disable PCH DPLL */
ee7b9f93 3132 intel_disable_pch_pll(intel_crtc);
8db9d77b 3133
6be4a607 3134 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3135 reg = FDI_RX_CTL(pipe);
3136 temp = I915_READ(reg);
3137 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3138
6be4a607 3139 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3140 reg = FDI_TX_CTL(pipe);
3141 temp = I915_READ(reg);
3142 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3143
3144 POSTING_READ(reg);
6be4a607 3145 udelay(100);
8db9d77b 3146
5eddb70b
CW		 3147 reg = FDI_RX_CTL(pipe);
3148 temp = I915_READ(reg);
3149 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3150
6be4a607 3151 /* Wait for the clocks to turn off. */
5eddb70b 3152 POSTING_READ(reg);
6be4a607 3153 udelay(100);
6b383a7f 3154
f7abfe8b 3155 intel_crtc->active = false;
6b383a7f 3156 intel_update_watermarks(dev);
d1ebd816
BW		 3157
3158 mutex_lock(&dev->struct_mutex);
6b383a7f 3159 intel_update_fbc(dev);
d1ebd816 3160 mutex_unlock(&dev->struct_mutex);
6be4a607 3161}
1b3c7a47 3162
6be4a607
JB		 3163static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3164{
3165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3166 int pipe = intel_crtc->pipe;
3167 int plane = intel_crtc->plane;
8db9d77b 3168
6be4a607
JB		 3169 /* XXX: When our outputs are all unaware of DPMS modes other than off
3170 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3171 */
3172 switch (mode) {
3173 case DRM_MODE_DPMS_ON:
3174 case DRM_MODE_DPMS_STANDBY:
3175 case DRM_MODE_DPMS_SUSPEND:
3176 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3177 ironlake_crtc_enable(crtc);
3178 break;
1b3c7a47 3179
6be4a607
JB		 3180 case DRM_MODE_DPMS_OFF:
3181 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3182 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3183 break;
3184 }
3185}
3186
ee7b9f93
JB		 3187static void ironlake_crtc_off(struct drm_crtc *crtc)
3188{
3189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3190 intel_put_pch_pll(intel_crtc);
3191}
3192
02e792fb
DV		 3193static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3194{
02e792fb 3195 if (!enable && intel_crtc->overlay) {
23f09ce3 3196 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3197 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3198
23f09ce3 3199 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3200 dev_priv->mm.interruptible = false;
3201 (void) intel_overlay_switch_off(intel_crtc->overlay);
3202 dev_priv->mm.interruptible = true;
23f09ce3 3203 mutex_unlock(&dev->struct_mutex);
02e792fb 3204 }
02e792fb 3205
5dcdbcb0
CW		 3206 /* Let userspace switch the overlay on again. In most cases userspace
3207 * has to recompute where to put it anyway.
3208 */
02e792fb
DV		 3209}
3210
0b8765c6 3211static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3212{
3213 struct drm_device *dev = crtc->dev;
79e53945
JB		 3214 struct drm_i915_private *dev_priv = dev->dev_private;
3215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3216 int pipe = intel_crtc->pipe;
80824003 3217 int plane = intel_crtc->plane;
79e53945 3218
f7abfe8b
CW		 3219 if (intel_crtc->active)
3220 return;
3221
3222 intel_crtc->active = true;
6b383a7f
CW		 3223 intel_update_watermarks(dev);
3224
63d7bbe9 3225 intel_enable_pll(dev_priv, pipe);
040484af 3226 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3227 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3228
0b8765c6 3229 intel_crtc_load_lut(crtc);
bed4a673 3230 intel_update_fbc(dev);
79e53945 3231
0b8765c6
JB		 3232 /* Give the overlay scaler a chance to enable if it's on this pipe */
3233 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3234 intel_crtc_update_cursor(crtc, true);
0b8765c6 3235}
79e53945 3236
0b8765c6
JB		 3237static void i9xx_crtc_disable(struct drm_crtc *crtc)
3238{
3239 struct drm_device *dev = crtc->dev;
3240 struct drm_i915_private *dev_priv = dev->dev_private;
3241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3242 int pipe = intel_crtc->pipe;
3243 int plane = intel_crtc->plane;
b690e96c 3244
f7abfe8b
CW		 3245 if (!intel_crtc->active)
3246 return;
3247
0b8765c6 3248 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3249 intel_crtc_wait_for_pending_flips(crtc);
3250 drm_vblank_off(dev, pipe);
0b8765c6 3251 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3252 intel_crtc_update_cursor(crtc, false);
0b8765c6 3253
973d04f9
CW		 3254 if (dev_priv->cfb_plane == plane)
3255 intel_disable_fbc(dev);
79e53945 3256
b24e7179 3257 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3258 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3259 intel_disable_pll(dev_priv, pipe);
0b8765c6 3260
f7abfe8b 3261 intel_crtc->active = false;
6b383a7f
CW		 3262 intel_update_fbc(dev);
3263 intel_update_watermarks(dev);
0b8765c6
JB		 3264}
3265
3266static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3267{
3268 /* XXX: When our outputs are all unaware of DPMS modes other than off
3269 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3270 */
3271 switch (mode) {
3272 case DRM_MODE_DPMS_ON:
3273 case DRM_MODE_DPMS_STANDBY:
3274 case DRM_MODE_DPMS_SUSPEND:
3275 i9xx_crtc_enable(crtc);
3276 break;
3277 case DRM_MODE_DPMS_OFF:
3278 i9xx_crtc_disable(crtc);
79e53945
JB		 3279 break;
3280 }
2c07245f
ZW		 3281}
3282
ee7b9f93
JB		 3283static void i9xx_crtc_off(struct drm_crtc *crtc)
3284{
3285}
3286
2c07245f
ZW		 3287/**
3288 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3289 */
3290static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3291{
3292 struct drm_device *dev = crtc->dev;
e70236a8 3293 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3294 struct drm_i915_master_private *master_priv;
3295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3296 int pipe = intel_crtc->pipe;
3297 bool enabled;
3298
032d2a0d
CW		 3299 if (intel_crtc->dpms_mode == mode)
3300 return;
3301
65655d4a 3302 intel_crtc->dpms_mode = mode;
debcaddc 3303
e70236a8 3304 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3305
3306 if (!dev->primary->master)
3307 return;
3308
3309 master_priv = dev->primary->master->driver_priv;
3310 if (!master_priv->sarea_priv)
3311 return;
3312
3313 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3314
3315 switch (pipe) {
3316 case 0:
3317 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3318 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3319 break;
3320 case 1:
3321 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3322 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3323 break;
3324 default:
9db4a9c7 3325 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3326 break;
3327 }
79e53945
JB		 3328}
3329
cdd59983
CW		 3330static void intel_crtc_disable(struct drm_crtc *crtc)
3331{
3332 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3333 struct drm_device *dev = crtc->dev;
ee7b9f93 3334 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983
CW		 3335
3336 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
ee7b9f93
JB		 3337 dev_priv->display.off(crtc);
3338
931872fc
CW		 3339 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3340 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3341
3342 if (crtc->fb) {
3343 mutex_lock(&dev->struct_mutex);
1690e1eb 3344 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3345 mutex_unlock(&dev->struct_mutex);
3346 }
3347}
3348
7e7d76c3
JB		 3349/* Prepare for a mode set.
3350 *
3351 * Note we could be a lot smarter here. We need to figure out which outputs
3352 * will be enabled, which disabled (in short, how the config will changes)
3353 * and perform the minimum necessary steps to accomplish that, e.g. updating
3354 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3355 * panel fitting is in the proper state, etc.
3356 */
3357static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3358{
7e7d76c3 3359 i9xx_crtc_disable(crtc);
79e53945
JB		 3360}
3361
7e7d76c3 3362static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3363{
7e7d76c3 3364 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3365}
3366
3367static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3368{
7e7d76c3 3369 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3370}
3371
3372static void ironlake_crtc_commit(struct drm_crtc *crtc)
3373{
7e7d76c3 3374 ironlake_crtc_enable(crtc);
79e53945
JB		 3375}
3376
0206e353 3377void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3378{
3379 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3380 /* lvds has its own version of prepare see intel_lvds_prepare */
3381 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3382}
3383
0206e353 3384void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3385{
3386 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57 3387 struct drm_device *dev = encoder->dev;
d47d7cb8 3388 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
d4270e57 3389
79e53945
JB		 3390 /* lvds has its own version of commit see intel_lvds_commit */
3391 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3392
3393 if (HAS_PCH_CPT(dev))
3394 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3395}
3396
ea5b213a
CW		 3397void intel_encoder_destroy(struct drm_encoder *encoder)
3398{
4ef69c7a 3399 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3400
ea5b213a
CW		 3401 drm_encoder_cleanup(encoder);
3402 kfree(intel_encoder);
3403}
3404
79e53945
JB		 3405static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3406 struct drm_display_mode *mode,
3407 struct drm_display_mode *adjusted_mode)
3408{
2c07245f 3409 struct drm_device *dev = crtc->dev;
89749350 3410
bad720ff 3411 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3412 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3413 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3414 return false;
2c07245f 3415 }
89749350 3416
f9bef081
DV		 3417 /* All interlaced capable intel hw wants timings in frames. Note though
3418 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3419 * timings, so we need to be careful not to clobber these.*/
3420 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3421 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3422
79e53945
JB		 3423 return true;
3424}
3425
25eb05fc
JB		 3426static int valleyview_get_display_clock_speed(struct drm_device *dev)
3427{
3428 return 400000; /* FIXME */
3429}
3430
e70236a8
JB		 3431static int i945_get_display_clock_speed(struct drm_device *dev)
3432{
3433 return 400000;
3434}
79e53945 3435
e70236a8 3436static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3437{
e70236a8
JB		 3438 return 333000;
3439}
79e53945 3440
e70236a8
JB		 3441static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3442{
3443 return 200000;
3444}
79e53945 3445
e70236a8
JB		 3446static int i915gm_get_display_clock_speed(struct drm_device *dev)
3447{
3448 u16 gcfgc = 0;
79e53945 3449
e70236a8
JB		 3450 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3451
3452 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3453 return 133000;
3454 else {
3455 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3456 case GC_DISPLAY_CLOCK_333_MHZ:
3457 return 333000;
3458 default:
3459 case GC_DISPLAY_CLOCK_190_200_MHZ:
3460 return 190000;
79e53945 3461 }
e70236a8
JB		 3462 }
3463}
3464
3465static int i865_get_display_clock_speed(struct drm_device *dev)
3466{
3467 return 266000;
3468}
3469
3470static int i855_get_display_clock_speed(struct drm_device *dev)
3471{
3472 u16 hpllcc = 0;
3473 /* Assume that the hardware is in the high speed state. This
3474 * should be the default.
3475 */
3476 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3477 case GC_CLOCK_133_200:
3478 case GC_CLOCK_100_200:
3479 return 200000;
3480 case GC_CLOCK_166_250:
3481 return 250000;
3482 case GC_CLOCK_100_133:
79e53945 3483 return 133000;
e70236a8 3484 }
79e53945 3485
e70236a8
JB		 3486 /* Shouldn't happen */
3487 return 0;
3488}
79e53945 3489
e70236a8
JB		 3490static int i830_get_display_clock_speed(struct drm_device *dev)
3491{
3492 return 133000;
79e53945
JB		 3493}
3494
2c07245f
ZW		 3495struct fdi_m_n {
3496 u32 tu;
3497 u32 gmch_m;
3498 u32 gmch_n;
3499 u32 link_m;
3500 u32 link_n;
3501};
3502
3503static void
3504fdi_reduce_ratio(u32 *num, u32 *den)
3505{
3506 while (*num > 0xffffff || *den > 0xffffff) {
3507 *num >>= 1;
3508 *den >>= 1;
3509 }
3510}
3511
2c07245f 3512static void
f2b115e6
AJ		 3513ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3514 int link_clock, struct fdi_m_n *m_n)
2c07245f 3515{
2c07245f
ZW		 3516 m_n->tu = 64; /* default size */
3517
22ed1113
CW		 3518 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3519 m_n->gmch_m = bits_per_pixel * pixel_clock;
3520 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3521 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3522
22ed1113
CW		 3523 m_n->link_m = pixel_clock;
3524 m_n->link_n = link_clock;
2c07245f
ZW		 3525 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3526}
3527
a7615030
CW		 3528static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3529{
72bbe58c
KP		 3530 if (i915_panel_use_ssc >= 0)
3531 return i915_panel_use_ssc != 0;
3532 return dev_priv->lvds_use_ssc
435793df 3533 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3534}
3535
5a354204
JB		 3536/**
3537 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3538 * @crtc: CRTC structure
3b5c78a3 3539 * @mode: requested mode
5a354204
JB		 3540 *
3541 * A pipe may be connected to one or more outputs. Based on the depth of the
3542 * attached framebuffer, choose a good color depth to use on the pipe.
3543 *
3544 * If possible, match the pipe depth to the fb depth. In some cases, this
3545 * isn't ideal, because the connected output supports a lesser or restricted
3546 * set of depths. Resolve that here:
3547 * LVDS typically supports only 6bpc, so clamp down in that case
3548 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3549 * Displays may support a restricted set as well, check EDID and clamp as
3550 * appropriate.
3b5c78a3 3551 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3552 *
3553 * RETURNS:
3554 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3555 * true if they don't match).
3556 */
3557static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 3558 unsigned int *pipe_bpp,
3559 struct drm_display_mode *mode)
5a354204
JB		 3560{
3561 struct drm_device *dev = crtc->dev;
3562 struct drm_i915_private *dev_priv = dev->dev_private;
3563 struct drm_encoder *encoder;
3564 struct drm_connector *connector;
3565 unsigned int display_bpc = UINT_MAX, bpc;
3566
3567 /* Walk the encoders & connectors on this crtc, get min bpc */
3568 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3569 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3570
3571 if (encoder->crtc != crtc)
3572 continue;
3573
3574 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3575 unsigned int lvds_bpc;
3576
3577 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3578 LVDS_A3_POWER_UP)
3579 lvds_bpc = 8;
3580 else
3581 lvds_bpc = 6;
3582
3583 if (lvds_bpc < display_bpc) {
82820490 3584 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3585 display_bpc = lvds_bpc;
3586 }
3587 continue;
3588 }
3589
3590 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3591 /* Use VBT settings if we have an eDP panel */
3592 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3593
3594 if (edp_bpc < display_bpc) {
82820490 3595 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 3596 display_bpc = edp_bpc;
3597 }
3598 continue;
3599 }
3600
3601 /* Not one of the known troublemakers, check the EDID */
3602 list_for_each_entry(connector, &dev->mode_config.connector_list,
3603 head) {
3604 if (connector->encoder != encoder)
3605 continue;
3606
62ac41a6
JB		 3607 /* Don't use an invalid EDID bpc value */
3608 if (connector->display_info.bpc &&
3609 connector->display_info.bpc < display_bpc) {
82820490 3610 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3611 display_bpc = connector->display_info.bpc;
3612 }
3613 }
3614
3615 /*
3616 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3617 * through, clamp it down. (Note: >12bpc will be caught below.)
3618 */
3619 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3620 if (display_bpc > 8 && display_bpc < 12) {
82820490 3621 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3622 display_bpc = 12;
3623 } else {
82820490 3624 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3625 display_bpc = 8;
3626 }
3627 }
3628 }
3629
3b5c78a3
AJ		 3630 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3631 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3632 display_bpc = 6;
3633 }
3634
5a354204
JB		 3635 /*
3636 * We could just drive the pipe at the highest bpc all the time and
3637 * enable dithering as needed, but that costs bandwidth. So choose
3638 * the minimum value that expresses the full color range of the fb but
3639 * also stays within the max display bpc discovered above.
3640 */
3641
3642 switch (crtc->fb->depth) {
3643 case 8:
3644 bpc = 8; /* since we go through a colormap */
3645 break;
3646 case 15:
3647 case 16:
3648 bpc = 6; /* min is 18bpp */
3649 break;
3650 case 24:
578393cd 3651 bpc = 8;
5a354204
JB		 3652 break;
3653 case 30:
578393cd 3654 bpc = 10;
5a354204
JB		 3655 break;
3656 case 48:
578393cd 3657 bpc = 12;
5a354204
JB		 3658 break;
3659 default:
3660 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3661 bpc = min((unsigned int)8, display_bpc);
3662 break;
3663 }
3664
578393cd
KP		 3665 display_bpc = min(display_bpc, bpc);
3666
82820490
AJ		 3667 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3668 bpc, display_bpc);
5a354204 3669
578393cd 3670 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3671
3672 return display_bpc != bpc;
3673}
3674
c65d77d8
JB		 3675static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3676{
3677 struct drm_device *dev = crtc->dev;
3678 struct drm_i915_private *dev_priv = dev->dev_private;
3679 int refclk;
3680
3681 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3682 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3683 refclk = dev_priv->lvds_ssc_freq * 1000;
3684 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3685 refclk / 1000);
3686 } else if (!IS_GEN2(dev)) {
3687 refclk = 96000;
3688 } else {
3689 refclk = 48000;
3690 }
3691
3692 return refclk;
3693}
3694
3695static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3696 intel_clock_t *clock)
3697{
3698 /* SDVO TV has fixed PLL values depend on its clock range,
3699 this mirrors vbios setting. */
3700 if (adjusted_mode->clock >= 100000
3701 && adjusted_mode->clock < 140500) {
3702 clock->p1 = 2;
3703 clock->p2 = 10;
3704 clock->n = 3;
3705 clock->m1 = 16;
3706 clock->m2 = 8;
3707 } else if (adjusted_mode->clock >= 140500
3708 && adjusted_mode->clock <= 200000) {
3709 clock->p1 = 1;
3710 clock->p2 = 10;
3711 clock->n = 6;
3712 clock->m1 = 12;
3713 clock->m2 = 8;
3714 }
3715}
3716
a7516a05
JB		 3717static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3718 intel_clock_t *clock,
3719 intel_clock_t *reduced_clock)
3720{
3721 struct drm_device *dev = crtc->dev;
3722 struct drm_i915_private *dev_priv = dev->dev_private;
3723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3724 int pipe = intel_crtc->pipe;
3725 u32 fp, fp2 = 0;
3726
3727 if (IS_PINEVIEW(dev)) {
3728 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3729 if (reduced_clock)
3730 fp2 = (1 << reduced_clock->n) << 16 |
3731 reduced_clock->m1 << 8 | reduced_clock->m2;
3732 } else {
3733 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3734 if (reduced_clock)
3735 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3736 reduced_clock->m2;
3737 }
3738
3739 I915_WRITE(FP0(pipe), fp);
3740
3741 intel_crtc->lowfreq_avail = false;
3742 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3743 reduced_clock && i915_powersave) {
3744 I915_WRITE(FP1(pipe), fp2);
3745 intel_crtc->lowfreq_avail = true;
3746 } else {
3747 I915_WRITE(FP1(pipe), fp);
3748 }
3749}
3750
93e537a1
DV		 3751static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3752 struct drm_display_mode *adjusted_mode)
3753{
3754 struct drm_device *dev = crtc->dev;
3755 struct drm_i915_private *dev_priv = dev->dev_private;
3756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3757 int pipe = intel_crtc->pipe;
284d5df5 3758 u32 temp;
93e537a1
DV		 3759
3760 temp = I915_READ(LVDS);
3761 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3762 if (pipe == 1) {
3763 temp |= LVDS_PIPEB_SELECT;
3764 } else {
3765 temp &= ~LVDS_PIPEB_SELECT;
3766 }
3767 /* set the corresponsding LVDS_BORDER bit */
3768 temp |= dev_priv->lvds_border_bits;
3769 /* Set the B0-B3 data pairs corresponding to whether we're going to
3770 * set the DPLLs for dual-channel mode or not.
3771 */
3772 if (clock->p2 == 7)
3773 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3774 else
3775 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3776
3777 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3778 * appropriately here, but we need to look more thoroughly into how
3779 * panels behave in the two modes.
3780 */
3781 /* set the dithering flag on LVDS as needed */
3782 if (INTEL_INFO(dev)->gen >= 4) {
3783 if (dev_priv->lvds_dither)
3784 temp |= LVDS_ENABLE_DITHER;
3785 else
3786 temp &= ~LVDS_ENABLE_DITHER;
3787 }
284d5df5 3788 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 3789 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 3790 temp |= LVDS_HSYNC_POLARITY;
93e537a1 3791 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 3792 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 3793 I915_WRITE(LVDS, temp);
3794}
3795
eb1cbe48
DV		 3796static void i9xx_update_pll(struct drm_crtc *crtc,
3797 struct drm_display_mode *mode,
3798 struct drm_display_mode *adjusted_mode,
3799 intel_clock_t *clock, intel_clock_t *reduced_clock,
3800 int num_connectors)
3801{
3802 struct drm_device *dev = crtc->dev;
3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3805 int pipe = intel_crtc->pipe;
3806 u32 dpll;
3807 bool is_sdvo;
3808
3809 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3810 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3811
3812 dpll = DPLL_VGA_MODE_DIS;
3813
3814 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3815 dpll |= DPLLB_MODE_LVDS;
3816 else
3817 dpll |= DPLLB_MODE_DAC_SERIAL;
3818 if (is_sdvo) {
3819 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3820 if (pixel_multiplier > 1) {
3821 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3822 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3823 }
3824 dpll |= DPLL_DVO_HIGH_SPEED;
3825 }
3826 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3827 dpll |= DPLL_DVO_HIGH_SPEED;
3828
3829 /* compute bitmask from p1 value */
3830 if (IS_PINEVIEW(dev))
3831 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3832 else {
3833 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3834 if (IS_G4X(dev) && reduced_clock)
3835 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3836 }
3837 switch (clock->p2) {
3838 case 5:
3839 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3840 break;
3841 case 7:
3842 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3843 break;
3844 case 10:
3845 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3846 break;
3847 case 14:
3848 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3849 break;
3850 }
3851 if (INTEL_INFO(dev)->gen >= 4)
3852 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3853
3854 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3855 dpll |= PLL_REF_INPUT_TVCLKINBC;
3856 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3857 /* XXX: just matching BIOS for now */
3858 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3859 dpll |= 3;
3860 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3861 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3862 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3863 else
3864 dpll |= PLL_REF_INPUT_DREFCLK;
3865
3866 dpll |= DPLL_VCO_ENABLE;
3867 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3868 POSTING_READ(DPLL(pipe));
3869 udelay(150);
3870
3871 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3872 * This is an exception to the general rule that mode_set doesn't turn
3873 * things on.
3874 */
3875 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3876 intel_update_lvds(crtc, clock, adjusted_mode);
3877
3878 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3879 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3880
3881 I915_WRITE(DPLL(pipe), dpll);
3882
3883 /* Wait for the clocks to stabilize. */
3884 POSTING_READ(DPLL(pipe));
3885 udelay(150);
3886
3887 if (INTEL_INFO(dev)->gen >= 4) {
3888 u32 temp = 0;
3889 if (is_sdvo) {
3890 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3891 if (temp > 1)
3892 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3893 else
3894 temp = 0;
3895 }
3896 I915_WRITE(DPLL_MD(pipe), temp);
3897 } else {
3898 /* The pixel multiplier can only be updated once the
3899 * DPLL is enabled and the clocks are stable.
3900 *
3901 * So write it again.
3902 */
3903 I915_WRITE(DPLL(pipe), dpll);
3904 }
3905}
3906
3907static void i8xx_update_pll(struct drm_crtc *crtc,
3908 struct drm_display_mode *adjusted_mode,
3909 intel_clock_t *clock,
3910 int num_connectors)
3911{
3912 struct drm_device *dev = crtc->dev;
3913 struct drm_i915_private *dev_priv = dev->dev_private;
3914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3915 int pipe = intel_crtc->pipe;
3916 u32 dpll;
3917
3918 dpll = DPLL_VGA_MODE_DIS;
3919
3920 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3921 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3922 } else {
3923 if (clock->p1 == 2)
3924 dpll |= PLL_P1_DIVIDE_BY_TWO;
3925 else
3926 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3927 if (clock->p2 == 4)
3928 dpll |= PLL_P2_DIVIDE_BY_4;
3929 }
3930
3931 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3932 /* XXX: just matching BIOS for now */
3933 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3934 dpll |= 3;
3935 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3936 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3937 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3938 else
3939 dpll |= PLL_REF_INPUT_DREFCLK;
3940
3941 dpll |= DPLL_VCO_ENABLE;
3942 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3943 POSTING_READ(DPLL(pipe));
3944 udelay(150);
3945
3946 I915_WRITE(DPLL(pipe), dpll);
3947
3948 /* Wait for the clocks to stabilize. */
3949 POSTING_READ(DPLL(pipe));
3950 udelay(150);
3951
3952 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3953 * This is an exception to the general rule that mode_set doesn't turn
3954 * things on.
3955 */
3956 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3957 intel_update_lvds(crtc, clock, adjusted_mode);
3958
3959 /* The pixel multiplier can only be updated once the
3960 * DPLL is enabled and the clocks are stable.
3961 *
3962 * So write it again.
3963 */
3964 I915_WRITE(DPLL(pipe), dpll);
3965}
3966
f564048e
EA		 3967static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3968 struct drm_display_mode *mode,
3969 struct drm_display_mode *adjusted_mode,
3970 int x, int y,
3971 struct drm_framebuffer *old_fb)
79e53945
JB		 3972{
3973 struct drm_device *dev = crtc->dev;
3974 struct drm_i915_private *dev_priv = dev->dev_private;
3975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3976 int pipe = intel_crtc->pipe;
80824003 3977 int plane = intel_crtc->plane;
c751ce4f 3978 int refclk, num_connectors = 0;
652c393a 3979 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 3980 u32 dspcntr, pipeconf, vsyncshift;
3981 bool ok, has_reduced_clock = false, is_sdvo = false;
3982 bool is_lvds = false, is_tv = false, is_dp = false;
79e53945 3983 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 3984 struct intel_encoder *encoder;
d4906093 3985 const intel_limit_t *limit;
5c3b82e2 3986 int ret;
79e53945 3987
5eddb70b
CW		 3988 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3989 if (encoder->base.crtc != crtc)
79e53945
JB		 3990 continue;
3991
5eddb70b 3992 switch (encoder->type) {
79e53945
JB		 3993 case INTEL_OUTPUT_LVDS:
3994 is_lvds = true;
3995 break;
3996 case INTEL_OUTPUT_SDVO:
7d57382e 3997 case INTEL_OUTPUT_HDMI:
79e53945 3998 is_sdvo = true;
5eddb70b 3999 if (encoder->needs_tv_clock)
e2f0ba97 4000 is_tv = true;
79e53945 4001 break;
79e53945
JB		 4002 case INTEL_OUTPUT_TVOUT:
4003 is_tv = true;
4004 break;
a4fc5ed6
KP		 4005 case INTEL_OUTPUT_DISPLAYPORT:
4006 is_dp = true;
4007 break;
79e53945 4008 }
43565a06 4009
c751ce4f 4010 num_connectors++;
79e53945
JB		 4011 }
4012
c65d77d8 4013 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4014
d4906093
ML		 4015 /*
4016 * Returns a set of divisors for the desired target clock with the given
4017 * refclk, or FALSE. The returned values represent the clock equation:
4018 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4019 */
1b894b59 4020 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4021 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4022 &clock);
79e53945
JB		 4023 if (!ok) {
4024 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4025 return -EINVAL;
79e53945
JB		 4026 }
4027
cda4b7d3 4028 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4029 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4030
ddc9003c 4031 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4032 /*
4033 * Ensure we match the reduced clock's P to the target clock.
4034 * If the clocks don't match, we can't switch the display clock
4035 * by using the FP0/FP1. In such case we will disable the LVDS
4036 * downclock feature.
4037 */
ddc9003c 4038 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4039 dev_priv->lvds_downclock,
4040 refclk,
cec2f356 4041 &clock,
5eddb70b 4042 &reduced_clock);
7026d4ac
ZW		 4043 }
4044
c65d77d8
JB		 4045 if (is_sdvo && is_tv)
4046 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4047
a7516a05
JB		 4048 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4049 &reduced_clock : NULL);
79e53945 4050
eb1cbe48
DV		 4051 if (IS_GEN2(dev))
4052 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
79e53945 4053 else
eb1cbe48
DV		 4054 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4055 has_reduced_clock ? &reduced_clock : NULL,
4056 num_connectors);
79e53945
JB		 4057
4058 /* setup pipeconf */
5eddb70b 4059 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4060
4061 /* Set up the display plane register */
4062 dspcntr = DISPPLANE_GAMMA_ENABLE;
4063
929c77fb
EA		 4064 if (pipe == 0)
4065 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4066 else
4067 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4068
a6c45cf0 4069 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4070 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4071 * core speed.
4072 *
4073 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4074 * pipe == 0 check?
4075 */
e70236a8
JB		 4076 if (mode->clock >
4077 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4078 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4079 else
5eddb70b 4080 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4081 }
4082
3b5c78a3
AJ		 4083 /* default to 8bpc */
4084 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4085 if (is_dp) {
4086 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4087 pipeconf |= PIPECONF_BPP_6 |
4088 PIPECONF_DITHER_EN |
4089 PIPECONF_DITHER_TYPE_SP;
4090 }
4091 }
4092
28c97730 4093 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4094 drm_mode_debug_printmodeline(mode);
4095
a7516a05
JB		 4096 if (HAS_PIPE_CXSR(dev)) {
4097 if (intel_crtc->lowfreq_avail) {
28c97730 4098 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4099 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4100 } else {
28c97730 4101 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4102 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4103 }
4104 }
4105
617cf884 4106 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 4107 if (!IS_GEN2(dev) &&
4108 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 4109 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4110 /* the chip adds 2 halflines automatically */
734b4157 4111 adjusted_mode->crtc_vtotal -= 1;
734b4157 4112 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4113 vsyncshift = adjusted_mode->crtc_hsync_start
4114 - adjusted_mode->crtc_htotal/2;
4115 } else {
617cf884 4116 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4117 vsyncshift = 0;
4118 }
4119
4120 if (!IS_GEN3(dev))
4121 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 4122
5eddb70b
CW		 4123 I915_WRITE(HTOTAL(pipe),
4124 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4125 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4126 I915_WRITE(HBLANK(pipe),
4127 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4128 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4129 I915_WRITE(HSYNC(pipe),
4130 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4131 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4132
4133 I915_WRITE(VTOTAL(pipe),
4134 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4135 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4136 I915_WRITE(VBLANK(pipe),
4137 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4138 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4139 I915_WRITE(VSYNC(pipe),
4140 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4141 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4142
4143 /* pipesrc and dspsize control the size that is scaled from,
4144 * which should always be the user's requested size.
79e53945 4145 */
929c77fb
EA		 4146 I915_WRITE(DSPSIZE(plane),
4147 ((mode->vdisplay - 1) << 16) |
4148 (mode->hdisplay - 1));
4149 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4150 I915_WRITE(PIPESRC(pipe),
4151 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4152
f564048e
EA		 4153 I915_WRITE(PIPECONF(pipe), pipeconf);
4154 POSTING_READ(PIPECONF(pipe));
929c77fb 4155 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4156
4157 intel_wait_for_vblank(dev, pipe);
4158
f564048e
EA		 4159 I915_WRITE(DSPCNTR(plane), dspcntr);
4160 POSTING_READ(DSPCNTR(plane));
4161
4162 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4163
4164 intel_update_watermarks(dev);
4165
f564048e
EA		 4166 return ret;
4167}
4168
9fb526db
KP		 4169/*
4170 * Initialize reference clocks when the driver loads
4171 */
4172void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4173{
4174 struct drm_i915_private *dev_priv = dev->dev_private;
4175 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4176 struct intel_encoder *encoder;
13d83a67
JB		 4177 u32 temp;
4178 bool has_lvds = false;
199e5d79
KP		 4179 bool has_cpu_edp = false;
4180 bool has_pch_edp = false;
4181 bool has_panel = false;
99eb6a01
KP		 4182 bool has_ck505 = false;
4183 bool can_ssc = false;
13d83a67
JB		 4184
4185 /* We need to take the global config into account */
199e5d79
KP		 4186 list_for_each_entry(encoder, &mode_config->encoder_list,
4187 base.head) {
4188 switch (encoder->type) {
4189 case INTEL_OUTPUT_LVDS:
4190 has_panel = true;
4191 has_lvds = true;
4192 break;
4193 case INTEL_OUTPUT_EDP:
4194 has_panel = true;
4195 if (intel_encoder_is_pch_edp(&encoder->base))
4196 has_pch_edp = true;
4197 else
4198 has_cpu_edp = true;
4199 break;
13d83a67
JB		 4200 }
4201 }
4202
99eb6a01
KP		 4203 if (HAS_PCH_IBX(dev)) {
4204 has_ck505 = dev_priv->display_clock_mode;
4205 can_ssc = has_ck505;
4206 } else {
4207 has_ck505 = false;
4208 can_ssc = true;
4209 }
4210
4211 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4212 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4213 has_ck505);
13d83a67
JB		 4214
4215 /* Ironlake: try to setup display ref clock before DPLL
4216 * enabling. This is only under driver's control after
4217 * PCH B stepping, previous chipset stepping should be
4218 * ignoring this setting.
4219 */
4220 temp = I915_READ(PCH_DREF_CONTROL);
4221 /* Always enable nonspread source */
4222 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4223
99eb6a01
KP		 4224 if (has_ck505)
4225 temp |= DREF_NONSPREAD_CK505_ENABLE;
4226 else
4227 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4228
199e5d79
KP		 4229 if (has_panel) {
4230 temp &= ~DREF_SSC_SOURCE_MASK;
4231 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4232
199e5d79 4233 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4234 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4235 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4236 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4237 } else
4238 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4239
4240 /* Get SSC going before enabling the outputs */
4241 I915_WRITE(PCH_DREF_CONTROL, temp);
4242 POSTING_READ(PCH_DREF_CONTROL);
4243 udelay(200);
4244
13d83a67
JB		 4245 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4246
4247 /* Enable CPU source on CPU attached eDP */
199e5d79 4248 if (has_cpu_edp) {
99eb6a01 4249 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4250 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4251 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4252 }
13d83a67
JB		 4253 else
4254 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4255 } else
4256 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4257
4258 I915_WRITE(PCH_DREF_CONTROL, temp);
4259 POSTING_READ(PCH_DREF_CONTROL);
4260 udelay(200);
4261 } else {
4262 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4263
4264 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4265
4266 /* Turn off CPU output */
4267 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4268
4269 I915_WRITE(PCH_DREF_CONTROL, temp);
4270 POSTING_READ(PCH_DREF_CONTROL);
4271 udelay(200);
4272
4273 /* Turn off the SSC source */
4274 temp &= ~DREF_SSC_SOURCE_MASK;
4275 temp |= DREF_SSC_SOURCE_DISABLE;
4276
4277 /* Turn off SSC1 */
4278 temp &= ~ DREF_SSC1_ENABLE;
4279
13d83a67
JB		 4280 I915_WRITE(PCH_DREF_CONTROL, temp);
4281 POSTING_READ(PCH_DREF_CONTROL);
4282 udelay(200);
4283 }
4284}
4285
d9d444cb
JB		 4286static int ironlake_get_refclk(struct drm_crtc *crtc)
4287{
4288 struct drm_device *dev = crtc->dev;
4289 struct drm_i915_private *dev_priv = dev->dev_private;
4290 struct intel_encoder *encoder;
4291 struct drm_mode_config *mode_config = &dev->mode_config;
4292 struct intel_encoder *edp_encoder = NULL;
4293 int num_connectors = 0;
4294 bool is_lvds = false;
4295
4296 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4297 if (encoder->base.crtc != crtc)
4298 continue;
4299
4300 switch (encoder->type) {
4301 case INTEL_OUTPUT_LVDS:
4302 is_lvds = true;
4303 break;
4304 case INTEL_OUTPUT_EDP:
4305 edp_encoder = encoder;
4306 break;
4307 }
4308 num_connectors++;
4309 }
4310
4311 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4312 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4313 dev_priv->lvds_ssc_freq);
4314 return dev_priv->lvds_ssc_freq * 1000;
4315 }
4316
4317 return 120000;
4318}
4319
f564048e
EA		 4320static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4321 struct drm_display_mode *mode,
4322 struct drm_display_mode *adjusted_mode,
4323 int x, int y,
4324 struct drm_framebuffer *old_fb)
79e53945
JB		 4325{
4326 struct drm_device *dev = crtc->dev;
4327 struct drm_i915_private *dev_priv = dev->dev_private;
4328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4329 int pipe = intel_crtc->pipe;
80824003 4330 int plane = intel_crtc->plane;
c751ce4f 4331 int refclk, num_connectors = 0;
652c393a 4332 intel_clock_t clock, reduced_clock;
5eddb70b 4333 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4334 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4335 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4336 struct drm_mode_config *mode_config = &dev->mode_config;
e3aef172 4337 struct intel_encoder *encoder, *edp_encoder = NULL;
d4906093 4338 const intel_limit_t *limit;
5c3b82e2 4339 int ret;
2c07245f 4340 struct fdi_m_n m_n = {0};
fae14981 4341 u32 temp;
5a354204
JB		 4342 int target_clock, pixel_multiplier, lane, link_bw, factor;
4343 unsigned int pipe_bpp;
4344 bool dither;
e3aef172 4345 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4346
5eddb70b
CW		 4347 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4348 if (encoder->base.crtc != crtc)
79e53945
JB		 4349 continue;
4350
5eddb70b 4351 switch (encoder->type) {
79e53945
JB		 4352 case INTEL_OUTPUT_LVDS:
4353 is_lvds = true;
4354 break;
4355 case INTEL_OUTPUT_SDVO:
7d57382e 4356 case INTEL_OUTPUT_HDMI:
79e53945 4357 is_sdvo = true;
5eddb70b 4358 if (encoder->needs_tv_clock)
e2f0ba97 4359 is_tv = true;
79e53945 4360 break;
79e53945
JB		 4361 case INTEL_OUTPUT_TVOUT:
4362 is_tv = true;
4363 break;
4364 case INTEL_OUTPUT_ANALOG:
4365 is_crt = true;
4366 break;
a4fc5ed6
KP		 4367 case INTEL_OUTPUT_DISPLAYPORT:
4368 is_dp = true;
4369 break;
32f9d658 4370 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4371 is_dp = true;
4372 if (intel_encoder_is_pch_edp(&encoder->base))
4373 is_pch_edp = true;
4374 else
4375 is_cpu_edp = true;
4376 edp_encoder = encoder;
32f9d658 4377 break;
79e53945 4378 }
43565a06 4379
c751ce4f 4380 num_connectors++;
79e53945
JB		 4381 }
4382
d9d444cb 4383 refclk = ironlake_get_refclk(crtc);
79e53945 4384
d4906093
ML		 4385 /*
4386 * Returns a set of divisors for the desired target clock with the given
4387 * refclk, or FALSE. The returned values represent the clock equation:
4388 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4389 */
1b894b59 4390 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4391 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4392 &clock);
79e53945
JB		 4393 if (!ok) {
4394 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4395 return -EINVAL;
79e53945
JB		 4396 }
4397
cda4b7d3 4398 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4399 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4400
ddc9003c 4401 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4402 /*
4403 * Ensure we match the reduced clock's P to the target clock.
4404 * If the clocks don't match, we can't switch the display clock
4405 * by using the FP0/FP1. In such case we will disable the LVDS
4406 * downclock feature.
4407 */
ddc9003c 4408 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4409 dev_priv->lvds_downclock,
4410 refclk,
cec2f356 4411 &clock,
5eddb70b 4412 &reduced_clock);
652c393a 4413 }
61e9653f
DV		 4414
4415 if (is_sdvo && is_tv)
4416 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4417
7026d4ac 4418
2c07245f 4419 /* FDI link */
8febb297
EA		 4420 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4421 lane = 0;
4422 /* CPU eDP doesn't require FDI link, so just set DP M/N
4423 according to current link config */
e3aef172 4424 if (is_cpu_edp) {
e3aef172 4425 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 4426 } else {
8febb297
EA		 4427 /* FDI is a binary signal running at ~2.7GHz, encoding
4428 * each output octet as 10 bits. The actual frequency
4429 * is stored as a divider into a 100MHz clock, and the
4430 * mode pixel clock is stored in units of 1KHz.
4431 * Hence the bw of each lane in terms of the mode signal
4432 * is:
4433 */
4434 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4435 }
58a27471 4436
94bf2ced
DV		 4437 /* [e]DP over FDI requires target mode clock instead of link clock. */
4438 if (edp_encoder)
4439 target_clock = intel_edp_target_clock(edp_encoder, mode);
4440 else if (is_dp)
4441 target_clock = mode->clock;
4442 else
4443 target_clock = adjusted_mode->clock;
4444
8febb297
EA		 4445 /* determine panel color depth */
4446 temp = I915_READ(PIPECONF(pipe));
4447 temp &= ~PIPE_BPC_MASK;
3b5c78a3 4448 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 4449 switch (pipe_bpp) {
4450 case 18:
4451 temp |= PIPE_6BPC;
8febb297 4452 break;
5a354204
JB		 4453 case 24:
4454 temp |= PIPE_8BPC;
8febb297 4455 break;
5a354204
JB		 4456 case 30:
4457 temp |= PIPE_10BPC;
8febb297 4458 break;
5a354204
JB		 4459 case 36:
4460 temp |= PIPE_12BPC;
8febb297
EA		 4461 break;
4462 default:
62ac41a6
JB		 4463 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4464 pipe_bpp);
5a354204
JB		 4465 temp |= PIPE_8BPC;
4466 pipe_bpp = 24;
4467 break;
8febb297 4468 }
77ffb597 4469
5a354204
JB		 4470 intel_crtc->bpp = pipe_bpp;
4471 I915_WRITE(PIPECONF(pipe), temp);
4472
8febb297
EA		 4473 if (!lane) {
4474 /*
4475 * Account for spread spectrum to avoid
4476 * oversubscribing the link. Max center spread
4477 * is 2.5%; use 5% for safety's sake.
4478 */
5a354204 4479 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4480 lane = bps / (link_bw * 8) + 1;
5eb08b69 4481 }
2c07245f 4482
8febb297
EA		 4483 intel_crtc->fdi_lanes = lane;
4484
4485 if (pixel_multiplier > 1)
4486 link_bw *= pixel_multiplier;
5a354204
JB		 4487 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4488 &m_n);
8febb297 4489
a07d6787
EA		 4490 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4491 if (has_reduced_clock)
4492 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4493 reduced_clock.m2;
79e53945 4494
c1858123 4495 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4496 factor = 21;
4497 if (is_lvds) {
4498 if ((intel_panel_use_ssc(dev_priv) &&
4499 dev_priv->lvds_ssc_freq == 100) ||
4500 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4501 factor = 25;
4502 } else if (is_sdvo && is_tv)
4503 factor = 20;
c1858123 4504
cb0e0931 4505 if (clock.m < factor * clock.n)
8febb297 4506 fp |= FP_CB_TUNE;
2c07245f 4507
5eddb70b 4508 dpll = 0;
2c07245f 4509
a07d6787
EA		 4510 if (is_lvds)
4511 dpll |= DPLLB_MODE_LVDS;
4512 else
4513 dpll |= DPLLB_MODE_DAC_SERIAL;
4514 if (is_sdvo) {
4515 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4516 if (pixel_multiplier > 1) {
4517 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4518 }
a07d6787
EA		 4519 dpll |= DPLL_DVO_HIGH_SPEED;
4520 }
e3aef172 4521 if (is_dp && !is_cpu_edp)
a07d6787 4522 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4523
a07d6787
EA		 4524 /* compute bitmask from p1 value */
4525 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4526 /* also FPA1 */
4527 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4528
4529 switch (clock.p2) {
4530 case 5:
4531 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4532 break;
4533 case 7:
4534 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4535 break;
4536 case 10:
4537 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4538 break;
4539 case 14:
4540 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4541 break;
79e53945
JB		 4542 }
4543
43565a06
KH		 4544 if (is_sdvo && is_tv)
4545 dpll |= PLL_REF_INPUT_TVCLKINBC;
4546 else if (is_tv)
79e53945 4547 /* XXX: just matching BIOS for now */
43565a06 4548 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4549 dpll |= 3;
a7615030 4550 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4551 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4552 else
4553 dpll |= PLL_REF_INPUT_DREFCLK;
4554
4555 /* setup pipeconf */
5eddb70b 4556 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4557
4558 /* Set up the display plane register */
4559 dspcntr = DISPPLANE_GAMMA_ENABLE;
4560
f7cb34d4 4561 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4562 drm_mode_debug_printmodeline(mode);
4563
9d82aa17
ED		 4564 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4565 * pre-Haswell/LPT generation */
4566 if (HAS_PCH_LPT(dev)) {
4567 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4568 pipe);
4569 } else if (!is_cpu_edp) {
ee7b9f93 4570 struct intel_pch_pll *pll;
4b645f14 4571
ee7b9f93
JB		 4572 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4573 if (pll == NULL) {
4574 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4575 pipe);
4b645f14
JB		 4576 return -EINVAL;
4577 }
ee7b9f93
JB		 4578 } else
4579 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4580
4581 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4582 * This is an exception to the general rule that mode_set doesn't turn
4583 * things on.
4584 */
4585 if (is_lvds) {
fae14981 4586 temp = I915_READ(PCH_LVDS);
5eddb70b 4587 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4588 if (HAS_PCH_CPT(dev)) {
4589 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4590 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4591 } else {
4592 if (pipe == 1)
4593 temp |= LVDS_PIPEB_SELECT;
4594 else
4595 temp &= ~LVDS_PIPEB_SELECT;
4596 }
4b645f14 4597
a3e17eb8 4598 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4599 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4600 /* Set the B0-B3 data pairs corresponding to whether we're going to
4601 * set the DPLLs for dual-channel mode or not.
4602 */
4603 if (clock.p2 == 7)
5eddb70b 4604 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4605 else
5eddb70b 4606 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4607
4608 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4609 * appropriately here, but we need to look more thoroughly into how
4610 * panels behave in the two modes.
4611 */
284d5df5 4612 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4613 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4614 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4615 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4616 temp |= LVDS_VSYNC_POLARITY;
fae14981 4617 I915_WRITE(PCH_LVDS, temp);
79e53945 4618 }
434ed097 4619
8febb297
EA		 4620 pipeconf &= ~PIPECONF_DITHER_EN;
4621 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 4622 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 4623 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 4624 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 4625 }
e3aef172 4626 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4627 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4628 } else {
8db9d77b 4629 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4630 I915_WRITE(TRANSDATA_M1(pipe), 0);
4631 I915_WRITE(TRANSDATA_N1(pipe), 0);
4632 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4633 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4634 }
79e53945 4635
ee7b9f93
JB		 4636 if (intel_crtc->pch_pll) {
4637 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4638
32f9d658 4639 /* Wait for the clocks to stabilize. */
ee7b9f93 4640 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4641 udelay(150);
4642
8febb297
EA		 4643 /* The pixel multiplier can only be updated once the
4644 * DPLL is enabled and the clocks are stable.
4645 *
4646 * So write it again.
4647 */
ee7b9f93 4648 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 4649 }
79e53945 4650
5eddb70b 4651 intel_crtc->lowfreq_avail = false;
ee7b9f93 4652 if (intel_crtc->pch_pll) {
4b645f14 4653 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 4654 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 4655 intel_crtc->lowfreq_avail = true;
4b645f14 4656 } else {
ee7b9f93 4657 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 4658 }
4659 }
4660
617cf884 4661 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 4662 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 4663 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 4664 /* the chip adds 2 halflines automatically */
734b4157 4665 adjusted_mode->crtc_vtotal -= 1;
734b4157 4666 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4667 I915_WRITE(VSYNCSHIFT(pipe),
4668 adjusted_mode->crtc_hsync_start
4669 - adjusted_mode->crtc_htotal/2);
4670 } else {
617cf884 4671 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4672 I915_WRITE(VSYNCSHIFT(pipe), 0);
4673 }
734b4157 4674
5eddb70b
CW		 4675 I915_WRITE(HTOTAL(pipe),
4676 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4677 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4678 I915_WRITE(HBLANK(pipe),
4679 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4680 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4681 I915_WRITE(HSYNC(pipe),
4682 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4683 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4684
4685 I915_WRITE(VTOTAL(pipe),
4686 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4687 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4688 I915_WRITE(VBLANK(pipe),
4689 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4690 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4691 I915_WRITE(VSYNC(pipe),
4692 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4693 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 4694
8febb297
EA		 4695 /* pipesrc controls the size that is scaled from, which should
4696 * always be the user's requested size.
79e53945 4697 */
5eddb70b
CW		 4698 I915_WRITE(PIPESRC(pipe),
4699 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4700
8febb297
EA		 4701 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4702 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4703 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4704 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 4705
e3aef172 4706 if (is_cpu_edp)
8febb297 4707 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 4708
5eddb70b
CW		 4709 I915_WRITE(PIPECONF(pipe), pipeconf);
4710 POSTING_READ(PIPECONF(pipe));
79e53945 4711
9d0498a2 4712 intel_wait_for_vblank(dev, pipe);
79e53945 4713
5eddb70b 4714 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 4715 POSTING_READ(DSPCNTR(plane));
79e53945 4716
5c3b82e2 4717 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 4718
4719 intel_update_watermarks(dev);
4720
1f8eeabf
ED		 4721 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4722
1f803ee5 4723 return ret;
79e53945
JB		 4724}
4725
f564048e
EA		 4726static int intel_crtc_mode_set(struct drm_crtc *crtc,
4727 struct drm_display_mode *mode,
4728 struct drm_display_mode *adjusted_mode,
4729 int x, int y,
4730 struct drm_framebuffer *old_fb)
4731{
4732 struct drm_device *dev = crtc->dev;
4733 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 4734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4735 int pipe = intel_crtc->pipe;
f564048e
EA		 4736 int ret;
4737
0b701d27 4738 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 4739
f564048e
EA		 4740 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4741 x, y, old_fb);
79e53945 4742 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 4743
d8e70a25
JB		 4744 if (ret)
4745 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4746 else
4747 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 4748
1f803ee5 4749 return ret;
79e53945
JB		 4750}
4751
3a9627f4
WF		 4752static bool intel_eld_uptodate(struct drm_connector *connector,
4753 int reg_eldv, uint32_t bits_eldv,
4754 int reg_elda, uint32_t bits_elda,
4755 int reg_edid)
4756{
4757 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4758 uint8_t *eld = connector->eld;
4759 uint32_t i;
4760
4761 i = I915_READ(reg_eldv);
4762 i &= bits_eldv;
4763
4764 if (!eld[0])
4765 return !i;
4766
4767 if (!i)
4768 return false;
4769
4770 i = I915_READ(reg_elda);
4771 i &= ~bits_elda;
4772 I915_WRITE(reg_elda, i);
4773
4774 for (i = 0; i < eld[2]; i++)
4775 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4776 return false;
4777
4778 return true;
4779}
4780
e0dac65e
WF		 4781static void g4x_write_eld(struct drm_connector *connector,
4782 struct drm_crtc *crtc)
4783{
4784 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4785 uint8_t *eld = connector->eld;
4786 uint32_t eldv;
4787 uint32_t len;
4788 uint32_t i;
4789
4790 i = I915_READ(G4X_AUD_VID_DID);
4791
4792 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4793 eldv = G4X_ELDV_DEVCL_DEVBLC;
4794 else
4795 eldv = G4X_ELDV_DEVCTG;
4796
3a9627f4
WF		 4797 if (intel_eld_uptodate(connector,
4798 G4X_AUD_CNTL_ST, eldv,
4799 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4800 G4X_HDMIW_HDMIEDID))
4801 return;
4802
e0dac65e
WF		 4803 i = I915_READ(G4X_AUD_CNTL_ST);
4804 i &= ~(eldv | G4X_ELD_ADDR);
4805 len = (i >> 9) & 0x1f; /* ELD buffer size */
4806 I915_WRITE(G4X_AUD_CNTL_ST, i);
4807
4808 if (!eld[0])
4809 return;
4810
4811 len = min_t(uint8_t, eld[2], len);
4812 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4813 for (i = 0; i < len; i++)
4814 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4815
4816 i = I915_READ(G4X_AUD_CNTL_ST);
4817 i |= eldv;
4818 I915_WRITE(G4X_AUD_CNTL_ST, i);
4819}
4820
4821static void ironlake_write_eld(struct drm_connector *connector,
4822 struct drm_crtc *crtc)
4823{
4824 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4825 uint8_t *eld = connector->eld;
4826 uint32_t eldv;
4827 uint32_t i;
4828 int len;
4829 int hdmiw_hdmiedid;
b6daa025 4830 int aud_config;
e0dac65e
WF		 4831 int aud_cntl_st;
4832 int aud_cntrl_st2;
4833
b3f33cbf 4834 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6 4835 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
b6daa025 4836 aud_config = IBX_AUD_CONFIG_A;
1202b4c6
WF		 4837 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4838 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 4839 } else {
1202b4c6 4840 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
b6daa025 4841 aud_config = CPT_AUD_CONFIG_A;
1202b4c6
WF		 4842 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4843 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 4844 }
4845
4846 i = to_intel_crtc(crtc)->pipe;
4847 hdmiw_hdmiedid += i * 0x100;
4848 aud_cntl_st += i * 0x100;
b6daa025 4849 aud_config += i * 0x100;
e0dac65e
WF		 4850
4851 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4852
4853 i = I915_READ(aud_cntl_st);
4854 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4855 if (!i) {
4856 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4857 /* operate blindly on all ports */
1202b4c6
WF		 4858 eldv = IBX_ELD_VALIDB;
4859 eldv |= IBX_ELD_VALIDB << 4;
4860 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 4861 } else {
4862 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 4863 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 4864 }
4865
3a9627f4
WF		 4866 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4867 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4868 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 4869 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4870 } else
4871 I915_WRITE(aud_config, 0);
e0dac65e 4872
3a9627f4
WF		 4873 if (intel_eld_uptodate(connector,
4874 aud_cntrl_st2, eldv,
4875 aud_cntl_st, IBX_ELD_ADDRESS,
4876 hdmiw_hdmiedid))
4877 return;
4878
e0dac65e
WF		 4879 i = I915_READ(aud_cntrl_st2);
4880 i &= ~eldv;
4881 I915_WRITE(aud_cntrl_st2, i);
4882
4883 if (!eld[0])
4884 return;
4885
e0dac65e 4886 i = I915_READ(aud_cntl_st);
1202b4c6 4887 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 4888 I915_WRITE(aud_cntl_st, i);
4889
4890 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
4891 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4892 for (i = 0; i < len; i++)
4893 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4894
4895 i = I915_READ(aud_cntrl_st2);
4896 i |= eldv;
4897 I915_WRITE(aud_cntrl_st2, i);
4898}
4899
4900void intel_write_eld(struct drm_encoder *encoder,
4901 struct drm_display_mode *mode)
4902{
4903 struct drm_crtc *crtc = encoder->crtc;
4904 struct drm_connector *connector;
4905 struct drm_device *dev = encoder->dev;
4906 struct drm_i915_private *dev_priv = dev->dev_private;
4907
4908 connector = drm_select_eld(encoder, mode);
4909 if (!connector)
4910 return;
4911
4912 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4913 connector->base.id,
4914 drm_get_connector_name(connector),
4915 connector->encoder->base.id,
4916 drm_get_encoder_name(connector->encoder));
4917
4918 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4919
4920 if (dev_priv->display.write_eld)
4921 dev_priv->display.write_eld(connector, crtc);
4922}
4923
79e53945
JB		 4924/** Loads the palette/gamma unit for the CRTC with the prepared values */
4925void intel_crtc_load_lut(struct drm_crtc *crtc)
4926{
4927 struct drm_device *dev = crtc->dev;
4928 struct drm_i915_private *dev_priv = dev->dev_private;
4929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 4930 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 4931 int i;
4932
4933 /* The clocks have to be on to load the palette. */
aed3f09d 4934 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 4935 return;
4936
f2b115e6 4937 /* use legacy palette for Ironlake */
bad720ff 4938 if (HAS_PCH_SPLIT(dev))
9db4a9c7 4939 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 4940
79e53945
JB		 4941 for (i = 0; i < 256; i++) {
4942 I915_WRITE(palreg + 4 * i,
4943 (intel_crtc->lut_r[i] << 16) |
4944 (intel_crtc->lut_g[i] << 8) |
4945 intel_crtc->lut_b[i]);
4946 }
4947}
4948
560b85bb
CW		 4949static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4950{
4951 struct drm_device *dev = crtc->dev;
4952 struct drm_i915_private *dev_priv = dev->dev_private;
4953 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4954 bool visible = base != 0;
4955 u32 cntl;
4956
4957 if (intel_crtc->cursor_visible == visible)
4958 return;
4959
9db4a9c7 4960 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 4961 if (visible) {
4962 /* On these chipsets we can only modify the base whilst
4963 * the cursor is disabled.
4964 */
9db4a9c7 4965 I915_WRITE(_CURABASE, base);
560b85bb
CW		 4966
4967 cntl &= ~(CURSOR_FORMAT_MASK);
4968 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4969 cntl |= CURSOR_ENABLE |
4970 CURSOR_GAMMA_ENABLE |
4971 CURSOR_FORMAT_ARGB;
4972 } else
4973 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 4974 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 4975
4976 intel_crtc->cursor_visible = visible;
4977}
4978
4979static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4980{
4981 struct drm_device *dev = crtc->dev;
4982 struct drm_i915_private *dev_priv = dev->dev_private;
4983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4984 int pipe = intel_crtc->pipe;
4985 bool visible = base != 0;
4986
4987 if (intel_crtc->cursor_visible != visible) {
548f245b 4988 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 4989 if (base) {
4990 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4991 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4992 cntl |= pipe << 28; /* Connect to correct pipe */
4993 } else {
4994 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4995 cntl |= CURSOR_MODE_DISABLE;
4996 }
9db4a9c7 4997 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 4998
4999 intel_crtc->cursor_visible = visible;
5000 }
5001 /* and commit changes on next vblank */
9db4a9c7 5002 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5003}
5004
65a21cd6
JB		 5005static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5006{
5007 struct drm_device *dev = crtc->dev;
5008 struct drm_i915_private *dev_priv = dev->dev_private;
5009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5010 int pipe = intel_crtc->pipe;
5011 bool visible = base != 0;
5012
5013 if (intel_crtc->cursor_visible != visible) {
5014 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5015 if (base) {
5016 cntl &= ~CURSOR_MODE;
5017 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5018 } else {
5019 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5020 cntl |= CURSOR_MODE_DISABLE;
5021 }
5022 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5023
5024 intel_crtc->cursor_visible = visible;
5025 }
5026 /* and commit changes on next vblank */
5027 I915_WRITE(CURBASE_IVB(pipe), base);
5028}
5029
cda4b7d3 5030/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5031static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5032 bool on)
cda4b7d3
CW		 5033{
5034 struct drm_device *dev = crtc->dev;
5035 struct drm_i915_private *dev_priv = dev->dev_private;
5036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5037 int pipe = intel_crtc->pipe;
5038 int x = intel_crtc->cursor_x;
5039 int y = intel_crtc->cursor_y;
560b85bb 5040 u32 base, pos;
cda4b7d3
CW		 5041 bool visible;
5042
5043 pos = 0;
5044
6b383a7f 5045 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5046 base = intel_crtc->cursor_addr;
5047 if (x > (int) crtc->fb->width)
5048 base = 0;
5049
5050 if (y > (int) crtc->fb->height)
5051 base = 0;
5052 } else
5053 base = 0;
5054
5055 if (x < 0) {
5056 if (x + intel_crtc->cursor_width < 0)
5057 base = 0;
5058
5059 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5060 x = -x;
5061 }
5062 pos |= x << CURSOR_X_SHIFT;
5063
5064 if (y < 0) {
5065 if (y + intel_crtc->cursor_height < 0)
5066 base = 0;
5067
5068 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5069 y = -y;
5070 }
5071 pos |= y << CURSOR_Y_SHIFT;
5072
5073 visible = base != 0;
560b85bb 5074 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5075 return;
5076
0cd83aa9 5077 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5078 I915_WRITE(CURPOS_IVB(pipe), pos);
5079 ivb_update_cursor(crtc, base);
5080 } else {
5081 I915_WRITE(CURPOS(pipe), pos);
5082 if (IS_845G(dev) || IS_I865G(dev))
5083 i845_update_cursor(crtc, base);
5084 else
5085 i9xx_update_cursor(crtc, base);
5086 }
cda4b7d3
CW		 5087}
5088
79e53945 5089static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5090 struct drm_file *file,
79e53945
JB		 5091 uint32_t handle,
5092 uint32_t width, uint32_t height)
5093{
5094 struct drm_device *dev = crtc->dev;
5095 struct drm_i915_private *dev_priv = dev->dev_private;
5096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5097 struct drm_i915_gem_object *obj;
cda4b7d3 5098 uint32_t addr;
3f8bc370 5099 int ret;
79e53945 5100
28c97730 5101 DRM_DEBUG_KMS("\n");
79e53945
JB		 5102
5103 /* if we want to turn off the cursor ignore width and height */
5104 if (!handle) {
28c97730 5105 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5106 addr = 0;
05394f39 5107 obj = NULL;
5004417d 5108 mutex_lock(&dev->struct_mutex);
3f8bc370 5109 goto finish;
79e53945
JB		 5110 }
5111
5112 /* Currently we only support 64x64 cursors */
5113 if (width != 64 || height != 64) {
5114 DRM_ERROR("we currently only support 64x64 cursors\n");
5115 return -EINVAL;
5116 }
5117
05394f39 5118 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5119 if (&obj->base == NULL)
79e53945
JB		 5120 return -ENOENT;
5121
05394f39 5122 if (obj->base.size < width * height * 4) {
79e53945 5123 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5124 ret = -ENOMEM;
5125 goto fail;
79e53945
JB		 5126 }
5127
71acb5eb 5128 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5129 mutex_lock(&dev->struct_mutex);
b295d1b6 5130 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5131 if (obj->tiling_mode) {
5132 DRM_ERROR("cursor cannot be tiled\n");
5133 ret = -EINVAL;
5134 goto fail_locked;
5135 }
5136
2da3b9b9 5137 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5138 if (ret) {
5139 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5140 goto fail_locked;
e7b526bb
CW		 5141 }
5142
d9e86c0e
CW		 5143 ret = i915_gem_object_put_fence(obj);
5144 if (ret) {
2da3b9b9 5145 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5146 goto fail_unpin;
5147 }
5148
05394f39 5149 addr = obj->gtt_offset;
71acb5eb 5150 } else {
6eeefaf3 5151 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5152 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5153 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5154 align);
71acb5eb
DA		 5155 if (ret) {
5156 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5157 goto fail_locked;
71acb5eb 5158 }
05394f39 5159 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5160 }
5161
a6c45cf0 5162 if (IS_GEN2(dev))
14b60391
JB		 5163 I915_WRITE(CURSIZE, (height << 12) | width);
5164
3f8bc370 5165 finish:
3f8bc370 5166 if (intel_crtc->cursor_bo) {
b295d1b6 5167 if (dev_priv->info->cursor_needs_physical) {
05394f39 5168 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5169 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5170 } else
5171 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5172 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5173 }
80824003 5174
7f9872e0 5175 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5176
5177 intel_crtc->cursor_addr = addr;
05394f39 5178 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5179 intel_crtc->cursor_width = width;
5180 intel_crtc->cursor_height = height;
5181
6b383a7f 5182 intel_crtc_update_cursor(crtc, true);
3f8bc370 5183
79e53945 5184 return 0;
e7b526bb 5185fail_unpin:
05394f39 5186 i915_gem_object_unpin(obj);
7f9872e0 5187fail_locked:
34b8686e 5188 mutex_unlock(&dev->struct_mutex);
bc9025bd 5189fail:
05394f39 5190 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5191 return ret;
79e53945
JB		 5192}
5193
5194static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5195{
79e53945 5196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5197
cda4b7d3
CW		 5198 intel_crtc->cursor_x = x;
5199 intel_crtc->cursor_y = y;
652c393a 5200
6b383a7f 5201 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5202
5203 return 0;
5204}
5205
5206/** Sets the color ramps on behalf of RandR */
5207void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5208 u16 blue, int regno)
5209{
5210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5211
5212 intel_crtc->lut_r[regno] = red >> 8;
5213 intel_crtc->lut_g[regno] = green >> 8;
5214 intel_crtc->lut_b[regno] = blue >> 8;
5215}
5216
b8c00ac5
DA		 5217void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5218 u16 *blue, int regno)
5219{
5220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5221
5222 *red = intel_crtc->lut_r[regno] << 8;
5223 *green = intel_crtc->lut_g[regno] << 8;
5224 *blue = intel_crtc->lut_b[regno] << 8;
5225}
5226
79e53945 5227static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5228 u16 *blue, uint32_t start, uint32_t size)
79e53945 5229{
7203425a 5230 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5232
7203425a 5233 for (i = start; i < end; i++) {
79e53945
JB		 5234 intel_crtc->lut_r[i] = red[i] >> 8;
5235 intel_crtc->lut_g[i] = green[i] >> 8;
5236 intel_crtc->lut_b[i] = blue[i] >> 8;
5237 }
5238
5239 intel_crtc_load_lut(crtc);
5240}
5241
5242/**
5243 * Get a pipe with a simple mode set on it for doing load-based monitor
5244 * detection.
5245 *
5246 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5247 * its requirements. The pipe will be connected to no other encoders.
79e53945 5248 *
c751ce4f 5249 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5250 * configured for it. In the future, it could choose to temporarily disable
5251 * some outputs to free up a pipe for its use.
5252 *
5253 * \return crtc, or NULL if no pipes are available.
5254 */
5255
5256/* VESA 640x480x72Hz mode to set on the pipe */
5257static struct drm_display_mode load_detect_mode = {
5258 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5259 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5260};
5261
d2dff872
CW		 5262static struct drm_framebuffer *
5263intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5264 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5265 struct drm_i915_gem_object *obj)
5266{
5267 struct intel_framebuffer *intel_fb;
5268 int ret;
5269
5270 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5271 if (!intel_fb) {
5272 drm_gem_object_unreference_unlocked(&obj->base);
5273 return ERR_PTR(-ENOMEM);
5274 }
5275
5276 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5277 if (ret) {
5278 drm_gem_object_unreference_unlocked(&obj->base);
5279 kfree(intel_fb);
5280 return ERR_PTR(ret);
5281 }
5282
5283 return &intel_fb->base;
5284}
5285
5286static u32
5287intel_framebuffer_pitch_for_width(int width, int bpp)
5288{
5289 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5290 return ALIGN(pitch, 64);
5291}
5292
5293static u32
5294intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5295{
5296 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5297 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5298}
5299
5300static struct drm_framebuffer *
5301intel_framebuffer_create_for_mode(struct drm_device *dev,
5302 struct drm_display_mode *mode,
5303 int depth, int bpp)
5304{
5305 struct drm_i915_gem_object *obj;
308e5bcb 5306 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5307
5308 obj = i915_gem_alloc_object(dev,
5309 intel_framebuffer_size_for_mode(mode, bpp));
5310 if (obj == NULL)
5311 return ERR_PTR(-ENOMEM);
5312
5313 mode_cmd.width = mode->hdisplay;
5314 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5315 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5316 bpp);
5ca0c34a 5317 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5318
5319 return intel_framebuffer_create(dev, &mode_cmd, obj);
5320}
5321
5322static struct drm_framebuffer *
5323mode_fits_in_fbdev(struct drm_device *dev,
5324 struct drm_display_mode *mode)
5325{
5326 struct drm_i915_private *dev_priv = dev->dev_private;
5327 struct drm_i915_gem_object *obj;
5328 struct drm_framebuffer *fb;
5329
5330 if (dev_priv->fbdev == NULL)
5331 return NULL;
5332
5333 obj = dev_priv->fbdev->ifb.obj;
5334 if (obj == NULL)
5335 return NULL;
5336
5337 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5338 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5339 fb->bits_per_pixel))
d2dff872
CW		 5340 return NULL;
5341
01f2c773 5342 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5343 return NULL;
5344
5345 return fb;
5346}
5347
7173188d
CW		 5348bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5349 struct drm_connector *connector,
5350 struct drm_display_mode *mode,
8261b191 5351 struct intel_load_detect_pipe *old)
79e53945
JB		 5352{
5353 struct intel_crtc *intel_crtc;
5354 struct drm_crtc *possible_crtc;
4ef69c7a 5355 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5356 struct drm_crtc *crtc = NULL;
5357 struct drm_device *dev = encoder->dev;
d2dff872 5358 struct drm_framebuffer *old_fb;
79e53945
JB		 5359 int i = -1;
5360
d2dff872
CW		 5361 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5362 connector->base.id, drm_get_connector_name(connector),
5363 encoder->base.id, drm_get_encoder_name(encoder));
5364
79e53945
JB		 5365 /*
5366 * Algorithm gets a little messy:
7a5e4805 5367 *
79e53945
JB		 5368 * - if the connector already has an assigned crtc, use it (but make
5369 * sure it's on first)
7a5e4805 5370 *
79e53945
JB		 5371 * - try to find the first unused crtc that can drive this connector,
5372 * and use that if we find one
79e53945
JB		 5373 */
5374
5375 /* See if we already have a CRTC for this connector */
5376 if (encoder->crtc) {
5377 crtc = encoder->crtc;
8261b191 5378
79e53945 5379 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5380 old->dpms_mode = intel_crtc->dpms_mode;
5381 old->load_detect_temp = false;
5382
5383 /* Make sure the crtc and connector are running */
79e53945 5384 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5385 struct drm_encoder_helper_funcs *encoder_funcs;
5386 struct drm_crtc_helper_funcs *crtc_funcs;
5387
79e53945
JB		 5388 crtc_funcs = crtc->helper_private;
5389 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5390
5391 encoder_funcs = encoder->helper_private;
79e53945
JB		 5392 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5393 }
8261b191 5394
7173188d 5395 return true;
79e53945
JB		 5396 }
5397
5398 /* Find an unused one (if possible) */
5399 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5400 i++;
5401 if (!(encoder->possible_crtcs & (1 << i)))
5402 continue;
5403 if (!possible_crtc->enabled) {
5404 crtc = possible_crtc;
5405 break;
5406 }
79e53945
JB		 5407 }
5408
5409 /*
5410 * If we didn't find an unused CRTC, don't use any.
5411 */
5412 if (!crtc) {
7173188d
CW		 5413 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5414 return false;
79e53945
JB		 5415 }
5416
5417 encoder->crtc = crtc;
c1c43977 5418 connector->encoder = encoder;
79e53945
JB		 5419
5420 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5421 old->dpms_mode = intel_crtc->dpms_mode;
5422 old->load_detect_temp = true;
d2dff872 5423 old->release_fb = NULL;
79e53945 5424
6492711d
CW		 5425 if (!mode)
5426 mode = &load_detect_mode;
79e53945 5427
d2dff872
CW		 5428 old_fb = crtc->fb;
5429
5430 /* We need a framebuffer large enough to accommodate all accesses
5431 * that the plane may generate whilst we perform load detection.
5432 * We can not rely on the fbcon either being present (we get called
5433 * during its initialisation to detect all boot displays, or it may
5434 * not even exist) or that it is large enough to satisfy the
5435 * requested mode.
5436 */
5437 crtc->fb = mode_fits_in_fbdev(dev, mode);
5438 if (crtc->fb == NULL) {
5439 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5440 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5441 old->release_fb = crtc->fb;
5442 } else
5443 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5444 if (IS_ERR(crtc->fb)) {
5445 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5446 crtc->fb = old_fb;
5447 return false;
79e53945 5448 }
79e53945 5449
d2dff872 5450 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5451 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5452 if (old->release_fb)
5453 old->release_fb->funcs->destroy(old->release_fb);
5454 crtc->fb = old_fb;
6492711d 5455 return false;
79e53945 5456 }
7173188d 5457
79e53945 5458 /* let the connector get through one full cycle before testing */
9d0498a2 5459 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5460
7173188d 5461 return true;
79e53945
JB		 5462}
5463
c1c43977 5464void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5465 struct drm_connector *connector,
5466 struct intel_load_detect_pipe *old)
79e53945 5467{
4ef69c7a 5468 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5469 struct drm_device *dev = encoder->dev;
5470 struct drm_crtc *crtc = encoder->crtc;
5471 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5472 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5473
d2dff872
CW		 5474 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5475 connector->base.id, drm_get_connector_name(connector),
5476 encoder->base.id, drm_get_encoder_name(encoder));
5477
8261b191 5478 if (old->load_detect_temp) {
c1c43977 5479 connector->encoder = NULL;
79e53945 5480 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5481
5482 if (old->release_fb)
5483 old->release_fb->funcs->destroy(old->release_fb);
5484
0622a53c 5485 return;
79e53945
JB		 5486 }
5487
c751ce4f 5488 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5489 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5490 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5491 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5492 }
5493}
5494
5495/* Returns the clock of the currently programmed mode of the given pipe. */
5496static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5497{
5498 struct drm_i915_private *dev_priv = dev->dev_private;
5499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5500 int pipe = intel_crtc->pipe;
548f245b 5501 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5502 u32 fp;
5503 intel_clock_t clock;
5504
5505 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5506 fp = I915_READ(FP0(pipe));
79e53945 5507 else
39adb7a5 5508 fp = I915_READ(FP1(pipe));
79e53945
JB		 5509
5510 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5511 if (IS_PINEVIEW(dev)) {
5512 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5513 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5514 } else {
5515 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5516 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5517 }
5518
a6c45cf0 5519 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5520 if (IS_PINEVIEW(dev))
5521 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5522 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5523 else
5524 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5525 DPLL_FPA01_P1_POST_DIV_SHIFT);
5526
5527 switch (dpll & DPLL_MODE_MASK) {
5528 case DPLLB_MODE_DAC_SERIAL:
5529 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5530 5 : 10;
5531 break;
5532 case DPLLB_MODE_LVDS:
5533 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5534 7 : 14;
5535 break;
5536 default:
28c97730 5537 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5538 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5539 return 0;
5540 }
5541
5542 /* XXX: Handle the 100Mhz refclk */
2177832f 5543 intel_clock(dev, 96000, &clock);
79e53945
JB		 5544 } else {
5545 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5546
5547 if (is_lvds) {
5548 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5549 DPLL_FPA01_P1_POST_DIV_SHIFT);
5550 clock.p2 = 14;
5551
5552 if ((dpll & PLL_REF_INPUT_MASK) ==
5553 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5554 /* XXX: might not be 66MHz */
2177832f 5555 intel_clock(dev, 66000, &clock);
79e53945 5556 } else
2177832f 5557 intel_clock(dev, 48000, &clock);
79e53945
JB		 5558 } else {
5559 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5560 clock.p1 = 2;
5561 else {
5562 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5563 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5564 }
5565 if (dpll & PLL_P2_DIVIDE_BY_4)
5566 clock.p2 = 4;
5567 else
5568 clock.p2 = 2;
5569
2177832f 5570 intel_clock(dev, 48000, &clock);
79e53945
JB		 5571 }
5572 }
5573
5574 /* XXX: It would be nice to validate the clocks, but we can't reuse
5575 * i830PllIsValid() because it relies on the xf86_config connector
5576 * configuration being accurate, which it isn't necessarily.
5577 */
5578
5579 return clock.dot;
5580}
5581
5582/** Returns the currently programmed mode of the given pipe. */
5583struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5584 struct drm_crtc *crtc)
5585{
548f245b 5586 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5588 int pipe = intel_crtc->pipe;
5589 struct drm_display_mode *mode;
548f245b
JB		 5590 int htot = I915_READ(HTOTAL(pipe));
5591 int hsync = I915_READ(HSYNC(pipe));
5592 int vtot = I915_READ(VTOTAL(pipe));
5593 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5594
5595 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5596 if (!mode)
5597 return NULL;
5598
5599 mode->clock = intel_crtc_clock_get(dev, crtc);
5600 mode->hdisplay = (htot & 0xffff) + 1;
5601 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5602 mode->hsync_start = (hsync & 0xffff) + 1;
5603 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5604 mode->vdisplay = (vtot & 0xffff) + 1;
5605 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5606 mode->vsync_start = (vsync & 0xffff) + 1;
5607 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5608
5609 drm_mode_set_name(mode);
79e53945
JB		 5610
5611 return mode;
5612}
5613
652c393a
JB		 5614#define GPU_IDLE_TIMEOUT 500 /* ms */
5615
5616/* When this timer fires, we've been idle for awhile */
5617static void intel_gpu_idle_timer(unsigned long arg)
5618{
5619 struct drm_device *dev = (struct drm_device *)arg;
5620 drm_i915_private_t *dev_priv = dev->dev_private;
5621
ff7ea4c0
CW		 5622 if (!list_empty(&dev_priv->mm.active_list)) {
5623 /* Still processing requests, so just re-arm the timer. */
5624 mod_timer(&dev_priv->idle_timer, jiffies +
5625 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5626 return;
5627 }
652c393a 5628
ff7ea4c0 5629 dev_priv->busy = false;
01dfba93 5630 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5631}
5632
652c393a
JB		 5633#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5634
5635static void intel_crtc_idle_timer(unsigned long arg)
5636{
5637 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5638 struct drm_crtc *crtc = &intel_crtc->base;
5639 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5640 struct intel_framebuffer *intel_fb;
652c393a 5641
ff7ea4c0
CW		 5642 intel_fb = to_intel_framebuffer(crtc->fb);
5643 if (intel_fb && intel_fb->obj->active) {
5644 /* The framebuffer is still being accessed by the GPU. */
5645 mod_timer(&intel_crtc->idle_timer, jiffies +
5646 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5647 return;
5648 }
652c393a 5649
ff7ea4c0 5650 intel_crtc->busy = false;
01dfba93 5651 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5652}
5653
3dec0095 5654static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5655{
5656 struct drm_device *dev = crtc->dev;
5657 drm_i915_private_t *dev_priv = dev->dev_private;
5658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5659 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5660 int dpll_reg = DPLL(pipe);
5661 int dpll;
652c393a 5662
bad720ff 5663 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5664 return;
5665
5666 if (!dev_priv->lvds_downclock_avail)
5667 return;
5668
dbdc6479 5669 dpll = I915_READ(dpll_reg);
652c393a 5670 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5671 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 5672
8ac5a6d5 5673 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 5674
5675 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5676 I915_WRITE(dpll_reg, dpll);
9d0498a2 5677 intel_wait_for_vblank(dev, pipe);
dbdc6479 5678
652c393a
JB		 5679 dpll = I915_READ(dpll_reg);
5680 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5681 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 5682 }
5683
5684 /* Schedule downclock */
3dec0095
DV		 5685 mod_timer(&intel_crtc->idle_timer, jiffies +
5686 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 5687}
5688
5689static void intel_decrease_pllclock(struct drm_crtc *crtc)
5690{
5691 struct drm_device *dev = crtc->dev;
5692 drm_i915_private_t *dev_priv = dev->dev_private;
5693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 5694
bad720ff 5695 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5696 return;
5697
5698 if (!dev_priv->lvds_downclock_avail)
5699 return;
5700
5701 /*
5702 * Since this is called by a timer, we should never get here in
5703 * the manual case.
5704 */
5705 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 5706 int pipe = intel_crtc->pipe;
5707 int dpll_reg = DPLL(pipe);
5708 int dpll;
f6e5b160 5709
44d98a61 5710 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 5711
8ac5a6d5 5712 assert_panel_unlocked(dev_priv, pipe);
652c393a 5713
dc257cf1 5714 dpll = I915_READ(dpll_reg);
652c393a
JB		 5715 dpll |= DISPLAY_RATE_SELECT_FPA1;
5716 I915_WRITE(dpll_reg, dpll);
9d0498a2 5717 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 5718 dpll = I915_READ(dpll_reg);
5719 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 5720 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 5721 }
5722
5723}
5724
5725/**
5726 * intel_idle_update - adjust clocks for idleness
5727 * @work: work struct
5728 *
5729 * Either the GPU or display (or both) went idle. Check the busy status
5730 * here and adjust the CRTC and GPU clocks as necessary.
5731 */
5732static void intel_idle_update(struct work_struct *work)
5733{
5734 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5735 idle_work);
5736 struct drm_device *dev = dev_priv->dev;
5737 struct drm_crtc *crtc;
5738 struct intel_crtc *intel_crtc;
5739
5740 if (!i915_powersave)
5741 return;
5742
5743 mutex_lock(&dev->struct_mutex);
5744
7648fa99
JB		 5745 i915_update_gfx_val(dev_priv);
5746
652c393a
JB		 5747 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5748 /* Skip inactive CRTCs */
5749 if (!crtc->fb)
5750 continue;
5751
5752 intel_crtc = to_intel_crtc(crtc);
5753 if (!intel_crtc->busy)
5754 intel_decrease_pllclock(crtc);
5755 }
5756
45ac22c8 5757
652c393a
JB		 5758 mutex_unlock(&dev->struct_mutex);
5759}
5760
5761/**
5762 * intel_mark_busy - mark the GPU and possibly the display busy
5763 * @dev: drm device
5764 * @obj: object we're operating on
5765 *
5766 * Callers can use this function to indicate that the GPU is busy processing
5767 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5768 * buffer), we'll also mark the display as busy, so we know to increase its
5769 * clock frequency.
5770 */
05394f39 5771void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 5772{
5773 drm_i915_private_t *dev_priv = dev->dev_private;
5774 struct drm_crtc *crtc = NULL;
5775 struct intel_framebuffer *intel_fb;
5776 struct intel_crtc *intel_crtc;
5777
5e17ee74
ZW		 5778 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5779 return;
5780
9104183d
CW		 5781 if (!dev_priv->busy) {
5782 intel_sanitize_pm(dev);
28cf798f 5783 dev_priv->busy = true;
9104183d 5784 } else
28cf798f
CW		 5785 mod_timer(&dev_priv->idle_timer, jiffies +
5786 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a 5787
acb87dfb
CW		 5788 if (obj == NULL)
5789 return;
5790
652c393a
JB		 5791 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5792 if (!crtc->fb)
5793 continue;
5794
5795 intel_crtc = to_intel_crtc(crtc);
5796 intel_fb = to_intel_framebuffer(crtc->fb);
5797 if (intel_fb->obj == obj) {
5798 if (!intel_crtc->busy) {
5799 /* Non-busy -> busy, upclock */
3dec0095 5800 intel_increase_pllclock(crtc);
652c393a
JB		 5801 intel_crtc->busy = true;
5802 } else {
5803 /* Busy -> busy, put off timer */
5804 mod_timer(&intel_crtc->idle_timer, jiffies +
5805 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5806 }
5807 }
5808 }
5809}
5810
79e53945
JB		 5811static void intel_crtc_destroy(struct drm_crtc *crtc)
5812{
5813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 5814 struct drm_device *dev = crtc->dev;
5815 struct intel_unpin_work *work;
5816 unsigned long flags;
5817
5818 spin_lock_irqsave(&dev->event_lock, flags);
5819 work = intel_crtc->unpin_work;
5820 intel_crtc->unpin_work = NULL;
5821 spin_unlock_irqrestore(&dev->event_lock, flags);
5822
5823 if (work) {
5824 cancel_work_sync(&work->work);
5825 kfree(work);
5826 }
79e53945
JB		 5827
5828 drm_crtc_cleanup(crtc);
67e77c5a 5829
79e53945
JB		 5830 kfree(intel_crtc);
5831}
5832
6b95a207
KH		 5833static void intel_unpin_work_fn(struct work_struct *__work)
5834{
5835 struct intel_unpin_work *work =
5836 container_of(__work, struct intel_unpin_work, work);
5837
5838 mutex_lock(&work->dev->struct_mutex);
1690e1eb 5839 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 5840 drm_gem_object_unreference(&work->pending_flip_obj->base);
5841 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 5842
7782de3b 5843 intel_update_fbc(work->dev);
6b95a207
KH		 5844 mutex_unlock(&work->dev->struct_mutex);
5845 kfree(work);
5846}
5847
1afe3e9d 5848static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 5849 struct drm_crtc *crtc)
6b95a207
KH		 5850{
5851 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 5852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5853 struct intel_unpin_work *work;
05394f39 5854 struct drm_i915_gem_object *obj;
6b95a207 5855 struct drm_pending_vblank_event *e;
49b14a5c 5856 struct timeval tnow, tvbl;
6b95a207
KH		 5857 unsigned long flags;
5858
5859 /* Ignore early vblank irqs */
5860 if (intel_crtc == NULL)
5861 return;
5862
49b14a5c
MK		 5863 do_gettimeofday(&tnow);
5864
6b95a207
KH		 5865 spin_lock_irqsave(&dev->event_lock, flags);
5866 work = intel_crtc->unpin_work;
5867 if (work == NULL || !work->pending) {
5868 spin_unlock_irqrestore(&dev->event_lock, flags);
5869 return;
5870 }
5871
5872 intel_crtc->unpin_work = NULL;
6b95a207
KH		 5873
5874 if (work->event) {
5875 e = work->event;
49b14a5c 5876 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 5877
5878 /* Called before vblank count and timestamps have
5879 * been updated for the vblank interval of flip
5880 * completion? Need to increment vblank count and
5881 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 5882 * to account for this. We assume this happened if we
5883 * get called over 0.9 frame durations after the last
5884 * timestamped vblank.
5885 *
5886 * This calculation can not be used with vrefresh rates
5887 * below 5Hz (10Hz to be on the safe side) without
5888 * promoting to 64 integers.
0af7e4df 5889 */
49b14a5c
MK		 5890 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5891 9 * crtc->framedur_ns) {
0af7e4df 5892 e->event.sequence++;
49b14a5c
MK		 5893 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5894 crtc->framedur_ns);
0af7e4df
MK		 5895 }
5896
49b14a5c
MK		 5897 e->event.tv_sec = tvbl.tv_sec;
5898 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 5899
6b95a207
KH		 5900 list_add_tail(&e->base.link,
5901 &e->base.file_priv->event_list);
5902 wake_up_interruptible(&e->base.file_priv->event_wait);
5903 }
5904
0af7e4df
MK		 5905 drm_vblank_put(dev, intel_crtc->pipe);
5906
6b95a207
KH		 5907 spin_unlock_irqrestore(&dev->event_lock, flags);
5908
05394f39 5909 obj = work->old_fb_obj;
d9e86c0e 5910
e59f2bac 5911 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 5912 &obj->pending_flip.counter);
5913 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 5914 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 5915
6b95a207 5916 schedule_work(&work->work);
e5510fac
JB		 5917
5918 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 5919}
5920
1afe3e9d
JB		 5921void intel_finish_page_flip(struct drm_device *dev, int pipe)
5922{
5923 drm_i915_private_t *dev_priv = dev->dev_private;
5924 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5925
49b14a5c 5926 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 5927}
5928
5929void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5930{
5931 drm_i915_private_t *dev_priv = dev->dev_private;
5932 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5933
49b14a5c 5934 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 5935}
5936
6b95a207
KH		 5937void intel_prepare_page_flip(struct drm_device *dev, int plane)
5938{
5939 drm_i915_private_t *dev_priv = dev->dev_private;
5940 struct intel_crtc *intel_crtc =
5941 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5942 unsigned long flags;
5943
5944 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 5945 if (intel_crtc->unpin_work) {
4e5359cd
SF		 5946 if ((++intel_crtc->unpin_work->pending) > 1)
5947 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 5948 } else {
5949 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5950 }
6b95a207
KH		 5951 spin_unlock_irqrestore(&dev->event_lock, flags);
5952}
5953
8c9f3aaf
JB		 5954static int intel_gen2_queue_flip(struct drm_device *dev,
5955 struct drm_crtc *crtc,
5956 struct drm_framebuffer *fb,
5957 struct drm_i915_gem_object *obj)
5958{
5959 struct drm_i915_private *dev_priv = dev->dev_private;
5960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5961 unsigned long offset;
5962 u32 flip_mask;
6d90c952 5963 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5964 int ret;
5965
6d90c952 5966 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5967 if (ret)
83d4092b 5968 goto err;
8c9f3aaf
JB		 5969
5970 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 5971 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf 5972
6d90c952 5973 ret = intel_ring_begin(ring, 6);
8c9f3aaf 5974 if (ret)
83d4092b 5975 goto err_unpin;
8c9f3aaf
JB		 5976
5977 /* Can't queue multiple flips, so wait for the previous
5978 * one to finish before executing the next.
5979 */
5980 if (intel_crtc->plane)
5981 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5982 else
5983 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 5984 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5985 intel_ring_emit(ring, MI_NOOP);
5986 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5987 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5988 intel_ring_emit(ring, fb->pitches[0]);
5989 intel_ring_emit(ring, obj->gtt_offset + offset);
5990 intel_ring_emit(ring, 0); /* aux display base address, unused */
5991 intel_ring_advance(ring);
83d4092b
CW		 5992 return 0;
5993
5994err_unpin:
5995 intel_unpin_fb_obj(obj);
5996err:
8c9f3aaf
JB		 5997 return ret;
5998}
5999
6000static int intel_gen3_queue_flip(struct drm_device *dev,
6001 struct drm_crtc *crtc,
6002 struct drm_framebuffer *fb,
6003 struct drm_i915_gem_object *obj)
6004{
6005 struct drm_i915_private *dev_priv = dev->dev_private;
6006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6007 unsigned long offset;
6008 u32 flip_mask;
6d90c952 6009 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6010 int ret;
6011
6d90c952 6012 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6013 if (ret)
83d4092b 6014 goto err;
8c9f3aaf
JB		 6015
6016 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 6017 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf 6018
6d90c952 6019 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6020 if (ret)
83d4092b 6021 goto err_unpin;
8c9f3aaf
JB		 6022
6023 if (intel_crtc->plane)
6024 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6025 else
6026 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6027 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6028 intel_ring_emit(ring, MI_NOOP);
6029 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6030 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6031 intel_ring_emit(ring, fb->pitches[0]);
6032 intel_ring_emit(ring, obj->gtt_offset + offset);
6033 intel_ring_emit(ring, MI_NOOP);
6034
6035 intel_ring_advance(ring);
83d4092b
CW		 6036 return 0;
6037
6038err_unpin:
6039 intel_unpin_fb_obj(obj);
6040err:
8c9f3aaf
JB		 6041 return ret;
6042}
6043
6044static int intel_gen4_queue_flip(struct drm_device *dev,
6045 struct drm_crtc *crtc,
6046 struct drm_framebuffer *fb,
6047 struct drm_i915_gem_object *obj)
6048{
6049 struct drm_i915_private *dev_priv = dev->dev_private;
6050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6051 uint32_t pf, pipesrc;
6d90c952 6052 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6053 int ret;
6054
6d90c952 6055 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6056 if (ret)
83d4092b 6057 goto err;
8c9f3aaf 6058
6d90c952 6059 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6060 if (ret)
83d4092b 6061 goto err_unpin;
8c9f3aaf
JB		 6062
6063 /* i965+ uses the linear or tiled offsets from the
6064 * Display Registers (which do not change across a page-flip)
6065 * so we need only reprogram the base address.
6066 */
6d90c952
DV		 6067 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6068 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6069 intel_ring_emit(ring, fb->pitches[0]);
6070 intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
8c9f3aaf
JB		 6071
6072 /* XXX Enabling the panel-fitter across page-flip is so far
6073 * untested on non-native modes, so ignore it for now.
6074 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6075 */
6076 pf = 0;
6077 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6078 intel_ring_emit(ring, pf | pipesrc);
6079 intel_ring_advance(ring);
83d4092b
CW		 6080 return 0;
6081
6082err_unpin:
6083 intel_unpin_fb_obj(obj);
6084err:
8c9f3aaf
JB		 6085 return ret;
6086}
6087
6088static int intel_gen6_queue_flip(struct drm_device *dev,
6089 struct drm_crtc *crtc,
6090 struct drm_framebuffer *fb,
6091 struct drm_i915_gem_object *obj)
6092{
6093 struct drm_i915_private *dev_priv = dev->dev_private;
6094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6095 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6096 uint32_t pf, pipesrc;
6097 int ret;
6098
6d90c952 6099 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6100 if (ret)
83d4092b 6101 goto err;
8c9f3aaf 6102
6d90c952 6103 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6104 if (ret)
83d4092b 6105 goto err_unpin;
8c9f3aaf 6106
6d90c952
DV		 6107 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6108 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6109 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6110 intel_ring_emit(ring, obj->gtt_offset);
8c9f3aaf 6111
dc257cf1
DV		 6112 /* Contrary to the suggestions in the documentation,
6113 * "Enable Panel Fitter" does not seem to be required when page
6114 * flipping with a non-native mode, and worse causes a normal
6115 * modeset to fail.
6116 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6117 */
6118 pf = 0;
8c9f3aaf 6119 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6120 intel_ring_emit(ring, pf | pipesrc);
6121 intel_ring_advance(ring);
83d4092b
CW		 6122 return 0;
6123
6124err_unpin:
6125 intel_unpin_fb_obj(obj);
6126err:
8c9f3aaf
JB		 6127 return ret;
6128}
6129
7c9017e5
JB		 6130/*
6131 * On gen7 we currently use the blit ring because (in early silicon at least)
6132 * the render ring doesn't give us interrpts for page flip completion, which
6133 * means clients will hang after the first flip is queued. Fortunately the
6134 * blit ring generates interrupts properly, so use it instead.
6135 */
6136static int intel_gen7_queue_flip(struct drm_device *dev,
6137 struct drm_crtc *crtc,
6138 struct drm_framebuffer *fb,
6139 struct drm_i915_gem_object *obj)
6140{
6141 struct drm_i915_private *dev_priv = dev->dev_private;
6142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6143 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6144 int ret;
6145
6146 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6147 if (ret)
83d4092b 6148 goto err;
7c9017e5
JB		 6149
6150 ret = intel_ring_begin(ring, 4);
6151 if (ret)
83d4092b 6152 goto err_unpin;
7c9017e5
JB		 6153
6154 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 6155 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 6156 intel_ring_emit(ring, (obj->gtt_offset));
6157 intel_ring_emit(ring, (MI_NOOP));
6158 intel_ring_advance(ring);
83d4092b
CW		 6159 return 0;
6160
6161err_unpin:
6162 intel_unpin_fb_obj(obj);
6163err:
7c9017e5
JB		 6164 return ret;
6165}
6166
8c9f3aaf
JB		 6167static int intel_default_queue_flip(struct drm_device *dev,
6168 struct drm_crtc *crtc,
6169 struct drm_framebuffer *fb,
6170 struct drm_i915_gem_object *obj)
6171{
6172 return -ENODEV;
6173}
6174
6b95a207
KH		 6175static int intel_crtc_page_flip(struct drm_crtc *crtc,
6176 struct drm_framebuffer *fb,
6177 struct drm_pending_vblank_event *event)
6178{
6179 struct drm_device *dev = crtc->dev;
6180 struct drm_i915_private *dev_priv = dev->dev_private;
6181 struct intel_framebuffer *intel_fb;
05394f39 6182 struct drm_i915_gem_object *obj;
6b95a207
KH		 6183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6184 struct intel_unpin_work *work;
8c9f3aaf 6185 unsigned long flags;
52e68630 6186 int ret;
6b95a207
KH		 6187
6188 work = kzalloc(sizeof *work, GFP_KERNEL);
6189 if (work == NULL)
6190 return -ENOMEM;
6191
6b95a207
KH		 6192 work->event = event;
6193 work->dev = crtc->dev;
6194 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6195 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6196 INIT_WORK(&work->work, intel_unpin_work_fn);
6197
7317c75e
JB		 6198 ret = drm_vblank_get(dev, intel_crtc->pipe);
6199 if (ret)
6200 goto free_work;
6201
6b95a207
KH		 6202 /* We borrow the event spin lock for protecting unpin_work */
6203 spin_lock_irqsave(&dev->event_lock, flags);
6204 if (intel_crtc->unpin_work) {
6205 spin_unlock_irqrestore(&dev->event_lock, flags);
6206 kfree(work);
7317c75e 6207 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6208
6209 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6210 return -EBUSY;
6211 }
6212 intel_crtc->unpin_work = work;
6213 spin_unlock_irqrestore(&dev->event_lock, flags);
6214
6215 intel_fb = to_intel_framebuffer(fb);
6216 obj = intel_fb->obj;
6217
468f0b44 6218 mutex_lock(&dev->struct_mutex);
6b95a207 6219
75dfca80 6220 /* Reference the objects for the scheduled work. */
05394f39
CW		 6221 drm_gem_object_reference(&work->old_fb_obj->base);
6222 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6223
6224 crtc->fb = fb;
96b099fd 6225
e1f99ce6 6226 work->pending_flip_obj = obj;
e1f99ce6 6227
4e5359cd
SF		 6228 work->enable_stall_check = true;
6229
e1f99ce6
CW		 6230 /* Block clients from rendering to the new back buffer until
6231 * the flip occurs and the object is no longer visible.
6232 */
05394f39 6233 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6234
8c9f3aaf
JB		 6235 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6236 if (ret)
6237 goto cleanup_pending;
6b95a207 6238
7782de3b 6239 intel_disable_fbc(dev);
acb87dfb 6240 intel_mark_busy(dev, obj);
6b95a207
KH		 6241 mutex_unlock(&dev->struct_mutex);
6242
e5510fac
JB		 6243 trace_i915_flip_request(intel_crtc->plane, obj);
6244
6b95a207 6245 return 0;
96b099fd 6246
8c9f3aaf
JB		 6247cleanup_pending:
6248 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6249 drm_gem_object_unreference(&work->old_fb_obj->base);
6250 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6251 mutex_unlock(&dev->struct_mutex);
6252
6253 spin_lock_irqsave(&dev->event_lock, flags);
6254 intel_crtc->unpin_work = NULL;
6255 spin_unlock_irqrestore(&dev->event_lock, flags);
6256
7317c75e
JB		 6257 drm_vblank_put(dev, intel_crtc->pipe);
6258free_work:
96b099fd
CW		 6259 kfree(work);
6260
6261 return ret;
6b95a207
KH		 6262}
6263
47f1c6c9
CW		 6264static void intel_sanitize_modesetting(struct drm_device *dev,
6265 int pipe, int plane)
6266{
6267 struct drm_i915_private *dev_priv = dev->dev_private;
6268 u32 reg, val;
a9dcf84b 6269 int i;
47f1c6c9 6270
f47166d2 6271 /* Clear any frame start delays used for debugging left by the BIOS */
a9dcf84b
DV		 6272 for_each_pipe(i) {
6273 reg = PIPECONF(i);
f47166d2
CW		 6274 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6275 }
6276
47f1c6c9
CW		 6277 if (HAS_PCH_SPLIT(dev))
6278 return;
6279
6280 /* Who knows what state these registers were left in by the BIOS or
6281 * grub?
6282 *
6283 * If we leave the registers in a conflicting state (e.g. with the
6284 * display plane reading from the other pipe than the one we intend
6285 * to use) then when we attempt to teardown the active mode, we will
6286 * not disable the pipes and planes in the correct order -- leaving
6287 * a plane reading from a disabled pipe and possibly leading to
6288 * undefined behaviour.
6289 */
6290
6291 reg = DSPCNTR(plane);
6292 val = I915_READ(reg);
6293
6294 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6295 return;
6296 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6297 return;
6298
6299 /* This display plane is active and attached to the other CPU pipe. */
6300 pipe = !pipe;
6301
6302 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6303 intel_disable_plane(dev_priv, plane, pipe);
6304 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6305}
79e53945 6306
f6e5b160
CW		 6307static void intel_crtc_reset(struct drm_crtc *crtc)
6308{
6309 struct drm_device *dev = crtc->dev;
6310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6311
6312 /* Reset flags back to the 'unknown' status so that they
6313 * will be correctly set on the initial modeset.
6314 */
6315 intel_crtc->dpms_mode = -1;
6316
6317 /* We need to fix up any BIOS configuration that conflicts with
6318 * our expectations.
6319 */
6320 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6321}
6322
6323static struct drm_crtc_helper_funcs intel_helper_funcs = {
6324 .dpms = intel_crtc_dpms,
6325 .mode_fixup = intel_crtc_mode_fixup,
6326 .mode_set = intel_crtc_mode_set,
6327 .mode_set_base = intel_pipe_set_base,
6328 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6329 .load_lut = intel_crtc_load_lut,
6330 .disable = intel_crtc_disable,
6331};
6332
6333static const struct drm_crtc_funcs intel_crtc_funcs = {
6334 .reset = intel_crtc_reset,
6335 .cursor_set = intel_crtc_cursor_set,
6336 .cursor_move = intel_crtc_cursor_move,
6337 .gamma_set = intel_crtc_gamma_set,
6338 .set_config = drm_crtc_helper_set_config,
6339 .destroy = intel_crtc_destroy,
6340 .page_flip = intel_crtc_page_flip,
6341};
6342
ee7b9f93
JB		 6343static void intel_pch_pll_init(struct drm_device *dev)
6344{
6345 drm_i915_private_t *dev_priv = dev->dev_private;
6346 int i;
6347
6348 if (dev_priv->num_pch_pll == 0) {
6349 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6350 return;
6351 }
6352
6353 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6354 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6355 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6356 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6357 }
6358}
6359
b358d0a6 6360static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6361{
22fd0fab 6362 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6363 struct intel_crtc *intel_crtc;
6364 int i;
6365
6366 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6367 if (intel_crtc == NULL)
6368 return;
6369
6370 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6371
6372 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6373 for (i = 0; i < 256; i++) {
6374 intel_crtc->lut_r[i] = i;
6375 intel_crtc->lut_g[i] = i;
6376 intel_crtc->lut_b[i] = i;
6377 }
6378
80824003
JB		 6379 /* Swap pipes & planes for FBC on pre-965 */
6380 intel_crtc->pipe = pipe;
6381 intel_crtc->plane = pipe;
e2e767ab 6382 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6383 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6384 intel_crtc->plane = !pipe;
80824003
JB		 6385 }
6386
22fd0fab
JB		 6387 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6388 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6389 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6390 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6391
5d1d0cc8 6392 intel_crtc_reset(&intel_crtc->base);
04dbff52 6393 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 6394 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 6395
6396 if (HAS_PCH_SPLIT(dev)) {
6397 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6398 intel_helper_funcs.commit = ironlake_crtc_commit;
6399 } else {
6400 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6401 intel_helper_funcs.commit = i9xx_crtc_commit;
6402 }
6403
79e53945
JB		 6404 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6405
652c393a
JB		 6406 intel_crtc->busy = false;
6407
6408 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6409 (unsigned long)intel_crtc);
79e53945
JB		 6410}
6411
08d7b3d1 6412int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6413 struct drm_file *file)
08d7b3d1 6414{
08d7b3d1 6415 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6416 struct drm_mode_object *drmmode_obj;
6417 struct intel_crtc *crtc;
08d7b3d1 6418
1cff8f6b
DV		 6419 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6420 return -ENODEV;
08d7b3d1 6421
c05422d5
DV		 6422 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6423 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6424
c05422d5 6425 if (!drmmode_obj) {
08d7b3d1
CW		 6426 DRM_ERROR("no such CRTC id\n");
6427 return -EINVAL;
6428 }
6429
c05422d5
DV		 6430 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6431 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6432
c05422d5 6433 return 0;
08d7b3d1
CW		 6434}
6435
c5e4df33 6436static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6437{
4ef69c7a 6438 struct intel_encoder *encoder;
79e53945 6439 int index_mask = 0;
79e53945
JB		 6440 int entry = 0;
6441
4ef69c7a
CW		 6442 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6443 if (type_mask & encoder->clone_mask)
79e53945
JB		 6444 index_mask |= (1 << entry);
6445 entry++;
6446 }
4ef69c7a 6447
79e53945
JB		 6448 return index_mask;
6449}
6450
4d302442
CW		 6451static bool has_edp_a(struct drm_device *dev)
6452{
6453 struct drm_i915_private *dev_priv = dev->dev_private;
6454
6455 if (!IS_MOBILE(dev))
6456 return false;
6457
6458 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6459 return false;
6460
6461 if (IS_GEN5(dev) &&
6462 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6463 return false;
6464
6465 return true;
6466}
6467
79e53945
JB		 6468static void intel_setup_outputs(struct drm_device *dev)
6469{
725e30ad 6470 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6471 struct intel_encoder *encoder;
cb0953d7 6472 bool dpd_is_edp = false;
f3cfcba6 6473 bool has_lvds;
79e53945 6474
f3cfcba6 6475 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 6476 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6477 /* disable the panel fitter on everything but LVDS */
6478 I915_WRITE(PFIT_CONTROL, 0);
6479 }
79e53945 6480
bad720ff 6481 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6482 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6483
4d302442 6484 if (has_edp_a(dev))
32f9d658
ZW		 6485 intel_dp_init(dev, DP_A);
6486
cb0953d7
AJ		 6487 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6488 intel_dp_init(dev, PCH_DP_D);
6489 }
6490
6491 intel_crt_init(dev);
6492
0e72a5b5
ED		 6493 if (IS_HASWELL(dev)) {
6494 int found;
6495
6496 /* Haswell uses DDI functions to detect digital outputs */
6497 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6498 /* DDI A only supports eDP */
6499 if (found)
6500 intel_ddi_init(dev, PORT_A);
6501
6502 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6503 * register */
6504 found = I915_READ(SFUSE_STRAP);
6505
6506 if (found & SFUSE_STRAP_DDIB_DETECTED)
6507 intel_ddi_init(dev, PORT_B);
6508 if (found & SFUSE_STRAP_DDIC_DETECTED)
6509 intel_ddi_init(dev, PORT_C);
6510 if (found & SFUSE_STRAP_DDID_DETECTED)
6511 intel_ddi_init(dev, PORT_D);
6512 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 6513 int found;
6514
30ad48b7 6515 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 6516 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 6517 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7
ZW		 6518 if (!found)
6519 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6520 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6521 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6522 }
6523
6524 if (I915_READ(HDMIC) & PORT_DETECTED)
6525 intel_hdmi_init(dev, HDMIC);
6526
6527 if (I915_READ(HDMID) & PORT_DETECTED)
6528 intel_hdmi_init(dev, HDMID);
6529
5eb08b69
ZW		 6530 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6531 intel_dp_init(dev, PCH_DP_C);
6532
cb0953d7 6533 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6534 intel_dp_init(dev, PCH_DP_D);
6535
103a196f 6536 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6537 bool found = false;
7d57382e 6538
725e30ad 6539 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6540 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 6541 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 6542 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6543 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6544 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6545 }
27185ae1 6546
b01f2c3a
JB		 6547 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6548 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6549 intel_dp_init(dev, DP_B);
b01f2c3a 6550 }
725e30ad 6551 }
13520b05
KH		 6552
6553 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6554
b01f2c3a
JB		 6555 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6556 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 6557 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 6558 }
27185ae1
ML		 6559
6560 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6561
b01f2c3a
JB		 6562 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6563 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6564 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6565 }
6566 if (SUPPORTS_INTEGRATED_DP(dev)) {
6567 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6568 intel_dp_init(dev, DP_C);
b01f2c3a 6569 }
725e30ad 6570 }
27185ae1 6571
b01f2c3a
JB		 6572 if (SUPPORTS_INTEGRATED_DP(dev) &&
6573 (I915_READ(DP_D) & DP_DETECTED)) {
6574 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6575 intel_dp_init(dev, DP_D);
b01f2c3a 6576 }
bad720ff 6577 } else if (IS_GEN2(dev))
79e53945
JB		 6578 intel_dvo_init(dev);
6579
103a196f 6580 if (SUPPORTS_TV(dev))
79e53945
JB		 6581 intel_tv_init(dev);
6582
4ef69c7a
CW		 6583 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6584 encoder->base.possible_crtcs = encoder->crtc_mask;
6585 encoder->base.possible_clones =
6586 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6587 }
47356eb6 6588
2c7111db
CW		 6589 /* disable all the possible outputs/crtcs before entering KMS mode */
6590 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 6591
6592 if (HAS_PCH_SPLIT(dev))
6593 ironlake_init_pch_refclk(dev);
79e53945
JB		 6594}
6595
6596static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6597{
6598 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6599
6600 drm_framebuffer_cleanup(fb);
05394f39 6601 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6602
6603 kfree(intel_fb);
6604}
6605
6606static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6607 struct drm_file *file,
79e53945
JB		 6608 unsigned int *handle)
6609{
6610 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6611 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6612
05394f39 6613 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6614}
6615
6616static const struct drm_framebuffer_funcs intel_fb_funcs = {
6617 .destroy = intel_user_framebuffer_destroy,
6618 .create_handle = intel_user_framebuffer_create_handle,
6619};
6620
38651674
DA		 6621int intel_framebuffer_init(struct drm_device *dev,
6622 struct intel_framebuffer *intel_fb,
308e5bcb 6623 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 6624 struct drm_i915_gem_object *obj)
79e53945 6625{
79e53945
JB		 6626 int ret;
6627
05394f39 6628 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6629 return -EINVAL;
6630
308e5bcb 6631 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 6632 return -EINVAL;
6633
308e5bcb 6634 switch (mode_cmd->pixel_format) {
04b3924d
VS		 6635 case DRM_FORMAT_RGB332:
6636 case DRM_FORMAT_RGB565:
6637 case DRM_FORMAT_XRGB8888:
b250da79 6638 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 6639 case DRM_FORMAT_ARGB8888:
6640 case DRM_FORMAT_XRGB2101010:
6641 case DRM_FORMAT_ARGB2101010:
308e5bcb 6642 /* RGB formats are common across chipsets */
b5626747 6643 break;
04b3924d
VS		 6644 case DRM_FORMAT_YUYV:
6645 case DRM_FORMAT_UYVY:
6646 case DRM_FORMAT_YVYU:
6647 case DRM_FORMAT_VYUY:
57cd6508
CW		 6648 break;
6649 default:
aca25848
ED		 6650 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6651 mode_cmd->pixel_format);
57cd6508
CW		 6652 return -EINVAL;
6653 }
6654
79e53945
JB		 6655 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6656 if (ret) {
6657 DRM_ERROR("framebuffer init failed %d\n", ret);
6658 return ret;
6659 }
6660
6661 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6662 intel_fb->obj = obj;
79e53945
JB		 6663 return 0;
6664}
6665
79e53945
JB		 6666static struct drm_framebuffer *
6667intel_user_framebuffer_create(struct drm_device *dev,
6668 struct drm_file *filp,
308e5bcb 6669 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 6670{
05394f39 6671 struct drm_i915_gem_object *obj;
79e53945 6672
308e5bcb
JB		 6673 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6674 mode_cmd->handles[0]));
c8725226 6675 if (&obj->base == NULL)
cce13ff7 6676 return ERR_PTR(-ENOENT);
79e53945 6677
d2dff872 6678 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6679}
6680
79e53945 6681static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6682 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6683 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6684};
6685
e70236a8
JB		 6686/* Set up chip specific display functions */
6687static void intel_init_display(struct drm_device *dev)
6688{
6689 struct drm_i915_private *dev_priv = dev->dev_private;
6690
6691 /* We always want a DPMS function */
f564048e 6692 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 6693 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 6694 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
ee7b9f93 6695 dev_priv->display.off = ironlake_crtc_off;
17638cd6 6696 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 6697 } else {
e70236a8 6698 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 6699 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
ee7b9f93 6700 dev_priv->display.off = i9xx_crtc_off;
17638cd6 6701 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 6702 }
e70236a8 6703
e70236a8 6704 /* Returns the core display clock speed */
25eb05fc
JB		 6705 if (IS_VALLEYVIEW(dev))
6706 dev_priv->display.get_display_clock_speed =
6707 valleyview_get_display_clock_speed;
6708 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 6709 dev_priv->display.get_display_clock_speed =
6710 i945_get_display_clock_speed;
6711 else if (IS_I915G(dev))
6712 dev_priv->display.get_display_clock_speed =
6713 i915_get_display_clock_speed;
f2b115e6 6714 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 6715 dev_priv->display.get_display_clock_speed =
6716 i9xx_misc_get_display_clock_speed;
6717 else if (IS_I915GM(dev))
6718 dev_priv->display.get_display_clock_speed =
6719 i915gm_get_display_clock_speed;
6720 else if (IS_I865G(dev))
6721 dev_priv->display.get_display_clock_speed =
6722 i865_get_display_clock_speed;
f0f8a9ce 6723 else if (IS_I85X(dev))
e70236a8
JB		 6724 dev_priv->display.get_display_clock_speed =
6725 i855_get_display_clock_speed;
6726 else /* 852, 830 */
6727 dev_priv->display.get_display_clock_speed =
6728 i830_get_display_clock_speed;
6729
7f8a8569 6730 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 6731 if (IS_GEN5(dev)) {
674cf967 6732 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 6733 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 6734 } else if (IS_GEN6(dev)) {
674cf967 6735 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 6736 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 6737 } else if (IS_IVYBRIDGE(dev)) {
6738 /* FIXME: detect B0+ stepping and use auto training */
6739 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 6740 dev_priv->display.write_eld = ironlake_write_eld;
c82e4d26
ED		 6741 } else if (IS_HASWELL(dev)) {
6742 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
4abb3c8c 6743 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 6744 } else
6745 dev_priv->display.update_wm = NULL;
ceb04246 6746 } else if (IS_VALLEYVIEW(dev)) {
575155a9
JB		 6747 dev_priv->display.force_wake_get = vlv_force_wake_get;
6748 dev_priv->display.force_wake_put = vlv_force_wake_put;
6067aaea 6749 } else if (IS_G4X(dev)) {
e0dac65e 6750 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 6751 }
8c9f3aaf
JB		 6752
6753 /* Default just returns -ENODEV to indicate unsupported */
6754 dev_priv->display.queue_flip = intel_default_queue_flip;
6755
6756 switch (INTEL_INFO(dev)->gen) {
6757 case 2:
6758 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6759 break;
6760
6761 case 3:
6762 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6763 break;
6764
6765 case 4:
6766 case 5:
6767 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6768 break;
6769
6770 case 6:
6771 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6772 break;
7c9017e5
JB		 6773 case 7:
6774 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6775 break;
8c9f3aaf 6776 }
e70236a8
JB		 6777}
6778
b690e96c
JB		 6779/*
6780 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6781 * resume, or other times. This quirk makes sure that's the case for
6782 * affected systems.
6783 */
0206e353 6784static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 6785{
6786 struct drm_i915_private *dev_priv = dev->dev_private;
6787
6788 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 6789 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 6790}
6791
435793df
KP		 6792/*
6793 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6794 */
6795static void quirk_ssc_force_disable(struct drm_device *dev)
6796{
6797 struct drm_i915_private *dev_priv = dev->dev_private;
6798 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 6799 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 6800}
6801
4dca20ef 6802/*
5a15ab5b
CE		 6803 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6804 * brightness value
4dca20ef
CE		 6805 */
6806static void quirk_invert_brightness(struct drm_device *dev)
6807{
6808 struct drm_i915_private *dev_priv = dev->dev_private;
6809 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 6810 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 6811}
6812
b690e96c
JB		 6813struct intel_quirk {
6814 int device;
6815 int subsystem_vendor;
6816 int subsystem_device;
6817 void (*hook)(struct drm_device *dev);
6818};
6819
c43b5634 6820static struct intel_quirk intel_quirks[] = {
b690e96c 6821 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 6822 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 6823
6824 /* Thinkpad R31 needs pipe A force quirk */
6825 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6826 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6827 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6828
6829 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6830 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6831 /* ThinkPad X40 needs pipe A force quirk */
6832
6833 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6834 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6835
6836 /* 855 & before need to leave pipe A & dpll A up */
6837 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6838 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 6839
6840 /* Lenovo U160 cannot use SSC on LVDS */
6841 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 6842
6843 /* Sony Vaio Y cannot use SSC on LVDS */
6844 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 6845
6846 /* Acer Aspire 5734Z must invert backlight brightness */
6847 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 6848};
6849
6850static void intel_init_quirks(struct drm_device *dev)
6851{
6852 struct pci_dev *d = dev->pdev;
6853 int i;
6854
6855 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6856 struct intel_quirk *q = &intel_quirks[i];
6857
6858 if (d->device == q->device &&
6859 (d->subsystem_vendor == q->subsystem_vendor ||
6860 q->subsystem_vendor == PCI_ANY_ID) &&
6861 (d->subsystem_device == q->subsystem_device ||
6862 q->subsystem_device == PCI_ANY_ID))
6863 q->hook(dev);
6864 }
6865}
6866
9cce37f4
JB		 6867/* Disable the VGA plane that we never use */
6868static void i915_disable_vga(struct drm_device *dev)
6869{
6870 struct drm_i915_private *dev_priv = dev->dev_private;
6871 u8 sr1;
6872 u32 vga_reg;
6873
6874 if (HAS_PCH_SPLIT(dev))
6875 vga_reg = CPU_VGACNTRL;
6876 else
6877 vga_reg = VGACNTRL;
6878
6879 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 6880 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 6881 sr1 = inb(VGA_SR_DATA);
6882 outb(sr1 | 1<<5, VGA_SR_DATA);
6883 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6884 udelay(300);
6885
6886 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6887 POSTING_READ(vga_reg);
6888}
6889
f82cfb6b
JB		 6890static void ivb_pch_pwm_override(struct drm_device *dev)
6891{
6892 struct drm_i915_private *dev_priv = dev->dev_private;
6893
6894 /*
6895 * IVB has CPU eDP backlight regs too, set things up to let the
6896 * PCH regs control the backlight
6897 */
7cf41601 6898 I915_WRITE(BLC_PWM_CPU_CTL2, BLM_PWM_ENABLE);
f82cfb6b 6899 I915_WRITE(BLC_PWM_CPU_CTL, 0);
7cf41601 6900 I915_WRITE(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE | BLM_PCH_OVERRIDE_ENABLE);
f82cfb6b
JB		 6901}
6902
f817586c
DV		 6903void intel_modeset_init_hw(struct drm_device *dev)
6904{
6905 struct drm_i915_private *dev_priv = dev->dev_private;
6906
6907 intel_init_clock_gating(dev);
6908
6909 if (IS_IRONLAKE_M(dev)) {
6910 ironlake_enable_drps(dev);
1833b134 6911 ironlake_enable_rc6(dev);
f817586c
DV		 6912 intel_init_emon(dev);
6913 }
6914
b6834bd6 6915 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
f817586c
DV		 6916 gen6_enable_rps(dev_priv);
6917 gen6_update_ring_freq(dev_priv);
6918 }
f82cfb6b
JB		 6919
6920 if (IS_IVYBRIDGE(dev))
6921 ivb_pch_pwm_override(dev);
f817586c
DV		 6922}
6923
79e53945
JB		 6924void intel_modeset_init(struct drm_device *dev)
6925{
652c393a 6926 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 6927 int i, ret;
79e53945
JB		 6928
6929 drm_mode_config_init(dev);
6930
6931 dev->mode_config.min_width = 0;
6932 dev->mode_config.min_height = 0;
6933
019d96cb
DA		 6934 dev->mode_config.preferred_depth = 24;
6935 dev->mode_config.prefer_shadow = 1;
6936
e6ecefaa 6937 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 6938
b690e96c
JB		 6939 intel_init_quirks(dev);
6940
1fa61106
ED		 6941 intel_init_pm(dev);
6942
45244b87
ED		 6943 intel_prepare_ddi(dev);
6944
e70236a8
JB		 6945 intel_init_display(dev);
6946
a6c45cf0
CW		 6947 if (IS_GEN2(dev)) {
6948 dev->mode_config.max_width = 2048;
6949 dev->mode_config.max_height = 2048;
6950 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 6951 dev->mode_config.max_width = 4096;
6952 dev->mode_config.max_height = 4096;
79e53945 6953 } else {
a6c45cf0
CW		 6954 dev->mode_config.max_width = 8192;
6955 dev->mode_config.max_height = 8192;
79e53945 6956 }
dd2757f8 6957 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 6958
28c97730 6959 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 6960 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 6961
a3524f1b 6962 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 6963 intel_crtc_init(dev, i);
00c2064b
JB		 6964 ret = intel_plane_init(dev, i);
6965 if (ret)
6966 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 6967 }
6968
ee7b9f93
JB		 6969 intel_pch_pll_init(dev);
6970
9cce37f4
JB		 6971 /* Just disable it once at startup */
6972 i915_disable_vga(dev);
79e53945 6973 intel_setup_outputs(dev);
652c393a 6974
652c393a
JB		 6975 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6976 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6977 (unsigned long)dev);
2c7111db
CW		 6978}
6979
6980void intel_modeset_gem_init(struct drm_device *dev)
6981{
1833b134 6982 intel_modeset_init_hw(dev);
02e792fb
DV		 6983
6984 intel_setup_overlay(dev);
79e53945
JB		 6985}
6986
6987void intel_modeset_cleanup(struct drm_device *dev)
6988{
652c393a
JB		 6989 struct drm_i915_private *dev_priv = dev->dev_private;
6990 struct drm_crtc *crtc;
6991 struct intel_crtc *intel_crtc;
6992
f87ea761 6993 drm_kms_helper_poll_fini(dev);
652c393a
JB		 6994 mutex_lock(&dev->struct_mutex);
6995
723bfd70
JB		 6996 intel_unregister_dsm_handler();
6997
6998
652c393a
JB		 6999 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7000 /* Skip inactive CRTCs */
7001 if (!crtc->fb)
7002 continue;
7003
7004 intel_crtc = to_intel_crtc(crtc);
3dec0095 7005 intel_increase_pllclock(crtc);
652c393a
JB		 7006 }
7007
973d04f9 7008 intel_disable_fbc(dev);
e70236a8 7009
f97108d1
JB		 7010 if (IS_IRONLAKE_M(dev))
7011 ironlake_disable_drps(dev);
b6834bd6 7012 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
3b8d8d91 7013 gen6_disable_rps(dev);
f97108d1 7014
d5bb081b
JB		 7015 if (IS_IRONLAKE_M(dev))
7016 ironlake_disable_rc6(dev);
0cdab21f 7017
57f350b6
JB		 7018 if (IS_VALLEYVIEW(dev))
7019 vlv_init_dpio(dev);
7020
69341a5e
KH		 7021 mutex_unlock(&dev->struct_mutex);
7022
6c0d9350
DV		 7023 /* Disable the irq before mode object teardown, for the irq might
7024 * enqueue unpin/hotplug work. */
7025 drm_irq_uninstall(dev);
7026 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 7027 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 7028
1630fe75
CW		 7029 /* flush any delayed tasks or pending work */
7030 flush_scheduled_work();
7031
3dec0095
DV		 7032 /* Shut off idle work before the crtcs get freed. */
7033 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7034 intel_crtc = to_intel_crtc(crtc);
7035 del_timer_sync(&intel_crtc->idle_timer);
7036 }
7037 del_timer_sync(&dev_priv->idle_timer);
7038 cancel_work_sync(&dev_priv->idle_work);
7039
79e53945
JB		 7040 drm_mode_config_cleanup(dev);
7041}
7042
f1c79df3
ZW		 7043/*
7044 * Return which encoder is currently attached for connector.
7045 */
df0e9248 7046struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 7047{
df0e9248
CW		 7048 return &intel_attached_encoder(connector)->base;
7049}
f1c79df3 7050
df0e9248
CW		 7051void intel_connector_attach_encoder(struct intel_connector *connector,
7052 struct intel_encoder *encoder)
7053{
7054 connector->encoder = encoder;
7055 drm_mode_connector_attach_encoder(&connector->base,
7056 &encoder->base);
79e53945 7057}
28d52043
DA		 7058
7059/*
7060 * set vga decode state - true == enable VGA decode
7061 */
7062int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7063{
7064 struct drm_i915_private *dev_priv = dev->dev_private;
7065 u16 gmch_ctrl;
7066
7067 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7068 if (state)
7069 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7070 else
7071 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7072 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7073 return 0;
7074}
c4a1d9e4
CW		 7075
7076#ifdef CONFIG_DEBUG_FS
7077#include <linux/seq_file.h>
7078
7079struct intel_display_error_state {
7080 struct intel_cursor_error_state {
7081 u32 control;
7082 u32 position;
7083 u32 base;
7084 u32 size;
7085 } cursor[2];
7086
7087 struct intel_pipe_error_state {
7088 u32 conf;
7089 u32 source;
7090
7091 u32 htotal;
7092 u32 hblank;
7093 u32 hsync;
7094 u32 vtotal;
7095 u32 vblank;
7096 u32 vsync;
7097 } pipe[2];
7098
7099 struct intel_plane_error_state {
7100 u32 control;
7101 u32 stride;
7102 u32 size;
7103 u32 pos;
7104 u32 addr;
7105 u32 surface;
7106 u32 tile_offset;
7107 } plane[2];
7108};
7109
7110struct intel_display_error_state *
7111intel_display_capture_error_state(struct drm_device *dev)
7112{
0206e353 7113 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 7114 struct intel_display_error_state *error;
7115 int i;
7116
7117 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7118 if (error == NULL)
7119 return NULL;
7120
7121 for (i = 0; i < 2; i++) {
7122 error->cursor[i].control = I915_READ(CURCNTR(i));
7123 error->cursor[i].position = I915_READ(CURPOS(i));
7124 error->cursor[i].base = I915_READ(CURBASE(i));
7125
7126 error->plane[i].control = I915_READ(DSPCNTR(i));
7127 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7128 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 7129 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 7130 error->plane[i].addr = I915_READ(DSPADDR(i));
7131 if (INTEL_INFO(dev)->gen >= 4) {
7132 error->plane[i].surface = I915_READ(DSPSURF(i));
7133 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7134 }
7135
7136 error->pipe[i].conf = I915_READ(PIPECONF(i));
7137 error->pipe[i].source = I915_READ(PIPESRC(i));
7138 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7139 error->pipe[i].hblank = I915_READ(HBLANK(i));
7140 error->pipe[i].hsync = I915_READ(HSYNC(i));
7141 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7142 error->pipe[i].vblank = I915_READ(VBLANK(i));
7143 error->pipe[i].vsync = I915_READ(VSYNC(i));
7144 }
7145
7146 return error;
7147}
7148
7149void
7150intel_display_print_error_state(struct seq_file *m,
7151 struct drm_device *dev,
7152 struct intel_display_error_state *error)
7153{
7154 int i;
7155
7156 for (i = 0; i < 2; i++) {
7157 seq_printf(m, "Pipe [%d]:\n", i);
7158 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7159 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7160 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7161 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7162 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7163 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7164 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7165 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7166
7167 seq_printf(m, "Plane [%d]:\n", i);
7168 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7169 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7170 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7171 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7172 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7173 if (INTEL_INFO(dev)->gen >= 4) {
7174 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7175 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7176 }
7177
7178 seq_printf(m, "Cursor [%d]:\n", i);
7179 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7180 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7181 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7182 }
7183}
7184#endif
Linux kernel - Deliverables
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