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drm/i915: Refresh cached DP port register value on resume
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
559be30c
TP		 44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
9dd4ffdf 50struct dp_link_dpll {
840b32b7 51 int clock;
9dd4ffdf
CML		 52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
840b32b7 56 { 162000,
9dd4ffdf 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
840b32b7 58 { 270000,
9dd4ffdf
CML		 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
840b32b7 63 { 162000,
9dd4ffdf 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
840b32b7 65 { 270000,
9dd4ffdf
CML		 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
65ce4bf5 69static const struct dp_link_dpll vlv_dpll[] = {
840b32b7 70 { 162000,
58f6e632 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
840b32b7 72 { 270000,
65ce4bf5
CML		 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
ef9348c8
CML		 76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
840b32b7 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
ef9348c8 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
840b32b7 88 { 270000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
840b32b7 90 { 540000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8
CML		 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
637a9c63 93
64987fc5
SJ		 94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
637a9c63 96static const int skl_rates[] = { 162000, 216000, 270000,
f4896f15
VS		 97 324000, 432000, 540000 };
98static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 99
cfcb0fc9
JB		 100/**
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
103 *
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
106 */
107static bool is_edp(struct intel_dp *intel_dp)
108{
da63a9f2
PZ		 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 112}
113
68b4d824 114static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 115{
68b4d824
ID		 116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
117
118 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 119}
120
df0e9248
CW		 121static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
122{
fa90ecef 123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 124}
125
ea5b213a 126static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 127static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 128static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 129static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 130static void vlv_steal_power_sequencer(struct drm_device *dev,
131 enum pipe pipe);
f21a2198 132static void intel_dp_unset_edid(struct intel_dp *intel_dp);
a4fc5ed6 133
ed4e9c1d
VS		 134static int
135intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 136{
7183dc29 137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 138
139 switch (max_link_bw) {
140 case DP_LINK_BW_1_62:
141 case DP_LINK_BW_2_7:
1db10e28 142 case DP_LINK_BW_5_4:
d4eead50 143 break;
a4fc5ed6 144 default:
d4eead50
ID		 145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
146 max_link_bw);
a4fc5ed6
KP		 147 max_link_bw = DP_LINK_BW_1_62;
148 break;
149 }
150 return max_link_bw;
151}
152
eeb6324d
PZ		 153static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
154{
155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
eeb6324d
PZ		 156 u8 source_max, sink_max;
157
ccb1a831 158 source_max = intel_dig_port->max_lanes;
eeb6324d
PZ		 159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
160
161 return min(source_max, sink_max);
162}
163
cd9dde44
AJ		 164/*
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
167 *
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
169 *
170 * 270000 * 1 * 8 / 10 == 216000
171 *
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
176 *
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
179 */
180
a4fc5ed6 181static int
c898261c 182intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 183{
cd9dde44 184 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 185}
186
fe27d53e
DA		 187static int
188intel_dp_max_data_rate(int max_link_clock, int max_lanes)
189{
190 return (max_link_clock * max_lanes * 8) / 10;
191}
192
c19de8eb 193static enum drm_mode_status
a4fc5ed6
KP		 194intel_dp_mode_valid(struct drm_connector *connector,
195 struct drm_display_mode *mode)
196{
df0e9248 197 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 198 struct intel_connector *intel_connector = to_intel_connector(connector);
199 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 200 int target_clock = mode->clock;
201 int max_rate, mode_rate, max_lanes, max_link_clock;
799487f5 202 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
a4fc5ed6 203
dd06f90e
JN		 204 if (is_edp(intel_dp) && fixed_mode) {
205 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 206 return MODE_PANEL;
207
dd06f90e 208 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 209 return MODE_PANEL;
03afc4a2
DV		 210
211 target_clock = fixed_mode->clock;
7de56f43
ZY		 212 }
213
50fec21a 214 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 215 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 216
217 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
218 mode_rate = intel_dp_link_required(target_clock, 18);
219
799487f5 220 if (mode_rate > max_rate || target_clock > max_dotclk)
c4867936 221 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 222
223 if (mode->clock < 10000)
224 return MODE_CLOCK_LOW;
225
0af78a2b
DV		 226 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
227 return MODE_H_ILLEGAL;
228
a4fc5ed6
KP		 229 return MODE_OK;
230}
231
a4f1289e 232uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 233{
234 int i;
235 uint32_t v = 0;
236
237 if (src_bytes > 4)
238 src_bytes = 4;
239 for (i = 0; i < src_bytes; i++)
240 v |= ((uint32_t) src[i]) << ((3-i) * 8);
241 return v;
242}
243
c2af70e2 244static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 245{
246 int i;
247 if (dst_bytes > 4)
248 dst_bytes = 4;
249 for (i = 0; i < dst_bytes; i++)
250 dst[i] = src >> ((3-i) * 8);
251}
252
bf13e81b
JN		 253static void
254intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 255 struct intel_dp *intel_dp);
bf13e81b
JN		 256static void
257intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 258 struct intel_dp *intel_dp);
bf13e81b 259
773538e8
VS		 260static void pps_lock(struct intel_dp *intel_dp)
261{
262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
263 struct intel_encoder *encoder = &intel_dig_port->base;
264 struct drm_device *dev = encoder->base.dev;
265 struct drm_i915_private *dev_priv = dev->dev_private;
266 enum intel_display_power_domain power_domain;
267
268 /*
269 * See vlv_power_sequencer_reset() why we need
270 * a power domain reference here.
271 */
25f78f58 272 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 273 intel_display_power_get(dev_priv, power_domain);
274
275 mutex_lock(&dev_priv->pps_mutex);
276}
277
278static void pps_unlock(struct intel_dp *intel_dp)
279{
280 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
281 struct intel_encoder *encoder = &intel_dig_port->base;
282 struct drm_device *dev = encoder->base.dev;
283 struct drm_i915_private *dev_priv = dev->dev_private;
284 enum intel_display_power_domain power_domain;
285
286 mutex_unlock(&dev_priv->pps_mutex);
287
25f78f58 288 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 289 intel_display_power_put(dev_priv, power_domain);
290}
291
961a0db0
VS		 292static void
293vlv_power_sequencer_kick(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct drm_device *dev = intel_dig_port->base.base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum pipe pipe = intel_dp->pps_pipe;
0047eedc
VS		 299 bool pll_enabled, release_cl_override = false;
300 enum dpio_phy phy = DPIO_PHY(pipe);
301 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
961a0db0
VS		 302 uint32_t DP;
303
304 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
305 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
306 pipe_name(pipe), port_name(intel_dig_port->port)))
307 return;
308
309 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
310 pipe_name(pipe), port_name(intel_dig_port->port));
311
312 /* Preserve the BIOS-computed detected bit. This is
313 * supposed to be read-only.
314 */
315 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
316 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
317 DP |= DP_PORT_WIDTH(1);
318 DP |= DP_LINK_TRAIN_PAT_1;
319
320 if (IS_CHERRYVIEW(dev))
321 DP |= DP_PIPE_SELECT_CHV(pipe);
322 else if (pipe == PIPE_B)
323 DP |= DP_PIPEB_SELECT;
324
d288f65f
VS		 325 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
326
327 /*
328 * The DPLL for the pipe must be enabled for this to work.
329 * So enable temporarily it if it's not already enabled.
330 */
0047eedc
VS		 331 if (!pll_enabled) {
332 release_cl_override = IS_CHERRYVIEW(dev) &&
333 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
334
3f36b937
TU		 335 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
336 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
337 DRM_ERROR("Failed to force on pll for pipe %c!\n",
338 pipe_name(pipe));
339 return;
340 }
0047eedc 341 }
d288f65f 342
961a0db0
VS		 343 /*
344 * Similar magic as in intel_dp_enable_port().
345 * We _must_ do this port enable + disable trick
346 * to make this power seqeuencer lock onto the port.
347 * Otherwise even VDD force bit won't work.
348 */
349 I915_WRITE(intel_dp->output_reg, DP);
350 POSTING_READ(intel_dp->output_reg);
351
352 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
353 POSTING_READ(intel_dp->output_reg);
354
355 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
356 POSTING_READ(intel_dp->output_reg);
d288f65f 357
0047eedc 358 if (!pll_enabled) {
d288f65f 359 vlv_force_pll_off(dev, pipe);
0047eedc
VS		 360
361 if (release_cl_override)
362 chv_phy_powergate_ch(dev_priv, phy, ch, false);
363 }
961a0db0
VS		 364}
365
bf13e81b
JN		 366static enum pipe
367vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
368{
369 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 370 struct drm_device *dev = intel_dig_port->base.base.dev;
371 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 372 struct intel_encoder *encoder;
373 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 374 enum pipe pipe;
bf13e81b 375
e39b999a 376 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 377
a8c3344e
VS		 378 /* We should never land here with regular DP ports */
379 WARN_ON(!is_edp(intel_dp));
380
a4a5d2f8
VS		 381 if (intel_dp->pps_pipe != INVALID_PIPE)
382 return intel_dp->pps_pipe;
383
384 /*
385 * We don't have power sequencer currently.
386 * Pick one that's not used by other ports.
387 */
19c8054c 388 for_each_intel_encoder(dev, encoder) {
a4a5d2f8
VS		 389 struct intel_dp *tmp;
390
391 if (encoder->type != INTEL_OUTPUT_EDP)
392 continue;
393
394 tmp = enc_to_intel_dp(&encoder->base);
395
396 if (tmp->pps_pipe != INVALID_PIPE)
397 pipes &= ~(1 << tmp->pps_pipe);
398 }
399
400 /*
401 * Didn't find one. This should not happen since there
402 * are two power sequencers and up to two eDP ports.
403 */
404 if (WARN_ON(pipes == 0))
a8c3344e
VS		 405 pipe = PIPE_A;
406 else
407 pipe = ffs(pipes) - 1;
a4a5d2f8 408
a8c3344e
VS		 409 vlv_steal_power_sequencer(dev, pipe);
410 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 411
412 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
413 pipe_name(intel_dp->pps_pipe),
414 port_name(intel_dig_port->port));
415
416 /* init power sequencer on this pipe and port */
36b5f425
VS		 417 intel_dp_init_panel_power_sequencer(dev, intel_dp);
418 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 419
961a0db0
VS		 420 /*
421 * Even vdd force doesn't work until we've made
422 * the power sequencer lock in on the port.
423 */
424 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 425
426 return intel_dp->pps_pipe;
427}
428
78597996
ID		 429static int
430bxt_power_sequencer_idx(struct intel_dp *intel_dp)
431{
432 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
433 struct drm_device *dev = intel_dig_port->base.base.dev;
434 struct drm_i915_private *dev_priv = dev->dev_private;
435
436 lockdep_assert_held(&dev_priv->pps_mutex);
437
438 /* We should never land here with regular DP ports */
439 WARN_ON(!is_edp(intel_dp));
440
441 /*
442 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
443 * mapping needs to be retrieved from VBT, for now just hard-code to
444 * use instance #0 always.
445 */
446 if (!intel_dp->pps_reset)
447 return 0;
448
449 intel_dp->pps_reset = false;
450
451 /*
452 * Only the HW needs to be reprogrammed, the SW state is fixed and
453 * has been setup during connector init.
454 */
455 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
456
457 return 0;
458}
459
6491ab27
VS		 460typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
461 enum pipe pipe);
462
463static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
464 enum pipe pipe)
465{
466 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
467}
468
469static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
470 enum pipe pipe)
471{
472 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
473}
474
475static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
476 enum pipe pipe)
477{
478 return true;
479}
bf13e81b 480
a4a5d2f8 481static enum pipe
6491ab27
VS		 482vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
483 enum port port,
484 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 485{
486 enum pipe pipe;
bf13e81b 487
bf13e81b
JN		 488 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
489 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
490 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 491
492 if (port_sel != PANEL_PORT_SELECT_VLV(port))
493 continue;
494
6491ab27
VS		 495 if (!pipe_check(dev_priv, pipe))
496 continue;
497
a4a5d2f8 498 return pipe;
bf13e81b
JN		 499 }
500
a4a5d2f8
VS		 501 return INVALID_PIPE;
502}
503
504static void
505vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
506{
507 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
508 struct drm_device *dev = intel_dig_port->base.base.dev;
509 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 510 enum port port = intel_dig_port->port;
511
512 lockdep_assert_held(&dev_priv->pps_mutex);
513
514 /* try to find a pipe with this port selected */
6491ab27
VS		 515 /* first pick one where the panel is on */
516 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
517 vlv_pipe_has_pp_on);
518 /* didn't find one? pick one where vdd is on */
519 if (intel_dp->pps_pipe == INVALID_PIPE)
520 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
521 vlv_pipe_has_vdd_on);
522 /* didn't find one? pick one with just the correct port */
523 if (intel_dp->pps_pipe == INVALID_PIPE)
524 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
525 vlv_pipe_any);
a4a5d2f8
VS		 526
527 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
528 if (intel_dp->pps_pipe == INVALID_PIPE) {
529 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
530 port_name(port));
531 return;
bf13e81b
JN		 532 }
533
a4a5d2f8
VS		 534 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
535 port_name(port), pipe_name(intel_dp->pps_pipe));
536
36b5f425
VS		 537 intel_dp_init_panel_power_sequencer(dev, intel_dp);
538 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 539}
540
78597996 541void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
773538e8
VS		 542{
543 struct drm_device *dev = dev_priv->dev;
544 struct intel_encoder *encoder;
545
78597996
ID		 546 if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
547 !IS_BROXTON(dev)))
773538e8
VS		 548 return;
549
550 /*
551 * We can't grab pps_mutex here due to deadlock with power_domain
552 * mutex when power_domain functions are called while holding pps_mutex.
553 * That also means that in order to use pps_pipe the code needs to
554 * hold both a power domain reference and pps_mutex, and the power domain
555 * reference get/put must be done while _not_ holding pps_mutex.
556 * pps_{lock,unlock}() do these steps in the correct order, so one
557 * should use them always.
558 */
559
19c8054c 560 for_each_intel_encoder(dev, encoder) {
773538e8
VS		 561 struct intel_dp *intel_dp;
562
563 if (encoder->type != INTEL_OUTPUT_EDP)
564 continue;
565
566 intel_dp = enc_to_intel_dp(&encoder->base);
78597996
ID		 567 if (IS_BROXTON(dev))
568 intel_dp->pps_reset = true;
569 else
570 intel_dp->pps_pipe = INVALID_PIPE;
773538e8 571 }
bf13e81b
JN		 572}
573
8e8232d5
ID		 574struct pps_registers {
575 i915_reg_t pp_ctrl;
576 i915_reg_t pp_stat;
577 i915_reg_t pp_on;
578 i915_reg_t pp_off;
579 i915_reg_t pp_div;
580};
581
582static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
583 struct intel_dp *intel_dp,
584 struct pps_registers *regs)
585{
586 memset(regs, 0, sizeof(*regs));
587
588 if (IS_BROXTON(dev_priv)) {
589 int idx = bxt_power_sequencer_idx(intel_dp);
590
591 regs->pp_ctrl = BXT_PP_CONTROL(idx);
592 regs->pp_stat = BXT_PP_STATUS(idx);
593 regs->pp_on = BXT_PP_ON_DELAYS(idx);
594 regs->pp_off = BXT_PP_OFF_DELAYS(idx);
595 } else if (HAS_PCH_SPLIT(dev_priv)) {
596 regs->pp_ctrl = PCH_PP_CONTROL;
597 regs->pp_stat = PCH_PP_STATUS;
598 regs->pp_on = PCH_PP_ON_DELAYS;
599 regs->pp_off = PCH_PP_OFF_DELAYS;
600 regs->pp_div = PCH_PP_DIVISOR;
601 } else {
602 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
603
604 regs->pp_ctrl = VLV_PIPE_PP_CONTROL(pipe);
605 regs->pp_stat = VLV_PIPE_PP_STATUS(pipe);
606 regs->pp_on = VLV_PIPE_PP_ON_DELAYS(pipe);
607 regs->pp_off = VLV_PIPE_PP_OFF_DELAYS(pipe);
608 regs->pp_div = VLV_PIPE_PP_DIVISOR(pipe);
609 }
610}
611
f0f59a00
VS		 612static i915_reg_t
613_pp_ctrl_reg(struct intel_dp *intel_dp)
bf13e81b 614{
8e8232d5 615 struct pps_registers regs;
bf13e81b 616
8e8232d5
ID		 617 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
618 &regs);
619
620 return regs.pp_ctrl;
bf13e81b
JN		 621}
622
f0f59a00
VS		 623static i915_reg_t
624_pp_stat_reg(struct intel_dp *intel_dp)
bf13e81b 625{
8e8232d5 626 struct pps_registers regs;
bf13e81b 627
8e8232d5
ID		 628 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
629 &regs);
630
631 return regs.pp_stat;
bf13e81b
JN		 632}
633
01527b31
CT		 634/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
635 This function only applicable when panel PM state is not to be tracked */
636static int edp_notify_handler(struct notifier_block *this, unsigned long code,
637 void *unused)
638{
639 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
640 edp_notifier);
641 struct drm_device *dev = intel_dp_to_dev(intel_dp);
642 struct drm_i915_private *dev_priv = dev->dev_private;
01527b31
CT		 643
644 if (!is_edp(intel_dp) || code != SYS_RESTART)
645 return 0;
646
773538e8 647 pps_lock(intel_dp);
e39b999a 648
666a4537 649 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e39b999a 650 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
f0f59a00 651 i915_reg_t pp_ctrl_reg, pp_div_reg;
649636ef 652 u32 pp_div;
e39b999a 653
01527b31
CT		 654 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
655 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
656 pp_div = I915_READ(pp_div_reg);
657 pp_div &= PP_REFERENCE_DIVIDER_MASK;
658
659 /* 0x1F write to PP_DIV_REG sets max cycle delay */
660 I915_WRITE(pp_div_reg, pp_div | 0x1F);
661 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
662 msleep(intel_dp->panel_power_cycle_delay);
663 }
664
773538e8 665 pps_unlock(intel_dp);
e39b999a 666
01527b31
CT		 667 return 0;
668}
669
4be73780 670static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 671{
30add22d 672 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 673 struct drm_i915_private *dev_priv = dev->dev_private;
674
e39b999a
VS		 675 lockdep_assert_held(&dev_priv->pps_mutex);
676
666a4537 677 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 678 intel_dp->pps_pipe == INVALID_PIPE)
679 return false;
680
bf13e81b 681 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 682}
683
4be73780 684static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 685{
30add22d 686 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 687 struct drm_i915_private *dev_priv = dev->dev_private;
688
e39b999a
VS		 689 lockdep_assert_held(&dev_priv->pps_mutex);
690
666a4537 691 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 692 intel_dp->pps_pipe == INVALID_PIPE)
693 return false;
694
773538e8 695 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 696}
697
9b984dae
KP		 698static void
699intel_dp_check_edp(struct intel_dp *intel_dp)
700{
30add22d 701 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 702 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 703
9b984dae
KP		 704 if (!is_edp(intel_dp))
705 return;
453c5420 706
4be73780 707 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 708 WARN(1, "eDP powered off while attempting aux channel communication.\n");
709 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 710 I915_READ(_pp_stat_reg(intel_dp)),
711 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 712 }
713}
714
9ee32fea
DV		 715static uint32_t
716intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
717{
718 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
719 struct drm_device *dev = intel_dig_port->base.base.dev;
720 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 721 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 722 uint32_t status;
723 bool done;
724
ef04f00d 725#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 726 if (has_aux_irq)
b18ac466 727 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 728 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 729 else
730 done = wait_for_atomic(C, 10) == 0;
731 if (!done)
732 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
733 has_aux_irq);
734#undef C
735
736 return status;
737}
738
6ffb1be7 739static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 740{
174edf1f 741 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
e7dc33f3 742 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
9ee32fea 743
a457f54b
VS		 744 if (index)
745 return 0;
746
ec5b01dd
DL		 747 /*
748 * The clock divider is based off the hrawclk, and would like to run at
a457f54b 749 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
a4fc5ed6 750 */
a457f54b 751 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 752}
753
754static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
755{
756 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 757 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd
DL		 758
759 if (index)
760 return 0;
761
a457f54b
VS		 762 /*
763 * The clock divider is based off the cdclk or PCH rawclk, and would
764 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
765 * divide by 2000 and use that
766 */
e7dc33f3 767 if (intel_dig_port->port == PORT_A)
fce18c4c 768 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
e7dc33f3
VS		 769 else
770 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 771}
772
773static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
774{
775 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 776 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd 777
a457f54b 778 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
2c55c336 779 /* Workaround for non-ULT HSW */
bc86625a
CW		 780 switch (index) {
781 case 0: return 63;
782 case 1: return 72;
783 default: return 0;
784 }
2c55c336 785 }
a457f54b
VS		 786
787 return ilk_get_aux_clock_divider(intel_dp, index);
b84a1cf8
RV		 788}
789
b6b5e383
DL		 790static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
791{
792 /*
793 * SKL doesn't need us to program the AUX clock divider (Hardware will
794 * derive the clock from CDCLK automatically). We still implement the
795 * get_aux_clock_divider vfunc to plug-in into the existing code.
796 */
797 return index ? 0 : 1;
798}
799
6ffb1be7
VS		 800static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
801 bool has_aux_irq,
802 int send_bytes,
803 uint32_t aux_clock_divider)
5ed12a19
DL		 804{
805 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
806 struct drm_device *dev = intel_dig_port->base.base.dev;
807 uint32_t precharge, timeout;
808
809 if (IS_GEN6(dev))
810 precharge = 3;
811 else
812 precharge = 5;
813
f3c6a3a7 814 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
5ed12a19
DL		 815 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
816 else
817 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
818
819 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 820 DP_AUX_CH_CTL_DONE |
5ed12a19 821 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 822 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 823 timeout |
788d4433 824 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 825 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
826 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 827 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 828}
829
b9ca5fad
DL		 830static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
831 bool has_aux_irq,
832 int send_bytes,
833 uint32_t unused)
834{
835 return DP_AUX_CH_CTL_SEND_BUSY |
836 DP_AUX_CH_CTL_DONE |
837 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
838 DP_AUX_CH_CTL_TIME_OUT_ERROR |
839 DP_AUX_CH_CTL_TIME_OUT_1600us |
840 DP_AUX_CH_CTL_RECEIVE_ERROR |
841 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
d4dcbdce 842 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
b9ca5fad
DL		 843 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
844}
845
b84a1cf8
RV		 846static int
847intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 848 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 849 uint8_t *recv, int recv_size)
850{
851 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
852 struct drm_device *dev = intel_dig_port->base.base.dev;
853 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 854 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
bc86625a 855 uint32_t aux_clock_divider;
b84a1cf8
RV		 856 int i, ret, recv_bytes;
857 uint32_t status;
5ed12a19 858 int try, clock = 0;
4e6b788c 859 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 860 bool vdd;
861
773538e8 862 pps_lock(intel_dp);
e39b999a 863
72c3500a
VS		 864 /*
865 * We will be called with VDD already enabled for dpcd/edid/oui reads.
866 * In such cases we want to leave VDD enabled and it's up to upper layers
867 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
868 * ourselves.
869 */
1e0560e0 870 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 871
872 /* dp aux is extremely sensitive to irq latency, hence request the
873 * lowest possible wakeup latency and so prevent the cpu from going into
874 * deep sleep states.
875 */
876 pm_qos_update_request(&dev_priv->pm_qos, 0);
877
878 intel_dp_check_edp(intel_dp);
5eb08b69 879
11bee43e
JB		 880 /* Try to wait for any previous AUX channel activity */
881 for (try = 0; try < 3; try++) {
ef04f00d 882 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 883 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
884 break;
885 msleep(1);
886 }
887
888 if (try == 3) {
02196c77
MK		 889 static u32 last_status = -1;
890 const u32 status = I915_READ(ch_ctl);
891
892 if (status != last_status) {
893 WARN(1, "dp_aux_ch not started status 0x%08x\n",
894 status);
895 last_status = status;
896 }
897
9ee32fea
DV		 898 ret = -EBUSY;
899 goto out;
4f7f7b7e
CW		 900 }
901
46a5ae9f
PZ		 902 /* Only 5 data registers! */
903 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
904 ret = -E2BIG;
905 goto out;
906 }
907
ec5b01dd 908 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 909 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
910 has_aux_irq,
911 send_bytes,
912 aux_clock_divider);
5ed12a19 913
bc86625a
CW		 914 /* Must try at least 3 times according to DP spec */
915 for (try = 0; try < 5; try++) {
916 /* Load the send data into the aux channel data registers */
917 for (i = 0; i < send_bytes; i += 4)
330e20ec 918 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
a4f1289e
RV		 919 intel_dp_pack_aux(send + i,
920 send_bytes - i));
bc86625a
CW		 921
922 /* Send the command and wait for it to complete */
5ed12a19 923 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 924
925 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
926
927 /* Clear done status and any errors */
928 I915_WRITE(ch_ctl,
929 status |
930 DP_AUX_CH_CTL_DONE |
931 DP_AUX_CH_CTL_TIME_OUT_ERROR |
932 DP_AUX_CH_CTL_RECEIVE_ERROR);
933
74ebf294 934 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 935 continue;
74ebf294
TP		 936
937 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
938 * 400us delay required for errors and timeouts
939 * Timeout errors from the HW already meet this
940 * requirement so skip to next iteration
941 */
942 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
943 usleep_range(400, 500);
bc86625a 944 continue;
74ebf294 945 }
bc86625a 946 if (status & DP_AUX_CH_CTL_DONE)
e058c945 947 goto done;
bc86625a 948 }
a4fc5ed6
KP		 949 }
950
a4fc5ed6 951 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 952 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 953 ret = -EBUSY;
954 goto out;
a4fc5ed6
KP		 955 }
956
e058c945 957done:
a4fc5ed6
KP		 958 /* Check for timeout or receive error.
959 * Timeouts occur when the sink is not connected
960 */
a5b3da54 961 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 962 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 963 ret = -EIO;
964 goto out;
a5b3da54 965 }
1ae8c0a5
KP		 966
967 /* Timeouts occur when the device isn't connected, so they're
968 * "normal" -- don't fill the kernel log with these */
a5b3da54 969 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 970 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 971 ret = -ETIMEDOUT;
972 goto out;
a4fc5ed6
KP		 973 }
974
975 /* Unload any bytes sent back from the other side */
976 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
977 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
14e01889
RV		 978
979 /*
980 * By BSpec: "Message sizes of 0 or >20 are not allowed."
981 * We have no idea of what happened so we return -EBUSY so
982 * drm layer takes care for the necessary retries.
983 */
984 if (recv_bytes == 0 || recv_bytes > 20) {
985 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
986 recv_bytes);
987 /*
988 * FIXME: This patch was created on top of a series that
989 * organize the retries at drm level. There EBUSY should
990 * also take care for 1ms wait before retrying.
991 * That aux retries re-org is still needed and after that is
992 * merged we remove this sleep from here.
993 */
994 usleep_range(1000, 1500);
995 ret = -EBUSY;
996 goto out;
997 }
998
a4fc5ed6
KP		 999 if (recv_bytes > recv_size)
1000 recv_bytes = recv_size;
0206e353 1001
4f7f7b7e 1002 for (i = 0; i < recv_bytes; i += 4)
330e20ec 1003 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
a4f1289e 1004 recv + i, recv_bytes - i);
a4fc5ed6 1005
9ee32fea
DV		 1006 ret = recv_bytes;
1007out:
1008 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1009
884f19e9
JN		 1010 if (vdd)
1011 edp_panel_vdd_off(intel_dp, false);
1012
773538e8 1013 pps_unlock(intel_dp);
e39b999a 1014
9ee32fea 1015 return ret;
a4fc5ed6
KP		 1016}
1017
a6c8aff0
JN		 1018#define BARE_ADDRESS_SIZE 3
1019#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 1020static ssize_t
1021intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 1022{
9d1a1031
JN		 1023 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1024 uint8_t txbuf[20], rxbuf[20];
1025 size_t txsize, rxsize;
a4fc5ed6 1026 int ret;
a4fc5ed6 1027
d2d9cbbd
VS		 1028 txbuf[0] = (msg->request << 4) |
1029 ((msg->address >> 16) & 0xf);
1030 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 1031 txbuf[2] = msg->address & 0xff;
1032 txbuf[3] = msg->size - 1;
46a5ae9f 1033
9d1a1031
JN		 1034 switch (msg->request & ~DP_AUX_I2C_MOT) {
1035 case DP_AUX_NATIVE_WRITE:
1036 case DP_AUX_I2C_WRITE:
c1e74122 1037 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
a6c8aff0 1038 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 1039 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 1040
9d1a1031
JN		 1041 if (WARN_ON(txsize > 20))
1042 return -E2BIG;
a4fc5ed6 1043
d81a67cc
ID		 1044 if (msg->buffer)
1045 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1046 else
1047 WARN_ON(msg->size);
a4fc5ed6 1048
9d1a1031
JN		 1049 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1050 if (ret > 0) {
1051 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 1052
a1ddefd8
JN		 1053 if (ret > 1) {
1054 /* Number of bytes written in a short write. */
1055 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1056 } else {
1057 /* Return payload size. */
1058 ret = msg->size;
1059 }
9d1a1031
JN		 1060 }
1061 break;
46a5ae9f 1062
9d1a1031
JN		 1063 case DP_AUX_NATIVE_READ:
1064 case DP_AUX_I2C_READ:
a6c8aff0 1065 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 1066 rxsize = msg->size + 1;
a4fc5ed6 1067
9d1a1031
JN		 1068 if (WARN_ON(rxsize > 20))
1069 return -E2BIG;
a4fc5ed6 1070
9d1a1031
JN		 1071 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1072 if (ret > 0) {
1073 msg->reply = rxbuf[0] >> 4;
1074 /*
1075 * Assume happy day, and copy the data. The caller is
1076 * expected to check msg->reply before touching it.
1077 *
1078 * Return payload size.
1079 */
1080 ret--;
1081 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1082 }
9d1a1031
JN		 1083 break;
1084
1085 default:
1086 ret = -EINVAL;
1087 break;
a4fc5ed6 1088 }
f51a44b9 1089
9d1a1031 1090 return ret;
a4fc5ed6
KP		 1091}
1092
f0f59a00
VS		 1093static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1094 enum port port)
da00bdcf
VS		 1095{
1096 switch (port) {
1097 case PORT_B:
1098 case PORT_C:
1099 case PORT_D:
1100 return DP_AUX_CH_CTL(port);
1101 default:
1102 MISSING_CASE(port);
1103 return DP_AUX_CH_CTL(PORT_B);
1104 }
1105}
1106
f0f59a00
VS		 1107static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1108 enum port port, int index)
330e20ec
VS		 1109{
1110 switch (port) {
1111 case PORT_B:
1112 case PORT_C:
1113 case PORT_D:
1114 return DP_AUX_CH_DATA(port, index);
1115 default:
1116 MISSING_CASE(port);
1117 return DP_AUX_CH_DATA(PORT_B, index);
1118 }
1119}
1120
f0f59a00
VS		 1121static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1122 enum port port)
da00bdcf
VS		 1123{
1124 switch (port) {
1125 case PORT_A:
1126 return DP_AUX_CH_CTL(port);
1127 case PORT_B:
1128 case PORT_C:
1129 case PORT_D:
1130 return PCH_DP_AUX_CH_CTL(port);
1131 default:
1132 MISSING_CASE(port);
1133 return DP_AUX_CH_CTL(PORT_A);
1134 }
1135}
1136
f0f59a00
VS		 1137static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1138 enum port port, int index)
330e20ec
VS		 1139{
1140 switch (port) {
1141 case PORT_A:
1142 return DP_AUX_CH_DATA(port, index);
1143 case PORT_B:
1144 case PORT_C:
1145 case PORT_D:
1146 return PCH_DP_AUX_CH_DATA(port, index);
1147 default:
1148 MISSING_CASE(port);
1149 return DP_AUX_CH_DATA(PORT_A, index);
1150 }
1151}
1152
da00bdcf
VS		 1153/*
1154 * On SKL we don't have Aux for port E so we rely
1155 * on VBT to set a proper alternate aux channel.
1156 */
1157static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1158{
1159 const struct ddi_vbt_port_info *info =
1160 &dev_priv->vbt.ddi_port_info[PORT_E];
1161
1162 switch (info->alternate_aux_channel) {
1163 case DP_AUX_A:
1164 return PORT_A;
1165 case DP_AUX_B:
1166 return PORT_B;
1167 case DP_AUX_C:
1168 return PORT_C;
1169 case DP_AUX_D:
1170 return PORT_D;
1171 default:
1172 MISSING_CASE(info->alternate_aux_channel);
1173 return PORT_A;
1174 }
1175}
1176
f0f59a00
VS		 1177static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1178 enum port port)
da00bdcf
VS		 1179{
1180 if (port == PORT_E)
1181 port = skl_porte_aux_port(dev_priv);
1182
1183 switch (port) {
1184 case PORT_A:
1185 case PORT_B:
1186 case PORT_C:
1187 case PORT_D:
1188 return DP_AUX_CH_CTL(port);
1189 default:
1190 MISSING_CASE(port);
1191 return DP_AUX_CH_CTL(PORT_A);
1192 }
1193}
1194
f0f59a00
VS		 1195static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1196 enum port port, int index)
330e20ec
VS		 1197{
1198 if (port == PORT_E)
1199 port = skl_porte_aux_port(dev_priv);
1200
1201 switch (port) {
1202 case PORT_A:
1203 case PORT_B:
1204 case PORT_C:
1205 case PORT_D:
1206 return DP_AUX_CH_DATA(port, index);
1207 default:
1208 MISSING_CASE(port);
1209 return DP_AUX_CH_DATA(PORT_A, index);
1210 }
1211}
1212
f0f59a00
VS		 1213static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1214 enum port port)
330e20ec
VS		 1215{
1216 if (INTEL_INFO(dev_priv)->gen >= 9)
1217 return skl_aux_ctl_reg(dev_priv, port);
1218 else if (HAS_PCH_SPLIT(dev_priv))
1219 return ilk_aux_ctl_reg(dev_priv, port);
1220 else
1221 return g4x_aux_ctl_reg(dev_priv, port);
1222}
1223
f0f59a00
VS		 1224static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1225 enum port port, int index)
330e20ec
VS		 1226{
1227 if (INTEL_INFO(dev_priv)->gen >= 9)
1228 return skl_aux_data_reg(dev_priv, port, index);
1229 else if (HAS_PCH_SPLIT(dev_priv))
1230 return ilk_aux_data_reg(dev_priv, port, index);
1231 else
1232 return g4x_aux_data_reg(dev_priv, port, index);
1233}
1234
1235static void intel_aux_reg_init(struct intel_dp *intel_dp)
1236{
1237 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1238 enum port port = dp_to_dig_port(intel_dp)->port;
1239 int i;
1240
1241 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1242 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1243 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1244}
1245
9d1a1031 1246static void
a121f4e5
VS		 1247intel_dp_aux_fini(struct intel_dp *intel_dp)
1248{
1249 drm_dp_aux_unregister(&intel_dp->aux);
1250 kfree(intel_dp->aux.name);
1251}
1252
1253static int
9d1a1031
JN		 1254intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1255{
33ad6626
JN		 1256 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1257 enum port port = intel_dig_port->port;
ab2c0672
DA		 1258 int ret;
1259
330e20ec 1260 intel_aux_reg_init(intel_dp);
8316f337 1261
a121f4e5
VS		 1262 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1263 if (!intel_dp->aux.name)
1264 return -ENOMEM;
1265
4d32c0d8 1266 intel_dp->aux.dev = connector->base.kdev;
9d1a1031 1267 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1268
a121f4e5
VS		 1269 DRM_DEBUG_KMS("registering %s bus for %s\n",
1270 intel_dp->aux.name,
0b99836f 1271 connector->base.kdev->kobj.name);
8316f337 1272
4f71d0cb 1273 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1274 if (ret < 0) {
4f71d0cb 1275 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
a121f4e5
VS		 1276 intel_dp->aux.name, ret);
1277 kfree(intel_dp->aux.name);
1278 return ret;
ab2c0672 1279 }
8a5e6aeb 1280
a121f4e5 1281 return 0;
a4fc5ed6
KP		 1282}
1283
80f65de3
ID		 1284static void
1285intel_dp_connector_unregister(struct intel_connector *intel_connector)
1286{
1287 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1288
4d32c0d8 1289 intel_dp_aux_fini(intel_dp);
80f65de3
ID		 1290 intel_connector_unregister(intel_connector);
1291}
1292
fc0f8e25 1293static int
12f6a2e2 1294intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1295{
94ca719e
VS		 1296 if (intel_dp->num_sink_rates) {
1297 *sink_rates = intel_dp->sink_rates;
1298 return intel_dp->num_sink_rates;
fc0f8e25 1299 }
12f6a2e2
VS		 1300
1301 *sink_rates = default_rates;
1302
1303 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1304}
1305
e588fa18 1306bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
ed63baaf 1307{
e588fa18
ACO		 1308 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1309 struct drm_device *dev = dig_port->base.base.dev;
1310
ed63baaf 1311 /* WaDisableHBR2:skl */
e87a005d 1312 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
ed63baaf
TS		 1313 return false;
1314
1315 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1316 (INTEL_INFO(dev)->gen >= 9))
1317 return true;
1318 else
1319 return false;
1320}
1321
a8f3ef61 1322static int
e588fa18 1323intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
a8f3ef61 1324{
e588fa18
ACO		 1325 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1326 struct drm_device *dev = dig_port->base.base.dev;
af7080f5
TS		 1327 int size;
1328
64987fc5
SJ		 1329 if (IS_BROXTON(dev)) {
1330 *source_rates = bxt_rates;
af7080f5 1331 size = ARRAY_SIZE(bxt_rates);
ef11bdb3 1332 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
637a9c63 1333 *source_rates = skl_rates;
af7080f5
TS		 1334 size = ARRAY_SIZE(skl_rates);
1335 } else {
1336 *source_rates = default_rates;
1337 size = ARRAY_SIZE(default_rates);
a8f3ef61 1338 }
636280ba 1339
ed63baaf 1340 /* This depends on the fact that 5.4 is last value in the array */
e588fa18 1341 if (!intel_dp_source_supports_hbr2(intel_dp))
af7080f5 1342 size--;
636280ba 1343
af7080f5 1344 return size;
a8f3ef61
SJ		 1345}
1346
c6bb3538
DV		 1347static void
1348intel_dp_set_clock(struct intel_encoder *encoder,
840b32b7 1349 struct intel_crtc_state *pipe_config)
c6bb3538
DV		 1350{
1351 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1352 const struct dp_link_dpll *divisor = NULL;
1353 int i, count = 0;
c6bb3538
DV		 1354
1355 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1356 divisor = gen4_dpll;
1357 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1358 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1359 divisor = pch_dpll;
1360 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1361 } else if (IS_CHERRYVIEW(dev)) {
1362 divisor = chv_dpll;
1363 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1364 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1365 divisor = vlv_dpll;
1366 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1367 }
9dd4ffdf
CML		 1368
1369 if (divisor && count) {
1370 for (i = 0; i < count; i++) {
840b32b7 1371 if (pipe_config->port_clock == divisor[i].clock) {
9dd4ffdf
CML		 1372 pipe_config->dpll = divisor[i].dpll;
1373 pipe_config->clock_set = true;
1374 break;
1375 }
1376 }
c6bb3538
DV		 1377 }
1378}
1379
2ecae76a
VS		 1380static int intersect_rates(const int *source_rates, int source_len,
1381 const int *sink_rates, int sink_len,
94ca719e 1382 int *common_rates)
a8f3ef61
SJ		 1383{
1384 int i = 0, j = 0, k = 0;
1385
a8f3ef61
SJ		 1386 while (i < source_len && j < sink_len) {
1387 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1388 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1389 return k;
94ca719e 1390 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1391 ++k;
1392 ++i;
1393 ++j;
1394 } else if (source_rates[i] < sink_rates[j]) {
1395 ++i;
1396 } else {
1397 ++j;
1398 }
1399 }
1400 return k;
1401}
1402
94ca719e
VS		 1403static int intel_dp_common_rates(struct intel_dp *intel_dp,
1404 int *common_rates)
2ecae76a 1405{
2ecae76a
VS		 1406 const int *source_rates, *sink_rates;
1407 int source_len, sink_len;
1408
1409 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
e588fa18 1410 source_len = intel_dp_source_rates(intel_dp, &source_rates);
2ecae76a
VS		 1411
1412 return intersect_rates(source_rates, source_len,
1413 sink_rates, sink_len,
94ca719e 1414 common_rates);
2ecae76a
VS		 1415}
1416
0336400e
VS		 1417static void snprintf_int_array(char *str, size_t len,
1418 const int *array, int nelem)
1419{
1420 int i;
1421
1422 str[0] = '\0';
1423
1424 for (i = 0; i < nelem; i++) {
b2f505be 1425 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
0336400e
VS		 1426 if (r >= len)
1427 return;
1428 str += r;
1429 len -= r;
1430 }
1431}
1432
1433static void intel_dp_print_rates(struct intel_dp *intel_dp)
1434{
0336400e 1435 const int *source_rates, *sink_rates;
94ca719e
VS		 1436 int source_len, sink_len, common_len;
1437 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1438 char str[128]; /* FIXME: too big for stack? */
1439
1440 if ((drm_debug & DRM_UT_KMS) == 0)
1441 return;
1442
e588fa18 1443 source_len = intel_dp_source_rates(intel_dp, &source_rates);
0336400e
VS		 1444 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1445 DRM_DEBUG_KMS("source rates: %s\n", str);
1446
1447 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1448 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1449 DRM_DEBUG_KMS("sink rates: %s\n", str);
1450
94ca719e
VS		 1451 common_len = intel_dp_common_rates(intel_dp, common_rates);
1452 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1453 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1454}
1455
f4896f15 1456static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1457{
1458 int i = 0;
1459
1460 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1461 if (find == rates[i])
1462 break;
1463
1464 return i;
1465}
1466
50fec21a
VS		 1467int
1468intel_dp_max_link_rate(struct intel_dp *intel_dp)
1469{
1470 int rates[DP_MAX_SUPPORTED_RATES] = {};
1471 int len;
1472
94ca719e 1473 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1474 if (WARN_ON(len <= 0))
1475 return 162000;
1476
1477 return rates[rate_to_index(0, rates) - 1];
1478}
1479
ed4e9c1d
VS		 1480int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1481{
94ca719e 1482 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1483}
1484
94223d04
ACO		 1485void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1486 uint8_t *link_bw, uint8_t *rate_select)
04a60f9f
VS		 1487{
1488 if (intel_dp->num_sink_rates) {
1489 *link_bw = 0;
1490 *rate_select =
1491 intel_dp_rate_select(intel_dp, port_clock);
1492 } else {
1493 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1494 *rate_select = 0;
1495 }
1496}
1497
00c09d70 1498bool
5bfe2ac0 1499intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1500 struct intel_crtc_state *pipe_config)
a4fc5ed6 1501{
5bfe2ac0 1502 struct drm_device *dev = encoder->base.dev;
36008365 1503 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1504 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1505 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1506 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1507 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1508 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1509 int lane_count, clock;
56071a20 1510 int min_lane_count = 1;
eeb6324d 1511 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1512 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1513 int min_clock = 0;
a8f3ef61 1514 int max_clock;
083f9560 1515 int bpp, mode_rate;
ff9a6750 1516 int link_avail, link_clock;
94ca719e
VS		 1517 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1518 int common_len;
04a60f9f 1519 uint8_t link_bw, rate_select;
a8f3ef61 1520
94ca719e 1521 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1522
1523 /* No common link rates between source and sink */
94ca719e 1524 WARN_ON(common_len <= 0);
a8f3ef61 1525
94ca719e 1526 max_clock = common_len - 1;
a4fc5ed6 1527
bc7d38a4 1528 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1529 pipe_config->has_pch_encoder = true;
1530
03afc4a2 1531 pipe_config->has_dp_encoder = true;
f769cd24 1532 pipe_config->has_drrs = false;
9fcb1704 1533 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
a4fc5ed6 1534
dd06f90e
JN		 1535 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1536 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1537 adjusted_mode);
a1b2278e
CK		 1538
1539 if (INTEL_INFO(dev)->gen >= 9) {
1540 int ret;
e435d6e5 1541 ret = skl_update_scaler_crtc(pipe_config);
a1b2278e
CK		 1542 if (ret)
1543 return ret;
1544 }
1545
b5667627 1546 if (HAS_GMCH_DISPLAY(dev))
2dd24552
JB		 1547 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1548 intel_connector->panel.fitting_mode);
1549 else
b074cec8
JB		 1550 intel_pch_panel_fitting(intel_crtc, pipe_config,
1551 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1552 }
1553
cb1793ce 1554 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1555 return false;
1556
083f9560 1557 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1558 "max bw %d pixel clock %iKHz\n",
94ca719e 1559 max_lane_count, common_rates[max_clock],
241bfc38 1560 adjusted_mode->crtc_clock);
083f9560 1561
36008365
DV		 1562 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1563 * bpc in between. */
3e7ca985 1564 bpp = pipe_config->pipe_bpp;
56071a20 1565 if (is_edp(intel_dp)) {
22ce5628
TS		 1566
1567 /* Get bpp from vbt only for panels that dont have bpp in edid */
1568 if (intel_connector->base.display_info.bpc == 0 &&
6aa23e65 1569 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
56071a20 1570 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
6aa23e65
JN		 1571 dev_priv->vbt.edp.bpp);
1572 bpp = dev_priv->vbt.edp.bpp;
56071a20
JN		 1573 }
1574
344c5bbc
JN		 1575 /*
1576 * Use the maximum clock and number of lanes the eDP panel
1577 * advertizes being capable of. The panels are generally
1578 * designed to support only a single clock and lane
1579 * configuration, and typically these values correspond to the
1580 * native resolution of the panel.
1581 */
1582 min_lane_count = max_lane_count;
1583 min_clock = max_clock;
7984211e 1584 }
657445fe 1585
36008365 1586 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1587 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1588 bpp);
36008365 1589
c6930992 1590 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1591 for (lane_count = min_lane_count;
1592 lane_count <= max_lane_count;
1593 lane_count <<= 1) {
1594
94ca719e 1595 link_clock = common_rates[clock];
36008365
DV		 1596 link_avail = intel_dp_max_data_rate(link_clock,
1597 lane_count);
1598
1599 if (mode_rate <= link_avail) {
1600 goto found;
1601 }
1602 }
1603 }
1604 }
c4867936 1605
36008365 1606 return false;
3685a8f3 1607
36008365 1608found:
55bc60db
VS		 1609 if (intel_dp->color_range_auto) {
1610 /*
1611 * See:
1612 * CEA-861-E - 5.1 Default Encoding Parameters
1613 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1614 */
0f2a2a75
VS		 1615 pipe_config->limited_color_range =
1616 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1617 } else {
1618 pipe_config->limited_color_range =
1619 intel_dp->limited_color_range;
55bc60db
VS		 1620 }
1621
90a6b7b0 1622 pipe_config->lane_count = lane_count;
a8f3ef61 1623
657445fe 1624 pipe_config->pipe_bpp = bpp;
94ca719e 1625 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1626
04a60f9f
VS		 1627 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1628 &link_bw, &rate_select);
1629
1630 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1631 link_bw, rate_select, pipe_config->lane_count,
ff9a6750 1632 pipe_config->port_clock, bpp);
36008365
DV		 1633 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1634 mode_rate, link_avail);
a4fc5ed6 1635
03afc4a2 1636 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1637 adjusted_mode->crtc_clock,
1638 pipe_config->port_clock,
03afc4a2 1639 &pipe_config->dp_m_n);
9d1a455b 1640
439d7ac0 1641 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1642 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1643 pipe_config->has_drrs = true;
439d7ac0
PB		 1644 intel_link_compute_m_n(bpp, lane_count,
1645 intel_connector->panel.downclock_mode->clock,
1646 pipe_config->port_clock,
1647 &pipe_config->dp_m2_n2);
1648 }
1649
14d41b3b
VS		 1650 /*
1651 * DPLL0 VCO may need to be adjusted to get the correct
1652 * clock for eDP. This will affect cdclk as well.
1653 */
1654 if (is_edp(intel_dp) &&
1655 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1656 int vco;
1657
1658 switch (pipe_config->port_clock / 2) {
1659 case 108000:
1660 case 216000:
63911d72 1661 vco = 8640000;
14d41b3b
VS		 1662 break;
1663 default:
63911d72 1664 vco = 8100000;
14d41b3b
VS		 1665 break;
1666 }
1667
1668 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1669 }
1670
a3c988ea 1671 if (!HAS_DDI(dev))
840b32b7 1672 intel_dp_set_clock(encoder, pipe_config);
c6bb3538 1673
03afc4a2 1674 return true;
a4fc5ed6
KP		 1675}
1676
901c2daf
VS		 1677void intel_dp_set_link_params(struct intel_dp *intel_dp,
1678 const struct intel_crtc_state *pipe_config)
1679{
1680 intel_dp->link_rate = pipe_config->port_clock;
1681 intel_dp->lane_count = pipe_config->lane_count;
1682}
1683
8ac33ed3 1684static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1685{
b934223d 1686 struct drm_device *dev = encoder->base.dev;
417e822d 1687 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1688 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1689 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1690 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
7c5f93b0 1691 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1692
901c2daf
VS		 1693 intel_dp_set_link_params(intel_dp, crtc->config);
1694
417e822d 1695 /*
1a2eb460 1696 * There are four kinds of DP registers:
417e822d
KP		 1697 *
1698 * IBX PCH
1a2eb460
KP		 1699 * SNB CPU
1700 * IVB CPU
417e822d
KP		 1701 * CPT PCH
1702 *
1703 * IBX PCH and CPU are the same for almost everything,
1704 * except that the CPU DP PLL is configured in this
1705 * register
1706 *
1707 * CPT PCH is quite different, having many bits moved
1708 * to the TRANS_DP_CTL register instead. That
1709 * configuration happens (oddly) in ironlake_pch_enable
1710 */
9c9e7927 1711
417e822d
KP		 1712 /* Preserve the BIOS-computed detected bit. This is
1713 * supposed to be read-only.
1714 */
1715 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1716
417e822d 1717 /* Handle DP bits in common between all three register formats */
417e822d 1718 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
90a6b7b0 1719 intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
a4fc5ed6 1720
417e822d 1721 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1722
39e5fa88 1723 if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1724 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1725 intel_dp->DP |= DP_SYNC_HS_HIGH;
1726 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1727 intel_dp->DP |= DP_SYNC_VS_HIGH;
1728 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1729
6aba5b6c 1730 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1731 intel_dp->DP |= DP_ENHANCED_FRAMING;
1732
7c62a164 1733 intel_dp->DP |= crtc->pipe << 29;
39e5fa88 1734 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
e3ef4479
VS		 1735 u32 trans_dp;
1736
39e5fa88 1737 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3ef4479
VS		 1738
1739 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1740 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1741 trans_dp |= TRANS_DP_ENH_FRAMING;
1742 else
1743 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1744 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
39e5fa88 1745 } else {
0f2a2a75 1746 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
666a4537 1747 !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
0f2a2a75 1748 intel_dp->DP |= DP_COLOR_RANGE_16_235;
417e822d
KP		 1749
1750 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1751 intel_dp->DP |= DP_SYNC_HS_HIGH;
1752 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1753 intel_dp->DP |= DP_SYNC_VS_HIGH;
1754 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1755
6aba5b6c 1756 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1757 intel_dp->DP |= DP_ENHANCED_FRAMING;
1758
39e5fa88 1759 if (IS_CHERRYVIEW(dev))
44f37d1f 1760 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
39e5fa88
VS		 1761 else if (crtc->pipe == PIPE_B)
1762 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 1763 }
a4fc5ed6
KP		 1764}
1765
ffd6749d
PZ		 1766#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1767#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1768
1a5ef5b7
PZ		 1769#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1770#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1771
ffd6749d
PZ		 1772#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1773#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1774
de9c1b6b
ID		 1775static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1776 struct intel_dp *intel_dp);
1777
4be73780 1778static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1779 u32 mask,
1780 u32 value)
bd943159 1781{
30add22d 1782 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1783 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 1784 i915_reg_t pp_stat_reg, pp_ctrl_reg;
453c5420 1785
e39b999a
VS		 1786 lockdep_assert_held(&dev_priv->pps_mutex);
1787
de9c1b6b
ID		 1788 intel_pps_verify_state(dev_priv, intel_dp);
1789
bf13e81b
JN		 1790 pp_stat_reg = _pp_stat_reg(intel_dp);
1791 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1792
99ea7127 1793 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1794 mask, value,
1795 I915_READ(pp_stat_reg),
1796 I915_READ(pp_ctrl_reg));
32ce697c 1797
3f177625
TU		 1798 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value,
1799 5 * USEC_PER_SEC, 10 * USEC_PER_MSEC))
99ea7127 1800 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1801 I915_READ(pp_stat_reg),
1802 I915_READ(pp_ctrl_reg));
54c136d4
CW		 1803
1804 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1805}
32ce697c 1806
4be73780 1807static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1808{
1809 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1810 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1811}
1812
4be73780 1813static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1814{
1815 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1816 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1817}
1818
4be73780 1819static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127 1820{
d28d4731
AK		 1821 ktime_t panel_power_on_time;
1822 s64 panel_power_off_duration;
1823
99ea7127 1824 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c 1825
d28d4731
AK		 1826 /* take the difference of currrent time and panel power off time
1827 * and then make panel wait for t11_t12 if needed. */
1828 panel_power_on_time = ktime_get_boottime();
1829 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1830
dce56b3c
PZ		 1831 /* When we disable the VDD override bit last we have to do the manual
1832 * wait. */
d28d4731
AK		 1833 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1834 wait_remaining_ms_from_jiffies(jiffies,
1835 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
dce56b3c 1836
4be73780 1837 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1838}
1839
4be73780 1840static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1841{
1842 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1843 intel_dp->backlight_on_delay);
1844}
1845
4be73780 1846static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1847{
1848 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1849 intel_dp->backlight_off_delay);
1850}
99ea7127 1851
832dd3c1
KP		 1852/* Read the current pp_control value, unlocking the register if it
1853 * is locked
1854 */
1855
453c5420 1856static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1857{
453c5420
JB		 1858 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1859 struct drm_i915_private *dev_priv = dev->dev_private;
1860 u32 control;
832dd3c1 1861
e39b999a
VS		 1862 lockdep_assert_held(&dev_priv->pps_mutex);
1863
bf13e81b 1864 control = I915_READ(_pp_ctrl_reg(intel_dp));
b0a08bec
VK		 1865 if (!IS_BROXTON(dev)) {
1866 control &= ~PANEL_UNLOCK_MASK;
1867 control |= PANEL_UNLOCK_REGS;
1868 }
832dd3c1 1869 return control;
bd943159
KP		 1870}
1871
951468f3
VS		 1872/*
1873 * Must be paired with edp_panel_vdd_off().
1874 * Must hold pps_mutex around the whole on/off sequence.
1875 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1876 */
1e0560e0 1877static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1878{
30add22d 1879 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1880 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1881 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1882 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1883 enum intel_display_power_domain power_domain;
5d613501 1884 u32 pp;
f0f59a00 1885 i915_reg_t pp_stat_reg, pp_ctrl_reg;
adddaaf4 1886 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1887
e39b999a
VS		 1888 lockdep_assert_held(&dev_priv->pps_mutex);
1889
97af61f5 1890 if (!is_edp(intel_dp))
adddaaf4 1891 return false;
bd943159 1892
2c623c11 1893 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1894 intel_dp->want_panel_vdd = true;
99ea7127 1895
4be73780 1896 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1897 return need_to_disable;
b0665d57 1898
25f78f58 1899 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 1900 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1901
3936fcf4
VS		 1902 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1903 port_name(intel_dig_port->port));
bd943159 1904
4be73780
DV		 1905 if (!edp_have_panel_power(intel_dp))
1906 wait_panel_power_cycle(intel_dp);
99ea7127 1907
453c5420 1908 pp = ironlake_get_pp_control(intel_dp);
5d613501 1909 pp |= EDP_FORCE_VDD;
ebf33b18 1910
bf13e81b
JN		 1911 pp_stat_reg = _pp_stat_reg(intel_dp);
1912 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1913
1914 I915_WRITE(pp_ctrl_reg, pp);
1915 POSTING_READ(pp_ctrl_reg);
1916 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1917 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1918 /*
1919 * If the panel wasn't on, delay before accessing aux channel
1920 */
4be73780 1921 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1922 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1923 port_name(intel_dig_port->port));
f01eca2e 1924 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1925 }
adddaaf4
JN		 1926
1927 return need_to_disable;
1928}
1929
951468f3
VS		 1930/*
1931 * Must be paired with intel_edp_panel_vdd_off() or
1932 * intel_edp_panel_off().
1933 * Nested calls to these functions are not allowed since
1934 * we drop the lock. Caller must use some higher level
1935 * locking to prevent nested calls from other threads.
1936 */
b80d6c78 1937void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1938{
c695b6b6 1939 bool vdd;
adddaaf4 1940
c695b6b6
VS		 1941 if (!is_edp(intel_dp))
1942 return;
1943
773538e8 1944 pps_lock(intel_dp);
c695b6b6 1945 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1946 pps_unlock(intel_dp);
c695b6b6 1947
e2c719b7 1948 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1949 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1950}
1951
4be73780 1952static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1953{
30add22d 1954 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1955 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1956 struct intel_digital_port *intel_dig_port =
1957 dp_to_dig_port(intel_dp);
1958 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1959 enum intel_display_power_domain power_domain;
5d613501 1960 u32 pp;
f0f59a00 1961 i915_reg_t pp_stat_reg, pp_ctrl_reg;
5d613501 1962
e39b999a 1963 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1964
15e899a0 1965 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1966
15e899a0 1967 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1968 return;
b0665d57 1969
3936fcf4
VS		 1970 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1971 port_name(intel_dig_port->port));
bd943159 1972
be2c9196
VS		 1973 pp = ironlake_get_pp_control(intel_dp);
1974 pp &= ~EDP_FORCE_VDD;
453c5420 1975
be2c9196
VS		 1976 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1977 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1978
be2c9196
VS		 1979 I915_WRITE(pp_ctrl_reg, pp);
1980 POSTING_READ(pp_ctrl_reg);
90791a5c 1981
be2c9196
VS		 1982 /* Make sure sequencer is idle before allowing subsequent activity */
1983 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1984 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1985
be2c9196 1986 if ((pp & POWER_TARGET_ON) == 0)
d28d4731 1987 intel_dp->panel_power_off_time = ktime_get_boottime();
e9cb81a2 1988
25f78f58 1989 power_domain = intel_display_port_aux_power_domain(intel_encoder);
be2c9196 1990 intel_display_power_put(dev_priv, power_domain);
bd943159 1991}
5d613501 1992
4be73780 1993static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1994{
1995 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1996 struct intel_dp, panel_vdd_work);
bd943159 1997
773538e8 1998 pps_lock(intel_dp);
15e899a0
VS		 1999 if (!intel_dp->want_panel_vdd)
2000 edp_panel_vdd_off_sync(intel_dp);
773538e8 2001 pps_unlock(intel_dp);
bd943159
KP		 2002}
2003
aba86890
ID		 2004static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2005{
2006 unsigned long delay;
2007
2008 /*
2009 * Queue the timer to fire a long time from now (relative to the power
2010 * down delay) to keep the panel power up across a sequence of
2011 * operations.
2012 */
2013 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2014 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2015}
2016
951468f3
VS		 2017/*
2018 * Must be paired with edp_panel_vdd_on().
2019 * Must hold pps_mutex around the whole on/off sequence.
2020 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2021 */
4be73780 2022static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 2023{
e39b999a
VS		 2024 struct drm_i915_private *dev_priv =
2025 intel_dp_to_dev(intel_dp)->dev_private;
2026
2027 lockdep_assert_held(&dev_priv->pps_mutex);
2028
97af61f5
KP		 2029 if (!is_edp(intel_dp))
2030 return;
5d613501 2031
e2c719b7 2032 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 2033 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 2034
bd943159
KP		 2035 intel_dp->want_panel_vdd = false;
2036
aba86890 2037 if (sync)
4be73780 2038 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 2039 else
2040 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 2041}
2042
9f0fb5be 2043static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 2044{
30add22d 2045 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 2046 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 2047 u32 pp;
f0f59a00 2048 i915_reg_t pp_ctrl_reg;
9934c132 2049
9f0fb5be
VS		 2050 lockdep_assert_held(&dev_priv->pps_mutex);
2051
97af61f5 2052 if (!is_edp(intel_dp))
bd943159 2053 return;
99ea7127 2054
3936fcf4
VS		 2055 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2056 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 2057
e7a89ace
VS		 2058 if (WARN(edp_have_panel_power(intel_dp),
2059 "eDP port %c panel power already on\n",
2060 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 2061 return;
9934c132 2062
4be73780 2063 wait_panel_power_cycle(intel_dp);
37c6c9b0 2064
bf13e81b 2065 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2066 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 2067 if (IS_GEN5(dev)) {
2068 /* ILK workaround: disable reset around power sequence */
2069 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 2070 I915_WRITE(pp_ctrl_reg, pp);
2071 POSTING_READ(pp_ctrl_reg);
05ce1a49 2072 }
37c6c9b0 2073
1c0ae80a 2074 pp |= POWER_TARGET_ON;
99ea7127
KP		 2075 if (!IS_GEN5(dev))
2076 pp |= PANEL_POWER_RESET;
2077
453c5420
JB		 2078 I915_WRITE(pp_ctrl_reg, pp);
2079 POSTING_READ(pp_ctrl_reg);
9934c132 2080
4be73780 2081 wait_panel_on(intel_dp);
dce56b3c 2082 intel_dp->last_power_on = jiffies;
9934c132 2083
05ce1a49
KP		 2084 if (IS_GEN5(dev)) {
2085 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 2086 I915_WRITE(pp_ctrl_reg, pp);
2087 POSTING_READ(pp_ctrl_reg);
05ce1a49 2088 }
9f0fb5be 2089}
e39b999a 2090
9f0fb5be
VS		 2091void intel_edp_panel_on(struct intel_dp *intel_dp)
2092{
2093 if (!is_edp(intel_dp))
2094 return;
2095
2096 pps_lock(intel_dp);
2097 edp_panel_on(intel_dp);
773538e8 2098 pps_unlock(intel_dp);
9934c132
JB		 2099}
2100
9f0fb5be
VS		 2101
2102static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 2103{
4e6e1a54
ID		 2104 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2105 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 2106 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 2107 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 2108 enum intel_display_power_domain power_domain;
99ea7127 2109 u32 pp;
f0f59a00 2110 i915_reg_t pp_ctrl_reg;
9934c132 2111
9f0fb5be
VS		 2112 lockdep_assert_held(&dev_priv->pps_mutex);
2113
97af61f5
KP		 2114 if (!is_edp(intel_dp))
2115 return;
37c6c9b0 2116
3936fcf4
VS		 2117 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2118 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 2119
3936fcf4
VS		 2120 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2121 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 2122
453c5420 2123 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 2124 /* We need to switch off panel power _and_ force vdd, for otherwise some
2125 * panels get very unhappy and cease to work. */
b3064154
PJ		 2126 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2127 EDP_BLC_ENABLE);
453c5420 2128
bf13e81b 2129 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2130
849e39f5
PZ		 2131 intel_dp->want_panel_vdd = false;
2132
453c5420
JB		 2133 I915_WRITE(pp_ctrl_reg, pp);
2134 POSTING_READ(pp_ctrl_reg);
9934c132 2135
d28d4731 2136 intel_dp->panel_power_off_time = ktime_get_boottime();
4be73780 2137 wait_panel_off(intel_dp);
849e39f5
PZ		 2138
2139 /* We got a reference when we enabled the VDD. */
25f78f58 2140 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 2141 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 2142}
e39b999a 2143
9f0fb5be
VS		 2144void intel_edp_panel_off(struct intel_dp *intel_dp)
2145{
2146 if (!is_edp(intel_dp))
2147 return;
e39b999a 2148
9f0fb5be
VS		 2149 pps_lock(intel_dp);
2150 edp_panel_off(intel_dp);
773538e8 2151 pps_unlock(intel_dp);
9934c132
JB		 2152}
2153
1250d107
JN		 2154/* Enable backlight in the panel power control. */
2155static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 2156{
da63a9f2
PZ		 2157 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2158 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 2159 struct drm_i915_private *dev_priv = dev->dev_private;
2160 u32 pp;
f0f59a00 2161 i915_reg_t pp_ctrl_reg;
32f9d658 2162
01cb9ea6
JB		 2163 /*
2164 * If we enable the backlight right away following a panel power
2165 * on, we may see slight flicker as the panel syncs with the eDP
2166 * link. So delay a bit to make sure the image is solid before
2167 * allowing it to appear.
2168 */
4be73780 2169 wait_backlight_on(intel_dp);
e39b999a 2170
773538e8 2171 pps_lock(intel_dp);
e39b999a 2172
453c5420 2173 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2174 pp |= EDP_BLC_ENABLE;
453c5420 2175
bf13e81b 2176 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2177
2178 I915_WRITE(pp_ctrl_reg, pp);
2179 POSTING_READ(pp_ctrl_reg);
e39b999a 2180
773538e8 2181 pps_unlock(intel_dp);
32f9d658
ZW		 2182}
2183
1250d107
JN		 2184/* Enable backlight PWM and backlight PP control. */
2185void intel_edp_backlight_on(struct intel_dp *intel_dp)
2186{
2187 if (!is_edp(intel_dp))
2188 return;
2189
2190 DRM_DEBUG_KMS("\n");
2191
2192 intel_panel_enable_backlight(intel_dp->attached_connector);
2193 _intel_edp_backlight_on(intel_dp);
2194}
2195
2196/* Disable backlight in the panel power control. */
2197static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2198{
30add22d 2199 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 2200 struct drm_i915_private *dev_priv = dev->dev_private;
2201 u32 pp;
f0f59a00 2202 i915_reg_t pp_ctrl_reg;
32f9d658 2203
f01eca2e
KP		 2204 if (!is_edp(intel_dp))
2205 return;
2206
773538e8 2207 pps_lock(intel_dp);
e39b999a 2208
453c5420 2209 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2210 pp &= ~EDP_BLC_ENABLE;
453c5420 2211
bf13e81b 2212 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2213
2214 I915_WRITE(pp_ctrl_reg, pp);
2215 POSTING_READ(pp_ctrl_reg);
f7d2323c 2216
773538e8 2217 pps_unlock(intel_dp);
e39b999a
VS		 2218
2219 intel_dp->last_backlight_off = jiffies;
f7d2323c 2220 edp_wait_backlight_off(intel_dp);
1250d107 2221}
f7d2323c 2222
1250d107
JN		 2223/* Disable backlight PP control and backlight PWM. */
2224void intel_edp_backlight_off(struct intel_dp *intel_dp)
2225{
2226 if (!is_edp(intel_dp))
2227 return;
2228
2229 DRM_DEBUG_KMS("\n");
f7d2323c 2230
1250d107 2231 _intel_edp_backlight_off(intel_dp);
f7d2323c 2232 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2233}
a4fc5ed6 2234
73580fb7
JN		 2235/*
2236 * Hook for controlling the panel power control backlight through the bl_power
2237 * sysfs attribute. Take care to handle multiple calls.
2238 */
2239static void intel_edp_backlight_power(struct intel_connector *connector,
2240 bool enable)
2241{
2242 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2243 bool is_enabled;
2244
773538e8 2245 pps_lock(intel_dp);
e39b999a 2246 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2247 pps_unlock(intel_dp);
73580fb7
JN		 2248
2249 if (is_enabled == enable)
2250 return;
2251
23ba9373
JN		 2252 DRM_DEBUG_KMS("panel power control backlight %s\n",
2253 enable ? "enable" : "disable");
73580fb7
JN		 2254
2255 if (enable)
2256 _intel_edp_backlight_on(intel_dp);
2257 else
2258 _intel_edp_backlight_off(intel_dp);
2259}
2260
64e1077a
VS		 2261static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2262{
2263 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2264 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2265 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2266
2267 I915_STATE_WARN(cur_state != state,
2268 "DP port %c state assertion failure (expected %s, current %s)\n",
2269 port_name(dig_port->port),
87ad3212 2270 onoff(state), onoff(cur_state));
64e1077a
VS		 2271}
2272#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2273
2274static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2275{
2276 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2277
2278 I915_STATE_WARN(cur_state != state,
2279 "eDP PLL state assertion failure (expected %s, current %s)\n",
87ad3212 2280 onoff(state), onoff(cur_state));
64e1077a
VS		 2281}
2282#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2283#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2284
2bd2ad64 2285static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 2286{
da63a9f2 2287 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2288 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2289 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2290
64e1077a
VS		 2291 assert_pipe_disabled(dev_priv, crtc->pipe);
2292 assert_dp_port_disabled(intel_dp);
2293 assert_edp_pll_disabled(dev_priv);
2bd2ad64 2294
abfce949
VS		 2295 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2296 crtc->config->port_clock);
2297
2298 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2299
2300 if (crtc->config->port_clock == 162000)
2301 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2302 else
2303 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2304
2305 I915_WRITE(DP_A, intel_dp->DP);
2306 POSTING_READ(DP_A);
2307 udelay(500);
2308
6b23f3e8
VS		 2309 /*
2310 * [DevILK] Work around required when enabling DP PLL
2311 * while a pipe is enabled going to FDI:
2312 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2313 * 2. Program DP PLL enable
2314 */
2315 if (IS_GEN5(dev_priv))
2316 intel_wait_for_vblank_if_active(dev_priv->dev, !crtc->pipe);
2317
0767935e 2318 intel_dp->DP |= DP_PLL_ENABLE;
6fec7662 2319
0767935e 2320 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2321 POSTING_READ(DP_A);
2322 udelay(200);
d240f20f
JB		 2323}
2324
2bd2ad64 2325static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2326{
da63a9f2 2327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2328 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2329 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2330
64e1077a
VS		 2331 assert_pipe_disabled(dev_priv, crtc->pipe);
2332 assert_dp_port_disabled(intel_dp);
2333 assert_edp_pll_enabled(dev_priv);
2bd2ad64 2334
abfce949
VS		 2335 DRM_DEBUG_KMS("disabling eDP PLL\n");
2336
6fec7662 2337 intel_dp->DP &= ~DP_PLL_ENABLE;
0767935e 2338
6fec7662 2339 I915_WRITE(DP_A, intel_dp->DP);
1af5fa1b 2340 POSTING_READ(DP_A);
d240f20f
JB		 2341 udelay(200);
2342}
2343
c7ad3810 2344/* If the sink supports it, try to set the power state appropriately */
c19b0669 2345void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2346{
2347 int ret, i;
2348
2349 /* Should have a valid DPCD by this point */
2350 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2351 return;
2352
2353 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2354 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2355 DP_SET_POWER_D3);
c7ad3810
JB		 2356 } else {
2357 /*
2358 * When turning on, we need to retry for 1ms to give the sink
2359 * time to wake up.
2360 */
2361 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2362 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2363 DP_SET_POWER_D0);
c7ad3810
JB		 2364 if (ret == 1)
2365 break;
2366 msleep(1);
2367 }
2368 }
f9cac721
JN		 2369
2370 if (ret != 1)
2371 DRM_DEBUG_KMS("failed to %s sink power state\n",
2372 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2373}
2374
19d8fe15
DV		 2375static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2376 enum pipe *pipe)
d240f20f 2377{
19d8fe15 2378 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2379 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 2380 struct drm_device *dev = encoder->base.dev;
2381 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 2382 enum intel_display_power_domain power_domain;
2383 u32 tmp;
6fa9a5ec 2384 bool ret;
6d129bea
ID		 2385
2386 power_domain = intel_display_port_power_domain(encoder);
6fa9a5ec 2387 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 2388 return false;
2389
6fa9a5ec
ID		 2390 ret = false;
2391
6d129bea 2392 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2393
2394 if (!(tmp & DP_PORT_EN))
6fa9a5ec 2395 goto out;
19d8fe15 2396
39e5fa88 2397 if (IS_GEN7(dev) && port == PORT_A) {
19d8fe15 2398 *pipe = PORT_TO_PIPE_CPT(tmp);
39e5fa88 2399 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
adc289d7 2400 enum pipe p;
19d8fe15 2401
adc289d7
VS		 2402 for_each_pipe(dev_priv, p) {
2403 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2404 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2405 *pipe = p;
6fa9a5ec
ID		 2406 ret = true;
2407
2408 goto out;
19d8fe15
DV		 2409 }
2410 }
19d8fe15 2411
4a0833ec 2412 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
f0f59a00 2413 i915_mmio_reg_offset(intel_dp->output_reg));
39e5fa88
VS		 2414 } else if (IS_CHERRYVIEW(dev)) {
2415 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2416 } else {
2417 *pipe = PORT_TO_PIPE(tmp);
4a0833ec 2418 }
d240f20f 2419
6fa9a5ec
ID		 2420 ret = true;
2421
2422out:
2423 intel_display_power_put(dev_priv, power_domain);
2424
2425 return ret;
19d8fe15 2426}
d240f20f 2427
045ac3b5 2428static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2429 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2430{
2431 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2432 u32 tmp, flags = 0;
63000ef6
XZ		 2433 struct drm_device *dev = encoder->base.dev;
2434 struct drm_i915_private *dev_priv = dev->dev_private;
2435 enum port port = dp_to_dig_port(intel_dp)->port;
2436 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 2437
9ed109a7 2438 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2439
2440 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2441
39e5fa88 2442 if (HAS_PCH_CPT(dev) && port != PORT_A) {
b81e34c2
VS		 2443 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2444
2445 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2446 flags |= DRM_MODE_FLAG_PHSYNC;
2447 else
2448 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2449
b81e34c2 2450 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2451 flags |= DRM_MODE_FLAG_PVSYNC;
2452 else
2453 flags |= DRM_MODE_FLAG_NVSYNC;
2454 } else {
39e5fa88 2455 if (tmp & DP_SYNC_HS_HIGH)
63000ef6
XZ		 2456 flags |= DRM_MODE_FLAG_PHSYNC;
2457 else
2458 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2459
39e5fa88 2460 if (tmp & DP_SYNC_VS_HIGH)
63000ef6
XZ		 2461 flags |= DRM_MODE_FLAG_PVSYNC;
2462 else
2463 flags |= DRM_MODE_FLAG_NVSYNC;
2464 }
045ac3b5 2465
2d112de7 2466 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2467
8c875fca 2468 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
666a4537 2469 !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
8c875fca
VS		 2470 pipe_config->limited_color_range = true;
2471
eb14cb74
VS		 2472 pipe_config->has_dp_encoder = true;
2473
90a6b7b0
VS		 2474 pipe_config->lane_count =
2475 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2476
eb14cb74
VS		 2477 intel_dp_get_m_n(crtc, pipe_config);
2478
18442d08 2479 if (port == PORT_A) {
b377e0df 2480 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
f1f644dc
JB		 2481 pipe_config->port_clock = 162000;
2482 else
2483 pipe_config->port_clock = 270000;
2484 }
18442d08 2485
e3b247da
VS		 2486 pipe_config->base.adjusted_mode.crtc_clock =
2487 intel_dotclock_calculate(pipe_config->port_clock,
2488 &pipe_config->dp_m_n);
7f16e5c1 2489
6aa23e65
JN		 2490 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2491 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
c6cd2ee2
JN		 2492 /*
2493 * This is a big fat ugly hack.
2494 *
2495 * Some machines in UEFI boot mode provide us a VBT that has 18
2496 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2497 * unknown we fail to light up. Yet the same BIOS boots up with
2498 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2499 * max, not what it tells us to use.
2500 *
2501 * Note: This will still be broken if the eDP panel is not lit
2502 * up by the BIOS, and thus we can't get the mode at module
2503 * load.
2504 */
2505 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2506 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2507 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
c6cd2ee2 2508 }
045ac3b5
JB		 2509}
2510
e8cb4558 2511static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2512{
e8cb4558 2513 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2514 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2515 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2516
6e3c9717 2517 if (crtc->config->has_audio)
495a5bb8 2518 intel_audio_codec_disable(encoder);
6cb49835 2519
b32c6f48
RV		 2520 if (HAS_PSR(dev) && !HAS_DDI(dev))
2521 intel_psr_disable(intel_dp);
2522
6cb49835
DV		 2523 /* Make sure the panel is off before trying to change the mode. But also
2524 * ensure that we have vdd while we switch off the panel. */
24f3e092 2525 intel_edp_panel_vdd_on(intel_dp);
4be73780 2526 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2527 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2528 intel_edp_panel_off(intel_dp);
3739850b 2529
08aff3fe
VS		 2530 /* disable the port before the pipe on g4x */
2531 if (INTEL_INFO(dev)->gen < 5)
3739850b 2532 intel_dp_link_down(intel_dp);
d240f20f
JB		 2533}
2534
08aff3fe 2535static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2536{
2bd2ad64 2537 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2538 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2539
49277c31 2540 intel_dp_link_down(intel_dp);
abfce949
VS		 2541
2542 /* Only ilk+ has port A */
08aff3fe
VS		 2543 if (port == PORT_A)
2544 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2545}
2546
2547static void vlv_post_disable_dp(struct intel_encoder *encoder)
2548{
2549 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2550
2551 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2552}
2553
a8f327fb
VS		 2554static void chv_post_disable_dp(struct intel_encoder *encoder)
2555{
2556 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2557 struct drm_device *dev = encoder->base.dev;
2558 struct drm_i915_private *dev_priv = dev->dev_private;
97fd4d5c 2559
a8f327fb
VS		 2560 intel_dp_link_down(intel_dp);
2561
2562 mutex_lock(&dev_priv->sb_lock);
2563
2564 /* Assert data lane reset */
2565 chv_data_lane_soft_reset(encoder, true);
580d3811 2566
a580516d 2567 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 2568}
2569
7b13b58a
VS		 2570static void
2571_intel_dp_set_link_train(struct intel_dp *intel_dp,
2572 uint32_t *DP,
2573 uint8_t dp_train_pat)
2574{
2575 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2576 struct drm_device *dev = intel_dig_port->base.base.dev;
2577 struct drm_i915_private *dev_priv = dev->dev_private;
2578 enum port port = intel_dig_port->port;
2579
2580 if (HAS_DDI(dev)) {
2581 uint32_t temp = I915_READ(DP_TP_CTL(port));
2582
2583 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2584 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2585 else
2586 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2587
2588 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2589 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2590 case DP_TRAINING_PATTERN_DISABLE:
2591 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2592
2593 break;
2594 case DP_TRAINING_PATTERN_1:
2595 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2596 break;
2597 case DP_TRAINING_PATTERN_2:
2598 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2599 break;
2600 case DP_TRAINING_PATTERN_3:
2601 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2602 break;
2603 }
2604 I915_WRITE(DP_TP_CTL(port), temp);
2605
39e5fa88
VS		 2606 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2607 (HAS_PCH_CPT(dev) && port != PORT_A)) {
7b13b58a
VS		 2608 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2609
2610 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2611 case DP_TRAINING_PATTERN_DISABLE:
2612 *DP |= DP_LINK_TRAIN_OFF_CPT;
2613 break;
2614 case DP_TRAINING_PATTERN_1:
2615 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2616 break;
2617 case DP_TRAINING_PATTERN_2:
2618 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2619 break;
2620 case DP_TRAINING_PATTERN_3:
2621 DRM_ERROR("DP training pattern 3 not supported\n");
2622 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2623 break;
2624 }
2625
2626 } else {
2627 if (IS_CHERRYVIEW(dev))
2628 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2629 else
2630 *DP &= ~DP_LINK_TRAIN_MASK;
2631
2632 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2633 case DP_TRAINING_PATTERN_DISABLE:
2634 *DP |= DP_LINK_TRAIN_OFF;
2635 break;
2636 case DP_TRAINING_PATTERN_1:
2637 *DP |= DP_LINK_TRAIN_PAT_1;
2638 break;
2639 case DP_TRAINING_PATTERN_2:
2640 *DP |= DP_LINK_TRAIN_PAT_2;
2641 break;
2642 case DP_TRAINING_PATTERN_3:
2643 if (IS_CHERRYVIEW(dev)) {
2644 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2645 } else {
2646 DRM_ERROR("DP training pattern 3 not supported\n");
2647 *DP |= DP_LINK_TRAIN_PAT_2;
2648 }
2649 break;
2650 }
2651 }
2652}
2653
2654static void intel_dp_enable_port(struct intel_dp *intel_dp)
2655{
2656 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2657 struct drm_i915_private *dev_priv = dev->dev_private;
6fec7662
VS		 2658 struct intel_crtc *crtc =
2659 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
7b13b58a 2660
7b13b58a
VS		 2661 /* enable with pattern 1 (as per spec) */
2662 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2663 DP_TRAINING_PATTERN_1);
2664
2665 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2666 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2667
2668 /*
2669 * Magic for VLV/CHV. We _must_ first set up the register
2670 * without actually enabling the port, and then do another
2671 * write to enable the port. Otherwise link training will
2672 * fail when the power sequencer is freshly used for this port.
2673 */
2674 intel_dp->DP |= DP_PORT_EN;
6fec7662
VS		 2675 if (crtc->config->has_audio)
2676 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
7b713f50
VS		 2677
2678 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2679 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2680}
2681
e8cb4558 2682static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2683{
e8cb4558
DV		 2684 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2685 struct drm_device *dev = encoder->base.dev;
2686 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2687 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2688 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
d6fbdd15 2689 enum pipe pipe = crtc->pipe;
5d613501 2690
0c33d8d7
DV		 2691 if (WARN_ON(dp_reg & DP_PORT_EN))
2692 return;
5d613501 2693
093e3f13
VS		 2694 pps_lock(intel_dp);
2695
666a4537 2696 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
093e3f13
VS		 2697 vlv_init_panel_power_sequencer(intel_dp);
2698
7b13b58a 2699 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2700
2701 edp_panel_vdd_on(intel_dp);
2702 edp_panel_on(intel_dp);
2703 edp_panel_vdd_off(intel_dp, true);
2704
2705 pps_unlock(intel_dp);
2706
666a4537 2707 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e0fce78f
VS		 2708 unsigned int lane_mask = 0x0;
2709
2710 if (IS_CHERRYVIEW(dev))
2711 lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2712
9b6de0a1
VS		 2713 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2714 lane_mask);
e0fce78f 2715 }
61234fa5 2716
f01eca2e 2717 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2718 intel_dp_start_link_train(intel_dp);
3ab9c637 2719 intel_dp_stop_link_train(intel_dp);
c1dec79a 2720
6e3c9717 2721 if (crtc->config->has_audio) {
c1dec79a 2722 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
d6fbdd15 2723 pipe_name(pipe));
c1dec79a
JN		 2724 intel_audio_codec_enable(encoder);
2725 }
ab1f90f9 2726}
89b667f8 2727
ecff4f3b
JN		 2728static void g4x_enable_dp(struct intel_encoder *encoder)
2729{
828f5c6e
JN		 2730 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2731
ecff4f3b 2732 intel_enable_dp(encoder);
4be73780 2733 intel_edp_backlight_on(intel_dp);
ab1f90f9 2734}
89b667f8 2735
ab1f90f9
JN		 2736static void vlv_enable_dp(struct intel_encoder *encoder)
2737{
828f5c6e
JN		 2738 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2739
4be73780 2740 intel_edp_backlight_on(intel_dp);
b32c6f48 2741 intel_psr_enable(intel_dp);
d240f20f
JB		 2742}
2743
ecff4f3b 2744static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2745{
2746 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6fbdd15 2747 enum port port = dp_to_dig_port(intel_dp)->port;
ab1f90f9 2748
8ac33ed3
DV		 2749 intel_dp_prepare(encoder);
2750
d41f1efb 2751 /* Only ilk+ has port A */
abfce949 2752 if (port == PORT_A)
ab1f90f9
JN		 2753 ironlake_edp_pll_on(intel_dp);
2754}
2755
83b84597
VS		 2756static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2757{
2758 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2759 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2760 enum pipe pipe = intel_dp->pps_pipe;
f0f59a00 2761 i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
83b84597
VS		 2762
2763 edp_panel_vdd_off_sync(intel_dp);
2764
2765 /*
2766 * VLV seems to get confused when multiple power seqeuencers
2767 * have the same port selected (even if only one has power/vdd
2768 * enabled). The failure manifests as vlv_wait_port_ready() failing
2769 * CHV on the other hand doesn't seem to mind having the same port
2770 * selected in multiple power seqeuencers, but let's clear the
2771 * port select always when logically disconnecting a power sequencer
2772 * from a port.
2773 */
2774 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2775 pipe_name(pipe), port_name(intel_dig_port->port));
2776 I915_WRITE(pp_on_reg, 0);
2777 POSTING_READ(pp_on_reg);
2778
2779 intel_dp->pps_pipe = INVALID_PIPE;
2780}
2781
a4a5d2f8
VS		 2782static void vlv_steal_power_sequencer(struct drm_device *dev,
2783 enum pipe pipe)
2784{
2785 struct drm_i915_private *dev_priv = dev->dev_private;
2786 struct intel_encoder *encoder;
2787
2788 lockdep_assert_held(&dev_priv->pps_mutex);
2789
ac3c12e4
VS		 2790 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2791 return;
2792
19c8054c 2793 for_each_intel_encoder(dev, encoder) {
a4a5d2f8 2794 struct intel_dp *intel_dp;
773538e8 2795 enum port port;
a4a5d2f8
VS		 2796
2797 if (encoder->type != INTEL_OUTPUT_EDP)
2798 continue;
2799
2800 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2801 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2802
2803 if (intel_dp->pps_pipe != pipe)
2804 continue;
2805
2806 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2807 pipe_name(pipe), port_name(port));
a4a5d2f8 2808
e02f9a06 2809 WARN(encoder->base.crtc,
034e43c6
VS		 2810 "stealing pipe %c power sequencer from active eDP port %c\n",
2811 pipe_name(pipe), port_name(port));
a4a5d2f8 2812
a4a5d2f8 2813 /* make sure vdd is off before we steal it */
83b84597 2814 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2815 }
2816}
2817
2818static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2819{
2820 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2821 struct intel_encoder *encoder = &intel_dig_port->base;
2822 struct drm_device *dev = encoder->base.dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2825
2826 lockdep_assert_held(&dev_priv->pps_mutex);
2827
093e3f13
VS		 2828 if (!is_edp(intel_dp))
2829 return;
2830
a4a5d2f8
VS		 2831 if (intel_dp->pps_pipe == crtc->pipe)
2832 return;
2833
2834 /*
2835 * If another power sequencer was being used on this
2836 * port previously make sure to turn off vdd there while
2837 * we still have control of it.
2838 */
2839 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2840 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2841
2842 /*
2843 * We may be stealing the power
2844 * sequencer from another port.
2845 */
2846 vlv_steal_power_sequencer(dev, crtc->pipe);
2847
2848 /* now it's all ours */
2849 intel_dp->pps_pipe = crtc->pipe;
2850
2851 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2852 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2853
2854 /* init power sequencer on this pipe and port */
36b5f425
VS		 2855 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2856 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2857}
2858
ab1f90f9 2859static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2860{
5f68c275 2861 vlv_phy_pre_encoder_enable(encoder);
ab1f90f9
JN		 2862
2863 intel_enable_dp(encoder);
89b667f8
JB		 2864}
2865
ecff4f3b 2866static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8 2867{
8ac33ed3
DV		 2868 intel_dp_prepare(encoder);
2869
6da2e616 2870 vlv_phy_pre_pll_enable(encoder);
a4fc5ed6
KP		 2871}
2872
e4a1d846
CML		 2873static void chv_pre_enable_dp(struct intel_encoder *encoder)
2874{
e7d2a717 2875 chv_phy_pre_encoder_enable(encoder);
e4a1d846 2876
e4a1d846 2877 intel_enable_dp(encoder);
b0b33846
VS		 2878
2879 /* Second common lane will stay alive on its own now */
e7d2a717 2880 chv_phy_release_cl2_override(encoder);
e4a1d846
CML		 2881}
2882
9197c88b
VS		 2883static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2884{
625695f8
VS		 2885 intel_dp_prepare(encoder);
2886
419b1b7a 2887 chv_phy_pre_pll_enable(encoder);
9197c88b
VS		 2888}
2889
d6db995f
VS		 2890static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
2891{
204970b5 2892 chv_phy_post_pll_disable(encoder);
d6db995f
VS		 2893}
2894
a4fc5ed6
KP		 2895/*
2896 * Fetch AUX CH registers 0x202 - 0x207 which contain
2897 * link status information
2898 */
94223d04 2899bool
93f62dad 2900intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2901{
9f085ebb
L		 2902 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2903 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2904}
2905
1100244e 2906/* These are source-specific values. */
94223d04 2907uint8_t
1a2eb460 2908intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2909{
30add22d 2910 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 2911 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 2912 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2913
9314726b
VK		 2914 if (IS_BROXTON(dev))
2915 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2916 else if (INTEL_INFO(dev)->gen >= 9) {
06411f08 2917 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
7ad14a29 2918 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2919 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
666a4537 2920 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
bd60018a 2921 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2922 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2923 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2924 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2925 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2926 else
bd60018a 2927 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2928}
2929
94223d04 2930uint8_t
1a2eb460
KP		 2931intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2932{
30add22d 2933 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2934 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2935
5a9d1f1a
DL		 2936 if (INTEL_INFO(dev)->gen >= 9) {
2937 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2938 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2939 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2940 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2941 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2942 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2943 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 2944 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2945 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 2946 default:
2947 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2948 }
2949 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2950 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2951 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2952 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2953 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2954 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2955 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2956 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2957 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2958 default:
bd60018a 2959 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2960 }
666a4537 2961 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e2fa6fba 2962 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2963 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2964 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2965 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2966 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2967 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2968 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2969 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2970 default:
bd60018a 2971 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2972 }
bc7d38a4 2973 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2974 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2975 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2976 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2977 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2978 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2979 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2980 default:
bd60018a 2981 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2982 }
2983 } else {
2984 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2985 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2986 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2987 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2988 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2989 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2990 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2991 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2992 default:
bd60018a 2993 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2994 }
a4fc5ed6
KP		 2995 }
2996}
2997
5829975c 2998static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba 2999{
53d98725 3000 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
e2fa6fba
P		 3001 unsigned long demph_reg_value, preemph_reg_value,
3002 uniqtranscale_reg_value;
3003 uint8_t train_set = intel_dp->train_set[0];
e2fa6fba
P		 3004
3005 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3006 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3007 preemph_reg_value = 0x0004000;
3008 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3009 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3010 demph_reg_value = 0x2B405555;
3011 uniqtranscale_reg_value = 0x552AB83A;
3012 break;
bd60018a 3013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3014 demph_reg_value = 0x2B404040;
3015 uniqtranscale_reg_value = 0x5548B83A;
3016 break;
bd60018a 3017 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3018 demph_reg_value = 0x2B245555;
3019 uniqtranscale_reg_value = 0x5560B83A;
3020 break;
bd60018a 3021 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3022 demph_reg_value = 0x2B405555;
3023 uniqtranscale_reg_value = 0x5598DA3A;
3024 break;
3025 default:
3026 return 0;
3027 }
3028 break;
bd60018a 3029 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3030 preemph_reg_value = 0x0002000;
3031 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3032 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3033 demph_reg_value = 0x2B404040;
3034 uniqtranscale_reg_value = 0x5552B83A;
3035 break;
bd60018a 3036 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3037 demph_reg_value = 0x2B404848;
3038 uniqtranscale_reg_value = 0x5580B83A;
3039 break;
bd60018a 3040 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3041 demph_reg_value = 0x2B404040;
3042 uniqtranscale_reg_value = 0x55ADDA3A;
3043 break;
3044 default:
3045 return 0;
3046 }
3047 break;
bd60018a 3048 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3049 preemph_reg_value = 0x0000000;
3050 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3051 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3052 demph_reg_value = 0x2B305555;
3053 uniqtranscale_reg_value = 0x5570B83A;
3054 break;
bd60018a 3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3056 demph_reg_value = 0x2B2B4040;
3057 uniqtranscale_reg_value = 0x55ADDA3A;
3058 break;
3059 default:
3060 return 0;
3061 }
3062 break;
bd60018a 3063 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3064 preemph_reg_value = 0x0006000;
3065 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3066 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3067 demph_reg_value = 0x1B405555;
3068 uniqtranscale_reg_value = 0x55ADDA3A;
3069 break;
3070 default:
3071 return 0;
3072 }
3073 break;
3074 default:
3075 return 0;
3076 }
3077
53d98725
ACO		 3078 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3079 uniqtranscale_reg_value, 0);
e2fa6fba
P		 3080
3081 return 0;
3082}
3083
5829975c 3084static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846 3085{
b7fa22d8
ACO		 3086 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3087 u32 deemph_reg_value, margin_reg_value;
3088 bool uniq_trans_scale = false;
e4a1d846 3089 uint8_t train_set = intel_dp->train_set[0];
e4a1d846
CML		 3090
3091 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3092 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3093 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3094 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3095 deemph_reg_value = 128;
3096 margin_reg_value = 52;
3097 break;
bd60018a 3098 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3099 deemph_reg_value = 128;
3100 margin_reg_value = 77;
3101 break;
bd60018a 3102 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3103 deemph_reg_value = 128;
3104 margin_reg_value = 102;
3105 break;
bd60018a 3106 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3107 deemph_reg_value = 128;
3108 margin_reg_value = 154;
b7fa22d8 3109 uniq_trans_scale = true;
e4a1d846
CML		 3110 break;
3111 default:
3112 return 0;
3113 }
3114 break;
bd60018a 3115 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3116 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3117 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3118 deemph_reg_value = 85;
3119 margin_reg_value = 78;
3120 break;
bd60018a 3121 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3122 deemph_reg_value = 85;
3123 margin_reg_value = 116;
3124 break;
bd60018a 3125 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3126 deemph_reg_value = 85;
3127 margin_reg_value = 154;
3128 break;
3129 default:
3130 return 0;
3131 }
3132 break;
bd60018a 3133 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3134 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3135 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3136 deemph_reg_value = 64;
3137 margin_reg_value = 104;
3138 break;
bd60018a 3139 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3140 deemph_reg_value = 64;
3141 margin_reg_value = 154;
3142 break;
3143 default:
3144 return 0;
3145 }
3146 break;
bd60018a 3147 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3148 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3149 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3150 deemph_reg_value = 43;
3151 margin_reg_value = 154;
3152 break;
3153 default:
3154 return 0;
3155 }
3156 break;
3157 default:
3158 return 0;
3159 }
3160
b7fa22d8
ACO		 3161 chv_set_phy_signal_level(encoder, deemph_reg_value,
3162 margin_reg_value, uniq_trans_scale);
e4a1d846
CML		 3163
3164 return 0;
3165}
3166
a4fc5ed6 3167static uint32_t
5829975c 3168gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3169{
3cf2efb1 3170 uint32_t signal_levels = 0;
a4fc5ed6 3171
3cf2efb1 3172 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3173 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3174 default:
3175 signal_levels |= DP_VOLTAGE_0_4;
3176 break;
bd60018a 3177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3178 signal_levels |= DP_VOLTAGE_0_6;
3179 break;
bd60018a 3180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3181 signal_levels |= DP_VOLTAGE_0_8;
3182 break;
bd60018a 3183 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3184 signal_levels |= DP_VOLTAGE_1_2;
3185 break;
3186 }
3cf2efb1 3187 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3188 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3189 default:
3190 signal_levels |= DP_PRE_EMPHASIS_0;
3191 break;
bd60018a 3192 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3193 signal_levels |= DP_PRE_EMPHASIS_3_5;
3194 break;
bd60018a 3195 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3196 signal_levels |= DP_PRE_EMPHASIS_6;
3197 break;
bd60018a 3198 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3199 signal_levels |= DP_PRE_EMPHASIS_9_5;
3200 break;
3201 }
3202 return signal_levels;
3203}
3204
e3421a18
ZW		 3205/* Gen6's DP voltage swing and pre-emphasis control */
3206static uint32_t
5829975c 3207gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3208{
3c5a62b5
YL		 3209 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3210 DP_TRAIN_PRE_EMPHASIS_MASK);
3211 switch (signal_levels) {
bd60018a
SJ		 3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3214 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3215 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3216 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3217 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3218 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3219 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3220 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3221 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3222 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3223 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3224 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3225 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3226 default:
3c5a62b5
YL		 3227 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3228 "0x%x\n", signal_levels);
3229 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3230 }
3231}
3232
1a2eb460
KP		 3233/* Gen7's DP voltage swing and pre-emphasis control */
3234static uint32_t
5829975c 3235gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3236{
3237 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3238 DP_TRAIN_PRE_EMPHASIS_MASK);
3239 switch (signal_levels) {
bd60018a 3240 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3241 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3243 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3244 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3245 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3246
bd60018a 3247 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3248 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3249 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3250 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3251
bd60018a 3252 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3253 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3254 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3255 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3256
3257 default:
3258 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3259 "0x%x\n", signal_levels);
3260 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3261 }
3262}
3263
94223d04 3264void
f4eb692e 3265intel_dp_set_signal_levels(struct intel_dp *intel_dp)
f0a3424e
PZ		 3266{
3267 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3268 enum port port = intel_dig_port->port;
f0a3424e 3269 struct drm_device *dev = intel_dig_port->base.base.dev;
b905a915 3270 struct drm_i915_private *dev_priv = to_i915(dev);
f8896f5d 3271 uint32_t signal_levels, mask = 0;
f0a3424e
PZ		 3272 uint8_t train_set = intel_dp->train_set[0];
3273
f8896f5d
DW		 3274 if (HAS_DDI(dev)) {
3275 signal_levels = ddi_signal_levels(intel_dp);
3276
3277 if (IS_BROXTON(dev))
3278 signal_levels = 0;
3279 else
3280 mask = DDI_BUF_EMP_MASK;
e4a1d846 3281 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3282 signal_levels = chv_signal_levels(intel_dp);
e2fa6fba 3283 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3284 signal_levels = vlv_signal_levels(intel_dp);
bc7d38a4 3285 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3286 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3287 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3288 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3289 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3290 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3291 } else {
5829975c 3292 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3293 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3294 }
3295
96fb9f9b
VK		 3296 if (mask)
3297 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3298
3299 DRM_DEBUG_KMS("Using vswing level %d\n",
3300 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3301 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3302 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3303 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e 3304
f4eb692e 3305 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
b905a915
ACO		 3306
3307 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3308 POSTING_READ(intel_dp->output_reg);
f0a3424e
PZ		 3309}
3310
94223d04 3311void
e9c176d5
ACO		 3312intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3313 uint8_t dp_train_pat)
a4fc5ed6 3314{
174edf1f 3315 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
90a6b7b0
VS		 3316 struct drm_i915_private *dev_priv =
3317 to_i915(intel_dig_port->base.base.dev);
a4fc5ed6 3318
f4eb692e 3319 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
47ea7542 3320
f4eb692e 3321 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
ea5b213a 3322 POSTING_READ(intel_dp->output_reg);
e9c176d5
ACO		 3323}
3324
94223d04 3325void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3ab9c637
ID		 3326{
3327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3328 struct drm_device *dev = intel_dig_port->base.base.dev;
3329 struct drm_i915_private *dev_priv = dev->dev_private;
3330 enum port port = intel_dig_port->port;
3331 uint32_t val;
3332
3333 if (!HAS_DDI(dev))
3334 return;
3335
3336 val = I915_READ(DP_TP_CTL(port));
3337 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3338 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3339 I915_WRITE(DP_TP_CTL(port), val);
3340
3341 /*
3342 * On PORT_A we can have only eDP in SST mode. There the only reason
3343 * we need to set idle transmission mode is to work around a HW issue
3344 * where we enable the pipe while not in idle link-training mode.
3345 * In this case there is requirement to wait for a minimum number of
3346 * idle patterns to be sent.
3347 */
3348 if (port == PORT_A)
3349 return;
3350
3351 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3352 1))
3353 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3354}
3355
a4fc5ed6 3356static void
ea5b213a 3357intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3358{
da63a9f2 3359 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1612c8bd 3360 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
bc7d38a4 3361 enum port port = intel_dig_port->port;
da63a9f2 3362 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3363 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 3364 uint32_t DP = intel_dp->DP;
a4fc5ed6 3365
bc76e320 3366 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3367 return;
3368
0c33d8d7 3369 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3370 return;
3371
28c97730 3372 DRM_DEBUG_KMS("\n");
32f9d658 3373
39e5fa88
VS		 3374 if ((IS_GEN7(dev) && port == PORT_A) ||
3375 (HAS_PCH_CPT(dev) && port != PORT_A)) {
e3421a18 3376 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1612c8bd 3377 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
e3421a18 3378 } else {
aad3d14d
VS		 3379 if (IS_CHERRYVIEW(dev))
3380 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3381 else
3382 DP &= ~DP_LINK_TRAIN_MASK;
1612c8bd 3383 DP |= DP_LINK_TRAIN_PAT_IDLE;
e3421a18 3384 }
1612c8bd 3385 I915_WRITE(intel_dp->output_reg, DP);
fe255d00 3386 POSTING_READ(intel_dp->output_reg);
5eb08b69 3387
1612c8bd
VS		 3388 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3389 I915_WRITE(intel_dp->output_reg, DP);
3390 POSTING_READ(intel_dp->output_reg);
3391
3392 /*
3393 * HW workaround for IBX, we need to move the port
3394 * to transcoder A after disabling it to allow the
3395 * matching HDMI port to be enabled on transcoder A.
3396 */
3397 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
0c241d5b
VS		 3398 /*
3399 * We get CPU/PCH FIFO underruns on the other pipe when
3400 * doing the workaround. Sweep them under the rug.
3401 */
3402 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3403 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3404
1612c8bd
VS		 3405 /* always enable with pattern 1 (as per spec) */
3406 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3407 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3408 I915_WRITE(intel_dp->output_reg, DP);
3409 POSTING_READ(intel_dp->output_reg);
3410
3411 DP &= ~DP_PORT_EN;
5bddd17f 3412 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3413 POSTING_READ(intel_dp->output_reg);
0c241d5b
VS		 3414
3415 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
3416 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3417 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5bddd17f
EA		 3418 }
3419
f01eca2e 3420 msleep(intel_dp->panel_power_down_delay);
6fec7662
VS		 3421
3422 intel_dp->DP = DP;
a4fc5ed6
KP		 3423}
3424
26d61aad
KP		 3425static bool
3426intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3427{
a031d709
RV		 3428 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3429 struct drm_device *dev = dig_port->base.base.dev;
3430 struct drm_i915_private *dev_priv = dev->dev_private;
3431
9f085ebb
L		 3432 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3433 sizeof(intel_dp->dpcd)) < 0)
edb39244 3434 return false; /* aux transfer failed */
92fd8fd1 3435
a8e98153 3436 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3437
edb39244
AJ		 3438 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3439 return false; /* DPCD not present */
3440
9f085ebb
L		 3441 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3442 &intel_dp->sink_count, 1) < 0)
30d9aa42
SS		 3443 return false;
3444
3445 /*
3446 * Sink count can change between short pulse hpd hence
3447 * a member variable in intel_dp will track any changes
3448 * between short pulse interrupts.
3449 */
3450 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3451
3452 /*
3453 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3454 * a dongle is present but no display. Unless we require to know
3455 * if a dongle is present or not, we don't need to update
3456 * downstream port information. So, an early return here saves
3457 * time from performing other operations which are not required.
3458 */
1034ce70 3459 if (!is_edp(intel_dp) && !intel_dp->sink_count)
30d9aa42
SS		 3460 return false;
3461
2293bb5c
SK		 3462 /* Check if the panel supports PSR */
3463 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3464 if (is_edp(intel_dp)) {
9f085ebb
L		 3465 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3466 intel_dp->psr_dpcd,
3467 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3468 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3469 dev_priv->psr.sink_support = true;
50003939 3470 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3471 }
474d1ec4
SJ		 3472
3473 if (INTEL_INFO(dev)->gen >= 9 &&
3474 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3475 uint8_t frame_sync_cap;
3476
3477 dev_priv->psr.sink_support = true;
9f085ebb
L		 3478 drm_dp_dpcd_read(&intel_dp->aux,
3479 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3480 &frame_sync_cap, 1);
474d1ec4
SJ		 3481 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3482 /* PSR2 needs frame sync as well */
3483 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3484 DRM_DEBUG_KMS("PSR2 %s on sink",
3485 dev_priv->psr.psr2_support ? "supported" : "not supported");
3486 }
86ee27b5
YA		 3487
3488 /* Read the eDP Display control capabilities registers */
3489 memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
3490 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
9a652cc0 3491 (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
86ee27b5
YA		 3492 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3493 sizeof(intel_dp->edp_dpcd)))
3494 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3495 intel_dp->edp_dpcd);
50003939
JN		 3496 }
3497
bc5133d5 3498 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
e588fa18 3499 yesno(intel_dp_source_supports_hbr2(intel_dp)),
742f491d 3500 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
06ea66b6 3501
fc0f8e25 3502 /* Intermediate frequency support */
86ee27b5 3503 if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */
94ca719e 3504 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3505 int i;
3506
9f085ebb
L		 3507 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3508 sink_rates, sizeof(sink_rates));
ea2d8a42 3509
94ca719e
VS		 3510 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3511 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3512
3513 if (val == 0)
3514 break;
3515
af77b974
SJ		 3516 /* Value read is in kHz while drm clock is saved in deca-kHz */
3517 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3518 }
94ca719e 3519 intel_dp->num_sink_rates = i;
fc0f8e25 3520 }
0336400e
VS		 3521
3522 intel_dp_print_rates(intel_dp);
3523
edb39244
AJ		 3524 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3525 DP_DWN_STRM_PORT_PRESENT))
3526 return true; /* native DP sink */
3527
3528 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3529 return true; /* no per-port downstream info */
3530
9f085ebb
L		 3531 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3532 intel_dp->downstream_ports,
3533 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3534 return false; /* downstream port status fetch failed */
3535
3536 return true;
92fd8fd1
KP		 3537}
3538
0d198328
AJ		 3539static void
3540intel_dp_probe_oui(struct intel_dp *intel_dp)
3541{
3542 u8 buf[3];
3543
3544 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3545 return;
3546
9f085ebb 3547 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3548 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3549 buf[0], buf[1], buf[2]);
3550
9f085ebb 3551 if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3552 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3553 buf[0], buf[1], buf[2]);
3554}
3555
0e32b39c
DA		 3556static bool
3557intel_dp_probe_mst(struct intel_dp *intel_dp)
3558{
3559 u8 buf[1];
3560
7cc96139
NS		 3561 if (!i915.enable_dp_mst)
3562 return false;
3563
0e32b39c
DA		 3564 if (!intel_dp->can_mst)
3565 return false;
3566
3567 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3568 return false;
3569
9f085ebb 3570 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
0e32b39c
DA		 3571 if (buf[0] & DP_MST_CAP) {
3572 DRM_DEBUG_KMS("Sink is MST capable\n");
3573 intel_dp->is_mst = true;
3574 } else {
3575 DRM_DEBUG_KMS("Sink is not MST capable\n");
3576 intel_dp->is_mst = false;
3577 }
3578 }
0e32b39c
DA		 3579
3580 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3581 return intel_dp->is_mst;
3582}
3583
e5a1cab5 3584static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
d2e216d0 3585{
082dcc7c 3586 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3587 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c 3588 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
ad9dc91b 3589 u8 buf;
e5a1cab5 3590 int ret = 0;
c6297843
RV		 3591 int count = 0;
3592 int attempts = 10;
d2e216d0 3593
082dcc7c
RV		 3594 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3595 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3596 ret = -EIO;
3597 goto out;
4373f0f2
PZ		 3598 }
3599
082dcc7c 3600 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
e5a1cab5 3601 buf & ~DP_TEST_SINK_START) < 0) {
082dcc7c 3602 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3603 ret = -EIO;
3604 goto out;
3605 }
d2e216d0 3606
c6297843
RV		 3607 do {
3608 intel_wait_for_vblank(dev, intel_crtc->pipe);
3609
3610 if (drm_dp_dpcd_readb(&intel_dp->aux,
3611 DP_TEST_SINK_MISC, &buf) < 0) {
3612 ret = -EIO;
3613 goto out;
3614 }
3615 count = buf & DP_TEST_COUNT_MASK;
3616 } while (--attempts && count);
3617
3618 if (attempts == 0) {
dc5a9037 3619 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
c6297843
RV		 3620 ret = -ETIMEDOUT;
3621 }
3622
e5a1cab5 3623 out:
082dcc7c 3624 hsw_enable_ips(intel_crtc);
e5a1cab5 3625 return ret;
082dcc7c
RV		 3626}
3627
3628static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3629{
3630 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3631 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c
RV		 3632 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3633 u8 buf;
e5a1cab5
RV		 3634 int ret;
3635
082dcc7c
RV		 3636 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3637 return -EIO;
3638
3639 if (!(buf & DP_TEST_CRC_SUPPORTED))
3640 return -ENOTTY;
3641
3642 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3643 return -EIO;
3644
6d8175da
RV		 3645 if (buf & DP_TEST_SINK_START) {
3646 ret = intel_dp_sink_crc_stop(intel_dp);
3647 if (ret)
3648 return ret;
3649 }
3650
082dcc7c 3651 hsw_disable_ips(intel_crtc);
1dda5f93 3652
9d1a1031 3653 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
082dcc7c
RV		 3654 buf | DP_TEST_SINK_START) < 0) {
3655 hsw_enable_ips(intel_crtc);
3656 return -EIO;
4373f0f2
PZ		 3657 }
3658
d72f9d91 3659 intel_wait_for_vblank(dev, intel_crtc->pipe);
082dcc7c
RV		 3660 return 0;
3661}
3662
3663int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3664{
3665 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3666 struct drm_device *dev = dig_port->base.base.dev;
3667 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3668 u8 buf;
621d4c76 3669 int count, ret;
082dcc7c 3670 int attempts = 6;
082dcc7c
RV		 3671
3672 ret = intel_dp_sink_crc_start(intel_dp);
3673 if (ret)
3674 return ret;
3675
ad9dc91b 3676 do {
621d4c76
RV		 3677 intel_wait_for_vblank(dev, intel_crtc->pipe);
3678
1dda5f93 3679 if (drm_dp_dpcd_readb(&intel_dp->aux,
4373f0f2
PZ		 3680 DP_TEST_SINK_MISC, &buf) < 0) {
3681 ret = -EIO;
afe0d67e 3682 goto stop;
4373f0f2 3683 }
621d4c76 3684 count = buf & DP_TEST_COUNT_MASK;
aabc95dc 3685
7e38eeff 3686 } while (--attempts && count == 0);
ad9dc91b
RV		 3687
3688 if (attempts == 0) {
7e38eeff
RV		 3689 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3690 ret = -ETIMEDOUT;
3691 goto stop;
3692 }
3693
3694 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3695 ret = -EIO;
3696 goto stop;
ad9dc91b 3697 }
d2e216d0 3698
afe0d67e 3699stop:
082dcc7c 3700 intel_dp_sink_crc_stop(intel_dp);
4373f0f2 3701 return ret;
d2e216d0
RV		 3702}
3703
a60f0e38
JB		 3704static bool
3705intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3706{
9f085ebb 3707 return drm_dp_dpcd_read(&intel_dp->aux,
9d1a1031
JN		 3708 DP_DEVICE_SERVICE_IRQ_VECTOR,
3709 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3710}
3711
0e32b39c
DA		 3712static bool
3713intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3714{
3715 int ret;
3716
9f085ebb 3717 ret = drm_dp_dpcd_read(&intel_dp->aux,
0e32b39c
DA		 3718 DP_SINK_COUNT_ESI,
3719 sink_irq_vector, 14);
3720 if (ret != 14)
3721 return false;
3722
3723 return true;
3724}
3725
c5d5ab7a
TP		 3726static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3727{
3728 uint8_t test_result = DP_TEST_ACK;
3729 return test_result;
3730}
3731
3732static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3733{
3734 uint8_t test_result = DP_TEST_NAK;
3735 return test_result;
3736}
3737
3738static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 3739{
c5d5ab7a 3740 uint8_t test_result = DP_TEST_NAK;
559be30c
TP		 3741 struct intel_connector *intel_connector = intel_dp->attached_connector;
3742 struct drm_connector *connector = &intel_connector->base;
3743
3744 if (intel_connector->detect_edid == NULL ||
ac6f2e29 3745 connector->edid_corrupt ||
559be30c
TP		 3746 intel_dp->aux.i2c_defer_count > 6) {
3747 /* Check EDID read for NACKs, DEFERs and corruption
3748 * (DP CTS 1.2 Core r1.1)
3749 * 4.2.2.4 : Failed EDID read, I2C_NAK
3750 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3751 * 4.2.2.6 : EDID corruption detected
3752 * Use failsafe mode for all cases
3753 */
3754 if (intel_dp->aux.i2c_nack_count > 0 ||
3755 intel_dp->aux.i2c_defer_count > 0)
3756 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3757 intel_dp->aux.i2c_nack_count,
3758 intel_dp->aux.i2c_defer_count);
3759 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3760 } else {
f79b468e
TS		 3761 struct edid *block = intel_connector->detect_edid;
3762
3763 /* We have to write the checksum
3764 * of the last block read
3765 */
3766 block += intel_connector->detect_edid->extensions;
3767
559be30c
TP		 3768 if (!drm_dp_dpcd_write(&intel_dp->aux,
3769 DP_TEST_EDID_CHECKSUM,
f79b468e 3770 &block->checksum,
5a1cc655 3771 1))
559be30c
TP		 3772 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3773
3774 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3775 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3776 }
3777
3778 /* Set test active flag here so userspace doesn't interrupt things */
3779 intel_dp->compliance_test_active = 1;
3780
c5d5ab7a
TP		 3781 return test_result;
3782}
3783
3784static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 3785{
c5d5ab7a
TP		 3786 uint8_t test_result = DP_TEST_NAK;
3787 return test_result;
3788}
3789
3790static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3791{
3792 uint8_t response = DP_TEST_NAK;
3793 uint8_t rxdata = 0;
3794 int status = 0;
3795
c5d5ab7a
TP		 3796 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3797 if (status <= 0) {
3798 DRM_DEBUG_KMS("Could not read test request from sink\n");
3799 goto update_status;
3800 }
3801
3802 switch (rxdata) {
3803 case DP_TEST_LINK_TRAINING:
3804 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3805 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3806 response = intel_dp_autotest_link_training(intel_dp);
3807 break;
3808 case DP_TEST_LINK_VIDEO_PATTERN:
3809 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3810 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3811 response = intel_dp_autotest_video_pattern(intel_dp);
3812 break;
3813 case DP_TEST_LINK_EDID_READ:
3814 DRM_DEBUG_KMS("EDID test requested\n");
3815 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3816 response = intel_dp_autotest_edid(intel_dp);
3817 break;
3818 case DP_TEST_LINK_PHY_TEST_PATTERN:
3819 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3820 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3821 response = intel_dp_autotest_phy_pattern(intel_dp);
3822 break;
3823 default:
3824 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3825 break;
3826 }
3827
3828update_status:
3829 status = drm_dp_dpcd_write(&intel_dp->aux,
3830 DP_TEST_RESPONSE,
3831 &response, 1);
3832 if (status <= 0)
3833 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 3834}
3835
0e32b39c
DA		 3836static int
3837intel_dp_check_mst_status(struct intel_dp *intel_dp)
3838{
3839 bool bret;
3840
3841 if (intel_dp->is_mst) {
3842 u8 esi[16] = { 0 };
3843 int ret = 0;
3844 int retry;
3845 bool handled;
3846 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3847go_again:
3848 if (bret == true) {
3849
3850 /* check link status - esi[10] = 0x200c */
90a6b7b0 3851 if (intel_dp->active_mst_links &&
901c2daf 3852 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
0e32b39c
DA		 3853 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3854 intel_dp_start_link_train(intel_dp);
0e32b39c
DA		 3855 intel_dp_stop_link_train(intel_dp);
3856 }
3857
6f34cc39 3858 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 3859 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3860
3861 if (handled) {
3862 for (retry = 0; retry < 3; retry++) {
3863 int wret;
3864 wret = drm_dp_dpcd_write(&intel_dp->aux,
3865 DP_SINK_COUNT_ESI+1,
3866 &esi[1], 3);
3867 if (wret == 3) {
3868 break;
3869 }
3870 }
3871
3872 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3873 if (bret == true) {
6f34cc39 3874 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 3875 goto go_again;
3876 }
3877 } else
3878 ret = 0;
3879
3880 return ret;
3881 } else {
3882 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3883 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3884 intel_dp->is_mst = false;
3885 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3886 /* send a hotplug event */
3887 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3888 }
3889 }
3890 return -EINVAL;
3891}
3892
5c9114d0
SS		 3893static void
3894intel_dp_check_link_status(struct intel_dp *intel_dp)
3895{
3896 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3897 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3898 u8 link_status[DP_LINK_STATUS_SIZE];
3899
3900 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3901
3902 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3903 DRM_ERROR("Failed to get link status\n");
3904 return;
3905 }
3906
3907 if (!intel_encoder->base.crtc)
3908 return;
3909
3910 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3911 return;
3912
3913 /* if link training is requested we should perform it always */
3914 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
3915 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
3916 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3917 intel_encoder->base.name);
3918 intel_dp_start_link_train(intel_dp);
3919 intel_dp_stop_link_train(intel_dp);
3920 }
3921}
3922
a4fc5ed6
KP		 3923/*
3924 * According to DP spec
3925 * 5.1.2:
3926 * 1. Read DPCD
3927 * 2. Configure link according to Receiver Capabilities
3928 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3929 * 4. Check link status on receipt of hot-plug interrupt
39ff747b
SS		 3930 *
3931 * intel_dp_short_pulse - handles short pulse interrupts
3932 * when full detection is not required.
3933 * Returns %true if short pulse is handled and full detection
3934 * is NOT required and %false otherwise.
a4fc5ed6 3935 */
39ff747b 3936static bool
5c9114d0 3937intel_dp_short_pulse(struct intel_dp *intel_dp)
a4fc5ed6 3938{
5b215bcf 3939 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a60f0e38 3940 u8 sink_irq_vector;
39ff747b
SS		 3941 u8 old_sink_count = intel_dp->sink_count;
3942 bool ret;
5b215bcf 3943
4df6960e
SS		 3944 /*
3945 * Clearing compliance test variables to allow capturing
3946 * of values for next automated test request.
3947 */
3948 intel_dp->compliance_test_active = 0;
3949 intel_dp->compliance_test_type = 0;
3950 intel_dp->compliance_test_data = 0;
3951
39ff747b
SS		 3952 /*
3953 * Now read the DPCD to see if it's actually running
3954 * If the current value of sink count doesn't match with
3955 * the value that was stored earlier or dpcd read failed
3956 * we need to do full detection
3957 */
3958 ret = intel_dp_get_dpcd(intel_dp);
3959
3960 if ((old_sink_count != intel_dp->sink_count) || !ret) {
3961 /* No need to proceed if we are going to do full detect */
3962 return false;
59cd09e1
JB		 3963 }
3964
a60f0e38
JB		 3965 /* Try to read the source of the interrupt */
3966 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3967 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3968 /* Clear interrupt source */
9d1a1031
JN		 3969 drm_dp_dpcd_writeb(&intel_dp->aux,
3970 DP_DEVICE_SERVICE_IRQ_VECTOR,
3971 sink_irq_vector);
a60f0e38
JB		 3972
3973 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
09b1eb13 3974 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
a60f0e38
JB		 3975 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3976 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3977 }
3978
5c9114d0
SS		 3979 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
3980 intel_dp_check_link_status(intel_dp);
3981 drm_modeset_unlock(&dev->mode_config.connection_mutex);
39ff747b
SS		 3982
3983 return true;
a4fc5ed6 3984}
a4fc5ed6 3985
caf9ab24 3986/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3987static enum drm_connector_status
26d61aad 3988intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3989{
caf9ab24 3990 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3991 uint8_t type;
3992
3993 if (!intel_dp_get_dpcd(intel_dp))
3994 return connector_status_disconnected;
3995
1034ce70
SS		 3996 if (is_edp(intel_dp))
3997 return connector_status_connected;
3998
caf9ab24
AJ		 3999 /* if there's no downstream port, we're done */
4000 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4001 return connector_status_connected;
caf9ab24
AJ		 4002
4003 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4004 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4005 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
9d1a1031 4006
30d9aa42
SS		 4007 return intel_dp->sink_count ?
4008 connector_status_connected : connector_status_disconnected;
caf9ab24
AJ		 4009 }
4010
4011 /* If no HPD, poke DDC gently */
0b99836f 4012 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4013 return connector_status_connected;
caf9ab24
AJ		 4014
4015 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4016 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4017 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4018 if (type == DP_DS_PORT_TYPE_VGA ||
4019 type == DP_DS_PORT_TYPE_NON_EDID)
4020 return connector_status_unknown;
4021 } else {
4022 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4023 DP_DWN_STRM_PORT_TYPE_MASK;
4024 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4025 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4026 return connector_status_unknown;
4027 }
caf9ab24
AJ		 4028
4029 /* Anything else is out of spec, warn and ignore */
4030 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4031 return connector_status_disconnected;
71ba9000
AJ		 4032}
4033
d410b56d
CW		 4034static enum drm_connector_status
4035edp_detect(struct intel_dp *intel_dp)
4036{
4037 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4038 enum drm_connector_status status;
4039
4040 status = intel_panel_detect(dev);
4041 if (status == connector_status_unknown)
4042 status = connector_status_connected;
4043
4044 return status;
4045}
4046
b93433cc
JN		 4047static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4048 struct intel_digital_port *port)
5eb08b69 4049{
b93433cc 4050 u32 bit;
01cb9ea6 4051
0df53b77
JN		 4052 switch (port->port) {
4053 case PORT_A:
4054 return true;
4055 case PORT_B:
4056 bit = SDE_PORTB_HOTPLUG;
4057 break;
4058 case PORT_C:
4059 bit = SDE_PORTC_HOTPLUG;
4060 break;
4061 case PORT_D:
4062 bit = SDE_PORTD_HOTPLUG;
4063 break;
4064 default:
4065 MISSING_CASE(port->port);
4066 return false;
4067 }
4068
4069 return I915_READ(SDEISR) & bit;
4070}
4071
4072static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4073 struct intel_digital_port *port)
4074{
4075 u32 bit;
4076
4077 switch (port->port) {
4078 case PORT_A:
4079 return true;
4080 case PORT_B:
4081 bit = SDE_PORTB_HOTPLUG_CPT;
4082 break;
4083 case PORT_C:
4084 bit = SDE_PORTC_HOTPLUG_CPT;
4085 break;
4086 case PORT_D:
4087 bit = SDE_PORTD_HOTPLUG_CPT;
4088 break;
a78695d3
JN		 4089 case PORT_E:
4090 bit = SDE_PORTE_HOTPLUG_SPT;
4091 break;
0df53b77
JN		 4092 default:
4093 MISSING_CASE(port->port);
4094 return false;
b93433cc 4095 }
1b469639 4096
b93433cc 4097 return I915_READ(SDEISR) & bit;
5eb08b69
ZW		 4098}
4099
7e66bcf2 4100static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
1d245987 4101 struct intel_digital_port *port)
a4fc5ed6 4102{
9642c81c 4103 u32 bit;
5eb08b69 4104
9642c81c
JN		 4105 switch (port->port) {
4106 case PORT_B:
4107 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4108 break;
4109 case PORT_C:
4110 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4111 break;
4112 case PORT_D:
4113 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4114 break;
4115 default:
4116 MISSING_CASE(port->port);
4117 return false;
4118 }
4119
4120 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4121}
4122
0780cd36
VS		 4123static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4124 struct intel_digital_port *port)
9642c81c
JN		 4125{
4126 u32 bit;
4127
4128 switch (port->port) {
4129 case PORT_B:
0780cd36 4130 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4131 break;
4132 case PORT_C:
0780cd36 4133 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4134 break;
4135 case PORT_D:
0780cd36 4136 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4137 break;
4138 default:
4139 MISSING_CASE(port->port);
4140 return false;
a4fc5ed6
KP		 4141 }
4142
1d245987 4143 return I915_READ(PORT_HOTPLUG_STAT) & bit;
2a592bec
DA		 4144}
4145
e464bfde 4146static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
e2ec35a5 4147 struct intel_digital_port *intel_dig_port)
e464bfde 4148{
e2ec35a5
SJ		 4149 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4150 enum port port;
e464bfde
JN		 4151 u32 bit;
4152
e2ec35a5
SJ		 4153 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4154 switch (port) {
e464bfde
JN		 4155 case PORT_A:
4156 bit = BXT_DE_PORT_HP_DDIA;
4157 break;
4158 case PORT_B:
4159 bit = BXT_DE_PORT_HP_DDIB;
4160 break;
4161 case PORT_C:
4162 bit = BXT_DE_PORT_HP_DDIC;
4163 break;
4164 default:
e2ec35a5 4165 MISSING_CASE(port);
e464bfde
JN		 4166 return false;
4167 }
4168
4169 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4170}
4171
7e66bcf2
JN		 4172/*
4173 * intel_digital_port_connected - is the specified port connected?
4174 * @dev_priv: i915 private structure
4175 * @port: the port to test
4176 *
4177 * Return %true if @port is connected, %false otherwise.
4178 */
237ed86c 4179bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
7e66bcf2
JN		 4180 struct intel_digital_port *port)
4181{
0df53b77 4182 if (HAS_PCH_IBX(dev_priv))
7e66bcf2 4183 return ibx_digital_port_connected(dev_priv, port);
22824fac 4184 else if (HAS_PCH_SPLIT(dev_priv))
0df53b77 4185 return cpt_digital_port_connected(dev_priv, port);
e464bfde
JN		 4186 else if (IS_BROXTON(dev_priv))
4187 return bxt_digital_port_connected(dev_priv, port);
0780cd36
VS		 4188 else if (IS_GM45(dev_priv))
4189 return gm45_digital_port_connected(dev_priv, port);
7e66bcf2
JN		 4190 else
4191 return g4x_digital_port_connected(dev_priv, port);
4192}
4193
8c241fef 4194static struct edid *
beb60608 4195intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4196{
beb60608 4197 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4198
9cd300e0
JN		 4199 /* use cached edid if we have one */
4200 if (intel_connector->edid) {
9cd300e0
JN		 4201 /* invalid edid */
4202 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4203 return NULL;
4204
55e9edeb 4205 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4206 } else
4207 return drm_get_edid(&intel_connector->base,
4208 &intel_dp->aux.ddc);
4209}
8c241fef 4210
beb60608
CW		 4211static void
4212intel_dp_set_edid(struct intel_dp *intel_dp)
4213{
4214 struct intel_connector *intel_connector = intel_dp->attached_connector;
4215 struct edid *edid;
8c241fef 4216
f21a2198 4217 intel_dp_unset_edid(intel_dp);
beb60608
CW		 4218 edid = intel_dp_get_edid(intel_dp);
4219 intel_connector->detect_edid = edid;
4220
4221 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4222 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4223 else
4224 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4225}
4226
beb60608
CW		 4227static void
4228intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4229{
beb60608 4230 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4231
beb60608
CW		 4232 kfree(intel_connector->detect_edid);
4233 intel_connector->detect_edid = NULL;
9cd300e0 4234
beb60608
CW		 4235 intel_dp->has_audio = false;
4236}
d6f24d0f 4237
f21a2198
SS		 4238static void
4239intel_dp_long_pulse(struct intel_connector *intel_connector)
a9756bb5 4240{
f21a2198 4241 struct drm_connector *connector = &intel_connector->base;
a9756bb5 4242 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4243 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4244 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4245 struct drm_device *dev = connector->dev;
a9756bb5 4246 enum drm_connector_status status;
671dedd2 4247 enum intel_display_power_domain power_domain;
0e32b39c 4248 bool ret;
09b1eb13 4249 u8 sink_irq_vector;
a9756bb5 4250
25f78f58
VS		 4251 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4252 intel_display_power_get(to_i915(dev), power_domain);
a9756bb5 4253
d410b56d
CW		 4254 /* Can't disconnect eDP, but you can close the lid... */
4255 if (is_edp(intel_dp))
4256 status = edp_detect(intel_dp);
c555a81d
ACO		 4257 else if (intel_digital_port_connected(to_i915(dev),
4258 dp_to_dig_port(intel_dp)))
4259 status = intel_dp_detect_dpcd(intel_dp);
a9756bb5 4260 else
c555a81d
ACO		 4261 status = connector_status_disconnected;
4262
4df6960e
SS		 4263 if (status != connector_status_connected) {
4264 intel_dp->compliance_test_active = 0;
4265 intel_dp->compliance_test_type = 0;
4266 intel_dp->compliance_test_data = 0;
4267
0e505a08 4268 if (intel_dp->is_mst) {
4269 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4270 intel_dp->is_mst,
4271 intel_dp->mst_mgr.mst_state);
4272 intel_dp->is_mst = false;
4273 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4274 intel_dp->is_mst);
4275 }
4276
c8c8fb33 4277 goto out;
4df6960e 4278 }
a9756bb5 4279
f21a2198
SS		 4280 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4281 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4282
0d198328
AJ		 4283 intel_dp_probe_oui(intel_dp);
4284
0e32b39c
DA		 4285 ret = intel_dp_probe_mst(intel_dp);
4286 if (ret) {
f21a2198
SS		 4287 /*
4288 * If we are in MST mode then this connector
4289 * won't appear connected or have anything
4290 * with EDID on it
4291 */
0e32b39c
DA		 4292 status = connector_status_disconnected;
4293 goto out;
7d23e3c3
SS		 4294 } else if (connector->status == connector_status_connected) {
4295 /*
4296 * If display was connected already and is still connected
4297 * check links status, there has been known issues of
4298 * link loss triggerring long pulse!!!!
4299 */
4300 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4301 intel_dp_check_link_status(intel_dp);
4302 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4303 goto out;
0e32b39c
DA		 4304 }
4305
4df6960e
SS		 4306 /*
4307 * Clearing NACK and defer counts to get their exact values
4308 * while reading EDID which are required by Compliance tests
4309 * 4.2.2.4 and 4.2.2.5
4310 */
4311 intel_dp->aux.i2c_nack_count = 0;
4312 intel_dp->aux.i2c_defer_count = 0;
4313
beb60608 4314 intel_dp_set_edid(intel_dp);
a9756bb5 4315
c8c8fb33 4316 status = connector_status_connected;
7d23e3c3 4317 intel_dp->detect_done = true;
c8c8fb33 4318
09b1eb13
TP		 4319 /* Try to read the source of the interrupt */
4320 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4321 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4322 /* Clear interrupt source */
4323 drm_dp_dpcd_writeb(&intel_dp->aux,
4324 DP_DEVICE_SERVICE_IRQ_VECTOR,
4325 sink_irq_vector);
4326
4327 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4328 intel_dp_handle_test_request(intel_dp);
4329 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4330 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4331 }
4332
c8c8fb33 4333out:
0e505a08 4334 if ((status != connector_status_connected) &&
4335 (intel_dp->is_mst == false))
f21a2198 4336 intel_dp_unset_edid(intel_dp);
7d23e3c3 4337
25f78f58 4338 intel_display_power_put(to_i915(dev), power_domain);
f21a2198
SS		 4339 return;
4340}
4341
4342static enum drm_connector_status
4343intel_dp_detect(struct drm_connector *connector, bool force)
4344{
4345 struct intel_dp *intel_dp = intel_attached_dp(connector);
4346 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4347 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4348 struct intel_connector *intel_connector = to_intel_connector(connector);
4349
4350 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4351 connector->base.id, connector->name);
4352
4353 if (intel_dp->is_mst) {
4354 /* MST devices are disconnected from a monitor POV */
4355 intel_dp_unset_edid(intel_dp);
4356 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4357 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4358 return connector_status_disconnected;
4359 }
4360
7d23e3c3
SS		 4361 /* If full detect is not performed yet, do a full detect */
4362 if (!intel_dp->detect_done)
4363 intel_dp_long_pulse(intel_dp->attached_connector);
4364
4365 intel_dp->detect_done = false;
f21a2198
SS		 4366
4367 if (intel_connector->detect_edid)
4368 return connector_status_connected;
4369 else
4370 return connector_status_disconnected;
a4fc5ed6
KP		 4371}
4372
beb60608
CW		 4373static void
4374intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4375{
df0e9248 4376 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4377 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
25f78f58 4378 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
671dedd2 4379 enum intel_display_power_domain power_domain;
a4fc5ed6 4380
beb60608
CW		 4381 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4382 connector->base.id, connector->name);
4383 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4384
beb60608
CW		 4385 if (connector->status != connector_status_connected)
4386 return;
671dedd2 4387
25f78f58
VS		 4388 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4389 intel_display_power_get(dev_priv, power_domain);
beb60608
CW		 4390
4391 intel_dp_set_edid(intel_dp);
4392
25f78f58 4393 intel_display_power_put(dev_priv, power_domain);
beb60608
CW		 4394
4395 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4396 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4397}
4398
4399static int intel_dp_get_modes(struct drm_connector *connector)
4400{
4401 struct intel_connector *intel_connector = to_intel_connector(connector);
4402 struct edid *edid;
4403
4404 edid = intel_connector->detect_edid;
4405 if (edid) {
4406 int ret = intel_connector_update_modes(connector, edid);
4407 if (ret)
4408 return ret;
4409 }
32f9d658 4410
f8779fda 4411 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4412 if (is_edp(intel_attached_dp(connector)) &&
4413 intel_connector->panel.fixed_mode) {
f8779fda 4414 struct drm_display_mode *mode;
beb60608
CW		 4415
4416 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4417 intel_connector->panel.fixed_mode);
f8779fda 4418 if (mode) {
32f9d658
ZW		 4419 drm_mode_probed_add(connector, mode);
4420 return 1;
4421 }
4422 }
beb60608 4423
32f9d658 4424 return 0;
a4fc5ed6
KP		 4425}
4426
1aad7ac0
CW		 4427static bool
4428intel_dp_detect_audio(struct drm_connector *connector)
4429{
1aad7ac0 4430 bool has_audio = false;
beb60608 4431 struct edid *edid;
1aad7ac0 4432
beb60608
CW		 4433 edid = to_intel_connector(connector)->detect_edid;
4434 if (edid)
1aad7ac0 4435 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4436
1aad7ac0
CW		 4437 return has_audio;
4438}
4439
f684960e
CW		 4440static int
4441intel_dp_set_property(struct drm_connector *connector,
4442 struct drm_property *property,
4443 uint64_t val)
4444{
e953fd7b 4445 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4446 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4447 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4448 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4449 int ret;
4450
662595df 4451 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4452 if (ret)
4453 return ret;
4454
3f43c48d 4455 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4456 int i = val;
4457 bool has_audio;
4458
4459 if (i == intel_dp->force_audio)
f684960e
CW		 4460 return 0;
4461
1aad7ac0 4462 intel_dp->force_audio = i;
f684960e 4463
c3e5f67b 4464 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4465 has_audio = intel_dp_detect_audio(connector);
4466 else
c3e5f67b 4467 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4468
4469 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4470 return 0;
4471
1aad7ac0 4472 intel_dp->has_audio = has_audio;
f684960e
CW		 4473 goto done;
4474 }
4475
e953fd7b 4476 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80 4477 bool old_auto = intel_dp->color_range_auto;
0f2a2a75 4478 bool old_range = intel_dp->limited_color_range;
ae4edb80 4479
55bc60db
VS		 4480 switch (val) {
4481 case INTEL_BROADCAST_RGB_AUTO:
4482 intel_dp->color_range_auto = true;
4483 break;
4484 case INTEL_BROADCAST_RGB_FULL:
4485 intel_dp->color_range_auto = false;
0f2a2a75 4486 intel_dp->limited_color_range = false;
55bc60db
VS		 4487 break;
4488 case INTEL_BROADCAST_RGB_LIMITED:
4489 intel_dp->color_range_auto = false;
0f2a2a75 4490 intel_dp->limited_color_range = true;
55bc60db
VS		 4491 break;
4492 default:
4493 return -EINVAL;
4494 }
ae4edb80
DV		 4495
4496 if (old_auto == intel_dp->color_range_auto &&
0f2a2a75 4497 old_range == intel_dp->limited_color_range)
ae4edb80
DV		 4498 return 0;
4499
e953fd7b
CW		 4500 goto done;
4501 }
4502
53b41837
YN		 4503 if (is_edp(intel_dp) &&
4504 property == connector->dev->mode_config.scaling_mode_property) {
4505 if (val == DRM_MODE_SCALE_NONE) {
4506 DRM_DEBUG_KMS("no scaling not supported\n");
4507 return -EINVAL;
4508 }
234126c6
VS		 4509 if (HAS_GMCH_DISPLAY(dev_priv) &&
4510 val == DRM_MODE_SCALE_CENTER) {
4511 DRM_DEBUG_KMS("centering not supported\n");
4512 return -EINVAL;
4513 }
53b41837
YN		 4514
4515 if (intel_connector->panel.fitting_mode == val) {
4516 /* the eDP scaling property is not changed */
4517 return 0;
4518 }
4519 intel_connector->panel.fitting_mode = val;
4520
4521 goto done;
4522 }
4523
f684960e
CW		 4524 return -EINVAL;
4525
4526done:
c0c36b94
CW		 4527 if (intel_encoder->base.crtc)
4528 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4529
4530 return 0;
4531}
4532
a4fc5ed6 4533static void
73845adf 4534intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4535{
1d508706 4536 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4537
10e972d3 4538 kfree(intel_connector->detect_edid);
beb60608 4539
9cd300e0
JN		 4540 if (!IS_ERR_OR_NULL(intel_connector->edid))
4541 kfree(intel_connector->edid);
4542
acd8db10
PZ		 4543 /* Can't call is_edp() since the encoder may have been destroyed
4544 * already. */
4545 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4546 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4547
a4fc5ed6 4548 drm_connector_cleanup(connector);
55f78c43 4549 kfree(connector);
a4fc5ed6
KP		 4550}
4551
00c09d70 4552void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4553{
da63a9f2
PZ		 4554 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4555 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4556
0e32b39c 4557 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4558 if (is_edp(intel_dp)) {
4559 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4560 /*
4561 * vdd might still be enabled do to the delayed vdd off.
4562 * Make sure vdd is actually turned off here.
4563 */
773538e8 4564 pps_lock(intel_dp);
4be73780 4565 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4566 pps_unlock(intel_dp);
4567
01527b31
CT		 4568 if (intel_dp->edp_notifier.notifier_call) {
4569 unregister_reboot_notifier(&intel_dp->edp_notifier);
4570 intel_dp->edp_notifier.notifier_call = NULL;
4571 }
bd943159 4572 }
c8bd0e49 4573 drm_encoder_cleanup(encoder);
da63a9f2 4574 kfree(intel_dig_port);
24d05927
DV		 4575}
4576
bf93ba67 4577void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
07f9cd0b
ID		 4578{
4579 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4580
4581 if (!is_edp(intel_dp))
4582 return;
4583
951468f3
VS		 4584 /*
4585 * vdd might still be enabled do to the delayed vdd off.
4586 * Make sure vdd is actually turned off here.
4587 */
afa4e53a 4588 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4589 pps_lock(intel_dp);
07f9cd0b 4590 edp_panel_vdd_off_sync(intel_dp);
773538e8 4591 pps_unlock(intel_dp);
07f9cd0b
ID		 4592}
4593
49e6bc51
VS		 4594static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4595{
4596 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4597 struct drm_device *dev = intel_dig_port->base.base.dev;
4598 struct drm_i915_private *dev_priv = dev->dev_private;
4599 enum intel_display_power_domain power_domain;
4600
4601 lockdep_assert_held(&dev_priv->pps_mutex);
4602
4603 if (!edp_have_panel_vdd(intel_dp))
4604 return;
4605
4606 /*
4607 * The VDD bit needs a power domain reference, so if the bit is
4608 * already enabled when we boot or resume, grab this reference and
4609 * schedule a vdd off, so we don't hold on to the reference
4610 * indefinitely.
4611 */
4612 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
25f78f58 4613 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
49e6bc51
VS		 4614 intel_display_power_get(dev_priv, power_domain);
4615
4616 edp_panel_vdd_schedule_off(intel_dp);
4617}
4618
bf93ba67 4619void intel_dp_encoder_reset(struct drm_encoder *encoder)
6d93c0c4 4620{
64989ca4
VS		 4621 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4622 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4623
4624 if (!HAS_DDI(dev_priv))
4625 intel_dp->DP = I915_READ(intel_dp->output_reg);
49e6bc51
VS		 4626
4627 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4628 return;
4629
49e6bc51
VS		 4630 pps_lock(intel_dp);
4631
4632 /*
4633 * Read out the current power sequencer assignment,
4634 * in case the BIOS did something with it.
4635 */
666a4537 4636 if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
49e6bc51
VS		 4637 vlv_initial_power_sequencer_setup(intel_dp);
4638
4639 intel_edp_panel_vdd_sanitize(intel_dp);
4640
4641 pps_unlock(intel_dp);
6d93c0c4
ID		 4642}
4643
a4fc5ed6 4644static const struct drm_connector_funcs intel_dp_connector_funcs = {
4d688a2a 4645 .dpms = drm_atomic_helper_connector_dpms,
a4fc5ed6 4646 .detect = intel_dp_detect,
beb60608 4647 .force = intel_dp_force,
a4fc5ed6 4648 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4649 .set_property = intel_dp_set_property,
2545e4a6 4650 .atomic_get_property = intel_connector_atomic_get_property,
73845adf 4651 .destroy = intel_dp_connector_destroy,
c6f95f27 4652 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4653 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4654};
4655
4656static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4657 .get_modes = intel_dp_get_modes,
4658 .mode_valid = intel_dp_mode_valid,
a4fc5ed6
KP		 4659};
4660
a4fc5ed6 4661static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4662 .reset = intel_dp_encoder_reset,
24d05927 4663 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4664};
4665
b2c5c181 4666enum irqreturn
13cf5504
DA		 4667intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4668{
4669 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4670 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4671 struct drm_device *dev = intel_dig_port->base.base.dev;
4672 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4673 enum intel_display_power_domain power_domain;
b2c5c181 4674 enum irqreturn ret = IRQ_NONE;
1c767b33 4675
2540058f
TI		 4676 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4677 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
0e32b39c 4678 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4679
7a7f84cc
VS		 4680 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4681 /*
4682 * vdd off can generate a long pulse on eDP which
4683 * would require vdd on to handle it, and thus we
4684 * would end up in an endless cycle of
4685 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4686 */
4687 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4688 port_name(intel_dig_port->port));
a8b3d52f 4689 return IRQ_HANDLED;
7a7f84cc
VS		 4690 }
4691
26fbb774
VS		 4692 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4693 port_name(intel_dig_port->port),
0e32b39c 4694 long_hpd ? "long" : "short");
13cf5504 4695
25f78f58 4696 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1c767b33
ID		 4697 intel_display_power_get(dev_priv, power_domain);
4698
0e32b39c 4699 if (long_hpd) {
7d23e3c3
SS		 4700 intel_dp_long_pulse(intel_dp->attached_connector);
4701 if (intel_dp->is_mst)
4702 ret = IRQ_HANDLED;
4703 goto put_power;
0e32b39c 4704
0e32b39c
DA		 4705 } else {
4706 if (intel_dp->is_mst) {
7d23e3c3
SS		 4707 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4708 /*
4709 * If we were in MST mode, and device is not
4710 * there, get out of MST mode
4711 */
4712 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4713 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4714 intel_dp->is_mst = false;
4715 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4716 intel_dp->is_mst);
4717 goto put_power;
4718 }
0e32b39c
DA		 4719 }
4720
39ff747b
SS		 4721 if (!intel_dp->is_mst) {
4722 if (!intel_dp_short_pulse(intel_dp)) {
4723 intel_dp_long_pulse(intel_dp->attached_connector);
4724 goto put_power;
4725 }
4726 }
0e32b39c 4727 }
b2c5c181
DV		 4728
4729 ret = IRQ_HANDLED;
4730
1c767b33
ID		 4731put_power:
4732 intel_display_power_put(dev_priv, power_domain);
4733
4734 return ret;
13cf5504
DA		 4735}
4736
477ec328 4737/* check the VBT to see whether the eDP is on another port */
5d8a7752 4738bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4739{
4740 struct drm_i915_private *dev_priv = dev->dev_private;
36e83a18 4741
53ce81a7
VS		 4742 /*
4743 * eDP not supported on g4x. so bail out early just
4744 * for a bit extra safety in case the VBT is bonkers.
4745 */
4746 if (INTEL_INFO(dev)->gen < 5)
4747 return false;
4748
3b32a35b
VS		 4749 if (port == PORT_A)
4750 return true;
4751
951d9efe 4752 return intel_bios_is_port_edp(dev_priv, port);
36e83a18
ZY		 4753}
4754
0e32b39c 4755void
f684960e
CW		 4756intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4757{
53b41837
YN		 4758 struct intel_connector *intel_connector = to_intel_connector(connector);
4759
3f43c48d 4760 intel_attach_force_audio_property(connector);
e953fd7b 4761 intel_attach_broadcast_rgb_property(connector);
55bc60db 4762 intel_dp->color_range_auto = true;
53b41837
YN		 4763
4764 if (is_edp(intel_dp)) {
4765 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4766 drm_object_attach_property(
4767 &connector->base,
53b41837 4768 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4769 DRM_MODE_SCALE_ASPECT);
4770 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4771 }
f684960e
CW		 4772}
4773
dada1a9f
ID		 4774static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4775{
d28d4731 4776 intel_dp->panel_power_off_time = ktime_get_boottime();
dada1a9f
ID		 4777 intel_dp->last_power_on = jiffies;
4778 intel_dp->last_backlight_off = jiffies;
4779}
4780
67a54566 4781static void
54648618
ID		 4782intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
4783 struct intel_dp *intel_dp, struct edp_power_seq *seq)
67a54566 4784{
b0a08bec 4785 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
8e8232d5 4786 struct pps_registers regs;
453c5420 4787
8e8232d5 4788 intel_pps_get_registers(dev_priv, intel_dp, &regs);
67a54566
DV		 4789
4790 /* Workaround: Need to write PP_CONTROL with the unlock key as
4791 * the very first thing. */
b0a08bec 4792 pp_ctl = ironlake_get_pp_control(intel_dp);
67a54566 4793
8e8232d5
ID		 4794 pp_on = I915_READ(regs.pp_on);
4795 pp_off = I915_READ(regs.pp_off);
54648618 4796 if (!IS_BROXTON(dev_priv)) {
8e8232d5
ID		 4797 I915_WRITE(regs.pp_ctrl, pp_ctl);
4798 pp_div = I915_READ(regs.pp_div);
b0a08bec 4799 }
67a54566
DV		 4800
4801 /* Pull timing values out of registers */
54648618
ID		 4802 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4803 PANEL_POWER_UP_DELAY_SHIFT;
67a54566 4804
54648618
ID		 4805 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4806 PANEL_LIGHT_ON_DELAY_SHIFT;
67a54566 4807
54648618
ID		 4808 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4809 PANEL_LIGHT_OFF_DELAY_SHIFT;
67a54566 4810
54648618
ID		 4811 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4812 PANEL_POWER_DOWN_DELAY_SHIFT;
67a54566 4813
54648618 4814 if (IS_BROXTON(dev_priv)) {
b0a08bec
VK		 4815 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4816 BXT_POWER_CYCLE_DELAY_SHIFT;
4817 if (tmp > 0)
54648618 4818 seq->t11_t12 = (tmp - 1) * 1000;
b0a08bec 4819 else
54648618 4820 seq->t11_t12 = 0;
b0a08bec 4821 } else {
54648618 4822 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
67a54566 4823 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 4824 }
54648618
ID		 4825}
4826
de9c1b6b
ID		 4827static void
4828intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
4829{
4830 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4831 state_name,
4832 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
4833}
4834
4835static void
4836intel_pps_verify_state(struct drm_i915_private *dev_priv,
4837 struct intel_dp *intel_dp)
4838{
4839 struct edp_power_seq hw;
4840 struct edp_power_seq *sw = &intel_dp->pps_delays;
4841
4842 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
4843
4844 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
4845 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
4846 DRM_ERROR("PPS state mismatch\n");
4847 intel_pps_dump_state("sw", sw);
4848 intel_pps_dump_state("hw", &hw);
4849 }
4850}
4851
54648618
ID		 4852static void
4853intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4854 struct intel_dp *intel_dp)
4855{
4856 struct drm_i915_private *dev_priv = dev->dev_private;
4857 struct edp_power_seq cur, vbt, spec,
4858 *final = &intel_dp->pps_delays;
4859
4860 lockdep_assert_held(&dev_priv->pps_mutex);
4861
4862 /* already initialized? */
4863 if (final->t11_t12 != 0)
4864 return;
4865
4866 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
67a54566 4867
de9c1b6b 4868 intel_pps_dump_state("cur", &cur);
67a54566 4869
6aa23e65 4870 vbt = dev_priv->vbt.edp.pps;
67a54566
DV		 4871
4872 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4873 * our hw here, which are all in 100usec. */
4874 spec.t1_t3 = 210 * 10;
4875 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4876 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4877 spec.t10 = 500 * 10;
4878 /* This one is special and actually in units of 100ms, but zero
4879 * based in the hw (so we need to add 100 ms). But the sw vbt
4880 * table multiplies it with 1000 to make it in units of 100usec,
4881 * too. */
4882 spec.t11_t12 = (510 + 100) * 10;
4883
de9c1b6b 4884 intel_pps_dump_state("vbt", &vbt);
67a54566
DV		 4885
4886 /* Use the max of the register settings and vbt. If both are
4887 * unset, fall back to the spec limits. */
36b5f425 4888#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4889 spec.field : \
4890 max(cur.field, vbt.field))
4891 assign_final(t1_t3);
4892 assign_final(t8);
4893 assign_final(t9);
4894 assign_final(t10);
4895 assign_final(t11_t12);
4896#undef assign_final
4897
36b5f425 4898#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4899 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4900 intel_dp->backlight_on_delay = get_delay(t8);
4901 intel_dp->backlight_off_delay = get_delay(t9);
4902 intel_dp->panel_power_down_delay = get_delay(t10);
4903 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4904#undef get_delay
4905
f30d26e4
JN		 4906 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4907 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4908 intel_dp->panel_power_cycle_delay);
4909
4910 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4911 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
de9c1b6b
ID		 4912
4913 /*
4914 * We override the HW backlight delays to 1 because we do manual waits
4915 * on them. For T8, even BSpec recommends doing it. For T9, if we
4916 * don't do this, we'll end up waiting for the backlight off delay
4917 * twice: once when we do the manual sleep, and once when we disable
4918 * the panel and wait for the PP_STATUS bit to become zero.
4919 */
4920 final->t8 = 1;
4921 final->t9 = 1;
f30d26e4
JN		 4922}
4923
4924static void
4925intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4926 struct intel_dp *intel_dp)
f30d26e4
JN		 4927{
4928 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 4929 u32 pp_on, pp_off, pp_div, port_sel = 0;
e7dc33f3 4930 int div = dev_priv->rawclk_freq / 1000;
8e8232d5 4931 struct pps_registers regs;
ad933b56 4932 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4933 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4934
e39b999a 4935 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420 4936
8e8232d5 4937 intel_pps_get_registers(dev_priv, intel_dp, &regs);
453c5420 4938
f30d26e4 4939 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
de9c1b6b
ID		 4940 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
4941 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4942 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4943 /* Compute the divisor for the pp clock, simply match the Bspec
4944 * formula. */
b0a08bec 4945 if (IS_BROXTON(dev)) {
8e8232d5 4946 pp_div = I915_READ(regs.pp_ctrl);
b0a08bec
VK		 4947 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
4948 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
4949 << BXT_POWER_CYCLE_DELAY_SHIFT);
4950 } else {
4951 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4952 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4953 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4954 }
67a54566
DV		 4955
4956 /* Haswell doesn't have any port selection bits for the panel
4957 * power sequencer any more. */
666a4537 4958 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
ad933b56 4959 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4960 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4961 if (port == PORT_A)
a24c144c 4962 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4963 else
a24c144c 4964 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4965 }
4966
453c5420
JB		 4967 pp_on |= port_sel;
4968
8e8232d5
ID		 4969 I915_WRITE(regs.pp_on, pp_on);
4970 I915_WRITE(regs.pp_off, pp_off);
b0a08bec 4971 if (IS_BROXTON(dev))
8e8232d5 4972 I915_WRITE(regs.pp_ctrl, pp_div);
b0a08bec 4973 else
8e8232d5 4974 I915_WRITE(regs.pp_div, pp_div);
67a54566 4975
67a54566 4976 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
8e8232d5
ID		 4977 I915_READ(regs.pp_on),
4978 I915_READ(regs.pp_off),
b0a08bec 4979 IS_BROXTON(dev) ?
8e8232d5
ID		 4980 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
4981 I915_READ(regs.pp_div));
f684960e
CW		 4982}
4983
b33a2815
VK		 4984/**
4985 * intel_dp_set_drrs_state - program registers for RR switch to take effect
4986 * @dev: DRM device
4987 * @refresh_rate: RR to be programmed
4988 *
4989 * This function gets called when refresh rate (RR) has to be changed from
4990 * one frequency to another. Switches can be between high and low RR
4991 * supported by the panel or to any other RR based on media playback (in
4992 * this case, RR value needs to be passed from user space).
4993 *
4994 * The caller of this function needs to take a lock on dev_priv->drrs.
4995 */
96178eeb 4996static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 4997{
4998 struct drm_i915_private *dev_priv = dev->dev_private;
4999 struct intel_encoder *encoder;
96178eeb
VK		 5000 struct intel_digital_port *dig_port = NULL;
5001 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 5002 struct intel_crtc_state *config = NULL;
439d7ac0 5003 struct intel_crtc *intel_crtc = NULL;
96178eeb 5004 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5005
5006 if (refresh_rate <= 0) {
5007 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5008 return;
5009 }
5010
96178eeb
VK		 5011 if (intel_dp == NULL) {
5012 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5013 return;
5014 }
5015
1fcc9d1c 5016 /*
e4d59f6b
RV		 5017 * FIXME: This needs proper synchronization with psr state for some
5018 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5019 */
439d7ac0 5020
96178eeb
VK		 5021 dig_port = dp_to_dig_port(intel_dp);
5022 encoder = &dig_port->base;
723f9aab 5023 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5024
5025 if (!intel_crtc) {
5026 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5027 return;
5028 }
5029
6e3c9717 5030 config = intel_crtc->config;
439d7ac0 5031
96178eeb 5032 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5033 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5034 return;
5035 }
5036
96178eeb
VK		 5037 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5038 refresh_rate)
439d7ac0
PB		 5039 index = DRRS_LOW_RR;
5040
96178eeb 5041 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5042 DRM_DEBUG_KMS(
5043 "DRRS requested for previously set RR...ignoring\n");
5044 return;
5045 }
5046
5047 if (!intel_crtc->active) {
5048 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5049 return;
5050 }
5051
44395bfe 5052 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 5053 switch (index) {
5054 case DRRS_HIGH_RR:
5055 intel_dp_set_m_n(intel_crtc, M1_N1);
5056 break;
5057 case DRRS_LOW_RR:
5058 intel_dp_set_m_n(intel_crtc, M2_N2);
5059 break;
5060 case DRRS_MAX_RR:
5061 default:
5062 DRM_ERROR("Unsupported refreshrate type\n");
5063 }
5064 } else if (INTEL_INFO(dev)->gen > 6) {
f0f59a00 5065 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
649636ef 5066 u32 val;
a4c30b1d 5067
649636ef 5068 val = I915_READ(reg);
439d7ac0 5069 if (index > DRRS_HIGH_RR) {
666a4537 5070 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
6fa7aec1
VK		 5071 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5072 else
5073 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5074 } else {
666a4537 5075 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
6fa7aec1
VK		 5076 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5077 else
5078 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5079 }
5080 I915_WRITE(reg, val);
5081 }
5082
4e9ac947
VK		 5083 dev_priv->drrs.refresh_rate_type = index;
5084
5085 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5086}
5087
b33a2815
VK		 5088/**
5089 * intel_edp_drrs_enable - init drrs struct if supported
5090 * @intel_dp: DP struct
5091 *
5092 * Initializes frontbuffer_bits and drrs.dp
5093 */
c395578e
VK		 5094void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5095{
5096 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5097 struct drm_i915_private *dev_priv = dev->dev_private;
5098 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5099 struct drm_crtc *crtc = dig_port->base.base.crtc;
5100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5101
5102 if (!intel_crtc->config->has_drrs) {
5103 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5104 return;
5105 }
5106
5107 mutex_lock(&dev_priv->drrs.mutex);
5108 if (WARN_ON(dev_priv->drrs.dp)) {
5109 DRM_ERROR("DRRS already enabled\n");
5110 goto unlock;
5111 }
5112
5113 dev_priv->drrs.busy_frontbuffer_bits = 0;
5114
5115 dev_priv->drrs.dp = intel_dp;
5116
5117unlock:
5118 mutex_unlock(&dev_priv->drrs.mutex);
5119}
5120
b33a2815
VK		 5121/**
5122 * intel_edp_drrs_disable - Disable DRRS
5123 * @intel_dp: DP struct
5124 *
5125 */
c395578e
VK		 5126void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5127{
5128 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5129 struct drm_i915_private *dev_priv = dev->dev_private;
5130 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5131 struct drm_crtc *crtc = dig_port->base.base.crtc;
5132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5133
5134 if (!intel_crtc->config->has_drrs)
5135 return;
5136
5137 mutex_lock(&dev_priv->drrs.mutex);
5138 if (!dev_priv->drrs.dp) {
5139 mutex_unlock(&dev_priv->drrs.mutex);
5140 return;
5141 }
5142
5143 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5144 intel_dp_set_drrs_state(dev_priv->dev,
5145 intel_dp->attached_connector->panel.
5146 fixed_mode->vrefresh);
5147
5148 dev_priv->drrs.dp = NULL;
5149 mutex_unlock(&dev_priv->drrs.mutex);
5150
5151 cancel_delayed_work_sync(&dev_priv->drrs.work);
5152}
5153
4e9ac947
VK		 5154static void intel_edp_drrs_downclock_work(struct work_struct *work)
5155{
5156 struct drm_i915_private *dev_priv =
5157 container_of(work, typeof(*dev_priv), drrs.work.work);
5158 struct intel_dp *intel_dp;
5159
5160 mutex_lock(&dev_priv->drrs.mutex);
5161
5162 intel_dp = dev_priv->drrs.dp;
5163
5164 if (!intel_dp)
5165 goto unlock;
5166
439d7ac0 5167 /*
4e9ac947
VK		 5168 * The delayed work can race with an invalidate hence we need to
5169 * recheck.
439d7ac0
PB		 5170 */
5171
4e9ac947
VK		 5172 if (dev_priv->drrs.busy_frontbuffer_bits)
5173 goto unlock;
439d7ac0 5174
4e9ac947
VK		 5175 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5176 intel_dp_set_drrs_state(dev_priv->dev,
5177 intel_dp->attached_connector->panel.
5178 downclock_mode->vrefresh);
439d7ac0 5179
4e9ac947 5180unlock:
4e9ac947 5181 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5182}
5183
b33a2815 5184/**
0ddfd203 5185 * intel_edp_drrs_invalidate - Disable Idleness DRRS
b33a2815
VK		 5186 * @dev: DRM device
5187 * @frontbuffer_bits: frontbuffer plane tracking bits
5188 *
0ddfd203
R		 5189 * This function gets called everytime rendering on the given planes start.
5190 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
b33a2815
VK		 5191 *
5192 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5193 */
a93fad0f
VK		 5194void intel_edp_drrs_invalidate(struct drm_device *dev,
5195 unsigned frontbuffer_bits)
5196{
5197 struct drm_i915_private *dev_priv = dev->dev_private;
5198 struct drm_crtc *crtc;
5199 enum pipe pipe;
5200
9da7d693 5201 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5202 return;
5203
88f933a8 5204 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5205
a93fad0f 5206 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5207 if (!dev_priv->drrs.dp) {
5208 mutex_unlock(&dev_priv->drrs.mutex);
5209 return;
5210 }
5211
a93fad0f
VK		 5212 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5213 pipe = to_intel_crtc(crtc)->pipe;
5214
c1d038c6
DV		 5215 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5216 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5217
0ddfd203 5218 /* invalidate means busy screen hence upclock */
c1d038c6 5219 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
a93fad0f
VK		 5220 intel_dp_set_drrs_state(dev_priv->dev,
5221 dev_priv->drrs.dp->attached_connector->panel.
5222 fixed_mode->vrefresh);
a93fad0f 5223
a93fad0f
VK		 5224 mutex_unlock(&dev_priv->drrs.mutex);
5225}
5226
b33a2815 5227/**
0ddfd203 5228 * intel_edp_drrs_flush - Restart Idleness DRRS
b33a2815
VK		 5229 * @dev: DRM device
5230 * @frontbuffer_bits: frontbuffer plane tracking bits
5231 *
0ddfd203
R		 5232 * This function gets called every time rendering on the given planes has
5233 * completed or flip on a crtc is completed. So DRRS should be upclocked
5234 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5235 * if no other planes are dirty.
b33a2815
VK		 5236 *
5237 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5238 */
a93fad0f
VK		 5239void intel_edp_drrs_flush(struct drm_device *dev,
5240 unsigned frontbuffer_bits)
5241{
5242 struct drm_i915_private *dev_priv = dev->dev_private;
5243 struct drm_crtc *crtc;
5244 enum pipe pipe;
5245
9da7d693 5246 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5247 return;
5248
88f933a8 5249 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5250
a93fad0f 5251 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5252 if (!dev_priv->drrs.dp) {
5253 mutex_unlock(&dev_priv->drrs.mutex);
5254 return;
5255 }
5256
a93fad0f
VK		 5257 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5258 pipe = to_intel_crtc(crtc)->pipe;
c1d038c6
DV		 5259
5260 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
a93fad0f
VK		 5261 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5262
0ddfd203 5263 /* flush means busy screen hence upclock */
c1d038c6 5264 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
0ddfd203
R		 5265 intel_dp_set_drrs_state(dev_priv->dev,
5266 dev_priv->drrs.dp->attached_connector->panel.
5267 fixed_mode->vrefresh);
5268
5269 /*
5270 * flush also means no more activity hence schedule downclock, if all
5271 * other fbs are quiescent too
5272 */
5273 if (!dev_priv->drrs.busy_frontbuffer_bits)
a93fad0f
VK		 5274 schedule_delayed_work(&dev_priv->drrs.work,
5275 msecs_to_jiffies(1000));
5276 mutex_unlock(&dev_priv->drrs.mutex);
5277}
5278
b33a2815
VK		 5279/**
5280 * DOC: Display Refresh Rate Switching (DRRS)
5281 *
5282 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5283 * which enables swtching between low and high refresh rates,
5284 * dynamically, based on the usage scenario. This feature is applicable
5285 * for internal panels.
5286 *
5287 * Indication that the panel supports DRRS is given by the panel EDID, which
5288 * would list multiple refresh rates for one resolution.
5289 *
5290 * DRRS is of 2 types - static and seamless.
5291 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5292 * (may appear as a blink on screen) and is used in dock-undock scenario.
5293 * Seamless DRRS involves changing RR without any visual effect to the user
5294 * and can be used during normal system usage. This is done by programming
5295 * certain registers.
5296 *
5297 * Support for static/seamless DRRS may be indicated in the VBT based on
5298 * inputs from the panel spec.
5299 *
5300 * DRRS saves power by switching to low RR based on usage scenarios.
5301 *
2e7a5701
DV		 5302 * The implementation is based on frontbuffer tracking implementation. When
5303 * there is a disturbance on the screen triggered by user activity or a periodic
5304 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5305 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5306 * made.
5307 *
5308 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5309 * and intel_edp_drrs_flush() are called.
b33a2815
VK		 5310 *
5311 * DRRS can be further extended to support other internal panels and also
5312 * the scenario of video playback wherein RR is set based on the rate
5313 * requested by userspace.
5314 */
5315
5316/**
5317 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5318 * @intel_connector: eDP connector
5319 * @fixed_mode: preferred mode of panel
5320 *
5321 * This function is called only once at driver load to initialize basic
5322 * DRRS stuff.
5323 *
5324 * Returns:
5325 * Downclock mode if panel supports it, else return NULL.
5326 * DRRS support is determined by the presence of downclock mode (apart
5327 * from VBT setting).
5328 */
4f9db5b5 5329static struct drm_display_mode *
96178eeb
VK		 5330intel_dp_drrs_init(struct intel_connector *intel_connector,
5331 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5332{
5333 struct drm_connector *connector = &intel_connector->base;
96178eeb 5334 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5335 struct drm_i915_private *dev_priv = dev->dev_private;
5336 struct drm_display_mode *downclock_mode = NULL;
5337
9da7d693
DV		 5338 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5339 mutex_init(&dev_priv->drrs.mutex);
5340
4f9db5b5
PB		 5341 if (INTEL_INFO(dev)->gen <= 6) {
5342 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5343 return NULL;
5344 }
5345
5346 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5347 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5348 return NULL;
5349 }
5350
5351 downclock_mode = intel_find_panel_downclock
5352 (dev, fixed_mode, connector);
5353
5354 if (!downclock_mode) {
a1d26342 5355 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5356 return NULL;
5357 }
5358
96178eeb 5359 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5360
96178eeb 5361 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5362 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5363 return downclock_mode;
5364}
5365
ed92f0b2 5366static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5367 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5368{
5369 struct drm_connector *connector = &intel_connector->base;
5370 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5371 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5372 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5373 struct drm_i915_private *dev_priv = dev->dev_private;
5374 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5375 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5376 bool has_dpcd;
5377 struct drm_display_mode *scan;
5378 struct edid *edid;
6517d273 5379 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5380
5381 if (!is_edp(intel_dp))
5382 return true;
5383
97a824e1
ID		 5384 /*
5385 * On IBX/CPT we may get here with LVDS already registered. Since the
5386 * driver uses the only internal power sequencer available for both
5387 * eDP and LVDS bail out early in this case to prevent interfering
5388 * with an already powered-on LVDS power sequencer.
5389 */
5390 if (intel_get_lvds_encoder(dev)) {
5391 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5392 DRM_INFO("LVDS was detected, not registering eDP\n");
5393
5394 return false;
5395 }
5396
49e6bc51 5397 pps_lock(intel_dp);
b4d06ede
ID		 5398
5399 intel_dp_init_panel_power_timestamps(intel_dp);
5400
5401 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5402 vlv_initial_power_sequencer_setup(intel_dp);
5403 } else {
5404 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5405 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5406 }
5407
49e6bc51 5408 intel_edp_panel_vdd_sanitize(intel_dp);
b4d06ede 5409
49e6bc51 5410 pps_unlock(intel_dp);
63635217 5411
ed92f0b2 5412 /* Cache DPCD and EDID for edp. */
ed92f0b2 5413 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5414
5415 if (has_dpcd) {
5416 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5417 dev_priv->no_aux_handshake =
5418 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5419 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5420 } else {
5421 /* if this fails, presume the device is a ghost */
5422 DRM_INFO("failed to retrieve link info, disabling eDP\n");
b4d06ede 5423 goto out_vdd_off;
ed92f0b2
PZ		 5424 }
5425
060c8778 5426 mutex_lock(&dev->mode_config.mutex);
0b99836f 5427 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5428 if (edid) {
5429 if (drm_add_edid_modes(connector, edid)) {
5430 drm_mode_connector_update_edid_property(connector,
5431 edid);
5432 drm_edid_to_eld(connector, edid);
5433 } else {
5434 kfree(edid);
5435 edid = ERR_PTR(-EINVAL);
5436 }
5437 } else {
5438 edid = ERR_PTR(-ENOENT);
5439 }
5440 intel_connector->edid = edid;
5441
5442 /* prefer fixed mode from EDID if available */
5443 list_for_each_entry(scan, &connector->probed_modes, head) {
5444 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5445 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5446 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5447 intel_connector, fixed_mode);
ed92f0b2
PZ		 5448 break;
5449 }
5450 }
5451
5452 /* fallback to VBT if available for eDP */
5453 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5454 fixed_mode = drm_mode_duplicate(dev,
5455 dev_priv->vbt.lfp_lvds_vbt_mode);
df457245 5456 if (fixed_mode) {
ed92f0b2 5457 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
df457245
VS		 5458 connector->display_info.width_mm = fixed_mode->width_mm;
5459 connector->display_info.height_mm = fixed_mode->height_mm;
5460 }
ed92f0b2 5461 }
060c8778 5462 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5463
666a4537 5464 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
01527b31
CT		 5465 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5466 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5467
5468 /*
5469 * Figure out the current pipe for the initial backlight setup.
5470 * If the current pipe isn't valid, try the PPS pipe, and if that
5471 * fails just assume pipe A.
5472 */
5473 if (IS_CHERRYVIEW(dev))
5474 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5475 else
5476 pipe = PORT_TO_PIPE(intel_dp->DP);
5477
5478 if (pipe != PIPE_A && pipe != PIPE_B)
5479 pipe = intel_dp->pps_pipe;
5480
5481 if (pipe != PIPE_A && pipe != PIPE_B)
5482 pipe = PIPE_A;
5483
5484 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5485 pipe_name(pipe));
01527b31
CT		 5486 }
5487
4f9db5b5 5488 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5507faeb 5489 intel_connector->panel.backlight.power = intel_edp_backlight_power;
6517d273 5490 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5491
5492 return true;
b4d06ede
ID		 5493
5494out_vdd_off:
5495 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5496 /*
5497 * vdd might still be enabled do to the delayed vdd off.
5498 * Make sure vdd is actually turned off here.
5499 */
5500 pps_lock(intel_dp);
5501 edp_panel_vdd_off_sync(intel_dp);
5502 pps_unlock(intel_dp);
5503
5504 return false;
ed92f0b2
PZ		 5505}
5506
16c25533 5507bool
f0fec3f2
PZ		 5508intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5509 struct intel_connector *intel_connector)
a4fc5ed6 5510{
f0fec3f2
PZ		 5511 struct drm_connector *connector = &intel_connector->base;
5512 struct intel_dp *intel_dp = &intel_dig_port->dp;
5513 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5514 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5515 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5516 enum port port = intel_dig_port->port;
a121f4e5 5517 int type, ret;
a4fc5ed6 5518
ccb1a831
VS		 5519 if (WARN(intel_dig_port->max_lanes < 1,
5520 "Not enough lanes (%d) for DP on port %c\n",
5521 intel_dig_port->max_lanes, port_name(port)))
5522 return false;
5523
a4a5d2f8
VS		 5524 intel_dp->pps_pipe = INVALID_PIPE;
5525
ec5b01dd 5526 /* intel_dp vfuncs */
b6b5e383
DL		 5527 if (INTEL_INFO(dev)->gen >= 9)
5528 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
ec5b01dd
DL		 5529 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5530 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5531 else if (HAS_PCH_SPLIT(dev))
5532 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5533 else
6ffb1be7 5534 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
ec5b01dd 5535
b9ca5fad
DL		 5536 if (INTEL_INFO(dev)->gen >= 9)
5537 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5538 else
6ffb1be7 5539 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
153b1100 5540
ad64217b
ACO		 5541 if (HAS_DDI(dev))
5542 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5543
0767935e
DV		 5544 /* Preserve the current hw state. */
5545 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5546 intel_dp->attached_connector = intel_connector;
3d3dc149 5547
3b32a35b 5548 if (intel_dp_is_edp(dev, port))
b329530c 5549 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5550 else
5551 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5552
f7d24902
ID		 5553 /*
5554 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5555 * for DP the encoder type can be set by the caller to
5556 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5557 */
5558 if (type == DRM_MODE_CONNECTOR_eDP)
5559 intel_encoder->type = INTEL_OUTPUT_EDP;
5560
c17ed5b5 5561 /* eDP only on port B and/or C on vlv/chv */
666a4537
WB		 5562 if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5563 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
c17ed5b5
VS		 5564 return false;
5565
e7281eab
ID		 5566 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5567 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5568 port_name(port));
5569
b329530c 5570 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5571 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5572
a4fc5ed6
KP		 5573 connector->interlace_allowed = true;
5574 connector->doublescan_allowed = 0;
5575
f0fec3f2 5576 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5577 edp_panel_vdd_work);
a4fc5ed6 5578
df0e9248 5579 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5580 drm_connector_register(connector);
a4fc5ed6 5581
affa9354 5582 if (HAS_DDI(dev))
bcbc889b
PZ		 5583 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5584 else
5585 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5586 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5587
0b99836f 5588 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5589 switch (port) {
5590 case PORT_A:
1d843f9d 5591 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5592 break;
5593 case PORT_B:
1d843f9d 5594 intel_encoder->hpd_pin = HPD_PORT_B;
e87a005d 5595 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
cf1d5883 5596 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5597 break;
5598 case PORT_C:
1d843f9d 5599 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5600 break;
5601 case PORT_D:
1d843f9d 5602 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30 5603 break;
26951caf
XZ		 5604 case PORT_E:
5605 intel_encoder->hpd_pin = HPD_PORT_E;
5606 break;
ab9d7c30 5607 default:
ad1c0b19 5608 BUG();
5eb08b69
ZW		 5609 }
5610
a121f4e5
VS		 5611 ret = intel_dp_aux_init(intel_dp, intel_connector);
5612 if (ret)
5613 goto fail;
c1f05264 5614
0e32b39c 5615 /* init MST on ports that can support it */
0c9b3715
JN		 5616 if (HAS_DP_MST(dev) &&
5617 (port == PORT_B || port == PORT_C || port == PORT_D))
5618 intel_dp_mst_encoder_init(intel_dig_port,
5619 intel_connector->base.base.id);
0e32b39c 5620
36b5f425 5621 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
a121f4e5
VS		 5622 intel_dp_aux_fini(intel_dp);
5623 intel_dp_mst_encoder_cleanup(intel_dig_port);
5624 goto fail;
b2f246a8 5625 }
32f9d658 5626
f684960e
CW		 5627 intel_dp_add_properties(intel_dp, connector);
5628
a4fc5ed6
KP		 5629 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5630 * 0xd. Failure to do so will result in spurious interrupts being
5631 * generated on the port when a cable is not attached.
5632 */
5633 if (IS_G4X(dev) && !IS_GM45(dev)) {
5634 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5635 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5636 }
16c25533 5637
aa7471d2
JN		 5638 i915_debugfs_connector_add(connector);
5639
16c25533 5640 return true;
a121f4e5
VS		 5641
5642fail:
a121f4e5
VS		 5643 drm_connector_unregister(connector);
5644 drm_connector_cleanup(connector);
5645
5646 return false;
a4fc5ed6 5647}
f0fec3f2 5648
457c52d8
CW		 5649bool intel_dp_init(struct drm_device *dev,
5650 i915_reg_t output_reg,
5651 enum port port)
f0fec3f2 5652{
13cf5504 5653 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5654 struct intel_digital_port *intel_dig_port;
5655 struct intel_encoder *intel_encoder;
5656 struct drm_encoder *encoder;
5657 struct intel_connector *intel_connector;
5658
b14c5679 5659 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2 5660 if (!intel_dig_port)
457c52d8 5661 return false;
f0fec3f2 5662
08d9bc92 5663 intel_connector = intel_connector_alloc();
11aee0f6
SM		 5664 if (!intel_connector)
5665 goto err_connector_alloc;
f0fec3f2
PZ		 5666
5667 intel_encoder = &intel_dig_port->base;
5668 encoder = &intel_encoder->base;
5669
893da0c9 5670 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
580d8ed5 5671 DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))
893da0c9 5672 goto err_encoder_init;
f0fec3f2 5673
5bfe2ac0 5674 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5675 intel_encoder->disable = intel_disable_dp;
00c09d70 5676 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5677 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5678 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5679 if (IS_CHERRYVIEW(dev)) {
9197c88b 5680 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5681 intel_encoder->pre_enable = chv_pre_enable_dp;
5682 intel_encoder->enable = vlv_enable_dp;
580d3811 5683 intel_encoder->post_disable = chv_post_disable_dp;
d6db995f 5684 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
e4a1d846 5685 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5686 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5687 intel_encoder->pre_enable = vlv_pre_enable_dp;
5688 intel_encoder->enable = vlv_enable_dp;
49277c31 5689 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5690 } else {
ecff4f3b
JN		 5691 intel_encoder->pre_enable = g4x_pre_enable_dp;
5692 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5693 if (INTEL_INFO(dev)->gen >= 5)
5694 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5695 }
f0fec3f2 5696
174edf1f 5697 intel_dig_port->port = port;
f0fec3f2 5698 intel_dig_port->dp.output_reg = output_reg;
ccb1a831 5699 intel_dig_port->max_lanes = 4;
f0fec3f2 5700
00c09d70 5701 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5702 if (IS_CHERRYVIEW(dev)) {
5703 if (port == PORT_D)
5704 intel_encoder->crtc_mask = 1 << 2;
5705 else
5706 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5707 } else {
5708 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5709 }
bc079e8b 5710 intel_encoder->cloneable = 0;
f0fec3f2 5711
13cf5504 5712 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 5713 dev_priv->hotplug.irq_port[port] = intel_dig_port;
13cf5504 5714
11aee0f6
SM		 5715 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5716 goto err_init_connector;
5717
457c52d8 5718 return true;
11aee0f6
SM		 5719
5720err_init_connector:
5721 drm_encoder_cleanup(encoder);
893da0c9 5722err_encoder_init:
11aee0f6
SM		 5723 kfree(intel_connector);
5724err_connector_alloc:
5725 kfree(intel_dig_port);
457c52d8 5726 return false;
f0fec3f2 5727}
0e32b39c
DA		 5728
5729void intel_dp_mst_suspend(struct drm_device *dev)
5730{
5731 struct drm_i915_private *dev_priv = dev->dev_private;
5732 int i;
5733
5734 /* disable MST */
5735 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5736 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 5737 if (!intel_dig_port)
5738 continue;
5739
5740 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5741 if (!intel_dig_port->dp.can_mst)
5742 continue;
5743 if (intel_dig_port->dp.is_mst)
5744 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5745 }
5746 }
5747}
5748
5749void intel_dp_mst_resume(struct drm_device *dev)
5750{
5751 struct drm_i915_private *dev_priv = dev->dev_private;
5752 int i;
5753
5754 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5755 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 5756 if (!intel_dig_port)
5757 continue;
5758 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5759 int ret;
5760
5761 if (!intel_dig_port->dp.can_mst)
5762 continue;
5763
5764 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5765 if (ret != 0) {
5766 intel_dp_check_mst_status(&intel_dig_port->dp);
5767 }
5768 }
5769 }
5770}
Linux kernel - Deliverables
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