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drm/i915/skl: Add support for edp 1.4 intermediate frequencies
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
9dd4ffdf
CML		 44struct dp_link_dpll {
45 int link_bw;
46 struct dpll dpll;
47};
48
49static const struct dp_link_dpll gen4_dpll[] = {
50 { DP_LINK_BW_1_62,
51 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
52 { DP_LINK_BW_2_7,
53 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
54};
55
56static const struct dp_link_dpll pch_dpll[] = {
57 { DP_LINK_BW_1_62,
58 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
59 { DP_LINK_BW_2_7,
60 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
61};
62
65ce4bf5
CML		 63static const struct dp_link_dpll vlv_dpll[] = {
64 { DP_LINK_BW_1_62,
58f6e632 65 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 66 { DP_LINK_BW_2_7,
67 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
68};
69
ef9348c8
CML		 70/*
71 * CHV supports eDP 1.4 that have more link rates.
72 * Below only provides the fixed rate but exclude variable rate.
73 */
74static const struct dp_link_dpll chv_dpll[] = {
75 /*
76 * CHV requires to program fractional division for m2.
77 * m2 is stored in fixed point format using formula below
78 * (m2_int << 22) | m2_fraction
79 */
80 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
81 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
82 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
83 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
84 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
85 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
86};
a8f3ef61
SJ		 87/* Skylake supports following rates */
88static const uint32_t gen9_rates[] = { 162000, 216000, 270000, 324000,
89 432000, 540000 };
90
91static const uint32_t default_rates[] = { 162000, 270000, 540000 };
ef9348c8 92
cfcb0fc9
JB		 93/**
94 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
95 * @intel_dp: DP struct
96 *
97 * If a CPU or PCH DP output is attached to an eDP panel, this function
98 * will return true, and false otherwise.
99 */
100static bool is_edp(struct intel_dp *intel_dp)
101{
da63a9f2
PZ		 102 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
103
104 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 105}
106
68b4d824 107static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 108{
68b4d824
ID		 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 112}
113
df0e9248
CW		 114static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
115{
fa90ecef 116 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 117}
118
ea5b213a 119static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 120static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 121static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 122static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 123static void vlv_steal_power_sequencer(struct drm_device *dev,
124 enum pipe pipe);
a4fc5ed6 125
0e32b39c 126int
ea5b213a 127intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 128{
7183dc29 129 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 130 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 131
132 switch (max_link_bw) {
133 case DP_LINK_BW_1_62:
134 case DP_LINK_BW_2_7:
135 break;
d4eead50 136 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 137 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
138 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 139 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
140 max_link_bw = DP_LINK_BW_5_4;
141 else
142 max_link_bw = DP_LINK_BW_2_7;
d4eead50 143 break;
a4fc5ed6 144 default:
d4eead50
ID		 145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
146 max_link_bw);
a4fc5ed6
KP		 147 max_link_bw = DP_LINK_BW_1_62;
148 break;
149 }
150 return max_link_bw;
151}
152
eeb6324d
PZ		 153static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
154{
155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
156 struct drm_device *dev = intel_dig_port->base.base.dev;
157 u8 source_max, sink_max;
158
159 source_max = 4;
160 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
161 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
162 source_max = 2;
163
164 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
165
166 return min(source_max, sink_max);
167}
168
cd9dde44
AJ		 169/*
170 * The units on the numbers in the next two are... bizarre. Examples will
171 * make it clearer; this one parallels an example in the eDP spec.
172 *
173 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
174 *
175 * 270000 * 1 * 8 / 10 == 216000
176 *
177 * The actual data capacity of that configuration is 2.16Gbit/s, so the
178 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
179 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
180 * 119000. At 18bpp that's 2142000 kilobits per second.
181 *
182 * Thus the strange-looking division by 10 in intel_dp_link_required, to
183 * get the result in decakilobits instead of kilobits.
184 */
185
a4fc5ed6 186static int
c898261c 187intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 188{
cd9dde44 189 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 190}
191
fe27d53e
DA		 192static int
193intel_dp_max_data_rate(int max_link_clock, int max_lanes)
194{
195 return (max_link_clock * max_lanes * 8) / 10;
196}
197
c19de8eb 198static enum drm_mode_status
a4fc5ed6
KP		 199intel_dp_mode_valid(struct drm_connector *connector,
200 struct drm_display_mode *mode)
201{
df0e9248 202 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 203 struct intel_connector *intel_connector = to_intel_connector(connector);
204 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 205 int target_clock = mode->clock;
206 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 207
dd06f90e
JN		 208 if (is_edp(intel_dp) && fixed_mode) {
209 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 210 return MODE_PANEL;
211
dd06f90e 212 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 213 return MODE_PANEL;
03afc4a2
DV		 214
215 target_clock = fixed_mode->clock;
7de56f43
ZY		 216 }
217
36008365 218 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 219 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 220
221 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
222 mode_rate = intel_dp_link_required(target_clock, 18);
223
224 if (mode_rate > max_rate)
c4867936 225 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 226
227 if (mode->clock < 10000)
228 return MODE_CLOCK_LOW;
229
0af78a2b
DV		 230 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
231 return MODE_H_ILLEGAL;
232
a4fc5ed6
KP		 233 return MODE_OK;
234}
235
a4f1289e 236uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 237{
238 int i;
239 uint32_t v = 0;
240
241 if (src_bytes > 4)
242 src_bytes = 4;
243 for (i = 0; i < src_bytes; i++)
244 v |= ((uint32_t) src[i]) << ((3-i) * 8);
245 return v;
246}
247
c2af70e2 248static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 249{
250 int i;
251 if (dst_bytes > 4)
252 dst_bytes = 4;
253 for (i = 0; i < dst_bytes; i++)
254 dst[i] = src >> ((3-i) * 8);
255}
256
fb0f8fbf
KP		 257/* hrawclock is 1/4 the FSB frequency */
258static int
259intel_hrawclk(struct drm_device *dev)
260{
261 struct drm_i915_private *dev_priv = dev->dev_private;
262 uint32_t clkcfg;
263
9473c8f4
VP		 264 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
265 if (IS_VALLEYVIEW(dev))
266 return 200;
267
fb0f8fbf
KP		 268 clkcfg = I915_READ(CLKCFG);
269 switch (clkcfg & CLKCFG_FSB_MASK) {
270 case CLKCFG_FSB_400:
271 return 100;
272 case CLKCFG_FSB_533:
273 return 133;
274 case CLKCFG_FSB_667:
275 return 166;
276 case CLKCFG_FSB_800:
277 return 200;
278 case CLKCFG_FSB_1067:
279 return 266;
280 case CLKCFG_FSB_1333:
281 return 333;
282 /* these two are just a guess; one of them might be right */
283 case CLKCFG_FSB_1600:
284 case CLKCFG_FSB_1600_ALT:
285 return 400;
286 default:
287 return 133;
288 }
289}
290
bf13e81b
JN		 291static void
292intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 293 struct intel_dp *intel_dp);
bf13e81b
JN		 294static void
295intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 296 struct intel_dp *intel_dp);
bf13e81b 297
773538e8
VS		 298static void pps_lock(struct intel_dp *intel_dp)
299{
300 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
301 struct intel_encoder *encoder = &intel_dig_port->base;
302 struct drm_device *dev = encoder->base.dev;
303 struct drm_i915_private *dev_priv = dev->dev_private;
304 enum intel_display_power_domain power_domain;
305
306 /*
307 * See vlv_power_sequencer_reset() why we need
308 * a power domain reference here.
309 */
310 power_domain = intel_display_port_power_domain(encoder);
311 intel_display_power_get(dev_priv, power_domain);
312
313 mutex_lock(&dev_priv->pps_mutex);
314}
315
316static void pps_unlock(struct intel_dp *intel_dp)
317{
318 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
319 struct intel_encoder *encoder = &intel_dig_port->base;
320 struct drm_device *dev = encoder->base.dev;
321 struct drm_i915_private *dev_priv = dev->dev_private;
322 enum intel_display_power_domain power_domain;
323
324 mutex_unlock(&dev_priv->pps_mutex);
325
326 power_domain = intel_display_port_power_domain(encoder);
327 intel_display_power_put(dev_priv, power_domain);
328}
329
961a0db0
VS		 330static void
331vlv_power_sequencer_kick(struct intel_dp *intel_dp)
332{
333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
334 struct drm_device *dev = intel_dig_port->base.base.dev;
335 struct drm_i915_private *dev_priv = dev->dev_private;
336 enum pipe pipe = intel_dp->pps_pipe;
d288f65f 337 bool pll_enabled;
961a0db0
VS		 338 uint32_t DP;
339
340 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
341 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
342 pipe_name(pipe), port_name(intel_dig_port->port)))
343 return;
344
345 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
346 pipe_name(pipe), port_name(intel_dig_port->port));
347
348 /* Preserve the BIOS-computed detected bit. This is
349 * supposed to be read-only.
350 */
351 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
352 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
353 DP |= DP_PORT_WIDTH(1);
354 DP |= DP_LINK_TRAIN_PAT_1;
355
356 if (IS_CHERRYVIEW(dev))
357 DP |= DP_PIPE_SELECT_CHV(pipe);
358 else if (pipe == PIPE_B)
359 DP |= DP_PIPEB_SELECT;
360
d288f65f
VS		 361 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
362
363 /*
364 * The DPLL for the pipe must be enabled for this to work.
365 * So enable temporarily it if it's not already enabled.
366 */
367 if (!pll_enabled)
368 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
369 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
370
961a0db0
VS		 371 /*
372 * Similar magic as in intel_dp_enable_port().
373 * We _must_ do this port enable + disable trick
374 * to make this power seqeuencer lock onto the port.
375 * Otherwise even VDD force bit won't work.
376 */
377 I915_WRITE(intel_dp->output_reg, DP);
378 POSTING_READ(intel_dp->output_reg);
379
380 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
381 POSTING_READ(intel_dp->output_reg);
382
383 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
384 POSTING_READ(intel_dp->output_reg);
d288f65f
VS		 385
386 if (!pll_enabled)
387 vlv_force_pll_off(dev, pipe);
961a0db0
VS		 388}
389
bf13e81b
JN		 390static enum pipe
391vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
392{
393 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 394 struct drm_device *dev = intel_dig_port->base.base.dev;
395 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 396 struct intel_encoder *encoder;
397 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 398 enum pipe pipe;
bf13e81b 399
e39b999a 400 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 401
a8c3344e
VS		 402 /* We should never land here with regular DP ports */
403 WARN_ON(!is_edp(intel_dp));
404
a4a5d2f8
VS		 405 if (intel_dp->pps_pipe != INVALID_PIPE)
406 return intel_dp->pps_pipe;
407
408 /*
409 * We don't have power sequencer currently.
410 * Pick one that's not used by other ports.
411 */
412 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
413 base.head) {
414 struct intel_dp *tmp;
415
416 if (encoder->type != INTEL_OUTPUT_EDP)
417 continue;
418
419 tmp = enc_to_intel_dp(&encoder->base);
420
421 if (tmp->pps_pipe != INVALID_PIPE)
422 pipes &= ~(1 << tmp->pps_pipe);
423 }
424
425 /*
426 * Didn't find one. This should not happen since there
427 * are two power sequencers and up to two eDP ports.
428 */
429 if (WARN_ON(pipes == 0))
a8c3344e
VS		 430 pipe = PIPE_A;
431 else
432 pipe = ffs(pipes) - 1;
a4a5d2f8 433
a8c3344e
VS		 434 vlv_steal_power_sequencer(dev, pipe);
435 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 436
437 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
438 pipe_name(intel_dp->pps_pipe),
439 port_name(intel_dig_port->port));
440
441 /* init power sequencer on this pipe and port */
36b5f425
VS		 442 intel_dp_init_panel_power_sequencer(dev, intel_dp);
443 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 444
961a0db0
VS		 445 /*
446 * Even vdd force doesn't work until we've made
447 * the power sequencer lock in on the port.
448 */
449 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 450
451 return intel_dp->pps_pipe;
452}
453
6491ab27
VS		 454typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
455 enum pipe pipe);
456
457static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
458 enum pipe pipe)
459{
460 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
461}
462
463static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
464 enum pipe pipe)
465{
466 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
467}
468
469static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
470 enum pipe pipe)
471{
472 return true;
473}
bf13e81b 474
a4a5d2f8 475static enum pipe
6491ab27
VS		 476vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
477 enum port port,
478 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 479{
480 enum pipe pipe;
bf13e81b 481
bf13e81b
JN		 482 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
483 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
484 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 485
486 if (port_sel != PANEL_PORT_SELECT_VLV(port))
487 continue;
488
6491ab27
VS		 489 if (!pipe_check(dev_priv, pipe))
490 continue;
491
a4a5d2f8 492 return pipe;
bf13e81b
JN		 493 }
494
a4a5d2f8
VS		 495 return INVALID_PIPE;
496}
497
498static void
499vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
500{
501 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
502 struct drm_device *dev = intel_dig_port->base.base.dev;
503 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 504 enum port port = intel_dig_port->port;
505
506 lockdep_assert_held(&dev_priv->pps_mutex);
507
508 /* try to find a pipe with this port selected */
6491ab27
VS		 509 /* first pick one where the panel is on */
510 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
511 vlv_pipe_has_pp_on);
512 /* didn't find one? pick one where vdd is on */
513 if (intel_dp->pps_pipe == INVALID_PIPE)
514 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
515 vlv_pipe_has_vdd_on);
516 /* didn't find one? pick one with just the correct port */
517 if (intel_dp->pps_pipe == INVALID_PIPE)
518 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
519 vlv_pipe_any);
a4a5d2f8
VS		 520
521 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
522 if (intel_dp->pps_pipe == INVALID_PIPE) {
523 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
524 port_name(port));
525 return;
bf13e81b
JN		 526 }
527
a4a5d2f8
VS		 528 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
529 port_name(port), pipe_name(intel_dp->pps_pipe));
530
36b5f425
VS		 531 intel_dp_init_panel_power_sequencer(dev, intel_dp);
532 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 533}
534
773538e8
VS		 535void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
536{
537 struct drm_device *dev = dev_priv->dev;
538 struct intel_encoder *encoder;
539
540 if (WARN_ON(!IS_VALLEYVIEW(dev)))
541 return;
542
543 /*
544 * We can't grab pps_mutex here due to deadlock with power_domain
545 * mutex when power_domain functions are called while holding pps_mutex.
546 * That also means that in order to use pps_pipe the code needs to
547 * hold both a power domain reference and pps_mutex, and the power domain
548 * reference get/put must be done while _not_ holding pps_mutex.
549 * pps_{lock,unlock}() do these steps in the correct order, so one
550 * should use them always.
551 */
552
553 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
554 struct intel_dp *intel_dp;
555
556 if (encoder->type != INTEL_OUTPUT_EDP)
557 continue;
558
559 intel_dp = enc_to_intel_dp(&encoder->base);
560 intel_dp->pps_pipe = INVALID_PIPE;
561 }
bf13e81b
JN		 562}
563
564static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
565{
566 struct drm_device *dev = intel_dp_to_dev(intel_dp);
567
568 if (HAS_PCH_SPLIT(dev))
569 return PCH_PP_CONTROL;
570 else
571 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
572}
573
574static u32 _pp_stat_reg(struct intel_dp *intel_dp)
575{
576 struct drm_device *dev = intel_dp_to_dev(intel_dp);
577
578 if (HAS_PCH_SPLIT(dev))
579 return PCH_PP_STATUS;
580 else
581 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
582}
583
01527b31
CT		 584/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
585 This function only applicable when panel PM state is not to be tracked */
586static int edp_notify_handler(struct notifier_block *this, unsigned long code,
587 void *unused)
588{
589 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
590 edp_notifier);
591 struct drm_device *dev = intel_dp_to_dev(intel_dp);
592 struct drm_i915_private *dev_priv = dev->dev_private;
593 u32 pp_div;
594 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 595
596 if (!is_edp(intel_dp) || code != SYS_RESTART)
597 return 0;
598
773538e8 599 pps_lock(intel_dp);
e39b999a 600
01527b31 601 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 602 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
603
01527b31
CT		 604 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
605 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
606 pp_div = I915_READ(pp_div_reg);
607 pp_div &= PP_REFERENCE_DIVIDER_MASK;
608
609 /* 0x1F write to PP_DIV_REG sets max cycle delay */
610 I915_WRITE(pp_div_reg, pp_div | 0x1F);
611 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
612 msleep(intel_dp->panel_power_cycle_delay);
613 }
614
773538e8 615 pps_unlock(intel_dp);
e39b999a 616
01527b31
CT		 617 return 0;
618}
619
4be73780 620static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 621{
30add22d 622 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 623 struct drm_i915_private *dev_priv = dev->dev_private;
624
e39b999a
VS		 625 lockdep_assert_held(&dev_priv->pps_mutex);
626
9a42356b
VS		 627 if (IS_VALLEYVIEW(dev) &&
628 intel_dp->pps_pipe == INVALID_PIPE)
629 return false;
630
bf13e81b 631 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 632}
633
4be73780 634static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 635{
30add22d 636 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 637 struct drm_i915_private *dev_priv = dev->dev_private;
638
e39b999a
VS		 639 lockdep_assert_held(&dev_priv->pps_mutex);
640
9a42356b
VS		 641 if (IS_VALLEYVIEW(dev) &&
642 intel_dp->pps_pipe == INVALID_PIPE)
643 return false;
644
773538e8 645 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 646}
647
9b984dae
KP		 648static void
649intel_dp_check_edp(struct intel_dp *intel_dp)
650{
30add22d 651 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 652 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 653
9b984dae
KP		 654 if (!is_edp(intel_dp))
655 return;
453c5420 656
4be73780 657 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 658 WARN(1, "eDP powered off while attempting aux channel communication.\n");
659 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 660 I915_READ(_pp_stat_reg(intel_dp)),
661 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 662 }
663}
664
9ee32fea
DV		 665static uint32_t
666intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
667{
668 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
669 struct drm_device *dev = intel_dig_port->base.base.dev;
670 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 671 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 672 uint32_t status;
673 bool done;
674
ef04f00d 675#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 676 if (has_aux_irq)
b18ac466 677 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 678 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 679 else
680 done = wait_for_atomic(C, 10) == 0;
681 if (!done)
682 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
683 has_aux_irq);
684#undef C
685
686 return status;
687}
688
ec5b01dd 689static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 690{
174edf1f
PZ		 691 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
692 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 693
ec5b01dd
DL		 694 /*
695 * The clock divider is based off the hrawclk, and would like to run at
696 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 697 */
ec5b01dd
DL		 698 return index ? 0 : intel_hrawclk(dev) / 2;
699}
700
701static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
702{
703 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
704 struct drm_device *dev = intel_dig_port->base.base.dev;
705
706 if (index)
707 return 0;
708
709 if (intel_dig_port->port == PORT_A) {
710 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 711 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 712 else
b84a1cf8 713 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 714 } else {
715 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
716 }
717}
718
719static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
720{
721 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
722 struct drm_device *dev = intel_dig_port->base.base.dev;
723 struct drm_i915_private *dev_priv = dev->dev_private;
724
725 if (intel_dig_port->port == PORT_A) {
726 if (index)
727 return 0;
728 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 729 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
730 /* Workaround for non-ULT HSW */
bc86625a
CW		 731 switch (index) {
732 case 0: return 63;
733 case 1: return 72;
734 default: return 0;
735 }
ec5b01dd 736 } else {
bc86625a 737 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 738 }
b84a1cf8
RV		 739}
740
ec5b01dd
DL		 741static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
742{
743 return index ? 0 : 100;
744}
745
b6b5e383
DL		 746static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
747{
748 /*
749 * SKL doesn't need us to program the AUX clock divider (Hardware will
750 * derive the clock from CDCLK automatically). We still implement the
751 * get_aux_clock_divider vfunc to plug-in into the existing code.
752 */
753 return index ? 0 : 1;
754}
755
5ed12a19
DL		 756static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
757 bool has_aux_irq,
758 int send_bytes,
759 uint32_t aux_clock_divider)
760{
761 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
762 struct drm_device *dev = intel_dig_port->base.base.dev;
763 uint32_t precharge, timeout;
764
765 if (IS_GEN6(dev))
766 precharge = 3;
767 else
768 precharge = 5;
769
770 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
771 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
772 else
773 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
774
775 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 776 DP_AUX_CH_CTL_DONE |
5ed12a19 777 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 778 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 779 timeout |
788d4433 780 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 781 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
782 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 783 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 784}
785
b9ca5fad
DL		 786static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
787 bool has_aux_irq,
788 int send_bytes,
789 uint32_t unused)
790{
791 return DP_AUX_CH_CTL_SEND_BUSY |
792 DP_AUX_CH_CTL_DONE |
793 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
794 DP_AUX_CH_CTL_TIME_OUT_ERROR |
795 DP_AUX_CH_CTL_TIME_OUT_1600us |
796 DP_AUX_CH_CTL_RECEIVE_ERROR |
797 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
798 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
799}
800
b84a1cf8
RV		 801static int
802intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 803 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 804 uint8_t *recv, int recv_size)
805{
806 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
807 struct drm_device *dev = intel_dig_port->base.base.dev;
808 struct drm_i915_private *dev_priv = dev->dev_private;
809 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
810 uint32_t ch_data = ch_ctl + 4;
bc86625a 811 uint32_t aux_clock_divider;
b84a1cf8
RV		 812 int i, ret, recv_bytes;
813 uint32_t status;
5ed12a19 814 int try, clock = 0;
4e6b788c 815 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 816 bool vdd;
817
773538e8 818 pps_lock(intel_dp);
e39b999a 819
72c3500a
VS		 820 /*
821 * We will be called with VDD already enabled for dpcd/edid/oui reads.
822 * In such cases we want to leave VDD enabled and it's up to upper layers
823 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
824 * ourselves.
825 */
1e0560e0 826 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 827
828 /* dp aux is extremely sensitive to irq latency, hence request the
829 * lowest possible wakeup latency and so prevent the cpu from going into
830 * deep sleep states.
831 */
832 pm_qos_update_request(&dev_priv->pm_qos, 0);
833
834 intel_dp_check_edp(intel_dp);
5eb08b69 835
c67a470b
PZ		 836 intel_aux_display_runtime_get(dev_priv);
837
11bee43e
JB		 838 /* Try to wait for any previous AUX channel activity */
839 for (try = 0; try < 3; try++) {
ef04f00d 840 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 841 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
842 break;
843 msleep(1);
844 }
845
846 if (try == 3) {
847 WARN(1, "dp_aux_ch not started status 0x%08x\n",
848 I915_READ(ch_ctl));
9ee32fea
DV		 849 ret = -EBUSY;
850 goto out;
4f7f7b7e
CW		 851 }
852
46a5ae9f
PZ		 853 /* Only 5 data registers! */
854 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
855 ret = -E2BIG;
856 goto out;
857 }
858
ec5b01dd 859 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 860 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
861 has_aux_irq,
862 send_bytes,
863 aux_clock_divider);
5ed12a19 864
bc86625a
CW		 865 /* Must try at least 3 times according to DP spec */
866 for (try = 0; try < 5; try++) {
867 /* Load the send data into the aux channel data registers */
868 for (i = 0; i < send_bytes; i += 4)
869 I915_WRITE(ch_data + i,
a4f1289e
RV		 870 intel_dp_pack_aux(send + i,
871 send_bytes - i));
bc86625a
CW		 872
873 /* Send the command and wait for it to complete */
5ed12a19 874 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 875
876 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
877
878 /* Clear done status and any errors */
879 I915_WRITE(ch_ctl,
880 status |
881 DP_AUX_CH_CTL_DONE |
882 DP_AUX_CH_CTL_TIME_OUT_ERROR |
883 DP_AUX_CH_CTL_RECEIVE_ERROR);
884
885 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
886 DP_AUX_CH_CTL_RECEIVE_ERROR))
887 continue;
888 if (status & DP_AUX_CH_CTL_DONE)
889 break;
890 }
4f7f7b7e 891 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 892 break;
893 }
894
a4fc5ed6 895 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 896 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 897 ret = -EBUSY;
898 goto out;
a4fc5ed6
KP		 899 }
900
901 /* Check for timeout or receive error.
902 * Timeouts occur when the sink is not connected
903 */
a5b3da54 904 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 905 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 906 ret = -EIO;
907 goto out;
a5b3da54 908 }
1ae8c0a5
KP		 909
910 /* Timeouts occur when the device isn't connected, so they're
911 * "normal" -- don't fill the kernel log with these */
a5b3da54 912 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 913 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 914 ret = -ETIMEDOUT;
915 goto out;
a4fc5ed6
KP		 916 }
917
918 /* Unload any bytes sent back from the other side */
919 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
920 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 921 if (recv_bytes > recv_size)
922 recv_bytes = recv_size;
0206e353 923
4f7f7b7e 924 for (i = 0; i < recv_bytes; i += 4)
a4f1289e
RV		 925 intel_dp_unpack_aux(I915_READ(ch_data + i),
926 recv + i, recv_bytes - i);
a4fc5ed6 927
9ee32fea
DV		 928 ret = recv_bytes;
929out:
930 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 931 intel_aux_display_runtime_put(dev_priv);
9ee32fea 932
884f19e9
JN		 933 if (vdd)
934 edp_panel_vdd_off(intel_dp, false);
935
773538e8 936 pps_unlock(intel_dp);
e39b999a 937
9ee32fea 938 return ret;
a4fc5ed6
KP		 939}
940
a6c8aff0
JN		 941#define BARE_ADDRESS_SIZE 3
942#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 943static ssize_t
944intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 945{
9d1a1031
JN		 946 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
947 uint8_t txbuf[20], rxbuf[20];
948 size_t txsize, rxsize;
a4fc5ed6 949 int ret;
a4fc5ed6 950
9d1a1031
JN		 951 txbuf[0] = msg->request << 4;
952 txbuf[1] = msg->address >> 8;
953 txbuf[2] = msg->address & 0xff;
954 txbuf[3] = msg->size - 1;
46a5ae9f 955
9d1a1031
JN		 956 switch (msg->request & ~DP_AUX_I2C_MOT) {
957 case DP_AUX_NATIVE_WRITE:
958 case DP_AUX_I2C_WRITE:
a6c8aff0 959 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 960 rxsize = 1;
f51a44b9 961
9d1a1031
JN		 962 if (WARN_ON(txsize > 20))
963 return -E2BIG;
a4fc5ed6 964
9d1a1031 965 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 966
9d1a1031
JN		 967 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
968 if (ret > 0) {
969 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 970
9d1a1031
JN		 971 /* Return payload size. */
972 ret = msg->size;
973 }
974 break;
46a5ae9f 975
9d1a1031
JN		 976 case DP_AUX_NATIVE_READ:
977 case DP_AUX_I2C_READ:
a6c8aff0 978 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 979 rxsize = msg->size + 1;
a4fc5ed6 980
9d1a1031
JN		 981 if (WARN_ON(rxsize > 20))
982 return -E2BIG;
a4fc5ed6 983
9d1a1031
JN		 984 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
985 if (ret > 0) {
986 msg->reply = rxbuf[0] >> 4;
987 /*
988 * Assume happy day, and copy the data. The caller is
989 * expected to check msg->reply before touching it.
990 *
991 * Return payload size.
992 */
993 ret--;
994 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 995 }
9d1a1031
JN		 996 break;
997
998 default:
999 ret = -EINVAL;
1000 break;
a4fc5ed6 1001 }
f51a44b9 1002
9d1a1031 1003 return ret;
a4fc5ed6
KP		 1004}
1005
9d1a1031
JN		 1006static void
1007intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1008{
1009 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 1010 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1011 enum port port = intel_dig_port->port;
0b99836f 1012 const char *name = NULL;
ab2c0672
DA		 1013 int ret;
1014
33ad6626
JN		 1015 switch (port) {
1016 case PORT_A:
1017 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 1018 name = "DPDDC-A";
ab2c0672 1019 break;
33ad6626
JN		 1020 case PORT_B:
1021 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 1022 name = "DPDDC-B";
ab2c0672 1023 break;
33ad6626
JN		 1024 case PORT_C:
1025 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 1026 name = "DPDDC-C";
ab2c0672 1027 break;
33ad6626
JN		 1028 case PORT_D:
1029 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1030 name = "DPDDC-D";
33ad6626
JN		 1031 break;
1032 default:
1033 BUG();
ab2c0672
DA		 1034 }
1035
1b1aad75
DL		 1036 /*
1037 * The AUX_CTL register is usually DP_CTL + 0x10.
1038 *
1039 * On Haswell and Broadwell though:
1040 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1041 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1042 *
1043 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1044 */
1045 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 1046 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1047
0b99836f 1048 intel_dp->aux.name = name;
9d1a1031
JN		 1049 intel_dp->aux.dev = dev->dev;
1050 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1051
0b99836f
JN		 1052 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1053 connector->base.kdev->kobj.name);
8316f337 1054
4f71d0cb 1055 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1056 if (ret < 0) {
4f71d0cb 1057 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1058 name, ret);
1059 return;
ab2c0672 1060 }
8a5e6aeb 1061
0b99836f
JN		 1062 ret = sysfs_create_link(&connector->base.kdev->kobj,
1063 &intel_dp->aux.ddc.dev.kobj,
1064 intel_dp->aux.ddc.dev.kobj.name);
1065 if (ret < 0) {
1066 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1067 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1068 }
a4fc5ed6
KP		 1069}
1070
80f65de3
ID		 1071static void
1072intel_dp_connector_unregister(struct intel_connector *intel_connector)
1073{
1074 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1075
0e32b39c
DA		 1076 if (!intel_connector->mst_port)
1077 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1078 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1079 intel_connector_unregister(intel_connector);
1080}
1081
5416d871 1082static void
5cec258b 1083skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
5416d871
DL		 1084{
1085 u32 ctrl1;
1086
1087 pipe_config->ddi_pll_sel = SKL_DPLL0;
1088 pipe_config->dpll_hw_state.cfgcr1 = 0;
1089 pipe_config->dpll_hw_state.cfgcr2 = 0;
1090
1091 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1092 switch (link_bw) {
1093 case DP_LINK_BW_1_62:
1094 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
1095 SKL_DPLL0);
1096 break;
1097 case DP_LINK_BW_2_7:
1098 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
1099 SKL_DPLL0);
1100 break;
1101 case DP_LINK_BW_5_4:
1102 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
1103 SKL_DPLL0);
1104 break;
1105 }
1106 pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1107}
1108
0e50338c 1109static void
5cec258b 1110hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
0e50338c
DV		 1111{
1112 switch (link_bw) {
1113 case DP_LINK_BW_1_62:
1114 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1115 break;
1116 case DP_LINK_BW_2_7:
1117 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1118 break;
1119 case DP_LINK_BW_5_4:
1120 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1121 break;
1122 }
1123}
1124
fc0f8e25
SJ		 1125static int
1126intel_read_sink_rates(struct intel_dp *intel_dp, uint32_t *sink_rates)
1127{
1128 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1129 int i = 0;
1130 uint16_t val;
1131
1132 if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
1133 /*
1134 * Receiver supports only main-link rate selection by
1135 * link rate table method, so read link rates from
1136 * supported_link_rates
1137 */
1138 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) {
1139 val = le16_to_cpu(intel_dp->supported_rates[i]);
1140 if (val == 0)
1141 break;
1142
1143 sink_rates[i] = val * 200;
1144 }
1145
1146 if (i <= 0)
1147 DRM_ERROR("No rates in SUPPORTED_LINK_RATES");
1148 }
1149 return i;
1150}
1151
a8f3ef61
SJ		 1152static int
1153intel_read_source_rates(struct intel_dp *intel_dp, uint32_t *source_rates)
1154{
1155 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1156 int i;
1157 int max_default_rate;
1158
1159 if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
1160 for (i = 0; i < ARRAY_SIZE(gen9_rates); ++i)
1161 source_rates[i] = gen9_rates[i];
1162 } else {
1163 /* Index of the max_link_bw supported + 1 */
1164 max_default_rate = (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1165 for (i = 0; i < max_default_rate; ++i)
1166 source_rates[i] = default_rates[i];
1167 }
1168 return i;
1169}
1170
c6bb3538
DV		 1171static void
1172intel_dp_set_clock(struct intel_encoder *encoder,
5cec258b 1173 struct intel_crtc_state *pipe_config, int link_bw)
c6bb3538
DV		 1174{
1175 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1176 const struct dp_link_dpll *divisor = NULL;
1177 int i, count = 0;
c6bb3538
DV		 1178
1179 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1180 divisor = gen4_dpll;
1181 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1182 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1183 divisor = pch_dpll;
1184 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1185 } else if (IS_CHERRYVIEW(dev)) {
1186 divisor = chv_dpll;
1187 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1188 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1189 divisor = vlv_dpll;
1190 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1191 }
9dd4ffdf
CML		 1192
1193 if (divisor && count) {
1194 for (i = 0; i < count; i++) {
1195 if (link_bw == divisor[i].link_bw) {
1196 pipe_config->dpll = divisor[i].dpll;
1197 pipe_config->clock_set = true;
1198 break;
1199 }
1200 }
c6bb3538
DV		 1201 }
1202}
1203
a8f3ef61
SJ		 1204static int intel_supported_rates(const uint32_t *source_rates, int source_len,
1205const uint32_t *sink_rates, int sink_len, uint32_t *supported_rates)
1206{
1207 int i = 0, j = 0, k = 0;
1208
1209 /* For panels with edp version less than 1.4 */
1210 if (sink_len == 0) {
1211 for (i = 0; i < source_len; ++i)
1212 supported_rates[i] = source_rates[i];
1213 return source_len;
1214 }
1215
1216 /* For edp1.4 panels, find the common rates between source and sink */
1217 while (i < source_len && j < sink_len) {
1218 if (source_rates[i] == sink_rates[j]) {
1219 supported_rates[k] = source_rates[i];
1220 ++k;
1221 ++i;
1222 ++j;
1223 } else if (source_rates[i] < sink_rates[j]) {
1224 ++i;
1225 } else {
1226 ++j;
1227 }
1228 }
1229 return k;
1230}
1231
1232static int rate_to_index(uint32_t find, const uint32_t *rates)
1233{
1234 int i = 0;
1235
1236 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1237 if (find == rates[i])
1238 break;
1239
1240 return i;
1241}
1242
00c09d70 1243bool
5bfe2ac0 1244intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1245 struct intel_crtc_state *pipe_config)
a4fc5ed6 1246{
5bfe2ac0 1247 struct drm_device *dev = encoder->base.dev;
36008365 1248 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1249 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1250 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1251 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1252 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1253 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1254 int lane_count, clock;
56071a20 1255 int min_lane_count = 1;
eeb6324d 1256 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1257 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1258 int min_clock = 0;
a8f3ef61 1259 int max_clock;
083f9560 1260 int bpp, mode_rate;
ff9a6750 1261 int link_avail, link_clock;
a8f3ef61
SJ		 1262 uint32_t sink_rates[8];
1263 uint32_t supported_rates[8] = {0};
1264 uint32_t source_rates[8];
1265 int source_len, sink_len, supported_len;
1266
1267 sink_len = intel_read_sink_rates(intel_dp, sink_rates);
1268
1269 source_len = intel_read_source_rates(intel_dp, source_rates);
1270
1271 supported_len = intel_supported_rates(source_rates, source_len,
1272 sink_rates, sink_len, supported_rates);
1273
1274 /* No common link rates between source and sink */
1275 WARN_ON(supported_len <= 0);
1276
1277 max_clock = supported_len - 1;
a4fc5ed6 1278
bc7d38a4 1279 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1280 pipe_config->has_pch_encoder = true;
1281
03afc4a2 1282 pipe_config->has_dp_encoder = true;
f769cd24 1283 pipe_config->has_drrs = false;
9ed109a7 1284 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1285
dd06f90e
JN		 1286 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1287 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1288 adjusted_mode);
2dd24552
JB		 1289 if (!HAS_PCH_SPLIT(dev))
1290 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1291 intel_connector->panel.fitting_mode);
1292 else
b074cec8
JB		 1293 intel_pch_panel_fitting(intel_crtc, pipe_config,
1294 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1295 }
1296
cb1793ce 1297 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1298 return false;
1299
083f9560 1300 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61
SJ		 1301 "max bw %d pixel clock %iKHz\n",
1302 max_lane_count, supported_rates[max_clock],
241bfc38 1303 adjusted_mode->crtc_clock);
083f9560 1304
36008365
DV		 1305 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1306 * bpc in between. */
3e7ca985 1307 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1308 if (is_edp(intel_dp)) {
1309 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1310 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1311 dev_priv->vbt.edp_bpp);
1312 bpp = dev_priv->vbt.edp_bpp;
1313 }
1314
344c5bbc
JN		 1315 /*
1316 * Use the maximum clock and number of lanes the eDP panel
1317 * advertizes being capable of. The panels are generally
1318 * designed to support only a single clock and lane
1319 * configuration, and typically these values correspond to the
1320 * native resolution of the panel.
1321 */
1322 min_lane_count = max_lane_count;
1323 min_clock = max_clock;
7984211e 1324 }
657445fe 1325
36008365 1326 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1327 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1328 bpp);
36008365 1329
c6930992 1330 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1331 for (lane_count = min_lane_count;
1332 lane_count <= max_lane_count;
1333 lane_count <<= 1) {
1334
1335 link_clock = supported_rates[clock];
36008365
DV		 1336 link_avail = intel_dp_max_data_rate(link_clock,
1337 lane_count);
1338
1339 if (mode_rate <= link_avail) {
1340 goto found;
1341 }
1342 }
1343 }
1344 }
c4867936 1345
36008365 1346 return false;
3685a8f3 1347
36008365 1348found:
55bc60db
VS		 1349 if (intel_dp->color_range_auto) {
1350 /*
1351 * See:
1352 * CEA-861-E - 5.1 Default Encoding Parameters
1353 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1354 */
18316c8c 1355 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1356 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1357 else
1358 intel_dp->color_range = 0;
1359 }
1360
3685a8f3 1361 if (intel_dp->color_range)
50f3b016 1362 pipe_config->limited_color_range = true;
a4fc5ed6 1363
36008365 1364 intel_dp->lane_count = lane_count;
a8f3ef61
SJ		 1365
1366 intel_dp->link_bw =
1367 drm_dp_link_rate_to_bw_code(supported_rates[clock]);
1368
1369 if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
1370 intel_dp->rate_select =
1371 rate_to_index(supported_rates[clock], sink_rates);
1372 intel_dp->link_bw = 0;
1373 }
1374
657445fe 1375 pipe_config->pipe_bpp = bpp;
a8f3ef61 1376 pipe_config->port_clock = supported_rates[clock];
a4fc5ed6 1377
36008365
DV		 1378 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1379 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1380 pipe_config->port_clock, bpp);
36008365
DV		 1381 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1382 mode_rate, link_avail);
a4fc5ed6 1383
03afc4a2 1384 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1385 adjusted_mode->crtc_clock,
1386 pipe_config->port_clock,
03afc4a2 1387 &pipe_config->dp_m_n);
9d1a455b 1388
439d7ac0 1389 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1390 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1391 pipe_config->has_drrs = true;
439d7ac0
PB		 1392 intel_link_compute_m_n(bpp, lane_count,
1393 intel_connector->panel.downclock_mode->clock,
1394 pipe_config->port_clock,
1395 &pipe_config->dp_m2_n2);
1396 }
1397
5416d871
DL		 1398 if (IS_SKYLAKE(dev) && is_edp(intel_dp))
1399 skl_edp_set_pll_config(pipe_config, intel_dp->link_bw);
1400 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1401 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1402 else
1403 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1404
03afc4a2 1405 return true;
a4fc5ed6
KP		 1406}
1407
7c62a164 1408static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1409{
7c62a164
DV		 1410 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1411 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1412 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1413 struct drm_i915_private *dev_priv = dev->dev_private;
1414 u32 dpa_ctl;
1415
6e3c9717
ACO		 1416 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1417 crtc->config->port_clock);
ea9b6006
DV		 1418 dpa_ctl = I915_READ(DP_A);
1419 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1420
6e3c9717 1421 if (crtc->config->port_clock == 162000) {
1ce17038
DV		 1422 /* For a long time we've carried around a ILK-DevA w/a for the
1423 * 160MHz clock. If we're really unlucky, it's still required.
1424 */
1425 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1426 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1427 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1428 } else {
1429 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1430 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1431 }
1ce17038 1432
ea9b6006
DV		 1433 I915_WRITE(DP_A, dpa_ctl);
1434
1435 POSTING_READ(DP_A);
1436 udelay(500);
1437}
1438
8ac33ed3 1439static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1440{
b934223d 1441 struct drm_device *dev = encoder->base.dev;
417e822d 1442 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1443 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1444 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1445 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
6e3c9717 1446 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1447
417e822d 1448 /*
1a2eb460 1449 * There are four kinds of DP registers:
417e822d
KP		 1450 *
1451 * IBX PCH
1a2eb460
KP		 1452 * SNB CPU
1453 * IVB CPU
417e822d
KP		 1454 * CPT PCH
1455 *
1456 * IBX PCH and CPU are the same for almost everything,
1457 * except that the CPU DP PLL is configured in this
1458 * register
1459 *
1460 * CPT PCH is quite different, having many bits moved
1461 * to the TRANS_DP_CTL register instead. That
1462 * configuration happens (oddly) in ironlake_pch_enable
1463 */
9c9e7927 1464
417e822d
KP		 1465 /* Preserve the BIOS-computed detected bit. This is
1466 * supposed to be read-only.
1467 */
1468 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1469
417e822d 1470 /* Handle DP bits in common between all three register formats */
417e822d 1471 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1472 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1473
6e3c9717 1474 if (crtc->config->has_audio)
ea5b213a 1475 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
247d89f6 1476
417e822d 1477 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1478
bc7d38a4 1479 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1480 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1481 intel_dp->DP |= DP_SYNC_HS_HIGH;
1482 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1483 intel_dp->DP |= DP_SYNC_VS_HIGH;
1484 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1485
6aba5b6c 1486 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1487 intel_dp->DP |= DP_ENHANCED_FRAMING;
1488
7c62a164 1489 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1490 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1491 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1492 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1493
1494 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1495 intel_dp->DP |= DP_SYNC_HS_HIGH;
1496 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1497 intel_dp->DP |= DP_SYNC_VS_HIGH;
1498 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1499
6aba5b6c 1500 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1501 intel_dp->DP |= DP_ENHANCED_FRAMING;
1502
44f37d1f
CML		 1503 if (!IS_CHERRYVIEW(dev)) {
1504 if (crtc->pipe == 1)
1505 intel_dp->DP |= DP_PIPEB_SELECT;
1506 } else {
1507 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1508 }
417e822d
KP		 1509 } else {
1510 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1511 }
a4fc5ed6
KP		 1512}
1513
ffd6749d
PZ		 1514#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1515#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1516
1a5ef5b7
PZ		 1517#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1518#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1519
ffd6749d
PZ		 1520#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1521#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1522
4be73780 1523static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1524 u32 mask,
1525 u32 value)
bd943159 1526{
30add22d 1527 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1528 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1529 u32 pp_stat_reg, pp_ctrl_reg;
1530
e39b999a
VS		 1531 lockdep_assert_held(&dev_priv->pps_mutex);
1532
bf13e81b
JN		 1533 pp_stat_reg = _pp_stat_reg(intel_dp);
1534 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1535
99ea7127 1536 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1537 mask, value,
1538 I915_READ(pp_stat_reg),
1539 I915_READ(pp_ctrl_reg));
32ce697c 1540
453c5420 1541 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1542 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1543 I915_READ(pp_stat_reg),
1544 I915_READ(pp_ctrl_reg));
32ce697c 1545 }
54c136d4
CW		 1546
1547 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1548}
32ce697c 1549
4be73780 1550static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1551{
1552 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1553 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1554}
1555
4be73780 1556static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1557{
1558 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1559 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1560}
1561
4be73780 1562static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1563{
1564 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1565
1566 /* When we disable the VDD override bit last we have to do the manual
1567 * wait. */
1568 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1569 intel_dp->panel_power_cycle_delay);
1570
4be73780 1571 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1572}
1573
4be73780 1574static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1575{
1576 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1577 intel_dp->backlight_on_delay);
1578}
1579
4be73780 1580static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1581{
1582 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1583 intel_dp->backlight_off_delay);
1584}
99ea7127 1585
832dd3c1
KP		 1586/* Read the current pp_control value, unlocking the register if it
1587 * is locked
1588 */
1589
453c5420 1590static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1591{
453c5420
JB		 1592 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1593 struct drm_i915_private *dev_priv = dev->dev_private;
1594 u32 control;
832dd3c1 1595
e39b999a
VS		 1596 lockdep_assert_held(&dev_priv->pps_mutex);
1597
bf13e81b 1598 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1599 control &= ~PANEL_UNLOCK_MASK;
1600 control |= PANEL_UNLOCK_REGS;
1601 return control;
bd943159
KP		 1602}
1603
951468f3
VS		 1604/*
1605 * Must be paired with edp_panel_vdd_off().
1606 * Must hold pps_mutex around the whole on/off sequence.
1607 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1608 */
1e0560e0 1609static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1610{
30add22d 1611 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1612 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1613 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1614 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1615 enum intel_display_power_domain power_domain;
5d613501 1616 u32 pp;
453c5420 1617 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1618 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1619
e39b999a
VS		 1620 lockdep_assert_held(&dev_priv->pps_mutex);
1621
97af61f5 1622 if (!is_edp(intel_dp))
adddaaf4 1623 return false;
bd943159 1624
2c623c11 1625 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1626 intel_dp->want_panel_vdd = true;
99ea7127 1627
4be73780 1628 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1629 return need_to_disable;
b0665d57 1630
4e6e1a54
ID		 1631 power_domain = intel_display_port_power_domain(intel_encoder);
1632 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1633
3936fcf4
VS		 1634 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1635 port_name(intel_dig_port->port));
bd943159 1636
4be73780
DV		 1637 if (!edp_have_panel_power(intel_dp))
1638 wait_panel_power_cycle(intel_dp);
99ea7127 1639
453c5420 1640 pp = ironlake_get_pp_control(intel_dp);
5d613501 1641 pp |= EDP_FORCE_VDD;
ebf33b18 1642
bf13e81b
JN		 1643 pp_stat_reg = _pp_stat_reg(intel_dp);
1644 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1645
1646 I915_WRITE(pp_ctrl_reg, pp);
1647 POSTING_READ(pp_ctrl_reg);
1648 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1649 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1650 /*
1651 * If the panel wasn't on, delay before accessing aux channel
1652 */
4be73780 1653 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1654 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1655 port_name(intel_dig_port->port));
f01eca2e 1656 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1657 }
adddaaf4
JN		 1658
1659 return need_to_disable;
1660}
1661
951468f3
VS		 1662/*
1663 * Must be paired with intel_edp_panel_vdd_off() or
1664 * intel_edp_panel_off().
1665 * Nested calls to these functions are not allowed since
1666 * we drop the lock. Caller must use some higher level
1667 * locking to prevent nested calls from other threads.
1668 */
b80d6c78 1669void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1670{
c695b6b6 1671 bool vdd;
adddaaf4 1672
c695b6b6
VS		 1673 if (!is_edp(intel_dp))
1674 return;
1675
773538e8 1676 pps_lock(intel_dp);
c695b6b6 1677 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1678 pps_unlock(intel_dp);
c695b6b6 1679
e2c719b7 1680 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1681 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1682}
1683
4be73780 1684static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1685{
30add22d 1686 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1687 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1688 struct intel_digital_port *intel_dig_port =
1689 dp_to_dig_port(intel_dp);
1690 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1691 enum intel_display_power_domain power_domain;
5d613501 1692 u32 pp;
453c5420 1693 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1694
e39b999a 1695 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1696
15e899a0 1697 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1698
15e899a0 1699 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1700 return;
b0665d57 1701
3936fcf4
VS		 1702 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1703 port_name(intel_dig_port->port));
bd943159 1704
be2c9196
VS		 1705 pp = ironlake_get_pp_control(intel_dp);
1706 pp &= ~EDP_FORCE_VDD;
453c5420 1707
be2c9196
VS		 1708 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1709 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1710
be2c9196
VS		 1711 I915_WRITE(pp_ctrl_reg, pp);
1712 POSTING_READ(pp_ctrl_reg);
90791a5c 1713
be2c9196
VS		 1714 /* Make sure sequencer is idle before allowing subsequent activity */
1715 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1716 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1717
be2c9196
VS		 1718 if ((pp & POWER_TARGET_ON) == 0)
1719 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1720
be2c9196
VS		 1721 power_domain = intel_display_port_power_domain(intel_encoder);
1722 intel_display_power_put(dev_priv, power_domain);
bd943159 1723}
5d613501 1724
4be73780 1725static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1726{
1727 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1728 struct intel_dp, panel_vdd_work);
bd943159 1729
773538e8 1730 pps_lock(intel_dp);
15e899a0
VS		 1731 if (!intel_dp->want_panel_vdd)
1732 edp_panel_vdd_off_sync(intel_dp);
773538e8 1733 pps_unlock(intel_dp);
bd943159
KP		 1734}
1735
aba86890
ID		 1736static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1737{
1738 unsigned long delay;
1739
1740 /*
1741 * Queue the timer to fire a long time from now (relative to the power
1742 * down delay) to keep the panel power up across a sequence of
1743 * operations.
1744 */
1745 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1746 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1747}
1748
951468f3
VS		 1749/*
1750 * Must be paired with edp_panel_vdd_on().
1751 * Must hold pps_mutex around the whole on/off sequence.
1752 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1753 */
4be73780 1754static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1755{
e39b999a
VS		 1756 struct drm_i915_private *dev_priv =
1757 intel_dp_to_dev(intel_dp)->dev_private;
1758
1759 lockdep_assert_held(&dev_priv->pps_mutex);
1760
97af61f5
KP		 1761 if (!is_edp(intel_dp))
1762 return;
5d613501 1763
e2c719b7 1764 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 1765 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1766
bd943159
KP		 1767 intel_dp->want_panel_vdd = false;
1768
aba86890 1769 if (sync)
4be73780 1770 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1771 else
1772 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1773}
1774
9f0fb5be 1775static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1776{
30add22d 1777 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1778 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1779 u32 pp;
453c5420 1780 u32 pp_ctrl_reg;
9934c132 1781
9f0fb5be
VS		 1782 lockdep_assert_held(&dev_priv->pps_mutex);
1783
97af61f5 1784 if (!is_edp(intel_dp))
bd943159 1785 return;
99ea7127 1786
3936fcf4
VS		 1787 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1788 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 1789
e7a89ace
VS		 1790 if (WARN(edp_have_panel_power(intel_dp),
1791 "eDP port %c panel power already on\n",
1792 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1793 return;
9934c132 1794
4be73780 1795 wait_panel_power_cycle(intel_dp);
37c6c9b0 1796
bf13e81b 1797 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1798 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1799 if (IS_GEN5(dev)) {
1800 /* ILK workaround: disable reset around power sequence */
1801 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1802 I915_WRITE(pp_ctrl_reg, pp);
1803 POSTING_READ(pp_ctrl_reg);
05ce1a49 1804 }
37c6c9b0 1805
1c0ae80a 1806 pp |= POWER_TARGET_ON;
99ea7127
KP		 1807 if (!IS_GEN5(dev))
1808 pp |= PANEL_POWER_RESET;
1809
453c5420
JB		 1810 I915_WRITE(pp_ctrl_reg, pp);
1811 POSTING_READ(pp_ctrl_reg);
9934c132 1812
4be73780 1813 wait_panel_on(intel_dp);
dce56b3c 1814 intel_dp->last_power_on = jiffies;
9934c132 1815
05ce1a49
KP		 1816 if (IS_GEN5(dev)) {
1817 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1818 I915_WRITE(pp_ctrl_reg, pp);
1819 POSTING_READ(pp_ctrl_reg);
05ce1a49 1820 }
9f0fb5be 1821}
e39b999a 1822
9f0fb5be
VS		 1823void intel_edp_panel_on(struct intel_dp *intel_dp)
1824{
1825 if (!is_edp(intel_dp))
1826 return;
1827
1828 pps_lock(intel_dp);
1829 edp_panel_on(intel_dp);
773538e8 1830 pps_unlock(intel_dp);
9934c132
JB		 1831}
1832
9f0fb5be
VS		 1833
1834static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1835{
4e6e1a54
ID		 1836 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1837 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1838 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1839 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1840 enum intel_display_power_domain power_domain;
99ea7127 1841 u32 pp;
453c5420 1842 u32 pp_ctrl_reg;
9934c132 1843
9f0fb5be
VS		 1844 lockdep_assert_held(&dev_priv->pps_mutex);
1845
97af61f5
KP		 1846 if (!is_edp(intel_dp))
1847 return;
37c6c9b0 1848
3936fcf4
VS		 1849 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1850 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 1851
3936fcf4
VS		 1852 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1853 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 1854
453c5420 1855 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1856 /* We need to switch off panel power _and_ force vdd, for otherwise some
1857 * panels get very unhappy and cease to work. */
b3064154
PJ		 1858 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1859 EDP_BLC_ENABLE);
453c5420 1860
bf13e81b 1861 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1862
849e39f5
PZ		 1863 intel_dp->want_panel_vdd = false;
1864
453c5420
JB		 1865 I915_WRITE(pp_ctrl_reg, pp);
1866 POSTING_READ(pp_ctrl_reg);
9934c132 1867
dce56b3c 1868 intel_dp->last_power_cycle = jiffies;
4be73780 1869 wait_panel_off(intel_dp);
849e39f5
PZ		 1870
1871 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1872 power_domain = intel_display_port_power_domain(intel_encoder);
1873 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1874}
e39b999a 1875
9f0fb5be
VS		 1876void intel_edp_panel_off(struct intel_dp *intel_dp)
1877{
1878 if (!is_edp(intel_dp))
1879 return;
e39b999a 1880
9f0fb5be
VS		 1881 pps_lock(intel_dp);
1882 edp_panel_off(intel_dp);
773538e8 1883 pps_unlock(intel_dp);
9934c132
JB		 1884}
1885
1250d107
JN		 1886/* Enable backlight in the panel power control. */
1887static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1888{
da63a9f2
PZ		 1889 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1890 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1891 struct drm_i915_private *dev_priv = dev->dev_private;
1892 u32 pp;
453c5420 1893 u32 pp_ctrl_reg;
32f9d658 1894
01cb9ea6
JB		 1895 /*
1896 * If we enable the backlight right away following a panel power
1897 * on, we may see slight flicker as the panel syncs with the eDP
1898 * link. So delay a bit to make sure the image is solid before
1899 * allowing it to appear.
1900 */
4be73780 1901 wait_backlight_on(intel_dp);
e39b999a 1902
773538e8 1903 pps_lock(intel_dp);
e39b999a 1904
453c5420 1905 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1906 pp |= EDP_BLC_ENABLE;
453c5420 1907
bf13e81b 1908 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1909
1910 I915_WRITE(pp_ctrl_reg, pp);
1911 POSTING_READ(pp_ctrl_reg);
e39b999a 1912
773538e8 1913 pps_unlock(intel_dp);
32f9d658
ZW		 1914}
1915
1250d107
JN		 1916/* Enable backlight PWM and backlight PP control. */
1917void intel_edp_backlight_on(struct intel_dp *intel_dp)
1918{
1919 if (!is_edp(intel_dp))
1920 return;
1921
1922 DRM_DEBUG_KMS("\n");
1923
1924 intel_panel_enable_backlight(intel_dp->attached_connector);
1925 _intel_edp_backlight_on(intel_dp);
1926}
1927
1928/* Disable backlight in the panel power control. */
1929static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1930{
30add22d 1931 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1932 struct drm_i915_private *dev_priv = dev->dev_private;
1933 u32 pp;
453c5420 1934 u32 pp_ctrl_reg;
32f9d658 1935
f01eca2e
KP		 1936 if (!is_edp(intel_dp))
1937 return;
1938
773538e8 1939 pps_lock(intel_dp);
e39b999a 1940
453c5420 1941 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1942 pp &= ~EDP_BLC_ENABLE;
453c5420 1943
bf13e81b 1944 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1945
1946 I915_WRITE(pp_ctrl_reg, pp);
1947 POSTING_READ(pp_ctrl_reg);
f7d2323c 1948
773538e8 1949 pps_unlock(intel_dp);
e39b999a
VS		 1950
1951 intel_dp->last_backlight_off = jiffies;
f7d2323c 1952 edp_wait_backlight_off(intel_dp);
1250d107 1953}
f7d2323c 1954
1250d107
JN		 1955/* Disable backlight PP control and backlight PWM. */
1956void intel_edp_backlight_off(struct intel_dp *intel_dp)
1957{
1958 if (!is_edp(intel_dp))
1959 return;
1960
1961 DRM_DEBUG_KMS("\n");
f7d2323c 1962
1250d107 1963 _intel_edp_backlight_off(intel_dp);
f7d2323c 1964 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1965}
a4fc5ed6 1966
73580fb7
JN		 1967/*
1968 * Hook for controlling the panel power control backlight through the bl_power
1969 * sysfs attribute. Take care to handle multiple calls.
1970 */
1971static void intel_edp_backlight_power(struct intel_connector *connector,
1972 bool enable)
1973{
1974 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1975 bool is_enabled;
1976
773538e8 1977 pps_lock(intel_dp);
e39b999a 1978 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1979 pps_unlock(intel_dp);
73580fb7
JN		 1980
1981 if (is_enabled == enable)
1982 return;
1983
23ba9373
JN		 1984 DRM_DEBUG_KMS("panel power control backlight %s\n",
1985 enable ? "enable" : "disable");
73580fb7
JN		 1986
1987 if (enable)
1988 _intel_edp_backlight_on(intel_dp);
1989 else
1990 _intel_edp_backlight_off(intel_dp);
1991}
1992
2bd2ad64 1993static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1994{
da63a9f2
PZ		 1995 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1996 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1997 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 u32 dpa_ctl;
2000
2bd2ad64
DV		 2001 assert_pipe_disabled(dev_priv,
2002 to_intel_crtc(crtc)->pipe);
2003
d240f20f
JB		 2004 DRM_DEBUG_KMS("\n");
2005 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 2006 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
2007 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2008
2009 /* We don't adjust intel_dp->DP while tearing down the link, to
2010 * facilitate link retraining (e.g. after hotplug). Hence clear all
2011 * enable bits here to ensure that we don't enable too much. */
2012 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
2013 intel_dp->DP |= DP_PLL_ENABLE;
2014 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2015 POSTING_READ(DP_A);
2016 udelay(200);
d240f20f
JB		 2017}
2018
2bd2ad64 2019static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2020{
da63a9f2
PZ		 2021 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2022 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2023 struct drm_device *dev = crtc->dev;
d240f20f
JB		 2024 struct drm_i915_private *dev_priv = dev->dev_private;
2025 u32 dpa_ctl;
2026
2bd2ad64
DV		 2027 assert_pipe_disabled(dev_priv,
2028 to_intel_crtc(crtc)->pipe);
2029
d240f20f 2030 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 2031 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
2032 "dp pll off, should be on\n");
2033 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2034
2035 /* We can't rely on the value tracked for the DP register in
2036 * intel_dp->DP because link_down must not change that (otherwise link
2037 * re-training will fail. */
298b0b39 2038 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 2039 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 2040 POSTING_READ(DP_A);
d240f20f
JB		 2041 udelay(200);
2042}
2043
c7ad3810 2044/* If the sink supports it, try to set the power state appropriately */
c19b0669 2045void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2046{
2047 int ret, i;
2048
2049 /* Should have a valid DPCD by this point */
2050 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2051 return;
2052
2053 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2054 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2055 DP_SET_POWER_D3);
c7ad3810
JB		 2056 } else {
2057 /*
2058 * When turning on, we need to retry for 1ms to give the sink
2059 * time to wake up.
2060 */
2061 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2062 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2063 DP_SET_POWER_D0);
c7ad3810
JB		 2064 if (ret == 1)
2065 break;
2066 msleep(1);
2067 }
2068 }
f9cac721
JN		 2069
2070 if (ret != 1)
2071 DRM_DEBUG_KMS("failed to %s sink power state\n",
2072 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2073}
2074
19d8fe15
DV		 2075static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2076 enum pipe *pipe)
d240f20f 2077{
19d8fe15 2078 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2079 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 2080 struct drm_device *dev = encoder->base.dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 2082 enum intel_display_power_domain power_domain;
2083 u32 tmp;
2084
2085 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 2086 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 2087 return false;
2088
2089 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2090
2091 if (!(tmp & DP_PORT_EN))
2092 return false;
2093
bc7d38a4 2094 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 2095 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 2096 } else if (IS_CHERRYVIEW(dev)) {
2097 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 2098 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 2099 *pipe = PORT_TO_PIPE(tmp);
2100 } else {
2101 u32 trans_sel;
2102 u32 trans_dp;
2103 int i;
2104
2105 switch (intel_dp->output_reg) {
2106 case PCH_DP_B:
2107 trans_sel = TRANS_DP_PORT_SEL_B;
2108 break;
2109 case PCH_DP_C:
2110 trans_sel = TRANS_DP_PORT_SEL_C;
2111 break;
2112 case PCH_DP_D:
2113 trans_sel = TRANS_DP_PORT_SEL_D;
2114 break;
2115 default:
2116 return true;
2117 }
2118
055e393f 2119 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 2120 trans_dp = I915_READ(TRANS_DP_CTL(i));
2121 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
2122 *pipe = i;
2123 return true;
2124 }
2125 }
19d8fe15 2126
4a0833ec
DV		 2127 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2128 intel_dp->output_reg);
2129 }
d240f20f 2130
19d8fe15
DV		 2131 return true;
2132}
d240f20f 2133
045ac3b5 2134static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2135 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2136{
2137 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2138 u32 tmp, flags = 0;
63000ef6
XZ		 2139 struct drm_device *dev = encoder->base.dev;
2140 struct drm_i915_private *dev_priv = dev->dev_private;
2141 enum port port = dp_to_dig_port(intel_dp)->port;
2142 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 2143 int dotclock;
045ac3b5 2144
9ed109a7
DV		 2145 tmp = I915_READ(intel_dp->output_reg);
2146 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
2147 pipe_config->has_audio = true;
2148
63000ef6 2149 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 2150 if (tmp & DP_SYNC_HS_HIGH)
2151 flags |= DRM_MODE_FLAG_PHSYNC;
2152 else
2153 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2154
63000ef6
XZ		 2155 if (tmp & DP_SYNC_VS_HIGH)
2156 flags |= DRM_MODE_FLAG_PVSYNC;
2157 else
2158 flags |= DRM_MODE_FLAG_NVSYNC;
2159 } else {
2160 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2161 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2162 flags |= DRM_MODE_FLAG_PHSYNC;
2163 else
2164 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2165
63000ef6
XZ		 2166 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2167 flags |= DRM_MODE_FLAG_PVSYNC;
2168 else
2169 flags |= DRM_MODE_FLAG_NVSYNC;
2170 }
045ac3b5 2171
2d112de7 2172 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2173
8c875fca
VS		 2174 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2175 tmp & DP_COLOR_RANGE_16_235)
2176 pipe_config->limited_color_range = true;
2177
eb14cb74
VS		 2178 pipe_config->has_dp_encoder = true;
2179
2180 intel_dp_get_m_n(crtc, pipe_config);
2181
18442d08 2182 if (port == PORT_A) {
f1f644dc
JB		 2183 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2184 pipe_config->port_clock = 162000;
2185 else
2186 pipe_config->port_clock = 270000;
2187 }
18442d08
VS		 2188
2189 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2190 &pipe_config->dp_m_n);
2191
2192 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2193 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2194
2d112de7 2195 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2196
c6cd2ee2
JN		 2197 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2198 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2199 /*
2200 * This is a big fat ugly hack.
2201 *
2202 * Some machines in UEFI boot mode provide us a VBT that has 18
2203 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2204 * unknown we fail to light up. Yet the same BIOS boots up with
2205 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2206 * max, not what it tells us to use.
2207 *
2208 * Note: This will still be broken if the eDP panel is not lit
2209 * up by the BIOS, and thus we can't get the mode at module
2210 * load.
2211 */
2212 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2213 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2214 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2215 }
045ac3b5
JB		 2216}
2217
e8cb4558 2218static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2219{
e8cb4558 2220 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2221 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2222 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2223
6e3c9717 2224 if (crtc->config->has_audio)
495a5bb8 2225 intel_audio_codec_disable(encoder);
6cb49835 2226
b32c6f48
RV		 2227 if (HAS_PSR(dev) && !HAS_DDI(dev))
2228 intel_psr_disable(intel_dp);
2229
6cb49835
DV		 2230 /* Make sure the panel is off before trying to change the mode. But also
2231 * ensure that we have vdd while we switch off the panel. */
24f3e092 2232 intel_edp_panel_vdd_on(intel_dp);
4be73780 2233 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2234 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2235 intel_edp_panel_off(intel_dp);
3739850b 2236
08aff3fe
VS		 2237 /* disable the port before the pipe on g4x */
2238 if (INTEL_INFO(dev)->gen < 5)
3739850b 2239 intel_dp_link_down(intel_dp);
d240f20f
JB		 2240}
2241
08aff3fe 2242static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2243{
2bd2ad64 2244 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2245 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2246
49277c31 2247 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2248 if (port == PORT_A)
2249 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2250}
2251
2252static void vlv_post_disable_dp(struct intel_encoder *encoder)
2253{
2254 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2255
2256 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2257}
2258
580d3811
VS		 2259static void chv_post_disable_dp(struct intel_encoder *encoder)
2260{
2261 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2262 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2263 struct drm_device *dev = encoder->base.dev;
2264 struct drm_i915_private *dev_priv = dev->dev_private;
2265 struct intel_crtc *intel_crtc =
2266 to_intel_crtc(encoder->base.crtc);
2267 enum dpio_channel ch = vlv_dport_to_channel(dport);
2268 enum pipe pipe = intel_crtc->pipe;
2269 u32 val;
2270
2271 intel_dp_link_down(intel_dp);
2272
2273 mutex_lock(&dev_priv->dpio_lock);
2274
2275 /* Propagate soft reset to data lane reset */
97fd4d5c 2276 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2277 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2278 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2279
97fd4d5c
VS		 2280 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2281 val |= CHV_PCS_REQ_SOFTRESET_EN;
2282 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2283
2284 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2285 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2286 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2287
2288 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2289 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2290 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2291
2292 mutex_unlock(&dev_priv->dpio_lock);
2293}
2294
7b13b58a
VS		 2295static void
2296_intel_dp_set_link_train(struct intel_dp *intel_dp,
2297 uint32_t *DP,
2298 uint8_t dp_train_pat)
2299{
2300 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2301 struct drm_device *dev = intel_dig_port->base.base.dev;
2302 struct drm_i915_private *dev_priv = dev->dev_private;
2303 enum port port = intel_dig_port->port;
2304
2305 if (HAS_DDI(dev)) {
2306 uint32_t temp = I915_READ(DP_TP_CTL(port));
2307
2308 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2309 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2310 else
2311 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2312
2313 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2314 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2315 case DP_TRAINING_PATTERN_DISABLE:
2316 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2317
2318 break;
2319 case DP_TRAINING_PATTERN_1:
2320 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2321 break;
2322 case DP_TRAINING_PATTERN_2:
2323 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2324 break;
2325 case DP_TRAINING_PATTERN_3:
2326 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2327 break;
2328 }
2329 I915_WRITE(DP_TP_CTL(port), temp);
2330
2331 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2332 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2333
2334 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2335 case DP_TRAINING_PATTERN_DISABLE:
2336 *DP |= DP_LINK_TRAIN_OFF_CPT;
2337 break;
2338 case DP_TRAINING_PATTERN_1:
2339 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2340 break;
2341 case DP_TRAINING_PATTERN_2:
2342 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2343 break;
2344 case DP_TRAINING_PATTERN_3:
2345 DRM_ERROR("DP training pattern 3 not supported\n");
2346 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2347 break;
2348 }
2349
2350 } else {
2351 if (IS_CHERRYVIEW(dev))
2352 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2353 else
2354 *DP &= ~DP_LINK_TRAIN_MASK;
2355
2356 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2357 case DP_TRAINING_PATTERN_DISABLE:
2358 *DP |= DP_LINK_TRAIN_OFF;
2359 break;
2360 case DP_TRAINING_PATTERN_1:
2361 *DP |= DP_LINK_TRAIN_PAT_1;
2362 break;
2363 case DP_TRAINING_PATTERN_2:
2364 *DP |= DP_LINK_TRAIN_PAT_2;
2365 break;
2366 case DP_TRAINING_PATTERN_3:
2367 if (IS_CHERRYVIEW(dev)) {
2368 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2369 } else {
2370 DRM_ERROR("DP training pattern 3 not supported\n");
2371 *DP |= DP_LINK_TRAIN_PAT_2;
2372 }
2373 break;
2374 }
2375 }
2376}
2377
2378static void intel_dp_enable_port(struct intel_dp *intel_dp)
2379{
2380 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2381 struct drm_i915_private *dev_priv = dev->dev_private;
2382
7b13b58a
VS		 2383 /* enable with pattern 1 (as per spec) */
2384 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2385 DP_TRAINING_PATTERN_1);
2386
2387 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2388 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2389
2390 /*
2391 * Magic for VLV/CHV. We _must_ first set up the register
2392 * without actually enabling the port, and then do another
2393 * write to enable the port. Otherwise link training will
2394 * fail when the power sequencer is freshly used for this port.
2395 */
2396 intel_dp->DP |= DP_PORT_EN;
2397
2398 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2399 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2400}
2401
e8cb4558 2402static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2403{
e8cb4558
DV		 2404 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2405 struct drm_device *dev = encoder->base.dev;
2406 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2407 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2408 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2409
0c33d8d7
DV		 2410 if (WARN_ON(dp_reg & DP_PORT_EN))
2411 return;
5d613501 2412
093e3f13
VS		 2413 pps_lock(intel_dp);
2414
2415 if (IS_VALLEYVIEW(dev))
2416 vlv_init_panel_power_sequencer(intel_dp);
2417
7b13b58a 2418 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2419
2420 edp_panel_vdd_on(intel_dp);
2421 edp_panel_on(intel_dp);
2422 edp_panel_vdd_off(intel_dp, true);
2423
2424 pps_unlock(intel_dp);
2425
61234fa5
VS		 2426 if (IS_VALLEYVIEW(dev))
2427 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2428
f01eca2e 2429 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2430 intel_dp_start_link_train(intel_dp);
33a34e4e 2431 intel_dp_complete_link_train(intel_dp);
3ab9c637 2432 intel_dp_stop_link_train(intel_dp);
c1dec79a 2433
6e3c9717 2434 if (crtc->config->has_audio) {
c1dec79a
JN		 2435 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2436 pipe_name(crtc->pipe));
2437 intel_audio_codec_enable(encoder);
2438 }
ab1f90f9 2439}
89b667f8 2440
ecff4f3b
JN		 2441static void g4x_enable_dp(struct intel_encoder *encoder)
2442{
828f5c6e
JN		 2443 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2444
ecff4f3b 2445 intel_enable_dp(encoder);
4be73780 2446 intel_edp_backlight_on(intel_dp);
ab1f90f9 2447}
89b667f8 2448
ab1f90f9
JN		 2449static void vlv_enable_dp(struct intel_encoder *encoder)
2450{
828f5c6e
JN		 2451 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2452
4be73780 2453 intel_edp_backlight_on(intel_dp);
b32c6f48 2454 intel_psr_enable(intel_dp);
d240f20f
JB		 2455}
2456
ecff4f3b 2457static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2458{
2459 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2460 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2461
8ac33ed3
DV		 2462 intel_dp_prepare(encoder);
2463
d41f1efb
DV		 2464 /* Only ilk+ has port A */
2465 if (dport->port == PORT_A) {
2466 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2467 ironlake_edp_pll_on(intel_dp);
d41f1efb 2468 }
ab1f90f9
JN		 2469}
2470
83b84597
VS		 2471static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2472{
2473 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2474 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2475 enum pipe pipe = intel_dp->pps_pipe;
2476 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2477
2478 edp_panel_vdd_off_sync(intel_dp);
2479
2480 /*
2481 * VLV seems to get confused when multiple power seqeuencers
2482 * have the same port selected (even if only one has power/vdd
2483 * enabled). The failure manifests as vlv_wait_port_ready() failing
2484 * CHV on the other hand doesn't seem to mind having the same port
2485 * selected in multiple power seqeuencers, but let's clear the
2486 * port select always when logically disconnecting a power sequencer
2487 * from a port.
2488 */
2489 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2490 pipe_name(pipe), port_name(intel_dig_port->port));
2491 I915_WRITE(pp_on_reg, 0);
2492 POSTING_READ(pp_on_reg);
2493
2494 intel_dp->pps_pipe = INVALID_PIPE;
2495}
2496
a4a5d2f8
VS		 2497static void vlv_steal_power_sequencer(struct drm_device *dev,
2498 enum pipe pipe)
2499{
2500 struct drm_i915_private *dev_priv = dev->dev_private;
2501 struct intel_encoder *encoder;
2502
2503 lockdep_assert_held(&dev_priv->pps_mutex);
2504
ac3c12e4
VS		 2505 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2506 return;
2507
a4a5d2f8
VS		 2508 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2509 base.head) {
2510 struct intel_dp *intel_dp;
773538e8 2511 enum port port;
a4a5d2f8
VS		 2512
2513 if (encoder->type != INTEL_OUTPUT_EDP)
2514 continue;
2515
2516 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2517 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2518
2519 if (intel_dp->pps_pipe != pipe)
2520 continue;
2521
2522 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2523 pipe_name(pipe), port_name(port));
a4a5d2f8 2524
034e43c6
VS		 2525 WARN(encoder->connectors_active,
2526 "stealing pipe %c power sequencer from active eDP port %c\n",
2527 pipe_name(pipe), port_name(port));
a4a5d2f8 2528
a4a5d2f8 2529 /* make sure vdd is off before we steal it */
83b84597 2530 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2531 }
2532}
2533
2534static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2535{
2536 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2537 struct intel_encoder *encoder = &intel_dig_port->base;
2538 struct drm_device *dev = encoder->base.dev;
2539 struct drm_i915_private *dev_priv = dev->dev_private;
2540 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2541
2542 lockdep_assert_held(&dev_priv->pps_mutex);
2543
093e3f13
VS		 2544 if (!is_edp(intel_dp))
2545 return;
2546
a4a5d2f8
VS		 2547 if (intel_dp->pps_pipe == crtc->pipe)
2548 return;
2549
2550 /*
2551 * If another power sequencer was being used on this
2552 * port previously make sure to turn off vdd there while
2553 * we still have control of it.
2554 */
2555 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2556 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2557
2558 /*
2559 * We may be stealing the power
2560 * sequencer from another port.
2561 */
2562 vlv_steal_power_sequencer(dev, crtc->pipe);
2563
2564 /* now it's all ours */
2565 intel_dp->pps_pipe = crtc->pipe;
2566
2567 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2568 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2569
2570 /* init power sequencer on this pipe and port */
36b5f425
VS		 2571 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2572 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2573}
2574
ab1f90f9 2575static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2576{
2bd2ad64 2577 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2578 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2579 struct drm_device *dev = encoder->base.dev;
89b667f8 2580 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2581 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2582 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2583 int pipe = intel_crtc->pipe;
2584 u32 val;
a4fc5ed6 2585
ab1f90f9 2586 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2587
ab3c759a 2588 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2589 val = 0;
2590 if (pipe)
2591 val |= (1<<21);
2592 else
2593 val &= ~(1<<21);
2594 val |= 0x001000c4;
ab3c759a
CML		 2595 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2596 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2597 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2598
ab1f90f9
JN		 2599 mutex_unlock(&dev_priv->dpio_lock);
2600
2601 intel_enable_dp(encoder);
89b667f8
JB		 2602}
2603
ecff4f3b 2604static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2605{
2606 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2607 struct drm_device *dev = encoder->base.dev;
2608 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2609 struct intel_crtc *intel_crtc =
2610 to_intel_crtc(encoder->base.crtc);
e4607fcf 2611 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2612 int pipe = intel_crtc->pipe;
89b667f8 2613
8ac33ed3
DV		 2614 intel_dp_prepare(encoder);
2615
89b667f8 2616 /* Program Tx lane resets to default */
0980a60f 2617 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2618 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2619 DPIO_PCS_TX_LANE2_RESET |
2620 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2621 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2622 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2623 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2624 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2625 DPIO_PCS_CLK_SOFT_RESET);
2626
2627 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2628 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2629 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2630 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2631 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2632}
2633
e4a1d846
CML		 2634static void chv_pre_enable_dp(struct intel_encoder *encoder)
2635{
2636 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2637 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2638 struct drm_device *dev = encoder->base.dev;
2639 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2640 struct intel_crtc *intel_crtc =
2641 to_intel_crtc(encoder->base.crtc);
2642 enum dpio_channel ch = vlv_dport_to_channel(dport);
2643 int pipe = intel_crtc->pipe;
2644 int data, i;
949c1d43 2645 u32 val;
e4a1d846 2646
e4a1d846 2647 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2648
570e2a74
VS		 2649 /* allow hardware to manage TX FIFO reset source */
2650 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2651 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2652 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2653
2654 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2655 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2656 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2657
949c1d43 2658 /* Deassert soft data lane reset*/
97fd4d5c 2659 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2660 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2661 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2662
2663 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2664 val |= CHV_PCS_REQ_SOFTRESET_EN;
2665 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2666
2667 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2668 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2669 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2670
97fd4d5c 2671 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2672 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2673 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2674
2675 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2676 for (i = 0; i < 4; i++) {
2677 /* Set the latency optimal bit */
2678 data = (i == 1) ? 0x0 : 0x6;
2679 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2680 data << DPIO_FRC_LATENCY_SHFIT);
2681
2682 /* Set the upar bit */
2683 data = (i == 1) ? 0x0 : 0x1;
2684 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2685 data << DPIO_UPAR_SHIFT);
2686 }
2687
2688 /* Data lane stagger programming */
2689 /* FIXME: Fix up value only after power analysis */
2690
2691 mutex_unlock(&dev_priv->dpio_lock);
2692
e4a1d846 2693 intel_enable_dp(encoder);
e4a1d846
CML		 2694}
2695
9197c88b
VS		 2696static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2697{
2698 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2699 struct drm_device *dev = encoder->base.dev;
2700 struct drm_i915_private *dev_priv = dev->dev_private;
2701 struct intel_crtc *intel_crtc =
2702 to_intel_crtc(encoder->base.crtc);
2703 enum dpio_channel ch = vlv_dport_to_channel(dport);
2704 enum pipe pipe = intel_crtc->pipe;
2705 u32 val;
2706
625695f8
VS		 2707 intel_dp_prepare(encoder);
2708
9197c88b
VS		 2709 mutex_lock(&dev_priv->dpio_lock);
2710
b9e5ac3c
VS		 2711 /* program left/right clock distribution */
2712 if (pipe != PIPE_B) {
2713 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2714 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2715 if (ch == DPIO_CH0)
2716 val |= CHV_BUFLEFTENA1_FORCE;
2717 if (ch == DPIO_CH1)
2718 val |= CHV_BUFRIGHTENA1_FORCE;
2719 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2720 } else {
2721 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2722 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2723 if (ch == DPIO_CH0)
2724 val |= CHV_BUFLEFTENA2_FORCE;
2725 if (ch == DPIO_CH1)
2726 val |= CHV_BUFRIGHTENA2_FORCE;
2727 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2728 }
2729
9197c88b
VS		 2730 /* program clock channel usage */
2731 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2732 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2733 if (pipe != PIPE_B)
2734 val &= ~CHV_PCS_USEDCLKCHANNEL;
2735 else
2736 val |= CHV_PCS_USEDCLKCHANNEL;
2737 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2738
2739 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2740 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2741 if (pipe != PIPE_B)
2742 val &= ~CHV_PCS_USEDCLKCHANNEL;
2743 else
2744 val |= CHV_PCS_USEDCLKCHANNEL;
2745 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2746
2747 /*
2748 * This a a bit weird since generally CL
2749 * matches the pipe, but here we need to
2750 * pick the CL based on the port.
2751 */
2752 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2753 if (pipe != PIPE_B)
2754 val &= ~CHV_CMN_USEDCLKCHANNEL;
2755 else
2756 val |= CHV_CMN_USEDCLKCHANNEL;
2757 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2758
2759 mutex_unlock(&dev_priv->dpio_lock);
2760}
2761
a4fc5ed6 2762/*
df0c237d
JB		 2763 * Native read with retry for link status and receiver capability reads for
2764 * cases where the sink may still be asleep.
9d1a1031
JN		 2765 *
2766 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2767 * supposed to retry 3 times per the spec.
a4fc5ed6 2768 */
9d1a1031
JN		 2769static ssize_t
2770intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2771 void *buffer, size_t size)
a4fc5ed6 2772{
9d1a1031
JN		 2773 ssize_t ret;
2774 int i;
61da5fab 2775
f6a19066
VS		 2776 /*
2777 * Sometime we just get the same incorrect byte repeated
2778 * over the entire buffer. Doing just one throw away read
2779 * initially seems to "solve" it.
2780 */
2781 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2782
61da5fab 2783 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2784 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2785 if (ret == size)
2786 return ret;
61da5fab
JB		 2787 msleep(1);
2788 }
a4fc5ed6 2789
9d1a1031 2790 return ret;
a4fc5ed6
KP		 2791}
2792
2793/*
2794 * Fetch AUX CH registers 0x202 - 0x207 which contain
2795 * link status information
2796 */
2797static bool
93f62dad 2798intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2799{
9d1a1031
JN		 2800 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2801 DP_LANE0_1_STATUS,
2802 link_status,
2803 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2804}
2805
1100244e 2806/* These are source-specific values. */
a4fc5ed6 2807static uint8_t
1a2eb460 2808intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2809{
30add22d 2810 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 2811 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 2812 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2813
7ad14a29
SJ		 2814 if (INTEL_INFO(dev)->gen >= 9) {
2815 if (dev_priv->vbt.edp_low_vswing && port == PORT_A)
2816 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2817 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
7ad14a29 2818 } else if (IS_VALLEYVIEW(dev))
bd60018a 2819 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2820 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2821 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2822 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2823 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2824 else
bd60018a 2825 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2826}
2827
2828static uint8_t
2829intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2830{
30add22d 2831 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2832 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2833
5a9d1f1a
DL		 2834 if (INTEL_INFO(dev)->gen >= 9) {
2835 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2836 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2837 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2838 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2839 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2840 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2841 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 2842 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2843 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 2844 default:
2845 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2846 }
2847 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2848 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2849 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2850 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2851 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2852 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2853 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2854 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2855 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2856 default:
bd60018a 2857 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2858 }
e2fa6fba
P		 2859 } else if (IS_VALLEYVIEW(dev)) {
2860 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2861 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2862 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2863 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2864 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2865 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2866 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2867 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2868 default:
bd60018a 2869 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2870 }
bc7d38a4 2871 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2872 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2873 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2874 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2875 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2876 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2877 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2878 default:
bd60018a 2879 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2880 }
2881 } else {
2882 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2883 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2884 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2885 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2886 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2887 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2888 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2889 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2890 default:
bd60018a 2891 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2892 }
a4fc5ed6
KP		 2893 }
2894}
2895
e2fa6fba
P		 2896static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2897{
2898 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2899 struct drm_i915_private *dev_priv = dev->dev_private;
2900 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2901 struct intel_crtc *intel_crtc =
2902 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2903 unsigned long demph_reg_value, preemph_reg_value,
2904 uniqtranscale_reg_value;
2905 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2906 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2907 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2908
2909 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2910 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2911 preemph_reg_value = 0x0004000;
2912 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2913 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2914 demph_reg_value = 0x2B405555;
2915 uniqtranscale_reg_value = 0x552AB83A;
2916 break;
bd60018a 2917 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2918 demph_reg_value = 0x2B404040;
2919 uniqtranscale_reg_value = 0x5548B83A;
2920 break;
bd60018a 2921 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2922 demph_reg_value = 0x2B245555;
2923 uniqtranscale_reg_value = 0x5560B83A;
2924 break;
bd60018a 2925 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2926 demph_reg_value = 0x2B405555;
2927 uniqtranscale_reg_value = 0x5598DA3A;
2928 break;
2929 default:
2930 return 0;
2931 }
2932 break;
bd60018a 2933 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2934 preemph_reg_value = 0x0002000;
2935 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2936 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2937 demph_reg_value = 0x2B404040;
2938 uniqtranscale_reg_value = 0x5552B83A;
2939 break;
bd60018a 2940 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2941 demph_reg_value = 0x2B404848;
2942 uniqtranscale_reg_value = 0x5580B83A;
2943 break;
bd60018a 2944 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2945 demph_reg_value = 0x2B404040;
2946 uniqtranscale_reg_value = 0x55ADDA3A;
2947 break;
2948 default:
2949 return 0;
2950 }
2951 break;
bd60018a 2952 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 2953 preemph_reg_value = 0x0000000;
2954 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2955 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2956 demph_reg_value = 0x2B305555;
2957 uniqtranscale_reg_value = 0x5570B83A;
2958 break;
bd60018a 2959 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2960 demph_reg_value = 0x2B2B4040;
2961 uniqtranscale_reg_value = 0x55ADDA3A;
2962 break;
2963 default:
2964 return 0;
2965 }
2966 break;
bd60018a 2967 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 2968 preemph_reg_value = 0x0006000;
2969 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2970 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2971 demph_reg_value = 0x1B405555;
2972 uniqtranscale_reg_value = 0x55ADDA3A;
2973 break;
2974 default:
2975 return 0;
2976 }
2977 break;
2978 default:
2979 return 0;
2980 }
2981
0980a60f 2982 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2983 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2984 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2985 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2986 uniqtranscale_reg_value);
ab3c759a
CML		 2987 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2988 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2989 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2990 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2991 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2992
2993 return 0;
2994}
2995
e4a1d846
CML		 2996static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2997{
2998 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2999 struct drm_i915_private *dev_priv = dev->dev_private;
3000 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3001 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3002 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3003 uint8_t train_set = intel_dp->train_set[0];
3004 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3005 enum pipe pipe = intel_crtc->pipe;
3006 int i;
e4a1d846
CML		 3007
3008 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3009 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3010 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3011 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3012 deemph_reg_value = 128;
3013 margin_reg_value = 52;
3014 break;
bd60018a 3015 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3016 deemph_reg_value = 128;
3017 margin_reg_value = 77;
3018 break;
bd60018a 3019 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3020 deemph_reg_value = 128;
3021 margin_reg_value = 102;
3022 break;
bd60018a 3023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3024 deemph_reg_value = 128;
3025 margin_reg_value = 154;
3026 /* FIXME extra to set for 1200 */
3027 break;
3028 default:
3029 return 0;
3030 }
3031 break;
bd60018a 3032 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3033 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3034 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3035 deemph_reg_value = 85;
3036 margin_reg_value = 78;
3037 break;
bd60018a 3038 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3039 deemph_reg_value = 85;
3040 margin_reg_value = 116;
3041 break;
bd60018a 3042 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3043 deemph_reg_value = 85;
3044 margin_reg_value = 154;
3045 break;
3046 default:
3047 return 0;
3048 }
3049 break;
bd60018a 3050 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3051 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3052 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3053 deemph_reg_value = 64;
3054 margin_reg_value = 104;
3055 break;
bd60018a 3056 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3057 deemph_reg_value = 64;
3058 margin_reg_value = 154;
3059 break;
3060 default:
3061 return 0;
3062 }
3063 break;
bd60018a 3064 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3065 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3066 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3067 deemph_reg_value = 43;
3068 margin_reg_value = 154;
3069 break;
3070 default:
3071 return 0;
3072 }
3073 break;
3074 default:
3075 return 0;
3076 }
3077
3078 mutex_lock(&dev_priv->dpio_lock);
3079
3080 /* Clear calc init */
1966e59e
VS		 3081 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3082 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3083 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3084 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3085 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3086
3087 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3088 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3089 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3090 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 3091 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 3092
a02ef3c7
VS		 3093 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3094 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3095 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3096 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3097
3098 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3099 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3100 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3101 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3102
e4a1d846 3103 /* Program swing deemph */
f72df8db
VS		 3104 for (i = 0; i < 4; i++) {
3105 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3106 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3107 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3108 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3109 }
e4a1d846
CML		 3110
3111 /* Program swing margin */
f72df8db
VS		 3112 for (i = 0; i < 4; i++) {
3113 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3114 val &= ~DPIO_SWING_MARGIN000_MASK;
3115 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3116 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3117 }
e4a1d846
CML		 3118
3119 /* Disable unique transition scale */
f72df8db
VS		 3120 for (i = 0; i < 4; i++) {
3121 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3122 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3123 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3124 }
e4a1d846
CML		 3125
3126 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3127 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3128 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3129 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3130
3131 /*
3132 * The document said it needs to set bit 27 for ch0 and bit 26
3133 * for ch1. Might be a typo in the doc.
3134 * For now, for this unique transition scale selection, set bit
3135 * 27 for ch0 and ch1.
3136 */
f72df8db
VS		 3137 for (i = 0; i < 4; i++) {
3138 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3139 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3140 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3141 }
e4a1d846 3142
f72df8db
VS		 3143 for (i = 0; i < 4; i++) {
3144 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3145 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3146 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3147 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3148 }
e4a1d846
CML		 3149 }
3150
3151 /* Start swing calculation */
1966e59e
VS		 3152 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3153 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3154 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3155
3156 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3157 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3158 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3159
3160 /* LRC Bypass */
3161 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3162 val |= DPIO_LRC_BYPASS;
3163 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3164
3165 mutex_unlock(&dev_priv->dpio_lock);
3166
3167 return 0;
3168}
3169
a4fc5ed6 3170static void
0301b3ac
JN		 3171intel_get_adjust_train(struct intel_dp *intel_dp,
3172 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3173{
3174 uint8_t v = 0;
3175 uint8_t p = 0;
3176 int lane;
1a2eb460
KP		 3177 uint8_t voltage_max;
3178 uint8_t preemph_max;
a4fc5ed6 3179
33a34e4e 3180 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3181 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3182 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3183
3184 if (this_v > v)
3185 v = this_v;
3186 if (this_p > p)
3187 p = this_p;
3188 }
3189
1a2eb460 3190 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3191 if (v >= voltage_max)
3192 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3193
1a2eb460
KP		 3194 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3195 if (p >= preemph_max)
3196 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3197
3198 for (lane = 0; lane < 4; lane++)
33a34e4e 3199 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3200}
3201
3202static uint32_t
f0a3424e 3203intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3204{
3cf2efb1 3205 uint32_t signal_levels = 0;
a4fc5ed6 3206
3cf2efb1 3207 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3209 default:
3210 signal_levels |= DP_VOLTAGE_0_4;
3211 break;
bd60018a 3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3213 signal_levels |= DP_VOLTAGE_0_6;
3214 break;
bd60018a 3215 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3216 signal_levels |= DP_VOLTAGE_0_8;
3217 break;
bd60018a 3218 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3219 signal_levels |= DP_VOLTAGE_1_2;
3220 break;
3221 }
3cf2efb1 3222 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3223 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3224 default:
3225 signal_levels |= DP_PRE_EMPHASIS_0;
3226 break;
bd60018a 3227 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3228 signal_levels |= DP_PRE_EMPHASIS_3_5;
3229 break;
bd60018a 3230 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3231 signal_levels |= DP_PRE_EMPHASIS_6;
3232 break;
bd60018a 3233 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3234 signal_levels |= DP_PRE_EMPHASIS_9_5;
3235 break;
3236 }
3237 return signal_levels;
3238}
3239
e3421a18
ZW		 3240/* Gen6's DP voltage swing and pre-emphasis control */
3241static uint32_t
3242intel_gen6_edp_signal_levels(uint8_t train_set)
3243{
3c5a62b5
YL		 3244 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3245 DP_TRAIN_PRE_EMPHASIS_MASK);
3246 switch (signal_levels) {
bd60018a
SJ		 3247 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3249 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3250 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3251 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3252 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3253 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3254 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3255 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3256 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3257 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3258 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3259 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3260 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3261 default:
3c5a62b5
YL		 3262 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3263 "0x%x\n", signal_levels);
3264 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3265 }
3266}
3267
1a2eb460
KP		 3268/* Gen7's DP voltage swing and pre-emphasis control */
3269static uint32_t
3270intel_gen7_edp_signal_levels(uint8_t train_set)
3271{
3272 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3273 DP_TRAIN_PRE_EMPHASIS_MASK);
3274 switch (signal_levels) {
bd60018a 3275 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3276 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3277 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3278 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3279 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3280 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3281
bd60018a 3282 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3283 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3284 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3285 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3286
bd60018a 3287 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3288 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3290 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3291
3292 default:
3293 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3294 "0x%x\n", signal_levels);
3295 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3296 }
3297}
3298
d6c0d722
PZ		 3299/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3300static uint32_t
f0a3424e 3301intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3302{
d6c0d722
PZ		 3303 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3304 DP_TRAIN_PRE_EMPHASIS_MASK);
3305 switch (signal_levels) {
bd60018a 3306 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3307 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3308 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3309 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3310 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3311 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3312 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3313 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3314
bd60018a 3315 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3316 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3317 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3318 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3319 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3320 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3321
bd60018a 3322 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3323 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3324 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3325 return DDI_BUF_TRANS_SELECT(8);
7ad14a29
SJ		 3326
3327 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3328 return DDI_BUF_TRANS_SELECT(9);
d6c0d722
PZ		 3329 default:
3330 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3331 "0x%x\n", signal_levels);
c5fe6a06 3332 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3333 }
a4fc5ed6
KP		 3334}
3335
f0a3424e
PZ		 3336/* Properly updates "DP" with the correct signal levels. */
3337static void
3338intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3339{
3340 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3341 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3342 struct drm_device *dev = intel_dig_port->base.base.dev;
3343 uint32_t signal_levels, mask;
3344 uint8_t train_set = intel_dp->train_set[0];
3345
5a9d1f1a 3346 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3347 signal_levels = intel_hsw_signal_levels(train_set);
3348 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3349 } else if (IS_CHERRYVIEW(dev)) {
3350 signal_levels = intel_chv_signal_levels(intel_dp);
3351 mask = 0;
e2fa6fba
P		 3352 } else if (IS_VALLEYVIEW(dev)) {
3353 signal_levels = intel_vlv_signal_levels(intel_dp);
3354 mask = 0;
bc7d38a4 3355 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3356 signal_levels = intel_gen7_edp_signal_levels(train_set);
3357 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3358 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3359 signal_levels = intel_gen6_edp_signal_levels(train_set);
3360 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3361 } else {
3362 signal_levels = intel_gen4_signal_levels(train_set);
3363 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3364 }
3365
3366 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3367
3368 *DP = (*DP & ~mask) | signal_levels;
3369}
3370
a4fc5ed6 3371static bool
ea5b213a 3372intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3373 uint32_t *DP,
58e10eb9 3374 uint8_t dp_train_pat)
a4fc5ed6 3375{
174edf1f
PZ		 3376 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3377 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3378 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3379 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3380 int ret, len;
a4fc5ed6 3381
7b13b58a 3382 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3383
70aff66c 3384 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3385 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3386
2cdfe6c8
JN		 3387 buf[0] = dp_train_pat;
3388 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3389 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3390 /* don't write DP_TRAINING_LANEx_SET on disable */
3391 len = 1;
3392 } else {
3393 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3394 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3395 len = intel_dp->lane_count + 1;
47ea7542 3396 }
a4fc5ed6 3397
9d1a1031
JN		 3398 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3399 buf, len);
2cdfe6c8
JN		 3400
3401 return ret == len;
a4fc5ed6
KP		 3402}
3403
70aff66c
JN		 3404static bool
3405intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3406 uint8_t dp_train_pat)
3407{
953d22e8 3408 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3409 intel_dp_set_signal_levels(intel_dp, DP);
3410 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3411}
3412
3413static bool
3414intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3415 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3416{
3417 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3418 struct drm_device *dev = intel_dig_port->base.base.dev;
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3420 int ret;
3421
3422 intel_get_adjust_train(intel_dp, link_status);
3423 intel_dp_set_signal_levels(intel_dp, DP);
3424
3425 I915_WRITE(intel_dp->output_reg, *DP);
3426 POSTING_READ(intel_dp->output_reg);
3427
9d1a1031
JN		 3428 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3429 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3430
3431 return ret == intel_dp->lane_count;
3432}
3433
3ab9c637
ID		 3434static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3435{
3436 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3437 struct drm_device *dev = intel_dig_port->base.base.dev;
3438 struct drm_i915_private *dev_priv = dev->dev_private;
3439 enum port port = intel_dig_port->port;
3440 uint32_t val;
3441
3442 if (!HAS_DDI(dev))
3443 return;
3444
3445 val = I915_READ(DP_TP_CTL(port));
3446 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3447 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3448 I915_WRITE(DP_TP_CTL(port), val);
3449
3450 /*
3451 * On PORT_A we can have only eDP in SST mode. There the only reason
3452 * we need to set idle transmission mode is to work around a HW issue
3453 * where we enable the pipe while not in idle link-training mode.
3454 * In this case there is requirement to wait for a minimum number of
3455 * idle patterns to be sent.
3456 */
3457 if (port == PORT_A)
3458 return;
3459
3460 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3461 1))
3462 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3463}
3464
33a34e4e 3465/* Enable corresponding port and start training pattern 1 */
c19b0669 3466void
33a34e4e 3467intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3468{
da63a9f2 3469 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3470 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3471 int i;
3472 uint8_t voltage;
cdb0e95b 3473 int voltage_tries, loop_tries;
ea5b213a 3474 uint32_t DP = intel_dp->DP;
6aba5b6c 3475 uint8_t link_config[2];
a4fc5ed6 3476
affa9354 3477 if (HAS_DDI(dev))
c19b0669
PZ		 3478 intel_ddi_prepare_link_retrain(encoder);
3479
3cf2efb1 3480 /* Write the link configuration data */
6aba5b6c
JN		 3481 link_config[0] = intel_dp->link_bw;
3482 link_config[1] = intel_dp->lane_count;
3483 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3484 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3485 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
a8f3ef61
SJ		 3486 if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0])
3487 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
3488 &intel_dp->rate_select, 1);
6aba5b6c
JN		 3489
3490 link_config[0] = 0;
3491 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3492 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3493
3494 DP |= DP_PORT_EN;
1a2eb460 3495
70aff66c
JN		 3496 /* clock recovery */
3497 if (!intel_dp_reset_link_train(intel_dp, &DP,
3498 DP_TRAINING_PATTERN_1 |
3499 DP_LINK_SCRAMBLING_DISABLE)) {
3500 DRM_ERROR("failed to enable link training\n");
3501 return;
3502 }
3503
a4fc5ed6 3504 voltage = 0xff;
cdb0e95b
KP		 3505 voltage_tries = 0;
3506 loop_tries = 0;
a4fc5ed6 3507 for (;;) {
70aff66c 3508 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3509
a7c9655f 3510 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3511 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3512 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3513 break;
93f62dad 3514 }
a4fc5ed6 3515
01916270 3516 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3517 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3518 break;
3519 }
3520
3521 /* Check to see if we've tried the max voltage */
3522 for (i = 0; i < intel_dp->lane_count; i++)
3523 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3524 break;
3b4f819d 3525 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3526 ++loop_tries;
3527 if (loop_tries == 5) {
3def84b3 3528 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3529 break;
3530 }
70aff66c
JN		 3531 intel_dp_reset_link_train(intel_dp, &DP,
3532 DP_TRAINING_PATTERN_1 |
3533 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3534 voltage_tries = 0;
3535 continue;
3536 }
a4fc5ed6 3537
3cf2efb1 3538 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3539 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3540 ++voltage_tries;
b06fbda3 3541 if (voltage_tries == 5) {
3def84b3 3542 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3543 break;
3544 }
3545 } else
3546 voltage_tries = 0;
3547 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3548
70aff66c
JN		 3549 /* Update training set as requested by target */
3550 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3551 DRM_ERROR("failed to update link training\n");
3552 break;
3553 }
a4fc5ed6
KP		 3554 }
3555
33a34e4e
JB		 3556 intel_dp->DP = DP;
3557}
3558
c19b0669 3559void
33a34e4e
JB		 3560intel_dp_complete_link_train(struct intel_dp *intel_dp)
3561{
33a34e4e 3562 bool channel_eq = false;
37f80975 3563 int tries, cr_tries;
33a34e4e 3564 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3565 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3566
3567 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3568 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3569 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3570
a4fc5ed6 3571 /* channel equalization */
70aff66c 3572 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3573 training_pattern |
70aff66c
JN		 3574 DP_LINK_SCRAMBLING_DISABLE)) {
3575 DRM_ERROR("failed to start channel equalization\n");
3576 return;
3577 }
3578
a4fc5ed6 3579 tries = 0;
37f80975 3580 cr_tries = 0;
a4fc5ed6
KP		 3581 channel_eq = false;
3582 for (;;) {
70aff66c 3583 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3584
37f80975
JB		 3585 if (cr_tries > 5) {
3586 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3587 break;
3588 }
3589
a7c9655f 3590 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3591 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3592 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3593 break;
70aff66c 3594 }
a4fc5ed6 3595
37f80975 3596 /* Make sure clock is still ok */
01916270 3597 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3598 intel_dp_start_link_train(intel_dp);
70aff66c 3599 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3600 training_pattern |
70aff66c 3601 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3602 cr_tries++;
3603 continue;
3604 }
3605
1ffdff13 3606 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3607 channel_eq = true;
3608 break;
3609 }
a4fc5ed6 3610
37f80975
JB		 3611 /* Try 5 times, then try clock recovery if that fails */
3612 if (tries > 5) {
37f80975 3613 intel_dp_start_link_train(intel_dp);
70aff66c 3614 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3615 training_pattern |
70aff66c 3616 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3617 tries = 0;
3618 cr_tries++;
3619 continue;
3620 }
a4fc5ed6 3621
70aff66c
JN		 3622 /* Update training set as requested by target */
3623 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3624 DRM_ERROR("failed to update link training\n");
3625 break;
3626 }
3cf2efb1 3627 ++tries;
869184a6 3628 }
3cf2efb1 3629
3ab9c637
ID		 3630 intel_dp_set_idle_link_train(intel_dp);
3631
3632 intel_dp->DP = DP;
3633
d6c0d722 3634 if (channel_eq)
07f42258 3635 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3636
3ab9c637
ID		 3637}
3638
3639void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3640{
70aff66c 3641 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3642 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3643}
3644
3645static void
ea5b213a 3646intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3647{
da63a9f2 3648 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3649 enum port port = intel_dig_port->port;
da63a9f2 3650 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3651 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 3652 uint32_t DP = intel_dp->DP;
a4fc5ed6 3653
bc76e320 3654 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3655 return;
3656
0c33d8d7 3657 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3658 return;
3659
28c97730 3660 DRM_DEBUG_KMS("\n");
32f9d658 3661
bc7d38a4 3662 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3663 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3664 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3665 } else {
aad3d14d
VS		 3666 if (IS_CHERRYVIEW(dev))
3667 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3668 else
3669 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3670 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3671 }
fe255d00 3672 POSTING_READ(intel_dp->output_reg);
5eb08b69 3673
493a7081 3674 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3675 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
5bddd17f
EA		 3676 /* Hardware workaround: leaving our transcoder select
3677 * set to transcoder B while it's off will prevent the
3678 * corresponding HDMI output on transcoder A.
3679 *
3680 * Combine this with another hardware workaround:
3681 * transcoder select bit can only be cleared while the
3682 * port is enabled.
3683 */
3684 DP &= ~DP_PIPEB_SELECT;
3685 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3686 POSTING_READ(intel_dp->output_reg);
5bddd17f
EA		 3687 }
3688
832afda6 3689 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3690 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3691 POSTING_READ(intel_dp->output_reg);
f01eca2e 3692 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3693}
3694
26d61aad
KP		 3695static bool
3696intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3697{
a031d709
RV		 3698 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3699 struct drm_device *dev = dig_port->base.base.dev;
3700 struct drm_i915_private *dev_priv = dev->dev_private;
fc0f8e25 3701 uint8_t rev;
a031d709 3702
9d1a1031
JN		 3703 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3704 sizeof(intel_dp->dpcd)) < 0)
edb39244 3705 return false; /* aux transfer failed */
92fd8fd1 3706
a8e98153 3707 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3708
edb39244
AJ		 3709 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3710 return false; /* DPCD not present */
3711
2293bb5c
SK		 3712 /* Check if the panel supports PSR */
3713 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3714 if (is_edp(intel_dp)) {
9d1a1031
JN		 3715 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3716 intel_dp->psr_dpcd,
3717 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3718 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3719 dev_priv->psr.sink_support = true;
50003939 3720 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3721 }
50003939
JN		 3722 }
3723
7809a611 3724 /* Training Pattern 3 support, both source and sink */
06ea66b6 3725 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
7809a611
JN		 3726 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3727 (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
06ea66b6 3728 intel_dp->use_tps3 = true;
f8d8a672 3729 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3730 } else
3731 intel_dp->use_tps3 = false;
3732
fc0f8e25
SJ		 3733 /* Intermediate frequency support */
3734 if (is_edp(intel_dp) &&
3735 (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3736 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3737 (rev >= 0x03)) { /* eDp v1.4 or higher */
3738 intel_dp_dpcd_read_wake(&intel_dp->aux,
3739 DP_SUPPORTED_LINK_RATES,
3740 intel_dp->supported_rates,
3741 sizeof(intel_dp->supported_rates));
3742 }
edb39244
AJ		 3743 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3744 DP_DWN_STRM_PORT_PRESENT))
3745 return true; /* native DP sink */
3746
3747 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3748 return true; /* no per-port downstream info */
3749
9d1a1031
JN		 3750 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3751 intel_dp->downstream_ports,
3752 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3753 return false; /* downstream port status fetch failed */
3754
3755 return true;
92fd8fd1
KP		 3756}
3757
0d198328
AJ		 3758static void
3759intel_dp_probe_oui(struct intel_dp *intel_dp)
3760{
3761 u8 buf[3];
3762
3763 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3764 return;
3765
9d1a1031 3766 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3767 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3768 buf[0], buf[1], buf[2]);
3769
9d1a1031 3770 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3771 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3772 buf[0], buf[1], buf[2]);
3773}
3774
0e32b39c
DA		 3775static bool
3776intel_dp_probe_mst(struct intel_dp *intel_dp)
3777{
3778 u8 buf[1];
3779
3780 if (!intel_dp->can_mst)
3781 return false;
3782
3783 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3784 return false;
3785
0e32b39c
DA		 3786 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3787 if (buf[0] & DP_MST_CAP) {
3788 DRM_DEBUG_KMS("Sink is MST capable\n");
3789 intel_dp->is_mst = true;
3790 } else {
3791 DRM_DEBUG_KMS("Sink is not MST capable\n");
3792 intel_dp->is_mst = false;
3793 }
3794 }
0e32b39c
DA		 3795
3796 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3797 return intel_dp->is_mst;
3798}
3799
d2e216d0
RV		 3800int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3801{
3802 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3803 struct drm_device *dev = intel_dig_port->base.base.dev;
3804 struct intel_crtc *intel_crtc =
3805 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3806 u8 buf;
3807 int test_crc_count;
3808 int attempts = 6;
d2e216d0 3809
ad9dc91b 3810 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3811 return -EIO;
d2e216d0 3812
ad9dc91b 3813 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3814 return -ENOTTY;
3815
1dda5f93
RV		 3816 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3817 return -EIO;
3818
9d1a1031 3819 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3820 buf | DP_TEST_SINK_START) < 0)
bda0381e 3821 return -EIO;
d2e216d0 3822
1dda5f93 3823 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3824 return -EIO;
ad9dc91b 3825 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 3826
ad9dc91b 3827 do {
1dda5f93
RV		 3828 if (drm_dp_dpcd_readb(&intel_dp->aux,
3829 DP_TEST_SINK_MISC, &buf) < 0)
3830 return -EIO;
ad9dc91b
RV		 3831 intel_wait_for_vblank(dev, intel_crtc->pipe);
3832 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3833
3834 if (attempts == 0) {
90bd1f46
DV		 3835 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
3836 return -ETIMEDOUT;
ad9dc91b 3837 }
d2e216d0 3838
9d1a1031 3839 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 3840 return -EIO;
d2e216d0 3841
1dda5f93
RV		 3842 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3843 return -EIO;
3844 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3845 buf & ~DP_TEST_SINK_START) < 0)
3846 return -EIO;
ce31d9f4 3847
d2e216d0
RV		 3848 return 0;
3849}
3850
a60f0e38
JB		 3851static bool
3852intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3853{
9d1a1031
JN		 3854 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3855 DP_DEVICE_SERVICE_IRQ_VECTOR,
3856 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3857}
3858
0e32b39c
DA		 3859static bool
3860intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3861{
3862 int ret;
3863
3864 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3865 DP_SINK_COUNT_ESI,
3866 sink_irq_vector, 14);
3867 if (ret != 14)
3868 return false;
3869
3870 return true;
3871}
3872
a60f0e38
JB		 3873static void
3874intel_dp_handle_test_request(struct intel_dp *intel_dp)
3875{
3876 /* NAK by default */
9d1a1031 3877 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3878}
3879
0e32b39c
DA		 3880static int
3881intel_dp_check_mst_status(struct intel_dp *intel_dp)
3882{
3883 bool bret;
3884
3885 if (intel_dp->is_mst) {
3886 u8 esi[16] = { 0 };
3887 int ret = 0;
3888 int retry;
3889 bool handled;
3890 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3891go_again:
3892 if (bret == true) {
3893
3894 /* check link status - esi[10] = 0x200c */
3895 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3896 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3897 intel_dp_start_link_train(intel_dp);
3898 intel_dp_complete_link_train(intel_dp);
3899 intel_dp_stop_link_train(intel_dp);
3900 }
3901
6f34cc39 3902 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 3903 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3904
3905 if (handled) {
3906 for (retry = 0; retry < 3; retry++) {
3907 int wret;
3908 wret = drm_dp_dpcd_write(&intel_dp->aux,
3909 DP_SINK_COUNT_ESI+1,
3910 &esi[1], 3);
3911 if (wret == 3) {
3912 break;
3913 }
3914 }
3915
3916 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3917 if (bret == true) {
6f34cc39 3918 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 3919 goto go_again;
3920 }
3921 } else
3922 ret = 0;
3923
3924 return ret;
3925 } else {
3926 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3927 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3928 intel_dp->is_mst = false;
3929 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3930 /* send a hotplug event */
3931 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3932 }
3933 }
3934 return -EINVAL;
3935}
3936
a4fc5ed6
KP		 3937/*
3938 * According to DP spec
3939 * 5.1.2:
3940 * 1. Read DPCD
3941 * 2. Configure link according to Receiver Capabilities
3942 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3943 * 4. Check link status on receipt of hot-plug interrupt
3944 */
a5146200 3945static void
ea5b213a 3946intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3947{
5b215bcf 3948 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3949 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3950 u8 sink_irq_vector;
93f62dad 3951 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3952
5b215bcf
DA		 3953 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3954
da63a9f2 3955 if (!intel_encoder->connectors_active)
d2b996ac 3956 return;
59cd09e1 3957
da63a9f2 3958 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3959 return;
3960
1a125d8a
ID		 3961 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3962 return;
3963
92fd8fd1 3964 /* Try to read receiver status if the link appears to be up */
93f62dad 3965 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3966 return;
3967 }
3968
92fd8fd1 3969 /* Now read the DPCD to see if it's actually running */
26d61aad 3970 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3971 return;
3972 }
3973
a60f0e38
JB		 3974 /* Try to read the source of the interrupt */
3975 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3976 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3977 /* Clear interrupt source */
9d1a1031
JN		 3978 drm_dp_dpcd_writeb(&intel_dp->aux,
3979 DP_DEVICE_SERVICE_IRQ_VECTOR,
3980 sink_irq_vector);
a60f0e38
JB		 3981
3982 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3983 intel_dp_handle_test_request(intel_dp);
3984 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3985 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3986 }
3987
1ffdff13 3988 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3989 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3990 intel_encoder->base.name);
33a34e4e
JB		 3991 intel_dp_start_link_train(intel_dp);
3992 intel_dp_complete_link_train(intel_dp);
3ab9c637 3993 intel_dp_stop_link_train(intel_dp);
33a34e4e 3994 }
a4fc5ed6 3995}
a4fc5ed6 3996
caf9ab24 3997/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3998static enum drm_connector_status
26d61aad 3999intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4000{
caf9ab24 4001 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4002 uint8_t type;
4003
4004 if (!intel_dp_get_dpcd(intel_dp))
4005 return connector_status_disconnected;
4006
4007 /* if there's no downstream port, we're done */
4008 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4009 return connector_status_connected;
caf9ab24
AJ		 4010
4011 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4012 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4013 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4014 uint8_t reg;
9d1a1031
JN		 4015
4016 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4017 &reg, 1) < 0)
caf9ab24 4018 return connector_status_unknown;
9d1a1031 4019
23235177
AJ		 4020 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4021 : connector_status_disconnected;
caf9ab24
AJ		 4022 }
4023
4024 /* If no HPD, poke DDC gently */
0b99836f 4025 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4026 return connector_status_connected;
caf9ab24
AJ		 4027
4028 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4029 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4030 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4031 if (type == DP_DS_PORT_TYPE_VGA ||
4032 type == DP_DS_PORT_TYPE_NON_EDID)
4033 return connector_status_unknown;
4034 } else {
4035 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4036 DP_DWN_STRM_PORT_TYPE_MASK;
4037 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4038 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4039 return connector_status_unknown;
4040 }
caf9ab24
AJ		 4041
4042 /* Anything else is out of spec, warn and ignore */
4043 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4044 return connector_status_disconnected;
71ba9000
AJ		 4045}
4046
d410b56d
CW		 4047static enum drm_connector_status
4048edp_detect(struct intel_dp *intel_dp)
4049{
4050 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4051 enum drm_connector_status status;
4052
4053 status = intel_panel_detect(dev);
4054 if (status == connector_status_unknown)
4055 status = connector_status_connected;
4056
4057 return status;
4058}
4059
5eb08b69 4060static enum drm_connector_status
a9756bb5 4061ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4062{
30add22d 4063 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4064 struct drm_i915_private *dev_priv = dev->dev_private;
4065 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4066
1b469639
DL		 4067 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4068 return connector_status_disconnected;
4069
26d61aad 4070 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4071}
4072
2a592bec
DA		 4073static int g4x_digital_port_connected(struct drm_device *dev,
4074 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4075{
a4fc5ed6 4076 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4077 uint32_t bit;
5eb08b69 4078
232a6ee9
TP		 4079 if (IS_VALLEYVIEW(dev)) {
4080 switch (intel_dig_port->port) {
4081 case PORT_B:
4082 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4083 break;
4084 case PORT_C:
4085 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4086 break;
4087 case PORT_D:
4088 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4089 break;
4090 default:
2a592bec 4091 return -EINVAL;
232a6ee9
TP		 4092 }
4093 } else {
4094 switch (intel_dig_port->port) {
4095 case PORT_B:
4096 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4097 break;
4098 case PORT_C:
4099 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4100 break;
4101 case PORT_D:
4102 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4103 break;
4104 default:
2a592bec 4105 return -EINVAL;
232a6ee9 4106 }
a4fc5ed6
KP		 4107 }
4108
10f76a38 4109 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4110 return 0;
4111 return 1;
4112}
4113
4114static enum drm_connector_status
4115g4x_dp_detect(struct intel_dp *intel_dp)
4116{
4117 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4118 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4119 int ret;
4120
4121 /* Can't disconnect eDP, but you can close the lid... */
4122 if (is_edp(intel_dp)) {
4123 enum drm_connector_status status;
4124
4125 status = intel_panel_detect(dev);
4126 if (status == connector_status_unknown)
4127 status = connector_status_connected;
4128 return status;
4129 }
4130
4131 ret = g4x_digital_port_connected(dev, intel_dig_port);
4132 if (ret == -EINVAL)
4133 return connector_status_unknown;
4134 else if (ret == 0)
a4fc5ed6
KP		 4135 return connector_status_disconnected;
4136
26d61aad 4137 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4138}
4139
8c241fef 4140static struct edid *
beb60608 4141intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4142{
beb60608 4143 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4144
9cd300e0
JN		 4145 /* use cached edid if we have one */
4146 if (intel_connector->edid) {
9cd300e0
JN		 4147 /* invalid edid */
4148 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4149 return NULL;
4150
55e9edeb 4151 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4152 } else
4153 return drm_get_edid(&intel_connector->base,
4154 &intel_dp->aux.ddc);
4155}
8c241fef 4156
beb60608
CW		 4157static void
4158intel_dp_set_edid(struct intel_dp *intel_dp)
4159{
4160 struct intel_connector *intel_connector = intel_dp->attached_connector;
4161 struct edid *edid;
8c241fef 4162
beb60608
CW		 4163 edid = intel_dp_get_edid(intel_dp);
4164 intel_connector->detect_edid = edid;
4165
4166 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4167 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4168 else
4169 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4170}
4171
beb60608
CW		 4172static void
4173intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4174{
beb60608 4175 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4176
beb60608
CW		 4177 kfree(intel_connector->detect_edid);
4178 intel_connector->detect_edid = NULL;
9cd300e0 4179
beb60608
CW		 4180 intel_dp->has_audio = false;
4181}
d6f24d0f 4182
beb60608
CW		 4183static enum intel_display_power_domain
4184intel_dp_power_get(struct intel_dp *dp)
4185{
4186 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4187 enum intel_display_power_domain power_domain;
4188
4189 power_domain = intel_display_port_power_domain(encoder);
4190 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4191
4192 return power_domain;
4193}
d6f24d0f 4194
beb60608
CW		 4195static void
4196intel_dp_power_put(struct intel_dp *dp,
4197 enum intel_display_power_domain power_domain)
4198{
4199 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4200 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4201}
4202
a9756bb5
ZW		 4203static enum drm_connector_status
4204intel_dp_detect(struct drm_connector *connector, bool force)
4205{
4206 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4207 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4208 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4209 struct drm_device *dev = connector->dev;
a9756bb5 4210 enum drm_connector_status status;
671dedd2 4211 enum intel_display_power_domain power_domain;
0e32b39c 4212 bool ret;
a9756bb5 4213
164c8598 4214 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4215 connector->base.id, connector->name);
beb60608 4216 intel_dp_unset_edid(intel_dp);
164c8598 4217
0e32b39c
DA		 4218 if (intel_dp->is_mst) {
4219 /* MST devices are disconnected from a monitor POV */
4220 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4221 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4222 return connector_status_disconnected;
0e32b39c
DA		 4223 }
4224
beb60608 4225 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4226
d410b56d
CW		 4227 /* Can't disconnect eDP, but you can close the lid... */
4228 if (is_edp(intel_dp))
4229 status = edp_detect(intel_dp);
4230 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4231 status = ironlake_dp_detect(intel_dp);
4232 else
4233 status = g4x_dp_detect(intel_dp);
4234 if (status != connector_status_connected)
c8c8fb33 4235 goto out;
a9756bb5 4236
0d198328
AJ		 4237 intel_dp_probe_oui(intel_dp);
4238
0e32b39c
DA		 4239 ret = intel_dp_probe_mst(intel_dp);
4240 if (ret) {
4241 /* if we are in MST mode then this connector
4242 won't appear connected or have anything with EDID on it */
4243 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4244 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4245 status = connector_status_disconnected;
4246 goto out;
4247 }
4248
beb60608 4249 intel_dp_set_edid(intel_dp);
a9756bb5 4250
d63885da
PZ		 4251 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4252 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4253 status = connector_status_connected;
4254
4255out:
beb60608 4256 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4257 return status;
a4fc5ed6
KP		 4258}
4259
beb60608
CW		 4260static void
4261intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4262{
df0e9248 4263 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4264 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4265 enum intel_display_power_domain power_domain;
a4fc5ed6 4266
beb60608
CW		 4267 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4268 connector->base.id, connector->name);
4269 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4270
beb60608
CW		 4271 if (connector->status != connector_status_connected)
4272 return;
671dedd2 4273
beb60608
CW		 4274 power_domain = intel_dp_power_get(intel_dp);
4275
4276 intel_dp_set_edid(intel_dp);
4277
4278 intel_dp_power_put(intel_dp, power_domain);
4279
4280 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4281 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4282}
4283
4284static int intel_dp_get_modes(struct drm_connector *connector)
4285{
4286 struct intel_connector *intel_connector = to_intel_connector(connector);
4287 struct edid *edid;
4288
4289 edid = intel_connector->detect_edid;
4290 if (edid) {
4291 int ret = intel_connector_update_modes(connector, edid);
4292 if (ret)
4293 return ret;
4294 }
32f9d658 4295
f8779fda 4296 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4297 if (is_edp(intel_attached_dp(connector)) &&
4298 intel_connector->panel.fixed_mode) {
f8779fda 4299 struct drm_display_mode *mode;
beb60608
CW		 4300
4301 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4302 intel_connector->panel.fixed_mode);
f8779fda 4303 if (mode) {
32f9d658
ZW		 4304 drm_mode_probed_add(connector, mode);
4305 return 1;
4306 }
4307 }
beb60608 4308
32f9d658 4309 return 0;
a4fc5ed6
KP		 4310}
4311
1aad7ac0
CW		 4312static bool
4313intel_dp_detect_audio(struct drm_connector *connector)
4314{
1aad7ac0 4315 bool has_audio = false;
beb60608 4316 struct edid *edid;
1aad7ac0 4317
beb60608
CW		 4318 edid = to_intel_connector(connector)->detect_edid;
4319 if (edid)
1aad7ac0 4320 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4321
1aad7ac0
CW		 4322 return has_audio;
4323}
4324
f684960e
CW		 4325static int
4326intel_dp_set_property(struct drm_connector *connector,
4327 struct drm_property *property,
4328 uint64_t val)
4329{
e953fd7b 4330 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4331 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4332 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4333 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4334 int ret;
4335
662595df 4336 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4337 if (ret)
4338 return ret;
4339
3f43c48d 4340 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4341 int i = val;
4342 bool has_audio;
4343
4344 if (i == intel_dp->force_audio)
f684960e
CW		 4345 return 0;
4346
1aad7ac0 4347 intel_dp->force_audio = i;
f684960e 4348
c3e5f67b 4349 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4350 has_audio = intel_dp_detect_audio(connector);
4351 else
c3e5f67b 4352 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4353
4354 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4355 return 0;
4356
1aad7ac0 4357 intel_dp->has_audio = has_audio;
f684960e
CW		 4358 goto done;
4359 }
4360
e953fd7b 4361 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4362 bool old_auto = intel_dp->color_range_auto;
4363 uint32_t old_range = intel_dp->color_range;
4364
55bc60db
VS		 4365 switch (val) {
4366 case INTEL_BROADCAST_RGB_AUTO:
4367 intel_dp->color_range_auto = true;
4368 break;
4369 case INTEL_BROADCAST_RGB_FULL:
4370 intel_dp->color_range_auto = false;
4371 intel_dp->color_range = 0;
4372 break;
4373 case INTEL_BROADCAST_RGB_LIMITED:
4374 intel_dp->color_range_auto = false;
4375 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4376 break;
4377 default:
4378 return -EINVAL;
4379 }
ae4edb80
DV		 4380
4381 if (old_auto == intel_dp->color_range_auto &&
4382 old_range == intel_dp->color_range)
4383 return 0;
4384
e953fd7b
CW		 4385 goto done;
4386 }
4387
53b41837
YN		 4388 if (is_edp(intel_dp) &&
4389 property == connector->dev->mode_config.scaling_mode_property) {
4390 if (val == DRM_MODE_SCALE_NONE) {
4391 DRM_DEBUG_KMS("no scaling not supported\n");
4392 return -EINVAL;
4393 }
4394
4395 if (intel_connector->panel.fitting_mode == val) {
4396 /* the eDP scaling property is not changed */
4397 return 0;
4398 }
4399 intel_connector->panel.fitting_mode = val;
4400
4401 goto done;
4402 }
4403
f684960e
CW		 4404 return -EINVAL;
4405
4406done:
c0c36b94
CW		 4407 if (intel_encoder->base.crtc)
4408 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4409
4410 return 0;
4411}
4412
a4fc5ed6 4413static void
73845adf 4414intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4415{
1d508706 4416 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4417
10e972d3 4418 kfree(intel_connector->detect_edid);
beb60608 4419
9cd300e0
JN		 4420 if (!IS_ERR_OR_NULL(intel_connector->edid))
4421 kfree(intel_connector->edid);
4422
acd8db10
PZ		 4423 /* Can't call is_edp() since the encoder may have been destroyed
4424 * already. */
4425 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4426 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4427
a4fc5ed6 4428 drm_connector_cleanup(connector);
55f78c43 4429 kfree(connector);
a4fc5ed6
KP		 4430}
4431
00c09d70 4432void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4433{
da63a9f2
PZ		 4434 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4435 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4436
4f71d0cb 4437 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4438 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4439 if (is_edp(intel_dp)) {
4440 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4441 /*
4442 * vdd might still be enabled do to the delayed vdd off.
4443 * Make sure vdd is actually turned off here.
4444 */
773538e8 4445 pps_lock(intel_dp);
4be73780 4446 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4447 pps_unlock(intel_dp);
4448
01527b31
CT		 4449 if (intel_dp->edp_notifier.notifier_call) {
4450 unregister_reboot_notifier(&intel_dp->edp_notifier);
4451 intel_dp->edp_notifier.notifier_call = NULL;
4452 }
bd943159 4453 }
c8bd0e49 4454 drm_encoder_cleanup(encoder);
da63a9f2 4455 kfree(intel_dig_port);
24d05927
DV		 4456}
4457
07f9cd0b
ID		 4458static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4459{
4460 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4461
4462 if (!is_edp(intel_dp))
4463 return;
4464
951468f3
VS		 4465 /*
4466 * vdd might still be enabled do to the delayed vdd off.
4467 * Make sure vdd is actually turned off here.
4468 */
afa4e53a 4469 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4470 pps_lock(intel_dp);
07f9cd0b 4471 edp_panel_vdd_off_sync(intel_dp);
773538e8 4472 pps_unlock(intel_dp);
07f9cd0b
ID		 4473}
4474
49e6bc51
VS		 4475static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4476{
4477 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4478 struct drm_device *dev = intel_dig_port->base.base.dev;
4479 struct drm_i915_private *dev_priv = dev->dev_private;
4480 enum intel_display_power_domain power_domain;
4481
4482 lockdep_assert_held(&dev_priv->pps_mutex);
4483
4484 if (!edp_have_panel_vdd(intel_dp))
4485 return;
4486
4487 /*
4488 * The VDD bit needs a power domain reference, so if the bit is
4489 * already enabled when we boot or resume, grab this reference and
4490 * schedule a vdd off, so we don't hold on to the reference
4491 * indefinitely.
4492 */
4493 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4494 power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4495 intel_display_power_get(dev_priv, power_domain);
4496
4497 edp_panel_vdd_schedule_off(intel_dp);
4498}
4499
6d93c0c4
ID		 4500static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4501{
49e6bc51
VS		 4502 struct intel_dp *intel_dp;
4503
4504 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4505 return;
4506
4507 intel_dp = enc_to_intel_dp(encoder);
4508
4509 pps_lock(intel_dp);
4510
4511 /*
4512 * Read out the current power sequencer assignment,
4513 * in case the BIOS did something with it.
4514 */
4515 if (IS_VALLEYVIEW(encoder->dev))
4516 vlv_initial_power_sequencer_setup(intel_dp);
4517
4518 intel_edp_panel_vdd_sanitize(intel_dp);
4519
4520 pps_unlock(intel_dp);
6d93c0c4
ID		 4521}
4522
a4fc5ed6 4523static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4524 .dpms = intel_connector_dpms,
a4fc5ed6 4525 .detect = intel_dp_detect,
beb60608 4526 .force = intel_dp_force,
a4fc5ed6 4527 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4528 .set_property = intel_dp_set_property,
2545e4a6 4529 .atomic_get_property = intel_connector_atomic_get_property,
73845adf 4530 .destroy = intel_dp_connector_destroy,
c6f95f27 4531 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
a4fc5ed6
KP		 4532};
4533
4534static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4535 .get_modes = intel_dp_get_modes,
4536 .mode_valid = intel_dp_mode_valid,
df0e9248 4537 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4538};
4539
a4fc5ed6 4540static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4541 .reset = intel_dp_encoder_reset,
24d05927 4542 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4543};
4544
0e32b39c 4545void
21d40d37 4546intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4547{
0e32b39c 4548 return;
c8110e52 4549}
6207937d 4550
b2c5c181 4551enum irqreturn
13cf5504
DA		 4552intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4553{
4554 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4555 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4556 struct drm_device *dev = intel_dig_port->base.base.dev;
4557 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4558 enum intel_display_power_domain power_domain;
b2c5c181 4559 enum irqreturn ret = IRQ_NONE;
1c767b33 4560
0e32b39c
DA		 4561 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4562 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4563
7a7f84cc
VS		 4564 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4565 /*
4566 * vdd off can generate a long pulse on eDP which
4567 * would require vdd on to handle it, and thus we
4568 * would end up in an endless cycle of
4569 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4570 */
4571 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4572 port_name(intel_dig_port->port));
a8b3d52f 4573 return IRQ_HANDLED;
7a7f84cc
VS		 4574 }
4575
26fbb774
VS		 4576 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4577 port_name(intel_dig_port->port),
0e32b39c 4578 long_hpd ? "long" : "short");
13cf5504 4579
1c767b33
ID		 4580 power_domain = intel_display_port_power_domain(intel_encoder);
4581 intel_display_power_get(dev_priv, power_domain);
4582
0e32b39c 4583 if (long_hpd) {
2a592bec
DA		 4584
4585 if (HAS_PCH_SPLIT(dev)) {
4586 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4587 goto mst_fail;
4588 } else {
4589 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4590 goto mst_fail;
4591 }
0e32b39c
DA		 4592
4593 if (!intel_dp_get_dpcd(intel_dp)) {
4594 goto mst_fail;
4595 }
4596
4597 intel_dp_probe_oui(intel_dp);
4598
4599 if (!intel_dp_probe_mst(intel_dp))
4600 goto mst_fail;
4601
4602 } else {
4603 if (intel_dp->is_mst) {
1c767b33 4604 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4605 goto mst_fail;
4606 }
4607
4608 if (!intel_dp->is_mst) {
4609 /*
4610 * we'll check the link status via the normal hot plug path later -
4611 * but for short hpds we should check it now
4612 */
5b215bcf 4613 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4614 intel_dp_check_link_status(intel_dp);
5b215bcf 4615 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4616 }
4617 }
b2c5c181
DV		 4618
4619 ret = IRQ_HANDLED;
4620
1c767b33 4621 goto put_power;
0e32b39c
DA		 4622mst_fail:
4623 /* if we were in MST mode, and device is not there get out of MST mode */
4624 if (intel_dp->is_mst) {
4625 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4626 intel_dp->is_mst = false;
4627 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4628 }
1c767b33
ID		 4629put_power:
4630 intel_display_power_put(dev_priv, power_domain);
4631
4632 return ret;
13cf5504
DA		 4633}
4634
e3421a18
ZW		 4635/* Return which DP Port should be selected for Transcoder DP control */
4636int
0206e353 4637intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4638{
4639 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4640 struct intel_encoder *intel_encoder;
4641 struct intel_dp *intel_dp;
e3421a18 4642
fa90ecef
PZ		 4643 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4644 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4645
fa90ecef
PZ		 4646 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4647 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4648 return intel_dp->output_reg;
e3421a18 4649 }
ea5b213a 4650
e3421a18
ZW		 4651 return -1;
4652}
4653
36e83a18 4654/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4655bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4656{
4657 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4658 union child_device_config *p_child;
36e83a18 4659 int i;
5d8a7752
VS		 4660 static const short port_mapping[] = {
4661 [PORT_B] = PORT_IDPB,
4662 [PORT_C] = PORT_IDPC,
4663 [PORT_D] = PORT_IDPD,
4664 };
36e83a18 4665
3b32a35b
VS		 4666 if (port == PORT_A)
4667 return true;
4668
41aa3448 4669 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4670 return false;
4671
41aa3448
RV		 4672 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4673 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4674
5d8a7752 4675 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4676 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4677 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4678 return true;
4679 }
4680 return false;
4681}
4682
0e32b39c 4683void
f684960e
CW		 4684intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4685{
53b41837
YN		 4686 struct intel_connector *intel_connector = to_intel_connector(connector);
4687
3f43c48d 4688 intel_attach_force_audio_property(connector);
e953fd7b 4689 intel_attach_broadcast_rgb_property(connector);
55bc60db 4690 intel_dp->color_range_auto = true;
53b41837
YN		 4691
4692 if (is_edp(intel_dp)) {
4693 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4694 drm_object_attach_property(
4695 &connector->base,
53b41837 4696 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4697 DRM_MODE_SCALE_ASPECT);
4698 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4699 }
f684960e
CW		 4700}
4701
dada1a9f
ID		 4702static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4703{
4704 intel_dp->last_power_cycle = jiffies;
4705 intel_dp->last_power_on = jiffies;
4706 intel_dp->last_backlight_off = jiffies;
4707}
4708
67a54566
DV		 4709static void
4710intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4711 struct intel_dp *intel_dp)
67a54566
DV		 4712{
4713 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4714 struct edp_power_seq cur, vbt, spec,
4715 *final = &intel_dp->pps_delays;
67a54566 4716 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4717 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4718
e39b999a
VS		 4719 lockdep_assert_held(&dev_priv->pps_mutex);
4720
81ddbc69
VS		 4721 /* already initialized? */
4722 if (final->t11_t12 != 0)
4723 return;
4724
453c5420 4725 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4726 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4727 pp_on_reg = PCH_PP_ON_DELAYS;
4728 pp_off_reg = PCH_PP_OFF_DELAYS;
4729 pp_div_reg = PCH_PP_DIVISOR;
4730 } else {
bf13e81b
JN		 4731 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4732
4733 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4734 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4735 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4736 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4737 }
67a54566
DV		 4738
4739 /* Workaround: Need to write PP_CONTROL with the unlock key as
4740 * the very first thing. */
453c5420 4741 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4742 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4743
453c5420
JB		 4744 pp_on = I915_READ(pp_on_reg);
4745 pp_off = I915_READ(pp_off_reg);
4746 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4747
4748 /* Pull timing values out of registers */
4749 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4750 PANEL_POWER_UP_DELAY_SHIFT;
4751
4752 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4753 PANEL_LIGHT_ON_DELAY_SHIFT;
4754
4755 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4756 PANEL_LIGHT_OFF_DELAY_SHIFT;
4757
4758 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4759 PANEL_POWER_DOWN_DELAY_SHIFT;
4760
4761 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4762 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4763
4764 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4765 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4766
41aa3448 4767 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4768
4769 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4770 * our hw here, which are all in 100usec. */
4771 spec.t1_t3 = 210 * 10;
4772 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4773 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4774 spec.t10 = 500 * 10;
4775 /* This one is special and actually in units of 100ms, but zero
4776 * based in the hw (so we need to add 100 ms). But the sw vbt
4777 * table multiplies it with 1000 to make it in units of 100usec,
4778 * too. */
4779 spec.t11_t12 = (510 + 100) * 10;
4780
4781 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4782 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4783
4784 /* Use the max of the register settings and vbt. If both are
4785 * unset, fall back to the spec limits. */
36b5f425 4786#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4787 spec.field : \
4788 max(cur.field, vbt.field))
4789 assign_final(t1_t3);
4790 assign_final(t8);
4791 assign_final(t9);
4792 assign_final(t10);
4793 assign_final(t11_t12);
4794#undef assign_final
4795
36b5f425 4796#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4797 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4798 intel_dp->backlight_on_delay = get_delay(t8);
4799 intel_dp->backlight_off_delay = get_delay(t9);
4800 intel_dp->panel_power_down_delay = get_delay(t10);
4801 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4802#undef get_delay
4803
f30d26e4
JN		 4804 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4805 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4806 intel_dp->panel_power_cycle_delay);
4807
4808 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4809 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 4810}
4811
4812static void
4813intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4814 struct intel_dp *intel_dp)
f30d26e4
JN		 4815{
4816 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4817 u32 pp_on, pp_off, pp_div, port_sel = 0;
4818 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4819 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4820 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4821 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4822
e39b999a 4823 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4824
4825 if (HAS_PCH_SPLIT(dev)) {
4826 pp_on_reg = PCH_PP_ON_DELAYS;
4827 pp_off_reg = PCH_PP_OFF_DELAYS;
4828 pp_div_reg = PCH_PP_DIVISOR;
4829 } else {
bf13e81b
JN		 4830 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4831
4832 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4833 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4834 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4835 }
4836
b2f19d1a
PZ		 4837 /*
4838 * And finally store the new values in the power sequencer. The
4839 * backlight delays are set to 1 because we do manual waits on them. For
4840 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4841 * we'll end up waiting for the backlight off delay twice: once when we
4842 * do the manual sleep, and once when we disable the panel and wait for
4843 * the PP_STATUS bit to become zero.
4844 */
f30d26e4 4845 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4846 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4847 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4848 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4849 /* Compute the divisor for the pp clock, simply match the Bspec
4850 * formula. */
453c5420 4851 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4852 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4853 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4854
4855 /* Haswell doesn't have any port selection bits for the panel
4856 * power sequencer any more. */
bc7d38a4 4857 if (IS_VALLEYVIEW(dev)) {
ad933b56 4858 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4859 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4860 if (port == PORT_A)
a24c144c 4861 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4862 else
a24c144c 4863 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4864 }
4865
453c5420
JB		 4866 pp_on |= port_sel;
4867
4868 I915_WRITE(pp_on_reg, pp_on);
4869 I915_WRITE(pp_off_reg, pp_off);
4870 I915_WRITE(pp_div_reg, pp_div);
67a54566 4871
67a54566 4872 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4873 I915_READ(pp_on_reg),
4874 I915_READ(pp_off_reg),
4875 I915_READ(pp_div_reg));
f684960e
CW		 4876}
4877
b33a2815
VK		 4878/**
4879 * intel_dp_set_drrs_state - program registers for RR switch to take effect
4880 * @dev: DRM device
4881 * @refresh_rate: RR to be programmed
4882 *
4883 * This function gets called when refresh rate (RR) has to be changed from
4884 * one frequency to another. Switches can be between high and low RR
4885 * supported by the panel or to any other RR based on media playback (in
4886 * this case, RR value needs to be passed from user space).
4887 *
4888 * The caller of this function needs to take a lock on dev_priv->drrs.
4889 */
96178eeb 4890static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 4891{
4892 struct drm_i915_private *dev_priv = dev->dev_private;
4893 struct intel_encoder *encoder;
96178eeb
VK		 4894 struct intel_digital_port *dig_port = NULL;
4895 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 4896 struct intel_crtc_state *config = NULL;
439d7ac0 4897 struct intel_crtc *intel_crtc = NULL;
439d7ac0 4898 u32 reg, val;
96178eeb 4899 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 4900
4901 if (refresh_rate <= 0) {
4902 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4903 return;
4904 }
4905
96178eeb
VK		 4906 if (intel_dp == NULL) {
4907 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 4908 return;
4909 }
4910
1fcc9d1c 4911 /*
e4d59f6b
RV		 4912 * FIXME: This needs proper synchronization with psr state for some
4913 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 4914 */
439d7ac0 4915
96178eeb
VK		 4916 dig_port = dp_to_dig_port(intel_dp);
4917 encoder = &dig_port->base;
439d7ac0
PB		 4918 intel_crtc = encoder->new_crtc;
4919
4920 if (!intel_crtc) {
4921 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4922 return;
4923 }
4924
6e3c9717 4925 config = intel_crtc->config;
439d7ac0 4926
96178eeb 4927 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 4928 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4929 return;
4930 }
4931
96178eeb
VK		 4932 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
4933 refresh_rate)
439d7ac0
PB		 4934 index = DRRS_LOW_RR;
4935
96178eeb 4936 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 4937 DRM_DEBUG_KMS(
4938 "DRRS requested for previously set RR...ignoring\n");
4939 return;
4940 }
4941
4942 if (!intel_crtc->active) {
4943 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4944 return;
4945 }
4946
44395bfe 4947 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 4948 switch (index) {
4949 case DRRS_HIGH_RR:
4950 intel_dp_set_m_n(intel_crtc, M1_N1);
4951 break;
4952 case DRRS_LOW_RR:
4953 intel_dp_set_m_n(intel_crtc, M2_N2);
4954 break;
4955 case DRRS_MAX_RR:
4956 default:
4957 DRM_ERROR("Unsupported refreshrate type\n");
4958 }
4959 } else if (INTEL_INFO(dev)->gen > 6) {
6e3c9717 4960 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
439d7ac0 4961 val = I915_READ(reg);
a4c30b1d 4962
439d7ac0 4963 if (index > DRRS_HIGH_RR) {
6fa7aec1
VK		 4964 if (IS_VALLEYVIEW(dev))
4965 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4966 else
4967 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 4968 } else {
6fa7aec1
VK		 4969 if (IS_VALLEYVIEW(dev))
4970 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4971 else
4972 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 4973 }
4974 I915_WRITE(reg, val);
4975 }
4976
4e9ac947
VK		 4977 dev_priv->drrs.refresh_rate_type = index;
4978
4979 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4980}
4981
b33a2815
VK		 4982/**
4983 * intel_edp_drrs_enable - init drrs struct if supported
4984 * @intel_dp: DP struct
4985 *
4986 * Initializes frontbuffer_bits and drrs.dp
4987 */
c395578e
VK		 4988void intel_edp_drrs_enable(struct intel_dp *intel_dp)
4989{
4990 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4991 struct drm_i915_private *dev_priv = dev->dev_private;
4992 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4993 struct drm_crtc *crtc = dig_port->base.base.crtc;
4994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4995
4996 if (!intel_crtc->config->has_drrs) {
4997 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
4998 return;
4999 }
5000
5001 mutex_lock(&dev_priv->drrs.mutex);
5002 if (WARN_ON(dev_priv->drrs.dp)) {
5003 DRM_ERROR("DRRS already enabled\n");
5004 goto unlock;
5005 }
5006
5007 dev_priv->drrs.busy_frontbuffer_bits = 0;
5008
5009 dev_priv->drrs.dp = intel_dp;
5010
5011unlock:
5012 mutex_unlock(&dev_priv->drrs.mutex);
5013}
5014
b33a2815
VK		 5015/**
5016 * intel_edp_drrs_disable - Disable DRRS
5017 * @intel_dp: DP struct
5018 *
5019 */
c395578e
VK		 5020void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5021{
5022 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5023 struct drm_i915_private *dev_priv = dev->dev_private;
5024 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5025 struct drm_crtc *crtc = dig_port->base.base.crtc;
5026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5027
5028 if (!intel_crtc->config->has_drrs)
5029 return;
5030
5031 mutex_lock(&dev_priv->drrs.mutex);
5032 if (!dev_priv->drrs.dp) {
5033 mutex_unlock(&dev_priv->drrs.mutex);
5034 return;
5035 }
5036
5037 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5038 intel_dp_set_drrs_state(dev_priv->dev,
5039 intel_dp->attached_connector->panel.
5040 fixed_mode->vrefresh);
5041
5042 dev_priv->drrs.dp = NULL;
5043 mutex_unlock(&dev_priv->drrs.mutex);
5044
5045 cancel_delayed_work_sync(&dev_priv->drrs.work);
5046}
5047
4e9ac947
VK		 5048static void intel_edp_drrs_downclock_work(struct work_struct *work)
5049{
5050 struct drm_i915_private *dev_priv =
5051 container_of(work, typeof(*dev_priv), drrs.work.work);
5052 struct intel_dp *intel_dp;
5053
5054 mutex_lock(&dev_priv->drrs.mutex);
5055
5056 intel_dp = dev_priv->drrs.dp;
5057
5058 if (!intel_dp)
5059 goto unlock;
5060
439d7ac0 5061 /*
4e9ac947
VK		 5062 * The delayed work can race with an invalidate hence we need to
5063 * recheck.
439d7ac0
PB		 5064 */
5065
4e9ac947
VK		 5066 if (dev_priv->drrs.busy_frontbuffer_bits)
5067 goto unlock;
439d7ac0 5068
4e9ac947
VK		 5069 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5070 intel_dp_set_drrs_state(dev_priv->dev,
5071 intel_dp->attached_connector->panel.
5072 downclock_mode->vrefresh);
439d7ac0 5073
4e9ac947 5074unlock:
439d7ac0 5075
4e9ac947 5076 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5077}
5078
b33a2815
VK		 5079/**
5080 * intel_edp_drrs_invalidate - Invalidate DRRS
5081 * @dev: DRM device
5082 * @frontbuffer_bits: frontbuffer plane tracking bits
5083 *
5084 * When there is a disturbance on screen (due to cursor movement/time
5085 * update etc), DRRS needs to be invalidated, i.e. need to switch to
5086 * high RR.
5087 *
5088 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5089 */
a93fad0f
VK		 5090void intel_edp_drrs_invalidate(struct drm_device *dev,
5091 unsigned frontbuffer_bits)
5092{
5093 struct drm_i915_private *dev_priv = dev->dev_private;
5094 struct drm_crtc *crtc;
5095 enum pipe pipe;
5096
5097 if (!dev_priv->drrs.dp)
5098 return;
5099
3954e733
R		 5100 cancel_delayed_work_sync(&dev_priv->drrs.work);
5101
a93fad0f
VK		 5102 mutex_lock(&dev_priv->drrs.mutex);
5103 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5104 pipe = to_intel_crtc(crtc)->pipe;
5105
5106 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
a93fad0f
VK		 5107 intel_dp_set_drrs_state(dev_priv->dev,
5108 dev_priv->drrs.dp->attached_connector->panel.
5109 fixed_mode->vrefresh);
5110 }
5111
5112 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5113
5114 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5115 mutex_unlock(&dev_priv->drrs.mutex);
5116}
5117
b33a2815
VK		 5118/**
5119 * intel_edp_drrs_flush - Flush DRRS
5120 * @dev: DRM device
5121 * @frontbuffer_bits: frontbuffer plane tracking bits
5122 *
5123 * When there is no movement on screen, DRRS work can be scheduled.
5124 * This DRRS work is responsible for setting relevant registers after a
5125 * timeout of 1 second.
5126 *
5127 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5128 */
a93fad0f
VK		 5129void intel_edp_drrs_flush(struct drm_device *dev,
5130 unsigned frontbuffer_bits)
5131{
5132 struct drm_i915_private *dev_priv = dev->dev_private;
5133 struct drm_crtc *crtc;
5134 enum pipe pipe;
5135
5136 if (!dev_priv->drrs.dp)
5137 return;
5138
3954e733
R		 5139 cancel_delayed_work_sync(&dev_priv->drrs.work);
5140
a93fad0f
VK		 5141 mutex_lock(&dev_priv->drrs.mutex);
5142 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5143 pipe = to_intel_crtc(crtc)->pipe;
5144 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5145
a93fad0f
VK		 5146 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR &&
5147 !dev_priv->drrs.busy_frontbuffer_bits)
5148 schedule_delayed_work(&dev_priv->drrs.work,
5149 msecs_to_jiffies(1000));
5150 mutex_unlock(&dev_priv->drrs.mutex);
5151}
5152
b33a2815
VK		 5153/**
5154 * DOC: Display Refresh Rate Switching (DRRS)
5155 *
5156 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5157 * which enables swtching between low and high refresh rates,
5158 * dynamically, based on the usage scenario. This feature is applicable
5159 * for internal panels.
5160 *
5161 * Indication that the panel supports DRRS is given by the panel EDID, which
5162 * would list multiple refresh rates for one resolution.
5163 *
5164 * DRRS is of 2 types - static and seamless.
5165 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5166 * (may appear as a blink on screen) and is used in dock-undock scenario.
5167 * Seamless DRRS involves changing RR without any visual effect to the user
5168 * and can be used during normal system usage. This is done by programming
5169 * certain registers.
5170 *
5171 * Support for static/seamless DRRS may be indicated in the VBT based on
5172 * inputs from the panel spec.
5173 *
5174 * DRRS saves power by switching to low RR based on usage scenarios.
5175 *
5176 * eDP DRRS:-
5177 * The implementation is based on frontbuffer tracking implementation.
5178 * When there is a disturbance on the screen triggered by user activity or a
5179 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5180 * When there is no movement on screen, after a timeout of 1 second, a switch
5181 * to low RR is made.
5182 * For integration with frontbuffer tracking code,
5183 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5184 *
5185 * DRRS can be further extended to support other internal panels and also
5186 * the scenario of video playback wherein RR is set based on the rate
5187 * requested by userspace.
5188 */
5189
5190/**
5191 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5192 * @intel_connector: eDP connector
5193 * @fixed_mode: preferred mode of panel
5194 *
5195 * This function is called only once at driver load to initialize basic
5196 * DRRS stuff.
5197 *
5198 * Returns:
5199 * Downclock mode if panel supports it, else return NULL.
5200 * DRRS support is determined by the presence of downclock mode (apart
5201 * from VBT setting).
5202 */
4f9db5b5 5203static struct drm_display_mode *
96178eeb
VK		 5204intel_dp_drrs_init(struct intel_connector *intel_connector,
5205 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5206{
5207 struct drm_connector *connector = &intel_connector->base;
96178eeb 5208 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5209 struct drm_i915_private *dev_priv = dev->dev_private;
5210 struct drm_display_mode *downclock_mode = NULL;
5211
5212 if (INTEL_INFO(dev)->gen <= 6) {
5213 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5214 return NULL;
5215 }
5216
5217 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5218 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5219 return NULL;
5220 }
5221
5222 downclock_mode = intel_find_panel_downclock
5223 (dev, fixed_mode, connector);
5224
5225 if (!downclock_mode) {
a1d26342 5226 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5227 return NULL;
5228 }
5229
4e9ac947
VK		 5230 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5231
96178eeb 5232 mutex_init(&dev_priv->drrs.mutex);
439d7ac0 5233
96178eeb 5234 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5235
96178eeb 5236 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5237 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5238 return downclock_mode;
5239}
5240
ed92f0b2 5241static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5242 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5243{
5244 struct drm_connector *connector = &intel_connector->base;
5245 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5246 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5247 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5248 struct drm_i915_private *dev_priv = dev->dev_private;
5249 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5250 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5251 bool has_dpcd;
5252 struct drm_display_mode *scan;
5253 struct edid *edid;
6517d273 5254 enum pipe pipe = INVALID_PIPE;
ed92f0b2 5255
96178eeb 5256 dev_priv->drrs.type = DRRS_NOT_SUPPORTED;
4f9db5b5 5257
ed92f0b2
PZ		 5258 if (!is_edp(intel_dp))
5259 return true;
5260
49e6bc51
VS		 5261 pps_lock(intel_dp);
5262 intel_edp_panel_vdd_sanitize(intel_dp);
5263 pps_unlock(intel_dp);
63635217 5264
ed92f0b2 5265 /* Cache DPCD and EDID for edp. */
ed92f0b2 5266 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5267
5268 if (has_dpcd) {
5269 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5270 dev_priv->no_aux_handshake =
5271 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5272 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5273 } else {
5274 /* if this fails, presume the device is a ghost */
5275 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5276 return false;
5277 }
5278
5279 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5280 pps_lock(intel_dp);
36b5f425 5281 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5282 pps_unlock(intel_dp);
ed92f0b2 5283
060c8778 5284 mutex_lock(&dev->mode_config.mutex);
0b99836f 5285 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5286 if (edid) {
5287 if (drm_add_edid_modes(connector, edid)) {
5288 drm_mode_connector_update_edid_property(connector,
5289 edid);
5290 drm_edid_to_eld(connector, edid);
5291 } else {
5292 kfree(edid);
5293 edid = ERR_PTR(-EINVAL);
5294 }
5295 } else {
5296 edid = ERR_PTR(-ENOENT);
5297 }
5298 intel_connector->edid = edid;
5299
5300 /* prefer fixed mode from EDID if available */
5301 list_for_each_entry(scan, &connector->probed_modes, head) {
5302 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5303 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5304 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5305 intel_connector, fixed_mode);
ed92f0b2
PZ		 5306 break;
5307 }
5308 }
5309
5310 /* fallback to VBT if available for eDP */
5311 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5312 fixed_mode = drm_mode_duplicate(dev,
5313 dev_priv->vbt.lfp_lvds_vbt_mode);
5314 if (fixed_mode)
5315 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5316 }
060c8778 5317 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5318
01527b31
CT		 5319 if (IS_VALLEYVIEW(dev)) {
5320 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5321 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5322
5323 /*
5324 * Figure out the current pipe for the initial backlight setup.
5325 * If the current pipe isn't valid, try the PPS pipe, and if that
5326 * fails just assume pipe A.
5327 */
5328 if (IS_CHERRYVIEW(dev))
5329 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5330 else
5331 pipe = PORT_TO_PIPE(intel_dp->DP);
5332
5333 if (pipe != PIPE_A && pipe != PIPE_B)
5334 pipe = intel_dp->pps_pipe;
5335
5336 if (pipe != PIPE_A && pipe != PIPE_B)
5337 pipe = PIPE_A;
5338
5339 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5340 pipe_name(pipe));
01527b31
CT		 5341 }
5342
4f9db5b5 5343 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5344 intel_connector->panel.backlight_power = intel_edp_backlight_power;
6517d273 5345 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5346
5347 return true;
5348}
5349
16c25533 5350bool
f0fec3f2
PZ		 5351intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5352 struct intel_connector *intel_connector)
a4fc5ed6 5353{
f0fec3f2
PZ		 5354 struct drm_connector *connector = &intel_connector->base;
5355 struct intel_dp *intel_dp = &intel_dig_port->dp;
5356 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5357 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5358 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5359 enum port port = intel_dig_port->port;
0b99836f 5360 int type;
a4fc5ed6 5361
a4a5d2f8
VS		 5362 intel_dp->pps_pipe = INVALID_PIPE;
5363
ec5b01dd 5364 /* intel_dp vfuncs */
b6b5e383
DL		 5365 if (INTEL_INFO(dev)->gen >= 9)
5366 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5367 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5368 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5369 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5370 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5371 else if (HAS_PCH_SPLIT(dev))
5372 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5373 else
5374 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5375
b9ca5fad
DL		 5376 if (INTEL_INFO(dev)->gen >= 9)
5377 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5378 else
5379 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5380
0767935e
DV		 5381 /* Preserve the current hw state. */
5382 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5383 intel_dp->attached_connector = intel_connector;
3d3dc149 5384
3b32a35b 5385 if (intel_dp_is_edp(dev, port))
b329530c 5386 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5387 else
5388 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5389
f7d24902
ID		 5390 /*
5391 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5392 * for DP the encoder type can be set by the caller to
5393 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5394 */
5395 if (type == DRM_MODE_CONNECTOR_eDP)
5396 intel_encoder->type = INTEL_OUTPUT_EDP;
5397
c17ed5b5
VS		 5398 /* eDP only on port B and/or C on vlv/chv */
5399 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5400 port != PORT_B && port != PORT_C))
5401 return false;
5402
e7281eab
ID		 5403 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5404 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5405 port_name(port));
5406
b329530c 5407 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5408 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5409
a4fc5ed6
KP		 5410 connector->interlace_allowed = true;
5411 connector->doublescan_allowed = 0;
5412
f0fec3f2 5413 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5414 edp_panel_vdd_work);
a4fc5ed6 5415
df0e9248 5416 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5417 drm_connector_register(connector);
a4fc5ed6 5418
affa9354 5419 if (HAS_DDI(dev))
bcbc889b
PZ		 5420 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5421 else
5422 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5423 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5424
0b99836f 5425 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5426 switch (port) {
5427 case PORT_A:
1d843f9d 5428 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5429 break;
5430 case PORT_B:
1d843f9d 5431 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5432 break;
5433 case PORT_C:
1d843f9d 5434 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5435 break;
5436 case PORT_D:
1d843f9d 5437 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5438 break;
5439 default:
ad1c0b19 5440 BUG();
5eb08b69
ZW		 5441 }
5442
dada1a9f 5443 if (is_edp(intel_dp)) {
773538e8 5444 pps_lock(intel_dp);
1e74a324
VS		 5445 intel_dp_init_panel_power_timestamps(intel_dp);
5446 if (IS_VALLEYVIEW(dev))
a4a5d2f8 5447 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5448 else
36b5f425 5449 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5450 pps_unlock(intel_dp);
dada1a9f 5451 }
0095e6dc 5452
9d1a1031 5453 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5454
0e32b39c 5455 /* init MST on ports that can support it */
c86ea3d0 5456 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
0e32b39c 5457 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5458 intel_dp_mst_encoder_init(intel_dig_port,
5459 intel_connector->base.base.id);
0e32b39c
DA		 5460 }
5461 }
5462
36b5f425 5463 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5464 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5465 if (is_edp(intel_dp)) {
5466 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5467 /*
5468 * vdd might still be enabled do to the delayed vdd off.
5469 * Make sure vdd is actually turned off here.
5470 */
773538e8 5471 pps_lock(intel_dp);
4be73780 5472 edp_panel_vdd_off_sync(intel_dp);
773538e8 5473 pps_unlock(intel_dp);
15b1d171 5474 }
34ea3d38 5475 drm_connector_unregister(connector);
b2f246a8 5476 drm_connector_cleanup(connector);
16c25533 5477 return false;
b2f246a8 5478 }
32f9d658 5479
f684960e
CW		 5480 intel_dp_add_properties(intel_dp, connector);
5481
a4fc5ed6
KP		 5482 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5483 * 0xd. Failure to do so will result in spurious interrupts being
5484 * generated on the port when a cable is not attached.
5485 */
5486 if (IS_G4X(dev) && !IS_GM45(dev)) {
5487 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5488 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5489 }
16c25533
PZ		 5490
5491 return true;
a4fc5ed6 5492}
f0fec3f2
PZ		 5493
5494void
5495intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5496{
13cf5504 5497 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5498 struct intel_digital_port *intel_dig_port;
5499 struct intel_encoder *intel_encoder;
5500 struct drm_encoder *encoder;
5501 struct intel_connector *intel_connector;
5502
b14c5679 5503 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5504 if (!intel_dig_port)
5505 return;
5506
b14c5679 5507 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5508 if (!intel_connector) {
5509 kfree(intel_dig_port);
5510 return;
5511 }
5512
5513 intel_encoder = &intel_dig_port->base;
5514 encoder = &intel_encoder->base;
5515
5516 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5517 DRM_MODE_ENCODER_TMDS);
5518
5bfe2ac0 5519 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5520 intel_encoder->disable = intel_disable_dp;
00c09d70 5521 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5522 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5523 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5524 if (IS_CHERRYVIEW(dev)) {
9197c88b 5525 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5526 intel_encoder->pre_enable = chv_pre_enable_dp;
5527 intel_encoder->enable = vlv_enable_dp;
580d3811 5528 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5529 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5530 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5531 intel_encoder->pre_enable = vlv_pre_enable_dp;
5532 intel_encoder->enable = vlv_enable_dp;
49277c31 5533 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5534 } else {
ecff4f3b
JN		 5535 intel_encoder->pre_enable = g4x_pre_enable_dp;
5536 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5537 if (INTEL_INFO(dev)->gen >= 5)
5538 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5539 }
f0fec3f2 5540
174edf1f 5541 intel_dig_port->port = port;
f0fec3f2
PZ		 5542 intel_dig_port->dp.output_reg = output_reg;
5543
00c09d70 5544 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5545 if (IS_CHERRYVIEW(dev)) {
5546 if (port == PORT_D)
5547 intel_encoder->crtc_mask = 1 << 2;
5548 else
5549 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5550 } else {
5551 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5552 }
bc079e8b 5553 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5554 intel_encoder->hot_plug = intel_dp_hot_plug;
5555
13cf5504
DA		 5556 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5557 dev_priv->hpd_irq_port[port] = intel_dig_port;
5558
15b1d171
PZ		 5559 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5560 drm_encoder_cleanup(encoder);
5561 kfree(intel_dig_port);
b2f246a8 5562 kfree(intel_connector);
15b1d171 5563 }
f0fec3f2 5564}
0e32b39c
DA		 5565
5566void intel_dp_mst_suspend(struct drm_device *dev)
5567{
5568 struct drm_i915_private *dev_priv = dev->dev_private;
5569 int i;
5570
5571 /* disable MST */
5572 for (i = 0; i < I915_MAX_PORTS; i++) {
5573 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5574 if (!intel_dig_port)
5575 continue;
5576
5577 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5578 if (!intel_dig_port->dp.can_mst)
5579 continue;
5580 if (intel_dig_port->dp.is_mst)
5581 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5582 }
5583 }
5584}
5585
5586void intel_dp_mst_resume(struct drm_device *dev)
5587{
5588 struct drm_i915_private *dev_priv = dev->dev_private;
5589 int i;
5590
5591 for (i = 0; i < I915_MAX_PORTS; i++) {
5592 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5593 if (!intel_dig_port)
5594 continue;
5595 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5596 int ret;
5597
5598 if (!intel_dig_port->dp.can_mst)
5599 continue;
5600
5601 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5602 if (ret != 0) {
5603 intel_dp_check_mst_status(&intel_dig_port->dp);
5604 }
5605 }
5606 }
5607}
Linux kernel - Deliverables
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