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drm/i915: extract set_m_n from ironlake_crtc_mode_set
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
a0c4da24
JB		 101static bool
102intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
021357ac
CW		 106static inline u32 /* units of 100MHz */
107intel_fdi_link_freq(struct drm_device *dev)
108{
8b99e68c
CW		 109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
021357ac
CW		 114}
115
e4b36699 116static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
d4906093 127 .find_pll = intel_find_best_PLL,
e4b36699
KP		 128};
129
130static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
d4906093 141 .find_pll = intel_find_best_PLL,
e4b36699 142};
273e27ca 143
e4b36699 144static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
d4906093 155 .find_pll = intel_find_best_PLL,
e4b36699
KP		 156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
d4906093 169 .find_pll = intel_find_best_PLL,
e4b36699
KP		 170};
171
273e27ca 172
e4b36699 173static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
044c7c41 185 },
d4906093 186 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 187};
188
189static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
d4906093 200 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 201};
202
203static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
044c7c41 214 },
d4906093 215 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 216};
217
218static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
044c7c41 229 },
d4906093 230 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 231};
232
233static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
273e27ca 243 .p2_slow = 10, .p2_fast = 10 },
0206e353 244 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 245};
246
f2b115e6 247static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 250 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
273e27ca 253 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
6115707b 260 .find_pll = intel_find_best_PLL,
e4b36699
KP		 261};
262
f2b115e6 263static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
6115707b 274 .find_pll = intel_find_best_PLL,
e4b36699
KP		 275};
276
273e27ca
EA		 277/* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
b91ad0ec 282static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
4547668a 293 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 294};
295
b91ad0ec 296static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 307 .find_pll = intel_g4x_find_best_PLL,
308};
309
310static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 321 .find_pll = intel_g4x_find_best_PLL,
322};
323
273e27ca 324/* LVDS 100mhz refclk limits. */
b91ad0ec 325static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
0206e353 333 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 336 .find_pll = intel_g4x_find_best_PLL,
337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
0206e353 347 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 350 .find_pll = intel_g4x_find_best_PLL,
351};
352
353static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
273e27ca 363 .p2_slow = 10, .p2_fast = 10 },
0206e353 364 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 365};
366
a0c4da24
JB		 367static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379};
380
381static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393};
394
395static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407};
408
57f350b6
JB		 409u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410{
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432}
433
a0c4da24
JB		 434static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436{
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454}
455
57f350b6
JB		 456static void vlv_init_dpio(struct drm_device *dev)
457{
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465}
466
618563e3
DV		 467static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468{
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471}
472
473static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483};
484
b0354385
TI		 485static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487{
488 unsigned int val;
489
121d527a
TI		 490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
618563e3
DV		 494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
b0354385
TI		 497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
14d94a3d 506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511}
512
1b894b59
CW		 513static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
2c07245f 515{
b91ad0ec
ZW		 516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 518 const intel_limit_t *limit;
b91ad0ec
ZW		 519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 522 /* LVDS dual channel */
1b894b59 523 if (refclk == 100000)
b91ad0ec
ZW		 524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
1b894b59 528 if (refclk == 100000)
b91ad0ec
ZW		 529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
2c07245f 536 else
b91ad0ec 537 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 538
539 return limit;
540}
541
044c7c41
ML		 542static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543{
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 549 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 550 /* LVDS with dual channel */
e4b36699 551 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 552 else
553 /* LVDS with dual channel */
e4b36699 554 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 557 limit = &intel_limits_g4x_hdmi;
044c7c41 558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 559 limit = &intel_limits_g4x_sdvo;
0206e353 560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 561 limit = &intel_limits_g4x_display_port;
044c7c41 562 } else /* The option is for other outputs */
e4b36699 563 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 564
565 return limit;
566}
567
1b894b59 568static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 569{
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
bad720ff 573 if (HAS_PCH_SPLIT(dev))
1b894b59 574 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 575 else if (IS_G4X(dev)) {
044c7c41 576 limit = intel_g4x_limit(crtc);
f2b115e6 577 } else if (IS_PINEVIEW(dev)) {
2177832f 578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 579 limit = &intel_limits_pineview_lvds;
2177832f 580 else
f2b115e6 581 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 596 limit = &intel_limits_i8xx_lvds;
79e53945 597 else
e4b36699 598 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 599 }
600 return limit;
601}
602
f2b115e6
AJ		 603/* m1 is reserved as 0 in Pineview, n is a ring counter */
604static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 605{
2177832f
SL		 606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610}
611
612static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613{
f2b115e6
AJ		 614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
2177832f
SL		 616 return;
617 }
79e53945
JB		 618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622}
623
79e53945
JB		 624/**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
4ef69c7a 627bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 628{
4ef69c7a 629 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 630 struct intel_encoder *encoder;
631
6c2b7c12
DV		 632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
4ef69c7a
CW		 634 return true;
635
636 return false;
79e53945
JB		 637}
638
7c04d1d9 639#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 640/**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
1b894b59
CW		 645static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
79e53945 648{
79e53945 649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 650 INTELPllInvalid("p1 out of range\n");
79e53945 651 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 652 INTELPllInvalid("p out of range\n");
79e53945 653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 654 INTELPllInvalid("m2 out of range\n");
79e53945 655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 656 INTELPllInvalid("m1 out of range\n");
f2b115e6 657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 658 INTELPllInvalid("m1 <= m2\n");
79e53945 659 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 660 INTELPllInvalid("m out of range\n");
79e53945 661 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 662 INTELPllInvalid("n out of range\n");
79e53945 663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 664 INTELPllInvalid("vco out of range\n");
79e53945
JB		 665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 669 INTELPllInvalid("dot out of range\n");
79e53945
JB		 670
671 return true;
672}
673
d4906093
ML		 674static bool
675intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
d4906093 678
79e53945
JB		 679{
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
79e53945
JB		 683 int err = target;
684
bc5e5718 685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 686 (I915_READ(LVDS)) != 0) {
79e53945
JB		 687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
b0354385 693 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
0206e353 704 memset(best_clock, 0, sizeof(*best_clock));
79e53945 705
42158660
ZY		 706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 717 int this_err;
718
2177832f 719 intel_clock(dev, refclk, &clock);
1b894b59
CW		 720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
79e53945 722 continue;
cec2f356
SP		 723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
79e53945
JB		 726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738}
739
d4906093
ML		 740static bool
741intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
d4906093
ML		 744{
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
6ba770dc
AJ		 750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 755 int lvds_reg;
756
c619eed4 757 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
f77f13e2 775 /* based on hardware requirement, prefer smaller n to precision */
d4906093 776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 777 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
2177832f 786 intel_clock(dev, refclk, &clock);
1b894b59
CW		 787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
d4906093 789 continue;
cec2f356
SP		 790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
1b894b59
CW		 793
794 this_err = abs(clock.dot - target);
d4906093
ML		 795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
2c07245f
ZW		 805 return found;
806}
807
5eb08b69 808static bool
f2b115e6 809intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
5eb08b69
ZW		 812{
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
4547668a 815
5eb08b69
ZW		 816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832}
833
a4fc5ed6
KP		 834/* DisplayPort has only two frequencies, 162MHz and 270MHz */
835static bool
836intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
a4fc5ed6 839{
5eddb70b
CW		 840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
a4fc5ed6 860}
a0c4da24
JB		 861static bool
862intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865{
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
af447bd3 872 flag = 0;
a0c4da24
JB		 873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928}
a4fc5ed6 929
a928d536
PZ		 930static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931{
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939}
940
9d0498a2
JB		 941/**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 950{
9d0498a2 951 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 952 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 953
a928d536
PZ		 954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
300387c0
CW		 959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
9d0498a2 975 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
9d0498a2
JB		 979 DRM_DEBUG_KMS("vblank wait timed out\n");
980}
981
ab7ad7f6
KP		 982/*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
ab7ad7f6
KP		 991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
58e10eb9 997 *
9d0498a2 998 */
58e10eb9 999void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1000{
1001 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 1002
1003 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 1004 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 1005
1006 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
284637d9 1009 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1010 } else {
837ba00f 1011 u32 last_line, line_mask;
58e10eb9 1012 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
837ba00f
PZ		 1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
ab7ad7f6
KP		 1020 /* Wait for the display line to settle */
1021 do {
837ba00f 1022 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1023 mdelay(5);
837ba00f 1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
284637d9 1027 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1028 }
79e53945
JB		 1029}
1030
b24e7179
JB		 1031static const char *state_string(bool enabled)
1032{
1033 return enabled ? "on" : "off";
1034}
1035
1036/* Only for pre-ILK configs */
1037static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039{
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050}
1051#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
040484af
JB		 1054/* For ILK+ */
1055static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
040484af 1059{
040484af
JB		 1060 u32 val;
1061 bool cur_state;
1062
9d82aa17
ED		 1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
92b27b08
CW		 1068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1070 return;
ee7b9f93 1071
92b27b08
CW		 1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
d3ccbe86 1095 }
040484af 1096}
92b27b08
CW		 1097#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1099
1100static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102{
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
bf507ef7
ED		 1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
040484af
JB		 1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
1121#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126{
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
59c859d6
ED		 1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
040484af
JB		 1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142}
1143#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
bf507ef7
ED		 1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
040484af
JB		 1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163}
1164
1165static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
1168 int reg;
1169 u32 val;
1170
59c859d6
ED		 1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
040484af
JB		 1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178}
1179
ea0760cf
JB		 1180static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182{
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
0de3b485 1186 bool locked = true;
ea0760cf
JB		 1187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1206 pipe_name(pipe));
ea0760cf
JB		 1207}
1208
b840d907
JB		 1209void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
b24e7179
JB		 1211{
1212 int reg;
1213 u32 val;
63d7bbe9 1214 bool cur_state;
b24e7179 1215
8e636784
DV		 1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
b24e7179
JB		 1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
63d7bbe9
JB		 1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1225 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1226}
1227
931872fc
CW		 1228static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
b24e7179
JB		 1230{
1231 int reg;
1232 u32 val;
931872fc 1233 bool cur_state;
b24e7179
JB		 1234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
931872fc
CW		 1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1241}
1242
931872fc
CW		 1243#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
b24e7179
JB		 1246static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248{
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
19ec1358 1253 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
19ec1358 1260 return;
28c05794 1261 }
19ec1358 1262
b24e7179
JB		 1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1272 }
1273}
1274
92f2584a
JB		 1275static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276{
1277 u32 val;
1278 bool enabled;
1279
9d82aa17
ED		 1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
92f2584a
JB		 1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289}
1290
1291static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
92f2584a
JB		 1304}
1305
4e634389
KP		 1306static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1308{
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322}
1323
1519b995
KP		 1324static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326{
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338}
1339
1340static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369}
1370
291906f1 1371static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1372 enum pipe pipe, int reg, u32 port_sel)
291906f1 1373{
47a05eca 1374 u32 val = I915_READ(reg);
4e634389 1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1377 reg, pipe_name(pipe));
de9a35ab 1378
75c5da27
DV		 1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1380 && (val & DP_PIPEB_SELECT),
de9a35ab 1381 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1382}
1383
1384static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe, int reg)
1386{
47a05eca 1387 u32 val = I915_READ(reg);
e9a851ed 1388 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1389 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1390 reg, pipe_name(pipe));
de9a35ab 1391
75c5da27
DV		 1392 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1393 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1394 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1395}
1396
1397static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399{
1400 int reg;
1401 u32 val;
291906f1 1402
f0575e92
KP		 1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1404 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1405 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1406
1407 reg = PCH_ADPA;
1408 val = I915_READ(reg);
e9a851ed 1409 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1410 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1411 pipe_name(pipe));
291906f1
JB		 1412
1413 reg = PCH_LVDS;
1414 val = I915_READ(reg);
e9a851ed 1415 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1416 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1417 pipe_name(pipe));
291906f1
JB		 1418
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1420 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1421 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1422}
1423
63d7bbe9
JB		 1424/**
1425 * intel_enable_pll - enable a PLL
1426 * @dev_priv: i915 private structure
1427 * @pipe: pipe PLL to enable
1428 *
1429 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1430 * make sure the PLL reg is writable first though, since the panel write
1431 * protect mechanism may be enabled.
1432 *
1433 * Note! This is for pre-ILK only.
7434a255
TR		 1434 *
1435 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1436 */
a37b9b34 1437static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1438{
1439 int reg;
1440 u32 val;
1441
1442 /* No really, not for ILK+ */
a0c4da24 1443 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1444
1445 /* PLL is protected by panel, make sure we can write it */
1446 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1447 assert_panel_unlocked(dev_priv, pipe);
1448
1449 reg = DPLL(pipe);
1450 val = I915_READ(reg);
1451 val |= DPLL_VCO_ENABLE;
1452
1453 /* We do this three times for luck */
1454 I915_WRITE(reg, val);
1455 POSTING_READ(reg);
1456 udelay(150); /* wait for warmup */
1457 I915_WRITE(reg, val);
1458 POSTING_READ(reg);
1459 udelay(150); /* wait for warmup */
1460 I915_WRITE(reg, val);
1461 POSTING_READ(reg);
1462 udelay(150); /* wait for warmup */
1463}
1464
1465/**
1466 * intel_disable_pll - disable a PLL
1467 * @dev_priv: i915 private structure
1468 * @pipe: pipe PLL to disable
1469 *
1470 * Disable the PLL for @pipe, making sure the pipe is off first.
1471 *
1472 * Note! This is for pre-ILK only.
1473 */
1474static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1475{
1476 int reg;
1477 u32 val;
1478
1479 /* Don't disable pipe A or pipe A PLLs if needed */
1480 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1481 return;
1482
1483 /* Make sure the pipe isn't still relying on us */
1484 assert_pipe_disabled(dev_priv, pipe);
1485
1486 reg = DPLL(pipe);
1487 val = I915_READ(reg);
1488 val &= ~DPLL_VCO_ENABLE;
1489 I915_WRITE(reg, val);
1490 POSTING_READ(reg);
1491}
1492
a416edef
ED		 1493/* SBI access */
1494static void
1495intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1496{
1497 unsigned long flags;
1498
1499 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1500 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1501 100)) {
1502 DRM_ERROR("timeout waiting for SBI to become ready\n");
1503 goto out_unlock;
1504 }
1505
1506 I915_WRITE(SBI_ADDR,
1507 (reg << 16));
1508 I915_WRITE(SBI_DATA,
1509 value);
1510 I915_WRITE(SBI_CTL_STAT,
1511 SBI_BUSY |
1512 SBI_CTL_OP_CRWR);
1513
39fb50f6 1514 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1515 100)) {
1516 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1517 goto out_unlock;
1518 }
1519
1520out_unlock:
1521 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1522}
1523
1524static u32
1525intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1526{
1527 unsigned long flags;
39fb50f6 1528 u32 value = 0;
a416edef
ED		 1529
1530 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1531 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1532 100)) {
1533 DRM_ERROR("timeout waiting for SBI to become ready\n");
1534 goto out_unlock;
1535 }
1536
1537 I915_WRITE(SBI_ADDR,
1538 (reg << 16));
1539 I915_WRITE(SBI_CTL_STAT,
1540 SBI_BUSY |
1541 SBI_CTL_OP_CRRD);
1542
39fb50f6 1543 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1544 100)) {
1545 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1546 goto out_unlock;
1547 }
1548
1549 value = I915_READ(SBI_DATA);
1550
1551out_unlock:
1552 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1553 return value;
1554}
1555
92f2584a
JB		 1556/**
1557 * intel_enable_pch_pll - enable PCH PLL
1558 * @dev_priv: i915 private structure
1559 * @pipe: pipe PLL to enable
1560 *
1561 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1562 * drives the transcoder clock.
1563 */
ee7b9f93 1564static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1565{
ee7b9f93 1566 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1567 struct intel_pch_pll *pll;
92f2584a
JB		 1568 int reg;
1569 u32 val;
1570
48da64a8 1571 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1572 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1573 pll = intel_crtc->pch_pll;
1574 if (pll == NULL)
1575 return;
1576
1577 if (WARN_ON(pll->refcount == 0))
1578 return;
ee7b9f93
JB		 1579
1580 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1581 pll->pll_reg, pll->active, pll->on,
1582 intel_crtc->base.base.id);
92f2584a
JB		 1583
1584 /* PCH refclock must be enabled first */
1585 assert_pch_refclk_enabled(dev_priv);
1586
ee7b9f93 1587 if (pll->active++ && pll->on) {
92b27b08 1588 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1589 return;
1590 }
1591
1592 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1593
1594 reg = pll->pll_reg;
92f2584a
JB		 1595 val = I915_READ(reg);
1596 val |= DPLL_VCO_ENABLE;
1597 I915_WRITE(reg, val);
1598 POSTING_READ(reg);
1599 udelay(200);
ee7b9f93
JB		 1600
1601 pll->on = true;
92f2584a
JB		 1602}
1603
ee7b9f93 1604static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1605{
ee7b9f93
JB		 1606 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1607 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1608 int reg;
ee7b9f93 1609 u32 val;
4c609cb8 1610
92f2584a
JB		 1611 /* PCH only available on ILK+ */
1612 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1613 if (pll == NULL)
1614 return;
92f2584a 1615
48da64a8
CW		 1616 if (WARN_ON(pll->refcount == 0))
1617 return;
7a419866 1618
ee7b9f93
JB		 1619 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1620 pll->pll_reg, pll->active, pll->on,
1621 intel_crtc->base.base.id);
7a419866 1622
48da64a8 1623 if (WARN_ON(pll->active == 0)) {
92b27b08 1624 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1625 return;
1626 }
1627
ee7b9f93 1628 if (--pll->active) {
92b27b08 1629 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1630 return;
ee7b9f93
JB		 1631 }
1632
1633 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1634
1635 /* Make sure transcoder isn't still depending on us */
1636 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1637
ee7b9f93 1638 reg = pll->pll_reg;
92f2584a
JB		 1639 val = I915_READ(reg);
1640 val &= ~DPLL_VCO_ENABLE;
1641 I915_WRITE(reg, val);
1642 POSTING_READ(reg);
1643 udelay(200);
ee7b9f93
JB		 1644
1645 pll->on = false;
92f2584a
JB		 1646}
1647
040484af
JB		 1648static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1649 enum pipe pipe)
1650{
1651 int reg;
5f7f726d 1652 u32 val, pipeconf_val;
7c26e5c6 1653 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1654
1655 /* PCH only available on ILK+ */
1656 BUG_ON(dev_priv->info->gen < 5);
1657
1658 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1659 assert_pch_pll_enabled(dev_priv,
1660 to_intel_crtc(crtc)->pch_pll,
1661 to_intel_crtc(crtc));
040484af
JB		 1662
1663 /* FDI must be feeding us bits for PCH ports */
1664 assert_fdi_tx_enabled(dev_priv, pipe);
1665 assert_fdi_rx_enabled(dev_priv, pipe);
1666
59c859d6
ED		 1667 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1668 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1669 return;
1670 }
040484af
JB		 1671 reg = TRANSCONF(pipe);
1672 val = I915_READ(reg);
5f7f726d 1673 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1674
1675 if (HAS_PCH_IBX(dev_priv->dev)) {
1676 /*
1677 * make the BPC in transcoder be consistent with
1678 * that in pipeconf reg.
1679 */
1680 val &= ~PIPE_BPC_MASK;
5f7f726d 1681 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1682 }
5f7f726d
PZ		 1683
1684 val &= ~TRANS_INTERLACE_MASK;
1685 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1686 if (HAS_PCH_IBX(dev_priv->dev) &&
1687 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1688 val |= TRANS_LEGACY_INTERLACED_ILK;
1689 else
1690 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1691 else
1692 val |= TRANS_PROGRESSIVE;
1693
040484af
JB		 1694 I915_WRITE(reg, val | TRANS_ENABLE);
1695 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1696 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1697}
1698
1699static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1700 enum pipe pipe)
1701{
1702 int reg;
1703 u32 val;
1704
1705 /* FDI relies on the transcoder */
1706 assert_fdi_tx_disabled(dev_priv, pipe);
1707 assert_fdi_rx_disabled(dev_priv, pipe);
1708
291906f1
JB		 1709 /* Ports must be off as well */
1710 assert_pch_ports_disabled(dev_priv, pipe);
1711
040484af
JB		 1712 reg = TRANSCONF(pipe);
1713 val = I915_READ(reg);
1714 val &= ~TRANS_ENABLE;
1715 I915_WRITE(reg, val);
1716 /* wait for PCH transcoder off, transcoder state */
1717 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1718 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1719}
1720
b24e7179 1721/**
309cfea8 1722 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1723 * @dev_priv: i915 private structure
1724 * @pipe: pipe to enable
040484af 1725 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1726 *
1727 * Enable @pipe, making sure that various hardware specific requirements
1728 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1729 *
1730 * @pipe should be %PIPE_A or %PIPE_B.
1731 *
1732 * Will wait until the pipe is actually running (i.e. first vblank) before
1733 * returning.
1734 */
040484af
JB		 1735static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1736 bool pch_port)
b24e7179
JB		 1737{
1738 int reg;
1739 u32 val;
1740
1741 /*
1742 * A pipe without a PLL won't actually be able to drive bits from
1743 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1744 * need the check.
1745 */
1746 if (!HAS_PCH_SPLIT(dev_priv->dev))
1747 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1748 else {
1749 if (pch_port) {
1750 /* if driving the PCH, we need FDI enabled */
1751 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1752 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1753 }
1754 /* FIXME: assert CPU port conditions for SNB+ */
1755 }
b24e7179
JB		 1756
1757 reg = PIPECONF(pipe);
1758 val = I915_READ(reg);
00d70b15
CW		 1759 if (val & PIPECONF_ENABLE)
1760 return;
1761
1762 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1763 intel_wait_for_vblank(dev_priv->dev, pipe);
1764}
1765
1766/**
309cfea8 1767 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1768 * @dev_priv: i915 private structure
1769 * @pipe: pipe to disable
1770 *
1771 * Disable @pipe, making sure that various hardware specific requirements
1772 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1773 *
1774 * @pipe should be %PIPE_A or %PIPE_B.
1775 *
1776 * Will wait until the pipe has shut down before returning.
1777 */
1778static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1779 enum pipe pipe)
1780{
1781 int reg;
1782 u32 val;
1783
1784 /*
1785 * Make sure planes won't keep trying to pump pixels to us,
1786 * or we might hang the display.
1787 */
1788 assert_planes_disabled(dev_priv, pipe);
1789
1790 /* Don't disable pipe A or pipe A PLLs if needed */
1791 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1792 return;
1793
1794 reg = PIPECONF(pipe);
1795 val = I915_READ(reg);
00d70b15
CW		 1796 if ((val & PIPECONF_ENABLE) == 0)
1797 return;
1798
1799 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1800 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1801}
1802
d74362c9
KP		 1803/*
1804 * Plane regs are double buffered, going from enabled->disabled needs a
1805 * trigger in order to latch. The display address reg provides this.
1806 */
6f1d69b0 1807void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1808 enum plane plane)
1809{
1810 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1811 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1812}
1813
b24e7179
JB		 1814/**
1815 * intel_enable_plane - enable a display plane on a given pipe
1816 * @dev_priv: i915 private structure
1817 * @plane: plane to enable
1818 * @pipe: pipe being fed
1819 *
1820 * Enable @plane on @pipe, making sure that @pipe is running first.
1821 */
1822static void intel_enable_plane(struct drm_i915_private *dev_priv,
1823 enum plane plane, enum pipe pipe)
1824{
1825 int reg;
1826 u32 val;
1827
1828 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1829 assert_pipe_enabled(dev_priv, pipe);
1830
1831 reg = DSPCNTR(plane);
1832 val = I915_READ(reg);
00d70b15
CW		 1833 if (val & DISPLAY_PLANE_ENABLE)
1834 return;
1835
1836 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1837 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1838 intel_wait_for_vblank(dev_priv->dev, pipe);
1839}
1840
b24e7179
JB		 1841/**
1842 * intel_disable_plane - disable a display plane
1843 * @dev_priv: i915 private structure
1844 * @plane: plane to disable
1845 * @pipe: pipe consuming the data
1846 *
1847 * Disable @plane; should be an independent operation.
1848 */
1849static void intel_disable_plane(struct drm_i915_private *dev_priv,
1850 enum plane plane, enum pipe pipe)
1851{
1852 int reg;
1853 u32 val;
1854
1855 reg = DSPCNTR(plane);
1856 val = I915_READ(reg);
00d70b15
CW		 1857 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1858 return;
1859
1860 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1861 intel_flush_display_plane(dev_priv, plane);
1862 intel_wait_for_vblank(dev_priv->dev, pipe);
1863}
1864
127bd2ac 1865int
48b956c5 1866intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1867 struct drm_i915_gem_object *obj,
919926ae 1868 struct intel_ring_buffer *pipelined)
6b95a207 1869{
ce453d81 1870 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1871 u32 alignment;
1872 int ret;
1873
05394f39 1874 switch (obj->tiling_mode) {
6b95a207 1875 case I915_TILING_NONE:
534843da
CW		 1876 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1877 alignment = 128 * 1024;
a6c45cf0 1878 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1879 alignment = 4 * 1024;
1880 else
1881 alignment = 64 * 1024;
6b95a207
KH		 1882 break;
1883 case I915_TILING_X:
1884 /* pin() will align the object as required by fence */
1885 alignment = 0;
1886 break;
1887 case I915_TILING_Y:
1888 /* FIXME: Is this true? */
1889 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1890 return -EINVAL;
1891 default:
1892 BUG();
1893 }
1894
ce453d81 1895 dev_priv->mm.interruptible = false;
2da3b9b9 1896 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1897 if (ret)
ce453d81 1898 goto err_interruptible;
6b95a207
KH		 1899
1900 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1901 * fence, whereas 965+ only requires a fence if using
1902 * framebuffer compression. For simplicity, we always install
1903 * a fence as the cost is not that onerous.
1904 */
06d98131 1905 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1906 if (ret)
1907 goto err_unpin;
1690e1eb 1908
9a5a53b3 1909 i915_gem_object_pin_fence(obj);
6b95a207 1910
ce453d81 1911 dev_priv->mm.interruptible = true;
6b95a207 1912 return 0;
48b956c5
CW		 1913
1914err_unpin:
1915 i915_gem_object_unpin(obj);
ce453d81
CW		 1916err_interruptible:
1917 dev_priv->mm.interruptible = true;
48b956c5 1918 return ret;
6b95a207
KH		 1919}
1920
1690e1eb
CW		 1921void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1922{
1923 i915_gem_object_unpin_fence(obj);
1924 i915_gem_object_unpin(obj);
1925}
1926
c2c75131
DV		 1927/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1928 * is assumed to be a power-of-two. */
1929static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1930 unsigned int bpp,
1931 unsigned int pitch)
1932{
1933 int tile_rows, tiles;
1934
1935 tile_rows = *y / 8;
1936 *y %= 8;
1937 tiles = *x / (512/bpp);
1938 *x %= 512/bpp;
1939
1940 return tile_rows * pitch * 8 + tiles * 4096;
1941}
1942
17638cd6
JB		 1943static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1944 int x, int y)
81255565
JB		 1945{
1946 struct drm_device *dev = crtc->dev;
1947 struct drm_i915_private *dev_priv = dev->dev_private;
1948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949 struct intel_framebuffer *intel_fb;
05394f39 1950 struct drm_i915_gem_object *obj;
81255565 1951 int plane = intel_crtc->plane;
e506a0c6 1952 unsigned long linear_offset;
81255565 1953 u32 dspcntr;
5eddb70b 1954 u32 reg;
81255565
JB		 1955
1956 switch (plane) {
1957 case 0:
1958 case 1:
1959 break;
1960 default:
1961 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1962 return -EINVAL;
1963 }
1964
1965 intel_fb = to_intel_framebuffer(fb);
1966 obj = intel_fb->obj;
81255565 1967
5eddb70b
CW		 1968 reg = DSPCNTR(plane);
1969 dspcntr = I915_READ(reg);
81255565
JB		 1970 /* Mask out pixel format bits in case we change it */
1971 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1972 switch (fb->bits_per_pixel) {
1973 case 8:
1974 dspcntr |= DISPPLANE_8BPP;
1975 break;
1976 case 16:
1977 if (fb->depth == 15)
1978 dspcntr |= DISPPLANE_15_16BPP;
1979 else
1980 dspcntr |= DISPPLANE_16BPP;
1981 break;
1982 case 24:
1983 case 32:
1984 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1985 break;
1986 default:
17638cd6 1987 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 1988 return -EINVAL;
1989 }
a6c45cf0 1990 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1991 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1992 dspcntr |= DISPPLANE_TILED;
1993 else
1994 dspcntr &= ~DISPPLANE_TILED;
1995 }
1996
5eddb70b 1997 I915_WRITE(reg, dspcntr);
81255565 1998
e506a0c6 1999 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2000
c2c75131
DV		 2001 if (INTEL_INFO(dev)->gen >= 4) {
2002 intel_crtc->dspaddr_offset =
2003 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2004 fb->bits_per_pixel / 8,
2005 fb->pitches[0]);
2006 linear_offset -= intel_crtc->dspaddr_offset;
2007 } else {
e506a0c6 2008 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2009 }
e506a0c6
DV		 2010
2011 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2012 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2013 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2014 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2015 I915_MODIFY_DISPBASE(DSPSURF(plane),
2016 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2017 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2018 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2019 } else
e506a0c6 2020 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2021 POSTING_READ(reg);
81255565 2022
17638cd6
JB		 2023 return 0;
2024}
2025
2026static int ironlake_update_plane(struct drm_crtc *crtc,
2027 struct drm_framebuffer *fb, int x, int y)
2028{
2029 struct drm_device *dev = crtc->dev;
2030 struct drm_i915_private *dev_priv = dev->dev_private;
2031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2032 struct intel_framebuffer *intel_fb;
2033 struct drm_i915_gem_object *obj;
2034 int plane = intel_crtc->plane;
e506a0c6 2035 unsigned long linear_offset;
17638cd6
JB		 2036 u32 dspcntr;
2037 u32 reg;
2038
2039 switch (plane) {
2040 case 0:
2041 case 1:
27f8227b 2042 case 2:
17638cd6
JB		 2043 break;
2044 default:
2045 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2046 return -EINVAL;
2047 }
2048
2049 intel_fb = to_intel_framebuffer(fb);
2050 obj = intel_fb->obj;
2051
2052 reg = DSPCNTR(plane);
2053 dspcntr = I915_READ(reg);
2054 /* Mask out pixel format bits in case we change it */
2055 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2056 switch (fb->bits_per_pixel) {
2057 case 8:
2058 dspcntr |= DISPPLANE_8BPP;
2059 break;
2060 case 16:
2061 if (fb->depth != 16)
2062 return -EINVAL;
2063
2064 dspcntr |= DISPPLANE_16BPP;
2065 break;
2066 case 24:
2067 case 32:
2068 if (fb->depth == 24)
2069 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2070 else if (fb->depth == 30)
2071 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2072 else
2073 return -EINVAL;
2074 break;
2075 default:
2076 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2077 return -EINVAL;
2078 }
2079
2080 if (obj->tiling_mode != I915_TILING_NONE)
2081 dspcntr |= DISPPLANE_TILED;
2082 else
2083 dspcntr &= ~DISPPLANE_TILED;
2084
2085 /* must disable */
2086 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2087
2088 I915_WRITE(reg, dspcntr);
2089
e506a0c6 2090 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131
DV		 2091 intel_crtc->dspaddr_offset =
2092 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2093 fb->bits_per_pixel / 8,
2094 fb->pitches[0]);
2095 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2096
e506a0c6
DV		 2097 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2098 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2099 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2100 I915_MODIFY_DISPBASE(DSPSURF(plane),
2101 obj->gtt_offset + intel_crtc->dspaddr_offset);
17638cd6 2102 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2103 I915_WRITE(DSPLINOFF(plane), linear_offset);
17638cd6
JB		 2104 POSTING_READ(reg);
2105
2106 return 0;
2107}
2108
2109/* Assume fb object is pinned & idle & fenced and just update base pointers */
2110static int
2111intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2112 int x, int y, enum mode_set_atomic state)
2113{
2114 struct drm_device *dev = crtc->dev;
2115 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2116
6b8e6ed0
CW		 2117 if (dev_priv->display.disable_fbc)
2118 dev_priv->display.disable_fbc(dev);
3dec0095 2119 intel_increase_pllclock(crtc);
81255565 2120
6b8e6ed0 2121 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2122}
2123
14667a4b
CW		 2124static int
2125intel_finish_fb(struct drm_framebuffer *old_fb)
2126{
2127 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2128 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2129 bool was_interruptible = dev_priv->mm.interruptible;
2130 int ret;
2131
2132 wait_event(dev_priv->pending_flip_queue,
2133 atomic_read(&dev_priv->mm.wedged) ||
2134 atomic_read(&obj->pending_flip) == 0);
2135
2136 /* Big Hammer, we also need to ensure that any pending
2137 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2138 * current scanout is retired before unpinning the old
2139 * framebuffer.
2140 *
2141 * This should only fail upon a hung GPU, in which case we
2142 * can safely continue.
2143 */
2144 dev_priv->mm.interruptible = false;
2145 ret = i915_gem_object_finish_gpu(obj);
2146 dev_priv->mm.interruptible = was_interruptible;
2147
2148 return ret;
2149}
2150
5c3b82e2 2151static int
3c4fdcfb 2152intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2153 struct drm_framebuffer *fb)
79e53945
JB		 2154{
2155 struct drm_device *dev = crtc->dev;
6b8e6ed0 2156 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2157 struct drm_i915_master_private *master_priv;
2158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2159 struct drm_framebuffer *old_fb;
5c3b82e2 2160 int ret;
79e53945
JB		 2161
2162 /* no fb bound */
94352cf9 2163 if (!fb) {
a5071c2f 2164 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2165 return 0;
2166 }
2167
5826eca5
ED		 2168 if(intel_crtc->plane > dev_priv->num_pipe) {
2169 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2170 intel_crtc->plane,
2171 dev_priv->num_pipe);
5c3b82e2 2172 return -EINVAL;
79e53945
JB		 2173 }
2174
5c3b82e2 2175 mutex_lock(&dev->struct_mutex);
265db958 2176 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2177 to_intel_framebuffer(fb)->obj,
919926ae 2178 NULL);
5c3b82e2
CW		 2179 if (ret != 0) {
2180 mutex_unlock(&dev->struct_mutex);
a5071c2f 2181 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2182 return ret;
2183 }
79e53945 2184
94352cf9
DV		 2185 if (crtc->fb)
2186 intel_finish_fb(crtc->fb);
265db958 2187
94352cf9 2188 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2189 if (ret) {
94352cf9 2190 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2191 mutex_unlock(&dev->struct_mutex);
a5071c2f 2192 DRM_ERROR("failed to update base address\n");
4e6cfefc 2193 return ret;
79e53945 2194 }
3c4fdcfb 2195
94352cf9
DV		 2196 old_fb = crtc->fb;
2197 crtc->fb = fb;
6c4c86f5
DV		 2198 crtc->x = x;
2199 crtc->y = y;
94352cf9 2200
b7f1de28
CW		 2201 if (old_fb) {
2202 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2203 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2204 }
652c393a 2205
6b8e6ed0 2206 intel_update_fbc(dev);
5c3b82e2 2207 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2208
2209 if (!dev->primary->master)
5c3b82e2 2210 return 0;
79e53945
JB		 2211
2212 master_priv = dev->primary->master->driver_priv;
2213 if (!master_priv->sarea_priv)
5c3b82e2 2214 return 0;
79e53945 2215
265db958 2216 if (intel_crtc->pipe) {
79e53945
JB		 2217 master_priv->sarea_priv->pipeB_x = x;
2218 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2219 } else {
2220 master_priv->sarea_priv->pipeA_x = x;
2221 master_priv->sarea_priv->pipeA_y = y;
79e53945 2222 }
5c3b82e2
CW		 2223
2224 return 0;
79e53945
JB		 2225}
2226
5eddb70b 2227static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2228{
2229 struct drm_device *dev = crtc->dev;
2230 struct drm_i915_private *dev_priv = dev->dev_private;
2231 u32 dpa_ctl;
2232
28c97730 2233 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2234 dpa_ctl = I915_READ(DP_A);
2235 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2236
2237 if (clock < 200000) {
2238 u32 temp;
2239 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2240 /* workaround for 160Mhz:
2241 1) program 0x4600c bits 15:0 = 0x8124
2242 2) program 0x46010 bit 0 = 1
2243 3) program 0x46034 bit 24 = 1
2244 4) program 0x64000 bit 14 = 1
2245 */
2246 temp = I915_READ(0x4600c);
2247 temp &= 0xffff0000;
2248 I915_WRITE(0x4600c, temp | 0x8124);
2249
2250 temp = I915_READ(0x46010);
2251 I915_WRITE(0x46010, temp | 1);
2252
2253 temp = I915_READ(0x46034);
2254 I915_WRITE(0x46034, temp | (1 << 24));
2255 } else {
2256 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2257 }
2258 I915_WRITE(DP_A, dpa_ctl);
2259
5eddb70b 2260 POSTING_READ(DP_A);
32f9d658
ZW		 2261 udelay(500);
2262}
2263
5e84e1a4
ZW		 2264static void intel_fdi_normal_train(struct drm_crtc *crtc)
2265{
2266 struct drm_device *dev = crtc->dev;
2267 struct drm_i915_private *dev_priv = dev->dev_private;
2268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269 int pipe = intel_crtc->pipe;
2270 u32 reg, temp;
2271
2272 /* enable normal train */
2273 reg = FDI_TX_CTL(pipe);
2274 temp = I915_READ(reg);
61e499bf 2275 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2276 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2277 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2278 } else {
2279 temp &= ~FDI_LINK_TRAIN_NONE;
2280 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2281 }
5e84e1a4
ZW		 2282 I915_WRITE(reg, temp);
2283
2284 reg = FDI_RX_CTL(pipe);
2285 temp = I915_READ(reg);
2286 if (HAS_PCH_CPT(dev)) {
2287 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2288 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2289 } else {
2290 temp &= ~FDI_LINK_TRAIN_NONE;
2291 temp |= FDI_LINK_TRAIN_NONE;
2292 }
2293 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2294
2295 /* wait one idle pattern time */
2296 POSTING_READ(reg);
2297 udelay(1000);
357555c0
JB		 2298
2299 /* IVB wants error correction enabled */
2300 if (IS_IVYBRIDGE(dev))
2301 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2302 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2303}
2304
291427f5
JB		 2305static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2306{
2307 struct drm_i915_private *dev_priv = dev->dev_private;
2308 u32 flags = I915_READ(SOUTH_CHICKEN1);
2309
2310 flags |= FDI_PHASE_SYNC_OVR(pipe);
2311 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2312 flags |= FDI_PHASE_SYNC_EN(pipe);
2313 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2314 POSTING_READ(SOUTH_CHICKEN1);
2315}
2316
8db9d77b
ZW		 2317/* The FDI link training functions for ILK/Ibexpeak. */
2318static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2319{
2320 struct drm_device *dev = crtc->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323 int pipe = intel_crtc->pipe;
0fc932b8 2324 int plane = intel_crtc->plane;
5eddb70b 2325 u32 reg, temp, tries;
8db9d77b 2326
0fc932b8
JB		 2327 /* FDI needs bits from pipe & plane first */
2328 assert_pipe_enabled(dev_priv, pipe);
2329 assert_plane_enabled(dev_priv, plane);
2330
e1a44743
AJ		 2331 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2332 for train result */
5eddb70b
CW		 2333 reg = FDI_RX_IMR(pipe);
2334 temp = I915_READ(reg);
e1a44743
AJ		 2335 temp &= ~FDI_RX_SYMBOL_LOCK;
2336 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2337 I915_WRITE(reg, temp);
2338 I915_READ(reg);
e1a44743
AJ		 2339 udelay(150);
2340
8db9d77b 2341 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2342 reg = FDI_TX_CTL(pipe);
2343 temp = I915_READ(reg);
77ffb597
AJ		 2344 temp &= ~(7 << 19);
2345 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2348 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2349
5eddb70b
CW		 2350 reg = FDI_RX_CTL(pipe);
2351 temp = I915_READ(reg);
8db9d77b
ZW		 2352 temp &= ~FDI_LINK_TRAIN_NONE;
2353 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2354 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2355
2356 POSTING_READ(reg);
8db9d77b
ZW		 2357 udelay(150);
2358
5b2adf89 2359 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2360 if (HAS_PCH_IBX(dev)) {
2361 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2362 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2363 FDI_RX_PHASE_SYNC_POINTER_EN);
2364 }
5b2adf89 2365
5eddb70b 2366 reg = FDI_RX_IIR(pipe);
e1a44743 2367 for (tries = 0; tries < 5; tries++) {
5eddb70b 2368 temp = I915_READ(reg);
8db9d77b
ZW		 2369 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2370
2371 if ((temp & FDI_RX_BIT_LOCK)) {
2372 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2373 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2374 break;
2375 }
8db9d77b 2376 }
e1a44743 2377 if (tries == 5)
5eddb70b 2378 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2379
2380 /* Train 2 */
5eddb70b
CW		 2381 reg = FDI_TX_CTL(pipe);
2382 temp = I915_READ(reg);
8db9d77b
ZW		 2383 temp &= ~FDI_LINK_TRAIN_NONE;
2384 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2385 I915_WRITE(reg, temp);
8db9d77b 2386
5eddb70b
CW		 2387 reg = FDI_RX_CTL(pipe);
2388 temp = I915_READ(reg);
8db9d77b
ZW		 2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2391 I915_WRITE(reg, temp);
8db9d77b 2392
5eddb70b
CW		 2393 POSTING_READ(reg);
2394 udelay(150);
8db9d77b 2395
5eddb70b 2396 reg = FDI_RX_IIR(pipe);
e1a44743 2397 for (tries = 0; tries < 5; tries++) {
5eddb70b 2398 temp = I915_READ(reg);
8db9d77b
ZW		 2399 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2400
2401 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2402 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2403 DRM_DEBUG_KMS("FDI train 2 done.\n");
2404 break;
2405 }
8db9d77b 2406 }
e1a44743 2407 if (tries == 5)
5eddb70b 2408 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2409
2410 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2411
8db9d77b
ZW		 2412}
2413
0206e353 2414static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2415 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2416 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2417 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2418 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2419};
2420
2421/* The FDI link training functions for SNB/Cougarpoint. */
2422static void gen6_fdi_link_train(struct drm_crtc *crtc)
2423{
2424 struct drm_device *dev = crtc->dev;
2425 struct drm_i915_private *dev_priv = dev->dev_private;
2426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2427 int pipe = intel_crtc->pipe;
fa37d39e 2428 u32 reg, temp, i, retry;
8db9d77b 2429
e1a44743
AJ		 2430 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2431 for train result */
5eddb70b
CW		 2432 reg = FDI_RX_IMR(pipe);
2433 temp = I915_READ(reg);
e1a44743
AJ		 2434 temp &= ~FDI_RX_SYMBOL_LOCK;
2435 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2436 I915_WRITE(reg, temp);
2437
2438 POSTING_READ(reg);
e1a44743
AJ		 2439 udelay(150);
2440
8db9d77b 2441 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2442 reg = FDI_TX_CTL(pipe);
2443 temp = I915_READ(reg);
77ffb597
AJ		 2444 temp &= ~(7 << 19);
2445 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_1;
2448 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2449 /* SNB-B */
2450 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2451 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2452
5eddb70b
CW		 2453 reg = FDI_RX_CTL(pipe);
2454 temp = I915_READ(reg);
8db9d77b
ZW		 2455 if (HAS_PCH_CPT(dev)) {
2456 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2457 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2458 } else {
2459 temp &= ~FDI_LINK_TRAIN_NONE;
2460 temp |= FDI_LINK_TRAIN_PATTERN_1;
2461 }
5eddb70b
CW		 2462 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2463
2464 POSTING_READ(reg);
8db9d77b
ZW		 2465 udelay(150);
2466
291427f5
JB		 2467 if (HAS_PCH_CPT(dev))
2468 cpt_phase_pointer_enable(dev, pipe);
2469
0206e353 2470 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2471 reg = FDI_TX_CTL(pipe);
2472 temp = I915_READ(reg);
8db9d77b
ZW		 2473 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2474 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2475 I915_WRITE(reg, temp);
2476
2477 POSTING_READ(reg);
8db9d77b
ZW		 2478 udelay(500);
2479
fa37d39e
SP		 2480 for (retry = 0; retry < 5; retry++) {
2481 reg = FDI_RX_IIR(pipe);
2482 temp = I915_READ(reg);
2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484 if (temp & FDI_RX_BIT_LOCK) {
2485 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2486 DRM_DEBUG_KMS("FDI train 1 done.\n");
2487 break;
2488 }
2489 udelay(50);
8db9d77b 2490 }
fa37d39e
SP		 2491 if (retry < 5)
2492 break;
8db9d77b
ZW		 2493 }
2494 if (i == 4)
5eddb70b 2495 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2496
2497 /* Train 2 */
5eddb70b
CW		 2498 reg = FDI_TX_CTL(pipe);
2499 temp = I915_READ(reg);
8db9d77b
ZW		 2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_2;
2502 if (IS_GEN6(dev)) {
2503 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2504 /* SNB-B */
2505 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2506 }
5eddb70b 2507 I915_WRITE(reg, temp);
8db9d77b 2508
5eddb70b
CW		 2509 reg = FDI_RX_CTL(pipe);
2510 temp = I915_READ(reg);
8db9d77b
ZW		 2511 if (HAS_PCH_CPT(dev)) {
2512 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2513 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2514 } else {
2515 temp &= ~FDI_LINK_TRAIN_NONE;
2516 temp |= FDI_LINK_TRAIN_PATTERN_2;
2517 }
5eddb70b
CW		 2518 I915_WRITE(reg, temp);
2519
2520 POSTING_READ(reg);
8db9d77b
ZW		 2521 udelay(150);
2522
0206e353 2523 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2524 reg = FDI_TX_CTL(pipe);
2525 temp = I915_READ(reg);
8db9d77b
ZW		 2526 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2528 I915_WRITE(reg, temp);
2529
2530 POSTING_READ(reg);
8db9d77b
ZW		 2531 udelay(500);
2532
fa37d39e
SP		 2533 for (retry = 0; retry < 5; retry++) {
2534 reg = FDI_RX_IIR(pipe);
2535 temp = I915_READ(reg);
2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537 if (temp & FDI_RX_SYMBOL_LOCK) {
2538 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2539 DRM_DEBUG_KMS("FDI train 2 done.\n");
2540 break;
2541 }
2542 udelay(50);
8db9d77b 2543 }
fa37d39e
SP		 2544 if (retry < 5)
2545 break;
8db9d77b
ZW		 2546 }
2547 if (i == 4)
5eddb70b 2548 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2549
2550 DRM_DEBUG_KMS("FDI train done.\n");
2551}
2552
357555c0
JB		 2553/* Manual link training for Ivy Bridge A0 parts */
2554static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2555{
2556 struct drm_device *dev = crtc->dev;
2557 struct drm_i915_private *dev_priv = dev->dev_private;
2558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2559 int pipe = intel_crtc->pipe;
2560 u32 reg, temp, i;
2561
2562 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2563 for train result */
2564 reg = FDI_RX_IMR(pipe);
2565 temp = I915_READ(reg);
2566 temp &= ~FDI_RX_SYMBOL_LOCK;
2567 temp &= ~FDI_RX_BIT_LOCK;
2568 I915_WRITE(reg, temp);
2569
2570 POSTING_READ(reg);
2571 udelay(150);
2572
2573 /* enable CPU FDI TX and PCH FDI RX */
2574 reg = FDI_TX_CTL(pipe);
2575 temp = I915_READ(reg);
2576 temp &= ~(7 << 19);
2577 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2578 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2579 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2580 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2581 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2582 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2583 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2584
2585 reg = FDI_RX_CTL(pipe);
2586 temp = I915_READ(reg);
2587 temp &= ~FDI_LINK_TRAIN_AUTO;
2588 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2590 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2591 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2592
2593 POSTING_READ(reg);
2594 udelay(150);
2595
291427f5
JB		 2596 if (HAS_PCH_CPT(dev))
2597 cpt_phase_pointer_enable(dev, pipe);
2598
0206e353 2599 for (i = 0; i < 4; i++) {
357555c0
JB		 2600 reg = FDI_TX_CTL(pipe);
2601 temp = I915_READ(reg);
2602 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603 temp |= snb_b_fdi_train_param[i];
2604 I915_WRITE(reg, temp);
2605
2606 POSTING_READ(reg);
2607 udelay(500);
2608
2609 reg = FDI_RX_IIR(pipe);
2610 temp = I915_READ(reg);
2611 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2612
2613 if (temp & FDI_RX_BIT_LOCK ||
2614 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2615 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2616 DRM_DEBUG_KMS("FDI train 1 done.\n");
2617 break;
2618 }
2619 }
2620 if (i == 4)
2621 DRM_ERROR("FDI train 1 fail!\n");
2622
2623 /* Train 2 */
2624 reg = FDI_TX_CTL(pipe);
2625 temp = I915_READ(reg);
2626 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2627 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2628 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2629 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2630 I915_WRITE(reg, temp);
2631
2632 reg = FDI_RX_CTL(pipe);
2633 temp = I915_READ(reg);
2634 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2636 I915_WRITE(reg, temp);
2637
2638 POSTING_READ(reg);
2639 udelay(150);
2640
0206e353 2641 for (i = 0; i < 4; i++) {
357555c0
JB		 2642 reg = FDI_TX_CTL(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645 temp |= snb_b_fdi_train_param[i];
2646 I915_WRITE(reg, temp);
2647
2648 POSTING_READ(reg);
2649 udelay(500);
2650
2651 reg = FDI_RX_IIR(pipe);
2652 temp = I915_READ(reg);
2653 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2654
2655 if (temp & FDI_RX_SYMBOL_LOCK) {
2656 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2657 DRM_DEBUG_KMS("FDI train 2 done.\n");
2658 break;
2659 }
2660 }
2661 if (i == 4)
2662 DRM_ERROR("FDI train 2 fail!\n");
2663
2664 DRM_DEBUG_KMS("FDI train done.\n");
2665}
2666
88cefb6c 2667static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2668{
88cefb6c 2669 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2670 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2671 int pipe = intel_crtc->pipe;
5eddb70b 2672 u32 reg, temp;
79e53945 2673
c64e311e 2674 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2675 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2676 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2677
c98e9dcf 2678 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2679 reg = FDI_RX_CTL(pipe);
2680 temp = I915_READ(reg);
2681 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2682 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2683 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2684 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2685
2686 POSTING_READ(reg);
c98e9dcf
JB		 2687 udelay(200);
2688
2689 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2690 temp = I915_READ(reg);
2691 I915_WRITE(reg, temp | FDI_PCDCLK);
2692
2693 POSTING_READ(reg);
c98e9dcf
JB		 2694 udelay(200);
2695
bf507ef7
ED		 2696 /* On Haswell, the PLL configuration for ports and pipes is handled
2697 * separately, as part of DDI setup */
2698 if (!IS_HASWELL(dev)) {
2699 /* Enable CPU FDI TX PLL, always on for Ironlake */
2700 reg = FDI_TX_CTL(pipe);
2701 temp = I915_READ(reg);
2702 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2703 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2704
bf507ef7
ED		 2705 POSTING_READ(reg);
2706 udelay(100);
2707 }
6be4a607 2708 }
0e23b99d
JB		 2709}
2710
88cefb6c
DV		 2711static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2712{
2713 struct drm_device *dev = intel_crtc->base.dev;
2714 struct drm_i915_private *dev_priv = dev->dev_private;
2715 int pipe = intel_crtc->pipe;
2716 u32 reg, temp;
2717
2718 /* Switch from PCDclk to Rawclk */
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2722
2723 /* Disable CPU FDI TX PLL */
2724 reg = FDI_TX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2727
2728 POSTING_READ(reg);
2729 udelay(100);
2730
2731 reg = FDI_RX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2734
2735 /* Wait for the clocks to turn off. */
2736 POSTING_READ(reg);
2737 udelay(100);
2738}
2739
291427f5
JB		 2740static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2741{
2742 struct drm_i915_private *dev_priv = dev->dev_private;
2743 u32 flags = I915_READ(SOUTH_CHICKEN1);
2744
2745 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2746 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2747 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2748 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2749 POSTING_READ(SOUTH_CHICKEN1);
2750}
0fc932b8
JB		 2751static void ironlake_fdi_disable(struct drm_crtc *crtc)
2752{
2753 struct drm_device *dev = crtc->dev;
2754 struct drm_i915_private *dev_priv = dev->dev_private;
2755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2756 int pipe = intel_crtc->pipe;
2757 u32 reg, temp;
2758
2759 /* disable CPU FDI tx and PCH FDI rx */
2760 reg = FDI_TX_CTL(pipe);
2761 temp = I915_READ(reg);
2762 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2763 POSTING_READ(reg);
2764
2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 temp &= ~(0x7 << 16);
2768 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2769 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2770
2771 POSTING_READ(reg);
2772 udelay(100);
2773
2774 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2775 if (HAS_PCH_IBX(dev)) {
2776 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2777 I915_WRITE(FDI_RX_CHICKEN(pipe),
2778 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2779 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2780 } else if (HAS_PCH_CPT(dev)) {
2781 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2782 }
0fc932b8
JB		 2783
2784 /* still set train pattern 1 */
2785 reg = FDI_TX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 temp &= ~FDI_LINK_TRAIN_NONE;
2788 temp |= FDI_LINK_TRAIN_PATTERN_1;
2789 I915_WRITE(reg, temp);
2790
2791 reg = FDI_RX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 if (HAS_PCH_CPT(dev)) {
2794 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2795 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2796 } else {
2797 temp &= ~FDI_LINK_TRAIN_NONE;
2798 temp |= FDI_LINK_TRAIN_PATTERN_1;
2799 }
2800 /* BPC in FDI rx is consistent with that in PIPECONF */
2801 temp &= ~(0x07 << 16);
2802 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2803 I915_WRITE(reg, temp);
2804
2805 POSTING_READ(reg);
2806 udelay(100);
2807}
2808
e6c3a2a6
CW		 2809static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2810{
0f91128d 2811 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2812
2813 if (crtc->fb == NULL)
2814 return;
2815
0f91128d
CW		 2816 mutex_lock(&dev->struct_mutex);
2817 intel_finish_fb(crtc->fb);
2818 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2819}
2820
040484af
JB		 2821static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2822{
2823 struct drm_device *dev = crtc->dev;
228d3e36 2824 struct intel_encoder *intel_encoder;
040484af
JB		 2825
2826 /*
2827 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2828 * must be driven by its own crtc; no sharing is possible.
2829 */
228d3e36 2830 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
040484af 2831
6ee8bab0
ED		 2832 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2833 * CPU handles all others */
2834 if (IS_HASWELL(dev)) {
2835 /* It is still unclear how this will work on PPT, so throw up a warning */
2836 WARN_ON(!HAS_PCH_LPT(dev));
2837
228d3e36 2838 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
6ee8bab0
ED		 2839 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2840 return true;
2841 } else {
2842 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
228d3e36 2843 intel_encoder->type);
6ee8bab0
ED		 2844 return false;
2845 }
2846 }
2847
228d3e36 2848 switch (intel_encoder->type) {
040484af 2849 case INTEL_OUTPUT_EDP:
228d3e36 2850 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2851 return false;
2852 continue;
2853 }
2854 }
2855
2856 return true;
2857}
2858
e615efe4
ED		 2859/* Program iCLKIP clock to the desired frequency */
2860static void lpt_program_iclkip(struct drm_crtc *crtc)
2861{
2862 struct drm_device *dev = crtc->dev;
2863 struct drm_i915_private *dev_priv = dev->dev_private;
2864 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2865 u32 temp;
2866
2867 /* It is necessary to ungate the pixclk gate prior to programming
2868 * the divisors, and gate it back when it is done.
2869 */
2870 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2871
2872 /* Disable SSCCTL */
2873 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2874 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2875 SBI_SSCCTL_DISABLE);
2876
2877 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2878 if (crtc->mode.clock == 20000) {
2879 auxdiv = 1;
2880 divsel = 0x41;
2881 phaseinc = 0x20;
2882 } else {
2883 /* The iCLK virtual clock root frequency is in MHz,
2884 * but the crtc->mode.clock in in KHz. To get the divisors,
2885 * it is necessary to divide one by another, so we
2886 * convert the virtual clock precision to KHz here for higher
2887 * precision.
2888 */
2889 u32 iclk_virtual_root_freq = 172800 * 1000;
2890 u32 iclk_pi_range = 64;
2891 u32 desired_divisor, msb_divisor_value, pi_value;
2892
2893 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2894 msb_divisor_value = desired_divisor / iclk_pi_range;
2895 pi_value = desired_divisor % iclk_pi_range;
2896
2897 auxdiv = 0;
2898 divsel = msb_divisor_value - 2;
2899 phaseinc = pi_value;
2900 }
2901
2902 /* This should not happen with any sane values */
2903 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2904 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2905 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2906 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2907
2908 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2909 crtc->mode.clock,
2910 auxdiv,
2911 divsel,
2912 phasedir,
2913 phaseinc);
2914
2915 /* Program SSCDIVINTPHASE6 */
2916 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2917 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2918 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2919 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2920 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2921 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2922 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2923
2924 intel_sbi_write(dev_priv,
2925 SBI_SSCDIVINTPHASE6,
2926 temp);
2927
2928 /* Program SSCAUXDIV */
2929 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2930 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2931 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2932 intel_sbi_write(dev_priv,
2933 SBI_SSCAUXDIV6,
2934 temp);
2935
2936
2937 /* Enable modulator and associated divider */
2938 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2939 temp &= ~SBI_SSCCTL_DISABLE;
2940 intel_sbi_write(dev_priv,
2941 SBI_SSCCTL6,
2942 temp);
2943
2944 /* Wait for initialization time */
2945 udelay(24);
2946
2947 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2948}
2949
f67a559d
JB		 2950/*
2951 * Enable PCH resources required for PCH ports:
2952 * - PCH PLLs
2953 * - FDI training & RX/TX
2954 * - update transcoder timings
2955 * - DP transcoding bits
2956 * - transcoder
2957 */
2958static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2959{
2960 struct drm_device *dev = crtc->dev;
2961 struct drm_i915_private *dev_priv = dev->dev_private;
2962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963 int pipe = intel_crtc->pipe;
ee7b9f93 2964 u32 reg, temp;
2c07245f 2965
e7e164db
CW		 2966 assert_transcoder_disabled(dev_priv, pipe);
2967
c98e9dcf 2968 /* For PCH output, training FDI link */
674cf967 2969 dev_priv->display.fdi_link_train(crtc);
2c07245f 2970
6f13b7b5
CW		 2971 intel_enable_pch_pll(intel_crtc);
2972
e615efe4
ED		 2973 if (HAS_PCH_LPT(dev)) {
2974 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2975 lpt_program_iclkip(crtc);
2976 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 2977 u32 sel;
4b645f14 2978
c98e9dcf 2979 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2980 switch (pipe) {
2981 default:
2982 case 0:
2983 temp |= TRANSA_DPLL_ENABLE;
2984 sel = TRANSA_DPLLB_SEL;
2985 break;
2986 case 1:
2987 temp |= TRANSB_DPLL_ENABLE;
2988 sel = TRANSB_DPLLB_SEL;
2989 break;
2990 case 2:
2991 temp |= TRANSC_DPLL_ENABLE;
2992 sel = TRANSC_DPLLB_SEL;
2993 break;
d64311ab 2994 }
ee7b9f93
JB		 2995 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2996 temp |= sel;
2997 else
2998 temp &= ~sel;
c98e9dcf 2999 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3000 }
5eddb70b 3001
d9b6cb56
JB		 3002 /* set transcoder timing, panel must allow it */
3003 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3004 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3005 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3006 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3007
5eddb70b
CW		 3008 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3009 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3010 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3011 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3012
f57e1e3a
ED		 3013 if (!IS_HASWELL(dev))
3014 intel_fdi_normal_train(crtc);
5e84e1a4 3015
c98e9dcf
JB		 3016 /* For PCH DP, enable TRANS_DP_CTL */
3017 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3018 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3019 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3020 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3021 reg = TRANS_DP_CTL(pipe);
3022 temp = I915_READ(reg);
3023 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3024 TRANS_DP_SYNC_MASK |
3025 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3026 temp |= (TRANS_DP_OUTPUT_ENABLE |
3027 TRANS_DP_ENH_FRAMING);
9325c9f0 3028 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3029
3030 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3031 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3032 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3033 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3034
3035 switch (intel_trans_dp_port_sel(crtc)) {
3036 case PCH_DP_B:
5eddb70b 3037 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3038 break;
3039 case PCH_DP_C:
5eddb70b 3040 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3041 break;
3042 case PCH_DP_D:
5eddb70b 3043 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3044 break;
3045 default:
3046 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3047 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3048 break;
32f9d658 3049 }
2c07245f 3050
5eddb70b 3051 I915_WRITE(reg, temp);
6be4a607 3052 }
b52eb4dc 3053
040484af 3054 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3055}
3056
ee7b9f93
JB		 3057static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3058{
3059 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3060
3061 if (pll == NULL)
3062 return;
3063
3064 if (pll->refcount == 0) {
3065 WARN(1, "bad PCH PLL refcount\n");
3066 return;
3067 }
3068
3069 --pll->refcount;
3070 intel_crtc->pch_pll = NULL;
3071}
3072
3073static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3074{
3075 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3076 struct intel_pch_pll *pll;
3077 int i;
3078
3079 pll = intel_crtc->pch_pll;
3080 if (pll) {
3081 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3082 intel_crtc->base.base.id, pll->pll_reg);
3083 goto prepare;
3084 }
3085
98b6bd99
DV		 3086 if (HAS_PCH_IBX(dev_priv->dev)) {
3087 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3088 i = intel_crtc->pipe;
3089 pll = &dev_priv->pch_plls[i];
3090
3091 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3092 intel_crtc->base.base.id, pll->pll_reg);
3093
3094 goto found;
3095 }
3096
ee7b9f93
JB		 3097 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3098 pll = &dev_priv->pch_plls[i];
3099
3100 /* Only want to check enabled timings first */
3101 if (pll->refcount == 0)
3102 continue;
3103
3104 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3105 fp == I915_READ(pll->fp0_reg)) {
3106 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3107 intel_crtc->base.base.id,
3108 pll->pll_reg, pll->refcount, pll->active);
3109
3110 goto found;
3111 }
3112 }
3113
3114 /* Ok no matching timings, maybe there's a free one? */
3115 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3116 pll = &dev_priv->pch_plls[i];
3117 if (pll->refcount == 0) {
3118 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3119 intel_crtc->base.base.id, pll->pll_reg);
3120 goto found;
3121 }
3122 }
3123
3124 return NULL;
3125
3126found:
3127 intel_crtc->pch_pll = pll;
3128 pll->refcount++;
3129 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3130prepare: /* separate function? */
3131 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3132
e04c7350
CW		 3133 /* Wait for the clocks to stabilize before rewriting the regs */
3134 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3135 POSTING_READ(pll->pll_reg);
3136 udelay(150);
e04c7350
CW		 3137
3138 I915_WRITE(pll->fp0_reg, fp);
3139 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3140 pll->on = false;
3141 return pll;
3142}
3143
d4270e57
JB		 3144void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3145{
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3147 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3148 u32 temp;
3149
3150 temp = I915_READ(dslreg);
3151 udelay(500);
3152 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3153 /* Without this, mode sets may fail silently on FDI */
3154 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3155 udelay(250);
3156 I915_WRITE(tc2reg, 0);
3157 if (wait_for(I915_READ(dslreg) != temp, 5))
3158 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3159 }
3160}
3161
f67a559d
JB		 3162static void ironlake_crtc_enable(struct drm_crtc *crtc)
3163{
3164 struct drm_device *dev = crtc->dev;
3165 struct drm_i915_private *dev_priv = dev->dev_private;
3166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3167 struct intel_encoder *encoder;
f67a559d
JB		 3168 int pipe = intel_crtc->pipe;
3169 int plane = intel_crtc->plane;
3170 u32 temp;
3171 bool is_pch_port;
3172
08a48469
DV		 3173 WARN_ON(!crtc->enabled);
3174
f67a559d
JB		 3175 if (intel_crtc->active)
3176 return;
3177
3178 intel_crtc->active = true;
3179 intel_update_watermarks(dev);
3180
3181 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3182 temp = I915_READ(PCH_LVDS);
3183 if ((temp & LVDS_PORT_EN) == 0)
3184 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3185 }
3186
3187 is_pch_port = intel_crtc_driving_pch(crtc);
3188
46b6f814 3189 if (is_pch_port) {
88cefb6c 3190 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3191 } else {
3192 assert_fdi_tx_disabled(dev_priv, pipe);
3193 assert_fdi_rx_disabled(dev_priv, pipe);
3194 }
f67a559d 3195
bf49ec8c
DV		 3196 for_each_encoder_on_crtc(dev, crtc, encoder)
3197 if (encoder->pre_enable)
3198 encoder->pre_enable(encoder);
3199
f67a559d
JB		 3200 /* Enable panel fitting for LVDS */
3201 if (dev_priv->pch_pf_size &&
3202 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3203 /* Force use of hard-coded filter coefficients
3204 * as some pre-programmed values are broken,
3205 * e.g. x201.
3206 */
9db4a9c7
JB		 3207 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3208 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3209 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3210 }
3211
9c54c0dd
JB		 3212 /*
3213 * On ILK+ LUT must be loaded before the pipe is running but with
3214 * clocks enabled
3215 */
3216 intel_crtc_load_lut(crtc);
3217
f67a559d
JB		 3218 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3219 intel_enable_plane(dev_priv, plane, pipe);
3220
3221 if (is_pch_port)
3222 ironlake_pch_enable(crtc);
c98e9dcf 3223
d1ebd816 3224 mutex_lock(&dev->struct_mutex);
bed4a673 3225 intel_update_fbc(dev);
d1ebd816
BW		 3226 mutex_unlock(&dev->struct_mutex);
3227
6b383a7f 3228 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3229
fa5c73b1
DV		 3230 for_each_encoder_on_crtc(dev, crtc, encoder)
3231 encoder->enable(encoder);
61b77ddd
DV		 3232
3233 if (HAS_PCH_CPT(dev))
3234 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 3235}
3236
3237static void ironlake_crtc_disable(struct drm_crtc *crtc)
3238{
3239 struct drm_device *dev = crtc->dev;
3240 struct drm_i915_private *dev_priv = dev->dev_private;
3241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3242 struct intel_encoder *encoder;
6be4a607
JB		 3243 int pipe = intel_crtc->pipe;
3244 int plane = intel_crtc->plane;
5eddb70b 3245 u32 reg, temp;
b52eb4dc 3246
ef9c3aee 3247
f7abfe8b
CW		 3248 if (!intel_crtc->active)
3249 return;
3250
ea9d758d
DV		 3251 for_each_encoder_on_crtc(dev, crtc, encoder)
3252 encoder->disable(encoder);
3253
e6c3a2a6 3254 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3255 drm_vblank_off(dev, pipe);
6b383a7f 3256 intel_crtc_update_cursor(crtc, false);
5eddb70b 3257
b24e7179 3258 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3259
973d04f9
CW		 3260 if (dev_priv->cfb_plane == plane)
3261 intel_disable_fbc(dev);
2c07245f 3262
b24e7179 3263 intel_disable_pipe(dev_priv, pipe);
32f9d658 3264
6be4a607 3265 /* Disable PF */
9db4a9c7
JB		 3266 I915_WRITE(PF_CTL(pipe), 0);
3267 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3268
bf49ec8c
DV		 3269 for_each_encoder_on_crtc(dev, crtc, encoder)
3270 if (encoder->post_disable)
3271 encoder->post_disable(encoder);
3272
0fc932b8 3273 ironlake_fdi_disable(crtc);
2c07245f 3274
040484af 3275 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3276
6be4a607
JB		 3277 if (HAS_PCH_CPT(dev)) {
3278 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3279 reg = TRANS_DP_CTL(pipe);
3280 temp = I915_READ(reg);
3281 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3282 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3283 I915_WRITE(reg, temp);
6be4a607
JB		 3284
3285 /* disable DPLL_SEL */
3286 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3287 switch (pipe) {
3288 case 0:
d64311ab 3289 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3290 break;
3291 case 1:
6be4a607 3292 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3293 break;
3294 case 2:
4b645f14 3295 /* C shares PLL A or B */
d64311ab 3296 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3297 break;
3298 default:
3299 BUG(); /* wtf */
3300 }
6be4a607 3301 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3302 }
e3421a18 3303
6be4a607 3304 /* disable PCH DPLL */
ee7b9f93 3305 intel_disable_pch_pll(intel_crtc);
8db9d77b 3306
88cefb6c 3307 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3308
f7abfe8b 3309 intel_crtc->active = false;
6b383a7f 3310 intel_update_watermarks(dev);
d1ebd816
BW		 3311
3312 mutex_lock(&dev->struct_mutex);
6b383a7f 3313 intel_update_fbc(dev);
d1ebd816 3314 mutex_unlock(&dev->struct_mutex);
6be4a607 3315}
1b3c7a47 3316
ee7b9f93
JB		 3317static void ironlake_crtc_off(struct drm_crtc *crtc)
3318{
3319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3320 intel_put_pch_pll(intel_crtc);
3321}
3322
02e792fb
DV		 3323static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3324{
02e792fb 3325 if (!enable && intel_crtc->overlay) {
23f09ce3 3326 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3327 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3328
23f09ce3 3329 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3330 dev_priv->mm.interruptible = false;
3331 (void) intel_overlay_switch_off(intel_crtc->overlay);
3332 dev_priv->mm.interruptible = true;
23f09ce3 3333 mutex_unlock(&dev->struct_mutex);
02e792fb 3334 }
02e792fb 3335
5dcdbcb0
CW		 3336 /* Let userspace switch the overlay on again. In most cases userspace
3337 * has to recompute where to put it anyway.
3338 */
02e792fb
DV		 3339}
3340
0b8765c6 3341static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3342{
3343 struct drm_device *dev = crtc->dev;
79e53945
JB		 3344 struct drm_i915_private *dev_priv = dev->dev_private;
3345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3346 struct intel_encoder *encoder;
79e53945 3347 int pipe = intel_crtc->pipe;
80824003 3348 int plane = intel_crtc->plane;
79e53945 3349
08a48469
DV		 3350 WARN_ON(!crtc->enabled);
3351
f7abfe8b
CW		 3352 if (intel_crtc->active)
3353 return;
3354
3355 intel_crtc->active = true;
6b383a7f
CW		 3356 intel_update_watermarks(dev);
3357
63d7bbe9 3358 intel_enable_pll(dev_priv, pipe);
040484af 3359 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3360 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3361
0b8765c6 3362 intel_crtc_load_lut(crtc);
bed4a673 3363 intel_update_fbc(dev);
79e53945 3364
0b8765c6
JB		 3365 /* Give the overlay scaler a chance to enable if it's on this pipe */
3366 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3367 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3368
fa5c73b1
DV		 3369 for_each_encoder_on_crtc(dev, crtc, encoder)
3370 encoder->enable(encoder);
0b8765c6 3371}
79e53945 3372
0b8765c6
JB		 3373static void i9xx_crtc_disable(struct drm_crtc *crtc)
3374{
3375 struct drm_device *dev = crtc->dev;
3376 struct drm_i915_private *dev_priv = dev->dev_private;
3377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3378 struct intel_encoder *encoder;
0b8765c6
JB		 3379 int pipe = intel_crtc->pipe;
3380 int plane = intel_crtc->plane;
b690e96c 3381
ef9c3aee 3382
f7abfe8b
CW		 3383 if (!intel_crtc->active)
3384 return;
3385
ea9d758d
DV		 3386 for_each_encoder_on_crtc(dev, crtc, encoder)
3387 encoder->disable(encoder);
3388
0b8765c6 3389 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3390 intel_crtc_wait_for_pending_flips(crtc);
3391 drm_vblank_off(dev, pipe);
0b8765c6 3392 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3393 intel_crtc_update_cursor(crtc, false);
0b8765c6 3394
973d04f9
CW		 3395 if (dev_priv->cfb_plane == plane)
3396 intel_disable_fbc(dev);
79e53945 3397
b24e7179 3398 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3399 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3400 intel_disable_pll(dev_priv, pipe);
0b8765c6 3401
f7abfe8b 3402 intel_crtc->active = false;
6b383a7f
CW		 3403 intel_update_fbc(dev);
3404 intel_update_watermarks(dev);
0b8765c6
JB		 3405}
3406
ee7b9f93
JB		 3407static void i9xx_crtc_off(struct drm_crtc *crtc)
3408{
3409}
3410
976f8a20
DV		 3411static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3412 bool enabled)
2c07245f
ZW		 3413{
3414 struct drm_device *dev = crtc->dev;
3415 struct drm_i915_master_private *master_priv;
3416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3417 int pipe = intel_crtc->pipe;
79e53945
JB		 3418
3419 if (!dev->primary->master)
3420 return;
3421
3422 master_priv = dev->primary->master->driver_priv;
3423 if (!master_priv->sarea_priv)
3424 return;
3425
79e53945
JB		 3426 switch (pipe) {
3427 case 0:
3428 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3429 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3430 break;
3431 case 1:
3432 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3433 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3434 break;
3435 default:
9db4a9c7 3436 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3437 break;
3438 }
79e53945
JB		 3439}
3440
976f8a20
DV		 3441/**
3442 * Sets the power management mode of the pipe and plane.
3443 */
3444void intel_crtc_update_dpms(struct drm_crtc *crtc)
3445{
3446 struct drm_device *dev = crtc->dev;
3447 struct drm_i915_private *dev_priv = dev->dev_private;
3448 struct intel_encoder *intel_encoder;
3449 bool enable = false;
3450
3451 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3452 enable |= intel_encoder->connectors_active;
3453
3454 if (enable)
3455 dev_priv->display.crtc_enable(crtc);
3456 else
3457 dev_priv->display.crtc_disable(crtc);
3458
3459 intel_crtc_update_sarea(crtc, enable);
3460}
3461
3462static void intel_crtc_noop(struct drm_crtc *crtc)
3463{
3464}
3465
cdd59983
CW		 3466static void intel_crtc_disable(struct drm_crtc *crtc)
3467{
cdd59983 3468 struct drm_device *dev = crtc->dev;
976f8a20 3469 struct drm_connector *connector;
ee7b9f93 3470 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3471
976f8a20
DV		 3472 /* crtc should still be enabled when we disable it. */
3473 WARN_ON(!crtc->enabled);
3474
3475 dev_priv->display.crtc_disable(crtc);
3476 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3477 dev_priv->display.off(crtc);
3478
931872fc
CW		 3479 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3480 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3481
3482 if (crtc->fb) {
3483 mutex_lock(&dev->struct_mutex);
1690e1eb 3484 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3485 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3486 crtc->fb = NULL;
3487 }
3488
3489 /* Update computed state. */
3490 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3491 if (!connector->encoder || !connector->encoder->crtc)
3492 continue;
3493
3494 if (connector->encoder->crtc != crtc)
3495 continue;
3496
3497 connector->dpms = DRM_MODE_DPMS_OFF;
3498 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3499 }
3500}
3501
a261b246 3502void intel_modeset_disable(struct drm_device *dev)
79e53945 3503{
a261b246
DV		 3504 struct drm_crtc *crtc;
3505
3506 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3507 if (crtc->enabled)
3508 intel_crtc_disable(crtc);
3509 }
79e53945
JB		 3510}
3511
1f703855 3512void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3513{
7e7d76c3
JB		 3514}
3515
ea5b213a 3516void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3517{
4ef69c7a 3518 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3519
ea5b213a
CW		 3520 drm_encoder_cleanup(encoder);
3521 kfree(intel_encoder);
7e7d76c3
JB		 3522}
3523
5ab432ef
DV		 3524/* Simple dpms helper for encodres with just one connector, no cloning and only
3525 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3526 * state of the entire output pipe. */
3527void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3528{
5ab432ef
DV		 3529 if (mode == DRM_MODE_DPMS_ON) {
3530 encoder->connectors_active = true;
3531
b2cabb0e 3532 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3533 } else {
3534 encoder->connectors_active = false;
3535
b2cabb0e 3536 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3537 }
79e53945
JB		 3538}
3539
0a91ca29
DV		 3540/* Cross check the actual hw state with our own modeset state tracking (and it's
3541 * internal consistency). */
b980514c 3542static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3543{
0a91ca29
DV		 3544 if (connector->get_hw_state(connector)) {
3545 struct intel_encoder *encoder = connector->encoder;
3546 struct drm_crtc *crtc;
3547 bool encoder_enabled;
3548 enum pipe pipe;
3549
3550 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3551 connector->base.base.id,
3552 drm_get_connector_name(&connector->base));
3553
3554 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3555 "wrong connector dpms state\n");
3556 WARN(connector->base.encoder != &encoder->base,
3557 "active connector not linked to encoder\n");
3558 WARN(!encoder->connectors_active,
3559 "encoder->connectors_active not set\n");
3560
3561 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3562 WARN(!encoder_enabled, "encoder not enabled\n");
3563 if (WARN_ON(!encoder->base.crtc))
3564 return;
3565
3566 crtc = encoder->base.crtc;
3567
3568 WARN(!crtc->enabled, "crtc not enabled\n");
3569 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3570 WARN(pipe != to_intel_crtc(crtc)->pipe,
3571 "encoder active on the wrong pipe\n");
3572 }
79e53945
JB		 3573}
3574
5ab432ef
DV		 3575/* Even simpler default implementation, if there's really no special case to
3576 * consider. */
3577void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3578{
5ab432ef 3579 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3580
5ab432ef
DV		 3581 /* All the simple cases only support two dpms states. */
3582 if (mode != DRM_MODE_DPMS_ON)
3583 mode = DRM_MODE_DPMS_OFF;
d4270e57 3584
5ab432ef
DV		 3585 if (mode == connector->dpms)
3586 return;
3587
3588 connector->dpms = mode;
3589
3590 /* Only need to change hw state when actually enabled */
3591 if (encoder->base.crtc)
3592 intel_encoder_dpms(encoder, mode);
3593 else
8af6cf88 3594 WARN_ON(encoder->connectors_active != false);
0a91ca29 3595
b980514c 3596 intel_modeset_check_state(connector->dev);
79e53945
JB		 3597}
3598
f0947c37
DV		 3599/* Simple connector->get_hw_state implementation for encoders that support only
3600 * one connector and no cloning and hence the encoder state determines the state
3601 * of the connector. */
3602bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3603{
24929352 3604 enum pipe pipe = 0;
f0947c37 3605 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3606
f0947c37 3607 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3608}
3609
79e53945 3610static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3611 const struct drm_display_mode *mode,
79e53945
JB		 3612 struct drm_display_mode *adjusted_mode)
3613{
2c07245f 3614 struct drm_device *dev = crtc->dev;
89749350 3615
bad720ff 3616 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3617 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3618 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3619 return false;
2c07245f 3620 }
89749350 3621
f9bef081
DV		 3622 /* All interlaced capable intel hw wants timings in frames. Note though
3623 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3624 * timings, so we need to be careful not to clobber these.*/
3625 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3626 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3627
44f46b42
CW		 3628 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3629 * with a hsync front porch of 0.
3630 */
3631 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3632 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3633 return false;
3634
79e53945
JB		 3635 return true;
3636}
3637
25eb05fc
JB		 3638static int valleyview_get_display_clock_speed(struct drm_device *dev)
3639{
3640 return 400000; /* FIXME */
3641}
3642
e70236a8
JB		 3643static int i945_get_display_clock_speed(struct drm_device *dev)
3644{
3645 return 400000;
3646}
79e53945 3647
e70236a8 3648static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3649{
e70236a8
JB		 3650 return 333000;
3651}
79e53945 3652
e70236a8
JB		 3653static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3654{
3655 return 200000;
3656}
79e53945 3657
e70236a8
JB		 3658static int i915gm_get_display_clock_speed(struct drm_device *dev)
3659{
3660 u16 gcfgc = 0;
79e53945 3661
e70236a8
JB		 3662 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3663
3664 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3665 return 133000;
3666 else {
3667 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3668 case GC_DISPLAY_CLOCK_333_MHZ:
3669 return 333000;
3670 default:
3671 case GC_DISPLAY_CLOCK_190_200_MHZ:
3672 return 190000;
79e53945 3673 }
e70236a8
JB		 3674 }
3675}
3676
3677static int i865_get_display_clock_speed(struct drm_device *dev)
3678{
3679 return 266000;
3680}
3681
3682static int i855_get_display_clock_speed(struct drm_device *dev)
3683{
3684 u16 hpllcc = 0;
3685 /* Assume that the hardware is in the high speed state. This
3686 * should be the default.
3687 */
3688 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3689 case GC_CLOCK_133_200:
3690 case GC_CLOCK_100_200:
3691 return 200000;
3692 case GC_CLOCK_166_250:
3693 return 250000;
3694 case GC_CLOCK_100_133:
79e53945 3695 return 133000;
e70236a8 3696 }
79e53945 3697
e70236a8
JB		 3698 /* Shouldn't happen */
3699 return 0;
3700}
79e53945 3701
e70236a8
JB		 3702static int i830_get_display_clock_speed(struct drm_device *dev)
3703{
3704 return 133000;
79e53945
JB		 3705}
3706
2c07245f
ZW		 3707struct fdi_m_n {
3708 u32 tu;
3709 u32 gmch_m;
3710 u32 gmch_n;
3711 u32 link_m;
3712 u32 link_n;
3713};
3714
3715static void
3716fdi_reduce_ratio(u32 *num, u32 *den)
3717{
3718 while (*num > 0xffffff || *den > 0xffffff) {
3719 *num >>= 1;
3720 *den >>= 1;
3721 }
3722}
3723
2c07245f 3724static void
f2b115e6
AJ		 3725ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3726 int link_clock, struct fdi_m_n *m_n)
2c07245f 3727{
2c07245f
ZW		 3728 m_n->tu = 64; /* default size */
3729
22ed1113
CW		 3730 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3731 m_n->gmch_m = bits_per_pixel * pixel_clock;
3732 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3733 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3734
22ed1113
CW		 3735 m_n->link_m = pixel_clock;
3736 m_n->link_n = link_clock;
2c07245f
ZW		 3737 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3738}
3739
a7615030
CW		 3740static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3741{
72bbe58c
KP		 3742 if (i915_panel_use_ssc >= 0)
3743 return i915_panel_use_ssc != 0;
3744 return dev_priv->lvds_use_ssc
435793df 3745 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3746}
3747
5a354204
JB		 3748/**
3749 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3750 * @crtc: CRTC structure
3b5c78a3 3751 * @mode: requested mode
5a354204
JB		 3752 *
3753 * A pipe may be connected to one or more outputs. Based on the depth of the
3754 * attached framebuffer, choose a good color depth to use on the pipe.
3755 *
3756 * If possible, match the pipe depth to the fb depth. In some cases, this
3757 * isn't ideal, because the connected output supports a lesser or restricted
3758 * set of depths. Resolve that here:
3759 * LVDS typically supports only 6bpc, so clamp down in that case
3760 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3761 * Displays may support a restricted set as well, check EDID and clamp as
3762 * appropriate.
3b5c78a3 3763 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3764 *
3765 * RETURNS:
3766 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3767 * true if they don't match).
3768 */
3769static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 3770 struct drm_framebuffer *fb,
3b5c78a3
AJ		 3771 unsigned int *pipe_bpp,
3772 struct drm_display_mode *mode)
5a354204
JB		 3773{
3774 struct drm_device *dev = crtc->dev;
3775 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 3776 struct drm_connector *connector;
6c2b7c12 3777 struct intel_encoder *intel_encoder;
5a354204
JB		 3778 unsigned int display_bpc = UINT_MAX, bpc;
3779
3780 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 3781 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 3782
3783 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3784 unsigned int lvds_bpc;
3785
3786 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3787 LVDS_A3_POWER_UP)
3788 lvds_bpc = 8;
3789 else
3790 lvds_bpc = 6;
3791
3792 if (lvds_bpc < display_bpc) {
82820490 3793 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3794 display_bpc = lvds_bpc;
3795 }
3796 continue;
3797 }
3798
5a354204
JB		 3799 /* Not one of the known troublemakers, check the EDID */
3800 list_for_each_entry(connector, &dev->mode_config.connector_list,
3801 head) {
6c2b7c12 3802 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 3803 continue;
3804
62ac41a6
JB		 3805 /* Don't use an invalid EDID bpc value */
3806 if (connector->display_info.bpc &&
3807 connector->display_info.bpc < display_bpc) {
82820490 3808 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3809 display_bpc = connector->display_info.bpc;
3810 }
3811 }
3812
3813 /*
3814 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3815 * through, clamp it down. (Note: >12bpc will be caught below.)
3816 */
3817 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3818 if (display_bpc > 8 && display_bpc < 12) {
82820490 3819 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3820 display_bpc = 12;
3821 } else {
82820490 3822 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3823 display_bpc = 8;
3824 }
3825 }
3826 }
3827
3b5c78a3
AJ		 3828 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3829 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3830 display_bpc = 6;
3831 }
3832
5a354204
JB		 3833 /*
3834 * We could just drive the pipe at the highest bpc all the time and
3835 * enable dithering as needed, but that costs bandwidth. So choose
3836 * the minimum value that expresses the full color range of the fb but
3837 * also stays within the max display bpc discovered above.
3838 */
3839
94352cf9 3840 switch (fb->depth) {
5a354204
JB		 3841 case 8:
3842 bpc = 8; /* since we go through a colormap */
3843 break;
3844 case 15:
3845 case 16:
3846 bpc = 6; /* min is 18bpp */
3847 break;
3848 case 24:
578393cd 3849 bpc = 8;
5a354204
JB		 3850 break;
3851 case 30:
578393cd 3852 bpc = 10;
5a354204
JB		 3853 break;
3854 case 48:
578393cd 3855 bpc = 12;
5a354204
JB		 3856 break;
3857 default:
3858 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3859 bpc = min((unsigned int)8, display_bpc);
3860 break;
3861 }
3862
578393cd
KP		 3863 display_bpc = min(display_bpc, bpc);
3864
82820490
AJ		 3865 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3866 bpc, display_bpc);
5a354204 3867
578393cd 3868 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3869
3870 return display_bpc != bpc;
3871}
3872
a0c4da24
JB		 3873static int vlv_get_refclk(struct drm_crtc *crtc)
3874{
3875 struct drm_device *dev = crtc->dev;
3876 struct drm_i915_private *dev_priv = dev->dev_private;
3877 int refclk = 27000; /* for DP & HDMI */
3878
3879 return 100000; /* only one validated so far */
3880
3881 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3882 refclk = 96000;
3883 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3884 if (intel_panel_use_ssc(dev_priv))
3885 refclk = 100000;
3886 else
3887 refclk = 96000;
3888 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3889 refclk = 100000;
3890 }
3891
3892 return refclk;
3893}
3894
c65d77d8
JB		 3895static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3896{
3897 struct drm_device *dev = crtc->dev;
3898 struct drm_i915_private *dev_priv = dev->dev_private;
3899 int refclk;
3900
a0c4da24
JB		 3901 if (IS_VALLEYVIEW(dev)) {
3902 refclk = vlv_get_refclk(crtc);
3903 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 3904 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3905 refclk = dev_priv->lvds_ssc_freq * 1000;
3906 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3907 refclk / 1000);
3908 } else if (!IS_GEN2(dev)) {
3909 refclk = 96000;
3910 } else {
3911 refclk = 48000;
3912 }
3913
3914 return refclk;
3915}
3916
3917static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3918 intel_clock_t *clock)
3919{
3920 /* SDVO TV has fixed PLL values depend on its clock range,
3921 this mirrors vbios setting. */
3922 if (adjusted_mode->clock >= 100000
3923 && adjusted_mode->clock < 140500) {
3924 clock->p1 = 2;
3925 clock->p2 = 10;
3926 clock->n = 3;
3927 clock->m1 = 16;
3928 clock->m2 = 8;
3929 } else if (adjusted_mode->clock >= 140500
3930 && adjusted_mode->clock <= 200000) {
3931 clock->p1 = 1;
3932 clock->p2 = 10;
3933 clock->n = 6;
3934 clock->m1 = 12;
3935 clock->m2 = 8;
3936 }
3937}
3938
a7516a05
JB		 3939static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3940 intel_clock_t *clock,
3941 intel_clock_t *reduced_clock)
3942{
3943 struct drm_device *dev = crtc->dev;
3944 struct drm_i915_private *dev_priv = dev->dev_private;
3945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3946 int pipe = intel_crtc->pipe;
3947 u32 fp, fp2 = 0;
3948
3949 if (IS_PINEVIEW(dev)) {
3950 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3951 if (reduced_clock)
3952 fp2 = (1 << reduced_clock->n) << 16 |
3953 reduced_clock->m1 << 8 | reduced_clock->m2;
3954 } else {
3955 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3956 if (reduced_clock)
3957 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3958 reduced_clock->m2;
3959 }
3960
3961 I915_WRITE(FP0(pipe), fp);
3962
3963 intel_crtc->lowfreq_avail = false;
3964 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3965 reduced_clock && i915_powersave) {
3966 I915_WRITE(FP1(pipe), fp2);
3967 intel_crtc->lowfreq_avail = true;
3968 } else {
3969 I915_WRITE(FP1(pipe), fp);
3970 }
3971}
3972
93e537a1
DV		 3973static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3974 struct drm_display_mode *adjusted_mode)
3975{
3976 struct drm_device *dev = crtc->dev;
3977 struct drm_i915_private *dev_priv = dev->dev_private;
3978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3979 int pipe = intel_crtc->pipe;
284d5df5 3980 u32 temp;
93e537a1
DV		 3981
3982 temp = I915_READ(LVDS);
3983 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3984 if (pipe == 1) {
3985 temp |= LVDS_PIPEB_SELECT;
3986 } else {
3987 temp &= ~LVDS_PIPEB_SELECT;
3988 }
3989 /* set the corresponsding LVDS_BORDER bit */
3990 temp |= dev_priv->lvds_border_bits;
3991 /* Set the B0-B3 data pairs corresponding to whether we're going to
3992 * set the DPLLs for dual-channel mode or not.
3993 */
3994 if (clock->p2 == 7)
3995 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3996 else
3997 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3998
3999 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4000 * appropriately here, but we need to look more thoroughly into how
4001 * panels behave in the two modes.
4002 */
4003 /* set the dithering flag on LVDS as needed */
4004 if (INTEL_INFO(dev)->gen >= 4) {
4005 if (dev_priv->lvds_dither)
4006 temp |= LVDS_ENABLE_DITHER;
4007 else
4008 temp &= ~LVDS_ENABLE_DITHER;
4009 }
284d5df5 4010 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4011 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4012 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4013 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4014 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4015 I915_WRITE(LVDS, temp);
4016}
4017
a0c4da24
JB		 4018static void vlv_update_pll(struct drm_crtc *crtc,
4019 struct drm_display_mode *mode,
4020 struct drm_display_mode *adjusted_mode,
4021 intel_clock_t *clock, intel_clock_t *reduced_clock,
4022 int refclk, int num_connectors)
4023{
4024 struct drm_device *dev = crtc->dev;
4025 struct drm_i915_private *dev_priv = dev->dev_private;
4026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4027 int pipe = intel_crtc->pipe;
4028 u32 dpll, mdiv, pdiv;
4029 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4030 bool is_hdmi;
4031
4032 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4033
4034 bestn = clock->n;
4035 bestm1 = clock->m1;
4036 bestm2 = clock->m2;
4037 bestp1 = clock->p1;
4038 bestp2 = clock->p2;
4039
4040 /* Enable DPIO clock input */
4041 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4042 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4043 I915_WRITE(DPLL(pipe), dpll);
4044 POSTING_READ(DPLL(pipe));
4045
4046 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4047 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4048 mdiv |= ((bestn << DPIO_N_SHIFT));
4049 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4050 mdiv |= (1 << DPIO_K_SHIFT);
4051 mdiv |= DPIO_ENABLE_CALIBRATION;
4052 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4053
4054 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4055
4056 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4057 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4058 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4059 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4060
4061 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4062
4063 dpll |= DPLL_VCO_ENABLE;
4064 I915_WRITE(DPLL(pipe), dpll);
4065 POSTING_READ(DPLL(pipe));
4066 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4067 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4068
4069 if (is_hdmi) {
4070 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4071
4072 if (temp > 1)
4073 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4074 else
4075 temp = 0;
4076
4077 I915_WRITE(DPLL_MD(pipe), temp);
4078 POSTING_READ(DPLL_MD(pipe));
4079 }
4080
4081 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4082}
4083
eb1cbe48
DV		 4084static void i9xx_update_pll(struct drm_crtc *crtc,
4085 struct drm_display_mode *mode,
4086 struct drm_display_mode *adjusted_mode,
4087 intel_clock_t *clock, intel_clock_t *reduced_clock,
4088 int num_connectors)
4089{
4090 struct drm_device *dev = crtc->dev;
4091 struct drm_i915_private *dev_priv = dev->dev_private;
4092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4093 int pipe = intel_crtc->pipe;
4094 u32 dpll;
4095 bool is_sdvo;
4096
4097 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4098 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4099
4100 dpll = DPLL_VGA_MODE_DIS;
4101
4102 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4103 dpll |= DPLLB_MODE_LVDS;
4104 else
4105 dpll |= DPLLB_MODE_DAC_SERIAL;
4106 if (is_sdvo) {
4107 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4108 if (pixel_multiplier > 1) {
4109 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4110 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4111 }
4112 dpll |= DPLL_DVO_HIGH_SPEED;
4113 }
4114 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4115 dpll |= DPLL_DVO_HIGH_SPEED;
4116
4117 /* compute bitmask from p1 value */
4118 if (IS_PINEVIEW(dev))
4119 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4120 else {
4121 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4122 if (IS_G4X(dev) && reduced_clock)
4123 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4124 }
4125 switch (clock->p2) {
4126 case 5:
4127 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4128 break;
4129 case 7:
4130 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4131 break;
4132 case 10:
4133 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4134 break;
4135 case 14:
4136 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4137 break;
4138 }
4139 if (INTEL_INFO(dev)->gen >= 4)
4140 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4141
4142 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4143 dpll |= PLL_REF_INPUT_TVCLKINBC;
4144 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4145 /* XXX: just matching BIOS for now */
4146 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4147 dpll |= 3;
4148 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4149 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4150 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4151 else
4152 dpll |= PLL_REF_INPUT_DREFCLK;
4153
4154 dpll |= DPLL_VCO_ENABLE;
4155 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4156 POSTING_READ(DPLL(pipe));
4157 udelay(150);
4158
4159 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4160 * This is an exception to the general rule that mode_set doesn't turn
4161 * things on.
4162 */
4163 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4164 intel_update_lvds(crtc, clock, adjusted_mode);
4165
4166 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4167 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4168
4169 I915_WRITE(DPLL(pipe), dpll);
4170
4171 /* Wait for the clocks to stabilize. */
4172 POSTING_READ(DPLL(pipe));
4173 udelay(150);
4174
4175 if (INTEL_INFO(dev)->gen >= 4) {
4176 u32 temp = 0;
4177 if (is_sdvo) {
4178 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4179 if (temp > 1)
4180 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4181 else
4182 temp = 0;
4183 }
4184 I915_WRITE(DPLL_MD(pipe), temp);
4185 } else {
4186 /* The pixel multiplier can only be updated once the
4187 * DPLL is enabled and the clocks are stable.
4188 *
4189 * So write it again.
4190 */
4191 I915_WRITE(DPLL(pipe), dpll);
4192 }
4193}
4194
4195static void i8xx_update_pll(struct drm_crtc *crtc,
4196 struct drm_display_mode *adjusted_mode,
4197 intel_clock_t *clock,
4198 int num_connectors)
4199{
4200 struct drm_device *dev = crtc->dev;
4201 struct drm_i915_private *dev_priv = dev->dev_private;
4202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4203 int pipe = intel_crtc->pipe;
4204 u32 dpll;
4205
4206 dpll = DPLL_VGA_MODE_DIS;
4207
4208 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4209 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4210 } else {
4211 if (clock->p1 == 2)
4212 dpll |= PLL_P1_DIVIDE_BY_TWO;
4213 else
4214 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4215 if (clock->p2 == 4)
4216 dpll |= PLL_P2_DIVIDE_BY_4;
4217 }
4218
4219 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4220 /* XXX: just matching BIOS for now */
4221 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4222 dpll |= 3;
4223 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4224 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4225 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4226 else
4227 dpll |= PLL_REF_INPUT_DREFCLK;
4228
4229 dpll |= DPLL_VCO_ENABLE;
4230 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4231 POSTING_READ(DPLL(pipe));
4232 udelay(150);
4233
eb1cbe48
DV		 4234 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4235 * This is an exception to the general rule that mode_set doesn't turn
4236 * things on.
4237 */
4238 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4239 intel_update_lvds(crtc, clock, adjusted_mode);
4240
5b5896e4
DV		 4241 I915_WRITE(DPLL(pipe), dpll);
4242
4243 /* Wait for the clocks to stabilize. */
4244 POSTING_READ(DPLL(pipe));
4245 udelay(150);
4246
eb1cbe48
DV		 4247 /* The pixel multiplier can only be updated once the
4248 * DPLL is enabled and the clocks are stable.
4249 *
4250 * So write it again.
4251 */
4252 I915_WRITE(DPLL(pipe), dpll);
4253}
4254
f564048e
EA		 4255static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4256 struct drm_display_mode *mode,
4257 struct drm_display_mode *adjusted_mode,
4258 int x, int y,
94352cf9 4259 struct drm_framebuffer *fb)
79e53945
JB		 4260{
4261 struct drm_device *dev = crtc->dev;
4262 struct drm_i915_private *dev_priv = dev->dev_private;
4263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4264 int pipe = intel_crtc->pipe;
80824003 4265 int plane = intel_crtc->plane;
c751ce4f 4266 int refclk, num_connectors = 0;
652c393a 4267 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 4268 u32 dspcntr, pipeconf, vsyncshift;
4269 bool ok, has_reduced_clock = false, is_sdvo = false;
4270 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4271 struct intel_encoder *encoder;
d4906093 4272 const intel_limit_t *limit;
5c3b82e2 4273 int ret;
79e53945 4274
6c2b7c12 4275 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4276 switch (encoder->type) {
79e53945
JB		 4277 case INTEL_OUTPUT_LVDS:
4278 is_lvds = true;
4279 break;
4280 case INTEL_OUTPUT_SDVO:
7d57382e 4281 case INTEL_OUTPUT_HDMI:
79e53945 4282 is_sdvo = true;
5eddb70b 4283 if (encoder->needs_tv_clock)
e2f0ba97 4284 is_tv = true;
79e53945 4285 break;
79e53945
JB		 4286 case INTEL_OUTPUT_TVOUT:
4287 is_tv = true;
4288 break;
a4fc5ed6
KP		 4289 case INTEL_OUTPUT_DISPLAYPORT:
4290 is_dp = true;
4291 break;
79e53945 4292 }
43565a06 4293
c751ce4f 4294 num_connectors++;
79e53945
JB		 4295 }
4296
c65d77d8 4297 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4298
d4906093
ML		 4299 /*
4300 * Returns a set of divisors for the desired target clock with the given
4301 * refclk, or FALSE. The returned values represent the clock equation:
4302 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4303 */
1b894b59 4304 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4305 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4306 &clock);
79e53945
JB		 4307 if (!ok) {
4308 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4309 return -EINVAL;
79e53945
JB		 4310 }
4311
cda4b7d3 4312 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4313 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4314
ddc9003c 4315 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4316 /*
4317 * Ensure we match the reduced clock's P to the target clock.
4318 * If the clocks don't match, we can't switch the display clock
4319 * by using the FP0/FP1. In such case we will disable the LVDS
4320 * downclock feature.
4321 */
ddc9003c 4322 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4323 dev_priv->lvds_downclock,
4324 refclk,
cec2f356 4325 &clock,
5eddb70b 4326 &reduced_clock);
7026d4ac
ZW		 4327 }
4328
c65d77d8
JB		 4329 if (is_sdvo && is_tv)
4330 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4331
a7516a05
JB		 4332 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4333 &reduced_clock : NULL);
79e53945 4334
eb1cbe48
DV		 4335 if (IS_GEN2(dev))
4336 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
a0c4da24
JB		 4337 else if (IS_VALLEYVIEW(dev))
4338 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4339 refclk, num_connectors);
79e53945 4340 else
eb1cbe48
DV		 4341 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4342 has_reduced_clock ? &reduced_clock : NULL,
4343 num_connectors);
79e53945
JB		 4344
4345 /* setup pipeconf */
5eddb70b 4346 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4347
4348 /* Set up the display plane register */
4349 dspcntr = DISPPLANE_GAMMA_ENABLE;
4350
929c77fb
EA		 4351 if (pipe == 0)
4352 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4353 else
4354 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4355
a6c45cf0 4356 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4357 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4358 * core speed.
4359 *
4360 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4361 * pipe == 0 check?
4362 */
e70236a8
JB		 4363 if (mode->clock >
4364 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4365 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4366 else
5eddb70b 4367 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4368 }
4369
3b5c78a3
AJ		 4370 /* default to 8bpc */
4371 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4372 if (is_dp) {
4373 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4374 pipeconf |= PIPECONF_BPP_6 |
4375 PIPECONF_DITHER_EN |
4376 PIPECONF_DITHER_TYPE_SP;
4377 }
4378 }
4379
28c97730 4380 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4381 drm_mode_debug_printmodeline(mode);
4382
a7516a05
JB		 4383 if (HAS_PIPE_CXSR(dev)) {
4384 if (intel_crtc->lowfreq_avail) {
28c97730 4385 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4386 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4387 } else {
28c97730 4388 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4389 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4390 }
4391 }
4392
617cf884 4393 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 4394 if (!IS_GEN2(dev) &&
4395 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 4396 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4397 /* the chip adds 2 halflines automatically */
734b4157 4398 adjusted_mode->crtc_vtotal -= 1;
734b4157 4399 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4400 vsyncshift = adjusted_mode->crtc_hsync_start
4401 - adjusted_mode->crtc_htotal/2;
4402 } else {
617cf884 4403 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4404 vsyncshift = 0;
4405 }
4406
4407 if (!IS_GEN3(dev))
4408 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 4409
5eddb70b
CW		 4410 I915_WRITE(HTOTAL(pipe),
4411 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4412 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4413 I915_WRITE(HBLANK(pipe),
4414 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4415 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4416 I915_WRITE(HSYNC(pipe),
4417 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4418 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4419
4420 I915_WRITE(VTOTAL(pipe),
4421 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4422 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4423 I915_WRITE(VBLANK(pipe),
4424 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4425 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4426 I915_WRITE(VSYNC(pipe),
4427 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4428 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4429
4430 /* pipesrc and dspsize control the size that is scaled from,
4431 * which should always be the user's requested size.
79e53945 4432 */
929c77fb
EA		 4433 I915_WRITE(DSPSIZE(plane),
4434 ((mode->vdisplay - 1) << 16) |
4435 (mode->hdisplay - 1));
4436 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4437 I915_WRITE(PIPESRC(pipe),
4438 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4439
f564048e
EA		 4440 I915_WRITE(PIPECONF(pipe), pipeconf);
4441 POSTING_READ(PIPECONF(pipe));
929c77fb 4442 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4443
4444 intel_wait_for_vblank(dev, pipe);
4445
f564048e
EA		 4446 I915_WRITE(DSPCNTR(plane), dspcntr);
4447 POSTING_READ(DSPCNTR(plane));
4448
94352cf9 4449 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4450
4451 intel_update_watermarks(dev);
4452
f564048e
EA		 4453 return ret;
4454}
4455
9fb526db
KP		 4456/*
4457 * Initialize reference clocks when the driver loads
4458 */
4459void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4460{
4461 struct drm_i915_private *dev_priv = dev->dev_private;
4462 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4463 struct intel_encoder *encoder;
13d83a67
JB		 4464 u32 temp;
4465 bool has_lvds = false;
199e5d79
KP		 4466 bool has_cpu_edp = false;
4467 bool has_pch_edp = false;
4468 bool has_panel = false;
99eb6a01
KP		 4469 bool has_ck505 = false;
4470 bool can_ssc = false;
13d83a67
JB		 4471
4472 /* We need to take the global config into account */
199e5d79
KP		 4473 list_for_each_entry(encoder, &mode_config->encoder_list,
4474 base.head) {
4475 switch (encoder->type) {
4476 case INTEL_OUTPUT_LVDS:
4477 has_panel = true;
4478 has_lvds = true;
4479 break;
4480 case INTEL_OUTPUT_EDP:
4481 has_panel = true;
4482 if (intel_encoder_is_pch_edp(&encoder->base))
4483 has_pch_edp = true;
4484 else
4485 has_cpu_edp = true;
4486 break;
13d83a67
JB		 4487 }
4488 }
4489
99eb6a01
KP		 4490 if (HAS_PCH_IBX(dev)) {
4491 has_ck505 = dev_priv->display_clock_mode;
4492 can_ssc = has_ck505;
4493 } else {
4494 has_ck505 = false;
4495 can_ssc = true;
4496 }
4497
4498 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4499 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4500 has_ck505);
13d83a67
JB		 4501
4502 /* Ironlake: try to setup display ref clock before DPLL
4503 * enabling. This is only under driver's control after
4504 * PCH B stepping, previous chipset stepping should be
4505 * ignoring this setting.
4506 */
4507 temp = I915_READ(PCH_DREF_CONTROL);
4508 /* Always enable nonspread source */
4509 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4510
99eb6a01
KP		 4511 if (has_ck505)
4512 temp |= DREF_NONSPREAD_CK505_ENABLE;
4513 else
4514 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4515
199e5d79
KP		 4516 if (has_panel) {
4517 temp &= ~DREF_SSC_SOURCE_MASK;
4518 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4519
199e5d79 4520 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4521 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4522 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4523 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4524 } else
4525 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4526
4527 /* Get SSC going before enabling the outputs */
4528 I915_WRITE(PCH_DREF_CONTROL, temp);
4529 POSTING_READ(PCH_DREF_CONTROL);
4530 udelay(200);
4531
13d83a67
JB		 4532 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4533
4534 /* Enable CPU source on CPU attached eDP */
199e5d79 4535 if (has_cpu_edp) {
99eb6a01 4536 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4537 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4538 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4539 }
13d83a67
JB		 4540 else
4541 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4542 } else
4543 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4544
4545 I915_WRITE(PCH_DREF_CONTROL, temp);
4546 POSTING_READ(PCH_DREF_CONTROL);
4547 udelay(200);
4548 } else {
4549 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4550
4551 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4552
4553 /* Turn off CPU output */
4554 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4555
4556 I915_WRITE(PCH_DREF_CONTROL, temp);
4557 POSTING_READ(PCH_DREF_CONTROL);
4558 udelay(200);
4559
4560 /* Turn off the SSC source */
4561 temp &= ~DREF_SSC_SOURCE_MASK;
4562 temp |= DREF_SSC_SOURCE_DISABLE;
4563
4564 /* Turn off SSC1 */
4565 temp &= ~ DREF_SSC1_ENABLE;
4566
13d83a67
JB		 4567 I915_WRITE(PCH_DREF_CONTROL, temp);
4568 POSTING_READ(PCH_DREF_CONTROL);
4569 udelay(200);
4570 }
4571}
4572
d9d444cb
JB		 4573static int ironlake_get_refclk(struct drm_crtc *crtc)
4574{
4575 struct drm_device *dev = crtc->dev;
4576 struct drm_i915_private *dev_priv = dev->dev_private;
4577 struct intel_encoder *encoder;
d9d444cb
JB		 4578 struct intel_encoder *edp_encoder = NULL;
4579 int num_connectors = 0;
4580 bool is_lvds = false;
4581
6c2b7c12 4582 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4583 switch (encoder->type) {
4584 case INTEL_OUTPUT_LVDS:
4585 is_lvds = true;
4586 break;
4587 case INTEL_OUTPUT_EDP:
4588 edp_encoder = encoder;
4589 break;
4590 }
4591 num_connectors++;
4592 }
4593
4594 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4595 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4596 dev_priv->lvds_ssc_freq);
4597 return dev_priv->lvds_ssc_freq * 1000;
4598 }
4599
4600 return 120000;
4601}
4602
c8203565
PZ		 4603static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4604 struct drm_display_mode *adjusted_mode,
4605 bool dither)
4606{
4607 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4609 int pipe = intel_crtc->pipe;
4610 uint32_t val;
4611
4612 val = I915_READ(PIPECONF(pipe));
4613
4614 val &= ~PIPE_BPC_MASK;
4615 switch (intel_crtc->bpp) {
4616 case 18:
4617 val |= PIPE_6BPC;
4618 break;
4619 case 24:
4620 val |= PIPE_8BPC;
4621 break;
4622 case 30:
4623 val |= PIPE_10BPC;
4624 break;
4625 case 36:
4626 val |= PIPE_12BPC;
4627 break;
4628 default:
cc769b62
PZ		 4629 /* Case prevented by intel_choose_pipe_bpp_dither. */
4630 BUG();
c8203565
PZ		 4631 }
4632
4633 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4634 if (dither)
4635 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4636
4637 val &= ~PIPECONF_INTERLACE_MASK;
4638 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4639 val |= PIPECONF_INTERLACED_ILK;
4640 else
4641 val |= PIPECONF_PROGRESSIVE;
4642
4643 I915_WRITE(PIPECONF(pipe), val);
4644 POSTING_READ(PIPECONF(pipe));
4645}
4646
6591c6e4
PZ		 4647static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4648 struct drm_display_mode *adjusted_mode,
4649 intel_clock_t *clock,
4650 bool *has_reduced_clock,
4651 intel_clock_t *reduced_clock)
4652{
4653 struct drm_device *dev = crtc->dev;
4654 struct drm_i915_private *dev_priv = dev->dev_private;
4655 struct intel_encoder *intel_encoder;
4656 int refclk;
4657 const intel_limit_t *limit;
4658 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4659
4660 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4661 switch (intel_encoder->type) {
4662 case INTEL_OUTPUT_LVDS:
4663 is_lvds = true;
4664 break;
4665 case INTEL_OUTPUT_SDVO:
4666 case INTEL_OUTPUT_HDMI:
4667 is_sdvo = true;
4668 if (intel_encoder->needs_tv_clock)
4669 is_tv = true;
4670 break;
4671 case INTEL_OUTPUT_TVOUT:
4672 is_tv = true;
4673 break;
4674 }
4675 }
4676
4677 refclk = ironlake_get_refclk(crtc);
4678
4679 /*
4680 * Returns a set of divisors for the desired target clock with the given
4681 * refclk, or FALSE. The returned values represent the clock equation:
4682 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4683 */
4684 limit = intel_limit(crtc, refclk);
4685 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4686 clock);
4687 if (!ret)
4688 return false;
4689
4690 if (is_lvds && dev_priv->lvds_downclock_avail) {
4691 /*
4692 * Ensure we match the reduced clock's P to the target clock.
4693 * If the clocks don't match, we can't switch the display clock
4694 * by using the FP0/FP1. In such case we will disable the LVDS
4695 * downclock feature.
4696 */
4697 *has_reduced_clock = limit->find_pll(limit, crtc,
4698 dev_priv->lvds_downclock,
4699 refclk,
4700 clock,
4701 reduced_clock);
4702 }
4703
4704 if (is_sdvo && is_tv)
4705 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4706
4707 return true;
4708}
4709
f48d8f23
PZ		 4710static void ironlake_set_m_n(struct drm_crtc *crtc,
4711 struct drm_display_mode *mode,
4712 struct drm_display_mode *adjusted_mode)
4713{
4714 struct drm_device *dev = crtc->dev;
4715 struct drm_i915_private *dev_priv = dev->dev_private;
4716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4717 enum pipe pipe = intel_crtc->pipe;
4718 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
4719 struct fdi_m_n m_n = {0};
4720 int target_clock, pixel_multiplier, lane, link_bw;
4721 bool is_dp = false, is_cpu_edp = false;
4722
4723 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4724 switch (intel_encoder->type) {
4725 case INTEL_OUTPUT_DISPLAYPORT:
4726 is_dp = true;
4727 break;
4728 case INTEL_OUTPUT_EDP:
4729 is_dp = true;
4730 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4731 is_cpu_edp = true;
4732 edp_encoder = intel_encoder;
4733 break;
4734 }
4735 }
4736
4737 /* FDI link */
4738 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4739 lane = 0;
4740 /* CPU eDP doesn't require FDI link, so just set DP M/N
4741 according to current link config */
4742 if (is_cpu_edp) {
4743 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4744 } else {
4745 /* FDI is a binary signal running at ~2.7GHz, encoding
4746 * each output octet as 10 bits. The actual frequency
4747 * is stored as a divider into a 100MHz clock, and the
4748 * mode pixel clock is stored in units of 1KHz.
4749 * Hence the bw of each lane in terms of the mode signal
4750 * is:
4751 */
4752 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4753 }
4754
4755 /* [e]DP over FDI requires target mode clock instead of link clock. */
4756 if (edp_encoder)
4757 target_clock = intel_edp_target_clock(edp_encoder, mode);
4758 else if (is_dp)
4759 target_clock = mode->clock;
4760 else
4761 target_clock = adjusted_mode->clock;
4762
4763 if (!lane) {
4764 /*
4765 * Account for spread spectrum to avoid
4766 * oversubscribing the link. Max center spread
4767 * is 2.5%; use 5% for safety's sake.
4768 */
4769 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4770 lane = bps / (link_bw * 8) + 1;
4771 }
4772
4773 intel_crtc->fdi_lanes = lane;
4774
4775 if (pixel_multiplier > 1)
4776 link_bw *= pixel_multiplier;
4777 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4778 &m_n);
4779
4780 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4781 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4782 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4783 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4784}
4785
f564048e
EA		 4786static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4787 struct drm_display_mode *mode,
4788 struct drm_display_mode *adjusted_mode,
4789 int x, int y,
94352cf9 4790 struct drm_framebuffer *fb)
79e53945
JB		 4791{
4792 struct drm_device *dev = crtc->dev;
4793 struct drm_i915_private *dev_priv = dev->dev_private;
4794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4795 int pipe = intel_crtc->pipe;
80824003 4796 int plane = intel_crtc->plane;
6591c6e4 4797 int num_connectors = 0;
652c393a 4798 intel_clock_t clock, reduced_clock;
a1f9e77e 4799 u32 dpll, fp = 0, fp2 = 0;
a07d6787 4800 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4801 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
f48d8f23 4802 struct intel_encoder *encoder;
fae14981 4803 u32 temp;
f48d8f23 4804 int ret, factor;
5a354204 4805 bool dither;
e3aef172 4806 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4807
6c2b7c12 4808 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4809 switch (encoder->type) {
79e53945
JB		 4810 case INTEL_OUTPUT_LVDS:
4811 is_lvds = true;
4812 break;
4813 case INTEL_OUTPUT_SDVO:
7d57382e 4814 case INTEL_OUTPUT_HDMI:
79e53945 4815 is_sdvo = true;
5eddb70b 4816 if (encoder->needs_tv_clock)
e2f0ba97 4817 is_tv = true;
79e53945 4818 break;
79e53945
JB		 4819 case INTEL_OUTPUT_TVOUT:
4820 is_tv = true;
4821 break;
4822 case INTEL_OUTPUT_ANALOG:
4823 is_crt = true;
4824 break;
a4fc5ed6
KP		 4825 case INTEL_OUTPUT_DISPLAYPORT:
4826 is_dp = true;
4827 break;
32f9d658 4828 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4829 is_dp = true;
4830 if (intel_encoder_is_pch_edp(&encoder->base))
4831 is_pch_edp = true;
4832 else
4833 is_cpu_edp = true;
32f9d658 4834 break;
79e53945 4835 }
43565a06 4836
c751ce4f 4837 num_connectors++;
79e53945
JB		 4838 }
4839
6591c6e4
PZ		 4840 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
4841 &has_reduced_clock, &reduced_clock);
79e53945
JB		 4842 if (!ok) {
4843 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4844 return -EINVAL;
79e53945
JB		 4845 }
4846
cda4b7d3 4847 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4848 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4849
8febb297 4850 /* determine panel color depth */
cc769b62 4851 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
c8203565
PZ		 4852 if (is_lvds && dev_priv->lvds_dither)
4853 dither = true;
4854
a07d6787
EA		 4855 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4856 if (has_reduced_clock)
4857 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4858 reduced_clock.m2;
79e53945 4859
c1858123 4860 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4861 factor = 21;
4862 if (is_lvds) {
4863 if ((intel_panel_use_ssc(dev_priv) &&
4864 dev_priv->lvds_ssc_freq == 100) ||
4865 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4866 factor = 25;
4867 } else if (is_sdvo && is_tv)
4868 factor = 20;
c1858123 4869
cb0e0931 4870 if (clock.m < factor * clock.n)
8febb297 4871 fp |= FP_CB_TUNE;
2c07245f 4872
5eddb70b 4873 dpll = 0;
2c07245f 4874
a07d6787
EA		 4875 if (is_lvds)
4876 dpll |= DPLLB_MODE_LVDS;
4877 else
4878 dpll |= DPLLB_MODE_DAC_SERIAL;
4879 if (is_sdvo) {
4880 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4881 if (pixel_multiplier > 1) {
4882 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4883 }
a07d6787
EA		 4884 dpll |= DPLL_DVO_HIGH_SPEED;
4885 }
e3aef172 4886 if (is_dp && !is_cpu_edp)
a07d6787 4887 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4888
a07d6787
EA		 4889 /* compute bitmask from p1 value */
4890 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4891 /* also FPA1 */
4892 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4893
4894 switch (clock.p2) {
4895 case 5:
4896 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4897 break;
4898 case 7:
4899 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4900 break;
4901 case 10:
4902 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4903 break;
4904 case 14:
4905 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4906 break;
79e53945
JB		 4907 }
4908
43565a06
KH		 4909 if (is_sdvo && is_tv)
4910 dpll |= PLL_REF_INPUT_TVCLKINBC;
4911 else if (is_tv)
79e53945 4912 /* XXX: just matching BIOS for now */
43565a06 4913 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4914 dpll |= 3;
a7615030 4915 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4916 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4917 else
4918 dpll |= PLL_REF_INPUT_DREFCLK;
4919
f7cb34d4 4920 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4921 drm_mode_debug_printmodeline(mode);
4922
9d82aa17
ED		 4923 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4924 * pre-Haswell/LPT generation */
4925 if (HAS_PCH_LPT(dev)) {
4926 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4927 pipe);
4928 } else if (!is_cpu_edp) {
ee7b9f93 4929 struct intel_pch_pll *pll;
4b645f14 4930
ee7b9f93
JB		 4931 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4932 if (pll == NULL) {
4933 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4934 pipe);
4b645f14
JB		 4935 return -EINVAL;
4936 }
ee7b9f93
JB		 4937 } else
4938 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4939
4940 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4941 * This is an exception to the general rule that mode_set doesn't turn
4942 * things on.
4943 */
4944 if (is_lvds) {
fae14981 4945 temp = I915_READ(PCH_LVDS);
5eddb70b 4946 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4947 if (HAS_PCH_CPT(dev)) {
4948 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4949 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4950 } else {
4951 if (pipe == 1)
4952 temp |= LVDS_PIPEB_SELECT;
4953 else
4954 temp &= ~LVDS_PIPEB_SELECT;
4955 }
4b645f14 4956
a3e17eb8 4957 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4958 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4959 /* Set the B0-B3 data pairs corresponding to whether we're going to
4960 * set the DPLLs for dual-channel mode or not.
4961 */
4962 if (clock.p2 == 7)
5eddb70b 4963 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4964 else
5eddb70b 4965 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4966
4967 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4968 * appropriately here, but we need to look more thoroughly into how
4969 * panels behave in the two modes.
4970 */
284d5df5 4971 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4972 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4973 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4974 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4975 temp |= LVDS_VSYNC_POLARITY;
fae14981 4976 I915_WRITE(PCH_LVDS, temp);
79e53945 4977 }
434ed097 4978
e3aef172 4979 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4980 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4981 } else {
8db9d77b 4982 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4983 I915_WRITE(TRANSDATA_M1(pipe), 0);
4984 I915_WRITE(TRANSDATA_N1(pipe), 0);
4985 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4986 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4987 }
79e53945 4988
ee7b9f93
JB		 4989 if (intel_crtc->pch_pll) {
4990 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4991
32f9d658 4992 /* Wait for the clocks to stabilize. */
ee7b9f93 4993 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4994 udelay(150);
4995
8febb297
EA		 4996 /* The pixel multiplier can only be updated once the
4997 * DPLL is enabled and the clocks are stable.
4998 *
4999 * So write it again.
5000 */
ee7b9f93 5001 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5002 }
79e53945 5003
5eddb70b 5004 intel_crtc->lowfreq_avail = false;
ee7b9f93 5005 if (intel_crtc->pch_pll) {
4b645f14 5006 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5007 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5008 intel_crtc->lowfreq_avail = true;
4b645f14 5009 } else {
ee7b9f93 5010 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5011 }
5012 }
5013
734b4157 5014 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157 5015 /* the chip adds 2 halflines automatically */
734b4157 5016 adjusted_mode->crtc_vtotal -= 1;
734b4157 5017 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 5018 I915_WRITE(VSYNCSHIFT(pipe),
5019 adjusted_mode->crtc_hsync_start
5020 - adjusted_mode->crtc_htotal/2);
5021 } else {
0529a0d9
DV		 5022 I915_WRITE(VSYNCSHIFT(pipe), 0);
5023 }
734b4157 5024
5eddb70b
CW		 5025 I915_WRITE(HTOTAL(pipe),
5026 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5027 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5028 I915_WRITE(HBLANK(pipe),
5029 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5030 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5031 I915_WRITE(HSYNC(pipe),
5032 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5033 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5034
5035 I915_WRITE(VTOTAL(pipe),
5036 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5037 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5038 I915_WRITE(VBLANK(pipe),
5039 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5040 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5041 I915_WRITE(VSYNC(pipe),
5042 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5043 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5044
8febb297
EA		 5045 /* pipesrc controls the size that is scaled from, which should
5046 * always be the user's requested size.
79e53945 5047 */
5eddb70b
CW		 5048 I915_WRITE(PIPESRC(pipe),
5049 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5050
f48d8f23 5051 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5052
e3aef172 5053 if (is_cpu_edp)
8febb297 5054 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5055
c8203565 5056 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5057
9d0498a2 5058 intel_wait_for_vblank(dev, pipe);
79e53945 5059
a1f9e77e
PZ		 5060 /* Set up the display plane register */
5061 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5062 POSTING_READ(DSPCNTR(plane));
79e53945 5063
94352cf9 5064 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5065
5066 intel_update_watermarks(dev);
5067
1f8eeabf
ED		 5068 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5069
1f803ee5 5070 return ret;
79e53945
JB		 5071}
5072
f564048e
EA		 5073static int intel_crtc_mode_set(struct drm_crtc *crtc,
5074 struct drm_display_mode *mode,
5075 struct drm_display_mode *adjusted_mode,
5076 int x, int y,
94352cf9 5077 struct drm_framebuffer *fb)
f564048e
EA		 5078{
5079 struct drm_device *dev = crtc->dev;
5080 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5082 int pipe = intel_crtc->pipe;
f564048e
EA		 5083 int ret;
5084
0b701d27 5085 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5086
f564048e 5087 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5088 x, y, fb);
79e53945 5089 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5090
1f803ee5 5091 return ret;
79e53945
JB		 5092}
5093
3a9627f4
WF		 5094static bool intel_eld_uptodate(struct drm_connector *connector,
5095 int reg_eldv, uint32_t bits_eldv,
5096 int reg_elda, uint32_t bits_elda,
5097 int reg_edid)
5098{
5099 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5100 uint8_t *eld = connector->eld;
5101 uint32_t i;
5102
5103 i = I915_READ(reg_eldv);
5104 i &= bits_eldv;
5105
5106 if (!eld[0])
5107 return !i;
5108
5109 if (!i)
5110 return false;
5111
5112 i = I915_READ(reg_elda);
5113 i &= ~bits_elda;
5114 I915_WRITE(reg_elda, i);
5115
5116 for (i = 0; i < eld[2]; i++)
5117 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5118 return false;
5119
5120 return true;
5121}
5122
e0dac65e
WF		 5123static void g4x_write_eld(struct drm_connector *connector,
5124 struct drm_crtc *crtc)
5125{
5126 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5127 uint8_t *eld = connector->eld;
5128 uint32_t eldv;
5129 uint32_t len;
5130 uint32_t i;
5131
5132 i = I915_READ(G4X_AUD_VID_DID);
5133
5134 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5135 eldv = G4X_ELDV_DEVCL_DEVBLC;
5136 else
5137 eldv = G4X_ELDV_DEVCTG;
5138
3a9627f4
WF		 5139 if (intel_eld_uptodate(connector,
5140 G4X_AUD_CNTL_ST, eldv,
5141 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5142 G4X_HDMIW_HDMIEDID))
5143 return;
5144
e0dac65e
WF		 5145 i = I915_READ(G4X_AUD_CNTL_ST);
5146 i &= ~(eldv | G4X_ELD_ADDR);
5147 len = (i >> 9) & 0x1f; /* ELD buffer size */
5148 I915_WRITE(G4X_AUD_CNTL_ST, i);
5149
5150 if (!eld[0])
5151 return;
5152
5153 len = min_t(uint8_t, eld[2], len);
5154 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5155 for (i = 0; i < len; i++)
5156 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5157
5158 i = I915_READ(G4X_AUD_CNTL_ST);
5159 i |= eldv;
5160 I915_WRITE(G4X_AUD_CNTL_ST, i);
5161}
5162
83358c85
WX		 5163static void haswell_write_eld(struct drm_connector *connector,
5164 struct drm_crtc *crtc)
5165{
5166 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5167 uint8_t *eld = connector->eld;
5168 struct drm_device *dev = crtc->dev;
5169 uint32_t eldv;
5170 uint32_t i;
5171 int len;
5172 int pipe = to_intel_crtc(crtc)->pipe;
5173 int tmp;
5174
5175 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5176 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5177 int aud_config = HSW_AUD_CFG(pipe);
5178 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5179
5180
5181 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5182
5183 /* Audio output enable */
5184 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5185 tmp = I915_READ(aud_cntrl_st2);
5186 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5187 I915_WRITE(aud_cntrl_st2, tmp);
5188
5189 /* Wait for 1 vertical blank */
5190 intel_wait_for_vblank(dev, pipe);
5191
5192 /* Set ELD valid state */
5193 tmp = I915_READ(aud_cntrl_st2);
5194 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5195 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5196 I915_WRITE(aud_cntrl_st2, tmp);
5197 tmp = I915_READ(aud_cntrl_st2);
5198 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5199
5200 /* Enable HDMI mode */
5201 tmp = I915_READ(aud_config);
5202 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5203 /* clear N_programing_enable and N_value_index */
5204 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5205 I915_WRITE(aud_config, tmp);
5206
5207 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5208
5209 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5210
5211 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5212 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5213 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5214 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5215 } else
5216 I915_WRITE(aud_config, 0);
5217
5218 if (intel_eld_uptodate(connector,
5219 aud_cntrl_st2, eldv,
5220 aud_cntl_st, IBX_ELD_ADDRESS,
5221 hdmiw_hdmiedid))
5222 return;
5223
5224 i = I915_READ(aud_cntrl_st2);
5225 i &= ~eldv;
5226 I915_WRITE(aud_cntrl_st2, i);
5227
5228 if (!eld[0])
5229 return;
5230
5231 i = I915_READ(aud_cntl_st);
5232 i &= ~IBX_ELD_ADDRESS;
5233 I915_WRITE(aud_cntl_st, i);
5234 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5235 DRM_DEBUG_DRIVER("port num:%d\n", i);
5236
5237 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5238 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5239 for (i = 0; i < len; i++)
5240 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5241
5242 i = I915_READ(aud_cntrl_st2);
5243 i |= eldv;
5244 I915_WRITE(aud_cntrl_st2, i);
5245
5246}
5247
e0dac65e
WF		 5248static void ironlake_write_eld(struct drm_connector *connector,
5249 struct drm_crtc *crtc)
5250{
5251 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5252 uint8_t *eld = connector->eld;
5253 uint32_t eldv;
5254 uint32_t i;
5255 int len;
5256 int hdmiw_hdmiedid;
b6daa025 5257 int aud_config;
e0dac65e
WF		 5258 int aud_cntl_st;
5259 int aud_cntrl_st2;
9b138a83 5260 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5261
b3f33cbf 5262 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5263 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5264 aud_config = IBX_AUD_CFG(pipe);
5265 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5266 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5267 } else {
9b138a83
WX		 5268 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5269 aud_config = CPT_AUD_CFG(pipe);
5270 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5271 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5272 }
5273
9b138a83 5274 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5275
5276 i = I915_READ(aud_cntl_st);
9b138a83 5277 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5278 if (!i) {
5279 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5280 /* operate blindly on all ports */
1202b4c6
WF		 5281 eldv = IBX_ELD_VALIDB;
5282 eldv |= IBX_ELD_VALIDB << 4;
5283 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5284 } else {
5285 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5286 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5287 }
5288
3a9627f4
WF		 5289 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5290 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5291 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5292 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5293 } else
5294 I915_WRITE(aud_config, 0);
e0dac65e 5295
3a9627f4
WF		 5296 if (intel_eld_uptodate(connector,
5297 aud_cntrl_st2, eldv,
5298 aud_cntl_st, IBX_ELD_ADDRESS,
5299 hdmiw_hdmiedid))
5300 return;
5301
e0dac65e
WF		 5302 i = I915_READ(aud_cntrl_st2);
5303 i &= ~eldv;
5304 I915_WRITE(aud_cntrl_st2, i);
5305
5306 if (!eld[0])
5307 return;
5308
e0dac65e 5309 i = I915_READ(aud_cntl_st);
1202b4c6 5310 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5311 I915_WRITE(aud_cntl_st, i);
5312
5313 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5314 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5315 for (i = 0; i < len; i++)
5316 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5317
5318 i = I915_READ(aud_cntrl_st2);
5319 i |= eldv;
5320 I915_WRITE(aud_cntrl_st2, i);
5321}
5322
5323void intel_write_eld(struct drm_encoder *encoder,
5324 struct drm_display_mode *mode)
5325{
5326 struct drm_crtc *crtc = encoder->crtc;
5327 struct drm_connector *connector;
5328 struct drm_device *dev = encoder->dev;
5329 struct drm_i915_private *dev_priv = dev->dev_private;
5330
5331 connector = drm_select_eld(encoder, mode);
5332 if (!connector)
5333 return;
5334
5335 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5336 connector->base.id,
5337 drm_get_connector_name(connector),
5338 connector->encoder->base.id,
5339 drm_get_encoder_name(connector->encoder));
5340
5341 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5342
5343 if (dev_priv->display.write_eld)
5344 dev_priv->display.write_eld(connector, crtc);
5345}
5346
79e53945
JB		 5347/** Loads the palette/gamma unit for the CRTC with the prepared values */
5348void intel_crtc_load_lut(struct drm_crtc *crtc)
5349{
5350 struct drm_device *dev = crtc->dev;
5351 struct drm_i915_private *dev_priv = dev->dev_private;
5352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5353 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5354 int i;
5355
5356 /* The clocks have to be on to load the palette. */
aed3f09d 5357 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5358 return;
5359
f2b115e6 5360 /* use legacy palette for Ironlake */
bad720ff 5361 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5362 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5363
79e53945
JB		 5364 for (i = 0; i < 256; i++) {
5365 I915_WRITE(palreg + 4 * i,
5366 (intel_crtc->lut_r[i] << 16) |
5367 (intel_crtc->lut_g[i] << 8) |
5368 intel_crtc->lut_b[i]);
5369 }
5370}
5371
560b85bb
CW		 5372static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5373{
5374 struct drm_device *dev = crtc->dev;
5375 struct drm_i915_private *dev_priv = dev->dev_private;
5376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5377 bool visible = base != 0;
5378 u32 cntl;
5379
5380 if (intel_crtc->cursor_visible == visible)
5381 return;
5382
9db4a9c7 5383 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5384 if (visible) {
5385 /* On these chipsets we can only modify the base whilst
5386 * the cursor is disabled.
5387 */
9db4a9c7 5388 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5389
5390 cntl &= ~(CURSOR_FORMAT_MASK);
5391 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5392 cntl |= CURSOR_ENABLE |
5393 CURSOR_GAMMA_ENABLE |
5394 CURSOR_FORMAT_ARGB;
5395 } else
5396 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5397 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5398
5399 intel_crtc->cursor_visible = visible;
5400}
5401
5402static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5403{
5404 struct drm_device *dev = crtc->dev;
5405 struct drm_i915_private *dev_priv = dev->dev_private;
5406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5407 int pipe = intel_crtc->pipe;
5408 bool visible = base != 0;
5409
5410 if (intel_crtc->cursor_visible != visible) {
548f245b 5411 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5412 if (base) {
5413 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5414 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5415 cntl |= pipe << 28; /* Connect to correct pipe */
5416 } else {
5417 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5418 cntl |= CURSOR_MODE_DISABLE;
5419 }
9db4a9c7 5420 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5421
5422 intel_crtc->cursor_visible = visible;
5423 }
5424 /* and commit changes on next vblank */
9db4a9c7 5425 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5426}
5427
65a21cd6
JB		 5428static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5429{
5430 struct drm_device *dev = crtc->dev;
5431 struct drm_i915_private *dev_priv = dev->dev_private;
5432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5433 int pipe = intel_crtc->pipe;
5434 bool visible = base != 0;
5435
5436 if (intel_crtc->cursor_visible != visible) {
5437 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5438 if (base) {
5439 cntl &= ~CURSOR_MODE;
5440 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5441 } else {
5442 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5443 cntl |= CURSOR_MODE_DISABLE;
5444 }
5445 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5446
5447 intel_crtc->cursor_visible = visible;
5448 }
5449 /* and commit changes on next vblank */
5450 I915_WRITE(CURBASE_IVB(pipe), base);
5451}
5452
cda4b7d3 5453/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5454static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5455 bool on)
cda4b7d3
CW		 5456{
5457 struct drm_device *dev = crtc->dev;
5458 struct drm_i915_private *dev_priv = dev->dev_private;
5459 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5460 int pipe = intel_crtc->pipe;
5461 int x = intel_crtc->cursor_x;
5462 int y = intel_crtc->cursor_y;
560b85bb 5463 u32 base, pos;
cda4b7d3
CW		 5464 bool visible;
5465
5466 pos = 0;
5467
6b383a7f 5468 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5469 base = intel_crtc->cursor_addr;
5470 if (x > (int) crtc->fb->width)
5471 base = 0;
5472
5473 if (y > (int) crtc->fb->height)
5474 base = 0;
5475 } else
5476 base = 0;
5477
5478 if (x < 0) {
5479 if (x + intel_crtc->cursor_width < 0)
5480 base = 0;
5481
5482 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5483 x = -x;
5484 }
5485 pos |= x << CURSOR_X_SHIFT;
5486
5487 if (y < 0) {
5488 if (y + intel_crtc->cursor_height < 0)
5489 base = 0;
5490
5491 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5492 y = -y;
5493 }
5494 pos |= y << CURSOR_Y_SHIFT;
5495
5496 visible = base != 0;
560b85bb 5497 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5498 return;
5499
0cd83aa9 5500 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5501 I915_WRITE(CURPOS_IVB(pipe), pos);
5502 ivb_update_cursor(crtc, base);
5503 } else {
5504 I915_WRITE(CURPOS(pipe), pos);
5505 if (IS_845G(dev) || IS_I865G(dev))
5506 i845_update_cursor(crtc, base);
5507 else
5508 i9xx_update_cursor(crtc, base);
5509 }
cda4b7d3
CW		 5510}
5511
79e53945 5512static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5513 struct drm_file *file,
79e53945
JB		 5514 uint32_t handle,
5515 uint32_t width, uint32_t height)
5516{
5517 struct drm_device *dev = crtc->dev;
5518 struct drm_i915_private *dev_priv = dev->dev_private;
5519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5520 struct drm_i915_gem_object *obj;
cda4b7d3 5521 uint32_t addr;
3f8bc370 5522 int ret;
79e53945 5523
79e53945
JB		 5524 /* if we want to turn off the cursor ignore width and height */
5525 if (!handle) {
28c97730 5526 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5527 addr = 0;
05394f39 5528 obj = NULL;
5004417d 5529 mutex_lock(&dev->struct_mutex);
3f8bc370 5530 goto finish;
79e53945
JB		 5531 }
5532
5533 /* Currently we only support 64x64 cursors */
5534 if (width != 64 || height != 64) {
5535 DRM_ERROR("we currently only support 64x64 cursors\n");
5536 return -EINVAL;
5537 }
5538
05394f39 5539 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5540 if (&obj->base == NULL)
79e53945
JB		 5541 return -ENOENT;
5542
05394f39 5543 if (obj->base.size < width * height * 4) {
79e53945 5544 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5545 ret = -ENOMEM;
5546 goto fail;
79e53945
JB		 5547 }
5548
71acb5eb 5549 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5550 mutex_lock(&dev->struct_mutex);
b295d1b6 5551 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5552 if (obj->tiling_mode) {
5553 DRM_ERROR("cursor cannot be tiled\n");
5554 ret = -EINVAL;
5555 goto fail_locked;
5556 }
5557
2da3b9b9 5558 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5559 if (ret) {
5560 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5561 goto fail_locked;
e7b526bb
CW		 5562 }
5563
d9e86c0e
CW		 5564 ret = i915_gem_object_put_fence(obj);
5565 if (ret) {
2da3b9b9 5566 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5567 goto fail_unpin;
5568 }
5569
05394f39 5570 addr = obj->gtt_offset;
71acb5eb 5571 } else {
6eeefaf3 5572 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5573 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5574 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5575 align);
71acb5eb
DA		 5576 if (ret) {
5577 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5578 goto fail_locked;
71acb5eb 5579 }
05394f39 5580 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5581 }
5582
a6c45cf0 5583 if (IS_GEN2(dev))
14b60391
JB		 5584 I915_WRITE(CURSIZE, (height << 12) | width);
5585
3f8bc370 5586 finish:
3f8bc370 5587 if (intel_crtc->cursor_bo) {
b295d1b6 5588 if (dev_priv->info->cursor_needs_physical) {
05394f39 5589 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5590 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5591 } else
5592 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5593 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5594 }
80824003 5595
7f9872e0 5596 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5597
5598 intel_crtc->cursor_addr = addr;
05394f39 5599 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5600 intel_crtc->cursor_width = width;
5601 intel_crtc->cursor_height = height;
5602
6b383a7f 5603 intel_crtc_update_cursor(crtc, true);
3f8bc370 5604
79e53945 5605 return 0;
e7b526bb 5606fail_unpin:
05394f39 5607 i915_gem_object_unpin(obj);
7f9872e0 5608fail_locked:
34b8686e 5609 mutex_unlock(&dev->struct_mutex);
bc9025bd 5610fail:
05394f39 5611 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5612 return ret;
79e53945
JB		 5613}
5614
5615static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5616{
79e53945 5617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5618
cda4b7d3
CW		 5619 intel_crtc->cursor_x = x;
5620 intel_crtc->cursor_y = y;
652c393a 5621
6b383a7f 5622 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5623
5624 return 0;
5625}
5626
5627/** Sets the color ramps on behalf of RandR */
5628void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5629 u16 blue, int regno)
5630{
5631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5632
5633 intel_crtc->lut_r[regno] = red >> 8;
5634 intel_crtc->lut_g[regno] = green >> 8;
5635 intel_crtc->lut_b[regno] = blue >> 8;
5636}
5637
b8c00ac5
DA		 5638void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5639 u16 *blue, int regno)
5640{
5641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5642
5643 *red = intel_crtc->lut_r[regno] << 8;
5644 *green = intel_crtc->lut_g[regno] << 8;
5645 *blue = intel_crtc->lut_b[regno] << 8;
5646}
5647
79e53945 5648static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5649 u16 *blue, uint32_t start, uint32_t size)
79e53945 5650{
7203425a 5651 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5653
7203425a 5654 for (i = start; i < end; i++) {
79e53945
JB		 5655 intel_crtc->lut_r[i] = red[i] >> 8;
5656 intel_crtc->lut_g[i] = green[i] >> 8;
5657 intel_crtc->lut_b[i] = blue[i] >> 8;
5658 }
5659
5660 intel_crtc_load_lut(crtc);
5661}
5662
5663/**
5664 * Get a pipe with a simple mode set on it for doing load-based monitor
5665 * detection.
5666 *
5667 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5668 * its requirements. The pipe will be connected to no other encoders.
79e53945 5669 *
c751ce4f 5670 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5671 * configured for it. In the future, it could choose to temporarily disable
5672 * some outputs to free up a pipe for its use.
5673 *
5674 * \return crtc, or NULL if no pipes are available.
5675 */
5676
5677/* VESA 640x480x72Hz mode to set on the pipe */
5678static struct drm_display_mode load_detect_mode = {
5679 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5680 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5681};
5682
d2dff872
CW		 5683static struct drm_framebuffer *
5684intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5685 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5686 struct drm_i915_gem_object *obj)
5687{
5688 struct intel_framebuffer *intel_fb;
5689 int ret;
5690
5691 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5692 if (!intel_fb) {
5693 drm_gem_object_unreference_unlocked(&obj->base);
5694 return ERR_PTR(-ENOMEM);
5695 }
5696
5697 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5698 if (ret) {
5699 drm_gem_object_unreference_unlocked(&obj->base);
5700 kfree(intel_fb);
5701 return ERR_PTR(ret);
5702 }
5703
5704 return &intel_fb->base;
5705}
5706
5707static u32
5708intel_framebuffer_pitch_for_width(int width, int bpp)
5709{
5710 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5711 return ALIGN(pitch, 64);
5712}
5713
5714static u32
5715intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5716{
5717 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5718 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5719}
5720
5721static struct drm_framebuffer *
5722intel_framebuffer_create_for_mode(struct drm_device *dev,
5723 struct drm_display_mode *mode,
5724 int depth, int bpp)
5725{
5726 struct drm_i915_gem_object *obj;
308e5bcb 5727 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5728
5729 obj = i915_gem_alloc_object(dev,
5730 intel_framebuffer_size_for_mode(mode, bpp));
5731 if (obj == NULL)
5732 return ERR_PTR(-ENOMEM);
5733
5734 mode_cmd.width = mode->hdisplay;
5735 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5736 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5737 bpp);
5ca0c34a 5738 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5739
5740 return intel_framebuffer_create(dev, &mode_cmd, obj);
5741}
5742
5743static struct drm_framebuffer *
5744mode_fits_in_fbdev(struct drm_device *dev,
5745 struct drm_display_mode *mode)
5746{
5747 struct drm_i915_private *dev_priv = dev->dev_private;
5748 struct drm_i915_gem_object *obj;
5749 struct drm_framebuffer *fb;
5750
5751 if (dev_priv->fbdev == NULL)
5752 return NULL;
5753
5754 obj = dev_priv->fbdev->ifb.obj;
5755 if (obj == NULL)
5756 return NULL;
5757
5758 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5759 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5760 fb->bits_per_pixel))
d2dff872
CW		 5761 return NULL;
5762
01f2c773 5763 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5764 return NULL;
5765
5766 return fb;
5767}
5768
d2434ab7 5769bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 5770 struct drm_display_mode *mode,
8261b191 5771 struct intel_load_detect_pipe *old)
79e53945
JB		 5772{
5773 struct intel_crtc *intel_crtc;
d2434ab7
DV		 5774 struct intel_encoder *intel_encoder =
5775 intel_attached_encoder(connector);
79e53945 5776 struct drm_crtc *possible_crtc;
4ef69c7a 5777 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5778 struct drm_crtc *crtc = NULL;
5779 struct drm_device *dev = encoder->dev;
94352cf9 5780 struct drm_framebuffer *fb;
79e53945
JB		 5781 int i = -1;
5782
d2dff872
CW		 5783 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5784 connector->base.id, drm_get_connector_name(connector),
5785 encoder->base.id, drm_get_encoder_name(encoder));
5786
79e53945
JB		 5787 /*
5788 * Algorithm gets a little messy:
7a5e4805 5789 *
79e53945
JB		 5790 * - if the connector already has an assigned crtc, use it (but make
5791 * sure it's on first)
7a5e4805 5792 *
79e53945
JB		 5793 * - try to find the first unused crtc that can drive this connector,
5794 * and use that if we find one
79e53945
JB		 5795 */
5796
5797 /* See if we already have a CRTC for this connector */
5798 if (encoder->crtc) {
5799 crtc = encoder->crtc;
8261b191 5800
24218aac 5801 old->dpms_mode = connector->dpms;
8261b191
CW		 5802 old->load_detect_temp = false;
5803
5804 /* Make sure the crtc and connector are running */
24218aac
DV		 5805 if (connector->dpms != DRM_MODE_DPMS_ON)
5806 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 5807
7173188d 5808 return true;
79e53945
JB		 5809 }
5810
5811 /* Find an unused one (if possible) */
5812 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5813 i++;
5814 if (!(encoder->possible_crtcs & (1 << i)))
5815 continue;
5816 if (!possible_crtc->enabled) {
5817 crtc = possible_crtc;
5818 break;
5819 }
79e53945
JB		 5820 }
5821
5822 /*
5823 * If we didn't find an unused CRTC, don't use any.
5824 */
5825 if (!crtc) {
7173188d
CW		 5826 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5827 return false;
79e53945
JB		 5828 }
5829
fc303101
DV		 5830 intel_encoder->new_crtc = to_intel_crtc(crtc);
5831 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 5832
5833 intel_crtc = to_intel_crtc(crtc);
24218aac 5834 old->dpms_mode = connector->dpms;
8261b191 5835 old->load_detect_temp = true;
d2dff872 5836 old->release_fb = NULL;
79e53945 5837
6492711d
CW		 5838 if (!mode)
5839 mode = &load_detect_mode;
79e53945 5840
d2dff872
CW		 5841 /* We need a framebuffer large enough to accommodate all accesses
5842 * that the plane may generate whilst we perform load detection.
5843 * We can not rely on the fbcon either being present (we get called
5844 * during its initialisation to detect all boot displays, or it may
5845 * not even exist) or that it is large enough to satisfy the
5846 * requested mode.
5847 */
94352cf9
DV		 5848 fb = mode_fits_in_fbdev(dev, mode);
5849 if (fb == NULL) {
d2dff872 5850 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 5851 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5852 old->release_fb = fb;
d2dff872
CW		 5853 } else
5854 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 5855 if (IS_ERR(fb)) {
d2dff872 5856 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 5857 goto fail;
79e53945 5858 }
79e53945 5859
94352cf9 5860 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 5861 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5862 if (old->release_fb)
5863 old->release_fb->funcs->destroy(old->release_fb);
24218aac 5864 goto fail;
79e53945 5865 }
7173188d 5866
79e53945 5867 /* let the connector get through one full cycle before testing */
9d0498a2 5868 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5869
7173188d 5870 return true;
24218aac
DV		 5871fail:
5872 connector->encoder = NULL;
5873 encoder->crtc = NULL;
24218aac 5874 return false;
79e53945
JB		 5875}
5876
d2434ab7 5877void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 5878 struct intel_load_detect_pipe *old)
79e53945 5879{
d2434ab7
DV		 5880 struct intel_encoder *intel_encoder =
5881 intel_attached_encoder(connector);
4ef69c7a 5882 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 5883
d2dff872
CW		 5884 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5885 connector->base.id, drm_get_connector_name(connector),
5886 encoder->base.id, drm_get_encoder_name(encoder));
5887
8261b191 5888 if (old->load_detect_temp) {
fc303101
DV		 5889 struct drm_crtc *crtc = encoder->crtc;
5890
5891 to_intel_connector(connector)->new_encoder = NULL;
5892 intel_encoder->new_crtc = NULL;
5893 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 5894
5895 if (old->release_fb)
5896 old->release_fb->funcs->destroy(old->release_fb);
5897
0622a53c 5898 return;
79e53945
JB		 5899 }
5900
c751ce4f 5901 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 5902 if (old->dpms_mode != DRM_MODE_DPMS_ON)
5903 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 5904}
5905
5906/* Returns the clock of the currently programmed mode of the given pipe. */
5907static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5908{
5909 struct drm_i915_private *dev_priv = dev->dev_private;
5910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5911 int pipe = intel_crtc->pipe;
548f245b 5912 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5913 u32 fp;
5914 intel_clock_t clock;
5915
5916 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5917 fp = I915_READ(FP0(pipe));
79e53945 5918 else
39adb7a5 5919 fp = I915_READ(FP1(pipe));
79e53945
JB		 5920
5921 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5922 if (IS_PINEVIEW(dev)) {
5923 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5924 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5925 } else {
5926 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5927 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5928 }
5929
a6c45cf0 5930 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5931 if (IS_PINEVIEW(dev))
5932 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5933 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5934 else
5935 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5936 DPLL_FPA01_P1_POST_DIV_SHIFT);
5937
5938 switch (dpll & DPLL_MODE_MASK) {
5939 case DPLLB_MODE_DAC_SERIAL:
5940 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5941 5 : 10;
5942 break;
5943 case DPLLB_MODE_LVDS:
5944 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5945 7 : 14;
5946 break;
5947 default:
28c97730 5948 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5949 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5950 return 0;
5951 }
5952
5953 /* XXX: Handle the 100Mhz refclk */
2177832f 5954 intel_clock(dev, 96000, &clock);
79e53945
JB		 5955 } else {
5956 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5957
5958 if (is_lvds) {
5959 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5960 DPLL_FPA01_P1_POST_DIV_SHIFT);
5961 clock.p2 = 14;
5962
5963 if ((dpll & PLL_REF_INPUT_MASK) ==
5964 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5965 /* XXX: might not be 66MHz */
2177832f 5966 intel_clock(dev, 66000, &clock);
79e53945 5967 } else
2177832f 5968 intel_clock(dev, 48000, &clock);
79e53945
JB		 5969 } else {
5970 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5971 clock.p1 = 2;
5972 else {
5973 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5974 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5975 }
5976 if (dpll & PLL_P2_DIVIDE_BY_4)
5977 clock.p2 = 4;
5978 else
5979 clock.p2 = 2;
5980
2177832f 5981 intel_clock(dev, 48000, &clock);
79e53945
JB		 5982 }
5983 }
5984
5985 /* XXX: It would be nice to validate the clocks, but we can't reuse
5986 * i830PllIsValid() because it relies on the xf86_config connector
5987 * configuration being accurate, which it isn't necessarily.
5988 */
5989
5990 return clock.dot;
5991}
5992
5993/** Returns the currently programmed mode of the given pipe. */
5994struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5995 struct drm_crtc *crtc)
5996{
548f245b 5997 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5999 int pipe = intel_crtc->pipe;
6000 struct drm_display_mode *mode;
548f245b
JB		 6001 int htot = I915_READ(HTOTAL(pipe));
6002 int hsync = I915_READ(HSYNC(pipe));
6003 int vtot = I915_READ(VTOTAL(pipe));
6004 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6005
6006 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6007 if (!mode)
6008 return NULL;
6009
6010 mode->clock = intel_crtc_clock_get(dev, crtc);
6011 mode->hdisplay = (htot & 0xffff) + 1;
6012 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6013 mode->hsync_start = (hsync & 0xffff) + 1;
6014 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6015 mode->vdisplay = (vtot & 0xffff) + 1;
6016 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6017 mode->vsync_start = (vsync & 0xffff) + 1;
6018 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6019
6020 drm_mode_set_name(mode);
79e53945
JB		 6021
6022 return mode;
6023}
6024
3dec0095 6025static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6026{
6027 struct drm_device *dev = crtc->dev;
6028 drm_i915_private_t *dev_priv = dev->dev_private;
6029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6030 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6031 int dpll_reg = DPLL(pipe);
6032 int dpll;
652c393a 6033
bad720ff 6034 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6035 return;
6036
6037 if (!dev_priv->lvds_downclock_avail)
6038 return;
6039
dbdc6479 6040 dpll = I915_READ(dpll_reg);
652c393a 6041 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6042 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6043
8ac5a6d5 6044 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6045
6046 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6047 I915_WRITE(dpll_reg, dpll);
9d0498a2 6048 intel_wait_for_vblank(dev, pipe);
dbdc6479 6049
652c393a
JB		 6050 dpll = I915_READ(dpll_reg);
6051 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6052 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6053 }
652c393a
JB		 6054}
6055
6056static void intel_decrease_pllclock(struct drm_crtc *crtc)
6057{
6058 struct drm_device *dev = crtc->dev;
6059 drm_i915_private_t *dev_priv = dev->dev_private;
6060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6061
bad720ff 6062 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6063 return;
6064
6065 if (!dev_priv->lvds_downclock_avail)
6066 return;
6067
6068 /*
6069 * Since this is called by a timer, we should never get here in
6070 * the manual case.
6071 */
6072 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6073 int pipe = intel_crtc->pipe;
6074 int dpll_reg = DPLL(pipe);
6075 int dpll;
f6e5b160 6076
44d98a61 6077 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6078
8ac5a6d5 6079 assert_panel_unlocked(dev_priv, pipe);
652c393a 6080
dc257cf1 6081 dpll = I915_READ(dpll_reg);
652c393a
JB		 6082 dpll |= DISPLAY_RATE_SELECT_FPA1;
6083 I915_WRITE(dpll_reg, dpll);
9d0498a2 6084 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6085 dpll = I915_READ(dpll_reg);
6086 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6087 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6088 }
6089
6090}
6091
f047e395
CW		 6092void intel_mark_busy(struct drm_device *dev)
6093{
f047e395
CW		 6094 i915_update_gfx_val(dev->dev_private);
6095}
6096
6097void intel_mark_idle(struct drm_device *dev)
652c393a 6098{
f047e395
CW		 6099}
6100
6101void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6102{
6103 struct drm_device *dev = obj->base.dev;
652c393a 6104 struct drm_crtc *crtc;
652c393a
JB		 6105
6106 if (!i915_powersave)
6107 return;
6108
652c393a 6109 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6110 if (!crtc->fb)
6111 continue;
6112
f047e395
CW		 6113 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6114 intel_increase_pllclock(crtc);
652c393a 6115 }
652c393a
JB		 6116}
6117
f047e395 6118void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6119{
f047e395
CW		 6120 struct drm_device *dev = obj->base.dev;
6121 struct drm_crtc *crtc;
652c393a 6122
f047e395 6123 if (!i915_powersave)
acb87dfb
CW		 6124 return;
6125
652c393a
JB		 6126 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6127 if (!crtc->fb)
6128 continue;
6129
f047e395
CW		 6130 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6131 intel_decrease_pllclock(crtc);
652c393a
JB		 6132 }
6133}
6134
79e53945
JB		 6135static void intel_crtc_destroy(struct drm_crtc *crtc)
6136{
6137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6138 struct drm_device *dev = crtc->dev;
6139 struct intel_unpin_work *work;
6140 unsigned long flags;
6141
6142 spin_lock_irqsave(&dev->event_lock, flags);
6143 work = intel_crtc->unpin_work;
6144 intel_crtc->unpin_work = NULL;
6145 spin_unlock_irqrestore(&dev->event_lock, flags);
6146
6147 if (work) {
6148 cancel_work_sync(&work->work);
6149 kfree(work);
6150 }
79e53945
JB		 6151
6152 drm_crtc_cleanup(crtc);
67e77c5a 6153
79e53945
JB		 6154 kfree(intel_crtc);
6155}
6156
6b95a207
KH		 6157static void intel_unpin_work_fn(struct work_struct *__work)
6158{
6159 struct intel_unpin_work *work =
6160 container_of(__work, struct intel_unpin_work, work);
6161
6162 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6163 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6164 drm_gem_object_unreference(&work->pending_flip_obj->base);
6165 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6166
7782de3b 6167 intel_update_fbc(work->dev);
6b95a207
KH		 6168 mutex_unlock(&work->dev->struct_mutex);
6169 kfree(work);
6170}
6171
1afe3e9d 6172static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6173 struct drm_crtc *crtc)
6b95a207
KH		 6174{
6175 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6177 struct intel_unpin_work *work;
05394f39 6178 struct drm_i915_gem_object *obj;
6b95a207 6179 struct drm_pending_vblank_event *e;
49b14a5c 6180 struct timeval tnow, tvbl;
6b95a207
KH		 6181 unsigned long flags;
6182
6183 /* Ignore early vblank irqs */
6184 if (intel_crtc == NULL)
6185 return;
6186
49b14a5c
MK		 6187 do_gettimeofday(&tnow);
6188
6b95a207
KH		 6189 spin_lock_irqsave(&dev->event_lock, flags);
6190 work = intel_crtc->unpin_work;
6191 if (work == NULL || !work->pending) {
6192 spin_unlock_irqrestore(&dev->event_lock, flags);
6193 return;
6194 }
6195
6196 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6197
6198 if (work->event) {
6199 e = work->event;
49b14a5c 6200 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6201
6202 /* Called before vblank count and timestamps have
6203 * been updated for the vblank interval of flip
6204 * completion? Need to increment vblank count and
6205 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6206 * to account for this. We assume this happened if we
6207 * get called over 0.9 frame durations after the last
6208 * timestamped vblank.
6209 *
6210 * This calculation can not be used with vrefresh rates
6211 * below 5Hz (10Hz to be on the safe side) without
6212 * promoting to 64 integers.
0af7e4df 6213 */
49b14a5c
MK		 6214 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6215 9 * crtc->framedur_ns) {
0af7e4df 6216 e->event.sequence++;
49b14a5c
MK		 6217 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6218 crtc->framedur_ns);
0af7e4df
MK		 6219 }
6220
49b14a5c
MK		 6221 e->event.tv_sec = tvbl.tv_sec;
6222 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6223
6b95a207
KH		 6224 list_add_tail(&e->base.link,
6225 &e->base.file_priv->event_list);
6226 wake_up_interruptible(&e->base.file_priv->event_wait);
6227 }
6228
0af7e4df
MK		 6229 drm_vblank_put(dev, intel_crtc->pipe);
6230
6b95a207
KH		 6231 spin_unlock_irqrestore(&dev->event_lock, flags);
6232
05394f39 6233 obj = work->old_fb_obj;
d9e86c0e 6234
e59f2bac 6235 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6236 &obj->pending_flip.counter);
6237 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6238 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6239
6b95a207 6240 schedule_work(&work->work);
e5510fac
JB		 6241
6242 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6243}
6244
1afe3e9d
JB		 6245void intel_finish_page_flip(struct drm_device *dev, int pipe)
6246{
6247 drm_i915_private_t *dev_priv = dev->dev_private;
6248 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6249
49b14a5c 6250 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6251}
6252
6253void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6254{
6255 drm_i915_private_t *dev_priv = dev->dev_private;
6256 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6257
49b14a5c 6258 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6259}
6260
6b95a207
KH		 6261void intel_prepare_page_flip(struct drm_device *dev, int plane)
6262{
6263 drm_i915_private_t *dev_priv = dev->dev_private;
6264 struct intel_crtc *intel_crtc =
6265 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6266 unsigned long flags;
6267
6268 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6269 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6270 if ((++intel_crtc->unpin_work->pending) > 1)
6271 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6272 } else {
6273 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6274 }
6b95a207
KH		 6275 spin_unlock_irqrestore(&dev->event_lock, flags);
6276}
6277
8c9f3aaf
JB		 6278static int intel_gen2_queue_flip(struct drm_device *dev,
6279 struct drm_crtc *crtc,
6280 struct drm_framebuffer *fb,
6281 struct drm_i915_gem_object *obj)
6282{
6283 struct drm_i915_private *dev_priv = dev->dev_private;
6284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6285 u32 flip_mask;
6d90c952 6286 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6287 int ret;
6288
6d90c952 6289 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6290 if (ret)
83d4092b 6291 goto err;
8c9f3aaf 6292
6d90c952 6293 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6294 if (ret)
83d4092b 6295 goto err_unpin;
8c9f3aaf
JB		 6296
6297 /* Can't queue multiple flips, so wait for the previous
6298 * one to finish before executing the next.
6299 */
6300 if (intel_crtc->plane)
6301 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6302 else
6303 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6304 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6305 intel_ring_emit(ring, MI_NOOP);
6306 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6307 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6308 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6309 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6310 intel_ring_emit(ring, 0); /* aux display base address, unused */
6311 intel_ring_advance(ring);
83d4092b
CW		 6312 return 0;
6313
6314err_unpin:
6315 intel_unpin_fb_obj(obj);
6316err:
8c9f3aaf
JB		 6317 return ret;
6318}
6319
6320static int intel_gen3_queue_flip(struct drm_device *dev,
6321 struct drm_crtc *crtc,
6322 struct drm_framebuffer *fb,
6323 struct drm_i915_gem_object *obj)
6324{
6325 struct drm_i915_private *dev_priv = dev->dev_private;
6326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6327 u32 flip_mask;
6d90c952 6328 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6329 int ret;
6330
6d90c952 6331 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6332 if (ret)
83d4092b 6333 goto err;
8c9f3aaf 6334
6d90c952 6335 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6336 if (ret)
83d4092b 6337 goto err_unpin;
8c9f3aaf
JB		 6338
6339 if (intel_crtc->plane)
6340 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6341 else
6342 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6343 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6344 intel_ring_emit(ring, MI_NOOP);
6345 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6346 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6347 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6348 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6349 intel_ring_emit(ring, MI_NOOP);
6350
6351 intel_ring_advance(ring);
83d4092b
CW		 6352 return 0;
6353
6354err_unpin:
6355 intel_unpin_fb_obj(obj);
6356err:
8c9f3aaf
JB		 6357 return ret;
6358}
6359
6360static int intel_gen4_queue_flip(struct drm_device *dev,
6361 struct drm_crtc *crtc,
6362 struct drm_framebuffer *fb,
6363 struct drm_i915_gem_object *obj)
6364{
6365 struct drm_i915_private *dev_priv = dev->dev_private;
6366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6367 uint32_t pf, pipesrc;
6d90c952 6368 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6369 int ret;
6370
6d90c952 6371 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6372 if (ret)
83d4092b 6373 goto err;
8c9f3aaf 6374
6d90c952 6375 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6376 if (ret)
83d4092b 6377 goto err_unpin;
8c9f3aaf
JB		 6378
6379 /* i965+ uses the linear or tiled offsets from the
6380 * Display Registers (which do not change across a page-flip)
6381 * so we need only reprogram the base address.
6382 */
6d90c952
DV		 6383 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6384 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6385 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6386 intel_ring_emit(ring,
6387 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6388 obj->tiling_mode);
8c9f3aaf
JB		 6389
6390 /* XXX Enabling the panel-fitter across page-flip is so far
6391 * untested on non-native modes, so ignore it for now.
6392 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6393 */
6394 pf = 0;
6395 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6396 intel_ring_emit(ring, pf | pipesrc);
6397 intel_ring_advance(ring);
83d4092b
CW		 6398 return 0;
6399
6400err_unpin:
6401 intel_unpin_fb_obj(obj);
6402err:
8c9f3aaf
JB		 6403 return ret;
6404}
6405
6406static int intel_gen6_queue_flip(struct drm_device *dev,
6407 struct drm_crtc *crtc,
6408 struct drm_framebuffer *fb,
6409 struct drm_i915_gem_object *obj)
6410{
6411 struct drm_i915_private *dev_priv = dev->dev_private;
6412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6413 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6414 uint32_t pf, pipesrc;
6415 int ret;
6416
6d90c952 6417 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6418 if (ret)
83d4092b 6419 goto err;
8c9f3aaf 6420
6d90c952 6421 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6422 if (ret)
83d4092b 6423 goto err_unpin;
8c9f3aaf 6424
6d90c952
DV		 6425 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6426 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6427 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 6428 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 6429
dc257cf1
DV		 6430 /* Contrary to the suggestions in the documentation,
6431 * "Enable Panel Fitter" does not seem to be required when page
6432 * flipping with a non-native mode, and worse causes a normal
6433 * modeset to fail.
6434 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6435 */
6436 pf = 0;
8c9f3aaf 6437 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6438 intel_ring_emit(ring, pf | pipesrc);
6439 intel_ring_advance(ring);
83d4092b
CW		 6440 return 0;
6441
6442err_unpin:
6443 intel_unpin_fb_obj(obj);
6444err:
8c9f3aaf
JB		 6445 return ret;
6446}
6447
7c9017e5
JB		 6448/*
6449 * On gen7 we currently use the blit ring because (in early silicon at least)
6450 * the render ring doesn't give us interrpts for page flip completion, which
6451 * means clients will hang after the first flip is queued. Fortunately the
6452 * blit ring generates interrupts properly, so use it instead.
6453 */
6454static int intel_gen7_queue_flip(struct drm_device *dev,
6455 struct drm_crtc *crtc,
6456 struct drm_framebuffer *fb,
6457 struct drm_i915_gem_object *obj)
6458{
6459 struct drm_i915_private *dev_priv = dev->dev_private;
6460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6461 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 6462 uint32_t plane_bit = 0;
7c9017e5
JB		 6463 int ret;
6464
6465 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6466 if (ret)
83d4092b 6467 goto err;
7c9017e5 6468
cb05d8de
DV		 6469 switch(intel_crtc->plane) {
6470 case PLANE_A:
6471 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6472 break;
6473 case PLANE_B:
6474 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6475 break;
6476 case PLANE_C:
6477 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6478 break;
6479 default:
6480 WARN_ONCE(1, "unknown plane in flip command\n");
6481 ret = -ENODEV;
ab3951eb 6482 goto err_unpin;
cb05d8de
DV		 6483 }
6484
7c9017e5
JB		 6485 ret = intel_ring_begin(ring, 4);
6486 if (ret)
83d4092b 6487 goto err_unpin;
7c9017e5 6488
cb05d8de 6489 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 6490 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 6491 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 6492 intel_ring_emit(ring, (MI_NOOP));
6493 intel_ring_advance(ring);
83d4092b
CW		 6494 return 0;
6495
6496err_unpin:
6497 intel_unpin_fb_obj(obj);
6498err:
7c9017e5
JB		 6499 return ret;
6500}
6501
8c9f3aaf
JB		 6502static int intel_default_queue_flip(struct drm_device *dev,
6503 struct drm_crtc *crtc,
6504 struct drm_framebuffer *fb,
6505 struct drm_i915_gem_object *obj)
6506{
6507 return -ENODEV;
6508}
6509
6b95a207
KH		 6510static int intel_crtc_page_flip(struct drm_crtc *crtc,
6511 struct drm_framebuffer *fb,
6512 struct drm_pending_vblank_event *event)
6513{
6514 struct drm_device *dev = crtc->dev;
6515 struct drm_i915_private *dev_priv = dev->dev_private;
6516 struct intel_framebuffer *intel_fb;
05394f39 6517 struct drm_i915_gem_object *obj;
6b95a207
KH		 6518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6519 struct intel_unpin_work *work;
8c9f3aaf 6520 unsigned long flags;
52e68630 6521 int ret;
6b95a207 6522
e6a595d2
VS		 6523 /* Can't change pixel format via MI display flips. */
6524 if (fb->pixel_format != crtc->fb->pixel_format)
6525 return -EINVAL;
6526
6527 /*
6528 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6529 * Note that pitch changes could also affect these register.
6530 */
6531 if (INTEL_INFO(dev)->gen > 3 &&
6532 (fb->offsets[0] != crtc->fb->offsets[0] ||
6533 fb->pitches[0] != crtc->fb->pitches[0]))
6534 return -EINVAL;
6535
6b95a207
KH		 6536 work = kzalloc(sizeof *work, GFP_KERNEL);
6537 if (work == NULL)
6538 return -ENOMEM;
6539
6b95a207
KH		 6540 work->event = event;
6541 work->dev = crtc->dev;
6542 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6543 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6544 INIT_WORK(&work->work, intel_unpin_work_fn);
6545
7317c75e
JB		 6546 ret = drm_vblank_get(dev, intel_crtc->pipe);
6547 if (ret)
6548 goto free_work;
6549
6b95a207
KH		 6550 /* We borrow the event spin lock for protecting unpin_work */
6551 spin_lock_irqsave(&dev->event_lock, flags);
6552 if (intel_crtc->unpin_work) {
6553 spin_unlock_irqrestore(&dev->event_lock, flags);
6554 kfree(work);
7317c75e 6555 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6556
6557 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6558 return -EBUSY;
6559 }
6560 intel_crtc->unpin_work = work;
6561 spin_unlock_irqrestore(&dev->event_lock, flags);
6562
6563 intel_fb = to_intel_framebuffer(fb);
6564 obj = intel_fb->obj;
6565
79158103
CW		 6566 ret = i915_mutex_lock_interruptible(dev);
6567 if (ret)
6568 goto cleanup;
6b95a207 6569
75dfca80 6570 /* Reference the objects for the scheduled work. */
05394f39
CW		 6571 drm_gem_object_reference(&work->old_fb_obj->base);
6572 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6573
6574 crtc->fb = fb;
96b099fd 6575
e1f99ce6 6576 work->pending_flip_obj = obj;
e1f99ce6 6577
4e5359cd
SF		 6578 work->enable_stall_check = true;
6579
e1f99ce6
CW		 6580 /* Block clients from rendering to the new back buffer until
6581 * the flip occurs and the object is no longer visible.
6582 */
05394f39 6583 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6584
8c9f3aaf
JB		 6585 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6586 if (ret)
6587 goto cleanup_pending;
6b95a207 6588
7782de3b 6589 intel_disable_fbc(dev);
f047e395 6590 intel_mark_fb_busy(obj);
6b95a207
KH		 6591 mutex_unlock(&dev->struct_mutex);
6592
e5510fac
JB		 6593 trace_i915_flip_request(intel_crtc->plane, obj);
6594
6b95a207 6595 return 0;
96b099fd 6596
8c9f3aaf
JB		 6597cleanup_pending:
6598 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6599 drm_gem_object_unreference(&work->old_fb_obj->base);
6600 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6601 mutex_unlock(&dev->struct_mutex);
6602
79158103 6603cleanup:
96b099fd
CW		 6604 spin_lock_irqsave(&dev->event_lock, flags);
6605 intel_crtc->unpin_work = NULL;
6606 spin_unlock_irqrestore(&dev->event_lock, flags);
6607
7317c75e
JB		 6608 drm_vblank_put(dev, intel_crtc->pipe);
6609free_work:
96b099fd
CW		 6610 kfree(work);
6611
6612 return ret;
6b95a207
KH		 6613}
6614
f6e5b160 6615static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 6616 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6617 .load_lut = intel_crtc_load_lut,
976f8a20 6618 .disable = intel_crtc_noop,
f6e5b160
CW		 6619};
6620
6ed0f796 6621bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 6622{
6ed0f796
DV		 6623 struct intel_encoder *other_encoder;
6624 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 6625
6ed0f796
DV		 6626 if (WARN_ON(!crtc))
6627 return false;
6628
6629 list_for_each_entry(other_encoder,
6630 &crtc->dev->mode_config.encoder_list,
6631 base.head) {
6632
6633 if (&other_encoder->new_crtc->base != crtc ||
6634 encoder == other_encoder)
6635 continue;
6636 else
6637 return true;
f47166d2
CW		 6638 }
6639
6ed0f796
DV		 6640 return false;
6641}
47f1c6c9 6642
50f56119
DV		 6643static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6644 struct drm_crtc *crtc)
6645{
6646 struct drm_device *dev;
6647 struct drm_crtc *tmp;
6648 int crtc_mask = 1;
47f1c6c9 6649
50f56119 6650 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 6651
50f56119 6652 dev = crtc->dev;
47f1c6c9 6653
50f56119
DV		 6654 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6655 if (tmp == crtc)
6656 break;
6657 crtc_mask <<= 1;
6658 }
47f1c6c9 6659
50f56119
DV		 6660 if (encoder->possible_crtcs & crtc_mask)
6661 return true;
6662 return false;
47f1c6c9 6663}
79e53945 6664
9a935856
DV		 6665/**
6666 * intel_modeset_update_staged_output_state
6667 *
6668 * Updates the staged output configuration state, e.g. after we've read out the
6669 * current hw state.
6670 */
6671static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 6672{
9a935856
DV		 6673 struct intel_encoder *encoder;
6674 struct intel_connector *connector;
f6e5b160 6675
9a935856
DV		 6676 list_for_each_entry(connector, &dev->mode_config.connector_list,
6677 base.head) {
6678 connector->new_encoder =
6679 to_intel_encoder(connector->base.encoder);
6680 }
f6e5b160 6681
9a935856
DV		 6682 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6683 base.head) {
6684 encoder->new_crtc =
6685 to_intel_crtc(encoder->base.crtc);
6686 }
f6e5b160
CW		 6687}
6688
9a935856
DV		 6689/**
6690 * intel_modeset_commit_output_state
6691 *
6692 * This function copies the stage display pipe configuration to the real one.
6693 */
6694static void intel_modeset_commit_output_state(struct drm_device *dev)
6695{
6696 struct intel_encoder *encoder;
6697 struct intel_connector *connector;
f6e5b160 6698
9a935856
DV		 6699 list_for_each_entry(connector, &dev->mode_config.connector_list,
6700 base.head) {
6701 connector->base.encoder = &connector->new_encoder->base;
6702 }
f6e5b160 6703
9a935856
DV		 6704 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6705 base.head) {
6706 encoder->base.crtc = &encoder->new_crtc->base;
6707 }
6708}
6709
7758a113
DV		 6710static struct drm_display_mode *
6711intel_modeset_adjusted_mode(struct drm_crtc *crtc,
6712 struct drm_display_mode *mode)
ee7b9f93 6713{
7758a113
DV		 6714 struct drm_device *dev = crtc->dev;
6715 struct drm_display_mode *adjusted_mode;
6716 struct drm_encoder_helper_funcs *encoder_funcs;
6717 struct intel_encoder *encoder;
ee7b9f93 6718
7758a113
DV		 6719 adjusted_mode = drm_mode_duplicate(dev, mode);
6720 if (!adjusted_mode)
6721 return ERR_PTR(-ENOMEM);
6722
6723 /* Pass our mode to the connectors and the CRTC to give them a chance to
6724 * adjust it according to limitations or connector properties, and also
6725 * a chance to reject the mode entirely.
6726 */
6727 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6728 base.head) {
6729
6730 if (&encoder->new_crtc->base != crtc)
6731 continue;
6732 encoder_funcs = encoder->base.helper_private;
6733 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
6734 adjusted_mode))) {
6735 DRM_DEBUG_KMS("Encoder fixup failed\n");
6736 goto fail;
6737 }
ee7b9f93
JB		 6738 }
6739
7758a113
DV		 6740 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
6741 DRM_DEBUG_KMS("CRTC fixup failed\n");
6742 goto fail;
ee7b9f93 6743 }
7758a113
DV		 6744 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6745
6746 return adjusted_mode;
6747fail:
6748 drm_mode_destroy(dev, adjusted_mode);
6749 return ERR_PTR(-EINVAL);
ee7b9f93
JB		 6750}
6751
e2e1ed41
DV		 6752/* Computes which crtcs are affected and sets the relevant bits in the mask. For
6753 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
6754static void
6755intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
6756 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 6757{
6758 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 6759 struct drm_device *dev = crtc->dev;
6760 struct intel_encoder *encoder;
6761 struct intel_connector *connector;
6762 struct drm_crtc *tmp_crtc;
79e53945 6763
e2e1ed41 6764 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 6765
e2e1ed41
DV		 6766 /* Check which crtcs have changed outputs connected to them, these need
6767 * to be part of the prepare_pipes mask. We don't (yet) support global
6768 * modeset across multiple crtcs, so modeset_pipes will only have one
6769 * bit set at most. */
6770 list_for_each_entry(connector, &dev->mode_config.connector_list,
6771 base.head) {
6772 if (connector->base.encoder == &connector->new_encoder->base)
6773 continue;
79e53945 6774
e2e1ed41
DV		 6775 if (connector->base.encoder) {
6776 tmp_crtc = connector->base.encoder->crtc;
6777
6778 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6779 }
6780
6781 if (connector->new_encoder)
6782 *prepare_pipes |=
6783 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 6784 }
6785
e2e1ed41
DV		 6786 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6787 base.head) {
6788 if (encoder->base.crtc == &encoder->new_crtc->base)
6789 continue;
6790
6791 if (encoder->base.crtc) {
6792 tmp_crtc = encoder->base.crtc;
6793
6794 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6795 }
6796
6797 if (encoder->new_crtc)
6798 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 6799 }
6800
e2e1ed41
DV		 6801 /* Check for any pipes that will be fully disabled ... */
6802 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6803 base.head) {
6804 bool used = false;
22fd0fab 6805
e2e1ed41
DV		 6806 /* Don't try to disable disabled crtcs. */
6807 if (!intel_crtc->base.enabled)
6808 continue;
7e7d76c3 6809
e2e1ed41
DV		 6810 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6811 base.head) {
6812 if (encoder->new_crtc == intel_crtc)
6813 used = true;
6814 }
6815
6816 if (!used)
6817 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 6818 }
6819
e2e1ed41
DV		 6820
6821 /* set_mode is also used to update properties on life display pipes. */
6822 intel_crtc = to_intel_crtc(crtc);
6823 if (crtc->enabled)
6824 *prepare_pipes |= 1 << intel_crtc->pipe;
6825
6826 /* We only support modeset on one single crtc, hence we need to do that
6827 * only for the passed in crtc iff we change anything else than just
6828 * disable crtcs.
6829 *
6830 * This is actually not true, to be fully compatible with the old crtc
6831 * helper we automatically disable _any_ output (i.e. doesn't need to be
6832 * connected to the crtc we're modesetting on) if it's disconnected.
6833 * Which is a rather nutty api (since changed the output configuration
6834 * without userspace's explicit request can lead to confusion), but
6835 * alas. Hence we currently need to modeset on all pipes we prepare. */
6836 if (*prepare_pipes)
6837 *modeset_pipes = *prepare_pipes;
6838
6839 /* ... and mask these out. */
6840 *modeset_pipes &= ~(*disable_pipes);
6841 *prepare_pipes &= ~(*disable_pipes);
6842}
6843
ea9d758d
DV		 6844static bool intel_crtc_in_use(struct drm_crtc *crtc)
6845{
6846 struct drm_encoder *encoder;
6847 struct drm_device *dev = crtc->dev;
6848
6849 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
6850 if (encoder->crtc == crtc)
6851 return true;
6852
6853 return false;
6854}
6855
6856static void
6857intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
6858{
6859 struct intel_encoder *intel_encoder;
6860 struct intel_crtc *intel_crtc;
6861 struct drm_connector *connector;
6862
6863 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
6864 base.head) {
6865 if (!intel_encoder->base.crtc)
6866 continue;
6867
6868 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
6869
6870 if (prepare_pipes & (1 << intel_crtc->pipe))
6871 intel_encoder->connectors_active = false;
6872 }
6873
6874 intel_modeset_commit_output_state(dev);
6875
6876 /* Update computed state. */
6877 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6878 base.head) {
6879 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
6880 }
6881
6882 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6883 if (!connector->encoder || !connector->encoder->crtc)
6884 continue;
6885
6886 intel_crtc = to_intel_crtc(connector->encoder->crtc);
6887
6888 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 6889 struct drm_property *dpms_property =
6890 dev->mode_config.dpms_property;
6891
ea9d758d 6892 connector->dpms = DRM_MODE_DPMS_ON;
68d34720
DV		 6893 drm_connector_property_set_value(connector,
6894 dpms_property,
6895 DRM_MODE_DPMS_ON);
ea9d758d
DV		 6896
6897 intel_encoder = to_intel_encoder(connector->encoder);
6898 intel_encoder->connectors_active = true;
6899 }
6900 }
6901
6902}
6903
25c5b266
DV		 6904#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
6905 list_for_each_entry((intel_crtc), \
6906 &(dev)->mode_config.crtc_list, \
6907 base.head) \
6908 if (mask & (1 <<(intel_crtc)->pipe)) \
6909
b980514c 6910void
8af6cf88
DV		 6911intel_modeset_check_state(struct drm_device *dev)
6912{
6913 struct intel_crtc *crtc;
6914 struct intel_encoder *encoder;
6915 struct intel_connector *connector;
6916
6917 list_for_each_entry(connector, &dev->mode_config.connector_list,
6918 base.head) {
6919 /* This also checks the encoder/connector hw state with the
6920 * ->get_hw_state callbacks. */
6921 intel_connector_check_state(connector);
6922
6923 WARN(&connector->new_encoder->base != connector->base.encoder,
6924 "connector's staged encoder doesn't match current encoder\n");
6925 }
6926
6927 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6928 base.head) {
6929 bool enabled = false;
6930 bool active = false;
6931 enum pipe pipe, tracked_pipe;
6932
6933 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
6934 encoder->base.base.id,
6935 drm_get_encoder_name(&encoder->base));
6936
6937 WARN(&encoder->new_crtc->base != encoder->base.crtc,
6938 "encoder's stage crtc doesn't match current crtc\n");
6939 WARN(encoder->connectors_active && !encoder->base.crtc,
6940 "encoder's active_connectors set, but no crtc\n");
6941
6942 list_for_each_entry(connector, &dev->mode_config.connector_list,
6943 base.head) {
6944 if (connector->base.encoder != &encoder->base)
6945 continue;
6946 enabled = true;
6947 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
6948 active = true;
6949 }
6950 WARN(!!encoder->base.crtc != enabled,
6951 "encoder's enabled state mismatch "
6952 "(expected %i, found %i)\n",
6953 !!encoder->base.crtc, enabled);
6954 WARN(active && !encoder->base.crtc,
6955 "active encoder with no crtc\n");
6956
6957 WARN(encoder->connectors_active != active,
6958 "encoder's computed active state doesn't match tracked active state "
6959 "(expected %i, found %i)\n", active, encoder->connectors_active);
6960
6961 active = encoder->get_hw_state(encoder, &pipe);
6962 WARN(active != encoder->connectors_active,
6963 "encoder's hw state doesn't match sw tracking "
6964 "(expected %i, found %i)\n",
6965 encoder->connectors_active, active);
6966
6967 if (!encoder->base.crtc)
6968 continue;
6969
6970 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
6971 WARN(active && pipe != tracked_pipe,
6972 "active encoder's pipe doesn't match"
6973 "(expected %i, found %i)\n",
6974 tracked_pipe, pipe);
6975
6976 }
6977
6978 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
6979 base.head) {
6980 bool enabled = false;
6981 bool active = false;
6982
6983 DRM_DEBUG_KMS("[CRTC:%d]\n",
6984 crtc->base.base.id);
6985
6986 WARN(crtc->active && !crtc->base.enabled,
6987 "active crtc, but not enabled in sw tracking\n");
6988
6989 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6990 base.head) {
6991 if (encoder->base.crtc != &crtc->base)
6992 continue;
6993 enabled = true;
6994 if (encoder->connectors_active)
6995 active = true;
6996 }
6997 WARN(active != crtc->active,
6998 "crtc's computed active state doesn't match tracked active state "
6999 "(expected %i, found %i)\n", active, crtc->active);
7000 WARN(enabled != crtc->base.enabled,
7001 "crtc's computed enabled state doesn't match tracked enabled state "
7002 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7003
7004 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7005 }
7006}
7007
a6778b3c
DV		 7008bool intel_set_mode(struct drm_crtc *crtc,
7009 struct drm_display_mode *mode,
94352cf9 7010 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7011{
7012 struct drm_device *dev = crtc->dev;
dbf2b54e 7013 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7014 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
a6778b3c 7015 struct drm_encoder_helper_funcs *encoder_funcs;
a6778b3c 7016 struct drm_encoder *encoder;
25c5b266
DV		 7017 struct intel_crtc *intel_crtc;
7018 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7019 bool ret = true;
7020
e2e1ed41 7021 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7022 &prepare_pipes, &disable_pipes);
7023
7024 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7025 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7026
976f8a20
DV		 7027 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7028 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7029
a6778b3c
DV		 7030 saved_hwmode = crtc->hwmode;
7031 saved_mode = crtc->mode;
a6778b3c 7032
25c5b266
DV		 7033 /* Hack: Because we don't (yet) support global modeset on multiple
7034 * crtcs, we don't keep track of the new mode for more than one crtc.
7035 * Hence simply check whether any bit is set in modeset_pipes in all the
7036 * pieces of code that are not yet converted to deal with mutliple crtcs
7037 * changing their mode at the same time. */
7038 adjusted_mode = NULL;
7039 if (modeset_pipes) {
7040 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7041 if (IS_ERR(adjusted_mode)) {
7042 return false;
7043 }
25c5b266 7044 }
a6778b3c 7045
ea9d758d
DV		 7046 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7047 if (intel_crtc->base.enabled)
7048 dev_priv->display.crtc_disable(&intel_crtc->base);
7049 }
a6778b3c 7050
6c4c86f5
DV		 7051 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7052 * to set it here already despite that we pass it down the callchain.
7053 */
7054 if (modeset_pipes)
25c5b266 7055 crtc->mode = *mode;
7758a113 7056
ea9d758d
DV		 7057 /* Only after disabling all output pipelines that will be changed can we
7058 * update the the output configuration. */
7059 intel_modeset_update_state(dev, prepare_pipes);
7060
a6778b3c
DV		 7061 /* Set up the DPLL and any encoders state that needs to adjust or depend
7062 * on the DPLL.
7063 */
25c5b266
DV		 7064 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7065 ret = !intel_crtc_mode_set(&intel_crtc->base,
7066 mode, adjusted_mode,
7067 x, y, fb);
7068 if (!ret)
7069 goto done;
a6778b3c 7070
25c5b266 7071 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
a6778b3c 7072
25c5b266
DV		 7073 if (encoder->crtc != &intel_crtc->base)
7074 continue;
a6778b3c 7075
25c5b266
DV		 7076 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7077 encoder->base.id, drm_get_encoder_name(encoder),
7078 mode->base.id, mode->name);
7079 encoder_funcs = encoder->helper_private;
7080 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7081 }
a6778b3c
DV		 7082 }
7083
7084 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7085 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7086 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7087
25c5b266
DV		 7088 if (modeset_pipes) {
7089 /* Store real post-adjustment hardware mode. */
7090 crtc->hwmode = *adjusted_mode;
a6778b3c 7091
25c5b266
DV		 7092 /* Calculate and store various constants which
7093 * are later needed by vblank and swap-completion
7094 * timestamping. They are derived from true hwmode.
7095 */
7096 drm_calc_timestamping_constants(crtc);
7097 }
a6778b3c
DV		 7098
7099 /* FIXME: add subpixel order */
7100done:
7101 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7102 if (!ret && crtc->enabled) {
a6778b3c
DV		 7103 crtc->hwmode = saved_hwmode;
7104 crtc->mode = saved_mode;
8af6cf88
DV		 7105 } else {
7106 intel_modeset_check_state(dev);
a6778b3c
DV		 7107 }
7108
7109 return ret;
7110}
7111
25c5b266
DV		 7112#undef for_each_intel_crtc_masked
7113
d9e55608
DV		 7114static void intel_set_config_free(struct intel_set_config *config)
7115{
7116 if (!config)
7117 return;
7118
1aa4b628
DV		 7119 kfree(config->save_connector_encoders);
7120 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7121 kfree(config);
7122}
7123
85f9eb71
DV		 7124static int intel_set_config_save_state(struct drm_device *dev,
7125 struct intel_set_config *config)
7126{
85f9eb71
DV		 7127 struct drm_encoder *encoder;
7128 struct drm_connector *connector;
7129 int count;
7130
1aa4b628
DV		 7131 config->save_encoder_crtcs =
7132 kcalloc(dev->mode_config.num_encoder,
7133 sizeof(struct drm_crtc *), GFP_KERNEL);
7134 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7135 return -ENOMEM;
7136
1aa4b628
DV		 7137 config->save_connector_encoders =
7138 kcalloc(dev->mode_config.num_connector,
7139 sizeof(struct drm_encoder *), GFP_KERNEL);
7140 if (!config->save_connector_encoders)
85f9eb71
DV		 7141 return -ENOMEM;
7142
7143 /* Copy data. Note that driver private data is not affected.
7144 * Should anything bad happen only the expected state is
7145 * restored, not the drivers personal bookkeeping.
7146 */
85f9eb71
DV		 7147 count = 0;
7148 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7149 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7150 }
7151
7152 count = 0;
7153 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7154 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7155 }
7156
7157 return 0;
7158}
7159
7160static void intel_set_config_restore_state(struct drm_device *dev,
7161 struct intel_set_config *config)
7162{
9a935856
DV		 7163 struct intel_encoder *encoder;
7164 struct intel_connector *connector;
85f9eb71
DV		 7165 int count;
7166
85f9eb71 7167 count = 0;
9a935856
DV		 7168 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7169 encoder->new_crtc =
7170 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7171 }
7172
7173 count = 0;
9a935856
DV		 7174 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7175 connector->new_encoder =
7176 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7177 }
7178}
7179
5e2b584e
DV		 7180static void
7181intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7182 struct intel_set_config *config)
7183{
7184
7185 /* We should be able to check here if the fb has the same properties
7186 * and then just flip_or_move it */
7187 if (set->crtc->fb != set->fb) {
7188 /* If we have no fb then treat it as a full mode set */
7189 if (set->crtc->fb == NULL) {
7190 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7191 config->mode_changed = true;
7192 } else if (set->fb == NULL) {
7193 config->mode_changed = true;
7194 } else if (set->fb->depth != set->crtc->fb->depth) {
7195 config->mode_changed = true;
7196 } else if (set->fb->bits_per_pixel !=
7197 set->crtc->fb->bits_per_pixel) {
7198 config->mode_changed = true;
7199 } else
7200 config->fb_changed = true;
7201 }
7202
835c5873 7203 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7204 config->fb_changed = true;
7205
7206 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7207 DRM_DEBUG_KMS("modes are different, full mode set\n");
7208 drm_mode_debug_printmodeline(&set->crtc->mode);
7209 drm_mode_debug_printmodeline(set->mode);
7210 config->mode_changed = true;
7211 }
7212}
7213
2e431051 7214static int
9a935856
DV		 7215intel_modeset_stage_output_state(struct drm_device *dev,
7216 struct drm_mode_set *set,
7217 struct intel_set_config *config)
50f56119 7218{
85f9eb71 7219 struct drm_crtc *new_crtc;
9a935856
DV		 7220 struct intel_connector *connector;
7221 struct intel_encoder *encoder;
2e431051 7222 int count, ro;
50f56119 7223
9a935856
DV		 7224 /* The upper layers ensure that we either disabl a crtc or have a list
7225 * of connectors. For paranoia, double-check this. */
7226 WARN_ON(!set->fb && (set->num_connectors != 0));
7227 WARN_ON(set->fb && (set->num_connectors == 0));
7228
50f56119 7229 count = 0;
9a935856
DV		 7230 list_for_each_entry(connector, &dev->mode_config.connector_list,
7231 base.head) {
7232 /* Otherwise traverse passed in connector list and get encoders
7233 * for them. */
50f56119 7234 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7235 if (set->connectors[ro] == &connector->base) {
7236 connector->new_encoder = connector->encoder;
50f56119
DV		 7237 break;
7238 }
7239 }
7240
9a935856
DV		 7241 /* If we disable the crtc, disable all its connectors. Also, if
7242 * the connector is on the changing crtc but not on the new
7243 * connector list, disable it. */
7244 if ((!set->fb || ro == set->num_connectors) &&
7245 connector->base.encoder &&
7246 connector->base.encoder->crtc == set->crtc) {
7247 connector->new_encoder = NULL;
7248
7249 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7250 connector->base.base.id,
7251 drm_get_connector_name(&connector->base));
7252 }
7253
7254
7255 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7256 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7257 config->mode_changed = true;
50f56119 7258 }
9a935856
DV		 7259
7260 /* Disable all disconnected encoders. */
7261 if (connector->base.status == connector_status_disconnected)
7262 connector->new_encoder = NULL;
50f56119 7263 }
9a935856 7264 /* connector->new_encoder is now updated for all connectors. */
50f56119 7265
9a935856 7266 /* Update crtc of enabled connectors. */
50f56119 7267 count = 0;
9a935856
DV		 7268 list_for_each_entry(connector, &dev->mode_config.connector_list,
7269 base.head) {
7270 if (!connector->new_encoder)
50f56119
DV		 7271 continue;
7272
9a935856 7273 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7274
7275 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7276 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7277 new_crtc = set->crtc;
7278 }
7279
7280 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7281 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7282 new_crtc)) {
5e2b584e 7283 return -EINVAL;
50f56119 7284 }
9a935856
DV		 7285 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7286
7287 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7288 connector->base.base.id,
7289 drm_get_connector_name(&connector->base),
7290 new_crtc->base.id);
7291 }
7292
7293 /* Check for any encoders that needs to be disabled. */
7294 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7295 base.head) {
7296 list_for_each_entry(connector,
7297 &dev->mode_config.connector_list,
7298 base.head) {
7299 if (connector->new_encoder == encoder) {
7300 WARN_ON(!connector->new_encoder->new_crtc);
7301
7302 goto next_encoder;
7303 }
7304 }
7305 encoder->new_crtc = NULL;
7306next_encoder:
7307 /* Only now check for crtc changes so we don't miss encoders
7308 * that will be disabled. */
7309 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7310 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7311 config->mode_changed = true;
50f56119
DV		 7312 }
7313 }
9a935856 7314 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7315
2e431051
DV		 7316 return 0;
7317}
7318
7319static int intel_crtc_set_config(struct drm_mode_set *set)
7320{
7321 struct drm_device *dev;
2e431051
DV		 7322 struct drm_mode_set save_set;
7323 struct intel_set_config *config;
7324 int ret;
2e431051 7325
8d3e375e
DV		 7326 BUG_ON(!set);
7327 BUG_ON(!set->crtc);
7328 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 7329
7330 if (!set->mode)
7331 set->fb = NULL;
7332
431e50f7
DV		 7333 /* The fb helper likes to play gross jokes with ->mode_set_config.
7334 * Unfortunately the crtc helper doesn't do much at all for this case,
7335 * so we have to cope with this madness until the fb helper is fixed up. */
7336 if (set->fb && set->num_connectors == 0)
7337 return 0;
7338
2e431051
DV		 7339 if (set->fb) {
7340 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7341 set->crtc->base.id, set->fb->base.id,
7342 (int)set->num_connectors, set->x, set->y);
7343 } else {
7344 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 7345 }
7346
7347 dev = set->crtc->dev;
7348
7349 ret = -ENOMEM;
7350 config = kzalloc(sizeof(*config), GFP_KERNEL);
7351 if (!config)
7352 goto out_config;
7353
7354 ret = intel_set_config_save_state(dev, config);
7355 if (ret)
7356 goto out_config;
7357
7358 save_set.crtc = set->crtc;
7359 save_set.mode = &set->crtc->mode;
7360 save_set.x = set->crtc->x;
7361 save_set.y = set->crtc->y;
7362 save_set.fb = set->crtc->fb;
7363
7364 /* Compute whether we need a full modeset, only an fb base update or no
7365 * change at all. In the future we might also check whether only the
7366 * mode changed, e.g. for LVDS where we only change the panel fitter in
7367 * such cases. */
7368 intel_set_config_compute_mode_changes(set, config);
7369
9a935856 7370 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 7371 if (ret)
7372 goto fail;
7373
5e2b584e 7374 if (config->mode_changed) {
87f1faa6 7375 if (set->mode) {
50f56119
DV		 7376 DRM_DEBUG_KMS("attempting to set mode from"
7377 " userspace\n");
7378 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 7379 }
7380
7381 if (!intel_set_mode(set->crtc, set->mode,
7382 set->x, set->y, set->fb)) {
7383 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7384 set->crtc->base.id);
7385 ret = -EINVAL;
7386 goto fail;
7387 }
5e2b584e 7388 } else if (config->fb_changed) {
4f660f49 7389 ret = intel_pipe_set_base(set->crtc,
94352cf9 7390 set->x, set->y, set->fb);
50f56119
DV		 7391 }
7392
d9e55608
DV		 7393 intel_set_config_free(config);
7394
50f56119
DV		 7395 return 0;
7396
7397fail:
85f9eb71 7398 intel_set_config_restore_state(dev, config);
50f56119
DV		 7399
7400 /* Try to restore the config */
5e2b584e 7401 if (config->mode_changed &&
a6778b3c
DV		 7402 !intel_set_mode(save_set.crtc, save_set.mode,
7403 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 7404 DRM_ERROR("failed to restore config after modeset failure\n");
7405
d9e55608
DV		 7406out_config:
7407 intel_set_config_free(config);
50f56119
DV		 7408 return ret;
7409}
7410
f6e5b160 7411static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 7412 .cursor_set = intel_crtc_cursor_set,
7413 .cursor_move = intel_crtc_cursor_move,
7414 .gamma_set = intel_crtc_gamma_set,
50f56119 7415 .set_config = intel_crtc_set_config,
f6e5b160
CW		 7416 .destroy = intel_crtc_destroy,
7417 .page_flip = intel_crtc_page_flip,
7418};
7419
ee7b9f93
JB		 7420static void intel_pch_pll_init(struct drm_device *dev)
7421{
7422 drm_i915_private_t *dev_priv = dev->dev_private;
7423 int i;
7424
7425 if (dev_priv->num_pch_pll == 0) {
7426 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7427 return;
7428 }
7429
7430 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7431 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7432 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7433 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7434 }
7435}
7436
b358d0a6 7437static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7438{
22fd0fab 7439 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7440 struct intel_crtc *intel_crtc;
7441 int i;
7442
7443 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7444 if (intel_crtc == NULL)
7445 return;
7446
7447 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7448
7449 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7450 for (i = 0; i < 256; i++) {
7451 intel_crtc->lut_r[i] = i;
7452 intel_crtc->lut_g[i] = i;
7453 intel_crtc->lut_b[i] = i;
7454 }
7455
80824003
JB		 7456 /* Swap pipes & planes for FBC on pre-965 */
7457 intel_crtc->pipe = pipe;
7458 intel_crtc->plane = pipe;
e2e767ab 7459 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7460 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7461 intel_crtc->plane = !pipe;
80824003
JB		 7462 }
7463
22fd0fab
JB		 7464 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7465 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7466 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7467 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7468
5a354204 7469 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 7470
79e53945 7471 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 7472}
7473
08d7b3d1 7474int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7475 struct drm_file *file)
08d7b3d1 7476{
08d7b3d1 7477 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7478 struct drm_mode_object *drmmode_obj;
7479 struct intel_crtc *crtc;
08d7b3d1 7480
1cff8f6b
DV		 7481 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7482 return -ENODEV;
08d7b3d1 7483
c05422d5
DV		 7484 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7485 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7486
c05422d5 7487 if (!drmmode_obj) {
08d7b3d1
CW		 7488 DRM_ERROR("no such CRTC id\n");
7489 return -EINVAL;
7490 }
7491
c05422d5
DV		 7492 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7493 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7494
c05422d5 7495 return 0;
08d7b3d1
CW		 7496}
7497
66a9278e 7498static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 7499{
66a9278e
DV		 7500 struct drm_device *dev = encoder->base.dev;
7501 struct intel_encoder *source_encoder;
79e53945 7502 int index_mask = 0;
79e53945
JB		 7503 int entry = 0;
7504
66a9278e
DV		 7505 list_for_each_entry(source_encoder,
7506 &dev->mode_config.encoder_list, base.head) {
7507
7508 if (encoder == source_encoder)
79e53945 7509 index_mask |= (1 << entry);
66a9278e
DV		 7510
7511 /* Intel hw has only one MUX where enocoders could be cloned. */
7512 if (encoder->cloneable && source_encoder->cloneable)
7513 index_mask |= (1 << entry);
7514
79e53945
JB		 7515 entry++;
7516 }
4ef69c7a 7517
79e53945
JB		 7518 return index_mask;
7519}
7520
4d302442
CW		 7521static bool has_edp_a(struct drm_device *dev)
7522{
7523 struct drm_i915_private *dev_priv = dev->dev_private;
7524
7525 if (!IS_MOBILE(dev))
7526 return false;
7527
7528 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7529 return false;
7530
7531 if (IS_GEN5(dev) &&
7532 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7533 return false;
7534
7535 return true;
7536}
7537
79e53945
JB		 7538static void intel_setup_outputs(struct drm_device *dev)
7539{
725e30ad 7540 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7541 struct intel_encoder *encoder;
cb0953d7 7542 bool dpd_is_edp = false;
f3cfcba6 7543 bool has_lvds;
79e53945 7544
f3cfcba6 7545 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 7546 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7547 /* disable the panel fitter on everything but LVDS */
7548 I915_WRITE(PFIT_CONTROL, 0);
7549 }
79e53945 7550
bad720ff 7551 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7552 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7553
4d302442 7554 if (has_edp_a(dev))
ab9d7c30 7555 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 7556
cb0953d7 7557 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 7558 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 7559 }
7560
7561 intel_crt_init(dev);
7562
0e72a5b5
ED		 7563 if (IS_HASWELL(dev)) {
7564 int found;
7565
7566 /* Haswell uses DDI functions to detect digital outputs */
7567 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7568 /* DDI A only supports eDP */
7569 if (found)
7570 intel_ddi_init(dev, PORT_A);
7571
7572 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7573 * register */
7574 found = I915_READ(SFUSE_STRAP);
7575
7576 if (found & SFUSE_STRAP_DDIB_DETECTED)
7577 intel_ddi_init(dev, PORT_B);
7578 if (found & SFUSE_STRAP_DDIC_DETECTED)
7579 intel_ddi_init(dev, PORT_C);
7580 if (found & SFUSE_STRAP_DDID_DETECTED)
7581 intel_ddi_init(dev, PORT_D);
7582 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 7583 int found;
7584
30ad48b7 7585 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 7586 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 7587 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 7588 if (!found)
08d644ad 7589 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 7590 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 7591 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 7592 }
7593
7594 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 7595 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 7596
b708a1d5 7597 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 7598 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 7599
5eb08b69 7600 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 7601 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 7602
cb0953d7 7603 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 7604 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 7605 } else if (IS_VALLEYVIEW(dev)) {
7606 int found;
7607
7608 if (I915_READ(SDVOB) & PORT_DETECTED) {
7609 /* SDVOB multiplex with HDMIB */
7610 found = intel_sdvo_init(dev, SDVOB, true);
7611 if (!found)
08d644ad 7612 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 7613 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 7614 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 7615 }
7616
7617 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 7618 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 7619
4a87d65d
JB		 7620 /* Shares lanes with HDMI on SDVOC */
7621 if (I915_READ(DP_C) & DP_DETECTED)
ab9d7c30 7622 intel_dp_init(dev, DP_C, PORT_C);
103a196f 7623 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7624 bool found = false;
7d57382e 7625
725e30ad 7626 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7627 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 7628 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 7629 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7630 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 7631 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 7632 }
27185ae1 7633
b01f2c3a
JB		 7634 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7635 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 7636 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 7637 }
725e30ad 7638 }
13520b05
KH		 7639
7640 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7641
b01f2c3a
JB		 7642 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7643 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 7644 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 7645 }
27185ae1
ML		 7646
7647 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7648
b01f2c3a
JB		 7649 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7650 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 7651 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 7652 }
7653 if (SUPPORTS_INTEGRATED_DP(dev)) {
7654 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 7655 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 7656 }
725e30ad 7657 }
27185ae1 7658
b01f2c3a
JB		 7659 if (SUPPORTS_INTEGRATED_DP(dev) &&
7660 (I915_READ(DP_D) & DP_DETECTED)) {
7661 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 7662 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 7663 }
bad720ff 7664 } else if (IS_GEN2(dev))
79e53945
JB		 7665 intel_dvo_init(dev);
7666
103a196f 7667 if (SUPPORTS_TV(dev))
79e53945
JB		 7668 intel_tv_init(dev);
7669
4ef69c7a
CW		 7670 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7671 encoder->base.possible_crtcs = encoder->crtc_mask;
7672 encoder->base.possible_clones =
66a9278e 7673 intel_encoder_clones(encoder);
79e53945 7674 }
47356eb6 7675
40579abe 7676 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 7677 ironlake_init_pch_refclk(dev);
79e53945
JB		 7678}
7679
7680static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7681{
7682 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7683
7684 drm_framebuffer_cleanup(fb);
05394f39 7685 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7686
7687 kfree(intel_fb);
7688}
7689
7690static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7691 struct drm_file *file,
79e53945
JB		 7692 unsigned int *handle)
7693{
7694 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7695 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7696
05394f39 7697 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7698}
7699
7700static const struct drm_framebuffer_funcs intel_fb_funcs = {
7701 .destroy = intel_user_framebuffer_destroy,
7702 .create_handle = intel_user_framebuffer_create_handle,
7703};
7704
38651674
DA		 7705int intel_framebuffer_init(struct drm_device *dev,
7706 struct intel_framebuffer *intel_fb,
308e5bcb 7707 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 7708 struct drm_i915_gem_object *obj)
79e53945 7709{
79e53945
JB		 7710 int ret;
7711
05394f39 7712 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7713 return -EINVAL;
7714
308e5bcb 7715 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 7716 return -EINVAL;
7717
308e5bcb 7718 switch (mode_cmd->pixel_format) {
04b3924d
VS		 7719 case DRM_FORMAT_RGB332:
7720 case DRM_FORMAT_RGB565:
7721 case DRM_FORMAT_XRGB8888:
b250da79 7722 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 7723 case DRM_FORMAT_ARGB8888:
7724 case DRM_FORMAT_XRGB2101010:
7725 case DRM_FORMAT_ARGB2101010:
308e5bcb 7726 /* RGB formats are common across chipsets */
b5626747 7727 break;
04b3924d
VS		 7728 case DRM_FORMAT_YUYV:
7729 case DRM_FORMAT_UYVY:
7730 case DRM_FORMAT_YVYU:
7731 case DRM_FORMAT_VYUY:
57cd6508
CW		 7732 break;
7733 default:
aca25848
ED		 7734 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7735 mode_cmd->pixel_format);
57cd6508
CW		 7736 return -EINVAL;
7737 }
7738
79e53945
JB		 7739 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7740 if (ret) {
7741 DRM_ERROR("framebuffer init failed %d\n", ret);
7742 return ret;
7743 }
7744
7745 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7746 intel_fb->obj = obj;
79e53945
JB		 7747 return 0;
7748}
7749
79e53945
JB		 7750static struct drm_framebuffer *
7751intel_user_framebuffer_create(struct drm_device *dev,
7752 struct drm_file *filp,
308e5bcb 7753 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 7754{
05394f39 7755 struct drm_i915_gem_object *obj;
79e53945 7756
308e5bcb
JB		 7757 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7758 mode_cmd->handles[0]));
c8725226 7759 if (&obj->base == NULL)
cce13ff7 7760 return ERR_PTR(-ENOENT);
79e53945 7761
d2dff872 7762 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7763}
7764
79e53945 7765static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7766 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7767 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7768};
7769
e70236a8
JB		 7770/* Set up chip specific display functions */
7771static void intel_init_display(struct drm_device *dev)
7772{
7773 struct drm_i915_private *dev_priv = dev->dev_private;
7774
7775 /* We always want a DPMS function */
f564048e 7776 if (HAS_PCH_SPLIT(dev)) {
f564048e 7777 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 7778 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7779 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 7780 dev_priv->display.off = ironlake_crtc_off;
17638cd6 7781 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 7782 } else {
f564048e 7783 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 7784 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7785 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 7786 dev_priv->display.off = i9xx_crtc_off;
17638cd6 7787 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 7788 }
e70236a8 7789
e70236a8 7790 /* Returns the core display clock speed */
25eb05fc
JB		 7791 if (IS_VALLEYVIEW(dev))
7792 dev_priv->display.get_display_clock_speed =
7793 valleyview_get_display_clock_speed;
7794 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 7795 dev_priv->display.get_display_clock_speed =
7796 i945_get_display_clock_speed;
7797 else if (IS_I915G(dev))
7798 dev_priv->display.get_display_clock_speed =
7799 i915_get_display_clock_speed;
f2b115e6 7800 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7801 dev_priv->display.get_display_clock_speed =
7802 i9xx_misc_get_display_clock_speed;
7803 else if (IS_I915GM(dev))
7804 dev_priv->display.get_display_clock_speed =
7805 i915gm_get_display_clock_speed;
7806 else if (IS_I865G(dev))
7807 dev_priv->display.get_display_clock_speed =
7808 i865_get_display_clock_speed;
f0f8a9ce 7809 else if (IS_I85X(dev))
e70236a8
JB		 7810 dev_priv->display.get_display_clock_speed =
7811 i855_get_display_clock_speed;
7812 else /* 852, 830 */
7813 dev_priv->display.get_display_clock_speed =
7814 i830_get_display_clock_speed;
7815
7f8a8569 7816 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 7817 if (IS_GEN5(dev)) {
674cf967 7818 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 7819 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 7820 } else if (IS_GEN6(dev)) {
674cf967 7821 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 7822 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 7823 } else if (IS_IVYBRIDGE(dev)) {
7824 /* FIXME: detect B0+ stepping and use auto training */
7825 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 7826 dev_priv->display.write_eld = ironlake_write_eld;
c82e4d26
ED		 7827 } else if (IS_HASWELL(dev)) {
7828 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 7829 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 7830 } else
7831 dev_priv->display.update_wm = NULL;
6067aaea 7832 } else if (IS_G4X(dev)) {
e0dac65e 7833 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 7834 }
8c9f3aaf
JB		 7835
7836 /* Default just returns -ENODEV to indicate unsupported */
7837 dev_priv->display.queue_flip = intel_default_queue_flip;
7838
7839 switch (INTEL_INFO(dev)->gen) {
7840 case 2:
7841 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7842 break;
7843
7844 case 3:
7845 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7846 break;
7847
7848 case 4:
7849 case 5:
7850 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7851 break;
7852
7853 case 6:
7854 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7855 break;
7c9017e5
JB		 7856 case 7:
7857 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7858 break;
8c9f3aaf 7859 }
e70236a8
JB		 7860}
7861
b690e96c
JB		 7862/*
7863 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7864 * resume, or other times. This quirk makes sure that's the case for
7865 * affected systems.
7866 */
0206e353 7867static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 7868{
7869 struct drm_i915_private *dev_priv = dev->dev_private;
7870
7871 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 7872 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 7873}
7874
435793df
KP		 7875/*
7876 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7877 */
7878static void quirk_ssc_force_disable(struct drm_device *dev)
7879{
7880 struct drm_i915_private *dev_priv = dev->dev_private;
7881 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 7882 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 7883}
7884
4dca20ef 7885/*
5a15ab5b
CE		 7886 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7887 * brightness value
4dca20ef
CE		 7888 */
7889static void quirk_invert_brightness(struct drm_device *dev)
7890{
7891 struct drm_i915_private *dev_priv = dev->dev_private;
7892 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 7893 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 7894}
7895
b690e96c
JB		 7896struct intel_quirk {
7897 int device;
7898 int subsystem_vendor;
7899 int subsystem_device;
7900 void (*hook)(struct drm_device *dev);
7901};
7902
c43b5634 7903static struct intel_quirk intel_quirks[] = {
b690e96c 7904 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 7905 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 7906
b690e96c
JB		 7907 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7908 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7909
b690e96c
JB		 7910 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7911 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7912
7913 /* 855 & before need to leave pipe A & dpll A up */
7914 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7915 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 7916 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 7917
7918 /* Lenovo U160 cannot use SSC on LVDS */
7919 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 7920
7921 /* Sony Vaio Y cannot use SSC on LVDS */
7922 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 7923
7924 /* Acer Aspire 5734Z must invert backlight brightness */
7925 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 7926};
7927
7928static void intel_init_quirks(struct drm_device *dev)
7929{
7930 struct pci_dev *d = dev->pdev;
7931 int i;
7932
7933 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7934 struct intel_quirk *q = &intel_quirks[i];
7935
7936 if (d->device == q->device &&
7937 (d->subsystem_vendor == q->subsystem_vendor ||
7938 q->subsystem_vendor == PCI_ANY_ID) &&
7939 (d->subsystem_device == q->subsystem_device ||
7940 q->subsystem_device == PCI_ANY_ID))
7941 q->hook(dev);
7942 }
7943}
7944
9cce37f4
JB		 7945/* Disable the VGA plane that we never use */
7946static void i915_disable_vga(struct drm_device *dev)
7947{
7948 struct drm_i915_private *dev_priv = dev->dev_private;
7949 u8 sr1;
7950 u32 vga_reg;
7951
7952 if (HAS_PCH_SPLIT(dev))
7953 vga_reg = CPU_VGACNTRL;
7954 else
7955 vga_reg = VGACNTRL;
7956
7957 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 7958 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 7959 sr1 = inb(VGA_SR_DATA);
7960 outb(sr1 | 1<<5, VGA_SR_DATA);
7961 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7962 udelay(300);
7963
7964 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7965 POSTING_READ(vga_reg);
7966}
7967
f817586c
DV		 7968void intel_modeset_init_hw(struct drm_device *dev)
7969{
0232e927
ED		 7970 /* We attempt to init the necessary power wells early in the initialization
7971 * time, so the subsystems that expect power to be enabled can work.
7972 */
7973 intel_init_power_wells(dev);
7974
a8f78b58
ED		 7975 intel_prepare_ddi(dev);
7976
f817586c
DV		 7977 intel_init_clock_gating(dev);
7978
79f5b2c7 7979 mutex_lock(&dev->struct_mutex);
8090c6b9 7980 intel_enable_gt_powersave(dev);
79f5b2c7 7981 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 7982}
7983
79e53945
JB		 7984void intel_modeset_init(struct drm_device *dev)
7985{
652c393a 7986 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 7987 int i, ret;
79e53945
JB		 7988
7989 drm_mode_config_init(dev);
7990
7991 dev->mode_config.min_width = 0;
7992 dev->mode_config.min_height = 0;
7993
019d96cb
DA		 7994 dev->mode_config.preferred_depth = 24;
7995 dev->mode_config.prefer_shadow = 1;
7996
e6ecefaa 7997 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 7998
b690e96c
JB		 7999 intel_init_quirks(dev);
8000
1fa61106
ED		 8001 intel_init_pm(dev);
8002
e70236a8
JB		 8003 intel_init_display(dev);
8004
a6c45cf0
CW		 8005 if (IS_GEN2(dev)) {
8006 dev->mode_config.max_width = 2048;
8007 dev->mode_config.max_height = 2048;
8008 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8009 dev->mode_config.max_width = 4096;
8010 dev->mode_config.max_height = 4096;
79e53945 8011 } else {
a6c45cf0
CW		 8012 dev->mode_config.max_width = 8192;
8013 dev->mode_config.max_height = 8192;
79e53945 8014 }
dd2757f8 8015 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8016
28c97730 8017 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8018 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8019
a3524f1b 8020 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8021 intel_crtc_init(dev, i);
00c2064b
JB		 8022 ret = intel_plane_init(dev, i);
8023 if (ret)
8024 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8025 }
8026
ee7b9f93
JB		 8027 intel_pch_pll_init(dev);
8028
9cce37f4
JB		 8029 /* Just disable it once at startup */
8030 i915_disable_vga(dev);
79e53945 8031 intel_setup_outputs(dev);
2c7111db
CW		 8032}
8033
24929352
DV		 8034static void
8035intel_connector_break_all_links(struct intel_connector *connector)
8036{
8037 connector->base.dpms = DRM_MODE_DPMS_OFF;
8038 connector->base.encoder = NULL;
8039 connector->encoder->connectors_active = false;
8040 connector->encoder->base.crtc = NULL;
8041}
8042
7fad798e
DV		 8043static void intel_enable_pipe_a(struct drm_device *dev)
8044{
8045 struct intel_connector *connector;
8046 struct drm_connector *crt = NULL;
8047 struct intel_load_detect_pipe load_detect_temp;
8048
8049 /* We can't just switch on the pipe A, we need to set things up with a
8050 * proper mode and output configuration. As a gross hack, enable pipe A
8051 * by enabling the load detect pipe once. */
8052 list_for_each_entry(connector,
8053 &dev->mode_config.connector_list,
8054 base.head) {
8055 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8056 crt = &connector->base;
8057 break;
8058 }
8059 }
8060
8061 if (!crt)
8062 return;
8063
8064 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8065 intel_release_load_detect_pipe(crt, &load_detect_temp);
8066
8067
8068}
8069
24929352
DV		 8070static void intel_sanitize_crtc(struct intel_crtc *crtc)
8071{
8072 struct drm_device *dev = crtc->base.dev;
8073 struct drm_i915_private *dev_priv = dev->dev_private;
8074 u32 reg, val;
8075
24929352
DV		 8076 /* Clear any frame start delays used for debugging left by the BIOS */
8077 reg = PIPECONF(crtc->pipe);
8078 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8079
8080 /* We need to sanitize the plane -> pipe mapping first because this will
8081 * disable the crtc (and hence change the state) if it is wrong. */
8082 if (!HAS_PCH_SPLIT(dev)) {
8083 struct intel_connector *connector;
8084 bool plane;
8085
8086 reg = DSPCNTR(crtc->plane);
8087 val = I915_READ(reg);
8088
8089 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
8090 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8091 goto ok;
8092
8093 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8094 crtc->base.base.id);
8095
8096 /* Pipe has the wrong plane attached and the plane is active.
8097 * Temporarily change the plane mapping and disable everything
8098 * ... */
8099 plane = crtc->plane;
8100 crtc->plane = !plane;
8101 dev_priv->display.crtc_disable(&crtc->base);
8102 crtc->plane = plane;
8103
8104 /* ... and break all links. */
8105 list_for_each_entry(connector, &dev->mode_config.connector_list,
8106 base.head) {
8107 if (connector->encoder->base.crtc != &crtc->base)
8108 continue;
8109
8110 intel_connector_break_all_links(connector);
8111 }
8112
8113 WARN_ON(crtc->active);
8114 crtc->base.enabled = false;
8115 }
8116ok:
8117
7fad798e
DV		 8118 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8119 crtc->pipe == PIPE_A && !crtc->active) {
8120 /* BIOS forgot to enable pipe A, this mostly happens after
8121 * resume. Force-enable the pipe to fix this, the update_dpms
8122 * call below we restore the pipe to the right state, but leave
8123 * the required bits on. */
8124 intel_enable_pipe_a(dev);
8125 }
8126
24929352
DV		 8127 /* Adjust the state of the output pipe according to whether we
8128 * have active connectors/encoders. */
8129 intel_crtc_update_dpms(&crtc->base);
8130
8131 if (crtc->active != crtc->base.enabled) {
8132 struct intel_encoder *encoder;
8133
8134 /* This can happen either due to bugs in the get_hw_state
8135 * functions or because the pipe is force-enabled due to the
8136 * pipe A quirk. */
8137 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8138 crtc->base.base.id,
8139 crtc->base.enabled ? "enabled" : "disabled",
8140 crtc->active ? "enabled" : "disabled");
8141
8142 crtc->base.enabled = crtc->active;
8143
8144 /* Because we only establish the connector -> encoder ->
8145 * crtc links if something is active, this means the
8146 * crtc is now deactivated. Break the links. connector
8147 * -> encoder links are only establish when things are
8148 * actually up, hence no need to break them. */
8149 WARN_ON(crtc->active);
8150
8151 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8152 WARN_ON(encoder->connectors_active);
8153 encoder->base.crtc = NULL;
8154 }
8155 }
8156}
8157
8158static void intel_sanitize_encoder(struct intel_encoder *encoder)
8159{
8160 struct intel_connector *connector;
8161 struct drm_device *dev = encoder->base.dev;
8162
8163 /* We need to check both for a crtc link (meaning that the
8164 * encoder is active and trying to read from a pipe) and the
8165 * pipe itself being active. */
8166 bool has_active_crtc = encoder->base.crtc &&
8167 to_intel_crtc(encoder->base.crtc)->active;
8168
8169 if (encoder->connectors_active && !has_active_crtc) {
8170 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8171 encoder->base.base.id,
8172 drm_get_encoder_name(&encoder->base));
8173
8174 /* Connector is active, but has no active pipe. This is
8175 * fallout from our resume register restoring. Disable
8176 * the encoder manually again. */
8177 if (encoder->base.crtc) {
8178 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8179 encoder->base.base.id,
8180 drm_get_encoder_name(&encoder->base));
8181 encoder->disable(encoder);
8182 }
8183
8184 /* Inconsistent output/port/pipe state happens presumably due to
8185 * a bug in one of the get_hw_state functions. Or someplace else
8186 * in our code, like the register restore mess on resume. Clamp
8187 * things to off as a safer default. */
8188 list_for_each_entry(connector,
8189 &dev->mode_config.connector_list,
8190 base.head) {
8191 if (connector->encoder != encoder)
8192 continue;
8193
8194 intel_connector_break_all_links(connector);
8195 }
8196 }
8197 /* Enabled encoders without active connectors will be fixed in
8198 * the crtc fixup. */
8199}
8200
8201/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8202 * and i915 state tracking structures. */
8203void intel_modeset_setup_hw_state(struct drm_device *dev)
8204{
8205 struct drm_i915_private *dev_priv = dev->dev_private;
8206 enum pipe pipe;
8207 u32 tmp;
8208 struct intel_crtc *crtc;
8209 struct intel_encoder *encoder;
8210 struct intel_connector *connector;
8211
8212 for_each_pipe(pipe) {
8213 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8214
8215 tmp = I915_READ(PIPECONF(pipe));
8216 if (tmp & PIPECONF_ENABLE)
8217 crtc->active = true;
8218 else
8219 crtc->active = false;
8220
8221 crtc->base.enabled = crtc->active;
8222
8223 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8224 crtc->base.base.id,
8225 crtc->active ? "enabled" : "disabled");
8226 }
8227
8228 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8229 base.head) {
8230 pipe = 0;
8231
8232 if (encoder->get_hw_state(encoder, &pipe)) {
8233 encoder->base.crtc =
8234 dev_priv->pipe_to_crtc_mapping[pipe];
8235 } else {
8236 encoder->base.crtc = NULL;
8237 }
8238
8239 encoder->connectors_active = false;
8240 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8241 encoder->base.base.id,
8242 drm_get_encoder_name(&encoder->base),
8243 encoder->base.crtc ? "enabled" : "disabled",
8244 pipe);
8245 }
8246
8247 list_for_each_entry(connector, &dev->mode_config.connector_list,
8248 base.head) {
8249 if (connector->get_hw_state(connector)) {
8250 connector->base.dpms = DRM_MODE_DPMS_ON;
8251 connector->encoder->connectors_active = true;
8252 connector->base.encoder = &connector->encoder->base;
8253 } else {
8254 connector->base.dpms = DRM_MODE_DPMS_OFF;
8255 connector->base.encoder = NULL;
8256 }
8257 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8258 connector->base.base.id,
8259 drm_get_connector_name(&connector->base),
8260 connector->base.encoder ? "enabled" : "disabled");
8261 }
8262
8263 /* HW state is read out, now we need to sanitize this mess. */
8264 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8265 base.head) {
8266 intel_sanitize_encoder(encoder);
8267 }
8268
8269 for_each_pipe(pipe) {
8270 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8271 intel_sanitize_crtc(crtc);
8272 }
9a935856
DV		 8273
8274 intel_modeset_update_staged_output_state(dev);
8af6cf88
DV		 8275
8276 intel_modeset_check_state(dev);
24929352
DV		 8277}
8278
2c7111db
CW		 8279void intel_modeset_gem_init(struct drm_device *dev)
8280{
1833b134 8281 intel_modeset_init_hw(dev);
02e792fb
DV		 8282
8283 intel_setup_overlay(dev);
24929352
DV		 8284
8285 intel_modeset_setup_hw_state(dev);
79e53945
JB		 8286}
8287
8288void intel_modeset_cleanup(struct drm_device *dev)
8289{
652c393a
JB		 8290 struct drm_i915_private *dev_priv = dev->dev_private;
8291 struct drm_crtc *crtc;
8292 struct intel_crtc *intel_crtc;
8293
f87ea761 8294 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8295 mutex_lock(&dev->struct_mutex);
8296
723bfd70
JB		 8297 intel_unregister_dsm_handler();
8298
8299
652c393a
JB		 8300 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8301 /* Skip inactive CRTCs */
8302 if (!crtc->fb)
8303 continue;
8304
8305 intel_crtc = to_intel_crtc(crtc);
3dec0095 8306 intel_increase_pllclock(crtc);
652c393a
JB		 8307 }
8308
973d04f9 8309 intel_disable_fbc(dev);
e70236a8 8310
8090c6b9 8311 intel_disable_gt_powersave(dev);
0cdab21f 8312
930ebb46
DV		 8313 ironlake_teardown_rc6(dev);
8314
57f350b6
JB		 8315 if (IS_VALLEYVIEW(dev))
8316 vlv_init_dpio(dev);
8317
69341a5e
KH		 8318 mutex_unlock(&dev->struct_mutex);
8319
6c0d9350
DV		 8320 /* Disable the irq before mode object teardown, for the irq might
8321 * enqueue unpin/hotplug work. */
8322 drm_irq_uninstall(dev);
8323 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 8324 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 8325
1630fe75
CW		 8326 /* flush any delayed tasks or pending work */
8327 flush_scheduled_work();
8328
79e53945
JB		 8329 drm_mode_config_cleanup(dev);
8330}
8331
f1c79df3
ZW		 8332/*
8333 * Return which encoder is currently attached for connector.
8334 */
df0e9248 8335struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8336{
df0e9248
CW		 8337 return &intel_attached_encoder(connector)->base;
8338}
f1c79df3 8339
df0e9248
CW		 8340void intel_connector_attach_encoder(struct intel_connector *connector,
8341 struct intel_encoder *encoder)
8342{
8343 connector->encoder = encoder;
8344 drm_mode_connector_attach_encoder(&connector->base,
8345 &encoder->base);
79e53945 8346}
28d52043
DA		 8347
8348/*
8349 * set vga decode state - true == enable VGA decode
8350 */
8351int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8352{
8353 struct drm_i915_private *dev_priv = dev->dev_private;
8354 u16 gmch_ctrl;
8355
8356 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8357 if (state)
8358 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8359 else
8360 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8361 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8362 return 0;
8363}
c4a1d9e4
CW		 8364
8365#ifdef CONFIG_DEBUG_FS
8366#include <linux/seq_file.h>
8367
8368struct intel_display_error_state {
8369 struct intel_cursor_error_state {
8370 u32 control;
8371 u32 position;
8372 u32 base;
8373 u32 size;
52331309 8374 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 8375
8376 struct intel_pipe_error_state {
8377 u32 conf;
8378 u32 source;
8379
8380 u32 htotal;
8381 u32 hblank;
8382 u32 hsync;
8383 u32 vtotal;
8384 u32 vblank;
8385 u32 vsync;
52331309 8386 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 8387
8388 struct intel_plane_error_state {
8389 u32 control;
8390 u32 stride;
8391 u32 size;
8392 u32 pos;
8393 u32 addr;
8394 u32 surface;
8395 u32 tile_offset;
52331309 8396 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 8397};
8398
8399struct intel_display_error_state *
8400intel_display_capture_error_state(struct drm_device *dev)
8401{
0206e353 8402 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8403 struct intel_display_error_state *error;
8404 int i;
8405
8406 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8407 if (error == NULL)
8408 return NULL;
8409
52331309 8410 for_each_pipe(i) {
c4a1d9e4
CW		 8411 error->cursor[i].control = I915_READ(CURCNTR(i));
8412 error->cursor[i].position = I915_READ(CURPOS(i));
8413 error->cursor[i].base = I915_READ(CURBASE(i));
8414
8415 error->plane[i].control = I915_READ(DSPCNTR(i));
8416 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8417 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 8418 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 8419 error->plane[i].addr = I915_READ(DSPADDR(i));
8420 if (INTEL_INFO(dev)->gen >= 4) {
8421 error->plane[i].surface = I915_READ(DSPSURF(i));
8422 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8423 }
8424
8425 error->pipe[i].conf = I915_READ(PIPECONF(i));
8426 error->pipe[i].source = I915_READ(PIPESRC(i));
8427 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8428 error->pipe[i].hblank = I915_READ(HBLANK(i));
8429 error->pipe[i].hsync = I915_READ(HSYNC(i));
8430 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8431 error->pipe[i].vblank = I915_READ(VBLANK(i));
8432 error->pipe[i].vsync = I915_READ(VSYNC(i));
8433 }
8434
8435 return error;
8436}
8437
8438void
8439intel_display_print_error_state(struct seq_file *m,
8440 struct drm_device *dev,
8441 struct intel_display_error_state *error)
8442{
52331309 8443 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8444 int i;
8445
52331309
DL		 8446 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8447 for_each_pipe(i) {
c4a1d9e4
CW		 8448 seq_printf(m, "Pipe [%d]:\n", i);
8449 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8450 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8451 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8452 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8453 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8454 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8455 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8456 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8457
8458 seq_printf(m, "Plane [%d]:\n", i);
8459 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8460 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8461 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8462 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8463 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8464 if (INTEL_INFO(dev)->gen >= 4) {
8465 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8466 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8467 }
8468
8469 seq_printf(m, "Cursor [%d]:\n", i);
8470 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8471 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8472 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8473 }
8474}
8475#endif
Linux kernel - Deliverables
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