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drm/i915: enable and disable DDI_FUNC_CTL at the right time
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
a0c4da24
JB		 101static bool
102intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
021357ac
CW		 106static inline u32 /* units of 100MHz */
107intel_fdi_link_freq(struct drm_device *dev)
108{
8b99e68c
CW		 109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
021357ac
CW		 114}
115
e4b36699 116static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
d4906093 127 .find_pll = intel_find_best_PLL,
e4b36699
KP		 128};
129
130static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
d4906093 141 .find_pll = intel_find_best_PLL,
e4b36699 142};
273e27ca 143
e4b36699 144static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
d4906093 155 .find_pll = intel_find_best_PLL,
e4b36699
KP		 156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
d4906093 169 .find_pll = intel_find_best_PLL,
e4b36699
KP		 170};
171
273e27ca 172
e4b36699 173static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
044c7c41 185 },
d4906093 186 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 187};
188
189static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
d4906093 200 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 201};
202
203static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
044c7c41 214 },
d4906093 215 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 216};
217
218static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
044c7c41 229 },
d4906093 230 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 231};
232
233static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
273e27ca 243 .p2_slow = 10, .p2_fast = 10 },
0206e353 244 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 245};
246
f2b115e6 247static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 250 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
273e27ca 253 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
6115707b 260 .find_pll = intel_find_best_PLL,
e4b36699
KP		 261};
262
f2b115e6 263static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
6115707b 274 .find_pll = intel_find_best_PLL,
e4b36699
KP		 275};
276
273e27ca
EA		 277/* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
b91ad0ec 282static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
4547668a 293 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 294};
295
b91ad0ec 296static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 307 .find_pll = intel_g4x_find_best_PLL,
308};
309
310static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 321 .find_pll = intel_g4x_find_best_PLL,
322};
323
273e27ca 324/* LVDS 100mhz refclk limits. */
b91ad0ec 325static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
0206e353 333 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 336 .find_pll = intel_g4x_find_best_PLL,
337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
0206e353 347 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 350 .find_pll = intel_g4x_find_best_PLL,
351};
352
353static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
273e27ca 363 .p2_slow = 10, .p2_fast = 10 },
0206e353 364 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 365};
366
a0c4da24
JB		 367static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379};
380
381static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
17dc9257 383 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393};
394
395static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 396 .dot = { .min = 25000, .max = 270000 },
397 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 398 .n = { .min = 1, .max = 7 },
74a4dd2e 399 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407};
408
57f350b6
JB		 409u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410{
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432}
433
a0c4da24
JB		 434static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436{
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454}
455
57f350b6
JB		 456static void vlv_init_dpio(struct drm_device *dev)
457{
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465}
466
618563e3
DV		 467static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468{
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471}
472
473static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483};
484
b0354385
TI		 485static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487{
488 unsigned int val;
489
121d527a
TI		 490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
618563e3
DV		 494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
b0354385
TI		 497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
14d94a3d 506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511}
512
1b894b59
CW		 513static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
2c07245f 515{
b91ad0ec
ZW		 516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 518 const intel_limit_t *limit;
b91ad0ec
ZW		 519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 522 /* LVDS dual channel */
1b894b59 523 if (refclk == 100000)
b91ad0ec
ZW		 524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
1b894b59 528 if (refclk == 100000)
b91ad0ec
ZW		 529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
2c07245f 536 else
b91ad0ec 537 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 538
539 return limit;
540}
541
044c7c41
ML		 542static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543{
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 549 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 550 /* LVDS with dual channel */
e4b36699 551 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 552 else
553 /* LVDS with dual channel */
e4b36699 554 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 557 limit = &intel_limits_g4x_hdmi;
044c7c41 558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 559 limit = &intel_limits_g4x_sdvo;
0206e353 560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 561 limit = &intel_limits_g4x_display_port;
044c7c41 562 } else /* The option is for other outputs */
e4b36699 563 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 564
565 return limit;
566}
567
1b894b59 568static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 569{
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
bad720ff 573 if (HAS_PCH_SPLIT(dev))
1b894b59 574 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 575 else if (IS_G4X(dev)) {
044c7c41 576 limit = intel_g4x_limit(crtc);
f2b115e6 577 } else if (IS_PINEVIEW(dev)) {
2177832f 578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 579 limit = &intel_limits_pineview_lvds;
2177832f 580 else
f2b115e6 581 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 596 limit = &intel_limits_i8xx_lvds;
79e53945 597 else
e4b36699 598 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 599 }
600 return limit;
601}
602
f2b115e6
AJ		 603/* m1 is reserved as 0 in Pineview, n is a ring counter */
604static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 605{
2177832f
SL		 606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610}
611
612static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613{
f2b115e6
AJ		 614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
2177832f
SL		 616 return;
617 }
79e53945
JB		 618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622}
623
79e53945
JB		 624/**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
4ef69c7a 627bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 628{
4ef69c7a 629 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 630 struct intel_encoder *encoder;
631
6c2b7c12
DV		 632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
4ef69c7a
CW		 634 return true;
635
636 return false;
79e53945
JB		 637}
638
7c04d1d9 639#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 640/**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
1b894b59
CW		 645static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
79e53945 648{
79e53945 649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 650 INTELPllInvalid("p1 out of range\n");
79e53945 651 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 652 INTELPllInvalid("p out of range\n");
79e53945 653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 654 INTELPllInvalid("m2 out of range\n");
79e53945 655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 656 INTELPllInvalid("m1 out of range\n");
f2b115e6 657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 658 INTELPllInvalid("m1 <= m2\n");
79e53945 659 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 660 INTELPllInvalid("m out of range\n");
79e53945 661 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 662 INTELPllInvalid("n out of range\n");
79e53945 663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 664 INTELPllInvalid("vco out of range\n");
79e53945
JB		 665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 669 INTELPllInvalid("dot out of range\n");
79e53945
JB		 670
671 return true;
672}
673
d4906093
ML		 674static bool
675intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
d4906093 678
79e53945
JB		 679{
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
79e53945
JB		 683 int err = target;
684
bc5e5718 685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 686 (I915_READ(LVDS)) != 0) {
79e53945
JB		 687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
b0354385 693 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
0206e353 704 memset(best_clock, 0, sizeof(*best_clock));
79e53945 705
42158660
ZY		 706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 717 int this_err;
718
2177832f 719 intel_clock(dev, refclk, &clock);
1b894b59
CW		 720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
79e53945 722 continue;
cec2f356
SP		 723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
79e53945
JB		 726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738}
739
d4906093
ML		 740static bool
741intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
d4906093
ML		 744{
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
6ba770dc
AJ		 750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 755 int lvds_reg;
756
c619eed4 757 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
f77f13e2 775 /* based on hardware requirement, prefer smaller n to precision */
d4906093 776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 777 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
2177832f 786 intel_clock(dev, refclk, &clock);
1b894b59
CW		 787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
d4906093 789 continue;
cec2f356
SP		 790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
1b894b59
CW		 793
794 this_err = abs(clock.dot - target);
d4906093
ML		 795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
2c07245f
ZW		 805 return found;
806}
807
5eb08b69 808static bool
f2b115e6 809intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
5eb08b69
ZW		 812{
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
4547668a 815
5eb08b69
ZW		 816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832}
833
a4fc5ed6
KP		 834/* DisplayPort has only two frequencies, 162MHz and 270MHz */
835static bool
836intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
a4fc5ed6 839{
5eddb70b
CW		 840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
a4fc5ed6 860}
a0c4da24
JB		 861static bool
862intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865{
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
af447bd3 872 flag = 0;
a0c4da24
JB		 873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928}
a4fc5ed6 929
a928d536
PZ		 930static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931{
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939}
940
9d0498a2
JB		 941/**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 950{
9d0498a2 951 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 952 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 953
a928d536
PZ		 954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
300387c0
CW		 959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
9d0498a2 975 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
9d0498a2
JB		 979 DRM_DEBUG_KMS("vblank wait timed out\n");
980}
981
ab7ad7f6
KP		 982/*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
ab7ad7f6
KP		 991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
58e10eb9 997 *
9d0498a2 998 */
58e10eb9 999void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1000{
1001 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 1002
1003 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 1004 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 1005
1006 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
284637d9 1009 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1010 } else {
837ba00f 1011 u32 last_line, line_mask;
58e10eb9 1012 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
837ba00f
PZ		 1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
ab7ad7f6
KP		 1020 /* Wait for the display line to settle */
1021 do {
837ba00f 1022 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1023 mdelay(5);
837ba00f 1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
284637d9 1027 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1028 }
79e53945
JB		 1029}
1030
b24e7179
JB		 1031static const char *state_string(bool enabled)
1032{
1033 return enabled ? "on" : "off";
1034}
1035
1036/* Only for pre-ILK configs */
1037static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039{
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050}
1051#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
040484af
JB		 1054/* For ILK+ */
1055static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
040484af 1059{
040484af
JB		 1060 u32 val;
1061 bool cur_state;
1062
9d82aa17
ED		 1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
92b27b08
CW		 1068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1070 return;
ee7b9f93 1071
92b27b08
CW		 1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
d3ccbe86 1095 }
040484af 1096}
92b27b08
CW		 1097#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1099
1100static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102{
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
bf507ef7
ED		 1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
040484af
JB		 1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
1121#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126{
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
59c859d6
ED		 1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
040484af
JB		 1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142}
1143#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
bf507ef7
ED		 1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
040484af
JB		 1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163}
1164
1165static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
1168 int reg;
1169 u32 val;
1170
59c859d6
ED		 1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
040484af
JB		 1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178}
1179
ea0760cf
JB		 1180static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182{
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
0de3b485 1186 bool locked = true;
ea0760cf
JB		 1187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1206 pipe_name(pipe));
ea0760cf
JB		 1207}
1208
b840d907
JB		 1209void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
b24e7179
JB		 1211{
1212 int reg;
1213 u32 val;
63d7bbe9 1214 bool cur_state;
b24e7179 1215
8e636784
DV		 1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
b24e7179
JB		 1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
63d7bbe9
JB		 1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1225 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1226}
1227
931872fc
CW		 1228static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
b24e7179
JB		 1230{
1231 int reg;
1232 u32 val;
931872fc 1233 bool cur_state;
b24e7179
JB		 1234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
931872fc
CW		 1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1241}
1242
931872fc
CW		 1243#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
b24e7179
JB		 1246static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248{
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
19ec1358 1253 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
19ec1358 1260 return;
28c05794 1261 }
19ec1358 1262
b24e7179
JB		 1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1272 }
1273}
1274
92f2584a
JB		 1275static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276{
1277 u32 val;
1278 bool enabled;
1279
9d82aa17
ED		 1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
92f2584a
JB		 1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289}
1290
1291static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
92f2584a
JB		 1304}
1305
4e634389
KP		 1306static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1308{
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322}
1323
1519b995
KP		 1324static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326{
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338}
1339
1340static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369}
1370
291906f1 1371static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1372 enum pipe pipe, int reg, u32 port_sel)
291906f1 1373{
47a05eca 1374 u32 val = I915_READ(reg);
4e634389 1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1377 reg, pipe_name(pipe));
de9a35ab 1378
75c5da27
DV		 1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1380 && (val & DP_PIPEB_SELECT),
de9a35ab 1381 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1382}
1383
1384static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe, int reg)
1386{
47a05eca 1387 u32 val = I915_READ(reg);
e9a851ed 1388 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1389 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1390 reg, pipe_name(pipe));
de9a35ab 1391
75c5da27
DV		 1392 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1393 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1394 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1395}
1396
1397static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399{
1400 int reg;
1401 u32 val;
291906f1 1402
f0575e92
KP		 1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1404 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1405 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1406
1407 reg = PCH_ADPA;
1408 val = I915_READ(reg);
e9a851ed 1409 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1410 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1411 pipe_name(pipe));
291906f1
JB		 1412
1413 reg = PCH_LVDS;
1414 val = I915_READ(reg);
e9a851ed 1415 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1416 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1417 pipe_name(pipe));
291906f1
JB		 1418
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1420 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1421 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1422}
1423
63d7bbe9
JB		 1424/**
1425 * intel_enable_pll - enable a PLL
1426 * @dev_priv: i915 private structure
1427 * @pipe: pipe PLL to enable
1428 *
1429 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1430 * make sure the PLL reg is writable first though, since the panel write
1431 * protect mechanism may be enabled.
1432 *
1433 * Note! This is for pre-ILK only.
7434a255
TR		 1434 *
1435 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1436 */
a37b9b34 1437static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1438{
1439 int reg;
1440 u32 val;
1441
1442 /* No really, not for ILK+ */
a0c4da24 1443 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1444
1445 /* PLL is protected by panel, make sure we can write it */
1446 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1447 assert_panel_unlocked(dev_priv, pipe);
1448
1449 reg = DPLL(pipe);
1450 val = I915_READ(reg);
1451 val |= DPLL_VCO_ENABLE;
1452
1453 /* We do this three times for luck */
1454 I915_WRITE(reg, val);
1455 POSTING_READ(reg);
1456 udelay(150); /* wait for warmup */
1457 I915_WRITE(reg, val);
1458 POSTING_READ(reg);
1459 udelay(150); /* wait for warmup */
1460 I915_WRITE(reg, val);
1461 POSTING_READ(reg);
1462 udelay(150); /* wait for warmup */
1463}
1464
1465/**
1466 * intel_disable_pll - disable a PLL
1467 * @dev_priv: i915 private structure
1468 * @pipe: pipe PLL to disable
1469 *
1470 * Disable the PLL for @pipe, making sure the pipe is off first.
1471 *
1472 * Note! This is for pre-ILK only.
1473 */
1474static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1475{
1476 int reg;
1477 u32 val;
1478
1479 /* Don't disable pipe A or pipe A PLLs if needed */
1480 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1481 return;
1482
1483 /* Make sure the pipe isn't still relying on us */
1484 assert_pipe_disabled(dev_priv, pipe);
1485
1486 reg = DPLL(pipe);
1487 val = I915_READ(reg);
1488 val &= ~DPLL_VCO_ENABLE;
1489 I915_WRITE(reg, val);
1490 POSTING_READ(reg);
1491}
1492
a416edef
ED		 1493/* SBI access */
1494static void
1495intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1496{
1497 unsigned long flags;
1498
1499 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1500 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1501 100)) {
1502 DRM_ERROR("timeout waiting for SBI to become ready\n");
1503 goto out_unlock;
1504 }
1505
1506 I915_WRITE(SBI_ADDR,
1507 (reg << 16));
1508 I915_WRITE(SBI_DATA,
1509 value);
1510 I915_WRITE(SBI_CTL_STAT,
1511 SBI_BUSY |
1512 SBI_CTL_OP_CRWR);
1513
39fb50f6 1514 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1515 100)) {
1516 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1517 goto out_unlock;
1518 }
1519
1520out_unlock:
1521 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1522}
1523
1524static u32
1525intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1526{
1527 unsigned long flags;
39fb50f6 1528 u32 value = 0;
a416edef
ED		 1529
1530 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1531 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1532 100)) {
1533 DRM_ERROR("timeout waiting for SBI to become ready\n");
1534 goto out_unlock;
1535 }
1536
1537 I915_WRITE(SBI_ADDR,
1538 (reg << 16));
1539 I915_WRITE(SBI_CTL_STAT,
1540 SBI_BUSY |
1541 SBI_CTL_OP_CRRD);
1542
39fb50f6 1543 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1544 100)) {
1545 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1546 goto out_unlock;
1547 }
1548
1549 value = I915_READ(SBI_DATA);
1550
1551out_unlock:
1552 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1553 return value;
1554}
1555
92f2584a
JB		 1556/**
1557 * intel_enable_pch_pll - enable PCH PLL
1558 * @dev_priv: i915 private structure
1559 * @pipe: pipe PLL to enable
1560 *
1561 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1562 * drives the transcoder clock.
1563 */
ee7b9f93 1564static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1565{
ee7b9f93 1566 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1567 struct intel_pch_pll *pll;
92f2584a
JB		 1568 int reg;
1569 u32 val;
1570
48da64a8 1571 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1572 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1573 pll = intel_crtc->pch_pll;
1574 if (pll == NULL)
1575 return;
1576
1577 if (WARN_ON(pll->refcount == 0))
1578 return;
ee7b9f93
JB		 1579
1580 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1581 pll->pll_reg, pll->active, pll->on,
1582 intel_crtc->base.base.id);
92f2584a
JB		 1583
1584 /* PCH refclock must be enabled first */
1585 assert_pch_refclk_enabled(dev_priv);
1586
ee7b9f93 1587 if (pll->active++ && pll->on) {
92b27b08 1588 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1589 return;
1590 }
1591
1592 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1593
1594 reg = pll->pll_reg;
92f2584a
JB		 1595 val = I915_READ(reg);
1596 val |= DPLL_VCO_ENABLE;
1597 I915_WRITE(reg, val);
1598 POSTING_READ(reg);
1599 udelay(200);
ee7b9f93
JB		 1600
1601 pll->on = true;
92f2584a
JB		 1602}
1603
ee7b9f93 1604static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1605{
ee7b9f93
JB		 1606 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1607 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1608 int reg;
ee7b9f93 1609 u32 val;
4c609cb8 1610
92f2584a
JB		 1611 /* PCH only available on ILK+ */
1612 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1613 if (pll == NULL)
1614 return;
92f2584a 1615
48da64a8
CW		 1616 if (WARN_ON(pll->refcount == 0))
1617 return;
7a419866 1618
ee7b9f93
JB		 1619 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1620 pll->pll_reg, pll->active, pll->on,
1621 intel_crtc->base.base.id);
7a419866 1622
48da64a8 1623 if (WARN_ON(pll->active == 0)) {
92b27b08 1624 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1625 return;
1626 }
1627
ee7b9f93 1628 if (--pll->active) {
92b27b08 1629 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1630 return;
ee7b9f93
JB		 1631 }
1632
1633 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1634
1635 /* Make sure transcoder isn't still depending on us */
1636 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1637
ee7b9f93 1638 reg = pll->pll_reg;
92f2584a
JB		 1639 val = I915_READ(reg);
1640 val &= ~DPLL_VCO_ENABLE;
1641 I915_WRITE(reg, val);
1642 POSTING_READ(reg);
1643 udelay(200);
ee7b9f93
JB		 1644
1645 pll->on = false;
92f2584a
JB		 1646}
1647
040484af
JB		 1648static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1649 enum pipe pipe)
1650{
1651 int reg;
5f7f726d 1652 u32 val, pipeconf_val;
7c26e5c6 1653 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1654
1655 /* PCH only available on ILK+ */
1656 BUG_ON(dev_priv->info->gen < 5);
1657
1658 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1659 assert_pch_pll_enabled(dev_priv,
1660 to_intel_crtc(crtc)->pch_pll,
1661 to_intel_crtc(crtc));
040484af
JB		 1662
1663 /* FDI must be feeding us bits for PCH ports */
1664 assert_fdi_tx_enabled(dev_priv, pipe);
1665 assert_fdi_rx_enabled(dev_priv, pipe);
1666
59c859d6
ED		 1667 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1668 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1669 return;
1670 }
040484af
JB		 1671 reg = TRANSCONF(pipe);
1672 val = I915_READ(reg);
5f7f726d 1673 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1674
1675 if (HAS_PCH_IBX(dev_priv->dev)) {
1676 /*
1677 * make the BPC in transcoder be consistent with
1678 * that in pipeconf reg.
1679 */
1680 val &= ~PIPE_BPC_MASK;
5f7f726d 1681 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1682 }
5f7f726d
PZ		 1683
1684 val &= ~TRANS_INTERLACE_MASK;
1685 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1686 if (HAS_PCH_IBX(dev_priv->dev) &&
1687 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1688 val |= TRANS_LEGACY_INTERLACED_ILK;
1689 else
1690 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1691 else
1692 val |= TRANS_PROGRESSIVE;
1693
040484af
JB		 1694 I915_WRITE(reg, val | TRANS_ENABLE);
1695 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1696 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1697}
1698
1699static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1700 enum pipe pipe)
1701{
1702 int reg;
1703 u32 val;
1704
1705 /* FDI relies on the transcoder */
1706 assert_fdi_tx_disabled(dev_priv, pipe);
1707 assert_fdi_rx_disabled(dev_priv, pipe);
1708
291906f1
JB		 1709 /* Ports must be off as well */
1710 assert_pch_ports_disabled(dev_priv, pipe);
1711
040484af
JB		 1712 reg = TRANSCONF(pipe);
1713 val = I915_READ(reg);
1714 val &= ~TRANS_ENABLE;
1715 I915_WRITE(reg, val);
1716 /* wait for PCH transcoder off, transcoder state */
1717 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1718 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1719}
1720
b24e7179 1721/**
309cfea8 1722 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1723 * @dev_priv: i915 private structure
1724 * @pipe: pipe to enable
040484af 1725 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1726 *
1727 * Enable @pipe, making sure that various hardware specific requirements
1728 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1729 *
1730 * @pipe should be %PIPE_A or %PIPE_B.
1731 *
1732 * Will wait until the pipe is actually running (i.e. first vblank) before
1733 * returning.
1734 */
040484af
JB		 1735static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1736 bool pch_port)
b24e7179
JB		 1737{
1738 int reg;
1739 u32 val;
1740
1741 /*
1742 * A pipe without a PLL won't actually be able to drive bits from
1743 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1744 * need the check.
1745 */
1746 if (!HAS_PCH_SPLIT(dev_priv->dev))
1747 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1748 else {
1749 if (pch_port) {
1750 /* if driving the PCH, we need FDI enabled */
1751 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1752 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1753 }
1754 /* FIXME: assert CPU port conditions for SNB+ */
1755 }
b24e7179
JB		 1756
1757 reg = PIPECONF(pipe);
1758 val = I915_READ(reg);
00d70b15
CW		 1759 if (val & PIPECONF_ENABLE)
1760 return;
1761
1762 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1763 intel_wait_for_vblank(dev_priv->dev, pipe);
1764}
1765
1766/**
309cfea8 1767 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1768 * @dev_priv: i915 private structure
1769 * @pipe: pipe to disable
1770 *
1771 * Disable @pipe, making sure that various hardware specific requirements
1772 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1773 *
1774 * @pipe should be %PIPE_A or %PIPE_B.
1775 *
1776 * Will wait until the pipe has shut down before returning.
1777 */
1778static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1779 enum pipe pipe)
1780{
1781 int reg;
1782 u32 val;
1783
1784 /*
1785 * Make sure planes won't keep trying to pump pixels to us,
1786 * or we might hang the display.
1787 */
1788 assert_planes_disabled(dev_priv, pipe);
1789
1790 /* Don't disable pipe A or pipe A PLLs if needed */
1791 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1792 return;
1793
1794 reg = PIPECONF(pipe);
1795 val = I915_READ(reg);
00d70b15
CW		 1796 if ((val & PIPECONF_ENABLE) == 0)
1797 return;
1798
1799 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1800 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1801}
1802
d74362c9
KP		 1803/*
1804 * Plane regs are double buffered, going from enabled->disabled needs a
1805 * trigger in order to latch. The display address reg provides this.
1806 */
6f1d69b0 1807void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1808 enum plane plane)
1809{
1810 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1811 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1812}
1813
b24e7179
JB		 1814/**
1815 * intel_enable_plane - enable a display plane on a given pipe
1816 * @dev_priv: i915 private structure
1817 * @plane: plane to enable
1818 * @pipe: pipe being fed
1819 *
1820 * Enable @plane on @pipe, making sure that @pipe is running first.
1821 */
1822static void intel_enable_plane(struct drm_i915_private *dev_priv,
1823 enum plane plane, enum pipe pipe)
1824{
1825 int reg;
1826 u32 val;
1827
1828 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1829 assert_pipe_enabled(dev_priv, pipe);
1830
1831 reg = DSPCNTR(plane);
1832 val = I915_READ(reg);
00d70b15
CW		 1833 if (val & DISPLAY_PLANE_ENABLE)
1834 return;
1835
1836 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1837 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1838 intel_wait_for_vblank(dev_priv->dev, pipe);
1839}
1840
b24e7179
JB		 1841/**
1842 * intel_disable_plane - disable a display plane
1843 * @dev_priv: i915 private structure
1844 * @plane: plane to disable
1845 * @pipe: pipe consuming the data
1846 *
1847 * Disable @plane; should be an independent operation.
1848 */
1849static void intel_disable_plane(struct drm_i915_private *dev_priv,
1850 enum plane plane, enum pipe pipe)
1851{
1852 int reg;
1853 u32 val;
1854
1855 reg = DSPCNTR(plane);
1856 val = I915_READ(reg);
00d70b15
CW		 1857 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1858 return;
1859
1860 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1861 intel_flush_display_plane(dev_priv, plane);
1862 intel_wait_for_vblank(dev_priv->dev, pipe);
1863}
1864
127bd2ac 1865int
48b956c5 1866intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1867 struct drm_i915_gem_object *obj,
919926ae 1868 struct intel_ring_buffer *pipelined)
6b95a207 1869{
ce453d81 1870 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1871 u32 alignment;
1872 int ret;
1873
05394f39 1874 switch (obj->tiling_mode) {
6b95a207 1875 case I915_TILING_NONE:
534843da
CW		 1876 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1877 alignment = 128 * 1024;
a6c45cf0 1878 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1879 alignment = 4 * 1024;
1880 else
1881 alignment = 64 * 1024;
6b95a207
KH		 1882 break;
1883 case I915_TILING_X:
1884 /* pin() will align the object as required by fence */
1885 alignment = 0;
1886 break;
1887 case I915_TILING_Y:
1888 /* FIXME: Is this true? */
1889 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1890 return -EINVAL;
1891 default:
1892 BUG();
1893 }
1894
ce453d81 1895 dev_priv->mm.interruptible = false;
2da3b9b9 1896 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1897 if (ret)
ce453d81 1898 goto err_interruptible;
6b95a207
KH		 1899
1900 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1901 * fence, whereas 965+ only requires a fence if using
1902 * framebuffer compression. For simplicity, we always install
1903 * a fence as the cost is not that onerous.
1904 */
06d98131 1905 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1906 if (ret)
1907 goto err_unpin;
1690e1eb 1908
9a5a53b3 1909 i915_gem_object_pin_fence(obj);
6b95a207 1910
ce453d81 1911 dev_priv->mm.interruptible = true;
6b95a207 1912 return 0;
48b956c5
CW		 1913
1914err_unpin:
1915 i915_gem_object_unpin(obj);
ce453d81
CW		 1916err_interruptible:
1917 dev_priv->mm.interruptible = true;
48b956c5 1918 return ret;
6b95a207
KH		 1919}
1920
1690e1eb
CW		 1921void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1922{
1923 i915_gem_object_unpin_fence(obj);
1924 i915_gem_object_unpin(obj);
1925}
1926
c2c75131
DV		 1927/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1928 * is assumed to be a power-of-two. */
1929static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1930 unsigned int bpp,
1931 unsigned int pitch)
1932{
1933 int tile_rows, tiles;
1934
1935 tile_rows = *y / 8;
1936 *y %= 8;
1937 tiles = *x / (512/bpp);
1938 *x %= 512/bpp;
1939
1940 return tile_rows * pitch * 8 + tiles * 4096;
1941}
1942
17638cd6
JB		 1943static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1944 int x, int y)
81255565
JB		 1945{
1946 struct drm_device *dev = crtc->dev;
1947 struct drm_i915_private *dev_priv = dev->dev_private;
1948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949 struct intel_framebuffer *intel_fb;
05394f39 1950 struct drm_i915_gem_object *obj;
81255565 1951 int plane = intel_crtc->plane;
e506a0c6 1952 unsigned long linear_offset;
81255565 1953 u32 dspcntr;
5eddb70b 1954 u32 reg;
81255565
JB		 1955
1956 switch (plane) {
1957 case 0:
1958 case 1:
1959 break;
1960 default:
1961 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1962 return -EINVAL;
1963 }
1964
1965 intel_fb = to_intel_framebuffer(fb);
1966 obj = intel_fb->obj;
81255565 1967
5eddb70b
CW		 1968 reg = DSPCNTR(plane);
1969 dspcntr = I915_READ(reg);
81255565
JB		 1970 /* Mask out pixel format bits in case we change it */
1971 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1972 switch (fb->bits_per_pixel) {
1973 case 8:
1974 dspcntr |= DISPPLANE_8BPP;
1975 break;
1976 case 16:
1977 if (fb->depth == 15)
1978 dspcntr |= DISPPLANE_15_16BPP;
1979 else
1980 dspcntr |= DISPPLANE_16BPP;
1981 break;
1982 case 24:
1983 case 32:
1984 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1985 break;
1986 default:
17638cd6 1987 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 1988 return -EINVAL;
1989 }
a6c45cf0 1990 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1991 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1992 dspcntr |= DISPPLANE_TILED;
1993 else
1994 dspcntr &= ~DISPPLANE_TILED;
1995 }
1996
5eddb70b 1997 I915_WRITE(reg, dspcntr);
81255565 1998
e506a0c6 1999 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2000
c2c75131
DV		 2001 if (INTEL_INFO(dev)->gen >= 4) {
2002 intel_crtc->dspaddr_offset =
2003 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2004 fb->bits_per_pixel / 8,
2005 fb->pitches[0]);
2006 linear_offset -= intel_crtc->dspaddr_offset;
2007 } else {
e506a0c6 2008 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2009 }
e506a0c6
DV		 2010
2011 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2012 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2013 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2014 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2015 I915_MODIFY_DISPBASE(DSPSURF(plane),
2016 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2017 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2018 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2019 } else
e506a0c6 2020 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2021 POSTING_READ(reg);
81255565 2022
17638cd6
JB		 2023 return 0;
2024}
2025
2026static int ironlake_update_plane(struct drm_crtc *crtc,
2027 struct drm_framebuffer *fb, int x, int y)
2028{
2029 struct drm_device *dev = crtc->dev;
2030 struct drm_i915_private *dev_priv = dev->dev_private;
2031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2032 struct intel_framebuffer *intel_fb;
2033 struct drm_i915_gem_object *obj;
2034 int plane = intel_crtc->plane;
e506a0c6 2035 unsigned long linear_offset;
17638cd6
JB		 2036 u32 dspcntr;
2037 u32 reg;
2038
2039 switch (plane) {
2040 case 0:
2041 case 1:
27f8227b 2042 case 2:
17638cd6
JB		 2043 break;
2044 default:
2045 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2046 return -EINVAL;
2047 }
2048
2049 intel_fb = to_intel_framebuffer(fb);
2050 obj = intel_fb->obj;
2051
2052 reg = DSPCNTR(plane);
2053 dspcntr = I915_READ(reg);
2054 /* Mask out pixel format bits in case we change it */
2055 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2056 switch (fb->bits_per_pixel) {
2057 case 8:
2058 dspcntr |= DISPPLANE_8BPP;
2059 break;
2060 case 16:
2061 if (fb->depth != 16)
2062 return -EINVAL;
2063
2064 dspcntr |= DISPPLANE_16BPP;
2065 break;
2066 case 24:
2067 case 32:
2068 if (fb->depth == 24)
2069 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2070 else if (fb->depth == 30)
2071 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2072 else
2073 return -EINVAL;
2074 break;
2075 default:
2076 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2077 return -EINVAL;
2078 }
2079
2080 if (obj->tiling_mode != I915_TILING_NONE)
2081 dspcntr |= DISPPLANE_TILED;
2082 else
2083 dspcntr &= ~DISPPLANE_TILED;
2084
2085 /* must disable */
2086 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2087
2088 I915_WRITE(reg, dspcntr);
2089
e506a0c6 2090 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131
DV		 2091 intel_crtc->dspaddr_offset =
2092 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2093 fb->bits_per_pixel / 8,
2094 fb->pitches[0]);
2095 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2096
e506a0c6
DV		 2097 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2098 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2099 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2100 I915_MODIFY_DISPBASE(DSPSURF(plane),
2101 obj->gtt_offset + intel_crtc->dspaddr_offset);
17638cd6 2102 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2103 I915_WRITE(DSPLINOFF(plane), linear_offset);
17638cd6
JB		 2104 POSTING_READ(reg);
2105
2106 return 0;
2107}
2108
2109/* Assume fb object is pinned & idle & fenced and just update base pointers */
2110static int
2111intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2112 int x, int y, enum mode_set_atomic state)
2113{
2114 struct drm_device *dev = crtc->dev;
2115 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2116
6b8e6ed0
CW		 2117 if (dev_priv->display.disable_fbc)
2118 dev_priv->display.disable_fbc(dev);
3dec0095 2119 intel_increase_pllclock(crtc);
81255565 2120
6b8e6ed0 2121 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2122}
2123
14667a4b
CW		 2124static int
2125intel_finish_fb(struct drm_framebuffer *old_fb)
2126{
2127 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2128 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2129 bool was_interruptible = dev_priv->mm.interruptible;
2130 int ret;
2131
2132 wait_event(dev_priv->pending_flip_queue,
2133 atomic_read(&dev_priv->mm.wedged) ||
2134 atomic_read(&obj->pending_flip) == 0);
2135
2136 /* Big Hammer, we also need to ensure that any pending
2137 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2138 * current scanout is retired before unpinning the old
2139 * framebuffer.
2140 *
2141 * This should only fail upon a hung GPU, in which case we
2142 * can safely continue.
2143 */
2144 dev_priv->mm.interruptible = false;
2145 ret = i915_gem_object_finish_gpu(obj);
2146 dev_priv->mm.interruptible = was_interruptible;
2147
2148 return ret;
2149}
2150
5c3b82e2 2151static int
3c4fdcfb 2152intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2153 struct drm_framebuffer *fb)
79e53945
JB		 2154{
2155 struct drm_device *dev = crtc->dev;
6b8e6ed0 2156 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2157 struct drm_i915_master_private *master_priv;
2158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2159 struct drm_framebuffer *old_fb;
5c3b82e2 2160 int ret;
79e53945
JB		 2161
2162 /* no fb bound */
94352cf9 2163 if (!fb) {
a5071c2f 2164 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2165 return 0;
2166 }
2167
5826eca5
ED		 2168 if(intel_crtc->plane > dev_priv->num_pipe) {
2169 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2170 intel_crtc->plane,
2171 dev_priv->num_pipe);
5c3b82e2 2172 return -EINVAL;
79e53945
JB		 2173 }
2174
5c3b82e2 2175 mutex_lock(&dev->struct_mutex);
265db958 2176 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2177 to_intel_framebuffer(fb)->obj,
919926ae 2178 NULL);
5c3b82e2
CW		 2179 if (ret != 0) {
2180 mutex_unlock(&dev->struct_mutex);
a5071c2f 2181 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2182 return ret;
2183 }
79e53945 2184
94352cf9
DV		 2185 if (crtc->fb)
2186 intel_finish_fb(crtc->fb);
265db958 2187
94352cf9 2188 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2189 if (ret) {
94352cf9 2190 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2191 mutex_unlock(&dev->struct_mutex);
a5071c2f 2192 DRM_ERROR("failed to update base address\n");
4e6cfefc 2193 return ret;
79e53945 2194 }
3c4fdcfb 2195
94352cf9
DV		 2196 old_fb = crtc->fb;
2197 crtc->fb = fb;
6c4c86f5
DV		 2198 crtc->x = x;
2199 crtc->y = y;
94352cf9 2200
b7f1de28
CW		 2201 if (old_fb) {
2202 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2203 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2204 }
652c393a 2205
6b8e6ed0 2206 intel_update_fbc(dev);
5c3b82e2 2207 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2208
2209 if (!dev->primary->master)
5c3b82e2 2210 return 0;
79e53945
JB		 2211
2212 master_priv = dev->primary->master->driver_priv;
2213 if (!master_priv->sarea_priv)
5c3b82e2 2214 return 0;
79e53945 2215
265db958 2216 if (intel_crtc->pipe) {
79e53945
JB		 2217 master_priv->sarea_priv->pipeB_x = x;
2218 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2219 } else {
2220 master_priv->sarea_priv->pipeA_x = x;
2221 master_priv->sarea_priv->pipeA_y = y;
79e53945 2222 }
5c3b82e2
CW		 2223
2224 return 0;
79e53945
JB		 2225}
2226
5eddb70b 2227static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2228{
2229 struct drm_device *dev = crtc->dev;
2230 struct drm_i915_private *dev_priv = dev->dev_private;
2231 u32 dpa_ctl;
2232
28c97730 2233 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2234 dpa_ctl = I915_READ(DP_A);
2235 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2236
2237 if (clock < 200000) {
2238 u32 temp;
2239 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2240 /* workaround for 160Mhz:
2241 1) program 0x4600c bits 15:0 = 0x8124
2242 2) program 0x46010 bit 0 = 1
2243 3) program 0x46034 bit 24 = 1
2244 4) program 0x64000 bit 14 = 1
2245 */
2246 temp = I915_READ(0x4600c);
2247 temp &= 0xffff0000;
2248 I915_WRITE(0x4600c, temp | 0x8124);
2249
2250 temp = I915_READ(0x46010);
2251 I915_WRITE(0x46010, temp | 1);
2252
2253 temp = I915_READ(0x46034);
2254 I915_WRITE(0x46034, temp | (1 << 24));
2255 } else {
2256 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2257 }
2258 I915_WRITE(DP_A, dpa_ctl);
2259
5eddb70b 2260 POSTING_READ(DP_A);
32f9d658
ZW		 2261 udelay(500);
2262}
2263
5e84e1a4
ZW		 2264static void intel_fdi_normal_train(struct drm_crtc *crtc)
2265{
2266 struct drm_device *dev = crtc->dev;
2267 struct drm_i915_private *dev_priv = dev->dev_private;
2268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269 int pipe = intel_crtc->pipe;
2270 u32 reg, temp;
2271
2272 /* enable normal train */
2273 reg = FDI_TX_CTL(pipe);
2274 temp = I915_READ(reg);
61e499bf 2275 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2276 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2277 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2278 } else {
2279 temp &= ~FDI_LINK_TRAIN_NONE;
2280 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2281 }
5e84e1a4
ZW		 2282 I915_WRITE(reg, temp);
2283
2284 reg = FDI_RX_CTL(pipe);
2285 temp = I915_READ(reg);
2286 if (HAS_PCH_CPT(dev)) {
2287 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2288 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2289 } else {
2290 temp &= ~FDI_LINK_TRAIN_NONE;
2291 temp |= FDI_LINK_TRAIN_NONE;
2292 }
2293 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2294
2295 /* wait one idle pattern time */
2296 POSTING_READ(reg);
2297 udelay(1000);
357555c0
JB		 2298
2299 /* IVB wants error correction enabled */
2300 if (IS_IVYBRIDGE(dev))
2301 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2302 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2303}
2304
291427f5
JB		 2305static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2306{
2307 struct drm_i915_private *dev_priv = dev->dev_private;
2308 u32 flags = I915_READ(SOUTH_CHICKEN1);
2309
2310 flags |= FDI_PHASE_SYNC_OVR(pipe);
2311 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2312 flags |= FDI_PHASE_SYNC_EN(pipe);
2313 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2314 POSTING_READ(SOUTH_CHICKEN1);
2315}
2316
8db9d77b
ZW		 2317/* The FDI link training functions for ILK/Ibexpeak. */
2318static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2319{
2320 struct drm_device *dev = crtc->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323 int pipe = intel_crtc->pipe;
0fc932b8 2324 int plane = intel_crtc->plane;
5eddb70b 2325 u32 reg, temp, tries;
8db9d77b 2326
0fc932b8
JB		 2327 /* FDI needs bits from pipe & plane first */
2328 assert_pipe_enabled(dev_priv, pipe);
2329 assert_plane_enabled(dev_priv, plane);
2330
e1a44743
AJ		 2331 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2332 for train result */
5eddb70b
CW		 2333 reg = FDI_RX_IMR(pipe);
2334 temp = I915_READ(reg);
e1a44743
AJ		 2335 temp &= ~FDI_RX_SYMBOL_LOCK;
2336 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2337 I915_WRITE(reg, temp);
2338 I915_READ(reg);
e1a44743
AJ		 2339 udelay(150);
2340
8db9d77b 2341 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2342 reg = FDI_TX_CTL(pipe);
2343 temp = I915_READ(reg);
77ffb597
AJ		 2344 temp &= ~(7 << 19);
2345 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2348 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2349
5eddb70b
CW		 2350 reg = FDI_RX_CTL(pipe);
2351 temp = I915_READ(reg);
8db9d77b
ZW		 2352 temp &= ~FDI_LINK_TRAIN_NONE;
2353 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2354 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2355
2356 POSTING_READ(reg);
8db9d77b
ZW		 2357 udelay(150);
2358
5b2adf89 2359 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2360 if (HAS_PCH_IBX(dev)) {
2361 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2362 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2363 FDI_RX_PHASE_SYNC_POINTER_EN);
2364 }
5b2adf89 2365
5eddb70b 2366 reg = FDI_RX_IIR(pipe);
e1a44743 2367 for (tries = 0; tries < 5; tries++) {
5eddb70b 2368 temp = I915_READ(reg);
8db9d77b
ZW		 2369 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2370
2371 if ((temp & FDI_RX_BIT_LOCK)) {
2372 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2373 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2374 break;
2375 }
8db9d77b 2376 }
e1a44743 2377 if (tries == 5)
5eddb70b 2378 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2379
2380 /* Train 2 */
5eddb70b
CW		 2381 reg = FDI_TX_CTL(pipe);
2382 temp = I915_READ(reg);
8db9d77b
ZW		 2383 temp &= ~FDI_LINK_TRAIN_NONE;
2384 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2385 I915_WRITE(reg, temp);
8db9d77b 2386
5eddb70b
CW		 2387 reg = FDI_RX_CTL(pipe);
2388 temp = I915_READ(reg);
8db9d77b
ZW		 2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2391 I915_WRITE(reg, temp);
8db9d77b 2392
5eddb70b
CW		 2393 POSTING_READ(reg);
2394 udelay(150);
8db9d77b 2395
5eddb70b 2396 reg = FDI_RX_IIR(pipe);
e1a44743 2397 for (tries = 0; tries < 5; tries++) {
5eddb70b 2398 temp = I915_READ(reg);
8db9d77b
ZW		 2399 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2400
2401 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2402 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2403 DRM_DEBUG_KMS("FDI train 2 done.\n");
2404 break;
2405 }
8db9d77b 2406 }
e1a44743 2407 if (tries == 5)
5eddb70b 2408 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2409
2410 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2411
8db9d77b
ZW		 2412}
2413
0206e353 2414static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2415 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2416 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2417 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2418 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2419};
2420
2421/* The FDI link training functions for SNB/Cougarpoint. */
2422static void gen6_fdi_link_train(struct drm_crtc *crtc)
2423{
2424 struct drm_device *dev = crtc->dev;
2425 struct drm_i915_private *dev_priv = dev->dev_private;
2426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2427 int pipe = intel_crtc->pipe;
fa37d39e 2428 u32 reg, temp, i, retry;
8db9d77b 2429
e1a44743
AJ		 2430 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2431 for train result */
5eddb70b
CW		 2432 reg = FDI_RX_IMR(pipe);
2433 temp = I915_READ(reg);
e1a44743
AJ		 2434 temp &= ~FDI_RX_SYMBOL_LOCK;
2435 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2436 I915_WRITE(reg, temp);
2437
2438 POSTING_READ(reg);
e1a44743
AJ		 2439 udelay(150);
2440
8db9d77b 2441 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2442 reg = FDI_TX_CTL(pipe);
2443 temp = I915_READ(reg);
77ffb597
AJ		 2444 temp &= ~(7 << 19);
2445 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_1;
2448 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2449 /* SNB-B */
2450 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2451 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2452
5eddb70b
CW		 2453 reg = FDI_RX_CTL(pipe);
2454 temp = I915_READ(reg);
8db9d77b
ZW		 2455 if (HAS_PCH_CPT(dev)) {
2456 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2457 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2458 } else {
2459 temp &= ~FDI_LINK_TRAIN_NONE;
2460 temp |= FDI_LINK_TRAIN_PATTERN_1;
2461 }
5eddb70b
CW		 2462 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2463
2464 POSTING_READ(reg);
8db9d77b
ZW		 2465 udelay(150);
2466
291427f5
JB		 2467 if (HAS_PCH_CPT(dev))
2468 cpt_phase_pointer_enable(dev, pipe);
2469
0206e353 2470 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2471 reg = FDI_TX_CTL(pipe);
2472 temp = I915_READ(reg);
8db9d77b
ZW		 2473 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2474 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2475 I915_WRITE(reg, temp);
2476
2477 POSTING_READ(reg);
8db9d77b
ZW		 2478 udelay(500);
2479
fa37d39e
SP		 2480 for (retry = 0; retry < 5; retry++) {
2481 reg = FDI_RX_IIR(pipe);
2482 temp = I915_READ(reg);
2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484 if (temp & FDI_RX_BIT_LOCK) {
2485 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2486 DRM_DEBUG_KMS("FDI train 1 done.\n");
2487 break;
2488 }
2489 udelay(50);
8db9d77b 2490 }
fa37d39e
SP		 2491 if (retry < 5)
2492 break;
8db9d77b
ZW		 2493 }
2494 if (i == 4)
5eddb70b 2495 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2496
2497 /* Train 2 */
5eddb70b
CW		 2498 reg = FDI_TX_CTL(pipe);
2499 temp = I915_READ(reg);
8db9d77b
ZW		 2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_2;
2502 if (IS_GEN6(dev)) {
2503 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2504 /* SNB-B */
2505 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2506 }
5eddb70b 2507 I915_WRITE(reg, temp);
8db9d77b 2508
5eddb70b
CW		 2509 reg = FDI_RX_CTL(pipe);
2510 temp = I915_READ(reg);
8db9d77b
ZW		 2511 if (HAS_PCH_CPT(dev)) {
2512 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2513 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2514 } else {
2515 temp &= ~FDI_LINK_TRAIN_NONE;
2516 temp |= FDI_LINK_TRAIN_PATTERN_2;
2517 }
5eddb70b
CW		 2518 I915_WRITE(reg, temp);
2519
2520 POSTING_READ(reg);
8db9d77b
ZW		 2521 udelay(150);
2522
0206e353 2523 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2524 reg = FDI_TX_CTL(pipe);
2525 temp = I915_READ(reg);
8db9d77b
ZW		 2526 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2528 I915_WRITE(reg, temp);
2529
2530 POSTING_READ(reg);
8db9d77b
ZW		 2531 udelay(500);
2532
fa37d39e
SP		 2533 for (retry = 0; retry < 5; retry++) {
2534 reg = FDI_RX_IIR(pipe);
2535 temp = I915_READ(reg);
2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537 if (temp & FDI_RX_SYMBOL_LOCK) {
2538 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2539 DRM_DEBUG_KMS("FDI train 2 done.\n");
2540 break;
2541 }
2542 udelay(50);
8db9d77b 2543 }
fa37d39e
SP		 2544 if (retry < 5)
2545 break;
8db9d77b
ZW		 2546 }
2547 if (i == 4)
5eddb70b 2548 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2549
2550 DRM_DEBUG_KMS("FDI train done.\n");
2551}
2552
357555c0
JB		 2553/* Manual link training for Ivy Bridge A0 parts */
2554static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2555{
2556 struct drm_device *dev = crtc->dev;
2557 struct drm_i915_private *dev_priv = dev->dev_private;
2558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2559 int pipe = intel_crtc->pipe;
2560 u32 reg, temp, i;
2561
2562 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2563 for train result */
2564 reg = FDI_RX_IMR(pipe);
2565 temp = I915_READ(reg);
2566 temp &= ~FDI_RX_SYMBOL_LOCK;
2567 temp &= ~FDI_RX_BIT_LOCK;
2568 I915_WRITE(reg, temp);
2569
2570 POSTING_READ(reg);
2571 udelay(150);
2572
2573 /* enable CPU FDI TX and PCH FDI RX */
2574 reg = FDI_TX_CTL(pipe);
2575 temp = I915_READ(reg);
2576 temp &= ~(7 << 19);
2577 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2578 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2579 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2580 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2581 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2582 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2583 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2584
2585 reg = FDI_RX_CTL(pipe);
2586 temp = I915_READ(reg);
2587 temp &= ~FDI_LINK_TRAIN_AUTO;
2588 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2590 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2591 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2592
2593 POSTING_READ(reg);
2594 udelay(150);
2595
291427f5
JB		 2596 if (HAS_PCH_CPT(dev))
2597 cpt_phase_pointer_enable(dev, pipe);
2598
0206e353 2599 for (i = 0; i < 4; i++) {
357555c0
JB		 2600 reg = FDI_TX_CTL(pipe);
2601 temp = I915_READ(reg);
2602 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603 temp |= snb_b_fdi_train_param[i];
2604 I915_WRITE(reg, temp);
2605
2606 POSTING_READ(reg);
2607 udelay(500);
2608
2609 reg = FDI_RX_IIR(pipe);
2610 temp = I915_READ(reg);
2611 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2612
2613 if (temp & FDI_RX_BIT_LOCK ||
2614 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2615 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2616 DRM_DEBUG_KMS("FDI train 1 done.\n");
2617 break;
2618 }
2619 }
2620 if (i == 4)
2621 DRM_ERROR("FDI train 1 fail!\n");
2622
2623 /* Train 2 */
2624 reg = FDI_TX_CTL(pipe);
2625 temp = I915_READ(reg);
2626 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2627 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2628 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2629 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2630 I915_WRITE(reg, temp);
2631
2632 reg = FDI_RX_CTL(pipe);
2633 temp = I915_READ(reg);
2634 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2636 I915_WRITE(reg, temp);
2637
2638 POSTING_READ(reg);
2639 udelay(150);
2640
0206e353 2641 for (i = 0; i < 4; i++) {
357555c0
JB		 2642 reg = FDI_TX_CTL(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645 temp |= snb_b_fdi_train_param[i];
2646 I915_WRITE(reg, temp);
2647
2648 POSTING_READ(reg);
2649 udelay(500);
2650
2651 reg = FDI_RX_IIR(pipe);
2652 temp = I915_READ(reg);
2653 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2654
2655 if (temp & FDI_RX_SYMBOL_LOCK) {
2656 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2657 DRM_DEBUG_KMS("FDI train 2 done.\n");
2658 break;
2659 }
2660 }
2661 if (i == 4)
2662 DRM_ERROR("FDI train 2 fail!\n");
2663
2664 DRM_DEBUG_KMS("FDI train done.\n");
2665}
2666
88cefb6c 2667static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2668{
88cefb6c 2669 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2670 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2671 int pipe = intel_crtc->pipe;
5eddb70b 2672 u32 reg, temp;
79e53945 2673
c64e311e 2674 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2675 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2676 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2677
c98e9dcf 2678 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2679 reg = FDI_RX_CTL(pipe);
2680 temp = I915_READ(reg);
2681 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2682 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2683 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2684 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2685
2686 POSTING_READ(reg);
c98e9dcf
JB		 2687 udelay(200);
2688
2689 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2690 temp = I915_READ(reg);
2691 I915_WRITE(reg, temp | FDI_PCDCLK);
2692
2693 POSTING_READ(reg);
c98e9dcf
JB		 2694 udelay(200);
2695
bf507ef7
ED		 2696 /* On Haswell, the PLL configuration for ports and pipes is handled
2697 * separately, as part of DDI setup */
2698 if (!IS_HASWELL(dev)) {
2699 /* Enable CPU FDI TX PLL, always on for Ironlake */
2700 reg = FDI_TX_CTL(pipe);
2701 temp = I915_READ(reg);
2702 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2703 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2704
bf507ef7
ED		 2705 POSTING_READ(reg);
2706 udelay(100);
2707 }
6be4a607 2708 }
0e23b99d
JB		 2709}
2710
88cefb6c
DV		 2711static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2712{
2713 struct drm_device *dev = intel_crtc->base.dev;
2714 struct drm_i915_private *dev_priv = dev->dev_private;
2715 int pipe = intel_crtc->pipe;
2716 u32 reg, temp;
2717
2718 /* Switch from PCDclk to Rawclk */
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2722
2723 /* Disable CPU FDI TX PLL */
2724 reg = FDI_TX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2727
2728 POSTING_READ(reg);
2729 udelay(100);
2730
2731 reg = FDI_RX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2734
2735 /* Wait for the clocks to turn off. */
2736 POSTING_READ(reg);
2737 udelay(100);
2738}
2739
291427f5
JB		 2740static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2741{
2742 struct drm_i915_private *dev_priv = dev->dev_private;
2743 u32 flags = I915_READ(SOUTH_CHICKEN1);
2744
2745 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2746 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2747 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2748 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2749 POSTING_READ(SOUTH_CHICKEN1);
2750}
0fc932b8
JB		 2751static void ironlake_fdi_disable(struct drm_crtc *crtc)
2752{
2753 struct drm_device *dev = crtc->dev;
2754 struct drm_i915_private *dev_priv = dev->dev_private;
2755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2756 int pipe = intel_crtc->pipe;
2757 u32 reg, temp;
2758
2759 /* disable CPU FDI tx and PCH FDI rx */
2760 reg = FDI_TX_CTL(pipe);
2761 temp = I915_READ(reg);
2762 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2763 POSTING_READ(reg);
2764
2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 temp &= ~(0x7 << 16);
2768 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2769 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2770
2771 POSTING_READ(reg);
2772 udelay(100);
2773
2774 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2775 if (HAS_PCH_IBX(dev)) {
2776 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2777 I915_WRITE(FDI_RX_CHICKEN(pipe),
2778 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2779 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2780 } else if (HAS_PCH_CPT(dev)) {
2781 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2782 }
0fc932b8
JB		 2783
2784 /* still set train pattern 1 */
2785 reg = FDI_TX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 temp &= ~FDI_LINK_TRAIN_NONE;
2788 temp |= FDI_LINK_TRAIN_PATTERN_1;
2789 I915_WRITE(reg, temp);
2790
2791 reg = FDI_RX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 if (HAS_PCH_CPT(dev)) {
2794 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2795 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2796 } else {
2797 temp &= ~FDI_LINK_TRAIN_NONE;
2798 temp |= FDI_LINK_TRAIN_PATTERN_1;
2799 }
2800 /* BPC in FDI rx is consistent with that in PIPECONF */
2801 temp &= ~(0x07 << 16);
2802 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2803 I915_WRITE(reg, temp);
2804
2805 POSTING_READ(reg);
2806 udelay(100);
2807}
2808
e6c3a2a6
CW		 2809static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2810{
0f91128d 2811 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2812
2813 if (crtc->fb == NULL)
2814 return;
2815
0f91128d
CW		 2816 mutex_lock(&dev->struct_mutex);
2817 intel_finish_fb(crtc->fb);
2818 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2819}
2820
040484af
JB		 2821static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2822{
2823 struct drm_device *dev = crtc->dev;
228d3e36 2824 struct intel_encoder *intel_encoder;
040484af
JB		 2825
2826 /*
2827 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2828 * must be driven by its own crtc; no sharing is possible.
2829 */
228d3e36 2830 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
040484af 2831
6ee8bab0
ED		 2832 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2833 * CPU handles all others */
2834 if (IS_HASWELL(dev)) {
2835 /* It is still unclear how this will work on PPT, so throw up a warning */
2836 WARN_ON(!HAS_PCH_LPT(dev));
2837
228d3e36 2838 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
6ee8bab0
ED		 2839 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2840 return true;
2841 } else {
2842 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
228d3e36 2843 intel_encoder->type);
6ee8bab0
ED		 2844 return false;
2845 }
2846 }
2847
228d3e36 2848 switch (intel_encoder->type) {
040484af 2849 case INTEL_OUTPUT_EDP:
228d3e36 2850 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2851 return false;
2852 continue;
2853 }
2854 }
2855
2856 return true;
2857}
2858
e615efe4
ED		 2859/* Program iCLKIP clock to the desired frequency */
2860static void lpt_program_iclkip(struct drm_crtc *crtc)
2861{
2862 struct drm_device *dev = crtc->dev;
2863 struct drm_i915_private *dev_priv = dev->dev_private;
2864 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2865 u32 temp;
2866
2867 /* It is necessary to ungate the pixclk gate prior to programming
2868 * the divisors, and gate it back when it is done.
2869 */
2870 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2871
2872 /* Disable SSCCTL */
2873 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2874 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2875 SBI_SSCCTL_DISABLE);
2876
2877 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2878 if (crtc->mode.clock == 20000) {
2879 auxdiv = 1;
2880 divsel = 0x41;
2881 phaseinc = 0x20;
2882 } else {
2883 /* The iCLK virtual clock root frequency is in MHz,
2884 * but the crtc->mode.clock in in KHz. To get the divisors,
2885 * it is necessary to divide one by another, so we
2886 * convert the virtual clock precision to KHz here for higher
2887 * precision.
2888 */
2889 u32 iclk_virtual_root_freq = 172800 * 1000;
2890 u32 iclk_pi_range = 64;
2891 u32 desired_divisor, msb_divisor_value, pi_value;
2892
2893 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2894 msb_divisor_value = desired_divisor / iclk_pi_range;
2895 pi_value = desired_divisor % iclk_pi_range;
2896
2897 auxdiv = 0;
2898 divsel = msb_divisor_value - 2;
2899 phaseinc = pi_value;
2900 }
2901
2902 /* This should not happen with any sane values */
2903 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2904 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2905 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2906 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2907
2908 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2909 crtc->mode.clock,
2910 auxdiv,
2911 divsel,
2912 phasedir,
2913 phaseinc);
2914
2915 /* Program SSCDIVINTPHASE6 */
2916 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2917 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2918 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2919 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2920 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2921 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2922 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2923
2924 intel_sbi_write(dev_priv,
2925 SBI_SSCDIVINTPHASE6,
2926 temp);
2927
2928 /* Program SSCAUXDIV */
2929 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2930 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2931 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2932 intel_sbi_write(dev_priv,
2933 SBI_SSCAUXDIV6,
2934 temp);
2935
2936
2937 /* Enable modulator and associated divider */
2938 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2939 temp &= ~SBI_SSCCTL_DISABLE;
2940 intel_sbi_write(dev_priv,
2941 SBI_SSCCTL6,
2942 temp);
2943
2944 /* Wait for initialization time */
2945 udelay(24);
2946
2947 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2948}
2949
f67a559d
JB		 2950/*
2951 * Enable PCH resources required for PCH ports:
2952 * - PCH PLLs
2953 * - FDI training & RX/TX
2954 * - update transcoder timings
2955 * - DP transcoding bits
2956 * - transcoder
2957 */
2958static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2959{
2960 struct drm_device *dev = crtc->dev;
2961 struct drm_i915_private *dev_priv = dev->dev_private;
2962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963 int pipe = intel_crtc->pipe;
ee7b9f93 2964 u32 reg, temp;
2c07245f 2965
e7e164db
CW		 2966 assert_transcoder_disabled(dev_priv, pipe);
2967
c98e9dcf 2968 /* For PCH output, training FDI link */
674cf967 2969 dev_priv->display.fdi_link_train(crtc);
2c07245f 2970
6f13b7b5
CW		 2971 intel_enable_pch_pll(intel_crtc);
2972
e615efe4
ED		 2973 if (HAS_PCH_LPT(dev)) {
2974 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2975 lpt_program_iclkip(crtc);
2976 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 2977 u32 sel;
4b645f14 2978
c98e9dcf 2979 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2980 switch (pipe) {
2981 default:
2982 case 0:
2983 temp |= TRANSA_DPLL_ENABLE;
2984 sel = TRANSA_DPLLB_SEL;
2985 break;
2986 case 1:
2987 temp |= TRANSB_DPLL_ENABLE;
2988 sel = TRANSB_DPLLB_SEL;
2989 break;
2990 case 2:
2991 temp |= TRANSC_DPLL_ENABLE;
2992 sel = TRANSC_DPLLB_SEL;
2993 break;
d64311ab 2994 }
ee7b9f93
JB		 2995 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2996 temp |= sel;
2997 else
2998 temp &= ~sel;
c98e9dcf 2999 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3000 }
5eddb70b 3001
d9b6cb56
JB		 3002 /* set transcoder timing, panel must allow it */
3003 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3004 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3005 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3006 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3007
5eddb70b
CW		 3008 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3009 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3010 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3011 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3012
f57e1e3a
ED		 3013 if (!IS_HASWELL(dev))
3014 intel_fdi_normal_train(crtc);
5e84e1a4 3015
c98e9dcf
JB		 3016 /* For PCH DP, enable TRANS_DP_CTL */
3017 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3018 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3019 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3020 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3021 reg = TRANS_DP_CTL(pipe);
3022 temp = I915_READ(reg);
3023 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3024 TRANS_DP_SYNC_MASK |
3025 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3026 temp |= (TRANS_DP_OUTPUT_ENABLE |
3027 TRANS_DP_ENH_FRAMING);
9325c9f0 3028 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3029
3030 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3031 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3032 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3033 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3034
3035 switch (intel_trans_dp_port_sel(crtc)) {
3036 case PCH_DP_B:
5eddb70b 3037 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3038 break;
3039 case PCH_DP_C:
5eddb70b 3040 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3041 break;
3042 case PCH_DP_D:
5eddb70b 3043 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3044 break;
3045 default:
3046 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3047 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3048 break;
32f9d658 3049 }
2c07245f 3050
5eddb70b 3051 I915_WRITE(reg, temp);
6be4a607 3052 }
b52eb4dc 3053
040484af 3054 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3055}
3056
ee7b9f93
JB		 3057static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3058{
3059 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3060
3061 if (pll == NULL)
3062 return;
3063
3064 if (pll->refcount == 0) {
3065 WARN(1, "bad PCH PLL refcount\n");
3066 return;
3067 }
3068
3069 --pll->refcount;
3070 intel_crtc->pch_pll = NULL;
3071}
3072
3073static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3074{
3075 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3076 struct intel_pch_pll *pll;
3077 int i;
3078
3079 pll = intel_crtc->pch_pll;
3080 if (pll) {
3081 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3082 intel_crtc->base.base.id, pll->pll_reg);
3083 goto prepare;
3084 }
3085
98b6bd99
DV		 3086 if (HAS_PCH_IBX(dev_priv->dev)) {
3087 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3088 i = intel_crtc->pipe;
3089 pll = &dev_priv->pch_plls[i];
3090
3091 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3092 intel_crtc->base.base.id, pll->pll_reg);
3093
3094 goto found;
3095 }
3096
ee7b9f93
JB		 3097 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3098 pll = &dev_priv->pch_plls[i];
3099
3100 /* Only want to check enabled timings first */
3101 if (pll->refcount == 0)
3102 continue;
3103
3104 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3105 fp == I915_READ(pll->fp0_reg)) {
3106 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3107 intel_crtc->base.base.id,
3108 pll->pll_reg, pll->refcount, pll->active);
3109
3110 goto found;
3111 }
3112 }
3113
3114 /* Ok no matching timings, maybe there's a free one? */
3115 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3116 pll = &dev_priv->pch_plls[i];
3117 if (pll->refcount == 0) {
3118 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3119 intel_crtc->base.base.id, pll->pll_reg);
3120 goto found;
3121 }
3122 }
3123
3124 return NULL;
3125
3126found:
3127 intel_crtc->pch_pll = pll;
3128 pll->refcount++;
3129 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3130prepare: /* separate function? */
3131 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3132
e04c7350
CW		 3133 /* Wait for the clocks to stabilize before rewriting the regs */
3134 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3135 POSTING_READ(pll->pll_reg);
3136 udelay(150);
e04c7350
CW		 3137
3138 I915_WRITE(pll->fp0_reg, fp);
3139 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3140 pll->on = false;
3141 return pll;
3142}
3143
d4270e57
JB		 3144void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3145{
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3147 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3148 u32 temp;
3149
3150 temp = I915_READ(dslreg);
3151 udelay(500);
3152 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3153 /* Without this, mode sets may fail silently on FDI */
3154 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3155 udelay(250);
3156 I915_WRITE(tc2reg, 0);
3157 if (wait_for(I915_READ(dslreg) != temp, 5))
3158 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3159 }
3160}
3161
f67a559d
JB		 3162static void ironlake_crtc_enable(struct drm_crtc *crtc)
3163{
3164 struct drm_device *dev = crtc->dev;
3165 struct drm_i915_private *dev_priv = dev->dev_private;
3166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3167 struct intel_encoder *encoder;
f67a559d
JB		 3168 int pipe = intel_crtc->pipe;
3169 int plane = intel_crtc->plane;
3170 u32 temp;
3171 bool is_pch_port;
3172
08a48469
DV		 3173 WARN_ON(!crtc->enabled);
3174
f67a559d
JB		 3175 if (intel_crtc->active)
3176 return;
3177
3178 intel_crtc->active = true;
3179 intel_update_watermarks(dev);
3180
3181 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3182 temp = I915_READ(PCH_LVDS);
3183 if ((temp & LVDS_PORT_EN) == 0)
3184 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3185 }
3186
3187 is_pch_port = intel_crtc_driving_pch(crtc);
3188
46b6f814 3189 if (is_pch_port) {
88cefb6c 3190 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3191 } else {
3192 assert_fdi_tx_disabled(dev_priv, pipe);
3193 assert_fdi_rx_disabled(dev_priv, pipe);
3194 }
f67a559d 3195
bf49ec8c
DV		 3196 for_each_encoder_on_crtc(dev, crtc, encoder)
3197 if (encoder->pre_enable)
3198 encoder->pre_enable(encoder);
3199
f67a559d
JB		 3200 /* Enable panel fitting for LVDS */
3201 if (dev_priv->pch_pf_size &&
3202 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3203 /* Force use of hard-coded filter coefficients
3204 * as some pre-programmed values are broken,
3205 * e.g. x201.
3206 */
9db4a9c7
JB		 3207 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3208 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3209 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3210 }
3211
9c54c0dd
JB		 3212 /*
3213 * On ILK+ LUT must be loaded before the pipe is running but with
3214 * clocks enabled
3215 */
3216 intel_crtc_load_lut(crtc);
3217
8d9ddbcb
PZ		 3218 if (IS_HASWELL(dev))
3219 intel_ddi_enable_pipe_func(crtc);
3220
f67a559d
JB		 3221 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3222 intel_enable_plane(dev_priv, plane, pipe);
3223
3224 if (is_pch_port)
3225 ironlake_pch_enable(crtc);
c98e9dcf 3226
d1ebd816 3227 mutex_lock(&dev->struct_mutex);
bed4a673 3228 intel_update_fbc(dev);
d1ebd816
BW		 3229 mutex_unlock(&dev->struct_mutex);
3230
6b383a7f 3231 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3232
fa5c73b1
DV		 3233 for_each_encoder_on_crtc(dev, crtc, encoder)
3234 encoder->enable(encoder);
61b77ddd
DV		 3235
3236 if (HAS_PCH_CPT(dev))
3237 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 3238}
3239
3240static void ironlake_crtc_disable(struct drm_crtc *crtc)
3241{
3242 struct drm_device *dev = crtc->dev;
3243 struct drm_i915_private *dev_priv = dev->dev_private;
3244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3245 struct intel_encoder *encoder;
6be4a607
JB		 3246 int pipe = intel_crtc->pipe;
3247 int plane = intel_crtc->plane;
5eddb70b 3248 u32 reg, temp;
b52eb4dc 3249
ef9c3aee 3250
f7abfe8b
CW		 3251 if (!intel_crtc->active)
3252 return;
3253
ea9d758d
DV		 3254 for_each_encoder_on_crtc(dev, crtc, encoder)
3255 encoder->disable(encoder);
3256
e6c3a2a6 3257 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3258 drm_vblank_off(dev, pipe);
6b383a7f 3259 intel_crtc_update_cursor(crtc, false);
5eddb70b 3260
b24e7179 3261 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3262
973d04f9
CW		 3263 if (dev_priv->cfb_plane == plane)
3264 intel_disable_fbc(dev);
2c07245f 3265
b24e7179 3266 intel_disable_pipe(dev_priv, pipe);
32f9d658 3267
8d9ddbcb
PZ		 3268 if (IS_HASWELL(dev))
3269 intel_ddi_disable_pipe_func(dev_priv, pipe);
3270
6be4a607 3271 /* Disable PF */
9db4a9c7
JB		 3272 I915_WRITE(PF_CTL(pipe), 0);
3273 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3274
bf49ec8c
DV		 3275 for_each_encoder_on_crtc(dev, crtc, encoder)
3276 if (encoder->post_disable)
3277 encoder->post_disable(encoder);
3278
0fc932b8 3279 ironlake_fdi_disable(crtc);
2c07245f 3280
040484af 3281 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3282
6be4a607
JB		 3283 if (HAS_PCH_CPT(dev)) {
3284 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3285 reg = TRANS_DP_CTL(pipe);
3286 temp = I915_READ(reg);
3287 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3288 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3289 I915_WRITE(reg, temp);
6be4a607
JB		 3290
3291 /* disable DPLL_SEL */
3292 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3293 switch (pipe) {
3294 case 0:
d64311ab 3295 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3296 break;
3297 case 1:
6be4a607 3298 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3299 break;
3300 case 2:
4b645f14 3301 /* C shares PLL A or B */
d64311ab 3302 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3303 break;
3304 default:
3305 BUG(); /* wtf */
3306 }
6be4a607 3307 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3308 }
e3421a18 3309
6be4a607 3310 /* disable PCH DPLL */
ee7b9f93 3311 intel_disable_pch_pll(intel_crtc);
8db9d77b 3312
88cefb6c 3313 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3314
f7abfe8b 3315 intel_crtc->active = false;
6b383a7f 3316 intel_update_watermarks(dev);
d1ebd816
BW		 3317
3318 mutex_lock(&dev->struct_mutex);
6b383a7f 3319 intel_update_fbc(dev);
d1ebd816 3320 mutex_unlock(&dev->struct_mutex);
6be4a607 3321}
1b3c7a47 3322
ee7b9f93
JB		 3323static void ironlake_crtc_off(struct drm_crtc *crtc)
3324{
3325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3326 intel_put_pch_pll(intel_crtc);
3327}
3328
02e792fb
DV		 3329static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3330{
02e792fb 3331 if (!enable && intel_crtc->overlay) {
23f09ce3 3332 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3333 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3334
23f09ce3 3335 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3336 dev_priv->mm.interruptible = false;
3337 (void) intel_overlay_switch_off(intel_crtc->overlay);
3338 dev_priv->mm.interruptible = true;
23f09ce3 3339 mutex_unlock(&dev->struct_mutex);
02e792fb 3340 }
02e792fb 3341
5dcdbcb0
CW		 3342 /* Let userspace switch the overlay on again. In most cases userspace
3343 * has to recompute where to put it anyway.
3344 */
02e792fb
DV		 3345}
3346
0b8765c6 3347static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3348{
3349 struct drm_device *dev = crtc->dev;
79e53945
JB		 3350 struct drm_i915_private *dev_priv = dev->dev_private;
3351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3352 struct intel_encoder *encoder;
79e53945 3353 int pipe = intel_crtc->pipe;
80824003 3354 int plane = intel_crtc->plane;
79e53945 3355
08a48469
DV		 3356 WARN_ON(!crtc->enabled);
3357
f7abfe8b
CW		 3358 if (intel_crtc->active)
3359 return;
3360
3361 intel_crtc->active = true;
6b383a7f
CW		 3362 intel_update_watermarks(dev);
3363
63d7bbe9 3364 intel_enable_pll(dev_priv, pipe);
040484af 3365 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3366 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3367
0b8765c6 3368 intel_crtc_load_lut(crtc);
bed4a673 3369 intel_update_fbc(dev);
79e53945 3370
0b8765c6
JB		 3371 /* Give the overlay scaler a chance to enable if it's on this pipe */
3372 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3373 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3374
fa5c73b1
DV		 3375 for_each_encoder_on_crtc(dev, crtc, encoder)
3376 encoder->enable(encoder);
0b8765c6 3377}
79e53945 3378
0b8765c6
JB		 3379static void i9xx_crtc_disable(struct drm_crtc *crtc)
3380{
3381 struct drm_device *dev = crtc->dev;
3382 struct drm_i915_private *dev_priv = dev->dev_private;
3383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3384 struct intel_encoder *encoder;
0b8765c6
JB		 3385 int pipe = intel_crtc->pipe;
3386 int plane = intel_crtc->plane;
b690e96c 3387
ef9c3aee 3388
f7abfe8b
CW		 3389 if (!intel_crtc->active)
3390 return;
3391
ea9d758d
DV		 3392 for_each_encoder_on_crtc(dev, crtc, encoder)
3393 encoder->disable(encoder);
3394
0b8765c6 3395 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3396 intel_crtc_wait_for_pending_flips(crtc);
3397 drm_vblank_off(dev, pipe);
0b8765c6 3398 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3399 intel_crtc_update_cursor(crtc, false);
0b8765c6 3400
973d04f9
CW		 3401 if (dev_priv->cfb_plane == plane)
3402 intel_disable_fbc(dev);
79e53945 3403
b24e7179 3404 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3405 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3406 intel_disable_pll(dev_priv, pipe);
0b8765c6 3407
f7abfe8b 3408 intel_crtc->active = false;
6b383a7f
CW		 3409 intel_update_fbc(dev);
3410 intel_update_watermarks(dev);
0b8765c6
JB		 3411}
3412
ee7b9f93
JB		 3413static void i9xx_crtc_off(struct drm_crtc *crtc)
3414{
3415}
3416
976f8a20
DV		 3417static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3418 bool enabled)
2c07245f
ZW		 3419{
3420 struct drm_device *dev = crtc->dev;
3421 struct drm_i915_master_private *master_priv;
3422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3423 int pipe = intel_crtc->pipe;
79e53945
JB		 3424
3425 if (!dev->primary->master)
3426 return;
3427
3428 master_priv = dev->primary->master->driver_priv;
3429 if (!master_priv->sarea_priv)
3430 return;
3431
79e53945
JB		 3432 switch (pipe) {
3433 case 0:
3434 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3435 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3436 break;
3437 case 1:
3438 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3439 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3440 break;
3441 default:
9db4a9c7 3442 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3443 break;
3444 }
79e53945
JB		 3445}
3446
976f8a20
DV		 3447/**
3448 * Sets the power management mode of the pipe and plane.
3449 */
3450void intel_crtc_update_dpms(struct drm_crtc *crtc)
3451{
3452 struct drm_device *dev = crtc->dev;
3453 struct drm_i915_private *dev_priv = dev->dev_private;
3454 struct intel_encoder *intel_encoder;
3455 bool enable = false;
3456
3457 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3458 enable |= intel_encoder->connectors_active;
3459
3460 if (enable)
3461 dev_priv->display.crtc_enable(crtc);
3462 else
3463 dev_priv->display.crtc_disable(crtc);
3464
3465 intel_crtc_update_sarea(crtc, enable);
3466}
3467
3468static void intel_crtc_noop(struct drm_crtc *crtc)
3469{
3470}
3471
cdd59983
CW		 3472static void intel_crtc_disable(struct drm_crtc *crtc)
3473{
cdd59983 3474 struct drm_device *dev = crtc->dev;
976f8a20 3475 struct drm_connector *connector;
ee7b9f93 3476 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3477
976f8a20
DV		 3478 /* crtc should still be enabled when we disable it. */
3479 WARN_ON(!crtc->enabled);
3480
3481 dev_priv->display.crtc_disable(crtc);
3482 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3483 dev_priv->display.off(crtc);
3484
931872fc
CW		 3485 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3486 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3487
3488 if (crtc->fb) {
3489 mutex_lock(&dev->struct_mutex);
1690e1eb 3490 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3491 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3492 crtc->fb = NULL;
3493 }
3494
3495 /* Update computed state. */
3496 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3497 if (!connector->encoder || !connector->encoder->crtc)
3498 continue;
3499
3500 if (connector->encoder->crtc != crtc)
3501 continue;
3502
3503 connector->dpms = DRM_MODE_DPMS_OFF;
3504 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3505 }
3506}
3507
a261b246 3508void intel_modeset_disable(struct drm_device *dev)
79e53945 3509{
a261b246
DV		 3510 struct drm_crtc *crtc;
3511
3512 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3513 if (crtc->enabled)
3514 intel_crtc_disable(crtc);
3515 }
79e53945
JB		 3516}
3517
1f703855 3518void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3519{
7e7d76c3
JB		 3520}
3521
ea5b213a 3522void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3523{
4ef69c7a 3524 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3525
ea5b213a
CW		 3526 drm_encoder_cleanup(encoder);
3527 kfree(intel_encoder);
7e7d76c3
JB		 3528}
3529
5ab432ef
DV		 3530/* Simple dpms helper for encodres with just one connector, no cloning and only
3531 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3532 * state of the entire output pipe. */
3533void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3534{
5ab432ef
DV		 3535 if (mode == DRM_MODE_DPMS_ON) {
3536 encoder->connectors_active = true;
3537
b2cabb0e 3538 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3539 } else {
3540 encoder->connectors_active = false;
3541
b2cabb0e 3542 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3543 }
79e53945
JB		 3544}
3545
0a91ca29
DV		 3546/* Cross check the actual hw state with our own modeset state tracking (and it's
3547 * internal consistency). */
b980514c 3548static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3549{
0a91ca29
DV		 3550 if (connector->get_hw_state(connector)) {
3551 struct intel_encoder *encoder = connector->encoder;
3552 struct drm_crtc *crtc;
3553 bool encoder_enabled;
3554 enum pipe pipe;
3555
3556 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3557 connector->base.base.id,
3558 drm_get_connector_name(&connector->base));
3559
3560 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3561 "wrong connector dpms state\n");
3562 WARN(connector->base.encoder != &encoder->base,
3563 "active connector not linked to encoder\n");
3564 WARN(!encoder->connectors_active,
3565 "encoder->connectors_active not set\n");
3566
3567 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3568 WARN(!encoder_enabled, "encoder not enabled\n");
3569 if (WARN_ON(!encoder->base.crtc))
3570 return;
3571
3572 crtc = encoder->base.crtc;
3573
3574 WARN(!crtc->enabled, "crtc not enabled\n");
3575 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3576 WARN(pipe != to_intel_crtc(crtc)->pipe,
3577 "encoder active on the wrong pipe\n");
3578 }
79e53945
JB		 3579}
3580
5ab432ef
DV		 3581/* Even simpler default implementation, if there's really no special case to
3582 * consider. */
3583void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3584{
5ab432ef 3585 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3586
5ab432ef
DV		 3587 /* All the simple cases only support two dpms states. */
3588 if (mode != DRM_MODE_DPMS_ON)
3589 mode = DRM_MODE_DPMS_OFF;
d4270e57 3590
5ab432ef
DV		 3591 if (mode == connector->dpms)
3592 return;
3593
3594 connector->dpms = mode;
3595
3596 /* Only need to change hw state when actually enabled */
3597 if (encoder->base.crtc)
3598 intel_encoder_dpms(encoder, mode);
3599 else
8af6cf88 3600 WARN_ON(encoder->connectors_active != false);
0a91ca29 3601
b980514c 3602 intel_modeset_check_state(connector->dev);
79e53945
JB		 3603}
3604
f0947c37
DV		 3605/* Simple connector->get_hw_state implementation for encoders that support only
3606 * one connector and no cloning and hence the encoder state determines the state
3607 * of the connector. */
3608bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3609{
24929352 3610 enum pipe pipe = 0;
f0947c37 3611 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3612
f0947c37 3613 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3614}
3615
79e53945 3616static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3617 const struct drm_display_mode *mode,
79e53945
JB		 3618 struct drm_display_mode *adjusted_mode)
3619{
2c07245f 3620 struct drm_device *dev = crtc->dev;
89749350 3621
bad720ff 3622 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3623 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3624 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3625 return false;
2c07245f 3626 }
89749350 3627
f9bef081
DV		 3628 /* All interlaced capable intel hw wants timings in frames. Note though
3629 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3630 * timings, so we need to be careful not to clobber these.*/
3631 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3632 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3633
44f46b42
CW		 3634 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3635 * with a hsync front porch of 0.
3636 */
3637 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3638 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3639 return false;
3640
79e53945
JB		 3641 return true;
3642}
3643
25eb05fc
JB		 3644static int valleyview_get_display_clock_speed(struct drm_device *dev)
3645{
3646 return 400000; /* FIXME */
3647}
3648
e70236a8
JB		 3649static int i945_get_display_clock_speed(struct drm_device *dev)
3650{
3651 return 400000;
3652}
79e53945 3653
e70236a8 3654static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3655{
e70236a8
JB		 3656 return 333000;
3657}
79e53945 3658
e70236a8
JB		 3659static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3660{
3661 return 200000;
3662}
79e53945 3663
e70236a8
JB		 3664static int i915gm_get_display_clock_speed(struct drm_device *dev)
3665{
3666 u16 gcfgc = 0;
79e53945 3667
e70236a8
JB		 3668 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3669
3670 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3671 return 133000;
3672 else {
3673 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3674 case GC_DISPLAY_CLOCK_333_MHZ:
3675 return 333000;
3676 default:
3677 case GC_DISPLAY_CLOCK_190_200_MHZ:
3678 return 190000;
79e53945 3679 }
e70236a8
JB		 3680 }
3681}
3682
3683static int i865_get_display_clock_speed(struct drm_device *dev)
3684{
3685 return 266000;
3686}
3687
3688static int i855_get_display_clock_speed(struct drm_device *dev)
3689{
3690 u16 hpllcc = 0;
3691 /* Assume that the hardware is in the high speed state. This
3692 * should be the default.
3693 */
3694 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3695 case GC_CLOCK_133_200:
3696 case GC_CLOCK_100_200:
3697 return 200000;
3698 case GC_CLOCK_166_250:
3699 return 250000;
3700 case GC_CLOCK_100_133:
79e53945 3701 return 133000;
e70236a8 3702 }
79e53945 3703
e70236a8
JB		 3704 /* Shouldn't happen */
3705 return 0;
3706}
79e53945 3707
e70236a8
JB		 3708static int i830_get_display_clock_speed(struct drm_device *dev)
3709{
3710 return 133000;
79e53945
JB		 3711}
3712
2c07245f
ZW		 3713struct fdi_m_n {
3714 u32 tu;
3715 u32 gmch_m;
3716 u32 gmch_n;
3717 u32 link_m;
3718 u32 link_n;
3719};
3720
3721static void
3722fdi_reduce_ratio(u32 *num, u32 *den)
3723{
3724 while (*num > 0xffffff || *den > 0xffffff) {
3725 *num >>= 1;
3726 *den >>= 1;
3727 }
3728}
3729
2c07245f 3730static void
f2b115e6
AJ		 3731ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3732 int link_clock, struct fdi_m_n *m_n)
2c07245f 3733{
2c07245f
ZW		 3734 m_n->tu = 64; /* default size */
3735
22ed1113
CW		 3736 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3737 m_n->gmch_m = bits_per_pixel * pixel_clock;
3738 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3739 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3740
22ed1113
CW		 3741 m_n->link_m = pixel_clock;
3742 m_n->link_n = link_clock;
2c07245f
ZW		 3743 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3744}
3745
a7615030
CW		 3746static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3747{
72bbe58c
KP		 3748 if (i915_panel_use_ssc >= 0)
3749 return i915_panel_use_ssc != 0;
3750 return dev_priv->lvds_use_ssc
435793df 3751 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3752}
3753
5a354204
JB		 3754/**
3755 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3756 * @crtc: CRTC structure
3b5c78a3 3757 * @mode: requested mode
5a354204
JB		 3758 *
3759 * A pipe may be connected to one or more outputs. Based on the depth of the
3760 * attached framebuffer, choose a good color depth to use on the pipe.
3761 *
3762 * If possible, match the pipe depth to the fb depth. In some cases, this
3763 * isn't ideal, because the connected output supports a lesser or restricted
3764 * set of depths. Resolve that here:
3765 * LVDS typically supports only 6bpc, so clamp down in that case
3766 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3767 * Displays may support a restricted set as well, check EDID and clamp as
3768 * appropriate.
3b5c78a3 3769 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3770 *
3771 * RETURNS:
3772 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3773 * true if they don't match).
3774 */
3775static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 3776 struct drm_framebuffer *fb,
3b5c78a3
AJ		 3777 unsigned int *pipe_bpp,
3778 struct drm_display_mode *mode)
5a354204
JB		 3779{
3780 struct drm_device *dev = crtc->dev;
3781 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 3782 struct drm_connector *connector;
6c2b7c12 3783 struct intel_encoder *intel_encoder;
5a354204
JB		 3784 unsigned int display_bpc = UINT_MAX, bpc;
3785
3786 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 3787 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 3788
3789 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3790 unsigned int lvds_bpc;
3791
3792 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3793 LVDS_A3_POWER_UP)
3794 lvds_bpc = 8;
3795 else
3796 lvds_bpc = 6;
3797
3798 if (lvds_bpc < display_bpc) {
82820490 3799 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3800 display_bpc = lvds_bpc;
3801 }
3802 continue;
3803 }
3804
5a354204
JB		 3805 /* Not one of the known troublemakers, check the EDID */
3806 list_for_each_entry(connector, &dev->mode_config.connector_list,
3807 head) {
6c2b7c12 3808 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 3809 continue;
3810
62ac41a6
JB		 3811 /* Don't use an invalid EDID bpc value */
3812 if (connector->display_info.bpc &&
3813 connector->display_info.bpc < display_bpc) {
82820490 3814 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3815 display_bpc = connector->display_info.bpc;
3816 }
3817 }
3818
3819 /*
3820 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3821 * through, clamp it down. (Note: >12bpc will be caught below.)
3822 */
3823 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3824 if (display_bpc > 8 && display_bpc < 12) {
82820490 3825 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3826 display_bpc = 12;
3827 } else {
82820490 3828 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3829 display_bpc = 8;
3830 }
3831 }
3832 }
3833
3b5c78a3
AJ		 3834 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3835 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3836 display_bpc = 6;
3837 }
3838
5a354204
JB		 3839 /*
3840 * We could just drive the pipe at the highest bpc all the time and
3841 * enable dithering as needed, but that costs bandwidth. So choose
3842 * the minimum value that expresses the full color range of the fb but
3843 * also stays within the max display bpc discovered above.
3844 */
3845
94352cf9 3846 switch (fb->depth) {
5a354204
JB		 3847 case 8:
3848 bpc = 8; /* since we go through a colormap */
3849 break;
3850 case 15:
3851 case 16:
3852 bpc = 6; /* min is 18bpp */
3853 break;
3854 case 24:
578393cd 3855 bpc = 8;
5a354204
JB		 3856 break;
3857 case 30:
578393cd 3858 bpc = 10;
5a354204
JB		 3859 break;
3860 case 48:
578393cd 3861 bpc = 12;
5a354204
JB		 3862 break;
3863 default:
3864 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3865 bpc = min((unsigned int)8, display_bpc);
3866 break;
3867 }
3868
578393cd
KP		 3869 display_bpc = min(display_bpc, bpc);
3870
82820490
AJ		 3871 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3872 bpc, display_bpc);
5a354204 3873
578393cd 3874 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3875
3876 return display_bpc != bpc;
3877}
3878
a0c4da24
JB		 3879static int vlv_get_refclk(struct drm_crtc *crtc)
3880{
3881 struct drm_device *dev = crtc->dev;
3882 struct drm_i915_private *dev_priv = dev->dev_private;
3883 int refclk = 27000; /* for DP & HDMI */
3884
3885 return 100000; /* only one validated so far */
3886
3887 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3888 refclk = 96000;
3889 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3890 if (intel_panel_use_ssc(dev_priv))
3891 refclk = 100000;
3892 else
3893 refclk = 96000;
3894 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3895 refclk = 100000;
3896 }
3897
3898 return refclk;
3899}
3900
c65d77d8
JB		 3901static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3902{
3903 struct drm_device *dev = crtc->dev;
3904 struct drm_i915_private *dev_priv = dev->dev_private;
3905 int refclk;
3906
a0c4da24
JB		 3907 if (IS_VALLEYVIEW(dev)) {
3908 refclk = vlv_get_refclk(crtc);
3909 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 3910 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3911 refclk = dev_priv->lvds_ssc_freq * 1000;
3912 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3913 refclk / 1000);
3914 } else if (!IS_GEN2(dev)) {
3915 refclk = 96000;
3916 } else {
3917 refclk = 48000;
3918 }
3919
3920 return refclk;
3921}
3922
3923static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3924 intel_clock_t *clock)
3925{
3926 /* SDVO TV has fixed PLL values depend on its clock range,
3927 this mirrors vbios setting. */
3928 if (adjusted_mode->clock >= 100000
3929 && adjusted_mode->clock < 140500) {
3930 clock->p1 = 2;
3931 clock->p2 = 10;
3932 clock->n = 3;
3933 clock->m1 = 16;
3934 clock->m2 = 8;
3935 } else if (adjusted_mode->clock >= 140500
3936 && adjusted_mode->clock <= 200000) {
3937 clock->p1 = 1;
3938 clock->p2 = 10;
3939 clock->n = 6;
3940 clock->m1 = 12;
3941 clock->m2 = 8;
3942 }
3943}
3944
a7516a05
JB		 3945static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3946 intel_clock_t *clock,
3947 intel_clock_t *reduced_clock)
3948{
3949 struct drm_device *dev = crtc->dev;
3950 struct drm_i915_private *dev_priv = dev->dev_private;
3951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3952 int pipe = intel_crtc->pipe;
3953 u32 fp, fp2 = 0;
3954
3955 if (IS_PINEVIEW(dev)) {
3956 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3957 if (reduced_clock)
3958 fp2 = (1 << reduced_clock->n) << 16 |
3959 reduced_clock->m1 << 8 | reduced_clock->m2;
3960 } else {
3961 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3962 if (reduced_clock)
3963 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3964 reduced_clock->m2;
3965 }
3966
3967 I915_WRITE(FP0(pipe), fp);
3968
3969 intel_crtc->lowfreq_avail = false;
3970 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3971 reduced_clock && i915_powersave) {
3972 I915_WRITE(FP1(pipe), fp2);
3973 intel_crtc->lowfreq_avail = true;
3974 } else {
3975 I915_WRITE(FP1(pipe), fp);
3976 }
3977}
3978
93e537a1
DV		 3979static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3980 struct drm_display_mode *adjusted_mode)
3981{
3982 struct drm_device *dev = crtc->dev;
3983 struct drm_i915_private *dev_priv = dev->dev_private;
3984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3985 int pipe = intel_crtc->pipe;
284d5df5 3986 u32 temp;
93e537a1
DV		 3987
3988 temp = I915_READ(LVDS);
3989 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3990 if (pipe == 1) {
3991 temp |= LVDS_PIPEB_SELECT;
3992 } else {
3993 temp &= ~LVDS_PIPEB_SELECT;
3994 }
3995 /* set the corresponsding LVDS_BORDER bit */
3996 temp |= dev_priv->lvds_border_bits;
3997 /* Set the B0-B3 data pairs corresponding to whether we're going to
3998 * set the DPLLs for dual-channel mode or not.
3999 */
4000 if (clock->p2 == 7)
4001 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4002 else
4003 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4004
4005 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4006 * appropriately here, but we need to look more thoroughly into how
4007 * panels behave in the two modes.
4008 */
4009 /* set the dithering flag on LVDS as needed */
4010 if (INTEL_INFO(dev)->gen >= 4) {
4011 if (dev_priv->lvds_dither)
4012 temp |= LVDS_ENABLE_DITHER;
4013 else
4014 temp &= ~LVDS_ENABLE_DITHER;
4015 }
284d5df5 4016 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4017 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4018 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4019 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4020 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4021 I915_WRITE(LVDS, temp);
4022}
4023
a0c4da24
JB		 4024static void vlv_update_pll(struct drm_crtc *crtc,
4025 struct drm_display_mode *mode,
4026 struct drm_display_mode *adjusted_mode,
4027 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4028 int num_connectors)
a0c4da24
JB		 4029{
4030 struct drm_device *dev = crtc->dev;
4031 struct drm_i915_private *dev_priv = dev->dev_private;
4032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4033 int pipe = intel_crtc->pipe;
4034 u32 dpll, mdiv, pdiv;
4035 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4036 bool is_sdvo;
4037 u32 temp;
4038
4039 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4040 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4041
2a8f64ca
VP		 4042 dpll = DPLL_VGA_MODE_DIS;
4043 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4044 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4045 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4046
4047 I915_WRITE(DPLL(pipe), dpll);
4048 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4049
4050 bestn = clock->n;
4051 bestm1 = clock->m1;
4052 bestm2 = clock->m2;
4053 bestp1 = clock->p1;
4054 bestp2 = clock->p2;
4055
2a8f64ca
VP		 4056 /*
4057 * In Valleyview PLL and program lane counter registers are exposed
4058 * through DPIO interface
4059 */
a0c4da24
JB		 4060 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4061 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4062 mdiv |= ((bestn << DPIO_N_SHIFT));
4063 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4064 mdiv |= (1 << DPIO_K_SHIFT);
4065 mdiv |= DPIO_ENABLE_CALIBRATION;
4066 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4067
4068 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4069
2a8f64ca 4070 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4071 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4072 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4073 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4074 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4075
2a8f64ca 4076 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4077
4078 dpll |= DPLL_VCO_ENABLE;
4079 I915_WRITE(DPLL(pipe), dpll);
4080 POSTING_READ(DPLL(pipe));
4081 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4082 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4083
2a8f64ca
VP		 4084 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4085
4086 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4087 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4088
4089 I915_WRITE(DPLL(pipe), dpll);
4090
4091 /* Wait for the clocks to stabilize. */
4092 POSTING_READ(DPLL(pipe));
4093 udelay(150);
a0c4da24 4094
2a8f64ca
VP		 4095 temp = 0;
4096 if (is_sdvo) {
4097 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4098 if (temp > 1)
4099 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4100 else
4101 temp = 0;
a0c4da24 4102 }
2a8f64ca
VP		 4103 I915_WRITE(DPLL_MD(pipe), temp);
4104 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4105
2a8f64ca
VP		 4106 /* Now program lane control registers */
4107 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4108 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4109 {
4110 temp = 0x1000C4;
4111 if(pipe == 1)
4112 temp |= (1 << 21);
4113 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4114 }
4115 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4116 {
4117 temp = 0x1000C4;
4118 if(pipe == 1)
4119 temp |= (1 << 21);
4120 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4121 }
a0c4da24
JB		 4122}
4123
eb1cbe48
DV		 4124static void i9xx_update_pll(struct drm_crtc *crtc,
4125 struct drm_display_mode *mode,
4126 struct drm_display_mode *adjusted_mode,
4127 intel_clock_t *clock, intel_clock_t *reduced_clock,
4128 int num_connectors)
4129{
4130 struct drm_device *dev = crtc->dev;
4131 struct drm_i915_private *dev_priv = dev->dev_private;
4132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4133 int pipe = intel_crtc->pipe;
4134 u32 dpll;
4135 bool is_sdvo;
4136
2a8f64ca
VP		 4137 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4138
eb1cbe48
DV		 4139 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4140 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4141
4142 dpll = DPLL_VGA_MODE_DIS;
4143
4144 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4145 dpll |= DPLLB_MODE_LVDS;
4146 else
4147 dpll |= DPLLB_MODE_DAC_SERIAL;
4148 if (is_sdvo) {
4149 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4150 if (pixel_multiplier > 1) {
4151 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4152 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4153 }
4154 dpll |= DPLL_DVO_HIGH_SPEED;
4155 }
4156 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4157 dpll |= DPLL_DVO_HIGH_SPEED;
4158
4159 /* compute bitmask from p1 value */
4160 if (IS_PINEVIEW(dev))
4161 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4162 else {
4163 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4164 if (IS_G4X(dev) && reduced_clock)
4165 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4166 }
4167 switch (clock->p2) {
4168 case 5:
4169 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4170 break;
4171 case 7:
4172 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4173 break;
4174 case 10:
4175 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4176 break;
4177 case 14:
4178 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4179 break;
4180 }
4181 if (INTEL_INFO(dev)->gen >= 4)
4182 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4183
4184 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4185 dpll |= PLL_REF_INPUT_TVCLKINBC;
4186 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4187 /* XXX: just matching BIOS for now */
4188 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4189 dpll |= 3;
4190 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4191 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4192 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4193 else
4194 dpll |= PLL_REF_INPUT_DREFCLK;
4195
4196 dpll |= DPLL_VCO_ENABLE;
4197 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4198 POSTING_READ(DPLL(pipe));
4199 udelay(150);
4200
4201 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4202 * This is an exception to the general rule that mode_set doesn't turn
4203 * things on.
4204 */
4205 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4206 intel_update_lvds(crtc, clock, adjusted_mode);
4207
4208 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4209 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4210
4211 I915_WRITE(DPLL(pipe), dpll);
4212
4213 /* Wait for the clocks to stabilize. */
4214 POSTING_READ(DPLL(pipe));
4215 udelay(150);
4216
4217 if (INTEL_INFO(dev)->gen >= 4) {
4218 u32 temp = 0;
4219 if (is_sdvo) {
4220 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4221 if (temp > 1)
4222 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4223 else
4224 temp = 0;
4225 }
4226 I915_WRITE(DPLL_MD(pipe), temp);
4227 } else {
4228 /* The pixel multiplier can only be updated once the
4229 * DPLL is enabled and the clocks are stable.
4230 *
4231 * So write it again.
4232 */
4233 I915_WRITE(DPLL(pipe), dpll);
4234 }
4235}
4236
4237static void i8xx_update_pll(struct drm_crtc *crtc,
4238 struct drm_display_mode *adjusted_mode,
2a8f64ca 4239 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4240 int num_connectors)
4241{
4242 struct drm_device *dev = crtc->dev;
4243 struct drm_i915_private *dev_priv = dev->dev_private;
4244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4245 int pipe = intel_crtc->pipe;
4246 u32 dpll;
4247
2a8f64ca
VP		 4248 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4249
eb1cbe48
DV		 4250 dpll = DPLL_VGA_MODE_DIS;
4251
4252 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4253 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4254 } else {
4255 if (clock->p1 == 2)
4256 dpll |= PLL_P1_DIVIDE_BY_TWO;
4257 else
4258 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4259 if (clock->p2 == 4)
4260 dpll |= PLL_P2_DIVIDE_BY_4;
4261 }
4262
4263 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4264 /* XXX: just matching BIOS for now */
4265 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4266 dpll |= 3;
4267 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4268 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4269 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4270 else
4271 dpll |= PLL_REF_INPUT_DREFCLK;
4272
4273 dpll |= DPLL_VCO_ENABLE;
4274 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4275 POSTING_READ(DPLL(pipe));
4276 udelay(150);
4277
eb1cbe48
DV		 4278 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4279 * This is an exception to the general rule that mode_set doesn't turn
4280 * things on.
4281 */
4282 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4283 intel_update_lvds(crtc, clock, adjusted_mode);
4284
5b5896e4
DV		 4285 I915_WRITE(DPLL(pipe), dpll);
4286
4287 /* Wait for the clocks to stabilize. */
4288 POSTING_READ(DPLL(pipe));
4289 udelay(150);
4290
eb1cbe48
DV		 4291 /* The pixel multiplier can only be updated once the
4292 * DPLL is enabled and the clocks are stable.
4293 *
4294 * So write it again.
4295 */
4296 I915_WRITE(DPLL(pipe), dpll);
4297}
4298
b0e77b9c
PZ		 4299static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4300 struct drm_display_mode *mode,
4301 struct drm_display_mode *adjusted_mode)
4302{
4303 struct drm_device *dev = intel_crtc->base.dev;
4304 struct drm_i915_private *dev_priv = dev->dev_private;
4305 enum pipe pipe = intel_crtc->pipe;
4306 uint32_t vsyncshift;
4307
4308 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4309 /* the chip adds 2 halflines automatically */
4310 adjusted_mode->crtc_vtotal -= 1;
4311 adjusted_mode->crtc_vblank_end -= 1;
4312 vsyncshift = adjusted_mode->crtc_hsync_start
4313 - adjusted_mode->crtc_htotal / 2;
4314 } else {
4315 vsyncshift = 0;
4316 }
4317
4318 if (INTEL_INFO(dev)->gen > 3)
4319 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4320
4321 I915_WRITE(HTOTAL(pipe),
4322 (adjusted_mode->crtc_hdisplay - 1) |
4323 ((adjusted_mode->crtc_htotal - 1) << 16));
4324 I915_WRITE(HBLANK(pipe),
4325 (adjusted_mode->crtc_hblank_start - 1) |
4326 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4327 I915_WRITE(HSYNC(pipe),
4328 (adjusted_mode->crtc_hsync_start - 1) |
4329 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4330
4331 I915_WRITE(VTOTAL(pipe),
4332 (adjusted_mode->crtc_vdisplay - 1) |
4333 ((adjusted_mode->crtc_vtotal - 1) << 16));
4334 I915_WRITE(VBLANK(pipe),
4335 (adjusted_mode->crtc_vblank_start - 1) |
4336 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4337 I915_WRITE(VSYNC(pipe),
4338 (adjusted_mode->crtc_vsync_start - 1) |
4339 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4340
4341 /* pipesrc controls the size that is scaled from, which should
4342 * always be the user's requested size.
4343 */
4344 I915_WRITE(PIPESRC(pipe),
4345 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4346}
4347
f564048e
EA		 4348static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4349 struct drm_display_mode *mode,
4350 struct drm_display_mode *adjusted_mode,
4351 int x, int y,
94352cf9 4352 struct drm_framebuffer *fb)
79e53945
JB		 4353{
4354 struct drm_device *dev = crtc->dev;
4355 struct drm_i915_private *dev_priv = dev->dev_private;
4356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4357 int pipe = intel_crtc->pipe;
80824003 4358 int plane = intel_crtc->plane;
c751ce4f 4359 int refclk, num_connectors = 0;
652c393a 4360 intel_clock_t clock, reduced_clock;
b0e77b9c 4361 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4362 bool ok, has_reduced_clock = false, is_sdvo = false;
4363 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4364 struct intel_encoder *encoder;
d4906093 4365 const intel_limit_t *limit;
5c3b82e2 4366 int ret;
79e53945 4367
6c2b7c12 4368 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4369 switch (encoder->type) {
79e53945
JB		 4370 case INTEL_OUTPUT_LVDS:
4371 is_lvds = true;
4372 break;
4373 case INTEL_OUTPUT_SDVO:
7d57382e 4374 case INTEL_OUTPUT_HDMI:
79e53945 4375 is_sdvo = true;
5eddb70b 4376 if (encoder->needs_tv_clock)
e2f0ba97 4377 is_tv = true;
79e53945 4378 break;
79e53945
JB		 4379 case INTEL_OUTPUT_TVOUT:
4380 is_tv = true;
4381 break;
a4fc5ed6
KP		 4382 case INTEL_OUTPUT_DISPLAYPORT:
4383 is_dp = true;
4384 break;
79e53945 4385 }
43565a06 4386
c751ce4f 4387 num_connectors++;
79e53945
JB		 4388 }
4389
c65d77d8 4390 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4391
d4906093
ML		 4392 /*
4393 * Returns a set of divisors for the desired target clock with the given
4394 * refclk, or FALSE. The returned values represent the clock equation:
4395 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4396 */
1b894b59 4397 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4398 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4399 &clock);
79e53945
JB		 4400 if (!ok) {
4401 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4402 return -EINVAL;
79e53945
JB		 4403 }
4404
cda4b7d3 4405 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4406 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4407
ddc9003c 4408 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4409 /*
4410 * Ensure we match the reduced clock's P to the target clock.
4411 * If the clocks don't match, we can't switch the display clock
4412 * by using the FP0/FP1. In such case we will disable the LVDS
4413 * downclock feature.
4414 */
ddc9003c 4415 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4416 dev_priv->lvds_downclock,
4417 refclk,
cec2f356 4418 &clock,
5eddb70b 4419 &reduced_clock);
7026d4ac
ZW		 4420 }
4421
c65d77d8
JB		 4422 if (is_sdvo && is_tv)
4423 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4424
eb1cbe48 4425 if (IS_GEN2(dev))
2a8f64ca
VP		 4426 i8xx_update_pll(crtc, adjusted_mode, &clock,
4427 has_reduced_clock ? &reduced_clock : NULL,
4428 num_connectors);
a0c4da24 4429 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4430 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4431 has_reduced_clock ? &reduced_clock : NULL,
4432 num_connectors);
79e53945 4433 else
eb1cbe48
DV		 4434 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4435 has_reduced_clock ? &reduced_clock : NULL,
4436 num_connectors);
79e53945
JB		 4437
4438 /* setup pipeconf */
5eddb70b 4439 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4440
4441 /* Set up the display plane register */
4442 dspcntr = DISPPLANE_GAMMA_ENABLE;
4443
929c77fb
EA		 4444 if (pipe == 0)
4445 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4446 else
4447 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4448
a6c45cf0 4449 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4450 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4451 * core speed.
4452 *
4453 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4454 * pipe == 0 check?
4455 */
e70236a8
JB		 4456 if (mode->clock >
4457 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4458 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4459 else
5eddb70b 4460 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4461 }
4462
3b5c78a3
AJ		 4463 /* default to 8bpc */
4464 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4465 if (is_dp) {
4466 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4467 pipeconf |= PIPECONF_BPP_6 |
4468 PIPECONF_DITHER_EN |
4469 PIPECONF_DITHER_TYPE_SP;
4470 }
4471 }
4472
19c03924
GB		 4473 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4474 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4475 pipeconf |= PIPECONF_BPP_6 |
4476 PIPECONF_ENABLE |
4477 I965_PIPECONF_ACTIVE;
4478 }
4479 }
4480
28c97730 4481 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4482 drm_mode_debug_printmodeline(mode);
4483
a7516a05
JB		 4484 if (HAS_PIPE_CXSR(dev)) {
4485 if (intel_crtc->lowfreq_avail) {
28c97730 4486 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4487 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4488 } else {
28c97730 4489 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4490 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4491 }
4492 }
4493
617cf884 4494 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4495 if (!IS_GEN2(dev) &&
b0e77b9c 4496 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4497 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4498 else
617cf884 4499 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4500
b0e77b9c 4501 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4502
4503 /* pipesrc and dspsize control the size that is scaled from,
4504 * which should always be the user's requested size.
79e53945 4505 */
929c77fb
EA		 4506 I915_WRITE(DSPSIZE(plane),
4507 ((mode->vdisplay - 1) << 16) |
4508 (mode->hdisplay - 1));
4509 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4510
f564048e
EA		 4511 I915_WRITE(PIPECONF(pipe), pipeconf);
4512 POSTING_READ(PIPECONF(pipe));
929c77fb 4513 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4514
4515 intel_wait_for_vblank(dev, pipe);
4516
f564048e
EA		 4517 I915_WRITE(DSPCNTR(plane), dspcntr);
4518 POSTING_READ(DSPCNTR(plane));
4519
94352cf9 4520 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4521
4522 intel_update_watermarks(dev);
4523
f564048e
EA		 4524 return ret;
4525}
4526
9fb526db
KP		 4527/*
4528 * Initialize reference clocks when the driver loads
4529 */
4530void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4531{
4532 struct drm_i915_private *dev_priv = dev->dev_private;
4533 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4534 struct intel_encoder *encoder;
13d83a67
JB		 4535 u32 temp;
4536 bool has_lvds = false;
199e5d79
KP		 4537 bool has_cpu_edp = false;
4538 bool has_pch_edp = false;
4539 bool has_panel = false;
99eb6a01
KP		 4540 bool has_ck505 = false;
4541 bool can_ssc = false;
13d83a67
JB		 4542
4543 /* We need to take the global config into account */
199e5d79
KP		 4544 list_for_each_entry(encoder, &mode_config->encoder_list,
4545 base.head) {
4546 switch (encoder->type) {
4547 case INTEL_OUTPUT_LVDS:
4548 has_panel = true;
4549 has_lvds = true;
4550 break;
4551 case INTEL_OUTPUT_EDP:
4552 has_panel = true;
4553 if (intel_encoder_is_pch_edp(&encoder->base))
4554 has_pch_edp = true;
4555 else
4556 has_cpu_edp = true;
4557 break;
13d83a67
JB		 4558 }
4559 }
4560
99eb6a01
KP		 4561 if (HAS_PCH_IBX(dev)) {
4562 has_ck505 = dev_priv->display_clock_mode;
4563 can_ssc = has_ck505;
4564 } else {
4565 has_ck505 = false;
4566 can_ssc = true;
4567 }
4568
4569 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4570 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4571 has_ck505);
13d83a67
JB		 4572
4573 /* Ironlake: try to setup display ref clock before DPLL
4574 * enabling. This is only under driver's control after
4575 * PCH B stepping, previous chipset stepping should be
4576 * ignoring this setting.
4577 */
4578 temp = I915_READ(PCH_DREF_CONTROL);
4579 /* Always enable nonspread source */
4580 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4581
99eb6a01
KP		 4582 if (has_ck505)
4583 temp |= DREF_NONSPREAD_CK505_ENABLE;
4584 else
4585 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4586
199e5d79
KP		 4587 if (has_panel) {
4588 temp &= ~DREF_SSC_SOURCE_MASK;
4589 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4590
199e5d79 4591 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4592 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4593 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4594 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4595 } else
4596 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4597
4598 /* Get SSC going before enabling the outputs */
4599 I915_WRITE(PCH_DREF_CONTROL, temp);
4600 POSTING_READ(PCH_DREF_CONTROL);
4601 udelay(200);
4602
13d83a67
JB		 4603 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4604
4605 /* Enable CPU source on CPU attached eDP */
199e5d79 4606 if (has_cpu_edp) {
99eb6a01 4607 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4608 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4609 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4610 }
13d83a67
JB		 4611 else
4612 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4613 } else
4614 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4615
4616 I915_WRITE(PCH_DREF_CONTROL, temp);
4617 POSTING_READ(PCH_DREF_CONTROL);
4618 udelay(200);
4619 } else {
4620 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4621
4622 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4623
4624 /* Turn off CPU output */
4625 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4626
4627 I915_WRITE(PCH_DREF_CONTROL, temp);
4628 POSTING_READ(PCH_DREF_CONTROL);
4629 udelay(200);
4630
4631 /* Turn off the SSC source */
4632 temp &= ~DREF_SSC_SOURCE_MASK;
4633 temp |= DREF_SSC_SOURCE_DISABLE;
4634
4635 /* Turn off SSC1 */
4636 temp &= ~ DREF_SSC1_ENABLE;
4637
13d83a67
JB		 4638 I915_WRITE(PCH_DREF_CONTROL, temp);
4639 POSTING_READ(PCH_DREF_CONTROL);
4640 udelay(200);
4641 }
4642}
4643
d9d444cb
JB		 4644static int ironlake_get_refclk(struct drm_crtc *crtc)
4645{
4646 struct drm_device *dev = crtc->dev;
4647 struct drm_i915_private *dev_priv = dev->dev_private;
4648 struct intel_encoder *encoder;
d9d444cb
JB		 4649 struct intel_encoder *edp_encoder = NULL;
4650 int num_connectors = 0;
4651 bool is_lvds = false;
4652
6c2b7c12 4653 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4654 switch (encoder->type) {
4655 case INTEL_OUTPUT_LVDS:
4656 is_lvds = true;
4657 break;
4658 case INTEL_OUTPUT_EDP:
4659 edp_encoder = encoder;
4660 break;
4661 }
4662 num_connectors++;
4663 }
4664
4665 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4666 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4667 dev_priv->lvds_ssc_freq);
4668 return dev_priv->lvds_ssc_freq * 1000;
4669 }
4670
4671 return 120000;
4672}
4673
c8203565
PZ		 4674static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4675 struct drm_display_mode *adjusted_mode,
4676 bool dither)
4677{
4678 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4680 int pipe = intel_crtc->pipe;
4681 uint32_t val;
4682
4683 val = I915_READ(PIPECONF(pipe));
4684
4685 val &= ~PIPE_BPC_MASK;
4686 switch (intel_crtc->bpp) {
4687 case 18:
4688 val |= PIPE_6BPC;
4689 break;
4690 case 24:
4691 val |= PIPE_8BPC;
4692 break;
4693 case 30:
4694 val |= PIPE_10BPC;
4695 break;
4696 case 36:
4697 val |= PIPE_12BPC;
4698 break;
4699 default:
cc769b62
PZ		 4700 /* Case prevented by intel_choose_pipe_bpp_dither. */
4701 BUG();
c8203565
PZ		 4702 }
4703
4704 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4705 if (dither)
4706 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4707
4708 val &= ~PIPECONF_INTERLACE_MASK;
4709 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4710 val |= PIPECONF_INTERLACED_ILK;
4711 else
4712 val |= PIPECONF_PROGRESSIVE;
4713
4714 I915_WRITE(PIPECONF(pipe), val);
4715 POSTING_READ(PIPECONF(pipe));
4716}
4717
6591c6e4
PZ		 4718static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4719 struct drm_display_mode *adjusted_mode,
4720 intel_clock_t *clock,
4721 bool *has_reduced_clock,
4722 intel_clock_t *reduced_clock)
4723{
4724 struct drm_device *dev = crtc->dev;
4725 struct drm_i915_private *dev_priv = dev->dev_private;
4726 struct intel_encoder *intel_encoder;
4727 int refclk;
4728 const intel_limit_t *limit;
4729 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4730
4731 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4732 switch (intel_encoder->type) {
4733 case INTEL_OUTPUT_LVDS:
4734 is_lvds = true;
4735 break;
4736 case INTEL_OUTPUT_SDVO:
4737 case INTEL_OUTPUT_HDMI:
4738 is_sdvo = true;
4739 if (intel_encoder->needs_tv_clock)
4740 is_tv = true;
4741 break;
4742 case INTEL_OUTPUT_TVOUT:
4743 is_tv = true;
4744 break;
4745 }
4746 }
4747
4748 refclk = ironlake_get_refclk(crtc);
4749
4750 /*
4751 * Returns a set of divisors for the desired target clock with the given
4752 * refclk, or FALSE. The returned values represent the clock equation:
4753 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4754 */
4755 limit = intel_limit(crtc, refclk);
4756 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4757 clock);
4758 if (!ret)
4759 return false;
4760
4761 if (is_lvds && dev_priv->lvds_downclock_avail) {
4762 /*
4763 * Ensure we match the reduced clock's P to the target clock.
4764 * If the clocks don't match, we can't switch the display clock
4765 * by using the FP0/FP1. In such case we will disable the LVDS
4766 * downclock feature.
4767 */
4768 *has_reduced_clock = limit->find_pll(limit, crtc,
4769 dev_priv->lvds_downclock,
4770 refclk,
4771 clock,
4772 reduced_clock);
4773 }
4774
4775 if (is_sdvo && is_tv)
4776 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4777
4778 return true;
4779}
4780
f48d8f23
PZ		 4781static void ironlake_set_m_n(struct drm_crtc *crtc,
4782 struct drm_display_mode *mode,
4783 struct drm_display_mode *adjusted_mode)
4784{
4785 struct drm_device *dev = crtc->dev;
4786 struct drm_i915_private *dev_priv = dev->dev_private;
4787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4788 enum pipe pipe = intel_crtc->pipe;
4789 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
4790 struct fdi_m_n m_n = {0};
4791 int target_clock, pixel_multiplier, lane, link_bw;
4792 bool is_dp = false, is_cpu_edp = false;
4793
4794 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4795 switch (intel_encoder->type) {
4796 case INTEL_OUTPUT_DISPLAYPORT:
4797 is_dp = true;
4798 break;
4799 case INTEL_OUTPUT_EDP:
4800 is_dp = true;
4801 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4802 is_cpu_edp = true;
4803 edp_encoder = intel_encoder;
4804 break;
4805 }
4806 }
4807
4808 /* FDI link */
4809 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4810 lane = 0;
4811 /* CPU eDP doesn't require FDI link, so just set DP M/N
4812 according to current link config */
4813 if (is_cpu_edp) {
4814 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4815 } else {
4816 /* FDI is a binary signal running at ~2.7GHz, encoding
4817 * each output octet as 10 bits. The actual frequency
4818 * is stored as a divider into a 100MHz clock, and the
4819 * mode pixel clock is stored in units of 1KHz.
4820 * Hence the bw of each lane in terms of the mode signal
4821 * is:
4822 */
4823 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4824 }
4825
4826 /* [e]DP over FDI requires target mode clock instead of link clock. */
4827 if (edp_encoder)
4828 target_clock = intel_edp_target_clock(edp_encoder, mode);
4829 else if (is_dp)
4830 target_clock = mode->clock;
4831 else
4832 target_clock = adjusted_mode->clock;
4833
4834 if (!lane) {
4835 /*
4836 * Account for spread spectrum to avoid
4837 * oversubscribing the link. Max center spread
4838 * is 2.5%; use 5% for safety's sake.
4839 */
4840 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4841 lane = bps / (link_bw * 8) + 1;
4842 }
4843
4844 intel_crtc->fdi_lanes = lane;
4845
4846 if (pixel_multiplier > 1)
4847 link_bw *= pixel_multiplier;
4848 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4849 &m_n);
4850
4851 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4852 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4853 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4854 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4855}
4856
de13a2e3
PZ		 4857static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
4858 struct drm_display_mode *adjusted_mode,
4859 intel_clock_t *clock, u32 fp)
79e53945 4860{
de13a2e3 4861 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 4862 struct drm_device *dev = crtc->dev;
4863 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 4864 struct intel_encoder *intel_encoder;
4865 uint32_t dpll;
4866 int factor, pixel_multiplier, num_connectors = 0;
4867 bool is_lvds = false, is_sdvo = false, is_tv = false;
4868 bool is_dp = false, is_cpu_edp = false;
79e53945 4869
de13a2e3
PZ		 4870 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4871 switch (intel_encoder->type) {
79e53945
JB		 4872 case INTEL_OUTPUT_LVDS:
4873 is_lvds = true;
4874 break;
4875 case INTEL_OUTPUT_SDVO:
7d57382e 4876 case INTEL_OUTPUT_HDMI:
79e53945 4877 is_sdvo = true;
de13a2e3 4878 if (intel_encoder->needs_tv_clock)
e2f0ba97 4879 is_tv = true;
79e53945 4880 break;
79e53945
JB		 4881 case INTEL_OUTPUT_TVOUT:
4882 is_tv = true;
4883 break;
a4fc5ed6
KP		 4884 case INTEL_OUTPUT_DISPLAYPORT:
4885 is_dp = true;
4886 break;
32f9d658 4887 case INTEL_OUTPUT_EDP:
e3aef172 4888 is_dp = true;
de13a2e3 4889 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 4890 is_cpu_edp = true;
32f9d658 4891 break;
79e53945 4892 }
43565a06 4893
c751ce4f 4894 num_connectors++;
79e53945
JB		 4895 }
4896
c1858123 4897 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4898 factor = 21;
4899 if (is_lvds) {
4900 if ((intel_panel_use_ssc(dev_priv) &&
4901 dev_priv->lvds_ssc_freq == 100) ||
4902 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4903 factor = 25;
4904 } else if (is_sdvo && is_tv)
4905 factor = 20;
c1858123 4906
de13a2e3 4907 if (clock->m < factor * clock->n)
8febb297 4908 fp |= FP_CB_TUNE;
2c07245f 4909
5eddb70b 4910 dpll = 0;
2c07245f 4911
a07d6787
EA		 4912 if (is_lvds)
4913 dpll |= DPLLB_MODE_LVDS;
4914 else
4915 dpll |= DPLLB_MODE_DAC_SERIAL;
4916 if (is_sdvo) {
de13a2e3 4917 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 4918 if (pixel_multiplier > 1) {
4919 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4920 }
a07d6787
EA		 4921 dpll |= DPLL_DVO_HIGH_SPEED;
4922 }
e3aef172 4923 if (is_dp && !is_cpu_edp)
a07d6787 4924 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4925
a07d6787 4926 /* compute bitmask from p1 value */
de13a2e3 4927 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 4928 /* also FPA1 */
de13a2e3 4929 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 4930
de13a2e3 4931 switch (clock->p2) {
a07d6787
EA		 4932 case 5:
4933 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4934 break;
4935 case 7:
4936 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4937 break;
4938 case 10:
4939 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4940 break;
4941 case 14:
4942 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4943 break;
79e53945
JB		 4944 }
4945
43565a06
KH		 4946 if (is_sdvo && is_tv)
4947 dpll |= PLL_REF_INPUT_TVCLKINBC;
4948 else if (is_tv)
79e53945 4949 /* XXX: just matching BIOS for now */
43565a06 4950 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4951 dpll |= 3;
a7615030 4952 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4953 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4954 else
4955 dpll |= PLL_REF_INPUT_DREFCLK;
4956
de13a2e3
PZ		 4957 return dpll;
4958}
4959
4960static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4961 struct drm_display_mode *mode,
4962 struct drm_display_mode *adjusted_mode,
4963 int x, int y,
4964 struct drm_framebuffer *fb)
4965{
4966 struct drm_device *dev = crtc->dev;
4967 struct drm_i915_private *dev_priv = dev->dev_private;
4968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4969 int pipe = intel_crtc->pipe;
4970 int plane = intel_crtc->plane;
4971 int num_connectors = 0;
4972 intel_clock_t clock, reduced_clock;
4973 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 4974 bool ok, has_reduced_clock = false;
4975 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 4976 struct intel_encoder *encoder;
4977 u32 temp;
4978 int ret;
4979 bool dither;
de13a2e3
PZ		 4980
4981 for_each_encoder_on_crtc(dev, crtc, encoder) {
4982 switch (encoder->type) {
4983 case INTEL_OUTPUT_LVDS:
4984 is_lvds = true;
4985 break;
de13a2e3
PZ		 4986 case INTEL_OUTPUT_DISPLAYPORT:
4987 is_dp = true;
4988 break;
4989 case INTEL_OUTPUT_EDP:
4990 is_dp = true;
e2f12b07 4991 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 4992 is_cpu_edp = true;
4993 break;
4994 }
4995
4996 num_connectors++;
4997 }
4998
4999 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5000 &has_reduced_clock, &reduced_clock);
5001 if (!ok) {
5002 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5003 return -EINVAL;
5004 }
5005
5006 /* Ensure that the cursor is valid for the new mode before changing... */
5007 intel_crtc_update_cursor(crtc, true);
5008
5009 /* determine panel color depth */
5010 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5011 if (is_lvds && dev_priv->lvds_dither)
5012 dither = true;
5013
5014 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5015 if (has_reduced_clock)
5016 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5017 reduced_clock.m2;
5018
5019 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5020
f7cb34d4 5021 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5022 drm_mode_debug_printmodeline(mode);
5023
9d82aa17
ED		 5024 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
5025 * pre-Haswell/LPT generation */
5026 if (HAS_PCH_LPT(dev)) {
5027 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
5028 pipe);
5029 } else if (!is_cpu_edp) {
ee7b9f93 5030 struct intel_pch_pll *pll;
4b645f14 5031
ee7b9f93
JB		 5032 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5033 if (pll == NULL) {
5034 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5035 pipe);
4b645f14
JB		 5036 return -EINVAL;
5037 }
ee7b9f93
JB		 5038 } else
5039 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5040
5041 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5042 * This is an exception to the general rule that mode_set doesn't turn
5043 * things on.
5044 */
5045 if (is_lvds) {
fae14981 5046 temp = I915_READ(PCH_LVDS);
5eddb70b 5047 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5048 if (HAS_PCH_CPT(dev)) {
5049 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5050 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5051 } else {
5052 if (pipe == 1)
5053 temp |= LVDS_PIPEB_SELECT;
5054 else
5055 temp &= ~LVDS_PIPEB_SELECT;
5056 }
4b645f14 5057
a3e17eb8 5058 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5059 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5060 /* Set the B0-B3 data pairs corresponding to whether we're going to
5061 * set the DPLLs for dual-channel mode or not.
5062 */
5063 if (clock.p2 == 7)
5eddb70b 5064 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5065 else
5eddb70b 5066 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5067
5068 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5069 * appropriately here, but we need to look more thoroughly into how
5070 * panels behave in the two modes.
5071 */
284d5df5 5072 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5073 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5074 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5075 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5076 temp |= LVDS_VSYNC_POLARITY;
fae14981 5077 I915_WRITE(PCH_LVDS, temp);
79e53945 5078 }
434ed097 5079
e3aef172 5080 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5081 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5082 } else {
8db9d77b 5083 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5084 I915_WRITE(TRANSDATA_M1(pipe), 0);
5085 I915_WRITE(TRANSDATA_N1(pipe), 0);
5086 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5087 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5088 }
79e53945 5089
ee7b9f93
JB		 5090 if (intel_crtc->pch_pll) {
5091 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5092
32f9d658 5093 /* Wait for the clocks to stabilize. */
ee7b9f93 5094 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5095 udelay(150);
5096
8febb297
EA		 5097 /* The pixel multiplier can only be updated once the
5098 * DPLL is enabled and the clocks are stable.
5099 *
5100 * So write it again.
5101 */
ee7b9f93 5102 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5103 }
79e53945 5104
5eddb70b 5105 intel_crtc->lowfreq_avail = false;
ee7b9f93 5106 if (intel_crtc->pch_pll) {
4b645f14 5107 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5108 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5109 intel_crtc->lowfreq_avail = true;
4b645f14 5110 } else {
ee7b9f93 5111 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5112 }
5113 }
5114
b0e77b9c 5115 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
2c07245f 5116
f48d8f23 5117 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5118
e3aef172 5119 if (is_cpu_edp)
8febb297 5120 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5121
c8203565 5122 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5123
9d0498a2 5124 intel_wait_for_vblank(dev, pipe);
79e53945 5125
a1f9e77e
PZ		 5126 /* Set up the display plane register */
5127 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5128 POSTING_READ(DSPCNTR(plane));
79e53945 5129
94352cf9 5130 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5131
5132 intel_update_watermarks(dev);
5133
1f8eeabf
ED		 5134 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5135
1f803ee5 5136 return ret;
79e53945
JB		 5137}
5138
f564048e
EA		 5139static int intel_crtc_mode_set(struct drm_crtc *crtc,
5140 struct drm_display_mode *mode,
5141 struct drm_display_mode *adjusted_mode,
5142 int x, int y,
94352cf9 5143 struct drm_framebuffer *fb)
f564048e
EA		 5144{
5145 struct drm_device *dev = crtc->dev;
5146 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5148 int pipe = intel_crtc->pipe;
f564048e
EA		 5149 int ret;
5150
0b701d27 5151 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5152
f564048e 5153 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5154 x, y, fb);
79e53945 5155 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5156
1f803ee5 5157 return ret;
79e53945
JB		 5158}
5159
3a9627f4
WF		 5160static bool intel_eld_uptodate(struct drm_connector *connector,
5161 int reg_eldv, uint32_t bits_eldv,
5162 int reg_elda, uint32_t bits_elda,
5163 int reg_edid)
5164{
5165 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5166 uint8_t *eld = connector->eld;
5167 uint32_t i;
5168
5169 i = I915_READ(reg_eldv);
5170 i &= bits_eldv;
5171
5172 if (!eld[0])
5173 return !i;
5174
5175 if (!i)
5176 return false;
5177
5178 i = I915_READ(reg_elda);
5179 i &= ~bits_elda;
5180 I915_WRITE(reg_elda, i);
5181
5182 for (i = 0; i < eld[2]; i++)
5183 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5184 return false;
5185
5186 return true;
5187}
5188
e0dac65e
WF		 5189static void g4x_write_eld(struct drm_connector *connector,
5190 struct drm_crtc *crtc)
5191{
5192 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5193 uint8_t *eld = connector->eld;
5194 uint32_t eldv;
5195 uint32_t len;
5196 uint32_t i;
5197
5198 i = I915_READ(G4X_AUD_VID_DID);
5199
5200 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5201 eldv = G4X_ELDV_DEVCL_DEVBLC;
5202 else
5203 eldv = G4X_ELDV_DEVCTG;
5204
3a9627f4
WF		 5205 if (intel_eld_uptodate(connector,
5206 G4X_AUD_CNTL_ST, eldv,
5207 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5208 G4X_HDMIW_HDMIEDID))
5209 return;
5210
e0dac65e
WF		 5211 i = I915_READ(G4X_AUD_CNTL_ST);
5212 i &= ~(eldv | G4X_ELD_ADDR);
5213 len = (i >> 9) & 0x1f; /* ELD buffer size */
5214 I915_WRITE(G4X_AUD_CNTL_ST, i);
5215
5216 if (!eld[0])
5217 return;
5218
5219 len = min_t(uint8_t, eld[2], len);
5220 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5221 for (i = 0; i < len; i++)
5222 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5223
5224 i = I915_READ(G4X_AUD_CNTL_ST);
5225 i |= eldv;
5226 I915_WRITE(G4X_AUD_CNTL_ST, i);
5227}
5228
83358c85
WX		 5229static void haswell_write_eld(struct drm_connector *connector,
5230 struct drm_crtc *crtc)
5231{
5232 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5233 uint8_t *eld = connector->eld;
5234 struct drm_device *dev = crtc->dev;
5235 uint32_t eldv;
5236 uint32_t i;
5237 int len;
5238 int pipe = to_intel_crtc(crtc)->pipe;
5239 int tmp;
5240
5241 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5242 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5243 int aud_config = HSW_AUD_CFG(pipe);
5244 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5245
5246
5247 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5248
5249 /* Audio output enable */
5250 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5251 tmp = I915_READ(aud_cntrl_st2);
5252 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5253 I915_WRITE(aud_cntrl_st2, tmp);
5254
5255 /* Wait for 1 vertical blank */
5256 intel_wait_for_vblank(dev, pipe);
5257
5258 /* Set ELD valid state */
5259 tmp = I915_READ(aud_cntrl_st2);
5260 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5261 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5262 I915_WRITE(aud_cntrl_st2, tmp);
5263 tmp = I915_READ(aud_cntrl_st2);
5264 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5265
5266 /* Enable HDMI mode */
5267 tmp = I915_READ(aud_config);
5268 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5269 /* clear N_programing_enable and N_value_index */
5270 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5271 I915_WRITE(aud_config, tmp);
5272
5273 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5274
5275 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5276
5277 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5278 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5279 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5280 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5281 } else
5282 I915_WRITE(aud_config, 0);
5283
5284 if (intel_eld_uptodate(connector,
5285 aud_cntrl_st2, eldv,
5286 aud_cntl_st, IBX_ELD_ADDRESS,
5287 hdmiw_hdmiedid))
5288 return;
5289
5290 i = I915_READ(aud_cntrl_st2);
5291 i &= ~eldv;
5292 I915_WRITE(aud_cntrl_st2, i);
5293
5294 if (!eld[0])
5295 return;
5296
5297 i = I915_READ(aud_cntl_st);
5298 i &= ~IBX_ELD_ADDRESS;
5299 I915_WRITE(aud_cntl_st, i);
5300 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5301 DRM_DEBUG_DRIVER("port num:%d\n", i);
5302
5303 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5304 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5305 for (i = 0; i < len; i++)
5306 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5307
5308 i = I915_READ(aud_cntrl_st2);
5309 i |= eldv;
5310 I915_WRITE(aud_cntrl_st2, i);
5311
5312}
5313
e0dac65e
WF		 5314static void ironlake_write_eld(struct drm_connector *connector,
5315 struct drm_crtc *crtc)
5316{
5317 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5318 uint8_t *eld = connector->eld;
5319 uint32_t eldv;
5320 uint32_t i;
5321 int len;
5322 int hdmiw_hdmiedid;
b6daa025 5323 int aud_config;
e0dac65e
WF		 5324 int aud_cntl_st;
5325 int aud_cntrl_st2;
9b138a83 5326 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5327
b3f33cbf 5328 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5329 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5330 aud_config = IBX_AUD_CFG(pipe);
5331 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5332 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5333 } else {
9b138a83
WX		 5334 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5335 aud_config = CPT_AUD_CFG(pipe);
5336 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5337 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5338 }
5339
9b138a83 5340 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5341
5342 i = I915_READ(aud_cntl_st);
9b138a83 5343 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5344 if (!i) {
5345 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5346 /* operate blindly on all ports */
1202b4c6
WF		 5347 eldv = IBX_ELD_VALIDB;
5348 eldv |= IBX_ELD_VALIDB << 4;
5349 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5350 } else {
5351 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5352 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5353 }
5354
3a9627f4
WF		 5355 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5356 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5357 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5358 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5359 } else
5360 I915_WRITE(aud_config, 0);
e0dac65e 5361
3a9627f4
WF		 5362 if (intel_eld_uptodate(connector,
5363 aud_cntrl_st2, eldv,
5364 aud_cntl_st, IBX_ELD_ADDRESS,
5365 hdmiw_hdmiedid))
5366 return;
5367
e0dac65e
WF		 5368 i = I915_READ(aud_cntrl_st2);
5369 i &= ~eldv;
5370 I915_WRITE(aud_cntrl_st2, i);
5371
5372 if (!eld[0])
5373 return;
5374
e0dac65e 5375 i = I915_READ(aud_cntl_st);
1202b4c6 5376 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5377 I915_WRITE(aud_cntl_st, i);
5378
5379 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5380 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5381 for (i = 0; i < len; i++)
5382 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5383
5384 i = I915_READ(aud_cntrl_st2);
5385 i |= eldv;
5386 I915_WRITE(aud_cntrl_st2, i);
5387}
5388
5389void intel_write_eld(struct drm_encoder *encoder,
5390 struct drm_display_mode *mode)
5391{
5392 struct drm_crtc *crtc = encoder->crtc;
5393 struct drm_connector *connector;
5394 struct drm_device *dev = encoder->dev;
5395 struct drm_i915_private *dev_priv = dev->dev_private;
5396
5397 connector = drm_select_eld(encoder, mode);
5398 if (!connector)
5399 return;
5400
5401 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5402 connector->base.id,
5403 drm_get_connector_name(connector),
5404 connector->encoder->base.id,
5405 drm_get_encoder_name(connector->encoder));
5406
5407 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5408
5409 if (dev_priv->display.write_eld)
5410 dev_priv->display.write_eld(connector, crtc);
5411}
5412
79e53945
JB		 5413/** Loads the palette/gamma unit for the CRTC with the prepared values */
5414void intel_crtc_load_lut(struct drm_crtc *crtc)
5415{
5416 struct drm_device *dev = crtc->dev;
5417 struct drm_i915_private *dev_priv = dev->dev_private;
5418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5419 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5420 int i;
5421
5422 /* The clocks have to be on to load the palette. */
aed3f09d 5423 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5424 return;
5425
f2b115e6 5426 /* use legacy palette for Ironlake */
bad720ff 5427 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5428 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5429
79e53945
JB		 5430 for (i = 0; i < 256; i++) {
5431 I915_WRITE(palreg + 4 * i,
5432 (intel_crtc->lut_r[i] << 16) |
5433 (intel_crtc->lut_g[i] << 8) |
5434 intel_crtc->lut_b[i]);
5435 }
5436}
5437
560b85bb
CW		 5438static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5439{
5440 struct drm_device *dev = crtc->dev;
5441 struct drm_i915_private *dev_priv = dev->dev_private;
5442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5443 bool visible = base != 0;
5444 u32 cntl;
5445
5446 if (intel_crtc->cursor_visible == visible)
5447 return;
5448
9db4a9c7 5449 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5450 if (visible) {
5451 /* On these chipsets we can only modify the base whilst
5452 * the cursor is disabled.
5453 */
9db4a9c7 5454 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5455
5456 cntl &= ~(CURSOR_FORMAT_MASK);
5457 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5458 cntl |= CURSOR_ENABLE |
5459 CURSOR_GAMMA_ENABLE |
5460 CURSOR_FORMAT_ARGB;
5461 } else
5462 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5463 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5464
5465 intel_crtc->cursor_visible = visible;
5466}
5467
5468static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5469{
5470 struct drm_device *dev = crtc->dev;
5471 struct drm_i915_private *dev_priv = dev->dev_private;
5472 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5473 int pipe = intel_crtc->pipe;
5474 bool visible = base != 0;
5475
5476 if (intel_crtc->cursor_visible != visible) {
548f245b 5477 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5478 if (base) {
5479 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5480 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5481 cntl |= pipe << 28; /* Connect to correct pipe */
5482 } else {
5483 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5484 cntl |= CURSOR_MODE_DISABLE;
5485 }
9db4a9c7 5486 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5487
5488 intel_crtc->cursor_visible = visible;
5489 }
5490 /* and commit changes on next vblank */
9db4a9c7 5491 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5492}
5493
65a21cd6
JB		 5494static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5495{
5496 struct drm_device *dev = crtc->dev;
5497 struct drm_i915_private *dev_priv = dev->dev_private;
5498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5499 int pipe = intel_crtc->pipe;
5500 bool visible = base != 0;
5501
5502 if (intel_crtc->cursor_visible != visible) {
5503 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5504 if (base) {
5505 cntl &= ~CURSOR_MODE;
5506 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5507 } else {
5508 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5509 cntl |= CURSOR_MODE_DISABLE;
5510 }
5511 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5512
5513 intel_crtc->cursor_visible = visible;
5514 }
5515 /* and commit changes on next vblank */
5516 I915_WRITE(CURBASE_IVB(pipe), base);
5517}
5518
cda4b7d3 5519/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5520static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5521 bool on)
cda4b7d3
CW		 5522{
5523 struct drm_device *dev = crtc->dev;
5524 struct drm_i915_private *dev_priv = dev->dev_private;
5525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5526 int pipe = intel_crtc->pipe;
5527 int x = intel_crtc->cursor_x;
5528 int y = intel_crtc->cursor_y;
560b85bb 5529 u32 base, pos;
cda4b7d3
CW		 5530 bool visible;
5531
5532 pos = 0;
5533
6b383a7f 5534 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5535 base = intel_crtc->cursor_addr;
5536 if (x > (int) crtc->fb->width)
5537 base = 0;
5538
5539 if (y > (int) crtc->fb->height)
5540 base = 0;
5541 } else
5542 base = 0;
5543
5544 if (x < 0) {
5545 if (x + intel_crtc->cursor_width < 0)
5546 base = 0;
5547
5548 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5549 x = -x;
5550 }
5551 pos |= x << CURSOR_X_SHIFT;
5552
5553 if (y < 0) {
5554 if (y + intel_crtc->cursor_height < 0)
5555 base = 0;
5556
5557 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5558 y = -y;
5559 }
5560 pos |= y << CURSOR_Y_SHIFT;
5561
5562 visible = base != 0;
560b85bb 5563 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5564 return;
5565
0cd83aa9 5566 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5567 I915_WRITE(CURPOS_IVB(pipe), pos);
5568 ivb_update_cursor(crtc, base);
5569 } else {
5570 I915_WRITE(CURPOS(pipe), pos);
5571 if (IS_845G(dev) || IS_I865G(dev))
5572 i845_update_cursor(crtc, base);
5573 else
5574 i9xx_update_cursor(crtc, base);
5575 }
cda4b7d3
CW		 5576}
5577
79e53945 5578static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5579 struct drm_file *file,
79e53945
JB		 5580 uint32_t handle,
5581 uint32_t width, uint32_t height)
5582{
5583 struct drm_device *dev = crtc->dev;
5584 struct drm_i915_private *dev_priv = dev->dev_private;
5585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5586 struct drm_i915_gem_object *obj;
cda4b7d3 5587 uint32_t addr;
3f8bc370 5588 int ret;
79e53945 5589
79e53945
JB		 5590 /* if we want to turn off the cursor ignore width and height */
5591 if (!handle) {
28c97730 5592 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5593 addr = 0;
05394f39 5594 obj = NULL;
5004417d 5595 mutex_lock(&dev->struct_mutex);
3f8bc370 5596 goto finish;
79e53945
JB		 5597 }
5598
5599 /* Currently we only support 64x64 cursors */
5600 if (width != 64 || height != 64) {
5601 DRM_ERROR("we currently only support 64x64 cursors\n");
5602 return -EINVAL;
5603 }
5604
05394f39 5605 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5606 if (&obj->base == NULL)
79e53945
JB		 5607 return -ENOENT;
5608
05394f39 5609 if (obj->base.size < width * height * 4) {
79e53945 5610 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5611 ret = -ENOMEM;
5612 goto fail;
79e53945
JB		 5613 }
5614
71acb5eb 5615 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5616 mutex_lock(&dev->struct_mutex);
b295d1b6 5617 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5618 if (obj->tiling_mode) {
5619 DRM_ERROR("cursor cannot be tiled\n");
5620 ret = -EINVAL;
5621 goto fail_locked;
5622 }
5623
2da3b9b9 5624 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5625 if (ret) {
5626 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5627 goto fail_locked;
e7b526bb
CW		 5628 }
5629
d9e86c0e
CW		 5630 ret = i915_gem_object_put_fence(obj);
5631 if (ret) {
2da3b9b9 5632 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5633 goto fail_unpin;
5634 }
5635
05394f39 5636 addr = obj->gtt_offset;
71acb5eb 5637 } else {
6eeefaf3 5638 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5639 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5640 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5641 align);
71acb5eb
DA		 5642 if (ret) {
5643 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5644 goto fail_locked;
71acb5eb 5645 }
05394f39 5646 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5647 }
5648
a6c45cf0 5649 if (IS_GEN2(dev))
14b60391
JB		 5650 I915_WRITE(CURSIZE, (height << 12) | width);
5651
3f8bc370 5652 finish:
3f8bc370 5653 if (intel_crtc->cursor_bo) {
b295d1b6 5654 if (dev_priv->info->cursor_needs_physical) {
05394f39 5655 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5656 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5657 } else
5658 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5659 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5660 }
80824003 5661
7f9872e0 5662 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5663
5664 intel_crtc->cursor_addr = addr;
05394f39 5665 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5666 intel_crtc->cursor_width = width;
5667 intel_crtc->cursor_height = height;
5668
6b383a7f 5669 intel_crtc_update_cursor(crtc, true);
3f8bc370 5670
79e53945 5671 return 0;
e7b526bb 5672fail_unpin:
05394f39 5673 i915_gem_object_unpin(obj);
7f9872e0 5674fail_locked:
34b8686e 5675 mutex_unlock(&dev->struct_mutex);
bc9025bd 5676fail:
05394f39 5677 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5678 return ret;
79e53945
JB		 5679}
5680
5681static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5682{
79e53945 5683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5684
cda4b7d3
CW		 5685 intel_crtc->cursor_x = x;
5686 intel_crtc->cursor_y = y;
652c393a 5687
6b383a7f 5688 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5689
5690 return 0;
5691}
5692
5693/** Sets the color ramps on behalf of RandR */
5694void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5695 u16 blue, int regno)
5696{
5697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5698
5699 intel_crtc->lut_r[regno] = red >> 8;
5700 intel_crtc->lut_g[regno] = green >> 8;
5701 intel_crtc->lut_b[regno] = blue >> 8;
5702}
5703
b8c00ac5
DA		 5704void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5705 u16 *blue, int regno)
5706{
5707 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5708
5709 *red = intel_crtc->lut_r[regno] << 8;
5710 *green = intel_crtc->lut_g[regno] << 8;
5711 *blue = intel_crtc->lut_b[regno] << 8;
5712}
5713
79e53945 5714static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5715 u16 *blue, uint32_t start, uint32_t size)
79e53945 5716{
7203425a 5717 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5719
7203425a 5720 for (i = start; i < end; i++) {
79e53945
JB		 5721 intel_crtc->lut_r[i] = red[i] >> 8;
5722 intel_crtc->lut_g[i] = green[i] >> 8;
5723 intel_crtc->lut_b[i] = blue[i] >> 8;
5724 }
5725
5726 intel_crtc_load_lut(crtc);
5727}
5728
5729/**
5730 * Get a pipe with a simple mode set on it for doing load-based monitor
5731 * detection.
5732 *
5733 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5734 * its requirements. The pipe will be connected to no other encoders.
79e53945 5735 *
c751ce4f 5736 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5737 * configured for it. In the future, it could choose to temporarily disable
5738 * some outputs to free up a pipe for its use.
5739 *
5740 * \return crtc, or NULL if no pipes are available.
5741 */
5742
5743/* VESA 640x480x72Hz mode to set on the pipe */
5744static struct drm_display_mode load_detect_mode = {
5745 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5746 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5747};
5748
d2dff872
CW		 5749static struct drm_framebuffer *
5750intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5751 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5752 struct drm_i915_gem_object *obj)
5753{
5754 struct intel_framebuffer *intel_fb;
5755 int ret;
5756
5757 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5758 if (!intel_fb) {
5759 drm_gem_object_unreference_unlocked(&obj->base);
5760 return ERR_PTR(-ENOMEM);
5761 }
5762
5763 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5764 if (ret) {
5765 drm_gem_object_unreference_unlocked(&obj->base);
5766 kfree(intel_fb);
5767 return ERR_PTR(ret);
5768 }
5769
5770 return &intel_fb->base;
5771}
5772
5773static u32
5774intel_framebuffer_pitch_for_width(int width, int bpp)
5775{
5776 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5777 return ALIGN(pitch, 64);
5778}
5779
5780static u32
5781intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5782{
5783 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5784 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5785}
5786
5787static struct drm_framebuffer *
5788intel_framebuffer_create_for_mode(struct drm_device *dev,
5789 struct drm_display_mode *mode,
5790 int depth, int bpp)
5791{
5792 struct drm_i915_gem_object *obj;
308e5bcb 5793 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5794
5795 obj = i915_gem_alloc_object(dev,
5796 intel_framebuffer_size_for_mode(mode, bpp));
5797 if (obj == NULL)
5798 return ERR_PTR(-ENOMEM);
5799
5800 mode_cmd.width = mode->hdisplay;
5801 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5802 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5803 bpp);
5ca0c34a 5804 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5805
5806 return intel_framebuffer_create(dev, &mode_cmd, obj);
5807}
5808
5809static struct drm_framebuffer *
5810mode_fits_in_fbdev(struct drm_device *dev,
5811 struct drm_display_mode *mode)
5812{
5813 struct drm_i915_private *dev_priv = dev->dev_private;
5814 struct drm_i915_gem_object *obj;
5815 struct drm_framebuffer *fb;
5816
5817 if (dev_priv->fbdev == NULL)
5818 return NULL;
5819
5820 obj = dev_priv->fbdev->ifb.obj;
5821 if (obj == NULL)
5822 return NULL;
5823
5824 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5825 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5826 fb->bits_per_pixel))
d2dff872
CW		 5827 return NULL;
5828
01f2c773 5829 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5830 return NULL;
5831
5832 return fb;
5833}
5834
d2434ab7 5835bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 5836 struct drm_display_mode *mode,
8261b191 5837 struct intel_load_detect_pipe *old)
79e53945
JB		 5838{
5839 struct intel_crtc *intel_crtc;
d2434ab7
DV		 5840 struct intel_encoder *intel_encoder =
5841 intel_attached_encoder(connector);
79e53945 5842 struct drm_crtc *possible_crtc;
4ef69c7a 5843 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5844 struct drm_crtc *crtc = NULL;
5845 struct drm_device *dev = encoder->dev;
94352cf9 5846 struct drm_framebuffer *fb;
79e53945
JB		 5847 int i = -1;
5848
d2dff872
CW		 5849 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5850 connector->base.id, drm_get_connector_name(connector),
5851 encoder->base.id, drm_get_encoder_name(encoder));
5852
79e53945
JB		 5853 /*
5854 * Algorithm gets a little messy:
7a5e4805 5855 *
79e53945
JB		 5856 * - if the connector already has an assigned crtc, use it (but make
5857 * sure it's on first)
7a5e4805 5858 *
79e53945
JB		 5859 * - try to find the first unused crtc that can drive this connector,
5860 * and use that if we find one
79e53945
JB		 5861 */
5862
5863 /* See if we already have a CRTC for this connector */
5864 if (encoder->crtc) {
5865 crtc = encoder->crtc;
8261b191 5866
24218aac 5867 old->dpms_mode = connector->dpms;
8261b191
CW		 5868 old->load_detect_temp = false;
5869
5870 /* Make sure the crtc and connector are running */
24218aac
DV		 5871 if (connector->dpms != DRM_MODE_DPMS_ON)
5872 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 5873
7173188d 5874 return true;
79e53945
JB		 5875 }
5876
5877 /* Find an unused one (if possible) */
5878 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5879 i++;
5880 if (!(encoder->possible_crtcs & (1 << i)))
5881 continue;
5882 if (!possible_crtc->enabled) {
5883 crtc = possible_crtc;
5884 break;
5885 }
79e53945
JB		 5886 }
5887
5888 /*
5889 * If we didn't find an unused CRTC, don't use any.
5890 */
5891 if (!crtc) {
7173188d
CW		 5892 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5893 return false;
79e53945
JB		 5894 }
5895
fc303101
DV		 5896 intel_encoder->new_crtc = to_intel_crtc(crtc);
5897 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 5898
5899 intel_crtc = to_intel_crtc(crtc);
24218aac 5900 old->dpms_mode = connector->dpms;
8261b191 5901 old->load_detect_temp = true;
d2dff872 5902 old->release_fb = NULL;
79e53945 5903
6492711d
CW		 5904 if (!mode)
5905 mode = &load_detect_mode;
79e53945 5906
d2dff872
CW		 5907 /* We need a framebuffer large enough to accommodate all accesses
5908 * that the plane may generate whilst we perform load detection.
5909 * We can not rely on the fbcon either being present (we get called
5910 * during its initialisation to detect all boot displays, or it may
5911 * not even exist) or that it is large enough to satisfy the
5912 * requested mode.
5913 */
94352cf9
DV		 5914 fb = mode_fits_in_fbdev(dev, mode);
5915 if (fb == NULL) {
d2dff872 5916 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 5917 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5918 old->release_fb = fb;
d2dff872
CW		 5919 } else
5920 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 5921 if (IS_ERR(fb)) {
d2dff872 5922 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 5923 goto fail;
79e53945 5924 }
79e53945 5925
94352cf9 5926 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 5927 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5928 if (old->release_fb)
5929 old->release_fb->funcs->destroy(old->release_fb);
24218aac 5930 goto fail;
79e53945 5931 }
7173188d 5932
79e53945 5933 /* let the connector get through one full cycle before testing */
9d0498a2 5934 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5935
7173188d 5936 return true;
24218aac
DV		 5937fail:
5938 connector->encoder = NULL;
5939 encoder->crtc = NULL;
24218aac 5940 return false;
79e53945
JB		 5941}
5942
d2434ab7 5943void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 5944 struct intel_load_detect_pipe *old)
79e53945 5945{
d2434ab7
DV		 5946 struct intel_encoder *intel_encoder =
5947 intel_attached_encoder(connector);
4ef69c7a 5948 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 5949
d2dff872
CW		 5950 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5951 connector->base.id, drm_get_connector_name(connector),
5952 encoder->base.id, drm_get_encoder_name(encoder));
5953
8261b191 5954 if (old->load_detect_temp) {
fc303101
DV		 5955 struct drm_crtc *crtc = encoder->crtc;
5956
5957 to_intel_connector(connector)->new_encoder = NULL;
5958 intel_encoder->new_crtc = NULL;
5959 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 5960
5961 if (old->release_fb)
5962 old->release_fb->funcs->destroy(old->release_fb);
5963
0622a53c 5964 return;
79e53945
JB		 5965 }
5966
c751ce4f 5967 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 5968 if (old->dpms_mode != DRM_MODE_DPMS_ON)
5969 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 5970}
5971
5972/* Returns the clock of the currently programmed mode of the given pipe. */
5973static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5974{
5975 struct drm_i915_private *dev_priv = dev->dev_private;
5976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5977 int pipe = intel_crtc->pipe;
548f245b 5978 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5979 u32 fp;
5980 intel_clock_t clock;
5981
5982 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5983 fp = I915_READ(FP0(pipe));
79e53945 5984 else
39adb7a5 5985 fp = I915_READ(FP1(pipe));
79e53945
JB		 5986
5987 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5988 if (IS_PINEVIEW(dev)) {
5989 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5990 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5991 } else {
5992 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5993 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5994 }
5995
a6c45cf0 5996 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5997 if (IS_PINEVIEW(dev))
5998 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5999 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6000 else
6001 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6002 DPLL_FPA01_P1_POST_DIV_SHIFT);
6003
6004 switch (dpll & DPLL_MODE_MASK) {
6005 case DPLLB_MODE_DAC_SERIAL:
6006 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6007 5 : 10;
6008 break;
6009 case DPLLB_MODE_LVDS:
6010 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6011 7 : 14;
6012 break;
6013 default:
28c97730 6014 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6015 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6016 return 0;
6017 }
6018
6019 /* XXX: Handle the 100Mhz refclk */
2177832f 6020 intel_clock(dev, 96000, &clock);
79e53945
JB		 6021 } else {
6022 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6023
6024 if (is_lvds) {
6025 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6026 DPLL_FPA01_P1_POST_DIV_SHIFT);
6027 clock.p2 = 14;
6028
6029 if ((dpll & PLL_REF_INPUT_MASK) ==
6030 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6031 /* XXX: might not be 66MHz */
2177832f 6032 intel_clock(dev, 66000, &clock);
79e53945 6033 } else
2177832f 6034 intel_clock(dev, 48000, &clock);
79e53945
JB		 6035 } else {
6036 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6037 clock.p1 = 2;
6038 else {
6039 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6040 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6041 }
6042 if (dpll & PLL_P2_DIVIDE_BY_4)
6043 clock.p2 = 4;
6044 else
6045 clock.p2 = 2;
6046
2177832f 6047 intel_clock(dev, 48000, &clock);
79e53945
JB		 6048 }
6049 }
6050
6051 /* XXX: It would be nice to validate the clocks, but we can't reuse
6052 * i830PllIsValid() because it relies on the xf86_config connector
6053 * configuration being accurate, which it isn't necessarily.
6054 */
6055
6056 return clock.dot;
6057}
6058
6059/** Returns the currently programmed mode of the given pipe. */
6060struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6061 struct drm_crtc *crtc)
6062{
548f245b 6063 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6065 int pipe = intel_crtc->pipe;
6066 struct drm_display_mode *mode;
548f245b
JB		 6067 int htot = I915_READ(HTOTAL(pipe));
6068 int hsync = I915_READ(HSYNC(pipe));
6069 int vtot = I915_READ(VTOTAL(pipe));
6070 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6071
6072 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6073 if (!mode)
6074 return NULL;
6075
6076 mode->clock = intel_crtc_clock_get(dev, crtc);
6077 mode->hdisplay = (htot & 0xffff) + 1;
6078 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6079 mode->hsync_start = (hsync & 0xffff) + 1;
6080 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6081 mode->vdisplay = (vtot & 0xffff) + 1;
6082 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6083 mode->vsync_start = (vsync & 0xffff) + 1;
6084 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6085
6086 drm_mode_set_name(mode);
79e53945
JB		 6087
6088 return mode;
6089}
6090
3dec0095 6091static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6092{
6093 struct drm_device *dev = crtc->dev;
6094 drm_i915_private_t *dev_priv = dev->dev_private;
6095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6096 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6097 int dpll_reg = DPLL(pipe);
6098 int dpll;
652c393a 6099
bad720ff 6100 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6101 return;
6102
6103 if (!dev_priv->lvds_downclock_avail)
6104 return;
6105
dbdc6479 6106 dpll = I915_READ(dpll_reg);
652c393a 6107 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6108 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6109
8ac5a6d5 6110 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6111
6112 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6113 I915_WRITE(dpll_reg, dpll);
9d0498a2 6114 intel_wait_for_vblank(dev, pipe);
dbdc6479 6115
652c393a
JB		 6116 dpll = I915_READ(dpll_reg);
6117 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6118 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6119 }
652c393a
JB		 6120}
6121
6122static void intel_decrease_pllclock(struct drm_crtc *crtc)
6123{
6124 struct drm_device *dev = crtc->dev;
6125 drm_i915_private_t *dev_priv = dev->dev_private;
6126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6127
bad720ff 6128 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6129 return;
6130
6131 if (!dev_priv->lvds_downclock_avail)
6132 return;
6133
6134 /*
6135 * Since this is called by a timer, we should never get here in
6136 * the manual case.
6137 */
6138 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6139 int pipe = intel_crtc->pipe;
6140 int dpll_reg = DPLL(pipe);
6141 int dpll;
f6e5b160 6142
44d98a61 6143 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6144
8ac5a6d5 6145 assert_panel_unlocked(dev_priv, pipe);
652c393a 6146
dc257cf1 6147 dpll = I915_READ(dpll_reg);
652c393a
JB		 6148 dpll |= DISPLAY_RATE_SELECT_FPA1;
6149 I915_WRITE(dpll_reg, dpll);
9d0498a2 6150 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6151 dpll = I915_READ(dpll_reg);
6152 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6153 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6154 }
6155
6156}
6157
f047e395
CW		 6158void intel_mark_busy(struct drm_device *dev)
6159{
f047e395
CW		 6160 i915_update_gfx_val(dev->dev_private);
6161}
6162
6163void intel_mark_idle(struct drm_device *dev)
652c393a 6164{
f047e395
CW		 6165}
6166
6167void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6168{
6169 struct drm_device *dev = obj->base.dev;
652c393a 6170 struct drm_crtc *crtc;
652c393a
JB		 6171
6172 if (!i915_powersave)
6173 return;
6174
652c393a 6175 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6176 if (!crtc->fb)
6177 continue;
6178
f047e395
CW		 6179 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6180 intel_increase_pllclock(crtc);
652c393a 6181 }
652c393a
JB		 6182}
6183
f047e395 6184void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6185{
f047e395
CW		 6186 struct drm_device *dev = obj->base.dev;
6187 struct drm_crtc *crtc;
652c393a 6188
f047e395 6189 if (!i915_powersave)
acb87dfb
CW		 6190 return;
6191
652c393a
JB		 6192 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6193 if (!crtc->fb)
6194 continue;
6195
f047e395
CW		 6196 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6197 intel_decrease_pllclock(crtc);
652c393a
JB		 6198 }
6199}
6200
79e53945
JB		 6201static void intel_crtc_destroy(struct drm_crtc *crtc)
6202{
6203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6204 struct drm_device *dev = crtc->dev;
6205 struct intel_unpin_work *work;
6206 unsigned long flags;
6207
6208 spin_lock_irqsave(&dev->event_lock, flags);
6209 work = intel_crtc->unpin_work;
6210 intel_crtc->unpin_work = NULL;
6211 spin_unlock_irqrestore(&dev->event_lock, flags);
6212
6213 if (work) {
6214 cancel_work_sync(&work->work);
6215 kfree(work);
6216 }
79e53945
JB		 6217
6218 drm_crtc_cleanup(crtc);
67e77c5a 6219
79e53945
JB		 6220 kfree(intel_crtc);
6221}
6222
6b95a207
KH		 6223static void intel_unpin_work_fn(struct work_struct *__work)
6224{
6225 struct intel_unpin_work *work =
6226 container_of(__work, struct intel_unpin_work, work);
6227
6228 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6229 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6230 drm_gem_object_unreference(&work->pending_flip_obj->base);
6231 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6232
7782de3b 6233 intel_update_fbc(work->dev);
6b95a207
KH		 6234 mutex_unlock(&work->dev->struct_mutex);
6235 kfree(work);
6236}
6237
1afe3e9d 6238static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6239 struct drm_crtc *crtc)
6b95a207
KH		 6240{
6241 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6243 struct intel_unpin_work *work;
05394f39 6244 struct drm_i915_gem_object *obj;
6b95a207 6245 struct drm_pending_vblank_event *e;
49b14a5c 6246 struct timeval tnow, tvbl;
6b95a207
KH		 6247 unsigned long flags;
6248
6249 /* Ignore early vblank irqs */
6250 if (intel_crtc == NULL)
6251 return;
6252
49b14a5c
MK		 6253 do_gettimeofday(&tnow);
6254
6b95a207
KH		 6255 spin_lock_irqsave(&dev->event_lock, flags);
6256 work = intel_crtc->unpin_work;
6257 if (work == NULL || !work->pending) {
6258 spin_unlock_irqrestore(&dev->event_lock, flags);
6259 return;
6260 }
6261
6262 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6263
6264 if (work->event) {
6265 e = work->event;
49b14a5c 6266 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6267
6268 /* Called before vblank count and timestamps have
6269 * been updated for the vblank interval of flip
6270 * completion? Need to increment vblank count and
6271 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6272 * to account for this. We assume this happened if we
6273 * get called over 0.9 frame durations after the last
6274 * timestamped vblank.
6275 *
6276 * This calculation can not be used with vrefresh rates
6277 * below 5Hz (10Hz to be on the safe side) without
6278 * promoting to 64 integers.
0af7e4df 6279 */
49b14a5c
MK		 6280 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6281 9 * crtc->framedur_ns) {
0af7e4df 6282 e->event.sequence++;
49b14a5c
MK		 6283 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6284 crtc->framedur_ns);
0af7e4df
MK		 6285 }
6286
49b14a5c
MK		 6287 e->event.tv_sec = tvbl.tv_sec;
6288 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6289
6b95a207
KH		 6290 list_add_tail(&e->base.link,
6291 &e->base.file_priv->event_list);
6292 wake_up_interruptible(&e->base.file_priv->event_wait);
6293 }
6294
0af7e4df
MK		 6295 drm_vblank_put(dev, intel_crtc->pipe);
6296
6b95a207
KH		 6297 spin_unlock_irqrestore(&dev->event_lock, flags);
6298
05394f39 6299 obj = work->old_fb_obj;
d9e86c0e 6300
e59f2bac 6301 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6302 &obj->pending_flip.counter);
6303 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6304 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6305
6b95a207 6306 schedule_work(&work->work);
e5510fac
JB		 6307
6308 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6309}
6310
1afe3e9d
JB		 6311void intel_finish_page_flip(struct drm_device *dev, int pipe)
6312{
6313 drm_i915_private_t *dev_priv = dev->dev_private;
6314 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6315
49b14a5c 6316 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6317}
6318
6319void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6320{
6321 drm_i915_private_t *dev_priv = dev->dev_private;
6322 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6323
49b14a5c 6324 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6325}
6326
6b95a207
KH		 6327void intel_prepare_page_flip(struct drm_device *dev, int plane)
6328{
6329 drm_i915_private_t *dev_priv = dev->dev_private;
6330 struct intel_crtc *intel_crtc =
6331 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6332 unsigned long flags;
6333
6334 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6335 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6336 if ((++intel_crtc->unpin_work->pending) > 1)
6337 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6338 } else {
6339 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6340 }
6b95a207
KH		 6341 spin_unlock_irqrestore(&dev->event_lock, flags);
6342}
6343
8c9f3aaf
JB		 6344static int intel_gen2_queue_flip(struct drm_device *dev,
6345 struct drm_crtc *crtc,
6346 struct drm_framebuffer *fb,
6347 struct drm_i915_gem_object *obj)
6348{
6349 struct drm_i915_private *dev_priv = dev->dev_private;
6350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6351 u32 flip_mask;
6d90c952 6352 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6353 int ret;
6354
6d90c952 6355 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6356 if (ret)
83d4092b 6357 goto err;
8c9f3aaf 6358
6d90c952 6359 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6360 if (ret)
83d4092b 6361 goto err_unpin;
8c9f3aaf
JB		 6362
6363 /* Can't queue multiple flips, so wait for the previous
6364 * one to finish before executing the next.
6365 */
6366 if (intel_crtc->plane)
6367 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6368 else
6369 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6370 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6371 intel_ring_emit(ring, MI_NOOP);
6372 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6373 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6374 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6375 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6376 intel_ring_emit(ring, 0); /* aux display base address, unused */
6377 intel_ring_advance(ring);
83d4092b
CW		 6378 return 0;
6379
6380err_unpin:
6381 intel_unpin_fb_obj(obj);
6382err:
8c9f3aaf
JB		 6383 return ret;
6384}
6385
6386static int intel_gen3_queue_flip(struct drm_device *dev,
6387 struct drm_crtc *crtc,
6388 struct drm_framebuffer *fb,
6389 struct drm_i915_gem_object *obj)
6390{
6391 struct drm_i915_private *dev_priv = dev->dev_private;
6392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6393 u32 flip_mask;
6d90c952 6394 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6395 int ret;
6396
6d90c952 6397 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6398 if (ret)
83d4092b 6399 goto err;
8c9f3aaf 6400
6d90c952 6401 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6402 if (ret)
83d4092b 6403 goto err_unpin;
8c9f3aaf
JB		 6404
6405 if (intel_crtc->plane)
6406 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6407 else
6408 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6409 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6410 intel_ring_emit(ring, MI_NOOP);
6411 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6412 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6413 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6414 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6415 intel_ring_emit(ring, MI_NOOP);
6416
6417 intel_ring_advance(ring);
83d4092b
CW		 6418 return 0;
6419
6420err_unpin:
6421 intel_unpin_fb_obj(obj);
6422err:
8c9f3aaf
JB		 6423 return ret;
6424}
6425
6426static int intel_gen4_queue_flip(struct drm_device *dev,
6427 struct drm_crtc *crtc,
6428 struct drm_framebuffer *fb,
6429 struct drm_i915_gem_object *obj)
6430{
6431 struct drm_i915_private *dev_priv = dev->dev_private;
6432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6433 uint32_t pf, pipesrc;
6d90c952 6434 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6435 int ret;
6436
6d90c952 6437 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6438 if (ret)
83d4092b 6439 goto err;
8c9f3aaf 6440
6d90c952 6441 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6442 if (ret)
83d4092b 6443 goto err_unpin;
8c9f3aaf
JB		 6444
6445 /* i965+ uses the linear or tiled offsets from the
6446 * Display Registers (which do not change across a page-flip)
6447 * so we need only reprogram the base address.
6448 */
6d90c952
DV		 6449 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6450 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6451 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6452 intel_ring_emit(ring,
6453 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6454 obj->tiling_mode);
8c9f3aaf
JB		 6455
6456 /* XXX Enabling the panel-fitter across page-flip is so far
6457 * untested on non-native modes, so ignore it for now.
6458 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6459 */
6460 pf = 0;
6461 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6462 intel_ring_emit(ring, pf | pipesrc);
6463 intel_ring_advance(ring);
83d4092b
CW		 6464 return 0;
6465
6466err_unpin:
6467 intel_unpin_fb_obj(obj);
6468err:
8c9f3aaf
JB		 6469 return ret;
6470}
6471
6472static int intel_gen6_queue_flip(struct drm_device *dev,
6473 struct drm_crtc *crtc,
6474 struct drm_framebuffer *fb,
6475 struct drm_i915_gem_object *obj)
6476{
6477 struct drm_i915_private *dev_priv = dev->dev_private;
6478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6479 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6480 uint32_t pf, pipesrc;
6481 int ret;
6482
6d90c952 6483 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6484 if (ret)
83d4092b 6485 goto err;
8c9f3aaf 6486
6d90c952 6487 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6488 if (ret)
83d4092b 6489 goto err_unpin;
8c9f3aaf 6490
6d90c952
DV		 6491 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6492 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6493 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 6494 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 6495
dc257cf1
DV		 6496 /* Contrary to the suggestions in the documentation,
6497 * "Enable Panel Fitter" does not seem to be required when page
6498 * flipping with a non-native mode, and worse causes a normal
6499 * modeset to fail.
6500 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6501 */
6502 pf = 0;
8c9f3aaf 6503 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6504 intel_ring_emit(ring, pf | pipesrc);
6505 intel_ring_advance(ring);
83d4092b
CW		 6506 return 0;
6507
6508err_unpin:
6509 intel_unpin_fb_obj(obj);
6510err:
8c9f3aaf
JB		 6511 return ret;
6512}
6513
7c9017e5
JB		 6514/*
6515 * On gen7 we currently use the blit ring because (in early silicon at least)
6516 * the render ring doesn't give us interrpts for page flip completion, which
6517 * means clients will hang after the first flip is queued. Fortunately the
6518 * blit ring generates interrupts properly, so use it instead.
6519 */
6520static int intel_gen7_queue_flip(struct drm_device *dev,
6521 struct drm_crtc *crtc,
6522 struct drm_framebuffer *fb,
6523 struct drm_i915_gem_object *obj)
6524{
6525 struct drm_i915_private *dev_priv = dev->dev_private;
6526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6527 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 6528 uint32_t plane_bit = 0;
7c9017e5
JB		 6529 int ret;
6530
6531 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6532 if (ret)
83d4092b 6533 goto err;
7c9017e5 6534
cb05d8de
DV		 6535 switch(intel_crtc->plane) {
6536 case PLANE_A:
6537 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6538 break;
6539 case PLANE_B:
6540 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6541 break;
6542 case PLANE_C:
6543 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6544 break;
6545 default:
6546 WARN_ONCE(1, "unknown plane in flip command\n");
6547 ret = -ENODEV;
ab3951eb 6548 goto err_unpin;
cb05d8de
DV		 6549 }
6550
7c9017e5
JB		 6551 ret = intel_ring_begin(ring, 4);
6552 if (ret)
83d4092b 6553 goto err_unpin;
7c9017e5 6554
cb05d8de 6555 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 6556 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 6557 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 6558 intel_ring_emit(ring, (MI_NOOP));
6559 intel_ring_advance(ring);
83d4092b
CW		 6560 return 0;
6561
6562err_unpin:
6563 intel_unpin_fb_obj(obj);
6564err:
7c9017e5
JB		 6565 return ret;
6566}
6567
8c9f3aaf
JB		 6568static int intel_default_queue_flip(struct drm_device *dev,
6569 struct drm_crtc *crtc,
6570 struct drm_framebuffer *fb,
6571 struct drm_i915_gem_object *obj)
6572{
6573 return -ENODEV;
6574}
6575
6b95a207
KH		 6576static int intel_crtc_page_flip(struct drm_crtc *crtc,
6577 struct drm_framebuffer *fb,
6578 struct drm_pending_vblank_event *event)
6579{
6580 struct drm_device *dev = crtc->dev;
6581 struct drm_i915_private *dev_priv = dev->dev_private;
6582 struct intel_framebuffer *intel_fb;
05394f39 6583 struct drm_i915_gem_object *obj;
6b95a207
KH		 6584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6585 struct intel_unpin_work *work;
8c9f3aaf 6586 unsigned long flags;
52e68630 6587 int ret;
6b95a207 6588
e6a595d2
VS		 6589 /* Can't change pixel format via MI display flips. */
6590 if (fb->pixel_format != crtc->fb->pixel_format)
6591 return -EINVAL;
6592
6593 /*
6594 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6595 * Note that pitch changes could also affect these register.
6596 */
6597 if (INTEL_INFO(dev)->gen > 3 &&
6598 (fb->offsets[0] != crtc->fb->offsets[0] ||
6599 fb->pitches[0] != crtc->fb->pitches[0]))
6600 return -EINVAL;
6601
6b95a207
KH		 6602 work = kzalloc(sizeof *work, GFP_KERNEL);
6603 if (work == NULL)
6604 return -ENOMEM;
6605
6b95a207
KH		 6606 work->event = event;
6607 work->dev = crtc->dev;
6608 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6609 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6610 INIT_WORK(&work->work, intel_unpin_work_fn);
6611
7317c75e
JB		 6612 ret = drm_vblank_get(dev, intel_crtc->pipe);
6613 if (ret)
6614 goto free_work;
6615
6b95a207
KH		 6616 /* We borrow the event spin lock for protecting unpin_work */
6617 spin_lock_irqsave(&dev->event_lock, flags);
6618 if (intel_crtc->unpin_work) {
6619 spin_unlock_irqrestore(&dev->event_lock, flags);
6620 kfree(work);
7317c75e 6621 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6622
6623 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6624 return -EBUSY;
6625 }
6626 intel_crtc->unpin_work = work;
6627 spin_unlock_irqrestore(&dev->event_lock, flags);
6628
6629 intel_fb = to_intel_framebuffer(fb);
6630 obj = intel_fb->obj;
6631
79158103
CW		 6632 ret = i915_mutex_lock_interruptible(dev);
6633 if (ret)
6634 goto cleanup;
6b95a207 6635
75dfca80 6636 /* Reference the objects for the scheduled work. */
05394f39
CW		 6637 drm_gem_object_reference(&work->old_fb_obj->base);
6638 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6639
6640 crtc->fb = fb;
96b099fd 6641
e1f99ce6 6642 work->pending_flip_obj = obj;
e1f99ce6 6643
4e5359cd
SF		 6644 work->enable_stall_check = true;
6645
e1f99ce6
CW		 6646 /* Block clients from rendering to the new back buffer until
6647 * the flip occurs and the object is no longer visible.
6648 */
05394f39 6649 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6650
8c9f3aaf
JB		 6651 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6652 if (ret)
6653 goto cleanup_pending;
6b95a207 6654
7782de3b 6655 intel_disable_fbc(dev);
f047e395 6656 intel_mark_fb_busy(obj);
6b95a207
KH		 6657 mutex_unlock(&dev->struct_mutex);
6658
e5510fac
JB		 6659 trace_i915_flip_request(intel_crtc->plane, obj);
6660
6b95a207 6661 return 0;
96b099fd 6662
8c9f3aaf
JB		 6663cleanup_pending:
6664 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6665 drm_gem_object_unreference(&work->old_fb_obj->base);
6666 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6667 mutex_unlock(&dev->struct_mutex);
6668
79158103 6669cleanup:
96b099fd
CW		 6670 spin_lock_irqsave(&dev->event_lock, flags);
6671 intel_crtc->unpin_work = NULL;
6672 spin_unlock_irqrestore(&dev->event_lock, flags);
6673
7317c75e
JB		 6674 drm_vblank_put(dev, intel_crtc->pipe);
6675free_work:
96b099fd
CW		 6676 kfree(work);
6677
6678 return ret;
6b95a207
KH		 6679}
6680
f6e5b160 6681static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 6682 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6683 .load_lut = intel_crtc_load_lut,
976f8a20 6684 .disable = intel_crtc_noop,
f6e5b160
CW		 6685};
6686
6ed0f796 6687bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 6688{
6ed0f796
DV		 6689 struct intel_encoder *other_encoder;
6690 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 6691
6ed0f796
DV		 6692 if (WARN_ON(!crtc))
6693 return false;
6694
6695 list_for_each_entry(other_encoder,
6696 &crtc->dev->mode_config.encoder_list,
6697 base.head) {
6698
6699 if (&other_encoder->new_crtc->base != crtc ||
6700 encoder == other_encoder)
6701 continue;
6702 else
6703 return true;
f47166d2
CW		 6704 }
6705
6ed0f796
DV		 6706 return false;
6707}
47f1c6c9 6708
50f56119
DV		 6709static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6710 struct drm_crtc *crtc)
6711{
6712 struct drm_device *dev;
6713 struct drm_crtc *tmp;
6714 int crtc_mask = 1;
47f1c6c9 6715
50f56119 6716 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 6717
50f56119 6718 dev = crtc->dev;
47f1c6c9 6719
50f56119
DV		 6720 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6721 if (tmp == crtc)
6722 break;
6723 crtc_mask <<= 1;
6724 }
47f1c6c9 6725
50f56119
DV		 6726 if (encoder->possible_crtcs & crtc_mask)
6727 return true;
6728 return false;
47f1c6c9 6729}
79e53945 6730
9a935856
DV		 6731/**
6732 * intel_modeset_update_staged_output_state
6733 *
6734 * Updates the staged output configuration state, e.g. after we've read out the
6735 * current hw state.
6736 */
6737static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 6738{
9a935856
DV		 6739 struct intel_encoder *encoder;
6740 struct intel_connector *connector;
f6e5b160 6741
9a935856
DV		 6742 list_for_each_entry(connector, &dev->mode_config.connector_list,
6743 base.head) {
6744 connector->new_encoder =
6745 to_intel_encoder(connector->base.encoder);
6746 }
f6e5b160 6747
9a935856
DV		 6748 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6749 base.head) {
6750 encoder->new_crtc =
6751 to_intel_crtc(encoder->base.crtc);
6752 }
f6e5b160
CW		 6753}
6754
9a935856
DV		 6755/**
6756 * intel_modeset_commit_output_state
6757 *
6758 * This function copies the stage display pipe configuration to the real one.
6759 */
6760static void intel_modeset_commit_output_state(struct drm_device *dev)
6761{
6762 struct intel_encoder *encoder;
6763 struct intel_connector *connector;
f6e5b160 6764
9a935856
DV		 6765 list_for_each_entry(connector, &dev->mode_config.connector_list,
6766 base.head) {
6767 connector->base.encoder = &connector->new_encoder->base;
6768 }
f6e5b160 6769
9a935856
DV		 6770 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6771 base.head) {
6772 encoder->base.crtc = &encoder->new_crtc->base;
6773 }
6774}
6775
7758a113
DV		 6776static struct drm_display_mode *
6777intel_modeset_adjusted_mode(struct drm_crtc *crtc,
6778 struct drm_display_mode *mode)
ee7b9f93 6779{
7758a113
DV		 6780 struct drm_device *dev = crtc->dev;
6781 struct drm_display_mode *adjusted_mode;
6782 struct drm_encoder_helper_funcs *encoder_funcs;
6783 struct intel_encoder *encoder;
ee7b9f93 6784
7758a113
DV		 6785 adjusted_mode = drm_mode_duplicate(dev, mode);
6786 if (!adjusted_mode)
6787 return ERR_PTR(-ENOMEM);
6788
6789 /* Pass our mode to the connectors and the CRTC to give them a chance to
6790 * adjust it according to limitations or connector properties, and also
6791 * a chance to reject the mode entirely.
6792 */
6793 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6794 base.head) {
6795
6796 if (&encoder->new_crtc->base != crtc)
6797 continue;
6798 encoder_funcs = encoder->base.helper_private;
6799 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
6800 adjusted_mode))) {
6801 DRM_DEBUG_KMS("Encoder fixup failed\n");
6802 goto fail;
6803 }
ee7b9f93
JB		 6804 }
6805
7758a113
DV		 6806 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
6807 DRM_DEBUG_KMS("CRTC fixup failed\n");
6808 goto fail;
ee7b9f93 6809 }
7758a113
DV		 6810 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6811
6812 return adjusted_mode;
6813fail:
6814 drm_mode_destroy(dev, adjusted_mode);
6815 return ERR_PTR(-EINVAL);
ee7b9f93
JB		 6816}
6817
e2e1ed41
DV		 6818/* Computes which crtcs are affected and sets the relevant bits in the mask. For
6819 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
6820static void
6821intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
6822 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 6823{
6824 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 6825 struct drm_device *dev = crtc->dev;
6826 struct intel_encoder *encoder;
6827 struct intel_connector *connector;
6828 struct drm_crtc *tmp_crtc;
79e53945 6829
e2e1ed41 6830 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 6831
e2e1ed41
DV		 6832 /* Check which crtcs have changed outputs connected to them, these need
6833 * to be part of the prepare_pipes mask. We don't (yet) support global
6834 * modeset across multiple crtcs, so modeset_pipes will only have one
6835 * bit set at most. */
6836 list_for_each_entry(connector, &dev->mode_config.connector_list,
6837 base.head) {
6838 if (connector->base.encoder == &connector->new_encoder->base)
6839 continue;
79e53945 6840
e2e1ed41
DV		 6841 if (connector->base.encoder) {
6842 tmp_crtc = connector->base.encoder->crtc;
6843
6844 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6845 }
6846
6847 if (connector->new_encoder)
6848 *prepare_pipes |=
6849 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 6850 }
6851
e2e1ed41
DV		 6852 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6853 base.head) {
6854 if (encoder->base.crtc == &encoder->new_crtc->base)
6855 continue;
6856
6857 if (encoder->base.crtc) {
6858 tmp_crtc = encoder->base.crtc;
6859
6860 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6861 }
6862
6863 if (encoder->new_crtc)
6864 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 6865 }
6866
e2e1ed41
DV		 6867 /* Check for any pipes that will be fully disabled ... */
6868 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6869 base.head) {
6870 bool used = false;
22fd0fab 6871
e2e1ed41
DV		 6872 /* Don't try to disable disabled crtcs. */
6873 if (!intel_crtc->base.enabled)
6874 continue;
7e7d76c3 6875
e2e1ed41
DV		 6876 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6877 base.head) {
6878 if (encoder->new_crtc == intel_crtc)
6879 used = true;
6880 }
6881
6882 if (!used)
6883 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 6884 }
6885
e2e1ed41
DV		 6886
6887 /* set_mode is also used to update properties on life display pipes. */
6888 intel_crtc = to_intel_crtc(crtc);
6889 if (crtc->enabled)
6890 *prepare_pipes |= 1 << intel_crtc->pipe;
6891
6892 /* We only support modeset on one single crtc, hence we need to do that
6893 * only for the passed in crtc iff we change anything else than just
6894 * disable crtcs.
6895 *
6896 * This is actually not true, to be fully compatible with the old crtc
6897 * helper we automatically disable _any_ output (i.e. doesn't need to be
6898 * connected to the crtc we're modesetting on) if it's disconnected.
6899 * Which is a rather nutty api (since changed the output configuration
6900 * without userspace's explicit request can lead to confusion), but
6901 * alas. Hence we currently need to modeset on all pipes we prepare. */
6902 if (*prepare_pipes)
6903 *modeset_pipes = *prepare_pipes;
6904
6905 /* ... and mask these out. */
6906 *modeset_pipes &= ~(*disable_pipes);
6907 *prepare_pipes &= ~(*disable_pipes);
6908}
6909
ea9d758d
DV		 6910static bool intel_crtc_in_use(struct drm_crtc *crtc)
6911{
6912 struct drm_encoder *encoder;
6913 struct drm_device *dev = crtc->dev;
6914
6915 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
6916 if (encoder->crtc == crtc)
6917 return true;
6918
6919 return false;
6920}
6921
6922static void
6923intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
6924{
6925 struct intel_encoder *intel_encoder;
6926 struct intel_crtc *intel_crtc;
6927 struct drm_connector *connector;
6928
6929 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
6930 base.head) {
6931 if (!intel_encoder->base.crtc)
6932 continue;
6933
6934 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
6935
6936 if (prepare_pipes & (1 << intel_crtc->pipe))
6937 intel_encoder->connectors_active = false;
6938 }
6939
6940 intel_modeset_commit_output_state(dev);
6941
6942 /* Update computed state. */
6943 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6944 base.head) {
6945 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
6946 }
6947
6948 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6949 if (!connector->encoder || !connector->encoder->crtc)
6950 continue;
6951
6952 intel_crtc = to_intel_crtc(connector->encoder->crtc);
6953
6954 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 6955 struct drm_property *dpms_property =
6956 dev->mode_config.dpms_property;
6957
ea9d758d 6958 connector->dpms = DRM_MODE_DPMS_ON;
68d34720
DV		 6959 drm_connector_property_set_value(connector,
6960 dpms_property,
6961 DRM_MODE_DPMS_ON);
ea9d758d
DV		 6962
6963 intel_encoder = to_intel_encoder(connector->encoder);
6964 intel_encoder->connectors_active = true;
6965 }
6966 }
6967
6968}
6969
25c5b266
DV		 6970#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
6971 list_for_each_entry((intel_crtc), \
6972 &(dev)->mode_config.crtc_list, \
6973 base.head) \
6974 if (mask & (1 <<(intel_crtc)->pipe)) \
6975
b980514c 6976void
8af6cf88
DV		 6977intel_modeset_check_state(struct drm_device *dev)
6978{
6979 struct intel_crtc *crtc;
6980 struct intel_encoder *encoder;
6981 struct intel_connector *connector;
6982
6983 list_for_each_entry(connector, &dev->mode_config.connector_list,
6984 base.head) {
6985 /* This also checks the encoder/connector hw state with the
6986 * ->get_hw_state callbacks. */
6987 intel_connector_check_state(connector);
6988
6989 WARN(&connector->new_encoder->base != connector->base.encoder,
6990 "connector's staged encoder doesn't match current encoder\n");
6991 }
6992
6993 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6994 base.head) {
6995 bool enabled = false;
6996 bool active = false;
6997 enum pipe pipe, tracked_pipe;
6998
6999 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7000 encoder->base.base.id,
7001 drm_get_encoder_name(&encoder->base));
7002
7003 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7004 "encoder's stage crtc doesn't match current crtc\n");
7005 WARN(encoder->connectors_active && !encoder->base.crtc,
7006 "encoder's active_connectors set, but no crtc\n");
7007
7008 list_for_each_entry(connector, &dev->mode_config.connector_list,
7009 base.head) {
7010 if (connector->base.encoder != &encoder->base)
7011 continue;
7012 enabled = true;
7013 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7014 active = true;
7015 }
7016 WARN(!!encoder->base.crtc != enabled,
7017 "encoder's enabled state mismatch "
7018 "(expected %i, found %i)\n",
7019 !!encoder->base.crtc, enabled);
7020 WARN(active && !encoder->base.crtc,
7021 "active encoder with no crtc\n");
7022
7023 WARN(encoder->connectors_active != active,
7024 "encoder's computed active state doesn't match tracked active state "
7025 "(expected %i, found %i)\n", active, encoder->connectors_active);
7026
7027 active = encoder->get_hw_state(encoder, &pipe);
7028 WARN(active != encoder->connectors_active,
7029 "encoder's hw state doesn't match sw tracking "
7030 "(expected %i, found %i)\n",
7031 encoder->connectors_active, active);
7032
7033 if (!encoder->base.crtc)
7034 continue;
7035
7036 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7037 WARN(active && pipe != tracked_pipe,
7038 "active encoder's pipe doesn't match"
7039 "(expected %i, found %i)\n",
7040 tracked_pipe, pipe);
7041
7042 }
7043
7044 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7045 base.head) {
7046 bool enabled = false;
7047 bool active = false;
7048
7049 DRM_DEBUG_KMS("[CRTC:%d]\n",
7050 crtc->base.base.id);
7051
7052 WARN(crtc->active && !crtc->base.enabled,
7053 "active crtc, but not enabled in sw tracking\n");
7054
7055 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7056 base.head) {
7057 if (encoder->base.crtc != &crtc->base)
7058 continue;
7059 enabled = true;
7060 if (encoder->connectors_active)
7061 active = true;
7062 }
7063 WARN(active != crtc->active,
7064 "crtc's computed active state doesn't match tracked active state "
7065 "(expected %i, found %i)\n", active, crtc->active);
7066 WARN(enabled != crtc->base.enabled,
7067 "crtc's computed enabled state doesn't match tracked enabled state "
7068 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7069
7070 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7071 }
7072}
7073
a6778b3c
DV		 7074bool intel_set_mode(struct drm_crtc *crtc,
7075 struct drm_display_mode *mode,
94352cf9 7076 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7077{
7078 struct drm_device *dev = crtc->dev;
dbf2b54e 7079 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7080 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
a6778b3c 7081 struct drm_encoder_helper_funcs *encoder_funcs;
a6778b3c 7082 struct drm_encoder *encoder;
25c5b266
DV		 7083 struct intel_crtc *intel_crtc;
7084 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7085 bool ret = true;
7086
e2e1ed41 7087 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7088 &prepare_pipes, &disable_pipes);
7089
7090 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7091 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7092
976f8a20
DV		 7093 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7094 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7095
a6778b3c
DV		 7096 saved_hwmode = crtc->hwmode;
7097 saved_mode = crtc->mode;
a6778b3c 7098
25c5b266
DV		 7099 /* Hack: Because we don't (yet) support global modeset on multiple
7100 * crtcs, we don't keep track of the new mode for more than one crtc.
7101 * Hence simply check whether any bit is set in modeset_pipes in all the
7102 * pieces of code that are not yet converted to deal with mutliple crtcs
7103 * changing their mode at the same time. */
7104 adjusted_mode = NULL;
7105 if (modeset_pipes) {
7106 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7107 if (IS_ERR(adjusted_mode)) {
7108 return false;
7109 }
25c5b266 7110 }
a6778b3c 7111
ea9d758d
DV		 7112 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7113 if (intel_crtc->base.enabled)
7114 dev_priv->display.crtc_disable(&intel_crtc->base);
7115 }
a6778b3c 7116
6c4c86f5
DV		 7117 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7118 * to set it here already despite that we pass it down the callchain.
7119 */
7120 if (modeset_pipes)
25c5b266 7121 crtc->mode = *mode;
7758a113 7122
ea9d758d
DV		 7123 /* Only after disabling all output pipelines that will be changed can we
7124 * update the the output configuration. */
7125 intel_modeset_update_state(dev, prepare_pipes);
7126
a6778b3c
DV		 7127 /* Set up the DPLL and any encoders state that needs to adjust or depend
7128 * on the DPLL.
7129 */
25c5b266
DV		 7130 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7131 ret = !intel_crtc_mode_set(&intel_crtc->base,
7132 mode, adjusted_mode,
7133 x, y, fb);
7134 if (!ret)
7135 goto done;
a6778b3c 7136
25c5b266 7137 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
a6778b3c 7138
25c5b266
DV		 7139 if (encoder->crtc != &intel_crtc->base)
7140 continue;
a6778b3c 7141
25c5b266
DV		 7142 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7143 encoder->base.id, drm_get_encoder_name(encoder),
7144 mode->base.id, mode->name);
7145 encoder_funcs = encoder->helper_private;
7146 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7147 }
a6778b3c
DV		 7148 }
7149
7150 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7151 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7152 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7153
25c5b266
DV		 7154 if (modeset_pipes) {
7155 /* Store real post-adjustment hardware mode. */
7156 crtc->hwmode = *adjusted_mode;
a6778b3c 7157
25c5b266
DV		 7158 /* Calculate and store various constants which
7159 * are later needed by vblank and swap-completion
7160 * timestamping. They are derived from true hwmode.
7161 */
7162 drm_calc_timestamping_constants(crtc);
7163 }
a6778b3c
DV		 7164
7165 /* FIXME: add subpixel order */
7166done:
7167 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7168 if (!ret && crtc->enabled) {
a6778b3c
DV		 7169 crtc->hwmode = saved_hwmode;
7170 crtc->mode = saved_mode;
8af6cf88
DV		 7171 } else {
7172 intel_modeset_check_state(dev);
a6778b3c
DV		 7173 }
7174
7175 return ret;
7176}
7177
25c5b266
DV		 7178#undef for_each_intel_crtc_masked
7179
d9e55608
DV		 7180static void intel_set_config_free(struct intel_set_config *config)
7181{
7182 if (!config)
7183 return;
7184
1aa4b628
DV		 7185 kfree(config->save_connector_encoders);
7186 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7187 kfree(config);
7188}
7189
85f9eb71
DV		 7190static int intel_set_config_save_state(struct drm_device *dev,
7191 struct intel_set_config *config)
7192{
85f9eb71
DV		 7193 struct drm_encoder *encoder;
7194 struct drm_connector *connector;
7195 int count;
7196
1aa4b628
DV		 7197 config->save_encoder_crtcs =
7198 kcalloc(dev->mode_config.num_encoder,
7199 sizeof(struct drm_crtc *), GFP_KERNEL);
7200 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7201 return -ENOMEM;
7202
1aa4b628
DV		 7203 config->save_connector_encoders =
7204 kcalloc(dev->mode_config.num_connector,
7205 sizeof(struct drm_encoder *), GFP_KERNEL);
7206 if (!config->save_connector_encoders)
85f9eb71
DV		 7207 return -ENOMEM;
7208
7209 /* Copy data. Note that driver private data is not affected.
7210 * Should anything bad happen only the expected state is
7211 * restored, not the drivers personal bookkeeping.
7212 */
85f9eb71
DV		 7213 count = 0;
7214 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7215 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7216 }
7217
7218 count = 0;
7219 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7220 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7221 }
7222
7223 return 0;
7224}
7225
7226static void intel_set_config_restore_state(struct drm_device *dev,
7227 struct intel_set_config *config)
7228{
9a935856
DV		 7229 struct intel_encoder *encoder;
7230 struct intel_connector *connector;
85f9eb71
DV		 7231 int count;
7232
85f9eb71 7233 count = 0;
9a935856
DV		 7234 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7235 encoder->new_crtc =
7236 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7237 }
7238
7239 count = 0;
9a935856
DV		 7240 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7241 connector->new_encoder =
7242 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7243 }
7244}
7245
5e2b584e
DV		 7246static void
7247intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7248 struct intel_set_config *config)
7249{
7250
7251 /* We should be able to check here if the fb has the same properties
7252 * and then just flip_or_move it */
7253 if (set->crtc->fb != set->fb) {
7254 /* If we have no fb then treat it as a full mode set */
7255 if (set->crtc->fb == NULL) {
7256 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7257 config->mode_changed = true;
7258 } else if (set->fb == NULL) {
7259 config->mode_changed = true;
7260 } else if (set->fb->depth != set->crtc->fb->depth) {
7261 config->mode_changed = true;
7262 } else if (set->fb->bits_per_pixel !=
7263 set->crtc->fb->bits_per_pixel) {
7264 config->mode_changed = true;
7265 } else
7266 config->fb_changed = true;
7267 }
7268
835c5873 7269 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7270 config->fb_changed = true;
7271
7272 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7273 DRM_DEBUG_KMS("modes are different, full mode set\n");
7274 drm_mode_debug_printmodeline(&set->crtc->mode);
7275 drm_mode_debug_printmodeline(set->mode);
7276 config->mode_changed = true;
7277 }
7278}
7279
2e431051 7280static int
9a935856
DV		 7281intel_modeset_stage_output_state(struct drm_device *dev,
7282 struct drm_mode_set *set,
7283 struct intel_set_config *config)
50f56119 7284{
85f9eb71 7285 struct drm_crtc *new_crtc;
9a935856
DV		 7286 struct intel_connector *connector;
7287 struct intel_encoder *encoder;
2e431051 7288 int count, ro;
50f56119 7289
9a935856
DV		 7290 /* The upper layers ensure that we either disabl a crtc or have a list
7291 * of connectors. For paranoia, double-check this. */
7292 WARN_ON(!set->fb && (set->num_connectors != 0));
7293 WARN_ON(set->fb && (set->num_connectors == 0));
7294
50f56119 7295 count = 0;
9a935856
DV		 7296 list_for_each_entry(connector, &dev->mode_config.connector_list,
7297 base.head) {
7298 /* Otherwise traverse passed in connector list and get encoders
7299 * for them. */
50f56119 7300 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7301 if (set->connectors[ro] == &connector->base) {
7302 connector->new_encoder = connector->encoder;
50f56119
DV		 7303 break;
7304 }
7305 }
7306
9a935856
DV		 7307 /* If we disable the crtc, disable all its connectors. Also, if
7308 * the connector is on the changing crtc but not on the new
7309 * connector list, disable it. */
7310 if ((!set->fb || ro == set->num_connectors) &&
7311 connector->base.encoder &&
7312 connector->base.encoder->crtc == set->crtc) {
7313 connector->new_encoder = NULL;
7314
7315 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7316 connector->base.base.id,
7317 drm_get_connector_name(&connector->base));
7318 }
7319
7320
7321 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7322 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7323 config->mode_changed = true;
50f56119 7324 }
9a935856
DV		 7325
7326 /* Disable all disconnected encoders. */
7327 if (connector->base.status == connector_status_disconnected)
7328 connector->new_encoder = NULL;
50f56119 7329 }
9a935856 7330 /* connector->new_encoder is now updated for all connectors. */
50f56119 7331
9a935856 7332 /* Update crtc of enabled connectors. */
50f56119 7333 count = 0;
9a935856
DV		 7334 list_for_each_entry(connector, &dev->mode_config.connector_list,
7335 base.head) {
7336 if (!connector->new_encoder)
50f56119
DV		 7337 continue;
7338
9a935856 7339 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7340
7341 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7342 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7343 new_crtc = set->crtc;
7344 }
7345
7346 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7347 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7348 new_crtc)) {
5e2b584e 7349 return -EINVAL;
50f56119 7350 }
9a935856
DV		 7351 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7352
7353 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7354 connector->base.base.id,
7355 drm_get_connector_name(&connector->base),
7356 new_crtc->base.id);
7357 }
7358
7359 /* Check for any encoders that needs to be disabled. */
7360 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7361 base.head) {
7362 list_for_each_entry(connector,
7363 &dev->mode_config.connector_list,
7364 base.head) {
7365 if (connector->new_encoder == encoder) {
7366 WARN_ON(!connector->new_encoder->new_crtc);
7367
7368 goto next_encoder;
7369 }
7370 }
7371 encoder->new_crtc = NULL;
7372next_encoder:
7373 /* Only now check for crtc changes so we don't miss encoders
7374 * that will be disabled. */
7375 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7376 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7377 config->mode_changed = true;
50f56119
DV		 7378 }
7379 }
9a935856 7380 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7381
2e431051
DV		 7382 return 0;
7383}
7384
7385static int intel_crtc_set_config(struct drm_mode_set *set)
7386{
7387 struct drm_device *dev;
2e431051
DV		 7388 struct drm_mode_set save_set;
7389 struct intel_set_config *config;
7390 int ret;
2e431051 7391
8d3e375e
DV		 7392 BUG_ON(!set);
7393 BUG_ON(!set->crtc);
7394 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 7395
7396 if (!set->mode)
7397 set->fb = NULL;
7398
431e50f7
DV		 7399 /* The fb helper likes to play gross jokes with ->mode_set_config.
7400 * Unfortunately the crtc helper doesn't do much at all for this case,
7401 * so we have to cope with this madness until the fb helper is fixed up. */
7402 if (set->fb && set->num_connectors == 0)
7403 return 0;
7404
2e431051
DV		 7405 if (set->fb) {
7406 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7407 set->crtc->base.id, set->fb->base.id,
7408 (int)set->num_connectors, set->x, set->y);
7409 } else {
7410 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 7411 }
7412
7413 dev = set->crtc->dev;
7414
7415 ret = -ENOMEM;
7416 config = kzalloc(sizeof(*config), GFP_KERNEL);
7417 if (!config)
7418 goto out_config;
7419
7420 ret = intel_set_config_save_state(dev, config);
7421 if (ret)
7422 goto out_config;
7423
7424 save_set.crtc = set->crtc;
7425 save_set.mode = &set->crtc->mode;
7426 save_set.x = set->crtc->x;
7427 save_set.y = set->crtc->y;
7428 save_set.fb = set->crtc->fb;
7429
7430 /* Compute whether we need a full modeset, only an fb base update or no
7431 * change at all. In the future we might also check whether only the
7432 * mode changed, e.g. for LVDS where we only change the panel fitter in
7433 * such cases. */
7434 intel_set_config_compute_mode_changes(set, config);
7435
9a935856 7436 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 7437 if (ret)
7438 goto fail;
7439
5e2b584e 7440 if (config->mode_changed) {
87f1faa6 7441 if (set->mode) {
50f56119
DV		 7442 DRM_DEBUG_KMS("attempting to set mode from"
7443 " userspace\n");
7444 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 7445 }
7446
7447 if (!intel_set_mode(set->crtc, set->mode,
7448 set->x, set->y, set->fb)) {
7449 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7450 set->crtc->base.id);
7451 ret = -EINVAL;
7452 goto fail;
7453 }
5e2b584e 7454 } else if (config->fb_changed) {
4f660f49 7455 ret = intel_pipe_set_base(set->crtc,
94352cf9 7456 set->x, set->y, set->fb);
50f56119
DV		 7457 }
7458
d9e55608
DV		 7459 intel_set_config_free(config);
7460
50f56119
DV		 7461 return 0;
7462
7463fail:
85f9eb71 7464 intel_set_config_restore_state(dev, config);
50f56119
DV		 7465
7466 /* Try to restore the config */
5e2b584e 7467 if (config->mode_changed &&
a6778b3c
DV		 7468 !intel_set_mode(save_set.crtc, save_set.mode,
7469 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 7470 DRM_ERROR("failed to restore config after modeset failure\n");
7471
d9e55608
DV		 7472out_config:
7473 intel_set_config_free(config);
50f56119
DV		 7474 return ret;
7475}
7476
f6e5b160 7477static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 7478 .cursor_set = intel_crtc_cursor_set,
7479 .cursor_move = intel_crtc_cursor_move,
7480 .gamma_set = intel_crtc_gamma_set,
50f56119 7481 .set_config = intel_crtc_set_config,
f6e5b160
CW		 7482 .destroy = intel_crtc_destroy,
7483 .page_flip = intel_crtc_page_flip,
7484};
7485
79f689aa
PZ		 7486static void intel_cpu_pll_init(struct drm_device *dev)
7487{
7488 if (IS_HASWELL(dev))
7489 intel_ddi_pll_init(dev);
7490}
7491
ee7b9f93
JB		 7492static void intel_pch_pll_init(struct drm_device *dev)
7493{
7494 drm_i915_private_t *dev_priv = dev->dev_private;
7495 int i;
7496
7497 if (dev_priv->num_pch_pll == 0) {
7498 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7499 return;
7500 }
7501
7502 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7503 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7504 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7505 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7506 }
7507}
7508
b358d0a6 7509static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7510{
22fd0fab 7511 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7512 struct intel_crtc *intel_crtc;
7513 int i;
7514
7515 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7516 if (intel_crtc == NULL)
7517 return;
7518
7519 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7520
7521 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7522 for (i = 0; i < 256; i++) {
7523 intel_crtc->lut_r[i] = i;
7524 intel_crtc->lut_g[i] = i;
7525 intel_crtc->lut_b[i] = i;
7526 }
7527
80824003
JB		 7528 /* Swap pipes & planes for FBC on pre-965 */
7529 intel_crtc->pipe = pipe;
7530 intel_crtc->plane = pipe;
e2e767ab 7531 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7532 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7533 intel_crtc->plane = !pipe;
80824003
JB		 7534 }
7535
22fd0fab
JB		 7536 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7537 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7538 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7539 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7540
5a354204 7541 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 7542
79e53945 7543 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 7544}
7545
08d7b3d1 7546int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7547 struct drm_file *file)
08d7b3d1 7548{
08d7b3d1 7549 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7550 struct drm_mode_object *drmmode_obj;
7551 struct intel_crtc *crtc;
08d7b3d1 7552
1cff8f6b
DV		 7553 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7554 return -ENODEV;
08d7b3d1 7555
c05422d5
DV		 7556 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7557 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7558
c05422d5 7559 if (!drmmode_obj) {
08d7b3d1
CW		 7560 DRM_ERROR("no such CRTC id\n");
7561 return -EINVAL;
7562 }
7563
c05422d5
DV		 7564 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7565 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7566
c05422d5 7567 return 0;
08d7b3d1
CW		 7568}
7569
66a9278e 7570static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 7571{
66a9278e
DV		 7572 struct drm_device *dev = encoder->base.dev;
7573 struct intel_encoder *source_encoder;
79e53945 7574 int index_mask = 0;
79e53945
JB		 7575 int entry = 0;
7576
66a9278e
DV		 7577 list_for_each_entry(source_encoder,
7578 &dev->mode_config.encoder_list, base.head) {
7579
7580 if (encoder == source_encoder)
79e53945 7581 index_mask |= (1 << entry);
66a9278e
DV		 7582
7583 /* Intel hw has only one MUX where enocoders could be cloned. */
7584 if (encoder->cloneable && source_encoder->cloneable)
7585 index_mask |= (1 << entry);
7586
79e53945
JB		 7587 entry++;
7588 }
4ef69c7a 7589
79e53945
JB		 7590 return index_mask;
7591}
7592
4d302442
CW		 7593static bool has_edp_a(struct drm_device *dev)
7594{
7595 struct drm_i915_private *dev_priv = dev->dev_private;
7596
7597 if (!IS_MOBILE(dev))
7598 return false;
7599
7600 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7601 return false;
7602
7603 if (IS_GEN5(dev) &&
7604 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7605 return false;
7606
7607 return true;
7608}
7609
79e53945
JB		 7610static void intel_setup_outputs(struct drm_device *dev)
7611{
725e30ad 7612 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7613 struct intel_encoder *encoder;
cb0953d7 7614 bool dpd_is_edp = false;
f3cfcba6 7615 bool has_lvds;
79e53945 7616
f3cfcba6 7617 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 7618 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7619 /* disable the panel fitter on everything but LVDS */
7620 I915_WRITE(PFIT_CONTROL, 0);
7621 }
79e53945 7622
bad720ff 7623 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7624 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7625
4d302442 7626 if (has_edp_a(dev))
ab9d7c30 7627 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 7628
cb0953d7 7629 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 7630 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 7631 }
7632
7633 intel_crt_init(dev);
7634
0e72a5b5
ED		 7635 if (IS_HASWELL(dev)) {
7636 int found;
7637
7638 /* Haswell uses DDI functions to detect digital outputs */
7639 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7640 /* DDI A only supports eDP */
7641 if (found)
7642 intel_ddi_init(dev, PORT_A);
7643
7644 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7645 * register */
7646 found = I915_READ(SFUSE_STRAP);
7647
7648 if (found & SFUSE_STRAP_DDIB_DETECTED)
7649 intel_ddi_init(dev, PORT_B);
7650 if (found & SFUSE_STRAP_DDIC_DETECTED)
7651 intel_ddi_init(dev, PORT_C);
7652 if (found & SFUSE_STRAP_DDID_DETECTED)
7653 intel_ddi_init(dev, PORT_D);
7654 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 7655 int found;
7656
30ad48b7 7657 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 7658 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 7659 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 7660 if (!found)
08d644ad 7661 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 7662 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 7663 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 7664 }
7665
7666 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 7667 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 7668
b708a1d5 7669 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 7670 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 7671
5eb08b69 7672 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 7673 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 7674
cb0953d7 7675 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 7676 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 7677 } else if (IS_VALLEYVIEW(dev)) {
7678 int found;
7679
19c03924
GB		 7680 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
7681 if (I915_READ(DP_C) & DP_DETECTED)
7682 intel_dp_init(dev, DP_C, PORT_C);
7683
4a87d65d
JB		 7684 if (I915_READ(SDVOB) & PORT_DETECTED) {
7685 /* SDVOB multiplex with HDMIB */
7686 found = intel_sdvo_init(dev, SDVOB, true);
7687 if (!found)
08d644ad 7688 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 7689 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 7690 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 7691 }
7692
7693 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 7694 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 7695
103a196f 7696 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7697 bool found = false;
7d57382e 7698
725e30ad 7699 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7700 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 7701 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 7702 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7703 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 7704 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 7705 }
27185ae1 7706
b01f2c3a
JB		 7707 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7708 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 7709 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 7710 }
725e30ad 7711 }
13520b05
KH		 7712
7713 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7714
b01f2c3a
JB		 7715 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7716 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 7717 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 7718 }
27185ae1
ML		 7719
7720 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7721
b01f2c3a
JB		 7722 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7723 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 7724 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 7725 }
7726 if (SUPPORTS_INTEGRATED_DP(dev)) {
7727 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 7728 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 7729 }
725e30ad 7730 }
27185ae1 7731
b01f2c3a
JB		 7732 if (SUPPORTS_INTEGRATED_DP(dev) &&
7733 (I915_READ(DP_D) & DP_DETECTED)) {
7734 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 7735 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 7736 }
bad720ff 7737 } else if (IS_GEN2(dev))
79e53945
JB		 7738 intel_dvo_init(dev);
7739
103a196f 7740 if (SUPPORTS_TV(dev))
79e53945
JB		 7741 intel_tv_init(dev);
7742
4ef69c7a
CW		 7743 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7744 encoder->base.possible_crtcs = encoder->crtc_mask;
7745 encoder->base.possible_clones =
66a9278e 7746 intel_encoder_clones(encoder);
79e53945 7747 }
47356eb6 7748
40579abe 7749 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 7750 ironlake_init_pch_refclk(dev);
79e53945
JB		 7751}
7752
7753static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7754{
7755 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7756
7757 drm_framebuffer_cleanup(fb);
05394f39 7758 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7759
7760 kfree(intel_fb);
7761}
7762
7763static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7764 struct drm_file *file,
79e53945
JB		 7765 unsigned int *handle)
7766{
7767 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7768 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7769
05394f39 7770 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7771}
7772
7773static const struct drm_framebuffer_funcs intel_fb_funcs = {
7774 .destroy = intel_user_framebuffer_destroy,
7775 .create_handle = intel_user_framebuffer_create_handle,
7776};
7777
38651674
DA		 7778int intel_framebuffer_init(struct drm_device *dev,
7779 struct intel_framebuffer *intel_fb,
308e5bcb 7780 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 7781 struct drm_i915_gem_object *obj)
79e53945 7782{
79e53945
JB		 7783 int ret;
7784
05394f39 7785 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7786 return -EINVAL;
7787
308e5bcb 7788 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 7789 return -EINVAL;
7790
308e5bcb 7791 switch (mode_cmd->pixel_format) {
04b3924d
VS		 7792 case DRM_FORMAT_RGB332:
7793 case DRM_FORMAT_RGB565:
7794 case DRM_FORMAT_XRGB8888:
b250da79 7795 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 7796 case DRM_FORMAT_ARGB8888:
7797 case DRM_FORMAT_XRGB2101010:
7798 case DRM_FORMAT_ARGB2101010:
308e5bcb 7799 /* RGB formats are common across chipsets */
b5626747 7800 break;
04b3924d
VS		 7801 case DRM_FORMAT_YUYV:
7802 case DRM_FORMAT_UYVY:
7803 case DRM_FORMAT_YVYU:
7804 case DRM_FORMAT_VYUY:
57cd6508
CW		 7805 break;
7806 default:
aca25848
ED		 7807 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7808 mode_cmd->pixel_format);
57cd6508
CW		 7809 return -EINVAL;
7810 }
7811
79e53945
JB		 7812 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7813 if (ret) {
7814 DRM_ERROR("framebuffer init failed %d\n", ret);
7815 return ret;
7816 }
7817
7818 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7819 intel_fb->obj = obj;
79e53945
JB		 7820 return 0;
7821}
7822
79e53945
JB		 7823static struct drm_framebuffer *
7824intel_user_framebuffer_create(struct drm_device *dev,
7825 struct drm_file *filp,
308e5bcb 7826 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 7827{
05394f39 7828 struct drm_i915_gem_object *obj;
79e53945 7829
308e5bcb
JB		 7830 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7831 mode_cmd->handles[0]));
c8725226 7832 if (&obj->base == NULL)
cce13ff7 7833 return ERR_PTR(-ENOENT);
79e53945 7834
d2dff872 7835 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7836}
7837
79e53945 7838static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7839 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7840 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7841};
7842
e70236a8
JB		 7843/* Set up chip specific display functions */
7844static void intel_init_display(struct drm_device *dev)
7845{
7846 struct drm_i915_private *dev_priv = dev->dev_private;
7847
7848 /* We always want a DPMS function */
f564048e 7849 if (HAS_PCH_SPLIT(dev)) {
f564048e 7850 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 7851 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7852 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 7853 dev_priv->display.off = ironlake_crtc_off;
17638cd6 7854 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 7855 } else {
f564048e 7856 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 7857 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7858 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 7859 dev_priv->display.off = i9xx_crtc_off;
17638cd6 7860 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 7861 }
e70236a8 7862
e70236a8 7863 /* Returns the core display clock speed */
25eb05fc
JB		 7864 if (IS_VALLEYVIEW(dev))
7865 dev_priv->display.get_display_clock_speed =
7866 valleyview_get_display_clock_speed;
7867 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 7868 dev_priv->display.get_display_clock_speed =
7869 i945_get_display_clock_speed;
7870 else if (IS_I915G(dev))
7871 dev_priv->display.get_display_clock_speed =
7872 i915_get_display_clock_speed;
f2b115e6 7873 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7874 dev_priv->display.get_display_clock_speed =
7875 i9xx_misc_get_display_clock_speed;
7876 else if (IS_I915GM(dev))
7877 dev_priv->display.get_display_clock_speed =
7878 i915gm_get_display_clock_speed;
7879 else if (IS_I865G(dev))
7880 dev_priv->display.get_display_clock_speed =
7881 i865_get_display_clock_speed;
f0f8a9ce 7882 else if (IS_I85X(dev))
e70236a8
JB		 7883 dev_priv->display.get_display_clock_speed =
7884 i855_get_display_clock_speed;
7885 else /* 852, 830 */
7886 dev_priv->display.get_display_clock_speed =
7887 i830_get_display_clock_speed;
7888
7f8a8569 7889 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 7890 if (IS_GEN5(dev)) {
674cf967 7891 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 7892 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 7893 } else if (IS_GEN6(dev)) {
674cf967 7894 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 7895 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 7896 } else if (IS_IVYBRIDGE(dev)) {
7897 /* FIXME: detect B0+ stepping and use auto training */
7898 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 7899 dev_priv->display.write_eld = ironlake_write_eld;
c82e4d26
ED		 7900 } else if (IS_HASWELL(dev)) {
7901 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 7902 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 7903 } else
7904 dev_priv->display.update_wm = NULL;
6067aaea 7905 } else if (IS_G4X(dev)) {
e0dac65e 7906 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 7907 }
8c9f3aaf
JB		 7908
7909 /* Default just returns -ENODEV to indicate unsupported */
7910 dev_priv->display.queue_flip = intel_default_queue_flip;
7911
7912 switch (INTEL_INFO(dev)->gen) {
7913 case 2:
7914 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7915 break;
7916
7917 case 3:
7918 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7919 break;
7920
7921 case 4:
7922 case 5:
7923 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7924 break;
7925
7926 case 6:
7927 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7928 break;
7c9017e5
JB		 7929 case 7:
7930 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7931 break;
8c9f3aaf 7932 }
e70236a8
JB		 7933}
7934
b690e96c
JB		 7935/*
7936 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7937 * resume, or other times. This quirk makes sure that's the case for
7938 * affected systems.
7939 */
0206e353 7940static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 7941{
7942 struct drm_i915_private *dev_priv = dev->dev_private;
7943
7944 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 7945 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 7946}
7947
435793df
KP		 7948/*
7949 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7950 */
7951static void quirk_ssc_force_disable(struct drm_device *dev)
7952{
7953 struct drm_i915_private *dev_priv = dev->dev_private;
7954 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 7955 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 7956}
7957
4dca20ef 7958/*
5a15ab5b
CE		 7959 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7960 * brightness value
4dca20ef
CE		 7961 */
7962static void quirk_invert_brightness(struct drm_device *dev)
7963{
7964 struct drm_i915_private *dev_priv = dev->dev_private;
7965 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 7966 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 7967}
7968
b690e96c
JB		 7969struct intel_quirk {
7970 int device;
7971 int subsystem_vendor;
7972 int subsystem_device;
7973 void (*hook)(struct drm_device *dev);
7974};
7975
c43b5634 7976static struct intel_quirk intel_quirks[] = {
b690e96c 7977 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 7978 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 7979
b690e96c
JB		 7980 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7981 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7982
b690e96c
JB		 7983 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7984 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7985
7986 /* 855 & before need to leave pipe A & dpll A up */
7987 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7988 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 7989 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 7990
7991 /* Lenovo U160 cannot use SSC on LVDS */
7992 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 7993
7994 /* Sony Vaio Y cannot use SSC on LVDS */
7995 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 7996
7997 /* Acer Aspire 5734Z must invert backlight brightness */
7998 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 7999};
8000
8001static void intel_init_quirks(struct drm_device *dev)
8002{
8003 struct pci_dev *d = dev->pdev;
8004 int i;
8005
8006 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8007 struct intel_quirk *q = &intel_quirks[i];
8008
8009 if (d->device == q->device &&
8010 (d->subsystem_vendor == q->subsystem_vendor ||
8011 q->subsystem_vendor == PCI_ANY_ID) &&
8012 (d->subsystem_device == q->subsystem_device ||
8013 q->subsystem_device == PCI_ANY_ID))
8014 q->hook(dev);
8015 }
8016}
8017
9cce37f4
JB		 8018/* Disable the VGA plane that we never use */
8019static void i915_disable_vga(struct drm_device *dev)
8020{
8021 struct drm_i915_private *dev_priv = dev->dev_private;
8022 u8 sr1;
8023 u32 vga_reg;
8024
8025 if (HAS_PCH_SPLIT(dev))
8026 vga_reg = CPU_VGACNTRL;
8027 else
8028 vga_reg = VGACNTRL;
8029
8030 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8031 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8032 sr1 = inb(VGA_SR_DATA);
8033 outb(sr1 | 1<<5, VGA_SR_DATA);
8034 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8035 udelay(300);
8036
8037 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8038 POSTING_READ(vga_reg);
8039}
8040
f817586c
DV		 8041void intel_modeset_init_hw(struct drm_device *dev)
8042{
0232e927
ED		 8043 /* We attempt to init the necessary power wells early in the initialization
8044 * time, so the subsystems that expect power to be enabled can work.
8045 */
8046 intel_init_power_wells(dev);
8047
a8f78b58
ED		 8048 intel_prepare_ddi(dev);
8049
f817586c
DV		 8050 intel_init_clock_gating(dev);
8051
79f5b2c7 8052 mutex_lock(&dev->struct_mutex);
8090c6b9 8053 intel_enable_gt_powersave(dev);
79f5b2c7 8054 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8055}
8056
79e53945
JB		 8057void intel_modeset_init(struct drm_device *dev)
8058{
652c393a 8059 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8060 int i, ret;
79e53945
JB		 8061
8062 drm_mode_config_init(dev);
8063
8064 dev->mode_config.min_width = 0;
8065 dev->mode_config.min_height = 0;
8066
019d96cb
DA		 8067 dev->mode_config.preferred_depth = 24;
8068 dev->mode_config.prefer_shadow = 1;
8069
e6ecefaa 8070 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8071
b690e96c
JB		 8072 intel_init_quirks(dev);
8073
1fa61106
ED		 8074 intel_init_pm(dev);
8075
e70236a8
JB		 8076 intel_init_display(dev);
8077
a6c45cf0
CW		 8078 if (IS_GEN2(dev)) {
8079 dev->mode_config.max_width = 2048;
8080 dev->mode_config.max_height = 2048;
8081 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8082 dev->mode_config.max_width = 4096;
8083 dev->mode_config.max_height = 4096;
79e53945 8084 } else {
a6c45cf0
CW		 8085 dev->mode_config.max_width = 8192;
8086 dev->mode_config.max_height = 8192;
79e53945 8087 }
dd2757f8 8088 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8089
28c97730 8090 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8091 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8092
a3524f1b 8093 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8094 intel_crtc_init(dev, i);
00c2064b
JB		 8095 ret = intel_plane_init(dev, i);
8096 if (ret)
8097 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8098 }
8099
79f689aa 8100 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8101 intel_pch_pll_init(dev);
8102
9cce37f4
JB		 8103 /* Just disable it once at startup */
8104 i915_disable_vga(dev);
79e53945 8105 intel_setup_outputs(dev);
2c7111db
CW		 8106}
8107
24929352
DV		 8108static void
8109intel_connector_break_all_links(struct intel_connector *connector)
8110{
8111 connector->base.dpms = DRM_MODE_DPMS_OFF;
8112 connector->base.encoder = NULL;
8113 connector->encoder->connectors_active = false;
8114 connector->encoder->base.crtc = NULL;
8115}
8116
7fad798e
DV		 8117static void intel_enable_pipe_a(struct drm_device *dev)
8118{
8119 struct intel_connector *connector;
8120 struct drm_connector *crt = NULL;
8121 struct intel_load_detect_pipe load_detect_temp;
8122
8123 /* We can't just switch on the pipe A, we need to set things up with a
8124 * proper mode and output configuration. As a gross hack, enable pipe A
8125 * by enabling the load detect pipe once. */
8126 list_for_each_entry(connector,
8127 &dev->mode_config.connector_list,
8128 base.head) {
8129 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8130 crt = &connector->base;
8131 break;
8132 }
8133 }
8134
8135 if (!crt)
8136 return;
8137
8138 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8139 intel_release_load_detect_pipe(crt, &load_detect_temp);
8140
8141
8142}
8143
24929352
DV		 8144static void intel_sanitize_crtc(struct intel_crtc *crtc)
8145{
8146 struct drm_device *dev = crtc->base.dev;
8147 struct drm_i915_private *dev_priv = dev->dev_private;
8148 u32 reg, val;
8149
24929352
DV		 8150 /* Clear any frame start delays used for debugging left by the BIOS */
8151 reg = PIPECONF(crtc->pipe);
8152 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8153
8154 /* We need to sanitize the plane -> pipe mapping first because this will
8155 * disable the crtc (and hence change the state) if it is wrong. */
8156 if (!HAS_PCH_SPLIT(dev)) {
8157 struct intel_connector *connector;
8158 bool plane;
8159
8160 reg = DSPCNTR(crtc->plane);
8161 val = I915_READ(reg);
8162
8163 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
8164 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8165 goto ok;
8166
8167 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8168 crtc->base.base.id);
8169
8170 /* Pipe has the wrong plane attached and the plane is active.
8171 * Temporarily change the plane mapping and disable everything
8172 * ... */
8173 plane = crtc->plane;
8174 crtc->plane = !plane;
8175 dev_priv->display.crtc_disable(&crtc->base);
8176 crtc->plane = plane;
8177
8178 /* ... and break all links. */
8179 list_for_each_entry(connector, &dev->mode_config.connector_list,
8180 base.head) {
8181 if (connector->encoder->base.crtc != &crtc->base)
8182 continue;
8183
8184 intel_connector_break_all_links(connector);
8185 }
8186
8187 WARN_ON(crtc->active);
8188 crtc->base.enabled = false;
8189 }
8190ok:
8191
7fad798e
DV		 8192 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8193 crtc->pipe == PIPE_A && !crtc->active) {
8194 /* BIOS forgot to enable pipe A, this mostly happens after
8195 * resume. Force-enable the pipe to fix this, the update_dpms
8196 * call below we restore the pipe to the right state, but leave
8197 * the required bits on. */
8198 intel_enable_pipe_a(dev);
8199 }
8200
24929352
DV		 8201 /* Adjust the state of the output pipe according to whether we
8202 * have active connectors/encoders. */
8203 intel_crtc_update_dpms(&crtc->base);
8204
8205 if (crtc->active != crtc->base.enabled) {
8206 struct intel_encoder *encoder;
8207
8208 /* This can happen either due to bugs in the get_hw_state
8209 * functions or because the pipe is force-enabled due to the
8210 * pipe A quirk. */
8211 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8212 crtc->base.base.id,
8213 crtc->base.enabled ? "enabled" : "disabled",
8214 crtc->active ? "enabled" : "disabled");
8215
8216 crtc->base.enabled = crtc->active;
8217
8218 /* Because we only establish the connector -> encoder ->
8219 * crtc links if something is active, this means the
8220 * crtc is now deactivated. Break the links. connector
8221 * -> encoder links are only establish when things are
8222 * actually up, hence no need to break them. */
8223 WARN_ON(crtc->active);
8224
8225 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8226 WARN_ON(encoder->connectors_active);
8227 encoder->base.crtc = NULL;
8228 }
8229 }
8230}
8231
8232static void intel_sanitize_encoder(struct intel_encoder *encoder)
8233{
8234 struct intel_connector *connector;
8235 struct drm_device *dev = encoder->base.dev;
8236
8237 /* We need to check both for a crtc link (meaning that the
8238 * encoder is active and trying to read from a pipe) and the
8239 * pipe itself being active. */
8240 bool has_active_crtc = encoder->base.crtc &&
8241 to_intel_crtc(encoder->base.crtc)->active;
8242
8243 if (encoder->connectors_active && !has_active_crtc) {
8244 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8245 encoder->base.base.id,
8246 drm_get_encoder_name(&encoder->base));
8247
8248 /* Connector is active, but has no active pipe. This is
8249 * fallout from our resume register restoring. Disable
8250 * the encoder manually again. */
8251 if (encoder->base.crtc) {
8252 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8253 encoder->base.base.id,
8254 drm_get_encoder_name(&encoder->base));
8255 encoder->disable(encoder);
8256 }
8257
8258 /* Inconsistent output/port/pipe state happens presumably due to
8259 * a bug in one of the get_hw_state functions. Or someplace else
8260 * in our code, like the register restore mess on resume. Clamp
8261 * things to off as a safer default. */
8262 list_for_each_entry(connector,
8263 &dev->mode_config.connector_list,
8264 base.head) {
8265 if (connector->encoder != encoder)
8266 continue;
8267
8268 intel_connector_break_all_links(connector);
8269 }
8270 }
8271 /* Enabled encoders without active connectors will be fixed in
8272 * the crtc fixup. */
8273}
8274
8275/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8276 * and i915 state tracking structures. */
8277void intel_modeset_setup_hw_state(struct drm_device *dev)
8278{
8279 struct drm_i915_private *dev_priv = dev->dev_private;
8280 enum pipe pipe;
8281 u32 tmp;
8282 struct intel_crtc *crtc;
8283 struct intel_encoder *encoder;
8284 struct intel_connector *connector;
8285
8286 for_each_pipe(pipe) {
8287 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8288
8289 tmp = I915_READ(PIPECONF(pipe));
8290 if (tmp & PIPECONF_ENABLE)
8291 crtc->active = true;
8292 else
8293 crtc->active = false;
8294
8295 crtc->base.enabled = crtc->active;
8296
8297 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8298 crtc->base.base.id,
8299 crtc->active ? "enabled" : "disabled");
8300 }
8301
8302 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8303 base.head) {
8304 pipe = 0;
8305
8306 if (encoder->get_hw_state(encoder, &pipe)) {
8307 encoder->base.crtc =
8308 dev_priv->pipe_to_crtc_mapping[pipe];
8309 } else {
8310 encoder->base.crtc = NULL;
8311 }
8312
8313 encoder->connectors_active = false;
8314 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8315 encoder->base.base.id,
8316 drm_get_encoder_name(&encoder->base),
8317 encoder->base.crtc ? "enabled" : "disabled",
8318 pipe);
8319 }
8320
8321 list_for_each_entry(connector, &dev->mode_config.connector_list,
8322 base.head) {
8323 if (connector->get_hw_state(connector)) {
8324 connector->base.dpms = DRM_MODE_DPMS_ON;
8325 connector->encoder->connectors_active = true;
8326 connector->base.encoder = &connector->encoder->base;
8327 } else {
8328 connector->base.dpms = DRM_MODE_DPMS_OFF;
8329 connector->base.encoder = NULL;
8330 }
8331 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8332 connector->base.base.id,
8333 drm_get_connector_name(&connector->base),
8334 connector->base.encoder ? "enabled" : "disabled");
8335 }
8336
8337 /* HW state is read out, now we need to sanitize this mess. */
8338 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8339 base.head) {
8340 intel_sanitize_encoder(encoder);
8341 }
8342
8343 for_each_pipe(pipe) {
8344 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8345 intel_sanitize_crtc(crtc);
8346 }
9a935856
DV		 8347
8348 intel_modeset_update_staged_output_state(dev);
8af6cf88
DV		 8349
8350 intel_modeset_check_state(dev);
24929352
DV		 8351}
8352
2c7111db
CW		 8353void intel_modeset_gem_init(struct drm_device *dev)
8354{
1833b134 8355 intel_modeset_init_hw(dev);
02e792fb
DV		 8356
8357 intel_setup_overlay(dev);
24929352
DV		 8358
8359 intel_modeset_setup_hw_state(dev);
79e53945
JB		 8360}
8361
8362void intel_modeset_cleanup(struct drm_device *dev)
8363{
652c393a
JB		 8364 struct drm_i915_private *dev_priv = dev->dev_private;
8365 struct drm_crtc *crtc;
8366 struct intel_crtc *intel_crtc;
8367
f87ea761 8368 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8369 mutex_lock(&dev->struct_mutex);
8370
723bfd70
JB		 8371 intel_unregister_dsm_handler();
8372
8373
652c393a
JB		 8374 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8375 /* Skip inactive CRTCs */
8376 if (!crtc->fb)
8377 continue;
8378
8379 intel_crtc = to_intel_crtc(crtc);
3dec0095 8380 intel_increase_pllclock(crtc);
652c393a
JB		 8381 }
8382
973d04f9 8383 intel_disable_fbc(dev);
e70236a8 8384
8090c6b9 8385 intel_disable_gt_powersave(dev);
0cdab21f 8386
930ebb46
DV		 8387 ironlake_teardown_rc6(dev);
8388
57f350b6
JB		 8389 if (IS_VALLEYVIEW(dev))
8390 vlv_init_dpio(dev);
8391
69341a5e
KH		 8392 mutex_unlock(&dev->struct_mutex);
8393
6c0d9350
DV		 8394 /* Disable the irq before mode object teardown, for the irq might
8395 * enqueue unpin/hotplug work. */
8396 drm_irq_uninstall(dev);
8397 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 8398 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 8399
1630fe75
CW		 8400 /* flush any delayed tasks or pending work */
8401 flush_scheduled_work();
8402
79e53945
JB		 8403 drm_mode_config_cleanup(dev);
8404}
8405
f1c79df3
ZW		 8406/*
8407 * Return which encoder is currently attached for connector.
8408 */
df0e9248 8409struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8410{
df0e9248
CW		 8411 return &intel_attached_encoder(connector)->base;
8412}
f1c79df3 8413
df0e9248
CW		 8414void intel_connector_attach_encoder(struct intel_connector *connector,
8415 struct intel_encoder *encoder)
8416{
8417 connector->encoder = encoder;
8418 drm_mode_connector_attach_encoder(&connector->base,
8419 &encoder->base);
79e53945 8420}
28d52043
DA		 8421
8422/*
8423 * set vga decode state - true == enable VGA decode
8424 */
8425int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8426{
8427 struct drm_i915_private *dev_priv = dev->dev_private;
8428 u16 gmch_ctrl;
8429
8430 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8431 if (state)
8432 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8433 else
8434 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8435 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8436 return 0;
8437}
c4a1d9e4
CW		 8438
8439#ifdef CONFIG_DEBUG_FS
8440#include <linux/seq_file.h>
8441
8442struct intel_display_error_state {
8443 struct intel_cursor_error_state {
8444 u32 control;
8445 u32 position;
8446 u32 base;
8447 u32 size;
52331309 8448 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 8449
8450 struct intel_pipe_error_state {
8451 u32 conf;
8452 u32 source;
8453
8454 u32 htotal;
8455 u32 hblank;
8456 u32 hsync;
8457 u32 vtotal;
8458 u32 vblank;
8459 u32 vsync;
52331309 8460 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 8461
8462 struct intel_plane_error_state {
8463 u32 control;
8464 u32 stride;
8465 u32 size;
8466 u32 pos;
8467 u32 addr;
8468 u32 surface;
8469 u32 tile_offset;
52331309 8470 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 8471};
8472
8473struct intel_display_error_state *
8474intel_display_capture_error_state(struct drm_device *dev)
8475{
0206e353 8476 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8477 struct intel_display_error_state *error;
8478 int i;
8479
8480 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8481 if (error == NULL)
8482 return NULL;
8483
52331309 8484 for_each_pipe(i) {
c4a1d9e4
CW		 8485 error->cursor[i].control = I915_READ(CURCNTR(i));
8486 error->cursor[i].position = I915_READ(CURPOS(i));
8487 error->cursor[i].base = I915_READ(CURBASE(i));
8488
8489 error->plane[i].control = I915_READ(DSPCNTR(i));
8490 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8491 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 8492 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 8493 error->plane[i].addr = I915_READ(DSPADDR(i));
8494 if (INTEL_INFO(dev)->gen >= 4) {
8495 error->plane[i].surface = I915_READ(DSPSURF(i));
8496 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8497 }
8498
8499 error->pipe[i].conf = I915_READ(PIPECONF(i));
8500 error->pipe[i].source = I915_READ(PIPESRC(i));
8501 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8502 error->pipe[i].hblank = I915_READ(HBLANK(i));
8503 error->pipe[i].hsync = I915_READ(HSYNC(i));
8504 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8505 error->pipe[i].vblank = I915_READ(VBLANK(i));
8506 error->pipe[i].vsync = I915_READ(VSYNC(i));
8507 }
8508
8509 return error;
8510}
8511
8512void
8513intel_display_print_error_state(struct seq_file *m,
8514 struct drm_device *dev,
8515 struct intel_display_error_state *error)
8516{
52331309 8517 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8518 int i;
8519
52331309
DL		 8520 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8521 for_each_pipe(i) {
c4a1d9e4
CW		 8522 seq_printf(m, "Pipe [%d]:\n", i);
8523 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8524 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8525 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8526 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8527 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8528 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8529 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8530 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8531
8532 seq_printf(m, "Plane [%d]:\n", i);
8533 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8534 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8535 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8536 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8537 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8538 if (INTEL_INFO(dev)->gen >= 4) {
8539 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8540 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8541 }
8542
8543 seq_printf(m, "Cursor [%d]:\n", i);
8544 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8545 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8546 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8547 }
8548}
8549#endif
Linux kernel - Deliverables
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