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ubsan: nds32: left shift cannot be represented in type 'int'
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e46d79a7
AM		 12019-12-17 Alan Modra <amodra@gmail.com>
2
3 * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
4 (print_insn_nds32): Use uint64_t for "given" and "given1".
5
5b660084
AM		 62019-12-17 Alan Modra <amodra@gmail.com>
7
8 * tic80-dis.c: Delete file.
9 * tic80-opc.c: Delete file.
10 * disassemble.c: Remove tic80 support.
11 * disassemble.h: Likewise.
12 * Makefile.am: Likewise.
13 * configure.ac: Likewise.
14 * Makefile.in: Regenerate.
15 * configure: Regenerate.
16 * po/POTFILES.in: Regenerate.
17
62e65990
AM		 182019-12-17 Alan Modra <amodra@gmail.com>
19
20 * bpf-ibld.c: Regenerate.
21
f81e7e2d
AM		 222019-12-16 Alan Modra <amodra@gmail.com>
23
24 * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without
25 conditional.
26 (aarch64_ext_imm): Avoid signed overflow.
27
488d02fe
AM		 282019-12-16 Alan Modra <amodra@gmail.com>
29
30 * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
31
8a92faab
AM		 322019-12-16 Alan Modra <amodra@gmail.com>
33
34 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
35
e6ced26a
AM		 362019-12-16 Alan Modra <amodra@gmail.com>
37
38 * xstormy16-ibld.c: Regenerate.
39
84e098cd
AM		 402019-12-16 Alan Modra <amodra@gmail.com>
41
42 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
43 value adjustment so that it doesn't affect reg field too.
44
36bd8ea7
AM		 452019-12-16 Alan Modra <amodra@gmail.com>
46
47 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
48 (get_number_of_operands, getargtype, getbits, getregname),
49 (getcopregname, getprocregname, gettrapstring, getcinvstring),
50 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
51 (powerof2, match_opcode, make_instruction, print_arguments),
52 (print_arg): Delete forward declarations, moving static to..
53 (getregname, getcopregname, getregliststring): ..these definitions.
54 (build_mask): Return unsigned int mask.
55 (match_opcode): Use unsigned int vars.
56
cedfc774
AM		 572019-12-16 Alan Modra <amodra@gmail.com>
58
59 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
60
4bdb25fe
AM		 612019-12-16 Alan Modra <amodra@gmail.com>
62
63 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
64 (struct objdump_disasm_info): Delete.
65 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
66 N32_IMMS to unsigned before shifting left.
67
cf950fd4
AM		 682019-12-16 Alan Modra <amodra@gmail.com>
69
70 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
71 (print_insn_moxie): Remove unnecessary cast.
72
967354c3
AM		 732019-12-12 Alan Modra <amodra@gmail.com>
74
75 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
76 mask.
77
1d61b032
AM		 782019-12-11 Alan Modra <amodra@gmail.com>
79
80 * arc-dis.c (BITS): Don't truncate high bits with shifts.
81 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
82 * tic54x-dis.c (print_instruction): Likewise.
83 * tilegx-opc.c (parse_insn_tilegx): Likewise.
84 * tilepro-opc.c (parse_insn_tilepro): Likewise.
85 * visium-dis.c (disassem_class0): Likewise.
86 * pdp11-dis.c (sign_extend): Likewise.
87 (SIGN_BITS): Delete.
88 * epiphany-ibld.c: Regenerate.
89 * lm32-ibld.c: Regenerate.
90 * m32c-ibld.c: Regenerate.
91
5afa80e9
AM		 922019-12-11 Alan Modra <amodra@gmail.com>
93
94 * ns32k-dis.c (sign_extend): Correct last patch.
95
5c05618a
AM		 962019-12-11 Alan Modra <amodra@gmail.com>
97
98 * vax-dis.c (NEXTLONG): Avoid signed overflow.
99
2a81ccbb
AM		 1002019-12-11 Alan Modra <amodra@gmail.com>
101
102 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
103 sign extend using shifts.
104
b84f6152
AM		 1052019-12-11 Alan Modra <amodra@gmail.com>
106
107 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
108
66152f16
AM		 1092019-12-11 Alan Modra <amodra@gmail.com>
110
111 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
112 on NULL registertable entry.
113 (tic4x_hash_opcode): Use unsigned arithmetic.
114
205c426a
AM		 1152019-12-11 Alan Modra <amodra@gmail.com>
116
117 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
118
fb4cb4e2
AM		 1192019-12-11 Alan Modra <amodra@gmail.com>
120
121 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
122 (bit_extract_simple, sign_extend): Likewise.
123
96f1f604
AM		 1242019-12-11 Alan Modra <amodra@gmail.com>
125
126 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
127
8c9b4171
AM		 1282019-12-11 Alan Modra <amodra@gmail.com>
129
130 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
131
334175b6
AM		 1322019-12-11 Alan Modra <amodra@gmail.com>
133
134 * m68k-dis.c (COERCE32): Cast value first.
135 (NEXTLONG, NEXTULONG): Avoid signed overflow.
136
f8a87c78
AM		 1372019-12-11 Alan Modra <amodra@gmail.com>
138
139 * h8300-dis.c (extract_immediate): Avoid signed overflow.
140 (bfd_h8_disassemble): Likewise.
141
159653d8
AM		 1422019-12-11 Alan Modra <amodra@gmail.com>
143
144 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
145 past end of operands array.
146
d93bba9e
AM		 1472019-12-11 Alan Modra <amodra@gmail.com>
148
149 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
150 overflow when collecting bytes of a number.
151
c202f69e
AM		 1522019-12-11 Alan Modra <amodra@gmail.com>
153
154 * cris-dis.c (print_with_operands): Avoid signed integer
155 overflow when collecting bytes of a 32-bit integer.
156
0ef562a4
AM		 1572019-12-11 Alan Modra <amodra@gmail.com>
158
159 * cr16-dis.c (EXTRACT, SBM): Rewrite.
160 (cr16_match_opcode): Delete duplicate bcond test.
161
2fd2b153
AM		 1622019-12-11 Alan Modra <amodra@gmail.com>
163
164 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
165 (SIGNBIT): New.
166 (MASKBITS, SIGNEXTEND): Rewrite.
167 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
168 unsigned arithmetic, instead assign result of SIGNEXTEND back
169 to x.
170 (fmtconst_val): Use 1u in shift expression.
171
a11db3e9
AM		 1722019-12-11 Alan Modra <amodra@gmail.com>
173
174 * arc-dis.c (find_format_from_table): Use ull constant when
175 shifting by up to 32.
176
9d48687b
AM		 1772019-12-11 Alan Modra <amodra@gmail.com>
178
179 PR 25270
180 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
181 false when field is zero for sve_size_tsz_bhs.
182
b8e61daa
AM		 1832019-12-11 Alan Modra <amodra@gmail.com>
184
185 * epiphany-ibld.c: Regenerate.
186
20135676
AM		 1872019-12-10 Alan Modra <amodra@gmail.com>
188
189 PR 24960
190 * disassemble.c (disassemble_free_target): New function.
191
103ebbc3
AM		 1922019-12-10 Alan Modra <amodra@gmail.com>
193
194 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
195 * disassemble.c (disassemble_init_for_target): Likewise.
196 * bpf-dis.c: Regenerate.
197 * epiphany-dis.c: Regenerate.
198 * fr30-dis.c: Regenerate.
199 * frv-dis.c: Regenerate.
200 * ip2k-dis.c: Regenerate.
201 * iq2000-dis.c: Regenerate.
202 * lm32-dis.c: Regenerate.
203 * m32c-dis.c: Regenerate.
204 * m32r-dis.c: Regenerate.
205 * mep-dis.c: Regenerate.
206 * mt-dis.c: Regenerate.
207 * or1k-dis.c: Regenerate.
208 * xc16x-dis.c: Regenerate.
209 * xstormy16-dis.c: Regenerate.
210
6f0e0752
AM		 2112019-12-10 Alan Modra <amodra@gmail.com>
212
213 * ppc-dis.c (private): Delete variable.
214 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
215 (powerpc_init_dialect): Don't use global private.
216
e7c22a69
AM		 2172019-12-10 Alan Modra <amodra@gmail.com>
218
219 * s12z-opc.c: Formatting.
220
0a6aef6b
AM		 2212019-12-08 Alan Modra <amodra@gmail.com>
222
223 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
224 registers.
225
2dc4b12f
JB		 2262019-12-05 Jan Beulich <jbeulich@suse.com>
227
228 * aarch64-tbl.h (aarch64_feature_crypto,
229 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
230 CRYPTO_V8_2_INSN): Delete.
231
378fd436
AM		 2322019-12-05 Alan Modra <amodra@gmail.com>
233
234 PR 25249
235 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
236 (struct string_buf): New.
237 (strbuf): New function.
238 (get_field): Use strbuf rather than strdup of local temp.
239 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
240 (get_field_rfsl, get_field_imm15): Likewise.
241 (get_field_rd, get_field_r1, get_field_r2): Update macros.
242 (get_field_special): Likewise. Don't strcpy spr. Formatting.
243 (print_insn_microblaze): Formatting. Init and pass string_buf to
244 get_field functions.
245
0ba59a29
JB		 2462019-12-04 Jan Beulich <jbeulich@suse.com>
247
248 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
249 * i386-tbl.h: Re-generate.
250
77ad8092
JB		 2512019-12-04 Jan Beulich <jbeulich@suse.com>
252
253 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
254
3036c899
JB		 2552019-12-04 Jan Beulich <jbeulich@suse.com>
256
257 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
258 forms.
259 (xbegin): Drop DefaultSize.
260 * i386-tbl.h: Re-generate.
261
8b301fbb
MI		 2622019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
263
264 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
265 Change the coproc CRC conditions to use the extension
266 feature set, second word, base on ARM_EXT2_CRC.
267
6aa385b9
JB		 2682019-11-14 Jan Beulich <jbeulich@suse.com>
269
270 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
271 * i386-tbl.h: Re-generate.
272
0cfa3eb3
JB		 2732019-11-14 Jan Beulich <jbeulich@suse.com>
274
275 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
276 JumpInterSegment, and JumpAbsolute entries.
277 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
278 JUMP_ABSOLUTE): Define.
279 (struct i386_opcode_modifier): Extend jump field to 3 bits.
280 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
281 fields.
282 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
283 JumpInterSegment): Define.
284 * i386-tbl.h: Re-generate.
285
6f2f06be
JB		 2862019-11-14 Jan Beulich <jbeulich@suse.com>
287
288 * i386-gen.c (operand_type_init): Remove
289 OPERAND_TYPE_JUMPABSOLUTE entry.
290 (opcode_modifiers): Add JumpAbsolute entry.
291 (operand_types): Remove JumpAbsolute entry.
292 * i386-opc.h (JumpAbsolute): Move between enums.
293 (struct i386_opcode_modifier): Add jumpabsolute field.
294 (union i386_operand_type): Remove jumpabsolute field.
295 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
296 * i386-init.h, i386-tbl.h: Re-generate.
297
601e8564
JB		 2982019-11-14 Jan Beulich <jbeulich@suse.com>
299
300 * i386-gen.c (opcode_modifiers): Add AnySize entry.
301 (operand_types): Remove AnySize entry.
302 * i386-opc.h (AnySize): Move between enums.
303 (struct i386_opcode_modifier): Add anysize field.
304 (OTUnused): Un-comment.
305 (union i386_operand_type): Remove anysize field.
306 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
307 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
308 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
309 AnySize.
310 * i386-tbl.h: Re-generate.
311
7722d40a
JW		 3122019-11-12 Nelson Chu <nelson.chu@sifive.com>
313
314 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
315 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
316 use the floating point register (FPR).
317
ce760a76
MI		 3182019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
319
320 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
321 cmode 1101.
322 (is_mve_encoding_conflict): Update cmode conflict checks for
323 MVE_VMVN_IMM.
324
51c8edf6
JB		 3252019-11-12 Jan Beulich <jbeulich@suse.com>
326
327 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
328 entry.
329 (operand_types): Remove EsSeg entry.
330 (main): Replace stale use of OTMax.
331 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
332 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
333 (EsSeg): Delete.
334 (OTUnused): Comment out.
335 (union i386_operand_type): Remove esseg field.
336 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
337 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
338 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
339 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
340 * i386-init.h, i386-tbl.h: Re-generate.
341
474da251
JB		 3422019-11-12 Jan Beulich <jbeulich@suse.com>
343
344 * i386-gen.c (operand_instances): Add RegB entry.
345 * i386-opc.h (enum operand_instance): Add RegB.
346 * i386-opc.tbl (RegC, RegD, RegB): Define.
347 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
348 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
349 monitorx, mwaitx): Drop ImmExt and convert encodings
350 accordingly.
351 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
352 (edx, rdx): Add Instance=RegD.
353 (ebx, rbx): Add Instance=RegB.
354 * i386-tbl.h: Re-generate.
355
75e5731b
JB		 3562019-11-12 Jan Beulich <jbeulich@suse.com>
357
358 * i386-gen.c (operand_type_init): Adjust
359 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
360 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
361 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
362 (operand_instances): New.
363 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
364 (output_operand_type): New parameter "instance". Process it.
365 (process_i386_operand_type): New local variable "instance".
366 (main): Adjust static assertions.
367 * i386-opc.h (INSTANCE_WIDTH): Define.
368 (enum operand_instance): New.
369 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
370 (union i386_operand_type): Replace acc, inoutportreg, and
371 shiftcount by instance.
372 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
373 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
374 Add Instance=.
375 * i386-init.h, i386-tbl.h: Re-generate.
376
91802f3c
JB		 3772019-11-11 Jan Beulich <jbeulich@suse.com>
378
379 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
380 smaxp/sminp entries' "tied_operand" field to 2.
381
4f5fc85d
JB		 3822019-11-11 Jan Beulich <jbeulich@suse.com>
383
384 * aarch64-opc.c (operand_general_constraint_met_p): Replace
385 "index" local variable by that of the already existing "num".
386
dc2be329
L		 3872019-11-08 H.J. Lu <hongjiu.lu@intel.com>
388
389 PR gas/25167
390 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
391 * i386-tbl.h: Regenerated.
392
f74a6307
JB		 3932019-11-08 Jan Beulich <jbeulich@suse.com>
394
395 * i386-gen.c (operand_type_init): Add Class= to
396 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
397 OPERAND_TYPE_REGBND entry.
398 (operand_classes): Add RegMask and RegBND entries.
399 (operand_types): Drop RegMask and RegBND entry.
400 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
401 (RegMask, RegBND): Delete.
402 (union i386_operand_type): Remove regmask and regbnd fields.
403 * i386-opc.tbl (RegMask, RegBND): Define.
404 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
405 Class=RegBND.
406 * i386-init.h, i386-tbl.h: Re-generate.
407
3528c362
JB		 4082019-11-08 Jan Beulich <jbeulich@suse.com>
409
410 * i386-gen.c (operand_type_init): Add Class= to
411 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
412 OPERAND_TYPE_REGZMM entries.
413 (operand_classes): Add RegMMX and RegSIMD entries.
414 (operand_types): Drop RegMMX and RegSIMD entries.
415 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
416 (RegMMX, RegSIMD): Delete.
417 (union i386_operand_type): Remove regmmx and regsimd fields.
418 * i386-opc.tbl (RegMMX): Define.
419 (RegXMM, RegYMM, RegZMM): Add Class=.
420 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
421 Class=RegSIMD.
422 * i386-init.h, i386-tbl.h: Re-generate.
423
4a5c67ed
JB		 4242019-11-08 Jan Beulich <jbeulich@suse.com>
425
426 * i386-gen.c (operand_type_init): Add Class= to
427 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
428 entries.
429 (operand_classes): Add RegCR, RegDR, and RegTR entries.
430 (operand_types): Drop Control, Debug, and Test entries.
431 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
432 (Control, Debug, Test): Delete.
433 (union i386_operand_type): Remove control, debug, and test
434 fields.
435 * i386-opc.tbl (Control, Debug, Test): Define.
436 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
437 Class=RegDR, and Test by Class=RegTR.
438 * i386-init.h, i386-tbl.h: Re-generate.
439
00cee14f
JB		 4402019-11-08 Jan Beulich <jbeulich@suse.com>
441
442 * i386-gen.c (operand_type_init): Add Class= to
443 OPERAND_TYPE_SREG entry.
444 (operand_classes): Add SReg entry.
445 (operand_types): Drop SReg entry.
446 * i386-opc.h (enum operand_class): Add SReg.
447 (SReg): Delete.
448 (union i386_operand_type): Remove sreg field.
449 * i386-opc.tbl (SReg): Define.
450 * i386-reg.tbl: Replace SReg by Class=SReg.
451 * i386-init.h, i386-tbl.h: Re-generate.
452
bab6aec1
JB		 4532019-11-08 Jan Beulich <jbeulich@suse.com>
454
455 * i386-gen.c (operand_type_init): Add Class=. New
456 OPERAND_TYPE_ANYIMM entry.
457 (operand_classes): New.
458 (operand_types): Drop Reg entry.
459 (output_operand_type): New parameter "class". Process it.
460 (process_i386_operand_type): New local variable "class".
461 (main): Adjust static assertions.
462 * i386-opc.h (CLASS_WIDTH): Define.
463 (enum operand_class): New.
464 (Reg): Replace by Class. Adjust comment.
465 (union i386_operand_type): Replace reg by class.
466 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
467 Class=.
468 * i386-reg.tbl: Replace Reg by Class=Reg.
469 * i386-init.h: Re-generate.
470
1f4cd317
MM		 4712019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
472
473 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
474 (aarch64_opcode_table): Add data gathering hint mnemonic.
475 * opcodes/aarch64-dis-2.c: Account for new instruction.
476
616ce08e
MM		 4772019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
478
479 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
480
481
8382113f
MM		 4822019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
483
484 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
485 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
486 aarch64_feature_f64mm): New feature sets.
487 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
488 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
489 instructions.
490 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
491 macros.
492 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
493 (OP_SVE_QQQ): New qualifier.
494 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
495 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
496 the movprfx constraint.
497 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
498 (aarch64_opcode_table): Define new instructions smmla,
499 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
500 uzip{1/2}, trn{1/2}.
501 * aarch64-opc.c (operand_general_constraint_met_p): Handle
502 AARCH64_OPND_SVE_ADDR_RI_S4x32.
503 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
504 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
505 Account for new instructions.
506 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
507 S4x32 operand.
508 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
509
aab2c27d
MM		 5102019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5112019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
512
513 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
514 Armv8.6-A.
515 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
516 (neon_opcodes): Add bfloat SIMD instructions.
517 (print_insn_coprocessor): Add new control character %b to print
518 condition code without checking cp_num.
519 (print_insn_neon): Account for BFloat16 instructions that have no
520 special top-byte handling.
521
33593eaf
MM		 5222019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5232019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
524
525 * arm-dis.c (print_insn_coprocessor,
526 print_insn_generic_coprocessor): Create wrapper functions around
527 the implementation of the print_insn_coprocessor control codes.
528 (print_insn_coprocessor_1): Original print_insn_coprocessor
529 function that now takes which array to look at as an argument.
530 (print_insn_arm): Use both print_insn_coprocessor and
531 print_insn_generic_coprocessor.
532 (print_insn_thumb32): As above.
533
df678013
MM		 5342019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5352019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
536
537 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
538 in reglane special case.
539 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
540 aarch64_find_next_opcode): Account for new instructions.
541 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
542 in reglane special case.
543 * aarch64-opc.c (struct operand_qualifier_data): Add data for
544 new AARCH64_OPND_QLF_S_2H qualifier.
545 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
546 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
547 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
548 sets.
549 (BFLOAT_SVE, BFLOAT): New feature set macros.
550 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
551 instructions.
552 (aarch64_opcode_table): Define new instructions bfdot,
553 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
554 bfcvtn2, bfcvt.
555
8ae2d3d9
MM		 5562019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5572019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
558
559 * aarch64-tbl.h (ARMV8_6): New macro.
560
142861df
JB		 5612019-11-07 Jan Beulich <jbeulich@suse.com>
562
563 * i386-dis.c (prefix_table): Add mcommit.
564 (rm_table): Add rdpru.
565 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
566 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
567 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
568 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
569 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
570 * i386-opc.tbl (mcommit, rdpru): New.
571 * i386-init.h, i386-tbl.h: Re-generate.
572
081e283f
JB		 5732019-11-07 Jan Beulich <jbeulich@suse.com>
574
575 * i386-dis.c (OP_Mwait): Drop local variable "names", use
576 "names32" instead.
577 (OP_Monitor): Drop local variable "op1_names", re-purpose
578 "names" for it instead, and replace former "names" uses by
579 "names32" ones.
580
c050c89a
JB		 5812019-11-07 Jan Beulich <jbeulich@suse.com>
582
583 PR/gas 25167
584 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
585 operand-less forms.
586 * opcodes/i386-tbl.h: Re-generate.
587
7abb8d81
JB		 5882019-11-05 Jan Beulich <jbeulich@suse.com>
589
590 * i386-dis.c (OP_Mwaitx): Delete.
591 (prefix_table): Use OP_Mwait for mwaitx entry.
592 (OP_Mwait): Also handle mwaitx.
593
267b8516
JB		 5942019-11-05 Jan Beulich <jbeulich@suse.com>
595
596 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
597 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
598 (prefix_table): Add respective entries.
599 (rm_table): Link to those entries.
600
f8687e93
JB		 6012019-11-05 Jan Beulich <jbeulich@suse.com>
602
603 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
604 (REG_0F1C_P_0_MOD_0): ... this.
605 (REG_0F1E_MOD_3): Rename to ...
606 (REG_0F1E_P_1_MOD_3): ... this.
607 (RM_0F01_REG_5): Rename to ...
608 (RM_0F01_REG_5_MOD_3): ... this.
609 (RM_0F01_REG_7): Rename to ...
610 (RM_0F01_REG_7_MOD_3): ... this.
611 (RM_0F1E_MOD_3_REG_7): Rename to ...
612 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
613 (RM_0FAE_REG_6): Rename to ...
614 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
615 (RM_0FAE_REG_7): Rename to ...
616 (RM_0FAE_REG_7_MOD_3): ... this.
617 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
618 (PREFIX_0F01_REG_5_MOD_0): ... this.
619 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
620 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
621 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
622 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
623 (PREFIX_0FAE_REG_0): Rename to ...
624 (PREFIX_0FAE_REG_0_MOD_3): ... this.
625 (PREFIX_0FAE_REG_1): Rename to ...
626 (PREFIX_0FAE_REG_1_MOD_3): ... this.
627 (PREFIX_0FAE_REG_2): Rename to ...
628 (PREFIX_0FAE_REG_2_MOD_3): ... this.
629 (PREFIX_0FAE_REG_3): Rename to ...
630 (PREFIX_0FAE_REG_3_MOD_3): ... this.
631 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
632 (PREFIX_0FAE_REG_4_MOD_0): ... this.
633 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
634 (PREFIX_0FAE_REG_4_MOD_3): ... this.
635 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
636 (PREFIX_0FAE_REG_5_MOD_0): ... this.
637 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
638 (PREFIX_0FAE_REG_5_MOD_3): ... this.
639 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
640 (PREFIX_0FAE_REG_6_MOD_0): ... this.
641 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
642 (PREFIX_0FAE_REG_6_MOD_3): ... this.
643 (PREFIX_0FAE_REG_7): Rename to ...
644 (PREFIX_0FAE_REG_7_MOD_0): ... this.
645 (PREFIX_MOD_0_0FC3): Rename to ...
646 (PREFIX_0FC3_MOD_0): ... this.
647 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
648 (PREFIX_0FC7_REG_6_MOD_0): ... this.
649 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
650 (PREFIX_0FC7_REG_6_MOD_3): ... this.
651 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
652 (PREFIX_0FC7_REG_7_MOD_3): ... this.
653 (reg_table, prefix_table, mod_table, rm_table): Adjust
654 accordingly.
655
5103274f
NC		 6562019-11-04 Nick Clifton <nickc@redhat.com>
657
658 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
659 of a v850 system register. Move the v850_sreg_names array into
660 this function.
661 (get_v850_reg_name): Likewise for ordinary register names.
662 (get_v850_vreg_name): Likewise for vector register names.
663 (get_v850_cc_name): Likewise for condition codes.
664 * get_v850_float_cc_name): Likewise for floating point condition
665 codes.
666 (get_v850_cacheop_name): Likewise for cache-ops.
667 (get_v850_prefop_name): Likewise for pref-ops.
668 (disassemble): Use the new accessor functions.
669
1820262b
DB		 6702019-10-30 Delia Burduv <delia.burduv@arm.com>
671
672 * aarch64-opc.c (print_immediate_offset_address): Don't print the
673 immediate for the writeback form of ldraa/ldrab if it is 0.
674 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
675 * aarch64-opc-2.c: Regenerated.
676
3cc17af5
JB		 6772019-10-30 Jan Beulich <jbeulich@suse.com>
678
679 * i386-gen.c (operand_type_shorthands): Delete.
680 (operand_type_init): Expand previous shorthands.
681 (set_bitfield_from_shorthand): Rename back to ...
682 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
683 of operand_type_init[].
684 (set_bitfield): Adjust call to the above function.
685 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
686 RegXMM, RegYMM, RegZMM): Define.
687 * i386-reg.tbl: Expand prior shorthands.
688
a2cebd03
JB		 6892019-10-30 Jan Beulich <jbeulich@suse.com>
690
691 * i386-gen.c (output_i386_opcode): Change order of fields
692 emitted to output.
693 * i386-opc.h (struct insn_template): Move operands field.
694 Convert extension_opcode field to unsigned short.
695 * i386-tbl.h: Re-generate.
696
507916b8
JB		 6972019-10-30 Jan Beulich <jbeulich@suse.com>
698
699 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
700 of W.
701 * i386-opc.h (W): Extend comment.
702 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
703 general purpose variants not allowing for byte operands.
704 * i386-tbl.h: Re-generate.
705
efea62b4
NC		 7062019-10-29 Nick Clifton <nickc@redhat.com>
707
708 * tic30-dis.c (print_branch): Correct size of operand array.
709
9adb2591
NC		 7102019-10-29 Nick Clifton <nickc@redhat.com>
711
712 * d30v-dis.c (print_insn): Check that operand index is valid
713 before attempting to access the operands array.
714
993a00a9
NC		 7152019-10-29 Nick Clifton <nickc@redhat.com>
716
717 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
718 locating the bit to be tested.
719
66a66a17
NC		 7202019-10-29 Nick Clifton <nickc@redhat.com>
721
722 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
723 values.
724 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
725 (print_insn_s12z): Check for illegal size values.
726
1ee3542c
NC		 7272019-10-28 Nick Clifton <nickc@redhat.com>
728
729 * csky-dis.c (csky_chars_to_number): Check for a negative
730 count. Use an unsigned integer to construct the return value.
731
bbf9a0b5
NC		 7322019-10-28 Nick Clifton <nickc@redhat.com>
733
734 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
735 operand buffer. Set value to 15 not 13.
736 (get_register_operand): Use OPERAND_BUFFER_LEN.
737 (get_indirect_operand): Likewise.
738 (print_two_operand): Likewise.
739 (print_three_operand): Likewise.
740 (print_oar_insn): Likewise.
741
d1e304bc
NC		 7422019-10-28 Nick Clifton <nickc@redhat.com>
743
744 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
745 (bit_extract_simple): Likewise.
746 (bit_copy): Likewise.
747 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
748 index_offset array are not accessed.
749
dee33451
NC		 7502019-10-28 Nick Clifton <nickc@redhat.com>
751
752 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
753 operand.
754
27cee81d
NC		 7552019-10-25 Nick Clifton <nickc@redhat.com>
756
757 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
758 access to opcodes.op array element.
759
de6d8dc2
NC		 7602019-10-23 Nick Clifton <nickc@redhat.com>
761
762 * rx-dis.c (get_register_name): Fix spelling typo in error
763 message.
764 (get_condition_name, get_flag_name, get_double_register_name)
765 (get_double_register_high_name, get_double_register_low_name)
766 (get_double_control_register_name, get_double_condition_name)
767 (get_opsize_name, get_size_name): Likewise.
768
6207ed28
NC		 7692019-10-22 Nick Clifton <nickc@redhat.com>
770
771 * rx-dis.c (get_size_name): New function. Provides safe
772 access to name array.
773 (get_opsize_name): Likewise.
774 (print_insn_rx): Use the accessor functions.
775
12234dfd
NC		 7762019-10-16 Nick Clifton <nickc@redhat.com>
777
778 * rx-dis.c (get_register_name): New function. Provides safe
779 access to name array.
780 (get_condition_name, get_flag_name, get_double_register_name)
781 (get_double_register_high_name, get_double_register_low_name)
782 (get_double_control_register_name, get_double_condition_name):
783 Likewise.
784 (print_insn_rx): Use the accessor functions.
785
1d378749
NC		 7862019-10-09 Nick Clifton <nickc@redhat.com>
787
788 PR 25041
789 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
790 instructions.
791
d241b910
JB		 7922019-10-07 Jan Beulich <jbeulich@suse.com>
793
794 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
795 (cmpsd): Likewise. Move EsSeg to other operand.
796 * opcodes/i386-tbl.h: Re-generate.
797
f5c5b7c1
AM		 7982019-09-23 Alan Modra <amodra@gmail.com>
799
800 * m68k-dis.c: Include cpu-m68k.h
801
7beeaeb8
AM		 8022019-09-23 Alan Modra <amodra@gmail.com>
803
804 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
805 "elf/mips.h" earlier.
806
3f9aad11
JB		 8072018-09-20 Jan Beulich <jbeulich@suse.com>
808
809 PR gas/25012
810 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
811 with SReg operand.
812 * i386-tbl.h: Re-generate.
813
fd361982
AM		 8142019-09-18 Alan Modra <amodra@gmail.com>
815
816 * arc-ext.c: Update throughout for bfd section macro changes.
817
e0b2a78c
SM		 8182019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
819
820 * Makefile.in: Re-generate.
821 * configure: Re-generate.
822
7e9ad3a3
JW		 8232019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
824
825 * riscv-opc.c (riscv_opcodes): Change subset field
826 to insn_class field for all instructions.
827 (riscv_insn_types): Likewise.
828
bb695960
PB		 8292019-09-16 Phil Blundell <pb@pbcl.net>
830
831 * configure: Regenerated.
832
8063ab7e
MV		 8332019-09-10 Miod Vallat <miod@online.fr>
834
835 PR 24982
836 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
837
60391a25
PB		 8382019-09-09 Phil Blundell <pb@pbcl.net>
839
840 binutils 2.33 branch created.
841
f44b758d
NC		 8422019-09-03 Nick Clifton <nickc@redhat.com>
843
844 PR 24961
845 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
846 greater than zero before indexing via (bufcnt -1).
847
1e4b5e7d
NC		 8482019-09-03 Nick Clifton <nickc@redhat.com>
849
850 PR 24958
851 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
852 (MAX_SPEC_REG_NAME_LEN): Define.
853 (struct mmix_dis_info): Use defined constants for array lengths.
854 (get_reg_name): New function.
855 (get_sprec_reg_name): New function.
856 (print_insn_mmix): Use new functions.
857
c4a23bf8
SP		 8582019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
859
860 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
861 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
862 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
863
a051e2f3
KT		 8642019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
865
866 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
867 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
868 (aarch64_sys_reg_supported_p): Update checks for the above.
869
08132bdd
SP		 8702019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
871
872 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
873 cases MVE_SQRSHRL and MVE_UQRSHLL.
874 (print_insn_mve): Add case for specifier 'k' to check
875 specific bit of the instruction.
876
d88bdcb4
PA		 8772019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
878
879 PR 24854
880 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
881 encountering an unknown machine type.
882 (print_insn_arc): Handle arc_insn_length returning 0. In error
883 cases return -1 rather than calling abort.
884
bc750500
JB		 8852019-08-07 Jan Beulich <jbeulich@suse.com>
886
887 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
888 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
889 IgnoreSize.
890 * i386-tbl.h: Re-generate.
891
23d188c7
BW		 8922019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
893
894 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
895 instructions.
896
c0d6f62f
JW		 8972019-07-30 Mel Chen <mel.chen@sifive.com>
898
899 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
900 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
901
902 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
903 fscsr.
904
0f3f7167
CZ		 9052019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
906
907 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
908 and MPY class instructions.
909 (parse_option): Add nps400 option.
910 (print_arc_disassembler_options): Add nps400 info.
911
7e126ba3
CZ		 9122019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
913
914 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
915 (bspop): Likewise.
916 (modapp): Likewise.
917 * arc-opc.c (RAD_CHK): Add.
918 * arc-tbl.h: Regenerate.
919
a028026d
KT		 9202019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
921
922 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
923 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
924
ac79ff9e
NC		 9252019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
926
927 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
928 instructions as UNPREDICTABLE.
929
231097b0
JM		 9302019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
931
932 * bpf-desc.c: Regenerated.
933
1d942ae9
JB		 9342019-07-17 Jan Beulich <jbeulich@suse.com>
935
936 * i386-gen.c (static_assert): Define.
937 (main): Use it.
938 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
939 (Opcode_Modifier_Num): ... this.
940 (Mem): Delete.
941
dfd69174
JB		 9422019-07-16 Jan Beulich <jbeulich@suse.com>
943
944 * i386-gen.c (operand_types): Move RegMem ...
945 (opcode_modifiers): ... here.
946 * i386-opc.h (RegMem): Move to opcode modifer enum.
947 (union i386_operand_type): Move regmem field ...
948 (struct i386_opcode_modifier): ... here.
949 * i386-opc.tbl (RegMem): Define.
950 (mov, movq): Move RegMem on segment, control, debug, and test
951 register flavors.
952 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
953 to non-SSE2AVX flavor.
954 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
955 Move RegMem on register only flavors. Drop IgnoreSize from
956 legacy encoding flavors.
957 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
958 flavors.
959 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
960 register only flavors.
961 (vmovd): Move RegMem and drop IgnoreSize on register only
962 flavor. Change opcode and operand order to store form.
963 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
964
21df382b
JB		 9652019-07-16 Jan Beulich <jbeulich@suse.com>
966
967 * i386-gen.c (operand_type_init, operand_types): Replace SReg
968 entries.
969 * i386-opc.h (SReg2, SReg3): Replace by ...
970 (SReg): ... this.
971 (union i386_operand_type): Replace sreg fields.
972 * i386-opc.tbl (mov, ): Use SReg.
973 (push, pop): Likewies. Drop i386 and x86-64 specific segment
974 register flavors.
975 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
976 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
977
3719fd55
JM		 9782019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
979
980 * bpf-desc.c: Regenerate.
981 * bpf-opc.c: Likewise.
982 * bpf-opc.h: Likewise.
983
92434a14
JM		 9842019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
985
986 * bpf-desc.c: Regenerate.
987 * bpf-opc.c: Likewise.
988
43dd7626
HPN		 9892019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
990
991 * arm-dis.c (print_insn_coprocessor): Rename index to
992 index_operand.
993
98602811
JW		 9942019-07-05 Kito Cheng <kito.cheng@sifive.com>
995
996 * riscv-opc.c (riscv_insn_types): Add r4 type.
997
998 * riscv-opc.c (riscv_insn_types): Add b and j type.
999
1000 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1001 format for sb type and correct s type.
1002
01c1ee4a
RS		 10032019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1004
1005 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1006 SVE FMOV alias of FCPY.
1007
83adff69
RS		 10082019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1009
1010 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1011 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1012
89418844
RS		 10132019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1014
1015 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1016 registers in an instruction prefixed by MOVPRFX.
1017
41be57ca
MM		 10182019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
1019
1020 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1021 sve_size_13 icode to account for variant behaviour of
1022 pmull{t,b}.
1023 * aarch64-dis-2.c: Regenerate.
1024 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1025 sve_size_13 icode to account for variant behaviour of
1026 pmull{t,b}.
1027 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1028 (OP_SVE_VVV_Q_D): Add new qualifier.
1029 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1030 (struct aarch64_opcode): Split pmull{t,b} into those requiring
1031 AES and those not.
1032
9d3bf266
JB		 10332019-07-01 Jan Beulich <jbeulich@suse.com>
1034
1035 * opcodes/i386-gen.c (operand_type_init): Remove
1036 OPERAND_TYPE_VEC_IMM4 entry.
1037 (operand_types): Remove Vec_Imm4.
1038 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1039 (union i386_operand_type): Remove vec_imm4.
1040 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1041 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1042
c3949f43
JB		 10432019-07-01 Jan Beulich <jbeulich@suse.com>
1044
1045 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1046 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1047 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1048 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1049 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1050 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1051 * i386-tbl.h: Re-generate.
1052
5641ec01
JB		 10532019-07-01 Jan Beulich <jbeulich@suse.com>
1054
1055 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1056 register operands.
1057 * i386-tbl.h: Re-generate.
1058
79dec6b7
JB		 10592019-07-01 Jan Beulich <jbeulich@suse.com>
1060
1061 * i386-opc.tbl (C): New.
1062 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1063 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1064 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1065 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1066 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1067 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1068 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1069 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1070 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1071 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1072 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1073 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1074 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1075 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1076 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1077 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1078 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1079 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1080 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1081 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1082 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1083 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1084 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1085 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1086 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1087 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1088 flavors.
1089 * i386-tbl.h: Re-generate.
1090
a0a1771e
JB		 10912019-07-01 Jan Beulich <jbeulich@suse.com>
1092
1093 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1094 register operands.
1095 * i386-tbl.h: Re-generate.
1096
cd546e7b
JB		 10972019-07-01 Jan Beulich <jbeulich@suse.com>
1098
1099 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1100 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1101 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1102 * i386-tbl.h: Re-generate.
1103
e3bba3fc
JB		 11042019-07-01 Jan Beulich <jbeulich@suse.com>
1105
1106 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1107 Disp8MemShift from register only templates.
1108 * i386-tbl.h: Re-generate.
1109
36cc073e
JB		 11102019-07-01 Jan Beulich <jbeulich@suse.com>
1111
1112 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1113 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1114 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1115 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1116 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1117 EVEX_W_0F11_P_3_M_1): Delete.
1118 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1119 EVEX_W_0F11_P_3): New.
1120 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1121 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1122 MOD_EVEX_0F11_PREFIX_3 table entries.
1123 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1124 PREFIX_EVEX_0F11 table entries.
1125 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1126 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1127 EVEX_W_0F11_P_3_M_{0,1} table entries.
1128
219920a7
JB		 11292019-07-01 Jan Beulich <jbeulich@suse.com>
1130
1131 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1132 Delete.
1133
e395f487
L		 11342019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1135
1136 PR binutils/24719
1137 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1138 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1139 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1140 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1141 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1142 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1143 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1144 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1145 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1146 PREFIX_EVEX_0F38C6_REG_6 entries.
1147 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1148 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1149 EVEX_W_0F38C7_R_6_P_2 entries.
1150 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1151 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1152 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1153 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1154 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1155 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1156 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1157
2b7bcc87
JB		 11582019-06-27 Jan Beulich <jbeulich@suse.com>
1159
1160 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1161 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1162 VEX_LEN_0F2D_P_3): Delete.
1163 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1164 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1165 (prefix_table): ... here.
1166
c1dc7af5
JB		 11672019-06-27 Jan Beulich <jbeulich@suse.com>
1168
1169 * i386-dis.c (Iq): Delete.
1170 (Id): New.
1171 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1172 TBM insns.
1173 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1174 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1175 (OP_E_memory): Also honor needindex when deciding whether an
1176 address size prefix needs printing.
1177 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1178
d7560e2d
JW		 11792019-06-26 Jim Wilson <jimw@sifive.com>
1180
1181 PR binutils/24739
1182 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1183 Set info->display_endian to info->endian_code.
1184
2c703856
JB		 11852019-06-25 Jan Beulich <jbeulich@suse.com>
1186
1187 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1188 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1189 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1190 OPERAND_TYPE_ACC64 entries.
1191 * i386-init.h: Re-generate.
1192
54fbadc0
JB		 11932019-06-25 Jan Beulich <jbeulich@suse.com>
1194
1195 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1196 Delete.
1197 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1198 of dqa_mode.
1199 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1200 entries here.
1201 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1202 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1203
a280ab8e
JB		 12042019-06-25 Jan Beulich <jbeulich@suse.com>
1205
1206 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1207 variables.
1208
e1a1babd
JB		 12092019-06-25 Jan Beulich <jbeulich@suse.com>
1210
1211 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1212 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1213 movnti.
d7560e2d 1214 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1215 * i386-tbl.h: Re-generate.
1216
b8364fa7
JB		 12172019-06-25 Jan Beulich <jbeulich@suse.com>
1218
1219 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1220 * i386-tbl.h: Re-generate.
1221
ad692897
L		 12222019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1223
1224 * i386-dis-evex.h: Break into ...
1225 * i386-dis-evex-len.h: New file.
1226 * i386-dis-evex-mod.h: Likewise.
1227 * i386-dis-evex-prefix.h: Likewise.
1228 * i386-dis-evex-reg.h: Likewise.
1229 * i386-dis-evex-w.h: Likewise.
1230 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1231 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1232 i386-dis-evex-mod.h.
1233
f0a6222e
L		 12342019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1235
1236 PR binutils/24700
1237 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1238 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1239 EVEX_W_0F385B_P_2.
1240 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1241 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1242 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1243 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1244 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1245 EVEX_LEN_0F385B_P_2_W_1.
1246 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1247 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1248 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1249 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1250 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1251 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1252 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1253 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1254 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1255 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1256
6e1c90b7
L		 12572019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1258
1259 PR binutils/24691
1260 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1261 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1262 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1263 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1264 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1265 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1266 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1267 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1268 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1269 EVEX_LEN_0F3A43_P_2_W_1.
1270 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1271 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1272 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1273 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1274 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1275 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1276 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1277 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1278 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1279 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1280 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1281 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1282
bcc5a6eb
NC		 12832019-06-14 Nick Clifton <nickc@redhat.com>
1284
1285 * po/fr.po; Updated French translation.
1286
e4c4ac46
SH		 12872019-06-13 Stafford Horne <shorne@gmail.com>
1288
1289 * or1k-asm.c: Regenerated.
1290 * or1k-desc.c: Regenerated.
1291 * or1k-desc.h: Regenerated.
1292 * or1k-dis.c: Regenerated.
1293 * or1k-ibld.c: Regenerated.
1294 * or1k-opc.c: Regenerated.
1295 * or1k-opc.h: Regenerated.
1296 * or1k-opinst.c: Regenerated.
1297
a0e44ef5
PB		 12982019-06-12 Peter Bergner <bergner@linux.ibm.com>
1299
1300 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1301
12efd68d
L		 13022019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1303
1304 PR binutils/24633
1305 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1306 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1307 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1308 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1309 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1310 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1311 EVEX_LEN_0F3A1B_P_2_W_1.
1312 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1313 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1314 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1315 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1316 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1317 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1318 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1319 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1320
63c6fc6c
L		 13212019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1322
1323 PR binutils/24626
1324 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1325 EVEX.vvvv when disassembling VEX and EVEX instructions.
1326 (OP_VEX): Set vex.register_specifier to 0 after readding
1327 vex.register_specifier.
1328 (OP_Vex_2src_1): Likewise.
1329 (OP_Vex_2src_2): Likewise.
1330 (OP_LWP_E): Likewise.
1331 (OP_EX_Vex): Don't check vex.register_specifier.
1332 (OP_XMM_Vex): Likewise.
1333
9186c494
L		 13342019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1335 Lili Cui <lili.cui@intel.com>
1336
1337 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1338 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1339 instructions.
1340 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1341 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1342 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1343 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1344 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1345 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1346 * i386-init.h: Regenerated.
1347 * i386-tbl.h: Likewise.
1348
5d79adc4
L		 13492019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1350 Lili Cui <lili.cui@intel.com>
1351
1352 * doc/c-i386.texi: Document enqcmd.
1353 * testsuite/gas/i386/enqcmd-intel.d: New file.
1354 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1355 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1356 * testsuite/gas/i386/enqcmd.d: Likewise.
1357 * testsuite/gas/i386/enqcmd.s: Likewise.
1358 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1359 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1360 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1361 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1362 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1363 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1364 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1365 and x86-64-enqcmd.
1366
a9d96ab9
AH		 13672019-06-04 Alan Hayward <alan.hayward@arm.com>
1368
1369 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1370
4f6d070a
AM		 13712019-06-03 Alan Modra <amodra@gmail.com>
1372
1373 * ppc-dis.c (prefix_opcd_indices): Correct size.
1374
a2f4b66c
L		 13752019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1376
1377 PR gas/24625
1378 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1379 Disp8ShiftVL.
1380 * i386-tbl.h: Regenerated.
1381
405b5bd8
AM		 13822019-05-24 Alan Modra <amodra@gmail.com>
1383
1384 * po/POTFILES.in: Regenerate.
1385
8acf1435
PB		 13862019-05-24 Peter Bergner <bergner@linux.ibm.com>
1387 Alan Modra <amodra@gmail.com>
1388
1389 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1390 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1391 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1392 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1393 XTOP>): Define and add entries.
1394 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1395 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1396 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1397 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1398
dd7efa79
PB		 13992019-05-24 Peter Bergner <bergner@linux.ibm.com>
1400 Alan Modra <amodra@gmail.com>
1401
1402 * ppc-dis.c (ppc_opts): Add "future" entry.
1403 (PREFIX_OPCD_SEGS): Define.
1404 (prefix_opcd_indices): New array.
1405 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1406 (lookup_prefix): New function.
1407 (print_insn_powerpc): Handle 64-bit prefix instructions.
1408 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1409 (PMRR, POWERXX): Define.
1410 (prefix_opcodes): New instruction table.
1411 (prefix_num_opcodes): New constant.
1412
79472b45
JM		 14132019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1414
1415 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1416 * configure: Regenerated.
1417 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1418 and cpu/bpf.opc.
1419 (HFILES): Add bpf-desc.h and bpf-opc.h.
1420 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1421 bpf-ibld.c and bpf-opc.c.
1422 (BPF_DEPS): Define.
1423 * Makefile.in: Regenerated.
1424 * disassemble.c (ARCH_bpf): Define.
1425 (disassembler): Add case for bfd_arch_bpf.
1426 (disassemble_init_for_target): Likewise.
1427 (enum epbf_isa_attr): Define.
1428 * disassemble.h: extern print_insn_bpf.
1429 * bpf-asm.c: Generated.
1430 * bpf-opc.h: Likewise.
1431 * bpf-opc.c: Likewise.
1432 * bpf-ibld.c: Likewise.
1433 * bpf-dis.c: Likewise.
1434 * bpf-desc.h: Likewise.
1435 * bpf-desc.c: Likewise.
1436
ba6cd17f
SD		 14372019-05-21 Sudakshina Das <sudi.das@arm.com>
1438
1439 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1440 and VMSR with the new operands.
1441
e39c1607
SD		 14422019-05-21 Sudakshina Das <sudi.das@arm.com>
1443
1444 * arm-dis.c (enum mve_instructions): New enum
1445 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1446 and cneg.
1447 (mve_opcodes): New instructions as above.
1448 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1449 csneg and csel.
1450 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1451
23d00a41
SD		 14522019-05-21 Sudakshina Das <sudi.das@arm.com>
1453
1454 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1455 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1456 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1457 uqshl, urshrl and urshr.
1458 (is_mve_okay_in_it): Add new instructions to TRUE list.
1459 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1460 (print_insn_mve): Updated to accept new %j,
1461 %<bitfield>m and %<bitfield>n patterns.
1462
cd4797ee
FS		 14632019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1464
1465 * mips-opc.c (mips_builtin_opcodes): Change source register
1466 constraint for DAUI.
1467
999b073b
NC		 14682019-05-20 Nick Clifton <nickc@redhat.com>
1469
1470 * po/fr.po: Updated French translation.
1471
14b456f2
AV		 14722019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1473 Michael Collison <michael.collison@arm.com>
1474
1475 * arm-dis.c (thumb32_opcodes): Add new instructions.
1476 (enum mve_instructions): Likewise.
1477 (enum mve_undefined): Add new reasons.
1478 (is_mve_encoding_conflict): Handle new instructions.
1479 (is_mve_undefined): Likewise.
1480 (is_mve_unpredictable): Likewise.
1481 (print_mve_undefined): Likewise.
1482 (print_mve_size): Likewise.
1483
f49bb598
AV		 14842019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1485 Michael Collison <michael.collison@arm.com>
1486
1487 * arm-dis.c (thumb32_opcodes): Add new instructions.
1488 (enum mve_instructions): Likewise.
1489 (is_mve_encoding_conflict): Handle new instructions.
1490 (is_mve_undefined): Likewise.
1491 (is_mve_unpredictable): Likewise.
1492 (print_mve_size): Likewise.
1493
56858bea
AV		 14942019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1495 Michael Collison <michael.collison@arm.com>
1496
1497 * arm-dis.c (thumb32_opcodes): Add new instructions.
1498 (enum mve_instructions): Likewise.
1499 (is_mve_encoding_conflict): Likewise.
1500 (is_mve_unpredictable): Likewise.
1501 (print_mve_size): Likewise.
1502
e523f101
AV		 15032019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1504 Michael Collison <michael.collison@arm.com>
1505
1506 * arm-dis.c (thumb32_opcodes): Add new instructions.
1507 (enum mve_instructions): Likewise.
1508 (is_mve_encoding_conflict): Handle new instructions.
1509 (is_mve_undefined): Likewise.
1510 (is_mve_unpredictable): Likewise.
1511 (print_mve_size): Likewise.
1512
66dcaa5d
AV		 15132019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1514 Michael Collison <michael.collison@arm.com>
1515
1516 * arm-dis.c (thumb32_opcodes): Add new instructions.
1517 (enum mve_instructions): Likewise.
1518 (is_mve_encoding_conflict): Handle new instructions.
1519 (is_mve_undefined): Likewise.
1520 (is_mve_unpredictable): Likewise.
1521 (print_mve_size): Likewise.
1522 (print_insn_mve): Likewise.
1523
d052b9b7
AV		 15242019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1525 Michael Collison <michael.collison@arm.com>
1526
1527 * arm-dis.c (thumb32_opcodes): Add new instructions.
1528 (print_insn_thumb32): Handle new instructions.
1529
ed63aa17
AV		 15302019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1531 Michael Collison <michael.collison@arm.com>
1532
1533 * arm-dis.c (enum mve_instructions): Add new instructions.
1534 (enum mve_undefined): Add new reasons.
1535 (is_mve_encoding_conflict): Handle new instructions.
1536 (is_mve_undefined): Likewise.
1537 (is_mve_unpredictable): Likewise.
1538 (print_mve_undefined): Likewise.
1539 (print_mve_size): Likewise.
1540 (print_mve_shift_n): Likewise.
1541 (print_insn_mve): Likewise.
1542
897b9bbc
AV		 15432019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1544 Michael Collison <michael.collison@arm.com>
1545
1546 * arm-dis.c (enum mve_instructions): Add new instructions.
1547 (is_mve_encoding_conflict): Handle new instructions.
1548 (is_mve_unpredictable): Likewise.
1549 (print_mve_rotate): Likewise.
1550 (print_mve_size): Likewise.
1551 (print_insn_mve): Likewise.
1552
1c8f2df8
AV		 15532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1554 Michael Collison <michael.collison@arm.com>
1555
1556 * arm-dis.c (enum mve_instructions): Add new instructions.
1557 (is_mve_encoding_conflict): Handle new instructions.
1558 (is_mve_unpredictable): Likewise.
1559 (print_mve_size): Likewise.
1560 (print_insn_mve): Likewise.
1561
d3b63143
AV		 15622019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1563 Michael Collison <michael.collison@arm.com>
1564
1565 * arm-dis.c (enum mve_instructions): Add new instructions.
1566 (enum mve_undefined): Add new reasons.
1567 (is_mve_encoding_conflict): Handle new instructions.
1568 (is_mve_undefined): Likewise.
1569 (is_mve_unpredictable): Likewise.
1570 (print_mve_undefined): Likewise.
1571 (print_mve_size): Likewise.
1572 (print_insn_mve): Likewise.
1573
14925797
AV		 15742019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1575 Michael Collison <michael.collison@arm.com>
1576
1577 * arm-dis.c (enum mve_instructions): Add new instructions.
1578 (is_mve_encoding_conflict): Handle new instructions.
1579 (is_mve_undefined): Likewise.
1580 (is_mve_unpredictable): Likewise.
1581 (print_mve_size): Likewise.
1582 (print_insn_mve): Likewise.
1583
c507f10b
AV		 15842019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1585 Michael Collison <michael.collison@arm.com>
1586
1587 * arm-dis.c (enum mve_instructions): Add new instructions.
1588 (enum mve_unpredictable): Add new reasons.
1589 (enum mve_undefined): Likewise.
1590 (is_mve_okay_in_it): Handle new isntructions.
1591 (is_mve_encoding_conflict): Likewise.
1592 (is_mve_undefined): Likewise.
1593 (is_mve_unpredictable): Likewise.
1594 (print_mve_vmov_index): Likewise.
1595 (print_simd_imm8): Likewise.
1596 (print_mve_undefined): Likewise.
1597 (print_mve_unpredictable): Likewise.
1598 (print_mve_size): Likewise.
1599 (print_insn_mve): Likewise.
1600
bf0b396d
AV		 16012019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1602 Michael Collison <michael.collison@arm.com>
1603
1604 * arm-dis.c (enum mve_instructions): Add new instructions.
1605 (enum mve_unpredictable): Add new reasons.
1606 (enum mve_undefined): Likewise.
1607 (is_mve_encoding_conflict): Handle new instructions.
1608 (is_mve_undefined): Likewise.
1609 (is_mve_unpredictable): Likewise.
1610 (print_mve_undefined): Likewise.
1611 (print_mve_unpredictable): Likewise.
1612 (print_mve_rounding_mode): Likewise.
1613 (print_mve_vcvt_size): Likewise.
1614 (print_mve_size): Likewise.
1615 (print_insn_mve): Likewise.
1616
ef1576a1
AV		 16172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1618 Michael Collison <michael.collison@arm.com>
1619
1620 * arm-dis.c (enum mve_instructions): Add new instructions.
1621 (enum mve_unpredictable): Add new reasons.
1622 (enum mve_undefined): Likewise.
1623 (is_mve_undefined): Handle new instructions.
1624 (is_mve_unpredictable): Likewise.
1625 (print_mve_undefined): Likewise.
1626 (print_mve_unpredictable): Likewise.
1627 (print_mve_size): Likewise.
1628 (print_insn_mve): Likewise.
1629
aef6d006
AV		 16302019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1631 Michael Collison <michael.collison@arm.com>
1632
1633 * arm-dis.c (enum mve_instructions): Add new instructions.
1634 (enum mve_undefined): Add new reasons.
1635 (insns): Add new instructions.
1636 (is_mve_encoding_conflict):
1637 (print_mve_vld_str_addr): New print function.
1638 (is_mve_undefined): Handle new instructions.
1639 (is_mve_unpredictable): Likewise.
1640 (print_mve_undefined): Likewise.
1641 (print_mve_size): Likewise.
1642 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1643 (print_insn_mve): Handle new operands.
1644
04d54ace
AV		 16452019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1646 Michael Collison <michael.collison@arm.com>
1647
1648 * arm-dis.c (enum mve_instructions): Add new instructions.
1649 (enum mve_unpredictable): Add new reasons.
1650 (is_mve_encoding_conflict): Handle new instructions.
1651 (is_mve_unpredictable): Likewise.
1652 (mve_opcodes): Add new instructions.
1653 (print_mve_unpredictable): Handle new reasons.
1654 (print_mve_register_blocks): New print function.
1655 (print_mve_size): Handle new instructions.
1656 (print_insn_mve): Likewise.
1657
9743db03
AV		 16582019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1659 Michael Collison <michael.collison@arm.com>
1660
1661 * arm-dis.c (enum mve_instructions): Add new instructions.
1662 (enum mve_unpredictable): Add new reasons.
1663 (enum mve_undefined): Likewise.
1664 (is_mve_encoding_conflict): Handle new instructions.
1665 (is_mve_undefined): Likewise.
1666 (is_mve_unpredictable): Likewise.
1667 (coprocessor_opcodes): Move NEON VDUP from here...
1668 (neon_opcodes): ... to here.
1669 (mve_opcodes): Add new instructions.
1670 (print_mve_undefined): Handle new reasons.
1671 (print_mve_unpredictable): Likewise.
1672 (print_mve_size): Handle new instructions.
1673 (print_insn_neon): Handle vdup.
1674 (print_insn_mve): Handle new operands.
1675
143275ea
AV		 16762019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1677 Michael Collison <michael.collison@arm.com>
1678
1679 * arm-dis.c (enum mve_instructions): Add new instructions.
1680 (enum mve_unpredictable): Add new values.
1681 (mve_opcodes): Add new instructions.
1682 (vec_condnames): New array with vector conditions.
1683 (mve_predicatenames): New array with predicate suffixes.
1684 (mve_vec_sizename): New array with vector sizes.
1685 (enum vpt_pred_state): New enum with vector predication states.
1686 (struct vpt_block): New struct type for vpt blocks.
1687 (vpt_block_state): Global struct to keep track of state.
1688 (mve_extract_pred_mask): New helper function.
1689 (num_instructions_vpt_block): Likewise.
1690 (mark_outside_vpt_block): Likewise.
1691 (mark_inside_vpt_block): Likewise.
1692 (invert_next_predicate_state): Likewise.
1693 (update_next_predicate_state): Likewise.
1694 (update_vpt_block_state): Likewise.
1695 (is_vpt_instruction): Likewise.
1696 (is_mve_encoding_conflict): Add entries for new instructions.
1697 (is_mve_unpredictable): Likewise.
1698 (print_mve_unpredictable): Handle new cases.
1699 (print_instruction_predicate): Likewise.
1700 (print_mve_size): New function.
1701 (print_vec_condition): New function.
1702 (print_insn_mve): Handle vpt blocks and new print operands.
1703
f08d8ce3
AV		 17042019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1705
1706 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1707 8, 14 and 15 for Armv8.1-M Mainline.
1708
73cd51e5
AV		 17092019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1710 Michael Collison <michael.collison@arm.com>
1711
1712 * arm-dis.c (enum mve_instructions): New enum.
1713 (enum mve_unpredictable): Likewise.
1714 (enum mve_undefined): Likewise.
1715 (struct mopcode32): New struct.
1716 (is_mve_okay_in_it): New function.
1717 (is_mve_architecture): Likewise.
1718 (arm_decode_field): Likewise.
1719 (arm_decode_field_multiple): Likewise.
1720 (is_mve_encoding_conflict): Likewise.
1721 (is_mve_undefined): Likewise.
1722 (is_mve_unpredictable): Likewise.
1723 (print_mve_undefined): Likewise.
1724 (print_mve_unpredictable): Likewise.
1725 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1726 (print_insn_mve): New function.
1727 (print_insn_thumb32): Handle MVE architecture.
1728 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1729
3076e594
NC		 17302019-05-10 Nick Clifton <nickc@redhat.com>
1731
1732 PR 24538
1733 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1734 end of the table prematurely.
1735
387e7624
FS		 17362019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1737
1738 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1739 macros for R6.
1740
0067be51
AM		 17412019-05-11 Alan Modra <amodra@gmail.com>
1742
1743 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1744 when -Mraw is in effect.
1745
42e6288f
MM		 17462019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1747
1748 * aarch64-dis-2.c: Regenerate.
1749 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1750 (OP_SVE_BBB): New variant set.
1751 (OP_SVE_DDDD): New variant set.
1752 (OP_SVE_HHH): New variant set.
1753 (OP_SVE_HHHU): New variant set.
1754 (OP_SVE_SSS): New variant set.
1755 (OP_SVE_SSSU): New variant set.
1756 (OP_SVE_SHH): New variant set.
1757 (OP_SVE_SBBU): New variant set.
1758 (OP_SVE_DSS): New variant set.
1759 (OP_SVE_DHHU): New variant set.
1760 (OP_SVE_VMV_HSD_BHS): New variant set.
1761 (OP_SVE_VVU_HSD_BHS): New variant set.
1762 (OP_SVE_VVVU_SD_BH): New variant set.
1763 (OP_SVE_VVVU_BHSD): New variant set.
1764 (OP_SVE_VVV_QHD_DBS): New variant set.
1765 (OP_SVE_VVV_HSD_BHS): New variant set.
1766 (OP_SVE_VVV_HSD_BHS2): New variant set.
1767 (OP_SVE_VVV_BHS_HSD): New variant set.
1768 (OP_SVE_VV_BHS_HSD): New variant set.
1769 (OP_SVE_VVV_SD): New variant set.
1770 (OP_SVE_VVU_BHS_HSD): New variant set.
1771 (OP_SVE_VZVV_SD): New variant set.
1772 (OP_SVE_VZVV_BH): New variant set.
1773 (OP_SVE_VZV_SD): New variant set.
1774 (aarch64_opcode_table): Add sve2 instructions.
1775
28ed815a
MM		 17762019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1777
1778 * aarch64-asm-2.c: Regenerated.
1779 * aarch64-dis-2.c: Regenerated.
1780 * aarch64-opc-2.c: Regenerated.
1781 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1782 for SVE_SHLIMM_UNPRED_22.
1783 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1784 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1785 operand.
1786
fd1dc4a0
MM		 17872019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1788
1789 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1790 sve_size_tsz_bhs iclass encode.
1791 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1792 sve_size_tsz_bhs iclass decode.
1793
31e36ab3
MM		 17942019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1795
1796 * aarch64-asm-2.c: Regenerated.
1797 * aarch64-dis-2.c: Regenerated.
1798 * aarch64-opc-2.c: Regenerated.
1799 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1800 for SVE_Zm4_11_INDEX.
1801 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1802 (fields): Handle SVE_i2h field.
1803 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1804 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1805
1be5f94f
MM		 18062019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1807
1808 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1809 sve_shift_tsz_bhsd iclass encode.
1810 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1811 sve_shift_tsz_bhsd iclass decode.
1812
3c17238b
MM		 18132019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1814
1815 * aarch64-asm-2.c: Regenerated.
1816 * aarch64-dis-2.c: Regenerated.
1817 * aarch64-opc-2.c: Regenerated.
1818 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1819 (aarch64_encode_variant_using_iclass): Handle
1820 sve_shift_tsz_hsd iclass encode.
1821 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1822 sve_shift_tsz_hsd iclass decode.
1823 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1824 for SVE_SHRIMM_UNPRED_22.
1825 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1826 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1827 operand.
1828
cd50a87a
MM		 18292019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1830
1831 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1832 sve_size_013 iclass encode.
1833 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1834 sve_size_013 iclass decode.
1835
3c705960
MM		 18362019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1837
1838 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1839 sve_size_bh iclass encode.
1840 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1841 sve_size_bh iclass decode.
1842
0a57e14f
MM		 18432019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1844
1845 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1846 sve_size_sd2 iclass encode.
1847 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1848 sve_size_sd2 iclass decode.
1849 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1850 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1851
c469c864
MM		 18522019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1853
1854 * aarch64-asm-2.c: Regenerated.
1855 * aarch64-dis-2.c: Regenerated.
1856 * aarch64-opc-2.c: Regenerated.
1857 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1858 for SVE_ADDR_ZX.
1859 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1860 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1861
116adc27
MM		 18622019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1863
1864 * aarch64-asm-2.c: Regenerated.
1865 * aarch64-dis-2.c: Regenerated.
1866 * aarch64-opc-2.c: Regenerated.
1867 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1868 for SVE_Zm3_11_INDEX.
1869 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1870 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1871 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1872 fields.
1873 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1874
3bd82c86
MM		 18752019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1876
1877 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1878 sve_size_hsd2 iclass encode.
1879 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1880 sve_size_hsd2 iclass decode.
1881 * aarch64-opc.c (fields): Handle SVE_size field.
1882 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1883
adccc507
MM		 18842019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1885
1886 * aarch64-asm-2.c: Regenerated.
1887 * aarch64-dis-2.c: Regenerated.
1888 * aarch64-opc-2.c: Regenerated.
1889 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1890 for SVE_IMM_ROT3.
1891 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1892 (fields): Handle SVE_rot3 field.
1893 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1894 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1895
5cd99750
MM		 18962019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1897
1898 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1899 instructions.
1900
7ce2460a
MM		 19012019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1902
1903 * aarch64-tbl.h
1904 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1905 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1906 aarch64_feature_sve2bitperm): New feature sets.
1907 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1908 for feature set addresses.
1909 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1910 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1911
41cee089
FS		 19122019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1913 Faraz Shahbazker <fshahbazker@wavecomp.com>
1914
1915 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1916 argument and set ASE_EVA_R6 appropriately.
1917 (set_default_mips_dis_options): Pass ISA to above.
1918 (parse_mips_dis_option): Likewise.
1919 * mips-opc.c (EVAR6): New macro.
1920 (mips_builtin_opcodes): Add llwpe, scwpe.
1921
b83b4b13
SD		 19222019-05-01 Sudakshina Das <sudi.das@arm.com>
1923
1924 * aarch64-asm-2.c: Regenerated.
1925 * aarch64-dis-2.c: Regenerated.
1926 * aarch64-opc-2.c: Regenerated.
1927 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1928 AARCH64_OPND_TME_UIMM16.
1929 (aarch64_print_operand): Likewise.
1930 * aarch64-tbl.h (QL_IMM_NIL): New.
1931 (TME): New.
1932 (_TME_INSN): New.
1933 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1934
4a90ce95
JD		 19352019-04-29 John Darrington <john@darrington.wattle.id.au>
1936
1937 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1938
a45328b9
AB		 19392019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1940 Faraz Shahbazker <fshahbazker@wavecomp.com>
1941
1942 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1943
d10be0cb
JD		 19442019-04-24 John Darrington <john@darrington.wattle.id.au>
1945
1946 * s12z-opc.h: Add extern "C" bracketing to help
1947 users who wish to use this interface in c++ code.
1948
a679f24e
JD		 19492019-04-24 John Darrington <john@darrington.wattle.id.au>
1950
1951 * s12z-opc.c (bm_decode): Handle bit map operations with the
1952 "reserved0" mode.
1953
32c36c3c
AV		 19542019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1955
1956 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1957 specifier. Add entries for VLDR and VSTR of system registers.
1958 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1959 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1960 of %J and %K format specifier.
1961
efd6b359
AV		 19622019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1963
1964 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1965 Add new entries for VSCCLRM instruction.
1966 (print_insn_coprocessor): Handle new %C format control code.
1967
6b0dd094
AV		 19682019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1969
1970 * arm-dis.c (enum isa): New enum.
1971 (struct sopcode32): New structure.
1972 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1973 set isa field of all current entries to ANY.
1974 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1975 Only match an entry if its isa field allows the current mode.
1976
4b5a202f
AV		 19772019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1978
1979 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1980 CLRM.
1981 (print_insn_thumb32): Add logic to print %n CLRM register list.
1982
60f993ce
AV		 19832019-04-15 Sudakshina Das <sudi.das@arm.com>
1984
1985 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1986 and %Q patterns.
1987
f6b2b12d
AV		 19882019-04-15 Sudakshina Das <sudi.das@arm.com>
1989
1990 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1991 (print_insn_thumb32): Edit the switch case for %Z.
1992
1889da70
AV		 19932019-04-15 Sudakshina Das <sudi.das@arm.com>
1994
1995 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1996
65d1bc05
AV		 19972019-04-15 Sudakshina Das <sudi.das@arm.com>
1998
1999 * arm-dis.c (thumb32_opcodes): New instruction bfl.
2000
1caf72a5
AV		 20012019-04-15 Sudakshina Das <sudi.das@arm.com>
2002
2003 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2004
f1c7f421
AV		 20052019-04-15 Sudakshina Das <sudi.das@arm.com>
2006
2007 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2008 Arm register with r13 and r15 unpredictable.
2009 (thumb32_opcodes): New instructions for bfx and bflx.
2010
4389b29a
AV		 20112019-04-15 Sudakshina Das <sudi.das@arm.com>
2012
2013 * arm-dis.c (thumb32_opcodes): New instructions for bf.
2014
e5d6e09e
AV		 20152019-04-15 Sudakshina Das <sudi.das@arm.com>
2016
2017 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2018
e12437dc
AV		 20192019-04-15 Sudakshina Das <sudi.das@arm.com>
2020
2021 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2022
031254f2
AV		 20232019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2024
2025 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2026
e5a557ac
JD		 20272019-04-12 John Darrington <john@darrington.wattle.id.au>
2028
2029 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2030 "optr". ("operator" is a reserved word in c++).
2031
bd7ceb8d
SD		 20322019-04-11 Sudakshina Das <sudi.das@arm.com>
2033
2034 * aarch64-opc.c (aarch64_print_operand): Add case for
2035 AARCH64_OPND_Rt_SP.
2036 (verify_constraints): Likewise.
2037 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2038 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2039 to accept Rt|SP as first operand.
2040 (AARCH64_OPERANDS): Add new Rt_SP.
2041 * aarch64-asm-2.c: Regenerated.
2042 * aarch64-dis-2.c: Regenerated.
2043 * aarch64-opc-2.c: Regenerated.
2044
e54010f1
SD		 20452019-04-11 Sudakshina Das <sudi.das@arm.com>
2046
2047 * aarch64-asm-2.c: Regenerated.
2048 * aarch64-dis-2.c: Likewise.
2049 * aarch64-opc-2.c: Likewise.
2050 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2051
7e96e219
RS		 20522019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2053
2054 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2055
6f2791d5
L		 20562019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2057
2058 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2059 * i386-init.h: Regenerated.
2060
e392bad3
AM		 20612019-04-07 Alan Modra <amodra@gmail.com>
2062
2063 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2064 op_separator to control printing of spaces, comma and parens
2065 rather than need_comma, need_paren and spaces vars.
2066
dffaa15c
AM		 20672019-04-07 Alan Modra <amodra@gmail.com>
2068
2069 PR 24421
2070 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2071 (print_insn_neon, print_insn_arm): Likewise.
2072
d6aab7a1
XG		 20732019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2074
2075 * i386-dis-evex.h (evex_table): Updated to support BF16
2076 instructions.
2077 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2078 and EVEX_W_0F3872_P_3.
2079 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2080 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2081 * i386-opc.h (enum): Add CpuAVX512_BF16.
2082 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2083 * i386-opc.tbl: Add AVX512 BF16 instructions.
2084 * i386-init.h: Regenerated.
2085 * i386-tbl.h: Likewise.
2086
66e85460
AM		 20872019-04-05 Alan Modra <amodra@gmail.com>
2088
2089 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2090 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2091 to favour printing of "-" branch hint when using the "y" bit.
2092 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2093
c2b1c275
AM		 20942019-04-05 Alan Modra <amodra@gmail.com>
2095
2096 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2097 opcode until first operand is output.
2098
aae9718e
PB		 20992019-04-04 Peter Bergner <bergner@linux.ibm.com>
2100
2101 PR gas/24349
2102 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2103 (valid_bo_post_v2): Add support for 'at' branch hints.
2104 (insert_bo): Only error on branch on ctr.
2105 (get_bo_hint_mask): New function.
2106 (insert_boe): Add new 'branch_taken' formal argument. Add support
2107 for inserting 'at' branch hints.
2108 (extract_boe): Add new 'branch_taken' formal argument. Add support
2109 for extracting 'at' branch hints.
2110 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2111 (BOE): Delete operand.
2112 (BOM, BOP): New operands.
2113 (RM): Update value.
2114 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2115 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2116 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2117 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2118 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2119 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2120 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2121 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2122 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2123 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2124 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2125 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2126 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2127 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2128 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2129 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2130 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2131 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2132 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2133 bttarl+>: New extended mnemonics.
2134
96a86c01
AM		 21352019-03-28 Alan Modra <amodra@gmail.com>
2136
2137 PR 24390
2138 * ppc-opc.c (BTF): Define.
2139 (powerpc_opcodes): Use for mtfsb*.
2140 * ppc-dis.c (print_insn_powerpc): Print fields with both
2141 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2142
796d6298
TC		 21432019-03-25 Tamar Christina <tamar.christina@arm.com>
2144
2145 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2146 (mapping_symbol_for_insn): Implement new algorithm.
2147 (print_insn): Remove duplicate code.
2148
60df3720
TC		 21492019-03-25 Tamar Christina <tamar.christina@arm.com>
2150
2151 * aarch64-dis.c (print_insn_aarch64):
2152 Implement override.
2153
51457761
TC		 21542019-03-25 Tamar Christina <tamar.christina@arm.com>
2155
2156 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2157 order.
2158
53b2f36b
TC		 21592019-03-25 Tamar Christina <tamar.christina@arm.com>
2160
2161 * aarch64-dis.c (last_stop_offset): New.
2162 (print_insn_aarch64): Use stop_offset.
2163
89199bb5
L		 21642019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2165
2166 PR gas/24359
2167 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2168 CPU_ANY_AVX2_FLAGS.
2169 * i386-init.h: Regenerated.
2170
97ed31ae
L		 21712019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2172
2173 PR gas/24348
2174 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2175 vmovdqu16, vmovdqu32 and vmovdqu64.
2176 * i386-tbl.h: Regenerated.
2177
0919bfe9
AK		 21782019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2179
2180 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2181 from vstrszb, vstrszh, and vstrszf.
2182
21832019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2184
2185 * s390-opc.txt: Add instruction descriptions.
2186
21820ebe
JW		 21872019-02-08 Jim Wilson <jimw@sifive.com>
2188
2189 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2190 <bne>: Likewise.
2191
f7dd2fb2
TC		 21922019-02-07 Tamar Christina <tamar.christina@arm.com>
2193
2194 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2195
6456d318
TC		 21962019-02-07 Tamar Christina <tamar.christina@arm.com>
2197
2198 PR binutils/23212
2199 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2200 * aarch64-opc.c (verify_elem_sd): New.
2201 (fields): Add FLD_sz entr.
2202 * aarch64-tbl.h (_SIMD_INSN): New.
2203 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2204 fmulx scalar and vector by element isns.
2205
4a83b610
NC		 22062019-02-07 Nick Clifton <nickc@redhat.com>
2207
2208 * po/sv.po: Updated Swedish translation.
2209
fc60b8c8
AK		 22102019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2211
2212 * s390-mkopc.c (main): Accept arch13 as cpu string.
2213 * s390-opc.c: Add new instruction formats and instruction opcode
2214 masks.
2215 * s390-opc.txt: Add new arch13 instructions.
2216
e10620d3
TC		 22172019-01-25 Sudakshina Das <sudi.das@arm.com>
2218
2219 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2220 (aarch64_opcode): Change encoding for stg, stzg
2221 st2g and st2zg.
2222 * aarch64-asm-2.c: Regenerated.
2223 * aarch64-dis-2.c: Regenerated.
2224 * aarch64-opc-2.c: Regenerated.
2225
20a4ca55
SD		 22262019-01-25 Sudakshina Das <sudi.das@arm.com>
2227
2228 * aarch64-asm-2.c: Regenerated.
2229 * aarch64-dis-2.c: Likewise.
2230 * aarch64-opc-2.c: Likewise.
2231 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2232
550fd7bf
SD		 22332019-01-25 Sudakshina Das <sudi.das@arm.com>
2234 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2235
2236 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2237 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2238 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2239 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2240 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2241 case for ldstgv_indexed.
2242 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2243 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2244 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2245 * aarch64-asm-2.c: Regenerated.
2246 * aarch64-dis-2.c: Regenerated.
2247 * aarch64-opc-2.c: Regenerated.
2248
d9938630
NC		 22492019-01-23 Nick Clifton <nickc@redhat.com>
2250
2251 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2252
375cd423
NC		 22532019-01-21 Nick Clifton <nickc@redhat.com>
2254
2255 * po/de.po: Updated German translation.
2256 * po/uk.po: Updated Ukranian translation.
2257
57299f48
CX		 22582019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2259 * mips-dis.c (mips_arch_choices): Fix typo in
2260 gs464, gs464e and gs264e descriptors.
2261
f48dfe41
NC		 22622019-01-19 Nick Clifton <nickc@redhat.com>
2263
2264 * configure: Regenerate.
2265 * po/opcodes.pot: Regenerate.
2266
f974f26c
NC		 22672018-06-24 Nick Clifton <nickc@redhat.com>
2268
2269 2.32 branch created.
2270
39f286cd
JD		 22712019-01-09 John Darrington <john@darrington.wattle.id.au>
2272
448b8ca8
JD		 2273 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2274 if it is null.
2275 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2276 zero.
2277
3107326d
AP		 22782019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2279
2280 * configure: Regenerate.
2281
7e9ca91e
AM		 22822019-01-07 Alan Modra <amodra@gmail.com>
2283
2284 * configure: Regenerate.
2285 * po/POTFILES.in: Regenerate.
2286
ef1ad42b
JD		 22872019-01-03 John Darrington <john@darrington.wattle.id.au>
2288
2289 * s12z-opc.c: New file.
2290 * s12z-opc.h: New file.
2291 * s12z-dis.c: Removed all code not directly related to display
2292 of instructions. Used the interface provided by the new files
2293 instead.
2294 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2295 * Makefile.in: Regenerate.
ef1ad42b 2296 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2297 * configure: Regenerate.
ef1ad42b 2298
82704155
AM		 22992019-01-01 Alan Modra <amodra@gmail.com>
2300
2301 Update year range in copyright notice of all files.
2302
d5c04e1b 2303For older changes see ChangeLog-2018
3499769a 2304\f
d5c04e1b 2305Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2306
2307Copying and distribution of this file, with or without modification,
2308are permitted in any medium without royalty provided the copyright
2309notice and this notice are preserved.
2310
2311Local Variables:
2312mode: change-log
2313left-margin: 8
2314fill-column: 74
2315version-control: never
2316End:
GDB Binutils - Deliverables
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