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ubsan: aarch64: left shift of negative value
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
f81e7e2d
AM		 12019-12-16 Alan Modra <amodra@gmail.com>
2
3 * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without
4 conditional.
5 (aarch64_ext_imm): Avoid signed overflow.
6
488d02fe
AM		 72019-12-16 Alan Modra <amodra@gmail.com>
8
9 * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
10
8a92faab
AM		 112019-12-16 Alan Modra <amodra@gmail.com>
12
13 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
14
e6ced26a
AM		 152019-12-16 Alan Modra <amodra@gmail.com>
16
17 * xstormy16-ibld.c: Regenerate.
18
84e098cd
AM		 192019-12-16 Alan Modra <amodra@gmail.com>
20
21 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
22 value adjustment so that it doesn't affect reg field too.
23
36bd8ea7
AM		 242019-12-16 Alan Modra <amodra@gmail.com>
25
26 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
27 (get_number_of_operands, getargtype, getbits, getregname),
28 (getcopregname, getprocregname, gettrapstring, getcinvstring),
29 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
30 (powerof2, match_opcode, make_instruction, print_arguments),
31 (print_arg): Delete forward declarations, moving static to..
32 (getregname, getcopregname, getregliststring): ..these definitions.
33 (build_mask): Return unsigned int mask.
34 (match_opcode): Use unsigned int vars.
35
cedfc774
AM		 362019-12-16 Alan Modra <amodra@gmail.com>
37
38 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
39
4bdb25fe
AM		 402019-12-16 Alan Modra <amodra@gmail.com>
41
42 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
43 (struct objdump_disasm_info): Delete.
44 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
45 N32_IMMS to unsigned before shifting left.
46
cf950fd4
AM		 472019-12-16 Alan Modra <amodra@gmail.com>
48
49 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
50 (print_insn_moxie): Remove unnecessary cast.
51
967354c3
AM		 522019-12-12 Alan Modra <amodra@gmail.com>
53
54 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
55 mask.
56
1d61b032
AM		 572019-12-11 Alan Modra <amodra@gmail.com>
58
59 * arc-dis.c (BITS): Don't truncate high bits with shifts.
60 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
61 * tic54x-dis.c (print_instruction): Likewise.
62 * tilegx-opc.c (parse_insn_tilegx): Likewise.
63 * tilepro-opc.c (parse_insn_tilepro): Likewise.
64 * visium-dis.c (disassem_class0): Likewise.
65 * pdp11-dis.c (sign_extend): Likewise.
66 (SIGN_BITS): Delete.
67 * epiphany-ibld.c: Regenerate.
68 * lm32-ibld.c: Regenerate.
69 * m32c-ibld.c: Regenerate.
70
5afa80e9
AM		 712019-12-11 Alan Modra <amodra@gmail.com>
72
73 * ns32k-dis.c (sign_extend): Correct last patch.
74
5c05618a
AM		 752019-12-11 Alan Modra <amodra@gmail.com>
76
77 * vax-dis.c (NEXTLONG): Avoid signed overflow.
78
2a81ccbb
AM		 792019-12-11 Alan Modra <amodra@gmail.com>
80
81 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
82 sign extend using shifts.
83
b84f6152
AM		 842019-12-11 Alan Modra <amodra@gmail.com>
85
86 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
87
66152f16
AM		 882019-12-11 Alan Modra <amodra@gmail.com>
89
90 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
91 on NULL registertable entry.
92 (tic4x_hash_opcode): Use unsigned arithmetic.
93
205c426a
AM		 942019-12-11 Alan Modra <amodra@gmail.com>
95
96 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
97
fb4cb4e2
AM		 982019-12-11 Alan Modra <amodra@gmail.com>
99
100 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
101 (bit_extract_simple, sign_extend): Likewise.
102
96f1f604
AM		 1032019-12-11 Alan Modra <amodra@gmail.com>
104
105 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
106
8c9b4171
AM		 1072019-12-11 Alan Modra <amodra@gmail.com>
108
109 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
110
334175b6
AM		 1112019-12-11 Alan Modra <amodra@gmail.com>
112
113 * m68k-dis.c (COERCE32): Cast value first.
114 (NEXTLONG, NEXTULONG): Avoid signed overflow.
115
f8a87c78
AM		 1162019-12-11 Alan Modra <amodra@gmail.com>
117
118 * h8300-dis.c (extract_immediate): Avoid signed overflow.
119 (bfd_h8_disassemble): Likewise.
120
159653d8
AM		 1212019-12-11 Alan Modra <amodra@gmail.com>
122
123 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
124 past end of operands array.
125
d93bba9e
AM		 1262019-12-11 Alan Modra <amodra@gmail.com>
127
128 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
129 overflow when collecting bytes of a number.
130
c202f69e
AM		 1312019-12-11 Alan Modra <amodra@gmail.com>
132
133 * cris-dis.c (print_with_operands): Avoid signed integer
134 overflow when collecting bytes of a 32-bit integer.
135
0ef562a4
AM		 1362019-12-11 Alan Modra <amodra@gmail.com>
137
138 * cr16-dis.c (EXTRACT, SBM): Rewrite.
139 (cr16_match_opcode): Delete duplicate bcond test.
140
2fd2b153
AM		 1412019-12-11 Alan Modra <amodra@gmail.com>
142
143 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
144 (SIGNBIT): New.
145 (MASKBITS, SIGNEXTEND): Rewrite.
146 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
147 unsigned arithmetic, instead assign result of SIGNEXTEND back
148 to x.
149 (fmtconst_val): Use 1u in shift expression.
150
a11db3e9
AM		 1512019-12-11 Alan Modra <amodra@gmail.com>
152
153 * arc-dis.c (find_format_from_table): Use ull constant when
154 shifting by up to 32.
155
9d48687b
AM		 1562019-12-11 Alan Modra <amodra@gmail.com>
157
158 PR 25270
159 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
160 false when field is zero for sve_size_tsz_bhs.
161
b8e61daa
AM		 1622019-12-11 Alan Modra <amodra@gmail.com>
163
164 * epiphany-ibld.c: Regenerate.
165
20135676
AM		 1662019-12-10 Alan Modra <amodra@gmail.com>
167
168 PR 24960
169 * disassemble.c (disassemble_free_target): New function.
170
103ebbc3
AM		 1712019-12-10 Alan Modra <amodra@gmail.com>
172
173 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
174 * disassemble.c (disassemble_init_for_target): Likewise.
175 * bpf-dis.c: Regenerate.
176 * epiphany-dis.c: Regenerate.
177 * fr30-dis.c: Regenerate.
178 * frv-dis.c: Regenerate.
179 * ip2k-dis.c: Regenerate.
180 * iq2000-dis.c: Regenerate.
181 * lm32-dis.c: Regenerate.
182 * m32c-dis.c: Regenerate.
183 * m32r-dis.c: Regenerate.
184 * mep-dis.c: Regenerate.
185 * mt-dis.c: Regenerate.
186 * or1k-dis.c: Regenerate.
187 * xc16x-dis.c: Regenerate.
188 * xstormy16-dis.c: Regenerate.
189
6f0e0752
AM		 1902019-12-10 Alan Modra <amodra@gmail.com>
191
192 * ppc-dis.c (private): Delete variable.
193 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
194 (powerpc_init_dialect): Don't use global private.
195
e7c22a69
AM		 1962019-12-10 Alan Modra <amodra@gmail.com>
197
198 * s12z-opc.c: Formatting.
199
0a6aef6b
AM		 2002019-12-08 Alan Modra <amodra@gmail.com>
201
202 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
203 registers.
204
2dc4b12f
JB		 2052019-12-05 Jan Beulich <jbeulich@suse.com>
206
207 * aarch64-tbl.h (aarch64_feature_crypto,
208 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
209 CRYPTO_V8_2_INSN): Delete.
210
378fd436
AM		 2112019-12-05 Alan Modra <amodra@gmail.com>
212
213 PR 25249
214 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
215 (struct string_buf): New.
216 (strbuf): New function.
217 (get_field): Use strbuf rather than strdup of local temp.
218 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
219 (get_field_rfsl, get_field_imm15): Likewise.
220 (get_field_rd, get_field_r1, get_field_r2): Update macros.
221 (get_field_special): Likewise. Don't strcpy spr. Formatting.
222 (print_insn_microblaze): Formatting. Init and pass string_buf to
223 get_field functions.
224
0ba59a29
JB		 2252019-12-04 Jan Beulich <jbeulich@suse.com>
226
227 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
228 * i386-tbl.h: Re-generate.
229
77ad8092
JB		 2302019-12-04 Jan Beulich <jbeulich@suse.com>
231
232 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
233
3036c899
JB		 2342019-12-04 Jan Beulich <jbeulich@suse.com>
235
236 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
237 forms.
238 (xbegin): Drop DefaultSize.
239 * i386-tbl.h: Re-generate.
240
8b301fbb
MI		 2412019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
242
243 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
244 Change the coproc CRC conditions to use the extension
245 feature set, second word, base on ARM_EXT2_CRC.
246
6aa385b9
JB		 2472019-11-14 Jan Beulich <jbeulich@suse.com>
248
249 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
250 * i386-tbl.h: Re-generate.
251
0cfa3eb3
JB		 2522019-11-14 Jan Beulich <jbeulich@suse.com>
253
254 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
255 JumpInterSegment, and JumpAbsolute entries.
256 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
257 JUMP_ABSOLUTE): Define.
258 (struct i386_opcode_modifier): Extend jump field to 3 bits.
259 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
260 fields.
261 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
262 JumpInterSegment): Define.
263 * i386-tbl.h: Re-generate.
264
6f2f06be
JB		 2652019-11-14 Jan Beulich <jbeulich@suse.com>
266
267 * i386-gen.c (operand_type_init): Remove
268 OPERAND_TYPE_JUMPABSOLUTE entry.
269 (opcode_modifiers): Add JumpAbsolute entry.
270 (operand_types): Remove JumpAbsolute entry.
271 * i386-opc.h (JumpAbsolute): Move between enums.
272 (struct i386_opcode_modifier): Add jumpabsolute field.
273 (union i386_operand_type): Remove jumpabsolute field.
274 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
275 * i386-init.h, i386-tbl.h: Re-generate.
276
601e8564
JB		 2772019-11-14 Jan Beulich <jbeulich@suse.com>
278
279 * i386-gen.c (opcode_modifiers): Add AnySize entry.
280 (operand_types): Remove AnySize entry.
281 * i386-opc.h (AnySize): Move between enums.
282 (struct i386_opcode_modifier): Add anysize field.
283 (OTUnused): Un-comment.
284 (union i386_operand_type): Remove anysize field.
285 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
286 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
287 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
288 AnySize.
289 * i386-tbl.h: Re-generate.
290
7722d40a
JW		 2912019-11-12 Nelson Chu <nelson.chu@sifive.com>
292
293 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
294 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
295 use the floating point register (FPR).
296
ce760a76
MI		 2972019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
298
299 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
300 cmode 1101.
301 (is_mve_encoding_conflict): Update cmode conflict checks for
302 MVE_VMVN_IMM.
303
51c8edf6
JB		 3042019-11-12 Jan Beulich <jbeulich@suse.com>
305
306 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
307 entry.
308 (operand_types): Remove EsSeg entry.
309 (main): Replace stale use of OTMax.
310 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
311 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
312 (EsSeg): Delete.
313 (OTUnused): Comment out.
314 (union i386_operand_type): Remove esseg field.
315 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
316 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
317 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
318 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
319 * i386-init.h, i386-tbl.h: Re-generate.
320
474da251
JB		 3212019-11-12 Jan Beulich <jbeulich@suse.com>
322
323 * i386-gen.c (operand_instances): Add RegB entry.
324 * i386-opc.h (enum operand_instance): Add RegB.
325 * i386-opc.tbl (RegC, RegD, RegB): Define.
326 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
327 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
328 monitorx, mwaitx): Drop ImmExt and convert encodings
329 accordingly.
330 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
331 (edx, rdx): Add Instance=RegD.
332 (ebx, rbx): Add Instance=RegB.
333 * i386-tbl.h: Re-generate.
334
75e5731b
JB		 3352019-11-12 Jan Beulich <jbeulich@suse.com>
336
337 * i386-gen.c (operand_type_init): Adjust
338 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
339 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
340 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
341 (operand_instances): New.
342 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
343 (output_operand_type): New parameter "instance". Process it.
344 (process_i386_operand_type): New local variable "instance".
345 (main): Adjust static assertions.
346 * i386-opc.h (INSTANCE_WIDTH): Define.
347 (enum operand_instance): New.
348 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
349 (union i386_operand_type): Replace acc, inoutportreg, and
350 shiftcount by instance.
351 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
352 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
353 Add Instance=.
354 * i386-init.h, i386-tbl.h: Re-generate.
355
91802f3c
JB		 3562019-11-11 Jan Beulich <jbeulich@suse.com>
357
358 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
359 smaxp/sminp entries' "tied_operand" field to 2.
360
4f5fc85d
JB		 3612019-11-11 Jan Beulich <jbeulich@suse.com>
362
363 * aarch64-opc.c (operand_general_constraint_met_p): Replace
364 "index" local variable by that of the already existing "num".
365
dc2be329
L		 3662019-11-08 H.J. Lu <hongjiu.lu@intel.com>
367
368 PR gas/25167
369 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
370 * i386-tbl.h: Regenerated.
371
f74a6307
JB		 3722019-11-08 Jan Beulich <jbeulich@suse.com>
373
374 * i386-gen.c (operand_type_init): Add Class= to
375 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
376 OPERAND_TYPE_REGBND entry.
377 (operand_classes): Add RegMask and RegBND entries.
378 (operand_types): Drop RegMask and RegBND entry.
379 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
380 (RegMask, RegBND): Delete.
381 (union i386_operand_type): Remove regmask and regbnd fields.
382 * i386-opc.tbl (RegMask, RegBND): Define.
383 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
384 Class=RegBND.
385 * i386-init.h, i386-tbl.h: Re-generate.
386
3528c362
JB		 3872019-11-08 Jan Beulich <jbeulich@suse.com>
388
389 * i386-gen.c (operand_type_init): Add Class= to
390 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
391 OPERAND_TYPE_REGZMM entries.
392 (operand_classes): Add RegMMX and RegSIMD entries.
393 (operand_types): Drop RegMMX and RegSIMD entries.
394 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
395 (RegMMX, RegSIMD): Delete.
396 (union i386_operand_type): Remove regmmx and regsimd fields.
397 * i386-opc.tbl (RegMMX): Define.
398 (RegXMM, RegYMM, RegZMM): Add Class=.
399 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
400 Class=RegSIMD.
401 * i386-init.h, i386-tbl.h: Re-generate.
402
4a5c67ed
JB		 4032019-11-08 Jan Beulich <jbeulich@suse.com>
404
405 * i386-gen.c (operand_type_init): Add Class= to
406 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
407 entries.
408 (operand_classes): Add RegCR, RegDR, and RegTR entries.
409 (operand_types): Drop Control, Debug, and Test entries.
410 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
411 (Control, Debug, Test): Delete.
412 (union i386_operand_type): Remove control, debug, and test
413 fields.
414 * i386-opc.tbl (Control, Debug, Test): Define.
415 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
416 Class=RegDR, and Test by Class=RegTR.
417 * i386-init.h, i386-tbl.h: Re-generate.
418
00cee14f
JB		 4192019-11-08 Jan Beulich <jbeulich@suse.com>
420
421 * i386-gen.c (operand_type_init): Add Class= to
422 OPERAND_TYPE_SREG entry.
423 (operand_classes): Add SReg entry.
424 (operand_types): Drop SReg entry.
425 * i386-opc.h (enum operand_class): Add SReg.
426 (SReg): Delete.
427 (union i386_operand_type): Remove sreg field.
428 * i386-opc.tbl (SReg): Define.
429 * i386-reg.tbl: Replace SReg by Class=SReg.
430 * i386-init.h, i386-tbl.h: Re-generate.
431
bab6aec1
JB		 4322019-11-08 Jan Beulich <jbeulich@suse.com>
433
434 * i386-gen.c (operand_type_init): Add Class=. New
435 OPERAND_TYPE_ANYIMM entry.
436 (operand_classes): New.
437 (operand_types): Drop Reg entry.
438 (output_operand_type): New parameter "class". Process it.
439 (process_i386_operand_type): New local variable "class".
440 (main): Adjust static assertions.
441 * i386-opc.h (CLASS_WIDTH): Define.
442 (enum operand_class): New.
443 (Reg): Replace by Class. Adjust comment.
444 (union i386_operand_type): Replace reg by class.
445 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
446 Class=.
447 * i386-reg.tbl: Replace Reg by Class=Reg.
448 * i386-init.h: Re-generate.
449
1f4cd317
MM		 4502019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
451
452 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
453 (aarch64_opcode_table): Add data gathering hint mnemonic.
454 * opcodes/aarch64-dis-2.c: Account for new instruction.
455
616ce08e
MM		 4562019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
457
458 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
459
460
8382113f
MM		 4612019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
462
463 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
464 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
465 aarch64_feature_f64mm): New feature sets.
466 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
467 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
468 instructions.
469 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
470 macros.
471 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
472 (OP_SVE_QQQ): New qualifier.
473 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
474 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
475 the movprfx constraint.
476 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
477 (aarch64_opcode_table): Define new instructions smmla,
478 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
479 uzip{1/2}, trn{1/2}.
480 * aarch64-opc.c (operand_general_constraint_met_p): Handle
481 AARCH64_OPND_SVE_ADDR_RI_S4x32.
482 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
483 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
484 Account for new instructions.
485 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
486 S4x32 operand.
487 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
488
aab2c27d
MM		 4892019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4902019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
491
492 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
493 Armv8.6-A.
494 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
495 (neon_opcodes): Add bfloat SIMD instructions.
496 (print_insn_coprocessor): Add new control character %b to print
497 condition code without checking cp_num.
498 (print_insn_neon): Account for BFloat16 instructions that have no
499 special top-byte handling.
500
33593eaf
MM		 5012019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5022019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
503
504 * arm-dis.c (print_insn_coprocessor,
505 print_insn_generic_coprocessor): Create wrapper functions around
506 the implementation of the print_insn_coprocessor control codes.
507 (print_insn_coprocessor_1): Original print_insn_coprocessor
508 function that now takes which array to look at as an argument.
509 (print_insn_arm): Use both print_insn_coprocessor and
510 print_insn_generic_coprocessor.
511 (print_insn_thumb32): As above.
512
df678013
MM		 5132019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5142019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
515
516 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
517 in reglane special case.
518 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
519 aarch64_find_next_opcode): Account for new instructions.
520 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
521 in reglane special case.
522 * aarch64-opc.c (struct operand_qualifier_data): Add data for
523 new AARCH64_OPND_QLF_S_2H qualifier.
524 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
525 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
526 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
527 sets.
528 (BFLOAT_SVE, BFLOAT): New feature set macros.
529 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
530 instructions.
531 (aarch64_opcode_table): Define new instructions bfdot,
532 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
533 bfcvtn2, bfcvt.
534
8ae2d3d9
MM		 5352019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5362019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
537
538 * aarch64-tbl.h (ARMV8_6): New macro.
539
142861df
JB		 5402019-11-07 Jan Beulich <jbeulich@suse.com>
541
542 * i386-dis.c (prefix_table): Add mcommit.
543 (rm_table): Add rdpru.
544 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
545 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
546 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
547 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
548 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
549 * i386-opc.tbl (mcommit, rdpru): New.
550 * i386-init.h, i386-tbl.h: Re-generate.
551
081e283f
JB		 5522019-11-07 Jan Beulich <jbeulich@suse.com>
553
554 * i386-dis.c (OP_Mwait): Drop local variable "names", use
555 "names32" instead.
556 (OP_Monitor): Drop local variable "op1_names", re-purpose
557 "names" for it instead, and replace former "names" uses by
558 "names32" ones.
559
c050c89a
JB		 5602019-11-07 Jan Beulich <jbeulich@suse.com>
561
562 PR/gas 25167
563 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
564 operand-less forms.
565 * opcodes/i386-tbl.h: Re-generate.
566
7abb8d81
JB		 5672019-11-05 Jan Beulich <jbeulich@suse.com>
568
569 * i386-dis.c (OP_Mwaitx): Delete.
570 (prefix_table): Use OP_Mwait for mwaitx entry.
571 (OP_Mwait): Also handle mwaitx.
572
267b8516
JB		 5732019-11-05 Jan Beulich <jbeulich@suse.com>
574
575 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
576 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
577 (prefix_table): Add respective entries.
578 (rm_table): Link to those entries.
579
f8687e93
JB		 5802019-11-05 Jan Beulich <jbeulich@suse.com>
581
582 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
583 (REG_0F1C_P_0_MOD_0): ... this.
584 (REG_0F1E_MOD_3): Rename to ...
585 (REG_0F1E_P_1_MOD_3): ... this.
586 (RM_0F01_REG_5): Rename to ...
587 (RM_0F01_REG_5_MOD_3): ... this.
588 (RM_0F01_REG_7): Rename to ...
589 (RM_0F01_REG_7_MOD_3): ... this.
590 (RM_0F1E_MOD_3_REG_7): Rename to ...
591 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
592 (RM_0FAE_REG_6): Rename to ...
593 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
594 (RM_0FAE_REG_7): Rename to ...
595 (RM_0FAE_REG_7_MOD_3): ... this.
596 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
597 (PREFIX_0F01_REG_5_MOD_0): ... this.
598 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
599 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
600 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
601 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
602 (PREFIX_0FAE_REG_0): Rename to ...
603 (PREFIX_0FAE_REG_0_MOD_3): ... this.
604 (PREFIX_0FAE_REG_1): Rename to ...
605 (PREFIX_0FAE_REG_1_MOD_3): ... this.
606 (PREFIX_0FAE_REG_2): Rename to ...
607 (PREFIX_0FAE_REG_2_MOD_3): ... this.
608 (PREFIX_0FAE_REG_3): Rename to ...
609 (PREFIX_0FAE_REG_3_MOD_3): ... this.
610 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
611 (PREFIX_0FAE_REG_4_MOD_0): ... this.
612 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
613 (PREFIX_0FAE_REG_4_MOD_3): ... this.
614 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
615 (PREFIX_0FAE_REG_5_MOD_0): ... this.
616 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
617 (PREFIX_0FAE_REG_5_MOD_3): ... this.
618 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
619 (PREFIX_0FAE_REG_6_MOD_0): ... this.
620 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
621 (PREFIX_0FAE_REG_6_MOD_3): ... this.
622 (PREFIX_0FAE_REG_7): Rename to ...
623 (PREFIX_0FAE_REG_7_MOD_0): ... this.
624 (PREFIX_MOD_0_0FC3): Rename to ...
625 (PREFIX_0FC3_MOD_0): ... this.
626 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
627 (PREFIX_0FC7_REG_6_MOD_0): ... this.
628 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
629 (PREFIX_0FC7_REG_6_MOD_3): ... this.
630 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
631 (PREFIX_0FC7_REG_7_MOD_3): ... this.
632 (reg_table, prefix_table, mod_table, rm_table): Adjust
633 accordingly.
634
5103274f
NC		 6352019-11-04 Nick Clifton <nickc@redhat.com>
636
637 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
638 of a v850 system register. Move the v850_sreg_names array into
639 this function.
640 (get_v850_reg_name): Likewise for ordinary register names.
641 (get_v850_vreg_name): Likewise for vector register names.
642 (get_v850_cc_name): Likewise for condition codes.
643 * get_v850_float_cc_name): Likewise for floating point condition
644 codes.
645 (get_v850_cacheop_name): Likewise for cache-ops.
646 (get_v850_prefop_name): Likewise for pref-ops.
647 (disassemble): Use the new accessor functions.
648
1820262b
DB		 6492019-10-30 Delia Burduv <delia.burduv@arm.com>
650
651 * aarch64-opc.c (print_immediate_offset_address): Don't print the
652 immediate for the writeback form of ldraa/ldrab if it is 0.
653 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
654 * aarch64-opc-2.c: Regenerated.
655
3cc17af5
JB		 6562019-10-30 Jan Beulich <jbeulich@suse.com>
657
658 * i386-gen.c (operand_type_shorthands): Delete.
659 (operand_type_init): Expand previous shorthands.
660 (set_bitfield_from_shorthand): Rename back to ...
661 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
662 of operand_type_init[].
663 (set_bitfield): Adjust call to the above function.
664 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
665 RegXMM, RegYMM, RegZMM): Define.
666 * i386-reg.tbl: Expand prior shorthands.
667
a2cebd03
JB		 6682019-10-30 Jan Beulich <jbeulich@suse.com>
669
670 * i386-gen.c (output_i386_opcode): Change order of fields
671 emitted to output.
672 * i386-opc.h (struct insn_template): Move operands field.
673 Convert extension_opcode field to unsigned short.
674 * i386-tbl.h: Re-generate.
675
507916b8
JB		 6762019-10-30 Jan Beulich <jbeulich@suse.com>
677
678 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
679 of W.
680 * i386-opc.h (W): Extend comment.
681 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
682 general purpose variants not allowing for byte operands.
683 * i386-tbl.h: Re-generate.
684
efea62b4
NC		 6852019-10-29 Nick Clifton <nickc@redhat.com>
686
687 * tic30-dis.c (print_branch): Correct size of operand array.
688
9adb2591
NC		 6892019-10-29 Nick Clifton <nickc@redhat.com>
690
691 * d30v-dis.c (print_insn): Check that operand index is valid
692 before attempting to access the operands array.
693
993a00a9
NC		 6942019-10-29 Nick Clifton <nickc@redhat.com>
695
696 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
697 locating the bit to be tested.
698
66a66a17
NC		 6992019-10-29 Nick Clifton <nickc@redhat.com>
700
701 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
702 values.
703 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
704 (print_insn_s12z): Check for illegal size values.
705
1ee3542c
NC		 7062019-10-28 Nick Clifton <nickc@redhat.com>
707
708 * csky-dis.c (csky_chars_to_number): Check for a negative
709 count. Use an unsigned integer to construct the return value.
710
bbf9a0b5
NC		 7112019-10-28 Nick Clifton <nickc@redhat.com>
712
713 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
714 operand buffer. Set value to 15 not 13.
715 (get_register_operand): Use OPERAND_BUFFER_LEN.
716 (get_indirect_operand): Likewise.
717 (print_two_operand): Likewise.
718 (print_three_operand): Likewise.
719 (print_oar_insn): Likewise.
720
d1e304bc
NC		 7212019-10-28 Nick Clifton <nickc@redhat.com>
722
723 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
724 (bit_extract_simple): Likewise.
725 (bit_copy): Likewise.
726 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
727 index_offset array are not accessed.
728
dee33451
NC		 7292019-10-28 Nick Clifton <nickc@redhat.com>
730
731 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
732 operand.
733
27cee81d
NC		 7342019-10-25 Nick Clifton <nickc@redhat.com>
735
736 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
737 access to opcodes.op array element.
738
de6d8dc2
NC		 7392019-10-23 Nick Clifton <nickc@redhat.com>
740
741 * rx-dis.c (get_register_name): Fix spelling typo in error
742 message.
743 (get_condition_name, get_flag_name, get_double_register_name)
744 (get_double_register_high_name, get_double_register_low_name)
745 (get_double_control_register_name, get_double_condition_name)
746 (get_opsize_name, get_size_name): Likewise.
747
6207ed28
NC		 7482019-10-22 Nick Clifton <nickc@redhat.com>
749
750 * rx-dis.c (get_size_name): New function. Provides safe
751 access to name array.
752 (get_opsize_name): Likewise.
753 (print_insn_rx): Use the accessor functions.
754
12234dfd
NC		 7552019-10-16 Nick Clifton <nickc@redhat.com>
756
757 * rx-dis.c (get_register_name): New function. Provides safe
758 access to name array.
759 (get_condition_name, get_flag_name, get_double_register_name)
760 (get_double_register_high_name, get_double_register_low_name)
761 (get_double_control_register_name, get_double_condition_name):
762 Likewise.
763 (print_insn_rx): Use the accessor functions.
764
1d378749
NC		 7652019-10-09 Nick Clifton <nickc@redhat.com>
766
767 PR 25041
768 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
769 instructions.
770
d241b910
JB		 7712019-10-07 Jan Beulich <jbeulich@suse.com>
772
773 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
774 (cmpsd): Likewise. Move EsSeg to other operand.
775 * opcodes/i386-tbl.h: Re-generate.
776
f5c5b7c1
AM		 7772019-09-23 Alan Modra <amodra@gmail.com>
778
779 * m68k-dis.c: Include cpu-m68k.h
780
7beeaeb8
AM		 7812019-09-23 Alan Modra <amodra@gmail.com>
782
783 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
784 "elf/mips.h" earlier.
785
3f9aad11
JB		 7862018-09-20 Jan Beulich <jbeulich@suse.com>
787
788 PR gas/25012
789 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
790 with SReg operand.
791 * i386-tbl.h: Re-generate.
792
fd361982
AM		 7932019-09-18 Alan Modra <amodra@gmail.com>
794
795 * arc-ext.c: Update throughout for bfd section macro changes.
796
e0b2a78c
SM		 7972019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
798
799 * Makefile.in: Re-generate.
800 * configure: Re-generate.
801
7e9ad3a3
JW		 8022019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
803
804 * riscv-opc.c (riscv_opcodes): Change subset field
805 to insn_class field for all instructions.
806 (riscv_insn_types): Likewise.
807
bb695960
PB		 8082019-09-16 Phil Blundell <pb@pbcl.net>
809
810 * configure: Regenerated.
811
8063ab7e
MV		 8122019-09-10 Miod Vallat <miod@online.fr>
813
814 PR 24982
815 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
816
60391a25
PB		 8172019-09-09 Phil Blundell <pb@pbcl.net>
818
819 binutils 2.33 branch created.
820
f44b758d
NC		 8212019-09-03 Nick Clifton <nickc@redhat.com>
822
823 PR 24961
824 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
825 greater than zero before indexing via (bufcnt -1).
826
1e4b5e7d
NC		 8272019-09-03 Nick Clifton <nickc@redhat.com>
828
829 PR 24958
830 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
831 (MAX_SPEC_REG_NAME_LEN): Define.
832 (struct mmix_dis_info): Use defined constants for array lengths.
833 (get_reg_name): New function.
834 (get_sprec_reg_name): New function.
835 (print_insn_mmix): Use new functions.
836
c4a23bf8
SP		 8372019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
838
839 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
840 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
841 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
842
a051e2f3
KT		 8432019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
844
845 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
846 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
847 (aarch64_sys_reg_supported_p): Update checks for the above.
848
08132bdd
SP		 8492019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
850
851 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
852 cases MVE_SQRSHRL and MVE_UQRSHLL.
853 (print_insn_mve): Add case for specifier 'k' to check
854 specific bit of the instruction.
855
d88bdcb4
PA		 8562019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
857
858 PR 24854
859 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
860 encountering an unknown machine type.
861 (print_insn_arc): Handle arc_insn_length returning 0. In error
862 cases return -1 rather than calling abort.
863
bc750500
JB		 8642019-08-07 Jan Beulich <jbeulich@suse.com>
865
866 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
867 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
868 IgnoreSize.
869 * i386-tbl.h: Re-generate.
870
23d188c7
BW		 8712019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
872
873 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
874 instructions.
875
c0d6f62f
JW		 8762019-07-30 Mel Chen <mel.chen@sifive.com>
877
878 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
879 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
880
881 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
882 fscsr.
883
0f3f7167
CZ		 8842019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
885
886 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
887 and MPY class instructions.
888 (parse_option): Add nps400 option.
889 (print_arc_disassembler_options): Add nps400 info.
890
7e126ba3
CZ		 8912019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
892
893 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
894 (bspop): Likewise.
895 (modapp): Likewise.
896 * arc-opc.c (RAD_CHK): Add.
897 * arc-tbl.h: Regenerate.
898
a028026d
KT		 8992019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
900
901 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
902 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
903
ac79ff9e
NC		 9042019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
905
906 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
907 instructions as UNPREDICTABLE.
908
231097b0
JM		 9092019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
910
911 * bpf-desc.c: Regenerated.
912
1d942ae9
JB		 9132019-07-17 Jan Beulich <jbeulich@suse.com>
914
915 * i386-gen.c (static_assert): Define.
916 (main): Use it.
917 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
918 (Opcode_Modifier_Num): ... this.
919 (Mem): Delete.
920
dfd69174
JB		 9212019-07-16 Jan Beulich <jbeulich@suse.com>
922
923 * i386-gen.c (operand_types): Move RegMem ...
924 (opcode_modifiers): ... here.
925 * i386-opc.h (RegMem): Move to opcode modifer enum.
926 (union i386_operand_type): Move regmem field ...
927 (struct i386_opcode_modifier): ... here.
928 * i386-opc.tbl (RegMem): Define.
929 (mov, movq): Move RegMem on segment, control, debug, and test
930 register flavors.
931 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
932 to non-SSE2AVX flavor.
933 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
934 Move RegMem on register only flavors. Drop IgnoreSize from
935 legacy encoding flavors.
936 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
937 flavors.
938 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
939 register only flavors.
940 (vmovd): Move RegMem and drop IgnoreSize on register only
941 flavor. Change opcode and operand order to store form.
942 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
943
21df382b
JB		 9442019-07-16 Jan Beulich <jbeulich@suse.com>
945
946 * i386-gen.c (operand_type_init, operand_types): Replace SReg
947 entries.
948 * i386-opc.h (SReg2, SReg3): Replace by ...
949 (SReg): ... this.
950 (union i386_operand_type): Replace sreg fields.
951 * i386-opc.tbl (mov, ): Use SReg.
952 (push, pop): Likewies. Drop i386 and x86-64 specific segment
953 register flavors.
954 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
955 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
956
3719fd55
JM		 9572019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
958
959 * bpf-desc.c: Regenerate.
960 * bpf-opc.c: Likewise.
961 * bpf-opc.h: Likewise.
962
92434a14
JM		 9632019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
964
965 * bpf-desc.c: Regenerate.
966 * bpf-opc.c: Likewise.
967
43dd7626
HPN		 9682019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
969
970 * arm-dis.c (print_insn_coprocessor): Rename index to
971 index_operand.
972
98602811
JW		 9732019-07-05 Kito Cheng <kito.cheng@sifive.com>
974
975 * riscv-opc.c (riscv_insn_types): Add r4 type.
976
977 * riscv-opc.c (riscv_insn_types): Add b and j type.
978
979 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
980 format for sb type and correct s type.
981
01c1ee4a
RS		 9822019-07-02 Richard Sandiford <richard.sandiford@arm.com>
983
984 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
985 SVE FMOV alias of FCPY.
986
83adff69
RS		 9872019-07-02 Richard Sandiford <richard.sandiford@arm.com>
988
989 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
990 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
991
89418844
RS		 9922019-07-02 Richard Sandiford <richard.sandiford@arm.com>
993
994 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
995 registers in an instruction prefixed by MOVPRFX.
996
41be57ca
MM		 9972019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
998
999 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1000 sve_size_13 icode to account for variant behaviour of
1001 pmull{t,b}.
1002 * aarch64-dis-2.c: Regenerate.
1003 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1004 sve_size_13 icode to account for variant behaviour of
1005 pmull{t,b}.
1006 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1007 (OP_SVE_VVV_Q_D): Add new qualifier.
1008 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1009 (struct aarch64_opcode): Split pmull{t,b} into those requiring
1010 AES and those not.
1011
9d3bf266
JB		 10122019-07-01 Jan Beulich <jbeulich@suse.com>
1013
1014 * opcodes/i386-gen.c (operand_type_init): Remove
1015 OPERAND_TYPE_VEC_IMM4 entry.
1016 (operand_types): Remove Vec_Imm4.
1017 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1018 (union i386_operand_type): Remove vec_imm4.
1019 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1020 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1021
c3949f43
JB		 10222019-07-01 Jan Beulich <jbeulich@suse.com>
1023
1024 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1025 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1026 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1027 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1028 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1029 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1030 * i386-tbl.h: Re-generate.
1031
5641ec01
JB		 10322019-07-01 Jan Beulich <jbeulich@suse.com>
1033
1034 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1035 register operands.
1036 * i386-tbl.h: Re-generate.
1037
79dec6b7
JB		 10382019-07-01 Jan Beulich <jbeulich@suse.com>
1039
1040 * i386-opc.tbl (C): New.
1041 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1042 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1043 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1044 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1045 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1046 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1047 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1048 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1049 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1050 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1051 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1052 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1053 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1054 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1055 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1056 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1057 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1058 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1059 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1060 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1061 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1062 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1063 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1064 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1065 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1066 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1067 flavors.
1068 * i386-tbl.h: Re-generate.
1069
a0a1771e
JB		 10702019-07-01 Jan Beulich <jbeulich@suse.com>
1071
1072 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1073 register operands.
1074 * i386-tbl.h: Re-generate.
1075
cd546e7b
JB		 10762019-07-01 Jan Beulich <jbeulich@suse.com>
1077
1078 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1079 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1080 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1081 * i386-tbl.h: Re-generate.
1082
e3bba3fc
JB		 10832019-07-01 Jan Beulich <jbeulich@suse.com>
1084
1085 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1086 Disp8MemShift from register only templates.
1087 * i386-tbl.h: Re-generate.
1088
36cc073e
JB		 10892019-07-01 Jan Beulich <jbeulich@suse.com>
1090
1091 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1092 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1093 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1094 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1095 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1096 EVEX_W_0F11_P_3_M_1): Delete.
1097 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1098 EVEX_W_0F11_P_3): New.
1099 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1100 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1101 MOD_EVEX_0F11_PREFIX_3 table entries.
1102 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1103 PREFIX_EVEX_0F11 table entries.
1104 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1105 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1106 EVEX_W_0F11_P_3_M_{0,1} table entries.
1107
219920a7
JB		 11082019-07-01 Jan Beulich <jbeulich@suse.com>
1109
1110 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1111 Delete.
1112
e395f487
L		 11132019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1114
1115 PR binutils/24719
1116 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1117 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1118 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1119 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1120 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1121 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1122 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1123 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1124 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1125 PREFIX_EVEX_0F38C6_REG_6 entries.
1126 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1127 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1128 EVEX_W_0F38C7_R_6_P_2 entries.
1129 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1130 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1131 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1132 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1133 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1134 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1135 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1136
2b7bcc87
JB		 11372019-06-27 Jan Beulich <jbeulich@suse.com>
1138
1139 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1140 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1141 VEX_LEN_0F2D_P_3): Delete.
1142 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1143 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1144 (prefix_table): ... here.
1145
c1dc7af5
JB		 11462019-06-27 Jan Beulich <jbeulich@suse.com>
1147
1148 * i386-dis.c (Iq): Delete.
1149 (Id): New.
1150 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1151 TBM insns.
1152 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1153 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1154 (OP_E_memory): Also honor needindex when deciding whether an
1155 address size prefix needs printing.
1156 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1157
d7560e2d
JW		 11582019-06-26 Jim Wilson <jimw@sifive.com>
1159
1160 PR binutils/24739
1161 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1162 Set info->display_endian to info->endian_code.
1163
2c703856
JB		 11642019-06-25 Jan Beulich <jbeulich@suse.com>
1165
1166 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1167 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1168 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1169 OPERAND_TYPE_ACC64 entries.
1170 * i386-init.h: Re-generate.
1171
54fbadc0
JB		 11722019-06-25 Jan Beulich <jbeulich@suse.com>
1173
1174 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1175 Delete.
1176 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1177 of dqa_mode.
1178 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1179 entries here.
1180 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1181 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1182
a280ab8e
JB		 11832019-06-25 Jan Beulich <jbeulich@suse.com>
1184
1185 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1186 variables.
1187
e1a1babd
JB		 11882019-06-25 Jan Beulich <jbeulich@suse.com>
1189
1190 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1191 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1192 movnti.
d7560e2d 1193 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1194 * i386-tbl.h: Re-generate.
1195
b8364fa7
JB		 11962019-06-25 Jan Beulich <jbeulich@suse.com>
1197
1198 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1199 * i386-tbl.h: Re-generate.
1200
ad692897
L		 12012019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1202
1203 * i386-dis-evex.h: Break into ...
1204 * i386-dis-evex-len.h: New file.
1205 * i386-dis-evex-mod.h: Likewise.
1206 * i386-dis-evex-prefix.h: Likewise.
1207 * i386-dis-evex-reg.h: Likewise.
1208 * i386-dis-evex-w.h: Likewise.
1209 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1210 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1211 i386-dis-evex-mod.h.
1212
f0a6222e
L		 12132019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1214
1215 PR binutils/24700
1216 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1217 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1218 EVEX_W_0F385B_P_2.
1219 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1220 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1221 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1222 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1223 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1224 EVEX_LEN_0F385B_P_2_W_1.
1225 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1226 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1227 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1228 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1229 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1230 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1231 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1232 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1233 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1234 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1235
6e1c90b7
L		 12362019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1237
1238 PR binutils/24691
1239 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1240 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1241 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1242 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1243 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1244 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1245 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1246 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1247 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1248 EVEX_LEN_0F3A43_P_2_W_1.
1249 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1250 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1251 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1252 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1253 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1254 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1255 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1256 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1257 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1258 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1259 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1260 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1261
bcc5a6eb
NC		 12622019-06-14 Nick Clifton <nickc@redhat.com>
1263
1264 * po/fr.po; Updated French translation.
1265
e4c4ac46
SH		 12662019-06-13 Stafford Horne <shorne@gmail.com>
1267
1268 * or1k-asm.c: Regenerated.
1269 * or1k-desc.c: Regenerated.
1270 * or1k-desc.h: Regenerated.
1271 * or1k-dis.c: Regenerated.
1272 * or1k-ibld.c: Regenerated.
1273 * or1k-opc.c: Regenerated.
1274 * or1k-opc.h: Regenerated.
1275 * or1k-opinst.c: Regenerated.
1276
a0e44ef5
PB		 12772019-06-12 Peter Bergner <bergner@linux.ibm.com>
1278
1279 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1280
12efd68d
L		 12812019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1282
1283 PR binutils/24633
1284 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1285 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1286 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1287 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1288 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1289 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1290 EVEX_LEN_0F3A1B_P_2_W_1.
1291 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1292 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1293 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1294 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1295 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1296 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1297 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1298 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1299
63c6fc6c
L		 13002019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1301
1302 PR binutils/24626
1303 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1304 EVEX.vvvv when disassembling VEX and EVEX instructions.
1305 (OP_VEX): Set vex.register_specifier to 0 after readding
1306 vex.register_specifier.
1307 (OP_Vex_2src_1): Likewise.
1308 (OP_Vex_2src_2): Likewise.
1309 (OP_LWP_E): Likewise.
1310 (OP_EX_Vex): Don't check vex.register_specifier.
1311 (OP_XMM_Vex): Likewise.
1312
9186c494
L		 13132019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1314 Lili Cui <lili.cui@intel.com>
1315
1316 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1317 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1318 instructions.
1319 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1320 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1321 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1322 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1323 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1324 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1325 * i386-init.h: Regenerated.
1326 * i386-tbl.h: Likewise.
1327
5d79adc4
L		 13282019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1329 Lili Cui <lili.cui@intel.com>
1330
1331 * doc/c-i386.texi: Document enqcmd.
1332 * testsuite/gas/i386/enqcmd-intel.d: New file.
1333 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1334 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1335 * testsuite/gas/i386/enqcmd.d: Likewise.
1336 * testsuite/gas/i386/enqcmd.s: Likewise.
1337 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1338 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1339 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1340 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1341 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1342 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1343 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1344 and x86-64-enqcmd.
1345
a9d96ab9
AH		 13462019-06-04 Alan Hayward <alan.hayward@arm.com>
1347
1348 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1349
4f6d070a
AM		 13502019-06-03 Alan Modra <amodra@gmail.com>
1351
1352 * ppc-dis.c (prefix_opcd_indices): Correct size.
1353
a2f4b66c
L		 13542019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1355
1356 PR gas/24625
1357 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1358 Disp8ShiftVL.
1359 * i386-tbl.h: Regenerated.
1360
405b5bd8
AM		 13612019-05-24 Alan Modra <amodra@gmail.com>
1362
1363 * po/POTFILES.in: Regenerate.
1364
8acf1435
PB		 13652019-05-24 Peter Bergner <bergner@linux.ibm.com>
1366 Alan Modra <amodra@gmail.com>
1367
1368 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1369 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1370 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1371 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1372 XTOP>): Define and add entries.
1373 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1374 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1375 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1376 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1377
dd7efa79
PB		 13782019-05-24 Peter Bergner <bergner@linux.ibm.com>
1379 Alan Modra <amodra@gmail.com>
1380
1381 * ppc-dis.c (ppc_opts): Add "future" entry.
1382 (PREFIX_OPCD_SEGS): Define.
1383 (prefix_opcd_indices): New array.
1384 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1385 (lookup_prefix): New function.
1386 (print_insn_powerpc): Handle 64-bit prefix instructions.
1387 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1388 (PMRR, POWERXX): Define.
1389 (prefix_opcodes): New instruction table.
1390 (prefix_num_opcodes): New constant.
1391
79472b45
JM		 13922019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1393
1394 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1395 * configure: Regenerated.
1396 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1397 and cpu/bpf.opc.
1398 (HFILES): Add bpf-desc.h and bpf-opc.h.
1399 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1400 bpf-ibld.c and bpf-opc.c.
1401 (BPF_DEPS): Define.
1402 * Makefile.in: Regenerated.
1403 * disassemble.c (ARCH_bpf): Define.
1404 (disassembler): Add case for bfd_arch_bpf.
1405 (disassemble_init_for_target): Likewise.
1406 (enum epbf_isa_attr): Define.
1407 * disassemble.h: extern print_insn_bpf.
1408 * bpf-asm.c: Generated.
1409 * bpf-opc.h: Likewise.
1410 * bpf-opc.c: Likewise.
1411 * bpf-ibld.c: Likewise.
1412 * bpf-dis.c: Likewise.
1413 * bpf-desc.h: Likewise.
1414 * bpf-desc.c: Likewise.
1415
ba6cd17f
SD		 14162019-05-21 Sudakshina Das <sudi.das@arm.com>
1417
1418 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1419 and VMSR with the new operands.
1420
e39c1607
SD		 14212019-05-21 Sudakshina Das <sudi.das@arm.com>
1422
1423 * arm-dis.c (enum mve_instructions): New enum
1424 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1425 and cneg.
1426 (mve_opcodes): New instructions as above.
1427 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1428 csneg and csel.
1429 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1430
23d00a41
SD		 14312019-05-21 Sudakshina Das <sudi.das@arm.com>
1432
1433 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1434 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1435 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1436 uqshl, urshrl and urshr.
1437 (is_mve_okay_in_it): Add new instructions to TRUE list.
1438 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1439 (print_insn_mve): Updated to accept new %j,
1440 %<bitfield>m and %<bitfield>n patterns.
1441
cd4797ee
FS		 14422019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1443
1444 * mips-opc.c (mips_builtin_opcodes): Change source register
1445 constraint for DAUI.
1446
999b073b
NC		 14472019-05-20 Nick Clifton <nickc@redhat.com>
1448
1449 * po/fr.po: Updated French translation.
1450
14b456f2
AV		 14512019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1452 Michael Collison <michael.collison@arm.com>
1453
1454 * arm-dis.c (thumb32_opcodes): Add new instructions.
1455 (enum mve_instructions): Likewise.
1456 (enum mve_undefined): Add new reasons.
1457 (is_mve_encoding_conflict): Handle new instructions.
1458 (is_mve_undefined): Likewise.
1459 (is_mve_unpredictable): Likewise.
1460 (print_mve_undefined): Likewise.
1461 (print_mve_size): Likewise.
1462
f49bb598
AV		 14632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1464 Michael Collison <michael.collison@arm.com>
1465
1466 * arm-dis.c (thumb32_opcodes): Add new instructions.
1467 (enum mve_instructions): Likewise.
1468 (is_mve_encoding_conflict): Handle new instructions.
1469 (is_mve_undefined): Likewise.
1470 (is_mve_unpredictable): Likewise.
1471 (print_mve_size): Likewise.
1472
56858bea
AV		 14732019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1474 Michael Collison <michael.collison@arm.com>
1475
1476 * arm-dis.c (thumb32_opcodes): Add new instructions.
1477 (enum mve_instructions): Likewise.
1478 (is_mve_encoding_conflict): Likewise.
1479 (is_mve_unpredictable): Likewise.
1480 (print_mve_size): Likewise.
1481
e523f101
AV		 14822019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1483 Michael Collison <michael.collison@arm.com>
1484
1485 * arm-dis.c (thumb32_opcodes): Add new instructions.
1486 (enum mve_instructions): Likewise.
1487 (is_mve_encoding_conflict): Handle new instructions.
1488 (is_mve_undefined): Likewise.
1489 (is_mve_unpredictable): Likewise.
1490 (print_mve_size): Likewise.
1491
66dcaa5d
AV		 14922019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1493 Michael Collison <michael.collison@arm.com>
1494
1495 * arm-dis.c (thumb32_opcodes): Add new instructions.
1496 (enum mve_instructions): Likewise.
1497 (is_mve_encoding_conflict): Handle new instructions.
1498 (is_mve_undefined): Likewise.
1499 (is_mve_unpredictable): Likewise.
1500 (print_mve_size): Likewise.
1501 (print_insn_mve): Likewise.
1502
d052b9b7
AV		 15032019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1504 Michael Collison <michael.collison@arm.com>
1505
1506 * arm-dis.c (thumb32_opcodes): Add new instructions.
1507 (print_insn_thumb32): Handle new instructions.
1508
ed63aa17
AV		 15092019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1510 Michael Collison <michael.collison@arm.com>
1511
1512 * arm-dis.c (enum mve_instructions): Add new instructions.
1513 (enum mve_undefined): Add new reasons.
1514 (is_mve_encoding_conflict): Handle new instructions.
1515 (is_mve_undefined): Likewise.
1516 (is_mve_unpredictable): Likewise.
1517 (print_mve_undefined): Likewise.
1518 (print_mve_size): Likewise.
1519 (print_mve_shift_n): Likewise.
1520 (print_insn_mve): Likewise.
1521
897b9bbc
AV		 15222019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1523 Michael Collison <michael.collison@arm.com>
1524
1525 * arm-dis.c (enum mve_instructions): Add new instructions.
1526 (is_mve_encoding_conflict): Handle new instructions.
1527 (is_mve_unpredictable): Likewise.
1528 (print_mve_rotate): Likewise.
1529 (print_mve_size): Likewise.
1530 (print_insn_mve): Likewise.
1531
1c8f2df8
AV		 15322019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1533 Michael Collison <michael.collison@arm.com>
1534
1535 * arm-dis.c (enum mve_instructions): Add new instructions.
1536 (is_mve_encoding_conflict): Handle new instructions.
1537 (is_mve_unpredictable): Likewise.
1538 (print_mve_size): Likewise.
1539 (print_insn_mve): Likewise.
1540
d3b63143
AV		 15412019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1542 Michael Collison <michael.collison@arm.com>
1543
1544 * arm-dis.c (enum mve_instructions): Add new instructions.
1545 (enum mve_undefined): Add new reasons.
1546 (is_mve_encoding_conflict): Handle new instructions.
1547 (is_mve_undefined): Likewise.
1548 (is_mve_unpredictable): Likewise.
1549 (print_mve_undefined): Likewise.
1550 (print_mve_size): Likewise.
1551 (print_insn_mve): Likewise.
1552
14925797
AV		 15532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1554 Michael Collison <michael.collison@arm.com>
1555
1556 * arm-dis.c (enum mve_instructions): Add new instructions.
1557 (is_mve_encoding_conflict): Handle new instructions.
1558 (is_mve_undefined): Likewise.
1559 (is_mve_unpredictable): Likewise.
1560 (print_mve_size): Likewise.
1561 (print_insn_mve): Likewise.
1562
c507f10b
AV		 15632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1564 Michael Collison <michael.collison@arm.com>
1565
1566 * arm-dis.c (enum mve_instructions): Add new instructions.
1567 (enum mve_unpredictable): Add new reasons.
1568 (enum mve_undefined): Likewise.
1569 (is_mve_okay_in_it): Handle new isntructions.
1570 (is_mve_encoding_conflict): Likewise.
1571 (is_mve_undefined): Likewise.
1572 (is_mve_unpredictable): Likewise.
1573 (print_mve_vmov_index): Likewise.
1574 (print_simd_imm8): Likewise.
1575 (print_mve_undefined): Likewise.
1576 (print_mve_unpredictable): Likewise.
1577 (print_mve_size): Likewise.
1578 (print_insn_mve): Likewise.
1579
bf0b396d
AV		 15802019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1581 Michael Collison <michael.collison@arm.com>
1582
1583 * arm-dis.c (enum mve_instructions): Add new instructions.
1584 (enum mve_unpredictable): Add new reasons.
1585 (enum mve_undefined): Likewise.
1586 (is_mve_encoding_conflict): Handle new instructions.
1587 (is_mve_undefined): Likewise.
1588 (is_mve_unpredictable): Likewise.
1589 (print_mve_undefined): Likewise.
1590 (print_mve_unpredictable): Likewise.
1591 (print_mve_rounding_mode): Likewise.
1592 (print_mve_vcvt_size): Likewise.
1593 (print_mve_size): Likewise.
1594 (print_insn_mve): Likewise.
1595
ef1576a1
AV		 15962019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1597 Michael Collison <michael.collison@arm.com>
1598
1599 * arm-dis.c (enum mve_instructions): Add new instructions.
1600 (enum mve_unpredictable): Add new reasons.
1601 (enum mve_undefined): Likewise.
1602 (is_mve_undefined): Handle new instructions.
1603 (is_mve_unpredictable): Likewise.
1604 (print_mve_undefined): Likewise.
1605 (print_mve_unpredictable): Likewise.
1606 (print_mve_size): Likewise.
1607 (print_insn_mve): Likewise.
1608
aef6d006
AV		 16092019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1610 Michael Collison <michael.collison@arm.com>
1611
1612 * arm-dis.c (enum mve_instructions): Add new instructions.
1613 (enum mve_undefined): Add new reasons.
1614 (insns): Add new instructions.
1615 (is_mve_encoding_conflict):
1616 (print_mve_vld_str_addr): New print function.
1617 (is_mve_undefined): Handle new instructions.
1618 (is_mve_unpredictable): Likewise.
1619 (print_mve_undefined): Likewise.
1620 (print_mve_size): Likewise.
1621 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1622 (print_insn_mve): Handle new operands.
1623
04d54ace
AV		 16242019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1625 Michael Collison <michael.collison@arm.com>
1626
1627 * arm-dis.c (enum mve_instructions): Add new instructions.
1628 (enum mve_unpredictable): Add new reasons.
1629 (is_mve_encoding_conflict): Handle new instructions.
1630 (is_mve_unpredictable): Likewise.
1631 (mve_opcodes): Add new instructions.
1632 (print_mve_unpredictable): Handle new reasons.
1633 (print_mve_register_blocks): New print function.
1634 (print_mve_size): Handle new instructions.
1635 (print_insn_mve): Likewise.
1636
9743db03
AV		 16372019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1638 Michael Collison <michael.collison@arm.com>
1639
1640 * arm-dis.c (enum mve_instructions): Add new instructions.
1641 (enum mve_unpredictable): Add new reasons.
1642 (enum mve_undefined): Likewise.
1643 (is_mve_encoding_conflict): Handle new instructions.
1644 (is_mve_undefined): Likewise.
1645 (is_mve_unpredictable): Likewise.
1646 (coprocessor_opcodes): Move NEON VDUP from here...
1647 (neon_opcodes): ... to here.
1648 (mve_opcodes): Add new instructions.
1649 (print_mve_undefined): Handle new reasons.
1650 (print_mve_unpredictable): Likewise.
1651 (print_mve_size): Handle new instructions.
1652 (print_insn_neon): Handle vdup.
1653 (print_insn_mve): Handle new operands.
1654
143275ea
AV		 16552019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1656 Michael Collison <michael.collison@arm.com>
1657
1658 * arm-dis.c (enum mve_instructions): Add new instructions.
1659 (enum mve_unpredictable): Add new values.
1660 (mve_opcodes): Add new instructions.
1661 (vec_condnames): New array with vector conditions.
1662 (mve_predicatenames): New array with predicate suffixes.
1663 (mve_vec_sizename): New array with vector sizes.
1664 (enum vpt_pred_state): New enum with vector predication states.
1665 (struct vpt_block): New struct type for vpt blocks.
1666 (vpt_block_state): Global struct to keep track of state.
1667 (mve_extract_pred_mask): New helper function.
1668 (num_instructions_vpt_block): Likewise.
1669 (mark_outside_vpt_block): Likewise.
1670 (mark_inside_vpt_block): Likewise.
1671 (invert_next_predicate_state): Likewise.
1672 (update_next_predicate_state): Likewise.
1673 (update_vpt_block_state): Likewise.
1674 (is_vpt_instruction): Likewise.
1675 (is_mve_encoding_conflict): Add entries for new instructions.
1676 (is_mve_unpredictable): Likewise.
1677 (print_mve_unpredictable): Handle new cases.
1678 (print_instruction_predicate): Likewise.
1679 (print_mve_size): New function.
1680 (print_vec_condition): New function.
1681 (print_insn_mve): Handle vpt blocks and new print operands.
1682
f08d8ce3
AV		 16832019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1684
1685 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1686 8, 14 and 15 for Armv8.1-M Mainline.
1687
73cd51e5
AV		 16882019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1689 Michael Collison <michael.collison@arm.com>
1690
1691 * arm-dis.c (enum mve_instructions): New enum.
1692 (enum mve_unpredictable): Likewise.
1693 (enum mve_undefined): Likewise.
1694 (struct mopcode32): New struct.
1695 (is_mve_okay_in_it): New function.
1696 (is_mve_architecture): Likewise.
1697 (arm_decode_field): Likewise.
1698 (arm_decode_field_multiple): Likewise.
1699 (is_mve_encoding_conflict): Likewise.
1700 (is_mve_undefined): Likewise.
1701 (is_mve_unpredictable): Likewise.
1702 (print_mve_undefined): Likewise.
1703 (print_mve_unpredictable): Likewise.
1704 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1705 (print_insn_mve): New function.
1706 (print_insn_thumb32): Handle MVE architecture.
1707 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1708
3076e594
NC		 17092019-05-10 Nick Clifton <nickc@redhat.com>
1710
1711 PR 24538
1712 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1713 end of the table prematurely.
1714
387e7624
FS		 17152019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1716
1717 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1718 macros for R6.
1719
0067be51
AM		 17202019-05-11 Alan Modra <amodra@gmail.com>
1721
1722 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1723 when -Mraw is in effect.
1724
42e6288f
MM		 17252019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1726
1727 * aarch64-dis-2.c: Regenerate.
1728 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1729 (OP_SVE_BBB): New variant set.
1730 (OP_SVE_DDDD): New variant set.
1731 (OP_SVE_HHH): New variant set.
1732 (OP_SVE_HHHU): New variant set.
1733 (OP_SVE_SSS): New variant set.
1734 (OP_SVE_SSSU): New variant set.
1735 (OP_SVE_SHH): New variant set.
1736 (OP_SVE_SBBU): New variant set.
1737 (OP_SVE_DSS): New variant set.
1738 (OP_SVE_DHHU): New variant set.
1739 (OP_SVE_VMV_HSD_BHS): New variant set.
1740 (OP_SVE_VVU_HSD_BHS): New variant set.
1741 (OP_SVE_VVVU_SD_BH): New variant set.
1742 (OP_SVE_VVVU_BHSD): New variant set.
1743 (OP_SVE_VVV_QHD_DBS): New variant set.
1744 (OP_SVE_VVV_HSD_BHS): New variant set.
1745 (OP_SVE_VVV_HSD_BHS2): New variant set.
1746 (OP_SVE_VVV_BHS_HSD): New variant set.
1747 (OP_SVE_VV_BHS_HSD): New variant set.
1748 (OP_SVE_VVV_SD): New variant set.
1749 (OP_SVE_VVU_BHS_HSD): New variant set.
1750 (OP_SVE_VZVV_SD): New variant set.
1751 (OP_SVE_VZVV_BH): New variant set.
1752 (OP_SVE_VZV_SD): New variant set.
1753 (aarch64_opcode_table): Add sve2 instructions.
1754
28ed815a
MM		 17552019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1756
1757 * aarch64-asm-2.c: Regenerated.
1758 * aarch64-dis-2.c: Regenerated.
1759 * aarch64-opc-2.c: Regenerated.
1760 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1761 for SVE_SHLIMM_UNPRED_22.
1762 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1763 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1764 operand.
1765
fd1dc4a0
MM		 17662019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1767
1768 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1769 sve_size_tsz_bhs iclass encode.
1770 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1771 sve_size_tsz_bhs iclass decode.
1772
31e36ab3
MM		 17732019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1774
1775 * aarch64-asm-2.c: Regenerated.
1776 * aarch64-dis-2.c: Regenerated.
1777 * aarch64-opc-2.c: Regenerated.
1778 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1779 for SVE_Zm4_11_INDEX.
1780 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1781 (fields): Handle SVE_i2h field.
1782 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1783 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1784
1be5f94f
MM		 17852019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1786
1787 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1788 sve_shift_tsz_bhsd iclass encode.
1789 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1790 sve_shift_tsz_bhsd iclass decode.
1791
3c17238b
MM		 17922019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1793
1794 * aarch64-asm-2.c: Regenerated.
1795 * aarch64-dis-2.c: Regenerated.
1796 * aarch64-opc-2.c: Regenerated.
1797 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1798 (aarch64_encode_variant_using_iclass): Handle
1799 sve_shift_tsz_hsd iclass encode.
1800 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1801 sve_shift_tsz_hsd iclass decode.
1802 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1803 for SVE_SHRIMM_UNPRED_22.
1804 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1805 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1806 operand.
1807
cd50a87a
MM		 18082019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1809
1810 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1811 sve_size_013 iclass encode.
1812 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1813 sve_size_013 iclass decode.
1814
3c705960
MM		 18152019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1816
1817 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1818 sve_size_bh iclass encode.
1819 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1820 sve_size_bh iclass decode.
1821
0a57e14f
MM		 18222019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1823
1824 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1825 sve_size_sd2 iclass encode.
1826 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1827 sve_size_sd2 iclass decode.
1828 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1829 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1830
c469c864
MM		 18312019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1832
1833 * aarch64-asm-2.c: Regenerated.
1834 * aarch64-dis-2.c: Regenerated.
1835 * aarch64-opc-2.c: Regenerated.
1836 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1837 for SVE_ADDR_ZX.
1838 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1839 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1840
116adc27
MM		 18412019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1842
1843 * aarch64-asm-2.c: Regenerated.
1844 * aarch64-dis-2.c: Regenerated.
1845 * aarch64-opc-2.c: Regenerated.
1846 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1847 for SVE_Zm3_11_INDEX.
1848 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1849 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1850 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1851 fields.
1852 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1853
3bd82c86
MM		 18542019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1855
1856 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1857 sve_size_hsd2 iclass encode.
1858 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1859 sve_size_hsd2 iclass decode.
1860 * aarch64-opc.c (fields): Handle SVE_size field.
1861 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1862
adccc507
MM		 18632019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1864
1865 * aarch64-asm-2.c: Regenerated.
1866 * aarch64-dis-2.c: Regenerated.
1867 * aarch64-opc-2.c: Regenerated.
1868 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1869 for SVE_IMM_ROT3.
1870 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1871 (fields): Handle SVE_rot3 field.
1872 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1873 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1874
5cd99750
MM		 18752019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1876
1877 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1878 instructions.
1879
7ce2460a
MM		 18802019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1881
1882 * aarch64-tbl.h
1883 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1884 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1885 aarch64_feature_sve2bitperm): New feature sets.
1886 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1887 for feature set addresses.
1888 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1889 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1890
41cee089
FS		 18912019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1892 Faraz Shahbazker <fshahbazker@wavecomp.com>
1893
1894 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1895 argument and set ASE_EVA_R6 appropriately.
1896 (set_default_mips_dis_options): Pass ISA to above.
1897 (parse_mips_dis_option): Likewise.
1898 * mips-opc.c (EVAR6): New macro.
1899 (mips_builtin_opcodes): Add llwpe, scwpe.
1900
b83b4b13
SD		 19012019-05-01 Sudakshina Das <sudi.das@arm.com>
1902
1903 * aarch64-asm-2.c: Regenerated.
1904 * aarch64-dis-2.c: Regenerated.
1905 * aarch64-opc-2.c: Regenerated.
1906 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1907 AARCH64_OPND_TME_UIMM16.
1908 (aarch64_print_operand): Likewise.
1909 * aarch64-tbl.h (QL_IMM_NIL): New.
1910 (TME): New.
1911 (_TME_INSN): New.
1912 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1913
4a90ce95
JD		 19142019-04-29 John Darrington <john@darrington.wattle.id.au>
1915
1916 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1917
a45328b9
AB		 19182019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1919 Faraz Shahbazker <fshahbazker@wavecomp.com>
1920
1921 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1922
d10be0cb
JD		 19232019-04-24 John Darrington <john@darrington.wattle.id.au>
1924
1925 * s12z-opc.h: Add extern "C" bracketing to help
1926 users who wish to use this interface in c++ code.
1927
a679f24e
JD		 19282019-04-24 John Darrington <john@darrington.wattle.id.au>
1929
1930 * s12z-opc.c (bm_decode): Handle bit map operations with the
1931 "reserved0" mode.
1932
32c36c3c
AV		 19332019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1934
1935 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1936 specifier. Add entries for VLDR and VSTR of system registers.
1937 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1938 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1939 of %J and %K format specifier.
1940
efd6b359
AV		 19412019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1942
1943 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1944 Add new entries for VSCCLRM instruction.
1945 (print_insn_coprocessor): Handle new %C format control code.
1946
6b0dd094
AV		 19472019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1948
1949 * arm-dis.c (enum isa): New enum.
1950 (struct sopcode32): New structure.
1951 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1952 set isa field of all current entries to ANY.
1953 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1954 Only match an entry if its isa field allows the current mode.
1955
4b5a202f
AV		 19562019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1957
1958 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1959 CLRM.
1960 (print_insn_thumb32): Add logic to print %n CLRM register list.
1961
60f993ce
AV		 19622019-04-15 Sudakshina Das <sudi.das@arm.com>
1963
1964 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1965 and %Q patterns.
1966
f6b2b12d
AV		 19672019-04-15 Sudakshina Das <sudi.das@arm.com>
1968
1969 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1970 (print_insn_thumb32): Edit the switch case for %Z.
1971
1889da70
AV		 19722019-04-15 Sudakshina Das <sudi.das@arm.com>
1973
1974 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1975
65d1bc05
AV		 19762019-04-15 Sudakshina Das <sudi.das@arm.com>
1977
1978 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1979
1caf72a5
AV		 19802019-04-15 Sudakshina Das <sudi.das@arm.com>
1981
1982 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1983
f1c7f421
AV		 19842019-04-15 Sudakshina Das <sudi.das@arm.com>
1985
1986 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1987 Arm register with r13 and r15 unpredictable.
1988 (thumb32_opcodes): New instructions for bfx and bflx.
1989
4389b29a
AV		 19902019-04-15 Sudakshina Das <sudi.das@arm.com>
1991
1992 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1993
e5d6e09e
AV		 19942019-04-15 Sudakshina Das <sudi.das@arm.com>
1995
1996 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1997
e12437dc
AV		 19982019-04-15 Sudakshina Das <sudi.das@arm.com>
1999
2000 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2001
031254f2
AV		 20022019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2003
2004 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2005
e5a557ac
JD		 20062019-04-12 John Darrington <john@darrington.wattle.id.au>
2007
2008 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2009 "optr". ("operator" is a reserved word in c++).
2010
bd7ceb8d
SD		 20112019-04-11 Sudakshina Das <sudi.das@arm.com>
2012
2013 * aarch64-opc.c (aarch64_print_operand): Add case for
2014 AARCH64_OPND_Rt_SP.
2015 (verify_constraints): Likewise.
2016 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2017 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2018 to accept Rt|SP as first operand.
2019 (AARCH64_OPERANDS): Add new Rt_SP.
2020 * aarch64-asm-2.c: Regenerated.
2021 * aarch64-dis-2.c: Regenerated.
2022 * aarch64-opc-2.c: Regenerated.
2023
e54010f1
SD		 20242019-04-11 Sudakshina Das <sudi.das@arm.com>
2025
2026 * aarch64-asm-2.c: Regenerated.
2027 * aarch64-dis-2.c: Likewise.
2028 * aarch64-opc-2.c: Likewise.
2029 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2030
7e96e219
RS		 20312019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2032
2033 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2034
6f2791d5
L		 20352019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2036
2037 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2038 * i386-init.h: Regenerated.
2039
e392bad3
AM		 20402019-04-07 Alan Modra <amodra@gmail.com>
2041
2042 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2043 op_separator to control printing of spaces, comma and parens
2044 rather than need_comma, need_paren and spaces vars.
2045
dffaa15c
AM		 20462019-04-07 Alan Modra <amodra@gmail.com>
2047
2048 PR 24421
2049 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2050 (print_insn_neon, print_insn_arm): Likewise.
2051
d6aab7a1
XG		 20522019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2053
2054 * i386-dis-evex.h (evex_table): Updated to support BF16
2055 instructions.
2056 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2057 and EVEX_W_0F3872_P_3.
2058 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2059 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2060 * i386-opc.h (enum): Add CpuAVX512_BF16.
2061 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2062 * i386-opc.tbl: Add AVX512 BF16 instructions.
2063 * i386-init.h: Regenerated.
2064 * i386-tbl.h: Likewise.
2065
66e85460
AM		 20662019-04-05 Alan Modra <amodra@gmail.com>
2067
2068 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2069 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2070 to favour printing of "-" branch hint when using the "y" bit.
2071 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2072
c2b1c275
AM		 20732019-04-05 Alan Modra <amodra@gmail.com>
2074
2075 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2076 opcode until first operand is output.
2077
aae9718e
PB		 20782019-04-04 Peter Bergner <bergner@linux.ibm.com>
2079
2080 PR gas/24349
2081 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2082 (valid_bo_post_v2): Add support for 'at' branch hints.
2083 (insert_bo): Only error on branch on ctr.
2084 (get_bo_hint_mask): New function.
2085 (insert_boe): Add new 'branch_taken' formal argument. Add support
2086 for inserting 'at' branch hints.
2087 (extract_boe): Add new 'branch_taken' formal argument. Add support
2088 for extracting 'at' branch hints.
2089 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2090 (BOE): Delete operand.
2091 (BOM, BOP): New operands.
2092 (RM): Update value.
2093 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2094 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2095 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2096 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2097 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2098 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2099 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2100 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2101 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2102 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2103 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2104 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2105 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2106 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2107 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2108 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2109 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2110 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2111 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2112 bttarl+>: New extended mnemonics.
2113
96a86c01
AM		 21142019-03-28 Alan Modra <amodra@gmail.com>
2115
2116 PR 24390
2117 * ppc-opc.c (BTF): Define.
2118 (powerpc_opcodes): Use for mtfsb*.
2119 * ppc-dis.c (print_insn_powerpc): Print fields with both
2120 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2121
796d6298
TC		 21222019-03-25 Tamar Christina <tamar.christina@arm.com>
2123
2124 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2125 (mapping_symbol_for_insn): Implement new algorithm.
2126 (print_insn): Remove duplicate code.
2127
60df3720
TC		 21282019-03-25 Tamar Christina <tamar.christina@arm.com>
2129
2130 * aarch64-dis.c (print_insn_aarch64):
2131 Implement override.
2132
51457761
TC		 21332019-03-25 Tamar Christina <tamar.christina@arm.com>
2134
2135 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2136 order.
2137
53b2f36b
TC		 21382019-03-25 Tamar Christina <tamar.christina@arm.com>
2139
2140 * aarch64-dis.c (last_stop_offset): New.
2141 (print_insn_aarch64): Use stop_offset.
2142
89199bb5
L		 21432019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2144
2145 PR gas/24359
2146 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2147 CPU_ANY_AVX2_FLAGS.
2148 * i386-init.h: Regenerated.
2149
97ed31ae
L		 21502019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2151
2152 PR gas/24348
2153 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2154 vmovdqu16, vmovdqu32 and vmovdqu64.
2155 * i386-tbl.h: Regenerated.
2156
0919bfe9
AK		 21572019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2158
2159 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2160 from vstrszb, vstrszh, and vstrszf.
2161
21622019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2163
2164 * s390-opc.txt: Add instruction descriptions.
2165
21820ebe
JW		 21662019-02-08 Jim Wilson <jimw@sifive.com>
2167
2168 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2169 <bne>: Likewise.
2170
f7dd2fb2
TC		 21712019-02-07 Tamar Christina <tamar.christina@arm.com>
2172
2173 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2174
6456d318
TC		 21752019-02-07 Tamar Christina <tamar.christina@arm.com>
2176
2177 PR binutils/23212
2178 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2179 * aarch64-opc.c (verify_elem_sd): New.
2180 (fields): Add FLD_sz entr.
2181 * aarch64-tbl.h (_SIMD_INSN): New.
2182 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2183 fmulx scalar and vector by element isns.
2184
4a83b610
NC		 21852019-02-07 Nick Clifton <nickc@redhat.com>
2186
2187 * po/sv.po: Updated Swedish translation.
2188
fc60b8c8
AK		 21892019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2190
2191 * s390-mkopc.c (main): Accept arch13 as cpu string.
2192 * s390-opc.c: Add new instruction formats and instruction opcode
2193 masks.
2194 * s390-opc.txt: Add new arch13 instructions.
2195
e10620d3
TC		 21962019-01-25 Sudakshina Das <sudi.das@arm.com>
2197
2198 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2199 (aarch64_opcode): Change encoding for stg, stzg
2200 st2g and st2zg.
2201 * aarch64-asm-2.c: Regenerated.
2202 * aarch64-dis-2.c: Regenerated.
2203 * aarch64-opc-2.c: Regenerated.
2204
20a4ca55
SD		 22052019-01-25 Sudakshina Das <sudi.das@arm.com>
2206
2207 * aarch64-asm-2.c: Regenerated.
2208 * aarch64-dis-2.c: Likewise.
2209 * aarch64-opc-2.c: Likewise.
2210 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2211
550fd7bf
SD		 22122019-01-25 Sudakshina Das <sudi.das@arm.com>
2213 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2214
2215 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2216 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2217 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2218 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2219 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2220 case for ldstgv_indexed.
2221 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2222 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2223 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2224 * aarch64-asm-2.c: Regenerated.
2225 * aarch64-dis-2.c: Regenerated.
2226 * aarch64-opc-2.c: Regenerated.
2227
d9938630
NC		 22282019-01-23 Nick Clifton <nickc@redhat.com>
2229
2230 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2231
375cd423
NC		 22322019-01-21 Nick Clifton <nickc@redhat.com>
2233
2234 * po/de.po: Updated German translation.
2235 * po/uk.po: Updated Ukranian translation.
2236
57299f48
CX		 22372019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2238 * mips-dis.c (mips_arch_choices): Fix typo in
2239 gs464, gs464e and gs264e descriptors.
2240
f48dfe41
NC		 22412019-01-19 Nick Clifton <nickc@redhat.com>
2242
2243 * configure: Regenerate.
2244 * po/opcodes.pot: Regenerate.
2245
f974f26c
NC		 22462018-06-24 Nick Clifton <nickc@redhat.com>
2247
2248 2.32 branch created.
2249
39f286cd
JD		 22502019-01-09 John Darrington <john@darrington.wattle.id.au>
2251
448b8ca8
JD		 2252 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2253 if it is null.
2254 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2255 zero.
2256
3107326d
AP		 22572019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2258
2259 * configure: Regenerate.
2260
7e9ca91e
AM		 22612019-01-07 Alan Modra <amodra@gmail.com>
2262
2263 * configure: Regenerate.
2264 * po/POTFILES.in: Regenerate.
2265
ef1ad42b
JD		 22662019-01-03 John Darrington <john@darrington.wattle.id.au>
2267
2268 * s12z-opc.c: New file.
2269 * s12z-opc.h: New file.
2270 * s12z-dis.c: Removed all code not directly related to display
2271 of instructions. Used the interface provided by the new files
2272 instead.
2273 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2274 * Makefile.in: Regenerate.
ef1ad42b 2275 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2276 * configure: Regenerate.
ef1ad42b 2277
82704155
AM		 22782019-01-01 Alan Modra <amodra@gmail.com>
2279
2280 Update year range in copyright notice of all files.
2281
d5c04e1b 2282For older changes see ChangeLog-2018
3499769a 2283\f
d5c04e1b 2284Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2285
2286Copying and distribution of this file, with or without modification,
2287are permitted in any medium without royalty provided the copyright
2288notice and this notice are preserved.
2289
2290Local Variables:
2291mode: change-log
2292left-margin: 8
2293fill-column: 74
2294version-control: never
2295End:
GDB Binutils - Deliverables
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