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drm/i915: Add to_user_ptr()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 75 int, int, intel_clock_t *, intel_clock_t *);
d4906093 76};
79e53945 77
2377b741
JB		 78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
d2acd215
DV		 81int
82intel_pch_rawclk(struct drm_device *dev)
83{
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89}
90
d4906093
ML		 91static bool
92intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
d4906093
ML		 95static bool
96intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
79e53945 99
a4fc5ed6
KP		 100static bool
101intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
5eb08b69 104static bool
f2b115e6 105intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
a4fc5ed6 108
a0c4da24
JB		 109static bool
110intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
021357ac
CW		 114static inline u32 /* units of 100MHz */
115intel_fdi_link_freq(struct drm_device *dev)
116{
8b99e68c
CW		 117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
021357ac
CW		 122}
123
e4b36699 124static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
d4906093 135 .find_pll = intel_find_best_PLL,
e4b36699
KP		 136};
137
138static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
d4906093 149 .find_pll = intel_find_best_PLL,
e4b36699 150};
273e27ca 151
e4b36699 152static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 157 .m1 = { .min = 8, .max = 18 },
158 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
d4906093 163 .find_pll = intel_find_best_PLL,
e4b36699
KP		 164};
165
166static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 171 .m1 = { .min = 8, .max = 18 },
172 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
d4906093 177 .find_pll = intel_find_best_PLL,
e4b36699
KP		 178};
179
273e27ca 180
e4b36699 181static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
044c7c41 193 },
d4906093 194 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 195};
196
197static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
d4906093 208 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
044c7c41 222 },
d4906093 223 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 224};
225
226static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
044c7c41 237 },
d4906093 238 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 239};
240
241static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
273e27ca 251 .p2_slow = 10, .p2_fast = 10 },
0206e353 252 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 258 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
273e27ca 261 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
6115707b 268 .find_pll = intel_find_best_PLL,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
6115707b 282 .find_pll = intel_find_best_PLL,
e4b36699
KP		 283};
284
273e27ca
EA		 285/* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
4547668a 301 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 302};
303
b91ad0ec 304static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 315 .find_pll = intel_g4x_find_best_PLL,
316};
317
318static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 329 .find_pll = intel_g4x_find_best_PLL,
330};
331
273e27ca 332/* LVDS 100mhz refclk limits. */
b91ad0ec 333static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
0206e353 341 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 344 .find_pll = intel_g4x_find_best_PLL,
345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
0206e353 355 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 358 .find_pll = intel_g4x_find_best_PLL,
359};
360
361static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
273e27ca 371 .p2_slow = 10, .p2_fast = 10 },
0206e353 372 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 373};
374
a0c4da24
JB		 375static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387};
388
389static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
17dc9257 391 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401};
402
403static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 406 .n = { .min = 1, .max = 7 },
74a4dd2e 407 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415};
416
57f350b6
JB		 417u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418{
09153000 419 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 420
57f350b6
JB		 421 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
422 DRM_ERROR("DPIO idle wait timed out\n");
09153000 423 return 0;
57f350b6
JB		 424 }
425
426 I915_WRITE(DPIO_REG, reg);
427 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
428 DPIO_BYTE);
429 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
430 DRM_ERROR("DPIO read wait timed out\n");
09153000 431 return 0;
57f350b6 432 }
57f350b6 433
09153000 434 return I915_READ(DPIO_DATA);
57f350b6
JB		 435}
436
a0c4da24
JB		 437static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
438 u32 val)
439{
09153000 440 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 441
a0c4da24
JB		 442 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
443 DRM_ERROR("DPIO idle wait timed out\n");
09153000 444 return;
a0c4da24
JB		 445 }
446
447 I915_WRITE(DPIO_DATA, val);
448 I915_WRITE(DPIO_REG, reg);
449 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
450 DPIO_BYTE);
451 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
452 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 453}
454
57f350b6
JB		 455static void vlv_init_dpio(struct drm_device *dev)
456{
457 struct drm_i915_private *dev_priv = dev->dev_private;
458
459 /* Reset the DPIO config */
460 I915_WRITE(DPIO_CTL, 0);
461 POSTING_READ(DPIO_CTL);
462 I915_WRITE(DPIO_CTL, 1);
463 POSTING_READ(DPIO_CTL);
464}
465
1b894b59
CW		 466static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
467 int refclk)
2c07245f 468{
b91ad0ec 469 struct drm_device *dev = crtc->dev;
2c07245f 470 const intel_limit_t *limit;
b91ad0ec
ZW		 471
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 473 if (intel_is_dual_link_lvds(dev)) {
b91ad0ec 474 /* LVDS dual channel */
1b894b59 475 if (refclk == 100000)
b91ad0ec
ZW		 476 limit = &intel_limits_ironlake_dual_lvds_100m;
477 else
478 limit = &intel_limits_ironlake_dual_lvds;
479 } else {
1b894b59 480 if (refclk == 100000)
b91ad0ec
ZW		 481 limit = &intel_limits_ironlake_single_lvds_100m;
482 else
483 limit = &intel_limits_ironlake_single_lvds;
484 }
485 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 486 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 487 limit = &intel_limits_ironlake_display_port;
2c07245f 488 else
b91ad0ec 489 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 490
491 return limit;
492}
493
044c7c41
ML		 494static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
495{
496 struct drm_device *dev = crtc->dev;
044c7c41
ML		 497 const intel_limit_t *limit;
498
499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 500 if (intel_is_dual_link_lvds(dev))
044c7c41 501 /* LVDS with dual channel */
e4b36699 502 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 503 else
504 /* LVDS with dual channel */
e4b36699 505 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 506 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
507 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 508 limit = &intel_limits_g4x_hdmi;
044c7c41 509 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 510 limit = &intel_limits_g4x_sdvo;
0206e353 511 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 512 limit = &intel_limits_g4x_display_port;
044c7c41 513 } else /* The option is for other outputs */
e4b36699 514 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 515
516 return limit;
517}
518
1b894b59 519static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 520{
521 struct drm_device *dev = crtc->dev;
522 const intel_limit_t *limit;
523
bad720ff 524 if (HAS_PCH_SPLIT(dev))
1b894b59 525 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 526 else if (IS_G4X(dev)) {
044c7c41 527 limit = intel_g4x_limit(crtc);
f2b115e6 528 } else if (IS_PINEVIEW(dev)) {
2177832f 529 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 530 limit = &intel_limits_pineview_lvds;
2177832f 531 else
f2b115e6 532 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 533 } else if (IS_VALLEYVIEW(dev)) {
534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
535 limit = &intel_limits_vlv_dac;
536 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
537 limit = &intel_limits_vlv_hdmi;
538 else
539 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 540 } else if (!IS_GEN2(dev)) {
541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
542 limit = &intel_limits_i9xx_lvds;
543 else
544 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 545 } else {
546 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 547 limit = &intel_limits_i8xx_lvds;
79e53945 548 else
e4b36699 549 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 550 }
551 return limit;
552}
553
f2b115e6
AJ		 554/* m1 is reserved as 0 in Pineview, n is a ring counter */
555static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 556{
2177832f
SL		 557 clock->m = clock->m2 + 2;
558 clock->p = clock->p1 * clock->p2;
559 clock->vco = refclk * clock->m / clock->n;
560 clock->dot = clock->vco / clock->p;
561}
562
563static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
564{
f2b115e6
AJ		 565 if (IS_PINEVIEW(dev)) {
566 pineview_clock(refclk, clock);
2177832f
SL		 567 return;
568 }
79e53945
JB		 569 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
570 clock->p = clock->p1 * clock->p2;
571 clock->vco = refclk * clock->m / (clock->n + 2);
572 clock->dot = clock->vco / clock->p;
573}
574
79e53945
JB		 575/**
576 * Returns whether any output on the specified pipe is of the specified type
577 */
4ef69c7a 578bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 579{
4ef69c7a 580 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 581 struct intel_encoder *encoder;
582
6c2b7c12
DV		 583 for_each_encoder_on_crtc(dev, crtc, encoder)
584 if (encoder->type == type)
4ef69c7a
CW		 585 return true;
586
587 return false;
79e53945
JB		 588}
589
7c04d1d9 590#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 591/**
592 * Returns whether the given set of divisors are valid for a given refclk with
593 * the given connectors.
594 */
595
1b894b59
CW		 596static bool intel_PLL_is_valid(struct drm_device *dev,
597 const intel_limit_t *limit,
598 const intel_clock_t *clock)
79e53945 599{
79e53945 600 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 601 INTELPllInvalid("p1 out of range\n");
79e53945 602 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 603 INTELPllInvalid("p out of range\n");
79e53945 604 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 605 INTELPllInvalid("m2 out of range\n");
79e53945 606 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 607 INTELPllInvalid("m1 out of range\n");
f2b115e6 608 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 609 INTELPllInvalid("m1 <= m2\n");
79e53945 610 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 611 INTELPllInvalid("m out of range\n");
79e53945 612 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 613 INTELPllInvalid("n out of range\n");
79e53945 614 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 615 INTELPllInvalid("vco out of range\n");
79e53945
JB		 616 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
617 * connector, etc., rather than just a single range.
618 */
619 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 620 INTELPllInvalid("dot out of range\n");
79e53945
JB		 621
622 return true;
623}
624
d4906093
ML		 625static bool
626intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 627 int target, int refclk, intel_clock_t *match_clock,
628 intel_clock_t *best_clock)
d4906093 629
79e53945
JB		 630{
631 struct drm_device *dev = crtc->dev;
79e53945 632 intel_clock_t clock;
79e53945
JB		 633 int err = target;
634
a210b028 635 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 636 /*
a210b028
DV		 637 * For LVDS just rely on its current settings for dual-channel.
638 * We haven't figured out how to reliably set up different
639 * single/dual channel state, if we even can.
79e53945 640 */
1974cad0 641 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 642 clock.p2 = limit->p2.p2_fast;
643 else
644 clock.p2 = limit->p2.p2_slow;
645 } else {
646 if (target < limit->p2.dot_limit)
647 clock.p2 = limit->p2.p2_slow;
648 else
649 clock.p2 = limit->p2.p2_fast;
650 }
651
0206e353 652 memset(best_clock, 0, sizeof(*best_clock));
79e53945 653
42158660
ZY		 654 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 clock.m1++) {
656 for (clock.m2 = limit->m2.min;
657 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 658 /* m1 is always 0 in Pineview */
659 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 660 break;
661 for (clock.n = limit->n.min;
662 clock.n <= limit->n.max; clock.n++) {
663 for (clock.p1 = limit->p1.min;
664 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 665 int this_err;
666
2177832f 667 intel_clock(dev, refclk, &clock);
1b894b59
CW		 668 if (!intel_PLL_is_valid(dev, limit,
669 &clock))
79e53945 670 continue;
cec2f356
SP		 671 if (match_clock &&
672 clock.p != match_clock->p)
673 continue;
79e53945
JB		 674
675 this_err = abs(clock.dot - target);
676 if (this_err < err) {
677 *best_clock = clock;
678 err = this_err;
679 }
680 }
681 }
682 }
683 }
684
685 return (err != target);
686}
687
d4906093
ML		 688static bool
689intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 690 int target, int refclk, intel_clock_t *match_clock,
691 intel_clock_t *best_clock)
d4906093
ML		 692{
693 struct drm_device *dev = crtc->dev;
d4906093
ML		 694 intel_clock_t clock;
695 int max_n;
696 bool found;
6ba770dc
AJ		 697 /* approximately equals target * 0.00585 */
698 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 699 found = false;
700
701 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 702 int lvds_reg;
703
c619eed4 704 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 705 lvds_reg = PCH_LVDS;
706 else
707 lvds_reg = LVDS;
1974cad0 708 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
f77f13e2 721 /* based on hardware requirement, prefer smaller n to precision */
d4906093 722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 723 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
2177832f 732 intel_clock(dev, refclk, &clock);
1b894b59
CW		 733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
d4906093 735 continue;
cec2f356
SP		 736 if (match_clock &&
737 clock.p != match_clock->p)
738 continue;
1b894b59
CW		 739
740 this_err = abs(clock.dot - target);
d4906093
ML		 741 if (this_err < err_most) {
742 *best_clock = clock;
743 err_most = this_err;
744 max_n = clock.n;
745 found = true;
746 }
747 }
748 }
749 }
750 }
2c07245f
ZW		 751 return found;
752}
753
5eb08b69 754static bool
f2b115e6 755intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 756 int target, int refclk, intel_clock_t *match_clock,
757 intel_clock_t *best_clock)
5eb08b69
ZW		 758{
759 struct drm_device *dev = crtc->dev;
760 intel_clock_t clock;
4547668a 761
5eb08b69
ZW		 762 if (target < 200000) {
763 clock.n = 1;
764 clock.p1 = 2;
765 clock.p2 = 10;
766 clock.m1 = 12;
767 clock.m2 = 9;
768 } else {
769 clock.n = 2;
770 clock.p1 = 1;
771 clock.p2 = 10;
772 clock.m1 = 14;
773 clock.m2 = 8;
774 }
775 intel_clock(dev, refclk, &clock);
776 memcpy(best_clock, &clock, sizeof(intel_clock_t));
777 return true;
778}
779
a4fc5ed6
KP		 780/* DisplayPort has only two frequencies, 162MHz and 270MHz */
781static bool
782intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 783 int target, int refclk, intel_clock_t *match_clock,
784 intel_clock_t *best_clock)
a4fc5ed6 785{
5eddb70b
CW		 786 intel_clock_t clock;
787 if (target < 200000) {
788 clock.p1 = 2;
789 clock.p2 = 10;
790 clock.n = 2;
791 clock.m1 = 23;
792 clock.m2 = 8;
793 } else {
794 clock.p1 = 1;
795 clock.p2 = 10;
796 clock.n = 1;
797 clock.m1 = 14;
798 clock.m2 = 2;
799 }
800 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
801 clock.p = (clock.p1 * clock.p2);
802 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
803 clock.vco = 0;
804 memcpy(best_clock, &clock, sizeof(intel_clock_t));
805 return true;
a4fc5ed6 806}
a0c4da24
JB		 807static bool
808intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
809 int target, int refclk, intel_clock_t *match_clock,
810 intel_clock_t *best_clock)
811{
812 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
813 u32 m, n, fastclk;
814 u32 updrate, minupdate, fracbits, p;
815 unsigned long bestppm, ppm, absppm;
816 int dotclk, flag;
817
af447bd3 818 flag = 0;
a0c4da24
JB		 819 dotclk = target * 1000;
820 bestppm = 1000000;
821 ppm = absppm = 0;
822 fastclk = dotclk / (2*100);
823 updrate = 0;
824 minupdate = 19200;
825 fracbits = 1;
826 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
827 bestm1 = bestm2 = bestp1 = bestp2 = 0;
828
829 /* based on hardware requirement, prefer smaller n to precision */
830 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
831 updrate = refclk / n;
832 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
833 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
834 if (p2 > 10)
835 p2 = p2 - 1;
836 p = p1 * p2;
837 /* based on hardware requirement, prefer bigger m1,m2 values */
838 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
839 m2 = (((2*(fastclk * p * n / m1 )) +
840 refclk) / (2*refclk));
841 m = m1 * m2;
842 vco = updrate * m;
843 if (vco >= limit->vco.min && vco < limit->vco.max) {
844 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
845 absppm = (ppm > 0) ? ppm : (-ppm);
846 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
847 bestppm = 0;
848 flag = 1;
849 }
850 if (absppm < bestppm - 10) {
851 bestppm = absppm;
852 flag = 1;
853 }
854 if (flag) {
855 bestn = n;
856 bestm1 = m1;
857 bestm2 = m2;
858 bestp1 = p1;
859 bestp2 = p2;
860 flag = 0;
861 }
862 }
863 }
864 }
865 }
866 }
867 best_clock->n = bestn;
868 best_clock->m1 = bestm1;
869 best_clock->m2 = bestm2;
870 best_clock->p1 = bestp1;
871 best_clock->p2 = bestp2;
872
873 return true;
874}
a4fc5ed6 875
a5c961d1
PZ		 876enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
877 enum pipe pipe)
878{
879 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
881
882 return intel_crtc->cpu_transcoder;
883}
884
a928d536
PZ		 885static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
886{
887 struct drm_i915_private *dev_priv = dev->dev_private;
888 u32 frame, frame_reg = PIPEFRAME(pipe);
889
890 frame = I915_READ(frame_reg);
891
892 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
893 DRM_DEBUG_KMS("vblank wait timed out\n");
894}
895
9d0498a2
JB		 896/**
897 * intel_wait_for_vblank - wait for vblank on a given pipe
898 * @dev: drm device
899 * @pipe: pipe to wait for
900 *
901 * Wait for vblank to occur on a given pipe. Needed for various bits of
902 * mode setting code.
903 */
904void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 905{
9d0498a2 906 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 907 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 908
a928d536
PZ		 909 if (INTEL_INFO(dev)->gen >= 5) {
910 ironlake_wait_for_vblank(dev, pipe);
911 return;
912 }
913
300387c0
CW		 914 /* Clear existing vblank status. Note this will clear any other
915 * sticky status fields as well.
916 *
917 * This races with i915_driver_irq_handler() with the result
918 * that either function could miss a vblank event. Here it is not
919 * fatal, as we will either wait upon the next vblank interrupt or
920 * timeout. Generally speaking intel_wait_for_vblank() is only
921 * called during modeset at which time the GPU should be idle and
922 * should *not* be performing page flips and thus not waiting on
923 * vblanks...
924 * Currently, the result of us stealing a vblank from the irq
925 * handler is that a single frame will be skipped during swapbuffers.
926 */
927 I915_WRITE(pipestat_reg,
928 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
929
9d0498a2 930 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 931 if (wait_for(I915_READ(pipestat_reg) &
932 PIPE_VBLANK_INTERRUPT_STATUS,
933 50))
9d0498a2
JB		 934 DRM_DEBUG_KMS("vblank wait timed out\n");
935}
936
ab7ad7f6
KP		 937/*
938 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 939 * @dev: drm device
940 * @pipe: pipe to wait for
941 *
942 * After disabling a pipe, we can't wait for vblank in the usual way,
943 * spinning on the vblank interrupt status bit, since we won't actually
944 * see an interrupt when the pipe is disabled.
945 *
ab7ad7f6
KP		 946 * On Gen4 and above:
947 * wait for the pipe register state bit to turn off
948 *
949 * Otherwise:
950 * wait for the display line value to settle (it usually
951 * ends up stopping at the start of the next frame).
58e10eb9 952 *
9d0498a2 953 */
58e10eb9 954void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 955{
956 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 957 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
958 pipe);
ab7ad7f6
KP		 959
960 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 961 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 962
963 /* Wait for the Pipe State to go off */
58e10eb9
CW		 964 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
965 100))
284637d9 966 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 967 } else {
837ba00f 968 u32 last_line, line_mask;
58e10eb9 969 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 970 unsigned long timeout = jiffies + msecs_to_jiffies(100);
971
837ba00f
PZ		 972 if (IS_GEN2(dev))
973 line_mask = DSL_LINEMASK_GEN2;
974 else
975 line_mask = DSL_LINEMASK_GEN3;
976
ab7ad7f6
KP		 977 /* Wait for the display line to settle */
978 do {
837ba00f 979 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 980 mdelay(5);
837ba00f 981 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 982 time_after(timeout, jiffies));
983 if (time_after(jiffies, timeout))
284637d9 984 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 985 }
79e53945
JB		 986}
987
b0ea7d37
DL		 988/*
989 * ibx_digital_port_connected - is the specified port connected?
990 * @dev_priv: i915 private structure
991 * @port: the port to test
992 *
993 * Returns true if @port is connected, false otherwise.
994 */
995bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
996 struct intel_digital_port *port)
997{
998 u32 bit;
999
c36346e3
DL		 1000 if (HAS_PCH_IBX(dev_priv->dev)) {
1001 switch(port->port) {
1002 case PORT_B:
1003 bit = SDE_PORTB_HOTPLUG;
1004 break;
1005 case PORT_C:
1006 bit = SDE_PORTC_HOTPLUG;
1007 break;
1008 case PORT_D:
1009 bit = SDE_PORTD_HOTPLUG;
1010 break;
1011 default:
1012 return true;
1013 }
1014 } else {
1015 switch(port->port) {
1016 case PORT_B:
1017 bit = SDE_PORTB_HOTPLUG_CPT;
1018 break;
1019 case PORT_C:
1020 bit = SDE_PORTC_HOTPLUG_CPT;
1021 break;
1022 case PORT_D:
1023 bit = SDE_PORTD_HOTPLUG_CPT;
1024 break;
1025 default:
1026 return true;
1027 }
b0ea7d37
DL		 1028 }
1029
1030 return I915_READ(SDEISR) & bit;
1031}
1032
b24e7179
JB		 1033static const char *state_string(bool enabled)
1034{
1035 return enabled ? "on" : "off";
1036}
1037
1038/* Only for pre-ILK configs */
1039static void assert_pll(struct drm_i915_private *dev_priv,
1040 enum pipe pipe, bool state)
1041{
1042 int reg;
1043 u32 val;
1044 bool cur_state;
1045
1046 reg = DPLL(pipe);
1047 val = I915_READ(reg);
1048 cur_state = !!(val & DPLL_VCO_ENABLE);
1049 WARN(cur_state != state,
1050 "PLL state assertion failure (expected %s, current %s)\n",
1051 state_string(state), state_string(cur_state));
1052}
1053#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1054#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055
040484af
JB		 1056/* For ILK+ */
1057static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1058 struct intel_pch_pll *pll,
1059 struct intel_crtc *crtc,
1060 bool state)
040484af 1061{
040484af
JB		 1062 u32 val;
1063 bool cur_state;
1064
9d82aa17
ED		 1065 if (HAS_PCH_LPT(dev_priv->dev)) {
1066 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1067 return;
1068 }
1069
92b27b08
CW		 1070 if (WARN (!pll,
1071 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1072 return;
ee7b9f93 1073
92b27b08
CW		 1074 val = I915_READ(pll->pll_reg);
1075 cur_state = !!(val & DPLL_VCO_ENABLE);
1076 WARN(cur_state != state,
1077 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1078 pll->pll_reg, state_string(state), state_string(cur_state), val);
1079
1080 /* Make sure the selected PLL is correctly attached to the transcoder */
1081 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1082 u32 pch_dpll;
1083
1084 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1085 cur_state = pll->pll_reg == _PCH_DPLL_B;
1086 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1087 "PLL[%d] not attached to this transcoder %d: %08x\n",
1088 cur_state, crtc->pipe, pch_dpll)) {
1089 cur_state = !!(val >> (4*crtc->pipe + 3));
1090 WARN(cur_state != state,
1091 "PLL[%d] not %s on this transcoder %d: %08x\n",
1092 pll->pll_reg == _PCH_DPLL_B,
1093 state_string(state),
1094 crtc->pipe,
1095 val);
1096 }
d3ccbe86 1097 }
040484af 1098}
92b27b08
CW		 1099#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1100#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1101
1102static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103 enum pipe pipe, bool state)
1104{
1105 int reg;
1106 u32 val;
1107 bool cur_state;
ad80a810
PZ		 1108 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1109 pipe);
040484af 1110
affa9354
PZ		 1111 if (HAS_DDI(dev_priv->dev)) {
1112 /* DDI does not have a specific FDI_TX register */
ad80a810 1113 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1114 val = I915_READ(reg);
ad80a810 1115 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1116 } else {
1117 reg = FDI_TX_CTL(pipe);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & FDI_TX_ENABLE);
1120 }
040484af
JB		 1121 WARN(cur_state != state,
1122 "FDI TX state assertion failure (expected %s, current %s)\n",
1123 state_string(state), state_string(cur_state));
1124}
1125#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1126#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1127
1128static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1129 enum pipe pipe, bool state)
1130{
1131 int reg;
1132 u32 val;
1133 bool cur_state;
1134
d63fa0dc
PZ		 1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1138 WARN(cur_state != state,
1139 "FDI RX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141}
1142#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1143#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1144
1145static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
1148 int reg;
1149 u32 val;
1150
1151 /* ILK FDI PLL is always enabled */
1152 if (dev_priv->info->gen == 5)
1153 return;
1154
bf507ef7 1155 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1156 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1157 return;
1158
040484af
JB		 1159 reg = FDI_TX_CTL(pipe);
1160 val = I915_READ(reg);
1161 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1162}
1163
1164static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1165 enum pipe pipe)
1166{
1167 int reg;
1168 u32 val;
1169
1170 reg = FDI_RX_CTL(pipe);
1171 val = I915_READ(reg);
1172 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1173}
1174
ea0760cf
JB		 1175static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1176 enum pipe pipe)
1177{
1178 int pp_reg, lvds_reg;
1179 u32 val;
1180 enum pipe panel_pipe = PIPE_A;
0de3b485 1181 bool locked = true;
ea0760cf
JB		 1182
1183 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1184 pp_reg = PCH_PP_CONTROL;
1185 lvds_reg = PCH_LVDS;
1186 } else {
1187 pp_reg = PP_CONTROL;
1188 lvds_reg = LVDS;
1189 }
1190
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1194 locked = false;
1195
1196 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1197 panel_pipe = PIPE_B;
1198
1199 WARN(panel_pipe == pipe && locked,
1200 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1201 pipe_name(pipe));
ea0760cf
JB		 1202}
1203
b840d907
JB		 1204void assert_pipe(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, bool state)
b24e7179
JB		 1206{
1207 int reg;
1208 u32 val;
63d7bbe9 1209 bool cur_state;
702e7a56
PZ		 1210 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1211 pipe);
b24e7179 1212
8e636784
DV		 1213 /* if we need the pipe A quirk it must be always on */
1214 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1215 state = true;
1216
69310161
PZ		 1217 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1218 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1219 cur_state = false;
1220 } else {
1221 reg = PIPECONF(cpu_transcoder);
1222 val = I915_READ(reg);
1223 cur_state = !!(val & PIPECONF_ENABLE);
1224 }
1225
63d7bbe9
JB		 1226 WARN(cur_state != state,
1227 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1228 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1229}
1230
931872fc
CW		 1231static void assert_plane(struct drm_i915_private *dev_priv,
1232 enum plane plane, bool state)
b24e7179
JB		 1233{
1234 int reg;
1235 u32 val;
931872fc 1236 bool cur_state;
b24e7179
JB		 1237
1238 reg = DSPCNTR(plane);
1239 val = I915_READ(reg);
931872fc
CW		 1240 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1241 WARN(cur_state != state,
1242 "plane %c assertion failure (expected %s, current %s)\n",
1243 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1244}
1245
931872fc
CW		 1246#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1247#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1248
b24e7179
JB		 1249static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1250 enum pipe pipe)
1251{
1252 int reg, i;
1253 u32 val;
1254 int cur_pipe;
1255
19ec1358 1256 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1257 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1258 reg = DSPCNTR(pipe);
1259 val = I915_READ(reg);
1260 WARN((val & DISPLAY_PLANE_ENABLE),
1261 "plane %c assertion failure, should be disabled but not\n",
1262 plane_name(pipe));
19ec1358 1263 return;
28c05794 1264 }
19ec1358 1265
b24e7179
JB		 1266 /* Need to check both planes against the pipe */
1267 for (i = 0; i < 2; i++) {
1268 reg = DSPCNTR(i);
1269 val = I915_READ(reg);
1270 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271 DISPPLANE_SEL_PIPE_SHIFT;
1272 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1273 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1275 }
1276}
1277
92f2584a
JB		 1278static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1279{
1280 u32 val;
1281 bool enabled;
1282
9d82aa17
ED		 1283 if (HAS_PCH_LPT(dev_priv->dev)) {
1284 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1285 return;
1286 }
1287
92f2584a
JB		 1288 val = I915_READ(PCH_DREF_CONTROL);
1289 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1290 DREF_SUPERSPREAD_SOURCE_MASK));
1291 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1292}
1293
1294static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296{
1297 int reg;
1298 u32 val;
1299 bool enabled;
1300
1301 reg = TRANSCONF(pipe);
1302 val = I915_READ(reg);
1303 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1304 WARN(enabled,
1305 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1306 pipe_name(pipe));
92f2584a
JB		 1307}
1308
4e634389
KP		 1309static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1310 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1311{
1312 if ((val & DP_PORT_EN) == 0)
1313 return false;
1314
1315 if (HAS_PCH_CPT(dev_priv->dev)) {
1316 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1317 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1318 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1319 return false;
1320 } else {
1321 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322 return false;
1323 }
1324 return true;
1325}
1326
1519b995
KP		 1327static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, u32 val)
1329{
1330 if ((val & PORT_ENABLE) == 0)
1331 return false;
1332
1333 if (HAS_PCH_CPT(dev_priv->dev)) {
1334 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1335 return false;
1336 } else {
1337 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1338 return false;
1339 }
1340 return true;
1341}
1342
1343static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1344 enum pipe pipe, u32 val)
1345{
1346 if ((val & LVDS_PORT_EN) == 0)
1347 return false;
1348
1349 if (HAS_PCH_CPT(dev_priv->dev)) {
1350 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1351 return false;
1352 } else {
1353 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1354 return false;
1355 }
1356 return true;
1357}
1358
1359static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1361{
1362 if ((val & ADPA_DAC_ENABLE) == 0)
1363 return false;
1364 if (HAS_PCH_CPT(dev_priv->dev)) {
1365 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1366 return false;
1367 } else {
1368 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1369 return false;
1370 }
1371 return true;
1372}
1373
291906f1 1374static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1375 enum pipe pipe, int reg, u32 port_sel)
291906f1 1376{
47a05eca 1377 u32 val = I915_READ(reg);
4e634389 1378 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1379 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1380 reg, pipe_name(pipe));
de9a35ab 1381
75c5da27
DV		 1382 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1383 && (val & DP_PIPEB_SELECT),
de9a35ab 1384 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1385}
1386
1387static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, int reg)
1389{
47a05eca 1390 u32 val = I915_READ(reg);
b70ad586 1391 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1392 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1393 reg, pipe_name(pipe));
de9a35ab 1394
75c5da27
DV		 1395 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1396 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1397 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1398}
1399
1400static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe)
1402{
1403 int reg;
1404 u32 val;
291906f1 1405
f0575e92
KP		 1406 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1407 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1408 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1409
1410 reg = PCH_ADPA;
1411 val = I915_READ(reg);
b70ad586 1412 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1413 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1414 pipe_name(pipe));
291906f1
JB		 1415
1416 reg = PCH_LVDS;
1417 val = I915_READ(reg);
b70ad586 1418 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1419 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1420 pipe_name(pipe));
291906f1
JB		 1421
1422 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1423 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1424 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1425}
1426
63d7bbe9
JB		 1427/**
1428 * intel_enable_pll - enable a PLL
1429 * @dev_priv: i915 private structure
1430 * @pipe: pipe PLL to enable
1431 *
1432 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1433 * make sure the PLL reg is writable first though, since the panel write
1434 * protect mechanism may be enabled.
1435 *
1436 * Note! This is for pre-ILK only.
7434a255
TR		 1437 *
1438 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1439 */
1440static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1441{
1442 int reg;
1443 u32 val;
1444
1445 /* No really, not for ILK+ */
a0c4da24 1446 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1447
1448 /* PLL is protected by panel, make sure we can write it */
1449 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1450 assert_panel_unlocked(dev_priv, pipe);
1451
1452 reg = DPLL(pipe);
1453 val = I915_READ(reg);
1454 val |= DPLL_VCO_ENABLE;
1455
1456 /* We do this three times for luck */
1457 I915_WRITE(reg, val);
1458 POSTING_READ(reg);
1459 udelay(150); /* wait for warmup */
1460 I915_WRITE(reg, val);
1461 POSTING_READ(reg);
1462 udelay(150); /* wait for warmup */
1463 I915_WRITE(reg, val);
1464 POSTING_READ(reg);
1465 udelay(150); /* wait for warmup */
1466}
1467
1468/**
1469 * intel_disable_pll - disable a PLL
1470 * @dev_priv: i915 private structure
1471 * @pipe: pipe PLL to disable
1472 *
1473 * Disable the PLL for @pipe, making sure the pipe is off first.
1474 *
1475 * Note! This is for pre-ILK only.
1476 */
1477static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1478{
1479 int reg;
1480 u32 val;
1481
1482 /* Don't disable pipe A or pipe A PLLs if needed */
1483 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1484 return;
1485
1486 /* Make sure the pipe isn't still relying on us */
1487 assert_pipe_disabled(dev_priv, pipe);
1488
1489 reg = DPLL(pipe);
1490 val = I915_READ(reg);
1491 val &= ~DPLL_VCO_ENABLE;
1492 I915_WRITE(reg, val);
1493 POSTING_READ(reg);
1494}
1495
a416edef
ED		 1496/* SBI access */
1497static void
988d6ee8
PZ		 1498intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1499 enum intel_sbi_destination destination)
a416edef 1500{
988d6ee8 1501 u32 tmp;
a416edef 1502
09153000 1503 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1504
39fb50f6 1505 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1506 100)) {
1507 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1508 return;
a416edef
ED		 1509 }
1510
988d6ee8
PZ		 1511 I915_WRITE(SBI_ADDR, (reg << 16));
1512 I915_WRITE(SBI_DATA, value);
1513
1514 if (destination == SBI_ICLK)
1515 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1516 else
1517 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1518 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1519
39fb50f6 1520 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1521 100)) {
1522 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1523 return;
a416edef 1524 }
a416edef
ED		 1525}
1526
1527static u32
988d6ee8
PZ		 1528intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1529 enum intel_sbi_destination destination)
a416edef 1530{
39fb50f6 1531 u32 value = 0;
09153000 1532 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1533
39fb50f6 1534 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1535 100)) {
1536 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1537 return 0;
a416edef
ED		 1538 }
1539
988d6ee8
PZ		 1540 I915_WRITE(SBI_ADDR, (reg << 16));
1541
1542 if (destination == SBI_ICLK)
1543 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1544 else
1545 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1546 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1547
39fb50f6 1548 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1549 100)) {
1550 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1551 return 0;
a416edef
ED		 1552 }
1553
09153000 1554 return I915_READ(SBI_DATA);
a416edef
ED		 1555}
1556
92f2584a 1557/**
b6b4e185 1558 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1559 * @dev_priv: i915 private structure
1560 * @pipe: pipe PLL to enable
1561 *
1562 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1563 * drives the transcoder clock.
1564 */
b6b4e185 1565static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1566{
ee7b9f93 1567 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1568 struct intel_pch_pll *pll;
92f2584a
JB		 1569 int reg;
1570 u32 val;
1571
48da64a8 1572 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1573 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1574 pll = intel_crtc->pch_pll;
1575 if (pll == NULL)
1576 return;
1577
1578 if (WARN_ON(pll->refcount == 0))
1579 return;
ee7b9f93
JB		 1580
1581 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1582 pll->pll_reg, pll->active, pll->on,
1583 intel_crtc->base.base.id);
92f2584a
JB		 1584
1585 /* PCH refclock must be enabled first */
1586 assert_pch_refclk_enabled(dev_priv);
1587
ee7b9f93 1588 if (pll->active++ && pll->on) {
92b27b08 1589 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1590 return;
1591 }
1592
1593 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1594
1595 reg = pll->pll_reg;
92f2584a
JB		 1596 val = I915_READ(reg);
1597 val |= DPLL_VCO_ENABLE;
1598 I915_WRITE(reg, val);
1599 POSTING_READ(reg);
1600 udelay(200);
ee7b9f93
JB		 1601
1602 pll->on = true;
92f2584a
JB		 1603}
1604
ee7b9f93 1605static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1606{
ee7b9f93
JB		 1607 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1608 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1609 int reg;
ee7b9f93 1610 u32 val;
4c609cb8 1611
92f2584a
JB		 1612 /* PCH only available on ILK+ */
1613 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1614 if (pll == NULL)
1615 return;
92f2584a 1616
48da64a8
CW		 1617 if (WARN_ON(pll->refcount == 0))
1618 return;
7a419866 1619
ee7b9f93
JB		 1620 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1621 pll->pll_reg, pll->active, pll->on,
1622 intel_crtc->base.base.id);
7a419866 1623
48da64a8 1624 if (WARN_ON(pll->active == 0)) {
92b27b08 1625 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1626 return;
1627 }
1628
ee7b9f93 1629 if (--pll->active) {
92b27b08 1630 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1631 return;
ee7b9f93
JB		 1632 }
1633
1634 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1635
1636 /* Make sure transcoder isn't still depending on us */
1637 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1638
ee7b9f93 1639 reg = pll->pll_reg;
92f2584a
JB		 1640 val = I915_READ(reg);
1641 val &= ~DPLL_VCO_ENABLE;
1642 I915_WRITE(reg, val);
1643 POSTING_READ(reg);
1644 udelay(200);
ee7b9f93
JB		 1645
1646 pll->on = false;
92f2584a
JB		 1647}
1648
b8a4f404
PZ		 1649static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1650 enum pipe pipe)
040484af 1651{
23670b32 1652 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1653 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1654 uint32_t reg, val, pipeconf_val;
040484af
JB		 1655
1656 /* PCH only available on ILK+ */
1657 BUG_ON(dev_priv->info->gen < 5);
1658
1659 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1660 assert_pch_pll_enabled(dev_priv,
1661 to_intel_crtc(crtc)->pch_pll,
1662 to_intel_crtc(crtc));
040484af
JB		 1663
1664 /* FDI must be feeding us bits for PCH ports */
1665 assert_fdi_tx_enabled(dev_priv, pipe);
1666 assert_fdi_rx_enabled(dev_priv, pipe);
1667
23670b32
DV		 1668 if (HAS_PCH_CPT(dev)) {
1669 /* Workaround: Set the timing override bit before enabling the
1670 * pch transcoder. */
1671 reg = TRANS_CHICKEN2(pipe);
1672 val = I915_READ(reg);
1673 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1674 I915_WRITE(reg, val);
59c859d6 1675 }
23670b32 1676
040484af
JB		 1677 reg = TRANSCONF(pipe);
1678 val = I915_READ(reg);
5f7f726d 1679 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1680
1681 if (HAS_PCH_IBX(dev_priv->dev)) {
1682 /*
1683 * make the BPC in transcoder be consistent with
1684 * that in pipeconf reg.
1685 */
dfd07d72
DV		 1686 val &= ~PIPECONF_BPC_MASK;
1687 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1688 }
5f7f726d
PZ		 1689
1690 val &= ~TRANS_INTERLACE_MASK;
1691 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1692 if (HAS_PCH_IBX(dev_priv->dev) &&
1693 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1694 val |= TRANS_LEGACY_INTERLACED_ILK;
1695 else
1696 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1697 else
1698 val |= TRANS_PROGRESSIVE;
1699
040484af
JB		 1700 I915_WRITE(reg, val | TRANS_ENABLE);
1701 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1702 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1703}
1704
8fb033d7 1705static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1706 enum transcoder cpu_transcoder)
040484af 1707{
8fb033d7 1708 u32 val, pipeconf_val;
8fb033d7
PZ		 1709
1710 /* PCH only available on ILK+ */
1711 BUG_ON(dev_priv->info->gen < 5);
1712
8fb033d7 1713 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1714 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1715 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1716
223a6fdf
PZ		 1717 /* Workaround: set timing override bit. */
1718 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1719 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1720 I915_WRITE(_TRANSA_CHICKEN2, val);
1721
25f3ef11 1722 val = TRANS_ENABLE;
937bb610 1723 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1724
9a76b1c6
PZ		 1725 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1726 PIPECONF_INTERLACED_ILK)
a35f2679 1727 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1728 else
1729 val |= TRANS_PROGRESSIVE;
1730
25f3ef11 1731 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1732 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1733 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1734}
1735
b8a4f404
PZ		 1736static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1737 enum pipe pipe)
040484af 1738{
23670b32
DV		 1739 struct drm_device *dev = dev_priv->dev;
1740 uint32_t reg, val;
040484af
JB		 1741
1742 /* FDI relies on the transcoder */
1743 assert_fdi_tx_disabled(dev_priv, pipe);
1744 assert_fdi_rx_disabled(dev_priv, pipe);
1745
291906f1
JB		 1746 /* Ports must be off as well */
1747 assert_pch_ports_disabled(dev_priv, pipe);
1748
040484af
JB		 1749 reg = TRANSCONF(pipe);
1750 val = I915_READ(reg);
1751 val &= ~TRANS_ENABLE;
1752 I915_WRITE(reg, val);
1753 /* wait for PCH transcoder off, transcoder state */
1754 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1755 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1756
1757 if (!HAS_PCH_IBX(dev)) {
1758 /* Workaround: Clear the timing override chicken bit again. */
1759 reg = TRANS_CHICKEN2(pipe);
1760 val = I915_READ(reg);
1761 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1762 I915_WRITE(reg, val);
1763 }
040484af
JB		 1764}
1765
ab4d966c 1766static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1767{
8fb033d7
PZ		 1768 u32 val;
1769
8a52fd9f 1770 val = I915_READ(_TRANSACONF);
8fb033d7 1771 val &= ~TRANS_ENABLE;
8a52fd9f 1772 I915_WRITE(_TRANSACONF, val);
8fb033d7 1773 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1774 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1775 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1776
1777 /* Workaround: clear timing override bit. */
1778 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1779 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1780 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1781}
1782
b24e7179 1783/**
309cfea8 1784 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1785 * @dev_priv: i915 private structure
1786 * @pipe: pipe to enable
040484af 1787 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1788 *
1789 * Enable @pipe, making sure that various hardware specific requirements
1790 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1791 *
1792 * @pipe should be %PIPE_A or %PIPE_B.
1793 *
1794 * Will wait until the pipe is actually running (i.e. first vblank) before
1795 * returning.
1796 */
040484af
JB		 1797static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1798 bool pch_port)
b24e7179 1799{
702e7a56
PZ		 1800 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1801 pipe);
1a240d4d 1802 enum pipe pch_transcoder;
b24e7179
JB		 1803 int reg;
1804 u32 val;
1805
681e5811 1806 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1807 pch_transcoder = TRANSCODER_A;
1808 else
1809 pch_transcoder = pipe;
1810
b24e7179
JB		 1811 /*
1812 * A pipe without a PLL won't actually be able to drive bits from
1813 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1814 * need the check.
1815 */
1816 if (!HAS_PCH_SPLIT(dev_priv->dev))
1817 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1818 else {
1819 if (pch_port) {
1820 /* if driving the PCH, we need FDI enabled */
cc391bbb 1821 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1822 assert_fdi_tx_pll_enabled(dev_priv,
1823 (enum pipe) cpu_transcoder);
040484af
JB		 1824 }
1825 /* FIXME: assert CPU port conditions for SNB+ */
1826 }
b24e7179 1827
702e7a56 1828 reg = PIPECONF(cpu_transcoder);
b24e7179 1829 val = I915_READ(reg);
00d70b15
CW		 1830 if (val & PIPECONF_ENABLE)
1831 return;
1832
1833 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1834 intel_wait_for_vblank(dev_priv->dev, pipe);
1835}
1836
1837/**
309cfea8 1838 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1839 * @dev_priv: i915 private structure
1840 * @pipe: pipe to disable
1841 *
1842 * Disable @pipe, making sure that various hardware specific requirements
1843 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1844 *
1845 * @pipe should be %PIPE_A or %PIPE_B.
1846 *
1847 * Will wait until the pipe has shut down before returning.
1848 */
1849static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1850 enum pipe pipe)
1851{
702e7a56
PZ		 1852 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1853 pipe);
b24e7179
JB		 1854 int reg;
1855 u32 val;
1856
1857 /*
1858 * Make sure planes won't keep trying to pump pixels to us,
1859 * or we might hang the display.
1860 */
1861 assert_planes_disabled(dev_priv, pipe);
1862
1863 /* Don't disable pipe A or pipe A PLLs if needed */
1864 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1865 return;
1866
702e7a56 1867 reg = PIPECONF(cpu_transcoder);
b24e7179 1868 val = I915_READ(reg);
00d70b15
CW		 1869 if ((val & PIPECONF_ENABLE) == 0)
1870 return;
1871
1872 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1873 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1874}
1875
d74362c9
KP		 1876/*
1877 * Plane regs are double buffered, going from enabled->disabled needs a
1878 * trigger in order to latch. The display address reg provides this.
1879 */
6f1d69b0 1880void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1881 enum plane plane)
1882{
14f86147
DL		 1883 if (dev_priv->info->gen >= 4)
1884 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1885 else
1886 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1887}
1888
b24e7179
JB		 1889/**
1890 * intel_enable_plane - enable a display plane on a given pipe
1891 * @dev_priv: i915 private structure
1892 * @plane: plane to enable
1893 * @pipe: pipe being fed
1894 *
1895 * Enable @plane on @pipe, making sure that @pipe is running first.
1896 */
1897static void intel_enable_plane(struct drm_i915_private *dev_priv,
1898 enum plane plane, enum pipe pipe)
1899{
1900 int reg;
1901 u32 val;
1902
1903 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1904 assert_pipe_enabled(dev_priv, pipe);
1905
1906 reg = DSPCNTR(plane);
1907 val = I915_READ(reg);
00d70b15
CW		 1908 if (val & DISPLAY_PLANE_ENABLE)
1909 return;
1910
1911 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1912 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1913 intel_wait_for_vblank(dev_priv->dev, pipe);
1914}
1915
b24e7179
JB		 1916/**
1917 * intel_disable_plane - disable a display plane
1918 * @dev_priv: i915 private structure
1919 * @plane: plane to disable
1920 * @pipe: pipe consuming the data
1921 *
1922 * Disable @plane; should be an independent operation.
1923 */
1924static void intel_disable_plane(struct drm_i915_private *dev_priv,
1925 enum plane plane, enum pipe pipe)
1926{
1927 int reg;
1928 u32 val;
1929
1930 reg = DSPCNTR(plane);
1931 val = I915_READ(reg);
00d70b15
CW		 1932 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1933 return;
1934
1935 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1936 intel_flush_display_plane(dev_priv, plane);
1937 intel_wait_for_vblank(dev_priv->dev, pipe);
1938}
1939
127bd2ac 1940int
48b956c5 1941intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1942 struct drm_i915_gem_object *obj,
919926ae 1943 struct intel_ring_buffer *pipelined)
6b95a207 1944{
ce453d81 1945 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1946 u32 alignment;
1947 int ret;
1948
05394f39 1949 switch (obj->tiling_mode) {
6b95a207 1950 case I915_TILING_NONE:
534843da
CW		 1951 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1952 alignment = 128 * 1024;
a6c45cf0 1953 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1954 alignment = 4 * 1024;
1955 else
1956 alignment = 64 * 1024;
6b95a207
KH		 1957 break;
1958 case I915_TILING_X:
1959 /* pin() will align the object as required by fence */
1960 alignment = 0;
1961 break;
1962 case I915_TILING_Y:
1963 /* FIXME: Is this true? */
1964 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1965 return -EINVAL;
1966 default:
1967 BUG();
1968 }
1969
ce453d81 1970 dev_priv->mm.interruptible = false;
2da3b9b9 1971 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1972 if (ret)
ce453d81 1973 goto err_interruptible;
6b95a207
KH		 1974
1975 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1976 * fence, whereas 965+ only requires a fence if using
1977 * framebuffer compression. For simplicity, we always install
1978 * a fence as the cost is not that onerous.
1979 */
06d98131 1980 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1981 if (ret)
1982 goto err_unpin;
1690e1eb 1983
9a5a53b3 1984 i915_gem_object_pin_fence(obj);
6b95a207 1985
ce453d81 1986 dev_priv->mm.interruptible = true;
6b95a207 1987 return 0;
48b956c5
CW		 1988
1989err_unpin:
1990 i915_gem_object_unpin(obj);
ce453d81
CW		 1991err_interruptible:
1992 dev_priv->mm.interruptible = true;
48b956c5 1993 return ret;
6b95a207
KH		 1994}
1995
1690e1eb
CW		 1996void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1997{
1998 i915_gem_object_unpin_fence(obj);
1999 i915_gem_object_unpin(obj);
2000}
2001
c2c75131
DV		 2002/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2003 * is assumed to be a power-of-two. */
5a35e99e
DL		 2004unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2005 unsigned int bpp,
2006 unsigned int pitch)
c2c75131
DV		 2007{
2008 int tile_rows, tiles;
2009
2010 tile_rows = *y / 8;
2011 *y %= 8;
2012 tiles = *x / (512/bpp);
2013 *x %= 512/bpp;
2014
2015 return tile_rows * pitch * 8 + tiles * 4096;
2016}
2017
17638cd6
JB		 2018static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2019 int x, int y)
81255565
JB		 2020{
2021 struct drm_device *dev = crtc->dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024 struct intel_framebuffer *intel_fb;
05394f39 2025 struct drm_i915_gem_object *obj;
81255565 2026 int plane = intel_crtc->plane;
e506a0c6 2027 unsigned long linear_offset;
81255565 2028 u32 dspcntr;
5eddb70b 2029 u32 reg;
81255565
JB		 2030
2031 switch (plane) {
2032 case 0:
2033 case 1:
2034 break;
2035 default:
2036 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2037 return -EINVAL;
2038 }
2039
2040 intel_fb = to_intel_framebuffer(fb);
2041 obj = intel_fb->obj;
81255565 2042
5eddb70b
CW		 2043 reg = DSPCNTR(plane);
2044 dspcntr = I915_READ(reg);
81255565
JB		 2045 /* Mask out pixel format bits in case we change it */
2046 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2047 switch (fb->pixel_format) {
2048 case DRM_FORMAT_C8:
81255565
JB		 2049 dspcntr |= DISPPLANE_8BPP;
2050 break;
57779d06
VS		 2051 case DRM_FORMAT_XRGB1555:
2052 case DRM_FORMAT_ARGB1555:
2053 dspcntr |= DISPPLANE_BGRX555;
81255565 2054 break;
57779d06
VS		 2055 case DRM_FORMAT_RGB565:
2056 dspcntr |= DISPPLANE_BGRX565;
2057 break;
2058 case DRM_FORMAT_XRGB8888:
2059 case DRM_FORMAT_ARGB8888:
2060 dspcntr |= DISPPLANE_BGRX888;
2061 break;
2062 case DRM_FORMAT_XBGR8888:
2063 case DRM_FORMAT_ABGR8888:
2064 dspcntr |= DISPPLANE_RGBX888;
2065 break;
2066 case DRM_FORMAT_XRGB2101010:
2067 case DRM_FORMAT_ARGB2101010:
2068 dspcntr |= DISPPLANE_BGRX101010;
2069 break;
2070 case DRM_FORMAT_XBGR2101010:
2071 case DRM_FORMAT_ABGR2101010:
2072 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2073 break;
2074 default:
57779d06 2075 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2076 return -EINVAL;
2077 }
57779d06 2078
a6c45cf0 2079 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2080 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2081 dspcntr |= DISPPLANE_TILED;
2082 else
2083 dspcntr &= ~DISPPLANE_TILED;
2084 }
2085
5eddb70b 2086 I915_WRITE(reg, dspcntr);
81255565 2087
e506a0c6 2088 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2089
c2c75131
DV		 2090 if (INTEL_INFO(dev)->gen >= 4) {
2091 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2092 intel_gen4_compute_offset_xtiled(&x, &y,
2093 fb->bits_per_pixel / 8,
2094 fb->pitches[0]);
c2c75131
DV		 2095 linear_offset -= intel_crtc->dspaddr_offset;
2096 } else {
e506a0c6 2097 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2098 }
e506a0c6
DV		 2099
2100 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2101 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2102 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2103 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2104 I915_MODIFY_DISPBASE(DSPSURF(plane),
2105 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2106 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2107 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2108 } else
e506a0c6 2109 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2110 POSTING_READ(reg);
81255565 2111
17638cd6
JB		 2112 return 0;
2113}
2114
2115static int ironlake_update_plane(struct drm_crtc *crtc,
2116 struct drm_framebuffer *fb, int x, int y)
2117{
2118 struct drm_device *dev = crtc->dev;
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2121 struct intel_framebuffer *intel_fb;
2122 struct drm_i915_gem_object *obj;
2123 int plane = intel_crtc->plane;
e506a0c6 2124 unsigned long linear_offset;
17638cd6
JB		 2125 u32 dspcntr;
2126 u32 reg;
2127
2128 switch (plane) {
2129 case 0:
2130 case 1:
27f8227b 2131 case 2:
17638cd6
JB		 2132 break;
2133 default:
2134 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2135 return -EINVAL;
2136 }
2137
2138 intel_fb = to_intel_framebuffer(fb);
2139 obj = intel_fb->obj;
2140
2141 reg = DSPCNTR(plane);
2142 dspcntr = I915_READ(reg);
2143 /* Mask out pixel format bits in case we change it */
2144 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2145 switch (fb->pixel_format) {
2146 case DRM_FORMAT_C8:
17638cd6
JB		 2147 dspcntr |= DISPPLANE_8BPP;
2148 break;
57779d06
VS		 2149 case DRM_FORMAT_RGB565:
2150 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2151 break;
57779d06
VS		 2152 case DRM_FORMAT_XRGB8888:
2153 case DRM_FORMAT_ARGB8888:
2154 dspcntr |= DISPPLANE_BGRX888;
2155 break;
2156 case DRM_FORMAT_XBGR8888:
2157 case DRM_FORMAT_ABGR8888:
2158 dspcntr |= DISPPLANE_RGBX888;
2159 break;
2160 case DRM_FORMAT_XRGB2101010:
2161 case DRM_FORMAT_ARGB2101010:
2162 dspcntr |= DISPPLANE_BGRX101010;
2163 break;
2164 case DRM_FORMAT_XBGR2101010:
2165 case DRM_FORMAT_ABGR2101010:
2166 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2167 break;
2168 default:
57779d06 2169 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2170 return -EINVAL;
2171 }
2172
2173 if (obj->tiling_mode != I915_TILING_NONE)
2174 dspcntr |= DISPPLANE_TILED;
2175 else
2176 dspcntr &= ~DISPPLANE_TILED;
2177
2178 /* must disable */
2179 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2180
2181 I915_WRITE(reg, dspcntr);
2182
e506a0c6 2183 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2184 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2185 intel_gen4_compute_offset_xtiled(&x, &y,
2186 fb->bits_per_pixel / 8,
2187 fb->pitches[0]);
c2c75131 2188 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2189
e506a0c6
DV		 2190 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2191 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2192 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2193 I915_MODIFY_DISPBASE(DSPSURF(plane),
2194 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2195 if (IS_HASWELL(dev)) {
2196 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2197 } else {
2198 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2199 I915_WRITE(DSPLINOFF(plane), linear_offset);
2200 }
17638cd6
JB		 2201 POSTING_READ(reg);
2202
2203 return 0;
2204}
2205
2206/* Assume fb object is pinned & idle & fenced and just update base pointers */
2207static int
2208intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2209 int x, int y, enum mode_set_atomic state)
2210{
2211 struct drm_device *dev = crtc->dev;
2212 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2213
6b8e6ed0
CW		 2214 if (dev_priv->display.disable_fbc)
2215 dev_priv->display.disable_fbc(dev);
3dec0095 2216 intel_increase_pllclock(crtc);
81255565 2217
6b8e6ed0 2218 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2219}
2220
96a02917
VS		 2221void intel_display_handle_reset(struct drm_device *dev)
2222{
2223 struct drm_i915_private *dev_priv = dev->dev_private;
2224 struct drm_crtc *crtc;
2225
2226 /*
2227 * Flips in the rings have been nuked by the reset,
2228 * so complete all pending flips so that user space
2229 * will get its events and not get stuck.
2230 *
2231 * Also update the base address of all primary
2232 * planes to the the last fb to make sure we're
2233 * showing the correct fb after a reset.
2234 *
2235 * Need to make two loops over the crtcs so that we
2236 * don't try to grab a crtc mutex before the
2237 * pending_flip_queue really got woken up.
2238 */
2239
2240 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2242 enum plane plane = intel_crtc->plane;
2243
2244 intel_prepare_page_flip(dev, plane);
2245 intel_finish_page_flip_plane(dev, plane);
2246 }
2247
2248 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2250
2251 mutex_lock(&crtc->mutex);
2252 if (intel_crtc->active)
2253 dev_priv->display.update_plane(crtc, crtc->fb,
2254 crtc->x, crtc->y);
2255 mutex_unlock(&crtc->mutex);
2256 }
2257}
2258
14667a4b
CW		 2259static int
2260intel_finish_fb(struct drm_framebuffer *old_fb)
2261{
2262 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2263 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2264 bool was_interruptible = dev_priv->mm.interruptible;
2265 int ret;
2266
14667a4b
CW		 2267 /* Big Hammer, we also need to ensure that any pending
2268 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2269 * current scanout is retired before unpinning the old
2270 * framebuffer.
2271 *
2272 * This should only fail upon a hung GPU, in which case we
2273 * can safely continue.
2274 */
2275 dev_priv->mm.interruptible = false;
2276 ret = i915_gem_object_finish_gpu(obj);
2277 dev_priv->mm.interruptible = was_interruptible;
2278
2279 return ret;
2280}
2281
198598d0
VS		 2282static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2283{
2284 struct drm_device *dev = crtc->dev;
2285 struct drm_i915_master_private *master_priv;
2286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2287
2288 if (!dev->primary->master)
2289 return;
2290
2291 master_priv = dev->primary->master->driver_priv;
2292 if (!master_priv->sarea_priv)
2293 return;
2294
2295 switch (intel_crtc->pipe) {
2296 case 0:
2297 master_priv->sarea_priv->pipeA_x = x;
2298 master_priv->sarea_priv->pipeA_y = y;
2299 break;
2300 case 1:
2301 master_priv->sarea_priv->pipeB_x = x;
2302 master_priv->sarea_priv->pipeB_y = y;
2303 break;
2304 default:
2305 break;
2306 }
2307}
2308
5c3b82e2 2309static int
3c4fdcfb 2310intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2311 struct drm_framebuffer *fb)
79e53945
JB		 2312{
2313 struct drm_device *dev = crtc->dev;
6b8e6ed0 2314 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2316 struct drm_framebuffer *old_fb;
5c3b82e2 2317 int ret;
79e53945
JB		 2318
2319 /* no fb bound */
94352cf9 2320 if (!fb) {
a5071c2f 2321 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2322 return 0;
2323 }
2324
5826eca5
ED		 2325 if(intel_crtc->plane > dev_priv->num_pipe) {
2326 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2327 intel_crtc->plane,
2328 dev_priv->num_pipe);
5c3b82e2 2329 return -EINVAL;
79e53945
JB		 2330 }
2331
5c3b82e2 2332 mutex_lock(&dev->struct_mutex);
265db958 2333 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2334 to_intel_framebuffer(fb)->obj,
919926ae 2335 NULL);
5c3b82e2
CW		 2336 if (ret != 0) {
2337 mutex_unlock(&dev->struct_mutex);
a5071c2f 2338 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2339 return ret;
2340 }
79e53945 2341
94352cf9 2342 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2343 if (ret) {
94352cf9 2344 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2345 mutex_unlock(&dev->struct_mutex);
a5071c2f 2346 DRM_ERROR("failed to update base address\n");
4e6cfefc 2347 return ret;
79e53945 2348 }
3c4fdcfb 2349
94352cf9
DV		 2350 old_fb = crtc->fb;
2351 crtc->fb = fb;
6c4c86f5
DV		 2352 crtc->x = x;
2353 crtc->y = y;
94352cf9 2354
b7f1de28
CW		 2355 if (old_fb) {
2356 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2357 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2358 }
652c393a 2359
6b8e6ed0 2360 intel_update_fbc(dev);
5c3b82e2 2361 mutex_unlock(&dev->struct_mutex);
79e53945 2362
198598d0 2363 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2364
2365 return 0;
79e53945
JB		 2366}
2367
5e84e1a4
ZW		 2368static void intel_fdi_normal_train(struct drm_crtc *crtc)
2369{
2370 struct drm_device *dev = crtc->dev;
2371 struct drm_i915_private *dev_priv = dev->dev_private;
2372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2373 int pipe = intel_crtc->pipe;
2374 u32 reg, temp;
2375
2376 /* enable normal train */
2377 reg = FDI_TX_CTL(pipe);
2378 temp = I915_READ(reg);
61e499bf 2379 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2380 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2381 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2382 } else {
2383 temp &= ~FDI_LINK_TRAIN_NONE;
2384 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2385 }
5e84e1a4
ZW		 2386 I915_WRITE(reg, temp);
2387
2388 reg = FDI_RX_CTL(pipe);
2389 temp = I915_READ(reg);
2390 if (HAS_PCH_CPT(dev)) {
2391 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2392 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2393 } else {
2394 temp &= ~FDI_LINK_TRAIN_NONE;
2395 temp |= FDI_LINK_TRAIN_NONE;
2396 }
2397 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2398
2399 /* wait one idle pattern time */
2400 POSTING_READ(reg);
2401 udelay(1000);
357555c0
JB		 2402
2403 /* IVB wants error correction enabled */
2404 if (IS_IVYBRIDGE(dev))
2405 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2406 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2407}
2408
01a415fd
DV		 2409static void ivb_modeset_global_resources(struct drm_device *dev)
2410{
2411 struct drm_i915_private *dev_priv = dev->dev_private;
2412 struct intel_crtc *pipe_B_crtc =
2413 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2414 struct intel_crtc *pipe_C_crtc =
2415 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2416 uint32_t temp;
2417
2418 /* When everything is off disable fdi C so that we could enable fdi B
2419 * with all lanes. XXX: This misses the case where a pipe is not using
2420 * any pch resources and so doesn't need any fdi lanes. */
2421 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2422 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2423 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2424
2425 temp = I915_READ(SOUTH_CHICKEN1);
2426 temp &= ~FDI_BC_BIFURCATION_SELECT;
2427 DRM_DEBUG_KMS("disabling fdi C rx\n");
2428 I915_WRITE(SOUTH_CHICKEN1, temp);
2429 }
2430}
2431
8db9d77b
ZW		 2432/* The FDI link training functions for ILK/Ibexpeak. */
2433static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2434{
2435 struct drm_device *dev = crtc->dev;
2436 struct drm_i915_private *dev_priv = dev->dev_private;
2437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2438 int pipe = intel_crtc->pipe;
0fc932b8 2439 int plane = intel_crtc->plane;
5eddb70b 2440 u32 reg, temp, tries;
8db9d77b 2441
0fc932b8
JB		 2442 /* FDI needs bits from pipe & plane first */
2443 assert_pipe_enabled(dev_priv, pipe);
2444 assert_plane_enabled(dev_priv, plane);
2445
e1a44743
AJ		 2446 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2447 for train result */
5eddb70b
CW		 2448 reg = FDI_RX_IMR(pipe);
2449 temp = I915_READ(reg);
e1a44743
AJ		 2450 temp &= ~FDI_RX_SYMBOL_LOCK;
2451 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2452 I915_WRITE(reg, temp);
2453 I915_READ(reg);
e1a44743
AJ		 2454 udelay(150);
2455
8db9d77b 2456 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2457 reg = FDI_TX_CTL(pipe);
2458 temp = I915_READ(reg);
77ffb597
AJ		 2459 temp &= ~(7 << 19);
2460 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2461 temp &= ~FDI_LINK_TRAIN_NONE;
2462 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2463 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2464
5eddb70b
CW		 2465 reg = FDI_RX_CTL(pipe);
2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2469 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2470
2471 POSTING_READ(reg);
8db9d77b
ZW		 2472 udelay(150);
2473
5b2adf89 2474 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2475 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2476 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2477 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2478
5eddb70b 2479 reg = FDI_RX_IIR(pipe);
e1a44743 2480 for (tries = 0; tries < 5; tries++) {
5eddb70b 2481 temp = I915_READ(reg);
8db9d77b
ZW		 2482 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2483
2484 if ((temp & FDI_RX_BIT_LOCK)) {
2485 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2486 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2487 break;
2488 }
8db9d77b 2489 }
e1a44743 2490 if (tries == 5)
5eddb70b 2491 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2492
2493 /* Train 2 */
5eddb70b
CW		 2494 reg = FDI_TX_CTL(pipe);
2495 temp = I915_READ(reg);
8db9d77b
ZW		 2496 temp &= ~FDI_LINK_TRAIN_NONE;
2497 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2498 I915_WRITE(reg, temp);
8db9d77b 2499
5eddb70b
CW		 2500 reg = FDI_RX_CTL(pipe);
2501 temp = I915_READ(reg);
8db9d77b
ZW		 2502 temp &= ~FDI_LINK_TRAIN_NONE;
2503 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2504 I915_WRITE(reg, temp);
8db9d77b 2505
5eddb70b
CW		 2506 POSTING_READ(reg);
2507 udelay(150);
8db9d77b 2508
5eddb70b 2509 reg = FDI_RX_IIR(pipe);
e1a44743 2510 for (tries = 0; tries < 5; tries++) {
5eddb70b 2511 temp = I915_READ(reg);
8db9d77b
ZW		 2512 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2513
2514 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2515 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2516 DRM_DEBUG_KMS("FDI train 2 done.\n");
2517 break;
2518 }
8db9d77b 2519 }
e1a44743 2520 if (tries == 5)
5eddb70b 2521 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2522
2523 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2524
8db9d77b
ZW		 2525}
2526
0206e353 2527static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2528 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2529 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2530 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2531 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2532};
2533
2534/* The FDI link training functions for SNB/Cougarpoint. */
2535static void gen6_fdi_link_train(struct drm_crtc *crtc)
2536{
2537 struct drm_device *dev = crtc->dev;
2538 struct drm_i915_private *dev_priv = dev->dev_private;
2539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2540 int pipe = intel_crtc->pipe;
fa37d39e 2541 u32 reg, temp, i, retry;
8db9d77b 2542
e1a44743
AJ		 2543 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2544 for train result */
5eddb70b
CW		 2545 reg = FDI_RX_IMR(pipe);
2546 temp = I915_READ(reg);
e1a44743
AJ		 2547 temp &= ~FDI_RX_SYMBOL_LOCK;
2548 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2549 I915_WRITE(reg, temp);
2550
2551 POSTING_READ(reg);
e1a44743
AJ		 2552 udelay(150);
2553
8db9d77b 2554 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
77ffb597
AJ		 2557 temp &= ~(7 << 19);
2558 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2559 temp &= ~FDI_LINK_TRAIN_NONE;
2560 temp |= FDI_LINK_TRAIN_PATTERN_1;
2561 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2562 /* SNB-B */
2563 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2564 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2565
d74cf324
DV		 2566 I915_WRITE(FDI_RX_MISC(pipe),
2567 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2568
5eddb70b
CW		 2569 reg = FDI_RX_CTL(pipe);
2570 temp = I915_READ(reg);
8db9d77b
ZW		 2571 if (HAS_PCH_CPT(dev)) {
2572 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2573 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2574 } else {
2575 temp &= ~FDI_LINK_TRAIN_NONE;
2576 temp |= FDI_LINK_TRAIN_PATTERN_1;
2577 }
5eddb70b
CW		 2578 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2579
2580 POSTING_READ(reg);
8db9d77b
ZW		 2581 udelay(150);
2582
0206e353 2583 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2584 reg = FDI_TX_CTL(pipe);
2585 temp = I915_READ(reg);
8db9d77b
ZW		 2586 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2587 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2588 I915_WRITE(reg, temp);
2589
2590 POSTING_READ(reg);
8db9d77b
ZW		 2591 udelay(500);
2592
fa37d39e
SP		 2593 for (retry = 0; retry < 5; retry++) {
2594 reg = FDI_RX_IIR(pipe);
2595 temp = I915_READ(reg);
2596 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2597 if (temp & FDI_RX_BIT_LOCK) {
2598 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2599 DRM_DEBUG_KMS("FDI train 1 done.\n");
2600 break;
2601 }
2602 udelay(50);
8db9d77b 2603 }
fa37d39e
SP		 2604 if (retry < 5)
2605 break;
8db9d77b
ZW		 2606 }
2607 if (i == 4)
5eddb70b 2608 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2609
2610 /* Train 2 */
5eddb70b
CW		 2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
8db9d77b
ZW		 2613 temp &= ~FDI_LINK_TRAIN_NONE;
2614 temp |= FDI_LINK_TRAIN_PATTERN_2;
2615 if (IS_GEN6(dev)) {
2616 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2617 /* SNB-B */
2618 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2619 }
5eddb70b 2620 I915_WRITE(reg, temp);
8db9d77b 2621
5eddb70b
CW		 2622 reg = FDI_RX_CTL(pipe);
2623 temp = I915_READ(reg);
8db9d77b
ZW		 2624 if (HAS_PCH_CPT(dev)) {
2625 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2626 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2627 } else {
2628 temp &= ~FDI_LINK_TRAIN_NONE;
2629 temp |= FDI_LINK_TRAIN_PATTERN_2;
2630 }
5eddb70b
CW		 2631 I915_WRITE(reg, temp);
2632
2633 POSTING_READ(reg);
8db9d77b
ZW		 2634 udelay(150);
2635
0206e353 2636 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2637 reg = FDI_TX_CTL(pipe);
2638 temp = I915_READ(reg);
8db9d77b
ZW		 2639 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2640 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2641 I915_WRITE(reg, temp);
2642
2643 POSTING_READ(reg);
8db9d77b
ZW		 2644 udelay(500);
2645
fa37d39e
SP		 2646 for (retry = 0; retry < 5; retry++) {
2647 reg = FDI_RX_IIR(pipe);
2648 temp = I915_READ(reg);
2649 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2650 if (temp & FDI_RX_SYMBOL_LOCK) {
2651 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2652 DRM_DEBUG_KMS("FDI train 2 done.\n");
2653 break;
2654 }
2655 udelay(50);
8db9d77b 2656 }
fa37d39e
SP		 2657 if (retry < 5)
2658 break;
8db9d77b
ZW		 2659 }
2660 if (i == 4)
5eddb70b 2661 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2662
2663 DRM_DEBUG_KMS("FDI train done.\n");
2664}
2665
357555c0
JB		 2666/* Manual link training for Ivy Bridge A0 parts */
2667static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2668{
2669 struct drm_device *dev = crtc->dev;
2670 struct drm_i915_private *dev_priv = dev->dev_private;
2671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2672 int pipe = intel_crtc->pipe;
2673 u32 reg, temp, i;
2674
2675 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2676 for train result */
2677 reg = FDI_RX_IMR(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~FDI_RX_SYMBOL_LOCK;
2680 temp &= ~FDI_RX_BIT_LOCK;
2681 I915_WRITE(reg, temp);
2682
2683 POSTING_READ(reg);
2684 udelay(150);
2685
01a415fd
DV		 2686 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2687 I915_READ(FDI_RX_IIR(pipe)));
2688
357555c0
JB		 2689 /* enable CPU FDI TX and PCH FDI RX */
2690 reg = FDI_TX_CTL(pipe);
2691 temp = I915_READ(reg);
2692 temp &= ~(7 << 19);
2693 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2694 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2695 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2696 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2697 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2698 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2699 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2700
d74cf324
DV		 2701 I915_WRITE(FDI_RX_MISC(pipe),
2702 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2703
357555c0
JB		 2704 reg = FDI_RX_CTL(pipe);
2705 temp = I915_READ(reg);
2706 temp &= ~FDI_LINK_TRAIN_AUTO;
2707 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2708 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2709 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2710 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2711
2712 POSTING_READ(reg);
2713 udelay(150);
2714
0206e353 2715 for (i = 0; i < 4; i++) {
357555c0
JB		 2716 reg = FDI_TX_CTL(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2719 temp |= snb_b_fdi_train_param[i];
2720 I915_WRITE(reg, temp);
2721
2722 POSTING_READ(reg);
2723 udelay(500);
2724
2725 reg = FDI_RX_IIR(pipe);
2726 temp = I915_READ(reg);
2727 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2728
2729 if (temp & FDI_RX_BIT_LOCK ||
2730 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2731 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2732 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2733 break;
2734 }
2735 }
2736 if (i == 4)
2737 DRM_ERROR("FDI train 1 fail!\n");
2738
2739 /* Train 2 */
2740 reg = FDI_TX_CTL(pipe);
2741 temp = I915_READ(reg);
2742 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2743 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2744 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2745 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2746 I915_WRITE(reg, temp);
2747
2748 reg = FDI_RX_CTL(pipe);
2749 temp = I915_READ(reg);
2750 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2751 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2752 I915_WRITE(reg, temp);
2753
2754 POSTING_READ(reg);
2755 udelay(150);
2756
0206e353 2757 for (i = 0; i < 4; i++) {
357555c0
JB		 2758 reg = FDI_TX_CTL(pipe);
2759 temp = I915_READ(reg);
2760 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2761 temp |= snb_b_fdi_train_param[i];
2762 I915_WRITE(reg, temp);
2763
2764 POSTING_READ(reg);
2765 udelay(500);
2766
2767 reg = FDI_RX_IIR(pipe);
2768 temp = I915_READ(reg);
2769 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2770
2771 if (temp & FDI_RX_SYMBOL_LOCK) {
2772 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2773 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2774 break;
2775 }
2776 }
2777 if (i == 4)
2778 DRM_ERROR("FDI train 2 fail!\n");
2779
2780 DRM_DEBUG_KMS("FDI train done.\n");
2781}
2782
88cefb6c 2783static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2784{
88cefb6c 2785 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2786 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2787 int pipe = intel_crtc->pipe;
5eddb70b 2788 u32 reg, temp;
79e53945 2789
c64e311e 2790
c98e9dcf 2791 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2792 reg = FDI_RX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2795 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2796 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2797 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2798
2799 POSTING_READ(reg);
c98e9dcf
JB		 2800 udelay(200);
2801
2802 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2803 temp = I915_READ(reg);
2804 I915_WRITE(reg, temp | FDI_PCDCLK);
2805
2806 POSTING_READ(reg);
c98e9dcf
JB		 2807 udelay(200);
2808
20749730
PZ		 2809 /* Enable CPU FDI TX PLL, always on for Ironlake */
2810 reg = FDI_TX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2813 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2814
20749730
PZ		 2815 POSTING_READ(reg);
2816 udelay(100);
6be4a607 2817 }
0e23b99d
JB		 2818}
2819
88cefb6c
DV		 2820static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2821{
2822 struct drm_device *dev = intel_crtc->base.dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 int pipe = intel_crtc->pipe;
2825 u32 reg, temp;
2826
2827 /* Switch from PCDclk to Rawclk */
2828 reg = FDI_RX_CTL(pipe);
2829 temp = I915_READ(reg);
2830 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2831
2832 /* Disable CPU FDI TX PLL */
2833 reg = FDI_TX_CTL(pipe);
2834 temp = I915_READ(reg);
2835 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2836
2837 POSTING_READ(reg);
2838 udelay(100);
2839
2840 reg = FDI_RX_CTL(pipe);
2841 temp = I915_READ(reg);
2842 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2843
2844 /* Wait for the clocks to turn off. */
2845 POSTING_READ(reg);
2846 udelay(100);
2847}
2848
0fc932b8
JB		 2849static void ironlake_fdi_disable(struct drm_crtc *crtc)
2850{
2851 struct drm_device *dev = crtc->dev;
2852 struct drm_i915_private *dev_priv = dev->dev_private;
2853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2854 int pipe = intel_crtc->pipe;
2855 u32 reg, temp;
2856
2857 /* disable CPU FDI tx and PCH FDI rx */
2858 reg = FDI_TX_CTL(pipe);
2859 temp = I915_READ(reg);
2860 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2861 POSTING_READ(reg);
2862
2863 reg = FDI_RX_CTL(pipe);
2864 temp = I915_READ(reg);
2865 temp &= ~(0x7 << 16);
dfd07d72 2866 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2867 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2868
2869 POSTING_READ(reg);
2870 udelay(100);
2871
2872 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2873 if (HAS_PCH_IBX(dev)) {
2874 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2875 }
0fc932b8
JB		 2876
2877 /* still set train pattern 1 */
2878 reg = FDI_TX_CTL(pipe);
2879 temp = I915_READ(reg);
2880 temp &= ~FDI_LINK_TRAIN_NONE;
2881 temp |= FDI_LINK_TRAIN_PATTERN_1;
2882 I915_WRITE(reg, temp);
2883
2884 reg = FDI_RX_CTL(pipe);
2885 temp = I915_READ(reg);
2886 if (HAS_PCH_CPT(dev)) {
2887 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2888 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2889 } else {
2890 temp &= ~FDI_LINK_TRAIN_NONE;
2891 temp |= FDI_LINK_TRAIN_PATTERN_1;
2892 }
2893 /* BPC in FDI rx is consistent with that in PIPECONF */
2894 temp &= ~(0x07 << 16);
dfd07d72 2895 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2896 I915_WRITE(reg, temp);
2897
2898 POSTING_READ(reg);
2899 udelay(100);
2900}
2901
5bb61643
CW		 2902static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2903{
2904 struct drm_device *dev = crtc->dev;
2905 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2907 unsigned long flags;
2908 bool pending;
2909
10d83730
VS		 2910 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2911 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2912 return false;
2913
2914 spin_lock_irqsave(&dev->event_lock, flags);
2915 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2916 spin_unlock_irqrestore(&dev->event_lock, flags);
2917
2918 return pending;
2919}
2920
e6c3a2a6
CW		 2921static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2922{
0f91128d 2923 struct drm_device *dev = crtc->dev;
5bb61643 2924 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2925
2926 if (crtc->fb == NULL)
2927 return;
2928
2c10d571
DV		 2929 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2930
5bb61643
CW		 2931 wait_event(dev_priv->pending_flip_queue,
2932 !intel_crtc_has_pending_flip(crtc));
2933
0f91128d
CW		 2934 mutex_lock(&dev->struct_mutex);
2935 intel_finish_fb(crtc->fb);
2936 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2937}
2938
fc316cbe 2939static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2940{
2941 struct drm_device *dev = crtc->dev;
228d3e36 2942 struct intel_encoder *intel_encoder;
040484af
JB		 2943
2944 /*
2945 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2946 * must be driven by its own crtc; no sharing is possible.
2947 */
228d3e36 2948 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2949 switch (intel_encoder->type) {
040484af 2950 case INTEL_OUTPUT_EDP:
228d3e36 2951 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2952 return false;
2953 continue;
2954 }
2955 }
2956
2957 return true;
2958}
2959
fc316cbe
PZ		 2960static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2961{
2962 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2963}
2964
e615efe4
ED		 2965/* Program iCLKIP clock to the desired frequency */
2966static void lpt_program_iclkip(struct drm_crtc *crtc)
2967{
2968 struct drm_device *dev = crtc->dev;
2969 struct drm_i915_private *dev_priv = dev->dev_private;
2970 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2971 u32 temp;
2972
09153000
DV		 2973 mutex_lock(&dev_priv->dpio_lock);
2974
e615efe4
ED		 2975 /* It is necessary to ungate the pixclk gate prior to programming
2976 * the divisors, and gate it back when it is done.
2977 */
2978 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2979
2980 /* Disable SSCCTL */
2981 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2982 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2983 SBI_SSCCTL_DISABLE,
2984 SBI_ICLK);
e615efe4
ED		 2985
2986 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2987 if (crtc->mode.clock == 20000) {
2988 auxdiv = 1;
2989 divsel = 0x41;
2990 phaseinc = 0x20;
2991 } else {
2992 /* The iCLK virtual clock root frequency is in MHz,
2993 * but the crtc->mode.clock in in KHz. To get the divisors,
2994 * it is necessary to divide one by another, so we
2995 * convert the virtual clock precision to KHz here for higher
2996 * precision.
2997 */
2998 u32 iclk_virtual_root_freq = 172800 * 1000;
2999 u32 iclk_pi_range = 64;
3000 u32 desired_divisor, msb_divisor_value, pi_value;
3001
3002 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3003 msb_divisor_value = desired_divisor / iclk_pi_range;
3004 pi_value = desired_divisor % iclk_pi_range;
3005
3006 auxdiv = 0;
3007 divsel = msb_divisor_value - 2;
3008 phaseinc = pi_value;
3009 }
3010
3011 /* This should not happen with any sane values */
3012 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3013 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3014 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3015 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3016
3017 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3018 crtc->mode.clock,
3019 auxdiv,
3020 divsel,
3021 phasedir,
3022 phaseinc);
3023
3024 /* Program SSCDIVINTPHASE6 */
988d6ee8 3025 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3026 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3027 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3028 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3029 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3030 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3031 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3032 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3033
3034 /* Program SSCAUXDIV */
988d6ee8 3035 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3036 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3037 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3038 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3039
3040 /* Enable modulator and associated divider */
988d6ee8 3041 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3042 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3043 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3044
3045 /* Wait for initialization time */
3046 udelay(24);
3047
3048 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3049
3050 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3051}
3052
f67a559d
JB		 3053/*
3054 * Enable PCH resources required for PCH ports:
3055 * - PCH PLLs
3056 * - FDI training & RX/TX
3057 * - update transcoder timings
3058 * - DP transcoding bits
3059 * - transcoder
3060 */
3061static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3062{
3063 struct drm_device *dev = crtc->dev;
3064 struct drm_i915_private *dev_priv = dev->dev_private;
3065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3066 int pipe = intel_crtc->pipe;
ee7b9f93 3067 u32 reg, temp;
2c07245f 3068
e7e164db
CW		 3069 assert_transcoder_disabled(dev_priv, pipe);
3070
cd986abb
DV		 3071 /* Write the TU size bits before fdi link training, so that error
3072 * detection works. */
3073 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3074 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3075
c98e9dcf 3076 /* For PCH output, training FDI link */
674cf967 3077 dev_priv->display.fdi_link_train(crtc);
2c07245f 3078
572deb37
DV		 3079 /* XXX: pch pll's can be enabled any time before we enable the PCH
3080 * transcoder, and we actually should do this to not upset any PCH
3081 * transcoder that already use the clock when we share it.
3082 *
3083 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3084 * unconditionally resets the pll - we need that to have the right LVDS
3085 * enable sequence. */
b6b4e185 3086 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3087
303b81e0 3088 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3089 u32 sel;
4b645f14 3090
c98e9dcf 3091 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3092 switch (pipe) {
3093 default:
3094 case 0:
3095 temp |= TRANSA_DPLL_ENABLE;
3096 sel = TRANSA_DPLLB_SEL;
3097 break;
3098 case 1:
3099 temp |= TRANSB_DPLL_ENABLE;
3100 sel = TRANSB_DPLLB_SEL;
3101 break;
3102 case 2:
3103 temp |= TRANSC_DPLL_ENABLE;
3104 sel = TRANSC_DPLLB_SEL;
3105 break;
d64311ab 3106 }
ee7b9f93
JB		 3107 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3108 temp |= sel;
3109 else
3110 temp &= ~sel;
c98e9dcf 3111 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3112 }
5eddb70b 3113
d9b6cb56
JB		 3114 /* set transcoder timing, panel must allow it */
3115 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3116 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3117 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3118 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3119
5eddb70b
CW		 3120 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3121 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3122 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3123 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3124
303b81e0 3125 intel_fdi_normal_train(crtc);
5e84e1a4 3126
c98e9dcf
JB		 3127 /* For PCH DP, enable TRANS_DP_CTL */
3128 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3129 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3130 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3131 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3132 reg = TRANS_DP_CTL(pipe);
3133 temp = I915_READ(reg);
3134 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3135 TRANS_DP_SYNC_MASK |
3136 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3137 temp |= (TRANS_DP_OUTPUT_ENABLE |
3138 TRANS_DP_ENH_FRAMING);
9325c9f0 3139 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3140
3141 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3142 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3143 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3144 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3145
3146 switch (intel_trans_dp_port_sel(crtc)) {
3147 case PCH_DP_B:
5eddb70b 3148 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3149 break;
3150 case PCH_DP_C:
5eddb70b 3151 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3152 break;
3153 case PCH_DP_D:
5eddb70b 3154 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3155 break;
3156 default:
e95d41e1 3157 BUG();
32f9d658 3158 }
2c07245f 3159
5eddb70b 3160 I915_WRITE(reg, temp);
6be4a607 3161 }
b52eb4dc 3162
b8a4f404 3163 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3164}
3165
1507e5bd
PZ		 3166static void lpt_pch_enable(struct drm_crtc *crtc)
3167{
3168 struct drm_device *dev = crtc->dev;
3169 struct drm_i915_private *dev_priv = dev->dev_private;
3170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3171 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3172
daed2dbb 3173 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3174
8c52b5e8 3175 lpt_program_iclkip(crtc);
1507e5bd 3176
0540e488 3177 /* Set transcoder timing. */
daed2dbb
PZ		 3178 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3179 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3180 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3181
daed2dbb
PZ		 3182 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3183 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3184 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3185 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3186
937bb610 3187 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3188}
3189
ee7b9f93
JB		 3190static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3191{
3192 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3193
3194 if (pll == NULL)
3195 return;
3196
3197 if (pll->refcount == 0) {
3198 WARN(1, "bad PCH PLL refcount\n");
3199 return;
3200 }
3201
3202 --pll->refcount;
3203 intel_crtc->pch_pll = NULL;
3204}
3205
3206static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3207{
3208 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3209 struct intel_pch_pll *pll;
3210 int i;
3211
3212 pll = intel_crtc->pch_pll;
3213 if (pll) {
3214 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3215 intel_crtc->base.base.id, pll->pll_reg);
3216 goto prepare;
3217 }
3218
98b6bd99
DV		 3219 if (HAS_PCH_IBX(dev_priv->dev)) {
3220 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3221 i = intel_crtc->pipe;
3222 pll = &dev_priv->pch_plls[i];
3223
3224 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3225 intel_crtc->base.base.id, pll->pll_reg);
3226
3227 goto found;
3228 }
3229
ee7b9f93
JB		 3230 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3231 pll = &dev_priv->pch_plls[i];
3232
3233 /* Only want to check enabled timings first */
3234 if (pll->refcount == 0)
3235 continue;
3236
3237 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3238 fp == I915_READ(pll->fp0_reg)) {
3239 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3240 intel_crtc->base.base.id,
3241 pll->pll_reg, pll->refcount, pll->active);
3242
3243 goto found;
3244 }
3245 }
3246
3247 /* Ok no matching timings, maybe there's a free one? */
3248 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3249 pll = &dev_priv->pch_plls[i];
3250 if (pll->refcount == 0) {
3251 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3252 intel_crtc->base.base.id, pll->pll_reg);
3253 goto found;
3254 }
3255 }
3256
3257 return NULL;
3258
3259found:
3260 intel_crtc->pch_pll = pll;
3261 pll->refcount++;
3262 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3263prepare: /* separate function? */
3264 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3265
e04c7350
CW		 3266 /* Wait for the clocks to stabilize before rewriting the regs */
3267 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3268 POSTING_READ(pll->pll_reg);
3269 udelay(150);
e04c7350
CW		 3270
3271 I915_WRITE(pll->fp0_reg, fp);
3272 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3273 pll->on = false;
3274 return pll;
3275}
3276
d4270e57
JB		 3277void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3278{
3279 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3280 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3281 u32 temp;
3282
3283 temp = I915_READ(dslreg);
3284 udelay(500);
3285 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3286 if (wait_for(I915_READ(dslreg) != temp, 5))
3287 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3288 }
3289}
3290
f67a559d
JB		 3291static void ironlake_crtc_enable(struct drm_crtc *crtc)
3292{
3293 struct drm_device *dev = crtc->dev;
3294 struct drm_i915_private *dev_priv = dev->dev_private;
3295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3296 struct intel_encoder *encoder;
f67a559d
JB		 3297 int pipe = intel_crtc->pipe;
3298 int plane = intel_crtc->plane;
3299 u32 temp;
3300 bool is_pch_port;
3301
08a48469
DV		 3302 WARN_ON(!crtc->enabled);
3303
f67a559d
JB		 3304 if (intel_crtc->active)
3305 return;
3306
3307 intel_crtc->active = true;
3308 intel_update_watermarks(dev);
3309
3310 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3311 temp = I915_READ(PCH_LVDS);
3312 if ((temp & LVDS_PORT_EN) == 0)
3313 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3314 }
3315
fc316cbe 3316 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3317
46b6f814 3318 if (is_pch_port) {
fff367c7
DV		 3319 /* Note: FDI PLL enabling _must_ be done before we enable the
3320 * cpu pipes, hence this is separate from all the other fdi/pch
3321 * enabling. */
88cefb6c 3322 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3323 } else {
3324 assert_fdi_tx_disabled(dev_priv, pipe);
3325 assert_fdi_rx_disabled(dev_priv, pipe);
3326 }
f67a559d 3327
bf49ec8c
DV		 3328 for_each_encoder_on_crtc(dev, crtc, encoder)
3329 if (encoder->pre_enable)
3330 encoder->pre_enable(encoder);
f67a559d
JB		 3331
3332 /* Enable panel fitting for LVDS */
3333 if (dev_priv->pch_pf_size &&
547dc041
JN		 3334 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3335 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3336 /* Force use of hard-coded filter coefficients
3337 * as some pre-programmed values are broken,
3338 * e.g. x201.
3339 */
13888d78
PZ		 3340 if (IS_IVYBRIDGE(dev))
3341 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3342 PF_PIPE_SEL_IVB(pipe));
3343 else
3344 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3345 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3346 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3347 }
3348
9c54c0dd
JB		 3349 /*
3350 * On ILK+ LUT must be loaded before the pipe is running but with
3351 * clocks enabled
3352 */
3353 intel_crtc_load_lut(crtc);
3354
f67a559d
JB		 3355 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3356 intel_enable_plane(dev_priv, plane, pipe);
3357
3358 if (is_pch_port)
3359 ironlake_pch_enable(crtc);
c98e9dcf 3360
d1ebd816 3361 mutex_lock(&dev->struct_mutex);
bed4a673 3362 intel_update_fbc(dev);
d1ebd816
BW		 3363 mutex_unlock(&dev->struct_mutex);
3364
6b383a7f 3365 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3366
fa5c73b1
DV		 3367 for_each_encoder_on_crtc(dev, crtc, encoder)
3368 encoder->enable(encoder);
61b77ddd
DV		 3369
3370 if (HAS_PCH_CPT(dev))
3371 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3372
3373 /*
3374 * There seems to be a race in PCH platform hw (at least on some
3375 * outputs) where an enabled pipe still completes any pageflip right
3376 * away (as if the pipe is off) instead of waiting for vblank. As soon
3377 * as the first vblank happend, everything works as expected. Hence just
3378 * wait for one vblank before returning to avoid strange things
3379 * happening.
3380 */
3381 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3382}
3383
4f771f10
PZ		 3384static void haswell_crtc_enable(struct drm_crtc *crtc)
3385{
3386 struct drm_device *dev = crtc->dev;
3387 struct drm_i915_private *dev_priv = dev->dev_private;
3388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3389 struct intel_encoder *encoder;
3390 int pipe = intel_crtc->pipe;
3391 int plane = intel_crtc->plane;
4f771f10
PZ		 3392 bool is_pch_port;
3393
3394 WARN_ON(!crtc->enabled);
3395
3396 if (intel_crtc->active)
3397 return;
3398
3399 intel_crtc->active = true;
3400 intel_update_watermarks(dev);
3401
fc316cbe 3402 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3403
83616634 3404 if (is_pch_port)
04945641 3405 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3406
3407 for_each_encoder_on_crtc(dev, crtc, encoder)
3408 if (encoder->pre_enable)
3409 encoder->pre_enable(encoder);
3410
1f544388 3411 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3412
1f544388 3413 /* Enable panel fitting for eDP */
547dc041
JN		 3414 if (dev_priv->pch_pf_size &&
3415 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3416 /* Force use of hard-coded filter coefficients
3417 * as some pre-programmed values are broken,
3418 * e.g. x201.
3419 */
54075a7d
PZ		 3420 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3421 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3422 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3423 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3424 }
3425
3426 /*
3427 * On ILK+ LUT must be loaded before the pipe is running but with
3428 * clocks enabled
3429 */
3430 intel_crtc_load_lut(crtc);
3431
1f544388
PZ		 3432 intel_ddi_set_pipe_settings(crtc);
3433 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3434
3435 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3436 intel_enable_plane(dev_priv, plane, pipe);
3437
3438 if (is_pch_port)
1507e5bd 3439 lpt_pch_enable(crtc);
4f771f10
PZ		 3440
3441 mutex_lock(&dev->struct_mutex);
3442 intel_update_fbc(dev);
3443 mutex_unlock(&dev->struct_mutex);
3444
3445 intel_crtc_update_cursor(crtc, true);
3446
3447 for_each_encoder_on_crtc(dev, crtc, encoder)
3448 encoder->enable(encoder);
3449
4f771f10
PZ		 3450 /*
3451 * There seems to be a race in PCH platform hw (at least on some
3452 * outputs) where an enabled pipe still completes any pageflip right
3453 * away (as if the pipe is off) instead of waiting for vblank. As soon
3454 * as the first vblank happend, everything works as expected. Hence just
3455 * wait for one vblank before returning to avoid strange things
3456 * happening.
3457 */
3458 intel_wait_for_vblank(dev, intel_crtc->pipe);
3459}
3460
6be4a607
JB		 3461static void ironlake_crtc_disable(struct drm_crtc *crtc)
3462{
3463 struct drm_device *dev = crtc->dev;
3464 struct drm_i915_private *dev_priv = dev->dev_private;
3465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3466 struct intel_encoder *encoder;
6be4a607
JB		 3467 int pipe = intel_crtc->pipe;
3468 int plane = intel_crtc->plane;
5eddb70b 3469 u32 reg, temp;
b52eb4dc 3470
ef9c3aee 3471
f7abfe8b
CW		 3472 if (!intel_crtc->active)
3473 return;
3474
ea9d758d
DV		 3475 for_each_encoder_on_crtc(dev, crtc, encoder)
3476 encoder->disable(encoder);
3477
e6c3a2a6 3478 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3479 drm_vblank_off(dev, pipe);
6b383a7f 3480 intel_crtc_update_cursor(crtc, false);
5eddb70b 3481
b24e7179 3482 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3483
973d04f9
CW		 3484 if (dev_priv->cfb_plane == plane)
3485 intel_disable_fbc(dev);
2c07245f 3486
b24e7179 3487 intel_disable_pipe(dev_priv, pipe);
32f9d658 3488
6be4a607 3489 /* Disable PF */
9db4a9c7
JB		 3490 I915_WRITE(PF_CTL(pipe), 0);
3491 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3492
bf49ec8c
DV		 3493 for_each_encoder_on_crtc(dev, crtc, encoder)
3494 if (encoder->post_disable)
3495 encoder->post_disable(encoder);
2c07245f 3496
0fc932b8 3497 ironlake_fdi_disable(crtc);
249c0e64 3498
b8a4f404 3499 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3500
6be4a607
JB		 3501 if (HAS_PCH_CPT(dev)) {
3502 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3503 reg = TRANS_DP_CTL(pipe);
3504 temp = I915_READ(reg);
3505 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3506 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3507 I915_WRITE(reg, temp);
6be4a607
JB		 3508
3509 /* disable DPLL_SEL */
3510 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3511 switch (pipe) {
3512 case 0:
d64311ab 3513 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3514 break;
3515 case 1:
6be4a607 3516 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3517 break;
3518 case 2:
4b645f14 3519 /* C shares PLL A or B */
d64311ab 3520 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3521 break;
3522 default:
3523 BUG(); /* wtf */
3524 }
6be4a607 3525 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3526 }
e3421a18 3527
6be4a607 3528 /* disable PCH DPLL */
ee7b9f93 3529 intel_disable_pch_pll(intel_crtc);
8db9d77b 3530
88cefb6c 3531 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3532
f7abfe8b 3533 intel_crtc->active = false;
6b383a7f 3534 intel_update_watermarks(dev);
d1ebd816
BW		 3535
3536 mutex_lock(&dev->struct_mutex);
6b383a7f 3537 intel_update_fbc(dev);
d1ebd816 3538 mutex_unlock(&dev->struct_mutex);
6be4a607 3539}
1b3c7a47 3540
4f771f10 3541static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3542{
4f771f10
PZ		 3543 struct drm_device *dev = crtc->dev;
3544 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3546 struct intel_encoder *encoder;
3547 int pipe = intel_crtc->pipe;
3548 int plane = intel_crtc->plane;
ad80a810 3549 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3550 bool is_pch_port;
ee7b9f93 3551
4f771f10
PZ		 3552 if (!intel_crtc->active)
3553 return;
3554
83616634
PZ		 3555 is_pch_port = haswell_crtc_driving_pch(crtc);
3556
4f771f10
PZ		 3557 for_each_encoder_on_crtc(dev, crtc, encoder)
3558 encoder->disable(encoder);
3559
3560 intel_crtc_wait_for_pending_flips(crtc);
3561 drm_vblank_off(dev, pipe);
3562 intel_crtc_update_cursor(crtc, false);
3563
3564 intel_disable_plane(dev_priv, plane, pipe);
3565
3566 if (dev_priv->cfb_plane == plane)
3567 intel_disable_fbc(dev);
3568
3569 intel_disable_pipe(dev_priv, pipe);
3570
ad80a810 3571 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3572
3573 /* Disable PF */
3574 I915_WRITE(PF_CTL(pipe), 0);
3575 I915_WRITE(PF_WIN_SZ(pipe), 0);
3576
1f544388 3577 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3578
3579 for_each_encoder_on_crtc(dev, crtc, encoder)
3580 if (encoder->post_disable)
3581 encoder->post_disable(encoder);
3582
83616634 3583 if (is_pch_port) {
ab4d966c 3584 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3585 intel_ddi_fdi_disable(crtc);
83616634 3586 }
4f771f10
PZ		 3587
3588 intel_crtc->active = false;
3589 intel_update_watermarks(dev);
3590
3591 mutex_lock(&dev->struct_mutex);
3592 intel_update_fbc(dev);
3593 mutex_unlock(&dev->struct_mutex);
3594}
3595
ee7b9f93
JB		 3596static void ironlake_crtc_off(struct drm_crtc *crtc)
3597{
3598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3599 intel_put_pch_pll(intel_crtc);
3600}
3601
6441ab5f
PZ		 3602static void haswell_crtc_off(struct drm_crtc *crtc)
3603{
a5c961d1
PZ		 3604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3605
3606 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3607 * start using it. */
1a240d4d 3608 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3609
6441ab5f
PZ		 3610 intel_ddi_put_crtc_pll(crtc);
3611}
3612
02e792fb
DV		 3613static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3614{
02e792fb 3615 if (!enable && intel_crtc->overlay) {
23f09ce3 3616 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3617 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3618
23f09ce3 3619 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3620 dev_priv->mm.interruptible = false;
3621 (void) intel_overlay_switch_off(intel_crtc->overlay);
3622 dev_priv->mm.interruptible = true;
23f09ce3 3623 mutex_unlock(&dev->struct_mutex);
02e792fb 3624 }
02e792fb 3625
5dcdbcb0
CW		 3626 /* Let userspace switch the overlay on again. In most cases userspace
3627 * has to recompute where to put it anyway.
3628 */
02e792fb
DV		 3629}
3630
0b8765c6 3631static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3632{
3633 struct drm_device *dev = crtc->dev;
79e53945
JB		 3634 struct drm_i915_private *dev_priv = dev->dev_private;
3635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3636 struct intel_encoder *encoder;
79e53945 3637 int pipe = intel_crtc->pipe;
80824003 3638 int plane = intel_crtc->plane;
79e53945 3639
08a48469
DV		 3640 WARN_ON(!crtc->enabled);
3641
f7abfe8b
CW		 3642 if (intel_crtc->active)
3643 return;
3644
3645 intel_crtc->active = true;
6b383a7f
CW		 3646 intel_update_watermarks(dev);
3647
63d7bbe9 3648 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3649
3650 for_each_encoder_on_crtc(dev, crtc, encoder)
3651 if (encoder->pre_enable)
3652 encoder->pre_enable(encoder);
3653
040484af 3654 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3655 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3656
0b8765c6 3657 intel_crtc_load_lut(crtc);
bed4a673 3658 intel_update_fbc(dev);
79e53945 3659
0b8765c6
JB		 3660 /* Give the overlay scaler a chance to enable if it's on this pipe */
3661 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3662 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3663
fa5c73b1
DV		 3664 for_each_encoder_on_crtc(dev, crtc, encoder)
3665 encoder->enable(encoder);
0b8765c6 3666}
79e53945 3667
0b8765c6
JB		 3668static void i9xx_crtc_disable(struct drm_crtc *crtc)
3669{
3670 struct drm_device *dev = crtc->dev;
3671 struct drm_i915_private *dev_priv = dev->dev_private;
3672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3673 struct intel_encoder *encoder;
0b8765c6
JB		 3674 int pipe = intel_crtc->pipe;
3675 int plane = intel_crtc->plane;
24a1f16d 3676 u32 pctl;
b690e96c 3677
ef9c3aee 3678
f7abfe8b
CW		 3679 if (!intel_crtc->active)
3680 return;
3681
ea9d758d
DV		 3682 for_each_encoder_on_crtc(dev, crtc, encoder)
3683 encoder->disable(encoder);
3684
0b8765c6 3685 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3686 intel_crtc_wait_for_pending_flips(crtc);
3687 drm_vblank_off(dev, pipe);
0b8765c6 3688 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3689 intel_crtc_update_cursor(crtc, false);
0b8765c6 3690
973d04f9
CW		 3691 if (dev_priv->cfb_plane == plane)
3692 intel_disable_fbc(dev);
79e53945 3693
b24e7179 3694 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3695 intel_disable_pipe(dev_priv, pipe);
24a1f16d
MK		 3696
3697 /* Disable pannel fitter if it is on this pipe. */
3698 pctl = I915_READ(PFIT_CONTROL);
3699 if ((pctl & PFIT_ENABLE) &&
3700 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3701 I915_WRITE(PFIT_CONTROL, 0);
3702
63d7bbe9 3703 intel_disable_pll(dev_priv, pipe);
0b8765c6 3704
f7abfe8b 3705 intel_crtc->active = false;
6b383a7f
CW		 3706 intel_update_fbc(dev);
3707 intel_update_watermarks(dev);
0b8765c6
JB		 3708}
3709
ee7b9f93
JB		 3710static void i9xx_crtc_off(struct drm_crtc *crtc)
3711{
3712}
3713
976f8a20
DV		 3714static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3715 bool enabled)
2c07245f
ZW		 3716{
3717 struct drm_device *dev = crtc->dev;
3718 struct drm_i915_master_private *master_priv;
3719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3720 int pipe = intel_crtc->pipe;
79e53945
JB		 3721
3722 if (!dev->primary->master)
3723 return;
3724
3725 master_priv = dev->primary->master->driver_priv;
3726 if (!master_priv->sarea_priv)
3727 return;
3728
79e53945
JB		 3729 switch (pipe) {
3730 case 0:
3731 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3732 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3733 break;
3734 case 1:
3735 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3736 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3737 break;
3738 default:
9db4a9c7 3739 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3740 break;
3741 }
79e53945
JB		 3742}
3743
976f8a20
DV		 3744/**
3745 * Sets the power management mode of the pipe and plane.
3746 */
3747void intel_crtc_update_dpms(struct drm_crtc *crtc)
3748{
3749 struct drm_device *dev = crtc->dev;
3750 struct drm_i915_private *dev_priv = dev->dev_private;
3751 struct intel_encoder *intel_encoder;
3752 bool enable = false;
3753
3754 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3755 enable |= intel_encoder->connectors_active;
3756
3757 if (enable)
3758 dev_priv->display.crtc_enable(crtc);
3759 else
3760 dev_priv->display.crtc_disable(crtc);
3761
3762 intel_crtc_update_sarea(crtc, enable);
3763}
3764
3765static void intel_crtc_noop(struct drm_crtc *crtc)
3766{
3767}
3768
cdd59983
CW		 3769static void intel_crtc_disable(struct drm_crtc *crtc)
3770{
cdd59983 3771 struct drm_device *dev = crtc->dev;
976f8a20 3772 struct drm_connector *connector;
ee7b9f93 3773 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3775
976f8a20
DV		 3776 /* crtc should still be enabled when we disable it. */
3777 WARN_ON(!crtc->enabled);
3778
7b9f35a6 3779 intel_crtc->eld_vld = false;
976f8a20
DV		 3780 dev_priv->display.crtc_disable(crtc);
3781 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3782 dev_priv->display.off(crtc);
3783
931872fc
CW		 3784 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3785 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3786
3787 if (crtc->fb) {
3788 mutex_lock(&dev->struct_mutex);
1690e1eb 3789 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3790 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3791 crtc->fb = NULL;
3792 }
3793
3794 /* Update computed state. */
3795 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3796 if (!connector->encoder || !connector->encoder->crtc)
3797 continue;
3798
3799 if (connector->encoder->crtc != crtc)
3800 continue;
3801
3802 connector->dpms = DRM_MODE_DPMS_OFF;
3803 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3804 }
3805}
3806
a261b246 3807void intel_modeset_disable(struct drm_device *dev)
79e53945 3808{
a261b246
DV		 3809 struct drm_crtc *crtc;
3810
3811 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3812 if (crtc->enabled)
3813 intel_crtc_disable(crtc);
3814 }
79e53945
JB		 3815}
3816
1f703855 3817void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3818{
7e7d76c3
JB		 3819}
3820
ea5b213a 3821void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3822{
4ef69c7a 3823 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3824
ea5b213a
CW		 3825 drm_encoder_cleanup(encoder);
3826 kfree(intel_encoder);
7e7d76c3
JB		 3827}
3828
5ab432ef
DV		 3829/* Simple dpms helper for encodres with just one connector, no cloning and only
3830 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3831 * state of the entire output pipe. */
3832void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3833{
5ab432ef
DV		 3834 if (mode == DRM_MODE_DPMS_ON) {
3835 encoder->connectors_active = true;
3836
b2cabb0e 3837 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3838 } else {
3839 encoder->connectors_active = false;
3840
b2cabb0e 3841 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3842 }
79e53945
JB		 3843}
3844
0a91ca29
DV		 3845/* Cross check the actual hw state with our own modeset state tracking (and it's
3846 * internal consistency). */
b980514c 3847static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3848{
0a91ca29
DV		 3849 if (connector->get_hw_state(connector)) {
3850 struct intel_encoder *encoder = connector->encoder;
3851 struct drm_crtc *crtc;
3852 bool encoder_enabled;
3853 enum pipe pipe;
3854
3855 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3856 connector->base.base.id,
3857 drm_get_connector_name(&connector->base));
3858
3859 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3860 "wrong connector dpms state\n");
3861 WARN(connector->base.encoder != &encoder->base,
3862 "active connector not linked to encoder\n");
3863 WARN(!encoder->connectors_active,
3864 "encoder->connectors_active not set\n");
3865
3866 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3867 WARN(!encoder_enabled, "encoder not enabled\n");
3868 if (WARN_ON(!encoder->base.crtc))
3869 return;
3870
3871 crtc = encoder->base.crtc;
3872
3873 WARN(!crtc->enabled, "crtc not enabled\n");
3874 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3875 WARN(pipe != to_intel_crtc(crtc)->pipe,
3876 "encoder active on the wrong pipe\n");
3877 }
79e53945
JB		 3878}
3879
5ab432ef
DV		 3880/* Even simpler default implementation, if there's really no special case to
3881 * consider. */
3882void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3883{
5ab432ef 3884 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3885
5ab432ef
DV		 3886 /* All the simple cases only support two dpms states. */
3887 if (mode != DRM_MODE_DPMS_ON)
3888 mode = DRM_MODE_DPMS_OFF;
d4270e57 3889
5ab432ef
DV		 3890 if (mode == connector->dpms)
3891 return;
3892
3893 connector->dpms = mode;
3894
3895 /* Only need to change hw state when actually enabled */
3896 if (encoder->base.crtc)
3897 intel_encoder_dpms(encoder, mode);
3898 else
8af6cf88 3899 WARN_ON(encoder->connectors_active != false);
0a91ca29 3900
b980514c 3901 intel_modeset_check_state(connector->dev);
79e53945
JB		 3902}
3903
f0947c37
DV		 3904/* Simple connector->get_hw_state implementation for encoders that support only
3905 * one connector and no cloning and hence the encoder state determines the state
3906 * of the connector. */
3907bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3908{
24929352 3909 enum pipe pipe = 0;
f0947c37 3910 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3911
f0947c37 3912 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3913}
3914
79e53945 3915static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3916 const struct drm_display_mode *mode,
79e53945
JB		 3917 struct drm_display_mode *adjusted_mode)
3918{
2c07245f 3919 struct drm_device *dev = crtc->dev;
89749350 3920
bad720ff 3921 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3922 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3923 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3924 return false;
2c07245f 3925 }
89749350 3926
f9bef081
DV		 3927 /* All interlaced capable intel hw wants timings in frames. Note though
3928 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3929 * timings, so we need to be careful not to clobber these.*/
3930 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3931 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3932
44f46b42
CW		 3933 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3934 * with a hsync front porch of 0.
3935 */
3936 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3937 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3938 return false;
3939
79e53945
JB		 3940 return true;
3941}
3942
25eb05fc
JB		 3943static int valleyview_get_display_clock_speed(struct drm_device *dev)
3944{
3945 return 400000; /* FIXME */
3946}
3947
e70236a8
JB		 3948static int i945_get_display_clock_speed(struct drm_device *dev)
3949{
3950 return 400000;
3951}
79e53945 3952
e70236a8 3953static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3954{
e70236a8
JB		 3955 return 333000;
3956}
79e53945 3957
e70236a8
JB		 3958static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3959{
3960 return 200000;
3961}
79e53945 3962
e70236a8
JB		 3963static int i915gm_get_display_clock_speed(struct drm_device *dev)
3964{
3965 u16 gcfgc = 0;
79e53945 3966
e70236a8
JB		 3967 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3968
3969 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3970 return 133000;
3971 else {
3972 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3973 case GC_DISPLAY_CLOCK_333_MHZ:
3974 return 333000;
3975 default:
3976 case GC_DISPLAY_CLOCK_190_200_MHZ:
3977 return 190000;
79e53945 3978 }
e70236a8
JB		 3979 }
3980}
3981
3982static int i865_get_display_clock_speed(struct drm_device *dev)
3983{
3984 return 266000;
3985}
3986
3987static int i855_get_display_clock_speed(struct drm_device *dev)
3988{
3989 u16 hpllcc = 0;
3990 /* Assume that the hardware is in the high speed state. This
3991 * should be the default.
3992 */
3993 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3994 case GC_CLOCK_133_200:
3995 case GC_CLOCK_100_200:
3996 return 200000;
3997 case GC_CLOCK_166_250:
3998 return 250000;
3999 case GC_CLOCK_100_133:
79e53945 4000 return 133000;
e70236a8 4001 }
79e53945 4002
e70236a8
JB		 4003 /* Shouldn't happen */
4004 return 0;
4005}
79e53945 4006
e70236a8
JB		 4007static int i830_get_display_clock_speed(struct drm_device *dev)
4008{
4009 return 133000;
79e53945
JB		 4010}
4011
2c07245f 4012static void
e69d0bc1 4013intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4014{
4015 while (*num > 0xffffff || *den > 0xffffff) {
4016 *num >>= 1;
4017 *den >>= 1;
4018 }
4019}
4020
e69d0bc1
DV		 4021void
4022intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4023 int pixel_clock, int link_clock,
4024 struct intel_link_m_n *m_n)
2c07245f 4025{
e69d0bc1 4026 m_n->tu = 64;
22ed1113
CW		 4027 m_n->gmch_m = bits_per_pixel * pixel_clock;
4028 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4029 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4030 m_n->link_m = pixel_clock;
4031 m_n->link_n = link_clock;
e69d0bc1 4032 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4033}
4034
a7615030
CW		 4035static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4036{
72bbe58c
KP		 4037 if (i915_panel_use_ssc >= 0)
4038 return i915_panel_use_ssc != 0;
4039 return dev_priv->lvds_use_ssc
435793df 4040 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4041}
4042
5a354204
JB		 4043/**
4044 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4045 * @crtc: CRTC structure
3b5c78a3 4046 * @mode: requested mode
5a354204
JB		 4047 *
4048 * A pipe may be connected to one or more outputs. Based on the depth of the
4049 * attached framebuffer, choose a good color depth to use on the pipe.
4050 *
4051 * If possible, match the pipe depth to the fb depth. In some cases, this
4052 * isn't ideal, because the connected output supports a lesser or restricted
4053 * set of depths. Resolve that here:
4054 * LVDS typically supports only 6bpc, so clamp down in that case
4055 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4056 * Displays may support a restricted set as well, check EDID and clamp as
4057 * appropriate.
3b5c78a3 4058 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4059 *
4060 * RETURNS:
4061 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4062 * true if they don't match).
4063 */
4064static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4065 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4066 unsigned int *pipe_bpp,
4067 struct drm_display_mode *mode)
5a354204
JB		 4068{
4069 struct drm_device *dev = crtc->dev;
4070 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4071 struct drm_connector *connector;
6c2b7c12 4072 struct intel_encoder *intel_encoder;
5a354204
JB		 4073 unsigned int display_bpc = UINT_MAX, bpc;
4074
4075 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4076 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4077
4078 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4079 unsigned int lvds_bpc;
4080
4081 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4082 LVDS_A3_POWER_UP)
4083 lvds_bpc = 8;
4084 else
4085 lvds_bpc = 6;
4086
4087 if (lvds_bpc < display_bpc) {
82820490 4088 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4089 display_bpc = lvds_bpc;
4090 }
4091 continue;
4092 }
4093
5a354204
JB		 4094 /* Not one of the known troublemakers, check the EDID */
4095 list_for_each_entry(connector, &dev->mode_config.connector_list,
4096 head) {
6c2b7c12 4097 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4098 continue;
4099
62ac41a6
JB		 4100 /* Don't use an invalid EDID bpc value */
4101 if (connector->display_info.bpc &&
4102 connector->display_info.bpc < display_bpc) {
82820490 4103 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4104 display_bpc = connector->display_info.bpc;
4105 }
4106 }
4107
2f4f649a
JN		 4108 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4109 /* Use VBT settings if we have an eDP panel */
4110 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4111
9a30a61f 4112 if (edp_bpc && edp_bpc < display_bpc) {
2f4f649a
JN		 4113 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4114 display_bpc = edp_bpc;
4115 }
4116 continue;
4117 }
4118
5a354204
JB		 4119 /*
4120 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4121 * through, clamp it down. (Note: >12bpc will be caught below.)
4122 */
4123 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4124 if (display_bpc > 8 && display_bpc < 12) {
82820490 4125 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4126 display_bpc = 12;
4127 } else {
82820490 4128 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4129 display_bpc = 8;
4130 }
4131 }
4132 }
4133
3b5c78a3
AJ		 4134 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4135 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4136 display_bpc = 6;
4137 }
4138
5a354204
JB		 4139 /*
4140 * We could just drive the pipe at the highest bpc all the time and
4141 * enable dithering as needed, but that costs bandwidth. So choose
4142 * the minimum value that expresses the full color range of the fb but
4143 * also stays within the max display bpc discovered above.
4144 */
4145
94352cf9 4146 switch (fb->depth) {
5a354204
JB		 4147 case 8:
4148 bpc = 8; /* since we go through a colormap */
4149 break;
4150 case 15:
4151 case 16:
4152 bpc = 6; /* min is 18bpp */
4153 break;
4154 case 24:
578393cd 4155 bpc = 8;
5a354204
JB		 4156 break;
4157 case 30:
578393cd 4158 bpc = 10;
5a354204
JB		 4159 break;
4160 case 48:
578393cd 4161 bpc = 12;
5a354204
JB		 4162 break;
4163 default:
4164 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4165 bpc = min((unsigned int)8, display_bpc);
4166 break;
4167 }
4168
578393cd
KP		 4169 display_bpc = min(display_bpc, bpc);
4170
82820490
AJ		 4171 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4172 bpc, display_bpc);
5a354204 4173
578393cd 4174 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4175
4176 return display_bpc != bpc;
4177}
4178
a0c4da24
JB		 4179static int vlv_get_refclk(struct drm_crtc *crtc)
4180{
4181 struct drm_device *dev = crtc->dev;
4182 struct drm_i915_private *dev_priv = dev->dev_private;
4183 int refclk = 27000; /* for DP & HDMI */
4184
4185 return 100000; /* only one validated so far */
4186
4187 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4188 refclk = 96000;
4189 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4190 if (intel_panel_use_ssc(dev_priv))
4191 refclk = 100000;
4192 else
4193 refclk = 96000;
4194 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4195 refclk = 100000;
4196 }
4197
4198 return refclk;
4199}
4200
c65d77d8
JB		 4201static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4202{
4203 struct drm_device *dev = crtc->dev;
4204 struct drm_i915_private *dev_priv = dev->dev_private;
4205 int refclk;
4206
a0c4da24
JB		 4207 if (IS_VALLEYVIEW(dev)) {
4208 refclk = vlv_get_refclk(crtc);
4209 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4210 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4211 refclk = dev_priv->lvds_ssc_freq * 1000;
4212 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4213 refclk / 1000);
4214 } else if (!IS_GEN2(dev)) {
4215 refclk = 96000;
4216 } else {
4217 refclk = 48000;
4218 }
4219
4220 return refclk;
4221}
4222
4223static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4224 intel_clock_t *clock)
4225{
4226 /* SDVO TV has fixed PLL values depend on its clock range,
4227 this mirrors vbios setting. */
4228 if (adjusted_mode->clock >= 100000
4229 && adjusted_mode->clock < 140500) {
4230 clock->p1 = 2;
4231 clock->p2 = 10;
4232 clock->n = 3;
4233 clock->m1 = 16;
4234 clock->m2 = 8;
4235 } else if (adjusted_mode->clock >= 140500
4236 && adjusted_mode->clock <= 200000) {
4237 clock->p1 = 1;
4238 clock->p2 = 10;
4239 clock->n = 6;
4240 clock->m1 = 12;
4241 clock->m2 = 8;
4242 }
4243}
4244
a7516a05
JB		 4245static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4246 intel_clock_t *clock,
4247 intel_clock_t *reduced_clock)
4248{
4249 struct drm_device *dev = crtc->dev;
4250 struct drm_i915_private *dev_priv = dev->dev_private;
4251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4252 int pipe = intel_crtc->pipe;
4253 u32 fp, fp2 = 0;
4254
4255 if (IS_PINEVIEW(dev)) {
4256 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4257 if (reduced_clock)
4258 fp2 = (1 << reduced_clock->n) << 16 |
4259 reduced_clock->m1 << 8 | reduced_clock->m2;
4260 } else {
4261 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4262 if (reduced_clock)
4263 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4264 reduced_clock->m2;
4265 }
4266
4267 I915_WRITE(FP0(pipe), fp);
4268
4269 intel_crtc->lowfreq_avail = false;
4270 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4271 reduced_clock && i915_powersave) {
4272 I915_WRITE(FP1(pipe), fp2);
4273 intel_crtc->lowfreq_avail = true;
4274 } else {
4275 I915_WRITE(FP1(pipe), fp);
4276 }
4277}
4278
a0c4da24
JB		 4279static void vlv_update_pll(struct drm_crtc *crtc,
4280 struct drm_display_mode *mode,
4281 struct drm_display_mode *adjusted_mode,
4282 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4283 int num_connectors)
a0c4da24
JB		 4284{
4285 struct drm_device *dev = crtc->dev;
4286 struct drm_i915_private *dev_priv = dev->dev_private;
4287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4288 int pipe = intel_crtc->pipe;
4289 u32 dpll, mdiv, pdiv;
4290 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4291 bool is_sdvo;
4292 u32 temp;
a0c4da24 4293
09153000
DV		 4294 mutex_lock(&dev_priv->dpio_lock);
4295
2a8f64ca
VP		 4296 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4297 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4298
2a8f64ca
VP		 4299 dpll = DPLL_VGA_MODE_DIS;
4300 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4301 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4302 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4303
4304 I915_WRITE(DPLL(pipe), dpll);
4305 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4306
4307 bestn = clock->n;
4308 bestm1 = clock->m1;
4309 bestm2 = clock->m2;
4310 bestp1 = clock->p1;
4311 bestp2 = clock->p2;
4312
2a8f64ca
VP		 4313 /*
4314 * In Valleyview PLL and program lane counter registers are exposed
4315 * through DPIO interface
4316 */
a0c4da24
JB		 4317 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4318 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4319 mdiv |= ((bestn << DPIO_N_SHIFT));
4320 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4321 mdiv |= (1 << DPIO_K_SHIFT);
4322 mdiv |= DPIO_ENABLE_CALIBRATION;
4323 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4324
4325 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4326
2a8f64ca 4327 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4328 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4329 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4330 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4331 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4332
2a8f64ca 4333 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4334
4335 dpll |= DPLL_VCO_ENABLE;
4336 I915_WRITE(DPLL(pipe), dpll);
4337 POSTING_READ(DPLL(pipe));
4338 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4339 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4340
2a8f64ca
VP		 4341 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4342
4343 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4344 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4345
4346 I915_WRITE(DPLL(pipe), dpll);
4347
4348 /* Wait for the clocks to stabilize. */
4349 POSTING_READ(DPLL(pipe));
4350 udelay(150);
a0c4da24 4351
2a8f64ca
VP		 4352 temp = 0;
4353 if (is_sdvo) {
4354 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4355 if (temp > 1)
4356 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4357 else
4358 temp = 0;
a0c4da24 4359 }
2a8f64ca
VP		 4360 I915_WRITE(DPLL_MD(pipe), temp);
4361 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4362
2a8f64ca
VP		 4363 /* Now program lane control registers */
4364 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4365 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4366 {
4367 temp = 0x1000C4;
4368 if(pipe == 1)
4369 temp |= (1 << 21);
4370 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4371 }
4372 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4373 {
4374 temp = 0x1000C4;
4375 if(pipe == 1)
4376 temp |= (1 << 21);
4377 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4378 }
09153000
DV		 4379
4380 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4381}
4382
eb1cbe48
DV		 4383static void i9xx_update_pll(struct drm_crtc *crtc,
4384 struct drm_display_mode *mode,
4385 struct drm_display_mode *adjusted_mode,
4386 intel_clock_t *clock, intel_clock_t *reduced_clock,
4387 int num_connectors)
4388{
4389 struct drm_device *dev = crtc->dev;
4390 struct drm_i915_private *dev_priv = dev->dev_private;
4391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4392 struct intel_encoder *encoder;
eb1cbe48
DV		 4393 int pipe = intel_crtc->pipe;
4394 u32 dpll;
4395 bool is_sdvo;
4396
2a8f64ca
VP		 4397 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4398
eb1cbe48
DV		 4399 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4400 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4401
4402 dpll = DPLL_VGA_MODE_DIS;
4403
4404 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4405 dpll |= DPLLB_MODE_LVDS;
4406 else
4407 dpll |= DPLLB_MODE_DAC_SERIAL;
4408 if (is_sdvo) {
4409 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4410 if (pixel_multiplier > 1) {
4411 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4412 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4413 }
4414 dpll |= DPLL_DVO_HIGH_SPEED;
4415 }
4416 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4417 dpll |= DPLL_DVO_HIGH_SPEED;
4418
4419 /* compute bitmask from p1 value */
4420 if (IS_PINEVIEW(dev))
4421 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4422 else {
4423 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4424 if (IS_G4X(dev) && reduced_clock)
4425 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4426 }
4427 switch (clock->p2) {
4428 case 5:
4429 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4430 break;
4431 case 7:
4432 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4433 break;
4434 case 10:
4435 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4436 break;
4437 case 14:
4438 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4439 break;
4440 }
4441 if (INTEL_INFO(dev)->gen >= 4)
4442 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4443
4444 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4445 dpll |= PLL_REF_INPUT_TVCLKINBC;
4446 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4447 /* XXX: just matching BIOS for now */
4448 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4449 dpll |= 3;
4450 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4451 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4452 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4453 else
4454 dpll |= PLL_REF_INPUT_DREFCLK;
4455
4456 dpll |= DPLL_VCO_ENABLE;
4457 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4458 POSTING_READ(DPLL(pipe));
4459 udelay(150);
4460
dafd226c
DV		 4461 for_each_encoder_on_crtc(dev, crtc, encoder)
4462 if (encoder->pre_pll_enable)
4463 encoder->pre_pll_enable(encoder);
eb1cbe48
DV		 4464
4465 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4466 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4467
4468 I915_WRITE(DPLL(pipe), dpll);
4469
4470 /* Wait for the clocks to stabilize. */
4471 POSTING_READ(DPLL(pipe));
4472 udelay(150);
4473
4474 if (INTEL_INFO(dev)->gen >= 4) {
4475 u32 temp = 0;
4476 if (is_sdvo) {
4477 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4478 if (temp > 1)
4479 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4480 else
4481 temp = 0;
4482 }
4483 I915_WRITE(DPLL_MD(pipe), temp);
4484 } else {
4485 /* The pixel multiplier can only be updated once the
4486 * DPLL is enabled and the clocks are stable.
4487 *
4488 * So write it again.
4489 */
4490 I915_WRITE(DPLL(pipe), dpll);
4491 }
4492}
4493
4494static void i8xx_update_pll(struct drm_crtc *crtc,
4495 struct drm_display_mode *adjusted_mode,
2a8f64ca 4496 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4497 int num_connectors)
4498{
4499 struct drm_device *dev = crtc->dev;
4500 struct drm_i915_private *dev_priv = dev->dev_private;
4501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4502 struct intel_encoder *encoder;
eb1cbe48
DV		 4503 int pipe = intel_crtc->pipe;
4504 u32 dpll;
4505
2a8f64ca
VP		 4506 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4507
eb1cbe48
DV		 4508 dpll = DPLL_VGA_MODE_DIS;
4509
4510 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4511 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4512 } else {
4513 if (clock->p1 == 2)
4514 dpll |= PLL_P1_DIVIDE_BY_TWO;
4515 else
4516 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4517 if (clock->p2 == 4)
4518 dpll |= PLL_P2_DIVIDE_BY_4;
4519 }
4520
83f377ab 4521 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4522 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4523 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4524 else
4525 dpll |= PLL_REF_INPUT_DREFCLK;
4526
4527 dpll |= DPLL_VCO_ENABLE;
4528 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4529 POSTING_READ(DPLL(pipe));
4530 udelay(150);
4531
dafd226c
DV		 4532 for_each_encoder_on_crtc(dev, crtc, encoder)
4533 if (encoder->pre_pll_enable)
4534 encoder->pre_pll_enable(encoder);
eb1cbe48 4535
5b5896e4
DV		 4536 I915_WRITE(DPLL(pipe), dpll);
4537
4538 /* Wait for the clocks to stabilize. */
4539 POSTING_READ(DPLL(pipe));
4540 udelay(150);
4541
eb1cbe48
DV		 4542 /* The pixel multiplier can only be updated once the
4543 * DPLL is enabled and the clocks are stable.
4544 *
4545 * So write it again.
4546 */
4547 I915_WRITE(DPLL(pipe), dpll);
4548}
4549
b0e77b9c
PZ		 4550static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4551 struct drm_display_mode *mode,
4552 struct drm_display_mode *adjusted_mode)
4553{
4554 struct drm_device *dev = intel_crtc->base.dev;
4555 struct drm_i915_private *dev_priv = dev->dev_private;
4556 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4557 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4558 uint32_t vsyncshift;
4559
4560 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4561 /* the chip adds 2 halflines automatically */
4562 adjusted_mode->crtc_vtotal -= 1;
4563 adjusted_mode->crtc_vblank_end -= 1;
4564 vsyncshift = adjusted_mode->crtc_hsync_start
4565 - adjusted_mode->crtc_htotal / 2;
4566 } else {
4567 vsyncshift = 0;
4568 }
4569
4570 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4571 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4572
fe2b8f9d 4573 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4574 (adjusted_mode->crtc_hdisplay - 1) |
4575 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4576 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4577 (adjusted_mode->crtc_hblank_start - 1) |
4578 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4579 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4580 (adjusted_mode->crtc_hsync_start - 1) |
4581 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4582
fe2b8f9d 4583 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4584 (adjusted_mode->crtc_vdisplay - 1) |
4585 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4586 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4587 (adjusted_mode->crtc_vblank_start - 1) |
4588 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4589 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4590 (adjusted_mode->crtc_vsync_start - 1) |
4591 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4592
b5e508d4
PZ		 4593 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4594 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4595 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4596 * bits. */
4597 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4598 (pipe == PIPE_B || pipe == PIPE_C))
4599 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4600
b0e77b9c
PZ		 4601 /* pipesrc controls the size that is scaled from, which should
4602 * always be the user's requested size.
4603 */
4604 I915_WRITE(PIPESRC(pipe),
4605 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4606}
4607
f564048e
EA		 4608static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4609 struct drm_display_mode *mode,
4610 struct drm_display_mode *adjusted_mode,
4611 int x, int y,
94352cf9 4612 struct drm_framebuffer *fb)
79e53945
JB		 4613{
4614 struct drm_device *dev = crtc->dev;
4615 struct drm_i915_private *dev_priv = dev->dev_private;
4616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4617 int pipe = intel_crtc->pipe;
80824003 4618 int plane = intel_crtc->plane;
c751ce4f 4619 int refclk, num_connectors = 0;
652c393a 4620 intel_clock_t clock, reduced_clock;
b0e77b9c 4621 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4622 bool ok, has_reduced_clock = false, is_sdvo = false;
4623 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4624 struct intel_encoder *encoder;
d4906093 4625 const intel_limit_t *limit;
5c3b82e2 4626 int ret;
79e53945 4627
6c2b7c12 4628 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4629 switch (encoder->type) {
79e53945
JB		 4630 case INTEL_OUTPUT_LVDS:
4631 is_lvds = true;
4632 break;
4633 case INTEL_OUTPUT_SDVO:
7d57382e 4634 case INTEL_OUTPUT_HDMI:
79e53945 4635 is_sdvo = true;
5eddb70b 4636 if (encoder->needs_tv_clock)
e2f0ba97 4637 is_tv = true;
79e53945 4638 break;
79e53945
JB		 4639 case INTEL_OUTPUT_TVOUT:
4640 is_tv = true;
4641 break;
a4fc5ed6
KP		 4642 case INTEL_OUTPUT_DISPLAYPORT:
4643 is_dp = true;
4644 break;
79e53945 4645 }
43565a06 4646
c751ce4f 4647 num_connectors++;
79e53945
JB		 4648 }
4649
c65d77d8 4650 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4651
d4906093
ML		 4652 /*
4653 * Returns a set of divisors for the desired target clock with the given
4654 * refclk, or FALSE. The returned values represent the clock equation:
4655 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4656 */
1b894b59 4657 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4658 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4659 &clock);
79e53945
JB		 4660 if (!ok) {
4661 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4662 return -EINVAL;
79e53945
JB		 4663 }
4664
cda4b7d3 4665 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4666 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4667
ddc9003c 4668 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4669 /*
4670 * Ensure we match the reduced clock's P to the target clock.
4671 * If the clocks don't match, we can't switch the display clock
4672 * by using the FP0/FP1. In such case we will disable the LVDS
4673 * downclock feature.
4674 */
ddc9003c 4675 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4676 dev_priv->lvds_downclock,
4677 refclk,
cec2f356 4678 &clock,
5eddb70b 4679 &reduced_clock);
7026d4ac
ZW		 4680 }
4681
c65d77d8
JB		 4682 if (is_sdvo && is_tv)
4683 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4684
eb1cbe48 4685 if (IS_GEN2(dev))
2a8f64ca
VP		 4686 i8xx_update_pll(crtc, adjusted_mode, &clock,
4687 has_reduced_clock ? &reduced_clock : NULL,
4688 num_connectors);
a0c4da24 4689 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4690 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4691 has_reduced_clock ? &reduced_clock : NULL,
4692 num_connectors);
79e53945 4693 else
eb1cbe48
DV		 4694 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4695 has_reduced_clock ? &reduced_clock : NULL,
4696 num_connectors);
79e53945
JB		 4697
4698 /* setup pipeconf */
5eddb70b 4699 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4700
4701 /* Set up the display plane register */
4702 dspcntr = DISPPLANE_GAMMA_ENABLE;
4703
929c77fb
EA		 4704 if (pipe == 0)
4705 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4706 else
4707 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4708
a6c45cf0 4709 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4710 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4711 * core speed.
4712 *
4713 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4714 * pipe == 0 check?
4715 */
e70236a8
JB		 4716 if (mode->clock >
4717 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4718 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4719 else
5eddb70b 4720 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4721 }
4722
3b5c78a3 4723 /* default to 8bpc */
dfd07d72 4724 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
3b5c78a3 4725 if (is_dp) {
0c96c65b 4726 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4727 pipeconf |= PIPECONF_6BPC |
3b5c78a3
AJ		 4728 PIPECONF_DITHER_EN |
4729 PIPECONF_DITHER_TYPE_SP;
4730 }
4731 }
4732
19c03924
GB		 4733 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4734 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4735 pipeconf |= PIPECONF_6BPC |
19c03924
GB		 4736 PIPECONF_ENABLE |
4737 I965_PIPECONF_ACTIVE;
4738 }
4739 }
4740
28c97730 4741 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4742 drm_mode_debug_printmodeline(mode);
4743
a7516a05
JB		 4744 if (HAS_PIPE_CXSR(dev)) {
4745 if (intel_crtc->lowfreq_avail) {
28c97730 4746 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4747 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4748 } else {
28c97730 4749 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4750 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4751 }
4752 }
4753
617cf884 4754 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4755 if (!IS_GEN2(dev) &&
b0e77b9c 4756 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4757 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4758 else
617cf884 4759 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4760
b0e77b9c 4761 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4762
4763 /* pipesrc and dspsize control the size that is scaled from,
4764 * which should always be the user's requested size.
79e53945 4765 */
929c77fb
EA		 4766 I915_WRITE(DSPSIZE(plane),
4767 ((mode->vdisplay - 1) << 16) |
4768 (mode->hdisplay - 1));
4769 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4770
f564048e
EA		 4771 I915_WRITE(PIPECONF(pipe), pipeconf);
4772 POSTING_READ(PIPECONF(pipe));
929c77fb 4773 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4774
4775 intel_wait_for_vblank(dev, pipe);
4776
f564048e
EA		 4777 I915_WRITE(DSPCNTR(plane), dspcntr);
4778 POSTING_READ(DSPCNTR(plane));
4779
94352cf9 4780 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4781
4782 intel_update_watermarks(dev);
4783
f564048e
EA		 4784 return ret;
4785}
4786
dde86e2d 4787static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4788{
4789 struct drm_i915_private *dev_priv = dev->dev_private;
4790 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4791 struct intel_encoder *encoder;
13d83a67
JB		 4792 u32 temp;
4793 bool has_lvds = false;
199e5d79
KP		 4794 bool has_cpu_edp = false;
4795 bool has_pch_edp = false;
4796 bool has_panel = false;
99eb6a01
KP		 4797 bool has_ck505 = false;
4798 bool can_ssc = false;
13d83a67
JB		 4799
4800 /* We need to take the global config into account */
199e5d79
KP		 4801 list_for_each_entry(encoder, &mode_config->encoder_list,
4802 base.head) {
4803 switch (encoder->type) {
4804 case INTEL_OUTPUT_LVDS:
4805 has_panel = true;
4806 has_lvds = true;
4807 break;
4808 case INTEL_OUTPUT_EDP:
4809 has_panel = true;
4810 if (intel_encoder_is_pch_edp(&encoder->base))
4811 has_pch_edp = true;
4812 else
4813 has_cpu_edp = true;
4814 break;
13d83a67
JB		 4815 }
4816 }
4817
99eb6a01
KP		 4818 if (HAS_PCH_IBX(dev)) {
4819 has_ck505 = dev_priv->display_clock_mode;
4820 can_ssc = has_ck505;
4821 } else {
4822 has_ck505 = false;
4823 can_ssc = true;
4824 }
4825
4826 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4827 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4828 has_ck505);
13d83a67
JB		 4829
4830 /* Ironlake: try to setup display ref clock before DPLL
4831 * enabling. This is only under driver's control after
4832 * PCH B stepping, previous chipset stepping should be
4833 * ignoring this setting.
4834 */
4835 temp = I915_READ(PCH_DREF_CONTROL);
4836 /* Always enable nonspread source */
4837 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4838
99eb6a01
KP		 4839 if (has_ck505)
4840 temp |= DREF_NONSPREAD_CK505_ENABLE;
4841 else
4842 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4843
199e5d79
KP		 4844 if (has_panel) {
4845 temp &= ~DREF_SSC_SOURCE_MASK;
4846 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4847
199e5d79 4848 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4849 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4850 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4851 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4852 } else
4853 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4854
4855 /* Get SSC going before enabling the outputs */
4856 I915_WRITE(PCH_DREF_CONTROL, temp);
4857 POSTING_READ(PCH_DREF_CONTROL);
4858 udelay(200);
4859
13d83a67
JB		 4860 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4861
4862 /* Enable CPU source on CPU attached eDP */
199e5d79 4863 if (has_cpu_edp) {
99eb6a01 4864 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4865 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4866 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4867 }
13d83a67
JB		 4868 else
4869 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4870 } else
4871 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4872
4873 I915_WRITE(PCH_DREF_CONTROL, temp);
4874 POSTING_READ(PCH_DREF_CONTROL);
4875 udelay(200);
4876 } else {
4877 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4878
4879 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4880
4881 /* Turn off CPU output */
4882 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4883
4884 I915_WRITE(PCH_DREF_CONTROL, temp);
4885 POSTING_READ(PCH_DREF_CONTROL);
4886 udelay(200);
4887
4888 /* Turn off the SSC source */
4889 temp &= ~DREF_SSC_SOURCE_MASK;
4890 temp |= DREF_SSC_SOURCE_DISABLE;
4891
4892 /* Turn off SSC1 */
4893 temp &= ~ DREF_SSC1_ENABLE;
4894
13d83a67
JB		 4895 I915_WRITE(PCH_DREF_CONTROL, temp);
4896 POSTING_READ(PCH_DREF_CONTROL);
4897 udelay(200);
4898 }
4899}
4900
dde86e2d
PZ		 4901/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4902static void lpt_init_pch_refclk(struct drm_device *dev)
4903{
4904 struct drm_i915_private *dev_priv = dev->dev_private;
4905 struct drm_mode_config *mode_config = &dev->mode_config;
4906 struct intel_encoder *encoder;
4907 bool has_vga = false;
4908 bool is_sdv = false;
4909 u32 tmp;
4910
4911 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4912 switch (encoder->type) {
4913 case INTEL_OUTPUT_ANALOG:
4914 has_vga = true;
4915 break;
4916 }
4917 }
4918
4919 if (!has_vga)
4920 return;
4921
c00db246
DV		 4922 mutex_lock(&dev_priv->dpio_lock);
4923
dde86e2d
PZ		 4924 /* XXX: Rip out SDV support once Haswell ships for real. */
4925 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4926 is_sdv = true;
4927
4928 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4929 tmp &= ~SBI_SSCCTL_DISABLE;
4930 tmp |= SBI_SSCCTL_PATHALT;
4931 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4932
4933 udelay(24);
4934
4935 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4936 tmp &= ~SBI_SSCCTL_PATHALT;
4937 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4938
4939 if (!is_sdv) {
4940 tmp = I915_READ(SOUTH_CHICKEN2);
4941 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4942 I915_WRITE(SOUTH_CHICKEN2, tmp);
4943
4944 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4945 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4946 DRM_ERROR("FDI mPHY reset assert timeout\n");
4947
4948 tmp = I915_READ(SOUTH_CHICKEN2);
4949 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4950 I915_WRITE(SOUTH_CHICKEN2, tmp);
4951
4952 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4953 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4954 100))
4955 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4956 }
4957
4958 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4959 tmp &= ~(0xFF << 24);
4960 tmp |= (0x12 << 24);
4961 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4962
4963 if (!is_sdv) {
4964 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4965 tmp &= ~(0x3 << 6);
4966 tmp |= (1 << 6) | (1 << 0);
4967 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4968 }
4969
4970 if (is_sdv) {
4971 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4972 tmp |= 0x7FFF;
4973 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4974 }
4975
4976 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4977 tmp |= (1 << 11);
4978 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4979
4980 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4981 tmp |= (1 << 11);
4982 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4983
4984 if (is_sdv) {
4985 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4986 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4987 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4988
4989 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4990 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4991 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4992
4993 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4994 tmp |= (0x3F << 8);
4995 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4996
4997 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4998 tmp |= (0x3F << 8);
4999 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5000 }
5001
5002 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5003 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5004 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5005
5006 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5007 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5008 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5009
5010 if (!is_sdv) {
5011 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5012 tmp &= ~(7 << 13);
5013 tmp |= (5 << 13);
5014 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5015
5016 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5017 tmp &= ~(7 << 13);
5018 tmp |= (5 << 13);
5019 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5020 }
5021
5022 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5023 tmp &= ~0xFF;
5024 tmp |= 0x1C;
5025 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5026
5027 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5028 tmp &= ~0xFF;
5029 tmp |= 0x1C;
5030 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5031
5032 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5033 tmp &= ~(0xFF << 16);
5034 tmp |= (0x1C << 16);
5035 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5036
5037 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5038 tmp &= ~(0xFF << 16);
5039 tmp |= (0x1C << 16);
5040 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5041
5042 if (!is_sdv) {
5043 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5044 tmp |= (1 << 27);
5045 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5046
5047 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5048 tmp |= (1 << 27);
5049 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5050
5051 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5052 tmp &= ~(0xF << 28);
5053 tmp |= (4 << 28);
5054 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5055
5056 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5057 tmp &= ~(0xF << 28);
5058 tmp |= (4 << 28);
5059 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5060 }
5061
5062 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5063 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5064 tmp |= SBI_DBUFF0_ENABLE;
5065 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5066
5067 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5068}
5069
5070/*
5071 * Initialize reference clocks when the driver loads
5072 */
5073void intel_init_pch_refclk(struct drm_device *dev)
5074{
5075 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5076 ironlake_init_pch_refclk(dev);
5077 else if (HAS_PCH_LPT(dev))
5078 lpt_init_pch_refclk(dev);
5079}
5080
d9d444cb
JB		 5081static int ironlake_get_refclk(struct drm_crtc *crtc)
5082{
5083 struct drm_device *dev = crtc->dev;
5084 struct drm_i915_private *dev_priv = dev->dev_private;
5085 struct intel_encoder *encoder;
d9d444cb
JB		 5086 struct intel_encoder *edp_encoder = NULL;
5087 int num_connectors = 0;
5088 bool is_lvds = false;
5089
6c2b7c12 5090 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5091 switch (encoder->type) {
5092 case INTEL_OUTPUT_LVDS:
5093 is_lvds = true;
5094 break;
5095 case INTEL_OUTPUT_EDP:
5096 edp_encoder = encoder;
5097 break;
5098 }
5099 num_connectors++;
5100 }
5101
5102 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5103 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5104 dev_priv->lvds_ssc_freq);
5105 return dev_priv->lvds_ssc_freq * 1000;
5106 }
5107
5108 return 120000;
5109}
5110
c8203565 5111static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5112 struct drm_display_mode *adjusted_mode,
c8203565 5113 bool dither)
79e53945 5114{
c8203565 5115 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5117 int pipe = intel_crtc->pipe;
c8203565
PZ		 5118 uint32_t val;
5119
5120 val = I915_READ(PIPECONF(pipe));
5121
dfd07d72 5122 val &= ~PIPECONF_BPC_MASK;
c8203565
PZ		 5123 switch (intel_crtc->bpp) {
5124 case 18:
dfd07d72 5125 val |= PIPECONF_6BPC;
c8203565
PZ		 5126 break;
5127 case 24:
dfd07d72 5128 val |= PIPECONF_8BPC;
c8203565
PZ		 5129 break;
5130 case 30:
dfd07d72 5131 val |= PIPECONF_10BPC;
c8203565
PZ		 5132 break;
5133 case 36:
dfd07d72 5134 val |= PIPECONF_12BPC;
c8203565
PZ		 5135 break;
5136 default:
cc769b62
PZ		 5137 /* Case prevented by intel_choose_pipe_bpp_dither. */
5138 BUG();
c8203565
PZ		 5139 }
5140
5141 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5142 if (dither)
5143 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5144
5145 val &= ~PIPECONF_INTERLACE_MASK;
5146 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5147 val |= PIPECONF_INTERLACED_ILK;
5148 else
5149 val |= PIPECONF_PROGRESSIVE;
5150
3685a8f3
VS		 5151 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5152 val |= PIPECONF_COLOR_RANGE_SELECT;
5153 else
5154 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5155
c8203565
PZ		 5156 I915_WRITE(PIPECONF(pipe), val);
5157 POSTING_READ(PIPECONF(pipe));
5158}
5159
86d3efce
VS		 5160/*
5161 * Set up the pipe CSC unit.
5162 *
5163 * Currently only full range RGB to limited range RGB conversion
5164 * is supported, but eventually this should handle various
5165 * RGB<->YCbCr scenarios as well.
5166 */
5167static void intel_set_pipe_csc(struct drm_crtc *crtc,
5168 const struct drm_display_mode *adjusted_mode)
5169{
5170 struct drm_device *dev = crtc->dev;
5171 struct drm_i915_private *dev_priv = dev->dev_private;
5172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5173 int pipe = intel_crtc->pipe;
5174 uint16_t coeff = 0x7800; /* 1.0 */
5175
5176 /*
5177 * TODO: Check what kind of values actually come out of the pipe
5178 * with these coeff/postoff values and adjust to get the best
5179 * accuracy. Perhaps we even need to take the bpc value into
5180 * consideration.
5181 */
5182
5183 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5184 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5185
5186 /*
5187 * GY/GU and RY/RU should be the other way around according
5188 * to BSpec, but reality doesn't agree. Just set them up in
5189 * a way that results in the correct picture.
5190 */
5191 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5192 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5193
5194 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5195 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5196
5197 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5198 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5199
5200 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5201 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5202 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5203
5204 if (INTEL_INFO(dev)->gen > 6) {
5205 uint16_t postoff = 0;
5206
5207 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5208 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5209
5210 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5211 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5212 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5213
5214 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5215 } else {
5216 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5217
5218 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5219 mode |= CSC_BLACK_SCREEN_OFFSET;
5220
5221 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5222 }
5223}
5224
ee2b0b38
PZ		 5225static void haswell_set_pipeconf(struct drm_crtc *crtc,
5226 struct drm_display_mode *adjusted_mode,
5227 bool dither)
5228{
5229 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5231 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5232 uint32_t val;
5233
702e7a56 5234 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5235
5236 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5237 if (dither)
5238 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5239
5240 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5241 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5242 val |= PIPECONF_INTERLACED_ILK;
5243 else
5244 val |= PIPECONF_PROGRESSIVE;
5245
702e7a56
PZ		 5246 I915_WRITE(PIPECONF(cpu_transcoder), val);
5247 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5248}
5249
6591c6e4
PZ		 5250static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5251 struct drm_display_mode *adjusted_mode,
5252 intel_clock_t *clock,
5253 bool *has_reduced_clock,
5254 intel_clock_t *reduced_clock)
5255{
5256 struct drm_device *dev = crtc->dev;
5257 struct drm_i915_private *dev_priv = dev->dev_private;
5258 struct intel_encoder *intel_encoder;
5259 int refclk;
d4906093 5260 const intel_limit_t *limit;
6591c6e4 5261 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5262
6591c6e4
PZ		 5263 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5264 switch (intel_encoder->type) {
79e53945
JB		 5265 case INTEL_OUTPUT_LVDS:
5266 is_lvds = true;
5267 break;
5268 case INTEL_OUTPUT_SDVO:
7d57382e 5269 case INTEL_OUTPUT_HDMI:
79e53945 5270 is_sdvo = true;
6591c6e4 5271 if (intel_encoder->needs_tv_clock)
e2f0ba97 5272 is_tv = true;
79e53945 5273 break;
79e53945
JB		 5274 case INTEL_OUTPUT_TVOUT:
5275 is_tv = true;
5276 break;
79e53945
JB		 5277 }
5278 }
5279
d9d444cb 5280 refclk = ironlake_get_refclk(crtc);
79e53945 5281
d4906093
ML		 5282 /*
5283 * Returns a set of divisors for the desired target clock with the given
5284 * refclk, or FALSE. The returned values represent the clock equation:
5285 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5286 */
1b894b59 5287 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5288 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5289 clock);
5290 if (!ret)
5291 return false;
cda4b7d3 5292
ddc9003c 5293 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5294 /*
5295 * Ensure we match the reduced clock's P to the target clock.
5296 * If the clocks don't match, we can't switch the display clock
5297 * by using the FP0/FP1. In such case we will disable the LVDS
5298 * downclock feature.
5299 */
6591c6e4
PZ		 5300 *has_reduced_clock = limit->find_pll(limit, crtc,
5301 dev_priv->lvds_downclock,
5302 refclk,
5303 clock,
5304 reduced_clock);
652c393a 5305 }
61e9653f
DV		 5306
5307 if (is_sdvo && is_tv)
6591c6e4
PZ		 5308 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5309
5310 return true;
5311}
5312
01a415fd
DV		 5313static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5314{
5315 struct drm_i915_private *dev_priv = dev->dev_private;
5316 uint32_t temp;
5317
5318 temp = I915_READ(SOUTH_CHICKEN1);
5319 if (temp & FDI_BC_BIFURCATION_SELECT)
5320 return;
5321
5322 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5323 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5324
5325 temp |= FDI_BC_BIFURCATION_SELECT;
5326 DRM_DEBUG_KMS("enabling fdi C rx\n");
5327 I915_WRITE(SOUTH_CHICKEN1, temp);
5328 POSTING_READ(SOUTH_CHICKEN1);
5329}
5330
5331static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5332{
5333 struct drm_device *dev = intel_crtc->base.dev;
5334 struct drm_i915_private *dev_priv = dev->dev_private;
5335 struct intel_crtc *pipe_B_crtc =
5336 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5337
5338 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5339 intel_crtc->pipe, intel_crtc->fdi_lanes);
5340 if (intel_crtc->fdi_lanes > 4) {
5341 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5342 intel_crtc->pipe, intel_crtc->fdi_lanes);
5343 /* Clamp lanes to avoid programming the hw with bogus values. */
5344 intel_crtc->fdi_lanes = 4;
5345
5346 return false;
5347 }
5348
5349 if (dev_priv->num_pipe == 2)
5350 return true;
5351
5352 switch (intel_crtc->pipe) {
5353 case PIPE_A:
5354 return true;
5355 case PIPE_B:
5356 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5357 intel_crtc->fdi_lanes > 2) {
5358 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5359 intel_crtc->pipe, intel_crtc->fdi_lanes);
5360 /* Clamp lanes to avoid programming the hw with bogus values. */
5361 intel_crtc->fdi_lanes = 2;
5362
5363 return false;
5364 }
5365
5366 if (intel_crtc->fdi_lanes > 2)
5367 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5368 else
5369 cpt_enable_fdi_bc_bifurcation(dev);
5370
5371 return true;
5372 case PIPE_C:
5373 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5374 if (intel_crtc->fdi_lanes > 2) {
5375 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5376 intel_crtc->pipe, intel_crtc->fdi_lanes);
5377 /* Clamp lanes to avoid programming the hw with bogus values. */
5378 intel_crtc->fdi_lanes = 2;
5379
5380 return false;
5381 }
5382 } else {
5383 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5384 return false;
5385 }
5386
5387 cpt_enable_fdi_bc_bifurcation(dev);
5388
5389 return true;
5390 default:
5391 BUG();
5392 }
5393}
5394
d4b1931c
PZ		 5395int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5396{
5397 /*
5398 * Account for spread spectrum to avoid
5399 * oversubscribing the link. Max center spread
5400 * is 2.5%; use 5% for safety's sake.
5401 */
5402 u32 bps = target_clock * bpp * 21 / 20;
5403 return bps / (link_bw * 8) + 1;
5404}
5405
f48d8f23
PZ		 5406static void ironlake_set_m_n(struct drm_crtc *crtc,
5407 struct drm_display_mode *mode,
5408 struct drm_display_mode *adjusted_mode)
79e53945
JB		 5409{
5410 struct drm_device *dev = crtc->dev;
5411 struct drm_i915_private *dev_priv = dev->dev_private;
5412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5413 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5414 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
e69d0bc1 5415 struct intel_link_m_n m_n = {0};
f48d8f23
PZ		 5416 int target_clock, pixel_multiplier, lane, link_bw;
5417 bool is_dp = false, is_cpu_edp = false;
79e53945 5418
f48d8f23
PZ		 5419 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5420 switch (intel_encoder->type) {
a4fc5ed6
KP		 5421 case INTEL_OUTPUT_DISPLAYPORT:
5422 is_dp = true;
5423 break;
32f9d658 5424 case INTEL_OUTPUT_EDP:
e3aef172 5425 is_dp = true;
f48d8f23 5426 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5427 is_cpu_edp = true;
f48d8f23 5428 edp_encoder = intel_encoder;
32f9d658 5429 break;
79e53945 5430 }
79e53945 5431 }
61e9653f 5432
2c07245f 5433 /* FDI link */
8febb297
EA		 5434 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5435 lane = 0;
5436 /* CPU eDP doesn't require FDI link, so just set DP M/N
5437 according to current link config */
e3aef172 5438 if (is_cpu_edp) {
e3aef172 5439 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5440 } else {
8febb297
EA		 5441 /* FDI is a binary signal running at ~2.7GHz, encoding
5442 * each output octet as 10 bits. The actual frequency
5443 * is stored as a divider into a 100MHz clock, and the
5444 * mode pixel clock is stored in units of 1KHz.
5445 * Hence the bw of each lane in terms of the mode signal
5446 * is:
5447 */
5448 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5449 }
58a27471 5450
94bf2ced
DV		 5451 /* [e]DP over FDI requires target mode clock instead of link clock. */
5452 if (edp_encoder)
5453 target_clock = intel_edp_target_clock(edp_encoder, mode);
5454 else if (is_dp)
5455 target_clock = mode->clock;
5456 else
5457 target_clock = adjusted_mode->clock;
5458
d4b1931c
PZ		 5459 if (!lane)
5460 lane = ironlake_get_lanes_required(target_clock, link_bw,
5461 intel_crtc->bpp);
2c07245f 5462
8febb297
EA		 5463 intel_crtc->fdi_lanes = lane;
5464
5465 if (pixel_multiplier > 1)
5466 link_bw *= pixel_multiplier;
e69d0bc1 5467 intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
8febb297 5468
afe2fcf5
PZ		 5469 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5470 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5471 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5472 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5473}
5474
de13a2e3
PZ		 5475static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5476 struct drm_display_mode *adjusted_mode,
5477 intel_clock_t *clock, u32 fp)
79e53945 5478{
de13a2e3 5479 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5480 struct drm_device *dev = crtc->dev;
5481 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5482 struct intel_encoder *intel_encoder;
5483 uint32_t dpll;
5484 int factor, pixel_multiplier, num_connectors = 0;
5485 bool is_lvds = false, is_sdvo = false, is_tv = false;
5486 bool is_dp = false, is_cpu_edp = false;
79e53945 5487
de13a2e3
PZ		 5488 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5489 switch (intel_encoder->type) {
79e53945
JB		 5490 case INTEL_OUTPUT_LVDS:
5491 is_lvds = true;
5492 break;
5493 case INTEL_OUTPUT_SDVO:
7d57382e 5494 case INTEL_OUTPUT_HDMI:
79e53945 5495 is_sdvo = true;
de13a2e3 5496 if (intel_encoder->needs_tv_clock)
e2f0ba97 5497 is_tv = true;
79e53945 5498 break;
79e53945
JB		 5499 case INTEL_OUTPUT_TVOUT:
5500 is_tv = true;
5501 break;
a4fc5ed6
KP		 5502 case INTEL_OUTPUT_DISPLAYPORT:
5503 is_dp = true;
5504 break;
32f9d658 5505 case INTEL_OUTPUT_EDP:
e3aef172 5506 is_dp = true;
de13a2e3 5507 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5508 is_cpu_edp = true;
32f9d658 5509 break;
79e53945 5510 }
43565a06 5511
c751ce4f 5512 num_connectors++;
79e53945 5513 }
79e53945 5514
c1858123 5515 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5516 factor = 21;
5517 if (is_lvds) {
5518 if ((intel_panel_use_ssc(dev_priv) &&
5519 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5520 intel_is_dual_link_lvds(dev))
8febb297
EA		 5521 factor = 25;
5522 } else if (is_sdvo && is_tv)
5523 factor = 20;
c1858123 5524
de13a2e3 5525 if (clock->m < factor * clock->n)
8febb297 5526 fp |= FP_CB_TUNE;
2c07245f 5527
5eddb70b 5528 dpll = 0;
2c07245f 5529
a07d6787
EA		 5530 if (is_lvds)
5531 dpll |= DPLLB_MODE_LVDS;
5532 else
5533 dpll |= DPLLB_MODE_DAC_SERIAL;
5534 if (is_sdvo) {
de13a2e3 5535 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5536 if (pixel_multiplier > 1) {
5537 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5538 }
a07d6787
EA		 5539 dpll |= DPLL_DVO_HIGH_SPEED;
5540 }
e3aef172 5541 if (is_dp && !is_cpu_edp)
a07d6787 5542 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5543
a07d6787 5544 /* compute bitmask from p1 value */
de13a2e3 5545 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5546 /* also FPA1 */
de13a2e3 5547 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5548
de13a2e3 5549 switch (clock->p2) {
a07d6787
EA		 5550 case 5:
5551 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5552 break;
5553 case 7:
5554 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5555 break;
5556 case 10:
5557 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5558 break;
5559 case 14:
5560 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5561 break;
79e53945
JB		 5562 }
5563
43565a06
KH		 5564 if (is_sdvo && is_tv)
5565 dpll |= PLL_REF_INPUT_TVCLKINBC;
5566 else if (is_tv)
79e53945 5567 /* XXX: just matching BIOS for now */
43565a06 5568 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5569 dpll |= 3;
a7615030 5570 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5571 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5572 else
5573 dpll |= PLL_REF_INPUT_DREFCLK;
5574
de13a2e3
PZ		 5575 return dpll;
5576}
5577
5578static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5579 struct drm_display_mode *mode,
5580 struct drm_display_mode *adjusted_mode,
5581 int x, int y,
5582 struct drm_framebuffer *fb)
5583{
5584 struct drm_device *dev = crtc->dev;
5585 struct drm_i915_private *dev_priv = dev->dev_private;
5586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5587 int pipe = intel_crtc->pipe;
5588 int plane = intel_crtc->plane;
5589 int num_connectors = 0;
5590 intel_clock_t clock, reduced_clock;
5591 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5592 bool ok, has_reduced_clock = false;
5593 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5594 struct intel_encoder *encoder;
de13a2e3 5595 int ret;
01a415fd 5596 bool dither, fdi_config_ok;
de13a2e3
PZ		 5597
5598 for_each_encoder_on_crtc(dev, crtc, encoder) {
5599 switch (encoder->type) {
5600 case INTEL_OUTPUT_LVDS:
5601 is_lvds = true;
5602 break;
de13a2e3
PZ		 5603 case INTEL_OUTPUT_DISPLAYPORT:
5604 is_dp = true;
5605 break;
5606 case INTEL_OUTPUT_EDP:
5607 is_dp = true;
e2f12b07 5608 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5609 is_cpu_edp = true;
5610 break;
5611 }
5612
5613 num_connectors++;
a07d6787 5614 }
79e53945 5615
5dc5298b
PZ		 5616 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5617 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5618
de13a2e3
PZ		 5619 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5620 &has_reduced_clock, &reduced_clock);
5621 if (!ok) {
5622 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5623 return -EINVAL;
79e53945
JB		 5624 }
5625
de13a2e3
PZ		 5626 /* Ensure that the cursor is valid for the new mode before changing... */
5627 intel_crtc_update_cursor(crtc, true);
5628
5629 /* determine panel color depth */
c8241969
JN		 5630 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5631 adjusted_mode);
de13a2e3
PZ		 5632 if (is_lvds && dev_priv->lvds_dither)
5633 dither = true;
5634
5635 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5636 if (has_reduced_clock)
5637 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5638 reduced_clock.m2;
5639
5640 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
79e53945 5641
f7cb34d4 5642 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5643 drm_mode_debug_printmodeline(mode);
5644
5dc5298b
PZ		 5645 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5646 if (!is_cpu_edp) {
ee7b9f93 5647 struct intel_pch_pll *pll;
4b645f14 5648
ee7b9f93
JB		 5649 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5650 if (pll == NULL) {
5651 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5652 pipe);
4b645f14
JB		 5653 return -EINVAL;
5654 }
ee7b9f93
JB		 5655 } else
5656 intel_put_pch_pll(intel_crtc);
79e53945 5657
2f0c2ad1 5658 if (is_dp && !is_cpu_edp)
a4fc5ed6 5659 intel_dp_set_m_n(crtc, mode, adjusted_mode);
79e53945 5660
dafd226c
DV		 5661 for_each_encoder_on_crtc(dev, crtc, encoder)
5662 if (encoder->pre_pll_enable)
5663 encoder->pre_pll_enable(encoder);
79e53945 5664
ee7b9f93
JB		 5665 if (intel_crtc->pch_pll) {
5666 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5667
32f9d658 5668 /* Wait for the clocks to stabilize. */
ee7b9f93 5669 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5670 udelay(150);
5671
8febb297
EA		 5672 /* The pixel multiplier can only be updated once the
5673 * DPLL is enabled and the clocks are stable.
5674 *
5675 * So write it again.
5676 */
ee7b9f93 5677 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5678 }
79e53945 5679
5eddb70b 5680 intel_crtc->lowfreq_avail = false;
ee7b9f93 5681 if (intel_crtc->pch_pll) {
4b645f14 5682 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5683 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5684 intel_crtc->lowfreq_avail = true;
4b645f14 5685 } else {
ee7b9f93 5686 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5687 }
5688 }
5689
b0e77b9c 5690 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5691
01a415fd
DV		 5692 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5693 * ironlake_check_fdi_lanes. */
f48d8f23 5694 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5695
01a415fd 5696 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5697
c8203565 5698 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5699
9d0498a2 5700 intel_wait_for_vblank(dev, pipe);
79e53945 5701
a1f9e77e
PZ		 5702 /* Set up the display plane register */
5703 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5704 POSTING_READ(DSPCNTR(plane));
79e53945 5705
94352cf9 5706 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5707
5708 intel_update_watermarks(dev);
5709
1f8eeabf
ED		 5710 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5711
01a415fd 5712 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5713}
5714
d6dd9eb1
DV		 5715static void haswell_modeset_global_resources(struct drm_device *dev)
5716{
5717 struct drm_i915_private *dev_priv = dev->dev_private;
5718 bool enable = false;
5719 struct intel_crtc *crtc;
5720 struct intel_encoder *encoder;
5721
5722 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5723 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5724 enable = true;
5725 /* XXX: Should check for edp transcoder here, but thanks to init
5726 * sequence that's not yet available. Just in case desktop eDP
5727 * on PORT D is possible on haswell, too. */
5728 }
5729
5730 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5731 base.head) {
5732 if (encoder->type != INTEL_OUTPUT_EDP &&
5733 encoder->connectors_active)
5734 enable = true;
5735 }
5736
5737 /* Even the eDP panel fitter is outside the always-on well. */
5738 if (dev_priv->pch_pf_size)
5739 enable = true;
5740
5741 intel_set_power_well(dev, enable);
5742}
5743
09b4ddf9
PZ		 5744static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5745 struct drm_display_mode *mode,
5746 struct drm_display_mode *adjusted_mode,
5747 int x, int y,
5748 struct drm_framebuffer *fb)
5749{
5750 struct drm_device *dev = crtc->dev;
5751 struct drm_i915_private *dev_priv = dev->dev_private;
5752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5753 int pipe = intel_crtc->pipe;
5754 int plane = intel_crtc->plane;
5755 int num_connectors = 0;
ed7ef439 5756 bool is_dp = false, is_cpu_edp = false;
09b4ddf9 5757 struct intel_encoder *encoder;
09b4ddf9
PZ		 5758 int ret;
5759 bool dither;
5760
5761 for_each_encoder_on_crtc(dev, crtc, encoder) {
5762 switch (encoder->type) {
09b4ddf9
PZ		 5763 case INTEL_OUTPUT_DISPLAYPORT:
5764 is_dp = true;
5765 break;
5766 case INTEL_OUTPUT_EDP:
5767 is_dp = true;
5768 if (!intel_encoder_is_pch_edp(&encoder->base))
5769 is_cpu_edp = true;
5770 break;
5771 }
5772
5773 num_connectors++;
5774 }
5775
5dc5298b
PZ		 5776 /* We are not sure yet this won't happen. */
5777 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5778 INTEL_PCH_TYPE(dev));
5779
5780 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5781 num_connectors, pipe_name(pipe));
5782
702e7a56 5783 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5784 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5785
5786 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5787
6441ab5f
PZ		 5788 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5789 return -EINVAL;
5790
09b4ddf9
PZ		 5791 /* Ensure that the cursor is valid for the new mode before changing... */
5792 intel_crtc_update_cursor(crtc, true);
5793
5794 /* determine panel color depth */
c8241969
JN		 5795 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5796 adjusted_mode);
09b4ddf9 5797
09b4ddf9
PZ		 5798 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5799 drm_mode_debug_printmodeline(mode);
5800
ed7ef439 5801 if (is_dp && !is_cpu_edp)
09b4ddf9 5802 intel_dp_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9
PZ		 5803
5804 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5805
5806 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5807
1eb8dfec
PZ		 5808 if (!is_dp || is_cpu_edp)
5809 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5810
ee2b0b38 5811 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5812
86d3efce
VS		 5813 intel_set_pipe_csc(crtc, adjusted_mode);
5814
09b4ddf9 5815 /* Set up the display plane register */
86d3efce 5816 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5817 POSTING_READ(DSPCNTR(plane));
5818
5819 ret = intel_pipe_set_base(crtc, x, y, fb);
5820
5821 intel_update_watermarks(dev);
5822
5823 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5824
1f803ee5 5825 return ret;
79e53945
JB		 5826}
5827
f564048e
EA		 5828static int intel_crtc_mode_set(struct drm_crtc *crtc,
5829 struct drm_display_mode *mode,
5830 struct drm_display_mode *adjusted_mode,
5831 int x, int y,
94352cf9 5832 struct drm_framebuffer *fb)
f564048e
EA		 5833{
5834 struct drm_device *dev = crtc->dev;
5835 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5836 struct drm_encoder_helper_funcs *encoder_funcs;
5837 struct intel_encoder *encoder;
0b701d27
EA		 5838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5839 int pipe = intel_crtc->pipe;
f564048e
EA		 5840 int ret;
5841
cc464b2a
PZ		 5842 if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5843 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5844 else
5845 intel_crtc->cpu_transcoder = pipe;
5846
0b701d27 5847 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5848
f564048e 5849 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5850 x, y, fb);
79e53945 5851 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5852
9256aa19
DV		 5853 if (ret != 0)
5854 return ret;
5855
5856 for_each_encoder_on_crtc(dev, crtc, encoder) {
5857 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5858 encoder->base.base.id,
5859 drm_get_encoder_name(&encoder->base),
5860 mode->base.id, mode->name);
5861 encoder_funcs = encoder->base.helper_private;
5862 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5863 }
5864
5865 return 0;
79e53945
JB		 5866}
5867
3a9627f4
WF		 5868static bool intel_eld_uptodate(struct drm_connector *connector,
5869 int reg_eldv, uint32_t bits_eldv,
5870 int reg_elda, uint32_t bits_elda,
5871 int reg_edid)
5872{
5873 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5874 uint8_t *eld = connector->eld;
5875 uint32_t i;
5876
5877 i = I915_READ(reg_eldv);
5878 i &= bits_eldv;
5879
5880 if (!eld[0])
5881 return !i;
5882
5883 if (!i)
5884 return false;
5885
5886 i = I915_READ(reg_elda);
5887 i &= ~bits_elda;
5888 I915_WRITE(reg_elda, i);
5889
5890 for (i = 0; i < eld[2]; i++)
5891 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5892 return false;
5893
5894 return true;
5895}
5896
e0dac65e
WF		 5897static void g4x_write_eld(struct drm_connector *connector,
5898 struct drm_crtc *crtc)
5899{
5900 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5901 uint8_t *eld = connector->eld;
5902 uint32_t eldv;
5903 uint32_t len;
5904 uint32_t i;
5905
5906 i = I915_READ(G4X_AUD_VID_DID);
5907
5908 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5909 eldv = G4X_ELDV_DEVCL_DEVBLC;
5910 else
5911 eldv = G4X_ELDV_DEVCTG;
5912
3a9627f4
WF		 5913 if (intel_eld_uptodate(connector,
5914 G4X_AUD_CNTL_ST, eldv,
5915 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5916 G4X_HDMIW_HDMIEDID))
5917 return;
5918
e0dac65e
WF		 5919 i = I915_READ(G4X_AUD_CNTL_ST);
5920 i &= ~(eldv | G4X_ELD_ADDR);
5921 len = (i >> 9) & 0x1f; /* ELD buffer size */
5922 I915_WRITE(G4X_AUD_CNTL_ST, i);
5923
5924 if (!eld[0])
5925 return;
5926
5927 len = min_t(uint8_t, eld[2], len);
5928 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5929 for (i = 0; i < len; i++)
5930 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5931
5932 i = I915_READ(G4X_AUD_CNTL_ST);
5933 i |= eldv;
5934 I915_WRITE(G4X_AUD_CNTL_ST, i);
5935}
5936
83358c85
WX		 5937static void haswell_write_eld(struct drm_connector *connector,
5938 struct drm_crtc *crtc)
5939{
5940 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5941 uint8_t *eld = connector->eld;
5942 struct drm_device *dev = crtc->dev;
7b9f35a6 5943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 5944 uint32_t eldv;
5945 uint32_t i;
5946 int len;
5947 int pipe = to_intel_crtc(crtc)->pipe;
5948 int tmp;
5949
5950 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5951 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5952 int aud_config = HSW_AUD_CFG(pipe);
5953 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5954
5955
5956 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5957
5958 /* Audio output enable */
5959 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5960 tmp = I915_READ(aud_cntrl_st2);
5961 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5962 I915_WRITE(aud_cntrl_st2, tmp);
5963
5964 /* Wait for 1 vertical blank */
5965 intel_wait_for_vblank(dev, pipe);
5966
5967 /* Set ELD valid state */
5968 tmp = I915_READ(aud_cntrl_st2);
5969 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5970 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5971 I915_WRITE(aud_cntrl_st2, tmp);
5972 tmp = I915_READ(aud_cntrl_st2);
5973 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5974
5975 /* Enable HDMI mode */
5976 tmp = I915_READ(aud_config);
5977 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5978 /* clear N_programing_enable and N_value_index */
5979 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5980 I915_WRITE(aud_config, tmp);
5981
5982 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5983
5984 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 5985 intel_crtc->eld_vld = true;
83358c85
WX		 5986
5987 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5988 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5989 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5990 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5991 } else
5992 I915_WRITE(aud_config, 0);
5993
5994 if (intel_eld_uptodate(connector,
5995 aud_cntrl_st2, eldv,
5996 aud_cntl_st, IBX_ELD_ADDRESS,
5997 hdmiw_hdmiedid))
5998 return;
5999
6000 i = I915_READ(aud_cntrl_st2);
6001 i &= ~eldv;
6002 I915_WRITE(aud_cntrl_st2, i);
6003
6004 if (!eld[0])
6005 return;
6006
6007 i = I915_READ(aud_cntl_st);
6008 i &= ~IBX_ELD_ADDRESS;
6009 I915_WRITE(aud_cntl_st, i);
6010 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6011 DRM_DEBUG_DRIVER("port num:%d\n", i);
6012
6013 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6014 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6015 for (i = 0; i < len; i++)
6016 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6017
6018 i = I915_READ(aud_cntrl_st2);
6019 i |= eldv;
6020 I915_WRITE(aud_cntrl_st2, i);
6021
6022}
6023
e0dac65e
WF		 6024static void ironlake_write_eld(struct drm_connector *connector,
6025 struct drm_crtc *crtc)
6026{
6027 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6028 uint8_t *eld = connector->eld;
6029 uint32_t eldv;
6030 uint32_t i;
6031 int len;
6032 int hdmiw_hdmiedid;
b6daa025 6033 int aud_config;
e0dac65e
WF		 6034 int aud_cntl_st;
6035 int aud_cntrl_st2;
9b138a83 6036 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6037
b3f33cbf 6038 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6039 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6040 aud_config = IBX_AUD_CFG(pipe);
6041 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6042 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6043 } else {
9b138a83
WX		 6044 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6045 aud_config = CPT_AUD_CFG(pipe);
6046 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6047 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6048 }
6049
9b138a83 6050 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6051
6052 i = I915_READ(aud_cntl_st);
9b138a83 6053 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6054 if (!i) {
6055 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6056 /* operate blindly on all ports */
1202b4c6
WF		 6057 eldv = IBX_ELD_VALIDB;
6058 eldv |= IBX_ELD_VALIDB << 4;
6059 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6060 } else {
6061 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6062 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6063 }
6064
3a9627f4
WF		 6065 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6066 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6067 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6068 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6069 } else
6070 I915_WRITE(aud_config, 0);
e0dac65e 6071
3a9627f4
WF		 6072 if (intel_eld_uptodate(connector,
6073 aud_cntrl_st2, eldv,
6074 aud_cntl_st, IBX_ELD_ADDRESS,
6075 hdmiw_hdmiedid))
6076 return;
6077
e0dac65e
WF		 6078 i = I915_READ(aud_cntrl_st2);
6079 i &= ~eldv;
6080 I915_WRITE(aud_cntrl_st2, i);
6081
6082 if (!eld[0])
6083 return;
6084
e0dac65e 6085 i = I915_READ(aud_cntl_st);
1202b4c6 6086 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6087 I915_WRITE(aud_cntl_st, i);
6088
6089 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6090 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6091 for (i = 0; i < len; i++)
6092 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6093
6094 i = I915_READ(aud_cntrl_st2);
6095 i |= eldv;
6096 I915_WRITE(aud_cntrl_st2, i);
6097}
6098
6099void intel_write_eld(struct drm_encoder *encoder,
6100 struct drm_display_mode *mode)
6101{
6102 struct drm_crtc *crtc = encoder->crtc;
6103 struct drm_connector *connector;
6104 struct drm_device *dev = encoder->dev;
6105 struct drm_i915_private *dev_priv = dev->dev_private;
6106
6107 connector = drm_select_eld(encoder, mode);
6108 if (!connector)
6109 return;
6110
6111 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6112 connector->base.id,
6113 drm_get_connector_name(connector),
6114 connector->encoder->base.id,
6115 drm_get_encoder_name(connector->encoder));
6116
6117 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6118
6119 if (dev_priv->display.write_eld)
6120 dev_priv->display.write_eld(connector, crtc);
6121}
6122
79e53945
JB		 6123/** Loads the palette/gamma unit for the CRTC with the prepared values */
6124void intel_crtc_load_lut(struct drm_crtc *crtc)
6125{
6126 struct drm_device *dev = crtc->dev;
6127 struct drm_i915_private *dev_priv = dev->dev_private;
6128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6129 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6130 int i;
6131
6132 /* The clocks have to be on to load the palette. */
aed3f09d 6133 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6134 return;
6135
f2b115e6 6136 /* use legacy palette for Ironlake */
bad720ff 6137 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6138 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6139
79e53945
JB		 6140 for (i = 0; i < 256; i++) {
6141 I915_WRITE(palreg + 4 * i,
6142 (intel_crtc->lut_r[i] << 16) |
6143 (intel_crtc->lut_g[i] << 8) |
6144 intel_crtc->lut_b[i]);
6145 }
6146}
6147
560b85bb
CW		 6148static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6149{
6150 struct drm_device *dev = crtc->dev;
6151 struct drm_i915_private *dev_priv = dev->dev_private;
6152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6153 bool visible = base != 0;
6154 u32 cntl;
6155
6156 if (intel_crtc->cursor_visible == visible)
6157 return;
6158
9db4a9c7 6159 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6160 if (visible) {
6161 /* On these chipsets we can only modify the base whilst
6162 * the cursor is disabled.
6163 */
9db4a9c7 6164 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6165
6166 cntl &= ~(CURSOR_FORMAT_MASK);
6167 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6168 cntl |= CURSOR_ENABLE |
6169 CURSOR_GAMMA_ENABLE |
6170 CURSOR_FORMAT_ARGB;
6171 } else
6172 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6173 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6174
6175 intel_crtc->cursor_visible = visible;
6176}
6177
6178static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6179{
6180 struct drm_device *dev = crtc->dev;
6181 struct drm_i915_private *dev_priv = dev->dev_private;
6182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6183 int pipe = intel_crtc->pipe;
6184 bool visible = base != 0;
6185
6186 if (intel_crtc->cursor_visible != visible) {
548f245b 6187 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6188 if (base) {
6189 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6190 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6191 cntl |= pipe << 28; /* Connect to correct pipe */
6192 } else {
6193 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6194 cntl |= CURSOR_MODE_DISABLE;
6195 }
9db4a9c7 6196 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6197
6198 intel_crtc->cursor_visible = visible;
6199 }
6200 /* and commit changes on next vblank */
9db4a9c7 6201 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6202}
6203
65a21cd6
JB		 6204static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6205{
6206 struct drm_device *dev = crtc->dev;
6207 struct drm_i915_private *dev_priv = dev->dev_private;
6208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6209 int pipe = intel_crtc->pipe;
6210 bool visible = base != 0;
6211
6212 if (intel_crtc->cursor_visible != visible) {
6213 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6214 if (base) {
6215 cntl &= ~CURSOR_MODE;
6216 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6217 } else {
6218 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6219 cntl |= CURSOR_MODE_DISABLE;
6220 }
86d3efce
VS		 6221 if (IS_HASWELL(dev))
6222 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6223 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6224
6225 intel_crtc->cursor_visible = visible;
6226 }
6227 /* and commit changes on next vblank */
6228 I915_WRITE(CURBASE_IVB(pipe), base);
6229}
6230
cda4b7d3 6231/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6232static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6233 bool on)
cda4b7d3
CW		 6234{
6235 struct drm_device *dev = crtc->dev;
6236 struct drm_i915_private *dev_priv = dev->dev_private;
6237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6238 int pipe = intel_crtc->pipe;
6239 int x = intel_crtc->cursor_x;
6240 int y = intel_crtc->cursor_y;
560b85bb 6241 u32 base, pos;
cda4b7d3
CW		 6242 bool visible;
6243
6244 pos = 0;
6245
6b383a7f 6246 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6247 base = intel_crtc->cursor_addr;
6248 if (x > (int) crtc->fb->width)
6249 base = 0;
6250
6251 if (y > (int) crtc->fb->height)
6252 base = 0;
6253 } else
6254 base = 0;
6255
6256 if (x < 0) {
6257 if (x + intel_crtc->cursor_width < 0)
6258 base = 0;
6259
6260 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6261 x = -x;
6262 }
6263 pos |= x << CURSOR_X_SHIFT;
6264
6265 if (y < 0) {
6266 if (y + intel_crtc->cursor_height < 0)
6267 base = 0;
6268
6269 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6270 y = -y;
6271 }
6272 pos |= y << CURSOR_Y_SHIFT;
6273
6274 visible = base != 0;
560b85bb 6275 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6276 return;
6277
0cd83aa9 6278 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6279 I915_WRITE(CURPOS_IVB(pipe), pos);
6280 ivb_update_cursor(crtc, base);
6281 } else {
6282 I915_WRITE(CURPOS(pipe), pos);
6283 if (IS_845G(dev) || IS_I865G(dev))
6284 i845_update_cursor(crtc, base);
6285 else
6286 i9xx_update_cursor(crtc, base);
6287 }
cda4b7d3
CW		 6288}
6289
79e53945 6290static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6291 struct drm_file *file,
79e53945
JB		 6292 uint32_t handle,
6293 uint32_t width, uint32_t height)
6294{
6295 struct drm_device *dev = crtc->dev;
6296 struct drm_i915_private *dev_priv = dev->dev_private;
6297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6298 struct drm_i915_gem_object *obj;
cda4b7d3 6299 uint32_t addr;
3f8bc370 6300 int ret;
79e53945 6301
79e53945
JB		 6302 /* if we want to turn off the cursor ignore width and height */
6303 if (!handle) {
28c97730 6304 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6305 addr = 0;
05394f39 6306 obj = NULL;
5004417d 6307 mutex_lock(&dev->struct_mutex);
3f8bc370 6308 goto finish;
79e53945
JB		 6309 }
6310
6311 /* Currently we only support 64x64 cursors */
6312 if (width != 64 || height != 64) {
6313 DRM_ERROR("we currently only support 64x64 cursors\n");
6314 return -EINVAL;
6315 }
6316
05394f39 6317 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6318 if (&obj->base == NULL)
79e53945
JB		 6319 return -ENOENT;
6320
05394f39 6321 if (obj->base.size < width * height * 4) {
79e53945 6322 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6323 ret = -ENOMEM;
6324 goto fail;
79e53945
JB		 6325 }
6326
71acb5eb 6327 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6328 mutex_lock(&dev->struct_mutex);
b295d1b6 6329 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6330 if (obj->tiling_mode) {
6331 DRM_ERROR("cursor cannot be tiled\n");
6332 ret = -EINVAL;
6333 goto fail_locked;
6334 }
6335
2da3b9b9 6336 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6337 if (ret) {
6338 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6339 goto fail_locked;
e7b526bb
CW		 6340 }
6341
d9e86c0e
CW		 6342 ret = i915_gem_object_put_fence(obj);
6343 if (ret) {
2da3b9b9 6344 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6345 goto fail_unpin;
6346 }
6347
05394f39 6348 addr = obj->gtt_offset;
71acb5eb 6349 } else {
6eeefaf3 6350 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6351 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6352 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6353 align);
71acb5eb
DA		 6354 if (ret) {
6355 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6356 goto fail_locked;
71acb5eb 6357 }
05394f39 6358 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6359 }
6360
a6c45cf0 6361 if (IS_GEN2(dev))
14b60391
JB		 6362 I915_WRITE(CURSIZE, (height << 12) | width);
6363
3f8bc370 6364 finish:
3f8bc370 6365 if (intel_crtc->cursor_bo) {
b295d1b6 6366 if (dev_priv->info->cursor_needs_physical) {
05394f39 6367 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6368 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6369 } else
6370 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6371 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6372 }
80824003 6373
7f9872e0 6374 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6375
6376 intel_crtc->cursor_addr = addr;
05394f39 6377 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6378 intel_crtc->cursor_width = width;
6379 intel_crtc->cursor_height = height;
6380
6b383a7f 6381 intel_crtc_update_cursor(crtc, true);
3f8bc370 6382
79e53945 6383 return 0;
e7b526bb 6384fail_unpin:
05394f39 6385 i915_gem_object_unpin(obj);
7f9872e0 6386fail_locked:
34b8686e 6387 mutex_unlock(&dev->struct_mutex);
bc9025bd 6388fail:
05394f39 6389 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6390 return ret;
79e53945
JB		 6391}
6392
6393static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6394{
79e53945 6395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6396
cda4b7d3
CW		 6397 intel_crtc->cursor_x = x;
6398 intel_crtc->cursor_y = y;
652c393a 6399
6b383a7f 6400 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6401
6402 return 0;
6403}
6404
6405/** Sets the color ramps on behalf of RandR */
6406void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6407 u16 blue, int regno)
6408{
6409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6410
6411 intel_crtc->lut_r[regno] = red >> 8;
6412 intel_crtc->lut_g[regno] = green >> 8;
6413 intel_crtc->lut_b[regno] = blue >> 8;
6414}
6415
b8c00ac5
DA		 6416void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6417 u16 *blue, int regno)
6418{
6419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6420
6421 *red = intel_crtc->lut_r[regno] << 8;
6422 *green = intel_crtc->lut_g[regno] << 8;
6423 *blue = intel_crtc->lut_b[regno] << 8;
6424}
6425
79e53945 6426static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6427 u16 *blue, uint32_t start, uint32_t size)
79e53945 6428{
7203425a 6429 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6431
7203425a 6432 for (i = start; i < end; i++) {
79e53945
JB		 6433 intel_crtc->lut_r[i] = red[i] >> 8;
6434 intel_crtc->lut_g[i] = green[i] >> 8;
6435 intel_crtc->lut_b[i] = blue[i] >> 8;
6436 }
6437
6438 intel_crtc_load_lut(crtc);
6439}
6440
6441/**
6442 * Get a pipe with a simple mode set on it for doing load-based monitor
6443 * detection.
6444 *
6445 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6446 * its requirements. The pipe will be connected to no other encoders.
79e53945 6447 *
c751ce4f 6448 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6449 * configured for it. In the future, it could choose to temporarily disable
6450 * some outputs to free up a pipe for its use.
6451 *
6452 * \return crtc, or NULL if no pipes are available.
6453 */
6454
6455/* VESA 640x480x72Hz mode to set on the pipe */
6456static struct drm_display_mode load_detect_mode = {
6457 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6458 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6459};
6460
d2dff872
CW		 6461static struct drm_framebuffer *
6462intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6463 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6464 struct drm_i915_gem_object *obj)
6465{
6466 struct intel_framebuffer *intel_fb;
6467 int ret;
6468
6469 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6470 if (!intel_fb) {
6471 drm_gem_object_unreference_unlocked(&obj->base);
6472 return ERR_PTR(-ENOMEM);
6473 }
6474
6475 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6476 if (ret) {
6477 drm_gem_object_unreference_unlocked(&obj->base);
6478 kfree(intel_fb);
6479 return ERR_PTR(ret);
6480 }
6481
6482 return &intel_fb->base;
6483}
6484
6485static u32
6486intel_framebuffer_pitch_for_width(int width, int bpp)
6487{
6488 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6489 return ALIGN(pitch, 64);
6490}
6491
6492static u32
6493intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6494{
6495 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6496 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6497}
6498
6499static struct drm_framebuffer *
6500intel_framebuffer_create_for_mode(struct drm_device *dev,
6501 struct drm_display_mode *mode,
6502 int depth, int bpp)
6503{
6504 struct drm_i915_gem_object *obj;
0fed39bd 6505 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6506
6507 obj = i915_gem_alloc_object(dev,
6508 intel_framebuffer_size_for_mode(mode, bpp));
6509 if (obj == NULL)
6510 return ERR_PTR(-ENOMEM);
6511
6512 mode_cmd.width = mode->hdisplay;
6513 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6514 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6515 bpp);
5ca0c34a 6516 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6517
6518 return intel_framebuffer_create(dev, &mode_cmd, obj);
6519}
6520
6521static struct drm_framebuffer *
6522mode_fits_in_fbdev(struct drm_device *dev,
6523 struct drm_display_mode *mode)
6524{
6525 struct drm_i915_private *dev_priv = dev->dev_private;
6526 struct drm_i915_gem_object *obj;
6527 struct drm_framebuffer *fb;
6528
6529 if (dev_priv->fbdev == NULL)
6530 return NULL;
6531
6532 obj = dev_priv->fbdev->ifb.obj;
6533 if (obj == NULL)
6534 return NULL;
6535
6536 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6537 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6538 fb->bits_per_pixel))
d2dff872
CW		 6539 return NULL;
6540
01f2c773 6541 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6542 return NULL;
6543
6544 return fb;
6545}
6546
d2434ab7 6547bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6548 struct drm_display_mode *mode,
8261b191 6549 struct intel_load_detect_pipe *old)
79e53945
JB		 6550{
6551 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6552 struct intel_encoder *intel_encoder =
6553 intel_attached_encoder(connector);
79e53945 6554 struct drm_crtc *possible_crtc;
4ef69c7a 6555 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6556 struct drm_crtc *crtc = NULL;
6557 struct drm_device *dev = encoder->dev;
94352cf9 6558 struct drm_framebuffer *fb;
79e53945
JB		 6559 int i = -1;
6560
d2dff872
CW		 6561 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6562 connector->base.id, drm_get_connector_name(connector),
6563 encoder->base.id, drm_get_encoder_name(encoder));
6564
79e53945
JB		 6565 /*
6566 * Algorithm gets a little messy:
7a5e4805 6567 *
79e53945
JB		 6568 * - if the connector already has an assigned crtc, use it (but make
6569 * sure it's on first)
7a5e4805 6570 *
79e53945
JB		 6571 * - try to find the first unused crtc that can drive this connector,
6572 * and use that if we find one
79e53945
JB		 6573 */
6574
6575 /* See if we already have a CRTC for this connector */
6576 if (encoder->crtc) {
6577 crtc = encoder->crtc;
8261b191 6578
7b24056b
DV		 6579 mutex_lock(&crtc->mutex);
6580
24218aac 6581 old->dpms_mode = connector->dpms;
8261b191
CW		 6582 old->load_detect_temp = false;
6583
6584 /* Make sure the crtc and connector are running */
24218aac
DV		 6585 if (connector->dpms != DRM_MODE_DPMS_ON)
6586 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6587
7173188d 6588 return true;
79e53945
JB		 6589 }
6590
6591 /* Find an unused one (if possible) */
6592 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6593 i++;
6594 if (!(encoder->possible_crtcs & (1 << i)))
6595 continue;
6596 if (!possible_crtc->enabled) {
6597 crtc = possible_crtc;
6598 break;
6599 }
79e53945
JB		 6600 }
6601
6602 /*
6603 * If we didn't find an unused CRTC, don't use any.
6604 */
6605 if (!crtc) {
7173188d
CW		 6606 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6607 return false;
79e53945
JB		 6608 }
6609
7b24056b 6610 mutex_lock(&crtc->mutex);
fc303101
DV		 6611 intel_encoder->new_crtc = to_intel_crtc(crtc);
6612 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6613
6614 intel_crtc = to_intel_crtc(crtc);
24218aac 6615 old->dpms_mode = connector->dpms;
8261b191 6616 old->load_detect_temp = true;
d2dff872 6617 old->release_fb = NULL;
79e53945 6618
6492711d
CW		 6619 if (!mode)
6620 mode = &load_detect_mode;
79e53945 6621
d2dff872
CW		 6622 /* We need a framebuffer large enough to accommodate all accesses
6623 * that the plane may generate whilst we perform load detection.
6624 * We can not rely on the fbcon either being present (we get called
6625 * during its initialisation to detect all boot displays, or it may
6626 * not even exist) or that it is large enough to satisfy the
6627 * requested mode.
6628 */
94352cf9
DV		 6629 fb = mode_fits_in_fbdev(dev, mode);
6630 if (fb == NULL) {
d2dff872 6631 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6632 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6633 old->release_fb = fb;
d2dff872
CW		 6634 } else
6635 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6636 if (IS_ERR(fb)) {
d2dff872 6637 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6638 mutex_unlock(&crtc->mutex);
0e8b3d3e 6639 return false;
79e53945 6640 }
79e53945 6641
c0c36b94 6642 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6643 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6644 if (old->release_fb)
6645 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6646 mutex_unlock(&crtc->mutex);
0e8b3d3e 6647 return false;
79e53945 6648 }
7173188d 6649
79e53945 6650 /* let the connector get through one full cycle before testing */
9d0498a2 6651 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6652 return true;
79e53945
JB		 6653}
6654
d2434ab7 6655void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6656 struct intel_load_detect_pipe *old)
79e53945 6657{
d2434ab7
DV		 6658 struct intel_encoder *intel_encoder =
6659 intel_attached_encoder(connector);
4ef69c7a 6660 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6661 struct drm_crtc *crtc = encoder->crtc;
79e53945 6662
d2dff872
CW		 6663 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6664 connector->base.id, drm_get_connector_name(connector),
6665 encoder->base.id, drm_get_encoder_name(encoder));
6666
8261b191 6667 if (old->load_detect_temp) {
fc303101
DV		 6668 to_intel_connector(connector)->new_encoder = NULL;
6669 intel_encoder->new_crtc = NULL;
6670 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6671
36206361
DV		 6672 if (old->release_fb) {
6673 drm_framebuffer_unregister_private(old->release_fb);
6674 drm_framebuffer_unreference(old->release_fb);
6675 }
d2dff872 6676
67c96400 6677 mutex_unlock(&crtc->mutex);
0622a53c 6678 return;
79e53945
JB		 6679 }
6680
c751ce4f 6681 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6682 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6683 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6684
6685 mutex_unlock(&crtc->mutex);
79e53945
JB		 6686}
6687
6688/* Returns the clock of the currently programmed mode of the given pipe. */
6689static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6690{
6691 struct drm_i915_private *dev_priv = dev->dev_private;
6692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6693 int pipe = intel_crtc->pipe;
548f245b 6694 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6695 u32 fp;
6696 intel_clock_t clock;
6697
6698 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6699 fp = I915_READ(FP0(pipe));
79e53945 6700 else
39adb7a5 6701 fp = I915_READ(FP1(pipe));
79e53945
JB		 6702
6703 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6704 if (IS_PINEVIEW(dev)) {
6705 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6706 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6707 } else {
6708 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6709 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6710 }
6711
a6c45cf0 6712 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6713 if (IS_PINEVIEW(dev))
6714 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6715 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6716 else
6717 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6718 DPLL_FPA01_P1_POST_DIV_SHIFT);
6719
6720 switch (dpll & DPLL_MODE_MASK) {
6721 case DPLLB_MODE_DAC_SERIAL:
6722 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6723 5 : 10;
6724 break;
6725 case DPLLB_MODE_LVDS:
6726 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6727 7 : 14;
6728 break;
6729 default:
28c97730 6730 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6731 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6732 return 0;
6733 }
6734
6735 /* XXX: Handle the 100Mhz refclk */
2177832f 6736 intel_clock(dev, 96000, &clock);
79e53945
JB		 6737 } else {
6738 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6739
6740 if (is_lvds) {
6741 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6742 DPLL_FPA01_P1_POST_DIV_SHIFT);
6743 clock.p2 = 14;
6744
6745 if ((dpll & PLL_REF_INPUT_MASK) ==
6746 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6747 /* XXX: might not be 66MHz */
2177832f 6748 intel_clock(dev, 66000, &clock);
79e53945 6749 } else
2177832f 6750 intel_clock(dev, 48000, &clock);
79e53945
JB		 6751 } else {
6752 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6753 clock.p1 = 2;
6754 else {
6755 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6756 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6757 }
6758 if (dpll & PLL_P2_DIVIDE_BY_4)
6759 clock.p2 = 4;
6760 else
6761 clock.p2 = 2;
6762
2177832f 6763 intel_clock(dev, 48000, &clock);
79e53945
JB		 6764 }
6765 }
6766
6767 /* XXX: It would be nice to validate the clocks, but we can't reuse
6768 * i830PllIsValid() because it relies on the xf86_config connector
6769 * configuration being accurate, which it isn't necessarily.
6770 */
6771
6772 return clock.dot;
6773}
6774
6775/** Returns the currently programmed mode of the given pipe. */
6776struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6777 struct drm_crtc *crtc)
6778{
548f245b 6779 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6781 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6782 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6783 int htot = I915_READ(HTOTAL(cpu_transcoder));
6784 int hsync = I915_READ(HSYNC(cpu_transcoder));
6785 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6786 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6787
6788 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6789 if (!mode)
6790 return NULL;
6791
6792 mode->clock = intel_crtc_clock_get(dev, crtc);
6793 mode->hdisplay = (htot & 0xffff) + 1;
6794 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6795 mode->hsync_start = (hsync & 0xffff) + 1;
6796 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6797 mode->vdisplay = (vtot & 0xffff) + 1;
6798 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6799 mode->vsync_start = (vsync & 0xffff) + 1;
6800 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6801
6802 drm_mode_set_name(mode);
79e53945
JB		 6803
6804 return mode;
6805}
6806
3dec0095 6807static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6808{
6809 struct drm_device *dev = crtc->dev;
6810 drm_i915_private_t *dev_priv = dev->dev_private;
6811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6812 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6813 int dpll_reg = DPLL(pipe);
6814 int dpll;
652c393a 6815
bad720ff 6816 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6817 return;
6818
6819 if (!dev_priv->lvds_downclock_avail)
6820 return;
6821
dbdc6479 6822 dpll = I915_READ(dpll_reg);
652c393a 6823 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6824 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6825
8ac5a6d5 6826 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6827
6828 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6829 I915_WRITE(dpll_reg, dpll);
9d0498a2 6830 intel_wait_for_vblank(dev, pipe);
dbdc6479 6831
652c393a
JB		 6832 dpll = I915_READ(dpll_reg);
6833 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6834 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6835 }
652c393a
JB		 6836}
6837
6838static void intel_decrease_pllclock(struct drm_crtc *crtc)
6839{
6840 struct drm_device *dev = crtc->dev;
6841 drm_i915_private_t *dev_priv = dev->dev_private;
6842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6843
bad720ff 6844 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6845 return;
6846
6847 if (!dev_priv->lvds_downclock_avail)
6848 return;
6849
6850 /*
6851 * Since this is called by a timer, we should never get here in
6852 * the manual case.
6853 */
6854 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6855 int pipe = intel_crtc->pipe;
6856 int dpll_reg = DPLL(pipe);
6857 int dpll;
f6e5b160 6858
44d98a61 6859 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6860
8ac5a6d5 6861 assert_panel_unlocked(dev_priv, pipe);
652c393a 6862
dc257cf1 6863 dpll = I915_READ(dpll_reg);
652c393a
JB		 6864 dpll |= DISPLAY_RATE_SELECT_FPA1;
6865 I915_WRITE(dpll_reg, dpll);
9d0498a2 6866 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6867 dpll = I915_READ(dpll_reg);
6868 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6869 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6870 }
6871
6872}
6873
f047e395
CW		 6874void intel_mark_busy(struct drm_device *dev)
6875{
f047e395
CW		 6876 i915_update_gfx_val(dev->dev_private);
6877}
6878
6879void intel_mark_idle(struct drm_device *dev)
652c393a 6880{
652c393a 6881 struct drm_crtc *crtc;
652c393a
JB		 6882
6883 if (!i915_powersave)
6884 return;
6885
652c393a 6886 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6887 if (!crtc->fb)
6888 continue;
6889
725a5b54 6890 intel_decrease_pllclock(crtc);
652c393a 6891 }
652c393a
JB		 6892}
6893
725a5b54 6894void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6895{
f047e395
CW		 6896 struct drm_device *dev = obj->base.dev;
6897 struct drm_crtc *crtc;
652c393a 6898
f047e395 6899 if (!i915_powersave)
acb87dfb
CW		 6900 return;
6901
652c393a
JB		 6902 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6903 if (!crtc->fb)
6904 continue;
6905
f047e395 6906 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6907 intel_increase_pllclock(crtc);
652c393a
JB		 6908 }
6909}
6910
79e53945
JB		 6911static void intel_crtc_destroy(struct drm_crtc *crtc)
6912{
6913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6914 struct drm_device *dev = crtc->dev;
6915 struct intel_unpin_work *work;
6916 unsigned long flags;
6917
6918 spin_lock_irqsave(&dev->event_lock, flags);
6919 work = intel_crtc->unpin_work;
6920 intel_crtc->unpin_work = NULL;
6921 spin_unlock_irqrestore(&dev->event_lock, flags);
6922
6923 if (work) {
6924 cancel_work_sync(&work->work);
6925 kfree(work);
6926 }
79e53945
JB		 6927
6928 drm_crtc_cleanup(crtc);
67e77c5a 6929
79e53945
JB		 6930 kfree(intel_crtc);
6931}
6932
6b95a207
KH		 6933static void intel_unpin_work_fn(struct work_struct *__work)
6934{
6935 struct intel_unpin_work *work =
6936 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6937 struct drm_device *dev = work->crtc->dev;
6b95a207 6938
b4a98e57 6939 mutex_lock(&dev->struct_mutex);
1690e1eb 6940 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6941 drm_gem_object_unreference(&work->pending_flip_obj->base);
6942 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6943
b4a98e57
CW		 6944 intel_update_fbc(dev);
6945 mutex_unlock(&dev->struct_mutex);
6946
6947 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6948 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6949
6b95a207
KH		 6950 kfree(work);
6951}
6952
1afe3e9d 6953static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6954 struct drm_crtc *crtc)
6b95a207
KH		 6955{
6956 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6958 struct intel_unpin_work *work;
6b95a207
KH		 6959 unsigned long flags;
6960
6961 /* Ignore early vblank irqs */
6962 if (intel_crtc == NULL)
6963 return;
6964
6965 spin_lock_irqsave(&dev->event_lock, flags);
6966 work = intel_crtc->unpin_work;
e7d841ca
CW		 6967
6968 /* Ensure we don't miss a work->pending update ... */
6969 smp_rmb();
6970
6971 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 6972 spin_unlock_irqrestore(&dev->event_lock, flags);
6973 return;
6974 }
6975
e7d841ca
CW		 6976 /* and that the unpin work is consistent wrt ->pending. */
6977 smp_rmb();
6978
6b95a207 6979 intel_crtc->unpin_work = NULL;
6b95a207 6980
45a066eb
RC		 6981 if (work->event)
6982 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6983
0af7e4df
MK		 6984 drm_vblank_put(dev, intel_crtc->pipe);
6985
6b95a207
KH		 6986 spin_unlock_irqrestore(&dev->event_lock, flags);
6987
2c10d571 6988 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6989
6990 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6991
6992 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6993}
6994
1afe3e9d
JB		 6995void intel_finish_page_flip(struct drm_device *dev, int pipe)
6996{
6997 drm_i915_private_t *dev_priv = dev->dev_private;
6998 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6999
49b14a5c 7000 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7001}
7002
7003void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7004{
7005 drm_i915_private_t *dev_priv = dev->dev_private;
7006 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7007
49b14a5c 7008 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7009}
7010
6b95a207
KH		 7011void intel_prepare_page_flip(struct drm_device *dev, int plane)
7012{
7013 drm_i915_private_t *dev_priv = dev->dev_private;
7014 struct intel_crtc *intel_crtc =
7015 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7016 unsigned long flags;
7017
e7d841ca
CW		 7018 /* NB: An MMIO update of the plane base pointer will also
7019 * generate a page-flip completion irq, i.e. every modeset
7020 * is also accompanied by a spurious intel_prepare_page_flip().
7021 */
6b95a207 7022 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7023 if (intel_crtc->unpin_work)
7024 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7025 spin_unlock_irqrestore(&dev->event_lock, flags);
7026}
7027
e7d841ca
CW		 7028inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7029{
7030 /* Ensure that the work item is consistent when activating it ... */
7031 smp_wmb();
7032 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7033 /* and that it is marked active as soon as the irq could fire. */
7034 smp_wmb();
7035}
7036
8c9f3aaf
JB		 7037static int intel_gen2_queue_flip(struct drm_device *dev,
7038 struct drm_crtc *crtc,
7039 struct drm_framebuffer *fb,
7040 struct drm_i915_gem_object *obj)
7041{
7042 struct drm_i915_private *dev_priv = dev->dev_private;
7043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7044 u32 flip_mask;
6d90c952 7045 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7046 int ret;
7047
6d90c952 7048 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7049 if (ret)
83d4092b 7050 goto err;
8c9f3aaf 7051
6d90c952 7052 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7053 if (ret)
83d4092b 7054 goto err_unpin;
8c9f3aaf
JB		 7055
7056 /* Can't queue multiple flips, so wait for the previous
7057 * one to finish before executing the next.
7058 */
7059 if (intel_crtc->plane)
7060 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7061 else
7062 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7063 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7064 intel_ring_emit(ring, MI_NOOP);
7065 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7066 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7067 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7068 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7069 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7070
7071 intel_mark_page_flip_active(intel_crtc);
6d90c952 7072 intel_ring_advance(ring);
83d4092b
CW		 7073 return 0;
7074
7075err_unpin:
7076 intel_unpin_fb_obj(obj);
7077err:
8c9f3aaf
JB		 7078 return ret;
7079}
7080
7081static int intel_gen3_queue_flip(struct drm_device *dev,
7082 struct drm_crtc *crtc,
7083 struct drm_framebuffer *fb,
7084 struct drm_i915_gem_object *obj)
7085{
7086 struct drm_i915_private *dev_priv = dev->dev_private;
7087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7088 u32 flip_mask;
6d90c952 7089 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7090 int ret;
7091
6d90c952 7092 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7093 if (ret)
83d4092b 7094 goto err;
8c9f3aaf 7095
6d90c952 7096 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7097 if (ret)
83d4092b 7098 goto err_unpin;
8c9f3aaf
JB		 7099
7100 if (intel_crtc->plane)
7101 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7102 else
7103 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7104 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7105 intel_ring_emit(ring, MI_NOOP);
7106 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7107 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7108 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7109 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7110 intel_ring_emit(ring, MI_NOOP);
7111
e7d841ca 7112 intel_mark_page_flip_active(intel_crtc);
6d90c952 7113 intel_ring_advance(ring);
83d4092b
CW		 7114 return 0;
7115
7116err_unpin:
7117 intel_unpin_fb_obj(obj);
7118err:
8c9f3aaf
JB		 7119 return ret;
7120}
7121
7122static int intel_gen4_queue_flip(struct drm_device *dev,
7123 struct drm_crtc *crtc,
7124 struct drm_framebuffer *fb,
7125 struct drm_i915_gem_object *obj)
7126{
7127 struct drm_i915_private *dev_priv = dev->dev_private;
7128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7129 uint32_t pf, pipesrc;
6d90c952 7130 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7131 int ret;
7132
6d90c952 7133 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7134 if (ret)
83d4092b 7135 goto err;
8c9f3aaf 7136
6d90c952 7137 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7138 if (ret)
83d4092b 7139 goto err_unpin;
8c9f3aaf
JB		 7140
7141 /* i965+ uses the linear or tiled offsets from the
7142 * Display Registers (which do not change across a page-flip)
7143 * so we need only reprogram the base address.
7144 */
6d90c952
DV		 7145 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7146 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7147 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7148 intel_ring_emit(ring,
7149 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7150 obj->tiling_mode);
8c9f3aaf
JB		 7151
7152 /* XXX Enabling the panel-fitter across page-flip is so far
7153 * untested on non-native modes, so ignore it for now.
7154 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7155 */
7156 pf = 0;
7157 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7158 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7159
7160 intel_mark_page_flip_active(intel_crtc);
6d90c952 7161 intel_ring_advance(ring);
83d4092b
CW		 7162 return 0;
7163
7164err_unpin:
7165 intel_unpin_fb_obj(obj);
7166err:
8c9f3aaf
JB		 7167 return ret;
7168}
7169
7170static int intel_gen6_queue_flip(struct drm_device *dev,
7171 struct drm_crtc *crtc,
7172 struct drm_framebuffer *fb,
7173 struct drm_i915_gem_object *obj)
7174{
7175 struct drm_i915_private *dev_priv = dev->dev_private;
7176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7177 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7178 uint32_t pf, pipesrc;
7179 int ret;
7180
6d90c952 7181 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7182 if (ret)
83d4092b 7183 goto err;
8c9f3aaf 7184
6d90c952 7185 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7186 if (ret)
83d4092b 7187 goto err_unpin;
8c9f3aaf 7188
6d90c952
DV		 7189 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7190 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7191 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7192 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7193
dc257cf1
DV		 7194 /* Contrary to the suggestions in the documentation,
7195 * "Enable Panel Fitter" does not seem to be required when page
7196 * flipping with a non-native mode, and worse causes a normal
7197 * modeset to fail.
7198 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7199 */
7200 pf = 0;
8c9f3aaf 7201 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7202 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7203
7204 intel_mark_page_flip_active(intel_crtc);
6d90c952 7205 intel_ring_advance(ring);
83d4092b
CW		 7206 return 0;
7207
7208err_unpin:
7209 intel_unpin_fb_obj(obj);
7210err:
8c9f3aaf
JB		 7211 return ret;
7212}
7213
7c9017e5
JB		 7214/*
7215 * On gen7 we currently use the blit ring because (in early silicon at least)
7216 * the render ring doesn't give us interrpts for page flip completion, which
7217 * means clients will hang after the first flip is queued. Fortunately the
7218 * blit ring generates interrupts properly, so use it instead.
7219 */
7220static int intel_gen7_queue_flip(struct drm_device *dev,
7221 struct drm_crtc *crtc,
7222 struct drm_framebuffer *fb,
7223 struct drm_i915_gem_object *obj)
7224{
7225 struct drm_i915_private *dev_priv = dev->dev_private;
7226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7227 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7228 uint32_t plane_bit = 0;
7c9017e5
JB		 7229 int ret;
7230
7231 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7232 if (ret)
83d4092b 7233 goto err;
7c9017e5 7234
cb05d8de
DV		 7235 switch(intel_crtc->plane) {
7236 case PLANE_A:
7237 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7238 break;
7239 case PLANE_B:
7240 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7241 break;
7242 case PLANE_C:
7243 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7244 break;
7245 default:
7246 WARN_ONCE(1, "unknown plane in flip command\n");
7247 ret = -ENODEV;
ab3951eb 7248 goto err_unpin;
cb05d8de
DV		 7249 }
7250
7c9017e5
JB		 7251 ret = intel_ring_begin(ring, 4);
7252 if (ret)
83d4092b 7253 goto err_unpin;
7c9017e5 7254
cb05d8de 7255 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7256 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7257 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7258 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7259
7260 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7261 intel_ring_advance(ring);
83d4092b
CW		 7262 return 0;
7263
7264err_unpin:
7265 intel_unpin_fb_obj(obj);
7266err:
7c9017e5
JB		 7267 return ret;
7268}
7269
8c9f3aaf
JB		 7270static int intel_default_queue_flip(struct drm_device *dev,
7271 struct drm_crtc *crtc,
7272 struct drm_framebuffer *fb,
7273 struct drm_i915_gem_object *obj)
7274{
7275 return -ENODEV;
7276}
7277
6b95a207
KH		 7278static int intel_crtc_page_flip(struct drm_crtc *crtc,
7279 struct drm_framebuffer *fb,
7280 struct drm_pending_vblank_event *event)
7281{
7282 struct drm_device *dev = crtc->dev;
7283 struct drm_i915_private *dev_priv = dev->dev_private;
7284 struct intel_framebuffer *intel_fb;
05394f39 7285 struct drm_i915_gem_object *obj;
6b95a207
KH		 7286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7287 struct intel_unpin_work *work;
8c9f3aaf 7288 unsigned long flags;
52e68630 7289 int ret;
6b95a207 7290
e6a595d2
VS		 7291 /* Can't change pixel format via MI display flips. */
7292 if (fb->pixel_format != crtc->fb->pixel_format)
7293 return -EINVAL;
7294
7295 /*
7296 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7297 * Note that pitch changes could also affect these register.
7298 */
7299 if (INTEL_INFO(dev)->gen > 3 &&
7300 (fb->offsets[0] != crtc->fb->offsets[0] ||
7301 fb->pitches[0] != crtc->fb->pitches[0]))
7302 return -EINVAL;
7303
6b95a207
KH		 7304 work = kzalloc(sizeof *work, GFP_KERNEL);
7305 if (work == NULL)
7306 return -ENOMEM;
7307
6b95a207 7308 work->event = event;
b4a98e57 7309 work->crtc = crtc;
6b95a207 7310 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7311 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7312 INIT_WORK(&work->work, intel_unpin_work_fn);
7313
7317c75e
JB		 7314 ret = drm_vblank_get(dev, intel_crtc->pipe);
7315 if (ret)
7316 goto free_work;
7317
6b95a207
KH		 7318 /* We borrow the event spin lock for protecting unpin_work */
7319 spin_lock_irqsave(&dev->event_lock, flags);
7320 if (intel_crtc->unpin_work) {
7321 spin_unlock_irqrestore(&dev->event_lock, flags);
7322 kfree(work);
7317c75e 7323 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7324
7325 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7326 return -EBUSY;
7327 }
7328 intel_crtc->unpin_work = work;
7329 spin_unlock_irqrestore(&dev->event_lock, flags);
7330
7331 intel_fb = to_intel_framebuffer(fb);
7332 obj = intel_fb->obj;
7333
b4a98e57
CW		 7334 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7335 flush_workqueue(dev_priv->wq);
7336
79158103
CW		 7337 ret = i915_mutex_lock_interruptible(dev);
7338 if (ret)
7339 goto cleanup;
6b95a207 7340
75dfca80 7341 /* Reference the objects for the scheduled work. */
05394f39
CW		 7342 drm_gem_object_reference(&work->old_fb_obj->base);
7343 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7344
7345 crtc->fb = fb;
96b099fd 7346
e1f99ce6 7347 work->pending_flip_obj = obj;
e1f99ce6 7348
4e5359cd
SF		 7349 work->enable_stall_check = true;
7350
b4a98e57 7351 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7352 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7353
8c9f3aaf
JB		 7354 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7355 if (ret)
7356 goto cleanup_pending;
6b95a207 7357
7782de3b 7358 intel_disable_fbc(dev);
f047e395 7359 intel_mark_fb_busy(obj);
6b95a207
KH		 7360 mutex_unlock(&dev->struct_mutex);
7361
e5510fac
JB		 7362 trace_i915_flip_request(intel_crtc->plane, obj);
7363
6b95a207 7364 return 0;
96b099fd 7365
8c9f3aaf 7366cleanup_pending:
b4a98e57 7367 atomic_dec(&intel_crtc->unpin_work_count);
05394f39
CW		 7368 drm_gem_object_unreference(&work->old_fb_obj->base);
7369 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7370 mutex_unlock(&dev->struct_mutex);
7371
79158103 7372cleanup:
96b099fd
CW		 7373 spin_lock_irqsave(&dev->event_lock, flags);
7374 intel_crtc->unpin_work = NULL;
7375 spin_unlock_irqrestore(&dev->event_lock, flags);
7376
7317c75e
JB		 7377 drm_vblank_put(dev, intel_crtc->pipe);
7378free_work:
96b099fd
CW		 7379 kfree(work);
7380
7381 return ret;
6b95a207
KH		 7382}
7383
f6e5b160 7384static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7385 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7386 .load_lut = intel_crtc_load_lut,
976f8a20 7387 .disable = intel_crtc_noop,
f6e5b160
CW		 7388};
7389
6ed0f796 7390bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7391{
6ed0f796
DV		 7392 struct intel_encoder *other_encoder;
7393 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7394
6ed0f796
DV		 7395 if (WARN_ON(!crtc))
7396 return false;
7397
7398 list_for_each_entry(other_encoder,
7399 &crtc->dev->mode_config.encoder_list,
7400 base.head) {
7401
7402 if (&other_encoder->new_crtc->base != crtc ||
7403 encoder == other_encoder)
7404 continue;
7405 else
7406 return true;
f47166d2
CW		 7407 }
7408
6ed0f796
DV		 7409 return false;
7410}
47f1c6c9 7411
50f56119
DV		 7412static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7413 struct drm_crtc *crtc)
7414{
7415 struct drm_device *dev;
7416 struct drm_crtc *tmp;
7417 int crtc_mask = 1;
47f1c6c9 7418
50f56119 7419 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7420
50f56119 7421 dev = crtc->dev;
47f1c6c9 7422
50f56119
DV		 7423 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7424 if (tmp == crtc)
7425 break;
7426 crtc_mask <<= 1;
7427 }
47f1c6c9 7428
50f56119
DV		 7429 if (encoder->possible_crtcs & crtc_mask)
7430 return true;
7431 return false;
47f1c6c9 7432}
79e53945 7433
9a935856
DV		 7434/**
7435 * intel_modeset_update_staged_output_state
7436 *
7437 * Updates the staged output configuration state, e.g. after we've read out the
7438 * current hw state.
7439 */
7440static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7441{
9a935856
DV		 7442 struct intel_encoder *encoder;
7443 struct intel_connector *connector;
f6e5b160 7444
9a935856
DV		 7445 list_for_each_entry(connector, &dev->mode_config.connector_list,
7446 base.head) {
7447 connector->new_encoder =
7448 to_intel_encoder(connector->base.encoder);
7449 }
f6e5b160 7450
9a935856
DV		 7451 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7452 base.head) {
7453 encoder->new_crtc =
7454 to_intel_crtc(encoder->base.crtc);
7455 }
f6e5b160
CW		 7456}
7457
9a935856
DV		 7458/**
7459 * intel_modeset_commit_output_state
7460 *
7461 * This function copies the stage display pipe configuration to the real one.
7462 */
7463static void intel_modeset_commit_output_state(struct drm_device *dev)
7464{
7465 struct intel_encoder *encoder;
7466 struct intel_connector *connector;
f6e5b160 7467
9a935856
DV		 7468 list_for_each_entry(connector, &dev->mode_config.connector_list,
7469 base.head) {
7470 connector->base.encoder = &connector->new_encoder->base;
7471 }
f6e5b160 7472
9a935856
DV		 7473 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7474 base.head) {
7475 encoder->base.crtc = &encoder->new_crtc->base;
7476 }
7477}
7478
7758a113
DV		 7479static struct drm_display_mode *
7480intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7481 struct drm_display_mode *mode)
ee7b9f93 7482{
7758a113
DV		 7483 struct drm_device *dev = crtc->dev;
7484 struct drm_display_mode *adjusted_mode;
7485 struct drm_encoder_helper_funcs *encoder_funcs;
7486 struct intel_encoder *encoder;
ee7b9f93 7487
7758a113
DV		 7488 adjusted_mode = drm_mode_duplicate(dev, mode);
7489 if (!adjusted_mode)
7490 return ERR_PTR(-ENOMEM);
7491
7492 /* Pass our mode to the connectors and the CRTC to give them a chance to
7493 * adjust it according to limitations or connector properties, and also
7494 * a chance to reject the mode entirely.
47f1c6c9 7495 */
7758a113
DV		 7496 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7497 base.head) {
47f1c6c9 7498
7758a113
DV		 7499 if (&encoder->new_crtc->base != crtc)
7500 continue;
7501 encoder_funcs = encoder->base.helper_private;
7502 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7503 adjusted_mode))) {
7504 DRM_DEBUG_KMS("Encoder fixup failed\n");
7505 goto fail;
7506 }
ee7b9f93 7507 }
47f1c6c9 7508
7758a113
DV		 7509 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7510 DRM_DEBUG_KMS("CRTC fixup failed\n");
7511 goto fail;
ee7b9f93 7512 }
7758a113 7513 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7514
7758a113
DV		 7515 return adjusted_mode;
7516fail:
7517 drm_mode_destroy(dev, adjusted_mode);
7518 return ERR_PTR(-EINVAL);
ee7b9f93 7519}
47f1c6c9 7520
e2e1ed41
DV		 7521/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7522 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7523static void
7524intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7525 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7526{
7527 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7528 struct drm_device *dev = crtc->dev;
7529 struct intel_encoder *encoder;
7530 struct intel_connector *connector;
7531 struct drm_crtc *tmp_crtc;
79e53945 7532
e2e1ed41 7533 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7534
e2e1ed41
DV		 7535 /* Check which crtcs have changed outputs connected to them, these need
7536 * to be part of the prepare_pipes mask. We don't (yet) support global
7537 * modeset across multiple crtcs, so modeset_pipes will only have one
7538 * bit set at most. */
7539 list_for_each_entry(connector, &dev->mode_config.connector_list,
7540 base.head) {
7541 if (connector->base.encoder == &connector->new_encoder->base)
7542 continue;
79e53945 7543
e2e1ed41
DV		 7544 if (connector->base.encoder) {
7545 tmp_crtc = connector->base.encoder->crtc;
7546
7547 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7548 }
7549
7550 if (connector->new_encoder)
7551 *prepare_pipes |=
7552 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7553 }
7554
e2e1ed41
DV		 7555 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7556 base.head) {
7557 if (encoder->base.crtc == &encoder->new_crtc->base)
7558 continue;
7559
7560 if (encoder->base.crtc) {
7561 tmp_crtc = encoder->base.crtc;
7562
7563 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7564 }
7565
7566 if (encoder->new_crtc)
7567 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7568 }
7569
e2e1ed41
DV		 7570 /* Check for any pipes that will be fully disabled ... */
7571 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7572 base.head) {
7573 bool used = false;
22fd0fab 7574
e2e1ed41
DV		 7575 /* Don't try to disable disabled crtcs. */
7576 if (!intel_crtc->base.enabled)
7577 continue;
7e7d76c3 7578
e2e1ed41
DV		 7579 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7580 base.head) {
7581 if (encoder->new_crtc == intel_crtc)
7582 used = true;
7583 }
7584
7585 if (!used)
7586 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7587 }
7588
e2e1ed41
DV		 7589
7590 /* set_mode is also used to update properties on life display pipes. */
7591 intel_crtc = to_intel_crtc(crtc);
7592 if (crtc->enabled)
7593 *prepare_pipes |= 1 << intel_crtc->pipe;
7594
7595 /* We only support modeset on one single crtc, hence we need to do that
7596 * only for the passed in crtc iff we change anything else than just
7597 * disable crtcs.
7598 *
7599 * This is actually not true, to be fully compatible with the old crtc
7600 * helper we automatically disable _any_ output (i.e. doesn't need to be
7601 * connected to the crtc we're modesetting on) if it's disconnected.
7602 * Which is a rather nutty api (since changed the output configuration
7603 * without userspace's explicit request can lead to confusion), but
7604 * alas. Hence we currently need to modeset on all pipes we prepare. */
7605 if (*prepare_pipes)
7606 *modeset_pipes = *prepare_pipes;
7607
7608 /* ... and mask these out. */
7609 *modeset_pipes &= ~(*disable_pipes);
7610 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7611}
79e53945 7612
ea9d758d 7613static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7614{
ea9d758d 7615 struct drm_encoder *encoder;
f6e5b160 7616 struct drm_device *dev = crtc->dev;
f6e5b160 7617
ea9d758d
DV		 7618 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7619 if (encoder->crtc == crtc)
7620 return true;
7621
7622 return false;
7623}
7624
7625static void
7626intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7627{
7628 struct intel_encoder *intel_encoder;
7629 struct intel_crtc *intel_crtc;
7630 struct drm_connector *connector;
7631
7632 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7633 base.head) {
7634 if (!intel_encoder->base.crtc)
7635 continue;
7636
7637 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7638
7639 if (prepare_pipes & (1 << intel_crtc->pipe))
7640 intel_encoder->connectors_active = false;
7641 }
7642
7643 intel_modeset_commit_output_state(dev);
7644
7645 /* Update computed state. */
7646 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7647 base.head) {
7648 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7649 }
7650
7651 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7652 if (!connector->encoder || !connector->encoder->crtc)
7653 continue;
7654
7655 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7656
7657 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7658 struct drm_property *dpms_property =
7659 dev->mode_config.dpms_property;
7660
ea9d758d 7661 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7662 drm_object_property_set_value(&connector->base,
68d34720
DV		 7663 dpms_property,
7664 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7665
7666 intel_encoder = to_intel_encoder(connector->encoder);
7667 intel_encoder->connectors_active = true;
7668 }
7669 }
7670
7671}
7672
25c5b266
DV		 7673#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7674 list_for_each_entry((intel_crtc), \
7675 &(dev)->mode_config.crtc_list, \
7676 base.head) \
7677 if (mask & (1 <<(intel_crtc)->pipe)) \
7678
b980514c 7679void
8af6cf88
DV		 7680intel_modeset_check_state(struct drm_device *dev)
7681{
7682 struct intel_crtc *crtc;
7683 struct intel_encoder *encoder;
7684 struct intel_connector *connector;
7685
7686 list_for_each_entry(connector, &dev->mode_config.connector_list,
7687 base.head) {
7688 /* This also checks the encoder/connector hw state with the
7689 * ->get_hw_state callbacks. */
7690 intel_connector_check_state(connector);
7691
7692 WARN(&connector->new_encoder->base != connector->base.encoder,
7693 "connector's staged encoder doesn't match current encoder\n");
7694 }
7695
7696 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7697 base.head) {
7698 bool enabled = false;
7699 bool active = false;
7700 enum pipe pipe, tracked_pipe;
7701
7702 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7703 encoder->base.base.id,
7704 drm_get_encoder_name(&encoder->base));
7705
7706 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7707 "encoder's stage crtc doesn't match current crtc\n");
7708 WARN(encoder->connectors_active && !encoder->base.crtc,
7709 "encoder's active_connectors set, but no crtc\n");
7710
7711 list_for_each_entry(connector, &dev->mode_config.connector_list,
7712 base.head) {
7713 if (connector->base.encoder != &encoder->base)
7714 continue;
7715 enabled = true;
7716 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7717 active = true;
7718 }
7719 WARN(!!encoder->base.crtc != enabled,
7720 "encoder's enabled state mismatch "
7721 "(expected %i, found %i)\n",
7722 !!encoder->base.crtc, enabled);
7723 WARN(active && !encoder->base.crtc,
7724 "active encoder with no crtc\n");
7725
7726 WARN(encoder->connectors_active != active,
7727 "encoder's computed active state doesn't match tracked active state "
7728 "(expected %i, found %i)\n", active, encoder->connectors_active);
7729
7730 active = encoder->get_hw_state(encoder, &pipe);
7731 WARN(active != encoder->connectors_active,
7732 "encoder's hw state doesn't match sw tracking "
7733 "(expected %i, found %i)\n",
7734 encoder->connectors_active, active);
7735
7736 if (!encoder->base.crtc)
7737 continue;
7738
7739 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7740 WARN(active && pipe != tracked_pipe,
7741 "active encoder's pipe doesn't match"
7742 "(expected %i, found %i)\n",
7743 tracked_pipe, pipe);
7744
7745 }
7746
7747 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7748 base.head) {
7749 bool enabled = false;
7750 bool active = false;
7751
7752 DRM_DEBUG_KMS("[CRTC:%d]\n",
7753 crtc->base.base.id);
7754
7755 WARN(crtc->active && !crtc->base.enabled,
7756 "active crtc, but not enabled in sw tracking\n");
7757
7758 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7759 base.head) {
7760 if (encoder->base.crtc != &crtc->base)
7761 continue;
7762 enabled = true;
7763 if (encoder->connectors_active)
7764 active = true;
7765 }
7766 WARN(active != crtc->active,
7767 "crtc's computed active state doesn't match tracked active state "
7768 "(expected %i, found %i)\n", active, crtc->active);
7769 WARN(enabled != crtc->base.enabled,
7770 "crtc's computed enabled state doesn't match tracked enabled state "
7771 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7772
7773 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7774 }
7775}
7776
c0c36b94
CW		 7777int intel_set_mode(struct drm_crtc *crtc,
7778 struct drm_display_mode *mode,
7779 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7780{
7781 struct drm_device *dev = crtc->dev;
dbf2b54e 7782 drm_i915_private_t *dev_priv = dev->dev_private;
3ac18232 7783 struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
25c5b266
DV		 7784 struct intel_crtc *intel_crtc;
7785 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7786 int ret = 0;
a6778b3c 7787
3ac18232 7788 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7789 if (!saved_mode)
7790 return -ENOMEM;
3ac18232 7791 saved_hwmode = saved_mode + 1;
a6778b3c 7792
e2e1ed41 7793 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7794 &prepare_pipes, &disable_pipes);
7795
7796 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7797 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7798
976f8a20
DV		 7799 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7800 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7801
3ac18232
TG		 7802 *saved_hwmode = crtc->hwmode;
7803 *saved_mode = crtc->mode;
a6778b3c 7804
25c5b266
DV		 7805 /* Hack: Because we don't (yet) support global modeset on multiple
7806 * crtcs, we don't keep track of the new mode for more than one crtc.
7807 * Hence simply check whether any bit is set in modeset_pipes in all the
7808 * pieces of code that are not yet converted to deal with mutliple crtcs
7809 * changing their mode at the same time. */
7810 adjusted_mode = NULL;
7811 if (modeset_pipes) {
7812 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7813 if (IS_ERR(adjusted_mode)) {
c0c36b94 7814 ret = PTR_ERR(adjusted_mode);
3ac18232 7815 goto out;
25c5b266 7816 }
25c5b266 7817 }
a6778b3c 7818
ea9d758d
DV		 7819 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7820 if (intel_crtc->base.enabled)
7821 dev_priv->display.crtc_disable(&intel_crtc->base);
7822 }
a6778b3c 7823
6c4c86f5
DV		 7824 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7825 * to set it here already despite that we pass it down the callchain.
f6e5b160 7826 */
6c4c86f5 7827 if (modeset_pipes)
25c5b266 7828 crtc->mode = *mode;
7758a113 7829
ea9d758d
DV		 7830 /* Only after disabling all output pipelines that will be changed can we
7831 * update the the output configuration. */
7832 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7833
47fab737
DV		 7834 if (dev_priv->display.modeset_global_resources)
7835 dev_priv->display.modeset_global_resources(dev);
7836
a6778b3c
DV		 7837 /* Set up the DPLL and any encoders state that needs to adjust or depend
7838 * on the DPLL.
f6e5b160 7839 */
25c5b266 7840 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94
CW		 7841 ret = intel_crtc_mode_set(&intel_crtc->base,
7842 mode, adjusted_mode,
7843 x, y, fb);
7844 if (ret)
7845 goto done;
a6778b3c
DV		 7846 }
7847
7848 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7849 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7850 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7851
25c5b266
DV		 7852 if (modeset_pipes) {
7853 /* Store real post-adjustment hardware mode. */
7854 crtc->hwmode = *adjusted_mode;
a6778b3c 7855
25c5b266
DV		 7856 /* Calculate and store various constants which
7857 * are later needed by vblank and swap-completion
7858 * timestamping. They are derived from true hwmode.
7859 */
7860 drm_calc_timestamping_constants(crtc);
7861 }
a6778b3c
DV		 7862
7863 /* FIXME: add subpixel order */
7864done:
7865 drm_mode_destroy(dev, adjusted_mode);
c0c36b94 7866 if (ret && crtc->enabled) {
3ac18232
TG		 7867 crtc->hwmode = *saved_hwmode;
7868 crtc->mode = *saved_mode;
8af6cf88
DV		 7869 } else {
7870 intel_modeset_check_state(dev);
a6778b3c
DV		 7871 }
7872
3ac18232
TG		 7873out:
7874 kfree(saved_mode);
a6778b3c 7875 return ret;
f6e5b160
CW		 7876}
7877
c0c36b94
CW		 7878void intel_crtc_restore_mode(struct drm_crtc *crtc)
7879{
7880 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7881}
7882
25c5b266
DV		 7883#undef for_each_intel_crtc_masked
7884
d9e55608
DV		 7885static void intel_set_config_free(struct intel_set_config *config)
7886{
7887 if (!config)
7888 return;
7889
1aa4b628
DV		 7890 kfree(config->save_connector_encoders);
7891 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7892 kfree(config);
7893}
7894
85f9eb71
DV		 7895static int intel_set_config_save_state(struct drm_device *dev,
7896 struct intel_set_config *config)
7897{
85f9eb71
DV		 7898 struct drm_encoder *encoder;
7899 struct drm_connector *connector;
7900 int count;
7901
1aa4b628
DV		 7902 config->save_encoder_crtcs =
7903 kcalloc(dev->mode_config.num_encoder,
7904 sizeof(struct drm_crtc *), GFP_KERNEL);
7905 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7906 return -ENOMEM;
7907
1aa4b628
DV		 7908 config->save_connector_encoders =
7909 kcalloc(dev->mode_config.num_connector,
7910 sizeof(struct drm_encoder *), GFP_KERNEL);
7911 if (!config->save_connector_encoders)
85f9eb71
DV		 7912 return -ENOMEM;
7913
7914 /* Copy data. Note that driver private data is not affected.
7915 * Should anything bad happen only the expected state is
7916 * restored, not the drivers personal bookkeeping.
7917 */
85f9eb71
DV		 7918 count = 0;
7919 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7920 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7921 }
7922
7923 count = 0;
7924 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7925 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7926 }
7927
7928 return 0;
7929}
7930
7931static void intel_set_config_restore_state(struct drm_device *dev,
7932 struct intel_set_config *config)
7933{
9a935856
DV		 7934 struct intel_encoder *encoder;
7935 struct intel_connector *connector;
85f9eb71
DV		 7936 int count;
7937
85f9eb71 7938 count = 0;
9a935856
DV		 7939 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7940 encoder->new_crtc =
7941 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7942 }
7943
7944 count = 0;
9a935856
DV		 7945 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7946 connector->new_encoder =
7947 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7948 }
7949}
7950
5e2b584e
DV		 7951static void
7952intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7953 struct intel_set_config *config)
7954{
7955
7956 /* We should be able to check here if the fb has the same properties
7957 * and then just flip_or_move it */
7958 if (set->crtc->fb != set->fb) {
7959 /* If we have no fb then treat it as a full mode set */
7960 if (set->crtc->fb == NULL) {
7961 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7962 config->mode_changed = true;
7963 } else if (set->fb == NULL) {
7964 config->mode_changed = true;
7965 } else if (set->fb->depth != set->crtc->fb->depth) {
7966 config->mode_changed = true;
7967 } else if (set->fb->bits_per_pixel !=
7968 set->crtc->fb->bits_per_pixel) {
7969 config->mode_changed = true;
7970 } else
7971 config->fb_changed = true;
7972 }
7973
835c5873 7974 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7975 config->fb_changed = true;
7976
7977 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7978 DRM_DEBUG_KMS("modes are different, full mode set\n");
7979 drm_mode_debug_printmodeline(&set->crtc->mode);
7980 drm_mode_debug_printmodeline(set->mode);
7981 config->mode_changed = true;
7982 }
7983}
7984
2e431051 7985static int
9a935856
DV		 7986intel_modeset_stage_output_state(struct drm_device *dev,
7987 struct drm_mode_set *set,
7988 struct intel_set_config *config)
50f56119 7989{
85f9eb71 7990 struct drm_crtc *new_crtc;
9a935856
DV		 7991 struct intel_connector *connector;
7992 struct intel_encoder *encoder;
2e431051 7993 int count, ro;
50f56119 7994
9abdda74 7995 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 7996 * of connectors. For paranoia, double-check this. */
7997 WARN_ON(!set->fb && (set->num_connectors != 0));
7998 WARN_ON(set->fb && (set->num_connectors == 0));
7999
50f56119 8000 count = 0;
9a935856
DV		 8001 list_for_each_entry(connector, &dev->mode_config.connector_list,
8002 base.head) {
8003 /* Otherwise traverse passed in connector list and get encoders
8004 * for them. */
50f56119 8005 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8006 if (set->connectors[ro] == &connector->base) {
8007 connector->new_encoder = connector->encoder;
50f56119
DV		 8008 break;
8009 }
8010 }
8011
9a935856
DV		 8012 /* If we disable the crtc, disable all its connectors. Also, if
8013 * the connector is on the changing crtc but not on the new
8014 * connector list, disable it. */
8015 if ((!set->fb || ro == set->num_connectors) &&
8016 connector->base.encoder &&
8017 connector->base.encoder->crtc == set->crtc) {
8018 connector->new_encoder = NULL;
8019
8020 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8021 connector->base.base.id,
8022 drm_get_connector_name(&connector->base));
8023 }
8024
8025
8026 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8027 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8028 config->mode_changed = true;
50f56119
DV		 8029 }
8030 }
9a935856 8031 /* connector->new_encoder is now updated for all connectors. */
50f56119 8032
9a935856 8033 /* Update crtc of enabled connectors. */
50f56119 8034 count = 0;
9a935856
DV		 8035 list_for_each_entry(connector, &dev->mode_config.connector_list,
8036 base.head) {
8037 if (!connector->new_encoder)
50f56119
DV		 8038 continue;
8039
9a935856 8040 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8041
8042 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8043 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8044 new_crtc = set->crtc;
8045 }
8046
8047 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8048 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8049 new_crtc)) {
5e2b584e 8050 return -EINVAL;
50f56119 8051 }
9a935856
DV		 8052 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8053
8054 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8055 connector->base.base.id,
8056 drm_get_connector_name(&connector->base),
8057 new_crtc->base.id);
8058 }
8059
8060 /* Check for any encoders that needs to be disabled. */
8061 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8062 base.head) {
8063 list_for_each_entry(connector,
8064 &dev->mode_config.connector_list,
8065 base.head) {
8066 if (connector->new_encoder == encoder) {
8067 WARN_ON(!connector->new_encoder->new_crtc);
8068
8069 goto next_encoder;
8070 }
8071 }
8072 encoder->new_crtc = NULL;
8073next_encoder:
8074 /* Only now check for crtc changes so we don't miss encoders
8075 * that will be disabled. */
8076 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8077 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8078 config->mode_changed = true;
50f56119
DV		 8079 }
8080 }
9a935856 8081 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8082
2e431051
DV		 8083 return 0;
8084}
8085
8086static int intel_crtc_set_config(struct drm_mode_set *set)
8087{
8088 struct drm_device *dev;
2e431051
DV		 8089 struct drm_mode_set save_set;
8090 struct intel_set_config *config;
8091 int ret;
2e431051 8092
8d3e375e
DV		 8093 BUG_ON(!set);
8094 BUG_ON(!set->crtc);
8095 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 8096
8097 if (!set->mode)
8098 set->fb = NULL;
8099
431e50f7
DV		 8100 /* The fb helper likes to play gross jokes with ->mode_set_config.
8101 * Unfortunately the crtc helper doesn't do much at all for this case,
8102 * so we have to cope with this madness until the fb helper is fixed up. */
8103 if (set->fb && set->num_connectors == 0)
8104 return 0;
8105
2e431051
DV		 8106 if (set->fb) {
8107 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8108 set->crtc->base.id, set->fb->base.id,
8109 (int)set->num_connectors, set->x, set->y);
8110 } else {
8111 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8112 }
8113
8114 dev = set->crtc->dev;
8115
8116 ret = -ENOMEM;
8117 config = kzalloc(sizeof(*config), GFP_KERNEL);
8118 if (!config)
8119 goto out_config;
8120
8121 ret = intel_set_config_save_state(dev, config);
8122 if (ret)
8123 goto out_config;
8124
8125 save_set.crtc = set->crtc;
8126 save_set.mode = &set->crtc->mode;
8127 save_set.x = set->crtc->x;
8128 save_set.y = set->crtc->y;
8129 save_set.fb = set->crtc->fb;
8130
8131 /* Compute whether we need a full modeset, only an fb base update or no
8132 * change at all. In the future we might also check whether only the
8133 * mode changed, e.g. for LVDS where we only change the panel fitter in
8134 * such cases. */
8135 intel_set_config_compute_mode_changes(set, config);
8136
9a935856 8137 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8138 if (ret)
8139 goto fail;
8140
5e2b584e 8141 if (config->mode_changed) {
87f1faa6 8142 if (set->mode) {
50f56119
DV		 8143 DRM_DEBUG_KMS("attempting to set mode from"
8144 " userspace\n");
8145 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8146 }
8147
c0c36b94
CW		 8148 ret = intel_set_mode(set->crtc, set->mode,
8149 set->x, set->y, set->fb);
8150 if (ret) {
8151 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8152 set->crtc->base.id, ret);
87f1faa6
DV		 8153 goto fail;
8154 }
5e2b584e 8155 } else if (config->fb_changed) {
4878cae2
VS		 8156 intel_crtc_wait_for_pending_flips(set->crtc);
8157
4f660f49 8158 ret = intel_pipe_set_base(set->crtc,
94352cf9 8159 set->x, set->y, set->fb);
50f56119
DV		 8160 }
8161
d9e55608
DV		 8162 intel_set_config_free(config);
8163
50f56119
DV		 8164 return 0;
8165
8166fail:
85f9eb71 8167 intel_set_config_restore_state(dev, config);
50f56119
DV		 8168
8169 /* Try to restore the config */
5e2b584e 8170 if (config->mode_changed &&
c0c36b94
CW		 8171 intel_set_mode(save_set.crtc, save_set.mode,
8172 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8173 DRM_ERROR("failed to restore config after modeset failure\n");
8174
d9e55608
DV		 8175out_config:
8176 intel_set_config_free(config);
50f56119
DV		 8177 return ret;
8178}
f6e5b160
CW		 8179
8180static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8181 .cursor_set = intel_crtc_cursor_set,
8182 .cursor_move = intel_crtc_cursor_move,
8183 .gamma_set = intel_crtc_gamma_set,
50f56119 8184 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8185 .destroy = intel_crtc_destroy,
8186 .page_flip = intel_crtc_page_flip,
8187};
8188
79f689aa
PZ		 8189static void intel_cpu_pll_init(struct drm_device *dev)
8190{
affa9354 8191 if (HAS_DDI(dev))
79f689aa
PZ		 8192 intel_ddi_pll_init(dev);
8193}
8194
ee7b9f93
JB		 8195static void intel_pch_pll_init(struct drm_device *dev)
8196{
8197 drm_i915_private_t *dev_priv = dev->dev_private;
8198 int i;
8199
8200 if (dev_priv->num_pch_pll == 0) {
8201 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8202 return;
8203 }
8204
8205 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8206 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8207 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8208 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8209 }
8210}
8211
b358d0a6 8212static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8213{
22fd0fab 8214 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8215 struct intel_crtc *intel_crtc;
8216 int i;
8217
8218 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8219 if (intel_crtc == NULL)
8220 return;
8221
8222 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8223
8224 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8225 for (i = 0; i < 256; i++) {
8226 intel_crtc->lut_r[i] = i;
8227 intel_crtc->lut_g[i] = i;
8228 intel_crtc->lut_b[i] = i;
8229 }
8230
80824003
JB		 8231 /* Swap pipes & planes for FBC on pre-965 */
8232 intel_crtc->pipe = pipe;
8233 intel_crtc->plane = pipe;
a5c961d1 8234 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8235 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8236 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8237 intel_crtc->plane = !pipe;
80824003
JB		 8238 }
8239
22fd0fab
JB		 8240 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8241 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8242 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8243 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8244
5a354204 8245 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8246
79e53945 8247 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8248}
8249
08d7b3d1 8250int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8251 struct drm_file *file)
08d7b3d1 8252{
08d7b3d1 8253 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8254 struct drm_mode_object *drmmode_obj;
8255 struct intel_crtc *crtc;
08d7b3d1 8256
1cff8f6b
DV		 8257 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8258 return -ENODEV;
08d7b3d1 8259
c05422d5
DV		 8260 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8261 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8262
c05422d5 8263 if (!drmmode_obj) {
08d7b3d1
CW		 8264 DRM_ERROR("no such CRTC id\n");
8265 return -EINVAL;
8266 }
8267
c05422d5
DV		 8268 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8269 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8270
c05422d5 8271 return 0;
08d7b3d1
CW		 8272}
8273
66a9278e 8274static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8275{
66a9278e
DV		 8276 struct drm_device *dev = encoder->base.dev;
8277 struct intel_encoder *source_encoder;
79e53945 8278 int index_mask = 0;
79e53945
JB		 8279 int entry = 0;
8280
66a9278e
DV		 8281 list_for_each_entry(source_encoder,
8282 &dev->mode_config.encoder_list, base.head) {
8283
8284 if (encoder == source_encoder)
79e53945 8285 index_mask |= (1 << entry);
66a9278e
DV		 8286
8287 /* Intel hw has only one MUX where enocoders could be cloned. */
8288 if (encoder->cloneable && source_encoder->cloneable)
8289 index_mask |= (1 << entry);
8290
79e53945
JB		 8291 entry++;
8292 }
4ef69c7a 8293
79e53945
JB		 8294 return index_mask;
8295}
8296
4d302442
CW		 8297static bool has_edp_a(struct drm_device *dev)
8298{
8299 struct drm_i915_private *dev_priv = dev->dev_private;
8300
8301 if (!IS_MOBILE(dev))
8302 return false;
8303
8304 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8305 return false;
8306
8307 if (IS_GEN5(dev) &&
8308 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8309 return false;
8310
8311 return true;
8312}
8313
79e53945
JB		 8314static void intel_setup_outputs(struct drm_device *dev)
8315{
725e30ad 8316 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8317 struct intel_encoder *encoder;
cb0953d7 8318 bool dpd_is_edp = false;
f3cfcba6 8319 bool has_lvds;
79e53945 8320
f3cfcba6 8321 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8322 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8323 /* disable the panel fitter on everything but LVDS */
8324 I915_WRITE(PFIT_CONTROL, 0);
8325 }
79e53945 8326
affa9354 8327 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8328 intel_crt_init(dev);
cb0953d7 8329
affa9354 8330 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8331 int found;
8332
8333 /* Haswell uses DDI functions to detect digital outputs */
8334 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8335 /* DDI A only supports eDP */
8336 if (found)
8337 intel_ddi_init(dev, PORT_A);
8338
8339 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8340 * register */
8341 found = I915_READ(SFUSE_STRAP);
8342
8343 if (found & SFUSE_STRAP_DDIB_DETECTED)
8344 intel_ddi_init(dev, PORT_B);
8345 if (found & SFUSE_STRAP_DDIC_DETECTED)
8346 intel_ddi_init(dev, PORT_C);
8347 if (found & SFUSE_STRAP_DDID_DETECTED)
8348 intel_ddi_init(dev, PORT_D);
8349 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8350 int found;
270b3042
DV		 8351 dpd_is_edp = intel_dpd_is_edp(dev);
8352
8353 if (has_edp_a(dev))
8354 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8355
30ad48b7 8356 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8357 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8358 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8359 if (!found)
08d644ad 8360 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8361 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8362 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8363 }
8364
8365 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8366 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8367
b708a1d5 8368 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8369 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8370
5eb08b69 8371 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8372 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8373
270b3042 8374 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8375 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8376 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8377 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8378 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8379 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8380
67cfc203
VS		 8381 if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
8382 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
8383 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8384 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d
JB		 8385 }
8386
67cfc203
VS		 8387 if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
8388 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
5eb08b69 8389
103a196f 8390 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8391 bool found = false;
7d57382e 8392
725e30ad 8393 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8394 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8395 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8396 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8397 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8398 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8399 }
27185ae1 8400
b01f2c3a
JB		 8401 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8402 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8403 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8404 }
725e30ad 8405 }
13520b05
KH		 8406
8407 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8408
b01f2c3a
JB		 8409 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8410 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8411 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8412 }
27185ae1
ML		 8413
8414 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8415
b01f2c3a
JB		 8416 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8417 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8418 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8419 }
8420 if (SUPPORTS_INTEGRATED_DP(dev)) {
8421 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8422 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8423 }
725e30ad 8424 }
27185ae1 8425
b01f2c3a
JB		 8426 if (SUPPORTS_INTEGRATED_DP(dev) &&
8427 (I915_READ(DP_D) & DP_DETECTED)) {
8428 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8429 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8430 }
bad720ff 8431 } else if (IS_GEN2(dev))
79e53945
JB		 8432 intel_dvo_init(dev);
8433
103a196f 8434 if (SUPPORTS_TV(dev))
79e53945
JB		 8435 intel_tv_init(dev);
8436
4ef69c7a
CW		 8437 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8438 encoder->base.possible_crtcs = encoder->crtc_mask;
8439 encoder->base.possible_clones =
66a9278e 8440 intel_encoder_clones(encoder);
79e53945 8441 }
47356eb6 8442
dde86e2d 8443 intel_init_pch_refclk(dev);
270b3042
DV		 8444
8445 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8446}
8447
8448static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8449{
8450 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8451
8452 drm_framebuffer_cleanup(fb);
05394f39 8453 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8454
8455 kfree(intel_fb);
8456}
8457
8458static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8459 struct drm_file *file,
79e53945
JB		 8460 unsigned int *handle)
8461{
8462 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8463 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8464
05394f39 8465 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8466}
8467
8468static const struct drm_framebuffer_funcs intel_fb_funcs = {
8469 .destroy = intel_user_framebuffer_destroy,
8470 .create_handle = intel_user_framebuffer_create_handle,
8471};
8472
38651674
DA		 8473int intel_framebuffer_init(struct drm_device *dev,
8474 struct intel_framebuffer *intel_fb,
308e5bcb 8475 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8476 struct drm_i915_gem_object *obj)
79e53945 8477{
79e53945
JB		 8478 int ret;
8479
c16ed4be
CW		 8480 if (obj->tiling_mode == I915_TILING_Y) {
8481 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8482 return -EINVAL;
c16ed4be 8483 }
57cd6508 8484
c16ed4be
CW		 8485 if (mode_cmd->pitches[0] & 63) {
8486 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8487 mode_cmd->pitches[0]);
57cd6508 8488 return -EINVAL;
c16ed4be 8489 }
57cd6508 8490
5d7bd705 8491 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8492 if (mode_cmd->pitches[0] > 32768) {
8493 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8494 mode_cmd->pitches[0]);
5d7bd705 8495 return -EINVAL;
c16ed4be 8496 }
5d7bd705
VS		 8497
8498 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8499 mode_cmd->pitches[0] != obj->stride) {
8500 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8501 mode_cmd->pitches[0], obj->stride);
5d7bd705 8502 return -EINVAL;
c16ed4be 8503 }
5d7bd705 8504
57779d06 8505 /* Reject formats not supported by any plane early. */
308e5bcb 8506 switch (mode_cmd->pixel_format) {
57779d06 8507 case DRM_FORMAT_C8:
04b3924d
VS		 8508 case DRM_FORMAT_RGB565:
8509 case DRM_FORMAT_XRGB8888:
8510 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8511 break;
8512 case DRM_FORMAT_XRGB1555:
8513 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8514 if (INTEL_INFO(dev)->gen > 3) {
8515 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8516 return -EINVAL;
c16ed4be 8517 }
57779d06
VS		 8518 break;
8519 case DRM_FORMAT_XBGR8888:
8520 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8521 case DRM_FORMAT_XRGB2101010:
8522 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8523 case DRM_FORMAT_XBGR2101010:
8524 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8525 if (INTEL_INFO(dev)->gen < 4) {
8526 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8527 return -EINVAL;
c16ed4be 8528 }
b5626747 8529 break;
04b3924d
VS		 8530 case DRM_FORMAT_YUYV:
8531 case DRM_FORMAT_UYVY:
8532 case DRM_FORMAT_YVYU:
8533 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8534 if (INTEL_INFO(dev)->gen < 5) {
8535 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8536 return -EINVAL;
c16ed4be 8537 }
57cd6508
CW		 8538 break;
8539 default:
c16ed4be 8540 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8541 return -EINVAL;
8542 }
8543
90f9a336
VS		 8544 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8545 if (mode_cmd->offsets[0] != 0)
8546 return -EINVAL;
8547
c7d73f6a
DV		 8548 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8549 intel_fb->obj = obj;
8550
79e53945
JB		 8551 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8552 if (ret) {
8553 DRM_ERROR("framebuffer init failed %d\n", ret);
8554 return ret;
8555 }
8556
79e53945
JB		 8557 return 0;
8558}
8559
79e53945
JB		 8560static struct drm_framebuffer *
8561intel_user_framebuffer_create(struct drm_device *dev,
8562 struct drm_file *filp,
308e5bcb 8563 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8564{
05394f39 8565 struct drm_i915_gem_object *obj;
79e53945 8566
308e5bcb
JB		 8567 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8568 mode_cmd->handles[0]));
c8725226 8569 if (&obj->base == NULL)
cce13ff7 8570 return ERR_PTR(-ENOENT);
79e53945 8571
d2dff872 8572 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8573}
8574
79e53945 8575static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8576 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8577 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8578};
8579
e70236a8
JB		 8580/* Set up chip specific display functions */
8581static void intel_init_display(struct drm_device *dev)
8582{
8583 struct drm_i915_private *dev_priv = dev->dev_private;
8584
8585 /* We always want a DPMS function */
affa9354 8586 if (HAS_DDI(dev)) {
09b4ddf9 8587 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8588 dev_priv->display.crtc_enable = haswell_crtc_enable;
8589 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8590 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8591 dev_priv->display.update_plane = ironlake_update_plane;
8592 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8593 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8594 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8595 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8596 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8597 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8598 } else {
f564048e 8599 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8600 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8601 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8602 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8603 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8604 }
e70236a8 8605
e70236a8 8606 /* Returns the core display clock speed */
25eb05fc
JB		 8607 if (IS_VALLEYVIEW(dev))
8608 dev_priv->display.get_display_clock_speed =
8609 valleyview_get_display_clock_speed;
8610 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8611 dev_priv->display.get_display_clock_speed =
8612 i945_get_display_clock_speed;
8613 else if (IS_I915G(dev))
8614 dev_priv->display.get_display_clock_speed =
8615 i915_get_display_clock_speed;
f2b115e6 8616 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8617 dev_priv->display.get_display_clock_speed =
8618 i9xx_misc_get_display_clock_speed;
8619 else if (IS_I915GM(dev))
8620 dev_priv->display.get_display_clock_speed =
8621 i915gm_get_display_clock_speed;
8622 else if (IS_I865G(dev))
8623 dev_priv->display.get_display_clock_speed =
8624 i865_get_display_clock_speed;
f0f8a9ce 8625 else if (IS_I85X(dev))
e70236a8
JB		 8626 dev_priv->display.get_display_clock_speed =
8627 i855_get_display_clock_speed;
8628 else /* 852, 830 */
8629 dev_priv->display.get_display_clock_speed =
8630 i830_get_display_clock_speed;
8631
7f8a8569 8632 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8633 if (IS_GEN5(dev)) {
674cf967 8634 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8635 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8636 } else if (IS_GEN6(dev)) {
674cf967 8637 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8638 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8639 } else if (IS_IVYBRIDGE(dev)) {
8640 /* FIXME: detect B0+ stepping and use auto training */
8641 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8642 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8643 dev_priv->display.modeset_global_resources =
8644 ivb_modeset_global_resources;
c82e4d26
ED		 8645 } else if (IS_HASWELL(dev)) {
8646 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8647 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8648 dev_priv->display.modeset_global_resources =
8649 haswell_modeset_global_resources;
a0e63c22 8650 }
6067aaea 8651 } else if (IS_G4X(dev)) {
e0dac65e 8652 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8653 }
8c9f3aaf
JB		 8654
8655 /* Default just returns -ENODEV to indicate unsupported */
8656 dev_priv->display.queue_flip = intel_default_queue_flip;
8657
8658 switch (INTEL_INFO(dev)->gen) {
8659 case 2:
8660 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8661 break;
8662
8663 case 3:
8664 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8665 break;
8666
8667 case 4:
8668 case 5:
8669 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8670 break;
8671
8672 case 6:
8673 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8674 break;
7c9017e5
JB		 8675 case 7:
8676 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8677 break;
8c9f3aaf 8678 }
e70236a8
JB		 8679}
8680
b690e96c
JB		 8681/*
8682 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8683 * resume, or other times. This quirk makes sure that's the case for
8684 * affected systems.
8685 */
0206e353 8686static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8687{
8688 struct drm_i915_private *dev_priv = dev->dev_private;
8689
8690 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8691 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8692}
8693
435793df
KP		 8694/*
8695 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8696 */
8697static void quirk_ssc_force_disable(struct drm_device *dev)
8698{
8699 struct drm_i915_private *dev_priv = dev->dev_private;
8700 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8701 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8702}
8703
4dca20ef 8704/*
5a15ab5b
CE		 8705 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8706 * brightness value
4dca20ef
CE		 8707 */
8708static void quirk_invert_brightness(struct drm_device *dev)
8709{
8710 struct drm_i915_private *dev_priv = dev->dev_private;
8711 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8712 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8713}
8714
b690e96c
JB		 8715struct intel_quirk {
8716 int device;
8717 int subsystem_vendor;
8718 int subsystem_device;
8719 void (*hook)(struct drm_device *dev);
8720};
8721
5f85f176
EE		 8722/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8723struct intel_dmi_quirk {
8724 void (*hook)(struct drm_device *dev);
8725 const struct dmi_system_id (*dmi_id_list)[];
8726};
8727
8728static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8729{
8730 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8731 return 1;
8732}
8733
8734static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8735 {
8736 .dmi_id_list = &(const struct dmi_system_id[]) {
8737 {
8738 .callback = intel_dmi_reverse_brightness,
8739 .ident = "NCR Corporation",
8740 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8741 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8742 },
8743 },
8744 { } /* terminating entry */
8745 },
8746 .hook = quirk_invert_brightness,
8747 },
8748};
8749
c43b5634 8750static struct intel_quirk intel_quirks[] = {
b690e96c 8751 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8752 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8753
b690e96c
JB		 8754 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8755 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8756
b690e96c
JB		 8757 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8758 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8759
ccd0d36e 8760 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8761 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8762 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8763
8764 /* Lenovo U160 cannot use SSC on LVDS */
8765 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8766
8767 /* Sony Vaio Y cannot use SSC on LVDS */
8768 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8769
8770 /* Acer Aspire 5734Z must invert backlight brightness */
8771 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8772
8773 /* Acer/eMachines G725 */
8774 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8775
8776 /* Acer/eMachines e725 */
8777 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8778
8779 /* Acer/Packard Bell NCL20 */
8780 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 8781
8782 /* Acer Aspire 4736Z */
8783 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 8784};
8785
8786static void intel_init_quirks(struct drm_device *dev)
8787{
8788 struct pci_dev *d = dev->pdev;
8789 int i;
8790
8791 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8792 struct intel_quirk *q = &intel_quirks[i];
8793
8794 if (d->device == q->device &&
8795 (d->subsystem_vendor == q->subsystem_vendor ||
8796 q->subsystem_vendor == PCI_ANY_ID) &&
8797 (d->subsystem_device == q->subsystem_device ||
8798 q->subsystem_device == PCI_ANY_ID))
8799 q->hook(dev);
8800 }
5f85f176
EE		 8801 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8802 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8803 intel_dmi_quirks[i].hook(dev);
8804 }
b690e96c
JB		 8805}
8806
9cce37f4
JB		 8807/* Disable the VGA plane that we never use */
8808static void i915_disable_vga(struct drm_device *dev)
8809{
8810 struct drm_i915_private *dev_priv = dev->dev_private;
8811 u8 sr1;
766aa1c4 8812 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 8813
8814 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8815 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8816 sr1 = inb(VGA_SR_DATA);
8817 outb(sr1 | 1<<5, VGA_SR_DATA);
8818 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8819 udelay(300);
8820
8821 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8822 POSTING_READ(vga_reg);
8823}
8824
f817586c
DV		 8825void intel_modeset_init_hw(struct drm_device *dev)
8826{
fa42e23c 8827 intel_init_power_well(dev);
0232e927 8828
a8f78b58
ED		 8829 intel_prepare_ddi(dev);
8830
f817586c
DV		 8831 intel_init_clock_gating(dev);
8832
79f5b2c7 8833 mutex_lock(&dev->struct_mutex);
8090c6b9 8834 intel_enable_gt_powersave(dev);
79f5b2c7 8835 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8836}
8837
79e53945
JB		 8838void intel_modeset_init(struct drm_device *dev)
8839{
652c393a 8840 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8841 int i, ret;
79e53945
JB		 8842
8843 drm_mode_config_init(dev);
8844
8845 dev->mode_config.min_width = 0;
8846 dev->mode_config.min_height = 0;
8847
019d96cb
DA		 8848 dev->mode_config.preferred_depth = 24;
8849 dev->mode_config.prefer_shadow = 1;
8850
e6ecefaa 8851 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8852
b690e96c
JB		 8853 intel_init_quirks(dev);
8854
1fa61106
ED		 8855 intel_init_pm(dev);
8856
e70236a8
JB		 8857 intel_init_display(dev);
8858
a6c45cf0
CW		 8859 if (IS_GEN2(dev)) {
8860 dev->mode_config.max_width = 2048;
8861 dev->mode_config.max_height = 2048;
8862 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8863 dev->mode_config.max_width = 4096;
8864 dev->mode_config.max_height = 4096;
79e53945 8865 } else {
a6c45cf0
CW		 8866 dev->mode_config.max_width = 8192;
8867 dev->mode_config.max_height = 8192;
79e53945 8868 }
5d4545ae 8869 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 8870
28c97730 8871 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8872 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8873
a3524f1b 8874 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8875 intel_crtc_init(dev, i);
00c2064b
JB		 8876 ret = intel_plane_init(dev, i);
8877 if (ret)
8878 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8879 }
8880
79f689aa 8881 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8882 intel_pch_pll_init(dev);
8883
9cce37f4
JB		 8884 /* Just disable it once at startup */
8885 i915_disable_vga(dev);
79e53945 8886 intel_setup_outputs(dev);
11be49eb
CW		 8887
8888 /* Just in case the BIOS is doing something questionable. */
8889 intel_disable_fbc(dev);
2c7111db
CW		 8890}
8891
24929352
DV		 8892static void
8893intel_connector_break_all_links(struct intel_connector *connector)
8894{
8895 connector->base.dpms = DRM_MODE_DPMS_OFF;
8896 connector->base.encoder = NULL;
8897 connector->encoder->connectors_active = false;
8898 connector->encoder->base.crtc = NULL;
8899}
8900
7fad798e
DV		 8901static void intel_enable_pipe_a(struct drm_device *dev)
8902{
8903 struct intel_connector *connector;
8904 struct drm_connector *crt = NULL;
8905 struct intel_load_detect_pipe load_detect_temp;
8906
8907 /* We can't just switch on the pipe A, we need to set things up with a
8908 * proper mode and output configuration. As a gross hack, enable pipe A
8909 * by enabling the load detect pipe once. */
8910 list_for_each_entry(connector,
8911 &dev->mode_config.connector_list,
8912 base.head) {
8913 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8914 crt = &connector->base;
8915 break;
8916 }
8917 }
8918
8919 if (!crt)
8920 return;
8921
8922 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8923 intel_release_load_detect_pipe(crt, &load_detect_temp);
8924
652c393a 8925
7fad798e
DV		 8926}
8927
fa555837
DV		 8928static bool
8929intel_check_plane_mapping(struct intel_crtc *crtc)
8930{
8931 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8932 u32 reg, val;
8933
8934 if (dev_priv->num_pipe == 1)
8935 return true;
8936
8937 reg = DSPCNTR(!crtc->plane);
8938 val = I915_READ(reg);
8939
8940 if ((val & DISPLAY_PLANE_ENABLE) &&
8941 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8942 return false;
8943
8944 return true;
8945}
8946
24929352
DV		 8947static void intel_sanitize_crtc(struct intel_crtc *crtc)
8948{
8949 struct drm_device *dev = crtc->base.dev;
8950 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8951 u32 reg;
24929352 8952
24929352 8953 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8954 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8955 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8956
8957 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8958 * disable the crtc (and hence change the state) if it is wrong. Note
8959 * that gen4+ has a fixed plane -> pipe mapping. */
8960 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8961 struct intel_connector *connector;
8962 bool plane;
8963
24929352
DV		 8964 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8965 crtc->base.base.id);
8966
8967 /* Pipe has the wrong plane attached and the plane is active.
8968 * Temporarily change the plane mapping and disable everything
8969 * ... */
8970 plane = crtc->plane;
8971 crtc->plane = !plane;
8972 dev_priv->display.crtc_disable(&crtc->base);
8973 crtc->plane = plane;
8974
8975 /* ... and break all links. */
8976 list_for_each_entry(connector, &dev->mode_config.connector_list,
8977 base.head) {
8978 if (connector->encoder->base.crtc != &crtc->base)
8979 continue;
8980
8981 intel_connector_break_all_links(connector);
8982 }
8983
8984 WARN_ON(crtc->active);
8985 crtc->base.enabled = false;
8986 }
24929352 8987
7fad798e
DV		 8988 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8989 crtc->pipe == PIPE_A && !crtc->active) {
8990 /* BIOS forgot to enable pipe A, this mostly happens after
8991 * resume. Force-enable the pipe to fix this, the update_dpms
8992 * call below we restore the pipe to the right state, but leave
8993 * the required bits on. */
8994 intel_enable_pipe_a(dev);
8995 }
8996
24929352
DV		 8997 /* Adjust the state of the output pipe according to whether we
8998 * have active connectors/encoders. */
8999 intel_crtc_update_dpms(&crtc->base);
9000
9001 if (crtc->active != crtc->base.enabled) {
9002 struct intel_encoder *encoder;
9003
9004 /* This can happen either due to bugs in the get_hw_state
9005 * functions or because the pipe is force-enabled due to the
9006 * pipe A quirk. */
9007 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9008 crtc->base.base.id,
9009 crtc->base.enabled ? "enabled" : "disabled",
9010 crtc->active ? "enabled" : "disabled");
9011
9012 crtc->base.enabled = crtc->active;
9013
9014 /* Because we only establish the connector -> encoder ->
9015 * crtc links if something is active, this means the
9016 * crtc is now deactivated. Break the links. connector
9017 * -> encoder links are only establish when things are
9018 * actually up, hence no need to break them. */
9019 WARN_ON(crtc->active);
9020
9021 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9022 WARN_ON(encoder->connectors_active);
9023 encoder->base.crtc = NULL;
9024 }
9025 }
9026}
9027
9028static void intel_sanitize_encoder(struct intel_encoder *encoder)
9029{
9030 struct intel_connector *connector;
9031 struct drm_device *dev = encoder->base.dev;
9032
9033 /* We need to check both for a crtc link (meaning that the
9034 * encoder is active and trying to read from a pipe) and the
9035 * pipe itself being active. */
9036 bool has_active_crtc = encoder->base.crtc &&
9037 to_intel_crtc(encoder->base.crtc)->active;
9038
9039 if (encoder->connectors_active && !has_active_crtc) {
9040 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9041 encoder->base.base.id,
9042 drm_get_encoder_name(&encoder->base));
9043
9044 /* Connector is active, but has no active pipe. This is
9045 * fallout from our resume register restoring. Disable
9046 * the encoder manually again. */
9047 if (encoder->base.crtc) {
9048 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9049 encoder->base.base.id,
9050 drm_get_encoder_name(&encoder->base));
9051 encoder->disable(encoder);
9052 }
9053
9054 /* Inconsistent output/port/pipe state happens presumably due to
9055 * a bug in one of the get_hw_state functions. Or someplace else
9056 * in our code, like the register restore mess on resume. Clamp
9057 * things to off as a safer default. */
9058 list_for_each_entry(connector,
9059 &dev->mode_config.connector_list,
9060 base.head) {
9061 if (connector->encoder != encoder)
9062 continue;
9063
9064 intel_connector_break_all_links(connector);
9065 }
9066 }
9067 /* Enabled encoders without active connectors will be fixed in
9068 * the crtc fixup. */
9069}
9070
44cec740 9071void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9072{
9073 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9074 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9075
9076 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9077 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9078 i915_disable_vga(dev);
0fde901f
KM		 9079 }
9080}
9081
24929352
DV		 9082/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9083 * and i915 state tracking structures. */
45e2b5f6
DV		 9084void intel_modeset_setup_hw_state(struct drm_device *dev,
9085 bool force_restore)
24929352
DV		 9086{
9087 struct drm_i915_private *dev_priv = dev->dev_private;
9088 enum pipe pipe;
9089 u32 tmp;
9090 struct intel_crtc *crtc;
9091 struct intel_encoder *encoder;
9092 struct intel_connector *connector;
9093
affa9354 9094 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9095 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9096
9097 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9098 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9099 case TRANS_DDI_EDP_INPUT_A_ON:
9100 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9101 pipe = PIPE_A;
9102 break;
9103 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9104 pipe = PIPE_B;
9105 break;
9106 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9107 pipe = PIPE_C;
9108 break;
9109 }
9110
9111 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9112 crtc->cpu_transcoder = TRANSCODER_EDP;
9113
9114 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9115 pipe_name(pipe));
9116 }
9117 }
9118
24929352
DV		 9119 for_each_pipe(pipe) {
9120 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9121
702e7a56 9122 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9123 if (tmp & PIPECONF_ENABLE)
9124 crtc->active = true;
9125 else
9126 crtc->active = false;
9127
9128 crtc->base.enabled = crtc->active;
9129
9130 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9131 crtc->base.base.id,
9132 crtc->active ? "enabled" : "disabled");
9133 }
9134
affa9354 9135 if (HAS_DDI(dev))
6441ab5f
PZ		 9136 intel_ddi_setup_hw_pll_state(dev);
9137
24929352
DV		 9138 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9139 base.head) {
9140 pipe = 0;
9141
9142 if (encoder->get_hw_state(encoder, &pipe)) {
9143 encoder->base.crtc =
9144 dev_priv->pipe_to_crtc_mapping[pipe];
9145 } else {
9146 encoder->base.crtc = NULL;
9147 }
9148
9149 encoder->connectors_active = false;
9150 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9151 encoder->base.base.id,
9152 drm_get_encoder_name(&encoder->base),
9153 encoder->base.crtc ? "enabled" : "disabled",
9154 pipe);
9155 }
9156
9157 list_for_each_entry(connector, &dev->mode_config.connector_list,
9158 base.head) {
9159 if (connector->get_hw_state(connector)) {
9160 connector->base.dpms = DRM_MODE_DPMS_ON;
9161 connector->encoder->connectors_active = true;
9162 connector->base.encoder = &connector->encoder->base;
9163 } else {
9164 connector->base.dpms = DRM_MODE_DPMS_OFF;
9165 connector->base.encoder = NULL;
9166 }
9167 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9168 connector->base.base.id,
9169 drm_get_connector_name(&connector->base),
9170 connector->base.encoder ? "enabled" : "disabled");
9171 }
9172
9173 /* HW state is read out, now we need to sanitize this mess. */
9174 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9175 base.head) {
9176 intel_sanitize_encoder(encoder);
9177 }
9178
9179 for_each_pipe(pipe) {
9180 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9181 intel_sanitize_crtc(crtc);
9182 }
9a935856 9183
45e2b5f6
DV		 9184 if (force_restore) {
9185 for_each_pipe(pipe) {
c0c36b94 9186 intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
45e2b5f6 9187 }
0fde901f
KM		 9188
9189 i915_redisable_vga(dev);
45e2b5f6
DV		 9190 } else {
9191 intel_modeset_update_staged_output_state(dev);
9192 }
8af6cf88
DV		 9193
9194 intel_modeset_check_state(dev);
2e938892
DV		 9195
9196 drm_mode_config_reset(dev);
2c7111db
CW		 9197}
9198
9199void intel_modeset_gem_init(struct drm_device *dev)
9200{
1833b134 9201 intel_modeset_init_hw(dev);
02e792fb
DV		 9202
9203 intel_setup_overlay(dev);
24929352 9204
45e2b5f6 9205 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9206}
9207
9208void intel_modeset_cleanup(struct drm_device *dev)
9209{
652c393a
JB		 9210 struct drm_i915_private *dev_priv = dev->dev_private;
9211 struct drm_crtc *crtc;
9212 struct intel_crtc *intel_crtc;
9213
f87ea761 9214 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9215 mutex_lock(&dev->struct_mutex);
9216
723bfd70
JB		 9217 intel_unregister_dsm_handler();
9218
9219
652c393a
JB		 9220 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9221 /* Skip inactive CRTCs */
9222 if (!crtc->fb)
9223 continue;
9224
9225 intel_crtc = to_intel_crtc(crtc);
3dec0095 9226 intel_increase_pllclock(crtc);
652c393a
JB		 9227 }
9228
973d04f9 9229 intel_disable_fbc(dev);
e70236a8 9230
8090c6b9 9231 intel_disable_gt_powersave(dev);
0cdab21f 9232
930ebb46
DV		 9233 ironlake_teardown_rc6(dev);
9234
57f350b6
JB		 9235 if (IS_VALLEYVIEW(dev))
9236 vlv_init_dpio(dev);
9237
69341a5e
KH		 9238 mutex_unlock(&dev->struct_mutex);
9239
6c0d9350
DV		 9240 /* Disable the irq before mode object teardown, for the irq might
9241 * enqueue unpin/hotplug work. */
9242 drm_irq_uninstall(dev);
9243 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9244 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9245
1630fe75
CW		 9246 /* flush any delayed tasks or pending work */
9247 flush_scheduled_work();
9248
79e53945 9249 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9250
9251 intel_cleanup_overlay(dev);
79e53945
JB		 9252}
9253
f1c79df3
ZW		 9254/*
9255 * Return which encoder is currently attached for connector.
9256 */
df0e9248 9257struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9258{
df0e9248
CW		 9259 return &intel_attached_encoder(connector)->base;
9260}
f1c79df3 9261
df0e9248
CW		 9262void intel_connector_attach_encoder(struct intel_connector *connector,
9263 struct intel_encoder *encoder)
9264{
9265 connector->encoder = encoder;
9266 drm_mode_connector_attach_encoder(&connector->base,
9267 &encoder->base);
79e53945 9268}
28d52043
DA		 9269
9270/*
9271 * set vga decode state - true == enable VGA decode
9272 */
9273int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9274{
9275 struct drm_i915_private *dev_priv = dev->dev_private;
9276 u16 gmch_ctrl;
9277
9278 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9279 if (state)
9280 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9281 else
9282 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9283 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9284 return 0;
9285}
c4a1d9e4
CW		 9286
9287#ifdef CONFIG_DEBUG_FS
9288#include <linux/seq_file.h>
9289
9290struct intel_display_error_state {
9291 struct intel_cursor_error_state {
9292 u32 control;
9293 u32 position;
9294 u32 base;
9295 u32 size;
52331309 9296 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9297
9298 struct intel_pipe_error_state {
9299 u32 conf;
9300 u32 source;
9301
9302 u32 htotal;
9303 u32 hblank;
9304 u32 hsync;
9305 u32 vtotal;
9306 u32 vblank;
9307 u32 vsync;
52331309 9308 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9309
9310 struct intel_plane_error_state {
9311 u32 control;
9312 u32 stride;
9313 u32 size;
9314 u32 pos;
9315 u32 addr;
9316 u32 surface;
9317 u32 tile_offset;
52331309 9318 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9319};
9320
9321struct intel_display_error_state *
9322intel_display_capture_error_state(struct drm_device *dev)
9323{
0206e353 9324 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9325 struct intel_display_error_state *error;
702e7a56 9326 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9327 int i;
9328
9329 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9330 if (error == NULL)
9331 return NULL;
9332
52331309 9333 for_each_pipe(i) {
702e7a56
PZ		 9334 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9335
c4a1d9e4
CW		 9336 error->cursor[i].control = I915_READ(CURCNTR(i));
9337 error->cursor[i].position = I915_READ(CURPOS(i));
9338 error->cursor[i].base = I915_READ(CURBASE(i));
9339
9340 error->plane[i].control = I915_READ(DSPCNTR(i));
9341 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9342 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9343 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9344 error->plane[i].addr = I915_READ(DSPADDR(i));
9345 if (INTEL_INFO(dev)->gen >= 4) {
9346 error->plane[i].surface = I915_READ(DSPSURF(i));
9347 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9348 }
9349
702e7a56 9350 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9351 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9352 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9353 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9354 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9355 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9356 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9357 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9358 }
9359
9360 return error;
9361}
9362
9363void
9364intel_display_print_error_state(struct seq_file *m,
9365 struct drm_device *dev,
9366 struct intel_display_error_state *error)
9367{
52331309 9368 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9369 int i;
9370
52331309
DL		 9371 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9372 for_each_pipe(i) {
c4a1d9e4
CW		 9373 seq_printf(m, "Pipe [%d]:\n", i);
9374 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9375 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9376 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9377 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9378 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9379 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9380 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9381 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9382
9383 seq_printf(m, "Plane [%d]:\n", i);
9384 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9385 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9386 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9387 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9388 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9389 if (INTEL_INFO(dev)->gen >= 4) {
9390 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9391 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9392 }
9393
9394 seq_printf(m, "Cursor [%d]:\n", i);
9395 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9396 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9397 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9398 }
9399}
9400#endif
Linux kernel - Deliverables
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