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drm/i915: unify the definitions of the HDMI/SDVO register
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
f4808ab8
VS		 74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
d4906093 92};
79e53945 93
2377b741
JB		 94/* FDI */
95#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
d2acd215
DV		 97int
98intel_pch_rawclk(struct drm_device *dev)
99{
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105}
106
d4906093
ML		 107static bool
108intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
d4906093
ML		 111static bool
112intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
79e53945 115
a4fc5ed6
KP		 116static bool
117intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
5eb08b69 120static bool
f2b115e6 121intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
a4fc5ed6 124
a0c4da24
JB		 125static bool
126intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
021357ac
CW		 130static inline u32 /* units of 100MHz */
131intel_fdi_link_freq(struct drm_device *dev)
132{
8b99e68c
CW		 133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
021357ac
CW		 138}
139
e4b36699 140static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699 166};
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
d4906093 193 .find_pll = intel_find_best_PLL,
e4b36699
KP		 194};
195
273e27ca 196
e4b36699 197static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
d4906093 224 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 225};
226
227static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
044c7c41 238 },
d4906093 239 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
044c7c41 253 },
d4906093 254 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 255};
256
257static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
273e27ca 267 .p2_slow = 10, .p2_fast = 10 },
0206e353 268 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 274 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
273e27ca 277 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
f2b115e6 287static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
6115707b 298 .find_pll = intel_find_best_PLL,
e4b36699
KP		 299};
300
273e27ca
EA		 301/* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
4547668a 317 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 318};
319
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
273e27ca 348/* LVDS 100mhz refclk limits. */
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
0206e353 357 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
0206e353 371 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 374 .find_pll = intel_g4x_find_best_PLL,
375};
376
377static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
273e27ca 387 .p2_slow = 10, .p2_fast = 10 },
0206e353 388 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 389};
390
a0c4da24
JB		 391static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
17dc9257 407 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
419static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 422 .n = { .min = 1, .max = 7 },
74a4dd2e 423 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431};
432
57f350b6
JB		 433u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434{
09153000 435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 436
57f350b6
JB		 437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
09153000 439 return 0;
57f350b6
JB		 440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
09153000 447 return 0;
57f350b6 448 }
57f350b6 449
09153000 450 return I915_READ(DPIO_DATA);
57f350b6
JB		 451}
452
a0c4da24
JB		 453static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455{
09153000 456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 457
a0c4da24
JB		 458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
09153000 460 return;
a0c4da24
JB		 461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 469}
470
57f350b6
JB		 471static void vlv_init_dpio(struct drm_device *dev)
472{
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480}
481
1b894b59
CW		 482static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk)
2c07245f 484{
b91ad0ec 485 struct drm_device *dev = crtc->dev;
2c07245f 486 const intel_limit_t *limit;
b91ad0ec
ZW		 487
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 489 if (intel_is_dual_link_lvds(dev)) {
1b894b59 490 if (refclk == 100000)
b91ad0ec
ZW		 491 limit = &intel_limits_ironlake_dual_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_dual_lvds;
494 } else {
1b894b59 495 if (refclk == 100000)
b91ad0ec
ZW		 496 limit = &intel_limits_ironlake_single_lvds_100m;
497 else
498 limit = &intel_limits_ironlake_single_lvds;
499 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 502 limit = &intel_limits_ironlake_display_port;
2c07245f 503 else
b91ad0ec 504 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 505
506 return limit;
507}
508
044c7c41
ML		 509static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
510{
511 struct drm_device *dev = crtc->dev;
044c7c41
ML		 512 const intel_limit_t *limit;
513
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 515 if (intel_is_dual_link_lvds(dev))
e4b36699 516 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 517 else
e4b36699 518 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 521 limit = &intel_limits_g4x_hdmi;
044c7c41 522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 523 limit = &intel_limits_g4x_sdvo;
0206e353 524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 525 limit = &intel_limits_g4x_display_port;
044c7c41 526 } else /* The option is for other outputs */
e4b36699 527 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 528
529 return limit;
530}
531
1b894b59 532static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 533{
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
bad720ff 537 if (HAS_PCH_SPLIT(dev))
1b894b59 538 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 539 else if (IS_G4X(dev)) {
044c7c41 540 limit = intel_g4x_limit(crtc);
f2b115e6 541 } else if (IS_PINEVIEW(dev)) {
2177832f 542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 543 limit = &intel_limits_pineview_lvds;
2177832f 544 else
f2b115e6 545 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
551 else
552 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 558 } else {
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 560 limit = &intel_limits_i8xx_lvds;
79e53945 561 else
e4b36699 562 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 563 }
564 return limit;
565}
566
f2b115e6
AJ		 567/* m1 is reserved as 0 in Pineview, n is a ring counter */
568static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 569{
2177832f
SL		 570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
574}
575
576static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
577{
f2b115e6
AJ		 578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
2177832f
SL		 580 return;
581 }
79e53945
JB		 582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
586}
587
79e53945
JB		 588/**
589 * Returns whether any output on the specified pipe is of the specified type
590 */
4ef69c7a 591bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 592{
4ef69c7a 593 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 594 struct intel_encoder *encoder;
595
6c2b7c12
DV		 596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
4ef69c7a
CW		 598 return true;
599
600 return false;
79e53945
JB		 601}
602
7c04d1d9 603#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 604/**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
1b894b59
CW		 609static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
79e53945 612{
79e53945 613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 614 INTELPllInvalid("p1 out of range\n");
79e53945 615 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 616 INTELPllInvalid("p out of range\n");
79e53945 617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 618 INTELPllInvalid("m2 out of range\n");
79e53945 619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 620 INTELPllInvalid("m1 out of range\n");
f2b115e6 621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 622 INTELPllInvalid("m1 <= m2\n");
79e53945 623 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 624 INTELPllInvalid("m out of range\n");
79e53945 625 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 626 INTELPllInvalid("n out of range\n");
79e53945 627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 628 INTELPllInvalid("vco out of range\n");
79e53945
JB		 629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 633 INTELPllInvalid("dot out of range\n");
79e53945
JB		 634
635 return true;
636}
637
d4906093
ML		 638static bool
639intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
d4906093 642
79e53945
JB		 643{
644 struct drm_device *dev = crtc->dev;
79e53945 645 intel_clock_t clock;
79e53945
JB		 646 int err = target;
647
a210b028 648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 649 /*
a210b028
DV		 650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
79e53945 653 */
1974cad0 654 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
0206e353 665 memset(best_clock, 0, sizeof(*best_clock));
79e53945 666
42158660
ZY		 667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 678 int this_err;
679
2177832f 680 intel_clock(dev, refclk, &clock);
1b894b59
CW		 681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
79e53945 683 continue;
cec2f356
SP		 684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
79e53945
JB		 687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699}
700
d4906093
ML		 701static bool
702intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
d4906093
ML		 705{
706 struct drm_device *dev = crtc->dev;
d4906093
ML		 707 intel_clock_t clock;
708 int max_n;
709 bool found;
6ba770dc
AJ		 710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 712 found = false;
713
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 715 int lvds_reg;
716
c619eed4 717 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
1974cad0 721 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
f77f13e2 734 /* based on hardware requirement, prefer smaller n to precision */
d4906093 735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 736 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err;
744
2177832f 745 intel_clock(dev, refclk, &clock);
1b894b59
CW		 746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
d4906093 748 continue;
cec2f356
SP		 749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
1b894b59
CW		 752
753 this_err = abs(clock.dot - target);
d4906093
ML		 754 if (this_err < err_most) {
755 *best_clock = clock;
756 err_most = this_err;
757 max_n = clock.n;
758 found = true;
759 }
760 }
761 }
762 }
763 }
2c07245f
ZW		 764 return found;
765}
766
5eb08b69 767static bool
f2b115e6 768intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
5eb08b69
ZW		 771{
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
4547668a 774
5eb08b69
ZW		 775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791}
792
a4fc5ed6
KP		 793/* DisplayPort has only two frequencies, 162MHz and 270MHz */
794static bool
795intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
a4fc5ed6 798{
5eddb70b
CW		 799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
a4fc5ed6 819}
a0c4da24
JB		 820static bool
821intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824{
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
829 int dotclk, flag;
830
af447bd3 831 flag = 0;
a0c4da24
JB		 832 dotclk = target * 1000;
833 bestppm = 1000000;
834 ppm = absppm = 0;
835 fastclk = dotclk / (2*100);
836 updrate = 0;
837 minupdate = 19200;
838 fracbits = 1;
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
847 if (p2 > 10)
848 p2 = p2 - 1;
849 p = p1 * p2;
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
854 m = m1 * m2;
855 vco = updrate * m;
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
860 bestppm = 0;
861 flag = 1;
862 }
863 if (absppm < bestppm - 10) {
864 bestppm = absppm;
865 flag = 1;
866 }
867 if (flag) {
868 bestn = n;
869 bestm1 = m1;
870 bestm2 = m2;
871 bestp1 = p1;
872 bestp2 = p2;
873 flag = 0;
874 }
875 }
876 }
877 }
878 }
879 }
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
885
886 return true;
887}
a4fc5ed6 888
a5c961d1
PZ		 889enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
894
895 return intel_crtc->cpu_transcoder;
896}
897
a928d536
PZ		 898static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
899{
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
902
903 frame = I915_READ(frame_reg);
904
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
907}
908
9d0498a2
JB		 909/**
910 * intel_wait_for_vblank - wait for vblank on a given pipe
911 * @dev: drm device
912 * @pipe: pipe to wait for
913 *
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 * mode setting code.
916 */
917void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 918{
9d0498a2 919 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 920 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 921
a928d536
PZ		 922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
924 return;
925 }
926
300387c0
CW		 927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
929 *
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
936 * vblanks...
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
939 */
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
942
9d0498a2 943 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
946 50))
9d0498a2
JB		 947 DRM_DEBUG_KMS("vblank wait timed out\n");
948}
949
ab7ad7f6
KP		 950/*
951 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
958 *
ab7ad7f6
KP		 959 * On Gen4 and above:
960 * wait for the pipe register state bit to turn off
961 *
962 * Otherwise:
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
58e10eb9 965 *
9d0498a2 966 */
58e10eb9 967void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 968{
969 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
ab7ad7f6
KP		 972
973 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 974 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 975
976 /* Wait for the Pipe State to go off */
58e10eb9
CW		 977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
978 100))
284637d9 979 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 980 } else {
837ba00f 981 u32 last_line, line_mask;
58e10eb9 982 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
984
837ba00f
PZ		 985 if (IS_GEN2(dev))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
ab7ad7f6
KP		 990 /* Wait for the display line to settle */
991 do {
837ba00f 992 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 993 mdelay(5);
837ba00f 994 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
284637d9 997 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 998 }
79e53945
JB		 999}
1000
b0ea7d37
DL		 1001/*
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1005 *
1006 * Returns true if @port is connected, false otherwise.
1007 */
1008bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1010{
1011 u32 bit;
1012
c36346e3
DL		 1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1015 case PORT_B:
1016 bit = SDE_PORTB_HOTPLUG;
1017 break;
1018 case PORT_C:
1019 bit = SDE_PORTC_HOTPLUG;
1020 break;
1021 case PORT_D:
1022 bit = SDE_PORTD_HOTPLUG;
1023 break;
1024 default:
1025 return true;
1026 }
1027 } else {
1028 switch(port->port) {
1029 case PORT_B:
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1031 break;
1032 case PORT_C:
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1034 break;
1035 case PORT_D:
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1037 break;
1038 default:
1039 return true;
1040 }
b0ea7d37
DL		 1041 }
1042
1043 return I915_READ(SDEISR) & bit;
1044}
1045
b24e7179
JB		 1046static const char *state_string(bool enabled)
1047{
1048 return enabled ? "on" : "off";
1049}
1050
1051/* Only for pre-ILK configs */
1052static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1054{
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DPLL(pipe);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1065}
1066#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
040484af
JB		 1069/* For ILK+ */
1070static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1073 bool state)
040484af 1074{
040484af
JB		 1075 u32 val;
1076 bool cur_state;
1077
9d82aa17
ED		 1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080 return;
1081 }
1082
92b27b08
CW		 1083 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1085 return;
ee7b9f93 1086
92b27b08
CW		 1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
d3ccbe86 1110 }
040484af 1111}
92b27b08
CW		 1112#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1114
1115static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117{
1118 int reg;
1119 u32 val;
1120 bool cur_state;
ad80a810
PZ		 1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
040484af 1123
affa9354
PZ		 1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
ad80a810 1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1127 val = I915_READ(reg);
ad80a810 1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
040484af
JB		 1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137}
1138#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143{
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
d63fa0dc
PZ		 1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154}
1155#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160{
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1166 return;
1167
bf507ef7 1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1169 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1170 return;
1171
040484af
JB		 1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175}
1176
1177static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179{
1180 int reg;
1181 u32 val;
1182
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186}
1187
ea0760cf
JB		 1188static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
0de3b485 1194 bool locked = true;
ea0760cf
JB		 1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1214 pipe_name(pipe));
ea0760cf
JB		 1215}
1216
b840d907
JB		 1217void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
b24e7179
JB		 1219{
1220 int reg;
1221 u32 val;
63d7bbe9 1222 bool cur_state;
702e7a56
PZ		 1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
b24e7179 1225
8e636784
DV		 1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true;
1229
69310161
PZ		 1230 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
63d7bbe9
JB		 1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1241 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1242}
1243
931872fc
CW		 1244static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
b24e7179
JB		 1246{
1247 int reg;
1248 u32 val;
931872fc 1249 bool cur_state;
b24e7179
JB		 1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
931872fc
CW		 1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1257}
1258
931872fc
CW		 1259#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
b24e7179
JB		 1262static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
1265 int reg, i;
1266 u32 val;
1267 int cur_pipe;
1268
19ec1358 1269 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1270 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1275 plane_name(pipe));
19ec1358 1276 return;
28c05794 1277 }
19ec1358 1278
b24e7179
JB		 1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1281 reg = DSPCNTR(i);
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1288 }
1289}
1290
92f2584a
JB		 1291static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1292{
1293 u32 val;
1294 bool enabled;
1295
9d82aa17
ED		 1296 if (HAS_PCH_LPT(dev_priv->dev)) {
1297 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1298 return;
1299 }
1300
92f2584a
JB		 1301 val = I915_READ(PCH_DREF_CONTROL);
1302 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1303 DREF_SUPERSPREAD_SOURCE_MASK));
1304 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1305}
1306
1307static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe)
1309{
1310 int reg;
1311 u32 val;
1312 bool enabled;
1313
1314 reg = TRANSCONF(pipe);
1315 val = I915_READ(reg);
1316 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1317 WARN(enabled,
1318 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1319 pipe_name(pipe));
92f2584a
JB		 1320}
1321
4e634389
KP		 1322static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1324{
1325 if ((val & DP_PORT_EN) == 0)
1326 return false;
1327
1328 if (HAS_PCH_CPT(dev_priv->dev)) {
1329 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1330 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1331 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1332 return false;
1333 } else {
1334 if ((val & DP_PIPE_MASK) != (pipe << 30))
1335 return false;
1336 }
1337 return true;
1338}
1339
1519b995
KP		 1340static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
1343 if ((val & PORT_ENABLE) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & LVDS_PORT_EN) == 0)
1360 return false;
1361
1362 if (HAS_PCH_CPT(dev_priv->dev)) {
1363 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1364 return false;
1365 } else {
1366 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1367 return false;
1368 }
1369 return true;
1370}
1371
1372static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 val)
1374{
1375 if ((val & ADPA_DAC_ENABLE) == 0)
1376 return false;
1377 if (HAS_PCH_CPT(dev_priv->dev)) {
1378 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1379 return false;
1380 } else {
1381 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1382 return false;
1383 }
1384 return true;
1385}
1386
291906f1 1387static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1388 enum pipe pipe, int reg, u32 port_sel)
291906f1 1389{
47a05eca 1390 u32 val = I915_READ(reg);
4e634389 1391 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1392 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1393 reg, pipe_name(pipe));
de9a35ab 1394
75c5da27
DV		 1395 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1396 && (val & DP_PIPEB_SELECT),
de9a35ab 1397 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1398}
1399
1400static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe, int reg)
1402{
47a05eca 1403 u32 val = I915_READ(reg);
b70ad586 1404 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1405 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1406 reg, pipe_name(pipe));
de9a35ab 1407
75c5da27
DV		 1408 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1409 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1410 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1411}
1412
1413static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe)
1415{
1416 int reg;
1417 u32 val;
291906f1 1418
f0575e92
KP		 1419 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1420 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1421 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1422
1423 reg = PCH_ADPA;
1424 val = I915_READ(reg);
b70ad586 1425 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1426 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1427 pipe_name(pipe));
291906f1
JB		 1428
1429 reg = PCH_LVDS;
1430 val = I915_READ(reg);
b70ad586 1431 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1432 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1433 pipe_name(pipe));
291906f1 1434
e2debe91
PZ		 1435 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1436 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1437 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1438}
1439
63d7bbe9
JB		 1440/**
1441 * intel_enable_pll - enable a PLL
1442 * @dev_priv: i915 private structure
1443 * @pipe: pipe PLL to enable
1444 *
1445 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1446 * make sure the PLL reg is writable first though, since the panel write
1447 * protect mechanism may be enabled.
1448 *
1449 * Note! This is for pre-ILK only.
7434a255
TR		 1450 *
1451 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1452 */
1453static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1454{
1455 int reg;
1456 u32 val;
1457
1458 /* No really, not for ILK+ */
a0c4da24 1459 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1460
1461 /* PLL is protected by panel, make sure we can write it */
1462 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1463 assert_panel_unlocked(dev_priv, pipe);
1464
1465 reg = DPLL(pipe);
1466 val = I915_READ(reg);
1467 val |= DPLL_VCO_ENABLE;
1468
1469 /* We do this three times for luck */
1470 I915_WRITE(reg, val);
1471 POSTING_READ(reg);
1472 udelay(150); /* wait for warmup */
1473 I915_WRITE(reg, val);
1474 POSTING_READ(reg);
1475 udelay(150); /* wait for warmup */
1476 I915_WRITE(reg, val);
1477 POSTING_READ(reg);
1478 udelay(150); /* wait for warmup */
1479}
1480
1481/**
1482 * intel_disable_pll - disable a PLL
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe PLL to disable
1485 *
1486 * Disable the PLL for @pipe, making sure the pipe is off first.
1487 *
1488 * Note! This is for pre-ILK only.
1489 */
1490static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1491{
1492 int reg;
1493 u32 val;
1494
1495 /* Don't disable pipe A or pipe A PLLs if needed */
1496 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1497 return;
1498
1499 /* Make sure the pipe isn't still relying on us */
1500 assert_pipe_disabled(dev_priv, pipe);
1501
1502 reg = DPLL(pipe);
1503 val = I915_READ(reg);
1504 val &= ~DPLL_VCO_ENABLE;
1505 I915_WRITE(reg, val);
1506 POSTING_READ(reg);
1507}
1508
a416edef
ED		 1509/* SBI access */
1510static void
988d6ee8
PZ		 1511intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1512 enum intel_sbi_destination destination)
a416edef 1513{
988d6ee8 1514 u32 tmp;
a416edef 1515
09153000 1516 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1517
39fb50f6 1518 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1519 100)) {
1520 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1521 return;
a416edef
ED		 1522 }
1523
988d6ee8
PZ		 1524 I915_WRITE(SBI_ADDR, (reg << 16));
1525 I915_WRITE(SBI_DATA, value);
1526
1527 if (destination == SBI_ICLK)
1528 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1529 else
1530 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1531 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1532
39fb50f6 1533 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1534 100)) {
1535 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1536 return;
a416edef 1537 }
a416edef
ED		 1538}
1539
1540static u32
988d6ee8
PZ		 1541intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1542 enum intel_sbi_destination destination)
a416edef 1543{
39fb50f6 1544 u32 value = 0;
09153000 1545 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1546
39fb50f6 1547 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1548 100)) {
1549 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1550 return 0;
a416edef
ED		 1551 }
1552
988d6ee8
PZ		 1553 I915_WRITE(SBI_ADDR, (reg << 16));
1554
1555 if (destination == SBI_ICLK)
1556 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1557 else
1558 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1559 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1560
39fb50f6 1561 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1562 100)) {
1563 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1564 return 0;
a416edef
ED		 1565 }
1566
09153000 1567 return I915_READ(SBI_DATA);
a416edef
ED		 1568}
1569
92f2584a 1570/**
b6b4e185 1571 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1572 * @dev_priv: i915 private structure
1573 * @pipe: pipe PLL to enable
1574 *
1575 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576 * drives the transcoder clock.
1577 */
b6b4e185 1578static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1579{
ee7b9f93 1580 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1581 struct intel_pch_pll *pll;
92f2584a
JB		 1582 int reg;
1583 u32 val;
1584
48da64a8 1585 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1586 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1587 pll = intel_crtc->pch_pll;
1588 if (pll == NULL)
1589 return;
1590
1591 if (WARN_ON(pll->refcount == 0))
1592 return;
ee7b9f93
JB		 1593
1594 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595 pll->pll_reg, pll->active, pll->on,
1596 intel_crtc->base.base.id);
92f2584a
JB		 1597
1598 /* PCH refclock must be enabled first */
1599 assert_pch_refclk_enabled(dev_priv);
1600
ee7b9f93 1601 if (pll->active++ && pll->on) {
92b27b08 1602 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1603 return;
1604 }
1605
1606 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1607
1608 reg = pll->pll_reg;
92f2584a
JB		 1609 val = I915_READ(reg);
1610 val |= DPLL_VCO_ENABLE;
1611 I915_WRITE(reg, val);
1612 POSTING_READ(reg);
1613 udelay(200);
ee7b9f93
JB		 1614
1615 pll->on = true;
92f2584a
JB		 1616}
1617
ee7b9f93 1618static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1619{
ee7b9f93
JB		 1620 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1621 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1622 int reg;
ee7b9f93 1623 u32 val;
4c609cb8 1624
92f2584a
JB		 1625 /* PCH only available on ILK+ */
1626 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1627 if (pll == NULL)
1628 return;
92f2584a 1629
48da64a8
CW		 1630 if (WARN_ON(pll->refcount == 0))
1631 return;
7a419866 1632
ee7b9f93
JB		 1633 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634 pll->pll_reg, pll->active, pll->on,
1635 intel_crtc->base.base.id);
7a419866 1636
48da64a8 1637 if (WARN_ON(pll->active == 0)) {
92b27b08 1638 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1639 return;
1640 }
1641
ee7b9f93 1642 if (--pll->active) {
92b27b08 1643 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1644 return;
ee7b9f93
JB		 1645 }
1646
1647 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1648
1649 /* Make sure transcoder isn't still depending on us */
1650 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1651
ee7b9f93 1652 reg = pll->pll_reg;
92f2584a
JB		 1653 val = I915_READ(reg);
1654 val &= ~DPLL_VCO_ENABLE;
1655 I915_WRITE(reg, val);
1656 POSTING_READ(reg);
1657 udelay(200);
ee7b9f93
JB		 1658
1659 pll->on = false;
92f2584a
JB		 1660}
1661
b8a4f404
PZ		 1662static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1663 enum pipe pipe)
040484af 1664{
23670b32 1665 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1666 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1667 uint32_t reg, val, pipeconf_val;
040484af
JB		 1668
1669 /* PCH only available on ILK+ */
1670 BUG_ON(dev_priv->info->gen < 5);
1671
1672 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1673 assert_pch_pll_enabled(dev_priv,
1674 to_intel_crtc(crtc)->pch_pll,
1675 to_intel_crtc(crtc));
040484af
JB		 1676
1677 /* FDI must be feeding us bits for PCH ports */
1678 assert_fdi_tx_enabled(dev_priv, pipe);
1679 assert_fdi_rx_enabled(dev_priv, pipe);
1680
23670b32
DV		 1681 if (HAS_PCH_CPT(dev)) {
1682 /* Workaround: Set the timing override bit before enabling the
1683 * pch transcoder. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
59c859d6 1688 }
23670b32 1689
040484af
JB		 1690 reg = TRANSCONF(pipe);
1691 val = I915_READ(reg);
5f7f726d 1692 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1693
1694 if (HAS_PCH_IBX(dev_priv->dev)) {
1695 /*
1696 * make the BPC in transcoder be consistent with
1697 * that in pipeconf reg.
1698 */
dfd07d72
DV		 1699 val &= ~PIPECONF_BPC_MASK;
1700 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1701 }
5f7f726d
PZ		 1702
1703 val &= ~TRANS_INTERLACE_MASK;
1704 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1705 if (HAS_PCH_IBX(dev_priv->dev) &&
1706 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1707 val |= TRANS_LEGACY_INTERLACED_ILK;
1708 else
1709 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1710 else
1711 val |= TRANS_PROGRESSIVE;
1712
040484af
JB		 1713 I915_WRITE(reg, val | TRANS_ENABLE);
1714 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1715 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1716}
1717
8fb033d7 1718static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1719 enum transcoder cpu_transcoder)
040484af 1720{
8fb033d7 1721 u32 val, pipeconf_val;
8fb033d7
PZ		 1722
1723 /* PCH only available on ILK+ */
1724 BUG_ON(dev_priv->info->gen < 5);
1725
8fb033d7 1726 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1727 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1728 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1729
223a6fdf
PZ		 1730 /* Workaround: set timing override bit. */
1731 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1732 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1733 I915_WRITE(_TRANSA_CHICKEN2, val);
1734
25f3ef11 1735 val = TRANS_ENABLE;
937bb610 1736 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1737
9a76b1c6
PZ		 1738 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1739 PIPECONF_INTERLACED_ILK)
a35f2679 1740 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1741 else
1742 val |= TRANS_PROGRESSIVE;
1743
25f3ef11 1744 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1745 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1746 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1747}
1748
b8a4f404
PZ		 1749static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1750 enum pipe pipe)
040484af 1751{
23670b32
DV		 1752 struct drm_device *dev = dev_priv->dev;
1753 uint32_t reg, val;
040484af
JB		 1754
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe);
1757 assert_fdi_rx_disabled(dev_priv, pipe);
1758
291906f1
JB		 1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1761
040484af
JB		 1762 reg = TRANSCONF(pipe);
1763 val = I915_READ(reg);
1764 val &= ~TRANS_ENABLE;
1765 I915_WRITE(reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1768 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1769
1770 if (!HAS_PCH_IBX(dev)) {
1771 /* Workaround: Clear the timing override chicken bit again. */
1772 reg = TRANS_CHICKEN2(pipe);
1773 val = I915_READ(reg);
1774 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1775 I915_WRITE(reg, val);
1776 }
040484af
JB		 1777}
1778
ab4d966c 1779static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1780{
8fb033d7
PZ		 1781 u32 val;
1782
8a52fd9f 1783 val = I915_READ(_TRANSACONF);
8fb033d7 1784 val &= ~TRANS_ENABLE;
8a52fd9f 1785 I915_WRITE(_TRANSACONF, val);
8fb033d7 1786 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1787 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1788 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1789
1790 /* Workaround: clear timing override bit. */
1791 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1792 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1793 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1794}
1795
b24e7179 1796/**
309cfea8 1797 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe to enable
040484af 1800 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1801 *
1802 * Enable @pipe, making sure that various hardware specific requirements
1803 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1804 *
1805 * @pipe should be %PIPE_A or %PIPE_B.
1806 *
1807 * Will wait until the pipe is actually running (i.e. first vblank) before
1808 * returning.
1809 */
040484af
JB		 1810static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1811 bool pch_port)
b24e7179 1812{
702e7a56
PZ		 1813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1814 pipe);
1a240d4d 1815 enum pipe pch_transcoder;
b24e7179
JB		 1816 int reg;
1817 u32 val;
1818
681e5811 1819 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1820 pch_transcoder = TRANSCODER_A;
1821 else
1822 pch_transcoder = pipe;
1823
b24e7179
JB		 1824 /*
1825 * A pipe without a PLL won't actually be able to drive bits from
1826 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1827 * need the check.
1828 */
1829 if (!HAS_PCH_SPLIT(dev_priv->dev))
1830 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1831 else {
1832 if (pch_port) {
1833 /* if driving the PCH, we need FDI enabled */
cc391bbb 1834 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1835 assert_fdi_tx_pll_enabled(dev_priv,
1836 (enum pipe) cpu_transcoder);
040484af
JB		 1837 }
1838 /* FIXME: assert CPU port conditions for SNB+ */
1839 }
b24e7179 1840
702e7a56 1841 reg = PIPECONF(cpu_transcoder);
b24e7179 1842 val = I915_READ(reg);
00d70b15
CW		 1843 if (val & PIPECONF_ENABLE)
1844 return;
1845
1846 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1847 intel_wait_for_vblank(dev_priv->dev, pipe);
1848}
1849
1850/**
309cfea8 1851 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1852 * @dev_priv: i915 private structure
1853 * @pipe: pipe to disable
1854 *
1855 * Disable @pipe, making sure that various hardware specific requirements
1856 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1857 *
1858 * @pipe should be %PIPE_A or %PIPE_B.
1859 *
1860 * Will wait until the pipe has shut down before returning.
1861 */
1862static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1863 enum pipe pipe)
1864{
702e7a56
PZ		 1865 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1866 pipe);
b24e7179
JB		 1867 int reg;
1868 u32 val;
1869
1870 /*
1871 * Make sure planes won't keep trying to pump pixels to us,
1872 * or we might hang the display.
1873 */
1874 assert_planes_disabled(dev_priv, pipe);
1875
1876 /* Don't disable pipe A or pipe A PLLs if needed */
1877 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1878 return;
1879
702e7a56 1880 reg = PIPECONF(cpu_transcoder);
b24e7179 1881 val = I915_READ(reg);
00d70b15
CW		 1882 if ((val & PIPECONF_ENABLE) == 0)
1883 return;
1884
1885 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1886 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1887}
1888
d74362c9
KP		 1889/*
1890 * Plane regs are double buffered, going from enabled->disabled needs a
1891 * trigger in order to latch. The display address reg provides this.
1892 */
6f1d69b0 1893void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1894 enum plane plane)
1895{
14f86147
DL		 1896 if (dev_priv->info->gen >= 4)
1897 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1898 else
1899 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1900}
1901
b24e7179
JB		 1902/**
1903 * intel_enable_plane - enable a display plane on a given pipe
1904 * @dev_priv: i915 private structure
1905 * @plane: plane to enable
1906 * @pipe: pipe being fed
1907 *
1908 * Enable @plane on @pipe, making sure that @pipe is running first.
1909 */
1910static void intel_enable_plane(struct drm_i915_private *dev_priv,
1911 enum plane plane, enum pipe pipe)
1912{
1913 int reg;
1914 u32 val;
1915
1916 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1917 assert_pipe_enabled(dev_priv, pipe);
1918
1919 reg = DSPCNTR(plane);
1920 val = I915_READ(reg);
00d70b15
CW		 1921 if (val & DISPLAY_PLANE_ENABLE)
1922 return;
1923
1924 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1925 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1926 intel_wait_for_vblank(dev_priv->dev, pipe);
1927}
1928
b24e7179
JB		 1929/**
1930 * intel_disable_plane - disable a display plane
1931 * @dev_priv: i915 private structure
1932 * @plane: plane to disable
1933 * @pipe: pipe consuming the data
1934 *
1935 * Disable @plane; should be an independent operation.
1936 */
1937static void intel_disable_plane(struct drm_i915_private *dev_priv,
1938 enum plane plane, enum pipe pipe)
1939{
1940 int reg;
1941 u32 val;
1942
1943 reg = DSPCNTR(plane);
1944 val = I915_READ(reg);
00d70b15
CW		 1945 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1946 return;
1947
1948 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1949 intel_flush_display_plane(dev_priv, plane);
1950 intel_wait_for_vblank(dev_priv->dev, pipe);
1951}
1952
127bd2ac 1953int
48b956c5 1954intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1955 struct drm_i915_gem_object *obj,
919926ae 1956 struct intel_ring_buffer *pipelined)
6b95a207 1957{
ce453d81 1958 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1959 u32 alignment;
1960 int ret;
1961
05394f39 1962 switch (obj->tiling_mode) {
6b95a207 1963 case I915_TILING_NONE:
534843da
CW		 1964 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1965 alignment = 128 * 1024;
a6c45cf0 1966 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1967 alignment = 4 * 1024;
1968 else
1969 alignment = 64 * 1024;
6b95a207
KH		 1970 break;
1971 case I915_TILING_X:
1972 /* pin() will align the object as required by fence */
1973 alignment = 0;
1974 break;
1975 case I915_TILING_Y:
1976 /* FIXME: Is this true? */
1977 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1978 return -EINVAL;
1979 default:
1980 BUG();
1981 }
1982
ce453d81 1983 dev_priv->mm.interruptible = false;
2da3b9b9 1984 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1985 if (ret)
ce453d81 1986 goto err_interruptible;
6b95a207
KH		 1987
1988 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1989 * fence, whereas 965+ only requires a fence if using
1990 * framebuffer compression. For simplicity, we always install
1991 * a fence as the cost is not that onerous.
1992 */
06d98131 1993 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1994 if (ret)
1995 goto err_unpin;
1690e1eb 1996
9a5a53b3 1997 i915_gem_object_pin_fence(obj);
6b95a207 1998
ce453d81 1999 dev_priv->mm.interruptible = true;
6b95a207 2000 return 0;
48b956c5
CW		 2001
2002err_unpin:
2003 i915_gem_object_unpin(obj);
ce453d81
CW		 2004err_interruptible:
2005 dev_priv->mm.interruptible = true;
48b956c5 2006 return ret;
6b95a207
KH		 2007}
2008
1690e1eb
CW		 2009void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2010{
2011 i915_gem_object_unpin_fence(obj);
2012 i915_gem_object_unpin(obj);
2013}
2014
c2c75131
DV		 2015/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2016 * is assumed to be a power-of-two. */
5a35e99e
DL		 2017unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2018 unsigned int bpp,
2019 unsigned int pitch)
c2c75131
DV		 2020{
2021 int tile_rows, tiles;
2022
2023 tile_rows = *y / 8;
2024 *y %= 8;
2025 tiles = *x / (512/bpp);
2026 *x %= 512/bpp;
2027
2028 return tile_rows * pitch * 8 + tiles * 4096;
2029}
2030
17638cd6
JB		 2031static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2032 int x, int y)
81255565
JB		 2033{
2034 struct drm_device *dev = crtc->dev;
2035 struct drm_i915_private *dev_priv = dev->dev_private;
2036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2037 struct intel_framebuffer *intel_fb;
05394f39 2038 struct drm_i915_gem_object *obj;
81255565 2039 int plane = intel_crtc->plane;
e506a0c6 2040 unsigned long linear_offset;
81255565 2041 u32 dspcntr;
5eddb70b 2042 u32 reg;
81255565
JB		 2043
2044 switch (plane) {
2045 case 0:
2046 case 1:
2047 break;
2048 default:
2049 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2050 return -EINVAL;
2051 }
2052
2053 intel_fb = to_intel_framebuffer(fb);
2054 obj = intel_fb->obj;
81255565 2055
5eddb70b
CW		 2056 reg = DSPCNTR(plane);
2057 dspcntr = I915_READ(reg);
81255565
JB		 2058 /* Mask out pixel format bits in case we change it */
2059 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2060 switch (fb->pixel_format) {
2061 case DRM_FORMAT_C8:
81255565
JB		 2062 dspcntr |= DISPPLANE_8BPP;
2063 break;
57779d06
VS		 2064 case DRM_FORMAT_XRGB1555:
2065 case DRM_FORMAT_ARGB1555:
2066 dspcntr |= DISPPLANE_BGRX555;
81255565 2067 break;
57779d06
VS		 2068 case DRM_FORMAT_RGB565:
2069 dspcntr |= DISPPLANE_BGRX565;
2070 break;
2071 case DRM_FORMAT_XRGB8888:
2072 case DRM_FORMAT_ARGB8888:
2073 dspcntr |= DISPPLANE_BGRX888;
2074 break;
2075 case DRM_FORMAT_XBGR8888:
2076 case DRM_FORMAT_ABGR8888:
2077 dspcntr |= DISPPLANE_RGBX888;
2078 break;
2079 case DRM_FORMAT_XRGB2101010:
2080 case DRM_FORMAT_ARGB2101010:
2081 dspcntr |= DISPPLANE_BGRX101010;
2082 break;
2083 case DRM_FORMAT_XBGR2101010:
2084 case DRM_FORMAT_ABGR2101010:
2085 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2086 break;
2087 default:
57779d06 2088 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2089 return -EINVAL;
2090 }
57779d06 2091
a6c45cf0 2092 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2093 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2094 dspcntr |= DISPPLANE_TILED;
2095 else
2096 dspcntr &= ~DISPPLANE_TILED;
2097 }
2098
5eddb70b 2099 I915_WRITE(reg, dspcntr);
81255565 2100
e506a0c6 2101 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2102
c2c75131
DV		 2103 if (INTEL_INFO(dev)->gen >= 4) {
2104 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2105 intel_gen4_compute_offset_xtiled(&x, &y,
2106 fb->bits_per_pixel / 8,
2107 fb->pitches[0]);
c2c75131
DV		 2108 linear_offset -= intel_crtc->dspaddr_offset;
2109 } else {
e506a0c6 2110 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2111 }
e506a0c6
DV		 2112
2113 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2114 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2115 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2116 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2117 I915_MODIFY_DISPBASE(DSPSURF(plane),
2118 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2119 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2120 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2121 } else
e506a0c6 2122 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2123 POSTING_READ(reg);
81255565 2124
17638cd6
JB		 2125 return 0;
2126}
2127
2128static int ironlake_update_plane(struct drm_crtc *crtc,
2129 struct drm_framebuffer *fb, int x, int y)
2130{
2131 struct drm_device *dev = crtc->dev;
2132 struct drm_i915_private *dev_priv = dev->dev_private;
2133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2134 struct intel_framebuffer *intel_fb;
2135 struct drm_i915_gem_object *obj;
2136 int plane = intel_crtc->plane;
e506a0c6 2137 unsigned long linear_offset;
17638cd6
JB		 2138 u32 dspcntr;
2139 u32 reg;
2140
2141 switch (plane) {
2142 case 0:
2143 case 1:
27f8227b 2144 case 2:
17638cd6
JB		 2145 break;
2146 default:
2147 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2148 return -EINVAL;
2149 }
2150
2151 intel_fb = to_intel_framebuffer(fb);
2152 obj = intel_fb->obj;
2153
2154 reg = DSPCNTR(plane);
2155 dspcntr = I915_READ(reg);
2156 /* Mask out pixel format bits in case we change it */
2157 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2158 switch (fb->pixel_format) {
2159 case DRM_FORMAT_C8:
17638cd6
JB		 2160 dspcntr |= DISPPLANE_8BPP;
2161 break;
57779d06
VS		 2162 case DRM_FORMAT_RGB565:
2163 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2164 break;
57779d06
VS		 2165 case DRM_FORMAT_XRGB8888:
2166 case DRM_FORMAT_ARGB8888:
2167 dspcntr |= DISPPLANE_BGRX888;
2168 break;
2169 case DRM_FORMAT_XBGR8888:
2170 case DRM_FORMAT_ABGR8888:
2171 dspcntr |= DISPPLANE_RGBX888;
2172 break;
2173 case DRM_FORMAT_XRGB2101010:
2174 case DRM_FORMAT_ARGB2101010:
2175 dspcntr |= DISPPLANE_BGRX101010;
2176 break;
2177 case DRM_FORMAT_XBGR2101010:
2178 case DRM_FORMAT_ABGR2101010:
2179 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2180 break;
2181 default:
57779d06 2182 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2183 return -EINVAL;
2184 }
2185
2186 if (obj->tiling_mode != I915_TILING_NONE)
2187 dspcntr |= DISPPLANE_TILED;
2188 else
2189 dspcntr &= ~DISPPLANE_TILED;
2190
2191 /* must disable */
2192 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2193
2194 I915_WRITE(reg, dspcntr);
2195
e506a0c6 2196 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2197 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2198 intel_gen4_compute_offset_xtiled(&x, &y,
2199 fb->bits_per_pixel / 8,
2200 fb->pitches[0]);
c2c75131 2201 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2202
e506a0c6
DV		 2203 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2204 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2205 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2206 I915_MODIFY_DISPBASE(DSPSURF(plane),
2207 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2208 if (IS_HASWELL(dev)) {
2209 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2210 } else {
2211 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2212 I915_WRITE(DSPLINOFF(plane), linear_offset);
2213 }
17638cd6
JB		 2214 POSTING_READ(reg);
2215
2216 return 0;
2217}
2218
2219/* Assume fb object is pinned & idle & fenced and just update base pointers */
2220static int
2221intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2222 int x, int y, enum mode_set_atomic state)
2223{
2224 struct drm_device *dev = crtc->dev;
2225 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2226
6b8e6ed0
CW		 2227 if (dev_priv->display.disable_fbc)
2228 dev_priv->display.disable_fbc(dev);
3dec0095 2229 intel_increase_pllclock(crtc);
81255565 2230
6b8e6ed0 2231 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2232}
2233
96a02917
VS		 2234void intel_display_handle_reset(struct drm_device *dev)
2235{
2236 struct drm_i915_private *dev_priv = dev->dev_private;
2237 struct drm_crtc *crtc;
2238
2239 /*
2240 * Flips in the rings have been nuked by the reset,
2241 * so complete all pending flips so that user space
2242 * will get its events and not get stuck.
2243 *
2244 * Also update the base address of all primary
2245 * planes to the the last fb to make sure we're
2246 * showing the correct fb after a reset.
2247 *
2248 * Need to make two loops over the crtcs so that we
2249 * don't try to grab a crtc mutex before the
2250 * pending_flip_queue really got woken up.
2251 */
2252
2253 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2255 enum plane plane = intel_crtc->plane;
2256
2257 intel_prepare_page_flip(dev, plane);
2258 intel_finish_page_flip_plane(dev, plane);
2259 }
2260
2261 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2263
2264 mutex_lock(&crtc->mutex);
2265 if (intel_crtc->active)
2266 dev_priv->display.update_plane(crtc, crtc->fb,
2267 crtc->x, crtc->y);
2268 mutex_unlock(&crtc->mutex);
2269 }
2270}
2271
14667a4b
CW		 2272static int
2273intel_finish_fb(struct drm_framebuffer *old_fb)
2274{
2275 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2276 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2277 bool was_interruptible = dev_priv->mm.interruptible;
2278 int ret;
2279
14667a4b
CW		 2280 /* Big Hammer, we also need to ensure that any pending
2281 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2282 * current scanout is retired before unpinning the old
2283 * framebuffer.
2284 *
2285 * This should only fail upon a hung GPU, in which case we
2286 * can safely continue.
2287 */
2288 dev_priv->mm.interruptible = false;
2289 ret = i915_gem_object_finish_gpu(obj);
2290 dev_priv->mm.interruptible = was_interruptible;
2291
2292 return ret;
2293}
2294
198598d0
VS		 2295static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2296{
2297 struct drm_device *dev = crtc->dev;
2298 struct drm_i915_master_private *master_priv;
2299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2300
2301 if (!dev->primary->master)
2302 return;
2303
2304 master_priv = dev->primary->master->driver_priv;
2305 if (!master_priv->sarea_priv)
2306 return;
2307
2308 switch (intel_crtc->pipe) {
2309 case 0:
2310 master_priv->sarea_priv->pipeA_x = x;
2311 master_priv->sarea_priv->pipeA_y = y;
2312 break;
2313 case 1:
2314 master_priv->sarea_priv->pipeB_x = x;
2315 master_priv->sarea_priv->pipeB_y = y;
2316 break;
2317 default:
2318 break;
2319 }
2320}
2321
5c3b82e2 2322static int
3c4fdcfb 2323intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2324 struct drm_framebuffer *fb)
79e53945
JB		 2325{
2326 struct drm_device *dev = crtc->dev;
6b8e6ed0 2327 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2329 struct drm_framebuffer *old_fb;
5c3b82e2 2330 int ret;
79e53945
JB		 2331
2332 /* no fb bound */
94352cf9 2333 if (!fb) {
a5071c2f 2334 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2335 return 0;
2336 }
2337
5826eca5
ED		 2338 if(intel_crtc->plane > dev_priv->num_pipe) {
2339 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2340 intel_crtc->plane,
2341 dev_priv->num_pipe);
5c3b82e2 2342 return -EINVAL;
79e53945
JB		 2343 }
2344
5c3b82e2 2345 mutex_lock(&dev->struct_mutex);
265db958 2346 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2347 to_intel_framebuffer(fb)->obj,
919926ae 2348 NULL);
5c3b82e2
CW		 2349 if (ret != 0) {
2350 mutex_unlock(&dev->struct_mutex);
a5071c2f 2351 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2352 return ret;
2353 }
79e53945 2354
94352cf9 2355 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2356 if (ret) {
94352cf9 2357 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2358 mutex_unlock(&dev->struct_mutex);
a5071c2f 2359 DRM_ERROR("failed to update base address\n");
4e6cfefc 2360 return ret;
79e53945 2361 }
3c4fdcfb 2362
94352cf9
DV		 2363 old_fb = crtc->fb;
2364 crtc->fb = fb;
6c4c86f5
DV		 2365 crtc->x = x;
2366 crtc->y = y;
94352cf9 2367
b7f1de28
CW		 2368 if (old_fb) {
2369 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2370 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2371 }
652c393a 2372
6b8e6ed0 2373 intel_update_fbc(dev);
5c3b82e2 2374 mutex_unlock(&dev->struct_mutex);
79e53945 2375
198598d0 2376 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2377
2378 return 0;
79e53945
JB		 2379}
2380
5e84e1a4
ZW		 2381static void intel_fdi_normal_train(struct drm_crtc *crtc)
2382{
2383 struct drm_device *dev = crtc->dev;
2384 struct drm_i915_private *dev_priv = dev->dev_private;
2385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2386 int pipe = intel_crtc->pipe;
2387 u32 reg, temp;
2388
2389 /* enable normal train */
2390 reg = FDI_TX_CTL(pipe);
2391 temp = I915_READ(reg);
61e499bf 2392 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2393 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2394 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2395 } else {
2396 temp &= ~FDI_LINK_TRAIN_NONE;
2397 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2398 }
5e84e1a4
ZW		 2399 I915_WRITE(reg, temp);
2400
2401 reg = FDI_RX_CTL(pipe);
2402 temp = I915_READ(reg);
2403 if (HAS_PCH_CPT(dev)) {
2404 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2405 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2406 } else {
2407 temp &= ~FDI_LINK_TRAIN_NONE;
2408 temp |= FDI_LINK_TRAIN_NONE;
2409 }
2410 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2411
2412 /* wait one idle pattern time */
2413 POSTING_READ(reg);
2414 udelay(1000);
357555c0
JB		 2415
2416 /* IVB wants error correction enabled */
2417 if (IS_IVYBRIDGE(dev))
2418 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2419 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2420}
2421
01a415fd
DV		 2422static void ivb_modeset_global_resources(struct drm_device *dev)
2423{
2424 struct drm_i915_private *dev_priv = dev->dev_private;
2425 struct intel_crtc *pipe_B_crtc =
2426 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2427 struct intel_crtc *pipe_C_crtc =
2428 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2429 uint32_t temp;
2430
2431 /* When everything is off disable fdi C so that we could enable fdi B
2432 * with all lanes. XXX: This misses the case where a pipe is not using
2433 * any pch resources and so doesn't need any fdi lanes. */
2434 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2435 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2436 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2437
2438 temp = I915_READ(SOUTH_CHICKEN1);
2439 temp &= ~FDI_BC_BIFURCATION_SELECT;
2440 DRM_DEBUG_KMS("disabling fdi C rx\n");
2441 I915_WRITE(SOUTH_CHICKEN1, temp);
2442 }
2443}
2444
8db9d77b
ZW		 2445/* The FDI link training functions for ILK/Ibexpeak. */
2446static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2447{
2448 struct drm_device *dev = crtc->dev;
2449 struct drm_i915_private *dev_priv = dev->dev_private;
2450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2451 int pipe = intel_crtc->pipe;
0fc932b8 2452 int plane = intel_crtc->plane;
5eddb70b 2453 u32 reg, temp, tries;
8db9d77b 2454
0fc932b8
JB		 2455 /* FDI needs bits from pipe & plane first */
2456 assert_pipe_enabled(dev_priv, pipe);
2457 assert_plane_enabled(dev_priv, plane);
2458
e1a44743
AJ		 2459 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2460 for train result */
5eddb70b
CW		 2461 reg = FDI_RX_IMR(pipe);
2462 temp = I915_READ(reg);
e1a44743
AJ		 2463 temp &= ~FDI_RX_SYMBOL_LOCK;
2464 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2465 I915_WRITE(reg, temp);
2466 I915_READ(reg);
e1a44743
AJ		 2467 udelay(150);
2468
8db9d77b 2469 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2470 reg = FDI_TX_CTL(pipe);
2471 temp = I915_READ(reg);
77ffb597
AJ		 2472 temp &= ~(7 << 19);
2473 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2474 temp &= ~FDI_LINK_TRAIN_NONE;
2475 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2476 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2477
5eddb70b
CW		 2478 reg = FDI_RX_CTL(pipe);
2479 temp = I915_READ(reg);
8db9d77b
ZW		 2480 temp &= ~FDI_LINK_TRAIN_NONE;
2481 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2482 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2483
2484 POSTING_READ(reg);
8db9d77b
ZW		 2485 udelay(150);
2486
5b2adf89 2487 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2488 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2489 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2490 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2491
5eddb70b 2492 reg = FDI_RX_IIR(pipe);
e1a44743 2493 for (tries = 0; tries < 5; tries++) {
5eddb70b 2494 temp = I915_READ(reg);
8db9d77b
ZW		 2495 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2496
2497 if ((temp & FDI_RX_BIT_LOCK)) {
2498 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2499 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2500 break;
2501 }
8db9d77b 2502 }
e1a44743 2503 if (tries == 5)
5eddb70b 2504 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2505
2506 /* Train 2 */
5eddb70b
CW		 2507 reg = FDI_TX_CTL(pipe);
2508 temp = I915_READ(reg);
8db9d77b
ZW		 2509 temp &= ~FDI_LINK_TRAIN_NONE;
2510 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2511 I915_WRITE(reg, temp);
8db9d77b 2512
5eddb70b
CW		 2513 reg = FDI_RX_CTL(pipe);
2514 temp = I915_READ(reg);
8db9d77b
ZW		 2515 temp &= ~FDI_LINK_TRAIN_NONE;
2516 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2517 I915_WRITE(reg, temp);
8db9d77b 2518
5eddb70b
CW		 2519 POSTING_READ(reg);
2520 udelay(150);
8db9d77b 2521
5eddb70b 2522 reg = FDI_RX_IIR(pipe);
e1a44743 2523 for (tries = 0; tries < 5; tries++) {
5eddb70b 2524 temp = I915_READ(reg);
8db9d77b
ZW		 2525 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2526
2527 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2528 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2529 DRM_DEBUG_KMS("FDI train 2 done.\n");
2530 break;
2531 }
8db9d77b 2532 }
e1a44743 2533 if (tries == 5)
5eddb70b 2534 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2535
2536 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2537
8db9d77b
ZW		 2538}
2539
0206e353 2540static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2541 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2542 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2543 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2544 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2545};
2546
2547/* The FDI link training functions for SNB/Cougarpoint. */
2548static void gen6_fdi_link_train(struct drm_crtc *crtc)
2549{
2550 struct drm_device *dev = crtc->dev;
2551 struct drm_i915_private *dev_priv = dev->dev_private;
2552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2553 int pipe = intel_crtc->pipe;
fa37d39e 2554 u32 reg, temp, i, retry;
8db9d77b 2555
e1a44743
AJ		 2556 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2557 for train result */
5eddb70b
CW		 2558 reg = FDI_RX_IMR(pipe);
2559 temp = I915_READ(reg);
e1a44743
AJ		 2560 temp &= ~FDI_RX_SYMBOL_LOCK;
2561 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2562 I915_WRITE(reg, temp);
2563
2564 POSTING_READ(reg);
e1a44743
AJ		 2565 udelay(150);
2566
8db9d77b 2567 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2568 reg = FDI_TX_CTL(pipe);
2569 temp = I915_READ(reg);
77ffb597
AJ		 2570 temp &= ~(7 << 19);
2571 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2572 temp &= ~FDI_LINK_TRAIN_NONE;
2573 temp |= FDI_LINK_TRAIN_PATTERN_1;
2574 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2575 /* SNB-B */
2576 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2577 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2578
d74cf324
DV		 2579 I915_WRITE(FDI_RX_MISC(pipe),
2580 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2581
5eddb70b
CW		 2582 reg = FDI_RX_CTL(pipe);
2583 temp = I915_READ(reg);
8db9d77b
ZW		 2584 if (HAS_PCH_CPT(dev)) {
2585 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2586 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2587 } else {
2588 temp &= ~FDI_LINK_TRAIN_NONE;
2589 temp |= FDI_LINK_TRAIN_PATTERN_1;
2590 }
5eddb70b
CW		 2591 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2592
2593 POSTING_READ(reg);
8db9d77b
ZW		 2594 udelay(150);
2595
0206e353 2596 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2597 reg = FDI_TX_CTL(pipe);
2598 temp = I915_READ(reg);
8db9d77b
ZW		 2599 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2600 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2601 I915_WRITE(reg, temp);
2602
2603 POSTING_READ(reg);
8db9d77b
ZW		 2604 udelay(500);
2605
fa37d39e
SP		 2606 for (retry = 0; retry < 5; retry++) {
2607 reg = FDI_RX_IIR(pipe);
2608 temp = I915_READ(reg);
2609 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2610 if (temp & FDI_RX_BIT_LOCK) {
2611 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2612 DRM_DEBUG_KMS("FDI train 1 done.\n");
2613 break;
2614 }
2615 udelay(50);
8db9d77b 2616 }
fa37d39e
SP		 2617 if (retry < 5)
2618 break;
8db9d77b
ZW		 2619 }
2620 if (i == 4)
5eddb70b 2621 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2622
2623 /* Train 2 */
5eddb70b
CW		 2624 reg = FDI_TX_CTL(pipe);
2625 temp = I915_READ(reg);
8db9d77b
ZW		 2626 temp &= ~FDI_LINK_TRAIN_NONE;
2627 temp |= FDI_LINK_TRAIN_PATTERN_2;
2628 if (IS_GEN6(dev)) {
2629 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2630 /* SNB-B */
2631 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2632 }
5eddb70b 2633 I915_WRITE(reg, temp);
8db9d77b 2634
5eddb70b
CW		 2635 reg = FDI_RX_CTL(pipe);
2636 temp = I915_READ(reg);
8db9d77b
ZW		 2637 if (HAS_PCH_CPT(dev)) {
2638 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2639 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2640 } else {
2641 temp &= ~FDI_LINK_TRAIN_NONE;
2642 temp |= FDI_LINK_TRAIN_PATTERN_2;
2643 }
5eddb70b
CW		 2644 I915_WRITE(reg, temp);
2645
2646 POSTING_READ(reg);
8db9d77b
ZW		 2647 udelay(150);
2648
0206e353 2649 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2650 reg = FDI_TX_CTL(pipe);
2651 temp = I915_READ(reg);
8db9d77b
ZW		 2652 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2653 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2654 I915_WRITE(reg, temp);
2655
2656 POSTING_READ(reg);
8db9d77b
ZW		 2657 udelay(500);
2658
fa37d39e
SP		 2659 for (retry = 0; retry < 5; retry++) {
2660 reg = FDI_RX_IIR(pipe);
2661 temp = I915_READ(reg);
2662 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2663 if (temp & FDI_RX_SYMBOL_LOCK) {
2664 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2665 DRM_DEBUG_KMS("FDI train 2 done.\n");
2666 break;
2667 }
2668 udelay(50);
8db9d77b 2669 }
fa37d39e
SP		 2670 if (retry < 5)
2671 break;
8db9d77b
ZW		 2672 }
2673 if (i == 4)
5eddb70b 2674 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2675
2676 DRM_DEBUG_KMS("FDI train done.\n");
2677}
2678
357555c0
JB		 2679/* Manual link training for Ivy Bridge A0 parts */
2680static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2681{
2682 struct drm_device *dev = crtc->dev;
2683 struct drm_i915_private *dev_priv = dev->dev_private;
2684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2685 int pipe = intel_crtc->pipe;
2686 u32 reg, temp, i;
2687
2688 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2689 for train result */
2690 reg = FDI_RX_IMR(pipe);
2691 temp = I915_READ(reg);
2692 temp &= ~FDI_RX_SYMBOL_LOCK;
2693 temp &= ~FDI_RX_BIT_LOCK;
2694 I915_WRITE(reg, temp);
2695
2696 POSTING_READ(reg);
2697 udelay(150);
2698
01a415fd
DV		 2699 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2700 I915_READ(FDI_RX_IIR(pipe)));
2701
357555c0
JB		 2702 /* enable CPU FDI TX and PCH FDI RX */
2703 reg = FDI_TX_CTL(pipe);
2704 temp = I915_READ(reg);
2705 temp &= ~(7 << 19);
2706 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2707 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2708 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2709 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2710 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2711 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2712 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2713
d74cf324
DV		 2714 I915_WRITE(FDI_RX_MISC(pipe),
2715 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2716
357555c0
JB		 2717 reg = FDI_RX_CTL(pipe);
2718 temp = I915_READ(reg);
2719 temp &= ~FDI_LINK_TRAIN_AUTO;
2720 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2721 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2722 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2723 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2724
2725 POSTING_READ(reg);
2726 udelay(150);
2727
0206e353 2728 for (i = 0; i < 4; i++) {
357555c0
JB		 2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732 temp |= snb_b_fdi_train_param[i];
2733 I915_WRITE(reg, temp);
2734
2735 POSTING_READ(reg);
2736 udelay(500);
2737
2738 reg = FDI_RX_IIR(pipe);
2739 temp = I915_READ(reg);
2740 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2741
2742 if (temp & FDI_RX_BIT_LOCK ||
2743 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2744 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2745 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2746 break;
2747 }
2748 }
2749 if (i == 4)
2750 DRM_ERROR("FDI train 1 fail!\n");
2751
2752 /* Train 2 */
2753 reg = FDI_TX_CTL(pipe);
2754 temp = I915_READ(reg);
2755 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2756 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2757 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2758 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2759 I915_WRITE(reg, temp);
2760
2761 reg = FDI_RX_CTL(pipe);
2762 temp = I915_READ(reg);
2763 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2764 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2765 I915_WRITE(reg, temp);
2766
2767 POSTING_READ(reg);
2768 udelay(150);
2769
0206e353 2770 for (i = 0; i < 4; i++) {
357555c0
JB		 2771 reg = FDI_TX_CTL(pipe);
2772 temp = I915_READ(reg);
2773 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2774 temp |= snb_b_fdi_train_param[i];
2775 I915_WRITE(reg, temp);
2776
2777 POSTING_READ(reg);
2778 udelay(500);
2779
2780 reg = FDI_RX_IIR(pipe);
2781 temp = I915_READ(reg);
2782 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2783
2784 if (temp & FDI_RX_SYMBOL_LOCK) {
2785 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2786 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2787 break;
2788 }
2789 }
2790 if (i == 4)
2791 DRM_ERROR("FDI train 2 fail!\n");
2792
2793 DRM_DEBUG_KMS("FDI train done.\n");
2794}
2795
88cefb6c 2796static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2797{
88cefb6c 2798 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2799 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2800 int pipe = intel_crtc->pipe;
5eddb70b 2801 u32 reg, temp;
79e53945 2802
c64e311e 2803
c98e9dcf 2804 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2805 reg = FDI_RX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2808 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2809 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2810 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2811
2812 POSTING_READ(reg);
c98e9dcf
JB		 2813 udelay(200);
2814
2815 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2816 temp = I915_READ(reg);
2817 I915_WRITE(reg, temp | FDI_PCDCLK);
2818
2819 POSTING_READ(reg);
c98e9dcf
JB		 2820 udelay(200);
2821
20749730
PZ		 2822 /* Enable CPU FDI TX PLL, always on for Ironlake */
2823 reg = FDI_TX_CTL(pipe);
2824 temp = I915_READ(reg);
2825 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2826 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2827
20749730
PZ		 2828 POSTING_READ(reg);
2829 udelay(100);
6be4a607 2830 }
0e23b99d
JB		 2831}
2832
88cefb6c
DV		 2833static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2834{
2835 struct drm_device *dev = intel_crtc->base.dev;
2836 struct drm_i915_private *dev_priv = dev->dev_private;
2837 int pipe = intel_crtc->pipe;
2838 u32 reg, temp;
2839
2840 /* Switch from PCDclk to Rawclk */
2841 reg = FDI_RX_CTL(pipe);
2842 temp = I915_READ(reg);
2843 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2844
2845 /* Disable CPU FDI TX PLL */
2846 reg = FDI_TX_CTL(pipe);
2847 temp = I915_READ(reg);
2848 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2849
2850 POSTING_READ(reg);
2851 udelay(100);
2852
2853 reg = FDI_RX_CTL(pipe);
2854 temp = I915_READ(reg);
2855 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2856
2857 /* Wait for the clocks to turn off. */
2858 POSTING_READ(reg);
2859 udelay(100);
2860}
2861
0fc932b8
JB		 2862static void ironlake_fdi_disable(struct drm_crtc *crtc)
2863{
2864 struct drm_device *dev = crtc->dev;
2865 struct drm_i915_private *dev_priv = dev->dev_private;
2866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2867 int pipe = intel_crtc->pipe;
2868 u32 reg, temp;
2869
2870 /* disable CPU FDI tx and PCH FDI rx */
2871 reg = FDI_TX_CTL(pipe);
2872 temp = I915_READ(reg);
2873 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2874 POSTING_READ(reg);
2875
2876 reg = FDI_RX_CTL(pipe);
2877 temp = I915_READ(reg);
2878 temp &= ~(0x7 << 16);
dfd07d72 2879 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2880 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2881
2882 POSTING_READ(reg);
2883 udelay(100);
2884
2885 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2886 if (HAS_PCH_IBX(dev)) {
2887 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2888 }
0fc932b8
JB		 2889
2890 /* still set train pattern 1 */
2891 reg = FDI_TX_CTL(pipe);
2892 temp = I915_READ(reg);
2893 temp &= ~FDI_LINK_TRAIN_NONE;
2894 temp |= FDI_LINK_TRAIN_PATTERN_1;
2895 I915_WRITE(reg, temp);
2896
2897 reg = FDI_RX_CTL(pipe);
2898 temp = I915_READ(reg);
2899 if (HAS_PCH_CPT(dev)) {
2900 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2901 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2902 } else {
2903 temp &= ~FDI_LINK_TRAIN_NONE;
2904 temp |= FDI_LINK_TRAIN_PATTERN_1;
2905 }
2906 /* BPC in FDI rx is consistent with that in PIPECONF */
2907 temp &= ~(0x07 << 16);
dfd07d72 2908 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2909 I915_WRITE(reg, temp);
2910
2911 POSTING_READ(reg);
2912 udelay(100);
2913}
2914
5bb61643
CW		 2915static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2916{
2917 struct drm_device *dev = crtc->dev;
2918 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2920 unsigned long flags;
2921 bool pending;
2922
10d83730
VS		 2923 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2924 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2925 return false;
2926
2927 spin_lock_irqsave(&dev->event_lock, flags);
2928 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2929 spin_unlock_irqrestore(&dev->event_lock, flags);
2930
2931 return pending;
2932}
2933
e6c3a2a6
CW		 2934static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2935{
0f91128d 2936 struct drm_device *dev = crtc->dev;
5bb61643 2937 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2938
2939 if (crtc->fb == NULL)
2940 return;
2941
2c10d571
DV		 2942 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2943
5bb61643
CW		 2944 wait_event(dev_priv->pending_flip_queue,
2945 !intel_crtc_has_pending_flip(crtc));
2946
0f91128d
CW		 2947 mutex_lock(&dev->struct_mutex);
2948 intel_finish_fb(crtc->fb);
2949 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2950}
2951
fc316cbe 2952static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2953{
2954 struct drm_device *dev = crtc->dev;
228d3e36 2955 struct intel_encoder *intel_encoder;
040484af
JB		 2956
2957 /*
2958 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2959 * must be driven by its own crtc; no sharing is possible.
2960 */
228d3e36 2961 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2962 switch (intel_encoder->type) {
040484af 2963 case INTEL_OUTPUT_EDP:
228d3e36 2964 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2965 return false;
2966 continue;
2967 }
2968 }
2969
2970 return true;
2971}
2972
fc316cbe
PZ		 2973static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2974{
2975 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2976}
2977
e615efe4
ED		 2978/* Program iCLKIP clock to the desired frequency */
2979static void lpt_program_iclkip(struct drm_crtc *crtc)
2980{
2981 struct drm_device *dev = crtc->dev;
2982 struct drm_i915_private *dev_priv = dev->dev_private;
2983 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2984 u32 temp;
2985
09153000
DV		 2986 mutex_lock(&dev_priv->dpio_lock);
2987
e615efe4
ED		 2988 /* It is necessary to ungate the pixclk gate prior to programming
2989 * the divisors, and gate it back when it is done.
2990 */
2991 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2992
2993 /* Disable SSCCTL */
2994 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2995 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2996 SBI_SSCCTL_DISABLE,
2997 SBI_ICLK);
e615efe4
ED		 2998
2999 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3000 if (crtc->mode.clock == 20000) {
3001 auxdiv = 1;
3002 divsel = 0x41;
3003 phaseinc = 0x20;
3004 } else {
3005 /* The iCLK virtual clock root frequency is in MHz,
3006 * but the crtc->mode.clock in in KHz. To get the divisors,
3007 * it is necessary to divide one by another, so we
3008 * convert the virtual clock precision to KHz here for higher
3009 * precision.
3010 */
3011 u32 iclk_virtual_root_freq = 172800 * 1000;
3012 u32 iclk_pi_range = 64;
3013 u32 desired_divisor, msb_divisor_value, pi_value;
3014
3015 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3016 msb_divisor_value = desired_divisor / iclk_pi_range;
3017 pi_value = desired_divisor % iclk_pi_range;
3018
3019 auxdiv = 0;
3020 divsel = msb_divisor_value - 2;
3021 phaseinc = pi_value;
3022 }
3023
3024 /* This should not happen with any sane values */
3025 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3026 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3027 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3028 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3029
3030 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3031 crtc->mode.clock,
3032 auxdiv,
3033 divsel,
3034 phasedir,
3035 phaseinc);
3036
3037 /* Program SSCDIVINTPHASE6 */
988d6ee8 3038 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3039 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3040 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3041 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3042 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3043 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3044 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3045 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3046
3047 /* Program SSCAUXDIV */
988d6ee8 3048 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3049 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3050 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3051 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3052
3053 /* Enable modulator and associated divider */
988d6ee8 3054 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3055 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3056 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3057
3058 /* Wait for initialization time */
3059 udelay(24);
3060
3061 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3062
3063 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3064}
3065
f67a559d
JB		 3066/*
3067 * Enable PCH resources required for PCH ports:
3068 * - PCH PLLs
3069 * - FDI training & RX/TX
3070 * - update transcoder timings
3071 * - DP transcoding bits
3072 * - transcoder
3073 */
3074static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3075{
3076 struct drm_device *dev = crtc->dev;
3077 struct drm_i915_private *dev_priv = dev->dev_private;
3078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3079 int pipe = intel_crtc->pipe;
ee7b9f93 3080 u32 reg, temp;
2c07245f 3081
e7e164db
CW		 3082 assert_transcoder_disabled(dev_priv, pipe);
3083
cd986abb
DV		 3084 /* Write the TU size bits before fdi link training, so that error
3085 * detection works. */
3086 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3087 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3088
c98e9dcf 3089 /* For PCH output, training FDI link */
674cf967 3090 dev_priv->display.fdi_link_train(crtc);
2c07245f 3091
572deb37
DV		 3092 /* XXX: pch pll's can be enabled any time before we enable the PCH
3093 * transcoder, and we actually should do this to not upset any PCH
3094 * transcoder that already use the clock when we share it.
3095 *
3096 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3097 * unconditionally resets the pll - we need that to have the right LVDS
3098 * enable sequence. */
b6b4e185 3099 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3100
303b81e0 3101 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3102 u32 sel;
4b645f14 3103
c98e9dcf 3104 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3105 switch (pipe) {
3106 default:
3107 case 0:
3108 temp |= TRANSA_DPLL_ENABLE;
3109 sel = TRANSA_DPLLB_SEL;
3110 break;
3111 case 1:
3112 temp |= TRANSB_DPLL_ENABLE;
3113 sel = TRANSB_DPLLB_SEL;
3114 break;
3115 case 2:
3116 temp |= TRANSC_DPLL_ENABLE;
3117 sel = TRANSC_DPLLB_SEL;
3118 break;
d64311ab 3119 }
ee7b9f93
JB		 3120 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3121 temp |= sel;
3122 else
3123 temp &= ~sel;
c98e9dcf 3124 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3125 }
5eddb70b 3126
d9b6cb56
JB		 3127 /* set transcoder timing, panel must allow it */
3128 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3129 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3130 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3131 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3132
5eddb70b
CW		 3133 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3134 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3135 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3136 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3137
303b81e0 3138 intel_fdi_normal_train(crtc);
5e84e1a4 3139
c98e9dcf
JB		 3140 /* For PCH DP, enable TRANS_DP_CTL */
3141 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3142 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3143 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3144 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3145 reg = TRANS_DP_CTL(pipe);
3146 temp = I915_READ(reg);
3147 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3148 TRANS_DP_SYNC_MASK |
3149 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3150 temp |= (TRANS_DP_OUTPUT_ENABLE |
3151 TRANS_DP_ENH_FRAMING);
9325c9f0 3152 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3153
3154 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3155 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3156 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3157 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3158
3159 switch (intel_trans_dp_port_sel(crtc)) {
3160 case PCH_DP_B:
5eddb70b 3161 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3162 break;
3163 case PCH_DP_C:
5eddb70b 3164 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3165 break;
3166 case PCH_DP_D:
5eddb70b 3167 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3168 break;
3169 default:
e95d41e1 3170 BUG();
32f9d658 3171 }
2c07245f 3172
5eddb70b 3173 I915_WRITE(reg, temp);
6be4a607 3174 }
b52eb4dc 3175
b8a4f404 3176 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3177}
3178
1507e5bd
PZ		 3179static void lpt_pch_enable(struct drm_crtc *crtc)
3180{
3181 struct drm_device *dev = crtc->dev;
3182 struct drm_i915_private *dev_priv = dev->dev_private;
3183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3184 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3185
daed2dbb 3186 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3187
8c52b5e8 3188 lpt_program_iclkip(crtc);
1507e5bd 3189
0540e488 3190 /* Set transcoder timing. */
daed2dbb
PZ		 3191 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3192 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3193 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3194
daed2dbb
PZ		 3195 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3196 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3197 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3198 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3199
937bb610 3200 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3201}
3202
ee7b9f93
JB		 3203static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3204{
3205 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3206
3207 if (pll == NULL)
3208 return;
3209
3210 if (pll->refcount == 0) {
3211 WARN(1, "bad PCH PLL refcount\n");
3212 return;
3213 }
3214
3215 --pll->refcount;
3216 intel_crtc->pch_pll = NULL;
3217}
3218
3219static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3220{
3221 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3222 struct intel_pch_pll *pll;
3223 int i;
3224
3225 pll = intel_crtc->pch_pll;
3226 if (pll) {
3227 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3228 intel_crtc->base.base.id, pll->pll_reg);
3229 goto prepare;
3230 }
3231
98b6bd99
DV		 3232 if (HAS_PCH_IBX(dev_priv->dev)) {
3233 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3234 i = intel_crtc->pipe;
3235 pll = &dev_priv->pch_plls[i];
3236
3237 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3238 intel_crtc->base.base.id, pll->pll_reg);
3239
3240 goto found;
3241 }
3242
ee7b9f93
JB		 3243 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3244 pll = &dev_priv->pch_plls[i];
3245
3246 /* Only want to check enabled timings first */
3247 if (pll->refcount == 0)
3248 continue;
3249
3250 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3251 fp == I915_READ(pll->fp0_reg)) {
3252 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3253 intel_crtc->base.base.id,
3254 pll->pll_reg, pll->refcount, pll->active);
3255
3256 goto found;
3257 }
3258 }
3259
3260 /* Ok no matching timings, maybe there's a free one? */
3261 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3262 pll = &dev_priv->pch_plls[i];
3263 if (pll->refcount == 0) {
3264 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3265 intel_crtc->base.base.id, pll->pll_reg);
3266 goto found;
3267 }
3268 }
3269
3270 return NULL;
3271
3272found:
3273 intel_crtc->pch_pll = pll;
3274 pll->refcount++;
3275 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3276prepare: /* separate function? */
3277 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3278
e04c7350
CW		 3279 /* Wait for the clocks to stabilize before rewriting the regs */
3280 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3281 POSTING_READ(pll->pll_reg);
3282 udelay(150);
e04c7350
CW		 3283
3284 I915_WRITE(pll->fp0_reg, fp);
3285 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3286 pll->on = false;
3287 return pll;
3288}
3289
d4270e57
JB		 3290void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3291{
3292 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3293 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3294 u32 temp;
3295
3296 temp = I915_READ(dslreg);
3297 udelay(500);
3298 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3299 if (wait_for(I915_READ(dslreg) != temp, 5))
3300 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3301 }
3302}
3303
f67a559d
JB		 3304static void ironlake_crtc_enable(struct drm_crtc *crtc)
3305{
3306 struct drm_device *dev = crtc->dev;
3307 struct drm_i915_private *dev_priv = dev->dev_private;
3308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3309 struct intel_encoder *encoder;
f67a559d
JB		 3310 int pipe = intel_crtc->pipe;
3311 int plane = intel_crtc->plane;
3312 u32 temp;
3313 bool is_pch_port;
3314
08a48469
DV		 3315 WARN_ON(!crtc->enabled);
3316
f67a559d
JB		 3317 if (intel_crtc->active)
3318 return;
3319
3320 intel_crtc->active = true;
3321 intel_update_watermarks(dev);
3322
3323 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3324 temp = I915_READ(PCH_LVDS);
3325 if ((temp & LVDS_PORT_EN) == 0)
3326 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3327 }
3328
fc316cbe 3329 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3330
46b6f814 3331 if (is_pch_port) {
fff367c7
DV		 3332 /* Note: FDI PLL enabling _must_ be done before we enable the
3333 * cpu pipes, hence this is separate from all the other fdi/pch
3334 * enabling. */
88cefb6c 3335 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3336 } else {
3337 assert_fdi_tx_disabled(dev_priv, pipe);
3338 assert_fdi_rx_disabled(dev_priv, pipe);
3339 }
f67a559d 3340
bf49ec8c
DV		 3341 for_each_encoder_on_crtc(dev, crtc, encoder)
3342 if (encoder->pre_enable)
3343 encoder->pre_enable(encoder);
f67a559d
JB		 3344
3345 /* Enable panel fitting for LVDS */
3346 if (dev_priv->pch_pf_size &&
547dc041
JN		 3347 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3348 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3349 /* Force use of hard-coded filter coefficients
3350 * as some pre-programmed values are broken,
3351 * e.g. x201.
3352 */
13888d78
PZ		 3353 if (IS_IVYBRIDGE(dev))
3354 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3355 PF_PIPE_SEL_IVB(pipe));
3356 else
3357 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3358 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3359 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3360 }
3361
9c54c0dd
JB		 3362 /*
3363 * On ILK+ LUT must be loaded before the pipe is running but with
3364 * clocks enabled
3365 */
3366 intel_crtc_load_lut(crtc);
3367
f67a559d
JB		 3368 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3369 intel_enable_plane(dev_priv, plane, pipe);
3370
3371 if (is_pch_port)
3372 ironlake_pch_enable(crtc);
c98e9dcf 3373
d1ebd816 3374 mutex_lock(&dev->struct_mutex);
bed4a673 3375 intel_update_fbc(dev);
d1ebd816
BW		 3376 mutex_unlock(&dev->struct_mutex);
3377
6b383a7f 3378 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3379
fa5c73b1
DV		 3380 for_each_encoder_on_crtc(dev, crtc, encoder)
3381 encoder->enable(encoder);
61b77ddd
DV		 3382
3383 if (HAS_PCH_CPT(dev))
3384 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3385
3386 /*
3387 * There seems to be a race in PCH platform hw (at least on some
3388 * outputs) where an enabled pipe still completes any pageflip right
3389 * away (as if the pipe is off) instead of waiting for vblank. As soon
3390 * as the first vblank happend, everything works as expected. Hence just
3391 * wait for one vblank before returning to avoid strange things
3392 * happening.
3393 */
3394 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3395}
3396
4f771f10
PZ		 3397static void haswell_crtc_enable(struct drm_crtc *crtc)
3398{
3399 struct drm_device *dev = crtc->dev;
3400 struct drm_i915_private *dev_priv = dev->dev_private;
3401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3402 struct intel_encoder *encoder;
3403 int pipe = intel_crtc->pipe;
3404 int plane = intel_crtc->plane;
4f771f10
PZ		 3405 bool is_pch_port;
3406
3407 WARN_ON(!crtc->enabled);
3408
3409 if (intel_crtc->active)
3410 return;
3411
3412 intel_crtc->active = true;
3413 intel_update_watermarks(dev);
3414
fc316cbe 3415 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3416
83616634 3417 if (is_pch_port)
04945641 3418 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3419
3420 for_each_encoder_on_crtc(dev, crtc, encoder)
3421 if (encoder->pre_enable)
3422 encoder->pre_enable(encoder);
3423
1f544388 3424 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3425
1f544388 3426 /* Enable panel fitting for eDP */
547dc041
JN		 3427 if (dev_priv->pch_pf_size &&
3428 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3429 /* Force use of hard-coded filter coefficients
3430 * as some pre-programmed values are broken,
3431 * e.g. x201.
3432 */
54075a7d
PZ		 3433 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3434 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3435 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3436 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3437 }
3438
3439 /*
3440 * On ILK+ LUT must be loaded before the pipe is running but with
3441 * clocks enabled
3442 */
3443 intel_crtc_load_lut(crtc);
3444
1f544388
PZ		 3445 intel_ddi_set_pipe_settings(crtc);
3446 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3447
3448 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3449 intel_enable_plane(dev_priv, plane, pipe);
3450
3451 if (is_pch_port)
1507e5bd 3452 lpt_pch_enable(crtc);
4f771f10
PZ		 3453
3454 mutex_lock(&dev->struct_mutex);
3455 intel_update_fbc(dev);
3456 mutex_unlock(&dev->struct_mutex);
3457
3458 intel_crtc_update_cursor(crtc, true);
3459
3460 for_each_encoder_on_crtc(dev, crtc, encoder)
3461 encoder->enable(encoder);
3462
4f771f10
PZ		 3463 /*
3464 * There seems to be a race in PCH platform hw (at least on some
3465 * outputs) where an enabled pipe still completes any pageflip right
3466 * away (as if the pipe is off) instead of waiting for vblank. As soon
3467 * as the first vblank happend, everything works as expected. Hence just
3468 * wait for one vblank before returning to avoid strange things
3469 * happening.
3470 */
3471 intel_wait_for_vblank(dev, intel_crtc->pipe);
3472}
3473
6be4a607
JB		 3474static void ironlake_crtc_disable(struct drm_crtc *crtc)
3475{
3476 struct drm_device *dev = crtc->dev;
3477 struct drm_i915_private *dev_priv = dev->dev_private;
3478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3479 struct intel_encoder *encoder;
6be4a607
JB		 3480 int pipe = intel_crtc->pipe;
3481 int plane = intel_crtc->plane;
5eddb70b 3482 u32 reg, temp;
b52eb4dc 3483
ef9c3aee 3484
f7abfe8b
CW		 3485 if (!intel_crtc->active)
3486 return;
3487
ea9d758d
DV		 3488 for_each_encoder_on_crtc(dev, crtc, encoder)
3489 encoder->disable(encoder);
3490
e6c3a2a6 3491 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3492 drm_vblank_off(dev, pipe);
6b383a7f 3493 intel_crtc_update_cursor(crtc, false);
5eddb70b 3494
b24e7179 3495 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3496
973d04f9
CW		 3497 if (dev_priv->cfb_plane == plane)
3498 intel_disable_fbc(dev);
2c07245f 3499
b24e7179 3500 intel_disable_pipe(dev_priv, pipe);
32f9d658 3501
6be4a607 3502 /* Disable PF */
9db4a9c7
JB		 3503 I915_WRITE(PF_CTL(pipe), 0);
3504 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3505
bf49ec8c
DV		 3506 for_each_encoder_on_crtc(dev, crtc, encoder)
3507 if (encoder->post_disable)
3508 encoder->post_disable(encoder);
2c07245f 3509
0fc932b8 3510 ironlake_fdi_disable(crtc);
249c0e64 3511
b8a4f404 3512 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3513
6be4a607
JB		 3514 if (HAS_PCH_CPT(dev)) {
3515 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3516 reg = TRANS_DP_CTL(pipe);
3517 temp = I915_READ(reg);
3518 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3519 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3520 I915_WRITE(reg, temp);
6be4a607
JB		 3521
3522 /* disable DPLL_SEL */
3523 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3524 switch (pipe) {
3525 case 0:
d64311ab 3526 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3527 break;
3528 case 1:
6be4a607 3529 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3530 break;
3531 case 2:
4b645f14 3532 /* C shares PLL A or B */
d64311ab 3533 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3534 break;
3535 default:
3536 BUG(); /* wtf */
3537 }
6be4a607 3538 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3539 }
e3421a18 3540
6be4a607 3541 /* disable PCH DPLL */
ee7b9f93 3542 intel_disable_pch_pll(intel_crtc);
8db9d77b 3543
88cefb6c 3544 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3545
f7abfe8b 3546 intel_crtc->active = false;
6b383a7f 3547 intel_update_watermarks(dev);
d1ebd816
BW		 3548
3549 mutex_lock(&dev->struct_mutex);
6b383a7f 3550 intel_update_fbc(dev);
d1ebd816 3551 mutex_unlock(&dev->struct_mutex);
6be4a607 3552}
1b3c7a47 3553
4f771f10 3554static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3555{
4f771f10
PZ		 3556 struct drm_device *dev = crtc->dev;
3557 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3559 struct intel_encoder *encoder;
3560 int pipe = intel_crtc->pipe;
3561 int plane = intel_crtc->plane;
ad80a810 3562 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3563 bool is_pch_port;
ee7b9f93 3564
4f771f10
PZ		 3565 if (!intel_crtc->active)
3566 return;
3567
83616634
PZ		 3568 is_pch_port = haswell_crtc_driving_pch(crtc);
3569
4f771f10
PZ		 3570 for_each_encoder_on_crtc(dev, crtc, encoder)
3571 encoder->disable(encoder);
3572
3573 intel_crtc_wait_for_pending_flips(crtc);
3574 drm_vblank_off(dev, pipe);
3575 intel_crtc_update_cursor(crtc, false);
3576
3577 intel_disable_plane(dev_priv, plane, pipe);
3578
3579 if (dev_priv->cfb_plane == plane)
3580 intel_disable_fbc(dev);
3581
3582 intel_disable_pipe(dev_priv, pipe);
3583
ad80a810 3584 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3585
3586 /* Disable PF */
3587 I915_WRITE(PF_CTL(pipe), 0);
3588 I915_WRITE(PF_WIN_SZ(pipe), 0);
3589
1f544388 3590 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3591
3592 for_each_encoder_on_crtc(dev, crtc, encoder)
3593 if (encoder->post_disable)
3594 encoder->post_disable(encoder);
3595
83616634 3596 if (is_pch_port) {
ab4d966c 3597 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3598 intel_ddi_fdi_disable(crtc);
83616634 3599 }
4f771f10
PZ		 3600
3601 intel_crtc->active = false;
3602 intel_update_watermarks(dev);
3603
3604 mutex_lock(&dev->struct_mutex);
3605 intel_update_fbc(dev);
3606 mutex_unlock(&dev->struct_mutex);
3607}
3608
ee7b9f93
JB		 3609static void ironlake_crtc_off(struct drm_crtc *crtc)
3610{
3611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3612 intel_put_pch_pll(intel_crtc);
3613}
3614
6441ab5f
PZ		 3615static void haswell_crtc_off(struct drm_crtc *crtc)
3616{
a5c961d1
PZ		 3617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3618
3619 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3620 * start using it. */
1a240d4d 3621 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3622
6441ab5f
PZ		 3623 intel_ddi_put_crtc_pll(crtc);
3624}
3625
02e792fb
DV		 3626static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3627{
02e792fb 3628 if (!enable && intel_crtc->overlay) {
23f09ce3 3629 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3630 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3631
23f09ce3 3632 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3633 dev_priv->mm.interruptible = false;
3634 (void) intel_overlay_switch_off(intel_crtc->overlay);
3635 dev_priv->mm.interruptible = true;
23f09ce3 3636 mutex_unlock(&dev->struct_mutex);
02e792fb 3637 }
02e792fb 3638
5dcdbcb0
CW		 3639 /* Let userspace switch the overlay on again. In most cases userspace
3640 * has to recompute where to put it anyway.
3641 */
02e792fb
DV		 3642}
3643
0b8765c6 3644static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3645{
3646 struct drm_device *dev = crtc->dev;
79e53945
JB		 3647 struct drm_i915_private *dev_priv = dev->dev_private;
3648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3649 struct intel_encoder *encoder;
79e53945 3650 int pipe = intel_crtc->pipe;
80824003 3651 int plane = intel_crtc->plane;
79e53945 3652
08a48469
DV		 3653 WARN_ON(!crtc->enabled);
3654
f7abfe8b
CW		 3655 if (intel_crtc->active)
3656 return;
3657
3658 intel_crtc->active = true;
6b383a7f
CW		 3659 intel_update_watermarks(dev);
3660
63d7bbe9 3661 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3662
3663 for_each_encoder_on_crtc(dev, crtc, encoder)
3664 if (encoder->pre_enable)
3665 encoder->pre_enable(encoder);
3666
040484af 3667 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3668 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3669
0b8765c6 3670 intel_crtc_load_lut(crtc);
bed4a673 3671 intel_update_fbc(dev);
79e53945 3672
0b8765c6
JB		 3673 /* Give the overlay scaler a chance to enable if it's on this pipe */
3674 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3675 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3676
fa5c73b1
DV		 3677 for_each_encoder_on_crtc(dev, crtc, encoder)
3678 encoder->enable(encoder);
0b8765c6 3679}
79e53945 3680
0b8765c6
JB		 3681static void i9xx_crtc_disable(struct drm_crtc *crtc)
3682{
3683 struct drm_device *dev = crtc->dev;
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3686 struct intel_encoder *encoder;
0b8765c6
JB		 3687 int pipe = intel_crtc->pipe;
3688 int plane = intel_crtc->plane;
24a1f16d 3689 u32 pctl;
b690e96c 3690
ef9c3aee 3691
f7abfe8b
CW		 3692 if (!intel_crtc->active)
3693 return;
3694
ea9d758d
DV		 3695 for_each_encoder_on_crtc(dev, crtc, encoder)
3696 encoder->disable(encoder);
3697
0b8765c6 3698 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3699 intel_crtc_wait_for_pending_flips(crtc);
3700 drm_vblank_off(dev, pipe);
0b8765c6 3701 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3702 intel_crtc_update_cursor(crtc, false);
0b8765c6 3703
973d04f9
CW		 3704 if (dev_priv->cfb_plane == plane)
3705 intel_disable_fbc(dev);
79e53945 3706
b24e7179 3707 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3708 intel_disable_pipe(dev_priv, pipe);
24a1f16d
MK		 3709
3710 /* Disable pannel fitter if it is on this pipe. */
3711 pctl = I915_READ(PFIT_CONTROL);
3712 if ((pctl & PFIT_ENABLE) &&
3713 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3714 I915_WRITE(PFIT_CONTROL, 0);
3715
63d7bbe9 3716 intel_disable_pll(dev_priv, pipe);
0b8765c6 3717
f7abfe8b 3718 intel_crtc->active = false;
6b383a7f
CW		 3719 intel_update_fbc(dev);
3720 intel_update_watermarks(dev);
0b8765c6
JB		 3721}
3722
ee7b9f93
JB		 3723static void i9xx_crtc_off(struct drm_crtc *crtc)
3724{
3725}
3726
976f8a20
DV		 3727static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3728 bool enabled)
2c07245f
ZW		 3729{
3730 struct drm_device *dev = crtc->dev;
3731 struct drm_i915_master_private *master_priv;
3732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3733 int pipe = intel_crtc->pipe;
79e53945
JB		 3734
3735 if (!dev->primary->master)
3736 return;
3737
3738 master_priv = dev->primary->master->driver_priv;
3739 if (!master_priv->sarea_priv)
3740 return;
3741
79e53945
JB		 3742 switch (pipe) {
3743 case 0:
3744 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3745 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3746 break;
3747 case 1:
3748 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3749 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3750 break;
3751 default:
9db4a9c7 3752 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3753 break;
3754 }
79e53945
JB		 3755}
3756
976f8a20
DV		 3757/**
3758 * Sets the power management mode of the pipe and plane.
3759 */
3760void intel_crtc_update_dpms(struct drm_crtc *crtc)
3761{
3762 struct drm_device *dev = crtc->dev;
3763 struct drm_i915_private *dev_priv = dev->dev_private;
3764 struct intel_encoder *intel_encoder;
3765 bool enable = false;
3766
3767 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3768 enable |= intel_encoder->connectors_active;
3769
3770 if (enable)
3771 dev_priv->display.crtc_enable(crtc);
3772 else
3773 dev_priv->display.crtc_disable(crtc);
3774
3775 intel_crtc_update_sarea(crtc, enable);
3776}
3777
3778static void intel_crtc_noop(struct drm_crtc *crtc)
3779{
3780}
3781
cdd59983
CW		 3782static void intel_crtc_disable(struct drm_crtc *crtc)
3783{
cdd59983 3784 struct drm_device *dev = crtc->dev;
976f8a20 3785 struct drm_connector *connector;
ee7b9f93 3786 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3788
976f8a20
DV		 3789 /* crtc should still be enabled when we disable it. */
3790 WARN_ON(!crtc->enabled);
3791
7b9f35a6 3792 intel_crtc->eld_vld = false;
976f8a20
DV		 3793 dev_priv->display.crtc_disable(crtc);
3794 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3795 dev_priv->display.off(crtc);
3796
931872fc
CW		 3797 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3798 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3799
3800 if (crtc->fb) {
3801 mutex_lock(&dev->struct_mutex);
1690e1eb 3802 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3803 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3804 crtc->fb = NULL;
3805 }
3806
3807 /* Update computed state. */
3808 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3809 if (!connector->encoder || !connector->encoder->crtc)
3810 continue;
3811
3812 if (connector->encoder->crtc != crtc)
3813 continue;
3814
3815 connector->dpms = DRM_MODE_DPMS_OFF;
3816 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3817 }
3818}
3819
a261b246 3820void intel_modeset_disable(struct drm_device *dev)
79e53945 3821{
a261b246
DV		 3822 struct drm_crtc *crtc;
3823
3824 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3825 if (crtc->enabled)
3826 intel_crtc_disable(crtc);
3827 }
79e53945
JB		 3828}
3829
1f703855 3830void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3831{
7e7d76c3
JB		 3832}
3833
ea5b213a 3834void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3835{
4ef69c7a 3836 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3837
ea5b213a
CW		 3838 drm_encoder_cleanup(encoder);
3839 kfree(intel_encoder);
7e7d76c3
JB		 3840}
3841
5ab432ef
DV		 3842/* Simple dpms helper for encodres with just one connector, no cloning and only
3843 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3844 * state of the entire output pipe. */
3845void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3846{
5ab432ef
DV		 3847 if (mode == DRM_MODE_DPMS_ON) {
3848 encoder->connectors_active = true;
3849
b2cabb0e 3850 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3851 } else {
3852 encoder->connectors_active = false;
3853
b2cabb0e 3854 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3855 }
79e53945
JB		 3856}
3857
0a91ca29
DV		 3858/* Cross check the actual hw state with our own modeset state tracking (and it's
3859 * internal consistency). */
b980514c 3860static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3861{
0a91ca29
DV		 3862 if (connector->get_hw_state(connector)) {
3863 struct intel_encoder *encoder = connector->encoder;
3864 struct drm_crtc *crtc;
3865 bool encoder_enabled;
3866 enum pipe pipe;
3867
3868 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3869 connector->base.base.id,
3870 drm_get_connector_name(&connector->base));
3871
3872 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3873 "wrong connector dpms state\n");
3874 WARN(connector->base.encoder != &encoder->base,
3875 "active connector not linked to encoder\n");
3876 WARN(!encoder->connectors_active,
3877 "encoder->connectors_active not set\n");
3878
3879 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3880 WARN(!encoder_enabled, "encoder not enabled\n");
3881 if (WARN_ON(!encoder->base.crtc))
3882 return;
3883
3884 crtc = encoder->base.crtc;
3885
3886 WARN(!crtc->enabled, "crtc not enabled\n");
3887 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3888 WARN(pipe != to_intel_crtc(crtc)->pipe,
3889 "encoder active on the wrong pipe\n");
3890 }
79e53945
JB		 3891}
3892
5ab432ef
DV		 3893/* Even simpler default implementation, if there's really no special case to
3894 * consider. */
3895void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3896{
5ab432ef 3897 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3898
5ab432ef
DV		 3899 /* All the simple cases only support two dpms states. */
3900 if (mode != DRM_MODE_DPMS_ON)
3901 mode = DRM_MODE_DPMS_OFF;
d4270e57 3902
5ab432ef
DV		 3903 if (mode == connector->dpms)
3904 return;
3905
3906 connector->dpms = mode;
3907
3908 /* Only need to change hw state when actually enabled */
3909 if (encoder->base.crtc)
3910 intel_encoder_dpms(encoder, mode);
3911 else
8af6cf88 3912 WARN_ON(encoder->connectors_active != false);
0a91ca29 3913
b980514c 3914 intel_modeset_check_state(connector->dev);
79e53945
JB		 3915}
3916
f0947c37
DV		 3917/* Simple connector->get_hw_state implementation for encoders that support only
3918 * one connector and no cloning and hence the encoder state determines the state
3919 * of the connector. */
3920bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3921{
24929352 3922 enum pipe pipe = 0;
f0947c37 3923 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3924
f0947c37 3925 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3926}
3927
79e53945 3928static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3929 const struct drm_display_mode *mode,
79e53945
JB		 3930 struct drm_display_mode *adjusted_mode)
3931{
2c07245f 3932 struct drm_device *dev = crtc->dev;
89749350 3933
bad720ff 3934 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3935 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3936 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3937 return false;
2c07245f 3938 }
89749350 3939
f9bef081
DV		 3940 /* All interlaced capable intel hw wants timings in frames. Note though
3941 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3942 * timings, so we need to be careful not to clobber these.*/
3943 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3944 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3945
44f46b42
CW		 3946 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3947 * with a hsync front porch of 0.
3948 */
3949 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3950 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3951 return false;
3952
79e53945
JB		 3953 return true;
3954}
3955
25eb05fc
JB		 3956static int valleyview_get_display_clock_speed(struct drm_device *dev)
3957{
3958 return 400000; /* FIXME */
3959}
3960
e70236a8
JB		 3961static int i945_get_display_clock_speed(struct drm_device *dev)
3962{
3963 return 400000;
3964}
79e53945 3965
e70236a8 3966static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3967{
e70236a8
JB		 3968 return 333000;
3969}
79e53945 3970
e70236a8
JB		 3971static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3972{
3973 return 200000;
3974}
79e53945 3975
e70236a8
JB		 3976static int i915gm_get_display_clock_speed(struct drm_device *dev)
3977{
3978 u16 gcfgc = 0;
79e53945 3979
e70236a8
JB		 3980 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3981
3982 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3983 return 133000;
3984 else {
3985 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3986 case GC_DISPLAY_CLOCK_333_MHZ:
3987 return 333000;
3988 default:
3989 case GC_DISPLAY_CLOCK_190_200_MHZ:
3990 return 190000;
79e53945 3991 }
e70236a8
JB		 3992 }
3993}
3994
3995static int i865_get_display_clock_speed(struct drm_device *dev)
3996{
3997 return 266000;
3998}
3999
4000static int i855_get_display_clock_speed(struct drm_device *dev)
4001{
4002 u16 hpllcc = 0;
4003 /* Assume that the hardware is in the high speed state. This
4004 * should be the default.
4005 */
4006 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4007 case GC_CLOCK_133_200:
4008 case GC_CLOCK_100_200:
4009 return 200000;
4010 case GC_CLOCK_166_250:
4011 return 250000;
4012 case GC_CLOCK_100_133:
79e53945 4013 return 133000;
e70236a8 4014 }
79e53945 4015
e70236a8
JB		 4016 /* Shouldn't happen */
4017 return 0;
4018}
79e53945 4019
e70236a8
JB		 4020static int i830_get_display_clock_speed(struct drm_device *dev)
4021{
4022 return 133000;
79e53945
JB		 4023}
4024
2c07245f 4025static void
e69d0bc1 4026intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4027{
4028 while (*num > 0xffffff || *den > 0xffffff) {
4029 *num >>= 1;
4030 *den >>= 1;
4031 }
4032}
4033
e69d0bc1
DV		 4034void
4035intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4036 int pixel_clock, int link_clock,
4037 struct intel_link_m_n *m_n)
2c07245f 4038{
e69d0bc1 4039 m_n->tu = 64;
22ed1113
CW		 4040 m_n->gmch_m = bits_per_pixel * pixel_clock;
4041 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4042 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4043 m_n->link_m = pixel_clock;
4044 m_n->link_n = link_clock;
e69d0bc1 4045 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4046}
4047
a7615030
CW		 4048static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4049{
72bbe58c
KP		 4050 if (i915_panel_use_ssc >= 0)
4051 return i915_panel_use_ssc != 0;
4052 return dev_priv->lvds_use_ssc
435793df 4053 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4054}
4055
5a354204
JB		 4056/**
4057 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4058 * @crtc: CRTC structure
3b5c78a3 4059 * @mode: requested mode
5a354204
JB		 4060 *
4061 * A pipe may be connected to one or more outputs. Based on the depth of the
4062 * attached framebuffer, choose a good color depth to use on the pipe.
4063 *
4064 * If possible, match the pipe depth to the fb depth. In some cases, this
4065 * isn't ideal, because the connected output supports a lesser or restricted
4066 * set of depths. Resolve that here:
4067 * LVDS typically supports only 6bpc, so clamp down in that case
4068 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4069 * Displays may support a restricted set as well, check EDID and clamp as
4070 * appropriate.
3b5c78a3 4071 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4072 *
4073 * RETURNS:
4074 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4075 * true if they don't match).
4076 */
4077static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4078 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4079 unsigned int *pipe_bpp,
4080 struct drm_display_mode *mode)
5a354204
JB		 4081{
4082 struct drm_device *dev = crtc->dev;
4083 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4084 struct drm_connector *connector;
6c2b7c12 4085 struct intel_encoder *intel_encoder;
5a354204
JB		 4086 unsigned int display_bpc = UINT_MAX, bpc;
4087
4088 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4089 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4090
4091 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4092 unsigned int lvds_bpc;
4093
4094 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4095 LVDS_A3_POWER_UP)
4096 lvds_bpc = 8;
4097 else
4098 lvds_bpc = 6;
4099
4100 if (lvds_bpc < display_bpc) {
82820490 4101 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4102 display_bpc = lvds_bpc;
4103 }
4104 continue;
4105 }
4106
5a354204
JB		 4107 /* Not one of the known troublemakers, check the EDID */
4108 list_for_each_entry(connector, &dev->mode_config.connector_list,
4109 head) {
6c2b7c12 4110 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4111 continue;
4112
62ac41a6
JB		 4113 /* Don't use an invalid EDID bpc value */
4114 if (connector->display_info.bpc &&
4115 connector->display_info.bpc < display_bpc) {
82820490 4116 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4117 display_bpc = connector->display_info.bpc;
4118 }
4119 }
4120
2f4f649a
JN		 4121 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4122 /* Use VBT settings if we have an eDP panel */
4123 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4124
9a30a61f 4125 if (edp_bpc && edp_bpc < display_bpc) {
2f4f649a
JN		 4126 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4127 display_bpc = edp_bpc;
4128 }
4129 continue;
4130 }
4131
5a354204
JB		 4132 /*
4133 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4134 * through, clamp it down. (Note: >12bpc will be caught below.)
4135 */
4136 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4137 if (display_bpc > 8 && display_bpc < 12) {
82820490 4138 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4139 display_bpc = 12;
4140 } else {
82820490 4141 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4142 display_bpc = 8;
4143 }
4144 }
4145 }
4146
3b5c78a3
AJ		 4147 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4148 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4149 display_bpc = 6;
4150 }
4151
5a354204
JB		 4152 /*
4153 * We could just drive the pipe at the highest bpc all the time and
4154 * enable dithering as needed, but that costs bandwidth. So choose
4155 * the minimum value that expresses the full color range of the fb but
4156 * also stays within the max display bpc discovered above.
4157 */
4158
94352cf9 4159 switch (fb->depth) {
5a354204
JB		 4160 case 8:
4161 bpc = 8; /* since we go through a colormap */
4162 break;
4163 case 15:
4164 case 16:
4165 bpc = 6; /* min is 18bpp */
4166 break;
4167 case 24:
578393cd 4168 bpc = 8;
5a354204
JB		 4169 break;
4170 case 30:
578393cd 4171 bpc = 10;
5a354204
JB		 4172 break;
4173 case 48:
578393cd 4174 bpc = 12;
5a354204
JB		 4175 break;
4176 default:
4177 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4178 bpc = min((unsigned int)8, display_bpc);
4179 break;
4180 }
4181
578393cd
KP		 4182 display_bpc = min(display_bpc, bpc);
4183
82820490
AJ		 4184 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4185 bpc, display_bpc);
5a354204 4186
578393cd 4187 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4188
4189 return display_bpc != bpc;
4190}
4191
a0c4da24
JB		 4192static int vlv_get_refclk(struct drm_crtc *crtc)
4193{
4194 struct drm_device *dev = crtc->dev;
4195 struct drm_i915_private *dev_priv = dev->dev_private;
4196 int refclk = 27000; /* for DP & HDMI */
4197
4198 return 100000; /* only one validated so far */
4199
4200 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4201 refclk = 96000;
4202 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4203 if (intel_panel_use_ssc(dev_priv))
4204 refclk = 100000;
4205 else
4206 refclk = 96000;
4207 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4208 refclk = 100000;
4209 }
4210
4211 return refclk;
4212}
4213
c65d77d8
JB		 4214static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4215{
4216 struct drm_device *dev = crtc->dev;
4217 struct drm_i915_private *dev_priv = dev->dev_private;
4218 int refclk;
4219
a0c4da24
JB		 4220 if (IS_VALLEYVIEW(dev)) {
4221 refclk = vlv_get_refclk(crtc);
4222 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4223 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4224 refclk = dev_priv->lvds_ssc_freq * 1000;
4225 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4226 refclk / 1000);
4227 } else if (!IS_GEN2(dev)) {
4228 refclk = 96000;
4229 } else {
4230 refclk = 48000;
4231 }
4232
4233 return refclk;
4234}
4235
4236static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4237 intel_clock_t *clock)
4238{
4239 /* SDVO TV has fixed PLL values depend on its clock range,
4240 this mirrors vbios setting. */
4241 if (adjusted_mode->clock >= 100000
4242 && adjusted_mode->clock < 140500) {
4243 clock->p1 = 2;
4244 clock->p2 = 10;
4245 clock->n = 3;
4246 clock->m1 = 16;
4247 clock->m2 = 8;
4248 } else if (adjusted_mode->clock >= 140500
4249 && adjusted_mode->clock <= 200000) {
4250 clock->p1 = 1;
4251 clock->p2 = 10;
4252 clock->n = 6;
4253 clock->m1 = 12;
4254 clock->m2 = 8;
4255 }
4256}
4257
a7516a05
JB		 4258static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4259 intel_clock_t *clock,
4260 intel_clock_t *reduced_clock)
4261{
4262 struct drm_device *dev = crtc->dev;
4263 struct drm_i915_private *dev_priv = dev->dev_private;
4264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4265 int pipe = intel_crtc->pipe;
4266 u32 fp, fp2 = 0;
4267
4268 if (IS_PINEVIEW(dev)) {
4269 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4270 if (reduced_clock)
4271 fp2 = (1 << reduced_clock->n) << 16 |
4272 reduced_clock->m1 << 8 | reduced_clock->m2;
4273 } else {
4274 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4275 if (reduced_clock)
4276 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4277 reduced_clock->m2;
4278 }
4279
4280 I915_WRITE(FP0(pipe), fp);
4281
4282 intel_crtc->lowfreq_avail = false;
4283 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4284 reduced_clock && i915_powersave) {
4285 I915_WRITE(FP1(pipe), fp2);
4286 intel_crtc->lowfreq_avail = true;
4287 } else {
4288 I915_WRITE(FP1(pipe), fp);
4289 }
4290}
4291
a0c4da24
JB		 4292static void vlv_update_pll(struct drm_crtc *crtc,
4293 struct drm_display_mode *mode,
4294 struct drm_display_mode *adjusted_mode,
4295 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4296 int num_connectors)
a0c4da24
JB		 4297{
4298 struct drm_device *dev = crtc->dev;
4299 struct drm_i915_private *dev_priv = dev->dev_private;
4300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4301 int pipe = intel_crtc->pipe;
4302 u32 dpll, mdiv, pdiv;
4303 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4304 bool is_sdvo;
4305 u32 temp;
a0c4da24 4306
09153000
DV		 4307 mutex_lock(&dev_priv->dpio_lock);
4308
2a8f64ca
VP		 4309 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4310 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4311
2a8f64ca
VP		 4312 dpll = DPLL_VGA_MODE_DIS;
4313 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4314 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4315 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4316
4317 I915_WRITE(DPLL(pipe), dpll);
4318 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4319
4320 bestn = clock->n;
4321 bestm1 = clock->m1;
4322 bestm2 = clock->m2;
4323 bestp1 = clock->p1;
4324 bestp2 = clock->p2;
4325
2a8f64ca
VP		 4326 /*
4327 * In Valleyview PLL and program lane counter registers are exposed
4328 * through DPIO interface
4329 */
a0c4da24
JB		 4330 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4331 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4332 mdiv |= ((bestn << DPIO_N_SHIFT));
4333 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4334 mdiv |= (1 << DPIO_K_SHIFT);
4335 mdiv |= DPIO_ENABLE_CALIBRATION;
4336 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4337
4338 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4339
2a8f64ca 4340 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4341 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4342 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4343 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4344 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4345
2a8f64ca 4346 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4347
4348 dpll |= DPLL_VCO_ENABLE;
4349 I915_WRITE(DPLL(pipe), dpll);
4350 POSTING_READ(DPLL(pipe));
4351 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4352 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4353
2a8f64ca
VP		 4354 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4355
4356 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4357 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4358
4359 I915_WRITE(DPLL(pipe), dpll);
4360
4361 /* Wait for the clocks to stabilize. */
4362 POSTING_READ(DPLL(pipe));
4363 udelay(150);
a0c4da24 4364
2a8f64ca
VP		 4365 temp = 0;
4366 if (is_sdvo) {
4367 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4368 if (temp > 1)
4369 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4370 else
4371 temp = 0;
a0c4da24 4372 }
2a8f64ca
VP		 4373 I915_WRITE(DPLL_MD(pipe), temp);
4374 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4375
2a8f64ca
VP		 4376 /* Now program lane control registers */
4377 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4378 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4379 {
4380 temp = 0x1000C4;
4381 if(pipe == 1)
4382 temp |= (1 << 21);
4383 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4384 }
4385 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4386 {
4387 temp = 0x1000C4;
4388 if(pipe == 1)
4389 temp |= (1 << 21);
4390 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4391 }
09153000
DV		 4392
4393 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4394}
4395
eb1cbe48
DV		 4396static void i9xx_update_pll(struct drm_crtc *crtc,
4397 struct drm_display_mode *mode,
4398 struct drm_display_mode *adjusted_mode,
4399 intel_clock_t *clock, intel_clock_t *reduced_clock,
4400 int num_connectors)
4401{
4402 struct drm_device *dev = crtc->dev;
4403 struct drm_i915_private *dev_priv = dev->dev_private;
4404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4405 struct intel_encoder *encoder;
eb1cbe48
DV		 4406 int pipe = intel_crtc->pipe;
4407 u32 dpll;
4408 bool is_sdvo;
4409
2a8f64ca
VP		 4410 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4411
eb1cbe48
DV		 4412 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4413 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4414
4415 dpll = DPLL_VGA_MODE_DIS;
4416
4417 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4418 dpll |= DPLLB_MODE_LVDS;
4419 else
4420 dpll |= DPLLB_MODE_DAC_SERIAL;
4421 if (is_sdvo) {
4422 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4423 if (pixel_multiplier > 1) {
4424 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4425 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4426 }
4427 dpll |= DPLL_DVO_HIGH_SPEED;
4428 }
4429 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4430 dpll |= DPLL_DVO_HIGH_SPEED;
4431
4432 /* compute bitmask from p1 value */
4433 if (IS_PINEVIEW(dev))
4434 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4435 else {
4436 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4437 if (IS_G4X(dev) && reduced_clock)
4438 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4439 }
4440 switch (clock->p2) {
4441 case 5:
4442 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4443 break;
4444 case 7:
4445 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4446 break;
4447 case 10:
4448 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4449 break;
4450 case 14:
4451 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4452 break;
4453 }
4454 if (INTEL_INFO(dev)->gen >= 4)
4455 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4456
4457 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4458 dpll |= PLL_REF_INPUT_TVCLKINBC;
4459 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4460 /* XXX: just matching BIOS for now */
4461 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4462 dpll |= 3;
4463 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4464 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4465 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4466 else
4467 dpll |= PLL_REF_INPUT_DREFCLK;
4468
4469 dpll |= DPLL_VCO_ENABLE;
4470 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4471 POSTING_READ(DPLL(pipe));
4472 udelay(150);
4473
dafd226c
DV		 4474 for_each_encoder_on_crtc(dev, crtc, encoder)
4475 if (encoder->pre_pll_enable)
4476 encoder->pre_pll_enable(encoder);
eb1cbe48
DV		 4477
4478 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4479 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4480
4481 I915_WRITE(DPLL(pipe), dpll);
4482
4483 /* Wait for the clocks to stabilize. */
4484 POSTING_READ(DPLL(pipe));
4485 udelay(150);
4486
4487 if (INTEL_INFO(dev)->gen >= 4) {
4488 u32 temp = 0;
4489 if (is_sdvo) {
4490 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4491 if (temp > 1)
4492 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4493 else
4494 temp = 0;
4495 }
4496 I915_WRITE(DPLL_MD(pipe), temp);
4497 } else {
4498 /* The pixel multiplier can only be updated once the
4499 * DPLL is enabled and the clocks are stable.
4500 *
4501 * So write it again.
4502 */
4503 I915_WRITE(DPLL(pipe), dpll);
4504 }
4505}
4506
4507static void i8xx_update_pll(struct drm_crtc *crtc,
4508 struct drm_display_mode *adjusted_mode,
2a8f64ca 4509 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4510 int num_connectors)
4511{
4512 struct drm_device *dev = crtc->dev;
4513 struct drm_i915_private *dev_priv = dev->dev_private;
4514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4515 struct intel_encoder *encoder;
eb1cbe48
DV		 4516 int pipe = intel_crtc->pipe;
4517 u32 dpll;
4518
2a8f64ca
VP		 4519 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4520
eb1cbe48
DV		 4521 dpll = DPLL_VGA_MODE_DIS;
4522
4523 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4524 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4525 } else {
4526 if (clock->p1 == 2)
4527 dpll |= PLL_P1_DIVIDE_BY_TWO;
4528 else
4529 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4530 if (clock->p2 == 4)
4531 dpll |= PLL_P2_DIVIDE_BY_4;
4532 }
4533
83f377ab 4534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4535 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4536 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4537 else
4538 dpll |= PLL_REF_INPUT_DREFCLK;
4539
4540 dpll |= DPLL_VCO_ENABLE;
4541 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4542 POSTING_READ(DPLL(pipe));
4543 udelay(150);
4544
dafd226c
DV		 4545 for_each_encoder_on_crtc(dev, crtc, encoder)
4546 if (encoder->pre_pll_enable)
4547 encoder->pre_pll_enable(encoder);
eb1cbe48 4548
5b5896e4
DV		 4549 I915_WRITE(DPLL(pipe), dpll);
4550
4551 /* Wait for the clocks to stabilize. */
4552 POSTING_READ(DPLL(pipe));
4553 udelay(150);
4554
eb1cbe48
DV		 4555 /* The pixel multiplier can only be updated once the
4556 * DPLL is enabled and the clocks are stable.
4557 *
4558 * So write it again.
4559 */
4560 I915_WRITE(DPLL(pipe), dpll);
4561}
4562
b0e77b9c
PZ		 4563static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4564 struct drm_display_mode *mode,
4565 struct drm_display_mode *adjusted_mode)
4566{
4567 struct drm_device *dev = intel_crtc->base.dev;
4568 struct drm_i915_private *dev_priv = dev->dev_private;
4569 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4570 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4571 uint32_t vsyncshift;
4572
4573 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4574 /* the chip adds 2 halflines automatically */
4575 adjusted_mode->crtc_vtotal -= 1;
4576 adjusted_mode->crtc_vblank_end -= 1;
4577 vsyncshift = adjusted_mode->crtc_hsync_start
4578 - adjusted_mode->crtc_htotal / 2;
4579 } else {
4580 vsyncshift = 0;
4581 }
4582
4583 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4584 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4585
fe2b8f9d 4586 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4587 (adjusted_mode->crtc_hdisplay - 1) |
4588 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4589 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4590 (adjusted_mode->crtc_hblank_start - 1) |
4591 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4592 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4593 (adjusted_mode->crtc_hsync_start - 1) |
4594 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4595
fe2b8f9d 4596 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4597 (adjusted_mode->crtc_vdisplay - 1) |
4598 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4599 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4600 (adjusted_mode->crtc_vblank_start - 1) |
4601 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4602 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4603 (adjusted_mode->crtc_vsync_start - 1) |
4604 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4605
b5e508d4
PZ		 4606 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4607 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4608 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4609 * bits. */
4610 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4611 (pipe == PIPE_B || pipe == PIPE_C))
4612 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4613
b0e77b9c
PZ		 4614 /* pipesrc controls the size that is scaled from, which should
4615 * always be the user's requested size.
4616 */
4617 I915_WRITE(PIPESRC(pipe),
4618 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4619}
4620
f564048e
EA		 4621static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4622 struct drm_display_mode *mode,
4623 struct drm_display_mode *adjusted_mode,
4624 int x, int y,
94352cf9 4625 struct drm_framebuffer *fb)
79e53945
JB		 4626{
4627 struct drm_device *dev = crtc->dev;
4628 struct drm_i915_private *dev_priv = dev->dev_private;
4629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4630 int pipe = intel_crtc->pipe;
80824003 4631 int plane = intel_crtc->plane;
c751ce4f 4632 int refclk, num_connectors = 0;
652c393a 4633 intel_clock_t clock, reduced_clock;
b0e77b9c 4634 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4635 bool ok, has_reduced_clock = false, is_sdvo = false;
4636 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4637 struct intel_encoder *encoder;
d4906093 4638 const intel_limit_t *limit;
5c3b82e2 4639 int ret;
79e53945 4640
6c2b7c12 4641 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4642 switch (encoder->type) {
79e53945
JB		 4643 case INTEL_OUTPUT_LVDS:
4644 is_lvds = true;
4645 break;
4646 case INTEL_OUTPUT_SDVO:
7d57382e 4647 case INTEL_OUTPUT_HDMI:
79e53945 4648 is_sdvo = true;
5eddb70b 4649 if (encoder->needs_tv_clock)
e2f0ba97 4650 is_tv = true;
79e53945 4651 break;
79e53945
JB		 4652 case INTEL_OUTPUT_TVOUT:
4653 is_tv = true;
4654 break;
a4fc5ed6
KP		 4655 case INTEL_OUTPUT_DISPLAYPORT:
4656 is_dp = true;
4657 break;
79e53945 4658 }
43565a06 4659
c751ce4f 4660 num_connectors++;
79e53945
JB		 4661 }
4662
c65d77d8 4663 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4664
d4906093
ML		 4665 /*
4666 * Returns a set of divisors for the desired target clock with the given
4667 * refclk, or FALSE. The returned values represent the clock equation:
4668 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4669 */
1b894b59 4670 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4671 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4672 &clock);
79e53945
JB		 4673 if (!ok) {
4674 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4675 return -EINVAL;
79e53945
JB		 4676 }
4677
cda4b7d3 4678 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4679 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4680
ddc9003c 4681 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4682 /*
4683 * Ensure we match the reduced clock's P to the target clock.
4684 * If the clocks don't match, we can't switch the display clock
4685 * by using the FP0/FP1. In such case we will disable the LVDS
4686 * downclock feature.
4687 */
ddc9003c 4688 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4689 dev_priv->lvds_downclock,
4690 refclk,
cec2f356 4691 &clock,
5eddb70b 4692 &reduced_clock);
7026d4ac
ZW		 4693 }
4694
c65d77d8
JB		 4695 if (is_sdvo && is_tv)
4696 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4697
eb1cbe48 4698 if (IS_GEN2(dev))
2a8f64ca
VP		 4699 i8xx_update_pll(crtc, adjusted_mode, &clock,
4700 has_reduced_clock ? &reduced_clock : NULL,
4701 num_connectors);
a0c4da24 4702 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4703 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4704 has_reduced_clock ? &reduced_clock : NULL,
4705 num_connectors);
79e53945 4706 else
eb1cbe48
DV		 4707 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4708 has_reduced_clock ? &reduced_clock : NULL,
4709 num_connectors);
79e53945
JB		 4710
4711 /* setup pipeconf */
5eddb70b 4712 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4713
4714 /* Set up the display plane register */
4715 dspcntr = DISPPLANE_GAMMA_ENABLE;
4716
929c77fb
EA		 4717 if (pipe == 0)
4718 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4719 else
4720 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4721
a6c45cf0 4722 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4723 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4724 * core speed.
4725 *
4726 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4727 * pipe == 0 check?
4728 */
e70236a8
JB		 4729 if (mode->clock >
4730 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4731 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4732 else
5eddb70b 4733 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4734 }
4735
3b5c78a3 4736 /* default to 8bpc */
dfd07d72 4737 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
3b5c78a3 4738 if (is_dp) {
0c96c65b 4739 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4740 pipeconf |= PIPECONF_6BPC |
3b5c78a3
AJ		 4741 PIPECONF_DITHER_EN |
4742 PIPECONF_DITHER_TYPE_SP;
4743 }
4744 }
4745
19c03924
GB		 4746 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4747 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4748 pipeconf |= PIPECONF_6BPC |
19c03924
GB		 4749 PIPECONF_ENABLE |
4750 I965_PIPECONF_ACTIVE;
4751 }
4752 }
4753
28c97730 4754 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4755 drm_mode_debug_printmodeline(mode);
4756
a7516a05
JB		 4757 if (HAS_PIPE_CXSR(dev)) {
4758 if (intel_crtc->lowfreq_avail) {
28c97730 4759 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4760 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4761 } else {
28c97730 4762 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4763 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4764 }
4765 }
4766
617cf884 4767 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4768 if (!IS_GEN2(dev) &&
b0e77b9c 4769 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4770 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4771 else
617cf884 4772 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4773
b0e77b9c 4774 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4775
4776 /* pipesrc and dspsize control the size that is scaled from,
4777 * which should always be the user's requested size.
79e53945 4778 */
929c77fb
EA		 4779 I915_WRITE(DSPSIZE(plane),
4780 ((mode->vdisplay - 1) << 16) |
4781 (mode->hdisplay - 1));
4782 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4783
f564048e
EA		 4784 I915_WRITE(PIPECONF(pipe), pipeconf);
4785 POSTING_READ(PIPECONF(pipe));
929c77fb 4786 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4787
4788 intel_wait_for_vblank(dev, pipe);
4789
f564048e
EA		 4790 I915_WRITE(DSPCNTR(plane), dspcntr);
4791 POSTING_READ(DSPCNTR(plane));
4792
94352cf9 4793 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4794
4795 intel_update_watermarks(dev);
4796
f564048e
EA		 4797 return ret;
4798}
4799
dde86e2d 4800static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4801{
4802 struct drm_i915_private *dev_priv = dev->dev_private;
4803 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4804 struct intel_encoder *encoder;
13d83a67
JB		 4805 u32 temp;
4806 bool has_lvds = false;
199e5d79
KP		 4807 bool has_cpu_edp = false;
4808 bool has_pch_edp = false;
4809 bool has_panel = false;
99eb6a01
KP		 4810 bool has_ck505 = false;
4811 bool can_ssc = false;
13d83a67
JB		 4812
4813 /* We need to take the global config into account */
199e5d79
KP		 4814 list_for_each_entry(encoder, &mode_config->encoder_list,
4815 base.head) {
4816 switch (encoder->type) {
4817 case INTEL_OUTPUT_LVDS:
4818 has_panel = true;
4819 has_lvds = true;
4820 break;
4821 case INTEL_OUTPUT_EDP:
4822 has_panel = true;
4823 if (intel_encoder_is_pch_edp(&encoder->base))
4824 has_pch_edp = true;
4825 else
4826 has_cpu_edp = true;
4827 break;
13d83a67
JB		 4828 }
4829 }
4830
99eb6a01
KP		 4831 if (HAS_PCH_IBX(dev)) {
4832 has_ck505 = dev_priv->display_clock_mode;
4833 can_ssc = has_ck505;
4834 } else {
4835 has_ck505 = false;
4836 can_ssc = true;
4837 }
4838
4839 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4840 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4841 has_ck505);
13d83a67
JB		 4842
4843 /* Ironlake: try to setup display ref clock before DPLL
4844 * enabling. This is only under driver's control after
4845 * PCH B stepping, previous chipset stepping should be
4846 * ignoring this setting.
4847 */
4848 temp = I915_READ(PCH_DREF_CONTROL);
4849 /* Always enable nonspread source */
4850 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4851
99eb6a01
KP		 4852 if (has_ck505)
4853 temp |= DREF_NONSPREAD_CK505_ENABLE;
4854 else
4855 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4856
199e5d79
KP		 4857 if (has_panel) {
4858 temp &= ~DREF_SSC_SOURCE_MASK;
4859 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4860
199e5d79 4861 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4862 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4863 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4864 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4865 } else
4866 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4867
4868 /* Get SSC going before enabling the outputs */
4869 I915_WRITE(PCH_DREF_CONTROL, temp);
4870 POSTING_READ(PCH_DREF_CONTROL);
4871 udelay(200);
4872
13d83a67
JB		 4873 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4874
4875 /* Enable CPU source on CPU attached eDP */
199e5d79 4876 if (has_cpu_edp) {
99eb6a01 4877 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4878 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4879 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4880 }
13d83a67
JB		 4881 else
4882 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4883 } else
4884 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4885
4886 I915_WRITE(PCH_DREF_CONTROL, temp);
4887 POSTING_READ(PCH_DREF_CONTROL);
4888 udelay(200);
4889 } else {
4890 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4891
4892 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4893
4894 /* Turn off CPU output */
4895 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4896
4897 I915_WRITE(PCH_DREF_CONTROL, temp);
4898 POSTING_READ(PCH_DREF_CONTROL);
4899 udelay(200);
4900
4901 /* Turn off the SSC source */
4902 temp &= ~DREF_SSC_SOURCE_MASK;
4903 temp |= DREF_SSC_SOURCE_DISABLE;
4904
4905 /* Turn off SSC1 */
4906 temp &= ~ DREF_SSC1_ENABLE;
4907
13d83a67
JB		 4908 I915_WRITE(PCH_DREF_CONTROL, temp);
4909 POSTING_READ(PCH_DREF_CONTROL);
4910 udelay(200);
4911 }
4912}
4913
dde86e2d
PZ		 4914/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4915static void lpt_init_pch_refclk(struct drm_device *dev)
4916{
4917 struct drm_i915_private *dev_priv = dev->dev_private;
4918 struct drm_mode_config *mode_config = &dev->mode_config;
4919 struct intel_encoder *encoder;
4920 bool has_vga = false;
4921 bool is_sdv = false;
4922 u32 tmp;
4923
4924 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4925 switch (encoder->type) {
4926 case INTEL_OUTPUT_ANALOG:
4927 has_vga = true;
4928 break;
4929 }
4930 }
4931
4932 if (!has_vga)
4933 return;
4934
c00db246
DV		 4935 mutex_lock(&dev_priv->dpio_lock);
4936
dde86e2d
PZ		 4937 /* XXX: Rip out SDV support once Haswell ships for real. */
4938 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4939 is_sdv = true;
4940
4941 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4942 tmp &= ~SBI_SSCCTL_DISABLE;
4943 tmp |= SBI_SSCCTL_PATHALT;
4944 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4945
4946 udelay(24);
4947
4948 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4949 tmp &= ~SBI_SSCCTL_PATHALT;
4950 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4951
4952 if (!is_sdv) {
4953 tmp = I915_READ(SOUTH_CHICKEN2);
4954 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4955 I915_WRITE(SOUTH_CHICKEN2, tmp);
4956
4957 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4958 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4959 DRM_ERROR("FDI mPHY reset assert timeout\n");
4960
4961 tmp = I915_READ(SOUTH_CHICKEN2);
4962 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4963 I915_WRITE(SOUTH_CHICKEN2, tmp);
4964
4965 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4966 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4967 100))
4968 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4969 }
4970
4971 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4972 tmp &= ~(0xFF << 24);
4973 tmp |= (0x12 << 24);
4974 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4975
4976 if (!is_sdv) {
4977 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4978 tmp &= ~(0x3 << 6);
4979 tmp |= (1 << 6) | (1 << 0);
4980 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4981 }
4982
4983 if (is_sdv) {
4984 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4985 tmp |= 0x7FFF;
4986 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4987 }
4988
4989 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4990 tmp |= (1 << 11);
4991 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4992
4993 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4994 tmp |= (1 << 11);
4995 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4996
4997 if (is_sdv) {
4998 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4999 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5000 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5001
5002 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5003 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5004 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5005
5006 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5007 tmp |= (0x3F << 8);
5008 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5009
5010 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5011 tmp |= (0x3F << 8);
5012 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5013 }
5014
5015 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5016 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5017 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5018
5019 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5020 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5021 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5022
5023 if (!is_sdv) {
5024 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5025 tmp &= ~(7 << 13);
5026 tmp |= (5 << 13);
5027 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5028
5029 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5030 tmp &= ~(7 << 13);
5031 tmp |= (5 << 13);
5032 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5033 }
5034
5035 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5036 tmp &= ~0xFF;
5037 tmp |= 0x1C;
5038 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5039
5040 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5041 tmp &= ~0xFF;
5042 tmp |= 0x1C;
5043 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5044
5045 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5046 tmp &= ~(0xFF << 16);
5047 tmp |= (0x1C << 16);
5048 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5049
5050 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5051 tmp &= ~(0xFF << 16);
5052 tmp |= (0x1C << 16);
5053 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5054
5055 if (!is_sdv) {
5056 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5057 tmp |= (1 << 27);
5058 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5059
5060 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5061 tmp |= (1 << 27);
5062 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5063
5064 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5065 tmp &= ~(0xF << 28);
5066 tmp |= (4 << 28);
5067 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5068
5069 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5070 tmp &= ~(0xF << 28);
5071 tmp |= (4 << 28);
5072 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5073 }
5074
5075 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5076 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5077 tmp |= SBI_DBUFF0_ENABLE;
5078 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5079
5080 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5081}
5082
5083/*
5084 * Initialize reference clocks when the driver loads
5085 */
5086void intel_init_pch_refclk(struct drm_device *dev)
5087{
5088 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5089 ironlake_init_pch_refclk(dev);
5090 else if (HAS_PCH_LPT(dev))
5091 lpt_init_pch_refclk(dev);
5092}
5093
d9d444cb
JB		 5094static int ironlake_get_refclk(struct drm_crtc *crtc)
5095{
5096 struct drm_device *dev = crtc->dev;
5097 struct drm_i915_private *dev_priv = dev->dev_private;
5098 struct intel_encoder *encoder;
d9d444cb
JB		 5099 struct intel_encoder *edp_encoder = NULL;
5100 int num_connectors = 0;
5101 bool is_lvds = false;
5102
6c2b7c12 5103 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5104 switch (encoder->type) {
5105 case INTEL_OUTPUT_LVDS:
5106 is_lvds = true;
5107 break;
5108 case INTEL_OUTPUT_EDP:
5109 edp_encoder = encoder;
5110 break;
5111 }
5112 num_connectors++;
5113 }
5114
5115 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5116 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5117 dev_priv->lvds_ssc_freq);
5118 return dev_priv->lvds_ssc_freq * 1000;
5119 }
5120
5121 return 120000;
5122}
5123
c8203565 5124static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5125 struct drm_display_mode *adjusted_mode,
c8203565 5126 bool dither)
79e53945 5127{
c8203565 5128 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5130 int pipe = intel_crtc->pipe;
c8203565
PZ		 5131 uint32_t val;
5132
5133 val = I915_READ(PIPECONF(pipe));
5134
dfd07d72 5135 val &= ~PIPECONF_BPC_MASK;
c8203565
PZ		 5136 switch (intel_crtc->bpp) {
5137 case 18:
dfd07d72 5138 val |= PIPECONF_6BPC;
c8203565
PZ		 5139 break;
5140 case 24:
dfd07d72 5141 val |= PIPECONF_8BPC;
c8203565
PZ		 5142 break;
5143 case 30:
dfd07d72 5144 val |= PIPECONF_10BPC;
c8203565
PZ		 5145 break;
5146 case 36:
dfd07d72 5147 val |= PIPECONF_12BPC;
c8203565
PZ		 5148 break;
5149 default:
cc769b62
PZ		 5150 /* Case prevented by intel_choose_pipe_bpp_dither. */
5151 BUG();
c8203565
PZ		 5152 }
5153
5154 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5155 if (dither)
5156 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5157
5158 val &= ~PIPECONF_INTERLACE_MASK;
5159 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5160 val |= PIPECONF_INTERLACED_ILK;
5161 else
5162 val |= PIPECONF_PROGRESSIVE;
5163
3685a8f3
VS		 5164 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5165 val |= PIPECONF_COLOR_RANGE_SELECT;
5166 else
5167 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5168
c8203565
PZ		 5169 I915_WRITE(PIPECONF(pipe), val);
5170 POSTING_READ(PIPECONF(pipe));
5171}
5172
86d3efce
VS		 5173/*
5174 * Set up the pipe CSC unit.
5175 *
5176 * Currently only full range RGB to limited range RGB conversion
5177 * is supported, but eventually this should handle various
5178 * RGB<->YCbCr scenarios as well.
5179 */
5180static void intel_set_pipe_csc(struct drm_crtc *crtc,
5181 const struct drm_display_mode *adjusted_mode)
5182{
5183 struct drm_device *dev = crtc->dev;
5184 struct drm_i915_private *dev_priv = dev->dev_private;
5185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5186 int pipe = intel_crtc->pipe;
5187 uint16_t coeff = 0x7800; /* 1.0 */
5188
5189 /*
5190 * TODO: Check what kind of values actually come out of the pipe
5191 * with these coeff/postoff values and adjust to get the best
5192 * accuracy. Perhaps we even need to take the bpc value into
5193 * consideration.
5194 */
5195
5196 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5197 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5198
5199 /*
5200 * GY/GU and RY/RU should be the other way around according
5201 * to BSpec, but reality doesn't agree. Just set them up in
5202 * a way that results in the correct picture.
5203 */
5204 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5205 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5206
5207 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5208 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5209
5210 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5211 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5212
5213 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5214 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5215 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5216
5217 if (INTEL_INFO(dev)->gen > 6) {
5218 uint16_t postoff = 0;
5219
5220 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5221 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5222
5223 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5224 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5225 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5226
5227 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5228 } else {
5229 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5230
5231 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5232 mode |= CSC_BLACK_SCREEN_OFFSET;
5233
5234 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5235 }
5236}
5237
ee2b0b38
PZ		 5238static void haswell_set_pipeconf(struct drm_crtc *crtc,
5239 struct drm_display_mode *adjusted_mode,
5240 bool dither)
5241{
5242 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5244 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5245 uint32_t val;
5246
702e7a56 5247 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5248
5249 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5250 if (dither)
5251 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5252
5253 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5254 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5255 val |= PIPECONF_INTERLACED_ILK;
5256 else
5257 val |= PIPECONF_PROGRESSIVE;
5258
702e7a56
PZ		 5259 I915_WRITE(PIPECONF(cpu_transcoder), val);
5260 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5261}
5262
6591c6e4
PZ		 5263static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5264 struct drm_display_mode *adjusted_mode,
5265 intel_clock_t *clock,
5266 bool *has_reduced_clock,
5267 intel_clock_t *reduced_clock)
5268{
5269 struct drm_device *dev = crtc->dev;
5270 struct drm_i915_private *dev_priv = dev->dev_private;
5271 struct intel_encoder *intel_encoder;
5272 int refclk;
d4906093 5273 const intel_limit_t *limit;
6591c6e4 5274 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5275
6591c6e4
PZ		 5276 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5277 switch (intel_encoder->type) {
79e53945
JB		 5278 case INTEL_OUTPUT_LVDS:
5279 is_lvds = true;
5280 break;
5281 case INTEL_OUTPUT_SDVO:
7d57382e 5282 case INTEL_OUTPUT_HDMI:
79e53945 5283 is_sdvo = true;
6591c6e4 5284 if (intel_encoder->needs_tv_clock)
e2f0ba97 5285 is_tv = true;
79e53945 5286 break;
79e53945
JB		 5287 case INTEL_OUTPUT_TVOUT:
5288 is_tv = true;
5289 break;
79e53945
JB		 5290 }
5291 }
5292
d9d444cb 5293 refclk = ironlake_get_refclk(crtc);
79e53945 5294
d4906093
ML		 5295 /*
5296 * Returns a set of divisors for the desired target clock with the given
5297 * refclk, or FALSE. The returned values represent the clock equation:
5298 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5299 */
1b894b59 5300 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5301 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5302 clock);
5303 if (!ret)
5304 return false;
cda4b7d3 5305
ddc9003c 5306 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5307 /*
5308 * Ensure we match the reduced clock's P to the target clock.
5309 * If the clocks don't match, we can't switch the display clock
5310 * by using the FP0/FP1. In such case we will disable the LVDS
5311 * downclock feature.
5312 */
6591c6e4
PZ		 5313 *has_reduced_clock = limit->find_pll(limit, crtc,
5314 dev_priv->lvds_downclock,
5315 refclk,
5316 clock,
5317 reduced_clock);
652c393a 5318 }
61e9653f
DV		 5319
5320 if (is_sdvo && is_tv)
6591c6e4
PZ		 5321 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5322
5323 return true;
5324}
5325
01a415fd
DV		 5326static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5327{
5328 struct drm_i915_private *dev_priv = dev->dev_private;
5329 uint32_t temp;
5330
5331 temp = I915_READ(SOUTH_CHICKEN1);
5332 if (temp & FDI_BC_BIFURCATION_SELECT)
5333 return;
5334
5335 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5336 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5337
5338 temp |= FDI_BC_BIFURCATION_SELECT;
5339 DRM_DEBUG_KMS("enabling fdi C rx\n");
5340 I915_WRITE(SOUTH_CHICKEN1, temp);
5341 POSTING_READ(SOUTH_CHICKEN1);
5342}
5343
5344static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5345{
5346 struct drm_device *dev = intel_crtc->base.dev;
5347 struct drm_i915_private *dev_priv = dev->dev_private;
5348 struct intel_crtc *pipe_B_crtc =
5349 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5350
5351 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5352 intel_crtc->pipe, intel_crtc->fdi_lanes);
5353 if (intel_crtc->fdi_lanes > 4) {
5354 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5355 intel_crtc->pipe, intel_crtc->fdi_lanes);
5356 /* Clamp lanes to avoid programming the hw with bogus values. */
5357 intel_crtc->fdi_lanes = 4;
5358
5359 return false;
5360 }
5361
5362 if (dev_priv->num_pipe == 2)
5363 return true;
5364
5365 switch (intel_crtc->pipe) {
5366 case PIPE_A:
5367 return true;
5368 case PIPE_B:
5369 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5370 intel_crtc->fdi_lanes > 2) {
5371 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5372 intel_crtc->pipe, intel_crtc->fdi_lanes);
5373 /* Clamp lanes to avoid programming the hw with bogus values. */
5374 intel_crtc->fdi_lanes = 2;
5375
5376 return false;
5377 }
5378
5379 if (intel_crtc->fdi_lanes > 2)
5380 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5381 else
5382 cpt_enable_fdi_bc_bifurcation(dev);
5383
5384 return true;
5385 case PIPE_C:
5386 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5387 if (intel_crtc->fdi_lanes > 2) {
5388 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5389 intel_crtc->pipe, intel_crtc->fdi_lanes);
5390 /* Clamp lanes to avoid programming the hw with bogus values. */
5391 intel_crtc->fdi_lanes = 2;
5392
5393 return false;
5394 }
5395 } else {
5396 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5397 return false;
5398 }
5399
5400 cpt_enable_fdi_bc_bifurcation(dev);
5401
5402 return true;
5403 default:
5404 BUG();
5405 }
5406}
5407
d4b1931c
PZ		 5408int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5409{
5410 /*
5411 * Account for spread spectrum to avoid
5412 * oversubscribing the link. Max center spread
5413 * is 2.5%; use 5% for safety's sake.
5414 */
5415 u32 bps = target_clock * bpp * 21 / 20;
5416 return bps / (link_bw * 8) + 1;
5417}
5418
f48d8f23
PZ		 5419static void ironlake_set_m_n(struct drm_crtc *crtc,
5420 struct drm_display_mode *mode,
5421 struct drm_display_mode *adjusted_mode)
79e53945
JB		 5422{
5423 struct drm_device *dev = crtc->dev;
5424 struct drm_i915_private *dev_priv = dev->dev_private;
5425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5426 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5427 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
e69d0bc1 5428 struct intel_link_m_n m_n = {0};
f48d8f23
PZ		 5429 int target_clock, pixel_multiplier, lane, link_bw;
5430 bool is_dp = false, is_cpu_edp = false;
79e53945 5431
f48d8f23
PZ		 5432 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5433 switch (intel_encoder->type) {
a4fc5ed6
KP		 5434 case INTEL_OUTPUT_DISPLAYPORT:
5435 is_dp = true;
5436 break;
32f9d658 5437 case INTEL_OUTPUT_EDP:
e3aef172 5438 is_dp = true;
f48d8f23 5439 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5440 is_cpu_edp = true;
f48d8f23 5441 edp_encoder = intel_encoder;
32f9d658 5442 break;
79e53945 5443 }
79e53945 5444 }
61e9653f 5445
2c07245f 5446 /* FDI link */
8febb297
EA		 5447 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5448 lane = 0;
5449 /* CPU eDP doesn't require FDI link, so just set DP M/N
5450 according to current link config */
e3aef172 5451 if (is_cpu_edp) {
e3aef172 5452 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5453 } else {
8febb297
EA		 5454 /* FDI is a binary signal running at ~2.7GHz, encoding
5455 * each output octet as 10 bits. The actual frequency
5456 * is stored as a divider into a 100MHz clock, and the
5457 * mode pixel clock is stored in units of 1KHz.
5458 * Hence the bw of each lane in terms of the mode signal
5459 * is:
5460 */
5461 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5462 }
58a27471 5463
94bf2ced
DV		 5464 /* [e]DP over FDI requires target mode clock instead of link clock. */
5465 if (edp_encoder)
5466 target_clock = intel_edp_target_clock(edp_encoder, mode);
5467 else if (is_dp)
5468 target_clock = mode->clock;
5469 else
5470 target_clock = adjusted_mode->clock;
5471
d4b1931c
PZ		 5472 if (!lane)
5473 lane = ironlake_get_lanes_required(target_clock, link_bw,
5474 intel_crtc->bpp);
2c07245f 5475
8febb297
EA		 5476 intel_crtc->fdi_lanes = lane;
5477
5478 if (pixel_multiplier > 1)
5479 link_bw *= pixel_multiplier;
e69d0bc1 5480 intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
8febb297 5481
afe2fcf5
PZ		 5482 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5483 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5484 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5485 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5486}
5487
de13a2e3
PZ		 5488static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5489 struct drm_display_mode *adjusted_mode,
5490 intel_clock_t *clock, u32 fp)
79e53945 5491{
de13a2e3 5492 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5493 struct drm_device *dev = crtc->dev;
5494 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5495 struct intel_encoder *intel_encoder;
5496 uint32_t dpll;
5497 int factor, pixel_multiplier, num_connectors = 0;
5498 bool is_lvds = false, is_sdvo = false, is_tv = false;
5499 bool is_dp = false, is_cpu_edp = false;
79e53945 5500
de13a2e3
PZ		 5501 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5502 switch (intel_encoder->type) {
79e53945
JB		 5503 case INTEL_OUTPUT_LVDS:
5504 is_lvds = true;
5505 break;
5506 case INTEL_OUTPUT_SDVO:
7d57382e 5507 case INTEL_OUTPUT_HDMI:
79e53945 5508 is_sdvo = true;
de13a2e3 5509 if (intel_encoder->needs_tv_clock)
e2f0ba97 5510 is_tv = true;
79e53945 5511 break;
79e53945
JB		 5512 case INTEL_OUTPUT_TVOUT:
5513 is_tv = true;
5514 break;
a4fc5ed6
KP		 5515 case INTEL_OUTPUT_DISPLAYPORT:
5516 is_dp = true;
5517 break;
32f9d658 5518 case INTEL_OUTPUT_EDP:
e3aef172 5519 is_dp = true;
de13a2e3 5520 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5521 is_cpu_edp = true;
32f9d658 5522 break;
79e53945 5523 }
43565a06 5524
c751ce4f 5525 num_connectors++;
79e53945 5526 }
79e53945 5527
c1858123 5528 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5529 factor = 21;
5530 if (is_lvds) {
5531 if ((intel_panel_use_ssc(dev_priv) &&
5532 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5533 intel_is_dual_link_lvds(dev))
8febb297
EA		 5534 factor = 25;
5535 } else if (is_sdvo && is_tv)
5536 factor = 20;
c1858123 5537
de13a2e3 5538 if (clock->m < factor * clock->n)
8febb297 5539 fp |= FP_CB_TUNE;
2c07245f 5540
5eddb70b 5541 dpll = 0;
2c07245f 5542
a07d6787
EA		 5543 if (is_lvds)
5544 dpll |= DPLLB_MODE_LVDS;
5545 else
5546 dpll |= DPLLB_MODE_DAC_SERIAL;
5547 if (is_sdvo) {
de13a2e3 5548 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5549 if (pixel_multiplier > 1) {
5550 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5551 }
a07d6787
EA		 5552 dpll |= DPLL_DVO_HIGH_SPEED;
5553 }
e3aef172 5554 if (is_dp && !is_cpu_edp)
a07d6787 5555 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5556
a07d6787 5557 /* compute bitmask from p1 value */
de13a2e3 5558 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5559 /* also FPA1 */
de13a2e3 5560 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5561
de13a2e3 5562 switch (clock->p2) {
a07d6787
EA		 5563 case 5:
5564 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5565 break;
5566 case 7:
5567 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5568 break;
5569 case 10:
5570 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5571 break;
5572 case 14:
5573 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5574 break;
79e53945
JB		 5575 }
5576
43565a06
KH		 5577 if (is_sdvo && is_tv)
5578 dpll |= PLL_REF_INPUT_TVCLKINBC;
5579 else if (is_tv)
79e53945 5580 /* XXX: just matching BIOS for now */
43565a06 5581 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5582 dpll |= 3;
a7615030 5583 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5584 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5585 else
5586 dpll |= PLL_REF_INPUT_DREFCLK;
5587
de13a2e3
PZ		 5588 return dpll;
5589}
5590
5591static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5592 struct drm_display_mode *mode,
5593 struct drm_display_mode *adjusted_mode,
5594 int x, int y,
5595 struct drm_framebuffer *fb)
5596{
5597 struct drm_device *dev = crtc->dev;
5598 struct drm_i915_private *dev_priv = dev->dev_private;
5599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5600 int pipe = intel_crtc->pipe;
5601 int plane = intel_crtc->plane;
5602 int num_connectors = 0;
5603 intel_clock_t clock, reduced_clock;
5604 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5605 bool ok, has_reduced_clock = false;
5606 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5607 struct intel_encoder *encoder;
de13a2e3 5608 int ret;
01a415fd 5609 bool dither, fdi_config_ok;
de13a2e3
PZ		 5610
5611 for_each_encoder_on_crtc(dev, crtc, encoder) {
5612 switch (encoder->type) {
5613 case INTEL_OUTPUT_LVDS:
5614 is_lvds = true;
5615 break;
de13a2e3
PZ		 5616 case INTEL_OUTPUT_DISPLAYPORT:
5617 is_dp = true;
5618 break;
5619 case INTEL_OUTPUT_EDP:
5620 is_dp = true;
e2f12b07 5621 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5622 is_cpu_edp = true;
5623 break;
5624 }
5625
5626 num_connectors++;
a07d6787 5627 }
79e53945 5628
5dc5298b
PZ		 5629 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5630 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5631
de13a2e3
PZ		 5632 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5633 &has_reduced_clock, &reduced_clock);
5634 if (!ok) {
5635 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5636 return -EINVAL;
79e53945
JB		 5637 }
5638
de13a2e3
PZ		 5639 /* Ensure that the cursor is valid for the new mode before changing... */
5640 intel_crtc_update_cursor(crtc, true);
5641
5642 /* determine panel color depth */
c8241969
JN		 5643 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5644 adjusted_mode);
de13a2e3
PZ		 5645 if (is_lvds && dev_priv->lvds_dither)
5646 dither = true;
5647
5648 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5649 if (has_reduced_clock)
5650 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5651 reduced_clock.m2;
5652
5653 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
79e53945 5654
f7cb34d4 5655 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5656 drm_mode_debug_printmodeline(mode);
5657
5dc5298b
PZ		 5658 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5659 if (!is_cpu_edp) {
ee7b9f93 5660 struct intel_pch_pll *pll;
4b645f14 5661
ee7b9f93
JB		 5662 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5663 if (pll == NULL) {
5664 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5665 pipe);
4b645f14
JB		 5666 return -EINVAL;
5667 }
ee7b9f93
JB		 5668 } else
5669 intel_put_pch_pll(intel_crtc);
79e53945 5670
2f0c2ad1 5671 if (is_dp && !is_cpu_edp)
a4fc5ed6 5672 intel_dp_set_m_n(crtc, mode, adjusted_mode);
79e53945 5673
dafd226c
DV		 5674 for_each_encoder_on_crtc(dev, crtc, encoder)
5675 if (encoder->pre_pll_enable)
5676 encoder->pre_pll_enable(encoder);
79e53945 5677
ee7b9f93
JB		 5678 if (intel_crtc->pch_pll) {
5679 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5680
32f9d658 5681 /* Wait for the clocks to stabilize. */
ee7b9f93 5682 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5683 udelay(150);
5684
8febb297
EA		 5685 /* The pixel multiplier can only be updated once the
5686 * DPLL is enabled and the clocks are stable.
5687 *
5688 * So write it again.
5689 */
ee7b9f93 5690 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5691 }
79e53945 5692
5eddb70b 5693 intel_crtc->lowfreq_avail = false;
ee7b9f93 5694 if (intel_crtc->pch_pll) {
4b645f14 5695 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5696 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5697 intel_crtc->lowfreq_avail = true;
4b645f14 5698 } else {
ee7b9f93 5699 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5700 }
5701 }
5702
b0e77b9c 5703 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5704
01a415fd
DV		 5705 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5706 * ironlake_check_fdi_lanes. */
f48d8f23 5707 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5708
01a415fd 5709 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5710
c8203565 5711 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5712
9d0498a2 5713 intel_wait_for_vblank(dev, pipe);
79e53945 5714
a1f9e77e
PZ		 5715 /* Set up the display plane register */
5716 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5717 POSTING_READ(DSPCNTR(plane));
79e53945 5718
94352cf9 5719 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5720
5721 intel_update_watermarks(dev);
5722
1f8eeabf
ED		 5723 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5724
01a415fd 5725 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5726}
5727
d6dd9eb1
DV		 5728static void haswell_modeset_global_resources(struct drm_device *dev)
5729{
5730 struct drm_i915_private *dev_priv = dev->dev_private;
5731 bool enable = false;
5732 struct intel_crtc *crtc;
5733 struct intel_encoder *encoder;
5734
5735 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5736 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5737 enable = true;
5738 /* XXX: Should check for edp transcoder here, but thanks to init
5739 * sequence that's not yet available. Just in case desktop eDP
5740 * on PORT D is possible on haswell, too. */
5741 }
5742
5743 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5744 base.head) {
5745 if (encoder->type != INTEL_OUTPUT_EDP &&
5746 encoder->connectors_active)
5747 enable = true;
5748 }
5749
5750 /* Even the eDP panel fitter is outside the always-on well. */
5751 if (dev_priv->pch_pf_size)
5752 enable = true;
5753
5754 intel_set_power_well(dev, enable);
5755}
5756
09b4ddf9
PZ		 5757static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5758 struct drm_display_mode *mode,
5759 struct drm_display_mode *adjusted_mode,
5760 int x, int y,
5761 struct drm_framebuffer *fb)
5762{
5763 struct drm_device *dev = crtc->dev;
5764 struct drm_i915_private *dev_priv = dev->dev_private;
5765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5766 int pipe = intel_crtc->pipe;
5767 int plane = intel_crtc->plane;
5768 int num_connectors = 0;
ed7ef439 5769 bool is_dp = false, is_cpu_edp = false;
09b4ddf9 5770 struct intel_encoder *encoder;
09b4ddf9
PZ		 5771 int ret;
5772 bool dither;
5773
5774 for_each_encoder_on_crtc(dev, crtc, encoder) {
5775 switch (encoder->type) {
09b4ddf9
PZ		 5776 case INTEL_OUTPUT_DISPLAYPORT:
5777 is_dp = true;
5778 break;
5779 case INTEL_OUTPUT_EDP:
5780 is_dp = true;
5781 if (!intel_encoder_is_pch_edp(&encoder->base))
5782 is_cpu_edp = true;
5783 break;
5784 }
5785
5786 num_connectors++;
5787 }
5788
5dc5298b
PZ		 5789 /* We are not sure yet this won't happen. */
5790 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5791 INTEL_PCH_TYPE(dev));
5792
5793 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5794 num_connectors, pipe_name(pipe));
5795
702e7a56 5796 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5797 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5798
5799 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5800
6441ab5f
PZ		 5801 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5802 return -EINVAL;
5803
09b4ddf9
PZ		 5804 /* Ensure that the cursor is valid for the new mode before changing... */
5805 intel_crtc_update_cursor(crtc, true);
5806
5807 /* determine panel color depth */
c8241969
JN		 5808 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5809 adjusted_mode);
09b4ddf9 5810
09b4ddf9
PZ		 5811 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5812 drm_mode_debug_printmodeline(mode);
5813
ed7ef439 5814 if (is_dp && !is_cpu_edp)
09b4ddf9 5815 intel_dp_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9
PZ		 5816
5817 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5818
5819 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5820
1eb8dfec
PZ		 5821 if (!is_dp || is_cpu_edp)
5822 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5823
ee2b0b38 5824 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5825
86d3efce
VS		 5826 intel_set_pipe_csc(crtc, adjusted_mode);
5827
09b4ddf9 5828 /* Set up the display plane register */
86d3efce 5829 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5830 POSTING_READ(DSPCNTR(plane));
5831
5832 ret = intel_pipe_set_base(crtc, x, y, fb);
5833
5834 intel_update_watermarks(dev);
5835
5836 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5837
1f803ee5 5838 return ret;
79e53945
JB		 5839}
5840
f564048e
EA		 5841static int intel_crtc_mode_set(struct drm_crtc *crtc,
5842 struct drm_display_mode *mode,
5843 struct drm_display_mode *adjusted_mode,
5844 int x, int y,
94352cf9 5845 struct drm_framebuffer *fb)
f564048e
EA		 5846{
5847 struct drm_device *dev = crtc->dev;
5848 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5849 struct drm_encoder_helper_funcs *encoder_funcs;
5850 struct intel_encoder *encoder;
0b701d27
EA		 5851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5852 int pipe = intel_crtc->pipe;
f564048e
EA		 5853 int ret;
5854
cc464b2a
PZ		 5855 if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5856 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5857 else
5858 intel_crtc->cpu_transcoder = pipe;
5859
0b701d27 5860 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5861
f564048e 5862 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5863 x, y, fb);
79e53945 5864 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5865
9256aa19
DV		 5866 if (ret != 0)
5867 return ret;
5868
5869 for_each_encoder_on_crtc(dev, crtc, encoder) {
5870 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5871 encoder->base.base.id,
5872 drm_get_encoder_name(&encoder->base),
5873 mode->base.id, mode->name);
5874 encoder_funcs = encoder->base.helper_private;
5875 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5876 }
5877
5878 return 0;
79e53945
JB		 5879}
5880
3a9627f4
WF		 5881static bool intel_eld_uptodate(struct drm_connector *connector,
5882 int reg_eldv, uint32_t bits_eldv,
5883 int reg_elda, uint32_t bits_elda,
5884 int reg_edid)
5885{
5886 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5887 uint8_t *eld = connector->eld;
5888 uint32_t i;
5889
5890 i = I915_READ(reg_eldv);
5891 i &= bits_eldv;
5892
5893 if (!eld[0])
5894 return !i;
5895
5896 if (!i)
5897 return false;
5898
5899 i = I915_READ(reg_elda);
5900 i &= ~bits_elda;
5901 I915_WRITE(reg_elda, i);
5902
5903 for (i = 0; i < eld[2]; i++)
5904 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5905 return false;
5906
5907 return true;
5908}
5909
e0dac65e
WF		 5910static void g4x_write_eld(struct drm_connector *connector,
5911 struct drm_crtc *crtc)
5912{
5913 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5914 uint8_t *eld = connector->eld;
5915 uint32_t eldv;
5916 uint32_t len;
5917 uint32_t i;
5918
5919 i = I915_READ(G4X_AUD_VID_DID);
5920
5921 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5922 eldv = G4X_ELDV_DEVCL_DEVBLC;
5923 else
5924 eldv = G4X_ELDV_DEVCTG;
5925
3a9627f4
WF		 5926 if (intel_eld_uptodate(connector,
5927 G4X_AUD_CNTL_ST, eldv,
5928 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5929 G4X_HDMIW_HDMIEDID))
5930 return;
5931
e0dac65e
WF		 5932 i = I915_READ(G4X_AUD_CNTL_ST);
5933 i &= ~(eldv | G4X_ELD_ADDR);
5934 len = (i >> 9) & 0x1f; /* ELD buffer size */
5935 I915_WRITE(G4X_AUD_CNTL_ST, i);
5936
5937 if (!eld[0])
5938 return;
5939
5940 len = min_t(uint8_t, eld[2], len);
5941 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5942 for (i = 0; i < len; i++)
5943 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5944
5945 i = I915_READ(G4X_AUD_CNTL_ST);
5946 i |= eldv;
5947 I915_WRITE(G4X_AUD_CNTL_ST, i);
5948}
5949
83358c85
WX		 5950static void haswell_write_eld(struct drm_connector *connector,
5951 struct drm_crtc *crtc)
5952{
5953 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5954 uint8_t *eld = connector->eld;
5955 struct drm_device *dev = crtc->dev;
7b9f35a6 5956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 5957 uint32_t eldv;
5958 uint32_t i;
5959 int len;
5960 int pipe = to_intel_crtc(crtc)->pipe;
5961 int tmp;
5962
5963 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5964 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5965 int aud_config = HSW_AUD_CFG(pipe);
5966 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5967
5968
5969 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5970
5971 /* Audio output enable */
5972 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5973 tmp = I915_READ(aud_cntrl_st2);
5974 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5975 I915_WRITE(aud_cntrl_st2, tmp);
5976
5977 /* Wait for 1 vertical blank */
5978 intel_wait_for_vblank(dev, pipe);
5979
5980 /* Set ELD valid state */
5981 tmp = I915_READ(aud_cntrl_st2);
5982 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5983 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5984 I915_WRITE(aud_cntrl_st2, tmp);
5985 tmp = I915_READ(aud_cntrl_st2);
5986 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5987
5988 /* Enable HDMI mode */
5989 tmp = I915_READ(aud_config);
5990 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5991 /* clear N_programing_enable and N_value_index */
5992 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5993 I915_WRITE(aud_config, tmp);
5994
5995 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5996
5997 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 5998 intel_crtc->eld_vld = true;
83358c85
WX		 5999
6000 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6001 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6002 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6003 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6004 } else
6005 I915_WRITE(aud_config, 0);
6006
6007 if (intel_eld_uptodate(connector,
6008 aud_cntrl_st2, eldv,
6009 aud_cntl_st, IBX_ELD_ADDRESS,
6010 hdmiw_hdmiedid))
6011 return;
6012
6013 i = I915_READ(aud_cntrl_st2);
6014 i &= ~eldv;
6015 I915_WRITE(aud_cntrl_st2, i);
6016
6017 if (!eld[0])
6018 return;
6019
6020 i = I915_READ(aud_cntl_st);
6021 i &= ~IBX_ELD_ADDRESS;
6022 I915_WRITE(aud_cntl_st, i);
6023 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6024 DRM_DEBUG_DRIVER("port num:%d\n", i);
6025
6026 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6027 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6028 for (i = 0; i < len; i++)
6029 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6030
6031 i = I915_READ(aud_cntrl_st2);
6032 i |= eldv;
6033 I915_WRITE(aud_cntrl_st2, i);
6034
6035}
6036
e0dac65e
WF		 6037static void ironlake_write_eld(struct drm_connector *connector,
6038 struct drm_crtc *crtc)
6039{
6040 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6041 uint8_t *eld = connector->eld;
6042 uint32_t eldv;
6043 uint32_t i;
6044 int len;
6045 int hdmiw_hdmiedid;
b6daa025 6046 int aud_config;
e0dac65e
WF		 6047 int aud_cntl_st;
6048 int aud_cntrl_st2;
9b138a83 6049 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6050
b3f33cbf 6051 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6052 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6053 aud_config = IBX_AUD_CFG(pipe);
6054 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6055 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6056 } else {
9b138a83
WX		 6057 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6058 aud_config = CPT_AUD_CFG(pipe);
6059 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6060 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6061 }
6062
9b138a83 6063 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6064
6065 i = I915_READ(aud_cntl_st);
9b138a83 6066 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6067 if (!i) {
6068 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6069 /* operate blindly on all ports */
1202b4c6
WF		 6070 eldv = IBX_ELD_VALIDB;
6071 eldv |= IBX_ELD_VALIDB << 4;
6072 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6073 } else {
6074 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6075 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6076 }
6077
3a9627f4
WF		 6078 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6079 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6080 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6081 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6082 } else
6083 I915_WRITE(aud_config, 0);
e0dac65e 6084
3a9627f4
WF		 6085 if (intel_eld_uptodate(connector,
6086 aud_cntrl_st2, eldv,
6087 aud_cntl_st, IBX_ELD_ADDRESS,
6088 hdmiw_hdmiedid))
6089 return;
6090
e0dac65e
WF		 6091 i = I915_READ(aud_cntrl_st2);
6092 i &= ~eldv;
6093 I915_WRITE(aud_cntrl_st2, i);
6094
6095 if (!eld[0])
6096 return;
6097
e0dac65e 6098 i = I915_READ(aud_cntl_st);
1202b4c6 6099 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6100 I915_WRITE(aud_cntl_st, i);
6101
6102 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6103 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6104 for (i = 0; i < len; i++)
6105 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6106
6107 i = I915_READ(aud_cntrl_st2);
6108 i |= eldv;
6109 I915_WRITE(aud_cntrl_st2, i);
6110}
6111
6112void intel_write_eld(struct drm_encoder *encoder,
6113 struct drm_display_mode *mode)
6114{
6115 struct drm_crtc *crtc = encoder->crtc;
6116 struct drm_connector *connector;
6117 struct drm_device *dev = encoder->dev;
6118 struct drm_i915_private *dev_priv = dev->dev_private;
6119
6120 connector = drm_select_eld(encoder, mode);
6121 if (!connector)
6122 return;
6123
6124 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6125 connector->base.id,
6126 drm_get_connector_name(connector),
6127 connector->encoder->base.id,
6128 drm_get_encoder_name(connector->encoder));
6129
6130 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6131
6132 if (dev_priv->display.write_eld)
6133 dev_priv->display.write_eld(connector, crtc);
6134}
6135
79e53945
JB		 6136/** Loads the palette/gamma unit for the CRTC with the prepared values */
6137void intel_crtc_load_lut(struct drm_crtc *crtc)
6138{
6139 struct drm_device *dev = crtc->dev;
6140 struct drm_i915_private *dev_priv = dev->dev_private;
6141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6142 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6143 int i;
6144
6145 /* The clocks have to be on to load the palette. */
aed3f09d 6146 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6147 return;
6148
f2b115e6 6149 /* use legacy palette for Ironlake */
bad720ff 6150 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6151 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6152
79e53945
JB		 6153 for (i = 0; i < 256; i++) {
6154 I915_WRITE(palreg + 4 * i,
6155 (intel_crtc->lut_r[i] << 16) |
6156 (intel_crtc->lut_g[i] << 8) |
6157 intel_crtc->lut_b[i]);
6158 }
6159}
6160
560b85bb
CW		 6161static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6162{
6163 struct drm_device *dev = crtc->dev;
6164 struct drm_i915_private *dev_priv = dev->dev_private;
6165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6166 bool visible = base != 0;
6167 u32 cntl;
6168
6169 if (intel_crtc->cursor_visible == visible)
6170 return;
6171
9db4a9c7 6172 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6173 if (visible) {
6174 /* On these chipsets we can only modify the base whilst
6175 * the cursor is disabled.
6176 */
9db4a9c7 6177 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6178
6179 cntl &= ~(CURSOR_FORMAT_MASK);
6180 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6181 cntl |= CURSOR_ENABLE |
6182 CURSOR_GAMMA_ENABLE |
6183 CURSOR_FORMAT_ARGB;
6184 } else
6185 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6186 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6187
6188 intel_crtc->cursor_visible = visible;
6189}
6190
6191static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6192{
6193 struct drm_device *dev = crtc->dev;
6194 struct drm_i915_private *dev_priv = dev->dev_private;
6195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6196 int pipe = intel_crtc->pipe;
6197 bool visible = base != 0;
6198
6199 if (intel_crtc->cursor_visible != visible) {
548f245b 6200 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6201 if (base) {
6202 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6203 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6204 cntl |= pipe << 28; /* Connect to correct pipe */
6205 } else {
6206 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6207 cntl |= CURSOR_MODE_DISABLE;
6208 }
9db4a9c7 6209 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6210
6211 intel_crtc->cursor_visible = visible;
6212 }
6213 /* and commit changes on next vblank */
9db4a9c7 6214 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6215}
6216
65a21cd6
JB		 6217static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6218{
6219 struct drm_device *dev = crtc->dev;
6220 struct drm_i915_private *dev_priv = dev->dev_private;
6221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6222 int pipe = intel_crtc->pipe;
6223 bool visible = base != 0;
6224
6225 if (intel_crtc->cursor_visible != visible) {
6226 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6227 if (base) {
6228 cntl &= ~CURSOR_MODE;
6229 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6230 } else {
6231 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6232 cntl |= CURSOR_MODE_DISABLE;
6233 }
86d3efce
VS		 6234 if (IS_HASWELL(dev))
6235 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6236 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6237
6238 intel_crtc->cursor_visible = visible;
6239 }
6240 /* and commit changes on next vblank */
6241 I915_WRITE(CURBASE_IVB(pipe), base);
6242}
6243
cda4b7d3 6244/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6245static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6246 bool on)
cda4b7d3
CW		 6247{
6248 struct drm_device *dev = crtc->dev;
6249 struct drm_i915_private *dev_priv = dev->dev_private;
6250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6251 int pipe = intel_crtc->pipe;
6252 int x = intel_crtc->cursor_x;
6253 int y = intel_crtc->cursor_y;
560b85bb 6254 u32 base, pos;
cda4b7d3
CW		 6255 bool visible;
6256
6257 pos = 0;
6258
6b383a7f 6259 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6260 base = intel_crtc->cursor_addr;
6261 if (x > (int) crtc->fb->width)
6262 base = 0;
6263
6264 if (y > (int) crtc->fb->height)
6265 base = 0;
6266 } else
6267 base = 0;
6268
6269 if (x < 0) {
6270 if (x + intel_crtc->cursor_width < 0)
6271 base = 0;
6272
6273 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6274 x = -x;
6275 }
6276 pos |= x << CURSOR_X_SHIFT;
6277
6278 if (y < 0) {
6279 if (y + intel_crtc->cursor_height < 0)
6280 base = 0;
6281
6282 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6283 y = -y;
6284 }
6285 pos |= y << CURSOR_Y_SHIFT;
6286
6287 visible = base != 0;
560b85bb 6288 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6289 return;
6290
0cd83aa9 6291 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6292 I915_WRITE(CURPOS_IVB(pipe), pos);
6293 ivb_update_cursor(crtc, base);
6294 } else {
6295 I915_WRITE(CURPOS(pipe), pos);
6296 if (IS_845G(dev) || IS_I865G(dev))
6297 i845_update_cursor(crtc, base);
6298 else
6299 i9xx_update_cursor(crtc, base);
6300 }
cda4b7d3
CW		 6301}
6302
79e53945 6303static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6304 struct drm_file *file,
79e53945
JB		 6305 uint32_t handle,
6306 uint32_t width, uint32_t height)
6307{
6308 struct drm_device *dev = crtc->dev;
6309 struct drm_i915_private *dev_priv = dev->dev_private;
6310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6311 struct drm_i915_gem_object *obj;
cda4b7d3 6312 uint32_t addr;
3f8bc370 6313 int ret;
79e53945 6314
79e53945
JB		 6315 /* if we want to turn off the cursor ignore width and height */
6316 if (!handle) {
28c97730 6317 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6318 addr = 0;
05394f39 6319 obj = NULL;
5004417d 6320 mutex_lock(&dev->struct_mutex);
3f8bc370 6321 goto finish;
79e53945
JB		 6322 }
6323
6324 /* Currently we only support 64x64 cursors */
6325 if (width != 64 || height != 64) {
6326 DRM_ERROR("we currently only support 64x64 cursors\n");
6327 return -EINVAL;
6328 }
6329
05394f39 6330 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6331 if (&obj->base == NULL)
79e53945
JB		 6332 return -ENOENT;
6333
05394f39 6334 if (obj->base.size < width * height * 4) {
79e53945 6335 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6336 ret = -ENOMEM;
6337 goto fail;
79e53945
JB		 6338 }
6339
71acb5eb 6340 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6341 mutex_lock(&dev->struct_mutex);
b295d1b6 6342 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6343 if (obj->tiling_mode) {
6344 DRM_ERROR("cursor cannot be tiled\n");
6345 ret = -EINVAL;
6346 goto fail_locked;
6347 }
6348
2da3b9b9 6349 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6350 if (ret) {
6351 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6352 goto fail_locked;
e7b526bb
CW		 6353 }
6354
d9e86c0e
CW		 6355 ret = i915_gem_object_put_fence(obj);
6356 if (ret) {
2da3b9b9 6357 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6358 goto fail_unpin;
6359 }
6360
05394f39 6361 addr = obj->gtt_offset;
71acb5eb 6362 } else {
6eeefaf3 6363 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6364 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6365 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6366 align);
71acb5eb
DA		 6367 if (ret) {
6368 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6369 goto fail_locked;
71acb5eb 6370 }
05394f39 6371 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6372 }
6373
a6c45cf0 6374 if (IS_GEN2(dev))
14b60391
JB		 6375 I915_WRITE(CURSIZE, (height << 12) | width);
6376
3f8bc370 6377 finish:
3f8bc370 6378 if (intel_crtc->cursor_bo) {
b295d1b6 6379 if (dev_priv->info->cursor_needs_physical) {
05394f39 6380 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6381 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6382 } else
6383 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6384 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6385 }
80824003 6386
7f9872e0 6387 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6388
6389 intel_crtc->cursor_addr = addr;
05394f39 6390 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6391 intel_crtc->cursor_width = width;
6392 intel_crtc->cursor_height = height;
6393
6b383a7f 6394 intel_crtc_update_cursor(crtc, true);
3f8bc370 6395
79e53945 6396 return 0;
e7b526bb 6397fail_unpin:
05394f39 6398 i915_gem_object_unpin(obj);
7f9872e0 6399fail_locked:
34b8686e 6400 mutex_unlock(&dev->struct_mutex);
bc9025bd 6401fail:
05394f39 6402 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6403 return ret;
79e53945
JB		 6404}
6405
6406static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6407{
79e53945 6408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6409
cda4b7d3
CW		 6410 intel_crtc->cursor_x = x;
6411 intel_crtc->cursor_y = y;
652c393a 6412
6b383a7f 6413 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6414
6415 return 0;
6416}
6417
6418/** Sets the color ramps on behalf of RandR */
6419void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6420 u16 blue, int regno)
6421{
6422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6423
6424 intel_crtc->lut_r[regno] = red >> 8;
6425 intel_crtc->lut_g[regno] = green >> 8;
6426 intel_crtc->lut_b[regno] = blue >> 8;
6427}
6428
b8c00ac5
DA		 6429void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6430 u16 *blue, int regno)
6431{
6432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6433
6434 *red = intel_crtc->lut_r[regno] << 8;
6435 *green = intel_crtc->lut_g[regno] << 8;
6436 *blue = intel_crtc->lut_b[regno] << 8;
6437}
6438
79e53945 6439static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6440 u16 *blue, uint32_t start, uint32_t size)
79e53945 6441{
7203425a 6442 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6443 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6444
7203425a 6445 for (i = start; i < end; i++) {
79e53945
JB		 6446 intel_crtc->lut_r[i] = red[i] >> 8;
6447 intel_crtc->lut_g[i] = green[i] >> 8;
6448 intel_crtc->lut_b[i] = blue[i] >> 8;
6449 }
6450
6451 intel_crtc_load_lut(crtc);
6452}
6453
79e53945
JB		 6454/* VESA 640x480x72Hz mode to set on the pipe */
6455static struct drm_display_mode load_detect_mode = {
6456 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6457 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6458};
6459
d2dff872
CW		 6460static struct drm_framebuffer *
6461intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6462 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6463 struct drm_i915_gem_object *obj)
6464{
6465 struct intel_framebuffer *intel_fb;
6466 int ret;
6467
6468 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6469 if (!intel_fb) {
6470 drm_gem_object_unreference_unlocked(&obj->base);
6471 return ERR_PTR(-ENOMEM);
6472 }
6473
6474 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6475 if (ret) {
6476 drm_gem_object_unreference_unlocked(&obj->base);
6477 kfree(intel_fb);
6478 return ERR_PTR(ret);
6479 }
6480
6481 return &intel_fb->base;
6482}
6483
6484static u32
6485intel_framebuffer_pitch_for_width(int width, int bpp)
6486{
6487 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6488 return ALIGN(pitch, 64);
6489}
6490
6491static u32
6492intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6493{
6494 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6495 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6496}
6497
6498static struct drm_framebuffer *
6499intel_framebuffer_create_for_mode(struct drm_device *dev,
6500 struct drm_display_mode *mode,
6501 int depth, int bpp)
6502{
6503 struct drm_i915_gem_object *obj;
0fed39bd 6504 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6505
6506 obj = i915_gem_alloc_object(dev,
6507 intel_framebuffer_size_for_mode(mode, bpp));
6508 if (obj == NULL)
6509 return ERR_PTR(-ENOMEM);
6510
6511 mode_cmd.width = mode->hdisplay;
6512 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6513 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6514 bpp);
5ca0c34a 6515 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6516
6517 return intel_framebuffer_create(dev, &mode_cmd, obj);
6518}
6519
6520static struct drm_framebuffer *
6521mode_fits_in_fbdev(struct drm_device *dev,
6522 struct drm_display_mode *mode)
6523{
6524 struct drm_i915_private *dev_priv = dev->dev_private;
6525 struct drm_i915_gem_object *obj;
6526 struct drm_framebuffer *fb;
6527
6528 if (dev_priv->fbdev == NULL)
6529 return NULL;
6530
6531 obj = dev_priv->fbdev->ifb.obj;
6532 if (obj == NULL)
6533 return NULL;
6534
6535 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6536 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6537 fb->bits_per_pixel))
d2dff872
CW		 6538 return NULL;
6539
01f2c773 6540 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6541 return NULL;
6542
6543 return fb;
6544}
6545
d2434ab7 6546bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6547 struct drm_display_mode *mode,
8261b191 6548 struct intel_load_detect_pipe *old)
79e53945
JB		 6549{
6550 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6551 struct intel_encoder *intel_encoder =
6552 intel_attached_encoder(connector);
79e53945 6553 struct drm_crtc *possible_crtc;
4ef69c7a 6554 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6555 struct drm_crtc *crtc = NULL;
6556 struct drm_device *dev = encoder->dev;
94352cf9 6557 struct drm_framebuffer *fb;
79e53945
JB		 6558 int i = -1;
6559
d2dff872
CW		 6560 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6561 connector->base.id, drm_get_connector_name(connector),
6562 encoder->base.id, drm_get_encoder_name(encoder));
6563
79e53945
JB		 6564 /*
6565 * Algorithm gets a little messy:
7a5e4805 6566 *
79e53945
JB		 6567 * - if the connector already has an assigned crtc, use it (but make
6568 * sure it's on first)
7a5e4805 6569 *
79e53945
JB		 6570 * - try to find the first unused crtc that can drive this connector,
6571 * and use that if we find one
79e53945
JB		 6572 */
6573
6574 /* See if we already have a CRTC for this connector */
6575 if (encoder->crtc) {
6576 crtc = encoder->crtc;
8261b191 6577
7b24056b
DV		 6578 mutex_lock(&crtc->mutex);
6579
24218aac 6580 old->dpms_mode = connector->dpms;
8261b191
CW		 6581 old->load_detect_temp = false;
6582
6583 /* Make sure the crtc and connector are running */
24218aac
DV		 6584 if (connector->dpms != DRM_MODE_DPMS_ON)
6585 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6586
7173188d 6587 return true;
79e53945
JB		 6588 }
6589
6590 /* Find an unused one (if possible) */
6591 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6592 i++;
6593 if (!(encoder->possible_crtcs & (1 << i)))
6594 continue;
6595 if (!possible_crtc->enabled) {
6596 crtc = possible_crtc;
6597 break;
6598 }
79e53945
JB		 6599 }
6600
6601 /*
6602 * If we didn't find an unused CRTC, don't use any.
6603 */
6604 if (!crtc) {
7173188d
CW		 6605 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6606 return false;
79e53945
JB		 6607 }
6608
7b24056b 6609 mutex_lock(&crtc->mutex);
fc303101
DV		 6610 intel_encoder->new_crtc = to_intel_crtc(crtc);
6611 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6612
6613 intel_crtc = to_intel_crtc(crtc);
24218aac 6614 old->dpms_mode = connector->dpms;
8261b191 6615 old->load_detect_temp = true;
d2dff872 6616 old->release_fb = NULL;
79e53945 6617
6492711d
CW		 6618 if (!mode)
6619 mode = &load_detect_mode;
79e53945 6620
d2dff872
CW		 6621 /* We need a framebuffer large enough to accommodate all accesses
6622 * that the plane may generate whilst we perform load detection.
6623 * We can not rely on the fbcon either being present (we get called
6624 * during its initialisation to detect all boot displays, or it may
6625 * not even exist) or that it is large enough to satisfy the
6626 * requested mode.
6627 */
94352cf9
DV		 6628 fb = mode_fits_in_fbdev(dev, mode);
6629 if (fb == NULL) {
d2dff872 6630 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6631 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6632 old->release_fb = fb;
d2dff872
CW		 6633 } else
6634 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6635 if (IS_ERR(fb)) {
d2dff872 6636 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6637 mutex_unlock(&crtc->mutex);
0e8b3d3e 6638 return false;
79e53945 6639 }
79e53945 6640
c0c36b94 6641 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6642 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6643 if (old->release_fb)
6644 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6645 mutex_unlock(&crtc->mutex);
0e8b3d3e 6646 return false;
79e53945 6647 }
7173188d 6648
79e53945 6649 /* let the connector get through one full cycle before testing */
9d0498a2 6650 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6651 return true;
79e53945
JB		 6652}
6653
d2434ab7 6654void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6655 struct intel_load_detect_pipe *old)
79e53945 6656{
d2434ab7
DV		 6657 struct intel_encoder *intel_encoder =
6658 intel_attached_encoder(connector);
4ef69c7a 6659 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6660 struct drm_crtc *crtc = encoder->crtc;
79e53945 6661
d2dff872
CW		 6662 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6663 connector->base.id, drm_get_connector_name(connector),
6664 encoder->base.id, drm_get_encoder_name(encoder));
6665
8261b191 6666 if (old->load_detect_temp) {
fc303101
DV		 6667 to_intel_connector(connector)->new_encoder = NULL;
6668 intel_encoder->new_crtc = NULL;
6669 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6670
36206361
DV		 6671 if (old->release_fb) {
6672 drm_framebuffer_unregister_private(old->release_fb);
6673 drm_framebuffer_unreference(old->release_fb);
6674 }
d2dff872 6675
67c96400 6676 mutex_unlock(&crtc->mutex);
0622a53c 6677 return;
79e53945
JB		 6678 }
6679
c751ce4f 6680 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6681 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6682 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6683
6684 mutex_unlock(&crtc->mutex);
79e53945
JB		 6685}
6686
6687/* Returns the clock of the currently programmed mode of the given pipe. */
6688static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6689{
6690 struct drm_i915_private *dev_priv = dev->dev_private;
6691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6692 int pipe = intel_crtc->pipe;
548f245b 6693 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6694 u32 fp;
6695 intel_clock_t clock;
6696
6697 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6698 fp = I915_READ(FP0(pipe));
79e53945 6699 else
39adb7a5 6700 fp = I915_READ(FP1(pipe));
79e53945
JB		 6701
6702 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6703 if (IS_PINEVIEW(dev)) {
6704 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6705 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6706 } else {
6707 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6708 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6709 }
6710
a6c45cf0 6711 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6712 if (IS_PINEVIEW(dev))
6713 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6714 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6715 else
6716 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6717 DPLL_FPA01_P1_POST_DIV_SHIFT);
6718
6719 switch (dpll & DPLL_MODE_MASK) {
6720 case DPLLB_MODE_DAC_SERIAL:
6721 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6722 5 : 10;
6723 break;
6724 case DPLLB_MODE_LVDS:
6725 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6726 7 : 14;
6727 break;
6728 default:
28c97730 6729 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6730 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6731 return 0;
6732 }
6733
6734 /* XXX: Handle the 100Mhz refclk */
2177832f 6735 intel_clock(dev, 96000, &clock);
79e53945
JB		 6736 } else {
6737 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6738
6739 if (is_lvds) {
6740 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6741 DPLL_FPA01_P1_POST_DIV_SHIFT);
6742 clock.p2 = 14;
6743
6744 if ((dpll & PLL_REF_INPUT_MASK) ==
6745 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6746 /* XXX: might not be 66MHz */
2177832f 6747 intel_clock(dev, 66000, &clock);
79e53945 6748 } else
2177832f 6749 intel_clock(dev, 48000, &clock);
79e53945
JB		 6750 } else {
6751 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6752 clock.p1 = 2;
6753 else {
6754 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6755 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6756 }
6757 if (dpll & PLL_P2_DIVIDE_BY_4)
6758 clock.p2 = 4;
6759 else
6760 clock.p2 = 2;
6761
2177832f 6762 intel_clock(dev, 48000, &clock);
79e53945
JB		 6763 }
6764 }
6765
6766 /* XXX: It would be nice to validate the clocks, but we can't reuse
6767 * i830PllIsValid() because it relies on the xf86_config connector
6768 * configuration being accurate, which it isn't necessarily.
6769 */
6770
6771 return clock.dot;
6772}
6773
6774/** Returns the currently programmed mode of the given pipe. */
6775struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6776 struct drm_crtc *crtc)
6777{
548f245b 6778 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6780 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6781 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6782 int htot = I915_READ(HTOTAL(cpu_transcoder));
6783 int hsync = I915_READ(HSYNC(cpu_transcoder));
6784 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6785 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6786
6787 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6788 if (!mode)
6789 return NULL;
6790
6791 mode->clock = intel_crtc_clock_get(dev, crtc);
6792 mode->hdisplay = (htot & 0xffff) + 1;
6793 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6794 mode->hsync_start = (hsync & 0xffff) + 1;
6795 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6796 mode->vdisplay = (vtot & 0xffff) + 1;
6797 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6798 mode->vsync_start = (vsync & 0xffff) + 1;
6799 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6800
6801 drm_mode_set_name(mode);
79e53945
JB		 6802
6803 return mode;
6804}
6805
3dec0095 6806static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6807{
6808 struct drm_device *dev = crtc->dev;
6809 drm_i915_private_t *dev_priv = dev->dev_private;
6810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6811 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6812 int dpll_reg = DPLL(pipe);
6813 int dpll;
652c393a 6814
bad720ff 6815 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6816 return;
6817
6818 if (!dev_priv->lvds_downclock_avail)
6819 return;
6820
dbdc6479 6821 dpll = I915_READ(dpll_reg);
652c393a 6822 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6823 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6824
8ac5a6d5 6825 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6826
6827 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6828 I915_WRITE(dpll_reg, dpll);
9d0498a2 6829 intel_wait_for_vblank(dev, pipe);
dbdc6479 6830
652c393a
JB		 6831 dpll = I915_READ(dpll_reg);
6832 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6833 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6834 }
652c393a
JB		 6835}
6836
6837static void intel_decrease_pllclock(struct drm_crtc *crtc)
6838{
6839 struct drm_device *dev = crtc->dev;
6840 drm_i915_private_t *dev_priv = dev->dev_private;
6841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6842
bad720ff 6843 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6844 return;
6845
6846 if (!dev_priv->lvds_downclock_avail)
6847 return;
6848
6849 /*
6850 * Since this is called by a timer, we should never get here in
6851 * the manual case.
6852 */
6853 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6854 int pipe = intel_crtc->pipe;
6855 int dpll_reg = DPLL(pipe);
6856 int dpll;
f6e5b160 6857
44d98a61 6858 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6859
8ac5a6d5 6860 assert_panel_unlocked(dev_priv, pipe);
652c393a 6861
dc257cf1 6862 dpll = I915_READ(dpll_reg);
652c393a
JB		 6863 dpll |= DISPLAY_RATE_SELECT_FPA1;
6864 I915_WRITE(dpll_reg, dpll);
9d0498a2 6865 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6866 dpll = I915_READ(dpll_reg);
6867 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6868 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6869 }
6870
6871}
6872
f047e395
CW		 6873void intel_mark_busy(struct drm_device *dev)
6874{
f047e395
CW		 6875 i915_update_gfx_val(dev->dev_private);
6876}
6877
6878void intel_mark_idle(struct drm_device *dev)
652c393a 6879{
652c393a 6880 struct drm_crtc *crtc;
652c393a
JB		 6881
6882 if (!i915_powersave)
6883 return;
6884
652c393a 6885 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6886 if (!crtc->fb)
6887 continue;
6888
725a5b54 6889 intel_decrease_pllclock(crtc);
652c393a 6890 }
652c393a
JB		 6891}
6892
725a5b54 6893void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6894{
f047e395
CW		 6895 struct drm_device *dev = obj->base.dev;
6896 struct drm_crtc *crtc;
652c393a 6897
f047e395 6898 if (!i915_powersave)
acb87dfb
CW		 6899 return;
6900
652c393a
JB		 6901 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6902 if (!crtc->fb)
6903 continue;
6904
f047e395 6905 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6906 intel_increase_pllclock(crtc);
652c393a
JB		 6907 }
6908}
6909
79e53945
JB		 6910static void intel_crtc_destroy(struct drm_crtc *crtc)
6911{
6912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6913 struct drm_device *dev = crtc->dev;
6914 struct intel_unpin_work *work;
6915 unsigned long flags;
6916
6917 spin_lock_irqsave(&dev->event_lock, flags);
6918 work = intel_crtc->unpin_work;
6919 intel_crtc->unpin_work = NULL;
6920 spin_unlock_irqrestore(&dev->event_lock, flags);
6921
6922 if (work) {
6923 cancel_work_sync(&work->work);
6924 kfree(work);
6925 }
79e53945
JB		 6926
6927 drm_crtc_cleanup(crtc);
67e77c5a 6928
79e53945
JB		 6929 kfree(intel_crtc);
6930}
6931
6b95a207
KH		 6932static void intel_unpin_work_fn(struct work_struct *__work)
6933{
6934 struct intel_unpin_work *work =
6935 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6936 struct drm_device *dev = work->crtc->dev;
6b95a207 6937
b4a98e57 6938 mutex_lock(&dev->struct_mutex);
1690e1eb 6939 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6940 drm_gem_object_unreference(&work->pending_flip_obj->base);
6941 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6942
b4a98e57
CW		 6943 intel_update_fbc(dev);
6944 mutex_unlock(&dev->struct_mutex);
6945
6946 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6947 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6948
6b95a207
KH		 6949 kfree(work);
6950}
6951
1afe3e9d 6952static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6953 struct drm_crtc *crtc)
6b95a207
KH		 6954{
6955 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6957 struct intel_unpin_work *work;
6b95a207
KH		 6958 unsigned long flags;
6959
6960 /* Ignore early vblank irqs */
6961 if (intel_crtc == NULL)
6962 return;
6963
6964 spin_lock_irqsave(&dev->event_lock, flags);
6965 work = intel_crtc->unpin_work;
e7d841ca
CW		 6966
6967 /* Ensure we don't miss a work->pending update ... */
6968 smp_rmb();
6969
6970 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 6971 spin_unlock_irqrestore(&dev->event_lock, flags);
6972 return;
6973 }
6974
e7d841ca
CW		 6975 /* and that the unpin work is consistent wrt ->pending. */
6976 smp_rmb();
6977
6b95a207 6978 intel_crtc->unpin_work = NULL;
6b95a207 6979
45a066eb
RC		 6980 if (work->event)
6981 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6982
0af7e4df
MK		 6983 drm_vblank_put(dev, intel_crtc->pipe);
6984
6b95a207
KH		 6985 spin_unlock_irqrestore(&dev->event_lock, flags);
6986
2c10d571 6987 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6988
6989 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6990
6991 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6992}
6993
1afe3e9d
JB		 6994void intel_finish_page_flip(struct drm_device *dev, int pipe)
6995{
6996 drm_i915_private_t *dev_priv = dev->dev_private;
6997 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6998
49b14a5c 6999 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7000}
7001
7002void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7003{
7004 drm_i915_private_t *dev_priv = dev->dev_private;
7005 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7006
49b14a5c 7007 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7008}
7009
6b95a207
KH		 7010void intel_prepare_page_flip(struct drm_device *dev, int plane)
7011{
7012 drm_i915_private_t *dev_priv = dev->dev_private;
7013 struct intel_crtc *intel_crtc =
7014 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7015 unsigned long flags;
7016
e7d841ca
CW		 7017 /* NB: An MMIO update of the plane base pointer will also
7018 * generate a page-flip completion irq, i.e. every modeset
7019 * is also accompanied by a spurious intel_prepare_page_flip().
7020 */
6b95a207 7021 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7022 if (intel_crtc->unpin_work)
7023 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7024 spin_unlock_irqrestore(&dev->event_lock, flags);
7025}
7026
e7d841ca
CW		 7027inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7028{
7029 /* Ensure that the work item is consistent when activating it ... */
7030 smp_wmb();
7031 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7032 /* and that it is marked active as soon as the irq could fire. */
7033 smp_wmb();
7034}
7035
8c9f3aaf
JB		 7036static int intel_gen2_queue_flip(struct drm_device *dev,
7037 struct drm_crtc *crtc,
7038 struct drm_framebuffer *fb,
7039 struct drm_i915_gem_object *obj)
7040{
7041 struct drm_i915_private *dev_priv = dev->dev_private;
7042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7043 u32 flip_mask;
6d90c952 7044 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7045 int ret;
7046
6d90c952 7047 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7048 if (ret)
83d4092b 7049 goto err;
8c9f3aaf 7050
6d90c952 7051 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7052 if (ret)
83d4092b 7053 goto err_unpin;
8c9f3aaf
JB		 7054
7055 /* Can't queue multiple flips, so wait for the previous
7056 * one to finish before executing the next.
7057 */
7058 if (intel_crtc->plane)
7059 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7060 else
7061 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7062 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7063 intel_ring_emit(ring, MI_NOOP);
7064 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7065 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7066 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7067 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7068 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7069
7070 intel_mark_page_flip_active(intel_crtc);
6d90c952 7071 intel_ring_advance(ring);
83d4092b
CW		 7072 return 0;
7073
7074err_unpin:
7075 intel_unpin_fb_obj(obj);
7076err:
8c9f3aaf
JB		 7077 return ret;
7078}
7079
7080static int intel_gen3_queue_flip(struct drm_device *dev,
7081 struct drm_crtc *crtc,
7082 struct drm_framebuffer *fb,
7083 struct drm_i915_gem_object *obj)
7084{
7085 struct drm_i915_private *dev_priv = dev->dev_private;
7086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7087 u32 flip_mask;
6d90c952 7088 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7089 int ret;
7090
6d90c952 7091 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7092 if (ret)
83d4092b 7093 goto err;
8c9f3aaf 7094
6d90c952 7095 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7096 if (ret)
83d4092b 7097 goto err_unpin;
8c9f3aaf
JB		 7098
7099 if (intel_crtc->plane)
7100 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7101 else
7102 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7103 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7104 intel_ring_emit(ring, MI_NOOP);
7105 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7106 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7107 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7108 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7109 intel_ring_emit(ring, MI_NOOP);
7110
e7d841ca 7111 intel_mark_page_flip_active(intel_crtc);
6d90c952 7112 intel_ring_advance(ring);
83d4092b
CW		 7113 return 0;
7114
7115err_unpin:
7116 intel_unpin_fb_obj(obj);
7117err:
8c9f3aaf
JB		 7118 return ret;
7119}
7120
7121static int intel_gen4_queue_flip(struct drm_device *dev,
7122 struct drm_crtc *crtc,
7123 struct drm_framebuffer *fb,
7124 struct drm_i915_gem_object *obj)
7125{
7126 struct drm_i915_private *dev_priv = dev->dev_private;
7127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7128 uint32_t pf, pipesrc;
6d90c952 7129 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7130 int ret;
7131
6d90c952 7132 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7133 if (ret)
83d4092b 7134 goto err;
8c9f3aaf 7135
6d90c952 7136 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7137 if (ret)
83d4092b 7138 goto err_unpin;
8c9f3aaf
JB		 7139
7140 /* i965+ uses the linear or tiled offsets from the
7141 * Display Registers (which do not change across a page-flip)
7142 * so we need only reprogram the base address.
7143 */
6d90c952
DV		 7144 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7145 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7146 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7147 intel_ring_emit(ring,
7148 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7149 obj->tiling_mode);
8c9f3aaf
JB		 7150
7151 /* XXX Enabling the panel-fitter across page-flip is so far
7152 * untested on non-native modes, so ignore it for now.
7153 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7154 */
7155 pf = 0;
7156 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7157 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7158
7159 intel_mark_page_flip_active(intel_crtc);
6d90c952 7160 intel_ring_advance(ring);
83d4092b
CW		 7161 return 0;
7162
7163err_unpin:
7164 intel_unpin_fb_obj(obj);
7165err:
8c9f3aaf
JB		 7166 return ret;
7167}
7168
7169static int intel_gen6_queue_flip(struct drm_device *dev,
7170 struct drm_crtc *crtc,
7171 struct drm_framebuffer *fb,
7172 struct drm_i915_gem_object *obj)
7173{
7174 struct drm_i915_private *dev_priv = dev->dev_private;
7175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7176 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7177 uint32_t pf, pipesrc;
7178 int ret;
7179
6d90c952 7180 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7181 if (ret)
83d4092b 7182 goto err;
8c9f3aaf 7183
6d90c952 7184 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7185 if (ret)
83d4092b 7186 goto err_unpin;
8c9f3aaf 7187
6d90c952
DV		 7188 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7189 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7190 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7191 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7192
dc257cf1
DV		 7193 /* Contrary to the suggestions in the documentation,
7194 * "Enable Panel Fitter" does not seem to be required when page
7195 * flipping with a non-native mode, and worse causes a normal
7196 * modeset to fail.
7197 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7198 */
7199 pf = 0;
8c9f3aaf 7200 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7201 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7202
7203 intel_mark_page_flip_active(intel_crtc);
6d90c952 7204 intel_ring_advance(ring);
83d4092b
CW		 7205 return 0;
7206
7207err_unpin:
7208 intel_unpin_fb_obj(obj);
7209err:
8c9f3aaf
JB		 7210 return ret;
7211}
7212
7c9017e5
JB		 7213/*
7214 * On gen7 we currently use the blit ring because (in early silicon at least)
7215 * the render ring doesn't give us interrpts for page flip completion, which
7216 * means clients will hang after the first flip is queued. Fortunately the
7217 * blit ring generates interrupts properly, so use it instead.
7218 */
7219static int intel_gen7_queue_flip(struct drm_device *dev,
7220 struct drm_crtc *crtc,
7221 struct drm_framebuffer *fb,
7222 struct drm_i915_gem_object *obj)
7223{
7224 struct drm_i915_private *dev_priv = dev->dev_private;
7225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7226 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7227 uint32_t plane_bit = 0;
7c9017e5
JB		 7228 int ret;
7229
7230 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7231 if (ret)
83d4092b 7232 goto err;
7c9017e5 7233
cb05d8de
DV		 7234 switch(intel_crtc->plane) {
7235 case PLANE_A:
7236 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7237 break;
7238 case PLANE_B:
7239 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7240 break;
7241 case PLANE_C:
7242 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7243 break;
7244 default:
7245 WARN_ONCE(1, "unknown plane in flip command\n");
7246 ret = -ENODEV;
ab3951eb 7247 goto err_unpin;
cb05d8de
DV		 7248 }
7249
7c9017e5
JB		 7250 ret = intel_ring_begin(ring, 4);
7251 if (ret)
83d4092b 7252 goto err_unpin;
7c9017e5 7253
cb05d8de 7254 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7255 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7256 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7257 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7258
7259 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7260 intel_ring_advance(ring);
83d4092b
CW		 7261 return 0;
7262
7263err_unpin:
7264 intel_unpin_fb_obj(obj);
7265err:
7c9017e5
JB		 7266 return ret;
7267}
7268
8c9f3aaf
JB		 7269static int intel_default_queue_flip(struct drm_device *dev,
7270 struct drm_crtc *crtc,
7271 struct drm_framebuffer *fb,
7272 struct drm_i915_gem_object *obj)
7273{
7274 return -ENODEV;
7275}
7276
6b95a207
KH		 7277static int intel_crtc_page_flip(struct drm_crtc *crtc,
7278 struct drm_framebuffer *fb,
7279 struct drm_pending_vblank_event *event)
7280{
7281 struct drm_device *dev = crtc->dev;
7282 struct drm_i915_private *dev_priv = dev->dev_private;
7283 struct intel_framebuffer *intel_fb;
05394f39 7284 struct drm_i915_gem_object *obj;
6b95a207
KH		 7285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7286 struct intel_unpin_work *work;
8c9f3aaf 7287 unsigned long flags;
52e68630 7288 int ret;
6b95a207 7289
e6a595d2
VS		 7290 /* Can't change pixel format via MI display flips. */
7291 if (fb->pixel_format != crtc->fb->pixel_format)
7292 return -EINVAL;
7293
7294 /*
7295 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7296 * Note that pitch changes could also affect these register.
7297 */
7298 if (INTEL_INFO(dev)->gen > 3 &&
7299 (fb->offsets[0] != crtc->fb->offsets[0] ||
7300 fb->pitches[0] != crtc->fb->pitches[0]))
7301 return -EINVAL;
7302
6b95a207
KH		 7303 work = kzalloc(sizeof *work, GFP_KERNEL);
7304 if (work == NULL)
7305 return -ENOMEM;
7306
6b95a207 7307 work->event = event;
b4a98e57 7308 work->crtc = crtc;
6b95a207 7309 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7310 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7311 INIT_WORK(&work->work, intel_unpin_work_fn);
7312
7317c75e
JB		 7313 ret = drm_vblank_get(dev, intel_crtc->pipe);
7314 if (ret)
7315 goto free_work;
7316
6b95a207
KH		 7317 /* We borrow the event spin lock for protecting unpin_work */
7318 spin_lock_irqsave(&dev->event_lock, flags);
7319 if (intel_crtc->unpin_work) {
7320 spin_unlock_irqrestore(&dev->event_lock, flags);
7321 kfree(work);
7317c75e 7322 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7323
7324 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7325 return -EBUSY;
7326 }
7327 intel_crtc->unpin_work = work;
7328 spin_unlock_irqrestore(&dev->event_lock, flags);
7329
7330 intel_fb = to_intel_framebuffer(fb);
7331 obj = intel_fb->obj;
7332
b4a98e57
CW		 7333 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7334 flush_workqueue(dev_priv->wq);
7335
79158103
CW		 7336 ret = i915_mutex_lock_interruptible(dev);
7337 if (ret)
7338 goto cleanup;
6b95a207 7339
75dfca80 7340 /* Reference the objects for the scheduled work. */
05394f39
CW		 7341 drm_gem_object_reference(&work->old_fb_obj->base);
7342 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7343
7344 crtc->fb = fb;
96b099fd 7345
e1f99ce6 7346 work->pending_flip_obj = obj;
e1f99ce6 7347
4e5359cd
SF		 7348 work->enable_stall_check = true;
7349
b4a98e57 7350 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7351 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7352
8c9f3aaf
JB		 7353 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7354 if (ret)
7355 goto cleanup_pending;
6b95a207 7356
7782de3b 7357 intel_disable_fbc(dev);
f047e395 7358 intel_mark_fb_busy(obj);
6b95a207
KH		 7359 mutex_unlock(&dev->struct_mutex);
7360
e5510fac
JB		 7361 trace_i915_flip_request(intel_crtc->plane, obj);
7362
6b95a207 7363 return 0;
96b099fd 7364
8c9f3aaf 7365cleanup_pending:
b4a98e57 7366 atomic_dec(&intel_crtc->unpin_work_count);
05394f39
CW		 7367 drm_gem_object_unreference(&work->old_fb_obj->base);
7368 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7369 mutex_unlock(&dev->struct_mutex);
7370
79158103 7371cleanup:
96b099fd
CW		 7372 spin_lock_irqsave(&dev->event_lock, flags);
7373 intel_crtc->unpin_work = NULL;
7374 spin_unlock_irqrestore(&dev->event_lock, flags);
7375
7317c75e
JB		 7376 drm_vblank_put(dev, intel_crtc->pipe);
7377free_work:
96b099fd
CW		 7378 kfree(work);
7379
7380 return ret;
6b95a207
KH		 7381}
7382
f6e5b160 7383static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7384 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7385 .load_lut = intel_crtc_load_lut,
976f8a20 7386 .disable = intel_crtc_noop,
f6e5b160
CW		 7387};
7388
6ed0f796 7389bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7390{
6ed0f796
DV		 7391 struct intel_encoder *other_encoder;
7392 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7393
6ed0f796
DV		 7394 if (WARN_ON(!crtc))
7395 return false;
7396
7397 list_for_each_entry(other_encoder,
7398 &crtc->dev->mode_config.encoder_list,
7399 base.head) {
7400
7401 if (&other_encoder->new_crtc->base != crtc ||
7402 encoder == other_encoder)
7403 continue;
7404 else
7405 return true;
f47166d2
CW		 7406 }
7407
6ed0f796
DV		 7408 return false;
7409}
47f1c6c9 7410
50f56119
DV		 7411static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7412 struct drm_crtc *crtc)
7413{
7414 struct drm_device *dev;
7415 struct drm_crtc *tmp;
7416 int crtc_mask = 1;
47f1c6c9 7417
50f56119 7418 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7419
50f56119 7420 dev = crtc->dev;
47f1c6c9 7421
50f56119
DV		 7422 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7423 if (tmp == crtc)
7424 break;
7425 crtc_mask <<= 1;
7426 }
47f1c6c9 7427
50f56119
DV		 7428 if (encoder->possible_crtcs & crtc_mask)
7429 return true;
7430 return false;
47f1c6c9 7431}
79e53945 7432
9a935856
DV		 7433/**
7434 * intel_modeset_update_staged_output_state
7435 *
7436 * Updates the staged output configuration state, e.g. after we've read out the
7437 * current hw state.
7438 */
7439static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7440{
9a935856
DV		 7441 struct intel_encoder *encoder;
7442 struct intel_connector *connector;
f6e5b160 7443
9a935856
DV		 7444 list_for_each_entry(connector, &dev->mode_config.connector_list,
7445 base.head) {
7446 connector->new_encoder =
7447 to_intel_encoder(connector->base.encoder);
7448 }
f6e5b160 7449
9a935856
DV		 7450 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7451 base.head) {
7452 encoder->new_crtc =
7453 to_intel_crtc(encoder->base.crtc);
7454 }
f6e5b160
CW		 7455}
7456
9a935856
DV		 7457/**
7458 * intel_modeset_commit_output_state
7459 *
7460 * This function copies the stage display pipe configuration to the real one.
7461 */
7462static void intel_modeset_commit_output_state(struct drm_device *dev)
7463{
7464 struct intel_encoder *encoder;
7465 struct intel_connector *connector;
f6e5b160 7466
9a935856
DV		 7467 list_for_each_entry(connector, &dev->mode_config.connector_list,
7468 base.head) {
7469 connector->base.encoder = &connector->new_encoder->base;
7470 }
f6e5b160 7471
9a935856
DV		 7472 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7473 base.head) {
7474 encoder->base.crtc = &encoder->new_crtc->base;
7475 }
7476}
7477
7758a113
DV		 7478static struct drm_display_mode *
7479intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7480 struct drm_display_mode *mode)
ee7b9f93 7481{
7758a113
DV		 7482 struct drm_device *dev = crtc->dev;
7483 struct drm_display_mode *adjusted_mode;
7484 struct drm_encoder_helper_funcs *encoder_funcs;
7485 struct intel_encoder *encoder;
ee7b9f93 7486
7758a113
DV		 7487 adjusted_mode = drm_mode_duplicate(dev, mode);
7488 if (!adjusted_mode)
7489 return ERR_PTR(-ENOMEM);
7490
7491 /* Pass our mode to the connectors and the CRTC to give them a chance to
7492 * adjust it according to limitations or connector properties, and also
7493 * a chance to reject the mode entirely.
47f1c6c9 7494 */
7758a113
DV		 7495 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7496 base.head) {
47f1c6c9 7497
7758a113
DV		 7498 if (&encoder->new_crtc->base != crtc)
7499 continue;
7500 encoder_funcs = encoder->base.helper_private;
7501 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7502 adjusted_mode))) {
7503 DRM_DEBUG_KMS("Encoder fixup failed\n");
7504 goto fail;
7505 }
ee7b9f93 7506 }
47f1c6c9 7507
7758a113
DV		 7508 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7509 DRM_DEBUG_KMS("CRTC fixup failed\n");
7510 goto fail;
ee7b9f93 7511 }
7758a113 7512 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7513
7758a113
DV		 7514 return adjusted_mode;
7515fail:
7516 drm_mode_destroy(dev, adjusted_mode);
7517 return ERR_PTR(-EINVAL);
ee7b9f93 7518}
47f1c6c9 7519
e2e1ed41
DV		 7520/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7521 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7522static void
7523intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7524 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7525{
7526 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7527 struct drm_device *dev = crtc->dev;
7528 struct intel_encoder *encoder;
7529 struct intel_connector *connector;
7530 struct drm_crtc *tmp_crtc;
79e53945 7531
e2e1ed41 7532 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7533
e2e1ed41
DV		 7534 /* Check which crtcs have changed outputs connected to them, these need
7535 * to be part of the prepare_pipes mask. We don't (yet) support global
7536 * modeset across multiple crtcs, so modeset_pipes will only have one
7537 * bit set at most. */
7538 list_for_each_entry(connector, &dev->mode_config.connector_list,
7539 base.head) {
7540 if (connector->base.encoder == &connector->new_encoder->base)
7541 continue;
79e53945 7542
e2e1ed41
DV		 7543 if (connector->base.encoder) {
7544 tmp_crtc = connector->base.encoder->crtc;
7545
7546 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7547 }
7548
7549 if (connector->new_encoder)
7550 *prepare_pipes |=
7551 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7552 }
7553
e2e1ed41
DV		 7554 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7555 base.head) {
7556 if (encoder->base.crtc == &encoder->new_crtc->base)
7557 continue;
7558
7559 if (encoder->base.crtc) {
7560 tmp_crtc = encoder->base.crtc;
7561
7562 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7563 }
7564
7565 if (encoder->new_crtc)
7566 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7567 }
7568
e2e1ed41
DV		 7569 /* Check for any pipes that will be fully disabled ... */
7570 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7571 base.head) {
7572 bool used = false;
22fd0fab 7573
e2e1ed41
DV		 7574 /* Don't try to disable disabled crtcs. */
7575 if (!intel_crtc->base.enabled)
7576 continue;
7e7d76c3 7577
e2e1ed41
DV		 7578 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7579 base.head) {
7580 if (encoder->new_crtc == intel_crtc)
7581 used = true;
7582 }
7583
7584 if (!used)
7585 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7586 }
7587
e2e1ed41
DV		 7588
7589 /* set_mode is also used to update properties on life display pipes. */
7590 intel_crtc = to_intel_crtc(crtc);
7591 if (crtc->enabled)
7592 *prepare_pipes |= 1 << intel_crtc->pipe;
7593
7594 /* We only support modeset on one single crtc, hence we need to do that
7595 * only for the passed in crtc iff we change anything else than just
7596 * disable crtcs.
7597 *
7598 * This is actually not true, to be fully compatible with the old crtc
7599 * helper we automatically disable _any_ output (i.e. doesn't need to be
7600 * connected to the crtc we're modesetting on) if it's disconnected.
7601 * Which is a rather nutty api (since changed the output configuration
7602 * without userspace's explicit request can lead to confusion), but
7603 * alas. Hence we currently need to modeset on all pipes we prepare. */
7604 if (*prepare_pipes)
7605 *modeset_pipes = *prepare_pipes;
7606
7607 /* ... and mask these out. */
7608 *modeset_pipes &= ~(*disable_pipes);
7609 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7610}
79e53945 7611
ea9d758d 7612static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7613{
ea9d758d 7614 struct drm_encoder *encoder;
f6e5b160 7615 struct drm_device *dev = crtc->dev;
f6e5b160 7616
ea9d758d
DV		 7617 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7618 if (encoder->crtc == crtc)
7619 return true;
7620
7621 return false;
7622}
7623
7624static void
7625intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7626{
7627 struct intel_encoder *intel_encoder;
7628 struct intel_crtc *intel_crtc;
7629 struct drm_connector *connector;
7630
7631 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7632 base.head) {
7633 if (!intel_encoder->base.crtc)
7634 continue;
7635
7636 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7637
7638 if (prepare_pipes & (1 << intel_crtc->pipe))
7639 intel_encoder->connectors_active = false;
7640 }
7641
7642 intel_modeset_commit_output_state(dev);
7643
7644 /* Update computed state. */
7645 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7646 base.head) {
7647 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7648 }
7649
7650 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7651 if (!connector->encoder || !connector->encoder->crtc)
7652 continue;
7653
7654 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7655
7656 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7657 struct drm_property *dpms_property =
7658 dev->mode_config.dpms_property;
7659
ea9d758d 7660 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7661 drm_object_property_set_value(&connector->base,
68d34720
DV		 7662 dpms_property,
7663 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7664
7665 intel_encoder = to_intel_encoder(connector->encoder);
7666 intel_encoder->connectors_active = true;
7667 }
7668 }
7669
7670}
7671
25c5b266
DV		 7672#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7673 list_for_each_entry((intel_crtc), \
7674 &(dev)->mode_config.crtc_list, \
7675 base.head) \
7676 if (mask & (1 <<(intel_crtc)->pipe)) \
7677
b980514c 7678void
8af6cf88
DV		 7679intel_modeset_check_state(struct drm_device *dev)
7680{
7681 struct intel_crtc *crtc;
7682 struct intel_encoder *encoder;
7683 struct intel_connector *connector;
7684
7685 list_for_each_entry(connector, &dev->mode_config.connector_list,
7686 base.head) {
7687 /* This also checks the encoder/connector hw state with the
7688 * ->get_hw_state callbacks. */
7689 intel_connector_check_state(connector);
7690
7691 WARN(&connector->new_encoder->base != connector->base.encoder,
7692 "connector's staged encoder doesn't match current encoder\n");
7693 }
7694
7695 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7696 base.head) {
7697 bool enabled = false;
7698 bool active = false;
7699 enum pipe pipe, tracked_pipe;
7700
7701 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7702 encoder->base.base.id,
7703 drm_get_encoder_name(&encoder->base));
7704
7705 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7706 "encoder's stage crtc doesn't match current crtc\n");
7707 WARN(encoder->connectors_active && !encoder->base.crtc,
7708 "encoder's active_connectors set, but no crtc\n");
7709
7710 list_for_each_entry(connector, &dev->mode_config.connector_list,
7711 base.head) {
7712 if (connector->base.encoder != &encoder->base)
7713 continue;
7714 enabled = true;
7715 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7716 active = true;
7717 }
7718 WARN(!!encoder->base.crtc != enabled,
7719 "encoder's enabled state mismatch "
7720 "(expected %i, found %i)\n",
7721 !!encoder->base.crtc, enabled);
7722 WARN(active && !encoder->base.crtc,
7723 "active encoder with no crtc\n");
7724
7725 WARN(encoder->connectors_active != active,
7726 "encoder's computed active state doesn't match tracked active state "
7727 "(expected %i, found %i)\n", active, encoder->connectors_active);
7728
7729 active = encoder->get_hw_state(encoder, &pipe);
7730 WARN(active != encoder->connectors_active,
7731 "encoder's hw state doesn't match sw tracking "
7732 "(expected %i, found %i)\n",
7733 encoder->connectors_active, active);
7734
7735 if (!encoder->base.crtc)
7736 continue;
7737
7738 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7739 WARN(active && pipe != tracked_pipe,
7740 "active encoder's pipe doesn't match"
7741 "(expected %i, found %i)\n",
7742 tracked_pipe, pipe);
7743
7744 }
7745
7746 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7747 base.head) {
7748 bool enabled = false;
7749 bool active = false;
7750
7751 DRM_DEBUG_KMS("[CRTC:%d]\n",
7752 crtc->base.base.id);
7753
7754 WARN(crtc->active && !crtc->base.enabled,
7755 "active crtc, but not enabled in sw tracking\n");
7756
7757 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7758 base.head) {
7759 if (encoder->base.crtc != &crtc->base)
7760 continue;
7761 enabled = true;
7762 if (encoder->connectors_active)
7763 active = true;
7764 }
7765 WARN(active != crtc->active,
7766 "crtc's computed active state doesn't match tracked active state "
7767 "(expected %i, found %i)\n", active, crtc->active);
7768 WARN(enabled != crtc->base.enabled,
7769 "crtc's computed enabled state doesn't match tracked enabled state "
7770 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7771
7772 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7773 }
7774}
7775
c0c36b94
CW		 7776int intel_set_mode(struct drm_crtc *crtc,
7777 struct drm_display_mode *mode,
7778 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7779{
7780 struct drm_device *dev = crtc->dev;
dbf2b54e 7781 drm_i915_private_t *dev_priv = dev->dev_private;
3ac18232 7782 struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
25c5b266
DV		 7783 struct intel_crtc *intel_crtc;
7784 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7785 int ret = 0;
a6778b3c 7786
3ac18232 7787 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7788 if (!saved_mode)
7789 return -ENOMEM;
3ac18232 7790 saved_hwmode = saved_mode + 1;
a6778b3c 7791
e2e1ed41 7792 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7793 &prepare_pipes, &disable_pipes);
7794
7795 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7796 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7797
976f8a20
DV		 7798 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7799 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7800
3ac18232
TG		 7801 *saved_hwmode = crtc->hwmode;
7802 *saved_mode = crtc->mode;
a6778b3c 7803
25c5b266
DV		 7804 /* Hack: Because we don't (yet) support global modeset on multiple
7805 * crtcs, we don't keep track of the new mode for more than one crtc.
7806 * Hence simply check whether any bit is set in modeset_pipes in all the
7807 * pieces of code that are not yet converted to deal with mutliple crtcs
7808 * changing their mode at the same time. */
7809 adjusted_mode = NULL;
7810 if (modeset_pipes) {
7811 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7812 if (IS_ERR(adjusted_mode)) {
c0c36b94 7813 ret = PTR_ERR(adjusted_mode);
3ac18232 7814 goto out;
25c5b266 7815 }
25c5b266 7816 }
a6778b3c 7817
ea9d758d
DV		 7818 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7819 if (intel_crtc->base.enabled)
7820 dev_priv->display.crtc_disable(&intel_crtc->base);
7821 }
a6778b3c 7822
6c4c86f5
DV		 7823 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7824 * to set it here already despite that we pass it down the callchain.
f6e5b160 7825 */
6c4c86f5 7826 if (modeset_pipes)
25c5b266 7827 crtc->mode = *mode;
7758a113 7828
ea9d758d
DV		 7829 /* Only after disabling all output pipelines that will be changed can we
7830 * update the the output configuration. */
7831 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7832
47fab737
DV		 7833 if (dev_priv->display.modeset_global_resources)
7834 dev_priv->display.modeset_global_resources(dev);
7835
a6778b3c
DV		 7836 /* Set up the DPLL and any encoders state that needs to adjust or depend
7837 * on the DPLL.
f6e5b160 7838 */
25c5b266 7839 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94
CW		 7840 ret = intel_crtc_mode_set(&intel_crtc->base,
7841 mode, adjusted_mode,
7842 x, y, fb);
7843 if (ret)
7844 goto done;
a6778b3c
DV		 7845 }
7846
7847 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7848 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7849 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7850
25c5b266
DV		 7851 if (modeset_pipes) {
7852 /* Store real post-adjustment hardware mode. */
7853 crtc->hwmode = *adjusted_mode;
a6778b3c 7854
25c5b266
DV		 7855 /* Calculate and store various constants which
7856 * are later needed by vblank and swap-completion
7857 * timestamping. They are derived from true hwmode.
7858 */
7859 drm_calc_timestamping_constants(crtc);
7860 }
a6778b3c
DV		 7861
7862 /* FIXME: add subpixel order */
7863done:
7864 drm_mode_destroy(dev, adjusted_mode);
c0c36b94 7865 if (ret && crtc->enabled) {
3ac18232
TG		 7866 crtc->hwmode = *saved_hwmode;
7867 crtc->mode = *saved_mode;
8af6cf88
DV		 7868 } else {
7869 intel_modeset_check_state(dev);
a6778b3c
DV		 7870 }
7871
3ac18232
TG		 7872out:
7873 kfree(saved_mode);
a6778b3c 7874 return ret;
f6e5b160
CW		 7875}
7876
c0c36b94
CW		 7877void intel_crtc_restore_mode(struct drm_crtc *crtc)
7878{
7879 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7880}
7881
25c5b266
DV		 7882#undef for_each_intel_crtc_masked
7883
d9e55608
DV		 7884static void intel_set_config_free(struct intel_set_config *config)
7885{
7886 if (!config)
7887 return;
7888
1aa4b628
DV		 7889 kfree(config->save_connector_encoders);
7890 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7891 kfree(config);
7892}
7893
85f9eb71
DV		 7894static int intel_set_config_save_state(struct drm_device *dev,
7895 struct intel_set_config *config)
7896{
85f9eb71
DV		 7897 struct drm_encoder *encoder;
7898 struct drm_connector *connector;
7899 int count;
7900
1aa4b628
DV		 7901 config->save_encoder_crtcs =
7902 kcalloc(dev->mode_config.num_encoder,
7903 sizeof(struct drm_crtc *), GFP_KERNEL);
7904 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7905 return -ENOMEM;
7906
1aa4b628
DV		 7907 config->save_connector_encoders =
7908 kcalloc(dev->mode_config.num_connector,
7909 sizeof(struct drm_encoder *), GFP_KERNEL);
7910 if (!config->save_connector_encoders)
85f9eb71
DV		 7911 return -ENOMEM;
7912
7913 /* Copy data. Note that driver private data is not affected.
7914 * Should anything bad happen only the expected state is
7915 * restored, not the drivers personal bookkeeping.
7916 */
85f9eb71
DV		 7917 count = 0;
7918 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7919 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7920 }
7921
7922 count = 0;
7923 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7924 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7925 }
7926
7927 return 0;
7928}
7929
7930static void intel_set_config_restore_state(struct drm_device *dev,
7931 struct intel_set_config *config)
7932{
9a935856
DV		 7933 struct intel_encoder *encoder;
7934 struct intel_connector *connector;
85f9eb71
DV		 7935 int count;
7936
85f9eb71 7937 count = 0;
9a935856
DV		 7938 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7939 encoder->new_crtc =
7940 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7941 }
7942
7943 count = 0;
9a935856
DV		 7944 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7945 connector->new_encoder =
7946 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7947 }
7948}
7949
5e2b584e
DV		 7950static void
7951intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7952 struct intel_set_config *config)
7953{
7954
7955 /* We should be able to check here if the fb has the same properties
7956 * and then just flip_or_move it */
7957 if (set->crtc->fb != set->fb) {
7958 /* If we have no fb then treat it as a full mode set */
7959 if (set->crtc->fb == NULL) {
7960 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7961 config->mode_changed = true;
7962 } else if (set->fb == NULL) {
7963 config->mode_changed = true;
7964 } else if (set->fb->depth != set->crtc->fb->depth) {
7965 config->mode_changed = true;
7966 } else if (set->fb->bits_per_pixel !=
7967 set->crtc->fb->bits_per_pixel) {
7968 config->mode_changed = true;
7969 } else
7970 config->fb_changed = true;
7971 }
7972
835c5873 7973 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7974 config->fb_changed = true;
7975
7976 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7977 DRM_DEBUG_KMS("modes are different, full mode set\n");
7978 drm_mode_debug_printmodeline(&set->crtc->mode);
7979 drm_mode_debug_printmodeline(set->mode);
7980 config->mode_changed = true;
7981 }
7982}
7983
2e431051 7984static int
9a935856
DV		 7985intel_modeset_stage_output_state(struct drm_device *dev,
7986 struct drm_mode_set *set,
7987 struct intel_set_config *config)
50f56119 7988{
85f9eb71 7989 struct drm_crtc *new_crtc;
9a935856
DV		 7990 struct intel_connector *connector;
7991 struct intel_encoder *encoder;
2e431051 7992 int count, ro;
50f56119 7993
9abdda74 7994 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 7995 * of connectors. For paranoia, double-check this. */
7996 WARN_ON(!set->fb && (set->num_connectors != 0));
7997 WARN_ON(set->fb && (set->num_connectors == 0));
7998
50f56119 7999 count = 0;
9a935856
DV		 8000 list_for_each_entry(connector, &dev->mode_config.connector_list,
8001 base.head) {
8002 /* Otherwise traverse passed in connector list and get encoders
8003 * for them. */
50f56119 8004 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8005 if (set->connectors[ro] == &connector->base) {
8006 connector->new_encoder = connector->encoder;
50f56119
DV		 8007 break;
8008 }
8009 }
8010
9a935856
DV		 8011 /* If we disable the crtc, disable all its connectors. Also, if
8012 * the connector is on the changing crtc but not on the new
8013 * connector list, disable it. */
8014 if ((!set->fb || ro == set->num_connectors) &&
8015 connector->base.encoder &&
8016 connector->base.encoder->crtc == set->crtc) {
8017 connector->new_encoder = NULL;
8018
8019 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8020 connector->base.base.id,
8021 drm_get_connector_name(&connector->base));
8022 }
8023
8024
8025 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8026 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8027 config->mode_changed = true;
50f56119
DV		 8028 }
8029 }
9a935856 8030 /* connector->new_encoder is now updated for all connectors. */
50f56119 8031
9a935856 8032 /* Update crtc of enabled connectors. */
50f56119 8033 count = 0;
9a935856
DV		 8034 list_for_each_entry(connector, &dev->mode_config.connector_list,
8035 base.head) {
8036 if (!connector->new_encoder)
50f56119
DV		 8037 continue;
8038
9a935856 8039 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8040
8041 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8042 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8043 new_crtc = set->crtc;
8044 }
8045
8046 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8047 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8048 new_crtc)) {
5e2b584e 8049 return -EINVAL;
50f56119 8050 }
9a935856
DV		 8051 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8052
8053 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8054 connector->base.base.id,
8055 drm_get_connector_name(&connector->base),
8056 new_crtc->base.id);
8057 }
8058
8059 /* Check for any encoders that needs to be disabled. */
8060 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8061 base.head) {
8062 list_for_each_entry(connector,
8063 &dev->mode_config.connector_list,
8064 base.head) {
8065 if (connector->new_encoder == encoder) {
8066 WARN_ON(!connector->new_encoder->new_crtc);
8067
8068 goto next_encoder;
8069 }
8070 }
8071 encoder->new_crtc = NULL;
8072next_encoder:
8073 /* Only now check for crtc changes so we don't miss encoders
8074 * that will be disabled. */
8075 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8076 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8077 config->mode_changed = true;
50f56119
DV		 8078 }
8079 }
9a935856 8080 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8081
2e431051
DV		 8082 return 0;
8083}
8084
8085static int intel_crtc_set_config(struct drm_mode_set *set)
8086{
8087 struct drm_device *dev;
2e431051
DV		 8088 struct drm_mode_set save_set;
8089 struct intel_set_config *config;
8090 int ret;
2e431051 8091
8d3e375e
DV		 8092 BUG_ON(!set);
8093 BUG_ON(!set->crtc);
8094 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 8095
8096 if (!set->mode)
8097 set->fb = NULL;
8098
431e50f7
DV		 8099 /* The fb helper likes to play gross jokes with ->mode_set_config.
8100 * Unfortunately the crtc helper doesn't do much at all for this case,
8101 * so we have to cope with this madness until the fb helper is fixed up. */
8102 if (set->fb && set->num_connectors == 0)
8103 return 0;
8104
2e431051
DV		 8105 if (set->fb) {
8106 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8107 set->crtc->base.id, set->fb->base.id,
8108 (int)set->num_connectors, set->x, set->y);
8109 } else {
8110 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8111 }
8112
8113 dev = set->crtc->dev;
8114
8115 ret = -ENOMEM;
8116 config = kzalloc(sizeof(*config), GFP_KERNEL);
8117 if (!config)
8118 goto out_config;
8119
8120 ret = intel_set_config_save_state(dev, config);
8121 if (ret)
8122 goto out_config;
8123
8124 save_set.crtc = set->crtc;
8125 save_set.mode = &set->crtc->mode;
8126 save_set.x = set->crtc->x;
8127 save_set.y = set->crtc->y;
8128 save_set.fb = set->crtc->fb;
8129
8130 /* Compute whether we need a full modeset, only an fb base update or no
8131 * change at all. In the future we might also check whether only the
8132 * mode changed, e.g. for LVDS where we only change the panel fitter in
8133 * such cases. */
8134 intel_set_config_compute_mode_changes(set, config);
8135
9a935856 8136 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8137 if (ret)
8138 goto fail;
8139
5e2b584e 8140 if (config->mode_changed) {
87f1faa6 8141 if (set->mode) {
50f56119
DV		 8142 DRM_DEBUG_KMS("attempting to set mode from"
8143 " userspace\n");
8144 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8145 }
8146
c0c36b94
CW		 8147 ret = intel_set_mode(set->crtc, set->mode,
8148 set->x, set->y, set->fb);
8149 if (ret) {
8150 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8151 set->crtc->base.id, ret);
87f1faa6
DV		 8152 goto fail;
8153 }
5e2b584e 8154 } else if (config->fb_changed) {
4878cae2
VS		 8155 intel_crtc_wait_for_pending_flips(set->crtc);
8156
4f660f49 8157 ret = intel_pipe_set_base(set->crtc,
94352cf9 8158 set->x, set->y, set->fb);
50f56119
DV		 8159 }
8160
d9e55608
DV		 8161 intel_set_config_free(config);
8162
50f56119
DV		 8163 return 0;
8164
8165fail:
85f9eb71 8166 intel_set_config_restore_state(dev, config);
50f56119
DV		 8167
8168 /* Try to restore the config */
5e2b584e 8169 if (config->mode_changed &&
c0c36b94
CW		 8170 intel_set_mode(save_set.crtc, save_set.mode,
8171 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8172 DRM_ERROR("failed to restore config after modeset failure\n");
8173
d9e55608
DV		 8174out_config:
8175 intel_set_config_free(config);
50f56119
DV		 8176 return ret;
8177}
f6e5b160
CW		 8178
8179static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8180 .cursor_set = intel_crtc_cursor_set,
8181 .cursor_move = intel_crtc_cursor_move,
8182 .gamma_set = intel_crtc_gamma_set,
50f56119 8183 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8184 .destroy = intel_crtc_destroy,
8185 .page_flip = intel_crtc_page_flip,
8186};
8187
79f689aa
PZ		 8188static void intel_cpu_pll_init(struct drm_device *dev)
8189{
affa9354 8190 if (HAS_DDI(dev))
79f689aa
PZ		 8191 intel_ddi_pll_init(dev);
8192}
8193
ee7b9f93
JB		 8194static void intel_pch_pll_init(struct drm_device *dev)
8195{
8196 drm_i915_private_t *dev_priv = dev->dev_private;
8197 int i;
8198
8199 if (dev_priv->num_pch_pll == 0) {
8200 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8201 return;
8202 }
8203
8204 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8205 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8206 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8207 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8208 }
8209}
8210
b358d0a6 8211static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8212{
22fd0fab 8213 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8214 struct intel_crtc *intel_crtc;
8215 int i;
8216
8217 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8218 if (intel_crtc == NULL)
8219 return;
8220
8221 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8222
8223 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8224 for (i = 0; i < 256; i++) {
8225 intel_crtc->lut_r[i] = i;
8226 intel_crtc->lut_g[i] = i;
8227 intel_crtc->lut_b[i] = i;
8228 }
8229
80824003
JB		 8230 /* Swap pipes & planes for FBC on pre-965 */
8231 intel_crtc->pipe = pipe;
8232 intel_crtc->plane = pipe;
a5c961d1 8233 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8234 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8235 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8236 intel_crtc->plane = !pipe;
80824003
JB		 8237 }
8238
22fd0fab
JB		 8239 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8240 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8241 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8242 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8243
5a354204 8244 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8245
79e53945 8246 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8247}
8248
08d7b3d1 8249int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8250 struct drm_file *file)
08d7b3d1 8251{
08d7b3d1 8252 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8253 struct drm_mode_object *drmmode_obj;
8254 struct intel_crtc *crtc;
08d7b3d1 8255
1cff8f6b
DV		 8256 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8257 return -ENODEV;
08d7b3d1 8258
c05422d5
DV		 8259 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8260 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8261
c05422d5 8262 if (!drmmode_obj) {
08d7b3d1
CW		 8263 DRM_ERROR("no such CRTC id\n");
8264 return -EINVAL;
8265 }
8266
c05422d5
DV		 8267 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8268 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8269
c05422d5 8270 return 0;
08d7b3d1
CW		 8271}
8272
66a9278e 8273static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8274{
66a9278e
DV		 8275 struct drm_device *dev = encoder->base.dev;
8276 struct intel_encoder *source_encoder;
79e53945 8277 int index_mask = 0;
79e53945
JB		 8278 int entry = 0;
8279
66a9278e
DV		 8280 list_for_each_entry(source_encoder,
8281 &dev->mode_config.encoder_list, base.head) {
8282
8283 if (encoder == source_encoder)
79e53945 8284 index_mask |= (1 << entry);
66a9278e
DV		 8285
8286 /* Intel hw has only one MUX where enocoders could be cloned. */
8287 if (encoder->cloneable && source_encoder->cloneable)
8288 index_mask |= (1 << entry);
8289
79e53945
JB		 8290 entry++;
8291 }
4ef69c7a 8292
79e53945
JB		 8293 return index_mask;
8294}
8295
4d302442
CW		 8296static bool has_edp_a(struct drm_device *dev)
8297{
8298 struct drm_i915_private *dev_priv = dev->dev_private;
8299
8300 if (!IS_MOBILE(dev))
8301 return false;
8302
8303 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8304 return false;
8305
8306 if (IS_GEN5(dev) &&
8307 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8308 return false;
8309
8310 return true;
8311}
8312
79e53945
JB		 8313static void intel_setup_outputs(struct drm_device *dev)
8314{
725e30ad 8315 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8316 struct intel_encoder *encoder;
cb0953d7 8317 bool dpd_is_edp = false;
f3cfcba6 8318 bool has_lvds;
79e53945 8319
f3cfcba6 8320 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8321 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8322 /* disable the panel fitter on everything but LVDS */
8323 I915_WRITE(PFIT_CONTROL, 0);
8324 }
79e53945 8325
affa9354 8326 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8327 intel_crt_init(dev);
cb0953d7 8328
affa9354 8329 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8330 int found;
8331
8332 /* Haswell uses DDI functions to detect digital outputs */
8333 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8334 /* DDI A only supports eDP */
8335 if (found)
8336 intel_ddi_init(dev, PORT_A);
8337
8338 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8339 * register */
8340 found = I915_READ(SFUSE_STRAP);
8341
8342 if (found & SFUSE_STRAP_DDIB_DETECTED)
8343 intel_ddi_init(dev, PORT_B);
8344 if (found & SFUSE_STRAP_DDIC_DETECTED)
8345 intel_ddi_init(dev, PORT_C);
8346 if (found & SFUSE_STRAP_DDID_DETECTED)
8347 intel_ddi_init(dev, PORT_D);
8348 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8349 int found;
270b3042
DV		 8350 dpd_is_edp = intel_dpd_is_edp(dev);
8351
8352 if (has_edp_a(dev))
8353 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8354
e2debe91 8355 if (I915_READ(PCH_HDMIB) & PORT_DETECTED) {
461ed3ca 8356 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8357 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8358 if (!found)
e2debe91 8359 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8360 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8361 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8362 }
8363
e2debe91
PZ		 8364 if (I915_READ(PCH_HDMIC) & PORT_DETECTED)
8365 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8366
e2debe91
PZ		 8367 if (!dpd_is_edp && I915_READ(PCH_HDMID) & PORT_DETECTED)
8368 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8369
5eb08b69 8370 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8371 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8372
270b3042 8373 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8374 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8375 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8376 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8377 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8378 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8379
e2debe91
PZ		 8380 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & PORT_DETECTED) {
8381 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8382 PORT_B);
67cfc203
VS		 8383 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8384 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d
JB		 8385 }
8386
e2debe91
PZ		 8387 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & PORT_DETECTED)
8388 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
8389 PORT_C);
5eb08b69 8390
103a196f 8391 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8392 bool found = false;
7d57382e 8393
e2debe91 8394 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8395 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8396 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8397 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8398 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8399 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8400 }
27185ae1 8401
b01f2c3a
JB		 8402 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8403 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8404 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8405 }
725e30ad 8406 }
13520b05
KH		 8407
8408 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8409
e2debe91 8410 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8411 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8412 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8413 }
27185ae1 8414
e2debe91 8415 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8416
b01f2c3a
JB		 8417 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8418 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8419 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8420 }
8421 if (SUPPORTS_INTEGRATED_DP(dev)) {
8422 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8423 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8424 }
725e30ad 8425 }
27185ae1 8426
b01f2c3a
JB		 8427 if (SUPPORTS_INTEGRATED_DP(dev) &&
8428 (I915_READ(DP_D) & DP_DETECTED)) {
8429 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8430 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8431 }
bad720ff 8432 } else if (IS_GEN2(dev))
79e53945
JB		 8433 intel_dvo_init(dev);
8434
103a196f 8435 if (SUPPORTS_TV(dev))
79e53945
JB		 8436 intel_tv_init(dev);
8437
4ef69c7a
CW		 8438 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8439 encoder->base.possible_crtcs = encoder->crtc_mask;
8440 encoder->base.possible_clones =
66a9278e 8441 intel_encoder_clones(encoder);
79e53945 8442 }
47356eb6 8443
dde86e2d 8444 intel_init_pch_refclk(dev);
270b3042
DV		 8445
8446 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8447}
8448
8449static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8450{
8451 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8452
8453 drm_framebuffer_cleanup(fb);
05394f39 8454 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8455
8456 kfree(intel_fb);
8457}
8458
8459static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8460 struct drm_file *file,
79e53945
JB		 8461 unsigned int *handle)
8462{
8463 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8464 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8465
05394f39 8466 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8467}
8468
8469static const struct drm_framebuffer_funcs intel_fb_funcs = {
8470 .destroy = intel_user_framebuffer_destroy,
8471 .create_handle = intel_user_framebuffer_create_handle,
8472};
8473
38651674
DA		 8474int intel_framebuffer_init(struct drm_device *dev,
8475 struct intel_framebuffer *intel_fb,
308e5bcb 8476 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8477 struct drm_i915_gem_object *obj)
79e53945 8478{
79e53945
JB		 8479 int ret;
8480
c16ed4be
CW		 8481 if (obj->tiling_mode == I915_TILING_Y) {
8482 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8483 return -EINVAL;
c16ed4be 8484 }
57cd6508 8485
c16ed4be
CW		 8486 if (mode_cmd->pitches[0] & 63) {
8487 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8488 mode_cmd->pitches[0]);
57cd6508 8489 return -EINVAL;
c16ed4be 8490 }
57cd6508 8491
5d7bd705 8492 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8493 if (mode_cmd->pitches[0] > 32768) {
8494 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8495 mode_cmd->pitches[0]);
5d7bd705 8496 return -EINVAL;
c16ed4be 8497 }
5d7bd705
VS		 8498
8499 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8500 mode_cmd->pitches[0] != obj->stride) {
8501 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8502 mode_cmd->pitches[0], obj->stride);
5d7bd705 8503 return -EINVAL;
c16ed4be 8504 }
5d7bd705 8505
57779d06 8506 /* Reject formats not supported by any plane early. */
308e5bcb 8507 switch (mode_cmd->pixel_format) {
57779d06 8508 case DRM_FORMAT_C8:
04b3924d
VS		 8509 case DRM_FORMAT_RGB565:
8510 case DRM_FORMAT_XRGB8888:
8511 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8512 break;
8513 case DRM_FORMAT_XRGB1555:
8514 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8515 if (INTEL_INFO(dev)->gen > 3) {
8516 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8517 return -EINVAL;
c16ed4be 8518 }
57779d06
VS		 8519 break;
8520 case DRM_FORMAT_XBGR8888:
8521 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8522 case DRM_FORMAT_XRGB2101010:
8523 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8524 case DRM_FORMAT_XBGR2101010:
8525 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8526 if (INTEL_INFO(dev)->gen < 4) {
8527 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8528 return -EINVAL;
c16ed4be 8529 }
b5626747 8530 break;
04b3924d
VS		 8531 case DRM_FORMAT_YUYV:
8532 case DRM_FORMAT_UYVY:
8533 case DRM_FORMAT_YVYU:
8534 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8535 if (INTEL_INFO(dev)->gen < 5) {
8536 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8537 return -EINVAL;
c16ed4be 8538 }
57cd6508
CW		 8539 break;
8540 default:
c16ed4be 8541 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8542 return -EINVAL;
8543 }
8544
90f9a336
VS		 8545 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8546 if (mode_cmd->offsets[0] != 0)
8547 return -EINVAL;
8548
c7d73f6a
DV		 8549 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8550 intel_fb->obj = obj;
8551
79e53945
JB		 8552 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8553 if (ret) {
8554 DRM_ERROR("framebuffer init failed %d\n", ret);
8555 return ret;
8556 }
8557
79e53945
JB		 8558 return 0;
8559}
8560
79e53945
JB		 8561static struct drm_framebuffer *
8562intel_user_framebuffer_create(struct drm_device *dev,
8563 struct drm_file *filp,
308e5bcb 8564 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8565{
05394f39 8566 struct drm_i915_gem_object *obj;
79e53945 8567
308e5bcb
JB		 8568 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8569 mode_cmd->handles[0]));
c8725226 8570 if (&obj->base == NULL)
cce13ff7 8571 return ERR_PTR(-ENOENT);
79e53945 8572
d2dff872 8573 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8574}
8575
79e53945 8576static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8577 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8578 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8579};
8580
e70236a8
JB		 8581/* Set up chip specific display functions */
8582static void intel_init_display(struct drm_device *dev)
8583{
8584 struct drm_i915_private *dev_priv = dev->dev_private;
8585
8586 /* We always want a DPMS function */
affa9354 8587 if (HAS_DDI(dev)) {
09b4ddf9 8588 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8589 dev_priv->display.crtc_enable = haswell_crtc_enable;
8590 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8591 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8592 dev_priv->display.update_plane = ironlake_update_plane;
8593 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8594 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8595 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8596 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8597 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8598 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8599 } else {
f564048e 8600 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8601 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8602 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8603 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8604 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8605 }
e70236a8 8606
e70236a8 8607 /* Returns the core display clock speed */
25eb05fc
JB		 8608 if (IS_VALLEYVIEW(dev))
8609 dev_priv->display.get_display_clock_speed =
8610 valleyview_get_display_clock_speed;
8611 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8612 dev_priv->display.get_display_clock_speed =
8613 i945_get_display_clock_speed;
8614 else if (IS_I915G(dev))
8615 dev_priv->display.get_display_clock_speed =
8616 i915_get_display_clock_speed;
f2b115e6 8617 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8618 dev_priv->display.get_display_clock_speed =
8619 i9xx_misc_get_display_clock_speed;
8620 else if (IS_I915GM(dev))
8621 dev_priv->display.get_display_clock_speed =
8622 i915gm_get_display_clock_speed;
8623 else if (IS_I865G(dev))
8624 dev_priv->display.get_display_clock_speed =
8625 i865_get_display_clock_speed;
f0f8a9ce 8626 else if (IS_I85X(dev))
e70236a8
JB		 8627 dev_priv->display.get_display_clock_speed =
8628 i855_get_display_clock_speed;
8629 else /* 852, 830 */
8630 dev_priv->display.get_display_clock_speed =
8631 i830_get_display_clock_speed;
8632
7f8a8569 8633 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8634 if (IS_GEN5(dev)) {
674cf967 8635 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8636 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8637 } else if (IS_GEN6(dev)) {
674cf967 8638 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8639 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8640 } else if (IS_IVYBRIDGE(dev)) {
8641 /* FIXME: detect B0+ stepping and use auto training */
8642 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8643 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8644 dev_priv->display.modeset_global_resources =
8645 ivb_modeset_global_resources;
c82e4d26
ED		 8646 } else if (IS_HASWELL(dev)) {
8647 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8648 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8649 dev_priv->display.modeset_global_resources =
8650 haswell_modeset_global_resources;
a0e63c22 8651 }
6067aaea 8652 } else if (IS_G4X(dev)) {
e0dac65e 8653 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8654 }
8c9f3aaf
JB		 8655
8656 /* Default just returns -ENODEV to indicate unsupported */
8657 dev_priv->display.queue_flip = intel_default_queue_flip;
8658
8659 switch (INTEL_INFO(dev)->gen) {
8660 case 2:
8661 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8662 break;
8663
8664 case 3:
8665 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8666 break;
8667
8668 case 4:
8669 case 5:
8670 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8671 break;
8672
8673 case 6:
8674 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8675 break;
7c9017e5
JB		 8676 case 7:
8677 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8678 break;
8c9f3aaf 8679 }
e70236a8
JB		 8680}
8681
b690e96c
JB		 8682/*
8683 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8684 * resume, or other times. This quirk makes sure that's the case for
8685 * affected systems.
8686 */
0206e353 8687static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8688{
8689 struct drm_i915_private *dev_priv = dev->dev_private;
8690
8691 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8692 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8693}
8694
435793df
KP		 8695/*
8696 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8697 */
8698static void quirk_ssc_force_disable(struct drm_device *dev)
8699{
8700 struct drm_i915_private *dev_priv = dev->dev_private;
8701 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8702 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8703}
8704
4dca20ef 8705/*
5a15ab5b
CE		 8706 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8707 * brightness value
4dca20ef
CE		 8708 */
8709static void quirk_invert_brightness(struct drm_device *dev)
8710{
8711 struct drm_i915_private *dev_priv = dev->dev_private;
8712 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8713 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8714}
8715
b690e96c
JB		 8716struct intel_quirk {
8717 int device;
8718 int subsystem_vendor;
8719 int subsystem_device;
8720 void (*hook)(struct drm_device *dev);
8721};
8722
5f85f176
EE		 8723/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8724struct intel_dmi_quirk {
8725 void (*hook)(struct drm_device *dev);
8726 const struct dmi_system_id (*dmi_id_list)[];
8727};
8728
8729static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8730{
8731 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8732 return 1;
8733}
8734
8735static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8736 {
8737 .dmi_id_list = &(const struct dmi_system_id[]) {
8738 {
8739 .callback = intel_dmi_reverse_brightness,
8740 .ident = "NCR Corporation",
8741 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8742 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8743 },
8744 },
8745 { } /* terminating entry */
8746 },
8747 .hook = quirk_invert_brightness,
8748 },
8749};
8750
c43b5634 8751static struct intel_quirk intel_quirks[] = {
b690e96c 8752 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8753 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8754
b690e96c
JB		 8755 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8756 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8757
b690e96c
JB		 8758 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8759 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8760
ccd0d36e 8761 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8762 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8763 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8764
8765 /* Lenovo U160 cannot use SSC on LVDS */
8766 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8767
8768 /* Sony Vaio Y cannot use SSC on LVDS */
8769 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8770
8771 /* Acer Aspire 5734Z must invert backlight brightness */
8772 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8773
8774 /* Acer/eMachines G725 */
8775 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8776
8777 /* Acer/eMachines e725 */
8778 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8779
8780 /* Acer/Packard Bell NCL20 */
8781 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 8782
8783 /* Acer Aspire 4736Z */
8784 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 8785};
8786
8787static void intel_init_quirks(struct drm_device *dev)
8788{
8789 struct pci_dev *d = dev->pdev;
8790 int i;
8791
8792 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8793 struct intel_quirk *q = &intel_quirks[i];
8794
8795 if (d->device == q->device &&
8796 (d->subsystem_vendor == q->subsystem_vendor ||
8797 q->subsystem_vendor == PCI_ANY_ID) &&
8798 (d->subsystem_device == q->subsystem_device ||
8799 q->subsystem_device == PCI_ANY_ID))
8800 q->hook(dev);
8801 }
5f85f176
EE		 8802 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8803 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8804 intel_dmi_quirks[i].hook(dev);
8805 }
b690e96c
JB		 8806}
8807
9cce37f4
JB		 8808/* Disable the VGA plane that we never use */
8809static void i915_disable_vga(struct drm_device *dev)
8810{
8811 struct drm_i915_private *dev_priv = dev->dev_private;
8812 u8 sr1;
766aa1c4 8813 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 8814
8815 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8816 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8817 sr1 = inb(VGA_SR_DATA);
8818 outb(sr1 | 1<<5, VGA_SR_DATA);
8819 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8820 udelay(300);
8821
8822 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8823 POSTING_READ(vga_reg);
8824}
8825
f817586c
DV		 8826void intel_modeset_init_hw(struct drm_device *dev)
8827{
fa42e23c 8828 intel_init_power_well(dev);
0232e927 8829
a8f78b58
ED		 8830 intel_prepare_ddi(dev);
8831
f817586c
DV		 8832 intel_init_clock_gating(dev);
8833
79f5b2c7 8834 mutex_lock(&dev->struct_mutex);
8090c6b9 8835 intel_enable_gt_powersave(dev);
79f5b2c7 8836 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8837}
8838
79e53945
JB		 8839void intel_modeset_init(struct drm_device *dev)
8840{
652c393a 8841 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8842 int i, ret;
79e53945
JB		 8843
8844 drm_mode_config_init(dev);
8845
8846 dev->mode_config.min_width = 0;
8847 dev->mode_config.min_height = 0;
8848
019d96cb
DA		 8849 dev->mode_config.preferred_depth = 24;
8850 dev->mode_config.prefer_shadow = 1;
8851
e6ecefaa 8852 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8853
b690e96c
JB		 8854 intel_init_quirks(dev);
8855
1fa61106
ED		 8856 intel_init_pm(dev);
8857
e70236a8
JB		 8858 intel_init_display(dev);
8859
a6c45cf0
CW		 8860 if (IS_GEN2(dev)) {
8861 dev->mode_config.max_width = 2048;
8862 dev->mode_config.max_height = 2048;
8863 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8864 dev->mode_config.max_width = 4096;
8865 dev->mode_config.max_height = 4096;
79e53945 8866 } else {
a6c45cf0
CW		 8867 dev->mode_config.max_width = 8192;
8868 dev->mode_config.max_height = 8192;
79e53945 8869 }
5d4545ae 8870 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 8871
28c97730 8872 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8873 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8874
a3524f1b 8875 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8876 intel_crtc_init(dev, i);
00c2064b
JB		 8877 ret = intel_plane_init(dev, i);
8878 if (ret)
8879 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8880 }
8881
79f689aa 8882 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8883 intel_pch_pll_init(dev);
8884
9cce37f4
JB		 8885 /* Just disable it once at startup */
8886 i915_disable_vga(dev);
79e53945 8887 intel_setup_outputs(dev);
11be49eb
CW		 8888
8889 /* Just in case the BIOS is doing something questionable. */
8890 intel_disable_fbc(dev);
2c7111db
CW		 8891}
8892
24929352
DV		 8893static void
8894intel_connector_break_all_links(struct intel_connector *connector)
8895{
8896 connector->base.dpms = DRM_MODE_DPMS_OFF;
8897 connector->base.encoder = NULL;
8898 connector->encoder->connectors_active = false;
8899 connector->encoder->base.crtc = NULL;
8900}
8901
7fad798e
DV		 8902static void intel_enable_pipe_a(struct drm_device *dev)
8903{
8904 struct intel_connector *connector;
8905 struct drm_connector *crt = NULL;
8906 struct intel_load_detect_pipe load_detect_temp;
8907
8908 /* We can't just switch on the pipe A, we need to set things up with a
8909 * proper mode and output configuration. As a gross hack, enable pipe A
8910 * by enabling the load detect pipe once. */
8911 list_for_each_entry(connector,
8912 &dev->mode_config.connector_list,
8913 base.head) {
8914 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8915 crt = &connector->base;
8916 break;
8917 }
8918 }
8919
8920 if (!crt)
8921 return;
8922
8923 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8924 intel_release_load_detect_pipe(crt, &load_detect_temp);
8925
652c393a 8926
7fad798e
DV		 8927}
8928
fa555837
DV		 8929static bool
8930intel_check_plane_mapping(struct intel_crtc *crtc)
8931{
8932 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8933 u32 reg, val;
8934
8935 if (dev_priv->num_pipe == 1)
8936 return true;
8937
8938 reg = DSPCNTR(!crtc->plane);
8939 val = I915_READ(reg);
8940
8941 if ((val & DISPLAY_PLANE_ENABLE) &&
8942 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8943 return false;
8944
8945 return true;
8946}
8947
24929352
DV		 8948static void intel_sanitize_crtc(struct intel_crtc *crtc)
8949{
8950 struct drm_device *dev = crtc->base.dev;
8951 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8952 u32 reg;
24929352 8953
24929352 8954 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8955 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8956 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8957
8958 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8959 * disable the crtc (and hence change the state) if it is wrong. Note
8960 * that gen4+ has a fixed plane -> pipe mapping. */
8961 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8962 struct intel_connector *connector;
8963 bool plane;
8964
24929352
DV		 8965 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8966 crtc->base.base.id);
8967
8968 /* Pipe has the wrong plane attached and the plane is active.
8969 * Temporarily change the plane mapping and disable everything
8970 * ... */
8971 plane = crtc->plane;
8972 crtc->plane = !plane;
8973 dev_priv->display.crtc_disable(&crtc->base);
8974 crtc->plane = plane;
8975
8976 /* ... and break all links. */
8977 list_for_each_entry(connector, &dev->mode_config.connector_list,
8978 base.head) {
8979 if (connector->encoder->base.crtc != &crtc->base)
8980 continue;
8981
8982 intel_connector_break_all_links(connector);
8983 }
8984
8985 WARN_ON(crtc->active);
8986 crtc->base.enabled = false;
8987 }
24929352 8988
7fad798e
DV		 8989 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8990 crtc->pipe == PIPE_A && !crtc->active) {
8991 /* BIOS forgot to enable pipe A, this mostly happens after
8992 * resume. Force-enable the pipe to fix this, the update_dpms
8993 * call below we restore the pipe to the right state, but leave
8994 * the required bits on. */
8995 intel_enable_pipe_a(dev);
8996 }
8997
24929352
DV		 8998 /* Adjust the state of the output pipe according to whether we
8999 * have active connectors/encoders. */
9000 intel_crtc_update_dpms(&crtc->base);
9001
9002 if (crtc->active != crtc->base.enabled) {
9003 struct intel_encoder *encoder;
9004
9005 /* This can happen either due to bugs in the get_hw_state
9006 * functions or because the pipe is force-enabled due to the
9007 * pipe A quirk. */
9008 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9009 crtc->base.base.id,
9010 crtc->base.enabled ? "enabled" : "disabled",
9011 crtc->active ? "enabled" : "disabled");
9012
9013 crtc->base.enabled = crtc->active;
9014
9015 /* Because we only establish the connector -> encoder ->
9016 * crtc links if something is active, this means the
9017 * crtc is now deactivated. Break the links. connector
9018 * -> encoder links are only establish when things are
9019 * actually up, hence no need to break them. */
9020 WARN_ON(crtc->active);
9021
9022 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9023 WARN_ON(encoder->connectors_active);
9024 encoder->base.crtc = NULL;
9025 }
9026 }
9027}
9028
9029static void intel_sanitize_encoder(struct intel_encoder *encoder)
9030{
9031 struct intel_connector *connector;
9032 struct drm_device *dev = encoder->base.dev;
9033
9034 /* We need to check both for a crtc link (meaning that the
9035 * encoder is active and trying to read from a pipe) and the
9036 * pipe itself being active. */
9037 bool has_active_crtc = encoder->base.crtc &&
9038 to_intel_crtc(encoder->base.crtc)->active;
9039
9040 if (encoder->connectors_active && !has_active_crtc) {
9041 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9042 encoder->base.base.id,
9043 drm_get_encoder_name(&encoder->base));
9044
9045 /* Connector is active, but has no active pipe. This is
9046 * fallout from our resume register restoring. Disable
9047 * the encoder manually again. */
9048 if (encoder->base.crtc) {
9049 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9050 encoder->base.base.id,
9051 drm_get_encoder_name(&encoder->base));
9052 encoder->disable(encoder);
9053 }
9054
9055 /* Inconsistent output/port/pipe state happens presumably due to
9056 * a bug in one of the get_hw_state functions. Or someplace else
9057 * in our code, like the register restore mess on resume. Clamp
9058 * things to off as a safer default. */
9059 list_for_each_entry(connector,
9060 &dev->mode_config.connector_list,
9061 base.head) {
9062 if (connector->encoder != encoder)
9063 continue;
9064
9065 intel_connector_break_all_links(connector);
9066 }
9067 }
9068 /* Enabled encoders without active connectors will be fixed in
9069 * the crtc fixup. */
9070}
9071
44cec740 9072void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9073{
9074 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9075 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9076
9077 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9078 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9079 i915_disable_vga(dev);
0fde901f
KM		 9080 }
9081}
9082
24929352
DV		 9083/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9084 * and i915 state tracking structures. */
45e2b5f6
DV		 9085void intel_modeset_setup_hw_state(struct drm_device *dev,
9086 bool force_restore)
24929352
DV		 9087{
9088 struct drm_i915_private *dev_priv = dev->dev_private;
9089 enum pipe pipe;
9090 u32 tmp;
9091 struct intel_crtc *crtc;
9092 struct intel_encoder *encoder;
9093 struct intel_connector *connector;
9094
affa9354 9095 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9096 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9097
9098 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9099 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9100 case TRANS_DDI_EDP_INPUT_A_ON:
9101 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9102 pipe = PIPE_A;
9103 break;
9104 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9105 pipe = PIPE_B;
9106 break;
9107 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9108 pipe = PIPE_C;
9109 break;
9110 }
9111
9112 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9113 crtc->cpu_transcoder = TRANSCODER_EDP;
9114
9115 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9116 pipe_name(pipe));
9117 }
9118 }
9119
24929352
DV		 9120 for_each_pipe(pipe) {
9121 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9122
702e7a56 9123 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9124 if (tmp & PIPECONF_ENABLE)
9125 crtc->active = true;
9126 else
9127 crtc->active = false;
9128
9129 crtc->base.enabled = crtc->active;
9130
9131 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9132 crtc->base.base.id,
9133 crtc->active ? "enabled" : "disabled");
9134 }
9135
affa9354 9136 if (HAS_DDI(dev))
6441ab5f
PZ		 9137 intel_ddi_setup_hw_pll_state(dev);
9138
24929352
DV		 9139 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9140 base.head) {
9141 pipe = 0;
9142
9143 if (encoder->get_hw_state(encoder, &pipe)) {
9144 encoder->base.crtc =
9145 dev_priv->pipe_to_crtc_mapping[pipe];
9146 } else {
9147 encoder->base.crtc = NULL;
9148 }
9149
9150 encoder->connectors_active = false;
9151 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9152 encoder->base.base.id,
9153 drm_get_encoder_name(&encoder->base),
9154 encoder->base.crtc ? "enabled" : "disabled",
9155 pipe);
9156 }
9157
9158 list_for_each_entry(connector, &dev->mode_config.connector_list,
9159 base.head) {
9160 if (connector->get_hw_state(connector)) {
9161 connector->base.dpms = DRM_MODE_DPMS_ON;
9162 connector->encoder->connectors_active = true;
9163 connector->base.encoder = &connector->encoder->base;
9164 } else {
9165 connector->base.dpms = DRM_MODE_DPMS_OFF;
9166 connector->base.encoder = NULL;
9167 }
9168 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9169 connector->base.base.id,
9170 drm_get_connector_name(&connector->base),
9171 connector->base.encoder ? "enabled" : "disabled");
9172 }
9173
9174 /* HW state is read out, now we need to sanitize this mess. */
9175 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9176 base.head) {
9177 intel_sanitize_encoder(encoder);
9178 }
9179
9180 for_each_pipe(pipe) {
9181 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9182 intel_sanitize_crtc(crtc);
9183 }
9a935856 9184
45e2b5f6
DV		 9185 if (force_restore) {
9186 for_each_pipe(pipe) {
c0c36b94 9187 intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
45e2b5f6 9188 }
0fde901f
KM		 9189
9190 i915_redisable_vga(dev);
45e2b5f6
DV		 9191 } else {
9192 intel_modeset_update_staged_output_state(dev);
9193 }
8af6cf88
DV		 9194
9195 intel_modeset_check_state(dev);
2e938892
DV		 9196
9197 drm_mode_config_reset(dev);
2c7111db
CW		 9198}
9199
9200void intel_modeset_gem_init(struct drm_device *dev)
9201{
1833b134 9202 intel_modeset_init_hw(dev);
02e792fb
DV		 9203
9204 intel_setup_overlay(dev);
24929352 9205
45e2b5f6 9206 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9207}
9208
9209void intel_modeset_cleanup(struct drm_device *dev)
9210{
652c393a
JB		 9211 struct drm_i915_private *dev_priv = dev->dev_private;
9212 struct drm_crtc *crtc;
9213 struct intel_crtc *intel_crtc;
9214
f87ea761 9215 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9216 mutex_lock(&dev->struct_mutex);
9217
723bfd70
JB		 9218 intel_unregister_dsm_handler();
9219
9220
652c393a
JB		 9221 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9222 /* Skip inactive CRTCs */
9223 if (!crtc->fb)
9224 continue;
9225
9226 intel_crtc = to_intel_crtc(crtc);
3dec0095 9227 intel_increase_pllclock(crtc);
652c393a
JB		 9228 }
9229
973d04f9 9230 intel_disable_fbc(dev);
e70236a8 9231
8090c6b9 9232 intel_disable_gt_powersave(dev);
0cdab21f 9233
930ebb46
DV		 9234 ironlake_teardown_rc6(dev);
9235
57f350b6
JB		 9236 if (IS_VALLEYVIEW(dev))
9237 vlv_init_dpio(dev);
9238
69341a5e
KH		 9239 mutex_unlock(&dev->struct_mutex);
9240
6c0d9350
DV		 9241 /* Disable the irq before mode object teardown, for the irq might
9242 * enqueue unpin/hotplug work. */
9243 drm_irq_uninstall(dev);
9244 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9245 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9246
1630fe75
CW		 9247 /* flush any delayed tasks or pending work */
9248 flush_scheduled_work();
9249
79e53945 9250 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9251
9252 intel_cleanup_overlay(dev);
79e53945
JB		 9253}
9254
f1c79df3
ZW		 9255/*
9256 * Return which encoder is currently attached for connector.
9257 */
df0e9248 9258struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9259{
df0e9248
CW		 9260 return &intel_attached_encoder(connector)->base;
9261}
f1c79df3 9262
df0e9248
CW		 9263void intel_connector_attach_encoder(struct intel_connector *connector,
9264 struct intel_encoder *encoder)
9265{
9266 connector->encoder = encoder;
9267 drm_mode_connector_attach_encoder(&connector->base,
9268 &encoder->base);
79e53945 9269}
28d52043
DA		 9270
9271/*
9272 * set vga decode state - true == enable VGA decode
9273 */
9274int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9275{
9276 struct drm_i915_private *dev_priv = dev->dev_private;
9277 u16 gmch_ctrl;
9278
9279 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9280 if (state)
9281 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9282 else
9283 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9284 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9285 return 0;
9286}
c4a1d9e4
CW		 9287
9288#ifdef CONFIG_DEBUG_FS
9289#include <linux/seq_file.h>
9290
9291struct intel_display_error_state {
9292 struct intel_cursor_error_state {
9293 u32 control;
9294 u32 position;
9295 u32 base;
9296 u32 size;
52331309 9297 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9298
9299 struct intel_pipe_error_state {
9300 u32 conf;
9301 u32 source;
9302
9303 u32 htotal;
9304 u32 hblank;
9305 u32 hsync;
9306 u32 vtotal;
9307 u32 vblank;
9308 u32 vsync;
52331309 9309 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9310
9311 struct intel_plane_error_state {
9312 u32 control;
9313 u32 stride;
9314 u32 size;
9315 u32 pos;
9316 u32 addr;
9317 u32 surface;
9318 u32 tile_offset;
52331309 9319 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9320};
9321
9322struct intel_display_error_state *
9323intel_display_capture_error_state(struct drm_device *dev)
9324{
0206e353 9325 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9326 struct intel_display_error_state *error;
702e7a56 9327 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9328 int i;
9329
9330 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9331 if (error == NULL)
9332 return NULL;
9333
52331309 9334 for_each_pipe(i) {
702e7a56
PZ		 9335 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9336
c4a1d9e4
CW		 9337 error->cursor[i].control = I915_READ(CURCNTR(i));
9338 error->cursor[i].position = I915_READ(CURPOS(i));
9339 error->cursor[i].base = I915_READ(CURBASE(i));
9340
9341 error->plane[i].control = I915_READ(DSPCNTR(i));
9342 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9343 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9344 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9345 error->plane[i].addr = I915_READ(DSPADDR(i));
9346 if (INTEL_INFO(dev)->gen >= 4) {
9347 error->plane[i].surface = I915_READ(DSPSURF(i));
9348 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9349 }
9350
702e7a56 9351 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9352 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9353 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9354 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9355 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9356 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9357 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9358 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9359 }
9360
9361 return error;
9362}
9363
9364void
9365intel_display_print_error_state(struct seq_file *m,
9366 struct drm_device *dev,
9367 struct intel_display_error_state *error)
9368{
52331309 9369 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9370 int i;
9371
52331309
DL		 9372 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9373 for_each_pipe(i) {
c4a1d9e4
CW		 9374 seq_printf(m, "Pipe [%d]:\n", i);
9375 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9376 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9377 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9378 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9379 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9380 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9381 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9382 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9383
9384 seq_printf(m, "Plane [%d]:\n", i);
9385 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9386 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9387 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9388 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9389 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9390 if (INTEL_INFO(dev)->gen >= 4) {
9391 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9392 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9393 }
9394
9395 seq_printf(m, "Cursor [%d]:\n", i);
9396 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9397 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9398 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9399 }
9400}
9401#endif
Linux kernel - Deliverables
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