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drm/i915: return actual brightness to .get_brightness callback
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
f4808ab8
VS		 74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
d4906093 92};
79e53945 93
2377b741
JB		 94/* FDI */
95#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
d2acd215
DV		 97int
98intel_pch_rawclk(struct drm_device *dev)
99{
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105}
106
d4906093
ML		 107static bool
108intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
d4906093
ML		 111static bool
112intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
79e53945 115
a4fc5ed6
KP		 116static bool
117intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
5eb08b69 120static bool
f2b115e6 121intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
a4fc5ed6 124
a0c4da24
JB		 125static bool
126intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
021357ac
CW		 130static inline u32 /* units of 100MHz */
131intel_fdi_link_freq(struct drm_device *dev)
132{
8b99e68c
CW		 133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
021357ac
CW		 138}
139
e4b36699 140static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699 166};
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
d4906093 193 .find_pll = intel_find_best_PLL,
e4b36699
KP		 194};
195
273e27ca 196
e4b36699 197static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
d4906093 224 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 225};
226
227static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
044c7c41 238 },
d4906093 239 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
044c7c41 253 },
d4906093 254 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 255};
256
257static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
273e27ca 267 .p2_slow = 10, .p2_fast = 10 },
0206e353 268 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 274 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
273e27ca 277 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
f2b115e6 287static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
6115707b 298 .find_pll = intel_find_best_PLL,
e4b36699
KP		 299};
300
273e27ca
EA		 301/* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
4547668a 317 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 318};
319
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
273e27ca 348/* LVDS 100mhz refclk limits. */
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
0206e353 357 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
0206e353 371 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 374 .find_pll = intel_g4x_find_best_PLL,
375};
376
377static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
273e27ca 387 .p2_slow = 10, .p2_fast = 10 },
0206e353 388 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 389};
390
a0c4da24
JB		 391static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
17dc9257 407 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
419static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 422 .n = { .min = 1, .max = 7 },
74a4dd2e 423 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431};
432
57f350b6
JB		 433u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434{
09153000 435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 436
57f350b6
JB		 437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
09153000 439 return 0;
57f350b6
JB		 440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
09153000 447 return 0;
57f350b6 448 }
57f350b6 449
09153000 450 return I915_READ(DPIO_DATA);
57f350b6
JB		 451}
452
a0c4da24
JB		 453static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455{
09153000 456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 457
a0c4da24
JB		 458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
09153000 460 return;
a0c4da24
JB		 461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 469}
470
57f350b6
JB		 471static void vlv_init_dpio(struct drm_device *dev)
472{
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480}
481
1b894b59
CW		 482static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk)
2c07245f 484{
b91ad0ec 485 struct drm_device *dev = crtc->dev;
2c07245f 486 const intel_limit_t *limit;
b91ad0ec
ZW		 487
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 489 if (intel_is_dual_link_lvds(dev)) {
1b894b59 490 if (refclk == 100000)
b91ad0ec
ZW		 491 limit = &intel_limits_ironlake_dual_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_dual_lvds;
494 } else {
1b894b59 495 if (refclk == 100000)
b91ad0ec
ZW		 496 limit = &intel_limits_ironlake_single_lvds_100m;
497 else
498 limit = &intel_limits_ironlake_single_lvds;
499 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 502 limit = &intel_limits_ironlake_display_port;
2c07245f 503 else
b91ad0ec 504 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 505
506 return limit;
507}
508
044c7c41
ML		 509static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
510{
511 struct drm_device *dev = crtc->dev;
044c7c41
ML		 512 const intel_limit_t *limit;
513
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 515 if (intel_is_dual_link_lvds(dev))
e4b36699 516 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 517 else
e4b36699 518 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 521 limit = &intel_limits_g4x_hdmi;
044c7c41 522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 523 limit = &intel_limits_g4x_sdvo;
0206e353 524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 525 limit = &intel_limits_g4x_display_port;
044c7c41 526 } else /* The option is for other outputs */
e4b36699 527 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 528
529 return limit;
530}
531
1b894b59 532static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 533{
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
bad720ff 537 if (HAS_PCH_SPLIT(dev))
1b894b59 538 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 539 else if (IS_G4X(dev)) {
044c7c41 540 limit = intel_g4x_limit(crtc);
f2b115e6 541 } else if (IS_PINEVIEW(dev)) {
2177832f 542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 543 limit = &intel_limits_pineview_lvds;
2177832f 544 else
f2b115e6 545 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
551 else
552 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 558 } else {
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 560 limit = &intel_limits_i8xx_lvds;
79e53945 561 else
e4b36699 562 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 563 }
564 return limit;
565}
566
f2b115e6
AJ		 567/* m1 is reserved as 0 in Pineview, n is a ring counter */
568static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 569{
2177832f
SL		 570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
574}
575
576static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
577{
f2b115e6
AJ		 578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
2177832f
SL		 580 return;
581 }
79e53945
JB		 582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
586}
587
79e53945
JB		 588/**
589 * Returns whether any output on the specified pipe is of the specified type
590 */
4ef69c7a 591bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 592{
4ef69c7a 593 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 594 struct intel_encoder *encoder;
595
6c2b7c12
DV		 596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
4ef69c7a
CW		 598 return true;
599
600 return false;
79e53945
JB		 601}
602
7c04d1d9 603#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 604/**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
1b894b59
CW		 609static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
79e53945 612{
79e53945 613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 614 INTELPllInvalid("p1 out of range\n");
79e53945 615 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 616 INTELPllInvalid("p out of range\n");
79e53945 617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 618 INTELPllInvalid("m2 out of range\n");
79e53945 619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 620 INTELPllInvalid("m1 out of range\n");
f2b115e6 621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 622 INTELPllInvalid("m1 <= m2\n");
79e53945 623 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 624 INTELPllInvalid("m out of range\n");
79e53945 625 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 626 INTELPllInvalid("n out of range\n");
79e53945 627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 628 INTELPllInvalid("vco out of range\n");
79e53945
JB		 629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 633 INTELPllInvalid("dot out of range\n");
79e53945
JB		 634
635 return true;
636}
637
d4906093
ML		 638static bool
639intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
d4906093 642
79e53945
JB		 643{
644 struct drm_device *dev = crtc->dev;
79e53945 645 intel_clock_t clock;
79e53945
JB		 646 int err = target;
647
a210b028 648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 649 /*
a210b028
DV		 650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
79e53945 653 */
1974cad0 654 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
0206e353 665 memset(best_clock, 0, sizeof(*best_clock));
79e53945 666
42158660
ZY		 667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 678 int this_err;
679
2177832f 680 intel_clock(dev, refclk, &clock);
1b894b59
CW		 681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
79e53945 683 continue;
cec2f356
SP		 684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
79e53945
JB		 687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699}
700
d4906093
ML		 701static bool
702intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
d4906093
ML		 705{
706 struct drm_device *dev = crtc->dev;
d4906093
ML		 707 intel_clock_t clock;
708 int max_n;
709 bool found;
6ba770dc
AJ		 710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 712 found = false;
713
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 715 int lvds_reg;
716
c619eed4 717 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
1974cad0 721 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
f77f13e2 734 /* based on hardware requirement, prefer smaller n to precision */
d4906093 735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 736 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err;
744
2177832f 745 intel_clock(dev, refclk, &clock);
1b894b59
CW		 746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
d4906093 748 continue;
cec2f356
SP		 749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
1b894b59
CW		 752
753 this_err = abs(clock.dot - target);
d4906093
ML		 754 if (this_err < err_most) {
755 *best_clock = clock;
756 err_most = this_err;
757 max_n = clock.n;
758 found = true;
759 }
760 }
761 }
762 }
763 }
2c07245f
ZW		 764 return found;
765}
766
5eb08b69 767static bool
f2b115e6 768intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
5eb08b69
ZW		 771{
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
4547668a 774
5eb08b69
ZW		 775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791}
792
a4fc5ed6
KP		 793/* DisplayPort has only two frequencies, 162MHz and 270MHz */
794static bool
795intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
a4fc5ed6 798{
5eddb70b
CW		 799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
a4fc5ed6 819}
a0c4da24
JB		 820static bool
821intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824{
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
829 int dotclk, flag;
830
af447bd3 831 flag = 0;
a0c4da24
JB		 832 dotclk = target * 1000;
833 bestppm = 1000000;
834 ppm = absppm = 0;
835 fastclk = dotclk / (2*100);
836 updrate = 0;
837 minupdate = 19200;
838 fracbits = 1;
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
847 if (p2 > 10)
848 p2 = p2 - 1;
849 p = p1 * p2;
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
854 m = m1 * m2;
855 vco = updrate * m;
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
860 bestppm = 0;
861 flag = 1;
862 }
863 if (absppm < bestppm - 10) {
864 bestppm = absppm;
865 flag = 1;
866 }
867 if (flag) {
868 bestn = n;
869 bestm1 = m1;
870 bestm2 = m2;
871 bestp1 = p1;
872 bestp2 = p2;
873 flag = 0;
874 }
875 }
876 }
877 }
878 }
879 }
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
885
886 return true;
887}
a4fc5ed6 888
a5c961d1
PZ		 889enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
894
895 return intel_crtc->cpu_transcoder;
896}
897
a928d536
PZ		 898static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
899{
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
902
903 frame = I915_READ(frame_reg);
904
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
907}
908
9d0498a2
JB		 909/**
910 * intel_wait_for_vblank - wait for vblank on a given pipe
911 * @dev: drm device
912 * @pipe: pipe to wait for
913 *
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 * mode setting code.
916 */
917void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 918{
9d0498a2 919 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 920 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 921
a928d536
PZ		 922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
924 return;
925 }
926
300387c0
CW		 927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
929 *
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
936 * vblanks...
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
939 */
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
942
9d0498a2 943 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
946 50))
9d0498a2
JB		 947 DRM_DEBUG_KMS("vblank wait timed out\n");
948}
949
ab7ad7f6
KP		 950/*
951 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
958 *
ab7ad7f6
KP		 959 * On Gen4 and above:
960 * wait for the pipe register state bit to turn off
961 *
962 * Otherwise:
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
58e10eb9 965 *
9d0498a2 966 */
58e10eb9 967void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 968{
969 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
ab7ad7f6
KP		 972
973 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 974 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 975
976 /* Wait for the Pipe State to go off */
58e10eb9
CW		 977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
978 100))
284637d9 979 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 980 } else {
837ba00f 981 u32 last_line, line_mask;
58e10eb9 982 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
984
837ba00f
PZ		 985 if (IS_GEN2(dev))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
ab7ad7f6
KP		 990 /* Wait for the display line to settle */
991 do {
837ba00f 992 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 993 mdelay(5);
837ba00f 994 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
284637d9 997 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 998 }
79e53945
JB		 999}
1000
b0ea7d37
DL		 1001/*
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1005 *
1006 * Returns true if @port is connected, false otherwise.
1007 */
1008bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1010{
1011 u32 bit;
1012
c36346e3
DL		 1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1015 case PORT_B:
1016 bit = SDE_PORTB_HOTPLUG;
1017 break;
1018 case PORT_C:
1019 bit = SDE_PORTC_HOTPLUG;
1020 break;
1021 case PORT_D:
1022 bit = SDE_PORTD_HOTPLUG;
1023 break;
1024 default:
1025 return true;
1026 }
1027 } else {
1028 switch(port->port) {
1029 case PORT_B:
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1031 break;
1032 case PORT_C:
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1034 break;
1035 case PORT_D:
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1037 break;
1038 default:
1039 return true;
1040 }
b0ea7d37
DL		 1041 }
1042
1043 return I915_READ(SDEISR) & bit;
1044}
1045
b24e7179
JB		 1046static const char *state_string(bool enabled)
1047{
1048 return enabled ? "on" : "off";
1049}
1050
1051/* Only for pre-ILK configs */
1052static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1054{
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DPLL(pipe);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1065}
1066#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
040484af
JB		 1069/* For ILK+ */
1070static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1073 bool state)
040484af 1074{
040484af
JB		 1075 u32 val;
1076 bool cur_state;
1077
9d82aa17
ED		 1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080 return;
1081 }
1082
92b27b08
CW		 1083 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1085 return;
ee7b9f93 1086
92b27b08
CW		 1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
d3ccbe86 1110 }
040484af 1111}
92b27b08
CW		 1112#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1114
1115static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117{
1118 int reg;
1119 u32 val;
1120 bool cur_state;
ad80a810
PZ		 1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
040484af 1123
affa9354
PZ		 1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
ad80a810 1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1127 val = I915_READ(reg);
ad80a810 1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
040484af
JB		 1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137}
1138#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143{
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
d63fa0dc
PZ		 1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154}
1155#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160{
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1166 return;
1167
bf507ef7 1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1169 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1170 return;
1171
040484af
JB		 1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175}
1176
1177static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179{
1180 int reg;
1181 u32 val;
1182
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186}
1187
ea0760cf
JB		 1188static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
0de3b485 1194 bool locked = true;
ea0760cf
JB		 1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1214 pipe_name(pipe));
ea0760cf
JB		 1215}
1216
b840d907
JB		 1217void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
b24e7179
JB		 1219{
1220 int reg;
1221 u32 val;
63d7bbe9 1222 bool cur_state;
702e7a56
PZ		 1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
b24e7179 1225
8e636784
DV		 1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true;
1229
69310161
PZ		 1230 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
63d7bbe9
JB		 1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1241 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1242}
1243
931872fc
CW		 1244static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
b24e7179
JB		 1246{
1247 int reg;
1248 u32 val;
931872fc 1249 bool cur_state;
b24e7179
JB		 1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
931872fc
CW		 1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1257}
1258
931872fc
CW		 1259#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
b24e7179
JB		 1262static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
1265 int reg, i;
1266 u32 val;
1267 int cur_pipe;
1268
19ec1358 1269 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1275 plane_name(pipe));
19ec1358 1276 return;
28c05794 1277 }
19ec1358 1278
b24e7179
JB		 1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1281 reg = DSPCNTR(i);
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1288 }
1289}
1290
92f2584a
JB		 1291static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1292{
1293 u32 val;
1294 bool enabled;
1295
9d82aa17
ED		 1296 if (HAS_PCH_LPT(dev_priv->dev)) {
1297 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1298 return;
1299 }
1300
92f2584a
JB		 1301 val = I915_READ(PCH_DREF_CONTROL);
1302 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1303 DREF_SUPERSPREAD_SOURCE_MASK));
1304 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1305}
1306
1307static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe)
1309{
1310 int reg;
1311 u32 val;
1312 bool enabled;
1313
1314 reg = TRANSCONF(pipe);
1315 val = I915_READ(reg);
1316 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1317 WARN(enabled,
1318 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1319 pipe_name(pipe));
92f2584a
JB		 1320}
1321
4e634389
KP		 1322static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1324{
1325 if ((val & DP_PORT_EN) == 0)
1326 return false;
1327
1328 if (HAS_PCH_CPT(dev_priv->dev)) {
1329 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1330 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1331 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1332 return false;
1333 } else {
1334 if ((val & DP_PIPE_MASK) != (pipe << 30))
1335 return false;
1336 }
1337 return true;
1338}
1339
1519b995
KP		 1340static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
dc0fa718 1343 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1347 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1348 return false;
1349 } else {
dc0fa718 1350 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & LVDS_PORT_EN) == 0)
1360 return false;
1361
1362 if (HAS_PCH_CPT(dev_priv->dev)) {
1363 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1364 return false;
1365 } else {
1366 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1367 return false;
1368 }
1369 return true;
1370}
1371
1372static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 val)
1374{
1375 if ((val & ADPA_DAC_ENABLE) == 0)
1376 return false;
1377 if (HAS_PCH_CPT(dev_priv->dev)) {
1378 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1379 return false;
1380 } else {
1381 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1382 return false;
1383 }
1384 return true;
1385}
1386
291906f1 1387static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1388 enum pipe pipe, int reg, u32 port_sel)
291906f1 1389{
47a05eca 1390 u32 val = I915_READ(reg);
4e634389 1391 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1392 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1393 reg, pipe_name(pipe));
de9a35ab 1394
75c5da27
DV		 1395 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1396 && (val & DP_PIPEB_SELECT),
de9a35ab 1397 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1398}
1399
1400static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe, int reg)
1402{
47a05eca 1403 u32 val = I915_READ(reg);
b70ad586 1404 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1405 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1406 reg, pipe_name(pipe));
de9a35ab 1407
dc0fa718 1408 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1409 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1410 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1411}
1412
1413static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe)
1415{
1416 int reg;
1417 u32 val;
291906f1 1418
f0575e92
KP		 1419 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1420 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1421 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1422
1423 reg = PCH_ADPA;
1424 val = I915_READ(reg);
b70ad586 1425 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1426 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1427 pipe_name(pipe));
291906f1
JB		 1428
1429 reg = PCH_LVDS;
1430 val = I915_READ(reg);
b70ad586 1431 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1432 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1433 pipe_name(pipe));
291906f1 1434
e2debe91
PZ		 1435 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1436 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1437 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1438}
1439
63d7bbe9
JB		 1440/**
1441 * intel_enable_pll - enable a PLL
1442 * @dev_priv: i915 private structure
1443 * @pipe: pipe PLL to enable
1444 *
1445 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1446 * make sure the PLL reg is writable first though, since the panel write
1447 * protect mechanism may be enabled.
1448 *
1449 * Note! This is for pre-ILK only.
7434a255
TR		 1450 *
1451 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1452 */
1453static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1454{
1455 int reg;
1456 u32 val;
1457
1458 /* No really, not for ILK+ */
a0c4da24 1459 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1460
1461 /* PLL is protected by panel, make sure we can write it */
1462 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1463 assert_panel_unlocked(dev_priv, pipe);
1464
1465 reg = DPLL(pipe);
1466 val = I915_READ(reg);
1467 val |= DPLL_VCO_ENABLE;
1468
1469 /* We do this three times for luck */
1470 I915_WRITE(reg, val);
1471 POSTING_READ(reg);
1472 udelay(150); /* wait for warmup */
1473 I915_WRITE(reg, val);
1474 POSTING_READ(reg);
1475 udelay(150); /* wait for warmup */
1476 I915_WRITE(reg, val);
1477 POSTING_READ(reg);
1478 udelay(150); /* wait for warmup */
1479}
1480
1481/**
1482 * intel_disable_pll - disable a PLL
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe PLL to disable
1485 *
1486 * Disable the PLL for @pipe, making sure the pipe is off first.
1487 *
1488 * Note! This is for pre-ILK only.
1489 */
1490static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1491{
1492 int reg;
1493 u32 val;
1494
1495 /* Don't disable pipe A or pipe A PLLs if needed */
1496 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1497 return;
1498
1499 /* Make sure the pipe isn't still relying on us */
1500 assert_pipe_disabled(dev_priv, pipe);
1501
1502 reg = DPLL(pipe);
1503 val = I915_READ(reg);
1504 val &= ~DPLL_VCO_ENABLE;
1505 I915_WRITE(reg, val);
1506 POSTING_READ(reg);
1507}
1508
a416edef
ED		 1509/* SBI access */
1510static void
988d6ee8
PZ		 1511intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1512 enum intel_sbi_destination destination)
a416edef 1513{
988d6ee8 1514 u32 tmp;
a416edef 1515
09153000 1516 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1517
39fb50f6 1518 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1519 100)) {
1520 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1521 return;
a416edef
ED		 1522 }
1523
988d6ee8
PZ		 1524 I915_WRITE(SBI_ADDR, (reg << 16));
1525 I915_WRITE(SBI_DATA, value);
1526
1527 if (destination == SBI_ICLK)
1528 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1529 else
1530 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1531 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1532
39fb50f6 1533 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1534 100)) {
1535 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1536 return;
a416edef 1537 }
a416edef
ED		 1538}
1539
1540static u32
988d6ee8
PZ		 1541intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1542 enum intel_sbi_destination destination)
a416edef 1543{
39fb50f6 1544 u32 value = 0;
09153000 1545 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1546
39fb50f6 1547 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1548 100)) {
1549 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1550 return 0;
a416edef
ED		 1551 }
1552
988d6ee8
PZ		 1553 I915_WRITE(SBI_ADDR, (reg << 16));
1554
1555 if (destination == SBI_ICLK)
1556 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1557 else
1558 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1559 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1560
39fb50f6 1561 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1562 100)) {
1563 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1564 return 0;
a416edef
ED		 1565 }
1566
09153000 1567 return I915_READ(SBI_DATA);
a416edef
ED		 1568}
1569
92f2584a 1570/**
b6b4e185 1571 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1572 * @dev_priv: i915 private structure
1573 * @pipe: pipe PLL to enable
1574 *
1575 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576 * drives the transcoder clock.
1577 */
b6b4e185 1578static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1579{
ee7b9f93 1580 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1581 struct intel_pch_pll *pll;
92f2584a
JB		 1582 int reg;
1583 u32 val;
1584
48da64a8 1585 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1586 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1587 pll = intel_crtc->pch_pll;
1588 if (pll == NULL)
1589 return;
1590
1591 if (WARN_ON(pll->refcount == 0))
1592 return;
ee7b9f93
JB		 1593
1594 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595 pll->pll_reg, pll->active, pll->on,
1596 intel_crtc->base.base.id);
92f2584a
JB		 1597
1598 /* PCH refclock must be enabled first */
1599 assert_pch_refclk_enabled(dev_priv);
1600
ee7b9f93 1601 if (pll->active++ && pll->on) {
92b27b08 1602 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1603 return;
1604 }
1605
1606 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1607
1608 reg = pll->pll_reg;
92f2584a
JB		 1609 val = I915_READ(reg);
1610 val |= DPLL_VCO_ENABLE;
1611 I915_WRITE(reg, val);
1612 POSTING_READ(reg);
1613 udelay(200);
ee7b9f93
JB		 1614
1615 pll->on = true;
92f2584a
JB		 1616}
1617
ee7b9f93 1618static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1619{
ee7b9f93
JB		 1620 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1621 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1622 int reg;
ee7b9f93 1623 u32 val;
4c609cb8 1624
92f2584a
JB		 1625 /* PCH only available on ILK+ */
1626 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1627 if (pll == NULL)
1628 return;
92f2584a 1629
48da64a8
CW		 1630 if (WARN_ON(pll->refcount == 0))
1631 return;
7a419866 1632
ee7b9f93
JB		 1633 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634 pll->pll_reg, pll->active, pll->on,
1635 intel_crtc->base.base.id);
7a419866 1636
48da64a8 1637 if (WARN_ON(pll->active == 0)) {
92b27b08 1638 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1639 return;
1640 }
1641
ee7b9f93 1642 if (--pll->active) {
92b27b08 1643 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1644 return;
ee7b9f93
JB		 1645 }
1646
1647 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1648
1649 /* Make sure transcoder isn't still depending on us */
1650 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1651
ee7b9f93 1652 reg = pll->pll_reg;
92f2584a
JB		 1653 val = I915_READ(reg);
1654 val &= ~DPLL_VCO_ENABLE;
1655 I915_WRITE(reg, val);
1656 POSTING_READ(reg);
1657 udelay(200);
ee7b9f93
JB		 1658
1659 pll->on = false;
92f2584a
JB		 1660}
1661
b8a4f404
PZ		 1662static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1663 enum pipe pipe)
040484af 1664{
23670b32 1665 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1666 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1667 uint32_t reg, val, pipeconf_val;
040484af
JB		 1668
1669 /* PCH only available on ILK+ */
1670 BUG_ON(dev_priv->info->gen < 5);
1671
1672 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1673 assert_pch_pll_enabled(dev_priv,
1674 to_intel_crtc(crtc)->pch_pll,
1675 to_intel_crtc(crtc));
040484af
JB		 1676
1677 /* FDI must be feeding us bits for PCH ports */
1678 assert_fdi_tx_enabled(dev_priv, pipe);
1679 assert_fdi_rx_enabled(dev_priv, pipe);
1680
23670b32
DV		 1681 if (HAS_PCH_CPT(dev)) {
1682 /* Workaround: Set the timing override bit before enabling the
1683 * pch transcoder. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
59c859d6 1688 }
23670b32 1689
040484af
JB		 1690 reg = TRANSCONF(pipe);
1691 val = I915_READ(reg);
5f7f726d 1692 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1693
1694 if (HAS_PCH_IBX(dev_priv->dev)) {
1695 /*
1696 * make the BPC in transcoder be consistent with
1697 * that in pipeconf reg.
1698 */
dfd07d72
DV		 1699 val &= ~PIPECONF_BPC_MASK;
1700 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1701 }
5f7f726d
PZ		 1702
1703 val &= ~TRANS_INTERLACE_MASK;
1704 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1705 if (HAS_PCH_IBX(dev_priv->dev) &&
1706 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1707 val |= TRANS_LEGACY_INTERLACED_ILK;
1708 else
1709 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1710 else
1711 val |= TRANS_PROGRESSIVE;
1712
040484af
JB		 1713 I915_WRITE(reg, val | TRANS_ENABLE);
1714 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1715 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1716}
1717
8fb033d7 1718static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1719 enum transcoder cpu_transcoder)
040484af 1720{
8fb033d7 1721 u32 val, pipeconf_val;
8fb033d7
PZ		 1722
1723 /* PCH only available on ILK+ */
1724 BUG_ON(dev_priv->info->gen < 5);
1725
8fb033d7 1726 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1727 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1728 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1729
223a6fdf
PZ		 1730 /* Workaround: set timing override bit. */
1731 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1732 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1733 I915_WRITE(_TRANSA_CHICKEN2, val);
1734
25f3ef11 1735 val = TRANS_ENABLE;
937bb610 1736 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1737
9a76b1c6
PZ		 1738 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1739 PIPECONF_INTERLACED_ILK)
a35f2679 1740 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1741 else
1742 val |= TRANS_PROGRESSIVE;
1743
25f3ef11 1744 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1745 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1746 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1747}
1748
b8a4f404
PZ		 1749static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1750 enum pipe pipe)
040484af 1751{
23670b32
DV		 1752 struct drm_device *dev = dev_priv->dev;
1753 uint32_t reg, val;
040484af
JB		 1754
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe);
1757 assert_fdi_rx_disabled(dev_priv, pipe);
1758
291906f1
JB		 1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1761
040484af
JB		 1762 reg = TRANSCONF(pipe);
1763 val = I915_READ(reg);
1764 val &= ~TRANS_ENABLE;
1765 I915_WRITE(reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1768 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1769
1770 if (!HAS_PCH_IBX(dev)) {
1771 /* Workaround: Clear the timing override chicken bit again. */
1772 reg = TRANS_CHICKEN2(pipe);
1773 val = I915_READ(reg);
1774 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1775 I915_WRITE(reg, val);
1776 }
040484af
JB		 1777}
1778
ab4d966c 1779static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1780{
8fb033d7
PZ		 1781 u32 val;
1782
8a52fd9f 1783 val = I915_READ(_TRANSACONF);
8fb033d7 1784 val &= ~TRANS_ENABLE;
8a52fd9f 1785 I915_WRITE(_TRANSACONF, val);
8fb033d7 1786 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1787 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1788 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1789
1790 /* Workaround: clear timing override bit. */
1791 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1792 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1793 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1794}
1795
b24e7179 1796/**
309cfea8 1797 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe to enable
040484af 1800 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1801 *
1802 * Enable @pipe, making sure that various hardware specific requirements
1803 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1804 *
1805 * @pipe should be %PIPE_A or %PIPE_B.
1806 *
1807 * Will wait until the pipe is actually running (i.e. first vblank) before
1808 * returning.
1809 */
040484af
JB		 1810static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1811 bool pch_port)
b24e7179 1812{
702e7a56
PZ		 1813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1814 pipe);
1a240d4d 1815 enum pipe pch_transcoder;
b24e7179
JB		 1816 int reg;
1817 u32 val;
1818
681e5811 1819 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1820 pch_transcoder = TRANSCODER_A;
1821 else
1822 pch_transcoder = pipe;
1823
b24e7179
JB		 1824 /*
1825 * A pipe without a PLL won't actually be able to drive bits from
1826 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1827 * need the check.
1828 */
1829 if (!HAS_PCH_SPLIT(dev_priv->dev))
1830 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1831 else {
1832 if (pch_port) {
1833 /* if driving the PCH, we need FDI enabled */
cc391bbb 1834 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1835 assert_fdi_tx_pll_enabled(dev_priv,
1836 (enum pipe) cpu_transcoder);
040484af
JB		 1837 }
1838 /* FIXME: assert CPU port conditions for SNB+ */
1839 }
b24e7179 1840
702e7a56 1841 reg = PIPECONF(cpu_transcoder);
b24e7179 1842 val = I915_READ(reg);
00d70b15
CW		 1843 if (val & PIPECONF_ENABLE)
1844 return;
1845
1846 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1847 intel_wait_for_vblank(dev_priv->dev, pipe);
1848}
1849
1850/**
309cfea8 1851 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1852 * @dev_priv: i915 private structure
1853 * @pipe: pipe to disable
1854 *
1855 * Disable @pipe, making sure that various hardware specific requirements
1856 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1857 *
1858 * @pipe should be %PIPE_A or %PIPE_B.
1859 *
1860 * Will wait until the pipe has shut down before returning.
1861 */
1862static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1863 enum pipe pipe)
1864{
702e7a56
PZ		 1865 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1866 pipe);
b24e7179
JB		 1867 int reg;
1868 u32 val;
1869
1870 /*
1871 * Make sure planes won't keep trying to pump pixels to us,
1872 * or we might hang the display.
1873 */
1874 assert_planes_disabled(dev_priv, pipe);
1875
1876 /* Don't disable pipe A or pipe A PLLs if needed */
1877 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1878 return;
1879
702e7a56 1880 reg = PIPECONF(cpu_transcoder);
b24e7179 1881 val = I915_READ(reg);
00d70b15
CW		 1882 if ((val & PIPECONF_ENABLE) == 0)
1883 return;
1884
1885 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1886 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1887}
1888
d74362c9
KP		 1889/*
1890 * Plane regs are double buffered, going from enabled->disabled needs a
1891 * trigger in order to latch. The display address reg provides this.
1892 */
6f1d69b0 1893void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1894 enum plane plane)
1895{
14f86147
DL		 1896 if (dev_priv->info->gen >= 4)
1897 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1898 else
1899 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1900}
1901
b24e7179
JB		 1902/**
1903 * intel_enable_plane - enable a display plane on a given pipe
1904 * @dev_priv: i915 private structure
1905 * @plane: plane to enable
1906 * @pipe: pipe being fed
1907 *
1908 * Enable @plane on @pipe, making sure that @pipe is running first.
1909 */
1910static void intel_enable_plane(struct drm_i915_private *dev_priv,
1911 enum plane plane, enum pipe pipe)
1912{
1913 int reg;
1914 u32 val;
1915
1916 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1917 assert_pipe_enabled(dev_priv, pipe);
1918
1919 reg = DSPCNTR(plane);
1920 val = I915_READ(reg);
00d70b15
CW		 1921 if (val & DISPLAY_PLANE_ENABLE)
1922 return;
1923
1924 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1925 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1926 intel_wait_for_vblank(dev_priv->dev, pipe);
1927}
1928
b24e7179
JB		 1929/**
1930 * intel_disable_plane - disable a display plane
1931 * @dev_priv: i915 private structure
1932 * @plane: plane to disable
1933 * @pipe: pipe consuming the data
1934 *
1935 * Disable @plane; should be an independent operation.
1936 */
1937static void intel_disable_plane(struct drm_i915_private *dev_priv,
1938 enum plane plane, enum pipe pipe)
1939{
1940 int reg;
1941 u32 val;
1942
1943 reg = DSPCNTR(plane);
1944 val = I915_READ(reg);
00d70b15
CW		 1945 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1946 return;
1947
1948 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1949 intel_flush_display_plane(dev_priv, plane);
1950 intel_wait_for_vblank(dev_priv->dev, pipe);
1951}
1952
693db184
CW		 1953static bool need_vtd_wa(struct drm_device *dev)
1954{
1955#ifdef CONFIG_INTEL_IOMMU
1956 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1957 return true;
1958#endif
1959 return false;
1960}
1961
127bd2ac 1962int
48b956c5 1963intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1964 struct drm_i915_gem_object *obj,
919926ae 1965 struct intel_ring_buffer *pipelined)
6b95a207 1966{
ce453d81 1967 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1968 u32 alignment;
1969 int ret;
1970
05394f39 1971 switch (obj->tiling_mode) {
6b95a207 1972 case I915_TILING_NONE:
534843da
CW		 1973 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1974 alignment = 128 * 1024;
a6c45cf0 1975 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1976 alignment = 4 * 1024;
1977 else
1978 alignment = 64 * 1024;
6b95a207
KH		 1979 break;
1980 case I915_TILING_X:
1981 /* pin() will align the object as required by fence */
1982 alignment = 0;
1983 break;
1984 case I915_TILING_Y:
1985 /* FIXME: Is this true? */
1986 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1987 return -EINVAL;
1988 default:
1989 BUG();
1990 }
1991
693db184
CW		 1992 /* Note that the w/a also requires 64 PTE of padding following the
1993 * bo. We currently fill all unused PTE with the shadow page and so
1994 * we should always have valid PTE following the scanout preventing
1995 * the VT-d warning.
1996 */
1997 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1998 alignment = 256 * 1024;
1999
ce453d81 2000 dev_priv->mm.interruptible = false;
2da3b9b9 2001 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2002 if (ret)
ce453d81 2003 goto err_interruptible;
6b95a207
KH		 2004
2005 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2006 * fence, whereas 965+ only requires a fence if using
2007 * framebuffer compression. For simplicity, we always install
2008 * a fence as the cost is not that onerous.
2009 */
06d98131 2010 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2011 if (ret)
2012 goto err_unpin;
1690e1eb 2013
9a5a53b3 2014 i915_gem_object_pin_fence(obj);
6b95a207 2015
ce453d81 2016 dev_priv->mm.interruptible = true;
6b95a207 2017 return 0;
48b956c5
CW		 2018
2019err_unpin:
2020 i915_gem_object_unpin(obj);
ce453d81
CW		 2021err_interruptible:
2022 dev_priv->mm.interruptible = true;
48b956c5 2023 return ret;
6b95a207
KH		 2024}
2025
1690e1eb
CW		 2026void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2027{
2028 i915_gem_object_unpin_fence(obj);
2029 i915_gem_object_unpin(obj);
2030}
2031
c2c75131
DV		 2032/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2033 * is assumed to be a power-of-two. */
bc752862
CW		 2034unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2035 unsigned int tiling_mode,
2036 unsigned int cpp,
2037 unsigned int pitch)
c2c75131 2038{
bc752862
CW		 2039 if (tiling_mode != I915_TILING_NONE) {
2040 unsigned int tile_rows, tiles;
c2c75131 2041
bc752862
CW		 2042 tile_rows = *y / 8;
2043 *y %= 8;
c2c75131 2044
bc752862
CW		 2045 tiles = *x / (512/cpp);
2046 *x %= 512/cpp;
2047
2048 return tile_rows * pitch * 8 + tiles * 4096;
2049 } else {
2050 unsigned int offset;
2051
2052 offset = *y * pitch + *x * cpp;
2053 *y = 0;
2054 *x = (offset & 4095) / cpp;
2055 return offset & -4096;
2056 }
c2c75131
DV		 2057}
2058
17638cd6
JB		 2059static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2060 int x, int y)
81255565
JB		 2061{
2062 struct drm_device *dev = crtc->dev;
2063 struct drm_i915_private *dev_priv = dev->dev_private;
2064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2065 struct intel_framebuffer *intel_fb;
05394f39 2066 struct drm_i915_gem_object *obj;
81255565 2067 int plane = intel_crtc->plane;
e506a0c6 2068 unsigned long linear_offset;
81255565 2069 u32 dspcntr;
5eddb70b 2070 u32 reg;
81255565
JB		 2071
2072 switch (plane) {
2073 case 0:
2074 case 1:
2075 break;
2076 default:
2077 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2078 return -EINVAL;
2079 }
2080
2081 intel_fb = to_intel_framebuffer(fb);
2082 obj = intel_fb->obj;
81255565 2083
5eddb70b
CW		 2084 reg = DSPCNTR(plane);
2085 dspcntr = I915_READ(reg);
81255565
JB		 2086 /* Mask out pixel format bits in case we change it */
2087 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2088 switch (fb->pixel_format) {
2089 case DRM_FORMAT_C8:
81255565
JB		 2090 dspcntr |= DISPPLANE_8BPP;
2091 break;
57779d06
VS		 2092 case DRM_FORMAT_XRGB1555:
2093 case DRM_FORMAT_ARGB1555:
2094 dspcntr |= DISPPLANE_BGRX555;
81255565 2095 break;
57779d06
VS		 2096 case DRM_FORMAT_RGB565:
2097 dspcntr |= DISPPLANE_BGRX565;
2098 break;
2099 case DRM_FORMAT_XRGB8888:
2100 case DRM_FORMAT_ARGB8888:
2101 dspcntr |= DISPPLANE_BGRX888;
2102 break;
2103 case DRM_FORMAT_XBGR8888:
2104 case DRM_FORMAT_ABGR8888:
2105 dspcntr |= DISPPLANE_RGBX888;
2106 break;
2107 case DRM_FORMAT_XRGB2101010:
2108 case DRM_FORMAT_ARGB2101010:
2109 dspcntr |= DISPPLANE_BGRX101010;
2110 break;
2111 case DRM_FORMAT_XBGR2101010:
2112 case DRM_FORMAT_ABGR2101010:
2113 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2114 break;
2115 default:
57779d06 2116 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2117 return -EINVAL;
2118 }
57779d06 2119
a6c45cf0 2120 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2121 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2122 dspcntr |= DISPPLANE_TILED;
2123 else
2124 dspcntr &= ~DISPPLANE_TILED;
2125 }
2126
5eddb70b 2127 I915_WRITE(reg, dspcntr);
81255565 2128
e506a0c6 2129 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2130
c2c75131
DV		 2131 if (INTEL_INFO(dev)->gen >= 4) {
2132 intel_crtc->dspaddr_offset =
bc752862
CW		 2133 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2134 fb->bits_per_pixel / 8,
2135 fb->pitches[0]);
c2c75131
DV		 2136 linear_offset -= intel_crtc->dspaddr_offset;
2137 } else {
e506a0c6 2138 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2139 }
e506a0c6
DV		 2140
2141 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2142 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2143 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2144 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2145 I915_MODIFY_DISPBASE(DSPSURF(plane),
2146 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2147 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2148 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2149 } else
e506a0c6 2150 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2151 POSTING_READ(reg);
81255565 2152
17638cd6
JB		 2153 return 0;
2154}
2155
2156static int ironlake_update_plane(struct drm_crtc *crtc,
2157 struct drm_framebuffer *fb, int x, int y)
2158{
2159 struct drm_device *dev = crtc->dev;
2160 struct drm_i915_private *dev_priv = dev->dev_private;
2161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2162 struct intel_framebuffer *intel_fb;
2163 struct drm_i915_gem_object *obj;
2164 int plane = intel_crtc->plane;
e506a0c6 2165 unsigned long linear_offset;
17638cd6
JB		 2166 u32 dspcntr;
2167 u32 reg;
2168
2169 switch (plane) {
2170 case 0:
2171 case 1:
27f8227b 2172 case 2:
17638cd6
JB		 2173 break;
2174 default:
2175 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2176 return -EINVAL;
2177 }
2178
2179 intel_fb = to_intel_framebuffer(fb);
2180 obj = intel_fb->obj;
2181
2182 reg = DSPCNTR(plane);
2183 dspcntr = I915_READ(reg);
2184 /* Mask out pixel format bits in case we change it */
2185 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2186 switch (fb->pixel_format) {
2187 case DRM_FORMAT_C8:
17638cd6
JB		 2188 dspcntr |= DISPPLANE_8BPP;
2189 break;
57779d06
VS		 2190 case DRM_FORMAT_RGB565:
2191 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2192 break;
57779d06
VS		 2193 case DRM_FORMAT_XRGB8888:
2194 case DRM_FORMAT_ARGB8888:
2195 dspcntr |= DISPPLANE_BGRX888;
2196 break;
2197 case DRM_FORMAT_XBGR8888:
2198 case DRM_FORMAT_ABGR8888:
2199 dspcntr |= DISPPLANE_RGBX888;
2200 break;
2201 case DRM_FORMAT_XRGB2101010:
2202 case DRM_FORMAT_ARGB2101010:
2203 dspcntr |= DISPPLANE_BGRX101010;
2204 break;
2205 case DRM_FORMAT_XBGR2101010:
2206 case DRM_FORMAT_ABGR2101010:
2207 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2208 break;
2209 default:
57779d06 2210 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2211 return -EINVAL;
2212 }
2213
2214 if (obj->tiling_mode != I915_TILING_NONE)
2215 dspcntr |= DISPPLANE_TILED;
2216 else
2217 dspcntr &= ~DISPPLANE_TILED;
2218
2219 /* must disable */
2220 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2221
2222 I915_WRITE(reg, dspcntr);
2223
e506a0c6 2224 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2225 intel_crtc->dspaddr_offset =
bc752862
CW		 2226 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2227 fb->bits_per_pixel / 8,
2228 fb->pitches[0]);
c2c75131 2229 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2230
e506a0c6
DV		 2231 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2232 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2233 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2234 I915_MODIFY_DISPBASE(DSPSURF(plane),
2235 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2236 if (IS_HASWELL(dev)) {
2237 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2238 } else {
2239 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2240 I915_WRITE(DSPLINOFF(plane), linear_offset);
2241 }
17638cd6
JB		 2242 POSTING_READ(reg);
2243
2244 return 0;
2245}
2246
2247/* Assume fb object is pinned & idle & fenced and just update base pointers */
2248static int
2249intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2250 int x, int y, enum mode_set_atomic state)
2251{
2252 struct drm_device *dev = crtc->dev;
2253 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2254
6b8e6ed0
CW		 2255 if (dev_priv->display.disable_fbc)
2256 dev_priv->display.disable_fbc(dev);
3dec0095 2257 intel_increase_pllclock(crtc);
81255565 2258
6b8e6ed0 2259 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2260}
2261
96a02917
VS		 2262void intel_display_handle_reset(struct drm_device *dev)
2263{
2264 struct drm_i915_private *dev_priv = dev->dev_private;
2265 struct drm_crtc *crtc;
2266
2267 /*
2268 * Flips in the rings have been nuked by the reset,
2269 * so complete all pending flips so that user space
2270 * will get its events and not get stuck.
2271 *
2272 * Also update the base address of all primary
2273 * planes to the the last fb to make sure we're
2274 * showing the correct fb after a reset.
2275 *
2276 * Need to make two loops over the crtcs so that we
2277 * don't try to grab a crtc mutex before the
2278 * pending_flip_queue really got woken up.
2279 */
2280
2281 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2283 enum plane plane = intel_crtc->plane;
2284
2285 intel_prepare_page_flip(dev, plane);
2286 intel_finish_page_flip_plane(dev, plane);
2287 }
2288
2289 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2291
2292 mutex_lock(&crtc->mutex);
2293 if (intel_crtc->active)
2294 dev_priv->display.update_plane(crtc, crtc->fb,
2295 crtc->x, crtc->y);
2296 mutex_unlock(&crtc->mutex);
2297 }
2298}
2299
14667a4b
CW		 2300static int
2301intel_finish_fb(struct drm_framebuffer *old_fb)
2302{
2303 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2304 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2305 bool was_interruptible = dev_priv->mm.interruptible;
2306 int ret;
2307
14667a4b
CW		 2308 /* Big Hammer, we also need to ensure that any pending
2309 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2310 * current scanout is retired before unpinning the old
2311 * framebuffer.
2312 *
2313 * This should only fail upon a hung GPU, in which case we
2314 * can safely continue.
2315 */
2316 dev_priv->mm.interruptible = false;
2317 ret = i915_gem_object_finish_gpu(obj);
2318 dev_priv->mm.interruptible = was_interruptible;
2319
2320 return ret;
2321}
2322
198598d0
VS		 2323static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2324{
2325 struct drm_device *dev = crtc->dev;
2326 struct drm_i915_master_private *master_priv;
2327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2328
2329 if (!dev->primary->master)
2330 return;
2331
2332 master_priv = dev->primary->master->driver_priv;
2333 if (!master_priv->sarea_priv)
2334 return;
2335
2336 switch (intel_crtc->pipe) {
2337 case 0:
2338 master_priv->sarea_priv->pipeA_x = x;
2339 master_priv->sarea_priv->pipeA_y = y;
2340 break;
2341 case 1:
2342 master_priv->sarea_priv->pipeB_x = x;
2343 master_priv->sarea_priv->pipeB_y = y;
2344 break;
2345 default:
2346 break;
2347 }
2348}
2349
5c3b82e2 2350static int
3c4fdcfb 2351intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2352 struct drm_framebuffer *fb)
79e53945
JB		 2353{
2354 struct drm_device *dev = crtc->dev;
6b8e6ed0 2355 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2357 struct drm_framebuffer *old_fb;
5c3b82e2 2358 int ret;
79e53945
JB		 2359
2360 /* no fb bound */
94352cf9 2361 if (!fb) {
a5071c2f 2362 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2363 return 0;
2364 }
2365
7eb552ae 2366 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
5826eca5
ED		 2367 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2368 intel_crtc->plane,
7eb552ae 2369 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2370 return -EINVAL;
79e53945
JB		 2371 }
2372
5c3b82e2 2373 mutex_lock(&dev->struct_mutex);
265db958 2374 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2375 to_intel_framebuffer(fb)->obj,
919926ae 2376 NULL);
5c3b82e2
CW		 2377 if (ret != 0) {
2378 mutex_unlock(&dev->struct_mutex);
a5071c2f 2379 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2380 return ret;
2381 }
79e53945 2382
94352cf9 2383 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2384 if (ret) {
94352cf9 2385 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2386 mutex_unlock(&dev->struct_mutex);
a5071c2f 2387 DRM_ERROR("failed to update base address\n");
4e6cfefc 2388 return ret;
79e53945 2389 }
3c4fdcfb 2390
94352cf9
DV		 2391 old_fb = crtc->fb;
2392 crtc->fb = fb;
6c4c86f5
DV		 2393 crtc->x = x;
2394 crtc->y = y;
94352cf9 2395
b7f1de28
CW		 2396 if (old_fb) {
2397 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2398 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2399 }
652c393a 2400
6b8e6ed0 2401 intel_update_fbc(dev);
5c3b82e2 2402 mutex_unlock(&dev->struct_mutex);
79e53945 2403
198598d0 2404 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2405
2406 return 0;
79e53945
JB		 2407}
2408
5e84e1a4
ZW		 2409static void intel_fdi_normal_train(struct drm_crtc *crtc)
2410{
2411 struct drm_device *dev = crtc->dev;
2412 struct drm_i915_private *dev_priv = dev->dev_private;
2413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2414 int pipe = intel_crtc->pipe;
2415 u32 reg, temp;
2416
2417 /* enable normal train */
2418 reg = FDI_TX_CTL(pipe);
2419 temp = I915_READ(reg);
61e499bf 2420 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2421 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2422 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2423 } else {
2424 temp &= ~FDI_LINK_TRAIN_NONE;
2425 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2426 }
5e84e1a4
ZW		 2427 I915_WRITE(reg, temp);
2428
2429 reg = FDI_RX_CTL(pipe);
2430 temp = I915_READ(reg);
2431 if (HAS_PCH_CPT(dev)) {
2432 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2433 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2434 } else {
2435 temp &= ~FDI_LINK_TRAIN_NONE;
2436 temp |= FDI_LINK_TRAIN_NONE;
2437 }
2438 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2439
2440 /* wait one idle pattern time */
2441 POSTING_READ(reg);
2442 udelay(1000);
357555c0
JB		 2443
2444 /* IVB wants error correction enabled */
2445 if (IS_IVYBRIDGE(dev))
2446 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2447 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2448}
2449
01a415fd
DV		 2450static void ivb_modeset_global_resources(struct drm_device *dev)
2451{
2452 struct drm_i915_private *dev_priv = dev->dev_private;
2453 struct intel_crtc *pipe_B_crtc =
2454 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2455 struct intel_crtc *pipe_C_crtc =
2456 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2457 uint32_t temp;
2458
2459 /* When everything is off disable fdi C so that we could enable fdi B
2460 * with all lanes. XXX: This misses the case where a pipe is not using
2461 * any pch resources and so doesn't need any fdi lanes. */
2462 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2463 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2464 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2465
2466 temp = I915_READ(SOUTH_CHICKEN1);
2467 temp &= ~FDI_BC_BIFURCATION_SELECT;
2468 DRM_DEBUG_KMS("disabling fdi C rx\n");
2469 I915_WRITE(SOUTH_CHICKEN1, temp);
2470 }
2471}
2472
8db9d77b
ZW		 2473/* The FDI link training functions for ILK/Ibexpeak. */
2474static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2475{
2476 struct drm_device *dev = crtc->dev;
2477 struct drm_i915_private *dev_priv = dev->dev_private;
2478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2479 int pipe = intel_crtc->pipe;
0fc932b8 2480 int plane = intel_crtc->plane;
5eddb70b 2481 u32 reg, temp, tries;
8db9d77b 2482
0fc932b8
JB		 2483 /* FDI needs bits from pipe & plane first */
2484 assert_pipe_enabled(dev_priv, pipe);
2485 assert_plane_enabled(dev_priv, plane);
2486
e1a44743
AJ		 2487 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2488 for train result */
5eddb70b
CW		 2489 reg = FDI_RX_IMR(pipe);
2490 temp = I915_READ(reg);
e1a44743
AJ		 2491 temp &= ~FDI_RX_SYMBOL_LOCK;
2492 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2493 I915_WRITE(reg, temp);
2494 I915_READ(reg);
e1a44743
AJ		 2495 udelay(150);
2496
8db9d77b 2497 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2498 reg = FDI_TX_CTL(pipe);
2499 temp = I915_READ(reg);
77ffb597
AJ		 2500 temp &= ~(7 << 19);
2501 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2502 temp &= ~FDI_LINK_TRAIN_NONE;
2503 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2504 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2505
5eddb70b
CW		 2506 reg = FDI_RX_CTL(pipe);
2507 temp = I915_READ(reg);
8db9d77b
ZW		 2508 temp &= ~FDI_LINK_TRAIN_NONE;
2509 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2510 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2511
2512 POSTING_READ(reg);
8db9d77b
ZW		 2513 udelay(150);
2514
5b2adf89 2515 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2516 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2517 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2518 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2519
5eddb70b 2520 reg = FDI_RX_IIR(pipe);
e1a44743 2521 for (tries = 0; tries < 5; tries++) {
5eddb70b 2522 temp = I915_READ(reg);
8db9d77b
ZW		 2523 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2524
2525 if ((temp & FDI_RX_BIT_LOCK)) {
2526 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2527 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2528 break;
2529 }
8db9d77b 2530 }
e1a44743 2531 if (tries == 5)
5eddb70b 2532 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2533
2534 /* Train 2 */
5eddb70b
CW		 2535 reg = FDI_TX_CTL(pipe);
2536 temp = I915_READ(reg);
8db9d77b
ZW		 2537 temp &= ~FDI_LINK_TRAIN_NONE;
2538 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2539 I915_WRITE(reg, temp);
8db9d77b 2540
5eddb70b
CW		 2541 reg = FDI_RX_CTL(pipe);
2542 temp = I915_READ(reg);
8db9d77b
ZW		 2543 temp &= ~FDI_LINK_TRAIN_NONE;
2544 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2545 I915_WRITE(reg, temp);
8db9d77b 2546
5eddb70b
CW		 2547 POSTING_READ(reg);
2548 udelay(150);
8db9d77b 2549
5eddb70b 2550 reg = FDI_RX_IIR(pipe);
e1a44743 2551 for (tries = 0; tries < 5; tries++) {
5eddb70b 2552 temp = I915_READ(reg);
8db9d77b
ZW		 2553 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2554
2555 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2556 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2557 DRM_DEBUG_KMS("FDI train 2 done.\n");
2558 break;
2559 }
8db9d77b 2560 }
e1a44743 2561 if (tries == 5)
5eddb70b 2562 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2563
2564 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2565
8db9d77b
ZW		 2566}
2567
0206e353 2568static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2569 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2570 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2571 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2572 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2573};
2574
2575/* The FDI link training functions for SNB/Cougarpoint. */
2576static void gen6_fdi_link_train(struct drm_crtc *crtc)
2577{
2578 struct drm_device *dev = crtc->dev;
2579 struct drm_i915_private *dev_priv = dev->dev_private;
2580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2581 int pipe = intel_crtc->pipe;
fa37d39e 2582 u32 reg, temp, i, retry;
8db9d77b 2583
e1a44743
AJ		 2584 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2585 for train result */
5eddb70b
CW		 2586 reg = FDI_RX_IMR(pipe);
2587 temp = I915_READ(reg);
e1a44743
AJ		 2588 temp &= ~FDI_RX_SYMBOL_LOCK;
2589 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2590 I915_WRITE(reg, temp);
2591
2592 POSTING_READ(reg);
e1a44743
AJ		 2593 udelay(150);
2594
8db9d77b 2595 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2596 reg = FDI_TX_CTL(pipe);
2597 temp = I915_READ(reg);
77ffb597
AJ		 2598 temp &= ~(7 << 19);
2599 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2600 temp &= ~FDI_LINK_TRAIN_NONE;
2601 temp |= FDI_LINK_TRAIN_PATTERN_1;
2602 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603 /* SNB-B */
2604 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2605 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2606
d74cf324
DV		 2607 I915_WRITE(FDI_RX_MISC(pipe),
2608 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2609
5eddb70b
CW		 2610 reg = FDI_RX_CTL(pipe);
2611 temp = I915_READ(reg);
8db9d77b
ZW		 2612 if (HAS_PCH_CPT(dev)) {
2613 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2614 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2615 } else {
2616 temp &= ~FDI_LINK_TRAIN_NONE;
2617 temp |= FDI_LINK_TRAIN_PATTERN_1;
2618 }
5eddb70b
CW		 2619 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2620
2621 POSTING_READ(reg);
8db9d77b
ZW		 2622 udelay(150);
2623
0206e353 2624 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2625 reg = FDI_TX_CTL(pipe);
2626 temp = I915_READ(reg);
8db9d77b
ZW		 2627 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2628 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2629 I915_WRITE(reg, temp);
2630
2631 POSTING_READ(reg);
8db9d77b
ZW		 2632 udelay(500);
2633
fa37d39e
SP		 2634 for (retry = 0; retry < 5; retry++) {
2635 reg = FDI_RX_IIR(pipe);
2636 temp = I915_READ(reg);
2637 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2638 if (temp & FDI_RX_BIT_LOCK) {
2639 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2640 DRM_DEBUG_KMS("FDI train 1 done.\n");
2641 break;
2642 }
2643 udelay(50);
8db9d77b 2644 }
fa37d39e
SP		 2645 if (retry < 5)
2646 break;
8db9d77b
ZW		 2647 }
2648 if (i == 4)
5eddb70b 2649 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2650
2651 /* Train 2 */
5eddb70b
CW		 2652 reg = FDI_TX_CTL(pipe);
2653 temp = I915_READ(reg);
8db9d77b
ZW		 2654 temp &= ~FDI_LINK_TRAIN_NONE;
2655 temp |= FDI_LINK_TRAIN_PATTERN_2;
2656 if (IS_GEN6(dev)) {
2657 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2658 /* SNB-B */
2659 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2660 }
5eddb70b 2661 I915_WRITE(reg, temp);
8db9d77b 2662
5eddb70b
CW		 2663 reg = FDI_RX_CTL(pipe);
2664 temp = I915_READ(reg);
8db9d77b
ZW		 2665 if (HAS_PCH_CPT(dev)) {
2666 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2667 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2668 } else {
2669 temp &= ~FDI_LINK_TRAIN_NONE;
2670 temp |= FDI_LINK_TRAIN_PATTERN_2;
2671 }
5eddb70b
CW		 2672 I915_WRITE(reg, temp);
2673
2674 POSTING_READ(reg);
8db9d77b
ZW		 2675 udelay(150);
2676
0206e353 2677 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2678 reg = FDI_TX_CTL(pipe);
2679 temp = I915_READ(reg);
8db9d77b
ZW		 2680 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2681 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2682 I915_WRITE(reg, temp);
2683
2684 POSTING_READ(reg);
8db9d77b
ZW		 2685 udelay(500);
2686
fa37d39e
SP		 2687 for (retry = 0; retry < 5; retry++) {
2688 reg = FDI_RX_IIR(pipe);
2689 temp = I915_READ(reg);
2690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2691 if (temp & FDI_RX_SYMBOL_LOCK) {
2692 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2693 DRM_DEBUG_KMS("FDI train 2 done.\n");
2694 break;
2695 }
2696 udelay(50);
8db9d77b 2697 }
fa37d39e
SP		 2698 if (retry < 5)
2699 break;
8db9d77b
ZW		 2700 }
2701 if (i == 4)
5eddb70b 2702 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2703
2704 DRM_DEBUG_KMS("FDI train done.\n");
2705}
2706
357555c0
JB		 2707/* Manual link training for Ivy Bridge A0 parts */
2708static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2709{
2710 struct drm_device *dev = crtc->dev;
2711 struct drm_i915_private *dev_priv = dev->dev_private;
2712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2713 int pipe = intel_crtc->pipe;
2714 u32 reg, temp, i;
2715
2716 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2717 for train result */
2718 reg = FDI_RX_IMR(pipe);
2719 temp = I915_READ(reg);
2720 temp &= ~FDI_RX_SYMBOL_LOCK;
2721 temp &= ~FDI_RX_BIT_LOCK;
2722 I915_WRITE(reg, temp);
2723
2724 POSTING_READ(reg);
2725 udelay(150);
2726
01a415fd
DV		 2727 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2728 I915_READ(FDI_RX_IIR(pipe)));
2729
357555c0
JB		 2730 /* enable CPU FDI TX and PCH FDI RX */
2731 reg = FDI_TX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 temp &= ~(7 << 19);
2734 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2735 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2736 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2737 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2738 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2739 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2740 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2741
d74cf324
DV		 2742 I915_WRITE(FDI_RX_MISC(pipe),
2743 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2744
357555c0
JB		 2745 reg = FDI_RX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 temp &= ~FDI_LINK_TRAIN_AUTO;
2748 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2749 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2750 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2751 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2752
2753 POSTING_READ(reg);
2754 udelay(150);
2755
0206e353 2756 for (i = 0; i < 4; i++) {
357555c0
JB		 2757 reg = FDI_TX_CTL(pipe);
2758 temp = I915_READ(reg);
2759 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2760 temp |= snb_b_fdi_train_param[i];
2761 I915_WRITE(reg, temp);
2762
2763 POSTING_READ(reg);
2764 udelay(500);
2765
2766 reg = FDI_RX_IIR(pipe);
2767 temp = I915_READ(reg);
2768 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2769
2770 if (temp & FDI_RX_BIT_LOCK ||
2771 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2772 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2773 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2774 break;
2775 }
2776 }
2777 if (i == 4)
2778 DRM_ERROR("FDI train 1 fail!\n");
2779
2780 /* Train 2 */
2781 reg = FDI_TX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2784 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2785 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2786 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2787 I915_WRITE(reg, temp);
2788
2789 reg = FDI_RX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2792 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2793 I915_WRITE(reg, temp);
2794
2795 POSTING_READ(reg);
2796 udelay(150);
2797
0206e353 2798 for (i = 0; i < 4; i++) {
357555c0
JB		 2799 reg = FDI_TX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2802 temp |= snb_b_fdi_train_param[i];
2803 I915_WRITE(reg, temp);
2804
2805 POSTING_READ(reg);
2806 udelay(500);
2807
2808 reg = FDI_RX_IIR(pipe);
2809 temp = I915_READ(reg);
2810 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2811
2812 if (temp & FDI_RX_SYMBOL_LOCK) {
2813 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2814 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2815 break;
2816 }
2817 }
2818 if (i == 4)
2819 DRM_ERROR("FDI train 2 fail!\n");
2820
2821 DRM_DEBUG_KMS("FDI train done.\n");
2822}
2823
88cefb6c 2824static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2825{
88cefb6c 2826 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2827 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2828 int pipe = intel_crtc->pipe;
5eddb70b 2829 u32 reg, temp;
79e53945 2830
c64e311e 2831
c98e9dcf 2832 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2833 reg = FDI_RX_CTL(pipe);
2834 temp = I915_READ(reg);
2835 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2836 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2837 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2838 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2839
2840 POSTING_READ(reg);
c98e9dcf
JB		 2841 udelay(200);
2842
2843 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2844 temp = I915_READ(reg);
2845 I915_WRITE(reg, temp | FDI_PCDCLK);
2846
2847 POSTING_READ(reg);
c98e9dcf
JB		 2848 udelay(200);
2849
20749730
PZ		 2850 /* Enable CPU FDI TX PLL, always on for Ironlake */
2851 reg = FDI_TX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2854 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2855
20749730
PZ		 2856 POSTING_READ(reg);
2857 udelay(100);
6be4a607 2858 }
0e23b99d
JB		 2859}
2860
88cefb6c
DV		 2861static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2862{
2863 struct drm_device *dev = intel_crtc->base.dev;
2864 struct drm_i915_private *dev_priv = dev->dev_private;
2865 int pipe = intel_crtc->pipe;
2866 u32 reg, temp;
2867
2868 /* Switch from PCDclk to Rawclk */
2869 reg = FDI_RX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2872
2873 /* Disable CPU FDI TX PLL */
2874 reg = FDI_TX_CTL(pipe);
2875 temp = I915_READ(reg);
2876 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2877
2878 POSTING_READ(reg);
2879 udelay(100);
2880
2881 reg = FDI_RX_CTL(pipe);
2882 temp = I915_READ(reg);
2883 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2884
2885 /* Wait for the clocks to turn off. */
2886 POSTING_READ(reg);
2887 udelay(100);
2888}
2889
0fc932b8
JB		 2890static void ironlake_fdi_disable(struct drm_crtc *crtc)
2891{
2892 struct drm_device *dev = crtc->dev;
2893 struct drm_i915_private *dev_priv = dev->dev_private;
2894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2895 int pipe = intel_crtc->pipe;
2896 u32 reg, temp;
2897
2898 /* disable CPU FDI tx and PCH FDI rx */
2899 reg = FDI_TX_CTL(pipe);
2900 temp = I915_READ(reg);
2901 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2902 POSTING_READ(reg);
2903
2904 reg = FDI_RX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~(0x7 << 16);
dfd07d72 2907 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2908 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2909
2910 POSTING_READ(reg);
2911 udelay(100);
2912
2913 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2914 if (HAS_PCH_IBX(dev)) {
2915 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2916 }
0fc932b8
JB		 2917
2918 /* still set train pattern 1 */
2919 reg = FDI_TX_CTL(pipe);
2920 temp = I915_READ(reg);
2921 temp &= ~FDI_LINK_TRAIN_NONE;
2922 temp |= FDI_LINK_TRAIN_PATTERN_1;
2923 I915_WRITE(reg, temp);
2924
2925 reg = FDI_RX_CTL(pipe);
2926 temp = I915_READ(reg);
2927 if (HAS_PCH_CPT(dev)) {
2928 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2929 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2930 } else {
2931 temp &= ~FDI_LINK_TRAIN_NONE;
2932 temp |= FDI_LINK_TRAIN_PATTERN_1;
2933 }
2934 /* BPC in FDI rx is consistent with that in PIPECONF */
2935 temp &= ~(0x07 << 16);
dfd07d72 2936 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2937 I915_WRITE(reg, temp);
2938
2939 POSTING_READ(reg);
2940 udelay(100);
2941}
2942
5bb61643
CW		 2943static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2944{
2945 struct drm_device *dev = crtc->dev;
2946 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2948 unsigned long flags;
2949 bool pending;
2950
10d83730
VS		 2951 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2952 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2953 return false;
2954
2955 spin_lock_irqsave(&dev->event_lock, flags);
2956 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2957 spin_unlock_irqrestore(&dev->event_lock, flags);
2958
2959 return pending;
2960}
2961
e6c3a2a6
CW		 2962static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2963{
0f91128d 2964 struct drm_device *dev = crtc->dev;
5bb61643 2965 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2966
2967 if (crtc->fb == NULL)
2968 return;
2969
2c10d571
DV		 2970 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2971
5bb61643
CW		 2972 wait_event(dev_priv->pending_flip_queue,
2973 !intel_crtc_has_pending_flip(crtc));
2974
0f91128d
CW		 2975 mutex_lock(&dev->struct_mutex);
2976 intel_finish_fb(crtc->fb);
2977 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2978}
2979
fc316cbe 2980static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2981{
2982 struct drm_device *dev = crtc->dev;
228d3e36 2983 struct intel_encoder *intel_encoder;
040484af
JB		 2984
2985 /*
2986 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2987 * must be driven by its own crtc; no sharing is possible.
2988 */
228d3e36 2989 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2990 switch (intel_encoder->type) {
040484af 2991 case INTEL_OUTPUT_EDP:
228d3e36 2992 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2993 return false;
2994 continue;
2995 }
2996 }
2997
2998 return true;
2999}
3000
fc316cbe
PZ		 3001static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3002{
3003 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3004}
3005
e615efe4
ED		 3006/* Program iCLKIP clock to the desired frequency */
3007static void lpt_program_iclkip(struct drm_crtc *crtc)
3008{
3009 struct drm_device *dev = crtc->dev;
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3011 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3012 u32 temp;
3013
09153000
DV		 3014 mutex_lock(&dev_priv->dpio_lock);
3015
e615efe4
ED		 3016 /* It is necessary to ungate the pixclk gate prior to programming
3017 * the divisors, and gate it back when it is done.
3018 */
3019 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3020
3021 /* Disable SSCCTL */
3022 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3023 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3024 SBI_SSCCTL_DISABLE,
3025 SBI_ICLK);
e615efe4
ED		 3026
3027 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3028 if (crtc->mode.clock == 20000) {
3029 auxdiv = 1;
3030 divsel = 0x41;
3031 phaseinc = 0x20;
3032 } else {
3033 /* The iCLK virtual clock root frequency is in MHz,
3034 * but the crtc->mode.clock in in KHz. To get the divisors,
3035 * it is necessary to divide one by another, so we
3036 * convert the virtual clock precision to KHz here for higher
3037 * precision.
3038 */
3039 u32 iclk_virtual_root_freq = 172800 * 1000;
3040 u32 iclk_pi_range = 64;
3041 u32 desired_divisor, msb_divisor_value, pi_value;
3042
3043 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3044 msb_divisor_value = desired_divisor / iclk_pi_range;
3045 pi_value = desired_divisor % iclk_pi_range;
3046
3047 auxdiv = 0;
3048 divsel = msb_divisor_value - 2;
3049 phaseinc = pi_value;
3050 }
3051
3052 /* This should not happen with any sane values */
3053 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3054 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3055 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3056 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3057
3058 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3059 crtc->mode.clock,
3060 auxdiv,
3061 divsel,
3062 phasedir,
3063 phaseinc);
3064
3065 /* Program SSCDIVINTPHASE6 */
988d6ee8 3066 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3067 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3068 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3069 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3070 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3071 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3072 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3073 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3074
3075 /* Program SSCAUXDIV */
988d6ee8 3076 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3077 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3078 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3079 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3080
3081 /* Enable modulator and associated divider */
988d6ee8 3082 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3083 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3084 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3085
3086 /* Wait for initialization time */
3087 udelay(24);
3088
3089 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3090
3091 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3092}
3093
f67a559d
JB		 3094/*
3095 * Enable PCH resources required for PCH ports:
3096 * - PCH PLLs
3097 * - FDI training & RX/TX
3098 * - update transcoder timings
3099 * - DP transcoding bits
3100 * - transcoder
3101 */
3102static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3103{
3104 struct drm_device *dev = crtc->dev;
3105 struct drm_i915_private *dev_priv = dev->dev_private;
3106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3107 int pipe = intel_crtc->pipe;
ee7b9f93 3108 u32 reg, temp;
2c07245f 3109
e7e164db
CW		 3110 assert_transcoder_disabled(dev_priv, pipe);
3111
cd986abb
DV		 3112 /* Write the TU size bits before fdi link training, so that error
3113 * detection works. */
3114 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3115 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3116
c98e9dcf 3117 /* For PCH output, training FDI link */
674cf967 3118 dev_priv->display.fdi_link_train(crtc);
2c07245f 3119
572deb37
DV		 3120 /* XXX: pch pll's can be enabled any time before we enable the PCH
3121 * transcoder, and we actually should do this to not upset any PCH
3122 * transcoder that already use the clock when we share it.
3123 *
3124 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3125 * unconditionally resets the pll - we need that to have the right LVDS
3126 * enable sequence. */
b6b4e185 3127 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3128
303b81e0 3129 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3130 u32 sel;
4b645f14 3131
c98e9dcf 3132 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3133 switch (pipe) {
3134 default:
3135 case 0:
3136 temp |= TRANSA_DPLL_ENABLE;
3137 sel = TRANSA_DPLLB_SEL;
3138 break;
3139 case 1:
3140 temp |= TRANSB_DPLL_ENABLE;
3141 sel = TRANSB_DPLLB_SEL;
3142 break;
3143 case 2:
3144 temp |= TRANSC_DPLL_ENABLE;
3145 sel = TRANSC_DPLLB_SEL;
3146 break;
d64311ab 3147 }
ee7b9f93
JB		 3148 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3149 temp |= sel;
3150 else
3151 temp &= ~sel;
c98e9dcf 3152 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3153 }
5eddb70b 3154
d9b6cb56
JB		 3155 /* set transcoder timing, panel must allow it */
3156 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3157 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3158 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3159 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3160
5eddb70b
CW		 3161 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3162 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3163 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3164 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3165
303b81e0 3166 intel_fdi_normal_train(crtc);
5e84e1a4 3167
c98e9dcf
JB		 3168 /* For PCH DP, enable TRANS_DP_CTL */
3169 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3170 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3171 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3172 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3173 reg = TRANS_DP_CTL(pipe);
3174 temp = I915_READ(reg);
3175 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3176 TRANS_DP_SYNC_MASK |
3177 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3178 temp |= (TRANS_DP_OUTPUT_ENABLE |
3179 TRANS_DP_ENH_FRAMING);
9325c9f0 3180 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3181
3182 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3183 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3184 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3185 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3186
3187 switch (intel_trans_dp_port_sel(crtc)) {
3188 case PCH_DP_B:
5eddb70b 3189 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3190 break;
3191 case PCH_DP_C:
5eddb70b 3192 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3193 break;
3194 case PCH_DP_D:
5eddb70b 3195 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3196 break;
3197 default:
e95d41e1 3198 BUG();
32f9d658 3199 }
2c07245f 3200
5eddb70b 3201 I915_WRITE(reg, temp);
6be4a607 3202 }
b52eb4dc 3203
b8a4f404 3204 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3205}
3206
1507e5bd
PZ		 3207static void lpt_pch_enable(struct drm_crtc *crtc)
3208{
3209 struct drm_device *dev = crtc->dev;
3210 struct drm_i915_private *dev_priv = dev->dev_private;
3211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3212 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3213
daed2dbb 3214 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3215
8c52b5e8 3216 lpt_program_iclkip(crtc);
1507e5bd 3217
0540e488 3218 /* Set transcoder timing. */
daed2dbb
PZ		 3219 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3220 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3221 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3222
daed2dbb
PZ		 3223 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3224 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3225 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3226 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3227
937bb610 3228 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3229}
3230
ee7b9f93
JB		 3231static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3232{
3233 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3234
3235 if (pll == NULL)
3236 return;
3237
3238 if (pll->refcount == 0) {
3239 WARN(1, "bad PCH PLL refcount\n");
3240 return;
3241 }
3242
3243 --pll->refcount;
3244 intel_crtc->pch_pll = NULL;
3245}
3246
3247static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3248{
3249 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3250 struct intel_pch_pll *pll;
3251 int i;
3252
3253 pll = intel_crtc->pch_pll;
3254 if (pll) {
3255 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3256 intel_crtc->base.base.id, pll->pll_reg);
3257 goto prepare;
3258 }
3259
98b6bd99
DV		 3260 if (HAS_PCH_IBX(dev_priv->dev)) {
3261 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3262 i = intel_crtc->pipe;
3263 pll = &dev_priv->pch_plls[i];
3264
3265 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3266 intel_crtc->base.base.id, pll->pll_reg);
3267
3268 goto found;
3269 }
3270
ee7b9f93
JB		 3271 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3272 pll = &dev_priv->pch_plls[i];
3273
3274 /* Only want to check enabled timings first */
3275 if (pll->refcount == 0)
3276 continue;
3277
3278 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3279 fp == I915_READ(pll->fp0_reg)) {
3280 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3281 intel_crtc->base.base.id,
3282 pll->pll_reg, pll->refcount, pll->active);
3283
3284 goto found;
3285 }
3286 }
3287
3288 /* Ok no matching timings, maybe there's a free one? */
3289 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3290 pll = &dev_priv->pch_plls[i];
3291 if (pll->refcount == 0) {
3292 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3293 intel_crtc->base.base.id, pll->pll_reg);
3294 goto found;
3295 }
3296 }
3297
3298 return NULL;
3299
3300found:
3301 intel_crtc->pch_pll = pll;
3302 pll->refcount++;
3303 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3304prepare: /* separate function? */
3305 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3306
e04c7350
CW		 3307 /* Wait for the clocks to stabilize before rewriting the regs */
3308 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3309 POSTING_READ(pll->pll_reg);
3310 udelay(150);
e04c7350
CW		 3311
3312 I915_WRITE(pll->fp0_reg, fp);
3313 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3314 pll->on = false;
3315 return pll;
3316}
3317
d4270e57
JB		 3318void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3319{
3320 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3321 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3322 u32 temp;
3323
3324 temp = I915_READ(dslreg);
3325 udelay(500);
3326 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3327 if (wait_for(I915_READ(dslreg) != temp, 5))
3328 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3329 }
3330}
3331
f67a559d
JB		 3332static void ironlake_crtc_enable(struct drm_crtc *crtc)
3333{
3334 struct drm_device *dev = crtc->dev;
3335 struct drm_i915_private *dev_priv = dev->dev_private;
3336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3337 struct intel_encoder *encoder;
f67a559d
JB		 3338 int pipe = intel_crtc->pipe;
3339 int plane = intel_crtc->plane;
3340 u32 temp;
3341 bool is_pch_port;
3342
08a48469
DV		 3343 WARN_ON(!crtc->enabled);
3344
f67a559d
JB		 3345 if (intel_crtc->active)
3346 return;
3347
3348 intel_crtc->active = true;
3349 intel_update_watermarks(dev);
3350
3351 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3352 temp = I915_READ(PCH_LVDS);
3353 if ((temp & LVDS_PORT_EN) == 0)
3354 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3355 }
3356
fc316cbe 3357 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3358
46b6f814 3359 if (is_pch_port) {
fff367c7
DV		 3360 /* Note: FDI PLL enabling _must_ be done before we enable the
3361 * cpu pipes, hence this is separate from all the other fdi/pch
3362 * enabling. */
88cefb6c 3363 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3364 } else {
3365 assert_fdi_tx_disabled(dev_priv, pipe);
3366 assert_fdi_rx_disabled(dev_priv, pipe);
3367 }
f67a559d 3368
bf49ec8c
DV		 3369 for_each_encoder_on_crtc(dev, crtc, encoder)
3370 if (encoder->pre_enable)
3371 encoder->pre_enable(encoder);
f67a559d
JB		 3372
3373 /* Enable panel fitting for LVDS */
3374 if (dev_priv->pch_pf_size &&
547dc041
JN		 3375 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3376 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3377 /* Force use of hard-coded filter coefficients
3378 * as some pre-programmed values are broken,
3379 * e.g. x201.
3380 */
13888d78
PZ		 3381 if (IS_IVYBRIDGE(dev))
3382 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3383 PF_PIPE_SEL_IVB(pipe));
3384 else
3385 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3386 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3387 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3388 }
3389
9c54c0dd
JB		 3390 /*
3391 * On ILK+ LUT must be loaded before the pipe is running but with
3392 * clocks enabled
3393 */
3394 intel_crtc_load_lut(crtc);
3395
f67a559d
JB		 3396 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3397 intel_enable_plane(dev_priv, plane, pipe);
3398
3399 if (is_pch_port)
3400 ironlake_pch_enable(crtc);
c98e9dcf 3401
d1ebd816 3402 mutex_lock(&dev->struct_mutex);
bed4a673 3403 intel_update_fbc(dev);
d1ebd816
BW		 3404 mutex_unlock(&dev->struct_mutex);
3405
6b383a7f 3406 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3407
fa5c73b1
DV		 3408 for_each_encoder_on_crtc(dev, crtc, encoder)
3409 encoder->enable(encoder);
61b77ddd
DV		 3410
3411 if (HAS_PCH_CPT(dev))
3412 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3413
3414 /*
3415 * There seems to be a race in PCH platform hw (at least on some
3416 * outputs) where an enabled pipe still completes any pageflip right
3417 * away (as if the pipe is off) instead of waiting for vblank. As soon
3418 * as the first vblank happend, everything works as expected. Hence just
3419 * wait for one vblank before returning to avoid strange things
3420 * happening.
3421 */
3422 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3423}
3424
4f771f10
PZ		 3425static void haswell_crtc_enable(struct drm_crtc *crtc)
3426{
3427 struct drm_device *dev = crtc->dev;
3428 struct drm_i915_private *dev_priv = dev->dev_private;
3429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3430 struct intel_encoder *encoder;
3431 int pipe = intel_crtc->pipe;
3432 int plane = intel_crtc->plane;
4f771f10
PZ		 3433 bool is_pch_port;
3434
3435 WARN_ON(!crtc->enabled);
3436
3437 if (intel_crtc->active)
3438 return;
3439
3440 intel_crtc->active = true;
3441 intel_update_watermarks(dev);
3442
fc316cbe 3443 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3444
83616634 3445 if (is_pch_port)
04945641 3446 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3447
3448 for_each_encoder_on_crtc(dev, crtc, encoder)
3449 if (encoder->pre_enable)
3450 encoder->pre_enable(encoder);
3451
1f544388 3452 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3453
1f544388 3454 /* Enable panel fitting for eDP */
547dc041
JN		 3455 if (dev_priv->pch_pf_size &&
3456 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3457 /* Force use of hard-coded filter coefficients
3458 * as some pre-programmed values are broken,
3459 * e.g. x201.
3460 */
54075a7d
PZ		 3461 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3462 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3463 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3464 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3465 }
3466
3467 /*
3468 * On ILK+ LUT must be loaded before the pipe is running but with
3469 * clocks enabled
3470 */
3471 intel_crtc_load_lut(crtc);
3472
1f544388 3473 intel_ddi_set_pipe_settings(crtc);
8228c251 3474 intel_ddi_enable_transcoder_func(crtc);
4f771f10
PZ		 3475
3476 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3477 intel_enable_plane(dev_priv, plane, pipe);
3478
3479 if (is_pch_port)
1507e5bd 3480 lpt_pch_enable(crtc);
4f771f10
PZ		 3481
3482 mutex_lock(&dev->struct_mutex);
3483 intel_update_fbc(dev);
3484 mutex_unlock(&dev->struct_mutex);
3485
3486 intel_crtc_update_cursor(crtc, true);
3487
3488 for_each_encoder_on_crtc(dev, crtc, encoder)
3489 encoder->enable(encoder);
3490
4f771f10
PZ		 3491 /*
3492 * There seems to be a race in PCH platform hw (at least on some
3493 * outputs) where an enabled pipe still completes any pageflip right
3494 * away (as if the pipe is off) instead of waiting for vblank. As soon
3495 * as the first vblank happend, everything works as expected. Hence just
3496 * wait for one vblank before returning to avoid strange things
3497 * happening.
3498 */
3499 intel_wait_for_vblank(dev, intel_crtc->pipe);
3500}
3501
6be4a607
JB		 3502static void ironlake_crtc_disable(struct drm_crtc *crtc)
3503{
3504 struct drm_device *dev = crtc->dev;
3505 struct drm_i915_private *dev_priv = dev->dev_private;
3506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3507 struct intel_encoder *encoder;
6be4a607
JB		 3508 int pipe = intel_crtc->pipe;
3509 int plane = intel_crtc->plane;
5eddb70b 3510 u32 reg, temp;
b52eb4dc 3511
ef9c3aee 3512
f7abfe8b
CW		 3513 if (!intel_crtc->active)
3514 return;
3515
ea9d758d
DV		 3516 for_each_encoder_on_crtc(dev, crtc, encoder)
3517 encoder->disable(encoder);
3518
e6c3a2a6 3519 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3520 drm_vblank_off(dev, pipe);
6b383a7f 3521 intel_crtc_update_cursor(crtc, false);
5eddb70b 3522
b24e7179 3523 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3524
973d04f9
CW		 3525 if (dev_priv->cfb_plane == plane)
3526 intel_disable_fbc(dev);
2c07245f 3527
b24e7179 3528 intel_disable_pipe(dev_priv, pipe);
32f9d658 3529
6be4a607 3530 /* Disable PF */
9db4a9c7
JB		 3531 I915_WRITE(PF_CTL(pipe), 0);
3532 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3533
bf49ec8c
DV		 3534 for_each_encoder_on_crtc(dev, crtc, encoder)
3535 if (encoder->post_disable)
3536 encoder->post_disable(encoder);
2c07245f 3537
0fc932b8 3538 ironlake_fdi_disable(crtc);
249c0e64 3539
b8a4f404 3540 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3541
6be4a607
JB		 3542 if (HAS_PCH_CPT(dev)) {
3543 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3544 reg = TRANS_DP_CTL(pipe);
3545 temp = I915_READ(reg);
3546 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3547 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3548 I915_WRITE(reg, temp);
6be4a607
JB		 3549
3550 /* disable DPLL_SEL */
3551 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3552 switch (pipe) {
3553 case 0:
d64311ab 3554 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3555 break;
3556 case 1:
6be4a607 3557 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3558 break;
3559 case 2:
4b645f14 3560 /* C shares PLL A or B */
d64311ab 3561 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3562 break;
3563 default:
3564 BUG(); /* wtf */
3565 }
6be4a607 3566 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3567 }
e3421a18 3568
6be4a607 3569 /* disable PCH DPLL */
ee7b9f93 3570 intel_disable_pch_pll(intel_crtc);
8db9d77b 3571
88cefb6c 3572 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3573
f7abfe8b 3574 intel_crtc->active = false;
6b383a7f 3575 intel_update_watermarks(dev);
d1ebd816
BW		 3576
3577 mutex_lock(&dev->struct_mutex);
6b383a7f 3578 intel_update_fbc(dev);
d1ebd816 3579 mutex_unlock(&dev->struct_mutex);
6be4a607 3580}
1b3c7a47 3581
4f771f10 3582static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3583{
4f771f10
PZ		 3584 struct drm_device *dev = crtc->dev;
3585 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3587 struct intel_encoder *encoder;
3588 int pipe = intel_crtc->pipe;
3589 int plane = intel_crtc->plane;
ad80a810 3590 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3591 bool is_pch_port;
ee7b9f93 3592
4f771f10
PZ		 3593 if (!intel_crtc->active)
3594 return;
3595
83616634
PZ		 3596 is_pch_port = haswell_crtc_driving_pch(crtc);
3597
4f771f10
PZ		 3598 for_each_encoder_on_crtc(dev, crtc, encoder)
3599 encoder->disable(encoder);
3600
3601 intel_crtc_wait_for_pending_flips(crtc);
3602 drm_vblank_off(dev, pipe);
3603 intel_crtc_update_cursor(crtc, false);
3604
3605 intel_disable_plane(dev_priv, plane, pipe);
3606
3607 if (dev_priv->cfb_plane == plane)
3608 intel_disable_fbc(dev);
3609
3610 intel_disable_pipe(dev_priv, pipe);
3611
ad80a810 3612 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3613
3614 /* Disable PF */
3615 I915_WRITE(PF_CTL(pipe), 0);
3616 I915_WRITE(PF_WIN_SZ(pipe), 0);
3617
1f544388 3618 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3619
3620 for_each_encoder_on_crtc(dev, crtc, encoder)
3621 if (encoder->post_disable)
3622 encoder->post_disable(encoder);
3623
83616634 3624 if (is_pch_port) {
ab4d966c 3625 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3626 intel_ddi_fdi_disable(crtc);
83616634 3627 }
4f771f10
PZ		 3628
3629 intel_crtc->active = false;
3630 intel_update_watermarks(dev);
3631
3632 mutex_lock(&dev->struct_mutex);
3633 intel_update_fbc(dev);
3634 mutex_unlock(&dev->struct_mutex);
3635}
3636
ee7b9f93
JB		 3637static void ironlake_crtc_off(struct drm_crtc *crtc)
3638{
3639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3640 intel_put_pch_pll(intel_crtc);
3641}
3642
6441ab5f
PZ		 3643static void haswell_crtc_off(struct drm_crtc *crtc)
3644{
a5c961d1
PZ		 3645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3646
3647 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3648 * start using it. */
1a240d4d 3649 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3650
6441ab5f
PZ		 3651 intel_ddi_put_crtc_pll(crtc);
3652}
3653
02e792fb
DV		 3654static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3655{
02e792fb 3656 if (!enable && intel_crtc->overlay) {
23f09ce3 3657 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3658 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3659
23f09ce3 3660 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3661 dev_priv->mm.interruptible = false;
3662 (void) intel_overlay_switch_off(intel_crtc->overlay);
3663 dev_priv->mm.interruptible = true;
23f09ce3 3664 mutex_unlock(&dev->struct_mutex);
02e792fb 3665 }
02e792fb 3666
5dcdbcb0
CW		 3667 /* Let userspace switch the overlay on again. In most cases userspace
3668 * has to recompute where to put it anyway.
3669 */
02e792fb
DV		 3670}
3671
61bc95c1
EE		 3672/**
3673 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3674 * cursor plane briefly if not already running after enabling the display
3675 * plane.
3676 * This workaround avoids occasional blank screens when self refresh is
3677 * enabled.
3678 */
3679static void
3680g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3681{
3682 u32 cntl = I915_READ(CURCNTR(pipe));
3683
3684 if ((cntl & CURSOR_MODE) == 0) {
3685 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3686
3687 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3688 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3689 intel_wait_for_vblank(dev_priv->dev, pipe);
3690 I915_WRITE(CURCNTR(pipe), cntl);
3691 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3692 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3693 }
3694}
3695
0b8765c6 3696static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3697{
3698 struct drm_device *dev = crtc->dev;
79e53945
JB		 3699 struct drm_i915_private *dev_priv = dev->dev_private;
3700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3701 struct intel_encoder *encoder;
79e53945 3702 int pipe = intel_crtc->pipe;
80824003 3703 int plane = intel_crtc->plane;
79e53945 3704
08a48469
DV		 3705 WARN_ON(!crtc->enabled);
3706
f7abfe8b
CW		 3707 if (intel_crtc->active)
3708 return;
3709
3710 intel_crtc->active = true;
6b383a7f
CW		 3711 intel_update_watermarks(dev);
3712
63d7bbe9 3713 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3714
3715 for_each_encoder_on_crtc(dev, crtc, encoder)
3716 if (encoder->pre_enable)
3717 encoder->pre_enable(encoder);
3718
040484af 3719 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3720 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3721 if (IS_G4X(dev))
3722 g4x_fixup_plane(dev_priv, pipe);
79e53945 3723
0b8765c6 3724 intel_crtc_load_lut(crtc);
bed4a673 3725 intel_update_fbc(dev);
79e53945 3726
0b8765c6
JB		 3727 /* Give the overlay scaler a chance to enable if it's on this pipe */
3728 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3729 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3730
fa5c73b1
DV		 3731 for_each_encoder_on_crtc(dev, crtc, encoder)
3732 encoder->enable(encoder);
0b8765c6 3733}
79e53945 3734
0b8765c6
JB		 3735static void i9xx_crtc_disable(struct drm_crtc *crtc)
3736{
3737 struct drm_device *dev = crtc->dev;
3738 struct drm_i915_private *dev_priv = dev->dev_private;
3739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3740 struct intel_encoder *encoder;
0b8765c6
JB		 3741 int pipe = intel_crtc->pipe;
3742 int plane = intel_crtc->plane;
24a1f16d 3743 u32 pctl;
b690e96c 3744
ef9c3aee 3745
f7abfe8b
CW		 3746 if (!intel_crtc->active)
3747 return;
3748
ea9d758d
DV		 3749 for_each_encoder_on_crtc(dev, crtc, encoder)
3750 encoder->disable(encoder);
3751
0b8765c6 3752 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3753 intel_crtc_wait_for_pending_flips(crtc);
3754 drm_vblank_off(dev, pipe);
0b8765c6 3755 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3756 intel_crtc_update_cursor(crtc, false);
0b8765c6 3757
973d04f9
CW		 3758 if (dev_priv->cfb_plane == plane)
3759 intel_disable_fbc(dev);
79e53945 3760
b24e7179 3761 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3762 intel_disable_pipe(dev_priv, pipe);
24a1f16d
MK		 3763
3764 /* Disable pannel fitter if it is on this pipe. */
3765 pctl = I915_READ(PFIT_CONTROL);
3766 if ((pctl & PFIT_ENABLE) &&
3767 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3768 I915_WRITE(PFIT_CONTROL, 0);
3769
63d7bbe9 3770 intel_disable_pll(dev_priv, pipe);
0b8765c6 3771
f7abfe8b 3772 intel_crtc->active = false;
6b383a7f
CW		 3773 intel_update_fbc(dev);
3774 intel_update_watermarks(dev);
0b8765c6
JB		 3775}
3776
ee7b9f93
JB		 3777static void i9xx_crtc_off(struct drm_crtc *crtc)
3778{
3779}
3780
976f8a20
DV		 3781static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3782 bool enabled)
2c07245f
ZW		 3783{
3784 struct drm_device *dev = crtc->dev;
3785 struct drm_i915_master_private *master_priv;
3786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3787 int pipe = intel_crtc->pipe;
79e53945
JB		 3788
3789 if (!dev->primary->master)
3790 return;
3791
3792 master_priv = dev->primary->master->driver_priv;
3793 if (!master_priv->sarea_priv)
3794 return;
3795
79e53945
JB		 3796 switch (pipe) {
3797 case 0:
3798 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3799 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3800 break;
3801 case 1:
3802 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3803 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3804 break;
3805 default:
9db4a9c7 3806 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3807 break;
3808 }
79e53945
JB		 3809}
3810
976f8a20
DV		 3811/**
3812 * Sets the power management mode of the pipe and plane.
3813 */
3814void intel_crtc_update_dpms(struct drm_crtc *crtc)
3815{
3816 struct drm_device *dev = crtc->dev;
3817 struct drm_i915_private *dev_priv = dev->dev_private;
3818 struct intel_encoder *intel_encoder;
3819 bool enable = false;
3820
3821 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3822 enable |= intel_encoder->connectors_active;
3823
3824 if (enable)
3825 dev_priv->display.crtc_enable(crtc);
3826 else
3827 dev_priv->display.crtc_disable(crtc);
3828
3829 intel_crtc_update_sarea(crtc, enable);
3830}
3831
cdd59983
CW		 3832static void intel_crtc_disable(struct drm_crtc *crtc)
3833{
cdd59983 3834 struct drm_device *dev = crtc->dev;
976f8a20 3835 struct drm_connector *connector;
ee7b9f93 3836 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3838
976f8a20
DV		 3839 /* crtc should still be enabled when we disable it. */
3840 WARN_ON(!crtc->enabled);
3841
7b9f35a6 3842 intel_crtc->eld_vld = false;
976f8a20
DV		 3843 dev_priv->display.crtc_disable(crtc);
3844 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3845 dev_priv->display.off(crtc);
3846
931872fc
CW		 3847 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3848 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3849
3850 if (crtc->fb) {
3851 mutex_lock(&dev->struct_mutex);
1690e1eb 3852 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3853 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3854 crtc->fb = NULL;
3855 }
3856
3857 /* Update computed state. */
3858 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3859 if (!connector->encoder || !connector->encoder->crtc)
3860 continue;
3861
3862 if (connector->encoder->crtc != crtc)
3863 continue;
3864
3865 connector->dpms = DRM_MODE_DPMS_OFF;
3866 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3867 }
3868}
3869
a261b246 3870void intel_modeset_disable(struct drm_device *dev)
79e53945 3871{
a261b246
DV		 3872 struct drm_crtc *crtc;
3873
3874 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3875 if (crtc->enabled)
3876 intel_crtc_disable(crtc);
3877 }
79e53945
JB		 3878}
3879
ea5b213a 3880void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3881{
4ef69c7a 3882 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3883
ea5b213a
CW		 3884 drm_encoder_cleanup(encoder);
3885 kfree(intel_encoder);
7e7d76c3
JB		 3886}
3887
5ab432ef
DV		 3888/* Simple dpms helper for encodres with just one connector, no cloning and only
3889 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3890 * state of the entire output pipe. */
3891void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3892{
5ab432ef
DV		 3893 if (mode == DRM_MODE_DPMS_ON) {
3894 encoder->connectors_active = true;
3895
b2cabb0e 3896 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3897 } else {
3898 encoder->connectors_active = false;
3899
b2cabb0e 3900 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3901 }
79e53945
JB		 3902}
3903
0a91ca29
DV		 3904/* Cross check the actual hw state with our own modeset state tracking (and it's
3905 * internal consistency). */
b980514c 3906static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3907{
0a91ca29
DV		 3908 if (connector->get_hw_state(connector)) {
3909 struct intel_encoder *encoder = connector->encoder;
3910 struct drm_crtc *crtc;
3911 bool encoder_enabled;
3912 enum pipe pipe;
3913
3914 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3915 connector->base.base.id,
3916 drm_get_connector_name(&connector->base));
3917
3918 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3919 "wrong connector dpms state\n");
3920 WARN(connector->base.encoder != &encoder->base,
3921 "active connector not linked to encoder\n");
3922 WARN(!encoder->connectors_active,
3923 "encoder->connectors_active not set\n");
3924
3925 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3926 WARN(!encoder_enabled, "encoder not enabled\n");
3927 if (WARN_ON(!encoder->base.crtc))
3928 return;
3929
3930 crtc = encoder->base.crtc;
3931
3932 WARN(!crtc->enabled, "crtc not enabled\n");
3933 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3934 WARN(pipe != to_intel_crtc(crtc)->pipe,
3935 "encoder active on the wrong pipe\n");
3936 }
79e53945
JB		 3937}
3938
5ab432ef
DV		 3939/* Even simpler default implementation, if there's really no special case to
3940 * consider. */
3941void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3942{
5ab432ef 3943 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3944
5ab432ef
DV		 3945 /* All the simple cases only support two dpms states. */
3946 if (mode != DRM_MODE_DPMS_ON)
3947 mode = DRM_MODE_DPMS_OFF;
d4270e57 3948
5ab432ef
DV		 3949 if (mode == connector->dpms)
3950 return;
3951
3952 connector->dpms = mode;
3953
3954 /* Only need to change hw state when actually enabled */
3955 if (encoder->base.crtc)
3956 intel_encoder_dpms(encoder, mode);
3957 else
8af6cf88 3958 WARN_ON(encoder->connectors_active != false);
0a91ca29 3959
b980514c 3960 intel_modeset_check_state(connector->dev);
79e53945
JB		 3961}
3962
f0947c37
DV		 3963/* Simple connector->get_hw_state implementation for encoders that support only
3964 * one connector and no cloning and hence the encoder state determines the state
3965 * of the connector. */
3966bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3967{
24929352 3968 enum pipe pipe = 0;
f0947c37 3969 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3970
f0947c37 3971 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3972}
3973
79e53945 3974static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3975 const struct drm_display_mode *mode,
79e53945
JB		 3976 struct drm_display_mode *adjusted_mode)
3977{
2c07245f 3978 struct drm_device *dev = crtc->dev;
89749350 3979
bad720ff 3980 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3981 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3982 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3983 return false;
2c07245f 3984 }
89749350 3985
f9bef081
DV		 3986 /* All interlaced capable intel hw wants timings in frames. Note though
3987 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3988 * timings, so we need to be careful not to clobber these.*/
3989 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3990 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3991
44f46b42
CW		 3992 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3993 * with a hsync front porch of 0.
3994 */
3995 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3996 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3997 return false;
3998
79e53945
JB		 3999 return true;
4000}
4001
25eb05fc
JB		 4002static int valleyview_get_display_clock_speed(struct drm_device *dev)
4003{
4004 return 400000; /* FIXME */
4005}
4006
e70236a8
JB		 4007static int i945_get_display_clock_speed(struct drm_device *dev)
4008{
4009 return 400000;
4010}
79e53945 4011
e70236a8 4012static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4013{
e70236a8
JB		 4014 return 333000;
4015}
79e53945 4016
e70236a8
JB		 4017static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4018{
4019 return 200000;
4020}
79e53945 4021
e70236a8
JB		 4022static int i915gm_get_display_clock_speed(struct drm_device *dev)
4023{
4024 u16 gcfgc = 0;
79e53945 4025
e70236a8
JB		 4026 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4027
4028 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4029 return 133000;
4030 else {
4031 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4032 case GC_DISPLAY_CLOCK_333_MHZ:
4033 return 333000;
4034 default:
4035 case GC_DISPLAY_CLOCK_190_200_MHZ:
4036 return 190000;
79e53945 4037 }
e70236a8
JB		 4038 }
4039}
4040
4041static int i865_get_display_clock_speed(struct drm_device *dev)
4042{
4043 return 266000;
4044}
4045
4046static int i855_get_display_clock_speed(struct drm_device *dev)
4047{
4048 u16 hpllcc = 0;
4049 /* Assume that the hardware is in the high speed state. This
4050 * should be the default.
4051 */
4052 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4053 case GC_CLOCK_133_200:
4054 case GC_CLOCK_100_200:
4055 return 200000;
4056 case GC_CLOCK_166_250:
4057 return 250000;
4058 case GC_CLOCK_100_133:
79e53945 4059 return 133000;
e70236a8 4060 }
79e53945 4061
e70236a8
JB		 4062 /* Shouldn't happen */
4063 return 0;
4064}
79e53945 4065
e70236a8
JB		 4066static int i830_get_display_clock_speed(struct drm_device *dev)
4067{
4068 return 133000;
79e53945
JB		 4069}
4070
2c07245f 4071static void
e69d0bc1 4072intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4073{
4074 while (*num > 0xffffff || *den > 0xffffff) {
4075 *num >>= 1;
4076 *den >>= 1;
4077 }
4078}
4079
e69d0bc1
DV		 4080void
4081intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4082 int pixel_clock, int link_clock,
4083 struct intel_link_m_n *m_n)
2c07245f 4084{
e69d0bc1 4085 m_n->tu = 64;
22ed1113
CW		 4086 m_n->gmch_m = bits_per_pixel * pixel_clock;
4087 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4088 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4089 m_n->link_m = pixel_clock;
4090 m_n->link_n = link_clock;
e69d0bc1 4091 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4092}
4093
a7615030
CW		 4094static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4095{
72bbe58c
KP		 4096 if (i915_panel_use_ssc >= 0)
4097 return i915_panel_use_ssc != 0;
4098 return dev_priv->lvds_use_ssc
435793df 4099 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4100}
4101
5a354204
JB		 4102/**
4103 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4104 * @crtc: CRTC structure
3b5c78a3 4105 * @mode: requested mode
5a354204
JB		 4106 *
4107 * A pipe may be connected to one or more outputs. Based on the depth of the
4108 * attached framebuffer, choose a good color depth to use on the pipe.
4109 *
4110 * If possible, match the pipe depth to the fb depth. In some cases, this
4111 * isn't ideal, because the connected output supports a lesser or restricted
4112 * set of depths. Resolve that here:
4113 * LVDS typically supports only 6bpc, so clamp down in that case
4114 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4115 * Displays may support a restricted set as well, check EDID and clamp as
4116 * appropriate.
3b5c78a3 4117 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4118 *
4119 * RETURNS:
4120 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4121 * true if they don't match).
4122 */
4123static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4124 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4125 unsigned int *pipe_bpp,
4126 struct drm_display_mode *mode)
5a354204
JB		 4127{
4128 struct drm_device *dev = crtc->dev;
4129 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4130 struct drm_connector *connector;
6c2b7c12 4131 struct intel_encoder *intel_encoder;
5a354204
JB		 4132 unsigned int display_bpc = UINT_MAX, bpc;
4133
4134 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4135 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4136
4137 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4138 unsigned int lvds_bpc;
4139
4140 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4141 LVDS_A3_POWER_UP)
4142 lvds_bpc = 8;
4143 else
4144 lvds_bpc = 6;
4145
4146 if (lvds_bpc < display_bpc) {
82820490 4147 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4148 display_bpc = lvds_bpc;
4149 }
4150 continue;
4151 }
4152
5a354204
JB		 4153 /* Not one of the known troublemakers, check the EDID */
4154 list_for_each_entry(connector, &dev->mode_config.connector_list,
4155 head) {
6c2b7c12 4156 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4157 continue;
4158
62ac41a6
JB		 4159 /* Don't use an invalid EDID bpc value */
4160 if (connector->display_info.bpc &&
4161 connector->display_info.bpc < display_bpc) {
82820490 4162 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4163 display_bpc = connector->display_info.bpc;
4164 }
4165 }
4166
2f4f649a
JN		 4167 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4168 /* Use VBT settings if we have an eDP panel */
4169 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4170
9a30a61f 4171 if (edp_bpc && edp_bpc < display_bpc) {
2f4f649a
JN		 4172 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4173 display_bpc = edp_bpc;
4174 }
4175 continue;
4176 }
4177
5a354204
JB		 4178 /*
4179 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4180 * through, clamp it down. (Note: >12bpc will be caught below.)
4181 */
4182 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4183 if (display_bpc > 8 && display_bpc < 12) {
82820490 4184 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4185 display_bpc = 12;
4186 } else {
82820490 4187 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4188 display_bpc = 8;
4189 }
4190 }
4191 }
4192
3b5c78a3
AJ		 4193 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4194 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4195 display_bpc = 6;
4196 }
4197
5a354204
JB		 4198 /*
4199 * We could just drive the pipe at the highest bpc all the time and
4200 * enable dithering as needed, but that costs bandwidth. So choose
4201 * the minimum value that expresses the full color range of the fb but
4202 * also stays within the max display bpc discovered above.
4203 */
4204
94352cf9 4205 switch (fb->depth) {
5a354204
JB		 4206 case 8:
4207 bpc = 8; /* since we go through a colormap */
4208 break;
4209 case 15:
4210 case 16:
4211 bpc = 6; /* min is 18bpp */
4212 break;
4213 case 24:
578393cd 4214 bpc = 8;
5a354204
JB		 4215 break;
4216 case 30:
578393cd 4217 bpc = 10;
5a354204
JB		 4218 break;
4219 case 48:
578393cd 4220 bpc = 12;
5a354204
JB		 4221 break;
4222 default:
4223 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4224 bpc = min((unsigned int)8, display_bpc);
4225 break;
4226 }
4227
578393cd
KP		 4228 display_bpc = min(display_bpc, bpc);
4229
82820490
AJ		 4230 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4231 bpc, display_bpc);
5a354204 4232
578393cd 4233 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4234
4235 return display_bpc != bpc;
4236}
4237
a0c4da24
JB		 4238static int vlv_get_refclk(struct drm_crtc *crtc)
4239{
4240 struct drm_device *dev = crtc->dev;
4241 struct drm_i915_private *dev_priv = dev->dev_private;
4242 int refclk = 27000; /* for DP & HDMI */
4243
4244 return 100000; /* only one validated so far */
4245
4246 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4247 refclk = 96000;
4248 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4249 if (intel_panel_use_ssc(dev_priv))
4250 refclk = 100000;
4251 else
4252 refclk = 96000;
4253 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4254 refclk = 100000;
4255 }
4256
4257 return refclk;
4258}
4259
c65d77d8
JB		 4260static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4261{
4262 struct drm_device *dev = crtc->dev;
4263 struct drm_i915_private *dev_priv = dev->dev_private;
4264 int refclk;
4265
a0c4da24
JB		 4266 if (IS_VALLEYVIEW(dev)) {
4267 refclk = vlv_get_refclk(crtc);
4268 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4269 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4270 refclk = dev_priv->lvds_ssc_freq * 1000;
4271 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4272 refclk / 1000);
4273 } else if (!IS_GEN2(dev)) {
4274 refclk = 96000;
4275 } else {
4276 refclk = 48000;
4277 }
4278
4279 return refclk;
4280}
4281
4282static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4283 intel_clock_t *clock)
4284{
4285 /* SDVO TV has fixed PLL values depend on its clock range,
4286 this mirrors vbios setting. */
4287 if (adjusted_mode->clock >= 100000
4288 && adjusted_mode->clock < 140500) {
4289 clock->p1 = 2;
4290 clock->p2 = 10;
4291 clock->n = 3;
4292 clock->m1 = 16;
4293 clock->m2 = 8;
4294 } else if (adjusted_mode->clock >= 140500
4295 && adjusted_mode->clock <= 200000) {
4296 clock->p1 = 1;
4297 clock->p2 = 10;
4298 clock->n = 6;
4299 clock->m1 = 12;
4300 clock->m2 = 8;
4301 }
4302}
4303
a7516a05
JB		 4304static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4305 intel_clock_t *clock,
4306 intel_clock_t *reduced_clock)
4307{
4308 struct drm_device *dev = crtc->dev;
4309 struct drm_i915_private *dev_priv = dev->dev_private;
4310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4311 int pipe = intel_crtc->pipe;
4312 u32 fp, fp2 = 0;
4313
4314 if (IS_PINEVIEW(dev)) {
4315 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4316 if (reduced_clock)
4317 fp2 = (1 << reduced_clock->n) << 16 |
4318 reduced_clock->m1 << 8 | reduced_clock->m2;
4319 } else {
4320 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4321 if (reduced_clock)
4322 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4323 reduced_clock->m2;
4324 }
4325
4326 I915_WRITE(FP0(pipe), fp);
4327
4328 intel_crtc->lowfreq_avail = false;
4329 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4330 reduced_clock && i915_powersave) {
4331 I915_WRITE(FP1(pipe), fp2);
4332 intel_crtc->lowfreq_avail = true;
4333 } else {
4334 I915_WRITE(FP1(pipe), fp);
4335 }
4336}
4337
a0c4da24
JB		 4338static void vlv_update_pll(struct drm_crtc *crtc,
4339 struct drm_display_mode *mode,
4340 struct drm_display_mode *adjusted_mode,
4341 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4342 int num_connectors)
a0c4da24
JB		 4343{
4344 struct drm_device *dev = crtc->dev;
4345 struct drm_i915_private *dev_priv = dev->dev_private;
4346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4347 int pipe = intel_crtc->pipe;
4348 u32 dpll, mdiv, pdiv;
4349 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4350 bool is_sdvo;
4351 u32 temp;
a0c4da24 4352
09153000
DV		 4353 mutex_lock(&dev_priv->dpio_lock);
4354
2a8f64ca
VP		 4355 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4356 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4357
2a8f64ca
VP		 4358 dpll = DPLL_VGA_MODE_DIS;
4359 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4360 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4361 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4362
4363 I915_WRITE(DPLL(pipe), dpll);
4364 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4365
4366 bestn = clock->n;
4367 bestm1 = clock->m1;
4368 bestm2 = clock->m2;
4369 bestp1 = clock->p1;
4370 bestp2 = clock->p2;
4371
2a8f64ca
VP		 4372 /*
4373 * In Valleyview PLL and program lane counter registers are exposed
4374 * through DPIO interface
4375 */
a0c4da24
JB		 4376 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4377 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4378 mdiv |= ((bestn << DPIO_N_SHIFT));
4379 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4380 mdiv |= (1 << DPIO_K_SHIFT);
4381 mdiv |= DPIO_ENABLE_CALIBRATION;
4382 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4383
4384 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4385
2a8f64ca 4386 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4387 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4388 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4389 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4390 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4391
2a8f64ca 4392 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4393
4394 dpll |= DPLL_VCO_ENABLE;
4395 I915_WRITE(DPLL(pipe), dpll);
4396 POSTING_READ(DPLL(pipe));
4397 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4398 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4399
2a8f64ca
VP		 4400 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4401
4402 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4403 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4404
4405 I915_WRITE(DPLL(pipe), dpll);
4406
4407 /* Wait for the clocks to stabilize. */
4408 POSTING_READ(DPLL(pipe));
4409 udelay(150);
a0c4da24 4410
2a8f64ca
VP		 4411 temp = 0;
4412 if (is_sdvo) {
4413 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4414 if (temp > 1)
4415 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4416 else
4417 temp = 0;
a0c4da24 4418 }
2a8f64ca
VP		 4419 I915_WRITE(DPLL_MD(pipe), temp);
4420 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4421
2a8f64ca
VP		 4422 /* Now program lane control registers */
4423 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4424 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4425 {
4426 temp = 0x1000C4;
4427 if(pipe == 1)
4428 temp |= (1 << 21);
4429 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4430 }
4431 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4432 {
4433 temp = 0x1000C4;
4434 if(pipe == 1)
4435 temp |= (1 << 21);
4436 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4437 }
09153000
DV		 4438
4439 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4440}
4441
eb1cbe48
DV		 4442static void i9xx_update_pll(struct drm_crtc *crtc,
4443 struct drm_display_mode *mode,
4444 struct drm_display_mode *adjusted_mode,
4445 intel_clock_t *clock, intel_clock_t *reduced_clock,
4446 int num_connectors)
4447{
4448 struct drm_device *dev = crtc->dev;
4449 struct drm_i915_private *dev_priv = dev->dev_private;
4450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4451 struct intel_encoder *encoder;
eb1cbe48
DV		 4452 int pipe = intel_crtc->pipe;
4453 u32 dpll;
4454 bool is_sdvo;
4455
2a8f64ca
VP		 4456 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4457
eb1cbe48
DV		 4458 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4459 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4460
4461 dpll = DPLL_VGA_MODE_DIS;
4462
4463 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4464 dpll |= DPLLB_MODE_LVDS;
4465 else
4466 dpll |= DPLLB_MODE_DAC_SERIAL;
4467 if (is_sdvo) {
4468 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4469 if (pixel_multiplier > 1) {
4470 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4471 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4472 }
4473 dpll |= DPLL_DVO_HIGH_SPEED;
4474 }
4475 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4476 dpll |= DPLL_DVO_HIGH_SPEED;
4477
4478 /* compute bitmask from p1 value */
4479 if (IS_PINEVIEW(dev))
4480 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4481 else {
4482 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4483 if (IS_G4X(dev) && reduced_clock)
4484 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4485 }
4486 switch (clock->p2) {
4487 case 5:
4488 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4489 break;
4490 case 7:
4491 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4492 break;
4493 case 10:
4494 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4495 break;
4496 case 14:
4497 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4498 break;
4499 }
4500 if (INTEL_INFO(dev)->gen >= 4)
4501 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4502
4503 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4504 dpll |= PLL_REF_INPUT_TVCLKINBC;
4505 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4506 /* XXX: just matching BIOS for now */
4507 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4508 dpll |= 3;
4509 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4510 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4511 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4512 else
4513 dpll |= PLL_REF_INPUT_DREFCLK;
4514
4515 dpll |= DPLL_VCO_ENABLE;
4516 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4517 POSTING_READ(DPLL(pipe));
4518 udelay(150);
4519
dafd226c
DV		 4520 for_each_encoder_on_crtc(dev, crtc, encoder)
4521 if (encoder->pre_pll_enable)
4522 encoder->pre_pll_enable(encoder);
eb1cbe48
DV		 4523
4524 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4525 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4526
4527 I915_WRITE(DPLL(pipe), dpll);
4528
4529 /* Wait for the clocks to stabilize. */
4530 POSTING_READ(DPLL(pipe));
4531 udelay(150);
4532
4533 if (INTEL_INFO(dev)->gen >= 4) {
4534 u32 temp = 0;
4535 if (is_sdvo) {
4536 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4537 if (temp > 1)
4538 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4539 else
4540 temp = 0;
4541 }
4542 I915_WRITE(DPLL_MD(pipe), temp);
4543 } else {
4544 /* The pixel multiplier can only be updated once the
4545 * DPLL is enabled and the clocks are stable.
4546 *
4547 * So write it again.
4548 */
4549 I915_WRITE(DPLL(pipe), dpll);
4550 }
4551}
4552
4553static void i8xx_update_pll(struct drm_crtc *crtc,
4554 struct drm_display_mode *adjusted_mode,
2a8f64ca 4555 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4556 int num_connectors)
4557{
4558 struct drm_device *dev = crtc->dev;
4559 struct drm_i915_private *dev_priv = dev->dev_private;
4560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4561 struct intel_encoder *encoder;
eb1cbe48
DV		 4562 int pipe = intel_crtc->pipe;
4563 u32 dpll;
4564
2a8f64ca
VP		 4565 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4566
eb1cbe48
DV		 4567 dpll = DPLL_VGA_MODE_DIS;
4568
4569 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4570 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4571 } else {
4572 if (clock->p1 == 2)
4573 dpll |= PLL_P1_DIVIDE_BY_TWO;
4574 else
4575 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4576 if (clock->p2 == 4)
4577 dpll |= PLL_P2_DIVIDE_BY_4;
4578 }
4579
83f377ab 4580 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4581 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4582 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4583 else
4584 dpll |= PLL_REF_INPUT_DREFCLK;
4585
4586 dpll |= DPLL_VCO_ENABLE;
4587 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4588 POSTING_READ(DPLL(pipe));
4589 udelay(150);
4590
dafd226c
DV		 4591 for_each_encoder_on_crtc(dev, crtc, encoder)
4592 if (encoder->pre_pll_enable)
4593 encoder->pre_pll_enable(encoder);
eb1cbe48 4594
5b5896e4
DV		 4595 I915_WRITE(DPLL(pipe), dpll);
4596
4597 /* Wait for the clocks to stabilize. */
4598 POSTING_READ(DPLL(pipe));
4599 udelay(150);
4600
eb1cbe48
DV		 4601 /* The pixel multiplier can only be updated once the
4602 * DPLL is enabled and the clocks are stable.
4603 *
4604 * So write it again.
4605 */
4606 I915_WRITE(DPLL(pipe), dpll);
4607}
4608
b0e77b9c
PZ		 4609static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4610 struct drm_display_mode *mode,
4611 struct drm_display_mode *adjusted_mode)
4612{
4613 struct drm_device *dev = intel_crtc->base.dev;
4614 struct drm_i915_private *dev_priv = dev->dev_private;
4615 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4616 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4617 uint32_t vsyncshift;
4618
4619 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4620 /* the chip adds 2 halflines automatically */
4621 adjusted_mode->crtc_vtotal -= 1;
4622 adjusted_mode->crtc_vblank_end -= 1;
4623 vsyncshift = adjusted_mode->crtc_hsync_start
4624 - adjusted_mode->crtc_htotal / 2;
4625 } else {
4626 vsyncshift = 0;
4627 }
4628
4629 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4630 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4631
fe2b8f9d 4632 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4633 (adjusted_mode->crtc_hdisplay - 1) |
4634 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4635 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4636 (adjusted_mode->crtc_hblank_start - 1) |
4637 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4638 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4639 (adjusted_mode->crtc_hsync_start - 1) |
4640 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4641
fe2b8f9d 4642 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4643 (adjusted_mode->crtc_vdisplay - 1) |
4644 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4645 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4646 (adjusted_mode->crtc_vblank_start - 1) |
4647 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4648 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4649 (adjusted_mode->crtc_vsync_start - 1) |
4650 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4651
b5e508d4
PZ		 4652 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4653 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4654 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4655 * bits. */
4656 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4657 (pipe == PIPE_B || pipe == PIPE_C))
4658 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4659
b0e77b9c
PZ		 4660 /* pipesrc controls the size that is scaled from, which should
4661 * always be the user's requested size.
4662 */
4663 I915_WRITE(PIPESRC(pipe),
4664 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4665}
4666
f564048e
EA		 4667static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4668 struct drm_display_mode *mode,
4669 struct drm_display_mode *adjusted_mode,
4670 int x, int y,
94352cf9 4671 struct drm_framebuffer *fb)
79e53945
JB		 4672{
4673 struct drm_device *dev = crtc->dev;
4674 struct drm_i915_private *dev_priv = dev->dev_private;
4675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4676 int pipe = intel_crtc->pipe;
80824003 4677 int plane = intel_crtc->plane;
c751ce4f 4678 int refclk, num_connectors = 0;
652c393a 4679 intel_clock_t clock, reduced_clock;
b0e77b9c 4680 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4681 bool ok, has_reduced_clock = false, is_sdvo = false;
4682 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4683 struct intel_encoder *encoder;
d4906093 4684 const intel_limit_t *limit;
5c3b82e2 4685 int ret;
79e53945 4686
6c2b7c12 4687 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4688 switch (encoder->type) {
79e53945
JB		 4689 case INTEL_OUTPUT_LVDS:
4690 is_lvds = true;
4691 break;
4692 case INTEL_OUTPUT_SDVO:
7d57382e 4693 case INTEL_OUTPUT_HDMI:
79e53945 4694 is_sdvo = true;
5eddb70b 4695 if (encoder->needs_tv_clock)
e2f0ba97 4696 is_tv = true;
79e53945 4697 break;
79e53945
JB		 4698 case INTEL_OUTPUT_TVOUT:
4699 is_tv = true;
4700 break;
a4fc5ed6
KP		 4701 case INTEL_OUTPUT_DISPLAYPORT:
4702 is_dp = true;
4703 break;
79e53945 4704 }
43565a06 4705
c751ce4f 4706 num_connectors++;
79e53945
JB		 4707 }
4708
c65d77d8 4709 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4710
d4906093
ML		 4711 /*
4712 * Returns a set of divisors for the desired target clock with the given
4713 * refclk, or FALSE. The returned values represent the clock equation:
4714 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4715 */
1b894b59 4716 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4717 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4718 &clock);
79e53945
JB		 4719 if (!ok) {
4720 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4721 return -EINVAL;
79e53945
JB		 4722 }
4723
cda4b7d3 4724 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4725 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4726
ddc9003c 4727 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4728 /*
4729 * Ensure we match the reduced clock's P to the target clock.
4730 * If the clocks don't match, we can't switch the display clock
4731 * by using the FP0/FP1. In such case we will disable the LVDS
4732 * downclock feature.
4733 */
ddc9003c 4734 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4735 dev_priv->lvds_downclock,
4736 refclk,
cec2f356 4737 &clock,
5eddb70b 4738 &reduced_clock);
7026d4ac
ZW		 4739 }
4740
c65d77d8
JB		 4741 if (is_sdvo && is_tv)
4742 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4743
eb1cbe48 4744 if (IS_GEN2(dev))
2a8f64ca
VP		 4745 i8xx_update_pll(crtc, adjusted_mode, &clock,
4746 has_reduced_clock ? &reduced_clock : NULL,
4747 num_connectors);
a0c4da24 4748 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4749 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4750 has_reduced_clock ? &reduced_clock : NULL,
4751 num_connectors);
79e53945 4752 else
eb1cbe48
DV		 4753 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4754 has_reduced_clock ? &reduced_clock : NULL,
4755 num_connectors);
79e53945
JB		 4756
4757 /* setup pipeconf */
5eddb70b 4758 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4759
4760 /* Set up the display plane register */
4761 dspcntr = DISPPLANE_GAMMA_ENABLE;
4762
da6ecc5d
JB		 4763 if (!IS_VALLEYVIEW(dev)) {
4764 if (pipe == 0)
4765 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4766 else
4767 dspcntr |= DISPPLANE_SEL_PIPE_B;
4768 }
79e53945 4769
a6c45cf0 4770 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4771 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4772 * core speed.
4773 *
4774 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4775 * pipe == 0 check?
4776 */
e70236a8
JB		 4777 if (mode->clock >
4778 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4779 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4780 else
5eddb70b 4781 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4782 }
4783
3b5c78a3 4784 /* default to 8bpc */
dfd07d72 4785 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
3b5c78a3 4786 if (is_dp) {
0c96c65b 4787 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4788 pipeconf |= PIPECONF_6BPC |
3b5c78a3
AJ		 4789 PIPECONF_DITHER_EN |
4790 PIPECONF_DITHER_TYPE_SP;
4791 }
4792 }
4793
19c03924
GB		 4794 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4795 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4796 pipeconf |= PIPECONF_6BPC |
19c03924
GB		 4797 PIPECONF_ENABLE |
4798 I965_PIPECONF_ACTIVE;
4799 }
4800 }
4801
28c97730 4802 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4803 drm_mode_debug_printmodeline(mode);
4804
a7516a05
JB		 4805 if (HAS_PIPE_CXSR(dev)) {
4806 if (intel_crtc->lowfreq_avail) {
28c97730 4807 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4808 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4809 } else {
28c97730 4810 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4811 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4812 }
4813 }
4814
617cf884 4815 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4816 if (!IS_GEN2(dev) &&
b0e77b9c 4817 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4818 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4819 else
617cf884 4820 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4821
b0e77b9c 4822 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4823
4824 /* pipesrc and dspsize control the size that is scaled from,
4825 * which should always be the user's requested size.
79e53945 4826 */
929c77fb
EA		 4827 I915_WRITE(DSPSIZE(plane),
4828 ((mode->vdisplay - 1) << 16) |
4829 (mode->hdisplay - 1));
4830 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4831
f564048e
EA		 4832 I915_WRITE(PIPECONF(pipe), pipeconf);
4833 POSTING_READ(PIPECONF(pipe));
929c77fb 4834 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4835
4836 intel_wait_for_vblank(dev, pipe);
4837
f564048e
EA		 4838 I915_WRITE(DSPCNTR(plane), dspcntr);
4839 POSTING_READ(DSPCNTR(plane));
4840
94352cf9 4841 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4842
4843 intel_update_watermarks(dev);
4844
f564048e
EA		 4845 return ret;
4846}
4847
dde86e2d 4848static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4849{
4850 struct drm_i915_private *dev_priv = dev->dev_private;
4851 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4852 struct intel_encoder *encoder;
13d83a67
JB		 4853 u32 temp;
4854 bool has_lvds = false;
199e5d79
KP		 4855 bool has_cpu_edp = false;
4856 bool has_pch_edp = false;
4857 bool has_panel = false;
99eb6a01
KP		 4858 bool has_ck505 = false;
4859 bool can_ssc = false;
13d83a67
JB		 4860
4861 /* We need to take the global config into account */
199e5d79
KP		 4862 list_for_each_entry(encoder, &mode_config->encoder_list,
4863 base.head) {
4864 switch (encoder->type) {
4865 case INTEL_OUTPUT_LVDS:
4866 has_panel = true;
4867 has_lvds = true;
4868 break;
4869 case INTEL_OUTPUT_EDP:
4870 has_panel = true;
4871 if (intel_encoder_is_pch_edp(&encoder->base))
4872 has_pch_edp = true;
4873 else
4874 has_cpu_edp = true;
4875 break;
13d83a67
JB		 4876 }
4877 }
4878
99eb6a01
KP		 4879 if (HAS_PCH_IBX(dev)) {
4880 has_ck505 = dev_priv->display_clock_mode;
4881 can_ssc = has_ck505;
4882 } else {
4883 has_ck505 = false;
4884 can_ssc = true;
4885 }
4886
4887 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4888 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4889 has_ck505);
13d83a67
JB		 4890
4891 /* Ironlake: try to setup display ref clock before DPLL
4892 * enabling. This is only under driver's control after
4893 * PCH B stepping, previous chipset stepping should be
4894 * ignoring this setting.
4895 */
4896 temp = I915_READ(PCH_DREF_CONTROL);
4897 /* Always enable nonspread source */
4898 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4899
99eb6a01
KP		 4900 if (has_ck505)
4901 temp |= DREF_NONSPREAD_CK505_ENABLE;
4902 else
4903 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4904
199e5d79
KP		 4905 if (has_panel) {
4906 temp &= ~DREF_SSC_SOURCE_MASK;
4907 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4908
199e5d79 4909 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4910 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4911 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4912 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4913 } else
4914 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4915
4916 /* Get SSC going before enabling the outputs */
4917 I915_WRITE(PCH_DREF_CONTROL, temp);
4918 POSTING_READ(PCH_DREF_CONTROL);
4919 udelay(200);
4920
13d83a67
JB		 4921 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4922
4923 /* Enable CPU source on CPU attached eDP */
199e5d79 4924 if (has_cpu_edp) {
99eb6a01 4925 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4926 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4927 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4928 }
13d83a67
JB		 4929 else
4930 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4931 } else
4932 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4933
4934 I915_WRITE(PCH_DREF_CONTROL, temp);
4935 POSTING_READ(PCH_DREF_CONTROL);
4936 udelay(200);
4937 } else {
4938 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4939
4940 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4941
4942 /* Turn off CPU output */
4943 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4944
4945 I915_WRITE(PCH_DREF_CONTROL, temp);
4946 POSTING_READ(PCH_DREF_CONTROL);
4947 udelay(200);
4948
4949 /* Turn off the SSC source */
4950 temp &= ~DREF_SSC_SOURCE_MASK;
4951 temp |= DREF_SSC_SOURCE_DISABLE;
4952
4953 /* Turn off SSC1 */
4954 temp &= ~ DREF_SSC1_ENABLE;
4955
13d83a67
JB		 4956 I915_WRITE(PCH_DREF_CONTROL, temp);
4957 POSTING_READ(PCH_DREF_CONTROL);
4958 udelay(200);
4959 }
4960}
4961
dde86e2d
PZ		 4962/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4963static void lpt_init_pch_refclk(struct drm_device *dev)
4964{
4965 struct drm_i915_private *dev_priv = dev->dev_private;
4966 struct drm_mode_config *mode_config = &dev->mode_config;
4967 struct intel_encoder *encoder;
4968 bool has_vga = false;
4969 bool is_sdv = false;
4970 u32 tmp;
4971
4972 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4973 switch (encoder->type) {
4974 case INTEL_OUTPUT_ANALOG:
4975 has_vga = true;
4976 break;
4977 }
4978 }
4979
4980 if (!has_vga)
4981 return;
4982
c00db246
DV		 4983 mutex_lock(&dev_priv->dpio_lock);
4984
dde86e2d
PZ		 4985 /* XXX: Rip out SDV support once Haswell ships for real. */
4986 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4987 is_sdv = true;
4988
4989 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4990 tmp &= ~SBI_SSCCTL_DISABLE;
4991 tmp |= SBI_SSCCTL_PATHALT;
4992 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4993
4994 udelay(24);
4995
4996 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4997 tmp &= ~SBI_SSCCTL_PATHALT;
4998 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4999
5000 if (!is_sdv) {
5001 tmp = I915_READ(SOUTH_CHICKEN2);
5002 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5003 I915_WRITE(SOUTH_CHICKEN2, tmp);
5004
5005 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5006 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5007 DRM_ERROR("FDI mPHY reset assert timeout\n");
5008
5009 tmp = I915_READ(SOUTH_CHICKEN2);
5010 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5011 I915_WRITE(SOUTH_CHICKEN2, tmp);
5012
5013 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5014 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5015 100))
5016 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5017 }
5018
5019 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5020 tmp &= ~(0xFF << 24);
5021 tmp |= (0x12 << 24);
5022 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5023
5024 if (!is_sdv) {
5025 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
5026 tmp &= ~(0x3 << 6);
5027 tmp |= (1 << 6) | (1 << 0);
5028 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
5029 }
5030
5031 if (is_sdv) {
5032 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5033 tmp |= 0x7FFF;
5034 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5035 }
5036
5037 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5038 tmp |= (1 << 11);
5039 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5040
5041 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5042 tmp |= (1 << 11);
5043 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5044
5045 if (is_sdv) {
5046 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5047 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5048 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5049
5050 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5051 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5052 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5053
5054 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5055 tmp |= (0x3F << 8);
5056 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5057
5058 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5059 tmp |= (0x3F << 8);
5060 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5061 }
5062
5063 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5064 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5065 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5066
5067 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5068 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5069 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5070
5071 if (!is_sdv) {
5072 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5073 tmp &= ~(7 << 13);
5074 tmp |= (5 << 13);
5075 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5076
5077 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5078 tmp &= ~(7 << 13);
5079 tmp |= (5 << 13);
5080 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5081 }
5082
5083 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5084 tmp &= ~0xFF;
5085 tmp |= 0x1C;
5086 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5087
5088 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5089 tmp &= ~0xFF;
5090 tmp |= 0x1C;
5091 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5092
5093 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5094 tmp &= ~(0xFF << 16);
5095 tmp |= (0x1C << 16);
5096 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5097
5098 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5099 tmp &= ~(0xFF << 16);
5100 tmp |= (0x1C << 16);
5101 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5102
5103 if (!is_sdv) {
5104 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5105 tmp |= (1 << 27);
5106 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5107
5108 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5109 tmp |= (1 << 27);
5110 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5111
5112 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5113 tmp &= ~(0xF << 28);
5114 tmp |= (4 << 28);
5115 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5116
5117 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5118 tmp &= ~(0xF << 28);
5119 tmp |= (4 << 28);
5120 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5121 }
5122
5123 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5124 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5125 tmp |= SBI_DBUFF0_ENABLE;
5126 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5127
5128 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5129}
5130
5131/*
5132 * Initialize reference clocks when the driver loads
5133 */
5134void intel_init_pch_refclk(struct drm_device *dev)
5135{
5136 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5137 ironlake_init_pch_refclk(dev);
5138 else if (HAS_PCH_LPT(dev))
5139 lpt_init_pch_refclk(dev);
5140}
5141
d9d444cb
JB		 5142static int ironlake_get_refclk(struct drm_crtc *crtc)
5143{
5144 struct drm_device *dev = crtc->dev;
5145 struct drm_i915_private *dev_priv = dev->dev_private;
5146 struct intel_encoder *encoder;
d9d444cb
JB		 5147 struct intel_encoder *edp_encoder = NULL;
5148 int num_connectors = 0;
5149 bool is_lvds = false;
5150
6c2b7c12 5151 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5152 switch (encoder->type) {
5153 case INTEL_OUTPUT_LVDS:
5154 is_lvds = true;
5155 break;
5156 case INTEL_OUTPUT_EDP:
5157 edp_encoder = encoder;
5158 break;
5159 }
5160 num_connectors++;
5161 }
5162
5163 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5164 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5165 dev_priv->lvds_ssc_freq);
5166 return dev_priv->lvds_ssc_freq * 1000;
5167 }
5168
5169 return 120000;
5170}
5171
c8203565 5172static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5173 struct drm_display_mode *adjusted_mode,
c8203565 5174 bool dither)
79e53945 5175{
c8203565 5176 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5178 int pipe = intel_crtc->pipe;
c8203565
PZ		 5179 uint32_t val;
5180
5181 val = I915_READ(PIPECONF(pipe));
5182
dfd07d72 5183 val &= ~PIPECONF_BPC_MASK;
c8203565
PZ		 5184 switch (intel_crtc->bpp) {
5185 case 18:
dfd07d72 5186 val |= PIPECONF_6BPC;
c8203565
PZ		 5187 break;
5188 case 24:
dfd07d72 5189 val |= PIPECONF_8BPC;
c8203565
PZ		 5190 break;
5191 case 30:
dfd07d72 5192 val |= PIPECONF_10BPC;
c8203565
PZ		 5193 break;
5194 case 36:
dfd07d72 5195 val |= PIPECONF_12BPC;
c8203565
PZ		 5196 break;
5197 default:
cc769b62
PZ		 5198 /* Case prevented by intel_choose_pipe_bpp_dither. */
5199 BUG();
c8203565
PZ		 5200 }
5201
5202 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5203 if (dither)
5204 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5205
5206 val &= ~PIPECONF_INTERLACE_MASK;
5207 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5208 val |= PIPECONF_INTERLACED_ILK;
5209 else
5210 val |= PIPECONF_PROGRESSIVE;
5211
3685a8f3
VS		 5212 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5213 val |= PIPECONF_COLOR_RANGE_SELECT;
5214 else
5215 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5216
c8203565
PZ		 5217 I915_WRITE(PIPECONF(pipe), val);
5218 POSTING_READ(PIPECONF(pipe));
5219}
5220
86d3efce
VS		 5221/*
5222 * Set up the pipe CSC unit.
5223 *
5224 * Currently only full range RGB to limited range RGB conversion
5225 * is supported, but eventually this should handle various
5226 * RGB<->YCbCr scenarios as well.
5227 */
5228static void intel_set_pipe_csc(struct drm_crtc *crtc,
5229 const struct drm_display_mode *adjusted_mode)
5230{
5231 struct drm_device *dev = crtc->dev;
5232 struct drm_i915_private *dev_priv = dev->dev_private;
5233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5234 int pipe = intel_crtc->pipe;
5235 uint16_t coeff = 0x7800; /* 1.0 */
5236
5237 /*
5238 * TODO: Check what kind of values actually come out of the pipe
5239 * with these coeff/postoff values and adjust to get the best
5240 * accuracy. Perhaps we even need to take the bpc value into
5241 * consideration.
5242 */
5243
5244 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5245 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5246
5247 /*
5248 * GY/GU and RY/RU should be the other way around according
5249 * to BSpec, but reality doesn't agree. Just set them up in
5250 * a way that results in the correct picture.
5251 */
5252 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5253 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5254
5255 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5256 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5257
5258 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5259 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5260
5261 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5262 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5263 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5264
5265 if (INTEL_INFO(dev)->gen > 6) {
5266 uint16_t postoff = 0;
5267
5268 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5269 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5270
5271 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5272 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5273 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5274
5275 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5276 } else {
5277 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5278
5279 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5280 mode |= CSC_BLACK_SCREEN_OFFSET;
5281
5282 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5283 }
5284}
5285
ee2b0b38
PZ		 5286static void haswell_set_pipeconf(struct drm_crtc *crtc,
5287 struct drm_display_mode *adjusted_mode,
5288 bool dither)
5289{
5290 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5292 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5293 uint32_t val;
5294
702e7a56 5295 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5296
5297 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5298 if (dither)
5299 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5300
5301 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5302 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5303 val |= PIPECONF_INTERLACED_ILK;
5304 else
5305 val |= PIPECONF_PROGRESSIVE;
5306
702e7a56
PZ		 5307 I915_WRITE(PIPECONF(cpu_transcoder), val);
5308 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5309}
5310
6591c6e4
PZ		 5311static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5312 struct drm_display_mode *adjusted_mode,
5313 intel_clock_t *clock,
5314 bool *has_reduced_clock,
5315 intel_clock_t *reduced_clock)
5316{
5317 struct drm_device *dev = crtc->dev;
5318 struct drm_i915_private *dev_priv = dev->dev_private;
5319 struct intel_encoder *intel_encoder;
5320 int refclk;
d4906093 5321 const intel_limit_t *limit;
6591c6e4 5322 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5323
6591c6e4
PZ		 5324 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5325 switch (intel_encoder->type) {
79e53945
JB		 5326 case INTEL_OUTPUT_LVDS:
5327 is_lvds = true;
5328 break;
5329 case INTEL_OUTPUT_SDVO:
7d57382e 5330 case INTEL_OUTPUT_HDMI:
79e53945 5331 is_sdvo = true;
6591c6e4 5332 if (intel_encoder->needs_tv_clock)
e2f0ba97 5333 is_tv = true;
79e53945 5334 break;
79e53945
JB		 5335 case INTEL_OUTPUT_TVOUT:
5336 is_tv = true;
5337 break;
79e53945
JB		 5338 }
5339 }
5340
d9d444cb 5341 refclk = ironlake_get_refclk(crtc);
79e53945 5342
d4906093
ML		 5343 /*
5344 * Returns a set of divisors for the desired target clock with the given
5345 * refclk, or FALSE. The returned values represent the clock equation:
5346 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5347 */
1b894b59 5348 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5349 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5350 clock);
5351 if (!ret)
5352 return false;
cda4b7d3 5353
ddc9003c 5354 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5355 /*
5356 * Ensure we match the reduced clock's P to the target clock.
5357 * If the clocks don't match, we can't switch the display clock
5358 * by using the FP0/FP1. In such case we will disable the LVDS
5359 * downclock feature.
5360 */
6591c6e4
PZ		 5361 *has_reduced_clock = limit->find_pll(limit, crtc,
5362 dev_priv->lvds_downclock,
5363 refclk,
5364 clock,
5365 reduced_clock);
652c393a 5366 }
61e9653f
DV		 5367
5368 if (is_sdvo && is_tv)
6591c6e4
PZ		 5369 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5370
5371 return true;
5372}
5373
01a415fd
DV		 5374static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5375{
5376 struct drm_i915_private *dev_priv = dev->dev_private;
5377 uint32_t temp;
5378
5379 temp = I915_READ(SOUTH_CHICKEN1);
5380 if (temp & FDI_BC_BIFURCATION_SELECT)
5381 return;
5382
5383 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5384 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5385
5386 temp |= FDI_BC_BIFURCATION_SELECT;
5387 DRM_DEBUG_KMS("enabling fdi C rx\n");
5388 I915_WRITE(SOUTH_CHICKEN1, temp);
5389 POSTING_READ(SOUTH_CHICKEN1);
5390}
5391
5392static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5393{
5394 struct drm_device *dev = intel_crtc->base.dev;
5395 struct drm_i915_private *dev_priv = dev->dev_private;
5396 struct intel_crtc *pipe_B_crtc =
5397 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5398
5399 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5400 intel_crtc->pipe, intel_crtc->fdi_lanes);
5401 if (intel_crtc->fdi_lanes > 4) {
5402 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5403 intel_crtc->pipe, intel_crtc->fdi_lanes);
5404 /* Clamp lanes to avoid programming the hw with bogus values. */
5405 intel_crtc->fdi_lanes = 4;
5406
5407 return false;
5408 }
5409
7eb552ae 5410 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5411 return true;
5412
5413 switch (intel_crtc->pipe) {
5414 case PIPE_A:
5415 return true;
5416 case PIPE_B:
5417 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5418 intel_crtc->fdi_lanes > 2) {
5419 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5420 intel_crtc->pipe, intel_crtc->fdi_lanes);
5421 /* Clamp lanes to avoid programming the hw with bogus values. */
5422 intel_crtc->fdi_lanes = 2;
5423
5424 return false;
5425 }
5426
5427 if (intel_crtc->fdi_lanes > 2)
5428 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5429 else
5430 cpt_enable_fdi_bc_bifurcation(dev);
5431
5432 return true;
5433 case PIPE_C:
5434 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5435 if (intel_crtc->fdi_lanes > 2) {
5436 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5437 intel_crtc->pipe, intel_crtc->fdi_lanes);
5438 /* Clamp lanes to avoid programming the hw with bogus values. */
5439 intel_crtc->fdi_lanes = 2;
5440
5441 return false;
5442 }
5443 } else {
5444 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5445 return false;
5446 }
5447
5448 cpt_enable_fdi_bc_bifurcation(dev);
5449
5450 return true;
5451 default:
5452 BUG();
5453 }
5454}
5455
d4b1931c
PZ		 5456int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5457{
5458 /*
5459 * Account for spread spectrum to avoid
5460 * oversubscribing the link. Max center spread
5461 * is 2.5%; use 5% for safety's sake.
5462 */
5463 u32 bps = target_clock * bpp * 21 / 20;
5464 return bps / (link_bw * 8) + 1;
5465}
5466
f48d8f23
PZ		 5467static void ironlake_set_m_n(struct drm_crtc *crtc,
5468 struct drm_display_mode *mode,
5469 struct drm_display_mode *adjusted_mode)
79e53945
JB		 5470{
5471 struct drm_device *dev = crtc->dev;
5472 struct drm_i915_private *dev_priv = dev->dev_private;
5473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5474 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5475 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
e69d0bc1 5476 struct intel_link_m_n m_n = {0};
f48d8f23
PZ		 5477 int target_clock, pixel_multiplier, lane, link_bw;
5478 bool is_dp = false, is_cpu_edp = false;
79e53945 5479
f48d8f23
PZ		 5480 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5481 switch (intel_encoder->type) {
a4fc5ed6
KP		 5482 case INTEL_OUTPUT_DISPLAYPORT:
5483 is_dp = true;
5484 break;
32f9d658 5485 case INTEL_OUTPUT_EDP:
e3aef172 5486 is_dp = true;
f48d8f23 5487 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5488 is_cpu_edp = true;
f48d8f23 5489 edp_encoder = intel_encoder;
32f9d658 5490 break;
79e53945 5491 }
79e53945 5492 }
61e9653f 5493
2c07245f 5494 /* FDI link */
8febb297
EA		 5495 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5496 lane = 0;
5497 /* CPU eDP doesn't require FDI link, so just set DP M/N
5498 according to current link config */
e3aef172 5499 if (is_cpu_edp) {
e3aef172 5500 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5501 } else {
8febb297
EA		 5502 /* FDI is a binary signal running at ~2.7GHz, encoding
5503 * each output octet as 10 bits. The actual frequency
5504 * is stored as a divider into a 100MHz clock, and the
5505 * mode pixel clock is stored in units of 1KHz.
5506 * Hence the bw of each lane in terms of the mode signal
5507 * is:
5508 */
5509 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5510 }
58a27471 5511
94bf2ced
DV		 5512 /* [e]DP over FDI requires target mode clock instead of link clock. */
5513 if (edp_encoder)
5514 target_clock = intel_edp_target_clock(edp_encoder, mode);
5515 else if (is_dp)
5516 target_clock = mode->clock;
5517 else
5518 target_clock = adjusted_mode->clock;
5519
d4b1931c
PZ		 5520 if (!lane)
5521 lane = ironlake_get_lanes_required(target_clock, link_bw,
5522 intel_crtc->bpp);
2c07245f 5523
8febb297
EA		 5524 intel_crtc->fdi_lanes = lane;
5525
5526 if (pixel_multiplier > 1)
5527 link_bw *= pixel_multiplier;
e69d0bc1 5528 intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
8febb297 5529
afe2fcf5
PZ		 5530 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5531 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5532 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5533 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5534}
5535
de13a2e3
PZ		 5536static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5537 struct drm_display_mode *adjusted_mode,
5538 intel_clock_t *clock, u32 fp)
79e53945 5539{
de13a2e3 5540 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5541 struct drm_device *dev = crtc->dev;
5542 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5543 struct intel_encoder *intel_encoder;
5544 uint32_t dpll;
5545 int factor, pixel_multiplier, num_connectors = 0;
5546 bool is_lvds = false, is_sdvo = false, is_tv = false;
5547 bool is_dp = false, is_cpu_edp = false;
79e53945 5548
de13a2e3
PZ		 5549 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5550 switch (intel_encoder->type) {
79e53945
JB		 5551 case INTEL_OUTPUT_LVDS:
5552 is_lvds = true;
5553 break;
5554 case INTEL_OUTPUT_SDVO:
7d57382e 5555 case INTEL_OUTPUT_HDMI:
79e53945 5556 is_sdvo = true;
de13a2e3 5557 if (intel_encoder->needs_tv_clock)
e2f0ba97 5558 is_tv = true;
79e53945 5559 break;
79e53945
JB		 5560 case INTEL_OUTPUT_TVOUT:
5561 is_tv = true;
5562 break;
a4fc5ed6
KP		 5563 case INTEL_OUTPUT_DISPLAYPORT:
5564 is_dp = true;
5565 break;
32f9d658 5566 case INTEL_OUTPUT_EDP:
e3aef172 5567 is_dp = true;
de13a2e3 5568 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5569 is_cpu_edp = true;
32f9d658 5570 break;
79e53945 5571 }
43565a06 5572
c751ce4f 5573 num_connectors++;
79e53945 5574 }
79e53945 5575
c1858123 5576 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5577 factor = 21;
5578 if (is_lvds) {
5579 if ((intel_panel_use_ssc(dev_priv) &&
5580 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5581 intel_is_dual_link_lvds(dev))
8febb297
EA		 5582 factor = 25;
5583 } else if (is_sdvo && is_tv)
5584 factor = 20;
c1858123 5585
de13a2e3 5586 if (clock->m < factor * clock->n)
8febb297 5587 fp |= FP_CB_TUNE;
2c07245f 5588
5eddb70b 5589 dpll = 0;
2c07245f 5590
a07d6787
EA		 5591 if (is_lvds)
5592 dpll |= DPLLB_MODE_LVDS;
5593 else
5594 dpll |= DPLLB_MODE_DAC_SERIAL;
5595 if (is_sdvo) {
de13a2e3 5596 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5597 if (pixel_multiplier > 1) {
5598 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5599 }
a07d6787
EA		 5600 dpll |= DPLL_DVO_HIGH_SPEED;
5601 }
e3aef172 5602 if (is_dp && !is_cpu_edp)
a07d6787 5603 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5604
a07d6787 5605 /* compute bitmask from p1 value */
de13a2e3 5606 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5607 /* also FPA1 */
de13a2e3 5608 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5609
de13a2e3 5610 switch (clock->p2) {
a07d6787
EA		 5611 case 5:
5612 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5613 break;
5614 case 7:
5615 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5616 break;
5617 case 10:
5618 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5619 break;
5620 case 14:
5621 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5622 break;
79e53945
JB		 5623 }
5624
43565a06
KH		 5625 if (is_sdvo && is_tv)
5626 dpll |= PLL_REF_INPUT_TVCLKINBC;
5627 else if (is_tv)
79e53945 5628 /* XXX: just matching BIOS for now */
43565a06 5629 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5630 dpll |= 3;
a7615030 5631 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5632 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5633 else
5634 dpll |= PLL_REF_INPUT_DREFCLK;
5635
de13a2e3
PZ		 5636 return dpll;
5637}
5638
5639static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5640 struct drm_display_mode *mode,
5641 struct drm_display_mode *adjusted_mode,
5642 int x, int y,
5643 struct drm_framebuffer *fb)
5644{
5645 struct drm_device *dev = crtc->dev;
5646 struct drm_i915_private *dev_priv = dev->dev_private;
5647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5648 int pipe = intel_crtc->pipe;
5649 int plane = intel_crtc->plane;
5650 int num_connectors = 0;
5651 intel_clock_t clock, reduced_clock;
5652 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5653 bool ok, has_reduced_clock = false;
5654 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5655 struct intel_encoder *encoder;
de13a2e3 5656 int ret;
01a415fd 5657 bool dither, fdi_config_ok;
de13a2e3
PZ		 5658
5659 for_each_encoder_on_crtc(dev, crtc, encoder) {
5660 switch (encoder->type) {
5661 case INTEL_OUTPUT_LVDS:
5662 is_lvds = true;
5663 break;
de13a2e3
PZ		 5664 case INTEL_OUTPUT_DISPLAYPORT:
5665 is_dp = true;
5666 break;
5667 case INTEL_OUTPUT_EDP:
5668 is_dp = true;
e2f12b07 5669 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5670 is_cpu_edp = true;
5671 break;
5672 }
5673
5674 num_connectors++;
a07d6787 5675 }
79e53945 5676
5dc5298b
PZ		 5677 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5678 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5679
de13a2e3
PZ		 5680 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5681 &has_reduced_clock, &reduced_clock);
5682 if (!ok) {
5683 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5684 return -EINVAL;
79e53945
JB		 5685 }
5686
de13a2e3
PZ		 5687 /* Ensure that the cursor is valid for the new mode before changing... */
5688 intel_crtc_update_cursor(crtc, true);
5689
5690 /* determine panel color depth */
c8241969
JN		 5691 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5692 adjusted_mode);
de13a2e3
PZ		 5693 if (is_lvds && dev_priv->lvds_dither)
5694 dither = true;
5695
5696 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5697 if (has_reduced_clock)
5698 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5699 reduced_clock.m2;
5700
5701 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
79e53945 5702
f7cb34d4 5703 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5704 drm_mode_debug_printmodeline(mode);
5705
5dc5298b
PZ		 5706 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5707 if (!is_cpu_edp) {
ee7b9f93 5708 struct intel_pch_pll *pll;
4b645f14 5709
ee7b9f93
JB		 5710 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5711 if (pll == NULL) {
5712 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5713 pipe);
4b645f14
JB		 5714 return -EINVAL;
5715 }
ee7b9f93
JB		 5716 } else
5717 intel_put_pch_pll(intel_crtc);
79e53945 5718
2f0c2ad1 5719 if (is_dp && !is_cpu_edp)
a4fc5ed6 5720 intel_dp_set_m_n(crtc, mode, adjusted_mode);
79e53945 5721
dafd226c
DV		 5722 for_each_encoder_on_crtc(dev, crtc, encoder)
5723 if (encoder->pre_pll_enable)
5724 encoder->pre_pll_enable(encoder);
79e53945 5725
ee7b9f93
JB		 5726 if (intel_crtc->pch_pll) {
5727 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5728
32f9d658 5729 /* Wait for the clocks to stabilize. */
ee7b9f93 5730 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5731 udelay(150);
5732
8febb297
EA		 5733 /* The pixel multiplier can only be updated once the
5734 * DPLL is enabled and the clocks are stable.
5735 *
5736 * So write it again.
5737 */
ee7b9f93 5738 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5739 }
79e53945 5740
5eddb70b 5741 intel_crtc->lowfreq_avail = false;
ee7b9f93 5742 if (intel_crtc->pch_pll) {
4b645f14 5743 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5744 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5745 intel_crtc->lowfreq_avail = true;
4b645f14 5746 } else {
ee7b9f93 5747 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5748 }
5749 }
5750
b0e77b9c 5751 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5752
01a415fd
DV		 5753 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5754 * ironlake_check_fdi_lanes. */
f48d8f23 5755 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5756
01a415fd 5757 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5758
c8203565 5759 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5760
9d0498a2 5761 intel_wait_for_vblank(dev, pipe);
79e53945 5762
a1f9e77e
PZ		 5763 /* Set up the display plane register */
5764 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5765 POSTING_READ(DSPCNTR(plane));
79e53945 5766
94352cf9 5767 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5768
5769 intel_update_watermarks(dev);
5770
1f8eeabf
ED		 5771 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5772
01a415fd 5773 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5774}
5775
d6dd9eb1
DV		 5776static void haswell_modeset_global_resources(struct drm_device *dev)
5777{
5778 struct drm_i915_private *dev_priv = dev->dev_private;
5779 bool enable = false;
5780 struct intel_crtc *crtc;
5781 struct intel_encoder *encoder;
5782
5783 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5784 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5785 enable = true;
5786 /* XXX: Should check for edp transcoder here, but thanks to init
5787 * sequence that's not yet available. Just in case desktop eDP
5788 * on PORT D is possible on haswell, too. */
5789 }
5790
5791 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5792 base.head) {
5793 if (encoder->type != INTEL_OUTPUT_EDP &&
5794 encoder->connectors_active)
5795 enable = true;
5796 }
5797
5798 /* Even the eDP panel fitter is outside the always-on well. */
5799 if (dev_priv->pch_pf_size)
5800 enable = true;
5801
5802 intel_set_power_well(dev, enable);
5803}
5804
09b4ddf9
PZ		 5805static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5806 struct drm_display_mode *mode,
5807 struct drm_display_mode *adjusted_mode,
5808 int x, int y,
5809 struct drm_framebuffer *fb)
5810{
5811 struct drm_device *dev = crtc->dev;
5812 struct drm_i915_private *dev_priv = dev->dev_private;
5813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5814 int pipe = intel_crtc->pipe;
5815 int plane = intel_crtc->plane;
5816 int num_connectors = 0;
ed7ef439 5817 bool is_dp = false, is_cpu_edp = false;
09b4ddf9 5818 struct intel_encoder *encoder;
09b4ddf9
PZ		 5819 int ret;
5820 bool dither;
5821
5822 for_each_encoder_on_crtc(dev, crtc, encoder) {
5823 switch (encoder->type) {
09b4ddf9
PZ		 5824 case INTEL_OUTPUT_DISPLAYPORT:
5825 is_dp = true;
5826 break;
5827 case INTEL_OUTPUT_EDP:
5828 is_dp = true;
5829 if (!intel_encoder_is_pch_edp(&encoder->base))
5830 is_cpu_edp = true;
5831 break;
5832 }
5833
5834 num_connectors++;
5835 }
5836
5dc5298b
PZ		 5837 /* We are not sure yet this won't happen. */
5838 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5839 INTEL_PCH_TYPE(dev));
5840
5841 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5842 num_connectors, pipe_name(pipe));
5843
702e7a56 5844 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5845 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5846
5847 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5848
6441ab5f
PZ		 5849 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5850 return -EINVAL;
5851
09b4ddf9
PZ		 5852 /* Ensure that the cursor is valid for the new mode before changing... */
5853 intel_crtc_update_cursor(crtc, true);
5854
5855 /* determine panel color depth */
c8241969
JN		 5856 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5857 adjusted_mode);
09b4ddf9 5858
09b4ddf9
PZ		 5859 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5860 drm_mode_debug_printmodeline(mode);
5861
ed7ef439 5862 if (is_dp && !is_cpu_edp)
09b4ddf9 5863 intel_dp_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9
PZ		 5864
5865 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5866
5867 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5868
1eb8dfec
PZ		 5869 if (!is_dp || is_cpu_edp)
5870 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5871
ee2b0b38 5872 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5873
86d3efce
VS		 5874 intel_set_pipe_csc(crtc, adjusted_mode);
5875
09b4ddf9 5876 /* Set up the display plane register */
86d3efce 5877 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5878 POSTING_READ(DSPCNTR(plane));
5879
5880 ret = intel_pipe_set_base(crtc, x, y, fb);
5881
5882 intel_update_watermarks(dev);
5883
5884 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5885
1f803ee5 5886 return ret;
79e53945
JB		 5887}
5888
f564048e
EA		 5889static int intel_crtc_mode_set(struct drm_crtc *crtc,
5890 struct drm_display_mode *mode,
5891 struct drm_display_mode *adjusted_mode,
5892 int x, int y,
94352cf9 5893 struct drm_framebuffer *fb)
f564048e
EA		 5894{
5895 struct drm_device *dev = crtc->dev;
5896 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5897 struct drm_encoder_helper_funcs *encoder_funcs;
5898 struct intel_encoder *encoder;
0b701d27
EA		 5899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5900 int pipe = intel_crtc->pipe;
f564048e
EA		 5901 int ret;
5902
cc464b2a
PZ		 5903 if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5904 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5905 else
5906 intel_crtc->cpu_transcoder = pipe;
5907
0b701d27 5908 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5909
f564048e 5910 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5911 x, y, fb);
79e53945 5912 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5913
9256aa19
DV		 5914 if (ret != 0)
5915 return ret;
5916
5917 for_each_encoder_on_crtc(dev, crtc, encoder) {
5918 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5919 encoder->base.base.id,
5920 drm_get_encoder_name(&encoder->base),
5921 mode->base.id, mode->name);
5922 encoder_funcs = encoder->base.helper_private;
5923 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5924 }
5925
5926 return 0;
79e53945
JB		 5927}
5928
3a9627f4
WF		 5929static bool intel_eld_uptodate(struct drm_connector *connector,
5930 int reg_eldv, uint32_t bits_eldv,
5931 int reg_elda, uint32_t bits_elda,
5932 int reg_edid)
5933{
5934 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5935 uint8_t *eld = connector->eld;
5936 uint32_t i;
5937
5938 i = I915_READ(reg_eldv);
5939 i &= bits_eldv;
5940
5941 if (!eld[0])
5942 return !i;
5943
5944 if (!i)
5945 return false;
5946
5947 i = I915_READ(reg_elda);
5948 i &= ~bits_elda;
5949 I915_WRITE(reg_elda, i);
5950
5951 for (i = 0; i < eld[2]; i++)
5952 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5953 return false;
5954
5955 return true;
5956}
5957
e0dac65e
WF		 5958static void g4x_write_eld(struct drm_connector *connector,
5959 struct drm_crtc *crtc)
5960{
5961 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5962 uint8_t *eld = connector->eld;
5963 uint32_t eldv;
5964 uint32_t len;
5965 uint32_t i;
5966
5967 i = I915_READ(G4X_AUD_VID_DID);
5968
5969 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5970 eldv = G4X_ELDV_DEVCL_DEVBLC;
5971 else
5972 eldv = G4X_ELDV_DEVCTG;
5973
3a9627f4
WF		 5974 if (intel_eld_uptodate(connector,
5975 G4X_AUD_CNTL_ST, eldv,
5976 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5977 G4X_HDMIW_HDMIEDID))
5978 return;
5979
e0dac65e
WF		 5980 i = I915_READ(G4X_AUD_CNTL_ST);
5981 i &= ~(eldv | G4X_ELD_ADDR);
5982 len = (i >> 9) & 0x1f; /* ELD buffer size */
5983 I915_WRITE(G4X_AUD_CNTL_ST, i);
5984
5985 if (!eld[0])
5986 return;
5987
5988 len = min_t(uint8_t, eld[2], len);
5989 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5990 for (i = 0; i < len; i++)
5991 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5992
5993 i = I915_READ(G4X_AUD_CNTL_ST);
5994 i |= eldv;
5995 I915_WRITE(G4X_AUD_CNTL_ST, i);
5996}
5997
83358c85
WX		 5998static void haswell_write_eld(struct drm_connector *connector,
5999 struct drm_crtc *crtc)
6000{
6001 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6002 uint8_t *eld = connector->eld;
6003 struct drm_device *dev = crtc->dev;
7b9f35a6 6004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6005 uint32_t eldv;
6006 uint32_t i;
6007 int len;
6008 int pipe = to_intel_crtc(crtc)->pipe;
6009 int tmp;
6010
6011 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6012 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6013 int aud_config = HSW_AUD_CFG(pipe);
6014 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6015
6016
6017 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6018
6019 /* Audio output enable */
6020 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6021 tmp = I915_READ(aud_cntrl_st2);
6022 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6023 I915_WRITE(aud_cntrl_st2, tmp);
6024
6025 /* Wait for 1 vertical blank */
6026 intel_wait_for_vblank(dev, pipe);
6027
6028 /* Set ELD valid state */
6029 tmp = I915_READ(aud_cntrl_st2);
6030 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6031 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6032 I915_WRITE(aud_cntrl_st2, tmp);
6033 tmp = I915_READ(aud_cntrl_st2);
6034 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6035
6036 /* Enable HDMI mode */
6037 tmp = I915_READ(aud_config);
6038 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6039 /* clear N_programing_enable and N_value_index */
6040 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6041 I915_WRITE(aud_config, tmp);
6042
6043 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6044
6045 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6046 intel_crtc->eld_vld = true;
83358c85
WX		 6047
6048 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6049 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6050 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6051 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6052 } else
6053 I915_WRITE(aud_config, 0);
6054
6055 if (intel_eld_uptodate(connector,
6056 aud_cntrl_st2, eldv,
6057 aud_cntl_st, IBX_ELD_ADDRESS,
6058 hdmiw_hdmiedid))
6059 return;
6060
6061 i = I915_READ(aud_cntrl_st2);
6062 i &= ~eldv;
6063 I915_WRITE(aud_cntrl_st2, i);
6064
6065 if (!eld[0])
6066 return;
6067
6068 i = I915_READ(aud_cntl_st);
6069 i &= ~IBX_ELD_ADDRESS;
6070 I915_WRITE(aud_cntl_st, i);
6071 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6072 DRM_DEBUG_DRIVER("port num:%d\n", i);
6073
6074 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6075 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6076 for (i = 0; i < len; i++)
6077 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6078
6079 i = I915_READ(aud_cntrl_st2);
6080 i |= eldv;
6081 I915_WRITE(aud_cntrl_st2, i);
6082
6083}
6084
e0dac65e
WF		 6085static void ironlake_write_eld(struct drm_connector *connector,
6086 struct drm_crtc *crtc)
6087{
6088 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6089 uint8_t *eld = connector->eld;
6090 uint32_t eldv;
6091 uint32_t i;
6092 int len;
6093 int hdmiw_hdmiedid;
b6daa025 6094 int aud_config;
e0dac65e
WF		 6095 int aud_cntl_st;
6096 int aud_cntrl_st2;
9b138a83 6097 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6098
b3f33cbf 6099 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6100 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6101 aud_config = IBX_AUD_CFG(pipe);
6102 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6103 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6104 } else {
9b138a83
WX		 6105 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6106 aud_config = CPT_AUD_CFG(pipe);
6107 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6108 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6109 }
6110
9b138a83 6111 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6112
6113 i = I915_READ(aud_cntl_st);
9b138a83 6114 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6115 if (!i) {
6116 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6117 /* operate blindly on all ports */
1202b4c6
WF		 6118 eldv = IBX_ELD_VALIDB;
6119 eldv |= IBX_ELD_VALIDB << 4;
6120 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6121 } else {
6122 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6123 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6124 }
6125
3a9627f4
WF		 6126 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6127 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6128 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6129 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6130 } else
6131 I915_WRITE(aud_config, 0);
e0dac65e 6132
3a9627f4
WF		 6133 if (intel_eld_uptodate(connector,
6134 aud_cntrl_st2, eldv,
6135 aud_cntl_st, IBX_ELD_ADDRESS,
6136 hdmiw_hdmiedid))
6137 return;
6138
e0dac65e
WF		 6139 i = I915_READ(aud_cntrl_st2);
6140 i &= ~eldv;
6141 I915_WRITE(aud_cntrl_st2, i);
6142
6143 if (!eld[0])
6144 return;
6145
e0dac65e 6146 i = I915_READ(aud_cntl_st);
1202b4c6 6147 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6148 I915_WRITE(aud_cntl_st, i);
6149
6150 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6151 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6152 for (i = 0; i < len; i++)
6153 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6154
6155 i = I915_READ(aud_cntrl_st2);
6156 i |= eldv;
6157 I915_WRITE(aud_cntrl_st2, i);
6158}
6159
6160void intel_write_eld(struct drm_encoder *encoder,
6161 struct drm_display_mode *mode)
6162{
6163 struct drm_crtc *crtc = encoder->crtc;
6164 struct drm_connector *connector;
6165 struct drm_device *dev = encoder->dev;
6166 struct drm_i915_private *dev_priv = dev->dev_private;
6167
6168 connector = drm_select_eld(encoder, mode);
6169 if (!connector)
6170 return;
6171
6172 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6173 connector->base.id,
6174 drm_get_connector_name(connector),
6175 connector->encoder->base.id,
6176 drm_get_encoder_name(connector->encoder));
6177
6178 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6179
6180 if (dev_priv->display.write_eld)
6181 dev_priv->display.write_eld(connector, crtc);
6182}
6183
79e53945
JB		 6184/** Loads the palette/gamma unit for the CRTC with the prepared values */
6185void intel_crtc_load_lut(struct drm_crtc *crtc)
6186{
6187 struct drm_device *dev = crtc->dev;
6188 struct drm_i915_private *dev_priv = dev->dev_private;
6189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6190 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6191 int i;
6192
6193 /* The clocks have to be on to load the palette. */
aed3f09d 6194 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6195 return;
6196
f2b115e6 6197 /* use legacy palette for Ironlake */
bad720ff 6198 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6199 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6200
79e53945
JB		 6201 for (i = 0; i < 256; i++) {
6202 I915_WRITE(palreg + 4 * i,
6203 (intel_crtc->lut_r[i] << 16) |
6204 (intel_crtc->lut_g[i] << 8) |
6205 intel_crtc->lut_b[i]);
6206 }
6207}
6208
560b85bb
CW		 6209static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6210{
6211 struct drm_device *dev = crtc->dev;
6212 struct drm_i915_private *dev_priv = dev->dev_private;
6213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6214 bool visible = base != 0;
6215 u32 cntl;
6216
6217 if (intel_crtc->cursor_visible == visible)
6218 return;
6219
9db4a9c7 6220 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6221 if (visible) {
6222 /* On these chipsets we can only modify the base whilst
6223 * the cursor is disabled.
6224 */
9db4a9c7 6225 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6226
6227 cntl &= ~(CURSOR_FORMAT_MASK);
6228 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6229 cntl |= CURSOR_ENABLE |
6230 CURSOR_GAMMA_ENABLE |
6231 CURSOR_FORMAT_ARGB;
6232 } else
6233 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6234 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6235
6236 intel_crtc->cursor_visible = visible;
6237}
6238
6239static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6240{
6241 struct drm_device *dev = crtc->dev;
6242 struct drm_i915_private *dev_priv = dev->dev_private;
6243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6244 int pipe = intel_crtc->pipe;
6245 bool visible = base != 0;
6246
6247 if (intel_crtc->cursor_visible != visible) {
548f245b 6248 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6249 if (base) {
6250 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6251 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6252 cntl |= pipe << 28; /* Connect to correct pipe */
6253 } else {
6254 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6255 cntl |= CURSOR_MODE_DISABLE;
6256 }
9db4a9c7 6257 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6258
6259 intel_crtc->cursor_visible = visible;
6260 }
6261 /* and commit changes on next vblank */
9db4a9c7 6262 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6263}
6264
65a21cd6
JB		 6265static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6266{
6267 struct drm_device *dev = crtc->dev;
6268 struct drm_i915_private *dev_priv = dev->dev_private;
6269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6270 int pipe = intel_crtc->pipe;
6271 bool visible = base != 0;
6272
6273 if (intel_crtc->cursor_visible != visible) {
6274 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6275 if (base) {
6276 cntl &= ~CURSOR_MODE;
6277 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6278 } else {
6279 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6280 cntl |= CURSOR_MODE_DISABLE;
6281 }
86d3efce
VS		 6282 if (IS_HASWELL(dev))
6283 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6284 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6285
6286 intel_crtc->cursor_visible = visible;
6287 }
6288 /* and commit changes on next vblank */
6289 I915_WRITE(CURBASE_IVB(pipe), base);
6290}
6291
cda4b7d3 6292/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6293static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6294 bool on)
cda4b7d3
CW		 6295{
6296 struct drm_device *dev = crtc->dev;
6297 struct drm_i915_private *dev_priv = dev->dev_private;
6298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6299 int pipe = intel_crtc->pipe;
6300 int x = intel_crtc->cursor_x;
6301 int y = intel_crtc->cursor_y;
560b85bb 6302 u32 base, pos;
cda4b7d3
CW		 6303 bool visible;
6304
6305 pos = 0;
6306
6b383a7f 6307 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6308 base = intel_crtc->cursor_addr;
6309 if (x > (int) crtc->fb->width)
6310 base = 0;
6311
6312 if (y > (int) crtc->fb->height)
6313 base = 0;
6314 } else
6315 base = 0;
6316
6317 if (x < 0) {
6318 if (x + intel_crtc->cursor_width < 0)
6319 base = 0;
6320
6321 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6322 x = -x;
6323 }
6324 pos |= x << CURSOR_X_SHIFT;
6325
6326 if (y < 0) {
6327 if (y + intel_crtc->cursor_height < 0)
6328 base = 0;
6329
6330 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6331 y = -y;
6332 }
6333 pos |= y << CURSOR_Y_SHIFT;
6334
6335 visible = base != 0;
560b85bb 6336 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6337 return;
6338
0cd83aa9 6339 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6340 I915_WRITE(CURPOS_IVB(pipe), pos);
6341 ivb_update_cursor(crtc, base);
6342 } else {
6343 I915_WRITE(CURPOS(pipe), pos);
6344 if (IS_845G(dev) || IS_I865G(dev))
6345 i845_update_cursor(crtc, base);
6346 else
6347 i9xx_update_cursor(crtc, base);
6348 }
cda4b7d3
CW		 6349}
6350
79e53945 6351static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6352 struct drm_file *file,
79e53945
JB		 6353 uint32_t handle,
6354 uint32_t width, uint32_t height)
6355{
6356 struct drm_device *dev = crtc->dev;
6357 struct drm_i915_private *dev_priv = dev->dev_private;
6358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6359 struct drm_i915_gem_object *obj;
cda4b7d3 6360 uint32_t addr;
3f8bc370 6361 int ret;
79e53945 6362
79e53945
JB		 6363 /* if we want to turn off the cursor ignore width and height */
6364 if (!handle) {
28c97730 6365 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6366 addr = 0;
05394f39 6367 obj = NULL;
5004417d 6368 mutex_lock(&dev->struct_mutex);
3f8bc370 6369 goto finish;
79e53945
JB		 6370 }
6371
6372 /* Currently we only support 64x64 cursors */
6373 if (width != 64 || height != 64) {
6374 DRM_ERROR("we currently only support 64x64 cursors\n");
6375 return -EINVAL;
6376 }
6377
05394f39 6378 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6379 if (&obj->base == NULL)
79e53945
JB		 6380 return -ENOENT;
6381
05394f39 6382 if (obj->base.size < width * height * 4) {
79e53945 6383 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6384 ret = -ENOMEM;
6385 goto fail;
79e53945
JB		 6386 }
6387
71acb5eb 6388 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6389 mutex_lock(&dev->struct_mutex);
b295d1b6 6390 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6391 unsigned alignment;
6392
d9e86c0e
CW		 6393 if (obj->tiling_mode) {
6394 DRM_ERROR("cursor cannot be tiled\n");
6395 ret = -EINVAL;
6396 goto fail_locked;
6397 }
6398
693db184
CW		 6399 /* Note that the w/a also requires 2 PTE of padding following
6400 * the bo. We currently fill all unused PTE with the shadow
6401 * page and so we should always have valid PTE following the
6402 * cursor preventing the VT-d warning.
6403 */
6404 alignment = 0;
6405 if (need_vtd_wa(dev))
6406 alignment = 64*1024;
6407
6408 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6409 if (ret) {
6410 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6411 goto fail_locked;
e7b526bb
CW		 6412 }
6413
d9e86c0e
CW		 6414 ret = i915_gem_object_put_fence(obj);
6415 if (ret) {
2da3b9b9 6416 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6417 goto fail_unpin;
6418 }
6419
05394f39 6420 addr = obj->gtt_offset;
71acb5eb 6421 } else {
6eeefaf3 6422 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6423 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6424 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6425 align);
71acb5eb
DA		 6426 if (ret) {
6427 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6428 goto fail_locked;
71acb5eb 6429 }
05394f39 6430 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6431 }
6432
a6c45cf0 6433 if (IS_GEN2(dev))
14b60391
JB		 6434 I915_WRITE(CURSIZE, (height << 12) | width);
6435
3f8bc370 6436 finish:
3f8bc370 6437 if (intel_crtc->cursor_bo) {
b295d1b6 6438 if (dev_priv->info->cursor_needs_physical) {
05394f39 6439 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6440 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6441 } else
6442 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6443 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6444 }
80824003 6445
7f9872e0 6446 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6447
6448 intel_crtc->cursor_addr = addr;
05394f39 6449 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6450 intel_crtc->cursor_width = width;
6451 intel_crtc->cursor_height = height;
6452
6b383a7f 6453 intel_crtc_update_cursor(crtc, true);
3f8bc370 6454
79e53945 6455 return 0;
e7b526bb 6456fail_unpin:
05394f39 6457 i915_gem_object_unpin(obj);
7f9872e0 6458fail_locked:
34b8686e 6459 mutex_unlock(&dev->struct_mutex);
bc9025bd 6460fail:
05394f39 6461 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6462 return ret;
79e53945
JB		 6463}
6464
6465static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6466{
79e53945 6467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6468
cda4b7d3
CW		 6469 intel_crtc->cursor_x = x;
6470 intel_crtc->cursor_y = y;
652c393a 6471
6b383a7f 6472 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6473
6474 return 0;
6475}
6476
6477/** Sets the color ramps on behalf of RandR */
6478void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6479 u16 blue, int regno)
6480{
6481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6482
6483 intel_crtc->lut_r[regno] = red >> 8;
6484 intel_crtc->lut_g[regno] = green >> 8;
6485 intel_crtc->lut_b[regno] = blue >> 8;
6486}
6487
b8c00ac5
DA		 6488void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6489 u16 *blue, int regno)
6490{
6491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6492
6493 *red = intel_crtc->lut_r[regno] << 8;
6494 *green = intel_crtc->lut_g[regno] << 8;
6495 *blue = intel_crtc->lut_b[regno] << 8;
6496}
6497
79e53945 6498static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6499 u16 *blue, uint32_t start, uint32_t size)
79e53945 6500{
7203425a 6501 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6503
7203425a 6504 for (i = start; i < end; i++) {
79e53945
JB		 6505 intel_crtc->lut_r[i] = red[i] >> 8;
6506 intel_crtc->lut_g[i] = green[i] >> 8;
6507 intel_crtc->lut_b[i] = blue[i] >> 8;
6508 }
6509
6510 intel_crtc_load_lut(crtc);
6511}
6512
79e53945
JB		 6513/* VESA 640x480x72Hz mode to set on the pipe */
6514static struct drm_display_mode load_detect_mode = {
6515 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6516 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6517};
6518
d2dff872
CW		 6519static struct drm_framebuffer *
6520intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6521 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6522 struct drm_i915_gem_object *obj)
6523{
6524 struct intel_framebuffer *intel_fb;
6525 int ret;
6526
6527 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6528 if (!intel_fb) {
6529 drm_gem_object_unreference_unlocked(&obj->base);
6530 return ERR_PTR(-ENOMEM);
6531 }
6532
6533 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6534 if (ret) {
6535 drm_gem_object_unreference_unlocked(&obj->base);
6536 kfree(intel_fb);
6537 return ERR_PTR(ret);
6538 }
6539
6540 return &intel_fb->base;
6541}
6542
6543static u32
6544intel_framebuffer_pitch_for_width(int width, int bpp)
6545{
6546 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6547 return ALIGN(pitch, 64);
6548}
6549
6550static u32
6551intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6552{
6553 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6554 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6555}
6556
6557static struct drm_framebuffer *
6558intel_framebuffer_create_for_mode(struct drm_device *dev,
6559 struct drm_display_mode *mode,
6560 int depth, int bpp)
6561{
6562 struct drm_i915_gem_object *obj;
0fed39bd 6563 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6564
6565 obj = i915_gem_alloc_object(dev,
6566 intel_framebuffer_size_for_mode(mode, bpp));
6567 if (obj == NULL)
6568 return ERR_PTR(-ENOMEM);
6569
6570 mode_cmd.width = mode->hdisplay;
6571 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6572 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6573 bpp);
5ca0c34a 6574 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6575
6576 return intel_framebuffer_create(dev, &mode_cmd, obj);
6577}
6578
6579static struct drm_framebuffer *
6580mode_fits_in_fbdev(struct drm_device *dev,
6581 struct drm_display_mode *mode)
6582{
6583 struct drm_i915_private *dev_priv = dev->dev_private;
6584 struct drm_i915_gem_object *obj;
6585 struct drm_framebuffer *fb;
6586
6587 if (dev_priv->fbdev == NULL)
6588 return NULL;
6589
6590 obj = dev_priv->fbdev->ifb.obj;
6591 if (obj == NULL)
6592 return NULL;
6593
6594 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6595 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6596 fb->bits_per_pixel))
d2dff872
CW		 6597 return NULL;
6598
01f2c773 6599 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6600 return NULL;
6601
6602 return fb;
6603}
6604
d2434ab7 6605bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6606 struct drm_display_mode *mode,
8261b191 6607 struct intel_load_detect_pipe *old)
79e53945
JB		 6608{
6609 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6610 struct intel_encoder *intel_encoder =
6611 intel_attached_encoder(connector);
79e53945 6612 struct drm_crtc *possible_crtc;
4ef69c7a 6613 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6614 struct drm_crtc *crtc = NULL;
6615 struct drm_device *dev = encoder->dev;
94352cf9 6616 struct drm_framebuffer *fb;
79e53945
JB		 6617 int i = -1;
6618
d2dff872
CW		 6619 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6620 connector->base.id, drm_get_connector_name(connector),
6621 encoder->base.id, drm_get_encoder_name(encoder));
6622
79e53945
JB		 6623 /*
6624 * Algorithm gets a little messy:
7a5e4805 6625 *
79e53945
JB		 6626 * - if the connector already has an assigned crtc, use it (but make
6627 * sure it's on first)
7a5e4805 6628 *
79e53945
JB		 6629 * - try to find the first unused crtc that can drive this connector,
6630 * and use that if we find one
79e53945
JB		 6631 */
6632
6633 /* See if we already have a CRTC for this connector */
6634 if (encoder->crtc) {
6635 crtc = encoder->crtc;
8261b191 6636
7b24056b
DV		 6637 mutex_lock(&crtc->mutex);
6638
24218aac 6639 old->dpms_mode = connector->dpms;
8261b191
CW		 6640 old->load_detect_temp = false;
6641
6642 /* Make sure the crtc and connector are running */
24218aac
DV		 6643 if (connector->dpms != DRM_MODE_DPMS_ON)
6644 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6645
7173188d 6646 return true;
79e53945
JB		 6647 }
6648
6649 /* Find an unused one (if possible) */
6650 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6651 i++;
6652 if (!(encoder->possible_crtcs & (1 << i)))
6653 continue;
6654 if (!possible_crtc->enabled) {
6655 crtc = possible_crtc;
6656 break;
6657 }
79e53945
JB		 6658 }
6659
6660 /*
6661 * If we didn't find an unused CRTC, don't use any.
6662 */
6663 if (!crtc) {
7173188d
CW		 6664 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6665 return false;
79e53945
JB		 6666 }
6667
7b24056b 6668 mutex_lock(&crtc->mutex);
fc303101
DV		 6669 intel_encoder->new_crtc = to_intel_crtc(crtc);
6670 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6671
6672 intel_crtc = to_intel_crtc(crtc);
24218aac 6673 old->dpms_mode = connector->dpms;
8261b191 6674 old->load_detect_temp = true;
d2dff872 6675 old->release_fb = NULL;
79e53945 6676
6492711d
CW		 6677 if (!mode)
6678 mode = &load_detect_mode;
79e53945 6679
d2dff872
CW		 6680 /* We need a framebuffer large enough to accommodate all accesses
6681 * that the plane may generate whilst we perform load detection.
6682 * We can not rely on the fbcon either being present (we get called
6683 * during its initialisation to detect all boot displays, or it may
6684 * not even exist) or that it is large enough to satisfy the
6685 * requested mode.
6686 */
94352cf9
DV		 6687 fb = mode_fits_in_fbdev(dev, mode);
6688 if (fb == NULL) {
d2dff872 6689 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6690 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6691 old->release_fb = fb;
d2dff872
CW		 6692 } else
6693 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6694 if (IS_ERR(fb)) {
d2dff872 6695 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6696 mutex_unlock(&crtc->mutex);
0e8b3d3e 6697 return false;
79e53945 6698 }
79e53945 6699
c0c36b94 6700 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6701 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6702 if (old->release_fb)
6703 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6704 mutex_unlock(&crtc->mutex);
0e8b3d3e 6705 return false;
79e53945 6706 }
7173188d 6707
79e53945 6708 /* let the connector get through one full cycle before testing */
9d0498a2 6709 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6710 return true;
79e53945
JB		 6711}
6712
d2434ab7 6713void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6714 struct intel_load_detect_pipe *old)
79e53945 6715{
d2434ab7
DV		 6716 struct intel_encoder *intel_encoder =
6717 intel_attached_encoder(connector);
4ef69c7a 6718 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6719 struct drm_crtc *crtc = encoder->crtc;
79e53945 6720
d2dff872
CW		 6721 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6722 connector->base.id, drm_get_connector_name(connector),
6723 encoder->base.id, drm_get_encoder_name(encoder));
6724
8261b191 6725 if (old->load_detect_temp) {
fc303101
DV		 6726 to_intel_connector(connector)->new_encoder = NULL;
6727 intel_encoder->new_crtc = NULL;
6728 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6729
36206361
DV		 6730 if (old->release_fb) {
6731 drm_framebuffer_unregister_private(old->release_fb);
6732 drm_framebuffer_unreference(old->release_fb);
6733 }
d2dff872 6734
67c96400 6735 mutex_unlock(&crtc->mutex);
0622a53c 6736 return;
79e53945
JB		 6737 }
6738
c751ce4f 6739 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6740 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6741 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6742
6743 mutex_unlock(&crtc->mutex);
79e53945
JB		 6744}
6745
6746/* Returns the clock of the currently programmed mode of the given pipe. */
6747static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6748{
6749 struct drm_i915_private *dev_priv = dev->dev_private;
6750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6751 int pipe = intel_crtc->pipe;
548f245b 6752 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6753 u32 fp;
6754 intel_clock_t clock;
6755
6756 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6757 fp = I915_READ(FP0(pipe));
79e53945 6758 else
39adb7a5 6759 fp = I915_READ(FP1(pipe));
79e53945
JB		 6760
6761 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6762 if (IS_PINEVIEW(dev)) {
6763 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6764 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6765 } else {
6766 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6767 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6768 }
6769
a6c45cf0 6770 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6771 if (IS_PINEVIEW(dev))
6772 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6773 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6774 else
6775 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6776 DPLL_FPA01_P1_POST_DIV_SHIFT);
6777
6778 switch (dpll & DPLL_MODE_MASK) {
6779 case DPLLB_MODE_DAC_SERIAL:
6780 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6781 5 : 10;
6782 break;
6783 case DPLLB_MODE_LVDS:
6784 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6785 7 : 14;
6786 break;
6787 default:
28c97730 6788 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6789 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6790 return 0;
6791 }
6792
6793 /* XXX: Handle the 100Mhz refclk */
2177832f 6794 intel_clock(dev, 96000, &clock);
79e53945
JB		 6795 } else {
6796 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6797
6798 if (is_lvds) {
6799 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6800 DPLL_FPA01_P1_POST_DIV_SHIFT);
6801 clock.p2 = 14;
6802
6803 if ((dpll & PLL_REF_INPUT_MASK) ==
6804 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6805 /* XXX: might not be 66MHz */
2177832f 6806 intel_clock(dev, 66000, &clock);
79e53945 6807 } else
2177832f 6808 intel_clock(dev, 48000, &clock);
79e53945
JB		 6809 } else {
6810 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6811 clock.p1 = 2;
6812 else {
6813 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6814 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6815 }
6816 if (dpll & PLL_P2_DIVIDE_BY_4)
6817 clock.p2 = 4;
6818 else
6819 clock.p2 = 2;
6820
2177832f 6821 intel_clock(dev, 48000, &clock);
79e53945
JB		 6822 }
6823 }
6824
6825 /* XXX: It would be nice to validate the clocks, but we can't reuse
6826 * i830PllIsValid() because it relies on the xf86_config connector
6827 * configuration being accurate, which it isn't necessarily.
6828 */
6829
6830 return clock.dot;
6831}
6832
6833/** Returns the currently programmed mode of the given pipe. */
6834struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6835 struct drm_crtc *crtc)
6836{
548f245b 6837 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6839 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6840 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6841 int htot = I915_READ(HTOTAL(cpu_transcoder));
6842 int hsync = I915_READ(HSYNC(cpu_transcoder));
6843 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6844 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6845
6846 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6847 if (!mode)
6848 return NULL;
6849
6850 mode->clock = intel_crtc_clock_get(dev, crtc);
6851 mode->hdisplay = (htot & 0xffff) + 1;
6852 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6853 mode->hsync_start = (hsync & 0xffff) + 1;
6854 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6855 mode->vdisplay = (vtot & 0xffff) + 1;
6856 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6857 mode->vsync_start = (vsync & 0xffff) + 1;
6858 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6859
6860 drm_mode_set_name(mode);
79e53945
JB		 6861
6862 return mode;
6863}
6864
3dec0095 6865static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6866{
6867 struct drm_device *dev = crtc->dev;
6868 drm_i915_private_t *dev_priv = dev->dev_private;
6869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6870 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6871 int dpll_reg = DPLL(pipe);
6872 int dpll;
652c393a 6873
bad720ff 6874 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6875 return;
6876
6877 if (!dev_priv->lvds_downclock_avail)
6878 return;
6879
dbdc6479 6880 dpll = I915_READ(dpll_reg);
652c393a 6881 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6882 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6883
8ac5a6d5 6884 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6885
6886 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6887 I915_WRITE(dpll_reg, dpll);
9d0498a2 6888 intel_wait_for_vblank(dev, pipe);
dbdc6479 6889
652c393a
JB		 6890 dpll = I915_READ(dpll_reg);
6891 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6892 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6893 }
652c393a
JB		 6894}
6895
6896static void intel_decrease_pllclock(struct drm_crtc *crtc)
6897{
6898 struct drm_device *dev = crtc->dev;
6899 drm_i915_private_t *dev_priv = dev->dev_private;
6900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6901
bad720ff 6902 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6903 return;
6904
6905 if (!dev_priv->lvds_downclock_avail)
6906 return;
6907
6908 /*
6909 * Since this is called by a timer, we should never get here in
6910 * the manual case.
6911 */
6912 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6913 int pipe = intel_crtc->pipe;
6914 int dpll_reg = DPLL(pipe);
6915 int dpll;
f6e5b160 6916
44d98a61 6917 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6918
8ac5a6d5 6919 assert_panel_unlocked(dev_priv, pipe);
652c393a 6920
dc257cf1 6921 dpll = I915_READ(dpll_reg);
652c393a
JB		 6922 dpll |= DISPLAY_RATE_SELECT_FPA1;
6923 I915_WRITE(dpll_reg, dpll);
9d0498a2 6924 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6925 dpll = I915_READ(dpll_reg);
6926 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6927 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6928 }
6929
6930}
6931
f047e395
CW		 6932void intel_mark_busy(struct drm_device *dev)
6933{
f047e395
CW		 6934 i915_update_gfx_val(dev->dev_private);
6935}
6936
6937void intel_mark_idle(struct drm_device *dev)
652c393a 6938{
652c393a 6939 struct drm_crtc *crtc;
652c393a
JB		 6940
6941 if (!i915_powersave)
6942 return;
6943
652c393a 6944 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6945 if (!crtc->fb)
6946 continue;
6947
725a5b54 6948 intel_decrease_pllclock(crtc);
652c393a 6949 }
652c393a
JB		 6950}
6951
725a5b54 6952void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6953{
f047e395
CW		 6954 struct drm_device *dev = obj->base.dev;
6955 struct drm_crtc *crtc;
652c393a 6956
f047e395 6957 if (!i915_powersave)
acb87dfb
CW		 6958 return;
6959
652c393a
JB		 6960 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6961 if (!crtc->fb)
6962 continue;
6963
f047e395 6964 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6965 intel_increase_pllclock(crtc);
652c393a
JB		 6966 }
6967}
6968
79e53945
JB		 6969static void intel_crtc_destroy(struct drm_crtc *crtc)
6970{
6971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6972 struct drm_device *dev = crtc->dev;
6973 struct intel_unpin_work *work;
6974 unsigned long flags;
6975
6976 spin_lock_irqsave(&dev->event_lock, flags);
6977 work = intel_crtc->unpin_work;
6978 intel_crtc->unpin_work = NULL;
6979 spin_unlock_irqrestore(&dev->event_lock, flags);
6980
6981 if (work) {
6982 cancel_work_sync(&work->work);
6983 kfree(work);
6984 }
79e53945
JB		 6985
6986 drm_crtc_cleanup(crtc);
67e77c5a 6987
79e53945
JB		 6988 kfree(intel_crtc);
6989}
6990
6b95a207
KH		 6991static void intel_unpin_work_fn(struct work_struct *__work)
6992{
6993 struct intel_unpin_work *work =
6994 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6995 struct drm_device *dev = work->crtc->dev;
6b95a207 6996
b4a98e57 6997 mutex_lock(&dev->struct_mutex);
1690e1eb 6998 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6999 drm_gem_object_unreference(&work->pending_flip_obj->base);
7000 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7001
b4a98e57
CW		 7002 intel_update_fbc(dev);
7003 mutex_unlock(&dev->struct_mutex);
7004
7005 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7006 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7007
6b95a207
KH		 7008 kfree(work);
7009}
7010
1afe3e9d 7011static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7012 struct drm_crtc *crtc)
6b95a207
KH		 7013{
7014 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7016 struct intel_unpin_work *work;
6b95a207
KH		 7017 unsigned long flags;
7018
7019 /* Ignore early vblank irqs */
7020 if (intel_crtc == NULL)
7021 return;
7022
7023 spin_lock_irqsave(&dev->event_lock, flags);
7024 work = intel_crtc->unpin_work;
e7d841ca
CW		 7025
7026 /* Ensure we don't miss a work->pending update ... */
7027 smp_rmb();
7028
7029 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7030 spin_unlock_irqrestore(&dev->event_lock, flags);
7031 return;
7032 }
7033
e7d841ca
CW		 7034 /* and that the unpin work is consistent wrt ->pending. */
7035 smp_rmb();
7036
6b95a207 7037 intel_crtc->unpin_work = NULL;
6b95a207 7038
45a066eb
RC		 7039 if (work->event)
7040 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7041
0af7e4df
MK		 7042 drm_vblank_put(dev, intel_crtc->pipe);
7043
6b95a207
KH		 7044 spin_unlock_irqrestore(&dev->event_lock, flags);
7045
2c10d571 7046 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7047
7048 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7049
7050 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7051}
7052
1afe3e9d
JB		 7053void intel_finish_page_flip(struct drm_device *dev, int pipe)
7054{
7055 drm_i915_private_t *dev_priv = dev->dev_private;
7056 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7057
49b14a5c 7058 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7059}
7060
7061void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7062{
7063 drm_i915_private_t *dev_priv = dev->dev_private;
7064 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7065
49b14a5c 7066 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7067}
7068
6b95a207
KH		 7069void intel_prepare_page_flip(struct drm_device *dev, int plane)
7070{
7071 drm_i915_private_t *dev_priv = dev->dev_private;
7072 struct intel_crtc *intel_crtc =
7073 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7074 unsigned long flags;
7075
e7d841ca
CW		 7076 /* NB: An MMIO update of the plane base pointer will also
7077 * generate a page-flip completion irq, i.e. every modeset
7078 * is also accompanied by a spurious intel_prepare_page_flip().
7079 */
6b95a207 7080 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7081 if (intel_crtc->unpin_work)
7082 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7083 spin_unlock_irqrestore(&dev->event_lock, flags);
7084}
7085
e7d841ca
CW		 7086inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7087{
7088 /* Ensure that the work item is consistent when activating it ... */
7089 smp_wmb();
7090 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7091 /* and that it is marked active as soon as the irq could fire. */
7092 smp_wmb();
7093}
7094
8c9f3aaf
JB		 7095static int intel_gen2_queue_flip(struct drm_device *dev,
7096 struct drm_crtc *crtc,
7097 struct drm_framebuffer *fb,
7098 struct drm_i915_gem_object *obj)
7099{
7100 struct drm_i915_private *dev_priv = dev->dev_private;
7101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7102 u32 flip_mask;
6d90c952 7103 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7104 int ret;
7105
6d90c952 7106 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7107 if (ret)
83d4092b 7108 goto err;
8c9f3aaf 7109
6d90c952 7110 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7111 if (ret)
83d4092b 7112 goto err_unpin;
8c9f3aaf
JB		 7113
7114 /* Can't queue multiple flips, so wait for the previous
7115 * one to finish before executing the next.
7116 */
7117 if (intel_crtc->plane)
7118 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7119 else
7120 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7121 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7122 intel_ring_emit(ring, MI_NOOP);
7123 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7124 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7125 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7126 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7127 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7128
7129 intel_mark_page_flip_active(intel_crtc);
6d90c952 7130 intel_ring_advance(ring);
83d4092b
CW		 7131 return 0;
7132
7133err_unpin:
7134 intel_unpin_fb_obj(obj);
7135err:
8c9f3aaf
JB		 7136 return ret;
7137}
7138
7139static int intel_gen3_queue_flip(struct drm_device *dev,
7140 struct drm_crtc *crtc,
7141 struct drm_framebuffer *fb,
7142 struct drm_i915_gem_object *obj)
7143{
7144 struct drm_i915_private *dev_priv = dev->dev_private;
7145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7146 u32 flip_mask;
6d90c952 7147 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7148 int ret;
7149
6d90c952 7150 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7151 if (ret)
83d4092b 7152 goto err;
8c9f3aaf 7153
6d90c952 7154 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7155 if (ret)
83d4092b 7156 goto err_unpin;
8c9f3aaf
JB		 7157
7158 if (intel_crtc->plane)
7159 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7160 else
7161 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7162 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7163 intel_ring_emit(ring, MI_NOOP);
7164 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7165 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7166 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7167 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7168 intel_ring_emit(ring, MI_NOOP);
7169
e7d841ca 7170 intel_mark_page_flip_active(intel_crtc);
6d90c952 7171 intel_ring_advance(ring);
83d4092b
CW		 7172 return 0;
7173
7174err_unpin:
7175 intel_unpin_fb_obj(obj);
7176err:
8c9f3aaf
JB		 7177 return ret;
7178}
7179
7180static int intel_gen4_queue_flip(struct drm_device *dev,
7181 struct drm_crtc *crtc,
7182 struct drm_framebuffer *fb,
7183 struct drm_i915_gem_object *obj)
7184{
7185 struct drm_i915_private *dev_priv = dev->dev_private;
7186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7187 uint32_t pf, pipesrc;
6d90c952 7188 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7189 int ret;
7190
6d90c952 7191 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7192 if (ret)
83d4092b 7193 goto err;
8c9f3aaf 7194
6d90c952 7195 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7196 if (ret)
83d4092b 7197 goto err_unpin;
8c9f3aaf
JB		 7198
7199 /* i965+ uses the linear or tiled offsets from the
7200 * Display Registers (which do not change across a page-flip)
7201 * so we need only reprogram the base address.
7202 */
6d90c952
DV		 7203 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7204 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7205 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7206 intel_ring_emit(ring,
7207 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7208 obj->tiling_mode);
8c9f3aaf
JB		 7209
7210 /* XXX Enabling the panel-fitter across page-flip is so far
7211 * untested on non-native modes, so ignore it for now.
7212 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7213 */
7214 pf = 0;
7215 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7216 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7217
7218 intel_mark_page_flip_active(intel_crtc);
6d90c952 7219 intel_ring_advance(ring);
83d4092b
CW		 7220 return 0;
7221
7222err_unpin:
7223 intel_unpin_fb_obj(obj);
7224err:
8c9f3aaf
JB		 7225 return ret;
7226}
7227
7228static int intel_gen6_queue_flip(struct drm_device *dev,
7229 struct drm_crtc *crtc,
7230 struct drm_framebuffer *fb,
7231 struct drm_i915_gem_object *obj)
7232{
7233 struct drm_i915_private *dev_priv = dev->dev_private;
7234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7235 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7236 uint32_t pf, pipesrc;
7237 int ret;
7238
6d90c952 7239 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7240 if (ret)
83d4092b 7241 goto err;
8c9f3aaf 7242
6d90c952 7243 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7244 if (ret)
83d4092b 7245 goto err_unpin;
8c9f3aaf 7246
6d90c952
DV		 7247 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7248 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7249 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7250 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7251
dc257cf1
DV		 7252 /* Contrary to the suggestions in the documentation,
7253 * "Enable Panel Fitter" does not seem to be required when page
7254 * flipping with a non-native mode, and worse causes a normal
7255 * modeset to fail.
7256 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7257 */
7258 pf = 0;
8c9f3aaf 7259 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7260 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7261
7262 intel_mark_page_flip_active(intel_crtc);
6d90c952 7263 intel_ring_advance(ring);
83d4092b
CW		 7264 return 0;
7265
7266err_unpin:
7267 intel_unpin_fb_obj(obj);
7268err:
8c9f3aaf
JB		 7269 return ret;
7270}
7271
7c9017e5
JB		 7272/*
7273 * On gen7 we currently use the blit ring because (in early silicon at least)
7274 * the render ring doesn't give us interrpts for page flip completion, which
7275 * means clients will hang after the first flip is queued. Fortunately the
7276 * blit ring generates interrupts properly, so use it instead.
7277 */
7278static int intel_gen7_queue_flip(struct drm_device *dev,
7279 struct drm_crtc *crtc,
7280 struct drm_framebuffer *fb,
7281 struct drm_i915_gem_object *obj)
7282{
7283 struct drm_i915_private *dev_priv = dev->dev_private;
7284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7285 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7286 uint32_t plane_bit = 0;
7c9017e5
JB		 7287 int ret;
7288
7289 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7290 if (ret)
83d4092b 7291 goto err;
7c9017e5 7292
cb05d8de
DV		 7293 switch(intel_crtc->plane) {
7294 case PLANE_A:
7295 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7296 break;
7297 case PLANE_B:
7298 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7299 break;
7300 case PLANE_C:
7301 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7302 break;
7303 default:
7304 WARN_ONCE(1, "unknown plane in flip command\n");
7305 ret = -ENODEV;
ab3951eb 7306 goto err_unpin;
cb05d8de
DV		 7307 }
7308
7c9017e5
JB		 7309 ret = intel_ring_begin(ring, 4);
7310 if (ret)
83d4092b 7311 goto err_unpin;
7c9017e5 7312
cb05d8de 7313 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7314 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7315 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7316 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7317
7318 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7319 intel_ring_advance(ring);
83d4092b
CW		 7320 return 0;
7321
7322err_unpin:
7323 intel_unpin_fb_obj(obj);
7324err:
7c9017e5
JB		 7325 return ret;
7326}
7327
8c9f3aaf
JB		 7328static int intel_default_queue_flip(struct drm_device *dev,
7329 struct drm_crtc *crtc,
7330 struct drm_framebuffer *fb,
7331 struct drm_i915_gem_object *obj)
7332{
7333 return -ENODEV;
7334}
7335
6b95a207
KH		 7336static int intel_crtc_page_flip(struct drm_crtc *crtc,
7337 struct drm_framebuffer *fb,
7338 struct drm_pending_vblank_event *event)
7339{
7340 struct drm_device *dev = crtc->dev;
7341 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7342 struct drm_framebuffer *old_fb = crtc->fb;
7343 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7345 struct intel_unpin_work *work;
8c9f3aaf 7346 unsigned long flags;
52e68630 7347 int ret;
6b95a207 7348
e6a595d2
VS		 7349 /* Can't change pixel format via MI display flips. */
7350 if (fb->pixel_format != crtc->fb->pixel_format)
7351 return -EINVAL;
7352
7353 /*
7354 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7355 * Note that pitch changes could also affect these register.
7356 */
7357 if (INTEL_INFO(dev)->gen > 3 &&
7358 (fb->offsets[0] != crtc->fb->offsets[0] ||
7359 fb->pitches[0] != crtc->fb->pitches[0]))
7360 return -EINVAL;
7361
6b95a207
KH		 7362 work = kzalloc(sizeof *work, GFP_KERNEL);
7363 if (work == NULL)
7364 return -ENOMEM;
7365
6b95a207 7366 work->event = event;
b4a98e57 7367 work->crtc = crtc;
4a35f83b 7368 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7369 INIT_WORK(&work->work, intel_unpin_work_fn);
7370
7317c75e
JB		 7371 ret = drm_vblank_get(dev, intel_crtc->pipe);
7372 if (ret)
7373 goto free_work;
7374
6b95a207
KH		 7375 /* We borrow the event spin lock for protecting unpin_work */
7376 spin_lock_irqsave(&dev->event_lock, flags);
7377 if (intel_crtc->unpin_work) {
7378 spin_unlock_irqrestore(&dev->event_lock, flags);
7379 kfree(work);
7317c75e 7380 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7381
7382 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7383 return -EBUSY;
7384 }
7385 intel_crtc->unpin_work = work;
7386 spin_unlock_irqrestore(&dev->event_lock, flags);
7387
b4a98e57
CW		 7388 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7389 flush_workqueue(dev_priv->wq);
7390
79158103
CW		 7391 ret = i915_mutex_lock_interruptible(dev);
7392 if (ret)
7393 goto cleanup;
6b95a207 7394
75dfca80 7395 /* Reference the objects for the scheduled work. */
05394f39
CW		 7396 drm_gem_object_reference(&work->old_fb_obj->base);
7397 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7398
7399 crtc->fb = fb;
96b099fd 7400
e1f99ce6 7401 work->pending_flip_obj = obj;
e1f99ce6 7402
4e5359cd
SF		 7403 work->enable_stall_check = true;
7404
b4a98e57 7405 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7406 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7407
8c9f3aaf
JB		 7408 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7409 if (ret)
7410 goto cleanup_pending;
6b95a207 7411
7782de3b 7412 intel_disable_fbc(dev);
f047e395 7413 intel_mark_fb_busy(obj);
6b95a207
KH		 7414 mutex_unlock(&dev->struct_mutex);
7415
e5510fac
JB		 7416 trace_i915_flip_request(intel_crtc->plane, obj);
7417
6b95a207 7418 return 0;
96b099fd 7419
8c9f3aaf 7420cleanup_pending:
b4a98e57 7421 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7422 crtc->fb = old_fb;
05394f39
CW		 7423 drm_gem_object_unreference(&work->old_fb_obj->base);
7424 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7425 mutex_unlock(&dev->struct_mutex);
7426
79158103 7427cleanup:
96b099fd
CW		 7428 spin_lock_irqsave(&dev->event_lock, flags);
7429 intel_crtc->unpin_work = NULL;
7430 spin_unlock_irqrestore(&dev->event_lock, flags);
7431
7317c75e
JB		 7432 drm_vblank_put(dev, intel_crtc->pipe);
7433free_work:
96b099fd
CW		 7434 kfree(work);
7435
7436 return ret;
6b95a207
KH		 7437}
7438
f6e5b160 7439static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7440 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7441 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7442};
7443
6ed0f796 7444bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7445{
6ed0f796
DV		 7446 struct intel_encoder *other_encoder;
7447 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7448
6ed0f796
DV		 7449 if (WARN_ON(!crtc))
7450 return false;
7451
7452 list_for_each_entry(other_encoder,
7453 &crtc->dev->mode_config.encoder_list,
7454 base.head) {
7455
7456 if (&other_encoder->new_crtc->base != crtc ||
7457 encoder == other_encoder)
7458 continue;
7459 else
7460 return true;
f47166d2
CW		 7461 }
7462
6ed0f796
DV		 7463 return false;
7464}
47f1c6c9 7465
50f56119
DV		 7466static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7467 struct drm_crtc *crtc)
7468{
7469 struct drm_device *dev;
7470 struct drm_crtc *tmp;
7471 int crtc_mask = 1;
47f1c6c9 7472
50f56119 7473 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7474
50f56119 7475 dev = crtc->dev;
47f1c6c9 7476
50f56119
DV		 7477 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7478 if (tmp == crtc)
7479 break;
7480 crtc_mask <<= 1;
7481 }
47f1c6c9 7482
50f56119
DV		 7483 if (encoder->possible_crtcs & crtc_mask)
7484 return true;
7485 return false;
47f1c6c9 7486}
79e53945 7487
9a935856
DV		 7488/**
7489 * intel_modeset_update_staged_output_state
7490 *
7491 * Updates the staged output configuration state, e.g. after we've read out the
7492 * current hw state.
7493 */
7494static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7495{
9a935856
DV		 7496 struct intel_encoder *encoder;
7497 struct intel_connector *connector;
f6e5b160 7498
9a935856
DV		 7499 list_for_each_entry(connector, &dev->mode_config.connector_list,
7500 base.head) {
7501 connector->new_encoder =
7502 to_intel_encoder(connector->base.encoder);
7503 }
f6e5b160 7504
9a935856
DV		 7505 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7506 base.head) {
7507 encoder->new_crtc =
7508 to_intel_crtc(encoder->base.crtc);
7509 }
f6e5b160
CW		 7510}
7511
9a935856
DV		 7512/**
7513 * intel_modeset_commit_output_state
7514 *
7515 * This function copies the stage display pipe configuration to the real one.
7516 */
7517static void intel_modeset_commit_output_state(struct drm_device *dev)
7518{
7519 struct intel_encoder *encoder;
7520 struct intel_connector *connector;
f6e5b160 7521
9a935856
DV		 7522 list_for_each_entry(connector, &dev->mode_config.connector_list,
7523 base.head) {
7524 connector->base.encoder = &connector->new_encoder->base;
7525 }
f6e5b160 7526
9a935856
DV		 7527 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7528 base.head) {
7529 encoder->base.crtc = &encoder->new_crtc->base;
7530 }
7531}
7532
7758a113
DV		 7533static struct drm_display_mode *
7534intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7535 struct drm_display_mode *mode)
ee7b9f93 7536{
7758a113
DV		 7537 struct drm_device *dev = crtc->dev;
7538 struct drm_display_mode *adjusted_mode;
7539 struct drm_encoder_helper_funcs *encoder_funcs;
7540 struct intel_encoder *encoder;
ee7b9f93 7541
7758a113
DV		 7542 adjusted_mode = drm_mode_duplicate(dev, mode);
7543 if (!adjusted_mode)
7544 return ERR_PTR(-ENOMEM);
7545
7546 /* Pass our mode to the connectors and the CRTC to give them a chance to
7547 * adjust it according to limitations or connector properties, and also
7548 * a chance to reject the mode entirely.
47f1c6c9 7549 */
7758a113
DV		 7550 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7551 base.head) {
47f1c6c9 7552
7758a113
DV		 7553 if (&encoder->new_crtc->base != crtc)
7554 continue;
7555 encoder_funcs = encoder->base.helper_private;
7556 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7557 adjusted_mode))) {
7558 DRM_DEBUG_KMS("Encoder fixup failed\n");
7559 goto fail;
7560 }
ee7b9f93 7561 }
47f1c6c9 7562
7758a113
DV		 7563 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7564 DRM_DEBUG_KMS("CRTC fixup failed\n");
7565 goto fail;
ee7b9f93 7566 }
7758a113 7567 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7568
7758a113
DV		 7569 return adjusted_mode;
7570fail:
7571 drm_mode_destroy(dev, adjusted_mode);
7572 return ERR_PTR(-EINVAL);
ee7b9f93 7573}
47f1c6c9 7574
e2e1ed41
DV		 7575/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7576 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7577static void
7578intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7579 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7580{
7581 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7582 struct drm_device *dev = crtc->dev;
7583 struct intel_encoder *encoder;
7584 struct intel_connector *connector;
7585 struct drm_crtc *tmp_crtc;
79e53945 7586
e2e1ed41 7587 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7588
e2e1ed41
DV		 7589 /* Check which crtcs have changed outputs connected to them, these need
7590 * to be part of the prepare_pipes mask. We don't (yet) support global
7591 * modeset across multiple crtcs, so modeset_pipes will only have one
7592 * bit set at most. */
7593 list_for_each_entry(connector, &dev->mode_config.connector_list,
7594 base.head) {
7595 if (connector->base.encoder == &connector->new_encoder->base)
7596 continue;
79e53945 7597
e2e1ed41
DV		 7598 if (connector->base.encoder) {
7599 tmp_crtc = connector->base.encoder->crtc;
7600
7601 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7602 }
7603
7604 if (connector->new_encoder)
7605 *prepare_pipes |=
7606 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7607 }
7608
e2e1ed41
DV		 7609 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7610 base.head) {
7611 if (encoder->base.crtc == &encoder->new_crtc->base)
7612 continue;
7613
7614 if (encoder->base.crtc) {
7615 tmp_crtc = encoder->base.crtc;
7616
7617 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7618 }
7619
7620 if (encoder->new_crtc)
7621 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7622 }
7623
e2e1ed41
DV		 7624 /* Check for any pipes that will be fully disabled ... */
7625 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7626 base.head) {
7627 bool used = false;
22fd0fab 7628
e2e1ed41
DV		 7629 /* Don't try to disable disabled crtcs. */
7630 if (!intel_crtc->base.enabled)
7631 continue;
7e7d76c3 7632
e2e1ed41
DV		 7633 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7634 base.head) {
7635 if (encoder->new_crtc == intel_crtc)
7636 used = true;
7637 }
7638
7639 if (!used)
7640 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7641 }
7642
e2e1ed41
DV		 7643
7644 /* set_mode is also used to update properties on life display pipes. */
7645 intel_crtc = to_intel_crtc(crtc);
7646 if (crtc->enabled)
7647 *prepare_pipes |= 1 << intel_crtc->pipe;
7648
7649 /* We only support modeset on one single crtc, hence we need to do that
7650 * only for the passed in crtc iff we change anything else than just
7651 * disable crtcs.
7652 *
7653 * This is actually not true, to be fully compatible with the old crtc
7654 * helper we automatically disable _any_ output (i.e. doesn't need to be
7655 * connected to the crtc we're modesetting on) if it's disconnected.
7656 * Which is a rather nutty api (since changed the output configuration
7657 * without userspace's explicit request can lead to confusion), but
7658 * alas. Hence we currently need to modeset on all pipes we prepare. */
7659 if (*prepare_pipes)
7660 *modeset_pipes = *prepare_pipes;
7661
7662 /* ... and mask these out. */
7663 *modeset_pipes &= ~(*disable_pipes);
7664 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7665}
79e53945 7666
ea9d758d 7667static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7668{
ea9d758d 7669 struct drm_encoder *encoder;
f6e5b160 7670 struct drm_device *dev = crtc->dev;
f6e5b160 7671
ea9d758d
DV		 7672 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7673 if (encoder->crtc == crtc)
7674 return true;
7675
7676 return false;
7677}
7678
7679static void
7680intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7681{
7682 struct intel_encoder *intel_encoder;
7683 struct intel_crtc *intel_crtc;
7684 struct drm_connector *connector;
7685
7686 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7687 base.head) {
7688 if (!intel_encoder->base.crtc)
7689 continue;
7690
7691 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7692
7693 if (prepare_pipes & (1 << intel_crtc->pipe))
7694 intel_encoder->connectors_active = false;
7695 }
7696
7697 intel_modeset_commit_output_state(dev);
7698
7699 /* Update computed state. */
7700 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7701 base.head) {
7702 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7703 }
7704
7705 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7706 if (!connector->encoder || !connector->encoder->crtc)
7707 continue;
7708
7709 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7710
7711 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7712 struct drm_property *dpms_property =
7713 dev->mode_config.dpms_property;
7714
ea9d758d 7715 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7716 drm_object_property_set_value(&connector->base,
68d34720
DV		 7717 dpms_property,
7718 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7719
7720 intel_encoder = to_intel_encoder(connector->encoder);
7721 intel_encoder->connectors_active = true;
7722 }
7723 }
7724
7725}
7726
25c5b266
DV		 7727#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7728 list_for_each_entry((intel_crtc), \
7729 &(dev)->mode_config.crtc_list, \
7730 base.head) \
7731 if (mask & (1 <<(intel_crtc)->pipe)) \
7732
b980514c 7733void
8af6cf88
DV		 7734intel_modeset_check_state(struct drm_device *dev)
7735{
7736 struct intel_crtc *crtc;
7737 struct intel_encoder *encoder;
7738 struct intel_connector *connector;
7739
7740 list_for_each_entry(connector, &dev->mode_config.connector_list,
7741 base.head) {
7742 /* This also checks the encoder/connector hw state with the
7743 * ->get_hw_state callbacks. */
7744 intel_connector_check_state(connector);
7745
7746 WARN(&connector->new_encoder->base != connector->base.encoder,
7747 "connector's staged encoder doesn't match current encoder\n");
7748 }
7749
7750 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7751 base.head) {
7752 bool enabled = false;
7753 bool active = false;
7754 enum pipe pipe, tracked_pipe;
7755
7756 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7757 encoder->base.base.id,
7758 drm_get_encoder_name(&encoder->base));
7759
7760 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7761 "encoder's stage crtc doesn't match current crtc\n");
7762 WARN(encoder->connectors_active && !encoder->base.crtc,
7763 "encoder's active_connectors set, but no crtc\n");
7764
7765 list_for_each_entry(connector, &dev->mode_config.connector_list,
7766 base.head) {
7767 if (connector->base.encoder != &encoder->base)
7768 continue;
7769 enabled = true;
7770 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7771 active = true;
7772 }
7773 WARN(!!encoder->base.crtc != enabled,
7774 "encoder's enabled state mismatch "
7775 "(expected %i, found %i)\n",
7776 !!encoder->base.crtc, enabled);
7777 WARN(active && !encoder->base.crtc,
7778 "active encoder with no crtc\n");
7779
7780 WARN(encoder->connectors_active != active,
7781 "encoder's computed active state doesn't match tracked active state "
7782 "(expected %i, found %i)\n", active, encoder->connectors_active);
7783
7784 active = encoder->get_hw_state(encoder, &pipe);
7785 WARN(active != encoder->connectors_active,
7786 "encoder's hw state doesn't match sw tracking "
7787 "(expected %i, found %i)\n",
7788 encoder->connectors_active, active);
7789
7790 if (!encoder->base.crtc)
7791 continue;
7792
7793 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7794 WARN(active && pipe != tracked_pipe,
7795 "active encoder's pipe doesn't match"
7796 "(expected %i, found %i)\n",
7797 tracked_pipe, pipe);
7798
7799 }
7800
7801 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7802 base.head) {
7803 bool enabled = false;
7804 bool active = false;
7805
7806 DRM_DEBUG_KMS("[CRTC:%d]\n",
7807 crtc->base.base.id);
7808
7809 WARN(crtc->active && !crtc->base.enabled,
7810 "active crtc, but not enabled in sw tracking\n");
7811
7812 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7813 base.head) {
7814 if (encoder->base.crtc != &crtc->base)
7815 continue;
7816 enabled = true;
7817 if (encoder->connectors_active)
7818 active = true;
7819 }
7820 WARN(active != crtc->active,
7821 "crtc's computed active state doesn't match tracked active state "
7822 "(expected %i, found %i)\n", active, crtc->active);
7823 WARN(enabled != crtc->base.enabled,
7824 "crtc's computed enabled state doesn't match tracked enabled state "
7825 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7826
7827 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7828 }
7829}
7830
c0c36b94
CW		 7831int intel_set_mode(struct drm_crtc *crtc,
7832 struct drm_display_mode *mode,
7833 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7834{
7835 struct drm_device *dev = crtc->dev;
dbf2b54e 7836 drm_i915_private_t *dev_priv = dev->dev_private;
3ac18232 7837 struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
25c5b266
DV		 7838 struct intel_crtc *intel_crtc;
7839 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7840 int ret = 0;
a6778b3c 7841
3ac18232 7842 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7843 if (!saved_mode)
7844 return -ENOMEM;
3ac18232 7845 saved_hwmode = saved_mode + 1;
a6778b3c 7846
e2e1ed41 7847 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7848 &prepare_pipes, &disable_pipes);
7849
7850 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7851 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7852
976f8a20
DV		 7853 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7854 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7855
3ac18232
TG		 7856 *saved_hwmode = crtc->hwmode;
7857 *saved_mode = crtc->mode;
a6778b3c 7858
25c5b266
DV		 7859 /* Hack: Because we don't (yet) support global modeset on multiple
7860 * crtcs, we don't keep track of the new mode for more than one crtc.
7861 * Hence simply check whether any bit is set in modeset_pipes in all the
7862 * pieces of code that are not yet converted to deal with mutliple crtcs
7863 * changing their mode at the same time. */
7864 adjusted_mode = NULL;
7865 if (modeset_pipes) {
7866 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7867 if (IS_ERR(adjusted_mode)) {
c0c36b94 7868 ret = PTR_ERR(adjusted_mode);
3ac18232 7869 goto out;
25c5b266 7870 }
25c5b266 7871 }
a6778b3c 7872
ea9d758d
DV		 7873 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7874 if (intel_crtc->base.enabled)
7875 dev_priv->display.crtc_disable(&intel_crtc->base);
7876 }
a6778b3c 7877
6c4c86f5
DV		 7878 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7879 * to set it here already despite that we pass it down the callchain.
f6e5b160 7880 */
6c4c86f5 7881 if (modeset_pipes)
25c5b266 7882 crtc->mode = *mode;
7758a113 7883
ea9d758d
DV		 7884 /* Only after disabling all output pipelines that will be changed can we
7885 * update the the output configuration. */
7886 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7887
47fab737
DV		 7888 if (dev_priv->display.modeset_global_resources)
7889 dev_priv->display.modeset_global_resources(dev);
7890
a6778b3c
DV		 7891 /* Set up the DPLL and any encoders state that needs to adjust or depend
7892 * on the DPLL.
f6e5b160 7893 */
25c5b266 7894 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94
CW		 7895 ret = intel_crtc_mode_set(&intel_crtc->base,
7896 mode, adjusted_mode,
7897 x, y, fb);
7898 if (ret)
7899 goto done;
a6778b3c
DV		 7900 }
7901
7902 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7903 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7904 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7905
25c5b266
DV		 7906 if (modeset_pipes) {
7907 /* Store real post-adjustment hardware mode. */
7908 crtc->hwmode = *adjusted_mode;
a6778b3c 7909
25c5b266
DV		 7910 /* Calculate and store various constants which
7911 * are later needed by vblank and swap-completion
7912 * timestamping. They are derived from true hwmode.
7913 */
7914 drm_calc_timestamping_constants(crtc);
7915 }
a6778b3c
DV		 7916
7917 /* FIXME: add subpixel order */
7918done:
7919 drm_mode_destroy(dev, adjusted_mode);
c0c36b94 7920 if (ret && crtc->enabled) {
3ac18232
TG		 7921 crtc->hwmode = *saved_hwmode;
7922 crtc->mode = *saved_mode;
8af6cf88
DV		 7923 } else {
7924 intel_modeset_check_state(dev);
a6778b3c
DV		 7925 }
7926
3ac18232
TG		 7927out:
7928 kfree(saved_mode);
a6778b3c 7929 return ret;
f6e5b160
CW		 7930}
7931
c0c36b94
CW		 7932void intel_crtc_restore_mode(struct drm_crtc *crtc)
7933{
7934 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7935}
7936
25c5b266
DV		 7937#undef for_each_intel_crtc_masked
7938
d9e55608
DV		 7939static void intel_set_config_free(struct intel_set_config *config)
7940{
7941 if (!config)
7942 return;
7943
1aa4b628
DV		 7944 kfree(config->save_connector_encoders);
7945 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7946 kfree(config);
7947}
7948
85f9eb71
DV		 7949static int intel_set_config_save_state(struct drm_device *dev,
7950 struct intel_set_config *config)
7951{
85f9eb71
DV		 7952 struct drm_encoder *encoder;
7953 struct drm_connector *connector;
7954 int count;
7955
1aa4b628
DV		 7956 config->save_encoder_crtcs =
7957 kcalloc(dev->mode_config.num_encoder,
7958 sizeof(struct drm_crtc *), GFP_KERNEL);
7959 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7960 return -ENOMEM;
7961
1aa4b628
DV		 7962 config->save_connector_encoders =
7963 kcalloc(dev->mode_config.num_connector,
7964 sizeof(struct drm_encoder *), GFP_KERNEL);
7965 if (!config->save_connector_encoders)
85f9eb71
DV		 7966 return -ENOMEM;
7967
7968 /* Copy data. Note that driver private data is not affected.
7969 * Should anything bad happen only the expected state is
7970 * restored, not the drivers personal bookkeeping.
7971 */
85f9eb71
DV		 7972 count = 0;
7973 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7974 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7975 }
7976
7977 count = 0;
7978 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7979 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7980 }
7981
7982 return 0;
7983}
7984
7985static void intel_set_config_restore_state(struct drm_device *dev,
7986 struct intel_set_config *config)
7987{
9a935856
DV		 7988 struct intel_encoder *encoder;
7989 struct intel_connector *connector;
85f9eb71
DV		 7990 int count;
7991
85f9eb71 7992 count = 0;
9a935856
DV		 7993 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7994 encoder->new_crtc =
7995 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7996 }
7997
7998 count = 0;
9a935856
DV		 7999 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8000 connector->new_encoder =
8001 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8002 }
8003}
8004
5e2b584e
DV		 8005static void
8006intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8007 struct intel_set_config *config)
8008{
8009
8010 /* We should be able to check here if the fb has the same properties
8011 * and then just flip_or_move it */
8012 if (set->crtc->fb != set->fb) {
8013 /* If we have no fb then treat it as a full mode set */
8014 if (set->crtc->fb == NULL) {
8015 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8016 config->mode_changed = true;
8017 } else if (set->fb == NULL) {
8018 config->mode_changed = true;
8019 } else if (set->fb->depth != set->crtc->fb->depth) {
8020 config->mode_changed = true;
8021 } else if (set->fb->bits_per_pixel !=
8022 set->crtc->fb->bits_per_pixel) {
8023 config->mode_changed = true;
8024 } else
8025 config->fb_changed = true;
8026 }
8027
835c5873 8028 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8029 config->fb_changed = true;
8030
8031 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8032 DRM_DEBUG_KMS("modes are different, full mode set\n");
8033 drm_mode_debug_printmodeline(&set->crtc->mode);
8034 drm_mode_debug_printmodeline(set->mode);
8035 config->mode_changed = true;
8036 }
8037}
8038
2e431051 8039static int
9a935856
DV		 8040intel_modeset_stage_output_state(struct drm_device *dev,
8041 struct drm_mode_set *set,
8042 struct intel_set_config *config)
50f56119 8043{
85f9eb71 8044 struct drm_crtc *new_crtc;
9a935856
DV		 8045 struct intel_connector *connector;
8046 struct intel_encoder *encoder;
2e431051 8047 int count, ro;
50f56119 8048
9abdda74 8049 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8050 * of connectors. For paranoia, double-check this. */
8051 WARN_ON(!set->fb && (set->num_connectors != 0));
8052 WARN_ON(set->fb && (set->num_connectors == 0));
8053
50f56119 8054 count = 0;
9a935856
DV		 8055 list_for_each_entry(connector, &dev->mode_config.connector_list,
8056 base.head) {
8057 /* Otherwise traverse passed in connector list and get encoders
8058 * for them. */
50f56119 8059 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8060 if (set->connectors[ro] == &connector->base) {
8061 connector->new_encoder = connector->encoder;
50f56119
DV		 8062 break;
8063 }
8064 }
8065
9a935856
DV		 8066 /* If we disable the crtc, disable all its connectors. Also, if
8067 * the connector is on the changing crtc but not on the new
8068 * connector list, disable it. */
8069 if ((!set->fb || ro == set->num_connectors) &&
8070 connector->base.encoder &&
8071 connector->base.encoder->crtc == set->crtc) {
8072 connector->new_encoder = NULL;
8073
8074 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8075 connector->base.base.id,
8076 drm_get_connector_name(&connector->base));
8077 }
8078
8079
8080 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8081 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8082 config->mode_changed = true;
50f56119
DV		 8083 }
8084 }
9a935856 8085 /* connector->new_encoder is now updated for all connectors. */
50f56119 8086
9a935856 8087 /* Update crtc of enabled connectors. */
50f56119 8088 count = 0;
9a935856
DV		 8089 list_for_each_entry(connector, &dev->mode_config.connector_list,
8090 base.head) {
8091 if (!connector->new_encoder)
50f56119
DV		 8092 continue;
8093
9a935856 8094 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8095
8096 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8097 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8098 new_crtc = set->crtc;
8099 }
8100
8101 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8102 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8103 new_crtc)) {
5e2b584e 8104 return -EINVAL;
50f56119 8105 }
9a935856
DV		 8106 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8107
8108 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8109 connector->base.base.id,
8110 drm_get_connector_name(&connector->base),
8111 new_crtc->base.id);
8112 }
8113
8114 /* Check for any encoders that needs to be disabled. */
8115 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8116 base.head) {
8117 list_for_each_entry(connector,
8118 &dev->mode_config.connector_list,
8119 base.head) {
8120 if (connector->new_encoder == encoder) {
8121 WARN_ON(!connector->new_encoder->new_crtc);
8122
8123 goto next_encoder;
8124 }
8125 }
8126 encoder->new_crtc = NULL;
8127next_encoder:
8128 /* Only now check for crtc changes so we don't miss encoders
8129 * that will be disabled. */
8130 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8131 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8132 config->mode_changed = true;
50f56119
DV		 8133 }
8134 }
9a935856 8135 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8136
2e431051
DV		 8137 return 0;
8138}
8139
8140static int intel_crtc_set_config(struct drm_mode_set *set)
8141{
8142 struct drm_device *dev;
2e431051
DV		 8143 struct drm_mode_set save_set;
8144 struct intel_set_config *config;
8145 int ret;
2e431051 8146
8d3e375e
DV		 8147 BUG_ON(!set);
8148 BUG_ON(!set->crtc);
8149 BUG_ON(!set->crtc->helper_private);
2e431051 8150
7e53f3a4
DV		 8151 /* Enforce sane interface api - has been abused by the fb helper. */
8152 BUG_ON(!set->mode && set->fb);
8153 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8154
2e431051
DV		 8155 if (set->fb) {
8156 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8157 set->crtc->base.id, set->fb->base.id,
8158 (int)set->num_connectors, set->x, set->y);
8159 } else {
8160 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8161 }
8162
8163 dev = set->crtc->dev;
8164
8165 ret = -ENOMEM;
8166 config = kzalloc(sizeof(*config), GFP_KERNEL);
8167 if (!config)
8168 goto out_config;
8169
8170 ret = intel_set_config_save_state(dev, config);
8171 if (ret)
8172 goto out_config;
8173
8174 save_set.crtc = set->crtc;
8175 save_set.mode = &set->crtc->mode;
8176 save_set.x = set->crtc->x;
8177 save_set.y = set->crtc->y;
8178 save_set.fb = set->crtc->fb;
8179
8180 /* Compute whether we need a full modeset, only an fb base update or no
8181 * change at all. In the future we might also check whether only the
8182 * mode changed, e.g. for LVDS where we only change the panel fitter in
8183 * such cases. */
8184 intel_set_config_compute_mode_changes(set, config);
8185
9a935856 8186 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8187 if (ret)
8188 goto fail;
8189
5e2b584e 8190 if (config->mode_changed) {
87f1faa6 8191 if (set->mode) {
50f56119
DV		 8192 DRM_DEBUG_KMS("attempting to set mode from"
8193 " userspace\n");
8194 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8195 }
8196
c0c36b94
CW		 8197 ret = intel_set_mode(set->crtc, set->mode,
8198 set->x, set->y, set->fb);
8199 if (ret) {
8200 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8201 set->crtc->base.id, ret);
87f1faa6
DV		 8202 goto fail;
8203 }
5e2b584e 8204 } else if (config->fb_changed) {
4878cae2
VS		 8205 intel_crtc_wait_for_pending_flips(set->crtc);
8206
4f660f49 8207 ret = intel_pipe_set_base(set->crtc,
94352cf9 8208 set->x, set->y, set->fb);
50f56119
DV		 8209 }
8210
d9e55608
DV		 8211 intel_set_config_free(config);
8212
50f56119
DV		 8213 return 0;
8214
8215fail:
85f9eb71 8216 intel_set_config_restore_state(dev, config);
50f56119
DV		 8217
8218 /* Try to restore the config */
5e2b584e 8219 if (config->mode_changed &&
c0c36b94
CW		 8220 intel_set_mode(save_set.crtc, save_set.mode,
8221 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8222 DRM_ERROR("failed to restore config after modeset failure\n");
8223
d9e55608
DV		 8224out_config:
8225 intel_set_config_free(config);
50f56119
DV		 8226 return ret;
8227}
f6e5b160
CW		 8228
8229static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8230 .cursor_set = intel_crtc_cursor_set,
8231 .cursor_move = intel_crtc_cursor_move,
8232 .gamma_set = intel_crtc_gamma_set,
50f56119 8233 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8234 .destroy = intel_crtc_destroy,
8235 .page_flip = intel_crtc_page_flip,
8236};
8237
79f689aa
PZ		 8238static void intel_cpu_pll_init(struct drm_device *dev)
8239{
affa9354 8240 if (HAS_DDI(dev))
79f689aa
PZ		 8241 intel_ddi_pll_init(dev);
8242}
8243
ee7b9f93
JB		 8244static void intel_pch_pll_init(struct drm_device *dev)
8245{
8246 drm_i915_private_t *dev_priv = dev->dev_private;
8247 int i;
8248
8249 if (dev_priv->num_pch_pll == 0) {
8250 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8251 return;
8252 }
8253
8254 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8255 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8256 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8257 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8258 }
8259}
8260
b358d0a6 8261static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8262{
22fd0fab 8263 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8264 struct intel_crtc *intel_crtc;
8265 int i;
8266
8267 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8268 if (intel_crtc == NULL)
8269 return;
8270
8271 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8272
8273 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8274 for (i = 0; i < 256; i++) {
8275 intel_crtc->lut_r[i] = i;
8276 intel_crtc->lut_g[i] = i;
8277 intel_crtc->lut_b[i] = i;
8278 }
8279
80824003
JB		 8280 /* Swap pipes & planes for FBC on pre-965 */
8281 intel_crtc->pipe = pipe;
8282 intel_crtc->plane = pipe;
a5c961d1 8283 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8284 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8285 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8286 intel_crtc->plane = !pipe;
80824003
JB		 8287 }
8288
22fd0fab
JB		 8289 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8290 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8291 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8292 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8293
5a354204 8294 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8295
79e53945 8296 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8297}
8298
08d7b3d1 8299int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8300 struct drm_file *file)
08d7b3d1 8301{
08d7b3d1 8302 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8303 struct drm_mode_object *drmmode_obj;
8304 struct intel_crtc *crtc;
08d7b3d1 8305
1cff8f6b
DV		 8306 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8307 return -ENODEV;
08d7b3d1 8308
c05422d5
DV		 8309 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8310 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8311
c05422d5 8312 if (!drmmode_obj) {
08d7b3d1
CW		 8313 DRM_ERROR("no such CRTC id\n");
8314 return -EINVAL;
8315 }
8316
c05422d5
DV		 8317 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8318 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8319
c05422d5 8320 return 0;
08d7b3d1
CW		 8321}
8322
66a9278e 8323static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8324{
66a9278e
DV		 8325 struct drm_device *dev = encoder->base.dev;
8326 struct intel_encoder *source_encoder;
79e53945 8327 int index_mask = 0;
79e53945
JB		 8328 int entry = 0;
8329
66a9278e
DV		 8330 list_for_each_entry(source_encoder,
8331 &dev->mode_config.encoder_list, base.head) {
8332
8333 if (encoder == source_encoder)
79e53945 8334 index_mask |= (1 << entry);
66a9278e
DV		 8335
8336 /* Intel hw has only one MUX where enocoders could be cloned. */
8337 if (encoder->cloneable && source_encoder->cloneable)
8338 index_mask |= (1 << entry);
8339
79e53945
JB		 8340 entry++;
8341 }
4ef69c7a 8342
79e53945
JB		 8343 return index_mask;
8344}
8345
4d302442
CW		 8346static bool has_edp_a(struct drm_device *dev)
8347{
8348 struct drm_i915_private *dev_priv = dev->dev_private;
8349
8350 if (!IS_MOBILE(dev))
8351 return false;
8352
8353 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8354 return false;
8355
8356 if (IS_GEN5(dev) &&
8357 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8358 return false;
8359
8360 return true;
8361}
8362
79e53945
JB		 8363static void intel_setup_outputs(struct drm_device *dev)
8364{
725e30ad 8365 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8366 struct intel_encoder *encoder;
cb0953d7 8367 bool dpd_is_edp = false;
f3cfcba6 8368 bool has_lvds;
79e53945 8369
f3cfcba6 8370 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8371 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8372 /* disable the panel fitter on everything but LVDS */
8373 I915_WRITE(PFIT_CONTROL, 0);
8374 }
79e53945 8375
affa9354 8376 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8377 intel_crt_init(dev);
cb0953d7 8378
affa9354 8379 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8380 int found;
8381
8382 /* Haswell uses DDI functions to detect digital outputs */
8383 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8384 /* DDI A only supports eDP */
8385 if (found)
8386 intel_ddi_init(dev, PORT_A);
8387
8388 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8389 * register */
8390 found = I915_READ(SFUSE_STRAP);
8391
8392 if (found & SFUSE_STRAP_DDIB_DETECTED)
8393 intel_ddi_init(dev, PORT_B);
8394 if (found & SFUSE_STRAP_DDIC_DETECTED)
8395 intel_ddi_init(dev, PORT_C);
8396 if (found & SFUSE_STRAP_DDID_DETECTED)
8397 intel_ddi_init(dev, PORT_D);
8398 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8399 int found;
270b3042
DV		 8400 dpd_is_edp = intel_dpd_is_edp(dev);
8401
8402 if (has_edp_a(dev))
8403 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8404
dc0fa718 8405 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8406 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8407 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8408 if (!found)
e2debe91 8409 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8410 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8411 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8412 }
8413
dc0fa718 8414 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8415 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8416
dc0fa718 8417 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8418 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8419
5eb08b69 8420 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8421 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8422
270b3042 8423 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8424 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8425 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8426 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8427 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8428 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8429
dc0fa718 8430 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8431 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8432 PORT_B);
67cfc203
VS		 8433 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8434 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8435 }
103a196f 8436 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8437 bool found = false;
7d57382e 8438
e2debe91 8439 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8440 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8441 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8442 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8443 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8444 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8445 }
27185ae1 8446
b01f2c3a
JB		 8447 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8448 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8449 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8450 }
725e30ad 8451 }
13520b05
KH		 8452
8453 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8454
e2debe91 8455 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8456 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8457 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8458 }
27185ae1 8459
e2debe91 8460 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8461
b01f2c3a
JB		 8462 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8463 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8464 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8465 }
8466 if (SUPPORTS_INTEGRATED_DP(dev)) {
8467 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8468 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8469 }
725e30ad 8470 }
27185ae1 8471
b01f2c3a
JB		 8472 if (SUPPORTS_INTEGRATED_DP(dev) &&
8473 (I915_READ(DP_D) & DP_DETECTED)) {
8474 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8475 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8476 }
bad720ff 8477 } else if (IS_GEN2(dev))
79e53945
JB		 8478 intel_dvo_init(dev);
8479
103a196f 8480 if (SUPPORTS_TV(dev))
79e53945
JB		 8481 intel_tv_init(dev);
8482
4ef69c7a
CW		 8483 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8484 encoder->base.possible_crtcs = encoder->crtc_mask;
8485 encoder->base.possible_clones =
66a9278e 8486 intel_encoder_clones(encoder);
79e53945 8487 }
47356eb6 8488
dde86e2d 8489 intel_init_pch_refclk(dev);
270b3042
DV		 8490
8491 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8492}
8493
8494static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8495{
8496 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8497
8498 drm_framebuffer_cleanup(fb);
05394f39 8499 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8500
8501 kfree(intel_fb);
8502}
8503
8504static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8505 struct drm_file *file,
79e53945
JB		 8506 unsigned int *handle)
8507{
8508 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8509 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8510
05394f39 8511 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8512}
8513
8514static const struct drm_framebuffer_funcs intel_fb_funcs = {
8515 .destroy = intel_user_framebuffer_destroy,
8516 .create_handle = intel_user_framebuffer_create_handle,
8517};
8518
38651674
DA		 8519int intel_framebuffer_init(struct drm_device *dev,
8520 struct intel_framebuffer *intel_fb,
308e5bcb 8521 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8522 struct drm_i915_gem_object *obj)
79e53945 8523{
79e53945
JB		 8524 int ret;
8525
c16ed4be
CW		 8526 if (obj->tiling_mode == I915_TILING_Y) {
8527 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8528 return -EINVAL;
c16ed4be 8529 }
57cd6508 8530
c16ed4be
CW		 8531 if (mode_cmd->pitches[0] & 63) {
8532 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8533 mode_cmd->pitches[0]);
57cd6508 8534 return -EINVAL;
c16ed4be 8535 }
57cd6508 8536
5d7bd705 8537 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8538 if (mode_cmd->pitches[0] > 32768) {
8539 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8540 mode_cmd->pitches[0]);
5d7bd705 8541 return -EINVAL;
c16ed4be 8542 }
5d7bd705
VS		 8543
8544 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8545 mode_cmd->pitches[0] != obj->stride) {
8546 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8547 mode_cmd->pitches[0], obj->stride);
5d7bd705 8548 return -EINVAL;
c16ed4be 8549 }
5d7bd705 8550
57779d06 8551 /* Reject formats not supported by any plane early. */
308e5bcb 8552 switch (mode_cmd->pixel_format) {
57779d06 8553 case DRM_FORMAT_C8:
04b3924d
VS		 8554 case DRM_FORMAT_RGB565:
8555 case DRM_FORMAT_XRGB8888:
8556 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8557 break;
8558 case DRM_FORMAT_XRGB1555:
8559 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8560 if (INTEL_INFO(dev)->gen > 3) {
8561 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8562 return -EINVAL;
c16ed4be 8563 }
57779d06
VS		 8564 break;
8565 case DRM_FORMAT_XBGR8888:
8566 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8567 case DRM_FORMAT_XRGB2101010:
8568 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8569 case DRM_FORMAT_XBGR2101010:
8570 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8571 if (INTEL_INFO(dev)->gen < 4) {
8572 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8573 return -EINVAL;
c16ed4be 8574 }
b5626747 8575 break;
04b3924d
VS		 8576 case DRM_FORMAT_YUYV:
8577 case DRM_FORMAT_UYVY:
8578 case DRM_FORMAT_YVYU:
8579 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8580 if (INTEL_INFO(dev)->gen < 5) {
8581 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8582 return -EINVAL;
c16ed4be 8583 }
57cd6508
CW		 8584 break;
8585 default:
c16ed4be 8586 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8587 return -EINVAL;
8588 }
8589
90f9a336
VS		 8590 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8591 if (mode_cmd->offsets[0] != 0)
8592 return -EINVAL;
8593
c7d73f6a
DV		 8594 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8595 intel_fb->obj = obj;
8596
79e53945
JB		 8597 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8598 if (ret) {
8599 DRM_ERROR("framebuffer init failed %d\n", ret);
8600 return ret;
8601 }
8602
79e53945
JB		 8603 return 0;
8604}
8605
79e53945
JB		 8606static struct drm_framebuffer *
8607intel_user_framebuffer_create(struct drm_device *dev,
8608 struct drm_file *filp,
308e5bcb 8609 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8610{
05394f39 8611 struct drm_i915_gem_object *obj;
79e53945 8612
308e5bcb
JB		 8613 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8614 mode_cmd->handles[0]));
c8725226 8615 if (&obj->base == NULL)
cce13ff7 8616 return ERR_PTR(-ENOENT);
79e53945 8617
d2dff872 8618 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8619}
8620
79e53945 8621static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8622 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8623 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8624};
8625
e70236a8
JB		 8626/* Set up chip specific display functions */
8627static void intel_init_display(struct drm_device *dev)
8628{
8629 struct drm_i915_private *dev_priv = dev->dev_private;
8630
affa9354 8631 if (HAS_DDI(dev)) {
09b4ddf9 8632 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8633 dev_priv->display.crtc_enable = haswell_crtc_enable;
8634 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8635 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8636 dev_priv->display.update_plane = ironlake_update_plane;
8637 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8638 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8639 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8640 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8641 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8642 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8643 } else {
f564048e 8644 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8645 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8646 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8647 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8648 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8649 }
e70236a8 8650
e70236a8 8651 /* Returns the core display clock speed */
25eb05fc
JB		 8652 if (IS_VALLEYVIEW(dev))
8653 dev_priv->display.get_display_clock_speed =
8654 valleyview_get_display_clock_speed;
8655 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8656 dev_priv->display.get_display_clock_speed =
8657 i945_get_display_clock_speed;
8658 else if (IS_I915G(dev))
8659 dev_priv->display.get_display_clock_speed =
8660 i915_get_display_clock_speed;
f2b115e6 8661 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8662 dev_priv->display.get_display_clock_speed =
8663 i9xx_misc_get_display_clock_speed;
8664 else if (IS_I915GM(dev))
8665 dev_priv->display.get_display_clock_speed =
8666 i915gm_get_display_clock_speed;
8667 else if (IS_I865G(dev))
8668 dev_priv->display.get_display_clock_speed =
8669 i865_get_display_clock_speed;
f0f8a9ce 8670 else if (IS_I85X(dev))
e70236a8
JB		 8671 dev_priv->display.get_display_clock_speed =
8672 i855_get_display_clock_speed;
8673 else /* 852, 830 */
8674 dev_priv->display.get_display_clock_speed =
8675 i830_get_display_clock_speed;
8676
7f8a8569 8677 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8678 if (IS_GEN5(dev)) {
674cf967 8679 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8680 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8681 } else if (IS_GEN6(dev)) {
674cf967 8682 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8683 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8684 } else if (IS_IVYBRIDGE(dev)) {
8685 /* FIXME: detect B0+ stepping and use auto training */
8686 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8687 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8688 dev_priv->display.modeset_global_resources =
8689 ivb_modeset_global_resources;
c82e4d26
ED		 8690 } else if (IS_HASWELL(dev)) {
8691 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8692 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8693 dev_priv->display.modeset_global_resources =
8694 haswell_modeset_global_resources;
a0e63c22 8695 }
6067aaea 8696 } else if (IS_G4X(dev)) {
e0dac65e 8697 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8698 }
8c9f3aaf
JB		 8699
8700 /* Default just returns -ENODEV to indicate unsupported */
8701 dev_priv->display.queue_flip = intel_default_queue_flip;
8702
8703 switch (INTEL_INFO(dev)->gen) {
8704 case 2:
8705 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8706 break;
8707
8708 case 3:
8709 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8710 break;
8711
8712 case 4:
8713 case 5:
8714 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8715 break;
8716
8717 case 6:
8718 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8719 break;
7c9017e5
JB		 8720 case 7:
8721 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8722 break;
8c9f3aaf 8723 }
e70236a8
JB		 8724}
8725
b690e96c
JB		 8726/*
8727 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8728 * resume, or other times. This quirk makes sure that's the case for
8729 * affected systems.
8730 */
0206e353 8731static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8732{
8733 struct drm_i915_private *dev_priv = dev->dev_private;
8734
8735 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8736 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8737}
8738
435793df
KP		 8739/*
8740 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8741 */
8742static void quirk_ssc_force_disable(struct drm_device *dev)
8743{
8744 struct drm_i915_private *dev_priv = dev->dev_private;
8745 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8746 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8747}
8748
4dca20ef 8749/*
5a15ab5b
CE		 8750 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8751 * brightness value
4dca20ef
CE		 8752 */
8753static void quirk_invert_brightness(struct drm_device *dev)
8754{
8755 struct drm_i915_private *dev_priv = dev->dev_private;
8756 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8757 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8758}
8759
b690e96c
JB		 8760struct intel_quirk {
8761 int device;
8762 int subsystem_vendor;
8763 int subsystem_device;
8764 void (*hook)(struct drm_device *dev);
8765};
8766
5f85f176
EE		 8767/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8768struct intel_dmi_quirk {
8769 void (*hook)(struct drm_device *dev);
8770 const struct dmi_system_id (*dmi_id_list)[];
8771};
8772
8773static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8774{
8775 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8776 return 1;
8777}
8778
8779static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8780 {
8781 .dmi_id_list = &(const struct dmi_system_id[]) {
8782 {
8783 .callback = intel_dmi_reverse_brightness,
8784 .ident = "NCR Corporation",
8785 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8786 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8787 },
8788 },
8789 { } /* terminating entry */
8790 },
8791 .hook = quirk_invert_brightness,
8792 },
8793};
8794
c43b5634 8795static struct intel_quirk intel_quirks[] = {
b690e96c 8796 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8797 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8798
b690e96c
JB		 8799 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8800 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8801
b690e96c
JB		 8802 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8803 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8804
ccd0d36e 8805 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8806 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8807 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8808
8809 /* Lenovo U160 cannot use SSC on LVDS */
8810 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8811
8812 /* Sony Vaio Y cannot use SSC on LVDS */
8813 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8814
8815 /* Acer Aspire 5734Z must invert backlight brightness */
8816 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8817
8818 /* Acer/eMachines G725 */
8819 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8820
8821 /* Acer/eMachines e725 */
8822 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8823
8824 /* Acer/Packard Bell NCL20 */
8825 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 8826
8827 /* Acer Aspire 4736Z */
8828 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 8829};
8830
8831static void intel_init_quirks(struct drm_device *dev)
8832{
8833 struct pci_dev *d = dev->pdev;
8834 int i;
8835
8836 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8837 struct intel_quirk *q = &intel_quirks[i];
8838
8839 if (d->device == q->device &&
8840 (d->subsystem_vendor == q->subsystem_vendor ||
8841 q->subsystem_vendor == PCI_ANY_ID) &&
8842 (d->subsystem_device == q->subsystem_device ||
8843 q->subsystem_device == PCI_ANY_ID))
8844 q->hook(dev);
8845 }
5f85f176
EE		 8846 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8847 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8848 intel_dmi_quirks[i].hook(dev);
8849 }
b690e96c
JB		 8850}
8851
9cce37f4
JB		 8852/* Disable the VGA plane that we never use */
8853static void i915_disable_vga(struct drm_device *dev)
8854{
8855 struct drm_i915_private *dev_priv = dev->dev_private;
8856 u8 sr1;
766aa1c4 8857 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 8858
8859 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8860 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8861 sr1 = inb(VGA_SR_DATA);
8862 outb(sr1 | 1<<5, VGA_SR_DATA);
8863 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8864 udelay(300);
8865
8866 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8867 POSTING_READ(vga_reg);
8868}
8869
f817586c
DV		 8870void intel_modeset_init_hw(struct drm_device *dev)
8871{
fa42e23c 8872 intel_init_power_well(dev);
0232e927 8873
a8f78b58
ED		 8874 intel_prepare_ddi(dev);
8875
f817586c
DV		 8876 intel_init_clock_gating(dev);
8877
79f5b2c7 8878 mutex_lock(&dev->struct_mutex);
8090c6b9 8879 intel_enable_gt_powersave(dev);
79f5b2c7 8880 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8881}
8882
79e53945
JB		 8883void intel_modeset_init(struct drm_device *dev)
8884{
652c393a 8885 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8886 int i, ret;
79e53945
JB		 8887
8888 drm_mode_config_init(dev);
8889
8890 dev->mode_config.min_width = 0;
8891 dev->mode_config.min_height = 0;
8892
019d96cb
DA		 8893 dev->mode_config.preferred_depth = 24;
8894 dev->mode_config.prefer_shadow = 1;
8895
e6ecefaa 8896 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8897
b690e96c
JB		 8898 intel_init_quirks(dev);
8899
1fa61106
ED		 8900 intel_init_pm(dev);
8901
e70236a8
JB		 8902 intel_init_display(dev);
8903
a6c45cf0
CW		 8904 if (IS_GEN2(dev)) {
8905 dev->mode_config.max_width = 2048;
8906 dev->mode_config.max_height = 2048;
8907 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8908 dev->mode_config.max_width = 4096;
8909 dev->mode_config.max_height = 4096;
79e53945 8910 } else {
a6c45cf0
CW		 8911 dev->mode_config.max_width = 8192;
8912 dev->mode_config.max_height = 8192;
79e53945 8913 }
5d4545ae 8914 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 8915
28c97730 8916 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 8917 INTEL_INFO(dev)->num_pipes,
8918 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 8919
7eb552ae 8920 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 8921 intel_crtc_init(dev, i);
00c2064b
JB		 8922 ret = intel_plane_init(dev, i);
8923 if (ret)
8924 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8925 }
8926
79f689aa 8927 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8928 intel_pch_pll_init(dev);
8929
9cce37f4
JB		 8930 /* Just disable it once at startup */
8931 i915_disable_vga(dev);
79e53945 8932 intel_setup_outputs(dev);
11be49eb
CW		 8933
8934 /* Just in case the BIOS is doing something questionable. */
8935 intel_disable_fbc(dev);
2c7111db
CW		 8936}
8937
24929352
DV		 8938static void
8939intel_connector_break_all_links(struct intel_connector *connector)
8940{
8941 connector->base.dpms = DRM_MODE_DPMS_OFF;
8942 connector->base.encoder = NULL;
8943 connector->encoder->connectors_active = false;
8944 connector->encoder->base.crtc = NULL;
8945}
8946
7fad798e
DV		 8947static void intel_enable_pipe_a(struct drm_device *dev)
8948{
8949 struct intel_connector *connector;
8950 struct drm_connector *crt = NULL;
8951 struct intel_load_detect_pipe load_detect_temp;
8952
8953 /* We can't just switch on the pipe A, we need to set things up with a
8954 * proper mode and output configuration. As a gross hack, enable pipe A
8955 * by enabling the load detect pipe once. */
8956 list_for_each_entry(connector,
8957 &dev->mode_config.connector_list,
8958 base.head) {
8959 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8960 crt = &connector->base;
8961 break;
8962 }
8963 }
8964
8965 if (!crt)
8966 return;
8967
8968 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8969 intel_release_load_detect_pipe(crt, &load_detect_temp);
8970
652c393a 8971
7fad798e
DV		 8972}
8973
fa555837
DV		 8974static bool
8975intel_check_plane_mapping(struct intel_crtc *crtc)
8976{
7eb552ae
BW		 8977 struct drm_device *dev = crtc->base.dev;
8978 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 8979 u32 reg, val;
8980
7eb552ae 8981 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 8982 return true;
8983
8984 reg = DSPCNTR(!crtc->plane);
8985 val = I915_READ(reg);
8986
8987 if ((val & DISPLAY_PLANE_ENABLE) &&
8988 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8989 return false;
8990
8991 return true;
8992}
8993
24929352
DV		 8994static void intel_sanitize_crtc(struct intel_crtc *crtc)
8995{
8996 struct drm_device *dev = crtc->base.dev;
8997 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8998 u32 reg;
24929352 8999
24929352 9000 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 9001 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 9002 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9003
9004 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9005 * disable the crtc (and hence change the state) if it is wrong. Note
9006 * that gen4+ has a fixed plane -> pipe mapping. */
9007 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9008 struct intel_connector *connector;
9009 bool plane;
9010
24929352
DV		 9011 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9012 crtc->base.base.id);
9013
9014 /* Pipe has the wrong plane attached and the plane is active.
9015 * Temporarily change the plane mapping and disable everything
9016 * ... */
9017 plane = crtc->plane;
9018 crtc->plane = !plane;
9019 dev_priv->display.crtc_disable(&crtc->base);
9020 crtc->plane = plane;
9021
9022 /* ... and break all links. */
9023 list_for_each_entry(connector, &dev->mode_config.connector_list,
9024 base.head) {
9025 if (connector->encoder->base.crtc != &crtc->base)
9026 continue;
9027
9028 intel_connector_break_all_links(connector);
9029 }
9030
9031 WARN_ON(crtc->active);
9032 crtc->base.enabled = false;
9033 }
24929352 9034
7fad798e
DV		 9035 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9036 crtc->pipe == PIPE_A && !crtc->active) {
9037 /* BIOS forgot to enable pipe A, this mostly happens after
9038 * resume. Force-enable the pipe to fix this, the update_dpms
9039 * call below we restore the pipe to the right state, but leave
9040 * the required bits on. */
9041 intel_enable_pipe_a(dev);
9042 }
9043
24929352
DV		 9044 /* Adjust the state of the output pipe according to whether we
9045 * have active connectors/encoders. */
9046 intel_crtc_update_dpms(&crtc->base);
9047
9048 if (crtc->active != crtc->base.enabled) {
9049 struct intel_encoder *encoder;
9050
9051 /* This can happen either due to bugs in the get_hw_state
9052 * functions or because the pipe is force-enabled due to the
9053 * pipe A quirk. */
9054 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9055 crtc->base.base.id,
9056 crtc->base.enabled ? "enabled" : "disabled",
9057 crtc->active ? "enabled" : "disabled");
9058
9059 crtc->base.enabled = crtc->active;
9060
9061 /* Because we only establish the connector -> encoder ->
9062 * crtc links if something is active, this means the
9063 * crtc is now deactivated. Break the links. connector
9064 * -> encoder links are only establish when things are
9065 * actually up, hence no need to break them. */
9066 WARN_ON(crtc->active);
9067
9068 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9069 WARN_ON(encoder->connectors_active);
9070 encoder->base.crtc = NULL;
9071 }
9072 }
9073}
9074
9075static void intel_sanitize_encoder(struct intel_encoder *encoder)
9076{
9077 struct intel_connector *connector;
9078 struct drm_device *dev = encoder->base.dev;
9079
9080 /* We need to check both for a crtc link (meaning that the
9081 * encoder is active and trying to read from a pipe) and the
9082 * pipe itself being active. */
9083 bool has_active_crtc = encoder->base.crtc &&
9084 to_intel_crtc(encoder->base.crtc)->active;
9085
9086 if (encoder->connectors_active && !has_active_crtc) {
9087 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9088 encoder->base.base.id,
9089 drm_get_encoder_name(&encoder->base));
9090
9091 /* Connector is active, but has no active pipe. This is
9092 * fallout from our resume register restoring. Disable
9093 * the encoder manually again. */
9094 if (encoder->base.crtc) {
9095 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9096 encoder->base.base.id,
9097 drm_get_encoder_name(&encoder->base));
9098 encoder->disable(encoder);
9099 }
9100
9101 /* Inconsistent output/port/pipe state happens presumably due to
9102 * a bug in one of the get_hw_state functions. Or someplace else
9103 * in our code, like the register restore mess on resume. Clamp
9104 * things to off as a safer default. */
9105 list_for_each_entry(connector,
9106 &dev->mode_config.connector_list,
9107 base.head) {
9108 if (connector->encoder != encoder)
9109 continue;
9110
9111 intel_connector_break_all_links(connector);
9112 }
9113 }
9114 /* Enabled encoders without active connectors will be fixed in
9115 * the crtc fixup. */
9116}
9117
44cec740 9118void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9119{
9120 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9121 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9122
9123 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9124 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9125 i915_disable_vga(dev);
0fde901f
KM		 9126 }
9127}
9128
24929352
DV		 9129/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9130 * and i915 state tracking structures. */
45e2b5f6
DV		 9131void intel_modeset_setup_hw_state(struct drm_device *dev,
9132 bool force_restore)
24929352
DV		 9133{
9134 struct drm_i915_private *dev_priv = dev->dev_private;
9135 enum pipe pipe;
9136 u32 tmp;
b5644d05 9137 struct drm_plane *plane;
24929352
DV		 9138 struct intel_crtc *crtc;
9139 struct intel_encoder *encoder;
9140 struct intel_connector *connector;
9141
affa9354 9142 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9143 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9144
9145 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9146 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9147 case TRANS_DDI_EDP_INPUT_A_ON:
9148 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9149 pipe = PIPE_A;
9150 break;
9151 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9152 pipe = PIPE_B;
9153 break;
9154 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9155 pipe = PIPE_C;
9156 break;
aaa148ec
DL		 9157 default:
9158 /* A bogus value has been programmed, disable
9159 * the transcoder */
9160 WARN(1, "Bogus eDP source %08x\n", tmp);
9161 intel_ddi_disable_transcoder_func(dev_priv,
9162 TRANSCODER_EDP);
9163 goto setup_pipes;
e28d54cb
PZ		 9164 }
9165
9166 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9167 crtc->cpu_transcoder = TRANSCODER_EDP;
9168
9169 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9170 pipe_name(pipe));
9171 }
9172 }
9173
aaa148ec 9174setup_pipes:
24929352
DV		 9175 for_each_pipe(pipe) {
9176 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9177
702e7a56 9178 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9179 if (tmp & PIPECONF_ENABLE)
9180 crtc->active = true;
9181 else
9182 crtc->active = false;
9183
9184 crtc->base.enabled = crtc->active;
9185
9186 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9187 crtc->base.base.id,
9188 crtc->active ? "enabled" : "disabled");
9189 }
9190
affa9354 9191 if (HAS_DDI(dev))
6441ab5f
PZ		 9192 intel_ddi_setup_hw_pll_state(dev);
9193
24929352
DV		 9194 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9195 base.head) {
9196 pipe = 0;
9197
9198 if (encoder->get_hw_state(encoder, &pipe)) {
9199 encoder->base.crtc =
9200 dev_priv->pipe_to_crtc_mapping[pipe];
9201 } else {
9202 encoder->base.crtc = NULL;
9203 }
9204
9205 encoder->connectors_active = false;
9206 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9207 encoder->base.base.id,
9208 drm_get_encoder_name(&encoder->base),
9209 encoder->base.crtc ? "enabled" : "disabled",
9210 pipe);
9211 }
9212
9213 list_for_each_entry(connector, &dev->mode_config.connector_list,
9214 base.head) {
9215 if (connector->get_hw_state(connector)) {
9216 connector->base.dpms = DRM_MODE_DPMS_ON;
9217 connector->encoder->connectors_active = true;
9218 connector->base.encoder = &connector->encoder->base;
9219 } else {
9220 connector->base.dpms = DRM_MODE_DPMS_OFF;
9221 connector->base.encoder = NULL;
9222 }
9223 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9224 connector->base.base.id,
9225 drm_get_connector_name(&connector->base),
9226 connector->base.encoder ? "enabled" : "disabled");
9227 }
9228
9229 /* HW state is read out, now we need to sanitize this mess. */
9230 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9231 base.head) {
9232 intel_sanitize_encoder(encoder);
9233 }
9234
9235 for_each_pipe(pipe) {
9236 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9237 intel_sanitize_crtc(crtc);
9238 }
9a935856 9239
45e2b5f6
DV		 9240 if (force_restore) {
9241 for_each_pipe(pipe) {
b5644d05
JB		 9242 struct drm_crtc *crtc =
9243 dev_priv->pipe_to_crtc_mapping[pipe];
9244 intel_crtc_restore_mode(crtc);
45e2b5f6 9245 }
b5644d05
JB		 9246 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9247 intel_plane_restore(plane);
0fde901f
KM		 9248
9249 i915_redisable_vga(dev);
45e2b5f6
DV		 9250 } else {
9251 intel_modeset_update_staged_output_state(dev);
9252 }
8af6cf88
DV		 9253
9254 intel_modeset_check_state(dev);
2e938892
DV		 9255
9256 drm_mode_config_reset(dev);
2c7111db
CW		 9257}
9258
9259void intel_modeset_gem_init(struct drm_device *dev)
9260{
1833b134 9261 intel_modeset_init_hw(dev);
02e792fb
DV		 9262
9263 intel_setup_overlay(dev);
24929352 9264
45e2b5f6 9265 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9266}
9267
9268void intel_modeset_cleanup(struct drm_device *dev)
9269{
652c393a
JB		 9270 struct drm_i915_private *dev_priv = dev->dev_private;
9271 struct drm_crtc *crtc;
9272 struct intel_crtc *intel_crtc;
9273
f87ea761 9274 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9275 mutex_lock(&dev->struct_mutex);
9276
723bfd70
JB		 9277 intel_unregister_dsm_handler();
9278
9279
652c393a
JB		 9280 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9281 /* Skip inactive CRTCs */
9282 if (!crtc->fb)
9283 continue;
9284
9285 intel_crtc = to_intel_crtc(crtc);
3dec0095 9286 intel_increase_pllclock(crtc);
652c393a
JB		 9287 }
9288
973d04f9 9289 intel_disable_fbc(dev);
e70236a8 9290
8090c6b9 9291 intel_disable_gt_powersave(dev);
0cdab21f 9292
930ebb46
DV		 9293 ironlake_teardown_rc6(dev);
9294
57f350b6
JB		 9295 if (IS_VALLEYVIEW(dev))
9296 vlv_init_dpio(dev);
9297
69341a5e
KH		 9298 mutex_unlock(&dev->struct_mutex);
9299
6c0d9350
DV		 9300 /* Disable the irq before mode object teardown, for the irq might
9301 * enqueue unpin/hotplug work. */
9302 drm_irq_uninstall(dev);
9303 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9304 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9305
1630fe75
CW		 9306 /* flush any delayed tasks or pending work */
9307 flush_scheduled_work();
9308
79e53945 9309 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9310
9311 intel_cleanup_overlay(dev);
79e53945
JB		 9312}
9313
f1c79df3
ZW		 9314/*
9315 * Return which encoder is currently attached for connector.
9316 */
df0e9248 9317struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9318{
df0e9248
CW		 9319 return &intel_attached_encoder(connector)->base;
9320}
f1c79df3 9321
df0e9248
CW		 9322void intel_connector_attach_encoder(struct intel_connector *connector,
9323 struct intel_encoder *encoder)
9324{
9325 connector->encoder = encoder;
9326 drm_mode_connector_attach_encoder(&connector->base,
9327 &encoder->base);
79e53945 9328}
28d52043
DA		 9329
9330/*
9331 * set vga decode state - true == enable VGA decode
9332 */
9333int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9334{
9335 struct drm_i915_private *dev_priv = dev->dev_private;
9336 u16 gmch_ctrl;
9337
9338 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9339 if (state)
9340 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9341 else
9342 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9343 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9344 return 0;
9345}
c4a1d9e4
CW		 9346
9347#ifdef CONFIG_DEBUG_FS
9348#include <linux/seq_file.h>
9349
9350struct intel_display_error_state {
9351 struct intel_cursor_error_state {
9352 u32 control;
9353 u32 position;
9354 u32 base;
9355 u32 size;
52331309 9356 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9357
9358 struct intel_pipe_error_state {
9359 u32 conf;
9360 u32 source;
9361
9362 u32 htotal;
9363 u32 hblank;
9364 u32 hsync;
9365 u32 vtotal;
9366 u32 vblank;
9367 u32 vsync;
52331309 9368 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9369
9370 struct intel_plane_error_state {
9371 u32 control;
9372 u32 stride;
9373 u32 size;
9374 u32 pos;
9375 u32 addr;
9376 u32 surface;
9377 u32 tile_offset;
52331309 9378 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9379};
9380
9381struct intel_display_error_state *
9382intel_display_capture_error_state(struct drm_device *dev)
9383{
0206e353 9384 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9385 struct intel_display_error_state *error;
702e7a56 9386 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9387 int i;
9388
9389 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9390 if (error == NULL)
9391 return NULL;
9392
52331309 9393 for_each_pipe(i) {
702e7a56
PZ		 9394 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9395
a18c4c3d
PZ		 9396 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9397 error->cursor[i].control = I915_READ(CURCNTR(i));
9398 error->cursor[i].position = I915_READ(CURPOS(i));
9399 error->cursor[i].base = I915_READ(CURBASE(i));
9400 } else {
9401 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9402 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9403 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9404 }
c4a1d9e4
CW		 9405
9406 error->plane[i].control = I915_READ(DSPCNTR(i));
9407 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9408 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9409 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9410 error->plane[i].pos = I915_READ(DSPPOS(i));
9411 }
ca291363
PZ		 9412 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9413 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9414 if (INTEL_INFO(dev)->gen >= 4) {
9415 error->plane[i].surface = I915_READ(DSPSURF(i));
9416 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9417 }
9418
702e7a56 9419 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9420 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9421 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9422 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9423 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9424 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9425 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9426 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9427 }
9428
9429 return error;
9430}
9431
9432void
9433intel_display_print_error_state(struct seq_file *m,
9434 struct drm_device *dev,
9435 struct intel_display_error_state *error)
9436{
9437 int i;
9438
7eb552ae 9439 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9440 for_each_pipe(i) {
c4a1d9e4
CW		 9441 seq_printf(m, "Pipe [%d]:\n", i);
9442 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9443 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9444 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9445 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9446 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9447 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9448 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9449 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9450
9451 seq_printf(m, "Plane [%d]:\n", i);
9452 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9453 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9454 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9455 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9456 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9457 }
4b71a570 9458 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9459 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9460 if (INTEL_INFO(dev)->gen >= 4) {
9461 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9462 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9463 }
9464
9465 seq_printf(m, "Cursor [%d]:\n", i);
9466 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9467 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9468 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9469 }
9470}
9471#endif
Linux kernel - Deliverables
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