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drm/i915: convert DP autodither code to new infrastructure
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
f4808ab8
VS		 74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
d4906093 92};
79e53945 93
2377b741
JB		 94/* FDI */
95#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
d2acd215
DV		 97int
98intel_pch_rawclk(struct drm_device *dev)
99{
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105}
106
d4906093
ML		 107static bool
108intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
d4906093
ML		 111static bool
112intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
79e53945 115
a4fc5ed6
KP		 116static bool
117intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
5eb08b69 120static bool
f2b115e6 121intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
a4fc5ed6 124
a0c4da24
JB		 125static bool
126intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
021357ac
CW		 130static inline u32 /* units of 100MHz */
131intel_fdi_link_freq(struct drm_device *dev)
132{
8b99e68c
CW		 133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
021357ac
CW		 138}
139
e4b36699 140static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699 166};
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
d4906093 193 .find_pll = intel_find_best_PLL,
e4b36699
KP		 194};
195
273e27ca 196
e4b36699 197static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
d4906093 224 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 225};
226
227static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
044c7c41 238 },
d4906093 239 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
044c7c41 253 },
d4906093 254 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 255};
256
257static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
273e27ca 267 .p2_slow = 10, .p2_fast = 10 },
0206e353 268 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 274 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
273e27ca 277 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
f2b115e6 287static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
6115707b 298 .find_pll = intel_find_best_PLL,
e4b36699
KP		 299};
300
273e27ca
EA		 301/* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
4547668a 317 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 318};
319
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
273e27ca 348/* LVDS 100mhz refclk limits. */
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
0206e353 357 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
0206e353 371 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 374 .find_pll = intel_g4x_find_best_PLL,
375};
376
377static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
273e27ca 387 .p2_slow = 10, .p2_fast = 10 },
0206e353 388 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 389};
390
a0c4da24
JB		 391static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
17dc9257 407 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
419static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 422 .n = { .min = 1, .max = 7 },
74a4dd2e 423 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431};
432
57f350b6
JB		 433u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434{
09153000 435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 436
57f350b6
JB		 437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
09153000 439 return 0;
57f350b6
JB		 440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
09153000 447 return 0;
57f350b6 448 }
57f350b6 449
09153000 450 return I915_READ(DPIO_DATA);
57f350b6
JB		 451}
452
a0c4da24
JB		 453static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455{
09153000 456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 457
a0c4da24
JB		 458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
09153000 460 return;
a0c4da24
JB		 461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 469}
470
57f350b6
JB		 471static void vlv_init_dpio(struct drm_device *dev)
472{
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480}
481
1b894b59
CW		 482static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk)
2c07245f 484{
b91ad0ec 485 struct drm_device *dev = crtc->dev;
2c07245f 486 const intel_limit_t *limit;
b91ad0ec
ZW		 487
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 489 if (intel_is_dual_link_lvds(dev)) {
1b894b59 490 if (refclk == 100000)
b91ad0ec
ZW		 491 limit = &intel_limits_ironlake_dual_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_dual_lvds;
494 } else {
1b894b59 495 if (refclk == 100000)
b91ad0ec
ZW		 496 limit = &intel_limits_ironlake_single_lvds_100m;
497 else
498 limit = &intel_limits_ironlake_single_lvds;
499 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 502 limit = &intel_limits_ironlake_display_port;
2c07245f 503 else
b91ad0ec 504 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 505
506 return limit;
507}
508
044c7c41
ML		 509static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
510{
511 struct drm_device *dev = crtc->dev;
044c7c41
ML		 512 const intel_limit_t *limit;
513
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 515 if (intel_is_dual_link_lvds(dev))
e4b36699 516 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 517 else
e4b36699 518 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 521 limit = &intel_limits_g4x_hdmi;
044c7c41 522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 523 limit = &intel_limits_g4x_sdvo;
0206e353 524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 525 limit = &intel_limits_g4x_display_port;
044c7c41 526 } else /* The option is for other outputs */
e4b36699 527 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 528
529 return limit;
530}
531
1b894b59 532static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 533{
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
bad720ff 537 if (HAS_PCH_SPLIT(dev))
1b894b59 538 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 539 else if (IS_G4X(dev)) {
044c7c41 540 limit = intel_g4x_limit(crtc);
f2b115e6 541 } else if (IS_PINEVIEW(dev)) {
2177832f 542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 543 limit = &intel_limits_pineview_lvds;
2177832f 544 else
f2b115e6 545 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
551 else
552 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 558 } else {
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 560 limit = &intel_limits_i8xx_lvds;
79e53945 561 else
e4b36699 562 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 563 }
564 return limit;
565}
566
f2b115e6
AJ		 567/* m1 is reserved as 0 in Pineview, n is a ring counter */
568static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 569{
2177832f
SL		 570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
574}
575
576static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
577{
f2b115e6
AJ		 578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
2177832f
SL		 580 return;
581 }
79e53945
JB		 582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
586}
587
79e53945
JB		 588/**
589 * Returns whether any output on the specified pipe is of the specified type
590 */
4ef69c7a 591bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 592{
4ef69c7a 593 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 594 struct intel_encoder *encoder;
595
6c2b7c12
DV		 596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
4ef69c7a
CW		 598 return true;
599
600 return false;
79e53945
JB		 601}
602
7c04d1d9 603#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 604/**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
1b894b59
CW		 609static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
79e53945 612{
79e53945 613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 614 INTELPllInvalid("p1 out of range\n");
79e53945 615 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 616 INTELPllInvalid("p out of range\n");
79e53945 617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 618 INTELPllInvalid("m2 out of range\n");
79e53945 619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 620 INTELPllInvalid("m1 out of range\n");
f2b115e6 621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 622 INTELPllInvalid("m1 <= m2\n");
79e53945 623 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 624 INTELPllInvalid("m out of range\n");
79e53945 625 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 626 INTELPllInvalid("n out of range\n");
79e53945 627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 628 INTELPllInvalid("vco out of range\n");
79e53945
JB		 629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 633 INTELPllInvalid("dot out of range\n");
79e53945
JB		 634
635 return true;
636}
637
d4906093
ML		 638static bool
639intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
d4906093 642
79e53945
JB		 643{
644 struct drm_device *dev = crtc->dev;
79e53945 645 intel_clock_t clock;
79e53945
JB		 646 int err = target;
647
a210b028 648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 649 /*
a210b028
DV		 650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
79e53945 653 */
1974cad0 654 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
0206e353 665 memset(best_clock, 0, sizeof(*best_clock));
79e53945 666
42158660
ZY		 667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 678 int this_err;
679
2177832f 680 intel_clock(dev, refclk, &clock);
1b894b59
CW		 681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
79e53945 683 continue;
cec2f356
SP		 684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
79e53945
JB		 687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699}
700
d4906093
ML		 701static bool
702intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
d4906093
ML		 705{
706 struct drm_device *dev = crtc->dev;
d4906093
ML		 707 intel_clock_t clock;
708 int max_n;
709 bool found;
6ba770dc
AJ		 710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 712 found = false;
713
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 715 int lvds_reg;
716
c619eed4 717 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
1974cad0 721 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
f77f13e2 734 /* based on hardware requirement, prefer smaller n to precision */
d4906093 735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 736 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err;
744
2177832f 745 intel_clock(dev, refclk, &clock);
1b894b59
CW		 746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
d4906093 748 continue;
cec2f356
SP		 749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
1b894b59
CW		 752
753 this_err = abs(clock.dot - target);
d4906093
ML		 754 if (this_err < err_most) {
755 *best_clock = clock;
756 err_most = this_err;
757 max_n = clock.n;
758 found = true;
759 }
760 }
761 }
762 }
763 }
2c07245f
ZW		 764 return found;
765}
766
5eb08b69 767static bool
f2b115e6 768intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
5eb08b69
ZW		 771{
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
4547668a 774
5eb08b69
ZW		 775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791}
792
a4fc5ed6
KP		 793/* DisplayPort has only two frequencies, 162MHz and 270MHz */
794static bool
795intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
a4fc5ed6 798{
5eddb70b
CW		 799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
a4fc5ed6 819}
a0c4da24
JB		 820static bool
821intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824{
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
829 int dotclk, flag;
830
af447bd3 831 flag = 0;
a0c4da24
JB		 832 dotclk = target * 1000;
833 bestppm = 1000000;
834 ppm = absppm = 0;
835 fastclk = dotclk / (2*100);
836 updrate = 0;
837 minupdate = 19200;
838 fracbits = 1;
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
847 if (p2 > 10)
848 p2 = p2 - 1;
849 p = p1 * p2;
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
854 m = m1 * m2;
855 vco = updrate * m;
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
860 bestppm = 0;
861 flag = 1;
862 }
863 if (absppm < bestppm - 10) {
864 bestppm = absppm;
865 flag = 1;
866 }
867 if (flag) {
868 bestn = n;
869 bestm1 = m1;
870 bestm2 = m2;
871 bestp1 = p1;
872 bestp2 = p2;
873 flag = 0;
874 }
875 }
876 }
877 }
878 }
879 }
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
885
886 return true;
887}
a4fc5ed6 888
a5c961d1
PZ		 889enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
894
895 return intel_crtc->cpu_transcoder;
896}
897
a928d536
PZ		 898static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
899{
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
902
903 frame = I915_READ(frame_reg);
904
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
907}
908
9d0498a2
JB		 909/**
910 * intel_wait_for_vblank - wait for vblank on a given pipe
911 * @dev: drm device
912 * @pipe: pipe to wait for
913 *
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 * mode setting code.
916 */
917void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 918{
9d0498a2 919 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 920 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 921
a928d536
PZ		 922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
924 return;
925 }
926
300387c0
CW		 927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
929 *
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
936 * vblanks...
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
939 */
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
942
9d0498a2 943 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
946 50))
9d0498a2
JB		 947 DRM_DEBUG_KMS("vblank wait timed out\n");
948}
949
ab7ad7f6
KP		 950/*
951 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
958 *
ab7ad7f6
KP		 959 * On Gen4 and above:
960 * wait for the pipe register state bit to turn off
961 *
962 * Otherwise:
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
58e10eb9 965 *
9d0498a2 966 */
58e10eb9 967void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 968{
969 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
ab7ad7f6
KP		 972
973 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 974 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 975
976 /* Wait for the Pipe State to go off */
58e10eb9
CW		 977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
978 100))
284637d9 979 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 980 } else {
837ba00f 981 u32 last_line, line_mask;
58e10eb9 982 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
984
837ba00f
PZ		 985 if (IS_GEN2(dev))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
ab7ad7f6
KP		 990 /* Wait for the display line to settle */
991 do {
837ba00f 992 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 993 mdelay(5);
837ba00f 994 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
284637d9 997 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 998 }
79e53945
JB		 999}
1000
b0ea7d37
DL		 1001/*
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1005 *
1006 * Returns true if @port is connected, false otherwise.
1007 */
1008bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1010{
1011 u32 bit;
1012
c36346e3
DL		 1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1015 case PORT_B:
1016 bit = SDE_PORTB_HOTPLUG;
1017 break;
1018 case PORT_C:
1019 bit = SDE_PORTC_HOTPLUG;
1020 break;
1021 case PORT_D:
1022 bit = SDE_PORTD_HOTPLUG;
1023 break;
1024 default:
1025 return true;
1026 }
1027 } else {
1028 switch(port->port) {
1029 case PORT_B:
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1031 break;
1032 case PORT_C:
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1034 break;
1035 case PORT_D:
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1037 break;
1038 default:
1039 return true;
1040 }
b0ea7d37
DL		 1041 }
1042
1043 return I915_READ(SDEISR) & bit;
1044}
1045
b24e7179
JB		 1046static const char *state_string(bool enabled)
1047{
1048 return enabled ? "on" : "off";
1049}
1050
1051/* Only for pre-ILK configs */
1052static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1054{
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DPLL(pipe);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1065}
1066#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
040484af
JB		 1069/* For ILK+ */
1070static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1073 bool state)
040484af 1074{
040484af
JB		 1075 u32 val;
1076 bool cur_state;
1077
9d82aa17
ED		 1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080 return;
1081 }
1082
92b27b08
CW		 1083 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1085 return;
ee7b9f93 1086
92b27b08
CW		 1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
d3ccbe86 1110 }
040484af 1111}
92b27b08
CW		 1112#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1114
1115static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117{
1118 int reg;
1119 u32 val;
1120 bool cur_state;
ad80a810
PZ		 1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
040484af 1123
affa9354
PZ		 1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
ad80a810 1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1127 val = I915_READ(reg);
ad80a810 1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
040484af
JB		 1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137}
1138#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143{
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
d63fa0dc
PZ		 1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154}
1155#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160{
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1166 return;
1167
bf507ef7 1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1169 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1170 return;
1171
040484af
JB		 1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175}
1176
1177static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179{
1180 int reg;
1181 u32 val;
1182
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186}
1187
ea0760cf
JB		 1188static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
0de3b485 1194 bool locked = true;
ea0760cf
JB		 1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1214 pipe_name(pipe));
ea0760cf
JB		 1215}
1216
b840d907
JB		 1217void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
b24e7179
JB		 1219{
1220 int reg;
1221 u32 val;
63d7bbe9 1222 bool cur_state;
702e7a56
PZ		 1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
b24e7179 1225
8e636784
DV		 1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true;
1229
69310161
PZ		 1230 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
63d7bbe9
JB		 1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1241 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1242}
1243
931872fc
CW		 1244static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
b24e7179
JB		 1246{
1247 int reg;
1248 u32 val;
931872fc 1249 bool cur_state;
b24e7179
JB		 1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
931872fc
CW		 1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1257}
1258
931872fc
CW		 1259#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
b24e7179
JB		 1262static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
1265 int reg, i;
1266 u32 val;
1267 int cur_pipe;
1268
19ec1358 1269 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1275 plane_name(pipe));
19ec1358 1276 return;
28c05794 1277 }
19ec1358 1278
b24e7179
JB		 1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1281 reg = DSPCNTR(i);
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1288 }
1289}
1290
92f2584a
JB		 1291static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1292{
1293 u32 val;
1294 bool enabled;
1295
9d82aa17
ED		 1296 if (HAS_PCH_LPT(dev_priv->dev)) {
1297 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1298 return;
1299 }
1300
92f2584a
JB		 1301 val = I915_READ(PCH_DREF_CONTROL);
1302 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1303 DREF_SUPERSPREAD_SOURCE_MASK));
1304 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1305}
1306
1307static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe)
1309{
1310 int reg;
1311 u32 val;
1312 bool enabled;
1313
1314 reg = TRANSCONF(pipe);
1315 val = I915_READ(reg);
1316 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1317 WARN(enabled,
1318 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1319 pipe_name(pipe));
92f2584a
JB		 1320}
1321
4e634389
KP		 1322static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1324{
1325 if ((val & DP_PORT_EN) == 0)
1326 return false;
1327
1328 if (HAS_PCH_CPT(dev_priv->dev)) {
1329 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1330 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1331 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1332 return false;
1333 } else {
1334 if ((val & DP_PIPE_MASK) != (pipe << 30))
1335 return false;
1336 }
1337 return true;
1338}
1339
1519b995
KP		 1340static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
dc0fa718 1343 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1347 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1348 return false;
1349 } else {
dc0fa718 1350 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & LVDS_PORT_EN) == 0)
1360 return false;
1361
1362 if (HAS_PCH_CPT(dev_priv->dev)) {
1363 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1364 return false;
1365 } else {
1366 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1367 return false;
1368 }
1369 return true;
1370}
1371
1372static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 val)
1374{
1375 if ((val & ADPA_DAC_ENABLE) == 0)
1376 return false;
1377 if (HAS_PCH_CPT(dev_priv->dev)) {
1378 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1379 return false;
1380 } else {
1381 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1382 return false;
1383 }
1384 return true;
1385}
1386
291906f1 1387static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1388 enum pipe pipe, int reg, u32 port_sel)
291906f1 1389{
47a05eca 1390 u32 val = I915_READ(reg);
4e634389 1391 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1392 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1393 reg, pipe_name(pipe));
de9a35ab 1394
75c5da27
DV		 1395 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1396 && (val & DP_PIPEB_SELECT),
de9a35ab 1397 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1398}
1399
1400static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe, int reg)
1402{
47a05eca 1403 u32 val = I915_READ(reg);
b70ad586 1404 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1405 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1406 reg, pipe_name(pipe));
de9a35ab 1407
dc0fa718 1408 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1409 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1410 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1411}
1412
1413static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe)
1415{
1416 int reg;
1417 u32 val;
291906f1 1418
f0575e92
KP		 1419 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1420 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1421 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1422
1423 reg = PCH_ADPA;
1424 val = I915_READ(reg);
b70ad586 1425 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1426 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1427 pipe_name(pipe));
291906f1
JB		 1428
1429 reg = PCH_LVDS;
1430 val = I915_READ(reg);
b70ad586 1431 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1432 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1433 pipe_name(pipe));
291906f1 1434
e2debe91
PZ		 1435 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1436 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1437 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1438}
1439
63d7bbe9
JB		 1440/**
1441 * intel_enable_pll - enable a PLL
1442 * @dev_priv: i915 private structure
1443 * @pipe: pipe PLL to enable
1444 *
1445 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1446 * make sure the PLL reg is writable first though, since the panel write
1447 * protect mechanism may be enabled.
1448 *
1449 * Note! This is for pre-ILK only.
7434a255
TR		 1450 *
1451 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1452 */
1453static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1454{
1455 int reg;
1456 u32 val;
1457
1458 /* No really, not for ILK+ */
a0c4da24 1459 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1460
1461 /* PLL is protected by panel, make sure we can write it */
1462 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1463 assert_panel_unlocked(dev_priv, pipe);
1464
1465 reg = DPLL(pipe);
1466 val = I915_READ(reg);
1467 val |= DPLL_VCO_ENABLE;
1468
1469 /* We do this three times for luck */
1470 I915_WRITE(reg, val);
1471 POSTING_READ(reg);
1472 udelay(150); /* wait for warmup */
1473 I915_WRITE(reg, val);
1474 POSTING_READ(reg);
1475 udelay(150); /* wait for warmup */
1476 I915_WRITE(reg, val);
1477 POSTING_READ(reg);
1478 udelay(150); /* wait for warmup */
1479}
1480
1481/**
1482 * intel_disable_pll - disable a PLL
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe PLL to disable
1485 *
1486 * Disable the PLL for @pipe, making sure the pipe is off first.
1487 *
1488 * Note! This is for pre-ILK only.
1489 */
1490static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1491{
1492 int reg;
1493 u32 val;
1494
1495 /* Don't disable pipe A or pipe A PLLs if needed */
1496 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1497 return;
1498
1499 /* Make sure the pipe isn't still relying on us */
1500 assert_pipe_disabled(dev_priv, pipe);
1501
1502 reg = DPLL(pipe);
1503 val = I915_READ(reg);
1504 val &= ~DPLL_VCO_ENABLE;
1505 I915_WRITE(reg, val);
1506 POSTING_READ(reg);
1507}
1508
a416edef
ED		 1509/* SBI access */
1510static void
988d6ee8
PZ		 1511intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1512 enum intel_sbi_destination destination)
a416edef 1513{
988d6ee8 1514 u32 tmp;
a416edef 1515
09153000 1516 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1517
39fb50f6 1518 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1519 100)) {
1520 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1521 return;
a416edef
ED		 1522 }
1523
988d6ee8
PZ		 1524 I915_WRITE(SBI_ADDR, (reg << 16));
1525 I915_WRITE(SBI_DATA, value);
1526
1527 if (destination == SBI_ICLK)
1528 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1529 else
1530 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1531 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1532
39fb50f6 1533 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1534 100)) {
1535 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1536 return;
a416edef 1537 }
a416edef
ED		 1538}
1539
1540static u32
988d6ee8
PZ		 1541intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1542 enum intel_sbi_destination destination)
a416edef 1543{
39fb50f6 1544 u32 value = 0;
09153000 1545 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1546
39fb50f6 1547 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1548 100)) {
1549 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1550 return 0;
a416edef
ED		 1551 }
1552
988d6ee8
PZ		 1553 I915_WRITE(SBI_ADDR, (reg << 16));
1554
1555 if (destination == SBI_ICLK)
1556 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1557 else
1558 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1559 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1560
39fb50f6 1561 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1562 100)) {
1563 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1564 return 0;
a416edef
ED		 1565 }
1566
09153000 1567 return I915_READ(SBI_DATA);
a416edef
ED		 1568}
1569
92f2584a 1570/**
b6b4e185 1571 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1572 * @dev_priv: i915 private structure
1573 * @pipe: pipe PLL to enable
1574 *
1575 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576 * drives the transcoder clock.
1577 */
b6b4e185 1578static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1579{
ee7b9f93 1580 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1581 struct intel_pch_pll *pll;
92f2584a
JB		 1582 int reg;
1583 u32 val;
1584
48da64a8 1585 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1586 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1587 pll = intel_crtc->pch_pll;
1588 if (pll == NULL)
1589 return;
1590
1591 if (WARN_ON(pll->refcount == 0))
1592 return;
ee7b9f93
JB		 1593
1594 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595 pll->pll_reg, pll->active, pll->on,
1596 intel_crtc->base.base.id);
92f2584a
JB		 1597
1598 /* PCH refclock must be enabled first */
1599 assert_pch_refclk_enabled(dev_priv);
1600
ee7b9f93 1601 if (pll->active++ && pll->on) {
92b27b08 1602 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1603 return;
1604 }
1605
1606 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1607
1608 reg = pll->pll_reg;
92f2584a
JB		 1609 val = I915_READ(reg);
1610 val |= DPLL_VCO_ENABLE;
1611 I915_WRITE(reg, val);
1612 POSTING_READ(reg);
1613 udelay(200);
ee7b9f93
JB		 1614
1615 pll->on = true;
92f2584a
JB		 1616}
1617
ee7b9f93 1618static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1619{
ee7b9f93
JB		 1620 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1621 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1622 int reg;
ee7b9f93 1623 u32 val;
4c609cb8 1624
92f2584a
JB		 1625 /* PCH only available on ILK+ */
1626 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1627 if (pll == NULL)
1628 return;
92f2584a 1629
48da64a8
CW		 1630 if (WARN_ON(pll->refcount == 0))
1631 return;
7a419866 1632
ee7b9f93
JB		 1633 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634 pll->pll_reg, pll->active, pll->on,
1635 intel_crtc->base.base.id);
7a419866 1636
48da64a8 1637 if (WARN_ON(pll->active == 0)) {
92b27b08 1638 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1639 return;
1640 }
1641
ee7b9f93 1642 if (--pll->active) {
92b27b08 1643 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1644 return;
ee7b9f93
JB		 1645 }
1646
1647 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1648
1649 /* Make sure transcoder isn't still depending on us */
1650 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1651
ee7b9f93 1652 reg = pll->pll_reg;
92f2584a
JB		 1653 val = I915_READ(reg);
1654 val &= ~DPLL_VCO_ENABLE;
1655 I915_WRITE(reg, val);
1656 POSTING_READ(reg);
1657 udelay(200);
ee7b9f93
JB		 1658
1659 pll->on = false;
92f2584a
JB		 1660}
1661
b8a4f404
PZ		 1662static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1663 enum pipe pipe)
040484af 1664{
23670b32 1665 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1666 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1667 uint32_t reg, val, pipeconf_val;
040484af
JB		 1668
1669 /* PCH only available on ILK+ */
1670 BUG_ON(dev_priv->info->gen < 5);
1671
1672 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1673 assert_pch_pll_enabled(dev_priv,
1674 to_intel_crtc(crtc)->pch_pll,
1675 to_intel_crtc(crtc));
040484af
JB		 1676
1677 /* FDI must be feeding us bits for PCH ports */
1678 assert_fdi_tx_enabled(dev_priv, pipe);
1679 assert_fdi_rx_enabled(dev_priv, pipe);
1680
23670b32
DV		 1681 if (HAS_PCH_CPT(dev)) {
1682 /* Workaround: Set the timing override bit before enabling the
1683 * pch transcoder. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
59c859d6 1688 }
23670b32 1689
040484af
JB		 1690 reg = TRANSCONF(pipe);
1691 val = I915_READ(reg);
5f7f726d 1692 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1693
1694 if (HAS_PCH_IBX(dev_priv->dev)) {
1695 /*
1696 * make the BPC in transcoder be consistent with
1697 * that in pipeconf reg.
1698 */
dfd07d72
DV		 1699 val &= ~PIPECONF_BPC_MASK;
1700 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1701 }
5f7f726d
PZ		 1702
1703 val &= ~TRANS_INTERLACE_MASK;
1704 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1705 if (HAS_PCH_IBX(dev_priv->dev) &&
1706 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1707 val |= TRANS_LEGACY_INTERLACED_ILK;
1708 else
1709 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1710 else
1711 val |= TRANS_PROGRESSIVE;
1712
040484af
JB		 1713 I915_WRITE(reg, val | TRANS_ENABLE);
1714 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1715 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1716}
1717
8fb033d7 1718static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1719 enum transcoder cpu_transcoder)
040484af 1720{
8fb033d7 1721 u32 val, pipeconf_val;
8fb033d7
PZ		 1722
1723 /* PCH only available on ILK+ */
1724 BUG_ON(dev_priv->info->gen < 5);
1725
8fb033d7 1726 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1727 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1728 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1729
223a6fdf
PZ		 1730 /* Workaround: set timing override bit. */
1731 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1732 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1733 I915_WRITE(_TRANSA_CHICKEN2, val);
1734
25f3ef11 1735 val = TRANS_ENABLE;
937bb610 1736 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1737
9a76b1c6
PZ		 1738 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1739 PIPECONF_INTERLACED_ILK)
a35f2679 1740 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1741 else
1742 val |= TRANS_PROGRESSIVE;
1743
25f3ef11 1744 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1745 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1746 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1747}
1748
b8a4f404
PZ		 1749static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1750 enum pipe pipe)
040484af 1751{
23670b32
DV		 1752 struct drm_device *dev = dev_priv->dev;
1753 uint32_t reg, val;
040484af
JB		 1754
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe);
1757 assert_fdi_rx_disabled(dev_priv, pipe);
1758
291906f1
JB		 1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1761
040484af
JB		 1762 reg = TRANSCONF(pipe);
1763 val = I915_READ(reg);
1764 val &= ~TRANS_ENABLE;
1765 I915_WRITE(reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1768 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1769
1770 if (!HAS_PCH_IBX(dev)) {
1771 /* Workaround: Clear the timing override chicken bit again. */
1772 reg = TRANS_CHICKEN2(pipe);
1773 val = I915_READ(reg);
1774 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1775 I915_WRITE(reg, val);
1776 }
040484af
JB		 1777}
1778
ab4d966c 1779static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1780{
8fb033d7
PZ		 1781 u32 val;
1782
8a52fd9f 1783 val = I915_READ(_TRANSACONF);
8fb033d7 1784 val &= ~TRANS_ENABLE;
8a52fd9f 1785 I915_WRITE(_TRANSACONF, val);
8fb033d7 1786 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1787 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1788 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1789
1790 /* Workaround: clear timing override bit. */
1791 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1792 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1793 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1794}
1795
b24e7179 1796/**
309cfea8 1797 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe to enable
040484af 1800 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1801 *
1802 * Enable @pipe, making sure that various hardware specific requirements
1803 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1804 *
1805 * @pipe should be %PIPE_A or %PIPE_B.
1806 *
1807 * Will wait until the pipe is actually running (i.e. first vblank) before
1808 * returning.
1809 */
040484af
JB		 1810static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1811 bool pch_port)
b24e7179 1812{
702e7a56
PZ		 1813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1814 pipe);
1a240d4d 1815 enum pipe pch_transcoder;
b24e7179
JB		 1816 int reg;
1817 u32 val;
1818
681e5811 1819 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1820 pch_transcoder = TRANSCODER_A;
1821 else
1822 pch_transcoder = pipe;
1823
b24e7179
JB		 1824 /*
1825 * A pipe without a PLL won't actually be able to drive bits from
1826 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1827 * need the check.
1828 */
1829 if (!HAS_PCH_SPLIT(dev_priv->dev))
1830 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1831 else {
1832 if (pch_port) {
1833 /* if driving the PCH, we need FDI enabled */
cc391bbb 1834 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1835 assert_fdi_tx_pll_enabled(dev_priv,
1836 (enum pipe) cpu_transcoder);
040484af
JB		 1837 }
1838 /* FIXME: assert CPU port conditions for SNB+ */
1839 }
b24e7179 1840
702e7a56 1841 reg = PIPECONF(cpu_transcoder);
b24e7179 1842 val = I915_READ(reg);
00d70b15
CW		 1843 if (val & PIPECONF_ENABLE)
1844 return;
1845
1846 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1847 intel_wait_for_vblank(dev_priv->dev, pipe);
1848}
1849
1850/**
309cfea8 1851 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1852 * @dev_priv: i915 private structure
1853 * @pipe: pipe to disable
1854 *
1855 * Disable @pipe, making sure that various hardware specific requirements
1856 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1857 *
1858 * @pipe should be %PIPE_A or %PIPE_B.
1859 *
1860 * Will wait until the pipe has shut down before returning.
1861 */
1862static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1863 enum pipe pipe)
1864{
702e7a56
PZ		 1865 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1866 pipe);
b24e7179
JB		 1867 int reg;
1868 u32 val;
1869
1870 /*
1871 * Make sure planes won't keep trying to pump pixels to us,
1872 * or we might hang the display.
1873 */
1874 assert_planes_disabled(dev_priv, pipe);
1875
1876 /* Don't disable pipe A or pipe A PLLs if needed */
1877 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1878 return;
1879
702e7a56 1880 reg = PIPECONF(cpu_transcoder);
b24e7179 1881 val = I915_READ(reg);
00d70b15
CW		 1882 if ((val & PIPECONF_ENABLE) == 0)
1883 return;
1884
1885 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1886 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1887}
1888
d74362c9
KP		 1889/*
1890 * Plane regs are double buffered, going from enabled->disabled needs a
1891 * trigger in order to latch. The display address reg provides this.
1892 */
6f1d69b0 1893void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1894 enum plane plane)
1895{
14f86147
DL		 1896 if (dev_priv->info->gen >= 4)
1897 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1898 else
1899 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1900}
1901
b24e7179
JB		 1902/**
1903 * intel_enable_plane - enable a display plane on a given pipe
1904 * @dev_priv: i915 private structure
1905 * @plane: plane to enable
1906 * @pipe: pipe being fed
1907 *
1908 * Enable @plane on @pipe, making sure that @pipe is running first.
1909 */
1910static void intel_enable_plane(struct drm_i915_private *dev_priv,
1911 enum plane plane, enum pipe pipe)
1912{
1913 int reg;
1914 u32 val;
1915
1916 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1917 assert_pipe_enabled(dev_priv, pipe);
1918
1919 reg = DSPCNTR(plane);
1920 val = I915_READ(reg);
00d70b15
CW		 1921 if (val & DISPLAY_PLANE_ENABLE)
1922 return;
1923
1924 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1925 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1926 intel_wait_for_vblank(dev_priv->dev, pipe);
1927}
1928
b24e7179
JB		 1929/**
1930 * intel_disable_plane - disable a display plane
1931 * @dev_priv: i915 private structure
1932 * @plane: plane to disable
1933 * @pipe: pipe consuming the data
1934 *
1935 * Disable @plane; should be an independent operation.
1936 */
1937static void intel_disable_plane(struct drm_i915_private *dev_priv,
1938 enum plane plane, enum pipe pipe)
1939{
1940 int reg;
1941 u32 val;
1942
1943 reg = DSPCNTR(plane);
1944 val = I915_READ(reg);
00d70b15
CW		 1945 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1946 return;
1947
1948 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1949 intel_flush_display_plane(dev_priv, plane);
1950 intel_wait_for_vblank(dev_priv->dev, pipe);
1951}
1952
693db184
CW		 1953static bool need_vtd_wa(struct drm_device *dev)
1954{
1955#ifdef CONFIG_INTEL_IOMMU
1956 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1957 return true;
1958#endif
1959 return false;
1960}
1961
127bd2ac 1962int
48b956c5 1963intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1964 struct drm_i915_gem_object *obj,
919926ae 1965 struct intel_ring_buffer *pipelined)
6b95a207 1966{
ce453d81 1967 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1968 u32 alignment;
1969 int ret;
1970
05394f39 1971 switch (obj->tiling_mode) {
6b95a207 1972 case I915_TILING_NONE:
534843da
CW		 1973 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1974 alignment = 128 * 1024;
a6c45cf0 1975 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1976 alignment = 4 * 1024;
1977 else
1978 alignment = 64 * 1024;
6b95a207
KH		 1979 break;
1980 case I915_TILING_X:
1981 /* pin() will align the object as required by fence */
1982 alignment = 0;
1983 break;
1984 case I915_TILING_Y:
1985 /* FIXME: Is this true? */
1986 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1987 return -EINVAL;
1988 default:
1989 BUG();
1990 }
1991
693db184
CW		 1992 /* Note that the w/a also requires 64 PTE of padding following the
1993 * bo. We currently fill all unused PTE with the shadow page and so
1994 * we should always have valid PTE following the scanout preventing
1995 * the VT-d warning.
1996 */
1997 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1998 alignment = 256 * 1024;
1999
ce453d81 2000 dev_priv->mm.interruptible = false;
2da3b9b9 2001 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2002 if (ret)
ce453d81 2003 goto err_interruptible;
6b95a207
KH		 2004
2005 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2006 * fence, whereas 965+ only requires a fence if using
2007 * framebuffer compression. For simplicity, we always install
2008 * a fence as the cost is not that onerous.
2009 */
06d98131 2010 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2011 if (ret)
2012 goto err_unpin;
1690e1eb 2013
9a5a53b3 2014 i915_gem_object_pin_fence(obj);
6b95a207 2015
ce453d81 2016 dev_priv->mm.interruptible = true;
6b95a207 2017 return 0;
48b956c5
CW		 2018
2019err_unpin:
2020 i915_gem_object_unpin(obj);
ce453d81
CW		 2021err_interruptible:
2022 dev_priv->mm.interruptible = true;
48b956c5 2023 return ret;
6b95a207
KH		 2024}
2025
1690e1eb
CW		 2026void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2027{
2028 i915_gem_object_unpin_fence(obj);
2029 i915_gem_object_unpin(obj);
2030}
2031
c2c75131
DV		 2032/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2033 * is assumed to be a power-of-two. */
bc752862
CW		 2034unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2035 unsigned int tiling_mode,
2036 unsigned int cpp,
2037 unsigned int pitch)
c2c75131 2038{
bc752862
CW		 2039 if (tiling_mode != I915_TILING_NONE) {
2040 unsigned int tile_rows, tiles;
c2c75131 2041
bc752862
CW		 2042 tile_rows = *y / 8;
2043 *y %= 8;
c2c75131 2044
bc752862
CW		 2045 tiles = *x / (512/cpp);
2046 *x %= 512/cpp;
2047
2048 return tile_rows * pitch * 8 + tiles * 4096;
2049 } else {
2050 unsigned int offset;
2051
2052 offset = *y * pitch + *x * cpp;
2053 *y = 0;
2054 *x = (offset & 4095) / cpp;
2055 return offset & -4096;
2056 }
c2c75131
DV		 2057}
2058
17638cd6
JB		 2059static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2060 int x, int y)
81255565
JB		 2061{
2062 struct drm_device *dev = crtc->dev;
2063 struct drm_i915_private *dev_priv = dev->dev_private;
2064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2065 struct intel_framebuffer *intel_fb;
05394f39 2066 struct drm_i915_gem_object *obj;
81255565 2067 int plane = intel_crtc->plane;
e506a0c6 2068 unsigned long linear_offset;
81255565 2069 u32 dspcntr;
5eddb70b 2070 u32 reg;
81255565
JB		 2071
2072 switch (plane) {
2073 case 0:
2074 case 1:
2075 break;
2076 default:
2077 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2078 return -EINVAL;
2079 }
2080
2081 intel_fb = to_intel_framebuffer(fb);
2082 obj = intel_fb->obj;
81255565 2083
5eddb70b
CW		 2084 reg = DSPCNTR(plane);
2085 dspcntr = I915_READ(reg);
81255565
JB		 2086 /* Mask out pixel format bits in case we change it */
2087 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2088 switch (fb->pixel_format) {
2089 case DRM_FORMAT_C8:
81255565
JB		 2090 dspcntr |= DISPPLANE_8BPP;
2091 break;
57779d06
VS		 2092 case DRM_FORMAT_XRGB1555:
2093 case DRM_FORMAT_ARGB1555:
2094 dspcntr |= DISPPLANE_BGRX555;
81255565 2095 break;
57779d06
VS		 2096 case DRM_FORMAT_RGB565:
2097 dspcntr |= DISPPLANE_BGRX565;
2098 break;
2099 case DRM_FORMAT_XRGB8888:
2100 case DRM_FORMAT_ARGB8888:
2101 dspcntr |= DISPPLANE_BGRX888;
2102 break;
2103 case DRM_FORMAT_XBGR8888:
2104 case DRM_FORMAT_ABGR8888:
2105 dspcntr |= DISPPLANE_RGBX888;
2106 break;
2107 case DRM_FORMAT_XRGB2101010:
2108 case DRM_FORMAT_ARGB2101010:
2109 dspcntr |= DISPPLANE_BGRX101010;
2110 break;
2111 case DRM_FORMAT_XBGR2101010:
2112 case DRM_FORMAT_ABGR2101010:
2113 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2114 break;
2115 default:
57779d06 2116 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2117 return -EINVAL;
2118 }
57779d06 2119
a6c45cf0 2120 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2121 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2122 dspcntr |= DISPPLANE_TILED;
2123 else
2124 dspcntr &= ~DISPPLANE_TILED;
2125 }
2126
5eddb70b 2127 I915_WRITE(reg, dspcntr);
81255565 2128
e506a0c6 2129 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2130
c2c75131
DV		 2131 if (INTEL_INFO(dev)->gen >= 4) {
2132 intel_crtc->dspaddr_offset =
bc752862
CW		 2133 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2134 fb->bits_per_pixel / 8,
2135 fb->pitches[0]);
c2c75131
DV		 2136 linear_offset -= intel_crtc->dspaddr_offset;
2137 } else {
e506a0c6 2138 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2139 }
e506a0c6
DV		 2140
2141 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2142 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2143 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2144 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2145 I915_MODIFY_DISPBASE(DSPSURF(plane),
2146 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2147 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2148 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2149 } else
e506a0c6 2150 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2151 POSTING_READ(reg);
81255565 2152
17638cd6
JB		 2153 return 0;
2154}
2155
2156static int ironlake_update_plane(struct drm_crtc *crtc,
2157 struct drm_framebuffer *fb, int x, int y)
2158{
2159 struct drm_device *dev = crtc->dev;
2160 struct drm_i915_private *dev_priv = dev->dev_private;
2161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2162 struct intel_framebuffer *intel_fb;
2163 struct drm_i915_gem_object *obj;
2164 int plane = intel_crtc->plane;
e506a0c6 2165 unsigned long linear_offset;
17638cd6
JB		 2166 u32 dspcntr;
2167 u32 reg;
2168
2169 switch (plane) {
2170 case 0:
2171 case 1:
27f8227b 2172 case 2:
17638cd6
JB		 2173 break;
2174 default:
2175 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2176 return -EINVAL;
2177 }
2178
2179 intel_fb = to_intel_framebuffer(fb);
2180 obj = intel_fb->obj;
2181
2182 reg = DSPCNTR(plane);
2183 dspcntr = I915_READ(reg);
2184 /* Mask out pixel format bits in case we change it */
2185 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2186 switch (fb->pixel_format) {
2187 case DRM_FORMAT_C8:
17638cd6
JB		 2188 dspcntr |= DISPPLANE_8BPP;
2189 break;
57779d06
VS		 2190 case DRM_FORMAT_RGB565:
2191 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2192 break;
57779d06
VS		 2193 case DRM_FORMAT_XRGB8888:
2194 case DRM_FORMAT_ARGB8888:
2195 dspcntr |= DISPPLANE_BGRX888;
2196 break;
2197 case DRM_FORMAT_XBGR8888:
2198 case DRM_FORMAT_ABGR8888:
2199 dspcntr |= DISPPLANE_RGBX888;
2200 break;
2201 case DRM_FORMAT_XRGB2101010:
2202 case DRM_FORMAT_ARGB2101010:
2203 dspcntr |= DISPPLANE_BGRX101010;
2204 break;
2205 case DRM_FORMAT_XBGR2101010:
2206 case DRM_FORMAT_ABGR2101010:
2207 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2208 break;
2209 default:
57779d06 2210 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2211 return -EINVAL;
2212 }
2213
2214 if (obj->tiling_mode != I915_TILING_NONE)
2215 dspcntr |= DISPPLANE_TILED;
2216 else
2217 dspcntr &= ~DISPPLANE_TILED;
2218
2219 /* must disable */
2220 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2221
2222 I915_WRITE(reg, dspcntr);
2223
e506a0c6 2224 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2225 intel_crtc->dspaddr_offset =
bc752862
CW		 2226 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2227 fb->bits_per_pixel / 8,
2228 fb->pitches[0]);
c2c75131 2229 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2230
e506a0c6
DV		 2231 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2232 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2233 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2234 I915_MODIFY_DISPBASE(DSPSURF(plane),
2235 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2236 if (IS_HASWELL(dev)) {
2237 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2238 } else {
2239 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2240 I915_WRITE(DSPLINOFF(plane), linear_offset);
2241 }
17638cd6
JB		 2242 POSTING_READ(reg);
2243
2244 return 0;
2245}
2246
2247/* Assume fb object is pinned & idle & fenced and just update base pointers */
2248static int
2249intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2250 int x, int y, enum mode_set_atomic state)
2251{
2252 struct drm_device *dev = crtc->dev;
2253 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2254
6b8e6ed0
CW		 2255 if (dev_priv->display.disable_fbc)
2256 dev_priv->display.disable_fbc(dev);
3dec0095 2257 intel_increase_pllclock(crtc);
81255565 2258
6b8e6ed0 2259 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2260}
2261
96a02917
VS		 2262void intel_display_handle_reset(struct drm_device *dev)
2263{
2264 struct drm_i915_private *dev_priv = dev->dev_private;
2265 struct drm_crtc *crtc;
2266
2267 /*
2268 * Flips in the rings have been nuked by the reset,
2269 * so complete all pending flips so that user space
2270 * will get its events and not get stuck.
2271 *
2272 * Also update the base address of all primary
2273 * planes to the the last fb to make sure we're
2274 * showing the correct fb after a reset.
2275 *
2276 * Need to make two loops over the crtcs so that we
2277 * don't try to grab a crtc mutex before the
2278 * pending_flip_queue really got woken up.
2279 */
2280
2281 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2283 enum plane plane = intel_crtc->plane;
2284
2285 intel_prepare_page_flip(dev, plane);
2286 intel_finish_page_flip_plane(dev, plane);
2287 }
2288
2289 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2291
2292 mutex_lock(&crtc->mutex);
2293 if (intel_crtc->active)
2294 dev_priv->display.update_plane(crtc, crtc->fb,
2295 crtc->x, crtc->y);
2296 mutex_unlock(&crtc->mutex);
2297 }
2298}
2299
14667a4b
CW		 2300static int
2301intel_finish_fb(struct drm_framebuffer *old_fb)
2302{
2303 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2304 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2305 bool was_interruptible = dev_priv->mm.interruptible;
2306 int ret;
2307
14667a4b
CW		 2308 /* Big Hammer, we also need to ensure that any pending
2309 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2310 * current scanout is retired before unpinning the old
2311 * framebuffer.
2312 *
2313 * This should only fail upon a hung GPU, in which case we
2314 * can safely continue.
2315 */
2316 dev_priv->mm.interruptible = false;
2317 ret = i915_gem_object_finish_gpu(obj);
2318 dev_priv->mm.interruptible = was_interruptible;
2319
2320 return ret;
2321}
2322
198598d0
VS		 2323static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2324{
2325 struct drm_device *dev = crtc->dev;
2326 struct drm_i915_master_private *master_priv;
2327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2328
2329 if (!dev->primary->master)
2330 return;
2331
2332 master_priv = dev->primary->master->driver_priv;
2333 if (!master_priv->sarea_priv)
2334 return;
2335
2336 switch (intel_crtc->pipe) {
2337 case 0:
2338 master_priv->sarea_priv->pipeA_x = x;
2339 master_priv->sarea_priv->pipeA_y = y;
2340 break;
2341 case 1:
2342 master_priv->sarea_priv->pipeB_x = x;
2343 master_priv->sarea_priv->pipeB_y = y;
2344 break;
2345 default:
2346 break;
2347 }
2348}
2349
5c3b82e2 2350static int
3c4fdcfb 2351intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2352 struct drm_framebuffer *fb)
79e53945
JB		 2353{
2354 struct drm_device *dev = crtc->dev;
6b8e6ed0 2355 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2357 struct drm_framebuffer *old_fb;
5c3b82e2 2358 int ret;
79e53945
JB		 2359
2360 /* no fb bound */
94352cf9 2361 if (!fb) {
a5071c2f 2362 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2363 return 0;
2364 }
2365
7eb552ae 2366 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
5826eca5
ED		 2367 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2368 intel_crtc->plane,
7eb552ae 2369 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2370 return -EINVAL;
79e53945
JB		 2371 }
2372
5c3b82e2 2373 mutex_lock(&dev->struct_mutex);
265db958 2374 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2375 to_intel_framebuffer(fb)->obj,
919926ae 2376 NULL);
5c3b82e2
CW		 2377 if (ret != 0) {
2378 mutex_unlock(&dev->struct_mutex);
a5071c2f 2379 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2380 return ret;
2381 }
79e53945 2382
94352cf9 2383 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2384 if (ret) {
94352cf9 2385 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2386 mutex_unlock(&dev->struct_mutex);
a5071c2f 2387 DRM_ERROR("failed to update base address\n");
4e6cfefc 2388 return ret;
79e53945 2389 }
3c4fdcfb 2390
94352cf9
DV		 2391 old_fb = crtc->fb;
2392 crtc->fb = fb;
6c4c86f5
DV		 2393 crtc->x = x;
2394 crtc->y = y;
94352cf9 2395
b7f1de28
CW		 2396 if (old_fb) {
2397 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2398 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2399 }
652c393a 2400
6b8e6ed0 2401 intel_update_fbc(dev);
5c3b82e2 2402 mutex_unlock(&dev->struct_mutex);
79e53945 2403
198598d0 2404 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2405
2406 return 0;
79e53945
JB		 2407}
2408
5e84e1a4
ZW		 2409static void intel_fdi_normal_train(struct drm_crtc *crtc)
2410{
2411 struct drm_device *dev = crtc->dev;
2412 struct drm_i915_private *dev_priv = dev->dev_private;
2413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2414 int pipe = intel_crtc->pipe;
2415 u32 reg, temp;
2416
2417 /* enable normal train */
2418 reg = FDI_TX_CTL(pipe);
2419 temp = I915_READ(reg);
61e499bf 2420 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2421 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2422 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2423 } else {
2424 temp &= ~FDI_LINK_TRAIN_NONE;
2425 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2426 }
5e84e1a4
ZW		 2427 I915_WRITE(reg, temp);
2428
2429 reg = FDI_RX_CTL(pipe);
2430 temp = I915_READ(reg);
2431 if (HAS_PCH_CPT(dev)) {
2432 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2433 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2434 } else {
2435 temp &= ~FDI_LINK_TRAIN_NONE;
2436 temp |= FDI_LINK_TRAIN_NONE;
2437 }
2438 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2439
2440 /* wait one idle pattern time */
2441 POSTING_READ(reg);
2442 udelay(1000);
357555c0
JB		 2443
2444 /* IVB wants error correction enabled */
2445 if (IS_IVYBRIDGE(dev))
2446 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2447 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2448}
2449
01a415fd
DV		 2450static void ivb_modeset_global_resources(struct drm_device *dev)
2451{
2452 struct drm_i915_private *dev_priv = dev->dev_private;
2453 struct intel_crtc *pipe_B_crtc =
2454 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2455 struct intel_crtc *pipe_C_crtc =
2456 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2457 uint32_t temp;
2458
2459 /* When everything is off disable fdi C so that we could enable fdi B
2460 * with all lanes. XXX: This misses the case where a pipe is not using
2461 * any pch resources and so doesn't need any fdi lanes. */
2462 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2463 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2464 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2465
2466 temp = I915_READ(SOUTH_CHICKEN1);
2467 temp &= ~FDI_BC_BIFURCATION_SELECT;
2468 DRM_DEBUG_KMS("disabling fdi C rx\n");
2469 I915_WRITE(SOUTH_CHICKEN1, temp);
2470 }
2471}
2472
8db9d77b
ZW		 2473/* The FDI link training functions for ILK/Ibexpeak. */
2474static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2475{
2476 struct drm_device *dev = crtc->dev;
2477 struct drm_i915_private *dev_priv = dev->dev_private;
2478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2479 int pipe = intel_crtc->pipe;
0fc932b8 2480 int plane = intel_crtc->plane;
5eddb70b 2481 u32 reg, temp, tries;
8db9d77b 2482
0fc932b8
JB		 2483 /* FDI needs bits from pipe & plane first */
2484 assert_pipe_enabled(dev_priv, pipe);
2485 assert_plane_enabled(dev_priv, plane);
2486
e1a44743
AJ		 2487 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2488 for train result */
5eddb70b
CW		 2489 reg = FDI_RX_IMR(pipe);
2490 temp = I915_READ(reg);
e1a44743
AJ		 2491 temp &= ~FDI_RX_SYMBOL_LOCK;
2492 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2493 I915_WRITE(reg, temp);
2494 I915_READ(reg);
e1a44743
AJ		 2495 udelay(150);
2496
8db9d77b 2497 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2498 reg = FDI_TX_CTL(pipe);
2499 temp = I915_READ(reg);
77ffb597
AJ		 2500 temp &= ~(7 << 19);
2501 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2502 temp &= ~FDI_LINK_TRAIN_NONE;
2503 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2504 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2505
5eddb70b
CW		 2506 reg = FDI_RX_CTL(pipe);
2507 temp = I915_READ(reg);
8db9d77b
ZW		 2508 temp &= ~FDI_LINK_TRAIN_NONE;
2509 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2510 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2511
2512 POSTING_READ(reg);
8db9d77b
ZW		 2513 udelay(150);
2514
5b2adf89 2515 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2516 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2517 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2518 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2519
5eddb70b 2520 reg = FDI_RX_IIR(pipe);
e1a44743 2521 for (tries = 0; tries < 5; tries++) {
5eddb70b 2522 temp = I915_READ(reg);
8db9d77b
ZW		 2523 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2524
2525 if ((temp & FDI_RX_BIT_LOCK)) {
2526 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2527 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2528 break;
2529 }
8db9d77b 2530 }
e1a44743 2531 if (tries == 5)
5eddb70b 2532 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2533
2534 /* Train 2 */
5eddb70b
CW		 2535 reg = FDI_TX_CTL(pipe);
2536 temp = I915_READ(reg);
8db9d77b
ZW		 2537 temp &= ~FDI_LINK_TRAIN_NONE;
2538 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2539 I915_WRITE(reg, temp);
8db9d77b 2540
5eddb70b
CW		 2541 reg = FDI_RX_CTL(pipe);
2542 temp = I915_READ(reg);
8db9d77b
ZW		 2543 temp &= ~FDI_LINK_TRAIN_NONE;
2544 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2545 I915_WRITE(reg, temp);
8db9d77b 2546
5eddb70b
CW		 2547 POSTING_READ(reg);
2548 udelay(150);
8db9d77b 2549
5eddb70b 2550 reg = FDI_RX_IIR(pipe);
e1a44743 2551 for (tries = 0; tries < 5; tries++) {
5eddb70b 2552 temp = I915_READ(reg);
8db9d77b
ZW		 2553 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2554
2555 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2556 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2557 DRM_DEBUG_KMS("FDI train 2 done.\n");
2558 break;
2559 }
8db9d77b 2560 }
e1a44743 2561 if (tries == 5)
5eddb70b 2562 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2563
2564 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2565
8db9d77b
ZW		 2566}
2567
0206e353 2568static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2569 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2570 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2571 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2572 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2573};
2574
2575/* The FDI link training functions for SNB/Cougarpoint. */
2576static void gen6_fdi_link_train(struct drm_crtc *crtc)
2577{
2578 struct drm_device *dev = crtc->dev;
2579 struct drm_i915_private *dev_priv = dev->dev_private;
2580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2581 int pipe = intel_crtc->pipe;
fa37d39e 2582 u32 reg, temp, i, retry;
8db9d77b 2583
e1a44743
AJ		 2584 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2585 for train result */
5eddb70b
CW		 2586 reg = FDI_RX_IMR(pipe);
2587 temp = I915_READ(reg);
e1a44743
AJ		 2588 temp &= ~FDI_RX_SYMBOL_LOCK;
2589 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2590 I915_WRITE(reg, temp);
2591
2592 POSTING_READ(reg);
e1a44743
AJ		 2593 udelay(150);
2594
8db9d77b 2595 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2596 reg = FDI_TX_CTL(pipe);
2597 temp = I915_READ(reg);
77ffb597
AJ		 2598 temp &= ~(7 << 19);
2599 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2600 temp &= ~FDI_LINK_TRAIN_NONE;
2601 temp |= FDI_LINK_TRAIN_PATTERN_1;
2602 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603 /* SNB-B */
2604 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2605 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2606
d74cf324
DV		 2607 I915_WRITE(FDI_RX_MISC(pipe),
2608 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2609
5eddb70b
CW		 2610 reg = FDI_RX_CTL(pipe);
2611 temp = I915_READ(reg);
8db9d77b
ZW		 2612 if (HAS_PCH_CPT(dev)) {
2613 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2614 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2615 } else {
2616 temp &= ~FDI_LINK_TRAIN_NONE;
2617 temp |= FDI_LINK_TRAIN_PATTERN_1;
2618 }
5eddb70b
CW		 2619 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2620
2621 POSTING_READ(reg);
8db9d77b
ZW		 2622 udelay(150);
2623
0206e353 2624 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2625 reg = FDI_TX_CTL(pipe);
2626 temp = I915_READ(reg);
8db9d77b
ZW		 2627 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2628 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2629 I915_WRITE(reg, temp);
2630
2631 POSTING_READ(reg);
8db9d77b
ZW		 2632 udelay(500);
2633
fa37d39e
SP		 2634 for (retry = 0; retry < 5; retry++) {
2635 reg = FDI_RX_IIR(pipe);
2636 temp = I915_READ(reg);
2637 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2638 if (temp & FDI_RX_BIT_LOCK) {
2639 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2640 DRM_DEBUG_KMS("FDI train 1 done.\n");
2641 break;
2642 }
2643 udelay(50);
8db9d77b 2644 }
fa37d39e
SP		 2645 if (retry < 5)
2646 break;
8db9d77b
ZW		 2647 }
2648 if (i == 4)
5eddb70b 2649 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2650
2651 /* Train 2 */
5eddb70b
CW		 2652 reg = FDI_TX_CTL(pipe);
2653 temp = I915_READ(reg);
8db9d77b
ZW		 2654 temp &= ~FDI_LINK_TRAIN_NONE;
2655 temp |= FDI_LINK_TRAIN_PATTERN_2;
2656 if (IS_GEN6(dev)) {
2657 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2658 /* SNB-B */
2659 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2660 }
5eddb70b 2661 I915_WRITE(reg, temp);
8db9d77b 2662
5eddb70b
CW		 2663 reg = FDI_RX_CTL(pipe);
2664 temp = I915_READ(reg);
8db9d77b
ZW		 2665 if (HAS_PCH_CPT(dev)) {
2666 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2667 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2668 } else {
2669 temp &= ~FDI_LINK_TRAIN_NONE;
2670 temp |= FDI_LINK_TRAIN_PATTERN_2;
2671 }
5eddb70b
CW		 2672 I915_WRITE(reg, temp);
2673
2674 POSTING_READ(reg);
8db9d77b
ZW		 2675 udelay(150);
2676
0206e353 2677 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2678 reg = FDI_TX_CTL(pipe);
2679 temp = I915_READ(reg);
8db9d77b
ZW		 2680 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2681 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2682 I915_WRITE(reg, temp);
2683
2684 POSTING_READ(reg);
8db9d77b
ZW		 2685 udelay(500);
2686
fa37d39e
SP		 2687 for (retry = 0; retry < 5; retry++) {
2688 reg = FDI_RX_IIR(pipe);
2689 temp = I915_READ(reg);
2690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2691 if (temp & FDI_RX_SYMBOL_LOCK) {
2692 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2693 DRM_DEBUG_KMS("FDI train 2 done.\n");
2694 break;
2695 }
2696 udelay(50);
8db9d77b 2697 }
fa37d39e
SP		 2698 if (retry < 5)
2699 break;
8db9d77b
ZW		 2700 }
2701 if (i == 4)
5eddb70b 2702 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2703
2704 DRM_DEBUG_KMS("FDI train done.\n");
2705}
2706
357555c0
JB		 2707/* Manual link training for Ivy Bridge A0 parts */
2708static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2709{
2710 struct drm_device *dev = crtc->dev;
2711 struct drm_i915_private *dev_priv = dev->dev_private;
2712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2713 int pipe = intel_crtc->pipe;
2714 u32 reg, temp, i;
2715
2716 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2717 for train result */
2718 reg = FDI_RX_IMR(pipe);
2719 temp = I915_READ(reg);
2720 temp &= ~FDI_RX_SYMBOL_LOCK;
2721 temp &= ~FDI_RX_BIT_LOCK;
2722 I915_WRITE(reg, temp);
2723
2724 POSTING_READ(reg);
2725 udelay(150);
2726
01a415fd
DV		 2727 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2728 I915_READ(FDI_RX_IIR(pipe)));
2729
357555c0
JB		 2730 /* enable CPU FDI TX and PCH FDI RX */
2731 reg = FDI_TX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 temp &= ~(7 << 19);
2734 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2735 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2736 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2737 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2738 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2739 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2740 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2741
d74cf324
DV		 2742 I915_WRITE(FDI_RX_MISC(pipe),
2743 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2744
357555c0
JB		 2745 reg = FDI_RX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 temp &= ~FDI_LINK_TRAIN_AUTO;
2748 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2749 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2750 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2751 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2752
2753 POSTING_READ(reg);
2754 udelay(150);
2755
0206e353 2756 for (i = 0; i < 4; i++) {
357555c0
JB		 2757 reg = FDI_TX_CTL(pipe);
2758 temp = I915_READ(reg);
2759 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2760 temp |= snb_b_fdi_train_param[i];
2761 I915_WRITE(reg, temp);
2762
2763 POSTING_READ(reg);
2764 udelay(500);
2765
2766 reg = FDI_RX_IIR(pipe);
2767 temp = I915_READ(reg);
2768 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2769
2770 if (temp & FDI_RX_BIT_LOCK ||
2771 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2772 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2773 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2774 break;
2775 }
2776 }
2777 if (i == 4)
2778 DRM_ERROR("FDI train 1 fail!\n");
2779
2780 /* Train 2 */
2781 reg = FDI_TX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2784 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2785 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2786 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2787 I915_WRITE(reg, temp);
2788
2789 reg = FDI_RX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2792 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2793 I915_WRITE(reg, temp);
2794
2795 POSTING_READ(reg);
2796 udelay(150);
2797
0206e353 2798 for (i = 0; i < 4; i++) {
357555c0
JB		 2799 reg = FDI_TX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2802 temp |= snb_b_fdi_train_param[i];
2803 I915_WRITE(reg, temp);
2804
2805 POSTING_READ(reg);
2806 udelay(500);
2807
2808 reg = FDI_RX_IIR(pipe);
2809 temp = I915_READ(reg);
2810 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2811
2812 if (temp & FDI_RX_SYMBOL_LOCK) {
2813 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2814 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2815 break;
2816 }
2817 }
2818 if (i == 4)
2819 DRM_ERROR("FDI train 2 fail!\n");
2820
2821 DRM_DEBUG_KMS("FDI train done.\n");
2822}
2823
88cefb6c 2824static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2825{
88cefb6c 2826 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2827 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2828 int pipe = intel_crtc->pipe;
5eddb70b 2829 u32 reg, temp;
79e53945 2830
c64e311e 2831
c98e9dcf 2832 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2833 reg = FDI_RX_CTL(pipe);
2834 temp = I915_READ(reg);
2835 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2836 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2837 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2838 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2839
2840 POSTING_READ(reg);
c98e9dcf
JB		 2841 udelay(200);
2842
2843 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2844 temp = I915_READ(reg);
2845 I915_WRITE(reg, temp | FDI_PCDCLK);
2846
2847 POSTING_READ(reg);
c98e9dcf
JB		 2848 udelay(200);
2849
20749730
PZ		 2850 /* Enable CPU FDI TX PLL, always on for Ironlake */
2851 reg = FDI_TX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2854 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2855
20749730
PZ		 2856 POSTING_READ(reg);
2857 udelay(100);
6be4a607 2858 }
0e23b99d
JB		 2859}
2860
88cefb6c
DV		 2861static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2862{
2863 struct drm_device *dev = intel_crtc->base.dev;
2864 struct drm_i915_private *dev_priv = dev->dev_private;
2865 int pipe = intel_crtc->pipe;
2866 u32 reg, temp;
2867
2868 /* Switch from PCDclk to Rawclk */
2869 reg = FDI_RX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2872
2873 /* Disable CPU FDI TX PLL */
2874 reg = FDI_TX_CTL(pipe);
2875 temp = I915_READ(reg);
2876 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2877
2878 POSTING_READ(reg);
2879 udelay(100);
2880
2881 reg = FDI_RX_CTL(pipe);
2882 temp = I915_READ(reg);
2883 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2884
2885 /* Wait for the clocks to turn off. */
2886 POSTING_READ(reg);
2887 udelay(100);
2888}
2889
0fc932b8
JB		 2890static void ironlake_fdi_disable(struct drm_crtc *crtc)
2891{
2892 struct drm_device *dev = crtc->dev;
2893 struct drm_i915_private *dev_priv = dev->dev_private;
2894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2895 int pipe = intel_crtc->pipe;
2896 u32 reg, temp;
2897
2898 /* disable CPU FDI tx and PCH FDI rx */
2899 reg = FDI_TX_CTL(pipe);
2900 temp = I915_READ(reg);
2901 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2902 POSTING_READ(reg);
2903
2904 reg = FDI_RX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~(0x7 << 16);
dfd07d72 2907 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2908 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2909
2910 POSTING_READ(reg);
2911 udelay(100);
2912
2913 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2914 if (HAS_PCH_IBX(dev)) {
2915 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2916 }
0fc932b8
JB		 2917
2918 /* still set train pattern 1 */
2919 reg = FDI_TX_CTL(pipe);
2920 temp = I915_READ(reg);
2921 temp &= ~FDI_LINK_TRAIN_NONE;
2922 temp |= FDI_LINK_TRAIN_PATTERN_1;
2923 I915_WRITE(reg, temp);
2924
2925 reg = FDI_RX_CTL(pipe);
2926 temp = I915_READ(reg);
2927 if (HAS_PCH_CPT(dev)) {
2928 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2929 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2930 } else {
2931 temp &= ~FDI_LINK_TRAIN_NONE;
2932 temp |= FDI_LINK_TRAIN_PATTERN_1;
2933 }
2934 /* BPC in FDI rx is consistent with that in PIPECONF */
2935 temp &= ~(0x07 << 16);
dfd07d72 2936 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2937 I915_WRITE(reg, temp);
2938
2939 POSTING_READ(reg);
2940 udelay(100);
2941}
2942
5bb61643
CW		 2943static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2944{
2945 struct drm_device *dev = crtc->dev;
2946 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2948 unsigned long flags;
2949 bool pending;
2950
10d83730
VS		 2951 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2952 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2953 return false;
2954
2955 spin_lock_irqsave(&dev->event_lock, flags);
2956 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2957 spin_unlock_irqrestore(&dev->event_lock, flags);
2958
2959 return pending;
2960}
2961
e6c3a2a6
CW		 2962static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2963{
0f91128d 2964 struct drm_device *dev = crtc->dev;
5bb61643 2965 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2966
2967 if (crtc->fb == NULL)
2968 return;
2969
2c10d571
DV		 2970 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2971
5bb61643
CW		 2972 wait_event(dev_priv->pending_flip_queue,
2973 !intel_crtc_has_pending_flip(crtc));
2974
0f91128d
CW		 2975 mutex_lock(&dev->struct_mutex);
2976 intel_finish_fb(crtc->fb);
2977 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2978}
2979
fc316cbe
PZ		 2980static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2981{
2982 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2983}
2984
e615efe4
ED		 2985/* Program iCLKIP clock to the desired frequency */
2986static void lpt_program_iclkip(struct drm_crtc *crtc)
2987{
2988 struct drm_device *dev = crtc->dev;
2989 struct drm_i915_private *dev_priv = dev->dev_private;
2990 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2991 u32 temp;
2992
09153000
DV		 2993 mutex_lock(&dev_priv->dpio_lock);
2994
e615efe4
ED		 2995 /* It is necessary to ungate the pixclk gate prior to programming
2996 * the divisors, and gate it back when it is done.
2997 */
2998 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2999
3000 /* Disable SSCCTL */
3001 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3002 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3003 SBI_SSCCTL_DISABLE,
3004 SBI_ICLK);
e615efe4
ED		 3005
3006 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3007 if (crtc->mode.clock == 20000) {
3008 auxdiv = 1;
3009 divsel = 0x41;
3010 phaseinc = 0x20;
3011 } else {
3012 /* The iCLK virtual clock root frequency is in MHz,
3013 * but the crtc->mode.clock in in KHz. To get the divisors,
3014 * it is necessary to divide one by another, so we
3015 * convert the virtual clock precision to KHz here for higher
3016 * precision.
3017 */
3018 u32 iclk_virtual_root_freq = 172800 * 1000;
3019 u32 iclk_pi_range = 64;
3020 u32 desired_divisor, msb_divisor_value, pi_value;
3021
3022 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3023 msb_divisor_value = desired_divisor / iclk_pi_range;
3024 pi_value = desired_divisor % iclk_pi_range;
3025
3026 auxdiv = 0;
3027 divsel = msb_divisor_value - 2;
3028 phaseinc = pi_value;
3029 }
3030
3031 /* This should not happen with any sane values */
3032 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3033 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3034 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3035 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3036
3037 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3038 crtc->mode.clock,
3039 auxdiv,
3040 divsel,
3041 phasedir,
3042 phaseinc);
3043
3044 /* Program SSCDIVINTPHASE6 */
988d6ee8 3045 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3046 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3047 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3048 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3049 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3050 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3051 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3052 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3053
3054 /* Program SSCAUXDIV */
988d6ee8 3055 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3056 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3057 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3058 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3059
3060 /* Enable modulator and associated divider */
988d6ee8 3061 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3062 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3063 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3064
3065 /* Wait for initialization time */
3066 udelay(24);
3067
3068 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3069
3070 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3071}
3072
f67a559d
JB		 3073/*
3074 * Enable PCH resources required for PCH ports:
3075 * - PCH PLLs
3076 * - FDI training & RX/TX
3077 * - update transcoder timings
3078 * - DP transcoding bits
3079 * - transcoder
3080 */
3081static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3082{
3083 struct drm_device *dev = crtc->dev;
3084 struct drm_i915_private *dev_priv = dev->dev_private;
3085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3086 int pipe = intel_crtc->pipe;
ee7b9f93 3087 u32 reg, temp;
2c07245f 3088
e7e164db
CW		 3089 assert_transcoder_disabled(dev_priv, pipe);
3090
cd986abb
DV		 3091 /* Write the TU size bits before fdi link training, so that error
3092 * detection works. */
3093 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3094 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3095
c98e9dcf 3096 /* For PCH output, training FDI link */
674cf967 3097 dev_priv->display.fdi_link_train(crtc);
2c07245f 3098
572deb37
DV		 3099 /* XXX: pch pll's can be enabled any time before we enable the PCH
3100 * transcoder, and we actually should do this to not upset any PCH
3101 * transcoder that already use the clock when we share it.
3102 *
3103 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3104 * unconditionally resets the pll - we need that to have the right LVDS
3105 * enable sequence. */
b6b4e185 3106 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3107
303b81e0 3108 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3109 u32 sel;
4b645f14 3110
c98e9dcf 3111 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3112 switch (pipe) {
3113 default:
3114 case 0:
3115 temp |= TRANSA_DPLL_ENABLE;
3116 sel = TRANSA_DPLLB_SEL;
3117 break;
3118 case 1:
3119 temp |= TRANSB_DPLL_ENABLE;
3120 sel = TRANSB_DPLLB_SEL;
3121 break;
3122 case 2:
3123 temp |= TRANSC_DPLL_ENABLE;
3124 sel = TRANSC_DPLLB_SEL;
3125 break;
d64311ab 3126 }
ee7b9f93
JB		 3127 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3128 temp |= sel;
3129 else
3130 temp &= ~sel;
c98e9dcf 3131 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3132 }
5eddb70b 3133
d9b6cb56
JB		 3134 /* set transcoder timing, panel must allow it */
3135 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3136 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3137 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3138 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3139
5eddb70b
CW		 3140 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3141 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3142 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3143 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3144
303b81e0 3145 intel_fdi_normal_train(crtc);
5e84e1a4 3146
c98e9dcf
JB		 3147 /* For PCH DP, enable TRANS_DP_CTL */
3148 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3149 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3150 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3151 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3152 reg = TRANS_DP_CTL(pipe);
3153 temp = I915_READ(reg);
3154 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3155 TRANS_DP_SYNC_MASK |
3156 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3157 temp |= (TRANS_DP_OUTPUT_ENABLE |
3158 TRANS_DP_ENH_FRAMING);
9325c9f0 3159 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3160
3161 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3162 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3163 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3164 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3165
3166 switch (intel_trans_dp_port_sel(crtc)) {
3167 case PCH_DP_B:
5eddb70b 3168 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3169 break;
3170 case PCH_DP_C:
5eddb70b 3171 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3172 break;
3173 case PCH_DP_D:
5eddb70b 3174 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3175 break;
3176 default:
e95d41e1 3177 BUG();
32f9d658 3178 }
2c07245f 3179
5eddb70b 3180 I915_WRITE(reg, temp);
6be4a607 3181 }
b52eb4dc 3182
b8a4f404 3183 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3184}
3185
1507e5bd
PZ		 3186static void lpt_pch_enable(struct drm_crtc *crtc)
3187{
3188 struct drm_device *dev = crtc->dev;
3189 struct drm_i915_private *dev_priv = dev->dev_private;
3190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3191 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3192
daed2dbb 3193 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3194
8c52b5e8 3195 lpt_program_iclkip(crtc);
1507e5bd 3196
0540e488 3197 /* Set transcoder timing. */
daed2dbb
PZ		 3198 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3199 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3200 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3201
daed2dbb
PZ		 3202 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3203 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3204 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3205 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3206
937bb610 3207 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3208}
3209
ee7b9f93
JB		 3210static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3211{
3212 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3213
3214 if (pll == NULL)
3215 return;
3216
3217 if (pll->refcount == 0) {
3218 WARN(1, "bad PCH PLL refcount\n");
3219 return;
3220 }
3221
3222 --pll->refcount;
3223 intel_crtc->pch_pll = NULL;
3224}
3225
3226static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3227{
3228 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3229 struct intel_pch_pll *pll;
3230 int i;
3231
3232 pll = intel_crtc->pch_pll;
3233 if (pll) {
3234 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3235 intel_crtc->base.base.id, pll->pll_reg);
3236 goto prepare;
3237 }
3238
98b6bd99
DV		 3239 if (HAS_PCH_IBX(dev_priv->dev)) {
3240 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3241 i = intel_crtc->pipe;
3242 pll = &dev_priv->pch_plls[i];
3243
3244 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3245 intel_crtc->base.base.id, pll->pll_reg);
3246
3247 goto found;
3248 }
3249
ee7b9f93
JB		 3250 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3251 pll = &dev_priv->pch_plls[i];
3252
3253 /* Only want to check enabled timings first */
3254 if (pll->refcount == 0)
3255 continue;
3256
3257 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3258 fp == I915_READ(pll->fp0_reg)) {
3259 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3260 intel_crtc->base.base.id,
3261 pll->pll_reg, pll->refcount, pll->active);
3262
3263 goto found;
3264 }
3265 }
3266
3267 /* Ok no matching timings, maybe there's a free one? */
3268 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3269 pll = &dev_priv->pch_plls[i];
3270 if (pll->refcount == 0) {
3271 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3272 intel_crtc->base.base.id, pll->pll_reg);
3273 goto found;
3274 }
3275 }
3276
3277 return NULL;
3278
3279found:
3280 intel_crtc->pch_pll = pll;
3281 pll->refcount++;
3282 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3283prepare: /* separate function? */
3284 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3285
e04c7350
CW		 3286 /* Wait for the clocks to stabilize before rewriting the regs */
3287 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3288 POSTING_READ(pll->pll_reg);
3289 udelay(150);
e04c7350
CW		 3290
3291 I915_WRITE(pll->fp0_reg, fp);
3292 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3293 pll->on = false;
3294 return pll;
3295}
3296
d4270e57
JB		 3297void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3298{
3299 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3300 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3301 u32 temp;
3302
3303 temp = I915_READ(dslreg);
3304 udelay(500);
3305 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3306 if (wait_for(I915_READ(dslreg) != temp, 5))
3307 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3308 }
3309}
3310
f67a559d
JB		 3311static void ironlake_crtc_enable(struct drm_crtc *crtc)
3312{
3313 struct drm_device *dev = crtc->dev;
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3316 struct intel_encoder *encoder;
f67a559d
JB		 3317 int pipe = intel_crtc->pipe;
3318 int plane = intel_crtc->plane;
3319 u32 temp;
f67a559d 3320
08a48469
DV		 3321 WARN_ON(!crtc->enabled);
3322
f67a559d
JB		 3323 if (intel_crtc->active)
3324 return;
3325
3326 intel_crtc->active = true;
3327 intel_update_watermarks(dev);
3328
3329 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3330 temp = I915_READ(PCH_LVDS);
3331 if ((temp & LVDS_PORT_EN) == 0)
3332 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3333 }
3334
f67a559d 3335
5bfe2ac0 3336 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3337 /* Note: FDI PLL enabling _must_ be done before we enable the
3338 * cpu pipes, hence this is separate from all the other fdi/pch
3339 * enabling. */
88cefb6c 3340 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3341 } else {
3342 assert_fdi_tx_disabled(dev_priv, pipe);
3343 assert_fdi_rx_disabled(dev_priv, pipe);
3344 }
f67a559d 3345
bf49ec8c
DV		 3346 for_each_encoder_on_crtc(dev, crtc, encoder)
3347 if (encoder->pre_enable)
3348 encoder->pre_enable(encoder);
f67a559d
JB		 3349
3350 /* Enable panel fitting for LVDS */
3351 if (dev_priv->pch_pf_size &&
547dc041
JN		 3352 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3353 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3354 /* Force use of hard-coded filter coefficients
3355 * as some pre-programmed values are broken,
3356 * e.g. x201.
3357 */
13888d78
PZ		 3358 if (IS_IVYBRIDGE(dev))
3359 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3360 PF_PIPE_SEL_IVB(pipe));
3361 else
3362 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3363 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3364 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3365 }
3366
9c54c0dd
JB		 3367 /*
3368 * On ILK+ LUT must be loaded before the pipe is running but with
3369 * clocks enabled
3370 */
3371 intel_crtc_load_lut(crtc);
3372
5bfe2ac0
DV		 3373 intel_enable_pipe(dev_priv, pipe,
3374 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3375 intel_enable_plane(dev_priv, plane, pipe);
3376
5bfe2ac0 3377 if (intel_crtc->config.has_pch_encoder)
f67a559d 3378 ironlake_pch_enable(crtc);
c98e9dcf 3379
d1ebd816 3380 mutex_lock(&dev->struct_mutex);
bed4a673 3381 intel_update_fbc(dev);
d1ebd816
BW		 3382 mutex_unlock(&dev->struct_mutex);
3383
6b383a7f 3384 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3385
fa5c73b1
DV		 3386 for_each_encoder_on_crtc(dev, crtc, encoder)
3387 encoder->enable(encoder);
61b77ddd
DV		 3388
3389 if (HAS_PCH_CPT(dev))
3390 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3391
3392 /*
3393 * There seems to be a race in PCH platform hw (at least on some
3394 * outputs) where an enabled pipe still completes any pageflip right
3395 * away (as if the pipe is off) instead of waiting for vblank. As soon
3396 * as the first vblank happend, everything works as expected. Hence just
3397 * wait for one vblank before returning to avoid strange things
3398 * happening.
3399 */
3400 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3401}
3402
4f771f10
PZ		 3403static void haswell_crtc_enable(struct drm_crtc *crtc)
3404{
3405 struct drm_device *dev = crtc->dev;
3406 struct drm_i915_private *dev_priv = dev->dev_private;
3407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3408 struct intel_encoder *encoder;
3409 int pipe = intel_crtc->pipe;
3410 int plane = intel_crtc->plane;
4f771f10
PZ		 3411
3412 WARN_ON(!crtc->enabled);
3413
3414 if (intel_crtc->active)
3415 return;
3416
3417 intel_crtc->active = true;
3418 intel_update_watermarks(dev);
3419
5bfe2ac0 3420 if (intel_crtc->config.has_pch_encoder)
04945641 3421 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3422
3423 for_each_encoder_on_crtc(dev, crtc, encoder)
3424 if (encoder->pre_enable)
3425 encoder->pre_enable(encoder);
3426
1f544388 3427 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3428
1f544388 3429 /* Enable panel fitting for eDP */
547dc041
JN		 3430 if (dev_priv->pch_pf_size &&
3431 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3432 /* Force use of hard-coded filter coefficients
3433 * as some pre-programmed values are broken,
3434 * e.g. x201.
3435 */
54075a7d
PZ		 3436 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3437 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3438 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3439 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3440 }
3441
3442 /*
3443 * On ILK+ LUT must be loaded before the pipe is running but with
3444 * clocks enabled
3445 */
3446 intel_crtc_load_lut(crtc);
3447
1f544388 3448 intel_ddi_set_pipe_settings(crtc);
8228c251 3449 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3450
5bfe2ac0
DV		 3451 intel_enable_pipe(dev_priv, pipe,
3452 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3453 intel_enable_plane(dev_priv, plane, pipe);
3454
5bfe2ac0 3455 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3456 lpt_pch_enable(crtc);
4f771f10
PZ		 3457
3458 mutex_lock(&dev->struct_mutex);
3459 intel_update_fbc(dev);
3460 mutex_unlock(&dev->struct_mutex);
3461
3462 intel_crtc_update_cursor(crtc, true);
3463
3464 for_each_encoder_on_crtc(dev, crtc, encoder)
3465 encoder->enable(encoder);
3466
4f771f10
PZ		 3467 /*
3468 * There seems to be a race in PCH platform hw (at least on some
3469 * outputs) where an enabled pipe still completes any pageflip right
3470 * away (as if the pipe is off) instead of waiting for vblank. As soon
3471 * as the first vblank happend, everything works as expected. Hence just
3472 * wait for one vblank before returning to avoid strange things
3473 * happening.
3474 */
3475 intel_wait_for_vblank(dev, intel_crtc->pipe);
3476}
3477
6be4a607
JB		 3478static void ironlake_crtc_disable(struct drm_crtc *crtc)
3479{
3480 struct drm_device *dev = crtc->dev;
3481 struct drm_i915_private *dev_priv = dev->dev_private;
3482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3483 struct intel_encoder *encoder;
6be4a607
JB		 3484 int pipe = intel_crtc->pipe;
3485 int plane = intel_crtc->plane;
5eddb70b 3486 u32 reg, temp;
b52eb4dc 3487
ef9c3aee 3488
f7abfe8b
CW		 3489 if (!intel_crtc->active)
3490 return;
3491
ea9d758d
DV		 3492 for_each_encoder_on_crtc(dev, crtc, encoder)
3493 encoder->disable(encoder);
3494
e6c3a2a6 3495 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3496 drm_vblank_off(dev, pipe);
6b383a7f 3497 intel_crtc_update_cursor(crtc, false);
5eddb70b 3498
b24e7179 3499 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3500
973d04f9
CW		 3501 if (dev_priv->cfb_plane == plane)
3502 intel_disable_fbc(dev);
2c07245f 3503
b24e7179 3504 intel_disable_pipe(dev_priv, pipe);
32f9d658 3505
6be4a607 3506 /* Disable PF */
9db4a9c7
JB		 3507 I915_WRITE(PF_CTL(pipe), 0);
3508 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3509
bf49ec8c
DV		 3510 for_each_encoder_on_crtc(dev, crtc, encoder)
3511 if (encoder->post_disable)
3512 encoder->post_disable(encoder);
2c07245f 3513
0fc932b8 3514 ironlake_fdi_disable(crtc);
249c0e64 3515
b8a4f404 3516 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3517
6be4a607
JB		 3518 if (HAS_PCH_CPT(dev)) {
3519 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3520 reg = TRANS_DP_CTL(pipe);
3521 temp = I915_READ(reg);
3522 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3523 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3524 I915_WRITE(reg, temp);
6be4a607
JB		 3525
3526 /* disable DPLL_SEL */
3527 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3528 switch (pipe) {
3529 case 0:
d64311ab 3530 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3531 break;
3532 case 1:
6be4a607 3533 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3534 break;
3535 case 2:
4b645f14 3536 /* C shares PLL A or B */
d64311ab 3537 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3538 break;
3539 default:
3540 BUG(); /* wtf */
3541 }
6be4a607 3542 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3543 }
e3421a18 3544
6be4a607 3545 /* disable PCH DPLL */
ee7b9f93 3546 intel_disable_pch_pll(intel_crtc);
8db9d77b 3547
88cefb6c 3548 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3549
f7abfe8b 3550 intel_crtc->active = false;
6b383a7f 3551 intel_update_watermarks(dev);
d1ebd816
BW		 3552
3553 mutex_lock(&dev->struct_mutex);
6b383a7f 3554 intel_update_fbc(dev);
d1ebd816 3555 mutex_unlock(&dev->struct_mutex);
6be4a607 3556}
1b3c7a47 3557
4f771f10 3558static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3559{
4f771f10
PZ		 3560 struct drm_device *dev = crtc->dev;
3561 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3563 struct intel_encoder *encoder;
3564 int pipe = intel_crtc->pipe;
3565 int plane = intel_crtc->plane;
ad80a810 3566 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3567 bool is_pch_port;
ee7b9f93 3568
4f771f10
PZ		 3569 if (!intel_crtc->active)
3570 return;
3571
83616634
PZ		 3572 is_pch_port = haswell_crtc_driving_pch(crtc);
3573
4f771f10
PZ		 3574 for_each_encoder_on_crtc(dev, crtc, encoder)
3575 encoder->disable(encoder);
3576
3577 intel_crtc_wait_for_pending_flips(crtc);
3578 drm_vblank_off(dev, pipe);
3579 intel_crtc_update_cursor(crtc, false);
3580
3581 intel_disable_plane(dev_priv, plane, pipe);
3582
3583 if (dev_priv->cfb_plane == plane)
3584 intel_disable_fbc(dev);
3585
3586 intel_disable_pipe(dev_priv, pipe);
3587
ad80a810 3588 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3589
3590 /* Disable PF */
3591 I915_WRITE(PF_CTL(pipe), 0);
3592 I915_WRITE(PF_WIN_SZ(pipe), 0);
3593
1f544388 3594 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3595
3596 for_each_encoder_on_crtc(dev, crtc, encoder)
3597 if (encoder->post_disable)
3598 encoder->post_disable(encoder);
3599
83616634 3600 if (is_pch_port) {
ab4d966c 3601 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3602 intel_ddi_fdi_disable(crtc);
83616634 3603 }
4f771f10
PZ		 3604
3605 intel_crtc->active = false;
3606 intel_update_watermarks(dev);
3607
3608 mutex_lock(&dev->struct_mutex);
3609 intel_update_fbc(dev);
3610 mutex_unlock(&dev->struct_mutex);
3611}
3612
ee7b9f93
JB		 3613static void ironlake_crtc_off(struct drm_crtc *crtc)
3614{
3615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3616 intel_put_pch_pll(intel_crtc);
3617}
3618
6441ab5f
PZ		 3619static void haswell_crtc_off(struct drm_crtc *crtc)
3620{
a5c961d1
PZ		 3621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3622
3623 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3624 * start using it. */
1a240d4d 3625 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3626
6441ab5f
PZ		 3627 intel_ddi_put_crtc_pll(crtc);
3628}
3629
02e792fb
DV		 3630static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3631{
02e792fb 3632 if (!enable && intel_crtc->overlay) {
23f09ce3 3633 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3634 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3635
23f09ce3 3636 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3637 dev_priv->mm.interruptible = false;
3638 (void) intel_overlay_switch_off(intel_crtc->overlay);
3639 dev_priv->mm.interruptible = true;
23f09ce3 3640 mutex_unlock(&dev->struct_mutex);
02e792fb 3641 }
02e792fb 3642
5dcdbcb0
CW		 3643 /* Let userspace switch the overlay on again. In most cases userspace
3644 * has to recompute where to put it anyway.
3645 */
02e792fb
DV		 3646}
3647
61bc95c1
EE		 3648/**
3649 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3650 * cursor plane briefly if not already running after enabling the display
3651 * plane.
3652 * This workaround avoids occasional blank screens when self refresh is
3653 * enabled.
3654 */
3655static void
3656g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3657{
3658 u32 cntl = I915_READ(CURCNTR(pipe));
3659
3660 if ((cntl & CURSOR_MODE) == 0) {
3661 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3662
3663 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3664 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3665 intel_wait_for_vblank(dev_priv->dev, pipe);
3666 I915_WRITE(CURCNTR(pipe), cntl);
3667 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3668 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3669 }
3670}
3671
0b8765c6 3672static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3673{
3674 struct drm_device *dev = crtc->dev;
79e53945
JB		 3675 struct drm_i915_private *dev_priv = dev->dev_private;
3676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3677 struct intel_encoder *encoder;
79e53945 3678 int pipe = intel_crtc->pipe;
80824003 3679 int plane = intel_crtc->plane;
79e53945 3680
08a48469
DV		 3681 WARN_ON(!crtc->enabled);
3682
f7abfe8b
CW		 3683 if (intel_crtc->active)
3684 return;
3685
3686 intel_crtc->active = true;
6b383a7f
CW		 3687 intel_update_watermarks(dev);
3688
63d7bbe9 3689 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3690
3691 for_each_encoder_on_crtc(dev, crtc, encoder)
3692 if (encoder->pre_enable)
3693 encoder->pre_enable(encoder);
3694
040484af 3695 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3696 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3697 if (IS_G4X(dev))
3698 g4x_fixup_plane(dev_priv, pipe);
79e53945 3699
0b8765c6 3700 intel_crtc_load_lut(crtc);
bed4a673 3701 intel_update_fbc(dev);
79e53945 3702
0b8765c6
JB		 3703 /* Give the overlay scaler a chance to enable if it's on this pipe */
3704 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3705 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3706
fa5c73b1
DV		 3707 for_each_encoder_on_crtc(dev, crtc, encoder)
3708 encoder->enable(encoder);
0b8765c6 3709}
79e53945 3710
0b8765c6
JB		 3711static void i9xx_crtc_disable(struct drm_crtc *crtc)
3712{
3713 struct drm_device *dev = crtc->dev;
3714 struct drm_i915_private *dev_priv = dev->dev_private;
3715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3716 struct intel_encoder *encoder;
0b8765c6
JB		 3717 int pipe = intel_crtc->pipe;
3718 int plane = intel_crtc->plane;
24a1f16d 3719 u32 pctl;
b690e96c 3720
ef9c3aee 3721
f7abfe8b
CW		 3722 if (!intel_crtc->active)
3723 return;
3724
ea9d758d
DV		 3725 for_each_encoder_on_crtc(dev, crtc, encoder)
3726 encoder->disable(encoder);
3727
0b8765c6 3728 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3729 intel_crtc_wait_for_pending_flips(crtc);
3730 drm_vblank_off(dev, pipe);
0b8765c6 3731 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3732 intel_crtc_update_cursor(crtc, false);
0b8765c6 3733
973d04f9
CW		 3734 if (dev_priv->cfb_plane == plane)
3735 intel_disable_fbc(dev);
79e53945 3736
b24e7179 3737 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3738 intel_disable_pipe(dev_priv, pipe);
24a1f16d
MK		 3739
3740 /* Disable pannel fitter if it is on this pipe. */
3741 pctl = I915_READ(PFIT_CONTROL);
3742 if ((pctl & PFIT_ENABLE) &&
3743 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3744 I915_WRITE(PFIT_CONTROL, 0);
3745
63d7bbe9 3746 intel_disable_pll(dev_priv, pipe);
0b8765c6 3747
f7abfe8b 3748 intel_crtc->active = false;
6b383a7f
CW		 3749 intel_update_fbc(dev);
3750 intel_update_watermarks(dev);
0b8765c6
JB		 3751}
3752
ee7b9f93
JB		 3753static void i9xx_crtc_off(struct drm_crtc *crtc)
3754{
3755}
3756
976f8a20
DV		 3757static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3758 bool enabled)
2c07245f
ZW		 3759{
3760 struct drm_device *dev = crtc->dev;
3761 struct drm_i915_master_private *master_priv;
3762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3763 int pipe = intel_crtc->pipe;
79e53945
JB		 3764
3765 if (!dev->primary->master)
3766 return;
3767
3768 master_priv = dev->primary->master->driver_priv;
3769 if (!master_priv->sarea_priv)
3770 return;
3771
79e53945
JB		 3772 switch (pipe) {
3773 case 0:
3774 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3775 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3776 break;
3777 case 1:
3778 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3779 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3780 break;
3781 default:
9db4a9c7 3782 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3783 break;
3784 }
79e53945
JB		 3785}
3786
976f8a20
DV		 3787/**
3788 * Sets the power management mode of the pipe and plane.
3789 */
3790void intel_crtc_update_dpms(struct drm_crtc *crtc)
3791{
3792 struct drm_device *dev = crtc->dev;
3793 struct drm_i915_private *dev_priv = dev->dev_private;
3794 struct intel_encoder *intel_encoder;
3795 bool enable = false;
3796
3797 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3798 enable |= intel_encoder->connectors_active;
3799
3800 if (enable)
3801 dev_priv->display.crtc_enable(crtc);
3802 else
3803 dev_priv->display.crtc_disable(crtc);
3804
3805 intel_crtc_update_sarea(crtc, enable);
3806}
3807
cdd59983
CW		 3808static void intel_crtc_disable(struct drm_crtc *crtc)
3809{
cdd59983 3810 struct drm_device *dev = crtc->dev;
976f8a20 3811 struct drm_connector *connector;
ee7b9f93 3812 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3814
976f8a20
DV		 3815 /* crtc should still be enabled when we disable it. */
3816 WARN_ON(!crtc->enabled);
3817
7b9f35a6 3818 intel_crtc->eld_vld = false;
976f8a20
DV		 3819 dev_priv->display.crtc_disable(crtc);
3820 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3821 dev_priv->display.off(crtc);
3822
931872fc
CW		 3823 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3824 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3825
3826 if (crtc->fb) {
3827 mutex_lock(&dev->struct_mutex);
1690e1eb 3828 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3829 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3830 crtc->fb = NULL;
3831 }
3832
3833 /* Update computed state. */
3834 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3835 if (!connector->encoder || !connector->encoder->crtc)
3836 continue;
3837
3838 if (connector->encoder->crtc != crtc)
3839 continue;
3840
3841 connector->dpms = DRM_MODE_DPMS_OFF;
3842 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3843 }
3844}
3845
a261b246 3846void intel_modeset_disable(struct drm_device *dev)
79e53945 3847{
a261b246
DV		 3848 struct drm_crtc *crtc;
3849
3850 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3851 if (crtc->enabled)
3852 intel_crtc_disable(crtc);
3853 }
79e53945
JB		 3854}
3855
ea5b213a 3856void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3857{
4ef69c7a 3858 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3859
ea5b213a
CW		 3860 drm_encoder_cleanup(encoder);
3861 kfree(intel_encoder);
7e7d76c3
JB		 3862}
3863
5ab432ef
DV		 3864/* Simple dpms helper for encodres with just one connector, no cloning and only
3865 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3866 * state of the entire output pipe. */
3867void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3868{
5ab432ef
DV		 3869 if (mode == DRM_MODE_DPMS_ON) {
3870 encoder->connectors_active = true;
3871
b2cabb0e 3872 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3873 } else {
3874 encoder->connectors_active = false;
3875
b2cabb0e 3876 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3877 }
79e53945
JB		 3878}
3879
0a91ca29
DV		 3880/* Cross check the actual hw state with our own modeset state tracking (and it's
3881 * internal consistency). */
b980514c 3882static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3883{
0a91ca29
DV		 3884 if (connector->get_hw_state(connector)) {
3885 struct intel_encoder *encoder = connector->encoder;
3886 struct drm_crtc *crtc;
3887 bool encoder_enabled;
3888 enum pipe pipe;
3889
3890 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3891 connector->base.base.id,
3892 drm_get_connector_name(&connector->base));
3893
3894 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3895 "wrong connector dpms state\n");
3896 WARN(connector->base.encoder != &encoder->base,
3897 "active connector not linked to encoder\n");
3898 WARN(!encoder->connectors_active,
3899 "encoder->connectors_active not set\n");
3900
3901 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3902 WARN(!encoder_enabled, "encoder not enabled\n");
3903 if (WARN_ON(!encoder->base.crtc))
3904 return;
3905
3906 crtc = encoder->base.crtc;
3907
3908 WARN(!crtc->enabled, "crtc not enabled\n");
3909 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3910 WARN(pipe != to_intel_crtc(crtc)->pipe,
3911 "encoder active on the wrong pipe\n");
3912 }
79e53945
JB		 3913}
3914
5ab432ef
DV		 3915/* Even simpler default implementation, if there's really no special case to
3916 * consider. */
3917void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3918{
5ab432ef 3919 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3920
5ab432ef
DV		 3921 /* All the simple cases only support two dpms states. */
3922 if (mode != DRM_MODE_DPMS_ON)
3923 mode = DRM_MODE_DPMS_OFF;
d4270e57 3924
5ab432ef
DV		 3925 if (mode == connector->dpms)
3926 return;
3927
3928 connector->dpms = mode;
3929
3930 /* Only need to change hw state when actually enabled */
3931 if (encoder->base.crtc)
3932 intel_encoder_dpms(encoder, mode);
3933 else
8af6cf88 3934 WARN_ON(encoder->connectors_active != false);
0a91ca29 3935
b980514c 3936 intel_modeset_check_state(connector->dev);
79e53945
JB		 3937}
3938
f0947c37
DV		 3939/* Simple connector->get_hw_state implementation for encoders that support only
3940 * one connector and no cloning and hence the encoder state determines the state
3941 * of the connector. */
3942bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3943{
24929352 3944 enum pipe pipe = 0;
f0947c37 3945 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3946
f0947c37 3947 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3948}
3949
b8cecdf5
DV		 3950static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3951 struct intel_crtc_config *pipe_config)
79e53945 3952{
2c07245f 3953 struct drm_device *dev = crtc->dev;
b8cecdf5 3954 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 3955
bad720ff 3956 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3957 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 3958 if (pipe_config->requested_mode.clock * 3
3959 > IRONLAKE_FDI_FREQ * 4)
2377b741 3960 return false;
2c07245f 3961 }
89749350 3962
f9bef081
DV		 3963 /* All interlaced capable intel hw wants timings in frames. Note though
3964 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3965 * timings, so we need to be careful not to clobber these.*/
7ae89233 3966 if (!pipe_config->timings_set)
f9bef081 3967 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3968
44f46b42
CW		 3969 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3970 * with a hsync front porch of 0.
3971 */
3972 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3973 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3974 return false;
3975
79e53945
JB		 3976 return true;
3977}
3978
25eb05fc
JB		 3979static int valleyview_get_display_clock_speed(struct drm_device *dev)
3980{
3981 return 400000; /* FIXME */
3982}
3983
e70236a8
JB		 3984static int i945_get_display_clock_speed(struct drm_device *dev)
3985{
3986 return 400000;
3987}
79e53945 3988
e70236a8 3989static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3990{
e70236a8
JB		 3991 return 333000;
3992}
79e53945 3993
e70236a8
JB		 3994static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3995{
3996 return 200000;
3997}
79e53945 3998
e70236a8
JB		 3999static int i915gm_get_display_clock_speed(struct drm_device *dev)
4000{
4001 u16 gcfgc = 0;
79e53945 4002
e70236a8
JB		 4003 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4004
4005 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4006 return 133000;
4007 else {
4008 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4009 case GC_DISPLAY_CLOCK_333_MHZ:
4010 return 333000;
4011 default:
4012 case GC_DISPLAY_CLOCK_190_200_MHZ:
4013 return 190000;
79e53945 4014 }
e70236a8
JB		 4015 }
4016}
4017
4018static int i865_get_display_clock_speed(struct drm_device *dev)
4019{
4020 return 266000;
4021}
4022
4023static int i855_get_display_clock_speed(struct drm_device *dev)
4024{
4025 u16 hpllcc = 0;
4026 /* Assume that the hardware is in the high speed state. This
4027 * should be the default.
4028 */
4029 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4030 case GC_CLOCK_133_200:
4031 case GC_CLOCK_100_200:
4032 return 200000;
4033 case GC_CLOCK_166_250:
4034 return 250000;
4035 case GC_CLOCK_100_133:
79e53945 4036 return 133000;
e70236a8 4037 }
79e53945 4038
e70236a8
JB		 4039 /* Shouldn't happen */
4040 return 0;
4041}
79e53945 4042
e70236a8
JB		 4043static int i830_get_display_clock_speed(struct drm_device *dev)
4044{
4045 return 133000;
79e53945
JB		 4046}
4047
2c07245f 4048static void
e69d0bc1 4049intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4050{
4051 while (*num > 0xffffff || *den > 0xffffff) {
4052 *num >>= 1;
4053 *den >>= 1;
4054 }
4055}
4056
e69d0bc1
DV		 4057void
4058intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4059 int pixel_clock, int link_clock,
4060 struct intel_link_m_n *m_n)
2c07245f 4061{
e69d0bc1 4062 m_n->tu = 64;
22ed1113
CW		 4063 m_n->gmch_m = bits_per_pixel * pixel_clock;
4064 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4065 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4066 m_n->link_m = pixel_clock;
4067 m_n->link_n = link_clock;
e69d0bc1 4068 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4069}
4070
a7615030
CW		 4071static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4072{
72bbe58c
KP		 4073 if (i915_panel_use_ssc >= 0)
4074 return i915_panel_use_ssc != 0;
4075 return dev_priv->lvds_use_ssc
435793df 4076 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4077}
4078
a0c4da24
JB		 4079static int vlv_get_refclk(struct drm_crtc *crtc)
4080{
4081 struct drm_device *dev = crtc->dev;
4082 struct drm_i915_private *dev_priv = dev->dev_private;
4083 int refclk = 27000; /* for DP & HDMI */
4084
4085 return 100000; /* only one validated so far */
4086
4087 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4088 refclk = 96000;
4089 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4090 if (intel_panel_use_ssc(dev_priv))
4091 refclk = 100000;
4092 else
4093 refclk = 96000;
4094 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4095 refclk = 100000;
4096 }
4097
4098 return refclk;
4099}
4100
c65d77d8
JB		 4101static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4102{
4103 struct drm_device *dev = crtc->dev;
4104 struct drm_i915_private *dev_priv = dev->dev_private;
4105 int refclk;
4106
a0c4da24
JB		 4107 if (IS_VALLEYVIEW(dev)) {
4108 refclk = vlv_get_refclk(crtc);
4109 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4110 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4111 refclk = dev_priv->lvds_ssc_freq * 1000;
4112 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4113 refclk / 1000);
4114 } else if (!IS_GEN2(dev)) {
4115 refclk = 96000;
4116 } else {
4117 refclk = 48000;
4118 }
4119
4120 return refclk;
4121}
4122
4123static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4124 intel_clock_t *clock)
4125{
4126 /* SDVO TV has fixed PLL values depend on its clock range,
4127 this mirrors vbios setting. */
4128 if (adjusted_mode->clock >= 100000
4129 && adjusted_mode->clock < 140500) {
4130 clock->p1 = 2;
4131 clock->p2 = 10;
4132 clock->n = 3;
4133 clock->m1 = 16;
4134 clock->m2 = 8;
4135 } else if (adjusted_mode->clock >= 140500
4136 && adjusted_mode->clock <= 200000) {
4137 clock->p1 = 1;
4138 clock->p2 = 10;
4139 clock->n = 6;
4140 clock->m1 = 12;
4141 clock->m2 = 8;
4142 }
4143}
4144
a7516a05
JB		 4145static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4146 intel_clock_t *clock,
4147 intel_clock_t *reduced_clock)
4148{
4149 struct drm_device *dev = crtc->dev;
4150 struct drm_i915_private *dev_priv = dev->dev_private;
4151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4152 int pipe = intel_crtc->pipe;
4153 u32 fp, fp2 = 0;
4154
4155 if (IS_PINEVIEW(dev)) {
4156 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4157 if (reduced_clock)
4158 fp2 = (1 << reduced_clock->n) << 16 |
4159 reduced_clock->m1 << 8 | reduced_clock->m2;
4160 } else {
4161 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4162 if (reduced_clock)
4163 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4164 reduced_clock->m2;
4165 }
4166
4167 I915_WRITE(FP0(pipe), fp);
4168
4169 intel_crtc->lowfreq_avail = false;
4170 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4171 reduced_clock && i915_powersave) {
4172 I915_WRITE(FP1(pipe), fp2);
4173 intel_crtc->lowfreq_avail = true;
4174 } else {
4175 I915_WRITE(FP1(pipe), fp);
4176 }
4177}
4178
a0c4da24 4179static void vlv_update_pll(struct drm_crtc *crtc,
a0c4da24 4180 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4181 int num_connectors)
a0c4da24
JB		 4182{
4183 struct drm_device *dev = crtc->dev;
4184 struct drm_i915_private *dev_priv = dev->dev_private;
4185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 4186 struct drm_display_mode *adjusted_mode =
4187 &intel_crtc->config.adjusted_mode;
4188 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
a0c4da24
JB		 4189 int pipe = intel_crtc->pipe;
4190 u32 dpll, mdiv, pdiv;
4191 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4192 bool is_sdvo;
4193 u32 temp;
a0c4da24 4194
09153000
DV		 4195 mutex_lock(&dev_priv->dpio_lock);
4196
2a8f64ca
VP		 4197 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4198 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4199
2a8f64ca
VP		 4200 dpll = DPLL_VGA_MODE_DIS;
4201 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4202 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4203 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4204
4205 I915_WRITE(DPLL(pipe), dpll);
4206 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4207
4208 bestn = clock->n;
4209 bestm1 = clock->m1;
4210 bestm2 = clock->m2;
4211 bestp1 = clock->p1;
4212 bestp2 = clock->p2;
4213
2a8f64ca
VP		 4214 /*
4215 * In Valleyview PLL and program lane counter registers are exposed
4216 * through DPIO interface
4217 */
a0c4da24
JB		 4218 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4219 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4220 mdiv |= ((bestn << DPIO_N_SHIFT));
4221 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4222 mdiv |= (1 << DPIO_K_SHIFT);
4223 mdiv |= DPIO_ENABLE_CALIBRATION;
4224 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4225
4226 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4227
2a8f64ca 4228 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4229 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4230 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4231 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4232 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4233
2a8f64ca 4234 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4235
4236 dpll |= DPLL_VCO_ENABLE;
4237 I915_WRITE(DPLL(pipe), dpll);
4238 POSTING_READ(DPLL(pipe));
4239 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4240 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4241
2a8f64ca
VP		 4242 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4243
4244 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4245 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4246
4247 I915_WRITE(DPLL(pipe), dpll);
4248
4249 /* Wait for the clocks to stabilize. */
4250 POSTING_READ(DPLL(pipe));
4251 udelay(150);
a0c4da24 4252
2a8f64ca
VP		 4253 temp = 0;
4254 if (is_sdvo) {
6cc5f341
DV		 4255 temp = 0;
4256 if (intel_crtc->config.pixel_multiplier > 1) {
4257 temp = (intel_crtc->config.pixel_multiplier - 1)
4258 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4259 }
a0c4da24 4260 }
2a8f64ca
VP		 4261 I915_WRITE(DPLL_MD(pipe), temp);
4262 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4263
2a8f64ca
VP		 4264 /* Now program lane control registers */
4265 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4266 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4267 {
4268 temp = 0x1000C4;
4269 if(pipe == 1)
4270 temp |= (1 << 21);
4271 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4272 }
4273 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4274 {
4275 temp = 0x1000C4;
4276 if(pipe == 1)
4277 temp |= (1 << 21);
4278 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4279 }
09153000
DV		 4280
4281 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4282}
4283
eb1cbe48 4284static void i9xx_update_pll(struct drm_crtc *crtc,
eb1cbe48
DV		 4285 intel_clock_t *clock, intel_clock_t *reduced_clock,
4286 int num_connectors)
4287{
4288 struct drm_device *dev = crtc->dev;
4289 struct drm_i915_private *dev_priv = dev->dev_private;
4290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 4291 struct drm_display_mode *adjusted_mode =
4292 &intel_crtc->config.adjusted_mode;
4293 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
dafd226c 4294 struct intel_encoder *encoder;
eb1cbe48
DV		 4295 int pipe = intel_crtc->pipe;
4296 u32 dpll;
4297 bool is_sdvo;
4298
2a8f64ca
VP		 4299 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4300
eb1cbe48
DV		 4301 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4302 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4303
4304 dpll = DPLL_VGA_MODE_DIS;
4305
4306 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4307 dpll |= DPLLB_MODE_LVDS;
4308 else
4309 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4310
eb1cbe48 4311 if (is_sdvo) {
6cc5f341
DV		 4312 if ((intel_crtc->config.pixel_multiplier > 1) &&
4313 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4314 dpll |= (intel_crtc->config.pixel_multiplier - 1)
4315 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48
DV		 4316 }
4317 dpll |= DPLL_DVO_HIGH_SPEED;
4318 }
4319 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4320 dpll |= DPLL_DVO_HIGH_SPEED;
4321
4322 /* compute bitmask from p1 value */
4323 if (IS_PINEVIEW(dev))
4324 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4325 else {
4326 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4327 if (IS_G4X(dev) && reduced_clock)
4328 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4329 }
4330 switch (clock->p2) {
4331 case 5:
4332 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4333 break;
4334 case 7:
4335 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4336 break;
4337 case 10:
4338 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4339 break;
4340 case 14:
4341 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4342 break;
4343 }
4344 if (INTEL_INFO(dev)->gen >= 4)
4345 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4346
4347 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4348 dpll |= PLL_REF_INPUT_TVCLKINBC;
4349 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4350 /* XXX: just matching BIOS for now */
4351 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4352 dpll |= 3;
4353 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4354 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4355 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4356 else
4357 dpll |= PLL_REF_INPUT_DREFCLK;
4358
4359 dpll |= DPLL_VCO_ENABLE;
4360 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4361 POSTING_READ(DPLL(pipe));
4362 udelay(150);
4363
dafd226c
DV		 4364 for_each_encoder_on_crtc(dev, crtc, encoder)
4365 if (encoder->pre_pll_enable)
4366 encoder->pre_pll_enable(encoder);
eb1cbe48
DV		 4367
4368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4369 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4370
4371 I915_WRITE(DPLL(pipe), dpll);
4372
4373 /* Wait for the clocks to stabilize. */
4374 POSTING_READ(DPLL(pipe));
4375 udelay(150);
4376
4377 if (INTEL_INFO(dev)->gen >= 4) {
4378 u32 temp = 0;
4379 if (is_sdvo) {
6cc5f341
DV		 4380 temp = 0;
4381 if (intel_crtc->config.pixel_multiplier > 1) {
4382 temp = (intel_crtc->config.pixel_multiplier - 1)
4383 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4384 }
eb1cbe48
DV		 4385 }
4386 I915_WRITE(DPLL_MD(pipe), temp);
4387 } else {
4388 /* The pixel multiplier can only be updated once the
4389 * DPLL is enabled and the clocks are stable.
4390 *
4391 * So write it again.
4392 */
4393 I915_WRITE(DPLL(pipe), dpll);
4394 }
4395}
4396
4397static void i8xx_update_pll(struct drm_crtc *crtc,
4398 struct drm_display_mode *adjusted_mode,
2a8f64ca 4399 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4400 int num_connectors)
4401{
4402 struct drm_device *dev = crtc->dev;
4403 struct drm_i915_private *dev_priv = dev->dev_private;
4404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4405 struct intel_encoder *encoder;
eb1cbe48
DV		 4406 int pipe = intel_crtc->pipe;
4407 u32 dpll;
4408
2a8f64ca
VP		 4409 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4410
eb1cbe48
DV		 4411 dpll = DPLL_VGA_MODE_DIS;
4412
4413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4414 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4415 } else {
4416 if (clock->p1 == 2)
4417 dpll |= PLL_P1_DIVIDE_BY_TWO;
4418 else
4419 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4420 if (clock->p2 == 4)
4421 dpll |= PLL_P2_DIVIDE_BY_4;
4422 }
4423
83f377ab 4424 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4425 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4426 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4427 else
4428 dpll |= PLL_REF_INPUT_DREFCLK;
4429
4430 dpll |= DPLL_VCO_ENABLE;
4431 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4432 POSTING_READ(DPLL(pipe));
4433 udelay(150);
4434
dafd226c
DV		 4435 for_each_encoder_on_crtc(dev, crtc, encoder)
4436 if (encoder->pre_pll_enable)
4437 encoder->pre_pll_enable(encoder);
eb1cbe48 4438
5b5896e4
DV		 4439 I915_WRITE(DPLL(pipe), dpll);
4440
4441 /* Wait for the clocks to stabilize. */
4442 POSTING_READ(DPLL(pipe));
4443 udelay(150);
4444
eb1cbe48
DV		 4445 /* The pixel multiplier can only be updated once the
4446 * DPLL is enabled and the clocks are stable.
4447 *
4448 * So write it again.
4449 */
4450 I915_WRITE(DPLL(pipe), dpll);
4451}
4452
b0e77b9c
PZ		 4453static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4454 struct drm_display_mode *mode,
4455 struct drm_display_mode *adjusted_mode)
4456{
4457 struct drm_device *dev = intel_crtc->base.dev;
4458 struct drm_i915_private *dev_priv = dev->dev_private;
4459 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4460 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4461 uint32_t vsyncshift;
4462
4463 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4464 /* the chip adds 2 halflines automatically */
4465 adjusted_mode->crtc_vtotal -= 1;
4466 adjusted_mode->crtc_vblank_end -= 1;
4467 vsyncshift = adjusted_mode->crtc_hsync_start
4468 - adjusted_mode->crtc_htotal / 2;
4469 } else {
4470 vsyncshift = 0;
4471 }
4472
4473 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4474 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4475
fe2b8f9d 4476 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4477 (adjusted_mode->crtc_hdisplay - 1) |
4478 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4479 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4480 (adjusted_mode->crtc_hblank_start - 1) |
4481 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4482 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4483 (adjusted_mode->crtc_hsync_start - 1) |
4484 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4485
fe2b8f9d 4486 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4487 (adjusted_mode->crtc_vdisplay - 1) |
4488 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4489 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4490 (adjusted_mode->crtc_vblank_start - 1) |
4491 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4492 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4493 (adjusted_mode->crtc_vsync_start - 1) |
4494 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4495
b5e508d4
PZ		 4496 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4497 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4498 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4499 * bits. */
4500 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4501 (pipe == PIPE_B || pipe == PIPE_C))
4502 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4503
b0e77b9c
PZ		 4504 /* pipesrc controls the size that is scaled from, which should
4505 * always be the user's requested size.
4506 */
4507 I915_WRITE(PIPESRC(pipe),
4508 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4509}
4510
f564048e 4511static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4512 int x, int y,
94352cf9 4513 struct drm_framebuffer *fb)
79e53945
JB		 4514{
4515 struct drm_device *dev = crtc->dev;
4516 struct drm_i915_private *dev_priv = dev->dev_private;
4517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4518 struct drm_display_mode *adjusted_mode =
4519 &intel_crtc->config.adjusted_mode;
4520 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4521 int pipe = intel_crtc->pipe;
80824003 4522 int plane = intel_crtc->plane;
c751ce4f 4523 int refclk, num_connectors = 0;
652c393a 4524 intel_clock_t clock, reduced_clock;
b0e77b9c 4525 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4526 bool ok, has_reduced_clock = false, is_sdvo = false;
4527 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4528 struct intel_encoder *encoder;
d4906093 4529 const intel_limit_t *limit;
5c3b82e2 4530 int ret;
79e53945 4531
6c2b7c12 4532 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4533 switch (encoder->type) {
79e53945
JB		 4534 case INTEL_OUTPUT_LVDS:
4535 is_lvds = true;
4536 break;
4537 case INTEL_OUTPUT_SDVO:
7d57382e 4538 case INTEL_OUTPUT_HDMI:
79e53945 4539 is_sdvo = true;
5eddb70b 4540 if (encoder->needs_tv_clock)
e2f0ba97 4541 is_tv = true;
79e53945 4542 break;
79e53945
JB		 4543 case INTEL_OUTPUT_TVOUT:
4544 is_tv = true;
4545 break;
a4fc5ed6
KP		 4546 case INTEL_OUTPUT_DISPLAYPORT:
4547 is_dp = true;
4548 break;
79e53945 4549 }
43565a06 4550
c751ce4f 4551 num_connectors++;
79e53945
JB		 4552 }
4553
c65d77d8 4554 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4555
d4906093
ML		 4556 /*
4557 * Returns a set of divisors for the desired target clock with the given
4558 * refclk, or FALSE. The returned values represent the clock equation:
4559 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4560 */
1b894b59 4561 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4562 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4563 &clock);
79e53945
JB		 4564 if (!ok) {
4565 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4566 return -EINVAL;
79e53945
JB		 4567 }
4568
cda4b7d3 4569 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4570 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4571
ddc9003c 4572 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4573 /*
4574 * Ensure we match the reduced clock's P to the target clock.
4575 * If the clocks don't match, we can't switch the display clock
4576 * by using the FP0/FP1. In such case we will disable the LVDS
4577 * downclock feature.
4578 */
ddc9003c 4579 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4580 dev_priv->lvds_downclock,
4581 refclk,
cec2f356 4582 &clock,
5eddb70b 4583 &reduced_clock);
7026d4ac
ZW		 4584 }
4585
c65d77d8
JB		 4586 if (is_sdvo && is_tv)
4587 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4588
eb1cbe48 4589 if (IS_GEN2(dev))
2a8f64ca
VP		 4590 i8xx_update_pll(crtc, adjusted_mode, &clock,
4591 has_reduced_clock ? &reduced_clock : NULL,
4592 num_connectors);
a0c4da24 4593 else if (IS_VALLEYVIEW(dev))
6cc5f341 4594 vlv_update_pll(crtc, &clock,
2a8f64ca
VP		 4595 has_reduced_clock ? &reduced_clock : NULL,
4596 num_connectors);
79e53945 4597 else
6cc5f341 4598 i9xx_update_pll(crtc, &clock,
eb1cbe48
DV		 4599 has_reduced_clock ? &reduced_clock : NULL,
4600 num_connectors);
79e53945
JB		 4601
4602 /* setup pipeconf */
5eddb70b 4603 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4604
4605 /* Set up the display plane register */
4606 dspcntr = DISPPLANE_GAMMA_ENABLE;
4607
da6ecc5d
JB		 4608 if (!IS_VALLEYVIEW(dev)) {
4609 if (pipe == 0)
4610 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4611 else
4612 dspcntr |= DISPPLANE_SEL_PIPE_B;
4613 }
79e53945 4614
a6c45cf0 4615 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4616 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4617 * core speed.
4618 *
4619 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4620 * pipe == 0 check?
4621 */
e70236a8
JB		 4622 if (mode->clock >
4623 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4624 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4625 else
5eddb70b 4626 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4627 }
4628
3b5c78a3 4629 /* default to 8bpc */
dfd07d72 4630 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
3b5c78a3 4631 if (is_dp) {
965e0c48 4632 if (intel_crtc->config.dither) {
dfd07d72 4633 pipeconf |= PIPECONF_6BPC |
3b5c78a3
AJ		 4634 PIPECONF_DITHER_EN |
4635 PIPECONF_DITHER_TYPE_SP;
4636 }
4637 }
4638
19c03924 4639 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
965e0c48 4640 if (intel_crtc->config.dither) {
dfd07d72 4641 pipeconf |= PIPECONF_6BPC |
19c03924
GB		 4642 PIPECONF_ENABLE |
4643 I965_PIPECONF_ACTIVE;
4644 }
4645 }
4646
28c97730 4647 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4648 drm_mode_debug_printmodeline(mode);
4649
a7516a05
JB		 4650 if (HAS_PIPE_CXSR(dev)) {
4651 if (intel_crtc->lowfreq_avail) {
28c97730 4652 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4653 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4654 } else {
28c97730 4655 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4656 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4657 }
4658 }
4659
617cf884 4660 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4661 if (!IS_GEN2(dev) &&
b0e77b9c 4662 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4663 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4664 else
617cf884 4665 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4666
b0e77b9c 4667 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4668
4669 /* pipesrc and dspsize control the size that is scaled from,
4670 * which should always be the user's requested size.
79e53945 4671 */
929c77fb
EA		 4672 I915_WRITE(DSPSIZE(plane),
4673 ((mode->vdisplay - 1) << 16) |
4674 (mode->hdisplay - 1));
4675 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4676
f564048e
EA		 4677 I915_WRITE(PIPECONF(pipe), pipeconf);
4678 POSTING_READ(PIPECONF(pipe));
929c77fb 4679 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4680
4681 intel_wait_for_vblank(dev, pipe);
4682
f564048e
EA		 4683 I915_WRITE(DSPCNTR(plane), dspcntr);
4684 POSTING_READ(DSPCNTR(plane));
4685
94352cf9 4686 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4687
4688 intel_update_watermarks(dev);
4689
f564048e
EA		 4690 return ret;
4691}
4692
dde86e2d 4693static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4694{
4695 struct drm_i915_private *dev_priv = dev->dev_private;
4696 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4697 struct intel_encoder *encoder;
13d83a67
JB		 4698 u32 temp;
4699 bool has_lvds = false;
199e5d79
KP		 4700 bool has_cpu_edp = false;
4701 bool has_pch_edp = false;
4702 bool has_panel = false;
99eb6a01
KP		 4703 bool has_ck505 = false;
4704 bool can_ssc = false;
13d83a67
JB		 4705
4706 /* We need to take the global config into account */
199e5d79
KP		 4707 list_for_each_entry(encoder, &mode_config->encoder_list,
4708 base.head) {
4709 switch (encoder->type) {
4710 case INTEL_OUTPUT_LVDS:
4711 has_panel = true;
4712 has_lvds = true;
4713 break;
4714 case INTEL_OUTPUT_EDP:
4715 has_panel = true;
4716 if (intel_encoder_is_pch_edp(&encoder->base))
4717 has_pch_edp = true;
4718 else
4719 has_cpu_edp = true;
4720 break;
13d83a67
JB		 4721 }
4722 }
4723
99eb6a01
KP		 4724 if (HAS_PCH_IBX(dev)) {
4725 has_ck505 = dev_priv->display_clock_mode;
4726 can_ssc = has_ck505;
4727 } else {
4728 has_ck505 = false;
4729 can_ssc = true;
4730 }
4731
4732 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4733 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4734 has_ck505);
13d83a67
JB		 4735
4736 /* Ironlake: try to setup display ref clock before DPLL
4737 * enabling. This is only under driver's control after
4738 * PCH B stepping, previous chipset stepping should be
4739 * ignoring this setting.
4740 */
4741 temp = I915_READ(PCH_DREF_CONTROL);
4742 /* Always enable nonspread source */
4743 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4744
99eb6a01
KP		 4745 if (has_ck505)
4746 temp |= DREF_NONSPREAD_CK505_ENABLE;
4747 else
4748 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4749
199e5d79
KP		 4750 if (has_panel) {
4751 temp &= ~DREF_SSC_SOURCE_MASK;
4752 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4753
199e5d79 4754 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4755 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4756 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4757 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4758 } else
4759 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4760
4761 /* Get SSC going before enabling the outputs */
4762 I915_WRITE(PCH_DREF_CONTROL, temp);
4763 POSTING_READ(PCH_DREF_CONTROL);
4764 udelay(200);
4765
13d83a67
JB		 4766 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4767
4768 /* Enable CPU source on CPU attached eDP */
199e5d79 4769 if (has_cpu_edp) {
99eb6a01 4770 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4771 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4772 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4773 }
13d83a67
JB		 4774 else
4775 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4776 } else
4777 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4778
4779 I915_WRITE(PCH_DREF_CONTROL, temp);
4780 POSTING_READ(PCH_DREF_CONTROL);
4781 udelay(200);
4782 } else {
4783 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4784
4785 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4786
4787 /* Turn off CPU output */
4788 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4789
4790 I915_WRITE(PCH_DREF_CONTROL, temp);
4791 POSTING_READ(PCH_DREF_CONTROL);
4792 udelay(200);
4793
4794 /* Turn off the SSC source */
4795 temp &= ~DREF_SSC_SOURCE_MASK;
4796 temp |= DREF_SSC_SOURCE_DISABLE;
4797
4798 /* Turn off SSC1 */
4799 temp &= ~ DREF_SSC1_ENABLE;
4800
13d83a67
JB		 4801 I915_WRITE(PCH_DREF_CONTROL, temp);
4802 POSTING_READ(PCH_DREF_CONTROL);
4803 udelay(200);
4804 }
4805}
4806
dde86e2d
PZ		 4807/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4808static void lpt_init_pch_refclk(struct drm_device *dev)
4809{
4810 struct drm_i915_private *dev_priv = dev->dev_private;
4811 struct drm_mode_config *mode_config = &dev->mode_config;
4812 struct intel_encoder *encoder;
4813 bool has_vga = false;
4814 bool is_sdv = false;
4815 u32 tmp;
4816
4817 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4818 switch (encoder->type) {
4819 case INTEL_OUTPUT_ANALOG:
4820 has_vga = true;
4821 break;
4822 }
4823 }
4824
4825 if (!has_vga)
4826 return;
4827
c00db246
DV		 4828 mutex_lock(&dev_priv->dpio_lock);
4829
dde86e2d
PZ		 4830 /* XXX: Rip out SDV support once Haswell ships for real. */
4831 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4832 is_sdv = true;
4833
4834 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4835 tmp &= ~SBI_SSCCTL_DISABLE;
4836 tmp |= SBI_SSCCTL_PATHALT;
4837 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4838
4839 udelay(24);
4840
4841 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4842 tmp &= ~SBI_SSCCTL_PATHALT;
4843 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4844
4845 if (!is_sdv) {
4846 tmp = I915_READ(SOUTH_CHICKEN2);
4847 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4848 I915_WRITE(SOUTH_CHICKEN2, tmp);
4849
4850 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4851 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4852 DRM_ERROR("FDI mPHY reset assert timeout\n");
4853
4854 tmp = I915_READ(SOUTH_CHICKEN2);
4855 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4856 I915_WRITE(SOUTH_CHICKEN2, tmp);
4857
4858 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4859 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4860 100))
4861 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4862 }
4863
4864 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4865 tmp &= ~(0xFF << 24);
4866 tmp |= (0x12 << 24);
4867 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4868
4869 if (!is_sdv) {
4870 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4871 tmp &= ~(0x3 << 6);
4872 tmp |= (1 << 6) | (1 << 0);
4873 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4874 }
4875
4876 if (is_sdv) {
4877 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4878 tmp |= 0x7FFF;
4879 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4880 }
4881
4882 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4883 tmp |= (1 << 11);
4884 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4885
4886 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4887 tmp |= (1 << 11);
4888 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4889
4890 if (is_sdv) {
4891 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4892 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4893 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4894
4895 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4896 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4897 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4898
4899 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4900 tmp |= (0x3F << 8);
4901 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4902
4903 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4904 tmp |= (0x3F << 8);
4905 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4906 }
4907
4908 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4909 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4910 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4911
4912 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4913 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4914 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4915
4916 if (!is_sdv) {
4917 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4918 tmp &= ~(7 << 13);
4919 tmp |= (5 << 13);
4920 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4921
4922 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4923 tmp &= ~(7 << 13);
4924 tmp |= (5 << 13);
4925 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4926 }
4927
4928 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4929 tmp &= ~0xFF;
4930 tmp |= 0x1C;
4931 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4932
4933 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
4934 tmp &= ~0xFF;
4935 tmp |= 0x1C;
4936 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
4937
4938 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
4939 tmp &= ~(0xFF << 16);
4940 tmp |= (0x1C << 16);
4941 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
4942
4943 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
4944 tmp &= ~(0xFF << 16);
4945 tmp |= (0x1C << 16);
4946 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
4947
4948 if (!is_sdv) {
4949 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
4950 tmp |= (1 << 27);
4951 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
4952
4953 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
4954 tmp |= (1 << 27);
4955 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
4956
4957 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
4958 tmp &= ~(0xF << 28);
4959 tmp |= (4 << 28);
4960 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
4961
4962 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
4963 tmp &= ~(0xF << 28);
4964 tmp |= (4 << 28);
4965 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
4966 }
4967
4968 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
4969 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
4970 tmp |= SBI_DBUFF0_ENABLE;
4971 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 4972
4973 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 4974}
4975
4976/*
4977 * Initialize reference clocks when the driver loads
4978 */
4979void intel_init_pch_refclk(struct drm_device *dev)
4980{
4981 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4982 ironlake_init_pch_refclk(dev);
4983 else if (HAS_PCH_LPT(dev))
4984 lpt_init_pch_refclk(dev);
4985}
4986
d9d444cb
JB		 4987static int ironlake_get_refclk(struct drm_crtc *crtc)
4988{
4989 struct drm_device *dev = crtc->dev;
4990 struct drm_i915_private *dev_priv = dev->dev_private;
4991 struct intel_encoder *encoder;
d9d444cb
JB		 4992 struct intel_encoder *edp_encoder = NULL;
4993 int num_connectors = 0;
4994 bool is_lvds = false;
4995
6c2b7c12 4996 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4997 switch (encoder->type) {
4998 case INTEL_OUTPUT_LVDS:
4999 is_lvds = true;
5000 break;
5001 case INTEL_OUTPUT_EDP:
5002 edp_encoder = encoder;
5003 break;
5004 }
5005 num_connectors++;
5006 }
5007
5008 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5009 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5010 dev_priv->lvds_ssc_freq);
5011 return dev_priv->lvds_ssc_freq * 1000;
5012 }
5013
5014 return 120000;
5015}
5016
c8203565 5017static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5018 struct drm_display_mode *adjusted_mode,
c8203565 5019 bool dither)
79e53945 5020{
c8203565 5021 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5023 int pipe = intel_crtc->pipe;
c8203565
PZ		 5024 uint32_t val;
5025
5026 val = I915_READ(PIPECONF(pipe));
5027
dfd07d72 5028 val &= ~PIPECONF_BPC_MASK;
965e0c48 5029 switch (intel_crtc->config.pipe_bpp) {
c8203565 5030 case 18:
dfd07d72 5031 val |= PIPECONF_6BPC;
c8203565
PZ		 5032 break;
5033 case 24:
dfd07d72 5034 val |= PIPECONF_8BPC;
c8203565
PZ		 5035 break;
5036 case 30:
dfd07d72 5037 val |= PIPECONF_10BPC;
c8203565
PZ		 5038 break;
5039 case 36:
dfd07d72 5040 val |= PIPECONF_12BPC;
c8203565
PZ		 5041 break;
5042 default:
cc769b62
PZ		 5043 /* Case prevented by intel_choose_pipe_bpp_dither. */
5044 BUG();
c8203565
PZ		 5045 }
5046
5047 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5048 if (dither)
5049 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5050
5051 val &= ~PIPECONF_INTERLACE_MASK;
5052 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5053 val |= PIPECONF_INTERLACED_ILK;
5054 else
5055 val |= PIPECONF_PROGRESSIVE;
5056
50f3b016 5057 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5058 val |= PIPECONF_COLOR_RANGE_SELECT;
5059 else
5060 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5061
c8203565
PZ		 5062 I915_WRITE(PIPECONF(pipe), val);
5063 POSTING_READ(PIPECONF(pipe));
5064}
5065
86d3efce
VS		 5066/*
5067 * Set up the pipe CSC unit.
5068 *
5069 * Currently only full range RGB to limited range RGB conversion
5070 * is supported, but eventually this should handle various
5071 * RGB<->YCbCr scenarios as well.
5072 */
50f3b016 5073static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5074{
5075 struct drm_device *dev = crtc->dev;
5076 struct drm_i915_private *dev_priv = dev->dev_private;
5077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5078 int pipe = intel_crtc->pipe;
5079 uint16_t coeff = 0x7800; /* 1.0 */
5080
5081 /*
5082 * TODO: Check what kind of values actually come out of the pipe
5083 * with these coeff/postoff values and adjust to get the best
5084 * accuracy. Perhaps we even need to take the bpc value into
5085 * consideration.
5086 */
5087
50f3b016 5088 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5089 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5090
5091 /*
5092 * GY/GU and RY/RU should be the other way around according
5093 * to BSpec, but reality doesn't agree. Just set them up in
5094 * a way that results in the correct picture.
5095 */
5096 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5097 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5098
5099 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5100 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5101
5102 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5103 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5104
5105 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5106 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5107 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5108
5109 if (INTEL_INFO(dev)->gen > 6) {
5110 uint16_t postoff = 0;
5111
50f3b016 5112 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5113 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5114
5115 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5116 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5117 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5118
5119 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5120 } else {
5121 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5122
50f3b016 5123 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5124 mode |= CSC_BLACK_SCREEN_OFFSET;
5125
5126 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5127 }
5128}
5129
ee2b0b38
PZ		 5130static void haswell_set_pipeconf(struct drm_crtc *crtc,
5131 struct drm_display_mode *adjusted_mode,
5132 bool dither)
5133{
5134 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5136 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5137 uint32_t val;
5138
702e7a56 5139 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5140
5141 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5142 if (dither)
5143 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5144
5145 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5146 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5147 val |= PIPECONF_INTERLACED_ILK;
5148 else
5149 val |= PIPECONF_PROGRESSIVE;
5150
702e7a56
PZ		 5151 I915_WRITE(PIPECONF(cpu_transcoder), val);
5152 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5153}
5154
6591c6e4
PZ		 5155static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5156 struct drm_display_mode *adjusted_mode,
5157 intel_clock_t *clock,
5158 bool *has_reduced_clock,
5159 intel_clock_t *reduced_clock)
5160{
5161 struct drm_device *dev = crtc->dev;
5162 struct drm_i915_private *dev_priv = dev->dev_private;
5163 struct intel_encoder *intel_encoder;
5164 int refclk;
d4906093 5165 const intel_limit_t *limit;
6591c6e4 5166 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5167
6591c6e4
PZ		 5168 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5169 switch (intel_encoder->type) {
79e53945
JB		 5170 case INTEL_OUTPUT_LVDS:
5171 is_lvds = true;
5172 break;
5173 case INTEL_OUTPUT_SDVO:
7d57382e 5174 case INTEL_OUTPUT_HDMI:
79e53945 5175 is_sdvo = true;
6591c6e4 5176 if (intel_encoder->needs_tv_clock)
e2f0ba97 5177 is_tv = true;
79e53945 5178 break;
79e53945
JB		 5179 case INTEL_OUTPUT_TVOUT:
5180 is_tv = true;
5181 break;
79e53945
JB		 5182 }
5183 }
5184
d9d444cb 5185 refclk = ironlake_get_refclk(crtc);
79e53945 5186
d4906093
ML		 5187 /*
5188 * Returns a set of divisors for the desired target clock with the given
5189 * refclk, or FALSE. The returned values represent the clock equation:
5190 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5191 */
1b894b59 5192 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5193 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5194 clock);
5195 if (!ret)
5196 return false;
cda4b7d3 5197
ddc9003c 5198 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5199 /*
5200 * Ensure we match the reduced clock's P to the target clock.
5201 * If the clocks don't match, we can't switch the display clock
5202 * by using the FP0/FP1. In such case we will disable the LVDS
5203 * downclock feature.
5204 */
6591c6e4
PZ		 5205 *has_reduced_clock = limit->find_pll(limit, crtc,
5206 dev_priv->lvds_downclock,
5207 refclk,
5208 clock,
5209 reduced_clock);
652c393a 5210 }
61e9653f
DV		 5211
5212 if (is_sdvo && is_tv)
6591c6e4
PZ		 5213 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5214
5215 return true;
5216}
5217
01a415fd
DV		 5218static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5219{
5220 struct drm_i915_private *dev_priv = dev->dev_private;
5221 uint32_t temp;
5222
5223 temp = I915_READ(SOUTH_CHICKEN1);
5224 if (temp & FDI_BC_BIFURCATION_SELECT)
5225 return;
5226
5227 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5228 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5229
5230 temp |= FDI_BC_BIFURCATION_SELECT;
5231 DRM_DEBUG_KMS("enabling fdi C rx\n");
5232 I915_WRITE(SOUTH_CHICKEN1, temp);
5233 POSTING_READ(SOUTH_CHICKEN1);
5234}
5235
5236static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5237{
5238 struct drm_device *dev = intel_crtc->base.dev;
5239 struct drm_i915_private *dev_priv = dev->dev_private;
5240 struct intel_crtc *pipe_B_crtc =
5241 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5242
5243 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5244 intel_crtc->pipe, intel_crtc->fdi_lanes);
5245 if (intel_crtc->fdi_lanes > 4) {
5246 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5247 intel_crtc->pipe, intel_crtc->fdi_lanes);
5248 /* Clamp lanes to avoid programming the hw with bogus values. */
5249 intel_crtc->fdi_lanes = 4;
5250
5251 return false;
5252 }
5253
7eb552ae 5254 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5255 return true;
5256
5257 switch (intel_crtc->pipe) {
5258 case PIPE_A:
5259 return true;
5260 case PIPE_B:
5261 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5262 intel_crtc->fdi_lanes > 2) {
5263 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5264 intel_crtc->pipe, intel_crtc->fdi_lanes);
5265 /* Clamp lanes to avoid programming the hw with bogus values. */
5266 intel_crtc->fdi_lanes = 2;
5267
5268 return false;
5269 }
5270
5271 if (intel_crtc->fdi_lanes > 2)
5272 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5273 else
5274 cpt_enable_fdi_bc_bifurcation(dev);
5275
5276 return true;
5277 case PIPE_C:
5278 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5279 if (intel_crtc->fdi_lanes > 2) {
5280 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5281 intel_crtc->pipe, intel_crtc->fdi_lanes);
5282 /* Clamp lanes to avoid programming the hw with bogus values. */
5283 intel_crtc->fdi_lanes = 2;
5284
5285 return false;
5286 }
5287 } else {
5288 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5289 return false;
5290 }
5291
5292 cpt_enable_fdi_bc_bifurcation(dev);
5293
5294 return true;
5295 default:
5296 BUG();
5297 }
5298}
5299
d4b1931c
PZ		 5300int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5301{
5302 /*
5303 * Account for spread spectrum to avoid
5304 * oversubscribing the link. Max center spread
5305 * is 2.5%; use 5% for safety's sake.
5306 */
5307 u32 bps = target_clock * bpp * 21 / 20;
5308 return bps / (link_bw * 8) + 1;
5309}
5310
6cc5f341 5311static void ironlake_set_m_n(struct drm_crtc *crtc)
79e53945
JB		 5312{
5313 struct drm_device *dev = crtc->dev;
5314 struct drm_i915_private *dev_priv = dev->dev_private;
5315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 5316 struct drm_display_mode *adjusted_mode =
5317 &intel_crtc->config.adjusted_mode;
5318 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
afe2fcf5 5319 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5320 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
e69d0bc1 5321 struct intel_link_m_n m_n = {0};
6cc5f341 5322 int target_clock, lane, link_bw;
f48d8f23 5323 bool is_dp = false, is_cpu_edp = false;
79e53945 5324
f48d8f23
PZ		 5325 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5326 switch (intel_encoder->type) {
a4fc5ed6
KP		 5327 case INTEL_OUTPUT_DISPLAYPORT:
5328 is_dp = true;
5329 break;
32f9d658 5330 case INTEL_OUTPUT_EDP:
e3aef172 5331 is_dp = true;
f48d8f23 5332 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5333 is_cpu_edp = true;
f48d8f23 5334 edp_encoder = intel_encoder;
32f9d658 5335 break;
79e53945 5336 }
79e53945 5337 }
61e9653f 5338
2c07245f 5339 /* FDI link */
8febb297
EA		 5340 lane = 0;
5341 /* CPU eDP doesn't require FDI link, so just set DP M/N
5342 according to current link config */
e3aef172 5343 if (is_cpu_edp) {
e3aef172 5344 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5345 } else {
8febb297
EA		 5346 /* FDI is a binary signal running at ~2.7GHz, encoding
5347 * each output octet as 10 bits. The actual frequency
5348 * is stored as a divider into a 100MHz clock, and the
5349 * mode pixel clock is stored in units of 1KHz.
5350 * Hence the bw of each lane in terms of the mode signal
5351 * is:
5352 */
5353 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5354 }
58a27471 5355
94bf2ced
DV		 5356 /* [e]DP over FDI requires target mode clock instead of link clock. */
5357 if (edp_encoder)
5358 target_clock = intel_edp_target_clock(edp_encoder, mode);
5359 else if (is_dp)
5360 target_clock = mode->clock;
5361 else
5362 target_clock = adjusted_mode->clock;
5363
d4b1931c
PZ		 5364 if (!lane)
5365 lane = ironlake_get_lanes_required(target_clock, link_bw,
965e0c48 5366 intel_crtc->config.pipe_bpp);
2c07245f 5367
8febb297
EA		 5368 intel_crtc->fdi_lanes = lane;
5369
6cc5f341
DV		 5370 if (intel_crtc->config.pixel_multiplier > 1)
5371 link_bw *= intel_crtc->config.pixel_multiplier;
965e0c48
DV		 5372 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5373 link_bw, &m_n);
8febb297 5374
afe2fcf5
PZ		 5375 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5376 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5377 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5378 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5379}
5380
de13a2e3 5381static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
de13a2e3 5382 intel_clock_t *clock, u32 fp)
79e53945 5383{
de13a2e3 5384 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5385 struct drm_device *dev = crtc->dev;
5386 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5387 struct intel_encoder *intel_encoder;
5388 uint32_t dpll;
6cc5f341 5389 int factor, num_connectors = 0;
de13a2e3
PZ		 5390 bool is_lvds = false, is_sdvo = false, is_tv = false;
5391 bool is_dp = false, is_cpu_edp = false;
79e53945 5392
de13a2e3
PZ		 5393 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5394 switch (intel_encoder->type) {
79e53945
JB		 5395 case INTEL_OUTPUT_LVDS:
5396 is_lvds = true;
5397 break;
5398 case INTEL_OUTPUT_SDVO:
7d57382e 5399 case INTEL_OUTPUT_HDMI:
79e53945 5400 is_sdvo = true;
de13a2e3 5401 if (intel_encoder->needs_tv_clock)
e2f0ba97 5402 is_tv = true;
79e53945 5403 break;
79e53945
JB		 5404 case INTEL_OUTPUT_TVOUT:
5405 is_tv = true;
5406 break;
a4fc5ed6
KP		 5407 case INTEL_OUTPUT_DISPLAYPORT:
5408 is_dp = true;
5409 break;
32f9d658 5410 case INTEL_OUTPUT_EDP:
e3aef172 5411 is_dp = true;
de13a2e3 5412 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5413 is_cpu_edp = true;
32f9d658 5414 break;
79e53945 5415 }
43565a06 5416
c751ce4f 5417 num_connectors++;
79e53945 5418 }
79e53945 5419
c1858123 5420 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5421 factor = 21;
5422 if (is_lvds) {
5423 if ((intel_panel_use_ssc(dev_priv) &&
5424 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5425 intel_is_dual_link_lvds(dev))
8febb297
EA		 5426 factor = 25;
5427 } else if (is_sdvo && is_tv)
5428 factor = 20;
c1858123 5429
de13a2e3 5430 if (clock->m < factor * clock->n)
8febb297 5431 fp |= FP_CB_TUNE;
2c07245f 5432
5eddb70b 5433 dpll = 0;
2c07245f 5434
a07d6787
EA		 5435 if (is_lvds)
5436 dpll |= DPLLB_MODE_LVDS;
5437 else
5438 dpll |= DPLLB_MODE_DAC_SERIAL;
5439 if (is_sdvo) {
6cc5f341
DV		 5440 if (intel_crtc->config.pixel_multiplier > 1) {
5441 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5442 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5443 }
a07d6787
EA		 5444 dpll |= DPLL_DVO_HIGH_SPEED;
5445 }
e3aef172 5446 if (is_dp && !is_cpu_edp)
a07d6787 5447 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5448
a07d6787 5449 /* compute bitmask from p1 value */
de13a2e3 5450 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5451 /* also FPA1 */
de13a2e3 5452 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5453
de13a2e3 5454 switch (clock->p2) {
a07d6787
EA		 5455 case 5:
5456 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5457 break;
5458 case 7:
5459 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5460 break;
5461 case 10:
5462 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5463 break;
5464 case 14:
5465 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5466 break;
79e53945
JB		 5467 }
5468
43565a06
KH		 5469 if (is_sdvo && is_tv)
5470 dpll |= PLL_REF_INPUT_TVCLKINBC;
5471 else if (is_tv)
79e53945 5472 /* XXX: just matching BIOS for now */
43565a06 5473 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5474 dpll |= 3;
a7615030 5475 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5476 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5477 else
5478 dpll |= PLL_REF_INPUT_DREFCLK;
5479
de13a2e3
PZ		 5480 return dpll;
5481}
5482
5483static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5484 int x, int y,
5485 struct drm_framebuffer *fb)
5486{
5487 struct drm_device *dev = crtc->dev;
5488 struct drm_i915_private *dev_priv = dev->dev_private;
5489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5490 struct drm_display_mode *adjusted_mode =
5491 &intel_crtc->config.adjusted_mode;
5492 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5493 int pipe = intel_crtc->pipe;
5494 int plane = intel_crtc->plane;
5495 int num_connectors = 0;
5496 intel_clock_t clock, reduced_clock;
5497 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5498 bool ok, has_reduced_clock = false;
5499 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5500 struct intel_encoder *encoder;
de13a2e3 5501 int ret;
01a415fd 5502 bool dither, fdi_config_ok;
de13a2e3
PZ		 5503
5504 for_each_encoder_on_crtc(dev, crtc, encoder) {
5505 switch (encoder->type) {
5506 case INTEL_OUTPUT_LVDS:
5507 is_lvds = true;
5508 break;
de13a2e3
PZ		 5509 case INTEL_OUTPUT_DISPLAYPORT:
5510 is_dp = true;
5511 break;
5512 case INTEL_OUTPUT_EDP:
5513 is_dp = true;
e2f12b07 5514 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5515 is_cpu_edp = true;
5516 break;
5517 }
5518
5519 num_connectors++;
a07d6787 5520 }
79e53945 5521
5dc5298b
PZ		 5522 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5523 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5524
de13a2e3
PZ		 5525 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5526 &has_reduced_clock, &reduced_clock);
5527 if (!ok) {
5528 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5529 return -EINVAL;
79e53945
JB		 5530 }
5531
de13a2e3
PZ		 5532 /* Ensure that the cursor is valid for the new mode before changing... */
5533 intel_crtc_update_cursor(crtc, true);
5534
5535 /* determine panel color depth */
4e53c2e0 5536 dither = intel_crtc->config.dither;
de13a2e3
PZ		 5537 if (is_lvds && dev_priv->lvds_dither)
5538 dither = true;
5539
5540 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5541 if (has_reduced_clock)
5542 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5543 reduced_clock.m2;
5544
6cc5f341 5545 dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
79e53945 5546
f7cb34d4 5547 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5548 drm_mode_debug_printmodeline(mode);
5549
5dc5298b
PZ		 5550 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5551 if (!is_cpu_edp) {
ee7b9f93 5552 struct intel_pch_pll *pll;
4b645f14 5553
ee7b9f93
JB		 5554 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5555 if (pll == NULL) {
5556 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5557 pipe);
4b645f14
JB		 5558 return -EINVAL;
5559 }
ee7b9f93
JB		 5560 } else
5561 intel_put_pch_pll(intel_crtc);
79e53945 5562
2f0c2ad1 5563 if (is_dp && !is_cpu_edp)
a4fc5ed6 5564 intel_dp_set_m_n(crtc, mode, adjusted_mode);
79e53945 5565
dafd226c
DV		 5566 for_each_encoder_on_crtc(dev, crtc, encoder)
5567 if (encoder->pre_pll_enable)
5568 encoder->pre_pll_enable(encoder);
79e53945 5569
ee7b9f93
JB		 5570 if (intel_crtc->pch_pll) {
5571 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5572
32f9d658 5573 /* Wait for the clocks to stabilize. */
ee7b9f93 5574 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5575 udelay(150);
5576
8febb297
EA		 5577 /* The pixel multiplier can only be updated once the
5578 * DPLL is enabled and the clocks are stable.
5579 *
5580 * So write it again.
5581 */
ee7b9f93 5582 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5583 }
79e53945 5584
5eddb70b 5585 intel_crtc->lowfreq_avail = false;
ee7b9f93 5586 if (intel_crtc->pch_pll) {
4b645f14 5587 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5588 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5589 intel_crtc->lowfreq_avail = true;
4b645f14 5590 } else {
ee7b9f93 5591 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5592 }
5593 }
5594
b0e77b9c 5595 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5596
01a415fd
DV		 5597 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5598 * ironlake_check_fdi_lanes. */
6cc5f341 5599 ironlake_set_m_n(crtc);
2c07245f 5600
01a415fd 5601 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5602
c8203565 5603 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5604
9d0498a2 5605 intel_wait_for_vblank(dev, pipe);
79e53945 5606
a1f9e77e
PZ		 5607 /* Set up the display plane register */
5608 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5609 POSTING_READ(DSPCNTR(plane));
79e53945 5610
94352cf9 5611 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5612
5613 intel_update_watermarks(dev);
5614
1f8eeabf
ED		 5615 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5616
01a415fd 5617 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5618}
5619
d6dd9eb1
DV		 5620static void haswell_modeset_global_resources(struct drm_device *dev)
5621{
5622 struct drm_i915_private *dev_priv = dev->dev_private;
5623 bool enable = false;
5624 struct intel_crtc *crtc;
5625 struct intel_encoder *encoder;
5626
5627 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5628 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5629 enable = true;
5630 /* XXX: Should check for edp transcoder here, but thanks to init
5631 * sequence that's not yet available. Just in case desktop eDP
5632 * on PORT D is possible on haswell, too. */
5633 }
5634
5635 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5636 base.head) {
5637 if (encoder->type != INTEL_OUTPUT_EDP &&
5638 encoder->connectors_active)
5639 enable = true;
5640 }
5641
5642 /* Even the eDP panel fitter is outside the always-on well. */
5643 if (dev_priv->pch_pf_size)
5644 enable = true;
5645
5646 intel_set_power_well(dev, enable);
5647}
5648
09b4ddf9 5649static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5650 int x, int y,
5651 struct drm_framebuffer *fb)
5652{
5653 struct drm_device *dev = crtc->dev;
5654 struct drm_i915_private *dev_priv = dev->dev_private;
5655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5656 struct drm_display_mode *adjusted_mode =
5657 &intel_crtc->config.adjusted_mode;
5658 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5659 int pipe = intel_crtc->pipe;
5660 int plane = intel_crtc->plane;
5661 int num_connectors = 0;
ed7ef439 5662 bool is_dp = false, is_cpu_edp = false;
09b4ddf9 5663 struct intel_encoder *encoder;
09b4ddf9
PZ		 5664 int ret;
5665 bool dither;
5666
5667 for_each_encoder_on_crtc(dev, crtc, encoder) {
5668 switch (encoder->type) {
09b4ddf9
PZ		 5669 case INTEL_OUTPUT_DISPLAYPORT:
5670 is_dp = true;
5671 break;
5672 case INTEL_OUTPUT_EDP:
5673 is_dp = true;
5674 if (!intel_encoder_is_pch_edp(&encoder->base))
5675 is_cpu_edp = true;
5676 break;
5677 }
5678
5679 num_connectors++;
5680 }
5681
5dc5298b
PZ		 5682 /* We are not sure yet this won't happen. */
5683 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5684 INTEL_PCH_TYPE(dev));
5685
5686 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5687 num_connectors, pipe_name(pipe));
5688
702e7a56 5689 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5690 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5691
5692 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5693
6441ab5f
PZ		 5694 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5695 return -EINVAL;
5696
09b4ddf9
PZ		 5697 /* Ensure that the cursor is valid for the new mode before changing... */
5698 intel_crtc_update_cursor(crtc, true);
5699
5700 /* determine panel color depth */
4e53c2e0 5701 dither = intel_crtc->config.dither;
09b4ddf9 5702
09b4ddf9
PZ		 5703 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5704 drm_mode_debug_printmodeline(mode);
5705
ed7ef439 5706 if (is_dp && !is_cpu_edp)
09b4ddf9 5707 intel_dp_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9
PZ		 5708
5709 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5710
5711 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5712
1eb8dfec 5713 if (!is_dp || is_cpu_edp)
6cc5f341 5714 ironlake_set_m_n(crtc);
09b4ddf9 5715
ee2b0b38 5716 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5717
50f3b016 5718 intel_set_pipe_csc(crtc);
86d3efce 5719
09b4ddf9 5720 /* Set up the display plane register */
86d3efce 5721 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5722 POSTING_READ(DSPCNTR(plane));
5723
5724 ret = intel_pipe_set_base(crtc, x, y, fb);
5725
5726 intel_update_watermarks(dev);
5727
5728 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5729
1f803ee5 5730 return ret;
79e53945
JB		 5731}
5732
f564048e 5733static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5734 int x, int y,
94352cf9 5735 struct drm_framebuffer *fb)
f564048e
EA		 5736{
5737 struct drm_device *dev = crtc->dev;
5738 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5739 struct drm_encoder_helper_funcs *encoder_funcs;
5740 struct intel_encoder *encoder;
0b701d27 5741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5742 struct drm_display_mode *adjusted_mode =
5743 &intel_crtc->config.adjusted_mode;
5744 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5745 int pipe = intel_crtc->pipe;
f564048e
EA		 5746 int ret;
5747
cc464b2a
PZ		 5748 if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5749 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5750 else
5751 intel_crtc->cpu_transcoder = pipe;
5752
0b701d27 5753 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5754
b8cecdf5
DV		 5755 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5756
79e53945 5757 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5758
9256aa19
DV		 5759 if (ret != 0)
5760 return ret;
5761
5762 for_each_encoder_on_crtc(dev, crtc, encoder) {
5763 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5764 encoder->base.base.id,
5765 drm_get_encoder_name(&encoder->base),
5766 mode->base.id, mode->name);
6cc5f341
DV		 5767 if (encoder->mode_set) {
5768 encoder->mode_set(encoder);
5769 } else {
5770 encoder_funcs = encoder->base.helper_private;
5771 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5772 }
9256aa19
DV		 5773 }
5774
5775 return 0;
79e53945
JB		 5776}
5777
3a9627f4
WF		 5778static bool intel_eld_uptodate(struct drm_connector *connector,
5779 int reg_eldv, uint32_t bits_eldv,
5780 int reg_elda, uint32_t bits_elda,
5781 int reg_edid)
5782{
5783 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5784 uint8_t *eld = connector->eld;
5785 uint32_t i;
5786
5787 i = I915_READ(reg_eldv);
5788 i &= bits_eldv;
5789
5790 if (!eld[0])
5791 return !i;
5792
5793 if (!i)
5794 return false;
5795
5796 i = I915_READ(reg_elda);
5797 i &= ~bits_elda;
5798 I915_WRITE(reg_elda, i);
5799
5800 for (i = 0; i < eld[2]; i++)
5801 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5802 return false;
5803
5804 return true;
5805}
5806
e0dac65e
WF		 5807static void g4x_write_eld(struct drm_connector *connector,
5808 struct drm_crtc *crtc)
5809{
5810 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5811 uint8_t *eld = connector->eld;
5812 uint32_t eldv;
5813 uint32_t len;
5814 uint32_t i;
5815
5816 i = I915_READ(G4X_AUD_VID_DID);
5817
5818 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5819 eldv = G4X_ELDV_DEVCL_DEVBLC;
5820 else
5821 eldv = G4X_ELDV_DEVCTG;
5822
3a9627f4
WF		 5823 if (intel_eld_uptodate(connector,
5824 G4X_AUD_CNTL_ST, eldv,
5825 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5826 G4X_HDMIW_HDMIEDID))
5827 return;
5828
e0dac65e
WF		 5829 i = I915_READ(G4X_AUD_CNTL_ST);
5830 i &= ~(eldv | G4X_ELD_ADDR);
5831 len = (i >> 9) & 0x1f; /* ELD buffer size */
5832 I915_WRITE(G4X_AUD_CNTL_ST, i);
5833
5834 if (!eld[0])
5835 return;
5836
5837 len = min_t(uint8_t, eld[2], len);
5838 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5839 for (i = 0; i < len; i++)
5840 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5841
5842 i = I915_READ(G4X_AUD_CNTL_ST);
5843 i |= eldv;
5844 I915_WRITE(G4X_AUD_CNTL_ST, i);
5845}
5846
83358c85
WX		 5847static void haswell_write_eld(struct drm_connector *connector,
5848 struct drm_crtc *crtc)
5849{
5850 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5851 uint8_t *eld = connector->eld;
5852 struct drm_device *dev = crtc->dev;
7b9f35a6 5853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 5854 uint32_t eldv;
5855 uint32_t i;
5856 int len;
5857 int pipe = to_intel_crtc(crtc)->pipe;
5858 int tmp;
5859
5860 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5861 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5862 int aud_config = HSW_AUD_CFG(pipe);
5863 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5864
5865
5866 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5867
5868 /* Audio output enable */
5869 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5870 tmp = I915_READ(aud_cntrl_st2);
5871 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5872 I915_WRITE(aud_cntrl_st2, tmp);
5873
5874 /* Wait for 1 vertical blank */
5875 intel_wait_for_vblank(dev, pipe);
5876
5877 /* Set ELD valid state */
5878 tmp = I915_READ(aud_cntrl_st2);
5879 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5880 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5881 I915_WRITE(aud_cntrl_st2, tmp);
5882 tmp = I915_READ(aud_cntrl_st2);
5883 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5884
5885 /* Enable HDMI mode */
5886 tmp = I915_READ(aud_config);
5887 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5888 /* clear N_programing_enable and N_value_index */
5889 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5890 I915_WRITE(aud_config, tmp);
5891
5892 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5893
5894 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 5895 intel_crtc->eld_vld = true;
83358c85
WX		 5896
5897 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5898 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5899 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5900 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5901 } else
5902 I915_WRITE(aud_config, 0);
5903
5904 if (intel_eld_uptodate(connector,
5905 aud_cntrl_st2, eldv,
5906 aud_cntl_st, IBX_ELD_ADDRESS,
5907 hdmiw_hdmiedid))
5908 return;
5909
5910 i = I915_READ(aud_cntrl_st2);
5911 i &= ~eldv;
5912 I915_WRITE(aud_cntrl_st2, i);
5913
5914 if (!eld[0])
5915 return;
5916
5917 i = I915_READ(aud_cntl_st);
5918 i &= ~IBX_ELD_ADDRESS;
5919 I915_WRITE(aud_cntl_st, i);
5920 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5921 DRM_DEBUG_DRIVER("port num:%d\n", i);
5922
5923 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5924 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5925 for (i = 0; i < len; i++)
5926 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5927
5928 i = I915_READ(aud_cntrl_st2);
5929 i |= eldv;
5930 I915_WRITE(aud_cntrl_st2, i);
5931
5932}
5933
e0dac65e
WF		 5934static void ironlake_write_eld(struct drm_connector *connector,
5935 struct drm_crtc *crtc)
5936{
5937 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5938 uint8_t *eld = connector->eld;
5939 uint32_t eldv;
5940 uint32_t i;
5941 int len;
5942 int hdmiw_hdmiedid;
b6daa025 5943 int aud_config;
e0dac65e
WF		 5944 int aud_cntl_st;
5945 int aud_cntrl_st2;
9b138a83 5946 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5947
b3f33cbf 5948 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5949 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5950 aud_config = IBX_AUD_CFG(pipe);
5951 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5952 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5953 } else {
9b138a83
WX		 5954 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5955 aud_config = CPT_AUD_CFG(pipe);
5956 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5957 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5958 }
5959
9b138a83 5960 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5961
5962 i = I915_READ(aud_cntl_st);
9b138a83 5963 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5964 if (!i) {
5965 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5966 /* operate blindly on all ports */
1202b4c6
WF		 5967 eldv = IBX_ELD_VALIDB;
5968 eldv |= IBX_ELD_VALIDB << 4;
5969 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5970 } else {
5971 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5972 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5973 }
5974
3a9627f4
WF		 5975 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5976 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5977 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5978 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5979 } else
5980 I915_WRITE(aud_config, 0);
e0dac65e 5981
3a9627f4
WF		 5982 if (intel_eld_uptodate(connector,
5983 aud_cntrl_st2, eldv,
5984 aud_cntl_st, IBX_ELD_ADDRESS,
5985 hdmiw_hdmiedid))
5986 return;
5987
e0dac65e
WF		 5988 i = I915_READ(aud_cntrl_st2);
5989 i &= ~eldv;
5990 I915_WRITE(aud_cntrl_st2, i);
5991
5992 if (!eld[0])
5993 return;
5994
e0dac65e 5995 i = I915_READ(aud_cntl_st);
1202b4c6 5996 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5997 I915_WRITE(aud_cntl_st, i);
5998
5999 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6000 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6001 for (i = 0; i < len; i++)
6002 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6003
6004 i = I915_READ(aud_cntrl_st2);
6005 i |= eldv;
6006 I915_WRITE(aud_cntrl_st2, i);
6007}
6008
6009void intel_write_eld(struct drm_encoder *encoder,
6010 struct drm_display_mode *mode)
6011{
6012 struct drm_crtc *crtc = encoder->crtc;
6013 struct drm_connector *connector;
6014 struct drm_device *dev = encoder->dev;
6015 struct drm_i915_private *dev_priv = dev->dev_private;
6016
6017 connector = drm_select_eld(encoder, mode);
6018 if (!connector)
6019 return;
6020
6021 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6022 connector->base.id,
6023 drm_get_connector_name(connector),
6024 connector->encoder->base.id,
6025 drm_get_encoder_name(connector->encoder));
6026
6027 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6028
6029 if (dev_priv->display.write_eld)
6030 dev_priv->display.write_eld(connector, crtc);
6031}
6032
79e53945
JB		 6033/** Loads the palette/gamma unit for the CRTC with the prepared values */
6034void intel_crtc_load_lut(struct drm_crtc *crtc)
6035{
6036 struct drm_device *dev = crtc->dev;
6037 struct drm_i915_private *dev_priv = dev->dev_private;
6038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6039 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6040 int i;
6041
6042 /* The clocks have to be on to load the palette. */
aed3f09d 6043 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6044 return;
6045
f2b115e6 6046 /* use legacy palette for Ironlake */
bad720ff 6047 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6048 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6049
79e53945
JB		 6050 for (i = 0; i < 256; i++) {
6051 I915_WRITE(palreg + 4 * i,
6052 (intel_crtc->lut_r[i] << 16) |
6053 (intel_crtc->lut_g[i] << 8) |
6054 intel_crtc->lut_b[i]);
6055 }
6056}
6057
560b85bb
CW		 6058static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6059{
6060 struct drm_device *dev = crtc->dev;
6061 struct drm_i915_private *dev_priv = dev->dev_private;
6062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6063 bool visible = base != 0;
6064 u32 cntl;
6065
6066 if (intel_crtc->cursor_visible == visible)
6067 return;
6068
9db4a9c7 6069 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6070 if (visible) {
6071 /* On these chipsets we can only modify the base whilst
6072 * the cursor is disabled.
6073 */
9db4a9c7 6074 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6075
6076 cntl &= ~(CURSOR_FORMAT_MASK);
6077 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6078 cntl |= CURSOR_ENABLE |
6079 CURSOR_GAMMA_ENABLE |
6080 CURSOR_FORMAT_ARGB;
6081 } else
6082 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6083 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6084
6085 intel_crtc->cursor_visible = visible;
6086}
6087
6088static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6089{
6090 struct drm_device *dev = crtc->dev;
6091 struct drm_i915_private *dev_priv = dev->dev_private;
6092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6093 int pipe = intel_crtc->pipe;
6094 bool visible = base != 0;
6095
6096 if (intel_crtc->cursor_visible != visible) {
548f245b 6097 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6098 if (base) {
6099 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6100 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6101 cntl |= pipe << 28; /* Connect to correct pipe */
6102 } else {
6103 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6104 cntl |= CURSOR_MODE_DISABLE;
6105 }
9db4a9c7 6106 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6107
6108 intel_crtc->cursor_visible = visible;
6109 }
6110 /* and commit changes on next vblank */
9db4a9c7 6111 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6112}
6113
65a21cd6
JB		 6114static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6115{
6116 struct drm_device *dev = crtc->dev;
6117 struct drm_i915_private *dev_priv = dev->dev_private;
6118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6119 int pipe = intel_crtc->pipe;
6120 bool visible = base != 0;
6121
6122 if (intel_crtc->cursor_visible != visible) {
6123 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6124 if (base) {
6125 cntl &= ~CURSOR_MODE;
6126 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6127 } else {
6128 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6129 cntl |= CURSOR_MODE_DISABLE;
6130 }
86d3efce
VS		 6131 if (IS_HASWELL(dev))
6132 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6133 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6134
6135 intel_crtc->cursor_visible = visible;
6136 }
6137 /* and commit changes on next vblank */
6138 I915_WRITE(CURBASE_IVB(pipe), base);
6139}
6140
cda4b7d3 6141/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6142static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6143 bool on)
cda4b7d3
CW		 6144{
6145 struct drm_device *dev = crtc->dev;
6146 struct drm_i915_private *dev_priv = dev->dev_private;
6147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6148 int pipe = intel_crtc->pipe;
6149 int x = intel_crtc->cursor_x;
6150 int y = intel_crtc->cursor_y;
560b85bb 6151 u32 base, pos;
cda4b7d3
CW		 6152 bool visible;
6153
6154 pos = 0;
6155
6b383a7f 6156 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6157 base = intel_crtc->cursor_addr;
6158 if (x > (int) crtc->fb->width)
6159 base = 0;
6160
6161 if (y > (int) crtc->fb->height)
6162 base = 0;
6163 } else
6164 base = 0;
6165
6166 if (x < 0) {
6167 if (x + intel_crtc->cursor_width < 0)
6168 base = 0;
6169
6170 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6171 x = -x;
6172 }
6173 pos |= x << CURSOR_X_SHIFT;
6174
6175 if (y < 0) {
6176 if (y + intel_crtc->cursor_height < 0)
6177 base = 0;
6178
6179 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6180 y = -y;
6181 }
6182 pos |= y << CURSOR_Y_SHIFT;
6183
6184 visible = base != 0;
560b85bb 6185 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6186 return;
6187
0cd83aa9 6188 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6189 I915_WRITE(CURPOS_IVB(pipe), pos);
6190 ivb_update_cursor(crtc, base);
6191 } else {
6192 I915_WRITE(CURPOS(pipe), pos);
6193 if (IS_845G(dev) || IS_I865G(dev))
6194 i845_update_cursor(crtc, base);
6195 else
6196 i9xx_update_cursor(crtc, base);
6197 }
cda4b7d3
CW		 6198}
6199
79e53945 6200static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6201 struct drm_file *file,
79e53945
JB		 6202 uint32_t handle,
6203 uint32_t width, uint32_t height)
6204{
6205 struct drm_device *dev = crtc->dev;
6206 struct drm_i915_private *dev_priv = dev->dev_private;
6207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6208 struct drm_i915_gem_object *obj;
cda4b7d3 6209 uint32_t addr;
3f8bc370 6210 int ret;
79e53945 6211
79e53945
JB		 6212 /* if we want to turn off the cursor ignore width and height */
6213 if (!handle) {
28c97730 6214 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6215 addr = 0;
05394f39 6216 obj = NULL;
5004417d 6217 mutex_lock(&dev->struct_mutex);
3f8bc370 6218 goto finish;
79e53945
JB		 6219 }
6220
6221 /* Currently we only support 64x64 cursors */
6222 if (width != 64 || height != 64) {
6223 DRM_ERROR("we currently only support 64x64 cursors\n");
6224 return -EINVAL;
6225 }
6226
05394f39 6227 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6228 if (&obj->base == NULL)
79e53945
JB		 6229 return -ENOENT;
6230
05394f39 6231 if (obj->base.size < width * height * 4) {
79e53945 6232 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6233 ret = -ENOMEM;
6234 goto fail;
79e53945
JB		 6235 }
6236
71acb5eb 6237 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6238 mutex_lock(&dev->struct_mutex);
b295d1b6 6239 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6240 unsigned alignment;
6241
d9e86c0e
CW		 6242 if (obj->tiling_mode) {
6243 DRM_ERROR("cursor cannot be tiled\n");
6244 ret = -EINVAL;
6245 goto fail_locked;
6246 }
6247
693db184
CW		 6248 /* Note that the w/a also requires 2 PTE of padding following
6249 * the bo. We currently fill all unused PTE with the shadow
6250 * page and so we should always have valid PTE following the
6251 * cursor preventing the VT-d warning.
6252 */
6253 alignment = 0;
6254 if (need_vtd_wa(dev))
6255 alignment = 64*1024;
6256
6257 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6258 if (ret) {
6259 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6260 goto fail_locked;
e7b526bb
CW		 6261 }
6262
d9e86c0e
CW		 6263 ret = i915_gem_object_put_fence(obj);
6264 if (ret) {
2da3b9b9 6265 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6266 goto fail_unpin;
6267 }
6268
05394f39 6269 addr = obj->gtt_offset;
71acb5eb 6270 } else {
6eeefaf3 6271 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6272 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6273 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6274 align);
71acb5eb
DA		 6275 if (ret) {
6276 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6277 goto fail_locked;
71acb5eb 6278 }
05394f39 6279 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6280 }
6281
a6c45cf0 6282 if (IS_GEN2(dev))
14b60391
JB		 6283 I915_WRITE(CURSIZE, (height << 12) | width);
6284
3f8bc370 6285 finish:
3f8bc370 6286 if (intel_crtc->cursor_bo) {
b295d1b6 6287 if (dev_priv->info->cursor_needs_physical) {
05394f39 6288 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6289 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6290 } else
6291 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6292 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6293 }
80824003 6294
7f9872e0 6295 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6296
6297 intel_crtc->cursor_addr = addr;
05394f39 6298 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6299 intel_crtc->cursor_width = width;
6300 intel_crtc->cursor_height = height;
6301
6b383a7f 6302 intel_crtc_update_cursor(crtc, true);
3f8bc370 6303
79e53945 6304 return 0;
e7b526bb 6305fail_unpin:
05394f39 6306 i915_gem_object_unpin(obj);
7f9872e0 6307fail_locked:
34b8686e 6308 mutex_unlock(&dev->struct_mutex);
bc9025bd 6309fail:
05394f39 6310 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6311 return ret;
79e53945
JB		 6312}
6313
6314static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6315{
79e53945 6316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6317
cda4b7d3
CW		 6318 intel_crtc->cursor_x = x;
6319 intel_crtc->cursor_y = y;
652c393a 6320
6b383a7f 6321 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6322
6323 return 0;
6324}
6325
6326/** Sets the color ramps on behalf of RandR */
6327void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6328 u16 blue, int regno)
6329{
6330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6331
6332 intel_crtc->lut_r[regno] = red >> 8;
6333 intel_crtc->lut_g[regno] = green >> 8;
6334 intel_crtc->lut_b[regno] = blue >> 8;
6335}
6336
b8c00ac5
DA		 6337void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6338 u16 *blue, int regno)
6339{
6340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6341
6342 *red = intel_crtc->lut_r[regno] << 8;
6343 *green = intel_crtc->lut_g[regno] << 8;
6344 *blue = intel_crtc->lut_b[regno] << 8;
6345}
6346
79e53945 6347static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6348 u16 *blue, uint32_t start, uint32_t size)
79e53945 6349{
7203425a 6350 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6352
7203425a 6353 for (i = start; i < end; i++) {
79e53945
JB		 6354 intel_crtc->lut_r[i] = red[i] >> 8;
6355 intel_crtc->lut_g[i] = green[i] >> 8;
6356 intel_crtc->lut_b[i] = blue[i] >> 8;
6357 }
6358
6359 intel_crtc_load_lut(crtc);
6360}
6361
79e53945
JB		 6362/* VESA 640x480x72Hz mode to set on the pipe */
6363static struct drm_display_mode load_detect_mode = {
6364 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6365 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6366};
6367
d2dff872
CW		 6368static struct drm_framebuffer *
6369intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6370 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6371 struct drm_i915_gem_object *obj)
6372{
6373 struct intel_framebuffer *intel_fb;
6374 int ret;
6375
6376 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6377 if (!intel_fb) {
6378 drm_gem_object_unreference_unlocked(&obj->base);
6379 return ERR_PTR(-ENOMEM);
6380 }
6381
6382 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6383 if (ret) {
6384 drm_gem_object_unreference_unlocked(&obj->base);
6385 kfree(intel_fb);
6386 return ERR_PTR(ret);
6387 }
6388
6389 return &intel_fb->base;
6390}
6391
6392static u32
6393intel_framebuffer_pitch_for_width(int width, int bpp)
6394{
6395 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6396 return ALIGN(pitch, 64);
6397}
6398
6399static u32
6400intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6401{
6402 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6403 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6404}
6405
6406static struct drm_framebuffer *
6407intel_framebuffer_create_for_mode(struct drm_device *dev,
6408 struct drm_display_mode *mode,
6409 int depth, int bpp)
6410{
6411 struct drm_i915_gem_object *obj;
0fed39bd 6412 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6413
6414 obj = i915_gem_alloc_object(dev,
6415 intel_framebuffer_size_for_mode(mode, bpp));
6416 if (obj == NULL)
6417 return ERR_PTR(-ENOMEM);
6418
6419 mode_cmd.width = mode->hdisplay;
6420 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6421 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6422 bpp);
5ca0c34a 6423 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6424
6425 return intel_framebuffer_create(dev, &mode_cmd, obj);
6426}
6427
6428static struct drm_framebuffer *
6429mode_fits_in_fbdev(struct drm_device *dev,
6430 struct drm_display_mode *mode)
6431{
6432 struct drm_i915_private *dev_priv = dev->dev_private;
6433 struct drm_i915_gem_object *obj;
6434 struct drm_framebuffer *fb;
6435
6436 if (dev_priv->fbdev == NULL)
6437 return NULL;
6438
6439 obj = dev_priv->fbdev->ifb.obj;
6440 if (obj == NULL)
6441 return NULL;
6442
6443 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6444 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6445 fb->bits_per_pixel))
d2dff872
CW		 6446 return NULL;
6447
01f2c773 6448 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6449 return NULL;
6450
6451 return fb;
6452}
6453
d2434ab7 6454bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6455 struct drm_display_mode *mode,
8261b191 6456 struct intel_load_detect_pipe *old)
79e53945
JB		 6457{
6458 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6459 struct intel_encoder *intel_encoder =
6460 intel_attached_encoder(connector);
79e53945 6461 struct drm_crtc *possible_crtc;
4ef69c7a 6462 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6463 struct drm_crtc *crtc = NULL;
6464 struct drm_device *dev = encoder->dev;
94352cf9 6465 struct drm_framebuffer *fb;
79e53945
JB		 6466 int i = -1;
6467
d2dff872
CW		 6468 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6469 connector->base.id, drm_get_connector_name(connector),
6470 encoder->base.id, drm_get_encoder_name(encoder));
6471
79e53945
JB		 6472 /*
6473 * Algorithm gets a little messy:
7a5e4805 6474 *
79e53945
JB		 6475 * - if the connector already has an assigned crtc, use it (but make
6476 * sure it's on first)
7a5e4805 6477 *
79e53945
JB		 6478 * - try to find the first unused crtc that can drive this connector,
6479 * and use that if we find one
79e53945
JB		 6480 */
6481
6482 /* See if we already have a CRTC for this connector */
6483 if (encoder->crtc) {
6484 crtc = encoder->crtc;
8261b191 6485
7b24056b
DV		 6486 mutex_lock(&crtc->mutex);
6487
24218aac 6488 old->dpms_mode = connector->dpms;
8261b191
CW		 6489 old->load_detect_temp = false;
6490
6491 /* Make sure the crtc and connector are running */
24218aac
DV		 6492 if (connector->dpms != DRM_MODE_DPMS_ON)
6493 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6494
7173188d 6495 return true;
79e53945
JB		 6496 }
6497
6498 /* Find an unused one (if possible) */
6499 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6500 i++;
6501 if (!(encoder->possible_crtcs & (1 << i)))
6502 continue;
6503 if (!possible_crtc->enabled) {
6504 crtc = possible_crtc;
6505 break;
6506 }
79e53945
JB		 6507 }
6508
6509 /*
6510 * If we didn't find an unused CRTC, don't use any.
6511 */
6512 if (!crtc) {
7173188d
CW		 6513 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6514 return false;
79e53945
JB		 6515 }
6516
7b24056b 6517 mutex_lock(&crtc->mutex);
fc303101
DV		 6518 intel_encoder->new_crtc = to_intel_crtc(crtc);
6519 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6520
6521 intel_crtc = to_intel_crtc(crtc);
24218aac 6522 old->dpms_mode = connector->dpms;
8261b191 6523 old->load_detect_temp = true;
d2dff872 6524 old->release_fb = NULL;
79e53945 6525
6492711d
CW		 6526 if (!mode)
6527 mode = &load_detect_mode;
79e53945 6528
d2dff872
CW		 6529 /* We need a framebuffer large enough to accommodate all accesses
6530 * that the plane may generate whilst we perform load detection.
6531 * We can not rely on the fbcon either being present (we get called
6532 * during its initialisation to detect all boot displays, or it may
6533 * not even exist) or that it is large enough to satisfy the
6534 * requested mode.
6535 */
94352cf9
DV		 6536 fb = mode_fits_in_fbdev(dev, mode);
6537 if (fb == NULL) {
d2dff872 6538 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6539 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6540 old->release_fb = fb;
d2dff872
CW		 6541 } else
6542 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6543 if (IS_ERR(fb)) {
d2dff872 6544 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6545 mutex_unlock(&crtc->mutex);
0e8b3d3e 6546 return false;
79e53945 6547 }
79e53945 6548
c0c36b94 6549 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6550 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6551 if (old->release_fb)
6552 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6553 mutex_unlock(&crtc->mutex);
0e8b3d3e 6554 return false;
79e53945 6555 }
7173188d 6556
79e53945 6557 /* let the connector get through one full cycle before testing */
9d0498a2 6558 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6559 return true;
79e53945
JB		 6560}
6561
d2434ab7 6562void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6563 struct intel_load_detect_pipe *old)
79e53945 6564{
d2434ab7
DV		 6565 struct intel_encoder *intel_encoder =
6566 intel_attached_encoder(connector);
4ef69c7a 6567 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6568 struct drm_crtc *crtc = encoder->crtc;
79e53945 6569
d2dff872
CW		 6570 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6571 connector->base.id, drm_get_connector_name(connector),
6572 encoder->base.id, drm_get_encoder_name(encoder));
6573
8261b191 6574 if (old->load_detect_temp) {
fc303101
DV		 6575 to_intel_connector(connector)->new_encoder = NULL;
6576 intel_encoder->new_crtc = NULL;
6577 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6578
36206361
DV		 6579 if (old->release_fb) {
6580 drm_framebuffer_unregister_private(old->release_fb);
6581 drm_framebuffer_unreference(old->release_fb);
6582 }
d2dff872 6583
67c96400 6584 mutex_unlock(&crtc->mutex);
0622a53c 6585 return;
79e53945
JB		 6586 }
6587
c751ce4f 6588 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6589 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6590 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6591
6592 mutex_unlock(&crtc->mutex);
79e53945
JB		 6593}
6594
6595/* Returns the clock of the currently programmed mode of the given pipe. */
6596static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6597{
6598 struct drm_i915_private *dev_priv = dev->dev_private;
6599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6600 int pipe = intel_crtc->pipe;
548f245b 6601 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6602 u32 fp;
6603 intel_clock_t clock;
6604
6605 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6606 fp = I915_READ(FP0(pipe));
79e53945 6607 else
39adb7a5 6608 fp = I915_READ(FP1(pipe));
79e53945
JB		 6609
6610 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6611 if (IS_PINEVIEW(dev)) {
6612 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6613 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6614 } else {
6615 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6616 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6617 }
6618
a6c45cf0 6619 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6620 if (IS_PINEVIEW(dev))
6621 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6622 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6623 else
6624 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6625 DPLL_FPA01_P1_POST_DIV_SHIFT);
6626
6627 switch (dpll & DPLL_MODE_MASK) {
6628 case DPLLB_MODE_DAC_SERIAL:
6629 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6630 5 : 10;
6631 break;
6632 case DPLLB_MODE_LVDS:
6633 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6634 7 : 14;
6635 break;
6636 default:
28c97730 6637 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6638 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6639 return 0;
6640 }
6641
6642 /* XXX: Handle the 100Mhz refclk */
2177832f 6643 intel_clock(dev, 96000, &clock);
79e53945
JB		 6644 } else {
6645 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6646
6647 if (is_lvds) {
6648 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6649 DPLL_FPA01_P1_POST_DIV_SHIFT);
6650 clock.p2 = 14;
6651
6652 if ((dpll & PLL_REF_INPUT_MASK) ==
6653 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6654 /* XXX: might not be 66MHz */
2177832f 6655 intel_clock(dev, 66000, &clock);
79e53945 6656 } else
2177832f 6657 intel_clock(dev, 48000, &clock);
79e53945
JB		 6658 } else {
6659 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6660 clock.p1 = 2;
6661 else {
6662 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6663 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6664 }
6665 if (dpll & PLL_P2_DIVIDE_BY_4)
6666 clock.p2 = 4;
6667 else
6668 clock.p2 = 2;
6669
2177832f 6670 intel_clock(dev, 48000, &clock);
79e53945
JB		 6671 }
6672 }
6673
6674 /* XXX: It would be nice to validate the clocks, but we can't reuse
6675 * i830PllIsValid() because it relies on the xf86_config connector
6676 * configuration being accurate, which it isn't necessarily.
6677 */
6678
6679 return clock.dot;
6680}
6681
6682/** Returns the currently programmed mode of the given pipe. */
6683struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6684 struct drm_crtc *crtc)
6685{
548f245b 6686 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6688 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6689 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6690 int htot = I915_READ(HTOTAL(cpu_transcoder));
6691 int hsync = I915_READ(HSYNC(cpu_transcoder));
6692 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6693 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6694
6695 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6696 if (!mode)
6697 return NULL;
6698
6699 mode->clock = intel_crtc_clock_get(dev, crtc);
6700 mode->hdisplay = (htot & 0xffff) + 1;
6701 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6702 mode->hsync_start = (hsync & 0xffff) + 1;
6703 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6704 mode->vdisplay = (vtot & 0xffff) + 1;
6705 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6706 mode->vsync_start = (vsync & 0xffff) + 1;
6707 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6708
6709 drm_mode_set_name(mode);
79e53945
JB		 6710
6711 return mode;
6712}
6713
3dec0095 6714static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6715{
6716 struct drm_device *dev = crtc->dev;
6717 drm_i915_private_t *dev_priv = dev->dev_private;
6718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6719 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6720 int dpll_reg = DPLL(pipe);
6721 int dpll;
652c393a 6722
bad720ff 6723 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6724 return;
6725
6726 if (!dev_priv->lvds_downclock_avail)
6727 return;
6728
dbdc6479 6729 dpll = I915_READ(dpll_reg);
652c393a 6730 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6731 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6732
8ac5a6d5 6733 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6734
6735 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6736 I915_WRITE(dpll_reg, dpll);
9d0498a2 6737 intel_wait_for_vblank(dev, pipe);
dbdc6479 6738
652c393a
JB		 6739 dpll = I915_READ(dpll_reg);
6740 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6741 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6742 }
652c393a
JB		 6743}
6744
6745static void intel_decrease_pllclock(struct drm_crtc *crtc)
6746{
6747 struct drm_device *dev = crtc->dev;
6748 drm_i915_private_t *dev_priv = dev->dev_private;
6749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6750
bad720ff 6751 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6752 return;
6753
6754 if (!dev_priv->lvds_downclock_avail)
6755 return;
6756
6757 /*
6758 * Since this is called by a timer, we should never get here in
6759 * the manual case.
6760 */
6761 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6762 int pipe = intel_crtc->pipe;
6763 int dpll_reg = DPLL(pipe);
6764 int dpll;
f6e5b160 6765
44d98a61 6766 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6767
8ac5a6d5 6768 assert_panel_unlocked(dev_priv, pipe);
652c393a 6769
dc257cf1 6770 dpll = I915_READ(dpll_reg);
652c393a
JB		 6771 dpll |= DISPLAY_RATE_SELECT_FPA1;
6772 I915_WRITE(dpll_reg, dpll);
9d0498a2 6773 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6774 dpll = I915_READ(dpll_reg);
6775 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6776 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6777 }
6778
6779}
6780
f047e395
CW		 6781void intel_mark_busy(struct drm_device *dev)
6782{
f047e395
CW		 6783 i915_update_gfx_val(dev->dev_private);
6784}
6785
6786void intel_mark_idle(struct drm_device *dev)
652c393a 6787{
652c393a 6788 struct drm_crtc *crtc;
652c393a
JB		 6789
6790 if (!i915_powersave)
6791 return;
6792
652c393a 6793 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6794 if (!crtc->fb)
6795 continue;
6796
725a5b54 6797 intel_decrease_pllclock(crtc);
652c393a 6798 }
652c393a
JB		 6799}
6800
725a5b54 6801void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6802{
f047e395
CW		 6803 struct drm_device *dev = obj->base.dev;
6804 struct drm_crtc *crtc;
652c393a 6805
f047e395 6806 if (!i915_powersave)
acb87dfb
CW		 6807 return;
6808
652c393a
JB		 6809 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6810 if (!crtc->fb)
6811 continue;
6812
f047e395 6813 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6814 intel_increase_pllclock(crtc);
652c393a
JB		 6815 }
6816}
6817
79e53945
JB		 6818static void intel_crtc_destroy(struct drm_crtc *crtc)
6819{
6820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6821 struct drm_device *dev = crtc->dev;
6822 struct intel_unpin_work *work;
6823 unsigned long flags;
6824
6825 spin_lock_irqsave(&dev->event_lock, flags);
6826 work = intel_crtc->unpin_work;
6827 intel_crtc->unpin_work = NULL;
6828 spin_unlock_irqrestore(&dev->event_lock, flags);
6829
6830 if (work) {
6831 cancel_work_sync(&work->work);
6832 kfree(work);
6833 }
79e53945
JB		 6834
6835 drm_crtc_cleanup(crtc);
67e77c5a 6836
79e53945
JB		 6837 kfree(intel_crtc);
6838}
6839
6b95a207
KH		 6840static void intel_unpin_work_fn(struct work_struct *__work)
6841{
6842 struct intel_unpin_work *work =
6843 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6844 struct drm_device *dev = work->crtc->dev;
6b95a207 6845
b4a98e57 6846 mutex_lock(&dev->struct_mutex);
1690e1eb 6847 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6848 drm_gem_object_unreference(&work->pending_flip_obj->base);
6849 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6850
b4a98e57
CW		 6851 intel_update_fbc(dev);
6852 mutex_unlock(&dev->struct_mutex);
6853
6854 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6855 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6856
6b95a207
KH		 6857 kfree(work);
6858}
6859
1afe3e9d 6860static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6861 struct drm_crtc *crtc)
6b95a207
KH		 6862{
6863 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6865 struct intel_unpin_work *work;
6b95a207
KH		 6866 unsigned long flags;
6867
6868 /* Ignore early vblank irqs */
6869 if (intel_crtc == NULL)
6870 return;
6871
6872 spin_lock_irqsave(&dev->event_lock, flags);
6873 work = intel_crtc->unpin_work;
e7d841ca
CW		 6874
6875 /* Ensure we don't miss a work->pending update ... */
6876 smp_rmb();
6877
6878 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 6879 spin_unlock_irqrestore(&dev->event_lock, flags);
6880 return;
6881 }
6882
e7d841ca
CW		 6883 /* and that the unpin work is consistent wrt ->pending. */
6884 smp_rmb();
6885
6b95a207 6886 intel_crtc->unpin_work = NULL;
6b95a207 6887
45a066eb
RC		 6888 if (work->event)
6889 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6890
0af7e4df
MK		 6891 drm_vblank_put(dev, intel_crtc->pipe);
6892
6b95a207
KH		 6893 spin_unlock_irqrestore(&dev->event_lock, flags);
6894
2c10d571 6895 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6896
6897 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6898
6899 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6900}
6901
1afe3e9d
JB		 6902void intel_finish_page_flip(struct drm_device *dev, int pipe)
6903{
6904 drm_i915_private_t *dev_priv = dev->dev_private;
6905 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6906
49b14a5c 6907 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6908}
6909
6910void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6911{
6912 drm_i915_private_t *dev_priv = dev->dev_private;
6913 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6914
49b14a5c 6915 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6916}
6917
6b95a207
KH		 6918void intel_prepare_page_flip(struct drm_device *dev, int plane)
6919{
6920 drm_i915_private_t *dev_priv = dev->dev_private;
6921 struct intel_crtc *intel_crtc =
6922 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6923 unsigned long flags;
6924
e7d841ca
CW		 6925 /* NB: An MMIO update of the plane base pointer will also
6926 * generate a page-flip completion irq, i.e. every modeset
6927 * is also accompanied by a spurious intel_prepare_page_flip().
6928 */
6b95a207 6929 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 6930 if (intel_crtc->unpin_work)
6931 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 6932 spin_unlock_irqrestore(&dev->event_lock, flags);
6933}
6934
e7d841ca
CW		 6935inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
6936{
6937 /* Ensure that the work item is consistent when activating it ... */
6938 smp_wmb();
6939 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
6940 /* and that it is marked active as soon as the irq could fire. */
6941 smp_wmb();
6942}
6943
8c9f3aaf
JB		 6944static int intel_gen2_queue_flip(struct drm_device *dev,
6945 struct drm_crtc *crtc,
6946 struct drm_framebuffer *fb,
6947 struct drm_i915_gem_object *obj)
6948{
6949 struct drm_i915_private *dev_priv = dev->dev_private;
6950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6951 u32 flip_mask;
6d90c952 6952 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6953 int ret;
6954
6d90c952 6955 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6956 if (ret)
83d4092b 6957 goto err;
8c9f3aaf 6958
6d90c952 6959 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6960 if (ret)
83d4092b 6961 goto err_unpin;
8c9f3aaf
JB		 6962
6963 /* Can't queue multiple flips, so wait for the previous
6964 * one to finish before executing the next.
6965 */
6966 if (intel_crtc->plane)
6967 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6968 else
6969 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6970 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6971 intel_ring_emit(ring, MI_NOOP);
6972 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6973 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6974 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6975 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 6976 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 6977
6978 intel_mark_page_flip_active(intel_crtc);
6d90c952 6979 intel_ring_advance(ring);
83d4092b
CW		 6980 return 0;
6981
6982err_unpin:
6983 intel_unpin_fb_obj(obj);
6984err:
8c9f3aaf
JB		 6985 return ret;
6986}
6987
6988static int intel_gen3_queue_flip(struct drm_device *dev,
6989 struct drm_crtc *crtc,
6990 struct drm_framebuffer *fb,
6991 struct drm_i915_gem_object *obj)
6992{
6993 struct drm_i915_private *dev_priv = dev->dev_private;
6994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6995 u32 flip_mask;
6d90c952 6996 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6997 int ret;
6998
6d90c952 6999 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7000 if (ret)
83d4092b 7001 goto err;
8c9f3aaf 7002
6d90c952 7003 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7004 if (ret)
83d4092b 7005 goto err_unpin;
8c9f3aaf
JB		 7006
7007 if (intel_crtc->plane)
7008 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7009 else
7010 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7011 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7012 intel_ring_emit(ring, MI_NOOP);
7013 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7014 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7015 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7016 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7017 intel_ring_emit(ring, MI_NOOP);
7018
e7d841ca 7019 intel_mark_page_flip_active(intel_crtc);
6d90c952 7020 intel_ring_advance(ring);
83d4092b
CW		 7021 return 0;
7022
7023err_unpin:
7024 intel_unpin_fb_obj(obj);
7025err:
8c9f3aaf
JB		 7026 return ret;
7027}
7028
7029static int intel_gen4_queue_flip(struct drm_device *dev,
7030 struct drm_crtc *crtc,
7031 struct drm_framebuffer *fb,
7032 struct drm_i915_gem_object *obj)
7033{
7034 struct drm_i915_private *dev_priv = dev->dev_private;
7035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7036 uint32_t pf, pipesrc;
6d90c952 7037 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7038 int ret;
7039
6d90c952 7040 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7041 if (ret)
83d4092b 7042 goto err;
8c9f3aaf 7043
6d90c952 7044 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7045 if (ret)
83d4092b 7046 goto err_unpin;
8c9f3aaf
JB		 7047
7048 /* i965+ uses the linear or tiled offsets from the
7049 * Display Registers (which do not change across a page-flip)
7050 * so we need only reprogram the base address.
7051 */
6d90c952
DV		 7052 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7053 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7054 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7055 intel_ring_emit(ring,
7056 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7057 obj->tiling_mode);
8c9f3aaf
JB		 7058
7059 /* XXX Enabling the panel-fitter across page-flip is so far
7060 * untested on non-native modes, so ignore it for now.
7061 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7062 */
7063 pf = 0;
7064 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7065 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7066
7067 intel_mark_page_flip_active(intel_crtc);
6d90c952 7068 intel_ring_advance(ring);
83d4092b
CW		 7069 return 0;
7070
7071err_unpin:
7072 intel_unpin_fb_obj(obj);
7073err:
8c9f3aaf
JB		 7074 return ret;
7075}
7076
7077static int intel_gen6_queue_flip(struct drm_device *dev,
7078 struct drm_crtc *crtc,
7079 struct drm_framebuffer *fb,
7080 struct drm_i915_gem_object *obj)
7081{
7082 struct drm_i915_private *dev_priv = dev->dev_private;
7083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7084 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7085 uint32_t pf, pipesrc;
7086 int ret;
7087
6d90c952 7088 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7089 if (ret)
83d4092b 7090 goto err;
8c9f3aaf 7091
6d90c952 7092 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7093 if (ret)
83d4092b 7094 goto err_unpin;
8c9f3aaf 7095
6d90c952
DV		 7096 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7097 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7098 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7099 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7100
dc257cf1
DV		 7101 /* Contrary to the suggestions in the documentation,
7102 * "Enable Panel Fitter" does not seem to be required when page
7103 * flipping with a non-native mode, and worse causes a normal
7104 * modeset to fail.
7105 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7106 */
7107 pf = 0;
8c9f3aaf 7108 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7109 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7110
7111 intel_mark_page_flip_active(intel_crtc);
6d90c952 7112 intel_ring_advance(ring);
83d4092b
CW		 7113 return 0;
7114
7115err_unpin:
7116 intel_unpin_fb_obj(obj);
7117err:
8c9f3aaf
JB		 7118 return ret;
7119}
7120
7c9017e5
JB		 7121/*
7122 * On gen7 we currently use the blit ring because (in early silicon at least)
7123 * the render ring doesn't give us interrpts for page flip completion, which
7124 * means clients will hang after the first flip is queued. Fortunately the
7125 * blit ring generates interrupts properly, so use it instead.
7126 */
7127static int intel_gen7_queue_flip(struct drm_device *dev,
7128 struct drm_crtc *crtc,
7129 struct drm_framebuffer *fb,
7130 struct drm_i915_gem_object *obj)
7131{
7132 struct drm_i915_private *dev_priv = dev->dev_private;
7133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7134 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7135 uint32_t plane_bit = 0;
7c9017e5
JB		 7136 int ret;
7137
7138 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7139 if (ret)
83d4092b 7140 goto err;
7c9017e5 7141
cb05d8de
DV		 7142 switch(intel_crtc->plane) {
7143 case PLANE_A:
7144 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7145 break;
7146 case PLANE_B:
7147 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7148 break;
7149 case PLANE_C:
7150 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7151 break;
7152 default:
7153 WARN_ONCE(1, "unknown plane in flip command\n");
7154 ret = -ENODEV;
ab3951eb 7155 goto err_unpin;
cb05d8de
DV		 7156 }
7157
7c9017e5
JB		 7158 ret = intel_ring_begin(ring, 4);
7159 if (ret)
83d4092b 7160 goto err_unpin;
7c9017e5 7161
cb05d8de 7162 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7163 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7164 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7165 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7166
7167 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7168 intel_ring_advance(ring);
83d4092b
CW		 7169 return 0;
7170
7171err_unpin:
7172 intel_unpin_fb_obj(obj);
7173err:
7c9017e5
JB		 7174 return ret;
7175}
7176
8c9f3aaf
JB		 7177static int intel_default_queue_flip(struct drm_device *dev,
7178 struct drm_crtc *crtc,
7179 struct drm_framebuffer *fb,
7180 struct drm_i915_gem_object *obj)
7181{
7182 return -ENODEV;
7183}
7184
6b95a207
KH		 7185static int intel_crtc_page_flip(struct drm_crtc *crtc,
7186 struct drm_framebuffer *fb,
7187 struct drm_pending_vblank_event *event)
7188{
7189 struct drm_device *dev = crtc->dev;
7190 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7191 struct drm_framebuffer *old_fb = crtc->fb;
7192 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7194 struct intel_unpin_work *work;
8c9f3aaf 7195 unsigned long flags;
52e68630 7196 int ret;
6b95a207 7197
e6a595d2
VS		 7198 /* Can't change pixel format via MI display flips. */
7199 if (fb->pixel_format != crtc->fb->pixel_format)
7200 return -EINVAL;
7201
7202 /*
7203 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7204 * Note that pitch changes could also affect these register.
7205 */
7206 if (INTEL_INFO(dev)->gen > 3 &&
7207 (fb->offsets[0] != crtc->fb->offsets[0] ||
7208 fb->pitches[0] != crtc->fb->pitches[0]))
7209 return -EINVAL;
7210
6b95a207
KH		 7211 work = kzalloc(sizeof *work, GFP_KERNEL);
7212 if (work == NULL)
7213 return -ENOMEM;
7214
6b95a207 7215 work->event = event;
b4a98e57 7216 work->crtc = crtc;
4a35f83b 7217 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7218 INIT_WORK(&work->work, intel_unpin_work_fn);
7219
7317c75e
JB		 7220 ret = drm_vblank_get(dev, intel_crtc->pipe);
7221 if (ret)
7222 goto free_work;
7223
6b95a207
KH		 7224 /* We borrow the event spin lock for protecting unpin_work */
7225 spin_lock_irqsave(&dev->event_lock, flags);
7226 if (intel_crtc->unpin_work) {
7227 spin_unlock_irqrestore(&dev->event_lock, flags);
7228 kfree(work);
7317c75e 7229 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7230
7231 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7232 return -EBUSY;
7233 }
7234 intel_crtc->unpin_work = work;
7235 spin_unlock_irqrestore(&dev->event_lock, flags);
7236
b4a98e57
CW		 7237 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7238 flush_workqueue(dev_priv->wq);
7239
79158103
CW		 7240 ret = i915_mutex_lock_interruptible(dev);
7241 if (ret)
7242 goto cleanup;
6b95a207 7243
75dfca80 7244 /* Reference the objects for the scheduled work. */
05394f39
CW		 7245 drm_gem_object_reference(&work->old_fb_obj->base);
7246 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7247
7248 crtc->fb = fb;
96b099fd 7249
e1f99ce6 7250 work->pending_flip_obj = obj;
e1f99ce6 7251
4e5359cd
SF		 7252 work->enable_stall_check = true;
7253
b4a98e57 7254 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7255 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7256
8c9f3aaf
JB		 7257 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7258 if (ret)
7259 goto cleanup_pending;
6b95a207 7260
7782de3b 7261 intel_disable_fbc(dev);
f047e395 7262 intel_mark_fb_busy(obj);
6b95a207
KH		 7263 mutex_unlock(&dev->struct_mutex);
7264
e5510fac
JB		 7265 trace_i915_flip_request(intel_crtc->plane, obj);
7266
6b95a207 7267 return 0;
96b099fd 7268
8c9f3aaf 7269cleanup_pending:
b4a98e57 7270 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7271 crtc->fb = old_fb;
05394f39
CW		 7272 drm_gem_object_unreference(&work->old_fb_obj->base);
7273 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7274 mutex_unlock(&dev->struct_mutex);
7275
79158103 7276cleanup:
96b099fd
CW		 7277 spin_lock_irqsave(&dev->event_lock, flags);
7278 intel_crtc->unpin_work = NULL;
7279 spin_unlock_irqrestore(&dev->event_lock, flags);
7280
7317c75e
JB		 7281 drm_vblank_put(dev, intel_crtc->pipe);
7282free_work:
96b099fd
CW		 7283 kfree(work);
7284
7285 return ret;
6b95a207
KH		 7286}
7287
f6e5b160 7288static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7289 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7290 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7291};
7292
6ed0f796 7293bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7294{
6ed0f796
DV		 7295 struct intel_encoder *other_encoder;
7296 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7297
6ed0f796
DV		 7298 if (WARN_ON(!crtc))
7299 return false;
7300
7301 list_for_each_entry(other_encoder,
7302 &crtc->dev->mode_config.encoder_list,
7303 base.head) {
7304
7305 if (&other_encoder->new_crtc->base != crtc ||
7306 encoder == other_encoder)
7307 continue;
7308 else
7309 return true;
f47166d2
CW		 7310 }
7311
6ed0f796
DV		 7312 return false;
7313}
47f1c6c9 7314
50f56119
DV		 7315static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7316 struct drm_crtc *crtc)
7317{
7318 struct drm_device *dev;
7319 struct drm_crtc *tmp;
7320 int crtc_mask = 1;
47f1c6c9 7321
50f56119 7322 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7323
50f56119 7324 dev = crtc->dev;
47f1c6c9 7325
50f56119
DV		 7326 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7327 if (tmp == crtc)
7328 break;
7329 crtc_mask <<= 1;
7330 }
47f1c6c9 7331
50f56119
DV		 7332 if (encoder->possible_crtcs & crtc_mask)
7333 return true;
7334 return false;
47f1c6c9 7335}
79e53945 7336
9a935856
DV		 7337/**
7338 * intel_modeset_update_staged_output_state
7339 *
7340 * Updates the staged output configuration state, e.g. after we've read out the
7341 * current hw state.
7342 */
7343static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7344{
9a935856
DV		 7345 struct intel_encoder *encoder;
7346 struct intel_connector *connector;
f6e5b160 7347
9a935856
DV		 7348 list_for_each_entry(connector, &dev->mode_config.connector_list,
7349 base.head) {
7350 connector->new_encoder =
7351 to_intel_encoder(connector->base.encoder);
7352 }
f6e5b160 7353
9a935856
DV		 7354 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7355 base.head) {
7356 encoder->new_crtc =
7357 to_intel_crtc(encoder->base.crtc);
7358 }
f6e5b160
CW		 7359}
7360
9a935856
DV		 7361/**
7362 * intel_modeset_commit_output_state
7363 *
7364 * This function copies the stage display pipe configuration to the real one.
7365 */
7366static void intel_modeset_commit_output_state(struct drm_device *dev)
7367{
7368 struct intel_encoder *encoder;
7369 struct intel_connector *connector;
f6e5b160 7370
9a935856
DV		 7371 list_for_each_entry(connector, &dev->mode_config.connector_list,
7372 base.head) {
7373 connector->base.encoder = &connector->new_encoder->base;
7374 }
f6e5b160 7375
9a935856
DV		 7376 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7377 base.head) {
7378 encoder->base.crtc = &encoder->new_crtc->base;
7379 }
7380}
7381
4e53c2e0
DV		 7382static int
7383pipe_config_set_bpp(struct drm_crtc *crtc,
7384 struct drm_framebuffer *fb,
7385 struct intel_crtc_config *pipe_config)
7386{
7387 struct drm_device *dev = crtc->dev;
7388 struct drm_connector *connector;
7389 int bpp;
7390
7391 switch (fb->depth) {
7392 case 8:
7393 bpp = 8*3; /* since we go through a colormap */
7394 break;
7395 case 15:
7396 case 16:
7397 bpp = 6*3; /* min is 18bpp */
7398 break;
7399 case 24:
7400 bpp = 8*3;
7401 break;
7402 case 30:
7403 bpp = 10*3;
7404 break;
7405 case 48:
7406 bpp = 12*3;
7407 break;
7408 default:
7409 DRM_DEBUG_KMS("unsupported depth\n");
7410 return -EINVAL;
7411 }
7412
7413 if (fb->depth > 24 && !HAS_PCH_SPLIT(dev)) {
7414 DRM_DEBUG_KMS("high depth not supported on gmch platforms\n");
7415 return -EINVAL;
7416 }
7417
7418 pipe_config->pipe_bpp = bpp;
7419
7420 /* Clamp display bpp to EDID value */
7421 list_for_each_entry(connector, &dev->mode_config.connector_list,
7422 head) {
7423 if (connector->encoder && connector->encoder->crtc != crtc)
7424 continue;
7425
7426 /* Don't use an invalid EDID bpc value */
7427 if (connector->display_info.bpc &&
7428 connector->display_info.bpc * 3 < bpp) {
7429 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7430 bpp, connector->display_info.bpc*3);
7431 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7432 }
7433 }
7434
7435 return bpp;
7436}
7437
b8cecdf5
DV		 7438static struct intel_crtc_config *
7439intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7440 struct drm_framebuffer *fb,
b8cecdf5 7441 struct drm_display_mode *mode)
ee7b9f93 7442{
7758a113 7443 struct drm_device *dev = crtc->dev;
7758a113
DV		 7444 struct drm_encoder_helper_funcs *encoder_funcs;
7445 struct intel_encoder *encoder;
b8cecdf5 7446 struct intel_crtc_config *pipe_config;
4e53c2e0 7447 int plane_bpp;
ee7b9f93 7448
b8cecdf5
DV		 7449 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7450 if (!pipe_config)
7758a113
DV		 7451 return ERR_PTR(-ENOMEM);
7452
b8cecdf5
DV		 7453 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7454 drm_mode_copy(&pipe_config->requested_mode, mode);
7455
4e53c2e0
DV		 7456 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7457 if (plane_bpp < 0)
7458 goto fail;
7459
7758a113
DV		 7460 /* Pass our mode to the connectors and the CRTC to give them a chance to
7461 * adjust it according to limitations or connector properties, and also
7462 * a chance to reject the mode entirely.
47f1c6c9 7463 */
7758a113
DV		 7464 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7465 base.head) {
47f1c6c9 7466
7758a113
DV		 7467 if (&encoder->new_crtc->base != crtc)
7468 continue;
7ae89233
DV		 7469
7470 if (encoder->compute_config) {
7471 if (!(encoder->compute_config(encoder, pipe_config))) {
7472 DRM_DEBUG_KMS("Encoder config failure\n");
7473 goto fail;
7474 }
7475
7476 continue;
7477 }
7478
7758a113 7479 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7480 if (!(encoder_funcs->mode_fixup(&encoder->base,
7481 &pipe_config->requested_mode,
7482 &pipe_config->adjusted_mode))) {
7758a113
DV		 7483 DRM_DEBUG_KMS("Encoder fixup failed\n");
7484 goto fail;
7485 }
ee7b9f93 7486 }
47f1c6c9 7487
b8cecdf5 7488 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7758a113
DV		 7489 DRM_DEBUG_KMS("CRTC fixup failed\n");
7490 goto fail;
ee7b9f93 7491 }
7758a113 7492 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7493
4e53c2e0
DV		 7494 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7495 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7496 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7497
b8cecdf5 7498 return pipe_config;
7758a113 7499fail:
b8cecdf5 7500 kfree(pipe_config);
7758a113 7501 return ERR_PTR(-EINVAL);
ee7b9f93 7502}
47f1c6c9 7503
e2e1ed41
DV		 7504/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7505 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7506static void
7507intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7508 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7509{
7510 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7511 struct drm_device *dev = crtc->dev;
7512 struct intel_encoder *encoder;
7513 struct intel_connector *connector;
7514 struct drm_crtc *tmp_crtc;
79e53945 7515
e2e1ed41 7516 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7517
e2e1ed41
DV		 7518 /* Check which crtcs have changed outputs connected to them, these need
7519 * to be part of the prepare_pipes mask. We don't (yet) support global
7520 * modeset across multiple crtcs, so modeset_pipes will only have one
7521 * bit set at most. */
7522 list_for_each_entry(connector, &dev->mode_config.connector_list,
7523 base.head) {
7524 if (connector->base.encoder == &connector->new_encoder->base)
7525 continue;
79e53945 7526
e2e1ed41
DV		 7527 if (connector->base.encoder) {
7528 tmp_crtc = connector->base.encoder->crtc;
7529
7530 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7531 }
7532
7533 if (connector->new_encoder)
7534 *prepare_pipes |=
7535 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7536 }
7537
e2e1ed41
DV		 7538 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7539 base.head) {
7540 if (encoder->base.crtc == &encoder->new_crtc->base)
7541 continue;
7542
7543 if (encoder->base.crtc) {
7544 tmp_crtc = encoder->base.crtc;
7545
7546 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7547 }
7548
7549 if (encoder->new_crtc)
7550 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7551 }
7552
e2e1ed41
DV		 7553 /* Check for any pipes that will be fully disabled ... */
7554 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7555 base.head) {
7556 bool used = false;
22fd0fab 7557
e2e1ed41
DV		 7558 /* Don't try to disable disabled crtcs. */
7559 if (!intel_crtc->base.enabled)
7560 continue;
7e7d76c3 7561
e2e1ed41
DV		 7562 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7563 base.head) {
7564 if (encoder->new_crtc == intel_crtc)
7565 used = true;
7566 }
7567
7568 if (!used)
7569 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7570 }
7571
e2e1ed41
DV		 7572
7573 /* set_mode is also used to update properties on life display pipes. */
7574 intel_crtc = to_intel_crtc(crtc);
7575 if (crtc->enabled)
7576 *prepare_pipes |= 1 << intel_crtc->pipe;
7577
7578 /* We only support modeset on one single crtc, hence we need to do that
7579 * only for the passed in crtc iff we change anything else than just
7580 * disable crtcs.
7581 *
7582 * This is actually not true, to be fully compatible with the old crtc
7583 * helper we automatically disable _any_ output (i.e. doesn't need to be
7584 * connected to the crtc we're modesetting on) if it's disconnected.
7585 * Which is a rather nutty api (since changed the output configuration
7586 * without userspace's explicit request can lead to confusion), but
7587 * alas. Hence we currently need to modeset on all pipes we prepare. */
7588 if (*prepare_pipes)
7589 *modeset_pipes = *prepare_pipes;
7590
7591 /* ... and mask these out. */
7592 *modeset_pipes &= ~(*disable_pipes);
7593 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7594}
79e53945 7595
ea9d758d 7596static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7597{
ea9d758d 7598 struct drm_encoder *encoder;
f6e5b160 7599 struct drm_device *dev = crtc->dev;
f6e5b160 7600
ea9d758d
DV		 7601 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7602 if (encoder->crtc == crtc)
7603 return true;
7604
7605 return false;
7606}
7607
7608static void
7609intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7610{
7611 struct intel_encoder *intel_encoder;
7612 struct intel_crtc *intel_crtc;
7613 struct drm_connector *connector;
7614
7615 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7616 base.head) {
7617 if (!intel_encoder->base.crtc)
7618 continue;
7619
7620 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7621
7622 if (prepare_pipes & (1 << intel_crtc->pipe))
7623 intel_encoder->connectors_active = false;
7624 }
7625
7626 intel_modeset_commit_output_state(dev);
7627
7628 /* Update computed state. */
7629 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7630 base.head) {
7631 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7632 }
7633
7634 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7635 if (!connector->encoder || !connector->encoder->crtc)
7636 continue;
7637
7638 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7639
7640 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7641 struct drm_property *dpms_property =
7642 dev->mode_config.dpms_property;
7643
ea9d758d 7644 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7645 drm_object_property_set_value(&connector->base,
68d34720
DV		 7646 dpms_property,
7647 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7648
7649 intel_encoder = to_intel_encoder(connector->encoder);
7650 intel_encoder->connectors_active = true;
7651 }
7652 }
7653
7654}
7655
25c5b266
DV		 7656#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7657 list_for_each_entry((intel_crtc), \
7658 &(dev)->mode_config.crtc_list, \
7659 base.head) \
7660 if (mask & (1 <<(intel_crtc)->pipe)) \
7661
b980514c 7662void
8af6cf88
DV		 7663intel_modeset_check_state(struct drm_device *dev)
7664{
7665 struct intel_crtc *crtc;
7666 struct intel_encoder *encoder;
7667 struct intel_connector *connector;
7668
7669 list_for_each_entry(connector, &dev->mode_config.connector_list,
7670 base.head) {
7671 /* This also checks the encoder/connector hw state with the
7672 * ->get_hw_state callbacks. */
7673 intel_connector_check_state(connector);
7674
7675 WARN(&connector->new_encoder->base != connector->base.encoder,
7676 "connector's staged encoder doesn't match current encoder\n");
7677 }
7678
7679 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7680 base.head) {
7681 bool enabled = false;
7682 bool active = false;
7683 enum pipe pipe, tracked_pipe;
7684
7685 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7686 encoder->base.base.id,
7687 drm_get_encoder_name(&encoder->base));
7688
7689 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7690 "encoder's stage crtc doesn't match current crtc\n");
7691 WARN(encoder->connectors_active && !encoder->base.crtc,
7692 "encoder's active_connectors set, but no crtc\n");
7693
7694 list_for_each_entry(connector, &dev->mode_config.connector_list,
7695 base.head) {
7696 if (connector->base.encoder != &encoder->base)
7697 continue;
7698 enabled = true;
7699 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7700 active = true;
7701 }
7702 WARN(!!encoder->base.crtc != enabled,
7703 "encoder's enabled state mismatch "
7704 "(expected %i, found %i)\n",
7705 !!encoder->base.crtc, enabled);
7706 WARN(active && !encoder->base.crtc,
7707 "active encoder with no crtc\n");
7708
7709 WARN(encoder->connectors_active != active,
7710 "encoder's computed active state doesn't match tracked active state "
7711 "(expected %i, found %i)\n", active, encoder->connectors_active);
7712
7713 active = encoder->get_hw_state(encoder, &pipe);
7714 WARN(active != encoder->connectors_active,
7715 "encoder's hw state doesn't match sw tracking "
7716 "(expected %i, found %i)\n",
7717 encoder->connectors_active, active);
7718
7719 if (!encoder->base.crtc)
7720 continue;
7721
7722 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7723 WARN(active && pipe != tracked_pipe,
7724 "active encoder's pipe doesn't match"
7725 "(expected %i, found %i)\n",
7726 tracked_pipe, pipe);
7727
7728 }
7729
7730 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7731 base.head) {
7732 bool enabled = false;
7733 bool active = false;
7734
7735 DRM_DEBUG_KMS("[CRTC:%d]\n",
7736 crtc->base.base.id);
7737
7738 WARN(crtc->active && !crtc->base.enabled,
7739 "active crtc, but not enabled in sw tracking\n");
7740
7741 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7742 base.head) {
7743 if (encoder->base.crtc != &crtc->base)
7744 continue;
7745 enabled = true;
7746 if (encoder->connectors_active)
7747 active = true;
7748 }
7749 WARN(active != crtc->active,
7750 "crtc's computed active state doesn't match tracked active state "
7751 "(expected %i, found %i)\n", active, crtc->active);
7752 WARN(enabled != crtc->base.enabled,
7753 "crtc's computed enabled state doesn't match tracked enabled state "
7754 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7755
7756 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7757 }
7758}
7759
c0c36b94
CW		 7760int intel_set_mode(struct drm_crtc *crtc,
7761 struct drm_display_mode *mode,
7762 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7763{
7764 struct drm_device *dev = crtc->dev;
dbf2b54e 7765 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 7766 struct drm_display_mode *saved_mode, *saved_hwmode;
7767 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 7768 struct intel_crtc *intel_crtc;
7769 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7770 int ret = 0;
a6778b3c 7771
3ac18232 7772 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7773 if (!saved_mode)
7774 return -ENOMEM;
3ac18232 7775 saved_hwmode = saved_mode + 1;
a6778b3c 7776
e2e1ed41 7777 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7778 &prepare_pipes, &disable_pipes);
7779
3ac18232
TG		 7780 *saved_hwmode = crtc->hwmode;
7781 *saved_mode = crtc->mode;
a6778b3c 7782
25c5b266
DV		 7783 /* Hack: Because we don't (yet) support global modeset on multiple
7784 * crtcs, we don't keep track of the new mode for more than one crtc.
7785 * Hence simply check whether any bit is set in modeset_pipes in all the
7786 * pieces of code that are not yet converted to deal with mutliple crtcs
7787 * changing their mode at the same time. */
25c5b266 7788 if (modeset_pipes) {
4e53c2e0 7789 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 7790 if (IS_ERR(pipe_config)) {
7791 ret = PTR_ERR(pipe_config);
7792 pipe_config = NULL;
7793
3ac18232 7794 goto out;
25c5b266 7795 }
25c5b266 7796 }
a6778b3c 7797
460da916
DV		 7798 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7799 modeset_pipes, prepare_pipes, disable_pipes);
7800
7801 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7802 intel_crtc_disable(&intel_crtc->base);
7803
ea9d758d
DV		 7804 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7805 if (intel_crtc->base.enabled)
7806 dev_priv->display.crtc_disable(&intel_crtc->base);
7807 }
a6778b3c 7808
6c4c86f5
DV		 7809 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7810 * to set it here already despite that we pass it down the callchain.
f6e5b160 7811 */
b8cecdf5 7812 if (modeset_pipes) {
25c5b266 7813 crtc->mode = *mode;
b8cecdf5
DV		 7814 /* mode_set/enable/disable functions rely on a correct pipe
7815 * config. */
7816 to_intel_crtc(crtc)->config = *pipe_config;
7817 }
7758a113 7818
ea9d758d
DV		 7819 /* Only after disabling all output pipelines that will be changed can we
7820 * update the the output configuration. */
7821 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7822
47fab737
DV		 7823 if (dev_priv->display.modeset_global_resources)
7824 dev_priv->display.modeset_global_resources(dev);
7825
a6778b3c
DV		 7826 /* Set up the DPLL and any encoders state that needs to adjust or depend
7827 * on the DPLL.
f6e5b160 7828 */
25c5b266 7829 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 7830 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 7831 x, y, fb);
7832 if (ret)
7833 goto done;
a6778b3c
DV		 7834 }
7835
7836 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7837 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7838 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7839
25c5b266
DV		 7840 if (modeset_pipes) {
7841 /* Store real post-adjustment hardware mode. */
b8cecdf5 7842 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 7843
25c5b266
DV		 7844 /* Calculate and store various constants which
7845 * are later needed by vblank and swap-completion
7846 * timestamping. They are derived from true hwmode.
7847 */
7848 drm_calc_timestamping_constants(crtc);
7849 }
a6778b3c
DV		 7850
7851 /* FIXME: add subpixel order */
7852done:
c0c36b94 7853 if (ret && crtc->enabled) {
3ac18232
TG		 7854 crtc->hwmode = *saved_hwmode;
7855 crtc->mode = *saved_mode;
8af6cf88
DV		 7856 } else {
7857 intel_modeset_check_state(dev);
a6778b3c
DV		 7858 }
7859
3ac18232 7860out:
b8cecdf5 7861 kfree(pipe_config);
3ac18232 7862 kfree(saved_mode);
a6778b3c 7863 return ret;
f6e5b160
CW		 7864}
7865
c0c36b94
CW		 7866void intel_crtc_restore_mode(struct drm_crtc *crtc)
7867{
7868 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7869}
7870
25c5b266
DV		 7871#undef for_each_intel_crtc_masked
7872
d9e55608
DV		 7873static void intel_set_config_free(struct intel_set_config *config)
7874{
7875 if (!config)
7876 return;
7877
1aa4b628
DV		 7878 kfree(config->save_connector_encoders);
7879 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7880 kfree(config);
7881}
7882
85f9eb71
DV		 7883static int intel_set_config_save_state(struct drm_device *dev,
7884 struct intel_set_config *config)
7885{
85f9eb71
DV		 7886 struct drm_encoder *encoder;
7887 struct drm_connector *connector;
7888 int count;
7889
1aa4b628
DV		 7890 config->save_encoder_crtcs =
7891 kcalloc(dev->mode_config.num_encoder,
7892 sizeof(struct drm_crtc *), GFP_KERNEL);
7893 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7894 return -ENOMEM;
7895
1aa4b628
DV		 7896 config->save_connector_encoders =
7897 kcalloc(dev->mode_config.num_connector,
7898 sizeof(struct drm_encoder *), GFP_KERNEL);
7899 if (!config->save_connector_encoders)
85f9eb71
DV		 7900 return -ENOMEM;
7901
7902 /* Copy data. Note that driver private data is not affected.
7903 * Should anything bad happen only the expected state is
7904 * restored, not the drivers personal bookkeeping.
7905 */
85f9eb71
DV		 7906 count = 0;
7907 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7908 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7909 }
7910
7911 count = 0;
7912 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7913 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7914 }
7915
7916 return 0;
7917}
7918
7919static void intel_set_config_restore_state(struct drm_device *dev,
7920 struct intel_set_config *config)
7921{
9a935856
DV		 7922 struct intel_encoder *encoder;
7923 struct intel_connector *connector;
85f9eb71
DV		 7924 int count;
7925
85f9eb71 7926 count = 0;
9a935856
DV		 7927 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7928 encoder->new_crtc =
7929 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7930 }
7931
7932 count = 0;
9a935856
DV		 7933 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7934 connector->new_encoder =
7935 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7936 }
7937}
7938
5e2b584e
DV		 7939static void
7940intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7941 struct intel_set_config *config)
7942{
7943
7944 /* We should be able to check here if the fb has the same properties
7945 * and then just flip_or_move it */
7946 if (set->crtc->fb != set->fb) {
7947 /* If we have no fb then treat it as a full mode set */
7948 if (set->crtc->fb == NULL) {
7949 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7950 config->mode_changed = true;
7951 } else if (set->fb == NULL) {
7952 config->mode_changed = true;
7953 } else if (set->fb->depth != set->crtc->fb->depth) {
7954 config->mode_changed = true;
7955 } else if (set->fb->bits_per_pixel !=
7956 set->crtc->fb->bits_per_pixel) {
7957 config->mode_changed = true;
7958 } else
7959 config->fb_changed = true;
7960 }
7961
835c5873 7962 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7963 config->fb_changed = true;
7964
7965 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7966 DRM_DEBUG_KMS("modes are different, full mode set\n");
7967 drm_mode_debug_printmodeline(&set->crtc->mode);
7968 drm_mode_debug_printmodeline(set->mode);
7969 config->mode_changed = true;
7970 }
7971}
7972
2e431051 7973static int
9a935856
DV		 7974intel_modeset_stage_output_state(struct drm_device *dev,
7975 struct drm_mode_set *set,
7976 struct intel_set_config *config)
50f56119 7977{
85f9eb71 7978 struct drm_crtc *new_crtc;
9a935856
DV		 7979 struct intel_connector *connector;
7980 struct intel_encoder *encoder;
2e431051 7981 int count, ro;
50f56119 7982
9abdda74 7983 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 7984 * of connectors. For paranoia, double-check this. */
7985 WARN_ON(!set->fb && (set->num_connectors != 0));
7986 WARN_ON(set->fb && (set->num_connectors == 0));
7987
50f56119 7988 count = 0;
9a935856
DV		 7989 list_for_each_entry(connector, &dev->mode_config.connector_list,
7990 base.head) {
7991 /* Otherwise traverse passed in connector list and get encoders
7992 * for them. */
50f56119 7993 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7994 if (set->connectors[ro] == &connector->base) {
7995 connector->new_encoder = connector->encoder;
50f56119
DV		 7996 break;
7997 }
7998 }
7999
9a935856
DV		 8000 /* If we disable the crtc, disable all its connectors. Also, if
8001 * the connector is on the changing crtc but not on the new
8002 * connector list, disable it. */
8003 if ((!set->fb || ro == set->num_connectors) &&
8004 connector->base.encoder &&
8005 connector->base.encoder->crtc == set->crtc) {
8006 connector->new_encoder = NULL;
8007
8008 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8009 connector->base.base.id,
8010 drm_get_connector_name(&connector->base));
8011 }
8012
8013
8014 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8015 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8016 config->mode_changed = true;
50f56119
DV		 8017 }
8018 }
9a935856 8019 /* connector->new_encoder is now updated for all connectors. */
50f56119 8020
9a935856 8021 /* Update crtc of enabled connectors. */
50f56119 8022 count = 0;
9a935856
DV		 8023 list_for_each_entry(connector, &dev->mode_config.connector_list,
8024 base.head) {
8025 if (!connector->new_encoder)
50f56119
DV		 8026 continue;
8027
9a935856 8028 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8029
8030 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8031 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8032 new_crtc = set->crtc;
8033 }
8034
8035 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8036 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8037 new_crtc)) {
5e2b584e 8038 return -EINVAL;
50f56119 8039 }
9a935856
DV		 8040 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8041
8042 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8043 connector->base.base.id,
8044 drm_get_connector_name(&connector->base),
8045 new_crtc->base.id);
8046 }
8047
8048 /* Check for any encoders that needs to be disabled. */
8049 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8050 base.head) {
8051 list_for_each_entry(connector,
8052 &dev->mode_config.connector_list,
8053 base.head) {
8054 if (connector->new_encoder == encoder) {
8055 WARN_ON(!connector->new_encoder->new_crtc);
8056
8057 goto next_encoder;
8058 }
8059 }
8060 encoder->new_crtc = NULL;
8061next_encoder:
8062 /* Only now check for crtc changes so we don't miss encoders
8063 * that will be disabled. */
8064 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8065 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8066 config->mode_changed = true;
50f56119
DV		 8067 }
8068 }
9a935856 8069 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8070
2e431051
DV		 8071 return 0;
8072}
8073
8074static int intel_crtc_set_config(struct drm_mode_set *set)
8075{
8076 struct drm_device *dev;
2e431051
DV		 8077 struct drm_mode_set save_set;
8078 struct intel_set_config *config;
8079 int ret;
2e431051 8080
8d3e375e
DV		 8081 BUG_ON(!set);
8082 BUG_ON(!set->crtc);
8083 BUG_ON(!set->crtc->helper_private);
2e431051 8084
7e53f3a4
DV		 8085 /* Enforce sane interface api - has been abused by the fb helper. */
8086 BUG_ON(!set->mode && set->fb);
8087 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8088
2e431051
DV		 8089 if (set->fb) {
8090 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8091 set->crtc->base.id, set->fb->base.id,
8092 (int)set->num_connectors, set->x, set->y);
8093 } else {
8094 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8095 }
8096
8097 dev = set->crtc->dev;
8098
8099 ret = -ENOMEM;
8100 config = kzalloc(sizeof(*config), GFP_KERNEL);
8101 if (!config)
8102 goto out_config;
8103
8104 ret = intel_set_config_save_state(dev, config);
8105 if (ret)
8106 goto out_config;
8107
8108 save_set.crtc = set->crtc;
8109 save_set.mode = &set->crtc->mode;
8110 save_set.x = set->crtc->x;
8111 save_set.y = set->crtc->y;
8112 save_set.fb = set->crtc->fb;
8113
8114 /* Compute whether we need a full modeset, only an fb base update or no
8115 * change at all. In the future we might also check whether only the
8116 * mode changed, e.g. for LVDS where we only change the panel fitter in
8117 * such cases. */
8118 intel_set_config_compute_mode_changes(set, config);
8119
9a935856 8120 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8121 if (ret)
8122 goto fail;
8123
5e2b584e 8124 if (config->mode_changed) {
87f1faa6 8125 if (set->mode) {
50f56119
DV		 8126 DRM_DEBUG_KMS("attempting to set mode from"
8127 " userspace\n");
8128 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8129 }
8130
c0c36b94
CW		 8131 ret = intel_set_mode(set->crtc, set->mode,
8132 set->x, set->y, set->fb);
8133 if (ret) {
8134 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8135 set->crtc->base.id, ret);
87f1faa6
DV		 8136 goto fail;
8137 }
5e2b584e 8138 } else if (config->fb_changed) {
4878cae2
VS		 8139 intel_crtc_wait_for_pending_flips(set->crtc);
8140
4f660f49 8141 ret = intel_pipe_set_base(set->crtc,
94352cf9 8142 set->x, set->y, set->fb);
50f56119
DV		 8143 }
8144
d9e55608
DV		 8145 intel_set_config_free(config);
8146
50f56119
DV		 8147 return 0;
8148
8149fail:
85f9eb71 8150 intel_set_config_restore_state(dev, config);
50f56119
DV		 8151
8152 /* Try to restore the config */
5e2b584e 8153 if (config->mode_changed &&
c0c36b94
CW		 8154 intel_set_mode(save_set.crtc, save_set.mode,
8155 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8156 DRM_ERROR("failed to restore config after modeset failure\n");
8157
d9e55608
DV		 8158out_config:
8159 intel_set_config_free(config);
50f56119
DV		 8160 return ret;
8161}
f6e5b160
CW		 8162
8163static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8164 .cursor_set = intel_crtc_cursor_set,
8165 .cursor_move = intel_crtc_cursor_move,
8166 .gamma_set = intel_crtc_gamma_set,
50f56119 8167 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8168 .destroy = intel_crtc_destroy,
8169 .page_flip = intel_crtc_page_flip,
8170};
8171
79f689aa
PZ		 8172static void intel_cpu_pll_init(struct drm_device *dev)
8173{
affa9354 8174 if (HAS_DDI(dev))
79f689aa
PZ		 8175 intel_ddi_pll_init(dev);
8176}
8177
ee7b9f93
JB		 8178static void intel_pch_pll_init(struct drm_device *dev)
8179{
8180 drm_i915_private_t *dev_priv = dev->dev_private;
8181 int i;
8182
8183 if (dev_priv->num_pch_pll == 0) {
8184 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8185 return;
8186 }
8187
8188 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8189 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8190 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8191 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8192 }
8193}
8194
b358d0a6 8195static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8196{
22fd0fab 8197 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8198 struct intel_crtc *intel_crtc;
8199 int i;
8200
8201 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8202 if (intel_crtc == NULL)
8203 return;
8204
8205 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8206
8207 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8208 for (i = 0; i < 256; i++) {
8209 intel_crtc->lut_r[i] = i;
8210 intel_crtc->lut_g[i] = i;
8211 intel_crtc->lut_b[i] = i;
8212 }
8213
80824003
JB		 8214 /* Swap pipes & planes for FBC on pre-965 */
8215 intel_crtc->pipe = pipe;
8216 intel_crtc->plane = pipe;
a5c961d1 8217 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8218 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8219 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8220 intel_crtc->plane = !pipe;
80824003
JB		 8221 }
8222
22fd0fab
JB		 8223 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8224 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8225 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8226 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8227
79e53945 8228 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8229}
8230
08d7b3d1 8231int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8232 struct drm_file *file)
08d7b3d1 8233{
08d7b3d1 8234 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8235 struct drm_mode_object *drmmode_obj;
8236 struct intel_crtc *crtc;
08d7b3d1 8237
1cff8f6b
DV		 8238 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8239 return -ENODEV;
08d7b3d1 8240
c05422d5
DV		 8241 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8242 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8243
c05422d5 8244 if (!drmmode_obj) {
08d7b3d1
CW		 8245 DRM_ERROR("no such CRTC id\n");
8246 return -EINVAL;
8247 }
8248
c05422d5
DV		 8249 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8250 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8251
c05422d5 8252 return 0;
08d7b3d1
CW		 8253}
8254
66a9278e 8255static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8256{
66a9278e
DV		 8257 struct drm_device *dev = encoder->base.dev;
8258 struct intel_encoder *source_encoder;
79e53945 8259 int index_mask = 0;
79e53945
JB		 8260 int entry = 0;
8261
66a9278e
DV		 8262 list_for_each_entry(source_encoder,
8263 &dev->mode_config.encoder_list, base.head) {
8264
8265 if (encoder == source_encoder)
79e53945 8266 index_mask |= (1 << entry);
66a9278e
DV		 8267
8268 /* Intel hw has only one MUX where enocoders could be cloned. */
8269 if (encoder->cloneable && source_encoder->cloneable)
8270 index_mask |= (1 << entry);
8271
79e53945
JB		 8272 entry++;
8273 }
4ef69c7a 8274
79e53945
JB		 8275 return index_mask;
8276}
8277
4d302442
CW		 8278static bool has_edp_a(struct drm_device *dev)
8279{
8280 struct drm_i915_private *dev_priv = dev->dev_private;
8281
8282 if (!IS_MOBILE(dev))
8283 return false;
8284
8285 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8286 return false;
8287
8288 if (IS_GEN5(dev) &&
8289 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8290 return false;
8291
8292 return true;
8293}
8294
79e53945
JB		 8295static void intel_setup_outputs(struct drm_device *dev)
8296{
725e30ad 8297 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8298 struct intel_encoder *encoder;
cb0953d7 8299 bool dpd_is_edp = false;
f3cfcba6 8300 bool has_lvds;
79e53945 8301
f3cfcba6 8302 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8303 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8304 /* disable the panel fitter on everything but LVDS */
8305 I915_WRITE(PFIT_CONTROL, 0);
8306 }
79e53945 8307
affa9354 8308 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8309 intel_crt_init(dev);
cb0953d7 8310
affa9354 8311 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8312 int found;
8313
8314 /* Haswell uses DDI functions to detect digital outputs */
8315 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8316 /* DDI A only supports eDP */
8317 if (found)
8318 intel_ddi_init(dev, PORT_A);
8319
8320 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8321 * register */
8322 found = I915_READ(SFUSE_STRAP);
8323
8324 if (found & SFUSE_STRAP_DDIB_DETECTED)
8325 intel_ddi_init(dev, PORT_B);
8326 if (found & SFUSE_STRAP_DDIC_DETECTED)
8327 intel_ddi_init(dev, PORT_C);
8328 if (found & SFUSE_STRAP_DDID_DETECTED)
8329 intel_ddi_init(dev, PORT_D);
8330 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8331 int found;
270b3042
DV		 8332 dpd_is_edp = intel_dpd_is_edp(dev);
8333
8334 if (has_edp_a(dev))
8335 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8336
dc0fa718 8337 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8338 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8339 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8340 if (!found)
e2debe91 8341 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8342 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8343 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8344 }
8345
dc0fa718 8346 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8347 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8348
dc0fa718 8349 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8350 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8351
5eb08b69 8352 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8353 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8354
270b3042 8355 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8356 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8357 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8358 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8359 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8360 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8361
dc0fa718 8362 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8363 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8364 PORT_B);
67cfc203
VS		 8365 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8366 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8367 }
103a196f 8368 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8369 bool found = false;
7d57382e 8370
e2debe91 8371 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8372 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8373 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8374 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8375 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8376 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8377 }
27185ae1 8378
b01f2c3a
JB		 8379 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8380 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8381 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8382 }
725e30ad 8383 }
13520b05
KH		 8384
8385 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8386
e2debe91 8387 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8388 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8389 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8390 }
27185ae1 8391
e2debe91 8392 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8393
b01f2c3a
JB		 8394 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8395 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8396 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8397 }
8398 if (SUPPORTS_INTEGRATED_DP(dev)) {
8399 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8400 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8401 }
725e30ad 8402 }
27185ae1 8403
b01f2c3a
JB		 8404 if (SUPPORTS_INTEGRATED_DP(dev) &&
8405 (I915_READ(DP_D) & DP_DETECTED)) {
8406 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8407 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8408 }
bad720ff 8409 } else if (IS_GEN2(dev))
79e53945
JB		 8410 intel_dvo_init(dev);
8411
103a196f 8412 if (SUPPORTS_TV(dev))
79e53945
JB		 8413 intel_tv_init(dev);
8414
4ef69c7a
CW		 8415 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8416 encoder->base.possible_crtcs = encoder->crtc_mask;
8417 encoder->base.possible_clones =
66a9278e 8418 intel_encoder_clones(encoder);
79e53945 8419 }
47356eb6 8420
dde86e2d 8421 intel_init_pch_refclk(dev);
270b3042
DV		 8422
8423 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8424}
8425
8426static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8427{
8428 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8429
8430 drm_framebuffer_cleanup(fb);
05394f39 8431 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8432
8433 kfree(intel_fb);
8434}
8435
8436static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8437 struct drm_file *file,
79e53945
JB		 8438 unsigned int *handle)
8439{
8440 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8441 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8442
05394f39 8443 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8444}
8445
8446static const struct drm_framebuffer_funcs intel_fb_funcs = {
8447 .destroy = intel_user_framebuffer_destroy,
8448 .create_handle = intel_user_framebuffer_create_handle,
8449};
8450
38651674
DA		 8451int intel_framebuffer_init(struct drm_device *dev,
8452 struct intel_framebuffer *intel_fb,
308e5bcb 8453 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8454 struct drm_i915_gem_object *obj)
79e53945 8455{
79e53945
JB		 8456 int ret;
8457
c16ed4be
CW		 8458 if (obj->tiling_mode == I915_TILING_Y) {
8459 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8460 return -EINVAL;
c16ed4be 8461 }
57cd6508 8462
c16ed4be
CW		 8463 if (mode_cmd->pitches[0] & 63) {
8464 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8465 mode_cmd->pitches[0]);
57cd6508 8466 return -EINVAL;
c16ed4be 8467 }
57cd6508 8468
5d7bd705 8469 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8470 if (mode_cmd->pitches[0] > 32768) {
8471 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8472 mode_cmd->pitches[0]);
5d7bd705 8473 return -EINVAL;
c16ed4be 8474 }
5d7bd705
VS		 8475
8476 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8477 mode_cmd->pitches[0] != obj->stride) {
8478 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8479 mode_cmd->pitches[0], obj->stride);
5d7bd705 8480 return -EINVAL;
c16ed4be 8481 }
5d7bd705 8482
57779d06 8483 /* Reject formats not supported by any plane early. */
308e5bcb 8484 switch (mode_cmd->pixel_format) {
57779d06 8485 case DRM_FORMAT_C8:
04b3924d
VS		 8486 case DRM_FORMAT_RGB565:
8487 case DRM_FORMAT_XRGB8888:
8488 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8489 break;
8490 case DRM_FORMAT_XRGB1555:
8491 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8492 if (INTEL_INFO(dev)->gen > 3) {
8493 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8494 return -EINVAL;
c16ed4be 8495 }
57779d06
VS		 8496 break;
8497 case DRM_FORMAT_XBGR8888:
8498 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8499 case DRM_FORMAT_XRGB2101010:
8500 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8501 case DRM_FORMAT_XBGR2101010:
8502 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8503 if (INTEL_INFO(dev)->gen < 4) {
8504 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8505 return -EINVAL;
c16ed4be 8506 }
b5626747 8507 break;
04b3924d
VS		 8508 case DRM_FORMAT_YUYV:
8509 case DRM_FORMAT_UYVY:
8510 case DRM_FORMAT_YVYU:
8511 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8512 if (INTEL_INFO(dev)->gen < 5) {
8513 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8514 return -EINVAL;
c16ed4be 8515 }
57cd6508
CW		 8516 break;
8517 default:
c16ed4be 8518 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8519 return -EINVAL;
8520 }
8521
90f9a336
VS		 8522 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8523 if (mode_cmd->offsets[0] != 0)
8524 return -EINVAL;
8525
c7d73f6a
DV		 8526 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8527 intel_fb->obj = obj;
8528
79e53945
JB		 8529 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8530 if (ret) {
8531 DRM_ERROR("framebuffer init failed %d\n", ret);
8532 return ret;
8533 }
8534
79e53945
JB		 8535 return 0;
8536}
8537
79e53945
JB		 8538static struct drm_framebuffer *
8539intel_user_framebuffer_create(struct drm_device *dev,
8540 struct drm_file *filp,
308e5bcb 8541 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8542{
05394f39 8543 struct drm_i915_gem_object *obj;
79e53945 8544
308e5bcb
JB		 8545 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8546 mode_cmd->handles[0]));
c8725226 8547 if (&obj->base == NULL)
cce13ff7 8548 return ERR_PTR(-ENOENT);
79e53945 8549
d2dff872 8550 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8551}
8552
79e53945 8553static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8554 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8555 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8556};
8557
e70236a8
JB		 8558/* Set up chip specific display functions */
8559static void intel_init_display(struct drm_device *dev)
8560{
8561 struct drm_i915_private *dev_priv = dev->dev_private;
8562
affa9354 8563 if (HAS_DDI(dev)) {
09b4ddf9 8564 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8565 dev_priv->display.crtc_enable = haswell_crtc_enable;
8566 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8567 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8568 dev_priv->display.update_plane = ironlake_update_plane;
8569 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8570 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8571 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8572 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8573 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8574 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8575 } else {
f564048e 8576 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8577 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8578 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8579 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8580 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8581 }
e70236a8 8582
e70236a8 8583 /* Returns the core display clock speed */
25eb05fc
JB		 8584 if (IS_VALLEYVIEW(dev))
8585 dev_priv->display.get_display_clock_speed =
8586 valleyview_get_display_clock_speed;
8587 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8588 dev_priv->display.get_display_clock_speed =
8589 i945_get_display_clock_speed;
8590 else if (IS_I915G(dev))
8591 dev_priv->display.get_display_clock_speed =
8592 i915_get_display_clock_speed;
f2b115e6 8593 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8594 dev_priv->display.get_display_clock_speed =
8595 i9xx_misc_get_display_clock_speed;
8596 else if (IS_I915GM(dev))
8597 dev_priv->display.get_display_clock_speed =
8598 i915gm_get_display_clock_speed;
8599 else if (IS_I865G(dev))
8600 dev_priv->display.get_display_clock_speed =
8601 i865_get_display_clock_speed;
f0f8a9ce 8602 else if (IS_I85X(dev))
e70236a8
JB		 8603 dev_priv->display.get_display_clock_speed =
8604 i855_get_display_clock_speed;
8605 else /* 852, 830 */
8606 dev_priv->display.get_display_clock_speed =
8607 i830_get_display_clock_speed;
8608
7f8a8569 8609 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8610 if (IS_GEN5(dev)) {
674cf967 8611 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8612 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8613 } else if (IS_GEN6(dev)) {
674cf967 8614 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8615 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8616 } else if (IS_IVYBRIDGE(dev)) {
8617 /* FIXME: detect B0+ stepping and use auto training */
8618 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8619 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8620 dev_priv->display.modeset_global_resources =
8621 ivb_modeset_global_resources;
c82e4d26
ED		 8622 } else if (IS_HASWELL(dev)) {
8623 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8624 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8625 dev_priv->display.modeset_global_resources =
8626 haswell_modeset_global_resources;
a0e63c22 8627 }
6067aaea 8628 } else if (IS_G4X(dev)) {
e0dac65e 8629 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8630 }
8c9f3aaf
JB		 8631
8632 /* Default just returns -ENODEV to indicate unsupported */
8633 dev_priv->display.queue_flip = intel_default_queue_flip;
8634
8635 switch (INTEL_INFO(dev)->gen) {
8636 case 2:
8637 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8638 break;
8639
8640 case 3:
8641 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8642 break;
8643
8644 case 4:
8645 case 5:
8646 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8647 break;
8648
8649 case 6:
8650 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8651 break;
7c9017e5
JB		 8652 case 7:
8653 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8654 break;
8c9f3aaf 8655 }
e70236a8
JB		 8656}
8657
b690e96c
JB		 8658/*
8659 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8660 * resume, or other times. This quirk makes sure that's the case for
8661 * affected systems.
8662 */
0206e353 8663static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8664{
8665 struct drm_i915_private *dev_priv = dev->dev_private;
8666
8667 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8668 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8669}
8670
435793df
KP		 8671/*
8672 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8673 */
8674static void quirk_ssc_force_disable(struct drm_device *dev)
8675{
8676 struct drm_i915_private *dev_priv = dev->dev_private;
8677 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8678 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8679}
8680
4dca20ef 8681/*
5a15ab5b
CE		 8682 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8683 * brightness value
4dca20ef
CE		 8684 */
8685static void quirk_invert_brightness(struct drm_device *dev)
8686{
8687 struct drm_i915_private *dev_priv = dev->dev_private;
8688 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8689 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8690}
8691
b690e96c
JB		 8692struct intel_quirk {
8693 int device;
8694 int subsystem_vendor;
8695 int subsystem_device;
8696 void (*hook)(struct drm_device *dev);
8697};
8698
5f85f176
EE		 8699/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8700struct intel_dmi_quirk {
8701 void (*hook)(struct drm_device *dev);
8702 const struct dmi_system_id (*dmi_id_list)[];
8703};
8704
8705static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8706{
8707 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8708 return 1;
8709}
8710
8711static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8712 {
8713 .dmi_id_list = &(const struct dmi_system_id[]) {
8714 {
8715 .callback = intel_dmi_reverse_brightness,
8716 .ident = "NCR Corporation",
8717 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8718 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8719 },
8720 },
8721 { } /* terminating entry */
8722 },
8723 .hook = quirk_invert_brightness,
8724 },
8725};
8726
c43b5634 8727static struct intel_quirk intel_quirks[] = {
b690e96c 8728 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8729 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8730
b690e96c
JB		 8731 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8732 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8733
b690e96c
JB		 8734 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8735 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8736
ccd0d36e 8737 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8738 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8739 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8740
8741 /* Lenovo U160 cannot use SSC on LVDS */
8742 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8743
8744 /* Sony Vaio Y cannot use SSC on LVDS */
8745 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8746
8747 /* Acer Aspire 5734Z must invert backlight brightness */
8748 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8749
8750 /* Acer/eMachines G725 */
8751 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8752
8753 /* Acer/eMachines e725 */
8754 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8755
8756 /* Acer/Packard Bell NCL20 */
8757 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 8758
8759 /* Acer Aspire 4736Z */
8760 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 8761};
8762
8763static void intel_init_quirks(struct drm_device *dev)
8764{
8765 struct pci_dev *d = dev->pdev;
8766 int i;
8767
8768 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8769 struct intel_quirk *q = &intel_quirks[i];
8770
8771 if (d->device == q->device &&
8772 (d->subsystem_vendor == q->subsystem_vendor ||
8773 q->subsystem_vendor == PCI_ANY_ID) &&
8774 (d->subsystem_device == q->subsystem_device ||
8775 q->subsystem_device == PCI_ANY_ID))
8776 q->hook(dev);
8777 }
5f85f176
EE		 8778 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8779 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8780 intel_dmi_quirks[i].hook(dev);
8781 }
b690e96c
JB		 8782}
8783
9cce37f4
JB		 8784/* Disable the VGA plane that we never use */
8785static void i915_disable_vga(struct drm_device *dev)
8786{
8787 struct drm_i915_private *dev_priv = dev->dev_private;
8788 u8 sr1;
766aa1c4 8789 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 8790
8791 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8792 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8793 sr1 = inb(VGA_SR_DATA);
8794 outb(sr1 | 1<<5, VGA_SR_DATA);
8795 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8796 udelay(300);
8797
8798 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8799 POSTING_READ(vga_reg);
8800}
8801
f817586c
DV		 8802void intel_modeset_init_hw(struct drm_device *dev)
8803{
fa42e23c 8804 intel_init_power_well(dev);
0232e927 8805
a8f78b58
ED		 8806 intel_prepare_ddi(dev);
8807
f817586c
DV		 8808 intel_init_clock_gating(dev);
8809
79f5b2c7 8810 mutex_lock(&dev->struct_mutex);
8090c6b9 8811 intel_enable_gt_powersave(dev);
79f5b2c7 8812 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8813}
8814
79e53945
JB		 8815void intel_modeset_init(struct drm_device *dev)
8816{
652c393a 8817 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8818 int i, ret;
79e53945
JB		 8819
8820 drm_mode_config_init(dev);
8821
8822 dev->mode_config.min_width = 0;
8823 dev->mode_config.min_height = 0;
8824
019d96cb
DA		 8825 dev->mode_config.preferred_depth = 24;
8826 dev->mode_config.prefer_shadow = 1;
8827
e6ecefaa 8828 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8829
b690e96c
JB		 8830 intel_init_quirks(dev);
8831
1fa61106
ED		 8832 intel_init_pm(dev);
8833
e70236a8
JB		 8834 intel_init_display(dev);
8835
a6c45cf0
CW		 8836 if (IS_GEN2(dev)) {
8837 dev->mode_config.max_width = 2048;
8838 dev->mode_config.max_height = 2048;
8839 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8840 dev->mode_config.max_width = 4096;
8841 dev->mode_config.max_height = 4096;
79e53945 8842 } else {
a6c45cf0
CW		 8843 dev->mode_config.max_width = 8192;
8844 dev->mode_config.max_height = 8192;
79e53945 8845 }
5d4545ae 8846 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 8847
28c97730 8848 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 8849 INTEL_INFO(dev)->num_pipes,
8850 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 8851
7eb552ae 8852 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 8853 intel_crtc_init(dev, i);
00c2064b
JB		 8854 ret = intel_plane_init(dev, i);
8855 if (ret)
8856 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8857 }
8858
79f689aa 8859 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8860 intel_pch_pll_init(dev);
8861
9cce37f4
JB		 8862 /* Just disable it once at startup */
8863 i915_disable_vga(dev);
79e53945 8864 intel_setup_outputs(dev);
11be49eb
CW		 8865
8866 /* Just in case the BIOS is doing something questionable. */
8867 intel_disable_fbc(dev);
2c7111db
CW		 8868}
8869
24929352
DV		 8870static void
8871intel_connector_break_all_links(struct intel_connector *connector)
8872{
8873 connector->base.dpms = DRM_MODE_DPMS_OFF;
8874 connector->base.encoder = NULL;
8875 connector->encoder->connectors_active = false;
8876 connector->encoder->base.crtc = NULL;
8877}
8878
7fad798e
DV		 8879static void intel_enable_pipe_a(struct drm_device *dev)
8880{
8881 struct intel_connector *connector;
8882 struct drm_connector *crt = NULL;
8883 struct intel_load_detect_pipe load_detect_temp;
8884
8885 /* We can't just switch on the pipe A, we need to set things up with a
8886 * proper mode and output configuration. As a gross hack, enable pipe A
8887 * by enabling the load detect pipe once. */
8888 list_for_each_entry(connector,
8889 &dev->mode_config.connector_list,
8890 base.head) {
8891 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8892 crt = &connector->base;
8893 break;
8894 }
8895 }
8896
8897 if (!crt)
8898 return;
8899
8900 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8901 intel_release_load_detect_pipe(crt, &load_detect_temp);
8902
652c393a 8903
7fad798e
DV		 8904}
8905
fa555837
DV		 8906static bool
8907intel_check_plane_mapping(struct intel_crtc *crtc)
8908{
7eb552ae
BW		 8909 struct drm_device *dev = crtc->base.dev;
8910 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 8911 u32 reg, val;
8912
7eb552ae 8913 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 8914 return true;
8915
8916 reg = DSPCNTR(!crtc->plane);
8917 val = I915_READ(reg);
8918
8919 if ((val & DISPLAY_PLANE_ENABLE) &&
8920 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8921 return false;
8922
8923 return true;
8924}
8925
24929352
DV		 8926static void intel_sanitize_crtc(struct intel_crtc *crtc)
8927{
8928 struct drm_device *dev = crtc->base.dev;
8929 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8930 u32 reg;
24929352 8931
24929352 8932 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8933 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8934 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8935
8936 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8937 * disable the crtc (and hence change the state) if it is wrong. Note
8938 * that gen4+ has a fixed plane -> pipe mapping. */
8939 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8940 struct intel_connector *connector;
8941 bool plane;
8942
24929352
DV		 8943 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8944 crtc->base.base.id);
8945
8946 /* Pipe has the wrong plane attached and the plane is active.
8947 * Temporarily change the plane mapping and disable everything
8948 * ... */
8949 plane = crtc->plane;
8950 crtc->plane = !plane;
8951 dev_priv->display.crtc_disable(&crtc->base);
8952 crtc->plane = plane;
8953
8954 /* ... and break all links. */
8955 list_for_each_entry(connector, &dev->mode_config.connector_list,
8956 base.head) {
8957 if (connector->encoder->base.crtc != &crtc->base)
8958 continue;
8959
8960 intel_connector_break_all_links(connector);
8961 }
8962
8963 WARN_ON(crtc->active);
8964 crtc->base.enabled = false;
8965 }
24929352 8966
7fad798e
DV		 8967 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8968 crtc->pipe == PIPE_A && !crtc->active) {
8969 /* BIOS forgot to enable pipe A, this mostly happens after
8970 * resume. Force-enable the pipe to fix this, the update_dpms
8971 * call below we restore the pipe to the right state, but leave
8972 * the required bits on. */
8973 intel_enable_pipe_a(dev);
8974 }
8975
24929352
DV		 8976 /* Adjust the state of the output pipe according to whether we
8977 * have active connectors/encoders. */
8978 intel_crtc_update_dpms(&crtc->base);
8979
8980 if (crtc->active != crtc->base.enabled) {
8981 struct intel_encoder *encoder;
8982
8983 /* This can happen either due to bugs in the get_hw_state
8984 * functions or because the pipe is force-enabled due to the
8985 * pipe A quirk. */
8986 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8987 crtc->base.base.id,
8988 crtc->base.enabled ? "enabled" : "disabled",
8989 crtc->active ? "enabled" : "disabled");
8990
8991 crtc->base.enabled = crtc->active;
8992
8993 /* Because we only establish the connector -> encoder ->
8994 * crtc links if something is active, this means the
8995 * crtc is now deactivated. Break the links. connector
8996 * -> encoder links are only establish when things are
8997 * actually up, hence no need to break them. */
8998 WARN_ON(crtc->active);
8999
9000 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9001 WARN_ON(encoder->connectors_active);
9002 encoder->base.crtc = NULL;
9003 }
9004 }
9005}
9006
9007static void intel_sanitize_encoder(struct intel_encoder *encoder)
9008{
9009 struct intel_connector *connector;
9010 struct drm_device *dev = encoder->base.dev;
9011
9012 /* We need to check both for a crtc link (meaning that the
9013 * encoder is active and trying to read from a pipe) and the
9014 * pipe itself being active. */
9015 bool has_active_crtc = encoder->base.crtc &&
9016 to_intel_crtc(encoder->base.crtc)->active;
9017
9018 if (encoder->connectors_active && !has_active_crtc) {
9019 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9020 encoder->base.base.id,
9021 drm_get_encoder_name(&encoder->base));
9022
9023 /* Connector is active, but has no active pipe. This is
9024 * fallout from our resume register restoring. Disable
9025 * the encoder manually again. */
9026 if (encoder->base.crtc) {
9027 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9028 encoder->base.base.id,
9029 drm_get_encoder_name(&encoder->base));
9030 encoder->disable(encoder);
9031 }
9032
9033 /* Inconsistent output/port/pipe state happens presumably due to
9034 * a bug in one of the get_hw_state functions. Or someplace else
9035 * in our code, like the register restore mess on resume. Clamp
9036 * things to off as a safer default. */
9037 list_for_each_entry(connector,
9038 &dev->mode_config.connector_list,
9039 base.head) {
9040 if (connector->encoder != encoder)
9041 continue;
9042
9043 intel_connector_break_all_links(connector);
9044 }
9045 }
9046 /* Enabled encoders without active connectors will be fixed in
9047 * the crtc fixup. */
9048}
9049
44cec740 9050void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9051{
9052 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9053 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9054
9055 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9056 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9057 i915_disable_vga(dev);
0fde901f
KM		 9058 }
9059}
9060
24929352
DV		 9061/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9062 * and i915 state tracking structures. */
45e2b5f6
DV		 9063void intel_modeset_setup_hw_state(struct drm_device *dev,
9064 bool force_restore)
24929352
DV		 9065{
9066 struct drm_i915_private *dev_priv = dev->dev_private;
9067 enum pipe pipe;
9068 u32 tmp;
b5644d05 9069 struct drm_plane *plane;
24929352
DV		 9070 struct intel_crtc *crtc;
9071 struct intel_encoder *encoder;
9072 struct intel_connector *connector;
9073
affa9354 9074 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9075 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9076
9077 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9078 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9079 case TRANS_DDI_EDP_INPUT_A_ON:
9080 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9081 pipe = PIPE_A;
9082 break;
9083 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9084 pipe = PIPE_B;
9085 break;
9086 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9087 pipe = PIPE_C;
9088 break;
aaa148ec
DL		 9089 default:
9090 /* A bogus value has been programmed, disable
9091 * the transcoder */
9092 WARN(1, "Bogus eDP source %08x\n", tmp);
9093 intel_ddi_disable_transcoder_func(dev_priv,
9094 TRANSCODER_EDP);
9095 goto setup_pipes;
e28d54cb
PZ		 9096 }
9097
9098 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9099 crtc->cpu_transcoder = TRANSCODER_EDP;
9100
9101 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9102 pipe_name(pipe));
9103 }
9104 }
9105
aaa148ec 9106setup_pipes:
24929352
DV		 9107 for_each_pipe(pipe) {
9108 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9109
702e7a56 9110 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9111 if (tmp & PIPECONF_ENABLE)
9112 crtc->active = true;
9113 else
9114 crtc->active = false;
9115
9116 crtc->base.enabled = crtc->active;
9117
9118 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9119 crtc->base.base.id,
9120 crtc->active ? "enabled" : "disabled");
9121 }
9122
affa9354 9123 if (HAS_DDI(dev))
6441ab5f
PZ		 9124 intel_ddi_setup_hw_pll_state(dev);
9125
24929352
DV		 9126 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9127 base.head) {
9128 pipe = 0;
9129
9130 if (encoder->get_hw_state(encoder, &pipe)) {
9131 encoder->base.crtc =
9132 dev_priv->pipe_to_crtc_mapping[pipe];
9133 } else {
9134 encoder->base.crtc = NULL;
9135 }
9136
9137 encoder->connectors_active = false;
9138 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9139 encoder->base.base.id,
9140 drm_get_encoder_name(&encoder->base),
9141 encoder->base.crtc ? "enabled" : "disabled",
9142 pipe);
9143 }
9144
9145 list_for_each_entry(connector, &dev->mode_config.connector_list,
9146 base.head) {
9147 if (connector->get_hw_state(connector)) {
9148 connector->base.dpms = DRM_MODE_DPMS_ON;
9149 connector->encoder->connectors_active = true;
9150 connector->base.encoder = &connector->encoder->base;
9151 } else {
9152 connector->base.dpms = DRM_MODE_DPMS_OFF;
9153 connector->base.encoder = NULL;
9154 }
9155 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9156 connector->base.base.id,
9157 drm_get_connector_name(&connector->base),
9158 connector->base.encoder ? "enabled" : "disabled");
9159 }
9160
9161 /* HW state is read out, now we need to sanitize this mess. */
9162 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9163 base.head) {
9164 intel_sanitize_encoder(encoder);
9165 }
9166
9167 for_each_pipe(pipe) {
9168 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9169 intel_sanitize_crtc(crtc);
9170 }
9a935856 9171
45e2b5f6
DV		 9172 if (force_restore) {
9173 for_each_pipe(pipe) {
b5644d05
JB		 9174 struct drm_crtc *crtc =
9175 dev_priv->pipe_to_crtc_mapping[pipe];
9176 intel_crtc_restore_mode(crtc);
45e2b5f6 9177 }
b5644d05
JB		 9178 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9179 intel_plane_restore(plane);
0fde901f
KM		 9180
9181 i915_redisable_vga(dev);
45e2b5f6
DV		 9182 } else {
9183 intel_modeset_update_staged_output_state(dev);
9184 }
8af6cf88
DV		 9185
9186 intel_modeset_check_state(dev);
2e938892
DV		 9187
9188 drm_mode_config_reset(dev);
2c7111db
CW		 9189}
9190
9191void intel_modeset_gem_init(struct drm_device *dev)
9192{
1833b134 9193 intel_modeset_init_hw(dev);
02e792fb
DV		 9194
9195 intel_setup_overlay(dev);
24929352 9196
45e2b5f6 9197 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9198}
9199
9200void intel_modeset_cleanup(struct drm_device *dev)
9201{
652c393a
JB		 9202 struct drm_i915_private *dev_priv = dev->dev_private;
9203 struct drm_crtc *crtc;
9204 struct intel_crtc *intel_crtc;
9205
f87ea761 9206 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9207 mutex_lock(&dev->struct_mutex);
9208
723bfd70
JB		 9209 intel_unregister_dsm_handler();
9210
9211
652c393a
JB		 9212 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9213 /* Skip inactive CRTCs */
9214 if (!crtc->fb)
9215 continue;
9216
9217 intel_crtc = to_intel_crtc(crtc);
3dec0095 9218 intel_increase_pllclock(crtc);
652c393a
JB		 9219 }
9220
973d04f9 9221 intel_disable_fbc(dev);
e70236a8 9222
8090c6b9 9223 intel_disable_gt_powersave(dev);
0cdab21f 9224
930ebb46
DV		 9225 ironlake_teardown_rc6(dev);
9226
57f350b6
JB		 9227 if (IS_VALLEYVIEW(dev))
9228 vlv_init_dpio(dev);
9229
69341a5e
KH		 9230 mutex_unlock(&dev->struct_mutex);
9231
6c0d9350
DV		 9232 /* Disable the irq before mode object teardown, for the irq might
9233 * enqueue unpin/hotplug work. */
9234 drm_irq_uninstall(dev);
9235 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9236 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9237
1630fe75
CW		 9238 /* flush any delayed tasks or pending work */
9239 flush_scheduled_work();
9240
79e53945 9241 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9242
9243 intel_cleanup_overlay(dev);
79e53945
JB		 9244}
9245
f1c79df3
ZW		 9246/*
9247 * Return which encoder is currently attached for connector.
9248 */
df0e9248 9249struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9250{
df0e9248
CW		 9251 return &intel_attached_encoder(connector)->base;
9252}
f1c79df3 9253
df0e9248
CW		 9254void intel_connector_attach_encoder(struct intel_connector *connector,
9255 struct intel_encoder *encoder)
9256{
9257 connector->encoder = encoder;
9258 drm_mode_connector_attach_encoder(&connector->base,
9259 &encoder->base);
79e53945 9260}
28d52043
DA		 9261
9262/*
9263 * set vga decode state - true == enable VGA decode
9264 */
9265int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9266{
9267 struct drm_i915_private *dev_priv = dev->dev_private;
9268 u16 gmch_ctrl;
9269
9270 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9271 if (state)
9272 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9273 else
9274 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9275 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9276 return 0;
9277}
c4a1d9e4
CW		 9278
9279#ifdef CONFIG_DEBUG_FS
9280#include <linux/seq_file.h>
9281
9282struct intel_display_error_state {
9283 struct intel_cursor_error_state {
9284 u32 control;
9285 u32 position;
9286 u32 base;
9287 u32 size;
52331309 9288 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9289
9290 struct intel_pipe_error_state {
9291 u32 conf;
9292 u32 source;
9293
9294 u32 htotal;
9295 u32 hblank;
9296 u32 hsync;
9297 u32 vtotal;
9298 u32 vblank;
9299 u32 vsync;
52331309 9300 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9301
9302 struct intel_plane_error_state {
9303 u32 control;
9304 u32 stride;
9305 u32 size;
9306 u32 pos;
9307 u32 addr;
9308 u32 surface;
9309 u32 tile_offset;
52331309 9310 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9311};
9312
9313struct intel_display_error_state *
9314intel_display_capture_error_state(struct drm_device *dev)
9315{
0206e353 9316 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9317 struct intel_display_error_state *error;
702e7a56 9318 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9319 int i;
9320
9321 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9322 if (error == NULL)
9323 return NULL;
9324
52331309 9325 for_each_pipe(i) {
702e7a56
PZ		 9326 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9327
a18c4c3d
PZ		 9328 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9329 error->cursor[i].control = I915_READ(CURCNTR(i));
9330 error->cursor[i].position = I915_READ(CURPOS(i));
9331 error->cursor[i].base = I915_READ(CURBASE(i));
9332 } else {
9333 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9334 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9335 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9336 }
c4a1d9e4
CW		 9337
9338 error->plane[i].control = I915_READ(DSPCNTR(i));
9339 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9340 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9341 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9342 error->plane[i].pos = I915_READ(DSPPOS(i));
9343 }
ca291363
PZ		 9344 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9345 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9346 if (INTEL_INFO(dev)->gen >= 4) {
9347 error->plane[i].surface = I915_READ(DSPSURF(i));
9348 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9349 }
9350
702e7a56 9351 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9352 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9353 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9354 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9355 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9356 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9357 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9358 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9359 }
9360
9361 return error;
9362}
9363
9364void
9365intel_display_print_error_state(struct seq_file *m,
9366 struct drm_device *dev,
9367 struct intel_display_error_state *error)
9368{
9369 int i;
9370
7eb552ae 9371 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9372 for_each_pipe(i) {
c4a1d9e4
CW		 9373 seq_printf(m, "Pipe [%d]:\n", i);
9374 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9375 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9376 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9377 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9378 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9379 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9380 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9381 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9382
9383 seq_printf(m, "Plane [%d]:\n", i);
9384 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9385 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9386 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9387 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9388 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9389 }
4b71a570 9390 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9391 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9392 if (INTEL_INFO(dev)->gen >= 4) {
9393 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9394 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9395 }
9396
9397 seq_printf(m, "Cursor [%d]:\n", i);
9398 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9399 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9400 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9401 }
9402}
9403#endif
Linux kernel - Deliverables
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