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drm/i915: move dp clock computations to encoder->compute_config
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
f4808ab8
VS		 62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
d4906093 80};
79e53945 81
2377b741
JB		 82/* FDI */
83#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
d2acd215
DV		 85int
86intel_pch_rawclk(struct drm_device *dev)
87{
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93}
94
d4906093
ML		 95static bool
96intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
d4906093
ML		 99static bool
100intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
79e53945 103
a0c4da24
JB		 104static bool
105intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
021357ac
CW		 109static inline u32 /* units of 100MHz */
110intel_fdi_link_freq(struct drm_device *dev)
111{
8b99e68c
CW		 112 if (IS_GEN5(dev)) {
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
115 } else
116 return 27;
021357ac
CW		 117}
118
e4b36699 119static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
d4906093 130 .find_pll = intel_find_best_PLL,
e4b36699
KP		 131};
132
133static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
d4906093 144 .find_pll = intel_find_best_PLL,
e4b36699 145};
273e27ca 146
e4b36699 147static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
d4906093 158 .find_pll = intel_find_best_PLL,
e4b36699
KP		 159};
160
161static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
d4906093 172 .find_pll = intel_find_best_PLL,
e4b36699
KP		 173};
174
273e27ca 175
e4b36699 176static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
186 .p2_slow = 10,
187 .p2_fast = 10
044c7c41 188 },
d4906093 189 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 190};
191
192static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
d4906093 203 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 204};
205
206static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
044c7c41 217 },
d4906093 218 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 219};
220
221static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
044c7c41 232 },
d4906093 233 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 234};
235
f2b115e6 236static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 239 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
273e27ca 242 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
6115707b 249 .find_pll = intel_find_best_PLL,
e4b36699
KP		 250};
251
f2b115e6 252static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
6115707b 263 .find_pll = intel_find_best_PLL,
e4b36699
KP		 264};
265
273e27ca
EA		 266/* Ironlake / Sandybridge
267 *
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
270 */
b91ad0ec 271static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
4547668a 282 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 283};
284
b91ad0ec 285static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 296 .find_pll = intel_g4x_find_best_PLL,
297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 310 .find_pll = intel_g4x_find_best_PLL,
311};
312
273e27ca 313/* LVDS 100mhz refclk limits. */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
0206e353 322 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 325 .find_pll = intel_g4x_find_best_PLL,
326};
327
328static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
0206e353 336 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 339 .find_pll = intel_g4x_find_best_PLL,
340};
341
a0c4da24
JB		 342static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
75e53986 350 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
354};
355
356static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
368};
369
370static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 373 .n = { .min = 1, .max = 7 },
74a4dd2e 374 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
75e53986 378 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
382};
383
57f350b6
JB		 384u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
385{
09153000 386 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 387
57f350b6
JB		 388 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
389 DRM_ERROR("DPIO idle wait timed out\n");
09153000 390 return 0;
57f350b6
JB		 391 }
392
393 I915_WRITE(DPIO_REG, reg);
394 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
395 DPIO_BYTE);
396 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
397 DRM_ERROR("DPIO read wait timed out\n");
09153000 398 return 0;
57f350b6 399 }
57f350b6 400
09153000 401 return I915_READ(DPIO_DATA);
57f350b6
JB		 402}
403
e2fa6fba 404void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
a0c4da24 405{
09153000 406 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 407
a0c4da24
JB		 408 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
409 DRM_ERROR("DPIO idle wait timed out\n");
09153000 410 return;
a0c4da24
JB		 411 }
412
413 I915_WRITE(DPIO_DATA, val);
414 I915_WRITE(DPIO_REG, reg);
415 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
416 DPIO_BYTE);
417 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
418 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 419}
420
1b894b59
CW		 421static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
422 int refclk)
2c07245f 423{
b91ad0ec 424 struct drm_device *dev = crtc->dev;
2c07245f 425 const intel_limit_t *limit;
b91ad0ec
ZW		 426
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 428 if (intel_is_dual_link_lvds(dev)) {
1b894b59 429 if (refclk == 100000)
b91ad0ec
ZW		 430 limit = &intel_limits_ironlake_dual_lvds_100m;
431 else
432 limit = &intel_limits_ironlake_dual_lvds;
433 } else {
1b894b59 434 if (refclk == 100000)
b91ad0ec
ZW		 435 limit = &intel_limits_ironlake_single_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_single_lvds;
438 }
c6bb3538 439 } else
b91ad0ec 440 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 441
442 return limit;
443}
444
044c7c41
ML		 445static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
446{
447 struct drm_device *dev = crtc->dev;
044c7c41
ML		 448 const intel_limit_t *limit;
449
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 451 if (intel_is_dual_link_lvds(dev))
e4b36699 452 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 453 else
e4b36699 454 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
456 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 457 limit = &intel_limits_g4x_hdmi;
044c7c41 458 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 459 limit = &intel_limits_g4x_sdvo;
044c7c41 460 } else /* The option is for other outputs */
e4b36699 461 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 462
463 return limit;
464}
465
1b894b59 466static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 467{
468 struct drm_device *dev = crtc->dev;
469 const intel_limit_t *limit;
470
bad720ff 471 if (HAS_PCH_SPLIT(dev))
1b894b59 472 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 473 else if (IS_G4X(dev)) {
044c7c41 474 limit = intel_g4x_limit(crtc);
f2b115e6 475 } else if (IS_PINEVIEW(dev)) {
2177832f 476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 477 limit = &intel_limits_pineview_lvds;
2177832f 478 else
f2b115e6 479 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 480 } else if (IS_VALLEYVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
482 limit = &intel_limits_vlv_dac;
483 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
484 limit = &intel_limits_vlv_hdmi;
485 else
486 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 487 } else if (!IS_GEN2(dev)) {
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
489 limit = &intel_limits_i9xx_lvds;
490 else
491 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 492 } else {
493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 494 limit = &intel_limits_i8xx_lvds;
79e53945 495 else
e4b36699 496 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 497 }
498 return limit;
499}
500
f2b115e6
AJ		 501/* m1 is reserved as 0 in Pineview, n is a ring counter */
502static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 503{
2177832f
SL		 504 clock->m = clock->m2 + 2;
505 clock->p = clock->p1 * clock->p2;
506 clock->vco = refclk * clock->m / clock->n;
507 clock->dot = clock->vco / clock->p;
508}
509
7429e9d4
DV		 510static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
511{
512 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
513}
514
2177832f
SL		 515static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
516{
f2b115e6
AJ		 517 if (IS_PINEVIEW(dev)) {
518 pineview_clock(refclk, clock);
2177832f
SL		 519 return;
520 }
7429e9d4 521 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 522 clock->p = clock->p1 * clock->p2;
523 clock->vco = refclk * clock->m / (clock->n + 2);
524 clock->dot = clock->vco / clock->p;
525}
526
79e53945
JB		 527/**
528 * Returns whether any output on the specified pipe is of the specified type
529 */
4ef69c7a 530bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 531{
4ef69c7a 532 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 533 struct intel_encoder *encoder;
534
6c2b7c12
DV		 535 for_each_encoder_on_crtc(dev, crtc, encoder)
536 if (encoder->type == type)
4ef69c7a
CW		 537 return true;
538
539 return false;
79e53945
JB		 540}
541
7c04d1d9 542#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 543/**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
1b894b59
CW		 548static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
79e53945 551{
79e53945 552 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 553 INTELPllInvalid("p1 out of range\n");
79e53945 554 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 555 INTELPllInvalid("p out of range\n");
79e53945 556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 557 INTELPllInvalid("m2 out of range\n");
79e53945 558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 559 INTELPllInvalid("m1 out of range\n");
f2b115e6 560 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 561 INTELPllInvalid("m1 <= m2\n");
79e53945 562 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 563 INTELPllInvalid("m out of range\n");
79e53945 564 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 565 INTELPllInvalid("n out of range\n");
79e53945 566 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 567 INTELPllInvalid("vco out of range\n");
79e53945
JB		 568 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
569 * connector, etc., rather than just a single range.
570 */
571 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 572 INTELPllInvalid("dot out of range\n");
79e53945
JB		 573
574 return true;
575}
576
d4906093
ML		 577static bool
578intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 579 int target, int refclk, intel_clock_t *match_clock,
580 intel_clock_t *best_clock)
d4906093 581
79e53945
JB		 582{
583 struct drm_device *dev = crtc->dev;
79e53945 584 intel_clock_t clock;
79e53945
JB		 585 int err = target;
586
a210b028 587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 588 /*
a210b028
DV		 589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
79e53945 592 */
1974cad0 593 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 594 clock.p2 = limit->p2.p2_fast;
595 else
596 clock.p2 = limit->p2.p2_slow;
597 } else {
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
600 else
601 clock.p2 = limit->p2.p2_fast;
602 }
603
0206e353 604 memset(best_clock, 0, sizeof(*best_clock));
79e53945 605
42158660
ZY		 606 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
607 clock.m1++) {
608 for (clock.m2 = limit->m2.min;
609 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 610 /* m1 is always 0 in Pineview */
611 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 612 break;
613 for (clock.n = limit->n.min;
614 clock.n <= limit->n.max; clock.n++) {
615 for (clock.p1 = limit->p1.min;
616 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 617 int this_err;
618
2177832f 619 intel_clock(dev, refclk, &clock);
1b894b59
CW		 620 if (!intel_PLL_is_valid(dev, limit,
621 &clock))
79e53945 622 continue;
cec2f356
SP		 623 if (match_clock &&
624 clock.p != match_clock->p)
625 continue;
79e53945
JB		 626
627 this_err = abs(clock.dot - target);
628 if (this_err < err) {
629 *best_clock = clock;
630 err = this_err;
631 }
632 }
633 }
634 }
635 }
636
637 return (err != target);
638}
639
d4906093
ML		 640static bool
641intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
d4906093
ML		 644{
645 struct drm_device *dev = crtc->dev;
d4906093
ML		 646 intel_clock_t clock;
647 int max_n;
648 bool found;
6ba770dc
AJ		 649 /* approximately equals target * 0.00585 */
650 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 651 found = false;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 654 int lvds_reg;
655
c619eed4 656 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 657 lvds_reg = PCH_LVDS;
658 else
659 lvds_reg = LVDS;
1974cad0 660 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 661 clock.p2 = limit->p2.p2_fast;
662 else
663 clock.p2 = limit->p2.p2_slow;
664 } else {
665 if (target < limit->p2.dot_limit)
666 clock.p2 = limit->p2.p2_slow;
667 else
668 clock.p2 = limit->p2.p2_fast;
669 }
670
671 memset(best_clock, 0, sizeof(*best_clock));
672 max_n = limit->n.max;
f77f13e2 673 /* based on hardware requirement, prefer smaller n to precision */
d4906093 674 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 675 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 676 for (clock.m1 = limit->m1.max;
677 clock.m1 >= limit->m1.min; clock.m1--) {
678 for (clock.m2 = limit->m2.max;
679 clock.m2 >= limit->m2.min; clock.m2--) {
680 for (clock.p1 = limit->p1.max;
681 clock.p1 >= limit->p1.min; clock.p1--) {
682 int this_err;
683
2177832f 684 intel_clock(dev, refclk, &clock);
1b894b59
CW		 685 if (!intel_PLL_is_valid(dev, limit,
686 &clock))
d4906093 687 continue;
cec2f356
SP		 688 if (match_clock &&
689 clock.p != match_clock->p)
690 continue;
1b894b59
CW		 691
692 this_err = abs(clock.dot - target);
d4906093
ML		 693 if (this_err < err_most) {
694 *best_clock = clock;
695 err_most = this_err;
696 max_n = clock.n;
697 found = true;
698 }
699 }
700 }
701 }
702 }
2c07245f
ZW		 703 return found;
704}
705
a0c4da24
JB		 706static bool
707intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
708 int target, int refclk, intel_clock_t *match_clock,
709 intel_clock_t *best_clock)
710{
711 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
712 u32 m, n, fastclk;
713 u32 updrate, minupdate, fracbits, p;
714 unsigned long bestppm, ppm, absppm;
715 int dotclk, flag;
716
af447bd3 717 flag = 0;
a0c4da24
JB		 718 dotclk = target * 1000;
719 bestppm = 1000000;
720 ppm = absppm = 0;
721 fastclk = dotclk / (2*100);
722 updrate = 0;
723 minupdate = 19200;
724 fracbits = 1;
725 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
726 bestm1 = bestm2 = bestp1 = bestp2 = 0;
727
728 /* based on hardware requirement, prefer smaller n to precision */
729 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
730 updrate = refclk / n;
731 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
732 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
733 if (p2 > 10)
734 p2 = p2 - 1;
735 p = p1 * p2;
736 /* based on hardware requirement, prefer bigger m1,m2 values */
737 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
738 m2 = (((2*(fastclk * p * n / m1 )) +
739 refclk) / (2*refclk));
740 m = m1 * m2;
741 vco = updrate * m;
742 if (vco >= limit->vco.min && vco < limit->vco.max) {
743 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
744 absppm = (ppm > 0) ? ppm : (-ppm);
745 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
746 bestppm = 0;
747 flag = 1;
748 }
749 if (absppm < bestppm - 10) {
750 bestppm = absppm;
751 flag = 1;
752 }
753 if (flag) {
754 bestn = n;
755 bestm1 = m1;
756 bestm2 = m2;
757 bestp1 = p1;
758 bestp2 = p2;
759 flag = 0;
760 }
761 }
762 }
763 }
764 }
765 }
766 best_clock->n = bestn;
767 best_clock->m1 = bestm1;
768 best_clock->m2 = bestm2;
769 best_clock->p1 = bestp1;
770 best_clock->p2 = bestp2;
771
772 return true;
773}
a4fc5ed6 774
a5c961d1
PZ		 775enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
776 enum pipe pipe)
777{
778 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
780
3b117c8f 781 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 782}
783
a928d536
PZ		 784static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
785{
786 struct drm_i915_private *dev_priv = dev->dev_private;
787 u32 frame, frame_reg = PIPEFRAME(pipe);
788
789 frame = I915_READ(frame_reg);
790
791 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
792 DRM_DEBUG_KMS("vblank wait timed out\n");
793}
794
9d0498a2
JB		 795/**
796 * intel_wait_for_vblank - wait for vblank on a given pipe
797 * @dev: drm device
798 * @pipe: pipe to wait for
799 *
800 * Wait for vblank to occur on a given pipe. Needed for various bits of
801 * mode setting code.
802 */
803void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 804{
9d0498a2 805 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 806 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 807
a928d536
PZ		 808 if (INTEL_INFO(dev)->gen >= 5) {
809 ironlake_wait_for_vblank(dev, pipe);
810 return;
811 }
812
300387c0
CW		 813 /* Clear existing vblank status. Note this will clear any other
814 * sticky status fields as well.
815 *
816 * This races with i915_driver_irq_handler() with the result
817 * that either function could miss a vblank event. Here it is not
818 * fatal, as we will either wait upon the next vblank interrupt or
819 * timeout. Generally speaking intel_wait_for_vblank() is only
820 * called during modeset at which time the GPU should be idle and
821 * should *not* be performing page flips and thus not waiting on
822 * vblanks...
823 * Currently, the result of us stealing a vblank from the irq
824 * handler is that a single frame will be skipped during swapbuffers.
825 */
826 I915_WRITE(pipestat_reg,
827 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
828
9d0498a2 829 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 830 if (wait_for(I915_READ(pipestat_reg) &
831 PIPE_VBLANK_INTERRUPT_STATUS,
832 50))
9d0498a2
JB		 833 DRM_DEBUG_KMS("vblank wait timed out\n");
834}
835
ab7ad7f6
KP		 836/*
837 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 838 * @dev: drm device
839 * @pipe: pipe to wait for
840 *
841 * After disabling a pipe, we can't wait for vblank in the usual way,
842 * spinning on the vblank interrupt status bit, since we won't actually
843 * see an interrupt when the pipe is disabled.
844 *
ab7ad7f6
KP		 845 * On Gen4 and above:
846 * wait for the pipe register state bit to turn off
847 *
848 * Otherwise:
849 * wait for the display line value to settle (it usually
850 * ends up stopping at the start of the next frame).
58e10eb9 851 *
9d0498a2 852 */
58e10eb9 853void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 854{
855 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 856 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
857 pipe);
ab7ad7f6
KP		 858
859 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 860 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 861
862 /* Wait for the Pipe State to go off */
58e10eb9
CW		 863 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
864 100))
284637d9 865 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 866 } else {
837ba00f 867 u32 last_line, line_mask;
58e10eb9 868 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 869 unsigned long timeout = jiffies + msecs_to_jiffies(100);
870
837ba00f
PZ		 871 if (IS_GEN2(dev))
872 line_mask = DSL_LINEMASK_GEN2;
873 else
874 line_mask = DSL_LINEMASK_GEN3;
875
ab7ad7f6
KP		 876 /* Wait for the display line to settle */
877 do {
837ba00f 878 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 879 mdelay(5);
837ba00f 880 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 881 time_after(timeout, jiffies));
882 if (time_after(jiffies, timeout))
284637d9 883 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 884 }
79e53945
JB		 885}
886
b0ea7d37
DL		 887/*
888 * ibx_digital_port_connected - is the specified port connected?
889 * @dev_priv: i915 private structure
890 * @port: the port to test
891 *
892 * Returns true if @port is connected, false otherwise.
893 */
894bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
895 struct intel_digital_port *port)
896{
897 u32 bit;
898
c36346e3
DL		 899 if (HAS_PCH_IBX(dev_priv->dev)) {
900 switch(port->port) {
901 case PORT_B:
902 bit = SDE_PORTB_HOTPLUG;
903 break;
904 case PORT_C:
905 bit = SDE_PORTC_HOTPLUG;
906 break;
907 case PORT_D:
908 bit = SDE_PORTD_HOTPLUG;
909 break;
910 default:
911 return true;
912 }
913 } else {
914 switch(port->port) {
915 case PORT_B:
916 bit = SDE_PORTB_HOTPLUG_CPT;
917 break;
918 case PORT_C:
919 bit = SDE_PORTC_HOTPLUG_CPT;
920 break;
921 case PORT_D:
922 bit = SDE_PORTD_HOTPLUG_CPT;
923 break;
924 default:
925 return true;
926 }
b0ea7d37
DL		 927 }
928
929 return I915_READ(SDEISR) & bit;
930}
931
b24e7179
JB		 932static const char *state_string(bool enabled)
933{
934 return enabled ? "on" : "off";
935}
936
937/* Only for pre-ILK configs */
938static void assert_pll(struct drm_i915_private *dev_priv,
939 enum pipe pipe, bool state)
940{
941 int reg;
942 u32 val;
943 bool cur_state;
944
945 reg = DPLL(pipe);
946 val = I915_READ(reg);
947 cur_state = !!(val & DPLL_VCO_ENABLE);
948 WARN(cur_state != state,
949 "PLL state assertion failure (expected %s, current %s)\n",
950 state_string(state), state_string(cur_state));
951}
952#define assert_pll_enabled(d, p) assert_pll(d, p, true)
953#define assert_pll_disabled(d, p) assert_pll(d, p, false)
954
040484af
JB		 955/* For ILK+ */
956static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 957 struct intel_pch_pll *pll,
958 struct intel_crtc *crtc,
959 bool state)
040484af 960{
040484af
JB		 961 u32 val;
962 bool cur_state;
963
9d82aa17
ED		 964 if (HAS_PCH_LPT(dev_priv->dev)) {
965 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
966 return;
967 }
968
92b27b08
CW		 969 if (WARN (!pll,
970 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 971 return;
ee7b9f93 972
92b27b08
CW		 973 val = I915_READ(pll->pll_reg);
974 cur_state = !!(val & DPLL_VCO_ENABLE);
975 WARN(cur_state != state,
976 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
977 pll->pll_reg, state_string(state), state_string(cur_state), val);
978
979 /* Make sure the selected PLL is correctly attached to the transcoder */
980 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 981 u32 pch_dpll;
982
983 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 984 cur_state = pll->pll_reg == _PCH_DPLL_B;
985 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 986 "PLL[%d] not attached to this transcoder %c: %08x\n",
987 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 988 cur_state = !!(val >> (4*crtc->pipe + 3));
989 WARN(cur_state != state,
4bb6f1f3 990 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 991 pll->pll_reg == _PCH_DPLL_B,
992 state_string(state),
4bb6f1f3 993 pipe_name(crtc->pipe),
92b27b08
CW		 994 val);
995 }
d3ccbe86 996 }
040484af 997}
92b27b08
CW		 998#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
999#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1000
1001static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1002 enum pipe pipe, bool state)
1003{
1004 int reg;
1005 u32 val;
1006 bool cur_state;
ad80a810
PZ		 1007 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1008 pipe);
040484af 1009
affa9354
PZ		 1010 if (HAS_DDI(dev_priv->dev)) {
1011 /* DDI does not have a specific FDI_TX register */
ad80a810 1012 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1013 val = I915_READ(reg);
ad80a810 1014 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1015 } else {
1016 reg = FDI_TX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_TX_ENABLE);
1019 }
040484af
JB		 1020 WARN(cur_state != state,
1021 "FDI TX state assertion failure (expected %s, current %s)\n",
1022 state_string(state), state_string(cur_state));
1023}
1024#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1025#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1026
1027static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1028 enum pipe pipe, bool state)
1029{
1030 int reg;
1031 u32 val;
1032 bool cur_state;
1033
d63fa0dc
PZ		 1034 reg = FDI_RX_CTL(pipe);
1035 val = I915_READ(reg);
1036 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1037 WARN(cur_state != state,
1038 "FDI RX state assertion failure (expected %s, current %s)\n",
1039 state_string(state), state_string(cur_state));
1040}
1041#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1042#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1043
1044static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1045 enum pipe pipe)
1046{
1047 int reg;
1048 u32 val;
1049
1050 /* ILK FDI PLL is always enabled */
1051 if (dev_priv->info->gen == 5)
1052 return;
1053
bf507ef7 1054 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1055 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1056 return;
1057
040484af
JB		 1058 reg = FDI_TX_CTL(pipe);
1059 val = I915_READ(reg);
1060 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1061}
1062
1063static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1064 enum pipe pipe)
1065{
1066 int reg;
1067 u32 val;
1068
1069 reg = FDI_RX_CTL(pipe);
1070 val = I915_READ(reg);
1071 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1072}
1073
ea0760cf
JB		 1074static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1075 enum pipe pipe)
1076{
1077 int pp_reg, lvds_reg;
1078 u32 val;
1079 enum pipe panel_pipe = PIPE_A;
0de3b485 1080 bool locked = true;
ea0760cf
JB		 1081
1082 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1083 pp_reg = PCH_PP_CONTROL;
1084 lvds_reg = PCH_LVDS;
1085 } else {
1086 pp_reg = PP_CONTROL;
1087 lvds_reg = LVDS;
1088 }
1089
1090 val = I915_READ(pp_reg);
1091 if (!(val & PANEL_POWER_ON) ||
1092 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1093 locked = false;
1094
1095 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1096 panel_pipe = PIPE_B;
1097
1098 WARN(panel_pipe == pipe && locked,
1099 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1100 pipe_name(pipe));
ea0760cf
JB		 1101}
1102
b840d907
JB		 1103void assert_pipe(struct drm_i915_private *dev_priv,
1104 enum pipe pipe, bool state)
b24e7179
JB		 1105{
1106 int reg;
1107 u32 val;
63d7bbe9 1108 bool cur_state;
702e7a56
PZ		 1109 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1110 pipe);
b24e7179 1111
8e636784
DV		 1112 /* if we need the pipe A quirk it must be always on */
1113 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1114 state = true;
1115
15d199ea
PZ		 1116 if (!intel_using_power_well(dev_priv->dev) &&
1117 cpu_transcoder != TRANSCODER_EDP) {
69310161
PZ		 1118 cur_state = false;
1119 } else {
1120 reg = PIPECONF(cpu_transcoder);
1121 val = I915_READ(reg);
1122 cur_state = !!(val & PIPECONF_ENABLE);
1123 }
1124
63d7bbe9
JB		 1125 WARN(cur_state != state,
1126 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1127 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1128}
1129
931872fc
CW		 1130static void assert_plane(struct drm_i915_private *dev_priv,
1131 enum plane plane, bool state)
b24e7179
JB		 1132{
1133 int reg;
1134 u32 val;
931872fc 1135 bool cur_state;
b24e7179
JB		 1136
1137 reg = DSPCNTR(plane);
1138 val = I915_READ(reg);
931872fc
CW		 1139 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1140 WARN(cur_state != state,
1141 "plane %c assertion failure (expected %s, current %s)\n",
1142 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1143}
1144
931872fc
CW		 1145#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1146#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1147
b24e7179
JB		 1148static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1149 enum pipe pipe)
1150{
1151 int reg, i;
1152 u32 val;
1153 int cur_pipe;
1154
19ec1358 1155 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1156 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1157 reg = DSPCNTR(pipe);
1158 val = I915_READ(reg);
1159 WARN((val & DISPLAY_PLANE_ENABLE),
1160 "plane %c assertion failure, should be disabled but not\n",
1161 plane_name(pipe));
19ec1358 1162 return;
28c05794 1163 }
19ec1358 1164
b24e7179
JB		 1165 /* Need to check both planes against the pipe */
1166 for (i = 0; i < 2; i++) {
1167 reg = DSPCNTR(i);
1168 val = I915_READ(reg);
1169 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1170 DISPPLANE_SEL_PIPE_SHIFT;
1171 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1172 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1173 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1174 }
1175}
1176
19332d7a
JB		 1177static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179{
1180 int reg, i;
1181 u32 val;
1182
1183 if (!IS_VALLEYVIEW(dev_priv->dev))
1184 return;
1185
1186 /* Need to check both planes against the pipe */
1187 for (i = 0; i < dev_priv->num_plane; i++) {
1188 reg = SPCNTR(pipe, i);
1189 val = I915_READ(reg);
1190 WARN((val & SP_ENABLE),
06da8da2
VS		 1191 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1192 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1193 }
1194}
1195
92f2584a
JB		 1196static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1197{
1198 u32 val;
1199 bool enabled;
1200
9d82aa17
ED		 1201 if (HAS_PCH_LPT(dev_priv->dev)) {
1202 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1203 return;
1204 }
1205
92f2584a
JB		 1206 val = I915_READ(PCH_DREF_CONTROL);
1207 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1208 DREF_SUPERSPREAD_SOURCE_MASK));
1209 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1210}
1211
1212static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1213 enum pipe pipe)
1214{
1215 int reg;
1216 u32 val;
1217 bool enabled;
1218
1219 reg = TRANSCONF(pipe);
1220 val = I915_READ(reg);
1221 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1222 WARN(enabled,
1223 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1224 pipe_name(pipe));
92f2584a
JB		 1225}
1226
4e634389
KP		 1227static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1229{
1230 if ((val & DP_PORT_EN) == 0)
1231 return false;
1232
1233 if (HAS_PCH_CPT(dev_priv->dev)) {
1234 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1235 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1236 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1237 return false;
1238 } else {
1239 if ((val & DP_PIPE_MASK) != (pipe << 30))
1240 return false;
1241 }
1242 return true;
1243}
1244
1519b995
KP		 1245static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 val)
1247{
dc0fa718 1248 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1252 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1253 return false;
1254 } else {
dc0fa718 1255 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1256 return false;
1257 }
1258 return true;
1259}
1260
1261static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1262 enum pipe pipe, u32 val)
1263{
1264 if ((val & LVDS_PORT_EN) == 0)
1265 return false;
1266
1267 if (HAS_PCH_CPT(dev_priv->dev)) {
1268 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1269 return false;
1270 } else {
1271 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1272 return false;
1273 }
1274 return true;
1275}
1276
1277static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1278 enum pipe pipe, u32 val)
1279{
1280 if ((val & ADPA_DAC_ENABLE) == 0)
1281 return false;
1282 if (HAS_PCH_CPT(dev_priv->dev)) {
1283 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1284 return false;
1285 } else {
1286 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1287 return false;
1288 }
1289 return true;
1290}
1291
291906f1 1292static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1293 enum pipe pipe, int reg, u32 port_sel)
291906f1 1294{
47a05eca 1295 u32 val = I915_READ(reg);
4e634389 1296 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1297 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1298 reg, pipe_name(pipe));
de9a35ab 1299
75c5da27
DV		 1300 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1301 && (val & DP_PIPEB_SELECT),
de9a35ab 1302 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1303}
1304
1305static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1306 enum pipe pipe, int reg)
1307{
47a05eca 1308 u32 val = I915_READ(reg);
b70ad586 1309 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1310 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1311 reg, pipe_name(pipe));
de9a35ab 1312
dc0fa718 1313 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1314 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1315 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1316}
1317
1318static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1319 enum pipe pipe)
1320{
1321 int reg;
1322 u32 val;
291906f1 1323
f0575e92
KP		 1324 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1325 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1326 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1327
1328 reg = PCH_ADPA;
1329 val = I915_READ(reg);
b70ad586 1330 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1331 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1332 pipe_name(pipe));
291906f1
JB		 1333
1334 reg = PCH_LVDS;
1335 val = I915_READ(reg);
b70ad586 1336 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1337 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1338 pipe_name(pipe));
291906f1 1339
e2debe91
PZ		 1340 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1341 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1342 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1343}
1344
63d7bbe9
JB		 1345/**
1346 * intel_enable_pll - enable a PLL
1347 * @dev_priv: i915 private structure
1348 * @pipe: pipe PLL to enable
1349 *
1350 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1351 * make sure the PLL reg is writable first though, since the panel write
1352 * protect mechanism may be enabled.
1353 *
1354 * Note! This is for pre-ILK only.
7434a255
TR		 1355 *
1356 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1357 */
1358static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1359{
1360 int reg;
1361 u32 val;
1362
58c6eaa2
DV		 1363 assert_pipe_disabled(dev_priv, pipe);
1364
63d7bbe9 1365 /* No really, not for ILK+ */
a0c4da24 1366 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1367
1368 /* PLL is protected by panel, make sure we can write it */
1369 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1370 assert_panel_unlocked(dev_priv, pipe);
1371
1372 reg = DPLL(pipe);
1373 val = I915_READ(reg);
1374 val |= DPLL_VCO_ENABLE;
1375
1376 /* We do this three times for luck */
1377 I915_WRITE(reg, val);
1378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
1380 I915_WRITE(reg, val);
1381 POSTING_READ(reg);
1382 udelay(150); /* wait for warmup */
1383 I915_WRITE(reg, val);
1384 POSTING_READ(reg);
1385 udelay(150); /* wait for warmup */
1386}
1387
1388/**
1389 * intel_disable_pll - disable a PLL
1390 * @dev_priv: i915 private structure
1391 * @pipe: pipe PLL to disable
1392 *
1393 * Disable the PLL for @pipe, making sure the pipe is off first.
1394 *
1395 * Note! This is for pre-ILK only.
1396 */
1397static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1398{
1399 int reg;
1400 u32 val;
1401
1402 /* Don't disable pipe A or pipe A PLLs if needed */
1403 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1404 return;
1405
1406 /* Make sure the pipe isn't still relying on us */
1407 assert_pipe_disabled(dev_priv, pipe);
1408
1409 reg = DPLL(pipe);
1410 val = I915_READ(reg);
1411 val &= ~DPLL_VCO_ENABLE;
1412 I915_WRITE(reg, val);
1413 POSTING_READ(reg);
1414}
1415
a416edef
ED		 1416/* SBI access */
1417static void
988d6ee8
PZ		 1418intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1419 enum intel_sbi_destination destination)
a416edef 1420{
988d6ee8 1421 u32 tmp;
a416edef 1422
09153000 1423 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1424
39fb50f6 1425 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1426 100)) {
1427 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1428 return;
a416edef
ED		 1429 }
1430
988d6ee8
PZ		 1431 I915_WRITE(SBI_ADDR, (reg << 16));
1432 I915_WRITE(SBI_DATA, value);
1433
1434 if (destination == SBI_ICLK)
1435 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1436 else
1437 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1438 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1439
39fb50f6 1440 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1441 100)) {
1442 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1443 return;
a416edef 1444 }
a416edef
ED		 1445}
1446
1447static u32
988d6ee8
PZ		 1448intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1449 enum intel_sbi_destination destination)
a416edef 1450{
39fb50f6 1451 u32 value = 0;
09153000 1452 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1453
39fb50f6 1454 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1455 100)) {
1456 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1457 return 0;
a416edef
ED		 1458 }
1459
988d6ee8
PZ		 1460 I915_WRITE(SBI_ADDR, (reg << 16));
1461
1462 if (destination == SBI_ICLK)
1463 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1464 else
1465 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1466 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1467
39fb50f6 1468 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1469 100)) {
1470 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1471 return 0;
a416edef
ED		 1472 }
1473
09153000 1474 return I915_READ(SBI_DATA);
a416edef
ED		 1475}
1476
89b667f8
JB		 1477void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1478{
1479 u32 port_mask;
1480
1481 if (!port)
1482 port_mask = DPLL_PORTB_READY_MASK;
1483 else
1484 port_mask = DPLL_PORTC_READY_MASK;
1485
1486 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1487 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1488 'B' + port, I915_READ(DPLL(0)));
1489}
1490
92f2584a 1491/**
b6b4e185 1492 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1493 * @dev_priv: i915 private structure
1494 * @pipe: pipe PLL to enable
1495 *
1496 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1497 * drives the transcoder clock.
1498 */
b6b4e185 1499static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1500{
ee7b9f93 1501 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1502 struct intel_pch_pll *pll;
92f2584a
JB		 1503 int reg;
1504 u32 val;
1505
48da64a8 1506 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1507 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1508 pll = intel_crtc->pch_pll;
1509 if (pll == NULL)
1510 return;
1511
1512 if (WARN_ON(pll->refcount == 0))
1513 return;
ee7b9f93
JB		 1514
1515 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1516 pll->pll_reg, pll->active, pll->on,
1517 intel_crtc->base.base.id);
92f2584a
JB		 1518
1519 /* PCH refclock must be enabled first */
1520 assert_pch_refclk_enabled(dev_priv);
1521
ee7b9f93 1522 if (pll->active++ && pll->on) {
92b27b08 1523 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1524 return;
1525 }
1526
1527 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1528
1529 reg = pll->pll_reg;
92f2584a
JB		 1530 val = I915_READ(reg);
1531 val |= DPLL_VCO_ENABLE;
1532 I915_WRITE(reg, val);
1533 POSTING_READ(reg);
1534 udelay(200);
ee7b9f93
JB		 1535
1536 pll->on = true;
92f2584a
JB		 1537}
1538
ee7b9f93 1539static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1540{
ee7b9f93
JB		 1541 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1542 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1543 int reg;
ee7b9f93 1544 u32 val;
4c609cb8 1545
92f2584a
JB		 1546 /* PCH only available on ILK+ */
1547 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1548 if (pll == NULL)
1549 return;
92f2584a 1550
48da64a8
CW		 1551 if (WARN_ON(pll->refcount == 0))
1552 return;
7a419866 1553
ee7b9f93
JB		 1554 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1555 pll->pll_reg, pll->active, pll->on,
1556 intel_crtc->base.base.id);
7a419866 1557
48da64a8 1558 if (WARN_ON(pll->active == 0)) {
92b27b08 1559 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1560 return;
1561 }
1562
ee7b9f93 1563 if (--pll->active) {
92b27b08 1564 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1565 return;
ee7b9f93
JB		 1566 }
1567
1568 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1569
1570 /* Make sure transcoder isn't still depending on us */
1571 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1572
ee7b9f93 1573 reg = pll->pll_reg;
92f2584a
JB		 1574 val = I915_READ(reg);
1575 val &= ~DPLL_VCO_ENABLE;
1576 I915_WRITE(reg, val);
1577 POSTING_READ(reg);
1578 udelay(200);
ee7b9f93
JB		 1579
1580 pll->on = false;
92f2584a
JB		 1581}
1582
b8a4f404
PZ		 1583static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1584 enum pipe pipe)
040484af 1585{
23670b32 1586 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1587 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1588 uint32_t reg, val, pipeconf_val;
040484af
JB		 1589
1590 /* PCH only available on ILK+ */
1591 BUG_ON(dev_priv->info->gen < 5);
1592
1593 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1594 assert_pch_pll_enabled(dev_priv,
1595 to_intel_crtc(crtc)->pch_pll,
1596 to_intel_crtc(crtc));
040484af
JB		 1597
1598 /* FDI must be feeding us bits for PCH ports */
1599 assert_fdi_tx_enabled(dev_priv, pipe);
1600 assert_fdi_rx_enabled(dev_priv, pipe);
1601
23670b32
DV		 1602 if (HAS_PCH_CPT(dev)) {
1603 /* Workaround: Set the timing override bit before enabling the
1604 * pch transcoder. */
1605 reg = TRANS_CHICKEN2(pipe);
1606 val = I915_READ(reg);
1607 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1608 I915_WRITE(reg, val);
59c859d6 1609 }
23670b32 1610
040484af
JB		 1611 reg = TRANSCONF(pipe);
1612 val = I915_READ(reg);
5f7f726d 1613 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1614
1615 if (HAS_PCH_IBX(dev_priv->dev)) {
1616 /*
1617 * make the BPC in transcoder be consistent with
1618 * that in pipeconf reg.
1619 */
dfd07d72
DV		 1620 val &= ~PIPECONF_BPC_MASK;
1621 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1622 }
5f7f726d
PZ		 1623
1624 val &= ~TRANS_INTERLACE_MASK;
1625 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1626 if (HAS_PCH_IBX(dev_priv->dev) &&
1627 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1628 val |= TRANS_LEGACY_INTERLACED_ILK;
1629 else
1630 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1631 else
1632 val |= TRANS_PROGRESSIVE;
1633
040484af
JB		 1634 I915_WRITE(reg, val | TRANS_ENABLE);
1635 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1636 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1637}
1638
8fb033d7 1639static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1640 enum transcoder cpu_transcoder)
040484af 1641{
8fb033d7 1642 u32 val, pipeconf_val;
8fb033d7
PZ		 1643
1644 /* PCH only available on ILK+ */
1645 BUG_ON(dev_priv->info->gen < 5);
1646
8fb033d7 1647 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1648 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1649 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1650
223a6fdf
PZ		 1651 /* Workaround: set timing override bit. */
1652 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1653 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1654 I915_WRITE(_TRANSA_CHICKEN2, val);
1655
25f3ef11 1656 val = TRANS_ENABLE;
937bb610 1657 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1658
9a76b1c6
PZ		 1659 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1660 PIPECONF_INTERLACED_ILK)
a35f2679 1661 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1662 else
1663 val |= TRANS_PROGRESSIVE;
1664
25f3ef11 1665 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1666 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1667 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1668}
1669
b8a4f404
PZ		 1670static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1671 enum pipe pipe)
040484af 1672{
23670b32
DV		 1673 struct drm_device *dev = dev_priv->dev;
1674 uint32_t reg, val;
040484af
JB		 1675
1676 /* FDI relies on the transcoder */
1677 assert_fdi_tx_disabled(dev_priv, pipe);
1678 assert_fdi_rx_disabled(dev_priv, pipe);
1679
291906f1
JB		 1680 /* Ports must be off as well */
1681 assert_pch_ports_disabled(dev_priv, pipe);
1682
040484af
JB		 1683 reg = TRANSCONF(pipe);
1684 val = I915_READ(reg);
1685 val &= ~TRANS_ENABLE;
1686 I915_WRITE(reg, val);
1687 /* wait for PCH transcoder off, transcoder state */
1688 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1689 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1690
1691 if (!HAS_PCH_IBX(dev)) {
1692 /* Workaround: Clear the timing override chicken bit again. */
1693 reg = TRANS_CHICKEN2(pipe);
1694 val = I915_READ(reg);
1695 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1696 I915_WRITE(reg, val);
1697 }
040484af
JB		 1698}
1699
ab4d966c 1700static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1701{
8fb033d7
PZ		 1702 u32 val;
1703
8a52fd9f 1704 val = I915_READ(_TRANSACONF);
8fb033d7 1705 val &= ~TRANS_ENABLE;
8a52fd9f 1706 I915_WRITE(_TRANSACONF, val);
8fb033d7 1707 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1708 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1709 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1710
1711 /* Workaround: clear timing override bit. */
1712 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1713 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1714 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1715}
1716
b24e7179 1717/**
309cfea8 1718 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1719 * @dev_priv: i915 private structure
1720 * @pipe: pipe to enable
040484af 1721 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1722 *
1723 * Enable @pipe, making sure that various hardware specific requirements
1724 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1725 *
1726 * @pipe should be %PIPE_A or %PIPE_B.
1727 *
1728 * Will wait until the pipe is actually running (i.e. first vblank) before
1729 * returning.
1730 */
040484af
JB		 1731static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1732 bool pch_port)
b24e7179 1733{
702e7a56
PZ		 1734 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1735 pipe);
1a240d4d 1736 enum pipe pch_transcoder;
b24e7179
JB		 1737 int reg;
1738 u32 val;
1739
58c6eaa2
DV		 1740 assert_planes_disabled(dev_priv, pipe);
1741 assert_sprites_disabled(dev_priv, pipe);
1742
681e5811 1743 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1744 pch_transcoder = TRANSCODER_A;
1745 else
1746 pch_transcoder = pipe;
1747
b24e7179
JB		 1748 /*
1749 * A pipe without a PLL won't actually be able to drive bits from
1750 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1751 * need the check.
1752 */
1753 if (!HAS_PCH_SPLIT(dev_priv->dev))
1754 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1755 else {
1756 if (pch_port) {
1757 /* if driving the PCH, we need FDI enabled */
cc391bbb 1758 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1759 assert_fdi_tx_pll_enabled(dev_priv,
1760 (enum pipe) cpu_transcoder);
040484af
JB		 1761 }
1762 /* FIXME: assert CPU port conditions for SNB+ */
1763 }
b24e7179 1764
702e7a56 1765 reg = PIPECONF(cpu_transcoder);
b24e7179 1766 val = I915_READ(reg);
00d70b15
CW		 1767 if (val & PIPECONF_ENABLE)
1768 return;
1769
1770 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1771 intel_wait_for_vblank(dev_priv->dev, pipe);
1772}
1773
1774/**
309cfea8 1775 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1776 * @dev_priv: i915 private structure
1777 * @pipe: pipe to disable
1778 *
1779 * Disable @pipe, making sure that various hardware specific requirements
1780 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1781 *
1782 * @pipe should be %PIPE_A or %PIPE_B.
1783 *
1784 * Will wait until the pipe has shut down before returning.
1785 */
1786static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1787 enum pipe pipe)
1788{
702e7a56
PZ		 1789 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1790 pipe);
b24e7179
JB		 1791 int reg;
1792 u32 val;
1793
1794 /*
1795 * Make sure planes won't keep trying to pump pixels to us,
1796 * or we might hang the display.
1797 */
1798 assert_planes_disabled(dev_priv, pipe);
19332d7a 1799 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1800
1801 /* Don't disable pipe A or pipe A PLLs if needed */
1802 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1803 return;
1804
702e7a56 1805 reg = PIPECONF(cpu_transcoder);
b24e7179 1806 val = I915_READ(reg);
00d70b15
CW		 1807 if ((val & PIPECONF_ENABLE) == 0)
1808 return;
1809
1810 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1811 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1812}
1813
d74362c9
KP		 1814/*
1815 * Plane regs are double buffered, going from enabled->disabled needs a
1816 * trigger in order to latch. The display address reg provides this.
1817 */
6f1d69b0 1818void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1819 enum plane plane)
1820{
14f86147
DL		 1821 if (dev_priv->info->gen >= 4)
1822 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1823 else
1824 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1825}
1826
b24e7179
JB		 1827/**
1828 * intel_enable_plane - enable a display plane on a given pipe
1829 * @dev_priv: i915 private structure
1830 * @plane: plane to enable
1831 * @pipe: pipe being fed
1832 *
1833 * Enable @plane on @pipe, making sure that @pipe is running first.
1834 */
1835static void intel_enable_plane(struct drm_i915_private *dev_priv,
1836 enum plane plane, enum pipe pipe)
1837{
1838 int reg;
1839 u32 val;
1840
1841 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1842 assert_pipe_enabled(dev_priv, pipe);
1843
1844 reg = DSPCNTR(plane);
1845 val = I915_READ(reg);
00d70b15
CW		 1846 if (val & DISPLAY_PLANE_ENABLE)
1847 return;
1848
1849 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1850 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1851 intel_wait_for_vblank(dev_priv->dev, pipe);
1852}
1853
b24e7179
JB		 1854/**
1855 * intel_disable_plane - disable a display plane
1856 * @dev_priv: i915 private structure
1857 * @plane: plane to disable
1858 * @pipe: pipe consuming the data
1859 *
1860 * Disable @plane; should be an independent operation.
1861 */
1862static void intel_disable_plane(struct drm_i915_private *dev_priv,
1863 enum plane plane, enum pipe pipe)
1864{
1865 int reg;
1866 u32 val;
1867
1868 reg = DSPCNTR(plane);
1869 val = I915_READ(reg);
00d70b15
CW		 1870 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1871 return;
1872
1873 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1874 intel_flush_display_plane(dev_priv, plane);
1875 intel_wait_for_vblank(dev_priv->dev, pipe);
1876}
1877
693db184
CW		 1878static bool need_vtd_wa(struct drm_device *dev)
1879{
1880#ifdef CONFIG_INTEL_IOMMU
1881 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1882 return true;
1883#endif
1884 return false;
1885}
1886
127bd2ac 1887int
48b956c5 1888intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1889 struct drm_i915_gem_object *obj,
919926ae 1890 struct intel_ring_buffer *pipelined)
6b95a207 1891{
ce453d81 1892 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1893 u32 alignment;
1894 int ret;
1895
05394f39 1896 switch (obj->tiling_mode) {
6b95a207 1897 case I915_TILING_NONE:
534843da
CW		 1898 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1899 alignment = 128 * 1024;
a6c45cf0 1900 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1901 alignment = 4 * 1024;
1902 else
1903 alignment = 64 * 1024;
6b95a207
KH		 1904 break;
1905 case I915_TILING_X:
1906 /* pin() will align the object as required by fence */
1907 alignment = 0;
1908 break;
1909 case I915_TILING_Y:
8bb6e959
DV		 1910 /* Despite that we check this in framebuffer_init userspace can
1911 * screw us over and change the tiling after the fact. Only
1912 * pinned buffers can't change their tiling. */
1913 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1914 return -EINVAL;
1915 default:
1916 BUG();
1917 }
1918
693db184
CW		 1919 /* Note that the w/a also requires 64 PTE of padding following the
1920 * bo. We currently fill all unused PTE with the shadow page and so
1921 * we should always have valid PTE following the scanout preventing
1922 * the VT-d warning.
1923 */
1924 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1925 alignment = 256 * 1024;
1926
ce453d81 1927 dev_priv->mm.interruptible = false;
2da3b9b9 1928 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1929 if (ret)
ce453d81 1930 goto err_interruptible;
6b95a207
KH		 1931
1932 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1933 * fence, whereas 965+ only requires a fence if using
1934 * framebuffer compression. For simplicity, we always install
1935 * a fence as the cost is not that onerous.
1936 */
06d98131 1937 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1938 if (ret)
1939 goto err_unpin;
1690e1eb 1940
9a5a53b3 1941 i915_gem_object_pin_fence(obj);
6b95a207 1942
ce453d81 1943 dev_priv->mm.interruptible = true;
6b95a207 1944 return 0;
48b956c5
CW		 1945
1946err_unpin:
1947 i915_gem_object_unpin(obj);
ce453d81
CW		 1948err_interruptible:
1949 dev_priv->mm.interruptible = true;
48b956c5 1950 return ret;
6b95a207
KH		 1951}
1952
1690e1eb
CW		 1953void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1954{
1955 i915_gem_object_unpin_fence(obj);
1956 i915_gem_object_unpin(obj);
1957}
1958
c2c75131
DV		 1959/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1960 * is assumed to be a power-of-two. */
bc752862
CW		 1961unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1962 unsigned int tiling_mode,
1963 unsigned int cpp,
1964 unsigned int pitch)
c2c75131 1965{
bc752862
CW		 1966 if (tiling_mode != I915_TILING_NONE) {
1967 unsigned int tile_rows, tiles;
c2c75131 1968
bc752862
CW		 1969 tile_rows = *y / 8;
1970 *y %= 8;
c2c75131 1971
bc752862
CW		 1972 tiles = *x / (512/cpp);
1973 *x %= 512/cpp;
1974
1975 return tile_rows * pitch * 8 + tiles * 4096;
1976 } else {
1977 unsigned int offset;
1978
1979 offset = *y * pitch + *x * cpp;
1980 *y = 0;
1981 *x = (offset & 4095) / cpp;
1982 return offset & -4096;
1983 }
c2c75131
DV		 1984}
1985
17638cd6
JB		 1986static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1987 int x, int y)
81255565
JB		 1988{
1989 struct drm_device *dev = crtc->dev;
1990 struct drm_i915_private *dev_priv = dev->dev_private;
1991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1992 struct intel_framebuffer *intel_fb;
05394f39 1993 struct drm_i915_gem_object *obj;
81255565 1994 int plane = intel_crtc->plane;
e506a0c6 1995 unsigned long linear_offset;
81255565 1996 u32 dspcntr;
5eddb70b 1997 u32 reg;
81255565
JB		 1998
1999 switch (plane) {
2000 case 0:
2001 case 1:
2002 break;
2003 default:
84f44ce7 2004 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2005 return -EINVAL;
2006 }
2007
2008 intel_fb = to_intel_framebuffer(fb);
2009 obj = intel_fb->obj;
81255565 2010
5eddb70b
CW		 2011 reg = DSPCNTR(plane);
2012 dspcntr = I915_READ(reg);
81255565
JB		 2013 /* Mask out pixel format bits in case we change it */
2014 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2015 switch (fb->pixel_format) {
2016 case DRM_FORMAT_C8:
81255565
JB		 2017 dspcntr |= DISPPLANE_8BPP;
2018 break;
57779d06
VS		 2019 case DRM_FORMAT_XRGB1555:
2020 case DRM_FORMAT_ARGB1555:
2021 dspcntr |= DISPPLANE_BGRX555;
81255565 2022 break;
57779d06
VS		 2023 case DRM_FORMAT_RGB565:
2024 dspcntr |= DISPPLANE_BGRX565;
2025 break;
2026 case DRM_FORMAT_XRGB8888:
2027 case DRM_FORMAT_ARGB8888:
2028 dspcntr |= DISPPLANE_BGRX888;
2029 break;
2030 case DRM_FORMAT_XBGR8888:
2031 case DRM_FORMAT_ABGR8888:
2032 dspcntr |= DISPPLANE_RGBX888;
2033 break;
2034 case DRM_FORMAT_XRGB2101010:
2035 case DRM_FORMAT_ARGB2101010:
2036 dspcntr |= DISPPLANE_BGRX101010;
2037 break;
2038 case DRM_FORMAT_XBGR2101010:
2039 case DRM_FORMAT_ABGR2101010:
2040 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2041 break;
2042 default:
baba133a 2043 BUG();
81255565 2044 }
57779d06 2045
a6c45cf0 2046 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2047 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2048 dspcntr |= DISPPLANE_TILED;
2049 else
2050 dspcntr &= ~DISPPLANE_TILED;
2051 }
2052
5eddb70b 2053 I915_WRITE(reg, dspcntr);
81255565 2054
e506a0c6 2055 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2056
c2c75131
DV		 2057 if (INTEL_INFO(dev)->gen >= 4) {
2058 intel_crtc->dspaddr_offset =
bc752862
CW		 2059 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2060 fb->bits_per_pixel / 8,
2061 fb->pitches[0]);
c2c75131
DV		 2062 linear_offset -= intel_crtc->dspaddr_offset;
2063 } else {
e506a0c6 2064 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2065 }
e506a0c6
DV		 2066
2067 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2068 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2069 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2070 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2071 I915_MODIFY_DISPBASE(DSPSURF(plane),
2072 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2073 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2074 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2075 } else
e506a0c6 2076 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2077 POSTING_READ(reg);
81255565 2078
17638cd6
JB		 2079 return 0;
2080}
2081
2082static int ironlake_update_plane(struct drm_crtc *crtc,
2083 struct drm_framebuffer *fb, int x, int y)
2084{
2085 struct drm_device *dev = crtc->dev;
2086 struct drm_i915_private *dev_priv = dev->dev_private;
2087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2088 struct intel_framebuffer *intel_fb;
2089 struct drm_i915_gem_object *obj;
2090 int plane = intel_crtc->plane;
e506a0c6 2091 unsigned long linear_offset;
17638cd6
JB		 2092 u32 dspcntr;
2093 u32 reg;
2094
2095 switch (plane) {
2096 case 0:
2097 case 1:
27f8227b 2098 case 2:
17638cd6
JB		 2099 break;
2100 default:
84f44ce7 2101 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2102 return -EINVAL;
2103 }
2104
2105 intel_fb = to_intel_framebuffer(fb);
2106 obj = intel_fb->obj;
2107
2108 reg = DSPCNTR(plane);
2109 dspcntr = I915_READ(reg);
2110 /* Mask out pixel format bits in case we change it */
2111 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2112 switch (fb->pixel_format) {
2113 case DRM_FORMAT_C8:
17638cd6
JB		 2114 dspcntr |= DISPPLANE_8BPP;
2115 break;
57779d06
VS		 2116 case DRM_FORMAT_RGB565:
2117 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2118 break;
57779d06
VS		 2119 case DRM_FORMAT_XRGB8888:
2120 case DRM_FORMAT_ARGB8888:
2121 dspcntr |= DISPPLANE_BGRX888;
2122 break;
2123 case DRM_FORMAT_XBGR8888:
2124 case DRM_FORMAT_ABGR8888:
2125 dspcntr |= DISPPLANE_RGBX888;
2126 break;
2127 case DRM_FORMAT_XRGB2101010:
2128 case DRM_FORMAT_ARGB2101010:
2129 dspcntr |= DISPPLANE_BGRX101010;
2130 break;
2131 case DRM_FORMAT_XBGR2101010:
2132 case DRM_FORMAT_ABGR2101010:
2133 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2134 break;
2135 default:
baba133a 2136 BUG();
17638cd6
JB		 2137 }
2138
2139 if (obj->tiling_mode != I915_TILING_NONE)
2140 dspcntr |= DISPPLANE_TILED;
2141 else
2142 dspcntr &= ~DISPPLANE_TILED;
2143
2144 /* must disable */
2145 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2146
2147 I915_WRITE(reg, dspcntr);
2148
e506a0c6 2149 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2150 intel_crtc->dspaddr_offset =
bc752862
CW		 2151 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2152 fb->bits_per_pixel / 8,
2153 fb->pitches[0]);
c2c75131 2154 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2155
e506a0c6
DV		 2156 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2157 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2158 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2159 I915_MODIFY_DISPBASE(DSPSURF(plane),
2160 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2161 if (IS_HASWELL(dev)) {
2162 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2163 } else {
2164 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2165 I915_WRITE(DSPLINOFF(plane), linear_offset);
2166 }
17638cd6
JB		 2167 POSTING_READ(reg);
2168
2169 return 0;
2170}
2171
2172/* Assume fb object is pinned & idle & fenced and just update base pointers */
2173static int
2174intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2175 int x, int y, enum mode_set_atomic state)
2176{
2177 struct drm_device *dev = crtc->dev;
2178 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2179
6b8e6ed0
CW		 2180 if (dev_priv->display.disable_fbc)
2181 dev_priv->display.disable_fbc(dev);
3dec0095 2182 intel_increase_pllclock(crtc);
81255565 2183
6b8e6ed0 2184 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2185}
2186
96a02917
VS		 2187void intel_display_handle_reset(struct drm_device *dev)
2188{
2189 struct drm_i915_private *dev_priv = dev->dev_private;
2190 struct drm_crtc *crtc;
2191
2192 /*
2193 * Flips in the rings have been nuked by the reset,
2194 * so complete all pending flips so that user space
2195 * will get its events and not get stuck.
2196 *
2197 * Also update the base address of all primary
2198 * planes to the the last fb to make sure we're
2199 * showing the correct fb after a reset.
2200 *
2201 * Need to make two loops over the crtcs so that we
2202 * don't try to grab a crtc mutex before the
2203 * pending_flip_queue really got woken up.
2204 */
2205
2206 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2208 enum plane plane = intel_crtc->plane;
2209
2210 intel_prepare_page_flip(dev, plane);
2211 intel_finish_page_flip_plane(dev, plane);
2212 }
2213
2214 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2216
2217 mutex_lock(&crtc->mutex);
2218 if (intel_crtc->active)
2219 dev_priv->display.update_plane(crtc, crtc->fb,
2220 crtc->x, crtc->y);
2221 mutex_unlock(&crtc->mutex);
2222 }
2223}
2224
14667a4b
CW		 2225static int
2226intel_finish_fb(struct drm_framebuffer *old_fb)
2227{
2228 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2229 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2230 bool was_interruptible = dev_priv->mm.interruptible;
2231 int ret;
2232
14667a4b
CW		 2233 /* Big Hammer, we also need to ensure that any pending
2234 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2235 * current scanout is retired before unpinning the old
2236 * framebuffer.
2237 *
2238 * This should only fail upon a hung GPU, in which case we
2239 * can safely continue.
2240 */
2241 dev_priv->mm.interruptible = false;
2242 ret = i915_gem_object_finish_gpu(obj);
2243 dev_priv->mm.interruptible = was_interruptible;
2244
2245 return ret;
2246}
2247
198598d0
VS		 2248static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2249{
2250 struct drm_device *dev = crtc->dev;
2251 struct drm_i915_master_private *master_priv;
2252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2253
2254 if (!dev->primary->master)
2255 return;
2256
2257 master_priv = dev->primary->master->driver_priv;
2258 if (!master_priv->sarea_priv)
2259 return;
2260
2261 switch (intel_crtc->pipe) {
2262 case 0:
2263 master_priv->sarea_priv->pipeA_x = x;
2264 master_priv->sarea_priv->pipeA_y = y;
2265 break;
2266 case 1:
2267 master_priv->sarea_priv->pipeB_x = x;
2268 master_priv->sarea_priv->pipeB_y = y;
2269 break;
2270 default:
2271 break;
2272 }
2273}
2274
5c3b82e2 2275static int
3c4fdcfb 2276intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2277 struct drm_framebuffer *fb)
79e53945
JB		 2278{
2279 struct drm_device *dev = crtc->dev;
6b8e6ed0 2280 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2282 struct drm_framebuffer *old_fb;
5c3b82e2 2283 int ret;
79e53945
JB		 2284
2285 /* no fb bound */
94352cf9 2286 if (!fb) {
a5071c2f 2287 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2288 return 0;
2289 }
2290
7eb552ae 2291 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2292 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2293 plane_name(intel_crtc->plane),
2294 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2295 return -EINVAL;
79e53945
JB		 2296 }
2297
5c3b82e2 2298 mutex_lock(&dev->struct_mutex);
265db958 2299 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2300 to_intel_framebuffer(fb)->obj,
919926ae 2301 NULL);
5c3b82e2
CW		 2302 if (ret != 0) {
2303 mutex_unlock(&dev->struct_mutex);
a5071c2f 2304 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2305 return ret;
2306 }
79e53945 2307
94352cf9 2308 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2309 if (ret) {
94352cf9 2310 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2311 mutex_unlock(&dev->struct_mutex);
a5071c2f 2312 DRM_ERROR("failed to update base address\n");
4e6cfefc 2313 return ret;
79e53945 2314 }
3c4fdcfb 2315
94352cf9
DV		 2316 old_fb = crtc->fb;
2317 crtc->fb = fb;
6c4c86f5
DV		 2318 crtc->x = x;
2319 crtc->y = y;
94352cf9 2320
b7f1de28
CW		 2321 if (old_fb) {
2322 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2323 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2324 }
652c393a 2325
6b8e6ed0 2326 intel_update_fbc(dev);
5c3b82e2 2327 mutex_unlock(&dev->struct_mutex);
79e53945 2328
198598d0 2329 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2330
2331 return 0;
79e53945
JB		 2332}
2333
5e84e1a4
ZW		 2334static void intel_fdi_normal_train(struct drm_crtc *crtc)
2335{
2336 struct drm_device *dev = crtc->dev;
2337 struct drm_i915_private *dev_priv = dev->dev_private;
2338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2339 int pipe = intel_crtc->pipe;
2340 u32 reg, temp;
2341
2342 /* enable normal train */
2343 reg = FDI_TX_CTL(pipe);
2344 temp = I915_READ(reg);
61e499bf 2345 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2346 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2347 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2348 } else {
2349 temp &= ~FDI_LINK_TRAIN_NONE;
2350 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2351 }
5e84e1a4
ZW		 2352 I915_WRITE(reg, temp);
2353
2354 reg = FDI_RX_CTL(pipe);
2355 temp = I915_READ(reg);
2356 if (HAS_PCH_CPT(dev)) {
2357 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2358 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2359 } else {
2360 temp &= ~FDI_LINK_TRAIN_NONE;
2361 temp |= FDI_LINK_TRAIN_NONE;
2362 }
2363 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2364
2365 /* wait one idle pattern time */
2366 POSTING_READ(reg);
2367 udelay(1000);
357555c0
JB		 2368
2369 /* IVB wants error correction enabled */
2370 if (IS_IVYBRIDGE(dev))
2371 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2372 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2373}
2374
01a415fd
DV		 2375static void ivb_modeset_global_resources(struct drm_device *dev)
2376{
2377 struct drm_i915_private *dev_priv = dev->dev_private;
2378 struct intel_crtc *pipe_B_crtc =
2379 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2380 struct intel_crtc *pipe_C_crtc =
2381 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2382 uint32_t temp;
2383
2384 /* When everything is off disable fdi C so that we could enable fdi B
2385 * with all lanes. XXX: This misses the case where a pipe is not using
2386 * any pch resources and so doesn't need any fdi lanes. */
2387 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2388 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2389 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2390
2391 temp = I915_READ(SOUTH_CHICKEN1);
2392 temp &= ~FDI_BC_BIFURCATION_SELECT;
2393 DRM_DEBUG_KMS("disabling fdi C rx\n");
2394 I915_WRITE(SOUTH_CHICKEN1, temp);
2395 }
2396}
2397
8db9d77b
ZW		 2398/* The FDI link training functions for ILK/Ibexpeak. */
2399static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2400{
2401 struct drm_device *dev = crtc->dev;
2402 struct drm_i915_private *dev_priv = dev->dev_private;
2403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2404 int pipe = intel_crtc->pipe;
0fc932b8 2405 int plane = intel_crtc->plane;
5eddb70b 2406 u32 reg, temp, tries;
8db9d77b 2407
0fc932b8
JB		 2408 /* FDI needs bits from pipe & plane first */
2409 assert_pipe_enabled(dev_priv, pipe);
2410 assert_plane_enabled(dev_priv, plane);
2411
e1a44743
AJ		 2412 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2413 for train result */
5eddb70b
CW		 2414 reg = FDI_RX_IMR(pipe);
2415 temp = I915_READ(reg);
e1a44743
AJ		 2416 temp &= ~FDI_RX_SYMBOL_LOCK;
2417 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2418 I915_WRITE(reg, temp);
2419 I915_READ(reg);
e1a44743
AJ		 2420 udelay(150);
2421
8db9d77b 2422 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2423 reg = FDI_TX_CTL(pipe);
2424 temp = I915_READ(reg);
77ffb597
AJ		 2425 temp &= ~(7 << 19);
2426 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2427 temp &= ~FDI_LINK_TRAIN_NONE;
2428 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2429 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2430
5eddb70b
CW		 2431 reg = FDI_RX_CTL(pipe);
2432 temp = I915_READ(reg);
8db9d77b
ZW		 2433 temp &= ~FDI_LINK_TRAIN_NONE;
2434 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2435 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2436
2437 POSTING_READ(reg);
8db9d77b
ZW		 2438 udelay(150);
2439
5b2adf89 2440 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2441 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2442 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2443 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2444
5eddb70b 2445 reg = FDI_RX_IIR(pipe);
e1a44743 2446 for (tries = 0; tries < 5; tries++) {
5eddb70b 2447 temp = I915_READ(reg);
8db9d77b
ZW		 2448 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2449
2450 if ((temp & FDI_RX_BIT_LOCK)) {
2451 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2452 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2453 break;
2454 }
8db9d77b 2455 }
e1a44743 2456 if (tries == 5)
5eddb70b 2457 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2458
2459 /* Train 2 */
5eddb70b
CW		 2460 reg = FDI_TX_CTL(pipe);
2461 temp = I915_READ(reg);
8db9d77b
ZW		 2462 temp &= ~FDI_LINK_TRAIN_NONE;
2463 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2464 I915_WRITE(reg, temp);
8db9d77b 2465
5eddb70b
CW		 2466 reg = FDI_RX_CTL(pipe);
2467 temp = I915_READ(reg);
8db9d77b
ZW		 2468 temp &= ~FDI_LINK_TRAIN_NONE;
2469 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2470 I915_WRITE(reg, temp);
8db9d77b 2471
5eddb70b
CW		 2472 POSTING_READ(reg);
2473 udelay(150);
8db9d77b 2474
5eddb70b 2475 reg = FDI_RX_IIR(pipe);
e1a44743 2476 for (tries = 0; tries < 5; tries++) {
5eddb70b 2477 temp = I915_READ(reg);
8db9d77b
ZW		 2478 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2479
2480 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2481 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2482 DRM_DEBUG_KMS("FDI train 2 done.\n");
2483 break;
2484 }
8db9d77b 2485 }
e1a44743 2486 if (tries == 5)
5eddb70b 2487 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2488
2489 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2490
8db9d77b
ZW		 2491}
2492
0206e353 2493static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2494 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2495 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2496 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2497 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2498};
2499
2500/* The FDI link training functions for SNB/Cougarpoint. */
2501static void gen6_fdi_link_train(struct drm_crtc *crtc)
2502{
2503 struct drm_device *dev = crtc->dev;
2504 struct drm_i915_private *dev_priv = dev->dev_private;
2505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2506 int pipe = intel_crtc->pipe;
fa37d39e 2507 u32 reg, temp, i, retry;
8db9d77b 2508
e1a44743
AJ		 2509 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2510 for train result */
5eddb70b
CW		 2511 reg = FDI_RX_IMR(pipe);
2512 temp = I915_READ(reg);
e1a44743
AJ		 2513 temp &= ~FDI_RX_SYMBOL_LOCK;
2514 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2515 I915_WRITE(reg, temp);
2516
2517 POSTING_READ(reg);
e1a44743
AJ		 2518 udelay(150);
2519
8db9d77b 2520 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2521 reg = FDI_TX_CTL(pipe);
2522 temp = I915_READ(reg);
77ffb597
AJ		 2523 temp &= ~(7 << 19);
2524 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2525 temp &= ~FDI_LINK_TRAIN_NONE;
2526 temp |= FDI_LINK_TRAIN_PATTERN_1;
2527 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2528 /* SNB-B */
2529 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2530 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2531
d74cf324
DV		 2532 I915_WRITE(FDI_RX_MISC(pipe),
2533 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2534
5eddb70b
CW		 2535 reg = FDI_RX_CTL(pipe);
2536 temp = I915_READ(reg);
8db9d77b
ZW		 2537 if (HAS_PCH_CPT(dev)) {
2538 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2539 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2540 } else {
2541 temp &= ~FDI_LINK_TRAIN_NONE;
2542 temp |= FDI_LINK_TRAIN_PATTERN_1;
2543 }
5eddb70b
CW		 2544 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2545
2546 POSTING_READ(reg);
8db9d77b
ZW		 2547 udelay(150);
2548
0206e353 2549 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2550 reg = FDI_TX_CTL(pipe);
2551 temp = I915_READ(reg);
8db9d77b
ZW		 2552 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2553 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2554 I915_WRITE(reg, temp);
2555
2556 POSTING_READ(reg);
8db9d77b
ZW		 2557 udelay(500);
2558
fa37d39e
SP		 2559 for (retry = 0; retry < 5; retry++) {
2560 reg = FDI_RX_IIR(pipe);
2561 temp = I915_READ(reg);
2562 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2563 if (temp & FDI_RX_BIT_LOCK) {
2564 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2565 DRM_DEBUG_KMS("FDI train 1 done.\n");
2566 break;
2567 }
2568 udelay(50);
8db9d77b 2569 }
fa37d39e
SP		 2570 if (retry < 5)
2571 break;
8db9d77b
ZW		 2572 }
2573 if (i == 4)
5eddb70b 2574 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2575
2576 /* Train 2 */
5eddb70b
CW		 2577 reg = FDI_TX_CTL(pipe);
2578 temp = I915_READ(reg);
8db9d77b
ZW		 2579 temp &= ~FDI_LINK_TRAIN_NONE;
2580 temp |= FDI_LINK_TRAIN_PATTERN_2;
2581 if (IS_GEN6(dev)) {
2582 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583 /* SNB-B */
2584 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2585 }
5eddb70b 2586 I915_WRITE(reg, temp);
8db9d77b 2587
5eddb70b
CW		 2588 reg = FDI_RX_CTL(pipe);
2589 temp = I915_READ(reg);
8db9d77b
ZW		 2590 if (HAS_PCH_CPT(dev)) {
2591 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2592 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2593 } else {
2594 temp &= ~FDI_LINK_TRAIN_NONE;
2595 temp |= FDI_LINK_TRAIN_PATTERN_2;
2596 }
5eddb70b
CW		 2597 I915_WRITE(reg, temp);
2598
2599 POSTING_READ(reg);
8db9d77b
ZW		 2600 udelay(150);
2601
0206e353 2602 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2603 reg = FDI_TX_CTL(pipe);
2604 temp = I915_READ(reg);
8db9d77b
ZW		 2605 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2606 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2607 I915_WRITE(reg, temp);
2608
2609 POSTING_READ(reg);
8db9d77b
ZW		 2610 udelay(500);
2611
fa37d39e
SP		 2612 for (retry = 0; retry < 5; retry++) {
2613 reg = FDI_RX_IIR(pipe);
2614 temp = I915_READ(reg);
2615 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2616 if (temp & FDI_RX_SYMBOL_LOCK) {
2617 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2618 DRM_DEBUG_KMS("FDI train 2 done.\n");
2619 break;
2620 }
2621 udelay(50);
8db9d77b 2622 }
fa37d39e
SP		 2623 if (retry < 5)
2624 break;
8db9d77b
ZW		 2625 }
2626 if (i == 4)
5eddb70b 2627 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2628
2629 DRM_DEBUG_KMS("FDI train done.\n");
2630}
2631
357555c0
JB		 2632/* Manual link training for Ivy Bridge A0 parts */
2633static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2634{
2635 struct drm_device *dev = crtc->dev;
2636 struct drm_i915_private *dev_priv = dev->dev_private;
2637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2638 int pipe = intel_crtc->pipe;
2639 u32 reg, temp, i;
2640
2641 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2642 for train result */
2643 reg = FDI_RX_IMR(pipe);
2644 temp = I915_READ(reg);
2645 temp &= ~FDI_RX_SYMBOL_LOCK;
2646 temp &= ~FDI_RX_BIT_LOCK;
2647 I915_WRITE(reg, temp);
2648
2649 POSTING_READ(reg);
2650 udelay(150);
2651
01a415fd
DV		 2652 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2653 I915_READ(FDI_RX_IIR(pipe)));
2654
357555c0
JB		 2655 /* enable CPU FDI TX and PCH FDI RX */
2656 reg = FDI_TX_CTL(pipe);
2657 temp = I915_READ(reg);
2658 temp &= ~(7 << 19);
2659 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2660 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2661 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2662 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2663 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2664 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2665 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2666
d74cf324
DV		 2667 I915_WRITE(FDI_RX_MISC(pipe),
2668 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2669
357555c0
JB		 2670 reg = FDI_RX_CTL(pipe);
2671 temp = I915_READ(reg);
2672 temp &= ~FDI_LINK_TRAIN_AUTO;
2673 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2674 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2675 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2676 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2677
2678 POSTING_READ(reg);
2679 udelay(150);
2680
0206e353 2681 for (i = 0; i < 4; i++) {
357555c0
JB		 2682 reg = FDI_TX_CTL(pipe);
2683 temp = I915_READ(reg);
2684 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2685 temp |= snb_b_fdi_train_param[i];
2686 I915_WRITE(reg, temp);
2687
2688 POSTING_READ(reg);
2689 udelay(500);
2690
2691 reg = FDI_RX_IIR(pipe);
2692 temp = I915_READ(reg);
2693 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2694
2695 if (temp & FDI_RX_BIT_LOCK ||
2696 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2697 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2698 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2699 break;
2700 }
2701 }
2702 if (i == 4)
2703 DRM_ERROR("FDI train 1 fail!\n");
2704
2705 /* Train 2 */
2706 reg = FDI_TX_CTL(pipe);
2707 temp = I915_READ(reg);
2708 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2709 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2710 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2711 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2712 I915_WRITE(reg, temp);
2713
2714 reg = FDI_RX_CTL(pipe);
2715 temp = I915_READ(reg);
2716 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2717 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2718 I915_WRITE(reg, temp);
2719
2720 POSTING_READ(reg);
2721 udelay(150);
2722
0206e353 2723 for (i = 0; i < 4; i++) {
357555c0
JB		 2724 reg = FDI_TX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2727 temp |= snb_b_fdi_train_param[i];
2728 I915_WRITE(reg, temp);
2729
2730 POSTING_READ(reg);
2731 udelay(500);
2732
2733 reg = FDI_RX_IIR(pipe);
2734 temp = I915_READ(reg);
2735 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2736
2737 if (temp & FDI_RX_SYMBOL_LOCK) {
2738 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2739 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2740 break;
2741 }
2742 }
2743 if (i == 4)
2744 DRM_ERROR("FDI train 2 fail!\n");
2745
2746 DRM_DEBUG_KMS("FDI train done.\n");
2747}
2748
88cefb6c 2749static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2750{
88cefb6c 2751 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2752 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2753 int pipe = intel_crtc->pipe;
5eddb70b 2754 u32 reg, temp;
79e53945 2755
c64e311e 2756
c98e9dcf 2757 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2758 reg = FDI_RX_CTL(pipe);
2759 temp = I915_READ(reg);
2760 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2761 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2762 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2763 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2764
2765 POSTING_READ(reg);
c98e9dcf
JB		 2766 udelay(200);
2767
2768 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2769 temp = I915_READ(reg);
2770 I915_WRITE(reg, temp | FDI_PCDCLK);
2771
2772 POSTING_READ(reg);
c98e9dcf
JB		 2773 udelay(200);
2774
20749730
PZ		 2775 /* Enable CPU FDI TX PLL, always on for Ironlake */
2776 reg = FDI_TX_CTL(pipe);
2777 temp = I915_READ(reg);
2778 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2779 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2780
20749730
PZ		 2781 POSTING_READ(reg);
2782 udelay(100);
6be4a607 2783 }
0e23b99d
JB		 2784}
2785
88cefb6c
DV		 2786static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2787{
2788 struct drm_device *dev = intel_crtc->base.dev;
2789 struct drm_i915_private *dev_priv = dev->dev_private;
2790 int pipe = intel_crtc->pipe;
2791 u32 reg, temp;
2792
2793 /* Switch from PCDclk to Rawclk */
2794 reg = FDI_RX_CTL(pipe);
2795 temp = I915_READ(reg);
2796 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2797
2798 /* Disable CPU FDI TX PLL */
2799 reg = FDI_TX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2802
2803 POSTING_READ(reg);
2804 udelay(100);
2805
2806 reg = FDI_RX_CTL(pipe);
2807 temp = I915_READ(reg);
2808 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2809
2810 /* Wait for the clocks to turn off. */
2811 POSTING_READ(reg);
2812 udelay(100);
2813}
2814
0fc932b8
JB		 2815static void ironlake_fdi_disable(struct drm_crtc *crtc)
2816{
2817 struct drm_device *dev = crtc->dev;
2818 struct drm_i915_private *dev_priv = dev->dev_private;
2819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2820 int pipe = intel_crtc->pipe;
2821 u32 reg, temp;
2822
2823 /* disable CPU FDI tx and PCH FDI rx */
2824 reg = FDI_TX_CTL(pipe);
2825 temp = I915_READ(reg);
2826 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2827 POSTING_READ(reg);
2828
2829 reg = FDI_RX_CTL(pipe);
2830 temp = I915_READ(reg);
2831 temp &= ~(0x7 << 16);
dfd07d72 2832 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2833 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2834
2835 POSTING_READ(reg);
2836 udelay(100);
2837
2838 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2839 if (HAS_PCH_IBX(dev)) {
2840 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2841 }
0fc932b8
JB		 2842
2843 /* still set train pattern 1 */
2844 reg = FDI_TX_CTL(pipe);
2845 temp = I915_READ(reg);
2846 temp &= ~FDI_LINK_TRAIN_NONE;
2847 temp |= FDI_LINK_TRAIN_PATTERN_1;
2848 I915_WRITE(reg, temp);
2849
2850 reg = FDI_RX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 if (HAS_PCH_CPT(dev)) {
2853 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2855 } else {
2856 temp &= ~FDI_LINK_TRAIN_NONE;
2857 temp |= FDI_LINK_TRAIN_PATTERN_1;
2858 }
2859 /* BPC in FDI rx is consistent with that in PIPECONF */
2860 temp &= ~(0x07 << 16);
dfd07d72 2861 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2862 I915_WRITE(reg, temp);
2863
2864 POSTING_READ(reg);
2865 udelay(100);
2866}
2867
5bb61643
CW		 2868static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2869{
2870 struct drm_device *dev = crtc->dev;
2871 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2873 unsigned long flags;
2874 bool pending;
2875
10d83730
VS		 2876 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2877 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2878 return false;
2879
2880 spin_lock_irqsave(&dev->event_lock, flags);
2881 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2882 spin_unlock_irqrestore(&dev->event_lock, flags);
2883
2884 return pending;
2885}
2886
e6c3a2a6
CW		 2887static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2888{
0f91128d 2889 struct drm_device *dev = crtc->dev;
5bb61643 2890 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2891
2892 if (crtc->fb == NULL)
2893 return;
2894
2c10d571
DV		 2895 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2896
5bb61643
CW		 2897 wait_event(dev_priv->pending_flip_queue,
2898 !intel_crtc_has_pending_flip(crtc));
2899
0f91128d
CW		 2900 mutex_lock(&dev->struct_mutex);
2901 intel_finish_fb(crtc->fb);
2902 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2903}
2904
e615efe4
ED		 2905/* Program iCLKIP clock to the desired frequency */
2906static void lpt_program_iclkip(struct drm_crtc *crtc)
2907{
2908 struct drm_device *dev = crtc->dev;
2909 struct drm_i915_private *dev_priv = dev->dev_private;
2910 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2911 u32 temp;
2912
09153000
DV		 2913 mutex_lock(&dev_priv->dpio_lock);
2914
e615efe4
ED		 2915 /* It is necessary to ungate the pixclk gate prior to programming
2916 * the divisors, and gate it back when it is done.
2917 */
2918 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2919
2920 /* Disable SSCCTL */
2921 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2922 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2923 SBI_SSCCTL_DISABLE,
2924 SBI_ICLK);
e615efe4
ED		 2925
2926 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2927 if (crtc->mode.clock == 20000) {
2928 auxdiv = 1;
2929 divsel = 0x41;
2930 phaseinc = 0x20;
2931 } else {
2932 /* The iCLK virtual clock root frequency is in MHz,
2933 * but the crtc->mode.clock in in KHz. To get the divisors,
2934 * it is necessary to divide one by another, so we
2935 * convert the virtual clock precision to KHz here for higher
2936 * precision.
2937 */
2938 u32 iclk_virtual_root_freq = 172800 * 1000;
2939 u32 iclk_pi_range = 64;
2940 u32 desired_divisor, msb_divisor_value, pi_value;
2941
2942 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2943 msb_divisor_value = desired_divisor / iclk_pi_range;
2944 pi_value = desired_divisor % iclk_pi_range;
2945
2946 auxdiv = 0;
2947 divsel = msb_divisor_value - 2;
2948 phaseinc = pi_value;
2949 }
2950
2951 /* This should not happen with any sane values */
2952 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2953 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2954 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2955 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2956
2957 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2958 crtc->mode.clock,
2959 auxdiv,
2960 divsel,
2961 phasedir,
2962 phaseinc);
2963
2964 /* Program SSCDIVINTPHASE6 */
988d6ee8 2965 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2966 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2967 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2968 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2969 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2970 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2971 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2972 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2973
2974 /* Program SSCAUXDIV */
988d6ee8 2975 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2976 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2977 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2978 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2979
2980 /* Enable modulator and associated divider */
988d6ee8 2981 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2982 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2983 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2984
2985 /* Wait for initialization time */
2986 udelay(24);
2987
2988 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2989
2990 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2991}
2992
f67a559d
JB		 2993/*
2994 * Enable PCH resources required for PCH ports:
2995 * - PCH PLLs
2996 * - FDI training & RX/TX
2997 * - update transcoder timings
2998 * - DP transcoding bits
2999 * - transcoder
3000 */
3001static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3002{
3003 struct drm_device *dev = crtc->dev;
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3006 int pipe = intel_crtc->pipe;
ee7b9f93 3007 u32 reg, temp;
2c07245f 3008
e7e164db
CW		 3009 assert_transcoder_disabled(dev_priv, pipe);
3010
cd986abb
DV		 3011 /* Write the TU size bits before fdi link training, so that error
3012 * detection works. */
3013 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3014 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3015
c98e9dcf 3016 /* For PCH output, training FDI link */
674cf967 3017 dev_priv->display.fdi_link_train(crtc);
2c07245f 3018
572deb37
DV		 3019 /* XXX: pch pll's can be enabled any time before we enable the PCH
3020 * transcoder, and we actually should do this to not upset any PCH
3021 * transcoder that already use the clock when we share it.
3022 *
3023 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3024 * unconditionally resets the pll - we need that to have the right LVDS
3025 * enable sequence. */
b6b4e185 3026 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3027
303b81e0 3028 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3029 u32 sel;
4b645f14 3030
c98e9dcf 3031 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3032 switch (pipe) {
3033 default:
3034 case 0:
3035 temp |= TRANSA_DPLL_ENABLE;
3036 sel = TRANSA_DPLLB_SEL;
3037 break;
3038 case 1:
3039 temp |= TRANSB_DPLL_ENABLE;
3040 sel = TRANSB_DPLLB_SEL;
3041 break;
3042 case 2:
3043 temp |= TRANSC_DPLL_ENABLE;
3044 sel = TRANSC_DPLLB_SEL;
3045 break;
d64311ab 3046 }
ee7b9f93
JB		 3047 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3048 temp |= sel;
3049 else
3050 temp &= ~sel;
c98e9dcf 3051 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3052 }
5eddb70b 3053
d9b6cb56
JB		 3054 /* set transcoder timing, panel must allow it */
3055 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3056 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3057 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3058 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3059
5eddb70b
CW		 3060 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3061 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3062 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3063 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3064
303b81e0 3065 intel_fdi_normal_train(crtc);
5e84e1a4 3066
c98e9dcf
JB		 3067 /* For PCH DP, enable TRANS_DP_CTL */
3068 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3069 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3070 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3071 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3072 reg = TRANS_DP_CTL(pipe);
3073 temp = I915_READ(reg);
3074 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3075 TRANS_DP_SYNC_MASK |
3076 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3077 temp |= (TRANS_DP_OUTPUT_ENABLE |
3078 TRANS_DP_ENH_FRAMING);
9325c9f0 3079 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3080
3081 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3082 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3083 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3084 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3085
3086 switch (intel_trans_dp_port_sel(crtc)) {
3087 case PCH_DP_B:
5eddb70b 3088 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3089 break;
3090 case PCH_DP_C:
5eddb70b 3091 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3092 break;
3093 case PCH_DP_D:
5eddb70b 3094 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3095 break;
3096 default:
e95d41e1 3097 BUG();
32f9d658 3098 }
2c07245f 3099
5eddb70b 3100 I915_WRITE(reg, temp);
6be4a607 3101 }
b52eb4dc 3102
b8a4f404 3103 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3104}
3105
1507e5bd
PZ		 3106static void lpt_pch_enable(struct drm_crtc *crtc)
3107{
3108 struct drm_device *dev = crtc->dev;
3109 struct drm_i915_private *dev_priv = dev->dev_private;
3110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3111 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3112
daed2dbb 3113 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3114
8c52b5e8 3115 lpt_program_iclkip(crtc);
1507e5bd 3116
0540e488 3117 /* Set transcoder timing. */
daed2dbb
PZ		 3118 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3119 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3120 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3121
daed2dbb
PZ		 3122 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3123 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3124 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3125 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3126
937bb610 3127 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3128}
3129
ee7b9f93
JB		 3130static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3131{
3132 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3133
3134 if (pll == NULL)
3135 return;
3136
3137 if (pll->refcount == 0) {
3138 WARN(1, "bad PCH PLL refcount\n");
3139 return;
3140 }
3141
3142 --pll->refcount;
3143 intel_crtc->pch_pll = NULL;
3144}
3145
3146static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3147{
3148 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3149 struct intel_pch_pll *pll;
3150 int i;
3151
3152 pll = intel_crtc->pch_pll;
3153 if (pll) {
3154 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3155 intel_crtc->base.base.id, pll->pll_reg);
3156 goto prepare;
3157 }
3158
98b6bd99
DV		 3159 if (HAS_PCH_IBX(dev_priv->dev)) {
3160 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3161 i = intel_crtc->pipe;
3162 pll = &dev_priv->pch_plls[i];
3163
3164 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3165 intel_crtc->base.base.id, pll->pll_reg);
3166
3167 goto found;
3168 }
3169
ee7b9f93
JB		 3170 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3171 pll = &dev_priv->pch_plls[i];
3172
3173 /* Only want to check enabled timings first */
3174 if (pll->refcount == 0)
3175 continue;
3176
3177 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3178 fp == I915_READ(pll->fp0_reg)) {
3179 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3180 intel_crtc->base.base.id,
3181 pll->pll_reg, pll->refcount, pll->active);
3182
3183 goto found;
3184 }
3185 }
3186
3187 /* Ok no matching timings, maybe there's a free one? */
3188 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3189 pll = &dev_priv->pch_plls[i];
3190 if (pll->refcount == 0) {
3191 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3192 intel_crtc->base.base.id, pll->pll_reg);
3193 goto found;
3194 }
3195 }
3196
3197 return NULL;
3198
3199found:
3200 intel_crtc->pch_pll = pll;
3201 pll->refcount++;
84f44ce7 3202 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3203prepare: /* separate function? */
3204 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3205
e04c7350
CW		 3206 /* Wait for the clocks to stabilize before rewriting the regs */
3207 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3208 POSTING_READ(pll->pll_reg);
3209 udelay(150);
e04c7350
CW		 3210
3211 I915_WRITE(pll->fp0_reg, fp);
3212 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3213 pll->on = false;
3214 return pll;
3215}
3216
d4270e57
JB		 3217void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3218{
3219 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3220 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3221 u32 temp;
3222
3223 temp = I915_READ(dslreg);
3224 udelay(500);
3225 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3226 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3227 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3228 }
3229}
3230
f67a559d
JB		 3231static void ironlake_crtc_enable(struct drm_crtc *crtc)
3232{
3233 struct drm_device *dev = crtc->dev;
3234 struct drm_i915_private *dev_priv = dev->dev_private;
3235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3236 struct intel_encoder *encoder;
f67a559d
JB		 3237 int pipe = intel_crtc->pipe;
3238 int plane = intel_crtc->plane;
3239 u32 temp;
f67a559d 3240
08a48469
DV		 3241 WARN_ON(!crtc->enabled);
3242
f67a559d
JB		 3243 if (intel_crtc->active)
3244 return;
3245
3246 intel_crtc->active = true;
8664281b
PZ		 3247
3248 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3249 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3250
f67a559d
JB		 3251 intel_update_watermarks(dev);
3252
3253 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3254 temp = I915_READ(PCH_LVDS);
3255 if ((temp & LVDS_PORT_EN) == 0)
3256 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3257 }
3258
f67a559d 3259
5bfe2ac0 3260 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3261 /* Note: FDI PLL enabling _must_ be done before we enable the
3262 * cpu pipes, hence this is separate from all the other fdi/pch
3263 * enabling. */
88cefb6c 3264 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3265 } else {
3266 assert_fdi_tx_disabled(dev_priv, pipe);
3267 assert_fdi_rx_disabled(dev_priv, pipe);
3268 }
f67a559d 3269
bf49ec8c
DV		 3270 for_each_encoder_on_crtc(dev, crtc, encoder)
3271 if (encoder->pre_enable)
3272 encoder->pre_enable(encoder);
f67a559d
JB		 3273
3274 /* Enable panel fitting for LVDS */
3275 if (dev_priv->pch_pf_size &&
547dc041
JN		 3276 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3277 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3278 /* Force use of hard-coded filter coefficients
3279 * as some pre-programmed values are broken,
3280 * e.g. x201.
3281 */
13888d78
PZ		 3282 if (IS_IVYBRIDGE(dev))
3283 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3284 PF_PIPE_SEL_IVB(pipe));
3285 else
3286 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3287 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3288 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3289 }
3290
9c54c0dd
JB		 3291 /*
3292 * On ILK+ LUT must be loaded before the pipe is running but with
3293 * clocks enabled
3294 */
3295 intel_crtc_load_lut(crtc);
3296
5bfe2ac0
DV		 3297 intel_enable_pipe(dev_priv, pipe,
3298 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3299 intel_enable_plane(dev_priv, plane, pipe);
3300
5bfe2ac0 3301 if (intel_crtc->config.has_pch_encoder)
f67a559d 3302 ironlake_pch_enable(crtc);
c98e9dcf 3303
d1ebd816 3304 mutex_lock(&dev->struct_mutex);
bed4a673 3305 intel_update_fbc(dev);
d1ebd816
BW		 3306 mutex_unlock(&dev->struct_mutex);
3307
6b383a7f 3308 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3309
fa5c73b1
DV		 3310 for_each_encoder_on_crtc(dev, crtc, encoder)
3311 encoder->enable(encoder);
61b77ddd
DV		 3312
3313 if (HAS_PCH_CPT(dev))
3314 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3315
3316 /*
3317 * There seems to be a race in PCH platform hw (at least on some
3318 * outputs) where an enabled pipe still completes any pageflip right
3319 * away (as if the pipe is off) instead of waiting for vblank. As soon
3320 * as the first vblank happend, everything works as expected. Hence just
3321 * wait for one vblank before returning to avoid strange things
3322 * happening.
3323 */
3324 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3325}
3326
4f771f10
PZ		 3327static void haswell_crtc_enable(struct drm_crtc *crtc)
3328{
3329 struct drm_device *dev = crtc->dev;
3330 struct drm_i915_private *dev_priv = dev->dev_private;
3331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3332 struct intel_encoder *encoder;
3333 int pipe = intel_crtc->pipe;
3334 int plane = intel_crtc->plane;
4f771f10
PZ		 3335
3336 WARN_ON(!crtc->enabled);
3337
3338 if (intel_crtc->active)
3339 return;
3340
3341 intel_crtc->active = true;
8664281b
PZ		 3342
3343 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3344 if (intel_crtc->config.has_pch_encoder)
3345 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3346
4f771f10
PZ		 3347 intel_update_watermarks(dev);
3348
5bfe2ac0 3349 if (intel_crtc->config.has_pch_encoder)
04945641 3350 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3351
3352 for_each_encoder_on_crtc(dev, crtc, encoder)
3353 if (encoder->pre_enable)
3354 encoder->pre_enable(encoder);
3355
1f544388 3356 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3357
1f544388 3358 /* Enable panel fitting for eDP */
547dc041
JN		 3359 if (dev_priv->pch_pf_size &&
3360 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3361 /* Force use of hard-coded filter coefficients
3362 * as some pre-programmed values are broken,
3363 * e.g. x201.
3364 */
54075a7d
PZ		 3365 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3366 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3367 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3368 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3369 }
3370
3371 /*
3372 * On ILK+ LUT must be loaded before the pipe is running but with
3373 * clocks enabled
3374 */
3375 intel_crtc_load_lut(crtc);
3376
1f544388 3377 intel_ddi_set_pipe_settings(crtc);
8228c251 3378 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3379
5bfe2ac0
DV		 3380 intel_enable_pipe(dev_priv, pipe,
3381 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3382 intel_enable_plane(dev_priv, plane, pipe);
3383
5bfe2ac0 3384 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3385 lpt_pch_enable(crtc);
4f771f10
PZ		 3386
3387 mutex_lock(&dev->struct_mutex);
3388 intel_update_fbc(dev);
3389 mutex_unlock(&dev->struct_mutex);
3390
3391 intel_crtc_update_cursor(crtc, true);
3392
3393 for_each_encoder_on_crtc(dev, crtc, encoder)
3394 encoder->enable(encoder);
3395
4f771f10
PZ		 3396 /*
3397 * There seems to be a race in PCH platform hw (at least on some
3398 * outputs) where an enabled pipe still completes any pageflip right
3399 * away (as if the pipe is off) instead of waiting for vblank. As soon
3400 * as the first vblank happend, everything works as expected. Hence just
3401 * wait for one vblank before returning to avoid strange things
3402 * happening.
3403 */
3404 intel_wait_for_vblank(dev, intel_crtc->pipe);
3405}
3406
6be4a607
JB		 3407static void ironlake_crtc_disable(struct drm_crtc *crtc)
3408{
3409 struct drm_device *dev = crtc->dev;
3410 struct drm_i915_private *dev_priv = dev->dev_private;
3411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3412 struct intel_encoder *encoder;
6be4a607
JB		 3413 int pipe = intel_crtc->pipe;
3414 int plane = intel_crtc->plane;
5eddb70b 3415 u32 reg, temp;
b52eb4dc 3416
ef9c3aee 3417
f7abfe8b
CW		 3418 if (!intel_crtc->active)
3419 return;
3420
ea9d758d
DV		 3421 for_each_encoder_on_crtc(dev, crtc, encoder)
3422 encoder->disable(encoder);
3423
e6c3a2a6 3424 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3425 drm_vblank_off(dev, pipe);
6b383a7f 3426 intel_crtc_update_cursor(crtc, false);
5eddb70b 3427
b24e7179 3428 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3429
973d04f9
CW		 3430 if (dev_priv->cfb_plane == plane)
3431 intel_disable_fbc(dev);
2c07245f 3432
8664281b 3433 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3434 intel_disable_pipe(dev_priv, pipe);
32f9d658 3435
6be4a607 3436 /* Disable PF */
9db4a9c7
JB		 3437 I915_WRITE(PF_CTL(pipe), 0);
3438 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3439
bf49ec8c
DV		 3440 for_each_encoder_on_crtc(dev, crtc, encoder)
3441 if (encoder->post_disable)
3442 encoder->post_disable(encoder);
2c07245f 3443
0fc932b8 3444 ironlake_fdi_disable(crtc);
249c0e64 3445
b8a4f404 3446 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3447 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3448
6be4a607
JB		 3449 if (HAS_PCH_CPT(dev)) {
3450 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3451 reg = TRANS_DP_CTL(pipe);
3452 temp = I915_READ(reg);
3453 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3454 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3455 I915_WRITE(reg, temp);
6be4a607
JB		 3456
3457 /* disable DPLL_SEL */
3458 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3459 switch (pipe) {
3460 case 0:
d64311ab 3461 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3462 break;
3463 case 1:
6be4a607 3464 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3465 break;
3466 case 2:
4b645f14 3467 /* C shares PLL A or B */
d64311ab 3468 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3469 break;
3470 default:
3471 BUG(); /* wtf */
3472 }
6be4a607 3473 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3474 }
e3421a18 3475
6be4a607 3476 /* disable PCH DPLL */
ee7b9f93 3477 intel_disable_pch_pll(intel_crtc);
8db9d77b 3478
88cefb6c 3479 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3480
f7abfe8b 3481 intel_crtc->active = false;
6b383a7f 3482 intel_update_watermarks(dev);
d1ebd816
BW		 3483
3484 mutex_lock(&dev->struct_mutex);
6b383a7f 3485 intel_update_fbc(dev);
d1ebd816 3486 mutex_unlock(&dev->struct_mutex);
6be4a607 3487}
1b3c7a47 3488
4f771f10 3489static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3490{
4f771f10
PZ		 3491 struct drm_device *dev = crtc->dev;
3492 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3494 struct intel_encoder *encoder;
3495 int pipe = intel_crtc->pipe;
3496 int plane = intel_crtc->plane;
3b117c8f 3497 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3498
4f771f10
PZ		 3499 if (!intel_crtc->active)
3500 return;
3501
3502 for_each_encoder_on_crtc(dev, crtc, encoder)
3503 encoder->disable(encoder);
3504
3505 intel_crtc_wait_for_pending_flips(crtc);
3506 drm_vblank_off(dev, pipe);
3507 intel_crtc_update_cursor(crtc, false);
3508
3509 intel_disable_plane(dev_priv, plane, pipe);
3510
3511 if (dev_priv->cfb_plane == plane)
3512 intel_disable_fbc(dev);
3513
8664281b
PZ		 3514 if (intel_crtc->config.has_pch_encoder)
3515 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3516 intel_disable_pipe(dev_priv, pipe);
3517
ad80a810 3518 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3519
f7708f78
PZ		 3520 /* XXX: Once we have proper panel fitter state tracking implemented with
3521 * hardware state read/check support we should switch to only disable
3522 * the panel fitter when we know it's used. */
3523 if (intel_using_power_well(dev)) {
3524 I915_WRITE(PF_CTL(pipe), 0);
3525 I915_WRITE(PF_WIN_SZ(pipe), 0);
3526 }
4f771f10 3527
1f544388 3528 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3529
3530 for_each_encoder_on_crtc(dev, crtc, encoder)
3531 if (encoder->post_disable)
3532 encoder->post_disable(encoder);
3533
88adfff1 3534 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3535 lpt_disable_pch_transcoder(dev_priv);
8664281b 3536 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3537 intel_ddi_fdi_disable(crtc);
83616634 3538 }
4f771f10
PZ		 3539
3540 intel_crtc->active = false;
3541 intel_update_watermarks(dev);
3542
3543 mutex_lock(&dev->struct_mutex);
3544 intel_update_fbc(dev);
3545 mutex_unlock(&dev->struct_mutex);
3546}
3547
ee7b9f93
JB		 3548static void ironlake_crtc_off(struct drm_crtc *crtc)
3549{
3550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3551 intel_put_pch_pll(intel_crtc);
3552}
3553
6441ab5f
PZ		 3554static void haswell_crtc_off(struct drm_crtc *crtc)
3555{
a5c961d1
PZ		 3556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3557
3558 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3559 * start using it. */
3b117c8f 3560 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3561
6441ab5f
PZ		 3562 intel_ddi_put_crtc_pll(crtc);
3563}
3564
02e792fb
DV		 3565static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3566{
02e792fb 3567 if (!enable && intel_crtc->overlay) {
23f09ce3 3568 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3569 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3570
23f09ce3 3571 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3572 dev_priv->mm.interruptible = false;
3573 (void) intel_overlay_switch_off(intel_crtc->overlay);
3574 dev_priv->mm.interruptible = true;
23f09ce3 3575 mutex_unlock(&dev->struct_mutex);
02e792fb 3576 }
02e792fb 3577
5dcdbcb0
CW		 3578 /* Let userspace switch the overlay on again. In most cases userspace
3579 * has to recompute where to put it anyway.
3580 */
02e792fb
DV		 3581}
3582
61bc95c1
EE		 3583/**
3584 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3585 * cursor plane briefly if not already running after enabling the display
3586 * plane.
3587 * This workaround avoids occasional blank screens when self refresh is
3588 * enabled.
3589 */
3590static void
3591g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3592{
3593 u32 cntl = I915_READ(CURCNTR(pipe));
3594
3595 if ((cntl & CURSOR_MODE) == 0) {
3596 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3597
3598 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3599 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3600 intel_wait_for_vblank(dev_priv->dev, pipe);
3601 I915_WRITE(CURCNTR(pipe), cntl);
3602 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3603 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3604 }
3605}
3606
89b667f8
JB		 3607static void valleyview_crtc_enable(struct drm_crtc *crtc)
3608{
3609 struct drm_device *dev = crtc->dev;
3610 struct drm_i915_private *dev_priv = dev->dev_private;
3611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3612 struct intel_encoder *encoder;
3613 int pipe = intel_crtc->pipe;
3614 int plane = intel_crtc->plane;
3615
3616 WARN_ON(!crtc->enabled);
3617
3618 if (intel_crtc->active)
3619 return;
3620
3621 intel_crtc->active = true;
3622 intel_update_watermarks(dev);
3623
3624 mutex_lock(&dev_priv->dpio_lock);
3625
3626 for_each_encoder_on_crtc(dev, crtc, encoder)
3627 if (encoder->pre_pll_enable)
3628 encoder->pre_pll_enable(encoder);
3629
3630 intel_enable_pll(dev_priv, pipe);
3631
3632 for_each_encoder_on_crtc(dev, crtc, encoder)
3633 if (encoder->pre_enable)
3634 encoder->pre_enable(encoder);
3635
3636 /* VLV wants encoder enabling _before_ the pipe is up. */
3637 for_each_encoder_on_crtc(dev, crtc, encoder)
3638 encoder->enable(encoder);
3639
3640 intel_enable_pipe(dev_priv, pipe, false);
3641 intel_enable_plane(dev_priv, plane, pipe);
3642
3643 intel_crtc_load_lut(crtc);
3644 intel_update_fbc(dev);
3645
3646 /* Give the overlay scaler a chance to enable if it's on this pipe */
3647 intel_crtc_dpms_overlay(intel_crtc, true);
3648 intel_crtc_update_cursor(crtc, true);
3649
3650 mutex_unlock(&dev_priv->dpio_lock);
3651}
3652
0b8765c6 3653static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3654{
3655 struct drm_device *dev = crtc->dev;
79e53945
JB		 3656 struct drm_i915_private *dev_priv = dev->dev_private;
3657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3658 struct intel_encoder *encoder;
79e53945 3659 int pipe = intel_crtc->pipe;
80824003 3660 int plane = intel_crtc->plane;
79e53945 3661
08a48469
DV		 3662 WARN_ON(!crtc->enabled);
3663
f7abfe8b
CW		 3664 if (intel_crtc->active)
3665 return;
3666
3667 intel_crtc->active = true;
6b383a7f
CW		 3668 intel_update_watermarks(dev);
3669
63d7bbe9 3670 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3671
3672 for_each_encoder_on_crtc(dev, crtc, encoder)
3673 if (encoder->pre_enable)
3674 encoder->pre_enable(encoder);
3675
040484af 3676 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3677 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3678 if (IS_G4X(dev))
3679 g4x_fixup_plane(dev_priv, pipe);
79e53945 3680
0b8765c6 3681 intel_crtc_load_lut(crtc);
bed4a673 3682 intel_update_fbc(dev);
79e53945 3683
0b8765c6
JB		 3684 /* Give the overlay scaler a chance to enable if it's on this pipe */
3685 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3686 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3687
fa5c73b1
DV		 3688 for_each_encoder_on_crtc(dev, crtc, encoder)
3689 encoder->enable(encoder);
0b8765c6 3690}
79e53945 3691
87476d63
DV		 3692static void i9xx_pfit_disable(struct intel_crtc *crtc)
3693{
3694 struct drm_device *dev = crtc->base.dev;
3695 struct drm_i915_private *dev_priv = dev->dev_private;
3696 enum pipe pipe;
3697 uint32_t pctl = I915_READ(PFIT_CONTROL);
3698
3699 assert_pipe_disabled(dev_priv, crtc->pipe);
3700
3701 if (INTEL_INFO(dev)->gen >= 4)
3702 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3703 else
3704 pipe = PIPE_B;
3705
3706 if (pipe == crtc->pipe) {
3707 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3708 I915_WRITE(PFIT_CONTROL, 0);
3709 }
3710}
3711
0b8765c6
JB		 3712static void i9xx_crtc_disable(struct drm_crtc *crtc)
3713{
3714 struct drm_device *dev = crtc->dev;
3715 struct drm_i915_private *dev_priv = dev->dev_private;
3716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3717 struct intel_encoder *encoder;
0b8765c6
JB		 3718 int pipe = intel_crtc->pipe;
3719 int plane = intel_crtc->plane;
ef9c3aee 3720
f7abfe8b
CW		 3721 if (!intel_crtc->active)
3722 return;
3723
ea9d758d
DV		 3724 for_each_encoder_on_crtc(dev, crtc, encoder)
3725 encoder->disable(encoder);
3726
0b8765c6 3727 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3728 intel_crtc_wait_for_pending_flips(crtc);
3729 drm_vblank_off(dev, pipe);
0b8765c6 3730 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3731 intel_crtc_update_cursor(crtc, false);
0b8765c6 3732
973d04f9
CW		 3733 if (dev_priv->cfb_plane == plane)
3734 intel_disable_fbc(dev);
79e53945 3735
b24e7179 3736 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3737 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3738
87476d63 3739 i9xx_pfit_disable(intel_crtc);
24a1f16d 3740
89b667f8
JB		 3741 for_each_encoder_on_crtc(dev, crtc, encoder)
3742 if (encoder->post_disable)
3743 encoder->post_disable(encoder);
3744
63d7bbe9 3745 intel_disable_pll(dev_priv, pipe);
0b8765c6 3746
f7abfe8b 3747 intel_crtc->active = false;
6b383a7f
CW		 3748 intel_update_fbc(dev);
3749 intel_update_watermarks(dev);
0b8765c6
JB		 3750}
3751
ee7b9f93
JB		 3752static void i9xx_crtc_off(struct drm_crtc *crtc)
3753{
3754}
3755
976f8a20
DV		 3756static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3757 bool enabled)
2c07245f
ZW		 3758{
3759 struct drm_device *dev = crtc->dev;
3760 struct drm_i915_master_private *master_priv;
3761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3762 int pipe = intel_crtc->pipe;
79e53945
JB		 3763
3764 if (!dev->primary->master)
3765 return;
3766
3767 master_priv = dev->primary->master->driver_priv;
3768 if (!master_priv->sarea_priv)
3769 return;
3770
79e53945
JB		 3771 switch (pipe) {
3772 case 0:
3773 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3774 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3775 break;
3776 case 1:
3777 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3778 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3779 break;
3780 default:
9db4a9c7 3781 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3782 break;
3783 }
79e53945
JB		 3784}
3785
976f8a20
DV		 3786/**
3787 * Sets the power management mode of the pipe and plane.
3788 */
3789void intel_crtc_update_dpms(struct drm_crtc *crtc)
3790{
3791 struct drm_device *dev = crtc->dev;
3792 struct drm_i915_private *dev_priv = dev->dev_private;
3793 struct intel_encoder *intel_encoder;
3794 bool enable = false;
3795
3796 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3797 enable |= intel_encoder->connectors_active;
3798
3799 if (enable)
3800 dev_priv->display.crtc_enable(crtc);
3801 else
3802 dev_priv->display.crtc_disable(crtc);
3803
3804 intel_crtc_update_sarea(crtc, enable);
3805}
3806
cdd59983
CW		 3807static void intel_crtc_disable(struct drm_crtc *crtc)
3808{
cdd59983 3809 struct drm_device *dev = crtc->dev;
976f8a20 3810 struct drm_connector *connector;
ee7b9f93 3811 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3813
976f8a20
DV		 3814 /* crtc should still be enabled when we disable it. */
3815 WARN_ON(!crtc->enabled);
3816
7b9f35a6 3817 intel_crtc->eld_vld = false;
976f8a20
DV		 3818 dev_priv->display.crtc_disable(crtc);
3819 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3820 dev_priv->display.off(crtc);
3821
931872fc
CW		 3822 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3823 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3824
3825 if (crtc->fb) {
3826 mutex_lock(&dev->struct_mutex);
1690e1eb 3827 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3828 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3829 crtc->fb = NULL;
3830 }
3831
3832 /* Update computed state. */
3833 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3834 if (!connector->encoder || !connector->encoder->crtc)
3835 continue;
3836
3837 if (connector->encoder->crtc != crtc)
3838 continue;
3839
3840 connector->dpms = DRM_MODE_DPMS_OFF;
3841 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3842 }
3843}
3844
a261b246 3845void intel_modeset_disable(struct drm_device *dev)
79e53945 3846{
a261b246
DV		 3847 struct drm_crtc *crtc;
3848
3849 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3850 if (crtc->enabled)
3851 intel_crtc_disable(crtc);
3852 }
79e53945
JB		 3853}
3854
ea5b213a 3855void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3856{
4ef69c7a 3857 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3858
ea5b213a
CW		 3859 drm_encoder_cleanup(encoder);
3860 kfree(intel_encoder);
7e7d76c3
JB		 3861}
3862
5ab432ef
DV		 3863/* Simple dpms helper for encodres with just one connector, no cloning and only
3864 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3865 * state of the entire output pipe. */
3866void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3867{
5ab432ef
DV		 3868 if (mode == DRM_MODE_DPMS_ON) {
3869 encoder->connectors_active = true;
3870
b2cabb0e 3871 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3872 } else {
3873 encoder->connectors_active = false;
3874
b2cabb0e 3875 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3876 }
79e53945
JB		 3877}
3878
0a91ca29
DV		 3879/* Cross check the actual hw state with our own modeset state tracking (and it's
3880 * internal consistency). */
b980514c 3881static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3882{
0a91ca29
DV		 3883 if (connector->get_hw_state(connector)) {
3884 struct intel_encoder *encoder = connector->encoder;
3885 struct drm_crtc *crtc;
3886 bool encoder_enabled;
3887 enum pipe pipe;
3888
3889 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3890 connector->base.base.id,
3891 drm_get_connector_name(&connector->base));
3892
3893 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3894 "wrong connector dpms state\n");
3895 WARN(connector->base.encoder != &encoder->base,
3896 "active connector not linked to encoder\n");
3897 WARN(!encoder->connectors_active,
3898 "encoder->connectors_active not set\n");
3899
3900 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3901 WARN(!encoder_enabled, "encoder not enabled\n");
3902 if (WARN_ON(!encoder->base.crtc))
3903 return;
3904
3905 crtc = encoder->base.crtc;
3906
3907 WARN(!crtc->enabled, "crtc not enabled\n");
3908 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3909 WARN(pipe != to_intel_crtc(crtc)->pipe,
3910 "encoder active on the wrong pipe\n");
3911 }
79e53945
JB		 3912}
3913
5ab432ef
DV		 3914/* Even simpler default implementation, if there's really no special case to
3915 * consider. */
3916void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3917{
5ab432ef 3918 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3919
5ab432ef
DV		 3920 /* All the simple cases only support two dpms states. */
3921 if (mode != DRM_MODE_DPMS_ON)
3922 mode = DRM_MODE_DPMS_OFF;
d4270e57 3923
5ab432ef
DV		 3924 if (mode == connector->dpms)
3925 return;
3926
3927 connector->dpms = mode;
3928
3929 /* Only need to change hw state when actually enabled */
3930 if (encoder->base.crtc)
3931 intel_encoder_dpms(encoder, mode);
3932 else
8af6cf88 3933 WARN_ON(encoder->connectors_active != false);
0a91ca29 3934
b980514c 3935 intel_modeset_check_state(connector->dev);
79e53945
JB		 3936}
3937
f0947c37
DV		 3938/* Simple connector->get_hw_state implementation for encoders that support only
3939 * one connector and no cloning and hence the encoder state determines the state
3940 * of the connector. */
3941bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3942{
24929352 3943 enum pipe pipe = 0;
f0947c37 3944 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3945
f0947c37 3946 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3947}
3948
b8cecdf5
DV		 3949static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3950 struct intel_crtc_config *pipe_config)
79e53945 3951{
2c07245f 3952 struct drm_device *dev = crtc->dev;
b8cecdf5 3953 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 3954
bad720ff 3955 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3956 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 3957 if (pipe_config->requested_mode.clock * 3
3958 > IRONLAKE_FDI_FREQ * 4)
2377b741 3959 return false;
2c07245f 3960 }
89749350 3961
f9bef081
DV		 3962 /* All interlaced capable intel hw wants timings in frames. Note though
3963 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3964 * timings, so we need to be careful not to clobber these.*/
7ae89233 3965 if (!pipe_config->timings_set)
f9bef081 3966 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3967
44f46b42
CW		 3968 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3969 * with a hsync front porch of 0.
3970 */
3971 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3972 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3973 return false;
3974
bd080ee5 3975 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 3976 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 3977 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 3978 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
3979 * for lvds. */
3980 pipe_config->pipe_bpp = 8*3;
3981 }
3982
79e53945
JB		 3983 return true;
3984}
3985
25eb05fc
JB		 3986static int valleyview_get_display_clock_speed(struct drm_device *dev)
3987{
3988 return 400000; /* FIXME */
3989}
3990
e70236a8
JB		 3991static int i945_get_display_clock_speed(struct drm_device *dev)
3992{
3993 return 400000;
3994}
79e53945 3995
e70236a8 3996static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3997{
e70236a8
JB		 3998 return 333000;
3999}
79e53945 4000
e70236a8
JB		 4001static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4002{
4003 return 200000;
4004}
79e53945 4005
e70236a8
JB		 4006static int i915gm_get_display_clock_speed(struct drm_device *dev)
4007{
4008 u16 gcfgc = 0;
79e53945 4009
e70236a8
JB		 4010 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4011
4012 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4013 return 133000;
4014 else {
4015 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4016 case GC_DISPLAY_CLOCK_333_MHZ:
4017 return 333000;
4018 default:
4019 case GC_DISPLAY_CLOCK_190_200_MHZ:
4020 return 190000;
79e53945 4021 }
e70236a8
JB		 4022 }
4023}
4024
4025static int i865_get_display_clock_speed(struct drm_device *dev)
4026{
4027 return 266000;
4028}
4029
4030static int i855_get_display_clock_speed(struct drm_device *dev)
4031{
4032 u16 hpllcc = 0;
4033 /* Assume that the hardware is in the high speed state. This
4034 * should be the default.
4035 */
4036 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4037 case GC_CLOCK_133_200:
4038 case GC_CLOCK_100_200:
4039 return 200000;
4040 case GC_CLOCK_166_250:
4041 return 250000;
4042 case GC_CLOCK_100_133:
79e53945 4043 return 133000;
e70236a8 4044 }
79e53945 4045
e70236a8
JB		 4046 /* Shouldn't happen */
4047 return 0;
4048}
79e53945 4049
e70236a8
JB		 4050static int i830_get_display_clock_speed(struct drm_device *dev)
4051{
4052 return 133000;
79e53945
JB		 4053}
4054
2c07245f 4055static void
e69d0bc1 4056intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4057{
4058 while (*num > 0xffffff || *den > 0xffffff) {
4059 *num >>= 1;
4060 *den >>= 1;
4061 }
4062}
4063
e69d0bc1
DV		 4064void
4065intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4066 int pixel_clock, int link_clock,
4067 struct intel_link_m_n *m_n)
2c07245f 4068{
e69d0bc1 4069 m_n->tu = 64;
22ed1113
CW		 4070 m_n->gmch_m = bits_per_pixel * pixel_clock;
4071 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4072 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4073 m_n->link_m = pixel_clock;
4074 m_n->link_n = link_clock;
e69d0bc1 4075 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4076}
4077
a7615030
CW		 4078static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4079{
72bbe58c
KP		 4080 if (i915_panel_use_ssc >= 0)
4081 return i915_panel_use_ssc != 0;
4082 return dev_priv->lvds_use_ssc
435793df 4083 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4084}
4085
a0c4da24
JB		 4086static int vlv_get_refclk(struct drm_crtc *crtc)
4087{
4088 struct drm_device *dev = crtc->dev;
4089 struct drm_i915_private *dev_priv = dev->dev_private;
4090 int refclk = 27000; /* for DP & HDMI */
4091
4092 return 100000; /* only one validated so far */
4093
4094 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4095 refclk = 96000;
4096 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4097 if (intel_panel_use_ssc(dev_priv))
4098 refclk = 100000;
4099 else
4100 refclk = 96000;
4101 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4102 refclk = 100000;
4103 }
4104
4105 return refclk;
4106}
4107
c65d77d8
JB		 4108static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4109{
4110 struct drm_device *dev = crtc->dev;
4111 struct drm_i915_private *dev_priv = dev->dev_private;
4112 int refclk;
4113
a0c4da24
JB		 4114 if (IS_VALLEYVIEW(dev)) {
4115 refclk = vlv_get_refclk(crtc);
4116 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4117 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4118 refclk = dev_priv->lvds_ssc_freq * 1000;
4119 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4120 refclk / 1000);
4121 } else if (!IS_GEN2(dev)) {
4122 refclk = 96000;
4123 } else {
4124 refclk = 48000;
4125 }
4126
4127 return refclk;
4128}
4129
f47709a9 4130static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
c65d77d8 4131{
f47709a9
DV		 4132 unsigned dotclock = crtc->config.adjusted_mode.clock;
4133 struct dpll *clock = &crtc->config.dpll;
4134
c65d77d8
JB		 4135 /* SDVO TV has fixed PLL values depend on its clock range,
4136 this mirrors vbios setting. */
f47709a9 4137 if (dotclock >= 100000 && dotclock < 140500) {
c65d77d8
JB		 4138 clock->p1 = 2;
4139 clock->p2 = 10;
4140 clock->n = 3;
4141 clock->m1 = 16;
4142 clock->m2 = 8;
f47709a9 4143 } else if (dotclock >= 140500 && dotclock <= 200000) {
c65d77d8
JB		 4144 clock->p1 = 1;
4145 clock->p2 = 10;
4146 clock->n = 6;
4147 clock->m1 = 12;
4148 clock->m2 = 8;
4149 }
f47709a9
DV		 4150
4151 crtc->config.clock_set = true;
c65d77d8
JB		 4152}
4153
7429e9d4
DV		 4154static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4155{
4156 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4157}
4158
4159static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4160{
4161 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4162}
4163
f47709a9 4164static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4165 intel_clock_t *reduced_clock)
4166{
f47709a9 4167 struct drm_device *dev = crtc->base.dev;
a7516a05 4168 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4169 int pipe = crtc->pipe;
a7516a05
JB		 4170 u32 fp, fp2 = 0;
4171
4172 if (IS_PINEVIEW(dev)) {
7429e9d4 4173 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4174 if (reduced_clock)
7429e9d4 4175 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4176 } else {
7429e9d4 4177 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4178 if (reduced_clock)
7429e9d4 4179 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4180 }
4181
4182 I915_WRITE(FP0(pipe), fp);
4183
f47709a9
DV		 4184 crtc->lowfreq_avail = false;
4185 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4186 reduced_clock && i915_powersave) {
4187 I915_WRITE(FP1(pipe), fp2);
f47709a9 4188 crtc->lowfreq_avail = true;
a7516a05
JB		 4189 } else {
4190 I915_WRITE(FP1(pipe), fp);
4191 }
4192}
4193
89b667f8
JB		 4194static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4195{
4196 u32 reg_val;
4197
4198 /*
4199 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4200 * and set it to a reasonable value instead.
4201 */
4202 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4203 reg_val &= 0xffffff00;
4204 reg_val |= 0x00000030;
4205 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4206
4207 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4208 reg_val &= 0x8cffffff;
4209 reg_val = 0x8c000000;
4210 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4211
4212 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4213 reg_val &= 0xffffff00;
4214 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4215
4216 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4217 reg_val &= 0x00ffffff;
4218 reg_val |= 0xb0000000;
4219 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4220}
4221
03afc4a2
DV		 4222static void intel_dp_set_m_n(struct intel_crtc *crtc)
4223{
4224 if (crtc->config.has_pch_encoder)
4225 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4226 else
4227 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4228}
4229
f47709a9 4230static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4231{
f47709a9 4232 struct drm_device *dev = crtc->base.dev;
a0c4da24 4233 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8
JB		 4234 struct drm_display_mode *adjusted_mode =
4235 &crtc->config.adjusted_mode;
4236 struct intel_encoder *encoder;
f47709a9 4237 int pipe = crtc->pipe;
89b667f8 4238 u32 dpll, mdiv;
a0c4da24 4239 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8
JB		 4240 bool is_hdmi;
4241 u32 coreclk, reg_val, temp;
a0c4da24 4242
09153000
DV		 4243 mutex_lock(&dev_priv->dpio_lock);
4244
89b667f8 4245 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4246
f47709a9
DV		 4247 bestn = crtc->config.dpll.n;
4248 bestm1 = crtc->config.dpll.m1;
4249 bestm2 = crtc->config.dpll.m2;
4250 bestp1 = crtc->config.dpll.p1;
4251 bestp2 = crtc->config.dpll.p2;
a0c4da24 4252
89b667f8
JB		 4253 /* See eDP HDMI DPIO driver vbios notes doc */
4254
4255 /* PLL B needs special handling */
4256 if (pipe)
4257 vlv_pllb_recal_opamp(dev_priv);
4258
4259 /* Set up Tx target for periodic Rcomp update */
4260 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4261
4262 /* Disable target IRef on PLL */
4263 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4264 reg_val &= 0x00ffffff;
4265 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4266
4267 /* Disable fast lock */
4268 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4269
4270 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4271 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4272 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4273 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4274 mdiv |= (1 << DPIO_K_SHIFT);
89b667f8
JB		 4275 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
4276 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4277 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4278 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
a0c4da24
JB		 4279 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4280
89b667f8
JB		 4281 mdiv |= DPIO_ENABLE_CALIBRATION;
4282 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4283
89b667f8
JB		 4284 /* Set HBR and RBR LPF coefficients */
4285 if (adjusted_mode->clock == 162000 ||
4286 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4287 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4288 0x005f0021);
4289 else
4290 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4291 0x00d0000f);
4292
4293 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4294 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4295 /* Use SSC source */
4296 if (!pipe)
4297 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4298 0x0df40000);
4299 else
4300 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4301 0x0df70000);
4302 } else { /* HDMI or VGA */
4303 /* Use bend source */
4304 if (!pipe)
4305 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4306 0x0df70000);
4307 else
4308 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4309 0x0df40000);
4310 }
a0c4da24 4311
89b667f8
JB		 4312 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4313 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4314 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4315 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4316 coreclk |= 0x01000000;
4317 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4318
89b667f8 4319 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4320
89b667f8
JB		 4321 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4322 if (encoder->pre_pll_enable)
4323 encoder->pre_pll_enable(encoder);
2a8f64ca 4324
89b667f8
JB		 4325 /* Enable DPIO clock input */
4326 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4327 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4328 if (pipe)
4329 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4330
89b667f8 4331 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4332 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4333 POSTING_READ(DPLL(pipe));
4334 udelay(150);
a0c4da24 4335
89b667f8
JB		 4336 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4337 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4338
4339 if (is_hdmi) {
6cc5f341 4340 temp = 0;
f47709a9
DV		 4341 if (crtc->config.pixel_multiplier > 1) {
4342 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4343 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4344 }
a0c4da24 4345
89b667f8
JB		 4346 I915_WRITE(DPLL_MD(pipe), temp);
4347 POSTING_READ(DPLL_MD(pipe));
2a8f64ca 4348 }
f47709a9 4349
89b667f8
JB		 4350 if (crtc->config.has_dp_encoder)
4351 intel_dp_set_m_n(crtc);
09153000
DV		 4352
4353 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4354}
4355
f47709a9
DV		 4356static void i9xx_update_pll(struct intel_crtc *crtc,
4357 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4358 int num_connectors)
4359{
f47709a9 4360 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4361 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4362 struct intel_encoder *encoder;
f47709a9 4363 int pipe = crtc->pipe;
eb1cbe48
DV		 4364 u32 dpll;
4365 bool is_sdvo;
f47709a9 4366 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4367
f47709a9 4368 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4369
f47709a9
DV		 4370 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4371 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4372
4373 dpll = DPLL_VGA_MODE_DIS;
4374
f47709a9 4375 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4376 dpll |= DPLLB_MODE_LVDS;
4377 else
4378 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4379
eb1cbe48 4380 if (is_sdvo) {
f47709a9 4381 if ((crtc->config.pixel_multiplier > 1) &&
6cc5f341 4382 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
f47709a9 4383 dpll |= (crtc->config.pixel_multiplier - 1)
6cc5f341 4384 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48
DV		 4385 }
4386 dpll |= DPLL_DVO_HIGH_SPEED;
4387 }
f47709a9 4388 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4389 dpll |= DPLL_DVO_HIGH_SPEED;
4390
4391 /* compute bitmask from p1 value */
4392 if (IS_PINEVIEW(dev))
4393 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4394 else {
4395 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4396 if (IS_G4X(dev) && reduced_clock)
4397 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4398 }
4399 switch (clock->p2) {
4400 case 5:
4401 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4402 break;
4403 case 7:
4404 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4405 break;
4406 case 10:
4407 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4408 break;
4409 case 14:
4410 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4411 break;
4412 }
4413 if (INTEL_INFO(dev)->gen >= 4)
4414 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4415
f47709a9 4416 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48 4417 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4418 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48
DV		 4419 /* XXX: just matching BIOS for now */
4420 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4421 dpll |= 3;
f47709a9 4422 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4423 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4424 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4425 else
4426 dpll |= PLL_REF_INPUT_DREFCLK;
4427
4428 dpll |= DPLL_VCO_ENABLE;
4429 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4430 POSTING_READ(DPLL(pipe));
4431 udelay(150);
4432
f47709a9 4433 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4434 if (encoder->pre_pll_enable)
4435 encoder->pre_pll_enable(encoder);
eb1cbe48 4436
f47709a9
DV		 4437 if (crtc->config.has_dp_encoder)
4438 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4439
4440 I915_WRITE(DPLL(pipe), dpll);
4441
4442 /* Wait for the clocks to stabilize. */
4443 POSTING_READ(DPLL(pipe));
4444 udelay(150);
4445
4446 if (INTEL_INFO(dev)->gen >= 4) {
4447 u32 temp = 0;
4448 if (is_sdvo) {
6cc5f341 4449 temp = 0;
f47709a9
DV		 4450 if (crtc->config.pixel_multiplier > 1) {
4451 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4452 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4453 }
eb1cbe48
DV		 4454 }
4455 I915_WRITE(DPLL_MD(pipe), temp);
4456 } else {
4457 /* The pixel multiplier can only be updated once the
4458 * DPLL is enabled and the clocks are stable.
4459 *
4460 * So write it again.
4461 */
4462 I915_WRITE(DPLL(pipe), dpll);
4463 }
4464}
4465
f47709a9 4466static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4467 struct drm_display_mode *adjusted_mode,
f47709a9 4468 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4469 int num_connectors)
4470{
f47709a9 4471 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4472 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4473 struct intel_encoder *encoder;
f47709a9 4474 int pipe = crtc->pipe;
eb1cbe48 4475 u32 dpll;
f47709a9 4476 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4477
f47709a9 4478 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4479
eb1cbe48
DV		 4480 dpll = DPLL_VGA_MODE_DIS;
4481
f47709a9 4482 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4483 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4484 } else {
4485 if (clock->p1 == 2)
4486 dpll |= PLL_P1_DIVIDE_BY_TWO;
4487 else
4488 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4489 if (clock->p2 == 4)
4490 dpll |= PLL_P2_DIVIDE_BY_4;
4491 }
4492
f47709a9 4493 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4494 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4495 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4496 else
4497 dpll |= PLL_REF_INPUT_DREFCLK;
4498
4499 dpll |= DPLL_VCO_ENABLE;
4500 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4501 POSTING_READ(DPLL(pipe));
4502 udelay(150);
4503
f47709a9 4504 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4505 if (encoder->pre_pll_enable)
4506 encoder->pre_pll_enable(encoder);
eb1cbe48 4507
5b5896e4
DV		 4508 I915_WRITE(DPLL(pipe), dpll);
4509
4510 /* Wait for the clocks to stabilize. */
4511 POSTING_READ(DPLL(pipe));
4512 udelay(150);
4513
eb1cbe48
DV		 4514 /* The pixel multiplier can only be updated once the
4515 * DPLL is enabled and the clocks are stable.
4516 *
4517 * So write it again.
4518 */
4519 I915_WRITE(DPLL(pipe), dpll);
4520}
4521
b0e77b9c
PZ		 4522static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4523 struct drm_display_mode *mode,
4524 struct drm_display_mode *adjusted_mode)
4525{
4526 struct drm_device *dev = intel_crtc->base.dev;
4527 struct drm_i915_private *dev_priv = dev->dev_private;
4528 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4529 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
b0e77b9c
PZ		 4530 uint32_t vsyncshift;
4531
4532 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4533 /* the chip adds 2 halflines automatically */
4534 adjusted_mode->crtc_vtotal -= 1;
4535 adjusted_mode->crtc_vblank_end -= 1;
4536 vsyncshift = adjusted_mode->crtc_hsync_start
4537 - adjusted_mode->crtc_htotal / 2;
4538 } else {
4539 vsyncshift = 0;
4540 }
4541
4542 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4543 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4544
fe2b8f9d 4545 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4546 (adjusted_mode->crtc_hdisplay - 1) |
4547 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4548 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4549 (adjusted_mode->crtc_hblank_start - 1) |
4550 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4551 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4552 (adjusted_mode->crtc_hsync_start - 1) |
4553 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4554
fe2b8f9d 4555 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4556 (adjusted_mode->crtc_vdisplay - 1) |
4557 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4558 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4559 (adjusted_mode->crtc_vblank_start - 1) |
4560 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4561 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4562 (adjusted_mode->crtc_vsync_start - 1) |
4563 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4564
b5e508d4
PZ		 4565 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4566 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4567 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4568 * bits. */
4569 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4570 (pipe == PIPE_B || pipe == PIPE_C))
4571 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4572
b0e77b9c
PZ		 4573 /* pipesrc controls the size that is scaled from, which should
4574 * always be the user's requested size.
4575 */
4576 I915_WRITE(PIPESRC(pipe),
4577 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4578}
4579
84b046f3
DV		 4580static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4581{
4582 struct drm_device *dev = intel_crtc->base.dev;
4583 struct drm_i915_private *dev_priv = dev->dev_private;
4584 uint32_t pipeconf;
4585
4586 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4587
4588 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4589 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4590 * core speed.
4591 *
4592 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4593 * pipe == 0 check?
4594 */
4595 if (intel_crtc->config.requested_mode.clock >
4596 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4597 pipeconf |= PIPECONF_DOUBLE_WIDE;
4598 else
4599 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4600 }
4601
4602 /* default to 8bpc */
4603 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4604 if (intel_crtc->config.has_dp_encoder) {
4605 if (intel_crtc->config.dither) {
4606 pipeconf |= PIPECONF_6BPC |
4607 PIPECONF_DITHER_EN |
4608 PIPECONF_DITHER_TYPE_SP;
4609 }
4610 }
4611
4612 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
4613 INTEL_OUTPUT_EDP)) {
4614 if (intel_crtc->config.dither) {
4615 pipeconf |= PIPECONF_6BPC |
4616 PIPECONF_ENABLE |
4617 I965_PIPECONF_ACTIVE;
4618 }
4619 }
4620
4621 if (HAS_PIPE_CXSR(dev)) {
4622 if (intel_crtc->lowfreq_avail) {
4623 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4624 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4625 } else {
4626 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4627 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4628 }
4629 }
4630
4631 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4632 if (!IS_GEN2(dev) &&
4633 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4634 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4635 else
4636 pipeconf |= PIPECONF_PROGRESSIVE;
4637
9c8e09b7
VS		 4638 if (IS_VALLEYVIEW(dev)) {
4639 if (intel_crtc->config.limited_color_range)
4640 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4641 else
4642 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4643 }
4644
84b046f3
DV		 4645 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4646 POSTING_READ(PIPECONF(intel_crtc->pipe));
4647}
4648
f564048e 4649static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4650 int x, int y,
94352cf9 4651 struct drm_framebuffer *fb)
79e53945
JB		 4652{
4653 struct drm_device *dev = crtc->dev;
4654 struct drm_i915_private *dev_priv = dev->dev_private;
4655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4656 struct drm_display_mode *adjusted_mode =
4657 &intel_crtc->config.adjusted_mode;
4658 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4659 int pipe = intel_crtc->pipe;
80824003 4660 int plane = intel_crtc->plane;
c751ce4f 4661 int refclk, num_connectors = 0;
652c393a 4662 intel_clock_t clock, reduced_clock;
84b046f3 4663 u32 dspcntr;
eb1cbe48 4664 bool ok, has_reduced_clock = false, is_sdvo = false;
8b47047b 4665 bool is_lvds = false, is_tv = false;
5eddb70b 4666 struct intel_encoder *encoder;
d4906093 4667 const intel_limit_t *limit;
5c3b82e2 4668 int ret;
79e53945 4669
6c2b7c12 4670 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4671 switch (encoder->type) {
79e53945
JB		 4672 case INTEL_OUTPUT_LVDS:
4673 is_lvds = true;
4674 break;
4675 case INTEL_OUTPUT_SDVO:
7d57382e 4676 case INTEL_OUTPUT_HDMI:
79e53945 4677 is_sdvo = true;
5eddb70b 4678 if (encoder->needs_tv_clock)
e2f0ba97 4679 is_tv = true;
79e53945 4680 break;
79e53945
JB		 4681 case INTEL_OUTPUT_TVOUT:
4682 is_tv = true;
4683 break;
79e53945 4684 }
43565a06 4685
c751ce4f 4686 num_connectors++;
79e53945
JB		 4687 }
4688
c65d77d8 4689 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4690
d4906093
ML		 4691 /*
4692 * Returns a set of divisors for the desired target clock with the given
4693 * refclk, or FALSE. The returned values represent the clock equation:
4694 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4695 */
1b894b59 4696 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4697 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4698 &clock);
79e53945
JB		 4699 if (!ok) {
4700 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4701 return -EINVAL;
79e53945
JB		 4702 }
4703
cda4b7d3 4704 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4705 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4706
ddc9003c 4707 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4708 /*
4709 * Ensure we match the reduced clock's P to the target clock.
4710 * If the clocks don't match, we can't switch the display clock
4711 * by using the FP0/FP1. In such case we will disable the LVDS
4712 * downclock feature.
4713 */
ddc9003c 4714 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4715 dev_priv->lvds_downclock,
4716 refclk,
cec2f356 4717 &clock,
5eddb70b 4718 &reduced_clock);
7026d4ac 4719 }
f47709a9
DV		 4720 /* Compat-code for transition, will disappear. */
4721 if (!intel_crtc->config.clock_set) {
4722 intel_crtc->config.dpll.n = clock.n;
4723 intel_crtc->config.dpll.m1 = clock.m1;
4724 intel_crtc->config.dpll.m2 = clock.m2;
4725 intel_crtc->config.dpll.p1 = clock.p1;
4726 intel_crtc->config.dpll.p2 = clock.p2;
4727 }
7026d4ac 4728
c65d77d8 4729 if (is_sdvo && is_tv)
f47709a9 4730 i9xx_adjust_sdvo_tv_clock(intel_crtc);
7026d4ac 4731
eb1cbe48 4732 if (IS_GEN2(dev))
f47709a9 4733 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4734 has_reduced_clock ? &reduced_clock : NULL,
4735 num_connectors);
a0c4da24 4736 else if (IS_VALLEYVIEW(dev))
f47709a9 4737 vlv_update_pll(intel_crtc);
79e53945 4738 else
f47709a9 4739 i9xx_update_pll(intel_crtc,
eb1cbe48 4740 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4741 num_connectors);
79e53945 4742
79e53945
JB		 4743 /* Set up the display plane register */
4744 dspcntr = DISPPLANE_GAMMA_ENABLE;
4745
da6ecc5d
JB		 4746 if (!IS_VALLEYVIEW(dev)) {
4747 if (pipe == 0)
4748 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4749 else
4750 dspcntr |= DISPPLANE_SEL_PIPE_B;
4751 }
79e53945 4752
2582a850 4753 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 4754 drm_mode_debug_printmodeline(mode);
4755
b0e77b9c 4756 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4757
4758 /* pipesrc and dspsize control the size that is scaled from,
4759 * which should always be the user's requested size.
79e53945 4760 */
929c77fb
EA		 4761 I915_WRITE(DSPSIZE(plane),
4762 ((mode->vdisplay - 1) << 16) |
4763 (mode->hdisplay - 1));
4764 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4765
84b046f3
DV		 4766 i9xx_set_pipeconf(intel_crtc);
4767
f564048e
EA		 4768 I915_WRITE(DSPCNTR(plane), dspcntr);
4769 POSTING_READ(DSPCNTR(plane));
4770
94352cf9 4771 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4772
4773 intel_update_watermarks(dev);
4774
f564048e
EA		 4775 return ret;
4776}
4777
0e8ffe1b
DV		 4778static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4779 struct intel_crtc_config *pipe_config)
4780{
4781 struct drm_device *dev = crtc->base.dev;
4782 struct drm_i915_private *dev_priv = dev->dev_private;
4783 uint32_t tmp;
4784
4785 tmp = I915_READ(PIPECONF(crtc->pipe));
4786 if (!(tmp & PIPECONF_ENABLE))
4787 return false;
4788
4789 return true;
4790}
4791
dde86e2d 4792static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4793{
4794 struct drm_i915_private *dev_priv = dev->dev_private;
4795 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4796 struct intel_encoder *encoder;
74cfd7ac 4797 u32 val, final;
13d83a67 4798 bool has_lvds = false;
199e5d79
KP		 4799 bool has_cpu_edp = false;
4800 bool has_pch_edp = false;
4801 bool has_panel = false;
99eb6a01
KP		 4802 bool has_ck505 = false;
4803 bool can_ssc = false;
13d83a67
JB		 4804
4805 /* We need to take the global config into account */
199e5d79
KP		 4806 list_for_each_entry(encoder, &mode_config->encoder_list,
4807 base.head) {
4808 switch (encoder->type) {
4809 case INTEL_OUTPUT_LVDS:
4810 has_panel = true;
4811 has_lvds = true;
4812 break;
4813 case INTEL_OUTPUT_EDP:
4814 has_panel = true;
4815 if (intel_encoder_is_pch_edp(&encoder->base))
4816 has_pch_edp = true;
4817 else
4818 has_cpu_edp = true;
4819 break;
13d83a67
JB		 4820 }
4821 }
4822
99eb6a01
KP		 4823 if (HAS_PCH_IBX(dev)) {
4824 has_ck505 = dev_priv->display_clock_mode;
4825 can_ssc = has_ck505;
4826 } else {
4827 has_ck505 = false;
4828 can_ssc = true;
4829 }
4830
4831 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4832 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4833 has_ck505);
13d83a67
JB		 4834
4835 /* Ironlake: try to setup display ref clock before DPLL
4836 * enabling. This is only under driver's control after
4837 * PCH B stepping, previous chipset stepping should be
4838 * ignoring this setting.
4839 */
74cfd7ac
CW		 4840 val = I915_READ(PCH_DREF_CONTROL);
4841
4842 /* As we must carefully and slowly disable/enable each source in turn,
4843 * compute the final state we want first and check if we need to
4844 * make any changes at all.
4845 */
4846 final = val;
4847 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4848 if (has_ck505)
4849 final |= DREF_NONSPREAD_CK505_ENABLE;
4850 else
4851 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4852
4853 final &= ~DREF_SSC_SOURCE_MASK;
4854 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4855 final &= ~DREF_SSC1_ENABLE;
4856
4857 if (has_panel) {
4858 final |= DREF_SSC_SOURCE_ENABLE;
4859
4860 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4861 final |= DREF_SSC1_ENABLE;
4862
4863 if (has_cpu_edp) {
4864 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4865 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4866 else
4867 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4868 } else
4869 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4870 } else {
4871 final |= DREF_SSC_SOURCE_DISABLE;
4872 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4873 }
4874
4875 if (final == val)
4876 return;
4877
13d83a67 4878 /* Always enable nonspread source */
74cfd7ac 4879 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4880
99eb6a01 4881 if (has_ck505)
74cfd7ac 4882 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 4883 else
74cfd7ac 4884 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4885
199e5d79 4886 if (has_panel) {
74cfd7ac
CW		 4887 val &= ~DREF_SSC_SOURCE_MASK;
4888 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4889
199e5d79 4890 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4891 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4892 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 4893 val |= DREF_SSC1_ENABLE;
e77166b5 4894 } else
74cfd7ac 4895 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4896
4897 /* Get SSC going before enabling the outputs */
74cfd7ac 4898 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4899 POSTING_READ(PCH_DREF_CONTROL);
4900 udelay(200);
4901
74cfd7ac 4902 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 4903
4904 /* Enable CPU source on CPU attached eDP */
199e5d79 4905 if (has_cpu_edp) {
99eb6a01 4906 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4907 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 4908 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4909 }
13d83a67 4910 else
74cfd7ac 4911 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 4912 } else
74cfd7ac 4913 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4914
74cfd7ac 4915 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4916 POSTING_READ(PCH_DREF_CONTROL);
4917 udelay(200);
4918 } else {
4919 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4920
74cfd7ac 4921 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 4922
4923 /* Turn off CPU output */
74cfd7ac 4924 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4925
74cfd7ac 4926 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4927 POSTING_READ(PCH_DREF_CONTROL);
4928 udelay(200);
4929
4930 /* Turn off the SSC source */
74cfd7ac
CW		 4931 val &= ~DREF_SSC_SOURCE_MASK;
4932 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 4933
4934 /* Turn off SSC1 */
74cfd7ac 4935 val &= ~DREF_SSC1_ENABLE;
199e5d79 4936
74cfd7ac 4937 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 4938 POSTING_READ(PCH_DREF_CONTROL);
4939 udelay(200);
4940 }
74cfd7ac
CW		 4941
4942 BUG_ON(val != final);
13d83a67
JB		 4943}
4944
dde86e2d
PZ		 4945/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4946static void lpt_init_pch_refclk(struct drm_device *dev)
4947{
4948 struct drm_i915_private *dev_priv = dev->dev_private;
4949 struct drm_mode_config *mode_config = &dev->mode_config;
4950 struct intel_encoder *encoder;
4951 bool has_vga = false;
4952 bool is_sdv = false;
4953 u32 tmp;
4954
4955 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4956 switch (encoder->type) {
4957 case INTEL_OUTPUT_ANALOG:
4958 has_vga = true;
4959 break;
4960 }
4961 }
4962
4963 if (!has_vga)
4964 return;
4965
c00db246
DV		 4966 mutex_lock(&dev_priv->dpio_lock);
4967
dde86e2d
PZ		 4968 /* XXX: Rip out SDV support once Haswell ships for real. */
4969 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4970 is_sdv = true;
4971
4972 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4973 tmp &= ~SBI_SSCCTL_DISABLE;
4974 tmp |= SBI_SSCCTL_PATHALT;
4975 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4976
4977 udelay(24);
4978
4979 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4980 tmp &= ~SBI_SSCCTL_PATHALT;
4981 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4982
4983 if (!is_sdv) {
4984 tmp = I915_READ(SOUTH_CHICKEN2);
4985 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4986 I915_WRITE(SOUTH_CHICKEN2, tmp);
4987
4988 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4989 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4990 DRM_ERROR("FDI mPHY reset assert timeout\n");
4991
4992 tmp = I915_READ(SOUTH_CHICKEN2);
4993 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4994 I915_WRITE(SOUTH_CHICKEN2, tmp);
4995
4996 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4997 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4998 100))
4999 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5000 }
5001
5002 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5003 tmp &= ~(0xFF << 24);
5004 tmp |= (0x12 << 24);
5005 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5006
dde86e2d
PZ		 5007 if (is_sdv) {
5008 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5009 tmp |= 0x7FFF;
5010 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5011 }
5012
5013 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5014 tmp |= (1 << 11);
5015 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5016
5017 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5018 tmp |= (1 << 11);
5019 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5020
5021 if (is_sdv) {
5022 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5023 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5024 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5025
5026 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5027 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5028 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5029
5030 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5031 tmp |= (0x3F << 8);
5032 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5033
5034 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5035 tmp |= (0x3F << 8);
5036 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5037 }
5038
5039 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5040 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5041 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5042
5043 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5044 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5045 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5046
5047 if (!is_sdv) {
5048 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5049 tmp &= ~(7 << 13);
5050 tmp |= (5 << 13);
5051 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5052
5053 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5054 tmp &= ~(7 << 13);
5055 tmp |= (5 << 13);
5056 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5057 }
5058
5059 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5060 tmp &= ~0xFF;
5061 tmp |= 0x1C;
5062 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5063
5064 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5065 tmp &= ~0xFF;
5066 tmp |= 0x1C;
5067 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5068
5069 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5070 tmp &= ~(0xFF << 16);
5071 tmp |= (0x1C << 16);
5072 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5073
5074 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5075 tmp &= ~(0xFF << 16);
5076 tmp |= (0x1C << 16);
5077 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5078
5079 if (!is_sdv) {
5080 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5081 tmp |= (1 << 27);
5082 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5083
5084 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5085 tmp |= (1 << 27);
5086 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5087
5088 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5089 tmp &= ~(0xF << 28);
5090 tmp |= (4 << 28);
5091 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5092
5093 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5094 tmp &= ~(0xF << 28);
5095 tmp |= (4 << 28);
5096 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5097 }
5098
5099 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5100 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5101 tmp |= SBI_DBUFF0_ENABLE;
5102 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5103
5104 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5105}
5106
5107/*
5108 * Initialize reference clocks when the driver loads
5109 */
5110void intel_init_pch_refclk(struct drm_device *dev)
5111{
5112 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5113 ironlake_init_pch_refclk(dev);
5114 else if (HAS_PCH_LPT(dev))
5115 lpt_init_pch_refclk(dev);
5116}
5117
d9d444cb
JB		 5118static int ironlake_get_refclk(struct drm_crtc *crtc)
5119{
5120 struct drm_device *dev = crtc->dev;
5121 struct drm_i915_private *dev_priv = dev->dev_private;
5122 struct intel_encoder *encoder;
d9d444cb
JB		 5123 struct intel_encoder *edp_encoder = NULL;
5124 int num_connectors = 0;
5125 bool is_lvds = false;
5126
6c2b7c12 5127 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5128 switch (encoder->type) {
5129 case INTEL_OUTPUT_LVDS:
5130 is_lvds = true;
5131 break;
5132 case INTEL_OUTPUT_EDP:
5133 edp_encoder = encoder;
5134 break;
5135 }
5136 num_connectors++;
5137 }
5138
5139 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5140 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5141 dev_priv->lvds_ssc_freq);
5142 return dev_priv->lvds_ssc_freq * 1000;
5143 }
5144
5145 return 120000;
5146}
5147
c8203565 5148static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5149 struct drm_display_mode *adjusted_mode,
c8203565 5150 bool dither)
79e53945 5151{
c8203565 5152 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5154 int pipe = intel_crtc->pipe;
c8203565
PZ		 5155 uint32_t val;
5156
5157 val = I915_READ(PIPECONF(pipe));
5158
dfd07d72 5159 val &= ~PIPECONF_BPC_MASK;
965e0c48 5160 switch (intel_crtc->config.pipe_bpp) {
c8203565 5161 case 18:
dfd07d72 5162 val |= PIPECONF_6BPC;
c8203565
PZ		 5163 break;
5164 case 24:
dfd07d72 5165 val |= PIPECONF_8BPC;
c8203565
PZ		 5166 break;
5167 case 30:
dfd07d72 5168 val |= PIPECONF_10BPC;
c8203565
PZ		 5169 break;
5170 case 36:
dfd07d72 5171 val |= PIPECONF_12BPC;
c8203565
PZ		 5172 break;
5173 default:
cc769b62
PZ		 5174 /* Case prevented by intel_choose_pipe_bpp_dither. */
5175 BUG();
c8203565
PZ		 5176 }
5177
5178 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5179 if (dither)
5180 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5181
5182 val &= ~PIPECONF_INTERLACE_MASK;
5183 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5184 val |= PIPECONF_INTERLACED_ILK;
5185 else
5186 val |= PIPECONF_PROGRESSIVE;
5187
50f3b016 5188 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5189 val |= PIPECONF_COLOR_RANGE_SELECT;
5190 else
5191 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5192
c8203565
PZ		 5193 I915_WRITE(PIPECONF(pipe), val);
5194 POSTING_READ(PIPECONF(pipe));
5195}
5196
86d3efce
VS		 5197/*
5198 * Set up the pipe CSC unit.
5199 *
5200 * Currently only full range RGB to limited range RGB conversion
5201 * is supported, but eventually this should handle various
5202 * RGB<->YCbCr scenarios as well.
5203 */
50f3b016 5204static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5205{
5206 struct drm_device *dev = crtc->dev;
5207 struct drm_i915_private *dev_priv = dev->dev_private;
5208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5209 int pipe = intel_crtc->pipe;
5210 uint16_t coeff = 0x7800; /* 1.0 */
5211
5212 /*
5213 * TODO: Check what kind of values actually come out of the pipe
5214 * with these coeff/postoff values and adjust to get the best
5215 * accuracy. Perhaps we even need to take the bpc value into
5216 * consideration.
5217 */
5218
50f3b016 5219 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5220 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5221
5222 /*
5223 * GY/GU and RY/RU should be the other way around according
5224 * to BSpec, but reality doesn't agree. Just set them up in
5225 * a way that results in the correct picture.
5226 */
5227 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5228 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5229
5230 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5231 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5232
5233 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5234 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5235
5236 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5237 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5238 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5239
5240 if (INTEL_INFO(dev)->gen > 6) {
5241 uint16_t postoff = 0;
5242
50f3b016 5243 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5244 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5245
5246 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5247 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5248 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5249
5250 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5251 } else {
5252 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5253
50f3b016 5254 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5255 mode |= CSC_BLACK_SCREEN_OFFSET;
5256
5257 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5258 }
5259}
5260
ee2b0b38
PZ		 5261static void haswell_set_pipeconf(struct drm_crtc *crtc,
5262 struct drm_display_mode *adjusted_mode,
5263 bool dither)
5264{
5265 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5267 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5268 uint32_t val;
5269
702e7a56 5270 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5271
5272 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5273 if (dither)
5274 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5275
5276 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5277 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5278 val |= PIPECONF_INTERLACED_ILK;
5279 else
5280 val |= PIPECONF_PROGRESSIVE;
5281
702e7a56
PZ		 5282 I915_WRITE(PIPECONF(cpu_transcoder), val);
5283 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5284}
5285
6591c6e4
PZ		 5286static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5287 struct drm_display_mode *adjusted_mode,
5288 intel_clock_t *clock,
5289 bool *has_reduced_clock,
5290 intel_clock_t *reduced_clock)
5291{
5292 struct drm_device *dev = crtc->dev;
5293 struct drm_i915_private *dev_priv = dev->dev_private;
5294 struct intel_encoder *intel_encoder;
5295 int refclk;
d4906093 5296 const intel_limit_t *limit;
6591c6e4 5297 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5298
6591c6e4
PZ		 5299 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5300 switch (intel_encoder->type) {
79e53945
JB		 5301 case INTEL_OUTPUT_LVDS:
5302 is_lvds = true;
5303 break;
5304 case INTEL_OUTPUT_SDVO:
7d57382e 5305 case INTEL_OUTPUT_HDMI:
79e53945 5306 is_sdvo = true;
6591c6e4 5307 if (intel_encoder->needs_tv_clock)
e2f0ba97 5308 is_tv = true;
79e53945 5309 break;
79e53945
JB		 5310 case INTEL_OUTPUT_TVOUT:
5311 is_tv = true;
5312 break;
79e53945
JB		 5313 }
5314 }
5315
d9d444cb 5316 refclk = ironlake_get_refclk(crtc);
79e53945 5317
d4906093
ML		 5318 /*
5319 * Returns a set of divisors for the desired target clock with the given
5320 * refclk, or FALSE. The returned values represent the clock equation:
5321 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5322 */
1b894b59 5323 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5324 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5325 clock);
5326 if (!ret)
5327 return false;
cda4b7d3 5328
ddc9003c 5329 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5330 /*
5331 * Ensure we match the reduced clock's P to the target clock.
5332 * If the clocks don't match, we can't switch the display clock
5333 * by using the FP0/FP1. In such case we will disable the LVDS
5334 * downclock feature.
5335 */
6591c6e4
PZ		 5336 *has_reduced_clock = limit->find_pll(limit, crtc,
5337 dev_priv->lvds_downclock,
5338 refclk,
5339 clock,
5340 reduced_clock);
652c393a 5341 }
61e9653f
DV		 5342
5343 if (is_sdvo && is_tv)
f47709a9 5344 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
6591c6e4
PZ		 5345
5346 return true;
5347}
5348
01a415fd
DV		 5349static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5350{
5351 struct drm_i915_private *dev_priv = dev->dev_private;
5352 uint32_t temp;
5353
5354 temp = I915_READ(SOUTH_CHICKEN1);
5355 if (temp & FDI_BC_BIFURCATION_SELECT)
5356 return;
5357
5358 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5359 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5360
5361 temp |= FDI_BC_BIFURCATION_SELECT;
5362 DRM_DEBUG_KMS("enabling fdi C rx\n");
5363 I915_WRITE(SOUTH_CHICKEN1, temp);
5364 POSTING_READ(SOUTH_CHICKEN1);
5365}
5366
5367static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5368{
5369 struct drm_device *dev = intel_crtc->base.dev;
5370 struct drm_i915_private *dev_priv = dev->dev_private;
5371 struct intel_crtc *pipe_B_crtc =
5372 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5373
84f44ce7
VS		 5374 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5375 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd 5376 if (intel_crtc->fdi_lanes > 4) {
84f44ce7
VS		 5377 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5378 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd
DV		 5379 /* Clamp lanes to avoid programming the hw with bogus values. */
5380 intel_crtc->fdi_lanes = 4;
5381
5382 return false;
5383 }
5384
7eb552ae 5385 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5386 return true;
5387
5388 switch (intel_crtc->pipe) {
5389 case PIPE_A:
5390 return true;
5391 case PIPE_B:
5392 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5393 intel_crtc->fdi_lanes > 2) {
84f44ce7
VS		 5394 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5395 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd
DV		 5396 /* Clamp lanes to avoid programming the hw with bogus values. */
5397 intel_crtc->fdi_lanes = 2;
5398
5399 return false;
5400 }
5401
5402 if (intel_crtc->fdi_lanes > 2)
5403 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5404 else
5405 cpt_enable_fdi_bc_bifurcation(dev);
5406
5407 return true;
5408 case PIPE_C:
5409 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5410 if (intel_crtc->fdi_lanes > 2) {
84f44ce7
VS		 5411 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5412 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd
DV		 5413 /* Clamp lanes to avoid programming the hw with bogus values. */
5414 intel_crtc->fdi_lanes = 2;
5415
5416 return false;
5417 }
5418 } else {
5419 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5420 return false;
5421 }
5422
5423 cpt_enable_fdi_bc_bifurcation(dev);
5424
5425 return true;
5426 default:
5427 BUG();
5428 }
5429}
5430
d4b1931c
PZ		 5431int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5432{
5433 /*
5434 * Account for spread spectrum to avoid
5435 * oversubscribing the link. Max center spread
5436 * is 2.5%; use 5% for safety's sake.
5437 */
5438 u32 bps = target_clock * bpp * 21 / 20;
5439 return bps / (link_bw * 8) + 1;
5440}
5441
6cf86a5e
DV		 5442void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5443 struct intel_link_m_n *m_n)
79e53945 5444{
6cf86a5e
DV		 5445 struct drm_device *dev = crtc->base.dev;
5446 struct drm_i915_private *dev_priv = dev->dev_private;
5447 int pipe = crtc->pipe;
5448
5449 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5450 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5451 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5452 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5453}
5454
5455void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5456 struct intel_link_m_n *m_n)
5457{
5458 struct drm_device *dev = crtc->base.dev;
79e53945 5459 struct drm_i915_private *dev_priv = dev->dev_private;
6cf86a5e 5460 int pipe = crtc->pipe;
3b117c8f 5461 enum transcoder transcoder = crtc->config.cpu_transcoder;
6cf86a5e
DV		 5462
5463 if (INTEL_INFO(dev)->gen >= 5) {
5464 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5465 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5466 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5467 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5468 } else {
5469 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5470 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5471 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5472 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5473 }
5474}
5475
5476static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5477{
5478 struct drm_device *dev = crtc->dev;
79e53945 5479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 5480 struct drm_display_mode *adjusted_mode =
5481 &intel_crtc->config.adjusted_mode;
e69d0bc1 5482 struct intel_link_m_n m_n = {0};
6cc5f341 5483 int target_clock, lane, link_bw;
61e9653f 5484
6cf86a5e
DV		 5485 /* FDI is a binary signal running at ~2.7GHz, encoding
5486 * each output octet as 10 bits. The actual frequency
5487 * is stored as a divider into a 100MHz clock, and the
5488 * mode pixel clock is stored in units of 1KHz.
5489 * Hence the bw of each lane in terms of the mode signal
5490 * is:
5491 */
5492 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
58a27471 5493
df92b1e6
DV		 5494 if (intel_crtc->config.pixel_target_clock)
5495 target_clock = intel_crtc->config.pixel_target_clock;
94bf2ced
DV		 5496 else
5497 target_clock = adjusted_mode->clock;
5498
6cf86a5e
DV		 5499 lane = ironlake_get_lanes_required(target_clock, link_bw,
5500 intel_crtc->config.pipe_bpp);
2c07245f 5501
8febb297
EA		 5502 intel_crtc->fdi_lanes = lane;
5503
6cc5f341
DV		 5504 if (intel_crtc->config.pixel_multiplier > 1)
5505 link_bw *= intel_crtc->config.pixel_multiplier;
965e0c48
DV		 5506 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5507 link_bw, &m_n);
8febb297 5508
6cf86a5e 5509 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
f48d8f23
PZ		 5510}
5511
7429e9d4
DV		 5512static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5513{
5514 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5515}
5516
de13a2e3 5517static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5518 u32 *fp,
9a7c7890 5519 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5520{
de13a2e3 5521 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5522 struct drm_device *dev = crtc->dev;
5523 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5524 struct intel_encoder *intel_encoder;
5525 uint32_t dpll;
6cc5f341 5526 int factor, num_connectors = 0;
de13a2e3 5527 bool is_lvds = false, is_sdvo = false, is_tv = false;
79e53945 5528
de13a2e3
PZ		 5529 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5530 switch (intel_encoder->type) {
79e53945
JB		 5531 case INTEL_OUTPUT_LVDS:
5532 is_lvds = true;
5533 break;
5534 case INTEL_OUTPUT_SDVO:
7d57382e 5535 case INTEL_OUTPUT_HDMI:
79e53945 5536 is_sdvo = true;
de13a2e3 5537 if (intel_encoder->needs_tv_clock)
e2f0ba97 5538 is_tv = true;
79e53945 5539 break;
79e53945
JB		 5540 case INTEL_OUTPUT_TVOUT:
5541 is_tv = true;
5542 break;
79e53945 5543 }
43565a06 5544
c751ce4f 5545 num_connectors++;
79e53945 5546 }
79e53945 5547
c1858123 5548 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5549 factor = 21;
5550 if (is_lvds) {
5551 if ((intel_panel_use_ssc(dev_priv) &&
5552 dev_priv->lvds_ssc_freq == 100) ||
f0b44056 5553 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297
EA		 5554 factor = 25;
5555 } else if (is_sdvo && is_tv)
5556 factor = 20;
c1858123 5557
7429e9d4 5558 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5559 *fp |= FP_CB_TUNE;
2c07245f 5560
9a7c7890
DV		 5561 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5562 *fp2 |= FP_CB_TUNE;
5563
5eddb70b 5564 dpll = 0;
2c07245f 5565
a07d6787
EA		 5566 if (is_lvds)
5567 dpll |= DPLLB_MODE_LVDS;
5568 else
5569 dpll |= DPLLB_MODE_DAC_SERIAL;
5570 if (is_sdvo) {
6cc5f341
DV		 5571 if (intel_crtc->config.pixel_multiplier > 1) {
5572 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5573 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5574 }
a07d6787
EA		 5575 dpll |= DPLL_DVO_HIGH_SPEED;
5576 }
8b47047b
DV		 5577 if (intel_crtc->config.has_dp_encoder &&
5578 intel_crtc->config.has_pch_encoder)
a07d6787 5579 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5580
a07d6787 5581 /* compute bitmask from p1 value */
7429e9d4 5582 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5583 /* also FPA1 */
7429e9d4 5584 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5585
7429e9d4 5586 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5587 case 5:
5588 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5589 break;
5590 case 7:
5591 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5592 break;
5593 case 10:
5594 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5595 break;
5596 case 14:
5597 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5598 break;
79e53945
JB		 5599 }
5600
43565a06
KH		 5601 if (is_sdvo && is_tv)
5602 dpll |= PLL_REF_INPUT_TVCLKINBC;
5603 else if (is_tv)
79e53945 5604 /* XXX: just matching BIOS for now */
43565a06 5605 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5606 dpll |= 3;
a7615030 5607 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5608 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5609 else
5610 dpll |= PLL_REF_INPUT_DREFCLK;
5611
de13a2e3
PZ		 5612 return dpll;
5613}
5614
5615static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5616 int x, int y,
5617 struct drm_framebuffer *fb)
5618{
5619 struct drm_device *dev = crtc->dev;
5620 struct drm_i915_private *dev_priv = dev->dev_private;
5621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5622 struct drm_display_mode *adjusted_mode =
5623 &intel_crtc->config.adjusted_mode;
5624 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5625 int pipe = intel_crtc->pipe;
5626 int plane = intel_crtc->plane;
5627 int num_connectors = 0;
5628 intel_clock_t clock, reduced_clock;
cbbab5bd 5629 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5630 bool ok, has_reduced_clock = false;
8b47047b 5631 bool is_lvds = false;
de13a2e3 5632 struct intel_encoder *encoder;
de13a2e3 5633 int ret;
01a415fd 5634 bool dither, fdi_config_ok;
de13a2e3
PZ		 5635
5636 for_each_encoder_on_crtc(dev, crtc, encoder) {
5637 switch (encoder->type) {
5638 case INTEL_OUTPUT_LVDS:
5639 is_lvds = true;
5640 break;
de13a2e3
PZ		 5641 }
5642
5643 num_connectors++;
a07d6787 5644 }
79e53945 5645
5dc5298b
PZ		 5646 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5647 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5648
3b117c8f 5649 intel_crtc->config.cpu_transcoder = pipe;
6cf86a5e 5650
de13a2e3
PZ		 5651 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5652 &has_reduced_clock, &reduced_clock);
5653 if (!ok) {
5654 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5655 return -EINVAL;
79e53945 5656 }
f47709a9
DV		 5657 /* Compat-code for transition, will disappear. */
5658 if (!intel_crtc->config.clock_set) {
5659 intel_crtc->config.dpll.n = clock.n;
5660 intel_crtc->config.dpll.m1 = clock.m1;
5661 intel_crtc->config.dpll.m2 = clock.m2;
5662 intel_crtc->config.dpll.p1 = clock.p1;
5663 intel_crtc->config.dpll.p2 = clock.p2;
5664 }
79e53945 5665
de13a2e3
PZ		 5666 /* Ensure that the cursor is valid for the new mode before changing... */
5667 intel_crtc_update_cursor(crtc, true);
5668
5669 /* determine panel color depth */
4e53c2e0 5670 dither = intel_crtc->config.dither;
de13a2e3
PZ		 5671 if (is_lvds && dev_priv->lvds_dither)
5672 dither = true;
5673
84f44ce7 5674 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 5675 drm_mode_debug_printmodeline(mode);
5676
5dc5298b 5677 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5678 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5679 struct intel_pch_pll *pll;
4b645f14 5680
7429e9d4 5681 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5682 if (has_reduced_clock)
7429e9d4 5683 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5684
7429e9d4 5685 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5686 &fp, &reduced_clock,
5687 has_reduced_clock ? &fp2 : NULL);
5688
ee7b9f93
JB		 5689 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5690 if (pll == NULL) {
84f44ce7
VS		 5691 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5692 pipe_name(pipe));
4b645f14
JB		 5693 return -EINVAL;
5694 }
ee7b9f93
JB		 5695 } else
5696 intel_put_pch_pll(intel_crtc);
79e53945 5697
03afc4a2
DV		 5698 if (intel_crtc->config.has_dp_encoder)
5699 intel_dp_set_m_n(intel_crtc);
79e53945 5700
dafd226c
DV		 5701 for_each_encoder_on_crtc(dev, crtc, encoder)
5702 if (encoder->pre_pll_enable)
5703 encoder->pre_pll_enable(encoder);
79e53945 5704
ee7b9f93
JB		 5705 if (intel_crtc->pch_pll) {
5706 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5707
32f9d658 5708 /* Wait for the clocks to stabilize. */
ee7b9f93 5709 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5710 udelay(150);
5711
8febb297
EA		 5712 /* The pixel multiplier can only be updated once the
5713 * DPLL is enabled and the clocks are stable.
5714 *
5715 * So write it again.
5716 */
ee7b9f93 5717 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5718 }
79e53945 5719
5eddb70b 5720 intel_crtc->lowfreq_avail = false;
ee7b9f93 5721 if (intel_crtc->pch_pll) {
4b645f14 5722 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5723 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5724 intel_crtc->lowfreq_avail = true;
4b645f14 5725 } else {
ee7b9f93 5726 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5727 }
5728 }
5729
b0e77b9c 5730 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5731
01a415fd
DV		 5732 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5733 * ironlake_check_fdi_lanes. */
6cf86a5e
DV		 5734 intel_crtc->fdi_lanes = 0;
5735 if (intel_crtc->config.has_pch_encoder)
5736 ironlake_fdi_set_m_n(crtc);
2c07245f 5737
01a415fd 5738 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5739
c8203565 5740 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5741
a1f9e77e
PZ		 5742 /* Set up the display plane register */
5743 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5744 POSTING_READ(DSPCNTR(plane));
79e53945 5745
94352cf9 5746 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5747
5748 intel_update_watermarks(dev);
5749
1f8eeabf
ED		 5750 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5751
01a415fd 5752 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5753}
5754
0e8ffe1b
DV		 5755static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5756 struct intel_crtc_config *pipe_config)
5757{
5758 struct drm_device *dev = crtc->base.dev;
5759 struct drm_i915_private *dev_priv = dev->dev_private;
5760 uint32_t tmp;
5761
5762 tmp = I915_READ(PIPECONF(crtc->pipe));
5763 if (!(tmp & PIPECONF_ENABLE))
5764 return false;
5765
88adfff1
DV		 5766 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5767 pipe_config->has_pch_encoder = true;
5768
0e8ffe1b
DV		 5769 return true;
5770}
5771
d6dd9eb1
DV		 5772static void haswell_modeset_global_resources(struct drm_device *dev)
5773{
5774 struct drm_i915_private *dev_priv = dev->dev_private;
5775 bool enable = false;
5776 struct intel_crtc *crtc;
5777 struct intel_encoder *encoder;
5778
5779 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5780 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5781 enable = true;
5782 /* XXX: Should check for edp transcoder here, but thanks to init
5783 * sequence that's not yet available. Just in case desktop eDP
5784 * on PORT D is possible on haswell, too. */
5785 }
5786
5787 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5788 base.head) {
5789 if (encoder->type != INTEL_OUTPUT_EDP &&
5790 encoder->connectors_active)
5791 enable = true;
5792 }
5793
5794 /* Even the eDP panel fitter is outside the always-on well. */
5795 if (dev_priv->pch_pf_size)
5796 enable = true;
5797
5798 intel_set_power_well(dev, enable);
5799}
5800
09b4ddf9 5801static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5802 int x, int y,
5803 struct drm_framebuffer *fb)
5804{
5805 struct drm_device *dev = crtc->dev;
5806 struct drm_i915_private *dev_priv = dev->dev_private;
5807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5808 struct drm_display_mode *adjusted_mode =
5809 &intel_crtc->config.adjusted_mode;
5810 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5811 int pipe = intel_crtc->pipe;
5812 int plane = intel_crtc->plane;
5813 int num_connectors = 0;
8b47047b 5814 bool is_cpu_edp = false;
09b4ddf9 5815 struct intel_encoder *encoder;
09b4ddf9
PZ		 5816 int ret;
5817 bool dither;
5818
5819 for_each_encoder_on_crtc(dev, crtc, encoder) {
5820 switch (encoder->type) {
09b4ddf9 5821 case INTEL_OUTPUT_EDP:
09b4ddf9
PZ		 5822 if (!intel_encoder_is_pch_edp(&encoder->base))
5823 is_cpu_edp = true;
5824 break;
5825 }
5826
5827 num_connectors++;
5828 }
5829
bba2181c 5830 if (is_cpu_edp)
3b117c8f 5831 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
bba2181c 5832 else
3b117c8f 5833 intel_crtc->config.cpu_transcoder = pipe;
bba2181c 5834
5dc5298b
PZ		 5835 /* We are not sure yet this won't happen. */
5836 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5837 INTEL_PCH_TYPE(dev));
5838
5839 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5840 num_connectors, pipe_name(pipe));
5841
3b117c8f 5842 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
1ce42920
PZ		 5843 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5844
5845 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5846
6441ab5f
PZ		 5847 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5848 return -EINVAL;
5849
09b4ddf9
PZ		 5850 /* Ensure that the cursor is valid for the new mode before changing... */
5851 intel_crtc_update_cursor(crtc, true);
5852
5853 /* determine panel color depth */
4e53c2e0 5854 dither = intel_crtc->config.dither;
09b4ddf9 5855
84f44ce7 5856 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
09b4ddf9
PZ		 5857 drm_mode_debug_printmodeline(mode);
5858
03afc4a2
DV		 5859 if (intel_crtc->config.has_dp_encoder)
5860 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5861
5862 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5863
5864 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5865
6cf86a5e
DV		 5866 if (intel_crtc->config.has_pch_encoder)
5867 ironlake_fdi_set_m_n(crtc);
09b4ddf9 5868
ee2b0b38 5869 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5870
50f3b016 5871 intel_set_pipe_csc(crtc);
86d3efce 5872
09b4ddf9 5873 /* Set up the display plane register */
86d3efce 5874 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5875 POSTING_READ(DSPCNTR(plane));
5876
5877 ret = intel_pipe_set_base(crtc, x, y, fb);
5878
5879 intel_update_watermarks(dev);
5880
5881 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5882
1f803ee5 5883 return ret;
79e53945
JB		 5884}
5885
0e8ffe1b
DV		 5886static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5887 struct intel_crtc_config *pipe_config)
5888{
5889 struct drm_device *dev = crtc->base.dev;
5890 struct drm_i915_private *dev_priv = dev->dev_private;
2bfce950 5891 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 5892 uint32_t tmp;
5893
2bfce950
PZ		 5894 if (!intel_using_power_well(dev_priv->dev) &&
5895 cpu_transcoder != TRANSCODER_EDP)
5896 return false;
5897
5898 tmp = I915_READ(PIPECONF(cpu_transcoder));
0e8ffe1b
DV		 5899 if (!(tmp & PIPECONF_ENABLE))
5900 return false;
5901
88adfff1 5902 /*
f196e6be 5903 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5904 * DDI E. So just check whether this pipe is wired to DDI E and whether
5905 * the PCH transcoder is on.
5906 */
f196e6be 5907 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
88adfff1
DV		 5908 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5909 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
5910 pipe_config->has_pch_encoder = true;
5911
0e8ffe1b
DV		 5912 return true;
5913}
5914
f564048e 5915static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5916 int x, int y,
94352cf9 5917 struct drm_framebuffer *fb)
f564048e
EA		 5918{
5919 struct drm_device *dev = crtc->dev;
5920 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5921 struct drm_encoder_helper_funcs *encoder_funcs;
5922 struct intel_encoder *encoder;
0b701d27 5923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5924 struct drm_display_mode *adjusted_mode =
5925 &intel_crtc->config.adjusted_mode;
5926 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5927 int pipe = intel_crtc->pipe;
f564048e
EA		 5928 int ret;
5929
0b701d27 5930 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5931
b8cecdf5
DV		 5932 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5933
79e53945 5934 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5935
9256aa19
DV		 5936 if (ret != 0)
5937 return ret;
5938
5939 for_each_encoder_on_crtc(dev, crtc, encoder) {
5940 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5941 encoder->base.base.id,
5942 drm_get_encoder_name(&encoder->base),
5943 mode->base.id, mode->name);
6cc5f341
DV		 5944 if (encoder->mode_set) {
5945 encoder->mode_set(encoder);
5946 } else {
5947 encoder_funcs = encoder->base.helper_private;
5948 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5949 }
9256aa19
DV		 5950 }
5951
5952 return 0;
79e53945
JB		 5953}
5954
3a9627f4
WF		 5955static bool intel_eld_uptodate(struct drm_connector *connector,
5956 int reg_eldv, uint32_t bits_eldv,
5957 int reg_elda, uint32_t bits_elda,
5958 int reg_edid)
5959{
5960 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5961 uint8_t *eld = connector->eld;
5962 uint32_t i;
5963
5964 i = I915_READ(reg_eldv);
5965 i &= bits_eldv;
5966
5967 if (!eld[0])
5968 return !i;
5969
5970 if (!i)
5971 return false;
5972
5973 i = I915_READ(reg_elda);
5974 i &= ~bits_elda;
5975 I915_WRITE(reg_elda, i);
5976
5977 for (i = 0; i < eld[2]; i++)
5978 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5979 return false;
5980
5981 return true;
5982}
5983
e0dac65e
WF		 5984static void g4x_write_eld(struct drm_connector *connector,
5985 struct drm_crtc *crtc)
5986{
5987 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5988 uint8_t *eld = connector->eld;
5989 uint32_t eldv;
5990 uint32_t len;
5991 uint32_t i;
5992
5993 i = I915_READ(G4X_AUD_VID_DID);
5994
5995 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5996 eldv = G4X_ELDV_DEVCL_DEVBLC;
5997 else
5998 eldv = G4X_ELDV_DEVCTG;
5999
3a9627f4
WF		 6000 if (intel_eld_uptodate(connector,
6001 G4X_AUD_CNTL_ST, eldv,
6002 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6003 G4X_HDMIW_HDMIEDID))
6004 return;
6005
e0dac65e
WF		 6006 i = I915_READ(G4X_AUD_CNTL_ST);
6007 i &= ~(eldv | G4X_ELD_ADDR);
6008 len = (i >> 9) & 0x1f; /* ELD buffer size */
6009 I915_WRITE(G4X_AUD_CNTL_ST, i);
6010
6011 if (!eld[0])
6012 return;
6013
6014 len = min_t(uint8_t, eld[2], len);
6015 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6016 for (i = 0; i < len; i++)
6017 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6018
6019 i = I915_READ(G4X_AUD_CNTL_ST);
6020 i |= eldv;
6021 I915_WRITE(G4X_AUD_CNTL_ST, i);
6022}
6023
83358c85
WX		 6024static void haswell_write_eld(struct drm_connector *connector,
6025 struct drm_crtc *crtc)
6026{
6027 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6028 uint8_t *eld = connector->eld;
6029 struct drm_device *dev = crtc->dev;
7b9f35a6 6030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6031 uint32_t eldv;
6032 uint32_t i;
6033 int len;
6034 int pipe = to_intel_crtc(crtc)->pipe;
6035 int tmp;
6036
6037 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6038 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6039 int aud_config = HSW_AUD_CFG(pipe);
6040 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6041
6042
6043 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6044
6045 /* Audio output enable */
6046 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6047 tmp = I915_READ(aud_cntrl_st2);
6048 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6049 I915_WRITE(aud_cntrl_st2, tmp);
6050
6051 /* Wait for 1 vertical blank */
6052 intel_wait_for_vblank(dev, pipe);
6053
6054 /* Set ELD valid state */
6055 tmp = I915_READ(aud_cntrl_st2);
6056 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6057 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6058 I915_WRITE(aud_cntrl_st2, tmp);
6059 tmp = I915_READ(aud_cntrl_st2);
6060 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6061
6062 /* Enable HDMI mode */
6063 tmp = I915_READ(aud_config);
6064 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6065 /* clear N_programing_enable and N_value_index */
6066 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6067 I915_WRITE(aud_config, tmp);
6068
6069 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6070
6071 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6072 intel_crtc->eld_vld = true;
83358c85
WX		 6073
6074 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6075 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6076 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6077 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6078 } else
6079 I915_WRITE(aud_config, 0);
6080
6081 if (intel_eld_uptodate(connector,
6082 aud_cntrl_st2, eldv,
6083 aud_cntl_st, IBX_ELD_ADDRESS,
6084 hdmiw_hdmiedid))
6085 return;
6086
6087 i = I915_READ(aud_cntrl_st2);
6088 i &= ~eldv;
6089 I915_WRITE(aud_cntrl_st2, i);
6090
6091 if (!eld[0])
6092 return;
6093
6094 i = I915_READ(aud_cntl_st);
6095 i &= ~IBX_ELD_ADDRESS;
6096 I915_WRITE(aud_cntl_st, i);
6097 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6098 DRM_DEBUG_DRIVER("port num:%d\n", i);
6099
6100 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6101 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6102 for (i = 0; i < len; i++)
6103 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6104
6105 i = I915_READ(aud_cntrl_st2);
6106 i |= eldv;
6107 I915_WRITE(aud_cntrl_st2, i);
6108
6109}
6110
e0dac65e
WF		 6111static void ironlake_write_eld(struct drm_connector *connector,
6112 struct drm_crtc *crtc)
6113{
6114 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6115 uint8_t *eld = connector->eld;
6116 uint32_t eldv;
6117 uint32_t i;
6118 int len;
6119 int hdmiw_hdmiedid;
b6daa025 6120 int aud_config;
e0dac65e
WF		 6121 int aud_cntl_st;
6122 int aud_cntrl_st2;
9b138a83 6123 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6124
b3f33cbf 6125 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6126 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6127 aud_config = IBX_AUD_CFG(pipe);
6128 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6129 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6130 } else {
9b138a83
WX		 6131 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6132 aud_config = CPT_AUD_CFG(pipe);
6133 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6134 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6135 }
6136
9b138a83 6137 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6138
6139 i = I915_READ(aud_cntl_st);
9b138a83 6140 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6141 if (!i) {
6142 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6143 /* operate blindly on all ports */
1202b4c6
WF		 6144 eldv = IBX_ELD_VALIDB;
6145 eldv |= IBX_ELD_VALIDB << 4;
6146 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6147 } else {
2582a850 6148 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6149 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6150 }
6151
3a9627f4
WF		 6152 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6153 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6154 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6155 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6156 } else
6157 I915_WRITE(aud_config, 0);
e0dac65e 6158
3a9627f4
WF		 6159 if (intel_eld_uptodate(connector,
6160 aud_cntrl_st2, eldv,
6161 aud_cntl_st, IBX_ELD_ADDRESS,
6162 hdmiw_hdmiedid))
6163 return;
6164
e0dac65e
WF		 6165 i = I915_READ(aud_cntrl_st2);
6166 i &= ~eldv;
6167 I915_WRITE(aud_cntrl_st2, i);
6168
6169 if (!eld[0])
6170 return;
6171
e0dac65e 6172 i = I915_READ(aud_cntl_st);
1202b4c6 6173 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6174 I915_WRITE(aud_cntl_st, i);
6175
6176 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6177 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6178 for (i = 0; i < len; i++)
6179 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6180
6181 i = I915_READ(aud_cntrl_st2);
6182 i |= eldv;
6183 I915_WRITE(aud_cntrl_st2, i);
6184}
6185
6186void intel_write_eld(struct drm_encoder *encoder,
6187 struct drm_display_mode *mode)
6188{
6189 struct drm_crtc *crtc = encoder->crtc;
6190 struct drm_connector *connector;
6191 struct drm_device *dev = encoder->dev;
6192 struct drm_i915_private *dev_priv = dev->dev_private;
6193
6194 connector = drm_select_eld(encoder, mode);
6195 if (!connector)
6196 return;
6197
6198 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6199 connector->base.id,
6200 drm_get_connector_name(connector),
6201 connector->encoder->base.id,
6202 drm_get_encoder_name(connector->encoder));
6203
6204 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6205
6206 if (dev_priv->display.write_eld)
6207 dev_priv->display.write_eld(connector, crtc);
6208}
6209
79e53945
JB		 6210/** Loads the palette/gamma unit for the CRTC with the prepared values */
6211void intel_crtc_load_lut(struct drm_crtc *crtc)
6212{
6213 struct drm_device *dev = crtc->dev;
6214 struct drm_i915_private *dev_priv = dev->dev_private;
6215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6216 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6217 int i;
6218
6219 /* The clocks have to be on to load the palette. */
aed3f09d 6220 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6221 return;
6222
f2b115e6 6223 /* use legacy palette for Ironlake */
bad720ff 6224 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6225 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6226
79e53945
JB		 6227 for (i = 0; i < 256; i++) {
6228 I915_WRITE(palreg + 4 * i,
6229 (intel_crtc->lut_r[i] << 16) |
6230 (intel_crtc->lut_g[i] << 8) |
6231 intel_crtc->lut_b[i]);
6232 }
6233}
6234
560b85bb
CW		 6235static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6236{
6237 struct drm_device *dev = crtc->dev;
6238 struct drm_i915_private *dev_priv = dev->dev_private;
6239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6240 bool visible = base != 0;
6241 u32 cntl;
6242
6243 if (intel_crtc->cursor_visible == visible)
6244 return;
6245
9db4a9c7 6246 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6247 if (visible) {
6248 /* On these chipsets we can only modify the base whilst
6249 * the cursor is disabled.
6250 */
9db4a9c7 6251 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6252
6253 cntl &= ~(CURSOR_FORMAT_MASK);
6254 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6255 cntl |= CURSOR_ENABLE |
6256 CURSOR_GAMMA_ENABLE |
6257 CURSOR_FORMAT_ARGB;
6258 } else
6259 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6260 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6261
6262 intel_crtc->cursor_visible = visible;
6263}
6264
6265static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6266{
6267 struct drm_device *dev = crtc->dev;
6268 struct drm_i915_private *dev_priv = dev->dev_private;
6269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6270 int pipe = intel_crtc->pipe;
6271 bool visible = base != 0;
6272
6273 if (intel_crtc->cursor_visible != visible) {
548f245b 6274 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6275 if (base) {
6276 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6277 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6278 cntl |= pipe << 28; /* Connect to correct pipe */
6279 } else {
6280 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6281 cntl |= CURSOR_MODE_DISABLE;
6282 }
9db4a9c7 6283 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6284
6285 intel_crtc->cursor_visible = visible;
6286 }
6287 /* and commit changes on next vblank */
9db4a9c7 6288 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6289}
6290
65a21cd6
JB		 6291static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6292{
6293 struct drm_device *dev = crtc->dev;
6294 struct drm_i915_private *dev_priv = dev->dev_private;
6295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6296 int pipe = intel_crtc->pipe;
6297 bool visible = base != 0;
6298
6299 if (intel_crtc->cursor_visible != visible) {
6300 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6301 if (base) {
6302 cntl &= ~CURSOR_MODE;
6303 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6304 } else {
6305 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6306 cntl |= CURSOR_MODE_DISABLE;
6307 }
86d3efce
VS		 6308 if (IS_HASWELL(dev))
6309 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6310 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6311
6312 intel_crtc->cursor_visible = visible;
6313 }
6314 /* and commit changes on next vblank */
6315 I915_WRITE(CURBASE_IVB(pipe), base);
6316}
6317
cda4b7d3 6318/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6319static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6320 bool on)
cda4b7d3
CW		 6321{
6322 struct drm_device *dev = crtc->dev;
6323 struct drm_i915_private *dev_priv = dev->dev_private;
6324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6325 int pipe = intel_crtc->pipe;
6326 int x = intel_crtc->cursor_x;
6327 int y = intel_crtc->cursor_y;
560b85bb 6328 u32 base, pos;
cda4b7d3
CW		 6329 bool visible;
6330
6331 pos = 0;
6332
6b383a7f 6333 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6334 base = intel_crtc->cursor_addr;
6335 if (x > (int) crtc->fb->width)
6336 base = 0;
6337
6338 if (y > (int) crtc->fb->height)
6339 base = 0;
6340 } else
6341 base = 0;
6342
6343 if (x < 0) {
6344 if (x + intel_crtc->cursor_width < 0)
6345 base = 0;
6346
6347 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6348 x = -x;
6349 }
6350 pos |= x << CURSOR_X_SHIFT;
6351
6352 if (y < 0) {
6353 if (y + intel_crtc->cursor_height < 0)
6354 base = 0;
6355
6356 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6357 y = -y;
6358 }
6359 pos |= y << CURSOR_Y_SHIFT;
6360
6361 visible = base != 0;
560b85bb 6362 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6363 return;
6364
0cd83aa9 6365 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6366 I915_WRITE(CURPOS_IVB(pipe), pos);
6367 ivb_update_cursor(crtc, base);
6368 } else {
6369 I915_WRITE(CURPOS(pipe), pos);
6370 if (IS_845G(dev) || IS_I865G(dev))
6371 i845_update_cursor(crtc, base);
6372 else
6373 i9xx_update_cursor(crtc, base);
6374 }
cda4b7d3
CW		 6375}
6376
79e53945 6377static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6378 struct drm_file *file,
79e53945
JB		 6379 uint32_t handle,
6380 uint32_t width, uint32_t height)
6381{
6382 struct drm_device *dev = crtc->dev;
6383 struct drm_i915_private *dev_priv = dev->dev_private;
6384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6385 struct drm_i915_gem_object *obj;
cda4b7d3 6386 uint32_t addr;
3f8bc370 6387 int ret;
79e53945 6388
79e53945
JB		 6389 /* if we want to turn off the cursor ignore width and height */
6390 if (!handle) {
28c97730 6391 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6392 addr = 0;
05394f39 6393 obj = NULL;
5004417d 6394 mutex_lock(&dev->struct_mutex);
3f8bc370 6395 goto finish;
79e53945
JB		 6396 }
6397
6398 /* Currently we only support 64x64 cursors */
6399 if (width != 64 || height != 64) {
6400 DRM_ERROR("we currently only support 64x64 cursors\n");
6401 return -EINVAL;
6402 }
6403
05394f39 6404 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6405 if (&obj->base == NULL)
79e53945
JB		 6406 return -ENOENT;
6407
05394f39 6408 if (obj->base.size < width * height * 4) {
79e53945 6409 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6410 ret = -ENOMEM;
6411 goto fail;
79e53945
JB		 6412 }
6413
71acb5eb 6414 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6415 mutex_lock(&dev->struct_mutex);
b295d1b6 6416 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6417 unsigned alignment;
6418
d9e86c0e
CW		 6419 if (obj->tiling_mode) {
6420 DRM_ERROR("cursor cannot be tiled\n");
6421 ret = -EINVAL;
6422 goto fail_locked;
6423 }
6424
693db184
CW		 6425 /* Note that the w/a also requires 2 PTE of padding following
6426 * the bo. We currently fill all unused PTE with the shadow
6427 * page and so we should always have valid PTE following the
6428 * cursor preventing the VT-d warning.
6429 */
6430 alignment = 0;
6431 if (need_vtd_wa(dev))
6432 alignment = 64*1024;
6433
6434 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6435 if (ret) {
6436 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6437 goto fail_locked;
e7b526bb
CW		 6438 }
6439
d9e86c0e
CW		 6440 ret = i915_gem_object_put_fence(obj);
6441 if (ret) {
2da3b9b9 6442 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6443 goto fail_unpin;
6444 }
6445
05394f39 6446 addr = obj->gtt_offset;
71acb5eb 6447 } else {
6eeefaf3 6448 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6449 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6450 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6451 align);
71acb5eb
DA		 6452 if (ret) {
6453 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6454 goto fail_locked;
71acb5eb 6455 }
05394f39 6456 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6457 }
6458
a6c45cf0 6459 if (IS_GEN2(dev))
14b60391
JB		 6460 I915_WRITE(CURSIZE, (height << 12) | width);
6461
3f8bc370 6462 finish:
3f8bc370 6463 if (intel_crtc->cursor_bo) {
b295d1b6 6464 if (dev_priv->info->cursor_needs_physical) {
05394f39 6465 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6466 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6467 } else
6468 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6469 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6470 }
80824003 6471
7f9872e0 6472 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6473
6474 intel_crtc->cursor_addr = addr;
05394f39 6475 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6476 intel_crtc->cursor_width = width;
6477 intel_crtc->cursor_height = height;
6478
6b383a7f 6479 intel_crtc_update_cursor(crtc, true);
3f8bc370 6480
79e53945 6481 return 0;
e7b526bb 6482fail_unpin:
05394f39 6483 i915_gem_object_unpin(obj);
7f9872e0 6484fail_locked:
34b8686e 6485 mutex_unlock(&dev->struct_mutex);
bc9025bd 6486fail:
05394f39 6487 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6488 return ret;
79e53945
JB		 6489}
6490
6491static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6492{
79e53945 6493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6494
cda4b7d3
CW		 6495 intel_crtc->cursor_x = x;
6496 intel_crtc->cursor_y = y;
652c393a 6497
6b383a7f 6498 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6499
6500 return 0;
6501}
6502
6503/** Sets the color ramps on behalf of RandR */
6504void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6505 u16 blue, int regno)
6506{
6507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6508
6509 intel_crtc->lut_r[regno] = red >> 8;
6510 intel_crtc->lut_g[regno] = green >> 8;
6511 intel_crtc->lut_b[regno] = blue >> 8;
6512}
6513
b8c00ac5
DA		 6514void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6515 u16 *blue, int regno)
6516{
6517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6518
6519 *red = intel_crtc->lut_r[regno] << 8;
6520 *green = intel_crtc->lut_g[regno] << 8;
6521 *blue = intel_crtc->lut_b[regno] << 8;
6522}
6523
79e53945 6524static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6525 u16 *blue, uint32_t start, uint32_t size)
79e53945 6526{
7203425a 6527 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6529
7203425a 6530 for (i = start; i < end; i++) {
79e53945
JB		 6531 intel_crtc->lut_r[i] = red[i] >> 8;
6532 intel_crtc->lut_g[i] = green[i] >> 8;
6533 intel_crtc->lut_b[i] = blue[i] >> 8;
6534 }
6535
6536 intel_crtc_load_lut(crtc);
6537}
6538
79e53945
JB		 6539/* VESA 640x480x72Hz mode to set on the pipe */
6540static struct drm_display_mode load_detect_mode = {
6541 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6542 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6543};
6544
d2dff872
CW		 6545static struct drm_framebuffer *
6546intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6547 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6548 struct drm_i915_gem_object *obj)
6549{
6550 struct intel_framebuffer *intel_fb;
6551 int ret;
6552
6553 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6554 if (!intel_fb) {
6555 drm_gem_object_unreference_unlocked(&obj->base);
6556 return ERR_PTR(-ENOMEM);
6557 }
6558
6559 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6560 if (ret) {
6561 drm_gem_object_unreference_unlocked(&obj->base);
6562 kfree(intel_fb);
6563 return ERR_PTR(ret);
6564 }
6565
6566 return &intel_fb->base;
6567}
6568
6569static u32
6570intel_framebuffer_pitch_for_width(int width, int bpp)
6571{
6572 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6573 return ALIGN(pitch, 64);
6574}
6575
6576static u32
6577intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6578{
6579 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6580 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6581}
6582
6583static struct drm_framebuffer *
6584intel_framebuffer_create_for_mode(struct drm_device *dev,
6585 struct drm_display_mode *mode,
6586 int depth, int bpp)
6587{
6588 struct drm_i915_gem_object *obj;
0fed39bd 6589 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6590
6591 obj = i915_gem_alloc_object(dev,
6592 intel_framebuffer_size_for_mode(mode, bpp));
6593 if (obj == NULL)
6594 return ERR_PTR(-ENOMEM);
6595
6596 mode_cmd.width = mode->hdisplay;
6597 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6598 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6599 bpp);
5ca0c34a 6600 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6601
6602 return intel_framebuffer_create(dev, &mode_cmd, obj);
6603}
6604
6605static struct drm_framebuffer *
6606mode_fits_in_fbdev(struct drm_device *dev,
6607 struct drm_display_mode *mode)
6608{
6609 struct drm_i915_private *dev_priv = dev->dev_private;
6610 struct drm_i915_gem_object *obj;
6611 struct drm_framebuffer *fb;
6612
6613 if (dev_priv->fbdev == NULL)
6614 return NULL;
6615
6616 obj = dev_priv->fbdev->ifb.obj;
6617 if (obj == NULL)
6618 return NULL;
6619
6620 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6621 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6622 fb->bits_per_pixel))
d2dff872
CW		 6623 return NULL;
6624
01f2c773 6625 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6626 return NULL;
6627
6628 return fb;
6629}
6630
d2434ab7 6631bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6632 struct drm_display_mode *mode,
8261b191 6633 struct intel_load_detect_pipe *old)
79e53945
JB		 6634{
6635 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6636 struct intel_encoder *intel_encoder =
6637 intel_attached_encoder(connector);
79e53945 6638 struct drm_crtc *possible_crtc;
4ef69c7a 6639 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6640 struct drm_crtc *crtc = NULL;
6641 struct drm_device *dev = encoder->dev;
94352cf9 6642 struct drm_framebuffer *fb;
79e53945
JB		 6643 int i = -1;
6644
d2dff872
CW		 6645 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6646 connector->base.id, drm_get_connector_name(connector),
6647 encoder->base.id, drm_get_encoder_name(encoder));
6648
79e53945
JB		 6649 /*
6650 * Algorithm gets a little messy:
7a5e4805 6651 *
79e53945
JB		 6652 * - if the connector already has an assigned crtc, use it (but make
6653 * sure it's on first)
7a5e4805 6654 *
79e53945
JB		 6655 * - try to find the first unused crtc that can drive this connector,
6656 * and use that if we find one
79e53945
JB		 6657 */
6658
6659 /* See if we already have a CRTC for this connector */
6660 if (encoder->crtc) {
6661 crtc = encoder->crtc;
8261b191 6662
7b24056b
DV		 6663 mutex_lock(&crtc->mutex);
6664
24218aac 6665 old->dpms_mode = connector->dpms;
8261b191
CW		 6666 old->load_detect_temp = false;
6667
6668 /* Make sure the crtc and connector are running */
24218aac
DV		 6669 if (connector->dpms != DRM_MODE_DPMS_ON)
6670 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6671
7173188d 6672 return true;
79e53945
JB		 6673 }
6674
6675 /* Find an unused one (if possible) */
6676 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6677 i++;
6678 if (!(encoder->possible_crtcs & (1 << i)))
6679 continue;
6680 if (!possible_crtc->enabled) {
6681 crtc = possible_crtc;
6682 break;
6683 }
79e53945
JB		 6684 }
6685
6686 /*
6687 * If we didn't find an unused CRTC, don't use any.
6688 */
6689 if (!crtc) {
7173188d
CW		 6690 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6691 return false;
79e53945
JB		 6692 }
6693
7b24056b 6694 mutex_lock(&crtc->mutex);
fc303101
DV		 6695 intel_encoder->new_crtc = to_intel_crtc(crtc);
6696 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6697
6698 intel_crtc = to_intel_crtc(crtc);
24218aac 6699 old->dpms_mode = connector->dpms;
8261b191 6700 old->load_detect_temp = true;
d2dff872 6701 old->release_fb = NULL;
79e53945 6702
6492711d
CW		 6703 if (!mode)
6704 mode = &load_detect_mode;
79e53945 6705
d2dff872
CW		 6706 /* We need a framebuffer large enough to accommodate all accesses
6707 * that the plane may generate whilst we perform load detection.
6708 * We can not rely on the fbcon either being present (we get called
6709 * during its initialisation to detect all boot displays, or it may
6710 * not even exist) or that it is large enough to satisfy the
6711 * requested mode.
6712 */
94352cf9
DV		 6713 fb = mode_fits_in_fbdev(dev, mode);
6714 if (fb == NULL) {
d2dff872 6715 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6716 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6717 old->release_fb = fb;
d2dff872
CW		 6718 } else
6719 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6720 if (IS_ERR(fb)) {
d2dff872 6721 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6722 mutex_unlock(&crtc->mutex);
0e8b3d3e 6723 return false;
79e53945 6724 }
79e53945 6725
c0c36b94 6726 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6727 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6728 if (old->release_fb)
6729 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6730 mutex_unlock(&crtc->mutex);
0e8b3d3e 6731 return false;
79e53945 6732 }
7173188d 6733
79e53945 6734 /* let the connector get through one full cycle before testing */
9d0498a2 6735 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6736 return true;
79e53945
JB		 6737}
6738
d2434ab7 6739void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6740 struct intel_load_detect_pipe *old)
79e53945 6741{
d2434ab7
DV		 6742 struct intel_encoder *intel_encoder =
6743 intel_attached_encoder(connector);
4ef69c7a 6744 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6745 struct drm_crtc *crtc = encoder->crtc;
79e53945 6746
d2dff872
CW		 6747 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6748 connector->base.id, drm_get_connector_name(connector),
6749 encoder->base.id, drm_get_encoder_name(encoder));
6750
8261b191 6751 if (old->load_detect_temp) {
fc303101
DV		 6752 to_intel_connector(connector)->new_encoder = NULL;
6753 intel_encoder->new_crtc = NULL;
6754 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6755
36206361
DV		 6756 if (old->release_fb) {
6757 drm_framebuffer_unregister_private(old->release_fb);
6758 drm_framebuffer_unreference(old->release_fb);
6759 }
d2dff872 6760
67c96400 6761 mutex_unlock(&crtc->mutex);
0622a53c 6762 return;
79e53945
JB		 6763 }
6764
c751ce4f 6765 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6766 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6767 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6768
6769 mutex_unlock(&crtc->mutex);
79e53945
JB		 6770}
6771
6772/* Returns the clock of the currently programmed mode of the given pipe. */
6773static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6774{
6775 struct drm_i915_private *dev_priv = dev->dev_private;
6776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6777 int pipe = intel_crtc->pipe;
548f245b 6778 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6779 u32 fp;
6780 intel_clock_t clock;
6781
6782 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6783 fp = I915_READ(FP0(pipe));
79e53945 6784 else
39adb7a5 6785 fp = I915_READ(FP1(pipe));
79e53945
JB		 6786
6787 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6788 if (IS_PINEVIEW(dev)) {
6789 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6790 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6791 } else {
6792 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6793 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6794 }
6795
a6c45cf0 6796 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6797 if (IS_PINEVIEW(dev))
6798 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6799 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6800 else
6801 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6802 DPLL_FPA01_P1_POST_DIV_SHIFT);
6803
6804 switch (dpll & DPLL_MODE_MASK) {
6805 case DPLLB_MODE_DAC_SERIAL:
6806 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6807 5 : 10;
6808 break;
6809 case DPLLB_MODE_LVDS:
6810 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6811 7 : 14;
6812 break;
6813 default:
28c97730 6814 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6815 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6816 return 0;
6817 }
6818
6819 /* XXX: Handle the 100Mhz refclk */
2177832f 6820 intel_clock(dev, 96000, &clock);
79e53945
JB		 6821 } else {
6822 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6823
6824 if (is_lvds) {
6825 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6826 DPLL_FPA01_P1_POST_DIV_SHIFT);
6827 clock.p2 = 14;
6828
6829 if ((dpll & PLL_REF_INPUT_MASK) ==
6830 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6831 /* XXX: might not be 66MHz */
2177832f 6832 intel_clock(dev, 66000, &clock);
79e53945 6833 } else
2177832f 6834 intel_clock(dev, 48000, &clock);
79e53945
JB		 6835 } else {
6836 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6837 clock.p1 = 2;
6838 else {
6839 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6840 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6841 }
6842 if (dpll & PLL_P2_DIVIDE_BY_4)
6843 clock.p2 = 4;
6844 else
6845 clock.p2 = 2;
6846
2177832f 6847 intel_clock(dev, 48000, &clock);
79e53945
JB		 6848 }
6849 }
6850
6851 /* XXX: It would be nice to validate the clocks, but we can't reuse
6852 * i830PllIsValid() because it relies on the xf86_config connector
6853 * configuration being accurate, which it isn't necessarily.
6854 */
6855
6856 return clock.dot;
6857}
6858
6859/** Returns the currently programmed mode of the given pipe. */
6860struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6861 struct drm_crtc *crtc)
6862{
548f245b 6863 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6865 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6866 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6867 int htot = I915_READ(HTOTAL(cpu_transcoder));
6868 int hsync = I915_READ(HSYNC(cpu_transcoder));
6869 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6870 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6871
6872 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6873 if (!mode)
6874 return NULL;
6875
6876 mode->clock = intel_crtc_clock_get(dev, crtc);
6877 mode->hdisplay = (htot & 0xffff) + 1;
6878 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6879 mode->hsync_start = (hsync & 0xffff) + 1;
6880 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6881 mode->vdisplay = (vtot & 0xffff) + 1;
6882 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6883 mode->vsync_start = (vsync & 0xffff) + 1;
6884 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6885
6886 drm_mode_set_name(mode);
79e53945
JB		 6887
6888 return mode;
6889}
6890
3dec0095 6891static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6892{
6893 struct drm_device *dev = crtc->dev;
6894 drm_i915_private_t *dev_priv = dev->dev_private;
6895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6896 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6897 int dpll_reg = DPLL(pipe);
6898 int dpll;
652c393a 6899
bad720ff 6900 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6901 return;
6902
6903 if (!dev_priv->lvds_downclock_avail)
6904 return;
6905
dbdc6479 6906 dpll = I915_READ(dpll_reg);
652c393a 6907 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6908 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6909
8ac5a6d5 6910 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6911
6912 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6913 I915_WRITE(dpll_reg, dpll);
9d0498a2 6914 intel_wait_for_vblank(dev, pipe);
dbdc6479 6915
652c393a
JB		 6916 dpll = I915_READ(dpll_reg);
6917 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6918 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6919 }
652c393a
JB		 6920}
6921
6922static void intel_decrease_pllclock(struct drm_crtc *crtc)
6923{
6924 struct drm_device *dev = crtc->dev;
6925 drm_i915_private_t *dev_priv = dev->dev_private;
6926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6927
bad720ff 6928 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6929 return;
6930
6931 if (!dev_priv->lvds_downclock_avail)
6932 return;
6933
6934 /*
6935 * Since this is called by a timer, we should never get here in
6936 * the manual case.
6937 */
6938 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6939 int pipe = intel_crtc->pipe;
6940 int dpll_reg = DPLL(pipe);
6941 int dpll;
f6e5b160 6942
44d98a61 6943 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6944
8ac5a6d5 6945 assert_panel_unlocked(dev_priv, pipe);
652c393a 6946
dc257cf1 6947 dpll = I915_READ(dpll_reg);
652c393a
JB		 6948 dpll |= DISPLAY_RATE_SELECT_FPA1;
6949 I915_WRITE(dpll_reg, dpll);
9d0498a2 6950 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6951 dpll = I915_READ(dpll_reg);
6952 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6953 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6954 }
6955
6956}
6957
f047e395
CW		 6958void intel_mark_busy(struct drm_device *dev)
6959{
f047e395
CW		 6960 i915_update_gfx_val(dev->dev_private);
6961}
6962
6963void intel_mark_idle(struct drm_device *dev)
652c393a 6964{
652c393a 6965 struct drm_crtc *crtc;
652c393a
JB		 6966
6967 if (!i915_powersave)
6968 return;
6969
652c393a 6970 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6971 if (!crtc->fb)
6972 continue;
6973
725a5b54 6974 intel_decrease_pllclock(crtc);
652c393a 6975 }
652c393a
JB		 6976}
6977
725a5b54 6978void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6979{
f047e395
CW		 6980 struct drm_device *dev = obj->base.dev;
6981 struct drm_crtc *crtc;
652c393a 6982
f047e395 6983 if (!i915_powersave)
acb87dfb
CW		 6984 return;
6985
652c393a
JB		 6986 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6987 if (!crtc->fb)
6988 continue;
6989
f047e395 6990 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6991 intel_increase_pllclock(crtc);
652c393a
JB		 6992 }
6993}
6994
79e53945
JB		 6995static void intel_crtc_destroy(struct drm_crtc *crtc)
6996{
6997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6998 struct drm_device *dev = crtc->dev;
6999 struct intel_unpin_work *work;
7000 unsigned long flags;
7001
7002 spin_lock_irqsave(&dev->event_lock, flags);
7003 work = intel_crtc->unpin_work;
7004 intel_crtc->unpin_work = NULL;
7005 spin_unlock_irqrestore(&dev->event_lock, flags);
7006
7007 if (work) {
7008 cancel_work_sync(&work->work);
7009 kfree(work);
7010 }
79e53945
JB		 7011
7012 drm_crtc_cleanup(crtc);
67e77c5a 7013
79e53945
JB		 7014 kfree(intel_crtc);
7015}
7016
6b95a207
KH		 7017static void intel_unpin_work_fn(struct work_struct *__work)
7018{
7019 struct intel_unpin_work *work =
7020 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7021 struct drm_device *dev = work->crtc->dev;
6b95a207 7022
b4a98e57 7023 mutex_lock(&dev->struct_mutex);
1690e1eb 7024 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7025 drm_gem_object_unreference(&work->pending_flip_obj->base);
7026 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7027
b4a98e57
CW		 7028 intel_update_fbc(dev);
7029 mutex_unlock(&dev->struct_mutex);
7030
7031 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7032 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7033
6b95a207
KH		 7034 kfree(work);
7035}
7036
1afe3e9d 7037static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7038 struct drm_crtc *crtc)
6b95a207
KH		 7039{
7040 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7042 struct intel_unpin_work *work;
6b95a207
KH		 7043 unsigned long flags;
7044
7045 /* Ignore early vblank irqs */
7046 if (intel_crtc == NULL)
7047 return;
7048
7049 spin_lock_irqsave(&dev->event_lock, flags);
7050 work = intel_crtc->unpin_work;
e7d841ca
CW		 7051
7052 /* Ensure we don't miss a work->pending update ... */
7053 smp_rmb();
7054
7055 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7056 spin_unlock_irqrestore(&dev->event_lock, flags);
7057 return;
7058 }
7059
e7d841ca
CW		 7060 /* and that the unpin work is consistent wrt ->pending. */
7061 smp_rmb();
7062
6b95a207 7063 intel_crtc->unpin_work = NULL;
6b95a207 7064
45a066eb
RC		 7065 if (work->event)
7066 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7067
0af7e4df
MK		 7068 drm_vblank_put(dev, intel_crtc->pipe);
7069
6b95a207
KH		 7070 spin_unlock_irqrestore(&dev->event_lock, flags);
7071
2c10d571 7072 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7073
7074 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7075
7076 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7077}
7078
1afe3e9d
JB		 7079void intel_finish_page_flip(struct drm_device *dev, int pipe)
7080{
7081 drm_i915_private_t *dev_priv = dev->dev_private;
7082 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7083
49b14a5c 7084 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7085}
7086
7087void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7088{
7089 drm_i915_private_t *dev_priv = dev->dev_private;
7090 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7091
49b14a5c 7092 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7093}
7094
6b95a207
KH		 7095void intel_prepare_page_flip(struct drm_device *dev, int plane)
7096{
7097 drm_i915_private_t *dev_priv = dev->dev_private;
7098 struct intel_crtc *intel_crtc =
7099 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7100 unsigned long flags;
7101
e7d841ca
CW		 7102 /* NB: An MMIO update of the plane base pointer will also
7103 * generate a page-flip completion irq, i.e. every modeset
7104 * is also accompanied by a spurious intel_prepare_page_flip().
7105 */
6b95a207 7106 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7107 if (intel_crtc->unpin_work)
7108 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7109 spin_unlock_irqrestore(&dev->event_lock, flags);
7110}
7111
e7d841ca
CW		 7112inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7113{
7114 /* Ensure that the work item is consistent when activating it ... */
7115 smp_wmb();
7116 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7117 /* and that it is marked active as soon as the irq could fire. */
7118 smp_wmb();
7119}
7120
8c9f3aaf
JB		 7121static int intel_gen2_queue_flip(struct drm_device *dev,
7122 struct drm_crtc *crtc,
7123 struct drm_framebuffer *fb,
7124 struct drm_i915_gem_object *obj)
7125{
7126 struct drm_i915_private *dev_priv = dev->dev_private;
7127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7128 u32 flip_mask;
6d90c952 7129 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7130 int ret;
7131
6d90c952 7132 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7133 if (ret)
83d4092b 7134 goto err;
8c9f3aaf 7135
6d90c952 7136 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7137 if (ret)
83d4092b 7138 goto err_unpin;
8c9f3aaf
JB		 7139
7140 /* Can't queue multiple flips, so wait for the previous
7141 * one to finish before executing the next.
7142 */
7143 if (intel_crtc->plane)
7144 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7145 else
7146 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7147 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7148 intel_ring_emit(ring, MI_NOOP);
7149 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7150 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7151 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7152 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7153 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7154
7155 intel_mark_page_flip_active(intel_crtc);
6d90c952 7156 intel_ring_advance(ring);
83d4092b
CW		 7157 return 0;
7158
7159err_unpin:
7160 intel_unpin_fb_obj(obj);
7161err:
8c9f3aaf
JB		 7162 return ret;
7163}
7164
7165static int intel_gen3_queue_flip(struct drm_device *dev,
7166 struct drm_crtc *crtc,
7167 struct drm_framebuffer *fb,
7168 struct drm_i915_gem_object *obj)
7169{
7170 struct drm_i915_private *dev_priv = dev->dev_private;
7171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7172 u32 flip_mask;
6d90c952 7173 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7174 int ret;
7175
6d90c952 7176 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7177 if (ret)
83d4092b 7178 goto err;
8c9f3aaf 7179
6d90c952 7180 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7181 if (ret)
83d4092b 7182 goto err_unpin;
8c9f3aaf
JB		 7183
7184 if (intel_crtc->plane)
7185 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7186 else
7187 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7188 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7189 intel_ring_emit(ring, MI_NOOP);
7190 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7191 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7192 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7193 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7194 intel_ring_emit(ring, MI_NOOP);
7195
e7d841ca 7196 intel_mark_page_flip_active(intel_crtc);
6d90c952 7197 intel_ring_advance(ring);
83d4092b
CW		 7198 return 0;
7199
7200err_unpin:
7201 intel_unpin_fb_obj(obj);
7202err:
8c9f3aaf
JB		 7203 return ret;
7204}
7205
7206static int intel_gen4_queue_flip(struct drm_device *dev,
7207 struct drm_crtc *crtc,
7208 struct drm_framebuffer *fb,
7209 struct drm_i915_gem_object *obj)
7210{
7211 struct drm_i915_private *dev_priv = dev->dev_private;
7212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7213 uint32_t pf, pipesrc;
6d90c952 7214 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7215 int ret;
7216
6d90c952 7217 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7218 if (ret)
83d4092b 7219 goto err;
8c9f3aaf 7220
6d90c952 7221 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7222 if (ret)
83d4092b 7223 goto err_unpin;
8c9f3aaf
JB		 7224
7225 /* i965+ uses the linear or tiled offsets from the
7226 * Display Registers (which do not change across a page-flip)
7227 * so we need only reprogram the base address.
7228 */
6d90c952
DV		 7229 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7230 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7231 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7232 intel_ring_emit(ring,
7233 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7234 obj->tiling_mode);
8c9f3aaf
JB		 7235
7236 /* XXX Enabling the panel-fitter across page-flip is so far
7237 * untested on non-native modes, so ignore it for now.
7238 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7239 */
7240 pf = 0;
7241 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7242 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7243
7244 intel_mark_page_flip_active(intel_crtc);
6d90c952 7245 intel_ring_advance(ring);
83d4092b
CW		 7246 return 0;
7247
7248err_unpin:
7249 intel_unpin_fb_obj(obj);
7250err:
8c9f3aaf
JB		 7251 return ret;
7252}
7253
7254static int intel_gen6_queue_flip(struct drm_device *dev,
7255 struct drm_crtc *crtc,
7256 struct drm_framebuffer *fb,
7257 struct drm_i915_gem_object *obj)
7258{
7259 struct drm_i915_private *dev_priv = dev->dev_private;
7260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7261 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7262 uint32_t pf, pipesrc;
7263 int ret;
7264
6d90c952 7265 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7266 if (ret)
83d4092b 7267 goto err;
8c9f3aaf 7268
6d90c952 7269 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7270 if (ret)
83d4092b 7271 goto err_unpin;
8c9f3aaf 7272
6d90c952
DV		 7273 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7274 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7275 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7276 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7277
dc257cf1
DV		 7278 /* Contrary to the suggestions in the documentation,
7279 * "Enable Panel Fitter" does not seem to be required when page
7280 * flipping with a non-native mode, and worse causes a normal
7281 * modeset to fail.
7282 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7283 */
7284 pf = 0;
8c9f3aaf 7285 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7286 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7287
7288 intel_mark_page_flip_active(intel_crtc);
6d90c952 7289 intel_ring_advance(ring);
83d4092b
CW		 7290 return 0;
7291
7292err_unpin:
7293 intel_unpin_fb_obj(obj);
7294err:
8c9f3aaf
JB		 7295 return ret;
7296}
7297
7c9017e5
JB		 7298/*
7299 * On gen7 we currently use the blit ring because (in early silicon at least)
7300 * the render ring doesn't give us interrpts for page flip completion, which
7301 * means clients will hang after the first flip is queued. Fortunately the
7302 * blit ring generates interrupts properly, so use it instead.
7303 */
7304static int intel_gen7_queue_flip(struct drm_device *dev,
7305 struct drm_crtc *crtc,
7306 struct drm_framebuffer *fb,
7307 struct drm_i915_gem_object *obj)
7308{
7309 struct drm_i915_private *dev_priv = dev->dev_private;
7310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7311 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7312 uint32_t plane_bit = 0;
7c9017e5
JB		 7313 int ret;
7314
7315 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7316 if (ret)
83d4092b 7317 goto err;
7c9017e5 7318
cb05d8de
DV		 7319 switch(intel_crtc->plane) {
7320 case PLANE_A:
7321 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7322 break;
7323 case PLANE_B:
7324 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7325 break;
7326 case PLANE_C:
7327 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7328 break;
7329 default:
7330 WARN_ONCE(1, "unknown plane in flip command\n");
7331 ret = -ENODEV;
ab3951eb 7332 goto err_unpin;
cb05d8de
DV		 7333 }
7334
7c9017e5
JB		 7335 ret = intel_ring_begin(ring, 4);
7336 if (ret)
83d4092b 7337 goto err_unpin;
7c9017e5 7338
cb05d8de 7339 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7340 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7341 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7342 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7343
7344 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7345 intel_ring_advance(ring);
83d4092b
CW		 7346 return 0;
7347
7348err_unpin:
7349 intel_unpin_fb_obj(obj);
7350err:
7c9017e5
JB		 7351 return ret;
7352}
7353
8c9f3aaf
JB		 7354static int intel_default_queue_flip(struct drm_device *dev,
7355 struct drm_crtc *crtc,
7356 struct drm_framebuffer *fb,
7357 struct drm_i915_gem_object *obj)
7358{
7359 return -ENODEV;
7360}
7361
6b95a207
KH		 7362static int intel_crtc_page_flip(struct drm_crtc *crtc,
7363 struct drm_framebuffer *fb,
7364 struct drm_pending_vblank_event *event)
7365{
7366 struct drm_device *dev = crtc->dev;
7367 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7368 struct drm_framebuffer *old_fb = crtc->fb;
7369 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7371 struct intel_unpin_work *work;
8c9f3aaf 7372 unsigned long flags;
52e68630 7373 int ret;
6b95a207 7374
e6a595d2
VS		 7375 /* Can't change pixel format via MI display flips. */
7376 if (fb->pixel_format != crtc->fb->pixel_format)
7377 return -EINVAL;
7378
7379 /*
7380 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7381 * Note that pitch changes could also affect these register.
7382 */
7383 if (INTEL_INFO(dev)->gen > 3 &&
7384 (fb->offsets[0] != crtc->fb->offsets[0] ||
7385 fb->pitches[0] != crtc->fb->pitches[0]))
7386 return -EINVAL;
7387
6b95a207
KH		 7388 work = kzalloc(sizeof *work, GFP_KERNEL);
7389 if (work == NULL)
7390 return -ENOMEM;
7391
6b95a207 7392 work->event = event;
b4a98e57 7393 work->crtc = crtc;
4a35f83b 7394 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7395 INIT_WORK(&work->work, intel_unpin_work_fn);
7396
7317c75e
JB		 7397 ret = drm_vblank_get(dev, intel_crtc->pipe);
7398 if (ret)
7399 goto free_work;
7400
6b95a207
KH		 7401 /* We borrow the event spin lock for protecting unpin_work */
7402 spin_lock_irqsave(&dev->event_lock, flags);
7403 if (intel_crtc->unpin_work) {
7404 spin_unlock_irqrestore(&dev->event_lock, flags);
7405 kfree(work);
7317c75e 7406 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7407
7408 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7409 return -EBUSY;
7410 }
7411 intel_crtc->unpin_work = work;
7412 spin_unlock_irqrestore(&dev->event_lock, flags);
7413
b4a98e57
CW		 7414 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7415 flush_workqueue(dev_priv->wq);
7416
79158103
CW		 7417 ret = i915_mutex_lock_interruptible(dev);
7418 if (ret)
7419 goto cleanup;
6b95a207 7420
75dfca80 7421 /* Reference the objects for the scheduled work. */
05394f39
CW		 7422 drm_gem_object_reference(&work->old_fb_obj->base);
7423 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7424
7425 crtc->fb = fb;
96b099fd 7426
e1f99ce6 7427 work->pending_flip_obj = obj;
e1f99ce6 7428
4e5359cd
SF		 7429 work->enable_stall_check = true;
7430
b4a98e57 7431 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7432 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7433
8c9f3aaf
JB		 7434 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7435 if (ret)
7436 goto cleanup_pending;
6b95a207 7437
7782de3b 7438 intel_disable_fbc(dev);
f047e395 7439 intel_mark_fb_busy(obj);
6b95a207
KH		 7440 mutex_unlock(&dev->struct_mutex);
7441
e5510fac
JB		 7442 trace_i915_flip_request(intel_crtc->plane, obj);
7443
6b95a207 7444 return 0;
96b099fd 7445
8c9f3aaf 7446cleanup_pending:
b4a98e57 7447 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7448 crtc->fb = old_fb;
05394f39
CW		 7449 drm_gem_object_unreference(&work->old_fb_obj->base);
7450 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7451 mutex_unlock(&dev->struct_mutex);
7452
79158103 7453cleanup:
96b099fd
CW		 7454 spin_lock_irqsave(&dev->event_lock, flags);
7455 intel_crtc->unpin_work = NULL;
7456 spin_unlock_irqrestore(&dev->event_lock, flags);
7457
7317c75e
JB		 7458 drm_vblank_put(dev, intel_crtc->pipe);
7459free_work:
96b099fd
CW		 7460 kfree(work);
7461
7462 return ret;
6b95a207
KH		 7463}
7464
f6e5b160 7465static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7466 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7467 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7468};
7469
6ed0f796 7470bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7471{
6ed0f796
DV		 7472 struct intel_encoder *other_encoder;
7473 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7474
6ed0f796
DV		 7475 if (WARN_ON(!crtc))
7476 return false;
7477
7478 list_for_each_entry(other_encoder,
7479 &crtc->dev->mode_config.encoder_list,
7480 base.head) {
7481
7482 if (&other_encoder->new_crtc->base != crtc ||
7483 encoder == other_encoder)
7484 continue;
7485 else
7486 return true;
f47166d2
CW		 7487 }
7488
6ed0f796
DV		 7489 return false;
7490}
47f1c6c9 7491
50f56119
DV		 7492static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7493 struct drm_crtc *crtc)
7494{
7495 struct drm_device *dev;
7496 struct drm_crtc *tmp;
7497 int crtc_mask = 1;
47f1c6c9 7498
50f56119 7499 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7500
50f56119 7501 dev = crtc->dev;
47f1c6c9 7502
50f56119
DV		 7503 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7504 if (tmp == crtc)
7505 break;
7506 crtc_mask <<= 1;
7507 }
47f1c6c9 7508
50f56119
DV		 7509 if (encoder->possible_crtcs & crtc_mask)
7510 return true;
7511 return false;
47f1c6c9 7512}
79e53945 7513
9a935856
DV		 7514/**
7515 * intel_modeset_update_staged_output_state
7516 *
7517 * Updates the staged output configuration state, e.g. after we've read out the
7518 * current hw state.
7519 */
7520static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7521{
9a935856
DV		 7522 struct intel_encoder *encoder;
7523 struct intel_connector *connector;
f6e5b160 7524
9a935856
DV		 7525 list_for_each_entry(connector, &dev->mode_config.connector_list,
7526 base.head) {
7527 connector->new_encoder =
7528 to_intel_encoder(connector->base.encoder);
7529 }
f6e5b160 7530
9a935856
DV		 7531 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7532 base.head) {
7533 encoder->new_crtc =
7534 to_intel_crtc(encoder->base.crtc);
7535 }
f6e5b160
CW		 7536}
7537
9a935856
DV		 7538/**
7539 * intel_modeset_commit_output_state
7540 *
7541 * This function copies the stage display pipe configuration to the real one.
7542 */
7543static void intel_modeset_commit_output_state(struct drm_device *dev)
7544{
7545 struct intel_encoder *encoder;
7546 struct intel_connector *connector;
f6e5b160 7547
9a935856
DV		 7548 list_for_each_entry(connector, &dev->mode_config.connector_list,
7549 base.head) {
7550 connector->base.encoder = &connector->new_encoder->base;
7551 }
f6e5b160 7552
9a935856
DV		 7553 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7554 base.head) {
7555 encoder->base.crtc = &encoder->new_crtc->base;
7556 }
7557}
7558
4e53c2e0
DV		 7559static int
7560pipe_config_set_bpp(struct drm_crtc *crtc,
7561 struct drm_framebuffer *fb,
7562 struct intel_crtc_config *pipe_config)
7563{
7564 struct drm_device *dev = crtc->dev;
7565 struct drm_connector *connector;
7566 int bpp;
7567
d42264b1
DV		 7568 switch (fb->pixel_format) {
7569 case DRM_FORMAT_C8:
4e53c2e0
DV		 7570 bpp = 8*3; /* since we go through a colormap */
7571 break;
d42264b1
DV		 7572 case DRM_FORMAT_XRGB1555:
7573 case DRM_FORMAT_ARGB1555:
7574 /* checked in intel_framebuffer_init already */
7575 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7576 return -EINVAL;
7577 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7578 bpp = 6*3; /* min is 18bpp */
7579 break;
d42264b1
DV		 7580 case DRM_FORMAT_XBGR8888:
7581 case DRM_FORMAT_ABGR8888:
7582 /* checked in intel_framebuffer_init already */
7583 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7584 return -EINVAL;
7585 case DRM_FORMAT_XRGB8888:
7586 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7587 bpp = 8*3;
7588 break;
d42264b1
DV		 7589 case DRM_FORMAT_XRGB2101010:
7590 case DRM_FORMAT_ARGB2101010:
7591 case DRM_FORMAT_XBGR2101010:
7592 case DRM_FORMAT_ABGR2101010:
7593 /* checked in intel_framebuffer_init already */
7594 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7595 return -EINVAL;
4e53c2e0
DV		 7596 bpp = 10*3;
7597 break;
baba133a 7598 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7599 default:
7600 DRM_DEBUG_KMS("unsupported depth\n");
7601 return -EINVAL;
7602 }
7603
4e53c2e0
DV		 7604 pipe_config->pipe_bpp = bpp;
7605
7606 /* Clamp display bpp to EDID value */
7607 list_for_each_entry(connector, &dev->mode_config.connector_list,
7608 head) {
7609 if (connector->encoder && connector->encoder->crtc != crtc)
7610 continue;
7611
7612 /* Don't use an invalid EDID bpc value */
7613 if (connector->display_info.bpc &&
7614 connector->display_info.bpc * 3 < bpp) {
7615 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7616 bpp, connector->display_info.bpc*3);
7617 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7618 }
996a2239
DV		 7619
7620 /* Clamp bpp to 8 on screens without EDID 1.4 */
7621 if (connector->display_info.bpc == 0 && bpp > 24) {
7622 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7623 bpp);
7624 pipe_config->pipe_bpp = 24;
7625 }
4e53c2e0
DV		 7626 }
7627
7628 return bpp;
7629}
7630
b8cecdf5
DV		 7631static struct intel_crtc_config *
7632intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7633 struct drm_framebuffer *fb,
b8cecdf5 7634 struct drm_display_mode *mode)
ee7b9f93 7635{
7758a113 7636 struct drm_device *dev = crtc->dev;
7758a113
DV		 7637 struct drm_encoder_helper_funcs *encoder_funcs;
7638 struct intel_encoder *encoder;
b8cecdf5 7639 struct intel_crtc_config *pipe_config;
4e53c2e0 7640 int plane_bpp;
ee7b9f93 7641
b8cecdf5
DV		 7642 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7643 if (!pipe_config)
7758a113
DV		 7644 return ERR_PTR(-ENOMEM);
7645
b8cecdf5
DV		 7646 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7647 drm_mode_copy(&pipe_config->requested_mode, mode);
7648
4e53c2e0
DV		 7649 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7650 if (plane_bpp < 0)
7651 goto fail;
7652
7758a113
DV		 7653 /* Pass our mode to the connectors and the CRTC to give them a chance to
7654 * adjust it according to limitations or connector properties, and also
7655 * a chance to reject the mode entirely.
47f1c6c9 7656 */
7758a113
DV		 7657 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7658 base.head) {
47f1c6c9 7659
7758a113
DV		 7660 if (&encoder->new_crtc->base != crtc)
7661 continue;
7ae89233
DV		 7662
7663 if (encoder->compute_config) {
7664 if (!(encoder->compute_config(encoder, pipe_config))) {
7665 DRM_DEBUG_KMS("Encoder config failure\n");
7666 goto fail;
7667 }
7668
7669 continue;
7670 }
7671
7758a113 7672 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7673 if (!(encoder_funcs->mode_fixup(&encoder->base,
7674 &pipe_config->requested_mode,
7675 &pipe_config->adjusted_mode))) {
7758a113
DV		 7676 DRM_DEBUG_KMS("Encoder fixup failed\n");
7677 goto fail;
7678 }
ee7b9f93 7679 }
47f1c6c9 7680
b8cecdf5 7681 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7758a113
DV		 7682 DRM_DEBUG_KMS("CRTC fixup failed\n");
7683 goto fail;
ee7b9f93 7684 }
7758a113 7685 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7686
4e53c2e0
DV		 7687 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7688 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7689 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7690
b8cecdf5 7691 return pipe_config;
7758a113 7692fail:
b8cecdf5 7693 kfree(pipe_config);
7758a113 7694 return ERR_PTR(-EINVAL);
ee7b9f93 7695}
47f1c6c9 7696
e2e1ed41
DV		 7697/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7698 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7699static void
7700intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7701 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7702{
7703 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7704 struct drm_device *dev = crtc->dev;
7705 struct intel_encoder *encoder;
7706 struct intel_connector *connector;
7707 struct drm_crtc *tmp_crtc;
79e53945 7708
e2e1ed41 7709 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7710
e2e1ed41
DV		 7711 /* Check which crtcs have changed outputs connected to them, these need
7712 * to be part of the prepare_pipes mask. We don't (yet) support global
7713 * modeset across multiple crtcs, so modeset_pipes will only have one
7714 * bit set at most. */
7715 list_for_each_entry(connector, &dev->mode_config.connector_list,
7716 base.head) {
7717 if (connector->base.encoder == &connector->new_encoder->base)
7718 continue;
79e53945 7719
e2e1ed41
DV		 7720 if (connector->base.encoder) {
7721 tmp_crtc = connector->base.encoder->crtc;
7722
7723 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7724 }
7725
7726 if (connector->new_encoder)
7727 *prepare_pipes |=
7728 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7729 }
7730
e2e1ed41
DV		 7731 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7732 base.head) {
7733 if (encoder->base.crtc == &encoder->new_crtc->base)
7734 continue;
7735
7736 if (encoder->base.crtc) {
7737 tmp_crtc = encoder->base.crtc;
7738
7739 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7740 }
7741
7742 if (encoder->new_crtc)
7743 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7744 }
7745
e2e1ed41
DV		 7746 /* Check for any pipes that will be fully disabled ... */
7747 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7748 base.head) {
7749 bool used = false;
22fd0fab 7750
e2e1ed41
DV		 7751 /* Don't try to disable disabled crtcs. */
7752 if (!intel_crtc->base.enabled)
7753 continue;
7e7d76c3 7754
e2e1ed41
DV		 7755 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7756 base.head) {
7757 if (encoder->new_crtc == intel_crtc)
7758 used = true;
7759 }
7760
7761 if (!used)
7762 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7763 }
7764
e2e1ed41
DV		 7765
7766 /* set_mode is also used to update properties on life display pipes. */
7767 intel_crtc = to_intel_crtc(crtc);
7768 if (crtc->enabled)
7769 *prepare_pipes |= 1 << intel_crtc->pipe;
7770
b6c5164d
DV		 7771 /*
7772 * For simplicity do a full modeset on any pipe where the output routing
7773 * changed. We could be more clever, but that would require us to be
7774 * more careful with calling the relevant encoder->mode_set functions.
7775 */
e2e1ed41
DV		 7776 if (*prepare_pipes)
7777 *modeset_pipes = *prepare_pipes;
7778
7779 /* ... and mask these out. */
7780 *modeset_pipes &= ~(*disable_pipes);
7781 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7782
7783 /*
7784 * HACK: We don't (yet) fully support global modesets. intel_set_config
7785 * obies this rule, but the modeset restore mode of
7786 * intel_modeset_setup_hw_state does not.
7787 */
7788 *modeset_pipes &= 1 << intel_crtc->pipe;
7789 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7790
7791 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7792 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7793}
79e53945 7794
ea9d758d 7795static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7796{
ea9d758d 7797 struct drm_encoder *encoder;
f6e5b160 7798 struct drm_device *dev = crtc->dev;
f6e5b160 7799
ea9d758d
DV		 7800 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7801 if (encoder->crtc == crtc)
7802 return true;
7803
7804 return false;
7805}
7806
7807static void
7808intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7809{
7810 struct intel_encoder *intel_encoder;
7811 struct intel_crtc *intel_crtc;
7812 struct drm_connector *connector;
7813
7814 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7815 base.head) {
7816 if (!intel_encoder->base.crtc)
7817 continue;
7818
7819 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7820
7821 if (prepare_pipes & (1 << intel_crtc->pipe))
7822 intel_encoder->connectors_active = false;
7823 }
7824
7825 intel_modeset_commit_output_state(dev);
7826
7827 /* Update computed state. */
7828 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7829 base.head) {
7830 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7831 }
7832
7833 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7834 if (!connector->encoder || !connector->encoder->crtc)
7835 continue;
7836
7837 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7838
7839 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7840 struct drm_property *dpms_property =
7841 dev->mode_config.dpms_property;
7842
ea9d758d 7843 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7844 drm_object_property_set_value(&connector->base,
68d34720
DV		 7845 dpms_property,
7846 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7847
7848 intel_encoder = to_intel_encoder(connector->encoder);
7849 intel_encoder->connectors_active = true;
7850 }
7851 }
7852
7853}
7854
25c5b266
DV		 7855#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7856 list_for_each_entry((intel_crtc), \
7857 &(dev)->mode_config.crtc_list, \
7858 base.head) \
7859 if (mask & (1 <<(intel_crtc)->pipe)) \
7860
0e8ffe1b
DV		 7861static bool
7862intel_pipe_config_compare(struct intel_crtc_config *current_config,
7863 struct intel_crtc_config *pipe_config)
7864{
88adfff1
DV		 7865 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7866 DRM_ERROR("mismatch in has_pch_encoder "
7867 "(expected %i, found %i)\n",
7868 current_config->has_pch_encoder,
7869 pipe_config->has_pch_encoder);
7870 return false;
7871 }
7872
0e8ffe1b
DV		 7873 return true;
7874}
7875
b980514c 7876void
8af6cf88
DV		 7877intel_modeset_check_state(struct drm_device *dev)
7878{
0e8ffe1b 7879 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 7880 struct intel_crtc *crtc;
7881 struct intel_encoder *encoder;
7882 struct intel_connector *connector;
0e8ffe1b 7883 struct intel_crtc_config pipe_config;
8af6cf88
DV		 7884
7885 list_for_each_entry(connector, &dev->mode_config.connector_list,
7886 base.head) {
7887 /* This also checks the encoder/connector hw state with the
7888 * ->get_hw_state callbacks. */
7889 intel_connector_check_state(connector);
7890
7891 WARN(&connector->new_encoder->base != connector->base.encoder,
7892 "connector's staged encoder doesn't match current encoder\n");
7893 }
7894
7895 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7896 base.head) {
7897 bool enabled = false;
7898 bool active = false;
7899 enum pipe pipe, tracked_pipe;
7900
7901 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7902 encoder->base.base.id,
7903 drm_get_encoder_name(&encoder->base));
7904
7905 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7906 "encoder's stage crtc doesn't match current crtc\n");
7907 WARN(encoder->connectors_active && !encoder->base.crtc,
7908 "encoder's active_connectors set, but no crtc\n");
7909
7910 list_for_each_entry(connector, &dev->mode_config.connector_list,
7911 base.head) {
7912 if (connector->base.encoder != &encoder->base)
7913 continue;
7914 enabled = true;
7915 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7916 active = true;
7917 }
7918 WARN(!!encoder->base.crtc != enabled,
7919 "encoder's enabled state mismatch "
7920 "(expected %i, found %i)\n",
7921 !!encoder->base.crtc, enabled);
7922 WARN(active && !encoder->base.crtc,
7923 "active encoder with no crtc\n");
7924
7925 WARN(encoder->connectors_active != active,
7926 "encoder's computed active state doesn't match tracked active state "
7927 "(expected %i, found %i)\n", active, encoder->connectors_active);
7928
7929 active = encoder->get_hw_state(encoder, &pipe);
7930 WARN(active != encoder->connectors_active,
7931 "encoder's hw state doesn't match sw tracking "
7932 "(expected %i, found %i)\n",
7933 encoder->connectors_active, active);
7934
7935 if (!encoder->base.crtc)
7936 continue;
7937
7938 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7939 WARN(active && pipe != tracked_pipe,
7940 "active encoder's pipe doesn't match"
7941 "(expected %i, found %i)\n",
7942 tracked_pipe, pipe);
7943
7944 }
7945
7946 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7947 base.head) {
7948 bool enabled = false;
7949 bool active = false;
7950
7951 DRM_DEBUG_KMS("[CRTC:%d]\n",
7952 crtc->base.base.id);
7953
7954 WARN(crtc->active && !crtc->base.enabled,
7955 "active crtc, but not enabled in sw tracking\n");
7956
7957 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7958 base.head) {
7959 if (encoder->base.crtc != &crtc->base)
7960 continue;
7961 enabled = true;
7962 if (encoder->connectors_active)
7963 active = true;
7964 }
7965 WARN(active != crtc->active,
7966 "crtc's computed active state doesn't match tracked active state "
7967 "(expected %i, found %i)\n", active, crtc->active);
7968 WARN(enabled != crtc->base.enabled,
7969 "crtc's computed enabled state doesn't match tracked enabled state "
7970 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7971
88adfff1 7972 memset(&pipe_config, 0, sizeof(pipe_config));
0e8ffe1b
DV		 7973 active = dev_priv->display.get_pipe_config(crtc,
7974 &pipe_config);
7975 WARN(crtc->active != active,
7976 "crtc active state doesn't match with hw state "
7977 "(expected %i, found %i)\n", crtc->active, active);
7978
7979 WARN(active &&
7980 !intel_pipe_config_compare(&crtc->config, &pipe_config),
7981 "pipe state doesn't match!\n");
8af6cf88
DV		 7982 }
7983}
7984
f30da187
DV		 7985static int __intel_set_mode(struct drm_crtc *crtc,
7986 struct drm_display_mode *mode,
7987 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7988{
7989 struct drm_device *dev = crtc->dev;
dbf2b54e 7990 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 7991 struct drm_display_mode *saved_mode, *saved_hwmode;
7992 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 7993 struct intel_crtc *intel_crtc;
7994 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7995 int ret = 0;
a6778b3c 7996
3ac18232 7997 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7998 if (!saved_mode)
7999 return -ENOMEM;
3ac18232 8000 saved_hwmode = saved_mode + 1;
a6778b3c 8001
e2e1ed41 8002 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8003 &prepare_pipes, &disable_pipes);
8004
3ac18232
TG		 8005 *saved_hwmode = crtc->hwmode;
8006 *saved_mode = crtc->mode;
a6778b3c 8007
25c5b266
DV		 8008 /* Hack: Because we don't (yet) support global modeset on multiple
8009 * crtcs, we don't keep track of the new mode for more than one crtc.
8010 * Hence simply check whether any bit is set in modeset_pipes in all the
8011 * pieces of code that are not yet converted to deal with mutliple crtcs
8012 * changing their mode at the same time. */
25c5b266 8013 if (modeset_pipes) {
4e53c2e0 8014 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8015 if (IS_ERR(pipe_config)) {
8016 ret = PTR_ERR(pipe_config);
8017 pipe_config = NULL;
8018
3ac18232 8019 goto out;
25c5b266 8020 }
25c5b266 8021 }
a6778b3c 8022
460da916
DV		 8023 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8024 intel_crtc_disable(&intel_crtc->base);
8025
ea9d758d
DV		 8026 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8027 if (intel_crtc->base.enabled)
8028 dev_priv->display.crtc_disable(&intel_crtc->base);
8029 }
a6778b3c 8030
6c4c86f5
DV		 8031 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8032 * to set it here already despite that we pass it down the callchain.
f6e5b160 8033 */
b8cecdf5 8034 if (modeset_pipes) {
3b117c8f 8035 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
25c5b266 8036 crtc->mode = *mode;
b8cecdf5
DV		 8037 /* mode_set/enable/disable functions rely on a correct pipe
8038 * config. */
8039 to_intel_crtc(crtc)->config = *pipe_config;
3b117c8f 8040 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
b8cecdf5 8041 }
7758a113 8042
ea9d758d
DV		 8043 /* Only after disabling all output pipelines that will be changed can we
8044 * update the the output configuration. */
8045 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8046
47fab737
DV		 8047 if (dev_priv->display.modeset_global_resources)
8048 dev_priv->display.modeset_global_resources(dev);
8049
a6778b3c
DV		 8050 /* Set up the DPLL and any encoders state that needs to adjust or depend
8051 * on the DPLL.
f6e5b160 8052 */
25c5b266 8053 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8054 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8055 x, y, fb);
8056 if (ret)
8057 goto done;
a6778b3c
DV		 8058 }
8059
8060 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8061 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8062 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8063
25c5b266
DV		 8064 if (modeset_pipes) {
8065 /* Store real post-adjustment hardware mode. */
b8cecdf5 8066 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8067
25c5b266
DV		 8068 /* Calculate and store various constants which
8069 * are later needed by vblank and swap-completion
8070 * timestamping. They are derived from true hwmode.
8071 */
8072 drm_calc_timestamping_constants(crtc);
8073 }
a6778b3c
DV		 8074
8075 /* FIXME: add subpixel order */
8076done:
c0c36b94 8077 if (ret && crtc->enabled) {
3ac18232
TG		 8078 crtc->hwmode = *saved_hwmode;
8079 crtc->mode = *saved_mode;
a6778b3c
DV		 8080 }
8081
3ac18232 8082out:
b8cecdf5 8083 kfree(pipe_config);
3ac18232 8084 kfree(saved_mode);
a6778b3c 8085 return ret;
f6e5b160
CW		 8086}
8087
f30da187
DV		 8088int intel_set_mode(struct drm_crtc *crtc,
8089 struct drm_display_mode *mode,
8090 int x, int y, struct drm_framebuffer *fb)
8091{
8092 int ret;
8093
8094 ret = __intel_set_mode(crtc, mode, x, y, fb);
8095
8096 if (ret == 0)
8097 intel_modeset_check_state(crtc->dev);
8098
8099 return ret;
8100}
8101
c0c36b94
CW		 8102void intel_crtc_restore_mode(struct drm_crtc *crtc)
8103{
8104 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8105}
8106
25c5b266
DV		 8107#undef for_each_intel_crtc_masked
8108
d9e55608
DV		 8109static void intel_set_config_free(struct intel_set_config *config)
8110{
8111 if (!config)
8112 return;
8113
1aa4b628
DV		 8114 kfree(config->save_connector_encoders);
8115 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8116 kfree(config);
8117}
8118
85f9eb71
DV		 8119static int intel_set_config_save_state(struct drm_device *dev,
8120 struct intel_set_config *config)
8121{
85f9eb71
DV		 8122 struct drm_encoder *encoder;
8123 struct drm_connector *connector;
8124 int count;
8125
1aa4b628
DV		 8126 config->save_encoder_crtcs =
8127 kcalloc(dev->mode_config.num_encoder,
8128 sizeof(struct drm_crtc *), GFP_KERNEL);
8129 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8130 return -ENOMEM;
8131
1aa4b628
DV		 8132 config->save_connector_encoders =
8133 kcalloc(dev->mode_config.num_connector,
8134 sizeof(struct drm_encoder *), GFP_KERNEL);
8135 if (!config->save_connector_encoders)
85f9eb71
DV		 8136 return -ENOMEM;
8137
8138 /* Copy data. Note that driver private data is not affected.
8139 * Should anything bad happen only the expected state is
8140 * restored, not the drivers personal bookkeeping.
8141 */
85f9eb71
DV		 8142 count = 0;
8143 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8144 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8145 }
8146
8147 count = 0;
8148 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8149 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8150 }
8151
8152 return 0;
8153}
8154
8155static void intel_set_config_restore_state(struct drm_device *dev,
8156 struct intel_set_config *config)
8157{
9a935856
DV		 8158 struct intel_encoder *encoder;
8159 struct intel_connector *connector;
85f9eb71
DV		 8160 int count;
8161
85f9eb71 8162 count = 0;
9a935856
DV		 8163 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8164 encoder->new_crtc =
8165 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8166 }
8167
8168 count = 0;
9a935856
DV		 8169 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8170 connector->new_encoder =
8171 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8172 }
8173}
8174
5e2b584e
DV		 8175static void
8176intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8177 struct intel_set_config *config)
8178{
8179
8180 /* We should be able to check here if the fb has the same properties
8181 * and then just flip_or_move it */
8182 if (set->crtc->fb != set->fb) {
8183 /* If we have no fb then treat it as a full mode set */
8184 if (set->crtc->fb == NULL) {
8185 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8186 config->mode_changed = true;
8187 } else if (set->fb == NULL) {
8188 config->mode_changed = true;
72f4901e
DV		 8189 } else if (set->fb->pixel_format !=
8190 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8191 config->mode_changed = true;
8192 } else
8193 config->fb_changed = true;
8194 }
8195
835c5873 8196 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8197 config->fb_changed = true;
8198
8199 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8200 DRM_DEBUG_KMS("modes are different, full mode set\n");
8201 drm_mode_debug_printmodeline(&set->crtc->mode);
8202 drm_mode_debug_printmodeline(set->mode);
8203 config->mode_changed = true;
8204 }
8205}
8206
2e431051 8207static int
9a935856
DV		 8208intel_modeset_stage_output_state(struct drm_device *dev,
8209 struct drm_mode_set *set,
8210 struct intel_set_config *config)
50f56119 8211{
85f9eb71 8212 struct drm_crtc *new_crtc;
9a935856
DV		 8213 struct intel_connector *connector;
8214 struct intel_encoder *encoder;
2e431051 8215 int count, ro;
50f56119 8216
9abdda74 8217 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8218 * of connectors. For paranoia, double-check this. */
8219 WARN_ON(!set->fb && (set->num_connectors != 0));
8220 WARN_ON(set->fb && (set->num_connectors == 0));
8221
50f56119 8222 count = 0;
9a935856
DV		 8223 list_for_each_entry(connector, &dev->mode_config.connector_list,
8224 base.head) {
8225 /* Otherwise traverse passed in connector list and get encoders
8226 * for them. */
50f56119 8227 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8228 if (set->connectors[ro] == &connector->base) {
8229 connector->new_encoder = connector->encoder;
50f56119
DV		 8230 break;
8231 }
8232 }
8233
9a935856
DV		 8234 /* If we disable the crtc, disable all its connectors. Also, if
8235 * the connector is on the changing crtc but not on the new
8236 * connector list, disable it. */
8237 if ((!set->fb || ro == set->num_connectors) &&
8238 connector->base.encoder &&
8239 connector->base.encoder->crtc == set->crtc) {
8240 connector->new_encoder = NULL;
8241
8242 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8243 connector->base.base.id,
8244 drm_get_connector_name(&connector->base));
8245 }
8246
8247
8248 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8249 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8250 config->mode_changed = true;
50f56119
DV		 8251 }
8252 }
9a935856 8253 /* connector->new_encoder is now updated for all connectors. */
50f56119 8254
9a935856 8255 /* Update crtc of enabled connectors. */
50f56119 8256 count = 0;
9a935856
DV		 8257 list_for_each_entry(connector, &dev->mode_config.connector_list,
8258 base.head) {
8259 if (!connector->new_encoder)
50f56119
DV		 8260 continue;
8261
9a935856 8262 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8263
8264 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8265 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8266 new_crtc = set->crtc;
8267 }
8268
8269 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8270 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8271 new_crtc)) {
5e2b584e 8272 return -EINVAL;
50f56119 8273 }
9a935856
DV		 8274 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8275
8276 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8277 connector->base.base.id,
8278 drm_get_connector_name(&connector->base),
8279 new_crtc->base.id);
8280 }
8281
8282 /* Check for any encoders that needs to be disabled. */
8283 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8284 base.head) {
8285 list_for_each_entry(connector,
8286 &dev->mode_config.connector_list,
8287 base.head) {
8288 if (connector->new_encoder == encoder) {
8289 WARN_ON(!connector->new_encoder->new_crtc);
8290
8291 goto next_encoder;
8292 }
8293 }
8294 encoder->new_crtc = NULL;
8295next_encoder:
8296 /* Only now check for crtc changes so we don't miss encoders
8297 * that will be disabled. */
8298 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8299 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8300 config->mode_changed = true;
50f56119
DV		 8301 }
8302 }
9a935856 8303 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8304
2e431051
DV		 8305 return 0;
8306}
8307
8308static int intel_crtc_set_config(struct drm_mode_set *set)
8309{
8310 struct drm_device *dev;
2e431051
DV		 8311 struct drm_mode_set save_set;
8312 struct intel_set_config *config;
8313 int ret;
2e431051 8314
8d3e375e
DV		 8315 BUG_ON(!set);
8316 BUG_ON(!set->crtc);
8317 BUG_ON(!set->crtc->helper_private);
2e431051 8318
7e53f3a4
DV		 8319 /* Enforce sane interface api - has been abused by the fb helper. */
8320 BUG_ON(!set->mode && set->fb);
8321 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8322
2e431051
DV		 8323 if (set->fb) {
8324 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8325 set->crtc->base.id, set->fb->base.id,
8326 (int)set->num_connectors, set->x, set->y);
8327 } else {
8328 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8329 }
8330
8331 dev = set->crtc->dev;
8332
8333 ret = -ENOMEM;
8334 config = kzalloc(sizeof(*config), GFP_KERNEL);
8335 if (!config)
8336 goto out_config;
8337
8338 ret = intel_set_config_save_state(dev, config);
8339 if (ret)
8340 goto out_config;
8341
8342 save_set.crtc = set->crtc;
8343 save_set.mode = &set->crtc->mode;
8344 save_set.x = set->crtc->x;
8345 save_set.y = set->crtc->y;
8346 save_set.fb = set->crtc->fb;
8347
8348 /* Compute whether we need a full modeset, only an fb base update or no
8349 * change at all. In the future we might also check whether only the
8350 * mode changed, e.g. for LVDS where we only change the panel fitter in
8351 * such cases. */
8352 intel_set_config_compute_mode_changes(set, config);
8353
9a935856 8354 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8355 if (ret)
8356 goto fail;
8357
5e2b584e 8358 if (config->mode_changed) {
87f1faa6 8359 if (set->mode) {
50f56119
DV		 8360 DRM_DEBUG_KMS("attempting to set mode from"
8361 " userspace\n");
8362 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8363 }
8364
c0c36b94
CW		 8365 ret = intel_set_mode(set->crtc, set->mode,
8366 set->x, set->y, set->fb);
8367 if (ret) {
8368 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8369 set->crtc->base.id, ret);
87f1faa6
DV		 8370 goto fail;
8371 }
5e2b584e 8372 } else if (config->fb_changed) {
4878cae2
VS		 8373 intel_crtc_wait_for_pending_flips(set->crtc);
8374
4f660f49 8375 ret = intel_pipe_set_base(set->crtc,
94352cf9 8376 set->x, set->y, set->fb);
50f56119
DV		 8377 }
8378
d9e55608
DV		 8379 intel_set_config_free(config);
8380
50f56119
DV		 8381 return 0;
8382
8383fail:
85f9eb71 8384 intel_set_config_restore_state(dev, config);
50f56119
DV		 8385
8386 /* Try to restore the config */
5e2b584e 8387 if (config->mode_changed &&
c0c36b94
CW		 8388 intel_set_mode(save_set.crtc, save_set.mode,
8389 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8390 DRM_ERROR("failed to restore config after modeset failure\n");
8391
d9e55608
DV		 8392out_config:
8393 intel_set_config_free(config);
50f56119
DV		 8394 return ret;
8395}
f6e5b160
CW		 8396
8397static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8398 .cursor_set = intel_crtc_cursor_set,
8399 .cursor_move = intel_crtc_cursor_move,
8400 .gamma_set = intel_crtc_gamma_set,
50f56119 8401 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8402 .destroy = intel_crtc_destroy,
8403 .page_flip = intel_crtc_page_flip,
8404};
8405
79f689aa
PZ		 8406static void intel_cpu_pll_init(struct drm_device *dev)
8407{
affa9354 8408 if (HAS_DDI(dev))
79f689aa
PZ		 8409 intel_ddi_pll_init(dev);
8410}
8411
ee7b9f93
JB		 8412static void intel_pch_pll_init(struct drm_device *dev)
8413{
8414 drm_i915_private_t *dev_priv = dev->dev_private;
8415 int i;
8416
8417 if (dev_priv->num_pch_pll == 0) {
8418 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8419 return;
8420 }
8421
8422 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8423 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8424 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8425 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8426 }
8427}
8428
b358d0a6 8429static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8430{
22fd0fab 8431 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8432 struct intel_crtc *intel_crtc;
8433 int i;
8434
8435 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8436 if (intel_crtc == NULL)
8437 return;
8438
8439 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8440
8441 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8442 for (i = 0; i < 256; i++) {
8443 intel_crtc->lut_r[i] = i;
8444 intel_crtc->lut_g[i] = i;
8445 intel_crtc->lut_b[i] = i;
8446 }
8447
80824003
JB		 8448 /* Swap pipes & planes for FBC on pre-965 */
8449 intel_crtc->pipe = pipe;
8450 intel_crtc->plane = pipe;
3b117c8f 8451 intel_crtc->config.cpu_transcoder = pipe;
e2e767ab 8452 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8453 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8454 intel_crtc->plane = !pipe;
80824003
JB		 8455 }
8456
22fd0fab
JB		 8457 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8458 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8459 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8460 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8461
79e53945 8462 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8463}
8464
08d7b3d1 8465int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8466 struct drm_file *file)
08d7b3d1 8467{
08d7b3d1 8468 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8469 struct drm_mode_object *drmmode_obj;
8470 struct intel_crtc *crtc;
08d7b3d1 8471
1cff8f6b
DV		 8472 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8473 return -ENODEV;
08d7b3d1 8474
c05422d5
DV		 8475 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8476 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8477
c05422d5 8478 if (!drmmode_obj) {
08d7b3d1
CW		 8479 DRM_ERROR("no such CRTC id\n");
8480 return -EINVAL;
8481 }
8482
c05422d5
DV		 8483 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8484 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8485
c05422d5 8486 return 0;
08d7b3d1
CW		 8487}
8488
66a9278e 8489static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8490{
66a9278e
DV		 8491 struct drm_device *dev = encoder->base.dev;
8492 struct intel_encoder *source_encoder;
79e53945 8493 int index_mask = 0;
79e53945
JB		 8494 int entry = 0;
8495
66a9278e
DV		 8496 list_for_each_entry(source_encoder,
8497 &dev->mode_config.encoder_list, base.head) {
8498
8499 if (encoder == source_encoder)
79e53945 8500 index_mask |= (1 << entry);
66a9278e
DV		 8501
8502 /* Intel hw has only one MUX where enocoders could be cloned. */
8503 if (encoder->cloneable && source_encoder->cloneable)
8504 index_mask |= (1 << entry);
8505
79e53945
JB		 8506 entry++;
8507 }
4ef69c7a 8508
79e53945
JB		 8509 return index_mask;
8510}
8511
4d302442
CW		 8512static bool has_edp_a(struct drm_device *dev)
8513{
8514 struct drm_i915_private *dev_priv = dev->dev_private;
8515
8516 if (!IS_MOBILE(dev))
8517 return false;
8518
8519 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8520 return false;
8521
8522 if (IS_GEN5(dev) &&
8523 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8524 return false;
8525
8526 return true;
8527}
8528
79e53945
JB		 8529static void intel_setup_outputs(struct drm_device *dev)
8530{
725e30ad 8531 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8532 struct intel_encoder *encoder;
cb0953d7 8533 bool dpd_is_edp = false;
f3cfcba6 8534 bool has_lvds;
79e53945 8535
f3cfcba6 8536 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8537 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8538 /* disable the panel fitter on everything but LVDS */
8539 I915_WRITE(PFIT_CONTROL, 0);
8540 }
79e53945 8541
c40c0f5b 8542 if (!IS_ULT(dev))
79935fca 8543 intel_crt_init(dev);
cb0953d7 8544
affa9354 8545 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8546 int found;
8547
8548 /* Haswell uses DDI functions to detect digital outputs */
8549 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8550 /* DDI A only supports eDP */
8551 if (found)
8552 intel_ddi_init(dev, PORT_A);
8553
8554 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8555 * register */
8556 found = I915_READ(SFUSE_STRAP);
8557
8558 if (found & SFUSE_STRAP_DDIB_DETECTED)
8559 intel_ddi_init(dev, PORT_B);
8560 if (found & SFUSE_STRAP_DDIC_DETECTED)
8561 intel_ddi_init(dev, PORT_C);
8562 if (found & SFUSE_STRAP_DDID_DETECTED)
8563 intel_ddi_init(dev, PORT_D);
8564 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8565 int found;
270b3042
DV		 8566 dpd_is_edp = intel_dpd_is_edp(dev);
8567
8568 if (has_edp_a(dev))
8569 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8570
dc0fa718 8571 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8572 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8573 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8574 if (!found)
e2debe91 8575 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8576 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8577 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8578 }
8579
dc0fa718 8580 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8581 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8582
dc0fa718 8583 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8584 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8585
5eb08b69 8586 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8587 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8588
270b3042 8589 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8590 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8591 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8592 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8593 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8594 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8595
dc0fa718 8596 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8597 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8598 PORT_B);
67cfc203
VS		 8599 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8600 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8601 }
103a196f 8602 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8603 bool found = false;
7d57382e 8604
e2debe91 8605 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8606 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8607 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8608 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8609 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8610 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8611 }
27185ae1 8612
b01f2c3a
JB		 8613 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8614 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8615 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8616 }
725e30ad 8617 }
13520b05
KH		 8618
8619 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8620
e2debe91 8621 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8622 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8623 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8624 }
27185ae1 8625
e2debe91 8626 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8627
b01f2c3a
JB		 8628 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8629 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8630 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8631 }
8632 if (SUPPORTS_INTEGRATED_DP(dev)) {
8633 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8634 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8635 }
725e30ad 8636 }
27185ae1 8637
b01f2c3a
JB		 8638 if (SUPPORTS_INTEGRATED_DP(dev) &&
8639 (I915_READ(DP_D) & DP_DETECTED)) {
8640 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8641 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8642 }
bad720ff 8643 } else if (IS_GEN2(dev))
79e53945
JB		 8644 intel_dvo_init(dev);
8645
103a196f 8646 if (SUPPORTS_TV(dev))
79e53945
JB		 8647 intel_tv_init(dev);
8648
4ef69c7a
CW		 8649 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8650 encoder->base.possible_crtcs = encoder->crtc_mask;
8651 encoder->base.possible_clones =
66a9278e 8652 intel_encoder_clones(encoder);
79e53945 8653 }
47356eb6 8654
dde86e2d 8655 intel_init_pch_refclk(dev);
270b3042
DV		 8656
8657 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8658}
8659
8660static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8661{
8662 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8663
8664 drm_framebuffer_cleanup(fb);
05394f39 8665 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8666
8667 kfree(intel_fb);
8668}
8669
8670static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8671 struct drm_file *file,
79e53945
JB		 8672 unsigned int *handle)
8673{
8674 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8675 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8676
05394f39 8677 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8678}
8679
8680static const struct drm_framebuffer_funcs intel_fb_funcs = {
8681 .destroy = intel_user_framebuffer_destroy,
8682 .create_handle = intel_user_framebuffer_create_handle,
8683};
8684
38651674
DA		 8685int intel_framebuffer_init(struct drm_device *dev,
8686 struct intel_framebuffer *intel_fb,
308e5bcb 8687 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8688 struct drm_i915_gem_object *obj)
79e53945 8689{
79e53945
JB		 8690 int ret;
8691
c16ed4be
CW		 8692 if (obj->tiling_mode == I915_TILING_Y) {
8693 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8694 return -EINVAL;
c16ed4be 8695 }
57cd6508 8696
c16ed4be
CW		 8697 if (mode_cmd->pitches[0] & 63) {
8698 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8699 mode_cmd->pitches[0]);
57cd6508 8700 return -EINVAL;
c16ed4be 8701 }
57cd6508 8702
5d7bd705 8703 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8704 if (mode_cmd->pitches[0] > 32768) {
8705 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8706 mode_cmd->pitches[0]);
5d7bd705 8707 return -EINVAL;
c16ed4be 8708 }
5d7bd705
VS		 8709
8710 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8711 mode_cmd->pitches[0] != obj->stride) {
8712 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8713 mode_cmd->pitches[0], obj->stride);
5d7bd705 8714 return -EINVAL;
c16ed4be 8715 }
5d7bd705 8716
57779d06 8717 /* Reject formats not supported by any plane early. */
308e5bcb 8718 switch (mode_cmd->pixel_format) {
57779d06 8719 case DRM_FORMAT_C8:
04b3924d
VS		 8720 case DRM_FORMAT_RGB565:
8721 case DRM_FORMAT_XRGB8888:
8722 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8723 break;
8724 case DRM_FORMAT_XRGB1555:
8725 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8726 if (INTEL_INFO(dev)->gen > 3) {
8727 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8728 return -EINVAL;
c16ed4be 8729 }
57779d06
VS		 8730 break;
8731 case DRM_FORMAT_XBGR8888:
8732 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8733 case DRM_FORMAT_XRGB2101010:
8734 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8735 case DRM_FORMAT_XBGR2101010:
8736 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8737 if (INTEL_INFO(dev)->gen < 4) {
8738 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8739 return -EINVAL;
c16ed4be 8740 }
b5626747 8741 break;
04b3924d
VS		 8742 case DRM_FORMAT_YUYV:
8743 case DRM_FORMAT_UYVY:
8744 case DRM_FORMAT_YVYU:
8745 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8746 if (INTEL_INFO(dev)->gen < 5) {
8747 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8748 return -EINVAL;
c16ed4be 8749 }
57cd6508
CW		 8750 break;
8751 default:
c16ed4be 8752 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8753 return -EINVAL;
8754 }
8755
90f9a336
VS		 8756 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8757 if (mode_cmd->offsets[0] != 0)
8758 return -EINVAL;
8759
c7d73f6a
DV		 8760 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8761 intel_fb->obj = obj;
8762
79e53945
JB		 8763 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8764 if (ret) {
8765 DRM_ERROR("framebuffer init failed %d\n", ret);
8766 return ret;
8767 }
8768
79e53945
JB		 8769 return 0;
8770}
8771
79e53945
JB		 8772static struct drm_framebuffer *
8773intel_user_framebuffer_create(struct drm_device *dev,
8774 struct drm_file *filp,
308e5bcb 8775 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8776{
05394f39 8777 struct drm_i915_gem_object *obj;
79e53945 8778
308e5bcb
JB		 8779 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8780 mode_cmd->handles[0]));
c8725226 8781 if (&obj->base == NULL)
cce13ff7 8782 return ERR_PTR(-ENOENT);
79e53945 8783
d2dff872 8784 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8785}
8786
79e53945 8787static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8788 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8789 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8790};
8791
e70236a8
JB		 8792/* Set up chip specific display functions */
8793static void intel_init_display(struct drm_device *dev)
8794{
8795 struct drm_i915_private *dev_priv = dev->dev_private;
8796
affa9354 8797 if (HAS_DDI(dev)) {
0e8ffe1b 8798 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 8799 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8800 dev_priv->display.crtc_enable = haswell_crtc_enable;
8801 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8802 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8803 dev_priv->display.update_plane = ironlake_update_plane;
8804 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 8805 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 8806 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8807 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8808 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8809 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8810 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 8811 } else if (IS_VALLEYVIEW(dev)) {
8812 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8813 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8814 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8815 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8816 dev_priv->display.off = i9xx_crtc_off;
8817 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8818 } else {
0e8ffe1b 8819 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 8820 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8821 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8822 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8823 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8824 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8825 }
e70236a8 8826
e70236a8 8827 /* Returns the core display clock speed */
25eb05fc
JB		 8828 if (IS_VALLEYVIEW(dev))
8829 dev_priv->display.get_display_clock_speed =
8830 valleyview_get_display_clock_speed;
8831 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8832 dev_priv->display.get_display_clock_speed =
8833 i945_get_display_clock_speed;
8834 else if (IS_I915G(dev))
8835 dev_priv->display.get_display_clock_speed =
8836 i915_get_display_clock_speed;
f2b115e6 8837 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8838 dev_priv->display.get_display_clock_speed =
8839 i9xx_misc_get_display_clock_speed;
8840 else if (IS_I915GM(dev))
8841 dev_priv->display.get_display_clock_speed =
8842 i915gm_get_display_clock_speed;
8843 else if (IS_I865G(dev))
8844 dev_priv->display.get_display_clock_speed =
8845 i865_get_display_clock_speed;
f0f8a9ce 8846 else if (IS_I85X(dev))
e70236a8
JB		 8847 dev_priv->display.get_display_clock_speed =
8848 i855_get_display_clock_speed;
8849 else /* 852, 830 */
8850 dev_priv->display.get_display_clock_speed =
8851 i830_get_display_clock_speed;
8852
7f8a8569 8853 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8854 if (IS_GEN5(dev)) {
674cf967 8855 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8856 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8857 } else if (IS_GEN6(dev)) {
674cf967 8858 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8859 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8860 } else if (IS_IVYBRIDGE(dev)) {
8861 /* FIXME: detect B0+ stepping and use auto training */
8862 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8863 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8864 dev_priv->display.modeset_global_resources =
8865 ivb_modeset_global_resources;
c82e4d26
ED		 8866 } else if (IS_HASWELL(dev)) {
8867 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8868 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8869 dev_priv->display.modeset_global_resources =
8870 haswell_modeset_global_resources;
a0e63c22 8871 }
6067aaea 8872 } else if (IS_G4X(dev)) {
e0dac65e 8873 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8874 }
8c9f3aaf
JB		 8875
8876 /* Default just returns -ENODEV to indicate unsupported */
8877 dev_priv->display.queue_flip = intel_default_queue_flip;
8878
8879 switch (INTEL_INFO(dev)->gen) {
8880 case 2:
8881 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8882 break;
8883
8884 case 3:
8885 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8886 break;
8887
8888 case 4:
8889 case 5:
8890 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8891 break;
8892
8893 case 6:
8894 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8895 break;
7c9017e5
JB		 8896 case 7:
8897 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8898 break;
8c9f3aaf 8899 }
e70236a8
JB		 8900}
8901
b690e96c
JB		 8902/*
8903 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8904 * resume, or other times. This quirk makes sure that's the case for
8905 * affected systems.
8906 */
0206e353 8907static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8908{
8909 struct drm_i915_private *dev_priv = dev->dev_private;
8910
8911 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8912 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8913}
8914
435793df
KP		 8915/*
8916 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8917 */
8918static void quirk_ssc_force_disable(struct drm_device *dev)
8919{
8920 struct drm_i915_private *dev_priv = dev->dev_private;
8921 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8922 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8923}
8924
4dca20ef 8925/*
5a15ab5b
CE		 8926 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8927 * brightness value
4dca20ef
CE		 8928 */
8929static void quirk_invert_brightness(struct drm_device *dev)
8930{
8931 struct drm_i915_private *dev_priv = dev->dev_private;
8932 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8933 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8934}
8935
b690e96c
JB		 8936struct intel_quirk {
8937 int device;
8938 int subsystem_vendor;
8939 int subsystem_device;
8940 void (*hook)(struct drm_device *dev);
8941};
8942
5f85f176
EE		 8943/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8944struct intel_dmi_quirk {
8945 void (*hook)(struct drm_device *dev);
8946 const struct dmi_system_id (*dmi_id_list)[];
8947};
8948
8949static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8950{
8951 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8952 return 1;
8953}
8954
8955static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8956 {
8957 .dmi_id_list = &(const struct dmi_system_id[]) {
8958 {
8959 .callback = intel_dmi_reverse_brightness,
8960 .ident = "NCR Corporation",
8961 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8962 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8963 },
8964 },
8965 { } /* terminating entry */
8966 },
8967 .hook = quirk_invert_brightness,
8968 },
8969};
8970
c43b5634 8971static struct intel_quirk intel_quirks[] = {
b690e96c 8972 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8973 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8974
b690e96c
JB		 8975 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8976 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8977
b690e96c
JB		 8978 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8979 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8980
ccd0d36e 8981 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8982 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8983 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8984
8985 /* Lenovo U160 cannot use SSC on LVDS */
8986 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8987
8988 /* Sony Vaio Y cannot use SSC on LVDS */
8989 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8990
8991 /* Acer Aspire 5734Z must invert backlight brightness */
8992 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8993
8994 /* Acer/eMachines G725 */
8995 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8996
8997 /* Acer/eMachines e725 */
8998 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8999
9000 /* Acer/Packard Bell NCL20 */
9001 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9002
9003 /* Acer Aspire 4736Z */
9004 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9005};
9006
9007static void intel_init_quirks(struct drm_device *dev)
9008{
9009 struct pci_dev *d = dev->pdev;
9010 int i;
9011
9012 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9013 struct intel_quirk *q = &intel_quirks[i];
9014
9015 if (d->device == q->device &&
9016 (d->subsystem_vendor == q->subsystem_vendor ||
9017 q->subsystem_vendor == PCI_ANY_ID) &&
9018 (d->subsystem_device == q->subsystem_device ||
9019 q->subsystem_device == PCI_ANY_ID))
9020 q->hook(dev);
9021 }
5f85f176
EE		 9022 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9023 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9024 intel_dmi_quirks[i].hook(dev);
9025 }
b690e96c
JB		 9026}
9027
9cce37f4
JB		 9028/* Disable the VGA plane that we never use */
9029static void i915_disable_vga(struct drm_device *dev)
9030{
9031 struct drm_i915_private *dev_priv = dev->dev_private;
9032 u8 sr1;
766aa1c4 9033 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9034
9035 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9036 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9037 sr1 = inb(VGA_SR_DATA);
9038 outb(sr1 | 1<<5, VGA_SR_DATA);
9039 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9040 udelay(300);
9041
9042 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9043 POSTING_READ(vga_reg);
9044}
9045
f817586c
DV		 9046void intel_modeset_init_hw(struct drm_device *dev)
9047{
fa42e23c 9048 intel_init_power_well(dev);
0232e927 9049
a8f78b58
ED		 9050 intel_prepare_ddi(dev);
9051
f817586c
DV		 9052 intel_init_clock_gating(dev);
9053
79f5b2c7 9054 mutex_lock(&dev->struct_mutex);
8090c6b9 9055 intel_enable_gt_powersave(dev);
79f5b2c7 9056 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9057}
9058
79e53945
JB		 9059void intel_modeset_init(struct drm_device *dev)
9060{
652c393a 9061 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9062 int i, j, ret;
79e53945
JB		 9063
9064 drm_mode_config_init(dev);
9065
9066 dev->mode_config.min_width = 0;
9067 dev->mode_config.min_height = 0;
9068
019d96cb
DA		 9069 dev->mode_config.preferred_depth = 24;
9070 dev->mode_config.prefer_shadow = 1;
9071
e6ecefaa 9072 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9073
b690e96c
JB		 9074 intel_init_quirks(dev);
9075
1fa61106
ED		 9076 intel_init_pm(dev);
9077
e3c74757
BW		 9078 if (INTEL_INFO(dev)->num_pipes == 0)
9079 return;
9080
e70236a8
JB		 9081 intel_init_display(dev);
9082
a6c45cf0
CW		 9083 if (IS_GEN2(dev)) {
9084 dev->mode_config.max_width = 2048;
9085 dev->mode_config.max_height = 2048;
9086 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9087 dev->mode_config.max_width = 4096;
9088 dev->mode_config.max_height = 4096;
79e53945 9089 } else {
a6c45cf0
CW		 9090 dev->mode_config.max_width = 8192;
9091 dev->mode_config.max_height = 8192;
79e53945 9092 }
5d4545ae 9093 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9094
28c97730 9095 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9096 INTEL_INFO(dev)->num_pipes,
9097 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9098
7eb552ae 9099 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9100 intel_crtc_init(dev, i);
7f1f3851
JB		 9101 for (j = 0; j < dev_priv->num_plane; j++) {
9102 ret = intel_plane_init(dev, i, j);
9103 if (ret)
06da8da2
VS		 9104 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9105 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9106 }
79e53945
JB		 9107 }
9108
79f689aa 9109 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9110 intel_pch_pll_init(dev);
9111
9cce37f4
JB		 9112 /* Just disable it once at startup */
9113 i915_disable_vga(dev);
79e53945 9114 intel_setup_outputs(dev);
11be49eb
CW		 9115
9116 /* Just in case the BIOS is doing something questionable. */
9117 intel_disable_fbc(dev);
2c7111db
CW		 9118}
9119
24929352
DV		 9120static void
9121intel_connector_break_all_links(struct intel_connector *connector)
9122{
9123 connector->base.dpms = DRM_MODE_DPMS_OFF;
9124 connector->base.encoder = NULL;
9125 connector->encoder->connectors_active = false;
9126 connector->encoder->base.crtc = NULL;
9127}
9128
7fad798e
DV		 9129static void intel_enable_pipe_a(struct drm_device *dev)
9130{
9131 struct intel_connector *connector;
9132 struct drm_connector *crt = NULL;
9133 struct intel_load_detect_pipe load_detect_temp;
9134
9135 /* We can't just switch on the pipe A, we need to set things up with a
9136 * proper mode and output configuration. As a gross hack, enable pipe A
9137 * by enabling the load detect pipe once. */
9138 list_for_each_entry(connector,
9139 &dev->mode_config.connector_list,
9140 base.head) {
9141 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9142 crt = &connector->base;
9143 break;
9144 }
9145 }
9146
9147 if (!crt)
9148 return;
9149
9150 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9151 intel_release_load_detect_pipe(crt, &load_detect_temp);
9152
652c393a 9153
7fad798e
DV		 9154}
9155
fa555837
DV		 9156static bool
9157intel_check_plane_mapping(struct intel_crtc *crtc)
9158{
7eb552ae
BW		 9159 struct drm_device *dev = crtc->base.dev;
9160 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9161 u32 reg, val;
9162
7eb552ae 9163 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9164 return true;
9165
9166 reg = DSPCNTR(!crtc->plane);
9167 val = I915_READ(reg);
9168
9169 if ((val & DISPLAY_PLANE_ENABLE) &&
9170 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9171 return false;
9172
9173 return true;
9174}
9175
24929352
DV		 9176static void intel_sanitize_crtc(struct intel_crtc *crtc)
9177{
9178 struct drm_device *dev = crtc->base.dev;
9179 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9180 u32 reg;
24929352 9181
24929352 9182 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9183 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9184 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9185
9186 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9187 * disable the crtc (and hence change the state) if it is wrong. Note
9188 * that gen4+ has a fixed plane -> pipe mapping. */
9189 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9190 struct intel_connector *connector;
9191 bool plane;
9192
24929352
DV		 9193 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9194 crtc->base.base.id);
9195
9196 /* Pipe has the wrong plane attached and the plane is active.
9197 * Temporarily change the plane mapping and disable everything
9198 * ... */
9199 plane = crtc->plane;
9200 crtc->plane = !plane;
9201 dev_priv->display.crtc_disable(&crtc->base);
9202 crtc->plane = plane;
9203
9204 /* ... and break all links. */
9205 list_for_each_entry(connector, &dev->mode_config.connector_list,
9206 base.head) {
9207 if (connector->encoder->base.crtc != &crtc->base)
9208 continue;
9209
9210 intel_connector_break_all_links(connector);
9211 }
9212
9213 WARN_ON(crtc->active);
9214 crtc->base.enabled = false;
9215 }
24929352 9216
7fad798e
DV		 9217 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9218 crtc->pipe == PIPE_A && !crtc->active) {
9219 /* BIOS forgot to enable pipe A, this mostly happens after
9220 * resume. Force-enable the pipe to fix this, the update_dpms
9221 * call below we restore the pipe to the right state, but leave
9222 * the required bits on. */
9223 intel_enable_pipe_a(dev);
9224 }
9225
24929352
DV		 9226 /* Adjust the state of the output pipe according to whether we
9227 * have active connectors/encoders. */
9228 intel_crtc_update_dpms(&crtc->base);
9229
9230 if (crtc->active != crtc->base.enabled) {
9231 struct intel_encoder *encoder;
9232
9233 /* This can happen either due to bugs in the get_hw_state
9234 * functions or because the pipe is force-enabled due to the
9235 * pipe A quirk. */
9236 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9237 crtc->base.base.id,
9238 crtc->base.enabled ? "enabled" : "disabled",
9239 crtc->active ? "enabled" : "disabled");
9240
9241 crtc->base.enabled = crtc->active;
9242
9243 /* Because we only establish the connector -> encoder ->
9244 * crtc links if something is active, this means the
9245 * crtc is now deactivated. Break the links. connector
9246 * -> encoder links are only establish when things are
9247 * actually up, hence no need to break them. */
9248 WARN_ON(crtc->active);
9249
9250 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9251 WARN_ON(encoder->connectors_active);
9252 encoder->base.crtc = NULL;
9253 }
9254 }
9255}
9256
9257static void intel_sanitize_encoder(struct intel_encoder *encoder)
9258{
9259 struct intel_connector *connector;
9260 struct drm_device *dev = encoder->base.dev;
9261
9262 /* We need to check both for a crtc link (meaning that the
9263 * encoder is active and trying to read from a pipe) and the
9264 * pipe itself being active. */
9265 bool has_active_crtc = encoder->base.crtc &&
9266 to_intel_crtc(encoder->base.crtc)->active;
9267
9268 if (encoder->connectors_active && !has_active_crtc) {
9269 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9270 encoder->base.base.id,
9271 drm_get_encoder_name(&encoder->base));
9272
9273 /* Connector is active, but has no active pipe. This is
9274 * fallout from our resume register restoring. Disable
9275 * the encoder manually again. */
9276 if (encoder->base.crtc) {
9277 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9278 encoder->base.base.id,
9279 drm_get_encoder_name(&encoder->base));
9280 encoder->disable(encoder);
9281 }
9282
9283 /* Inconsistent output/port/pipe state happens presumably due to
9284 * a bug in one of the get_hw_state functions. Or someplace else
9285 * in our code, like the register restore mess on resume. Clamp
9286 * things to off as a safer default. */
9287 list_for_each_entry(connector,
9288 &dev->mode_config.connector_list,
9289 base.head) {
9290 if (connector->encoder != encoder)
9291 continue;
9292
9293 intel_connector_break_all_links(connector);
9294 }
9295 }
9296 /* Enabled encoders without active connectors will be fixed in
9297 * the crtc fixup. */
9298}
9299
44cec740 9300void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9301{
9302 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9303 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9304
9305 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9306 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9307 i915_disable_vga(dev);
0fde901f
KM		 9308 }
9309}
9310
24929352
DV		 9311/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9312 * and i915 state tracking structures. */
45e2b5f6
DV		 9313void intel_modeset_setup_hw_state(struct drm_device *dev,
9314 bool force_restore)
24929352
DV		 9315{
9316 struct drm_i915_private *dev_priv = dev->dev_private;
9317 enum pipe pipe;
9318 u32 tmp;
b5644d05 9319 struct drm_plane *plane;
24929352
DV		 9320 struct intel_crtc *crtc;
9321 struct intel_encoder *encoder;
9322 struct intel_connector *connector;
9323
affa9354 9324 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9325 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9326
9327 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9328 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9329 case TRANS_DDI_EDP_INPUT_A_ON:
9330 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9331 pipe = PIPE_A;
9332 break;
9333 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9334 pipe = PIPE_B;
9335 break;
9336 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9337 pipe = PIPE_C;
9338 break;
aaa148ec
DL		 9339 default:
9340 /* A bogus value has been programmed, disable
9341 * the transcoder */
9342 WARN(1, "Bogus eDP source %08x\n", tmp);
9343 intel_ddi_disable_transcoder_func(dev_priv,
9344 TRANSCODER_EDP);
9345 goto setup_pipes;
e28d54cb
PZ		 9346 }
9347
9348 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3b117c8f 9349 crtc->config.cpu_transcoder = TRANSCODER_EDP;
e28d54cb
PZ		 9350
9351 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9352 pipe_name(pipe));
9353 }
9354 }
9355
aaa148ec 9356setup_pipes:
0e8ffe1b
DV		 9357 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9358 base.head) {
3b117c8f 9359 enum transcoder tmp = crtc->config.cpu_transcoder;
88adfff1 9360 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f
DV		 9361 crtc->config.cpu_transcoder = tmp;
9362
0e8ffe1b
DV		 9363 crtc->active = dev_priv->display.get_pipe_config(crtc,
9364 &crtc->config);
24929352
DV		 9365
9366 crtc->base.enabled = crtc->active;
9367
9368 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9369 crtc->base.base.id,
9370 crtc->active ? "enabled" : "disabled");
9371 }
9372
affa9354 9373 if (HAS_DDI(dev))
6441ab5f
PZ		 9374 intel_ddi_setup_hw_pll_state(dev);
9375
24929352
DV		 9376 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9377 base.head) {
9378 pipe = 0;
9379
9380 if (encoder->get_hw_state(encoder, &pipe)) {
9381 encoder->base.crtc =
9382 dev_priv->pipe_to_crtc_mapping[pipe];
9383 } else {
9384 encoder->base.crtc = NULL;
9385 }
9386
9387 encoder->connectors_active = false;
9388 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9389 encoder->base.base.id,
9390 drm_get_encoder_name(&encoder->base),
9391 encoder->base.crtc ? "enabled" : "disabled",
9392 pipe);
9393 }
9394
9395 list_for_each_entry(connector, &dev->mode_config.connector_list,
9396 base.head) {
9397 if (connector->get_hw_state(connector)) {
9398 connector->base.dpms = DRM_MODE_DPMS_ON;
9399 connector->encoder->connectors_active = true;
9400 connector->base.encoder = &connector->encoder->base;
9401 } else {
9402 connector->base.dpms = DRM_MODE_DPMS_OFF;
9403 connector->base.encoder = NULL;
9404 }
9405 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9406 connector->base.base.id,
9407 drm_get_connector_name(&connector->base),
9408 connector->base.encoder ? "enabled" : "disabled");
9409 }
9410
9411 /* HW state is read out, now we need to sanitize this mess. */
9412 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9413 base.head) {
9414 intel_sanitize_encoder(encoder);
9415 }
9416
9417 for_each_pipe(pipe) {
9418 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9419 intel_sanitize_crtc(crtc);
9420 }
9a935856 9421
45e2b5f6 9422 if (force_restore) {
f30da187
DV		 9423 /*
9424 * We need to use raw interfaces for restoring state to avoid
9425 * checking (bogus) intermediate states.
9426 */
45e2b5f6 9427 for_each_pipe(pipe) {
b5644d05
JB		 9428 struct drm_crtc *crtc =
9429 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9430
9431 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9432 crtc->fb);
45e2b5f6 9433 }
b5644d05
JB		 9434 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9435 intel_plane_restore(plane);
0fde901f
KM		 9436
9437 i915_redisable_vga(dev);
45e2b5f6
DV		 9438 } else {
9439 intel_modeset_update_staged_output_state(dev);
9440 }
8af6cf88
DV		 9441
9442 intel_modeset_check_state(dev);
2e938892
DV		 9443
9444 drm_mode_config_reset(dev);
2c7111db
CW		 9445}
9446
9447void intel_modeset_gem_init(struct drm_device *dev)
9448{
1833b134 9449 intel_modeset_init_hw(dev);
02e792fb
DV		 9450
9451 intel_setup_overlay(dev);
24929352 9452
45e2b5f6 9453 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9454}
9455
9456void intel_modeset_cleanup(struct drm_device *dev)
9457{
652c393a
JB		 9458 struct drm_i915_private *dev_priv = dev->dev_private;
9459 struct drm_crtc *crtc;
9460 struct intel_crtc *intel_crtc;
9461
fd0c0642
DV		 9462 /*
9463 * Interrupts and polling as the first thing to avoid creating havoc.
9464 * Too much stuff here (turning of rps, connectors, ...) would
9465 * experience fancy races otherwise.
9466 */
9467 drm_irq_uninstall(dev);
9468 cancel_work_sync(&dev_priv->hotplug_work);
9469 /*
9470 * Due to the hpd irq storm handling the hotplug work can re-arm the
9471 * poll handlers. Hence disable polling after hpd handling is shut down.
9472 */
f87ea761 9473 drm_kms_helper_poll_fini(dev);
fd0c0642 9474
652c393a
JB		 9475 mutex_lock(&dev->struct_mutex);
9476
723bfd70
JB		 9477 intel_unregister_dsm_handler();
9478
652c393a
JB		 9479 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9480 /* Skip inactive CRTCs */
9481 if (!crtc->fb)
9482 continue;
9483
9484 intel_crtc = to_intel_crtc(crtc);
3dec0095 9485 intel_increase_pllclock(crtc);
652c393a
JB		 9486 }
9487
973d04f9 9488 intel_disable_fbc(dev);
e70236a8 9489
8090c6b9 9490 intel_disable_gt_powersave(dev);
0cdab21f 9491
930ebb46
DV		 9492 ironlake_teardown_rc6(dev);
9493
69341a5e
KH		 9494 mutex_unlock(&dev->struct_mutex);
9495
1630fe75
CW		 9496 /* flush any delayed tasks or pending work */
9497 flush_scheduled_work();
9498
dc652f90
JN		 9499 /* destroy backlight, if any, before the connectors */
9500 intel_panel_destroy_backlight(dev);
9501
79e53945 9502 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9503
9504 intel_cleanup_overlay(dev);
79e53945
JB		 9505}
9506
f1c79df3
ZW		 9507/*
9508 * Return which encoder is currently attached for connector.
9509 */
df0e9248 9510struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9511{
df0e9248
CW		 9512 return &intel_attached_encoder(connector)->base;
9513}
f1c79df3 9514
df0e9248
CW		 9515void intel_connector_attach_encoder(struct intel_connector *connector,
9516 struct intel_encoder *encoder)
9517{
9518 connector->encoder = encoder;
9519 drm_mode_connector_attach_encoder(&connector->base,
9520 &encoder->base);
79e53945 9521}
28d52043
DA		 9522
9523/*
9524 * set vga decode state - true == enable VGA decode
9525 */
9526int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9527{
9528 struct drm_i915_private *dev_priv = dev->dev_private;
9529 u16 gmch_ctrl;
9530
9531 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9532 if (state)
9533 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9534 else
9535 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9536 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9537 return 0;
9538}
c4a1d9e4
CW		 9539
9540#ifdef CONFIG_DEBUG_FS
9541#include <linux/seq_file.h>
9542
9543struct intel_display_error_state {
9544 struct intel_cursor_error_state {
9545 u32 control;
9546 u32 position;
9547 u32 base;
9548 u32 size;
52331309 9549 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9550
9551 struct intel_pipe_error_state {
9552 u32 conf;
9553 u32 source;
9554
9555 u32 htotal;
9556 u32 hblank;
9557 u32 hsync;
9558 u32 vtotal;
9559 u32 vblank;
9560 u32 vsync;
52331309 9561 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9562
9563 struct intel_plane_error_state {
9564 u32 control;
9565 u32 stride;
9566 u32 size;
9567 u32 pos;
9568 u32 addr;
9569 u32 surface;
9570 u32 tile_offset;
52331309 9571 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9572};
9573
9574struct intel_display_error_state *
9575intel_display_capture_error_state(struct drm_device *dev)
9576{
0206e353 9577 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9578 struct intel_display_error_state *error;
702e7a56 9579 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9580 int i;
9581
9582 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9583 if (error == NULL)
9584 return NULL;
9585
52331309 9586 for_each_pipe(i) {
702e7a56
PZ		 9587 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9588
a18c4c3d
PZ		 9589 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9590 error->cursor[i].control = I915_READ(CURCNTR(i));
9591 error->cursor[i].position = I915_READ(CURPOS(i));
9592 error->cursor[i].base = I915_READ(CURBASE(i));
9593 } else {
9594 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9595 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9596 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9597 }
c4a1d9e4
CW		 9598
9599 error->plane[i].control = I915_READ(DSPCNTR(i));
9600 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9601 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9602 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9603 error->plane[i].pos = I915_READ(DSPPOS(i));
9604 }
ca291363
PZ		 9605 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9606 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9607 if (INTEL_INFO(dev)->gen >= 4) {
9608 error->plane[i].surface = I915_READ(DSPSURF(i));
9609 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9610 }
9611
702e7a56 9612 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9613 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9614 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9615 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9616 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9617 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9618 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9619 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9620 }
9621
9622 return error;
9623}
9624
9625void
9626intel_display_print_error_state(struct seq_file *m,
9627 struct drm_device *dev,
9628 struct intel_display_error_state *error)
9629{
9630 int i;
9631
7eb552ae 9632 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9633 for_each_pipe(i) {
c4a1d9e4
CW		 9634 seq_printf(m, "Pipe [%d]:\n", i);
9635 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9636 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9637 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9638 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9639 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9640 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9641 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9642 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9643
9644 seq_printf(m, "Plane [%d]:\n", i);
9645 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9646 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9647 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9648 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9649 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9650 }
4b71a570 9651 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9652 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9653 if (INTEL_INFO(dev)->gen >= 4) {
9654 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9655 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9656 }
9657
9658 seq_printf(m, "Cursor [%d]:\n", i);
9659 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9660 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9661 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9662 }
9663}
9664#endif
Linux kernel - Deliverables
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