projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: consolidate pch pll computations a bit
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
f4808ab8
VS		 62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
d4906093 80};
79e53945 81
2377b741
JB		 82/* FDI */
83#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
d2acd215
DV		 85int
86intel_pch_rawclk(struct drm_device *dev)
87{
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93}
94
d4906093
ML		 95static bool
96intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
d4906093
ML		 99static bool
100intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
79e53945 103
a4fc5ed6
KP		 104static bool
105intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
5eb08b69 108static bool
f2b115e6 109intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 110 int target, int refclk, intel_clock_t *match_clock,
111 intel_clock_t *best_clock);
a4fc5ed6 112
a0c4da24
JB		 113static bool
114intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
115 int target, int refclk, intel_clock_t *match_clock,
116 intel_clock_t *best_clock);
117
021357ac
CW		 118static inline u32 /* units of 100MHz */
119intel_fdi_link_freq(struct drm_device *dev)
120{
8b99e68c
CW		 121 if (IS_GEN5(dev)) {
122 struct drm_i915_private *dev_priv = dev->dev_private;
123 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
124 } else
125 return 27;
021357ac
CW		 126}
127
e4b36699 128static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 129 .dot = { .min = 25000, .max = 350000 },
130 .vco = { .min = 930000, .max = 1400000 },
131 .n = { .min = 3, .max = 16 },
132 .m = { .min = 96, .max = 140 },
133 .m1 = { .min = 18, .max = 26 },
134 .m2 = { .min = 6, .max = 16 },
135 .p = { .min = 4, .max = 128 },
136 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 137 .p2 = { .dot_limit = 165000,
138 .p2_slow = 4, .p2_fast = 2 },
d4906093 139 .find_pll = intel_find_best_PLL,
e4b36699
KP		 140};
141
142static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 143 .dot = { .min = 25000, .max = 350000 },
144 .vco = { .min = 930000, .max = 1400000 },
145 .n = { .min = 3, .max = 16 },
146 .m = { .min = 96, .max = 140 },
147 .m1 = { .min = 18, .max = 26 },
148 .m2 = { .min = 6, .max = 16 },
149 .p = { .min = 4, .max = 128 },
150 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 151 .p2 = { .dot_limit = 165000,
152 .p2_slow = 14, .p2_fast = 7 },
d4906093 153 .find_pll = intel_find_best_PLL,
e4b36699 154};
273e27ca 155
e4b36699 156static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 157 .dot = { .min = 20000, .max = 400000 },
158 .vco = { .min = 1400000, .max = 2800000 },
159 .n = { .min = 1, .max = 6 },
160 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 161 .m1 = { .min = 8, .max = 18 },
162 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 163 .p = { .min = 5, .max = 80 },
164 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 165 .p2 = { .dot_limit = 200000,
166 .p2_slow = 10, .p2_fast = 5 },
d4906093 167 .find_pll = intel_find_best_PLL,
e4b36699
KP		 168};
169
170static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 171 .dot = { .min = 20000, .max = 400000 },
172 .vco = { .min = 1400000, .max = 2800000 },
173 .n = { .min = 1, .max = 6 },
174 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 175 .m1 = { .min = 8, .max = 18 },
176 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 177 .p = { .min = 7, .max = 98 },
178 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 179 .p2 = { .dot_limit = 112000,
180 .p2_slow = 14, .p2_fast = 7 },
d4906093 181 .find_pll = intel_find_best_PLL,
e4b36699
KP		 182};
183
273e27ca 184
e4b36699 185static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 186 .dot = { .min = 25000, .max = 270000 },
187 .vco = { .min = 1750000, .max = 3500000},
188 .n = { .min = 1, .max = 4 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 10, .max = 30 },
193 .p1 = { .min = 1, .max = 3},
194 .p2 = { .dot_limit = 270000,
195 .p2_slow = 10,
196 .p2_fast = 10
044c7c41 197 },
d4906093 198 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 199};
200
201static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 202 .dot = { .min = 22000, .max = 400000 },
203 .vco = { .min = 1750000, .max = 3500000},
204 .n = { .min = 1, .max = 4 },
205 .m = { .min = 104, .max = 138 },
206 .m1 = { .min = 16, .max = 23 },
207 .m2 = { .min = 5, .max = 11 },
208 .p = { .min = 5, .max = 80 },
209 .p1 = { .min = 1, .max = 8},
210 .p2 = { .dot_limit = 165000,
211 .p2_slow = 10, .p2_fast = 5 },
d4906093 212 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 213};
214
215static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 216 .dot = { .min = 20000, .max = 115000 },
217 .vco = { .min = 1750000, .max = 3500000 },
218 .n = { .min = 1, .max = 3 },
219 .m = { .min = 104, .max = 138 },
220 .m1 = { .min = 17, .max = 23 },
221 .m2 = { .min = 5, .max = 11 },
222 .p = { .min = 28, .max = 112 },
223 .p1 = { .min = 2, .max = 8 },
224 .p2 = { .dot_limit = 0,
225 .p2_slow = 14, .p2_fast = 14
044c7c41 226 },
d4906093 227 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 228};
229
230static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 231 .dot = { .min = 80000, .max = 224000 },
232 .vco = { .min = 1750000, .max = 3500000 },
233 .n = { .min = 1, .max = 3 },
234 .m = { .min = 104, .max = 138 },
235 .m1 = { .min = 17, .max = 23 },
236 .m2 = { .min = 5, .max = 11 },
237 .p = { .min = 14, .max = 42 },
238 .p1 = { .min = 2, .max = 6 },
239 .p2 = { .dot_limit = 0,
240 .p2_slow = 7, .p2_fast = 7
044c7c41 241 },
d4906093 242 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 243};
244
245static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 246 .dot = { .min = 161670, .max = 227000 },
247 .vco = { .min = 1750000, .max = 3500000},
248 .n = { .min = 1, .max = 2 },
249 .m = { .min = 97, .max = 108 },
250 .m1 = { .min = 0x10, .max = 0x12 },
251 .m2 = { .min = 0x05, .max = 0x06 },
252 .p = { .min = 10, .max = 20 },
253 .p1 = { .min = 1, .max = 2},
254 .p2 = { .dot_limit = 0,
273e27ca 255 .p2_slow = 10, .p2_fast = 10 },
0206e353 256 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 257};
258
f2b115e6 259static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 260 .dot = { .min = 20000, .max = 400000},
261 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 262 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 263 .n = { .min = 3, .max = 6 },
264 .m = { .min = 2, .max = 256 },
273e27ca 265 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 266 .m1 = { .min = 0, .max = 0 },
267 .m2 = { .min = 0, .max = 254 },
268 .p = { .min = 5, .max = 80 },
269 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 270 .p2 = { .dot_limit = 200000,
271 .p2_slow = 10, .p2_fast = 5 },
6115707b 272 .find_pll = intel_find_best_PLL,
e4b36699
KP		 273};
274
f2b115e6 275static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 276 .dot = { .min = 20000, .max = 400000 },
277 .vco = { .min = 1700000, .max = 3500000 },
278 .n = { .min = 3, .max = 6 },
279 .m = { .min = 2, .max = 256 },
280 .m1 = { .min = 0, .max = 0 },
281 .m2 = { .min = 0, .max = 254 },
282 .p = { .min = 7, .max = 112 },
283 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 284 .p2 = { .dot_limit = 112000,
285 .p2_slow = 14, .p2_fast = 14 },
6115707b 286 .find_pll = intel_find_best_PLL,
e4b36699
KP		 287};
288
273e27ca
EA		 289/* Ironlake / Sandybridge
290 *
291 * We calculate clock using (register_value + 2) for N/M1/M2, so here
292 * the range value for them is (actual_value - 2).
293 */
b91ad0ec 294static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 295 .dot = { .min = 25000, .max = 350000 },
296 .vco = { .min = 1760000, .max = 3510000 },
297 .n = { .min = 1, .max = 5 },
298 .m = { .min = 79, .max = 127 },
299 .m1 = { .min = 12, .max = 22 },
300 .m2 = { .min = 5, .max = 9 },
301 .p = { .min = 5, .max = 80 },
302 .p1 = { .min = 1, .max = 8 },
303 .p2 = { .dot_limit = 225000,
304 .p2_slow = 10, .p2_fast = 5 },
4547668a 305 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 306};
307
b91ad0ec 308static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 309 .dot = { .min = 25000, .max = 350000 },
310 .vco = { .min = 1760000, .max = 3510000 },
311 .n = { .min = 1, .max = 3 },
312 .m = { .min = 79, .max = 118 },
313 .m1 = { .min = 12, .max = 22 },
314 .m2 = { .min = 5, .max = 9 },
315 .p = { .min = 28, .max = 112 },
316 .p1 = { .min = 2, .max = 8 },
317 .p2 = { .dot_limit = 225000,
318 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 319 .find_pll = intel_g4x_find_best_PLL,
320};
321
322static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 323 .dot = { .min = 25000, .max = 350000 },
324 .vco = { .min = 1760000, .max = 3510000 },
325 .n = { .min = 1, .max = 3 },
326 .m = { .min = 79, .max = 127 },
327 .m1 = { .min = 12, .max = 22 },
328 .m2 = { .min = 5, .max = 9 },
329 .p = { .min = 14, .max = 56 },
330 .p1 = { .min = 2, .max = 8 },
331 .p2 = { .dot_limit = 225000,
332 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 333 .find_pll = intel_g4x_find_best_PLL,
334};
335
273e27ca 336/* LVDS 100mhz refclk limits. */
b91ad0ec 337static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 338 .dot = { .min = 25000, .max = 350000 },
339 .vco = { .min = 1760000, .max = 3510000 },
340 .n = { .min = 1, .max = 2 },
341 .m = { .min = 79, .max = 126 },
342 .m1 = { .min = 12, .max = 22 },
343 .m2 = { .min = 5, .max = 9 },
344 .p = { .min = 28, .max = 112 },
0206e353 345 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 346 .p2 = { .dot_limit = 225000,
347 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 348 .find_pll = intel_g4x_find_best_PLL,
349};
350
351static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 352 .dot = { .min = 25000, .max = 350000 },
353 .vco = { .min = 1760000, .max = 3510000 },
354 .n = { .min = 1, .max = 3 },
355 .m = { .min = 79, .max = 126 },
356 .m1 = { .min = 12, .max = 22 },
357 .m2 = { .min = 5, .max = 9 },
358 .p = { .min = 14, .max = 42 },
0206e353 359 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 360 .p2 = { .dot_limit = 225000,
361 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 362 .find_pll = intel_g4x_find_best_PLL,
363};
364
365static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 366 .dot = { .min = 25000, .max = 350000 },
367 .vco = { .min = 1760000, .max = 3510000},
368 .n = { .min = 1, .max = 2 },
369 .m = { .min = 81, .max = 90 },
370 .m1 = { .min = 12, .max = 22 },
371 .m2 = { .min = 5, .max = 9 },
372 .p = { .min = 10, .max = 20 },
373 .p1 = { .min = 1, .max = 2},
374 .p2 = { .dot_limit = 0,
273e27ca 375 .p2_slow = 10, .p2_fast = 10 },
0206e353 376 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 377};
378
a0c4da24
JB		 379static const intel_limit_t intel_limits_vlv_dac = {
380 .dot = { .min = 25000, .max = 270000 },
381 .vco = { .min = 4000000, .max = 6000000 },
382 .n = { .min = 1, .max = 7 },
383 .m = { .min = 22, .max = 450 }, /* guess */
384 .m1 = { .min = 2, .max = 3 },
385 .m2 = { .min = 11, .max = 156 },
386 .p = { .min = 10, .max = 30 },
75e53986 387 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 388 .p2 = { .dot_limit = 270000,
389 .p2_slow = 2, .p2_fast = 20 },
390 .find_pll = intel_vlv_find_best_pll,
391};
392
393static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 394 .dot = { .min = 25000, .max = 270000 },
395 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 396 .n = { .min = 1, .max = 7 },
397 .m = { .min = 60, .max = 300 }, /* guess */
398 .m1 = { .min = 2, .max = 3 },
399 .m2 = { .min = 11, .max = 156 },
400 .p = { .min = 10, .max = 30 },
401 .p1 = { .min = 2, .max = 3 },
402 .p2 = { .dot_limit = 270000,
403 .p2_slow = 2, .p2_fast = 20 },
404 .find_pll = intel_vlv_find_best_pll,
405};
406
407static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 408 .dot = { .min = 25000, .max = 270000 },
409 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 410 .n = { .min = 1, .max = 7 },
74a4dd2e 411 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 412 .m1 = { .min = 2, .max = 3 },
413 .m2 = { .min = 11, .max = 156 },
414 .p = { .min = 10, .max = 30 },
75e53986 415 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 416 .p2 = { .dot_limit = 270000,
417 .p2_slow = 2, .p2_fast = 20 },
418 .find_pll = intel_vlv_find_best_pll,
419};
420
57f350b6
JB		 421u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
422{
09153000 423 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 424
57f350b6
JB		 425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
09153000 427 return 0;
57f350b6
JB		 428 }
429
430 I915_WRITE(DPIO_REG, reg);
431 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
432 DPIO_BYTE);
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
09153000 435 return 0;
57f350b6 436 }
57f350b6 437
09153000 438 return I915_READ(DPIO_DATA);
57f350b6
JB		 439}
440
e2fa6fba 441void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
a0c4da24 442{
09153000 443 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 444
a0c4da24
JB		 445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO idle wait timed out\n");
09153000 447 return;
a0c4da24
JB		 448 }
449
450 I915_WRITE(DPIO_DATA, val);
451 I915_WRITE(DPIO_REG, reg);
452 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
453 DPIO_BYTE);
454 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
455 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 456}
457
1b894b59
CW		 458static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
459 int refclk)
2c07245f 460{
b91ad0ec 461 struct drm_device *dev = crtc->dev;
2c07245f 462 const intel_limit_t *limit;
b91ad0ec
ZW		 463
464 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 465 if (intel_is_dual_link_lvds(dev)) {
1b894b59 466 if (refclk == 100000)
b91ad0ec
ZW		 467 limit = &intel_limits_ironlake_dual_lvds_100m;
468 else
469 limit = &intel_limits_ironlake_dual_lvds;
470 } else {
1b894b59 471 if (refclk == 100000)
b91ad0ec
ZW		 472 limit = &intel_limits_ironlake_single_lvds_100m;
473 else
474 limit = &intel_limits_ironlake_single_lvds;
475 }
476 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 477 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 478 limit = &intel_limits_ironlake_display_port;
2c07245f 479 else
b91ad0ec 480 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 481
482 return limit;
483}
484
044c7c41
ML		 485static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
486{
487 struct drm_device *dev = crtc->dev;
044c7c41
ML		 488 const intel_limit_t *limit;
489
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 491 if (intel_is_dual_link_lvds(dev))
e4b36699 492 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 493 else
e4b36699 494 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 495 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
496 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 497 limit = &intel_limits_g4x_hdmi;
044c7c41 498 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 499 limit = &intel_limits_g4x_sdvo;
0206e353 500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 501 limit = &intel_limits_g4x_display_port;
044c7c41 502 } else /* The option is for other outputs */
e4b36699 503 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 504
505 return limit;
506}
507
1b894b59 508static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 509{
510 struct drm_device *dev = crtc->dev;
511 const intel_limit_t *limit;
512
bad720ff 513 if (HAS_PCH_SPLIT(dev))
1b894b59 514 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 515 else if (IS_G4X(dev)) {
044c7c41 516 limit = intel_g4x_limit(crtc);
f2b115e6 517 } else if (IS_PINEVIEW(dev)) {
2177832f 518 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 519 limit = &intel_limits_pineview_lvds;
2177832f 520 else
f2b115e6 521 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 522 } else if (IS_VALLEYVIEW(dev)) {
523 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
524 limit = &intel_limits_vlv_dac;
525 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
526 limit = &intel_limits_vlv_hdmi;
527 else
528 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 529 } else if (!IS_GEN2(dev)) {
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
531 limit = &intel_limits_i9xx_lvds;
532 else
533 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 534 } else {
535 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 536 limit = &intel_limits_i8xx_lvds;
79e53945 537 else
e4b36699 538 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 539 }
540 return limit;
541}
542
f2b115e6
AJ		 543/* m1 is reserved as 0 in Pineview, n is a ring counter */
544static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 545{
2177832f
SL		 546 clock->m = clock->m2 + 2;
547 clock->p = clock->p1 * clock->p2;
548 clock->vco = refclk * clock->m / clock->n;
549 clock->dot = clock->vco / clock->p;
550}
551
552static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
553{
f2b115e6
AJ		 554 if (IS_PINEVIEW(dev)) {
555 pineview_clock(refclk, clock);
2177832f
SL		 556 return;
557 }
79e53945
JB		 558 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
559 clock->p = clock->p1 * clock->p2;
560 clock->vco = refclk * clock->m / (clock->n + 2);
561 clock->dot = clock->vco / clock->p;
562}
563
79e53945
JB		 564/**
565 * Returns whether any output on the specified pipe is of the specified type
566 */
4ef69c7a 567bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 568{
4ef69c7a 569 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 570 struct intel_encoder *encoder;
571
6c2b7c12
DV		 572 for_each_encoder_on_crtc(dev, crtc, encoder)
573 if (encoder->type == type)
4ef69c7a
CW		 574 return true;
575
576 return false;
79e53945
JB		 577}
578
7c04d1d9 579#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 580/**
581 * Returns whether the given set of divisors are valid for a given refclk with
582 * the given connectors.
583 */
584
1b894b59
CW		 585static bool intel_PLL_is_valid(struct drm_device *dev,
586 const intel_limit_t *limit,
587 const intel_clock_t *clock)
79e53945 588{
79e53945 589 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 590 INTELPllInvalid("p1 out of range\n");
79e53945 591 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 592 INTELPllInvalid("p out of range\n");
79e53945 593 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 594 INTELPllInvalid("m2 out of range\n");
79e53945 595 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 596 INTELPllInvalid("m1 out of range\n");
f2b115e6 597 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 598 INTELPllInvalid("m1 <= m2\n");
79e53945 599 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 600 INTELPllInvalid("m out of range\n");
79e53945 601 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 602 INTELPllInvalid("n out of range\n");
79e53945 603 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 604 INTELPllInvalid("vco out of range\n");
79e53945
JB		 605 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
606 * connector, etc., rather than just a single range.
607 */
608 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 609 INTELPllInvalid("dot out of range\n");
79e53945
JB		 610
611 return true;
612}
613
d4906093
ML		 614static bool
615intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 616 int target, int refclk, intel_clock_t *match_clock,
617 intel_clock_t *best_clock)
d4906093 618
79e53945
JB		 619{
620 struct drm_device *dev = crtc->dev;
79e53945 621 intel_clock_t clock;
79e53945
JB		 622 int err = target;
623
a210b028 624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 625 /*
a210b028
DV		 626 * For LVDS just rely on its current settings for dual-channel.
627 * We haven't figured out how to reliably set up different
628 * single/dual channel state, if we even can.
79e53945 629 */
1974cad0 630 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 631 clock.p2 = limit->p2.p2_fast;
632 else
633 clock.p2 = limit->p2.p2_slow;
634 } else {
635 if (target < limit->p2.dot_limit)
636 clock.p2 = limit->p2.p2_slow;
637 else
638 clock.p2 = limit->p2.p2_fast;
639 }
640
0206e353 641 memset(best_clock, 0, sizeof(*best_clock));
79e53945 642
42158660
ZY		 643 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
644 clock.m1++) {
645 for (clock.m2 = limit->m2.min;
646 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 647 /* m1 is always 0 in Pineview */
648 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 649 break;
650 for (clock.n = limit->n.min;
651 clock.n <= limit->n.max; clock.n++) {
652 for (clock.p1 = limit->p1.min;
653 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 654 int this_err;
655
2177832f 656 intel_clock(dev, refclk, &clock);
1b894b59
CW		 657 if (!intel_PLL_is_valid(dev, limit,
658 &clock))
79e53945 659 continue;
cec2f356
SP		 660 if (match_clock &&
661 clock.p != match_clock->p)
662 continue;
79e53945
JB		 663
664 this_err = abs(clock.dot - target);
665 if (this_err < err) {
666 *best_clock = clock;
667 err = this_err;
668 }
669 }
670 }
671 }
672 }
673
674 return (err != target);
675}
676
d4906093
ML		 677static bool
678intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 679 int target, int refclk, intel_clock_t *match_clock,
680 intel_clock_t *best_clock)
d4906093
ML		 681{
682 struct drm_device *dev = crtc->dev;
d4906093
ML		 683 intel_clock_t clock;
684 int max_n;
685 bool found;
6ba770dc
AJ		 686 /* approximately equals target * 0.00585 */
687 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 688 found = false;
689
690 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 691 int lvds_reg;
692
c619eed4 693 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 694 lvds_reg = PCH_LVDS;
695 else
696 lvds_reg = LVDS;
1974cad0 697 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 698 clock.p2 = limit->p2.p2_fast;
699 else
700 clock.p2 = limit->p2.p2_slow;
701 } else {
702 if (target < limit->p2.dot_limit)
703 clock.p2 = limit->p2.p2_slow;
704 else
705 clock.p2 = limit->p2.p2_fast;
706 }
707
708 memset(best_clock, 0, sizeof(*best_clock));
709 max_n = limit->n.max;
f77f13e2 710 /* based on hardware requirement, prefer smaller n to precision */
d4906093 711 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 712 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 713 for (clock.m1 = limit->m1.max;
714 clock.m1 >= limit->m1.min; clock.m1--) {
715 for (clock.m2 = limit->m2.max;
716 clock.m2 >= limit->m2.min; clock.m2--) {
717 for (clock.p1 = limit->p1.max;
718 clock.p1 >= limit->p1.min; clock.p1--) {
719 int this_err;
720
2177832f 721 intel_clock(dev, refclk, &clock);
1b894b59
CW		 722 if (!intel_PLL_is_valid(dev, limit,
723 &clock))
d4906093 724 continue;
cec2f356
SP		 725 if (match_clock &&
726 clock.p != match_clock->p)
727 continue;
1b894b59
CW		 728
729 this_err = abs(clock.dot - target);
d4906093
ML		 730 if (this_err < err_most) {
731 *best_clock = clock;
732 err_most = this_err;
733 max_n = clock.n;
734 found = true;
735 }
736 }
737 }
738 }
739 }
2c07245f
ZW		 740 return found;
741}
742
5eb08b69 743static bool
f2b115e6 744intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 745 int target, int refclk, intel_clock_t *match_clock,
746 intel_clock_t *best_clock)
5eb08b69
ZW		 747{
748 struct drm_device *dev = crtc->dev;
749 intel_clock_t clock;
4547668a 750
5eb08b69
ZW		 751 if (target < 200000) {
752 clock.n = 1;
753 clock.p1 = 2;
754 clock.p2 = 10;
755 clock.m1 = 12;
756 clock.m2 = 9;
757 } else {
758 clock.n = 2;
759 clock.p1 = 1;
760 clock.p2 = 10;
761 clock.m1 = 14;
762 clock.m2 = 8;
763 }
764 intel_clock(dev, refclk, &clock);
765 memcpy(best_clock, &clock, sizeof(intel_clock_t));
766 return true;
767}
768
a4fc5ed6
KP		 769/* DisplayPort has only two frequencies, 162MHz and 270MHz */
770static bool
771intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 772 int target, int refclk, intel_clock_t *match_clock,
773 intel_clock_t *best_clock)
a4fc5ed6 774{
5eddb70b
CW		 775 intel_clock_t clock;
776 if (target < 200000) {
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.n = 2;
780 clock.m1 = 23;
781 clock.m2 = 8;
782 } else {
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.n = 1;
786 clock.m1 = 14;
787 clock.m2 = 2;
788 }
789 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
790 clock.p = (clock.p1 * clock.p2);
791 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
792 clock.vco = 0;
793 memcpy(best_clock, &clock, sizeof(intel_clock_t));
794 return true;
a4fc5ed6 795}
a0c4da24
JB		 796static bool
797intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
798 int target, int refclk, intel_clock_t *match_clock,
799 intel_clock_t *best_clock)
800{
801 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
802 u32 m, n, fastclk;
803 u32 updrate, minupdate, fracbits, p;
804 unsigned long bestppm, ppm, absppm;
805 int dotclk, flag;
806
af447bd3 807 flag = 0;
a0c4da24
JB		 808 dotclk = target * 1000;
809 bestppm = 1000000;
810 ppm = absppm = 0;
811 fastclk = dotclk / (2*100);
812 updrate = 0;
813 minupdate = 19200;
814 fracbits = 1;
815 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
816 bestm1 = bestm2 = bestp1 = bestp2 = 0;
817
818 /* based on hardware requirement, prefer smaller n to precision */
819 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
820 updrate = refclk / n;
821 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
822 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
823 if (p2 > 10)
824 p2 = p2 - 1;
825 p = p1 * p2;
826 /* based on hardware requirement, prefer bigger m1,m2 values */
827 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
828 m2 = (((2*(fastclk * p * n / m1 )) +
829 refclk) / (2*refclk));
830 m = m1 * m2;
831 vco = updrate * m;
832 if (vco >= limit->vco.min && vco < limit->vco.max) {
833 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
834 absppm = (ppm > 0) ? ppm : (-ppm);
835 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
836 bestppm = 0;
837 flag = 1;
838 }
839 if (absppm < bestppm - 10) {
840 bestppm = absppm;
841 flag = 1;
842 }
843 if (flag) {
844 bestn = n;
845 bestm1 = m1;
846 bestm2 = m2;
847 bestp1 = p1;
848 bestp2 = p2;
849 flag = 0;
850 }
851 }
852 }
853 }
854 }
855 }
856 best_clock->n = bestn;
857 best_clock->m1 = bestm1;
858 best_clock->m2 = bestm2;
859 best_clock->p1 = bestp1;
860 best_clock->p2 = bestp2;
861
862 return true;
863}
a4fc5ed6 864
a5c961d1
PZ		 865enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
866 enum pipe pipe)
867{
868 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
870
3b117c8f 871 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 872}
873
a928d536
PZ		 874static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
875{
876 struct drm_i915_private *dev_priv = dev->dev_private;
877 u32 frame, frame_reg = PIPEFRAME(pipe);
878
879 frame = I915_READ(frame_reg);
880
881 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
882 DRM_DEBUG_KMS("vblank wait timed out\n");
883}
884
9d0498a2
JB		 885/**
886 * intel_wait_for_vblank - wait for vblank on a given pipe
887 * @dev: drm device
888 * @pipe: pipe to wait for
889 *
890 * Wait for vblank to occur on a given pipe. Needed for various bits of
891 * mode setting code.
892 */
893void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 894{
9d0498a2 895 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 896 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 897
a928d536
PZ		 898 if (INTEL_INFO(dev)->gen >= 5) {
899 ironlake_wait_for_vblank(dev, pipe);
900 return;
901 }
902
300387c0
CW		 903 /* Clear existing vblank status. Note this will clear any other
904 * sticky status fields as well.
905 *
906 * This races with i915_driver_irq_handler() with the result
907 * that either function could miss a vblank event. Here it is not
908 * fatal, as we will either wait upon the next vblank interrupt or
909 * timeout. Generally speaking intel_wait_for_vblank() is only
910 * called during modeset at which time the GPU should be idle and
911 * should *not* be performing page flips and thus not waiting on
912 * vblanks...
913 * Currently, the result of us stealing a vblank from the irq
914 * handler is that a single frame will be skipped during swapbuffers.
915 */
916 I915_WRITE(pipestat_reg,
917 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
918
9d0498a2 919 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 920 if (wait_for(I915_READ(pipestat_reg) &
921 PIPE_VBLANK_INTERRUPT_STATUS,
922 50))
9d0498a2
JB		 923 DRM_DEBUG_KMS("vblank wait timed out\n");
924}
925
ab7ad7f6
KP		 926/*
927 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 928 * @dev: drm device
929 * @pipe: pipe to wait for
930 *
931 * After disabling a pipe, we can't wait for vblank in the usual way,
932 * spinning on the vblank interrupt status bit, since we won't actually
933 * see an interrupt when the pipe is disabled.
934 *
ab7ad7f6
KP		 935 * On Gen4 and above:
936 * wait for the pipe register state bit to turn off
937 *
938 * Otherwise:
939 * wait for the display line value to settle (it usually
940 * ends up stopping at the start of the next frame).
58e10eb9 941 *
9d0498a2 942 */
58e10eb9 943void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 944{
945 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 946 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
947 pipe);
ab7ad7f6
KP		 948
949 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 950 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 951
952 /* Wait for the Pipe State to go off */
58e10eb9
CW		 953 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
954 100))
284637d9 955 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 956 } else {
837ba00f 957 u32 last_line, line_mask;
58e10eb9 958 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 959 unsigned long timeout = jiffies + msecs_to_jiffies(100);
960
837ba00f
PZ		 961 if (IS_GEN2(dev))
962 line_mask = DSL_LINEMASK_GEN2;
963 else
964 line_mask = DSL_LINEMASK_GEN3;
965
ab7ad7f6
KP		 966 /* Wait for the display line to settle */
967 do {
837ba00f 968 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 969 mdelay(5);
837ba00f 970 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 971 time_after(timeout, jiffies));
972 if (time_after(jiffies, timeout))
284637d9 973 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 974 }
79e53945
JB		 975}
976
b0ea7d37
DL		 977/*
978 * ibx_digital_port_connected - is the specified port connected?
979 * @dev_priv: i915 private structure
980 * @port: the port to test
981 *
982 * Returns true if @port is connected, false otherwise.
983 */
984bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
985 struct intel_digital_port *port)
986{
987 u32 bit;
988
c36346e3
DL		 989 if (HAS_PCH_IBX(dev_priv->dev)) {
990 switch(port->port) {
991 case PORT_B:
992 bit = SDE_PORTB_HOTPLUG;
993 break;
994 case PORT_C:
995 bit = SDE_PORTC_HOTPLUG;
996 break;
997 case PORT_D:
998 bit = SDE_PORTD_HOTPLUG;
999 break;
1000 default:
1001 return true;
1002 }
1003 } else {
1004 switch(port->port) {
1005 case PORT_B:
1006 bit = SDE_PORTB_HOTPLUG_CPT;
1007 break;
1008 case PORT_C:
1009 bit = SDE_PORTC_HOTPLUG_CPT;
1010 break;
1011 case PORT_D:
1012 bit = SDE_PORTD_HOTPLUG_CPT;
1013 break;
1014 default:
1015 return true;
1016 }
b0ea7d37
DL		 1017 }
1018
1019 return I915_READ(SDEISR) & bit;
1020}
1021
b24e7179
JB		 1022static const char *state_string(bool enabled)
1023{
1024 return enabled ? "on" : "off";
1025}
1026
1027/* Only for pre-ILK configs */
1028static void assert_pll(struct drm_i915_private *dev_priv,
1029 enum pipe pipe, bool state)
1030{
1031 int reg;
1032 u32 val;
1033 bool cur_state;
1034
1035 reg = DPLL(pipe);
1036 val = I915_READ(reg);
1037 cur_state = !!(val & DPLL_VCO_ENABLE);
1038 WARN(cur_state != state,
1039 "PLL state assertion failure (expected %s, current %s)\n",
1040 state_string(state), state_string(cur_state));
1041}
1042#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1043#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1044
040484af
JB		 1045/* For ILK+ */
1046static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1047 struct intel_pch_pll *pll,
1048 struct intel_crtc *crtc,
1049 bool state)
040484af 1050{
040484af
JB		 1051 u32 val;
1052 bool cur_state;
1053
9d82aa17
ED		 1054 if (HAS_PCH_LPT(dev_priv->dev)) {
1055 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1056 return;
1057 }
1058
92b27b08
CW		 1059 if (WARN (!pll,
1060 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1061 return;
ee7b9f93 1062
92b27b08
CW		 1063 val = I915_READ(pll->pll_reg);
1064 cur_state = !!(val & DPLL_VCO_ENABLE);
1065 WARN(cur_state != state,
1066 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1067 pll->pll_reg, state_string(state), state_string(cur_state), val);
1068
1069 /* Make sure the selected PLL is correctly attached to the transcoder */
1070 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1071 u32 pch_dpll;
1072
1073 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1074 cur_state = pll->pll_reg == _PCH_DPLL_B;
1075 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 1076 "PLL[%d] not attached to this transcoder %c: %08x\n",
1077 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 1078 cur_state = !!(val >> (4*crtc->pipe + 3));
1079 WARN(cur_state != state,
4bb6f1f3 1080 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 1081 pll->pll_reg == _PCH_DPLL_B,
1082 state_string(state),
4bb6f1f3 1083 pipe_name(crtc->pipe),
92b27b08
CW		 1084 val);
1085 }
d3ccbe86 1086 }
040484af 1087}
92b27b08
CW		 1088#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1089#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1090
1091static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1092 enum pipe pipe, bool state)
1093{
1094 int reg;
1095 u32 val;
1096 bool cur_state;
ad80a810
PZ		 1097 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1098 pipe);
040484af 1099
affa9354
PZ		 1100 if (HAS_DDI(dev_priv->dev)) {
1101 /* DDI does not have a specific FDI_TX register */
ad80a810 1102 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1103 val = I915_READ(reg);
ad80a810 1104 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1105 } else {
1106 reg = FDI_TX_CTL(pipe);
1107 val = I915_READ(reg);
1108 cur_state = !!(val & FDI_TX_ENABLE);
1109 }
040484af
JB		 1110 WARN(cur_state != state,
1111 "FDI TX state assertion failure (expected %s, current %s)\n",
1112 state_string(state), state_string(cur_state));
1113}
1114#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1115#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1116
1117static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1118 enum pipe pipe, bool state)
1119{
1120 int reg;
1121 u32 val;
1122 bool cur_state;
1123
d63fa0dc
PZ		 1124 reg = FDI_RX_CTL(pipe);
1125 val = I915_READ(reg);
1126 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1127 WARN(cur_state != state,
1128 "FDI RX state assertion failure (expected %s, current %s)\n",
1129 state_string(state), state_string(cur_state));
1130}
1131#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1132#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1133
1134static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1135 enum pipe pipe)
1136{
1137 int reg;
1138 u32 val;
1139
1140 /* ILK FDI PLL is always enabled */
1141 if (dev_priv->info->gen == 5)
1142 return;
1143
bf507ef7 1144 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1145 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1146 return;
1147
040484af
JB		 1148 reg = FDI_TX_CTL(pipe);
1149 val = I915_READ(reg);
1150 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1151}
1152
1153static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1154 enum pipe pipe)
1155{
1156 int reg;
1157 u32 val;
1158
1159 reg = FDI_RX_CTL(pipe);
1160 val = I915_READ(reg);
1161 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1162}
1163
ea0760cf
JB		 1164static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1165 enum pipe pipe)
1166{
1167 int pp_reg, lvds_reg;
1168 u32 val;
1169 enum pipe panel_pipe = PIPE_A;
0de3b485 1170 bool locked = true;
ea0760cf
JB		 1171
1172 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1173 pp_reg = PCH_PP_CONTROL;
1174 lvds_reg = PCH_LVDS;
1175 } else {
1176 pp_reg = PP_CONTROL;
1177 lvds_reg = LVDS;
1178 }
1179
1180 val = I915_READ(pp_reg);
1181 if (!(val & PANEL_POWER_ON) ||
1182 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1183 locked = false;
1184
1185 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1186 panel_pipe = PIPE_B;
1187
1188 WARN(panel_pipe == pipe && locked,
1189 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1190 pipe_name(pipe));
ea0760cf
JB		 1191}
1192
b840d907
JB		 1193void assert_pipe(struct drm_i915_private *dev_priv,
1194 enum pipe pipe, bool state)
b24e7179
JB		 1195{
1196 int reg;
1197 u32 val;
63d7bbe9 1198 bool cur_state;
702e7a56
PZ		 1199 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1200 pipe);
b24e7179 1201
8e636784
DV		 1202 /* if we need the pipe A quirk it must be always on */
1203 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1204 state = true;
1205
15d199ea
PZ		 1206 if (!intel_using_power_well(dev_priv->dev) &&
1207 cpu_transcoder != TRANSCODER_EDP) {
69310161
PZ		 1208 cur_state = false;
1209 } else {
1210 reg = PIPECONF(cpu_transcoder);
1211 val = I915_READ(reg);
1212 cur_state = !!(val & PIPECONF_ENABLE);
1213 }
1214
63d7bbe9
JB		 1215 WARN(cur_state != state,
1216 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1217 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1218}
1219
931872fc
CW		 1220static void assert_plane(struct drm_i915_private *dev_priv,
1221 enum plane plane, bool state)
b24e7179
JB		 1222{
1223 int reg;
1224 u32 val;
931872fc 1225 bool cur_state;
b24e7179
JB		 1226
1227 reg = DSPCNTR(plane);
1228 val = I915_READ(reg);
931872fc
CW		 1229 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1230 WARN(cur_state != state,
1231 "plane %c assertion failure (expected %s, current %s)\n",
1232 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1233}
1234
931872fc
CW		 1235#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1236#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1237
b24e7179
JB		 1238static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1239 enum pipe pipe)
1240{
1241 int reg, i;
1242 u32 val;
1243 int cur_pipe;
1244
19ec1358 1245 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1246 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1247 reg = DSPCNTR(pipe);
1248 val = I915_READ(reg);
1249 WARN((val & DISPLAY_PLANE_ENABLE),
1250 "plane %c assertion failure, should be disabled but not\n",
1251 plane_name(pipe));
19ec1358 1252 return;
28c05794 1253 }
19ec1358 1254
b24e7179
JB		 1255 /* Need to check both planes against the pipe */
1256 for (i = 0; i < 2; i++) {
1257 reg = DSPCNTR(i);
1258 val = I915_READ(reg);
1259 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1260 DISPPLANE_SEL_PIPE_SHIFT;
1261 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1262 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1263 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1264 }
1265}
1266
19332d7a
JB		 1267static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1268 enum pipe pipe)
1269{
1270 int reg, i;
1271 u32 val;
1272
1273 if (!IS_VALLEYVIEW(dev_priv->dev))
1274 return;
1275
1276 /* Need to check both planes against the pipe */
1277 for (i = 0; i < dev_priv->num_plane; i++) {
1278 reg = SPCNTR(pipe, i);
1279 val = I915_READ(reg);
1280 WARN((val & SP_ENABLE),
06da8da2
VS		 1281 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1282 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1283 }
1284}
1285
92f2584a
JB		 1286static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1287{
1288 u32 val;
1289 bool enabled;
1290
9d82aa17
ED		 1291 if (HAS_PCH_LPT(dev_priv->dev)) {
1292 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1293 return;
1294 }
1295
92f2584a
JB		 1296 val = I915_READ(PCH_DREF_CONTROL);
1297 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1298 DREF_SUPERSPREAD_SOURCE_MASK));
1299 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1300}
1301
1302static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1303 enum pipe pipe)
1304{
1305 int reg;
1306 u32 val;
1307 bool enabled;
1308
1309 reg = TRANSCONF(pipe);
1310 val = I915_READ(reg);
1311 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1312 WARN(enabled,
1313 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1314 pipe_name(pipe));
92f2584a
JB		 1315}
1316
4e634389
KP		 1317static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1319{
1320 if ((val & DP_PORT_EN) == 0)
1321 return false;
1322
1323 if (HAS_PCH_CPT(dev_priv->dev)) {
1324 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1325 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1326 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1327 return false;
1328 } else {
1329 if ((val & DP_PIPE_MASK) != (pipe << 30))
1330 return false;
1331 }
1332 return true;
1333}
1334
1519b995
KP		 1335static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1336 enum pipe pipe, u32 val)
1337{
dc0fa718 1338 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1339 return false;
1340
1341 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1342 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1343 return false;
1344 } else {
dc0fa718 1345 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1346 return false;
1347 }
1348 return true;
1349}
1350
1351static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1352 enum pipe pipe, u32 val)
1353{
1354 if ((val & LVDS_PORT_EN) == 0)
1355 return false;
1356
1357 if (HAS_PCH_CPT(dev_priv->dev)) {
1358 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1359 return false;
1360 } else {
1361 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1362 return false;
1363 }
1364 return true;
1365}
1366
1367static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe, u32 val)
1369{
1370 if ((val & ADPA_DAC_ENABLE) == 0)
1371 return false;
1372 if (HAS_PCH_CPT(dev_priv->dev)) {
1373 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1374 return false;
1375 } else {
1376 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1377 return false;
1378 }
1379 return true;
1380}
1381
291906f1 1382static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1383 enum pipe pipe, int reg, u32 port_sel)
291906f1 1384{
47a05eca 1385 u32 val = I915_READ(reg);
4e634389 1386 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1387 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1388 reg, pipe_name(pipe));
de9a35ab 1389
75c5da27
DV		 1390 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1391 && (val & DP_PIPEB_SELECT),
de9a35ab 1392 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1393}
1394
1395static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe, int reg)
1397{
47a05eca 1398 u32 val = I915_READ(reg);
b70ad586 1399 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1400 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1401 reg, pipe_name(pipe));
de9a35ab 1402
dc0fa718 1403 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1404 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1405 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1406}
1407
1408static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1409 enum pipe pipe)
1410{
1411 int reg;
1412 u32 val;
291906f1 1413
f0575e92
KP		 1414 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1415 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1416 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1417
1418 reg = PCH_ADPA;
1419 val = I915_READ(reg);
b70ad586 1420 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1421 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1422 pipe_name(pipe));
291906f1
JB		 1423
1424 reg = PCH_LVDS;
1425 val = I915_READ(reg);
b70ad586 1426 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1427 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1428 pipe_name(pipe));
291906f1 1429
e2debe91
PZ		 1430 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1431 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1432 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1433}
1434
63d7bbe9
JB		 1435/**
1436 * intel_enable_pll - enable a PLL
1437 * @dev_priv: i915 private structure
1438 * @pipe: pipe PLL to enable
1439 *
1440 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1441 * make sure the PLL reg is writable first though, since the panel write
1442 * protect mechanism may be enabled.
1443 *
1444 * Note! This is for pre-ILK only.
7434a255
TR		 1445 *
1446 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1447 */
1448static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1449{
1450 int reg;
1451 u32 val;
1452
58c6eaa2
DV		 1453 assert_pipe_disabled(dev_priv, pipe);
1454
63d7bbe9 1455 /* No really, not for ILK+ */
a0c4da24 1456 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1457
1458 /* PLL is protected by panel, make sure we can write it */
1459 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1460 assert_panel_unlocked(dev_priv, pipe);
1461
1462 reg = DPLL(pipe);
1463 val = I915_READ(reg);
1464 val |= DPLL_VCO_ENABLE;
1465
1466 /* We do this three times for luck */
1467 I915_WRITE(reg, val);
1468 POSTING_READ(reg);
1469 udelay(150); /* wait for warmup */
1470 I915_WRITE(reg, val);
1471 POSTING_READ(reg);
1472 udelay(150); /* wait for warmup */
1473 I915_WRITE(reg, val);
1474 POSTING_READ(reg);
1475 udelay(150); /* wait for warmup */
1476}
1477
1478/**
1479 * intel_disable_pll - disable a PLL
1480 * @dev_priv: i915 private structure
1481 * @pipe: pipe PLL to disable
1482 *
1483 * Disable the PLL for @pipe, making sure the pipe is off first.
1484 *
1485 * Note! This is for pre-ILK only.
1486 */
1487static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1488{
1489 int reg;
1490 u32 val;
1491
1492 /* Don't disable pipe A or pipe A PLLs if needed */
1493 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1494 return;
1495
1496 /* Make sure the pipe isn't still relying on us */
1497 assert_pipe_disabled(dev_priv, pipe);
1498
1499 reg = DPLL(pipe);
1500 val = I915_READ(reg);
1501 val &= ~DPLL_VCO_ENABLE;
1502 I915_WRITE(reg, val);
1503 POSTING_READ(reg);
1504}
1505
a416edef
ED		 1506/* SBI access */
1507static void
988d6ee8
PZ		 1508intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1509 enum intel_sbi_destination destination)
a416edef 1510{
988d6ee8 1511 u32 tmp;
a416edef 1512
09153000 1513 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1514
39fb50f6 1515 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1516 100)) {
1517 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1518 return;
a416edef
ED		 1519 }
1520
988d6ee8
PZ		 1521 I915_WRITE(SBI_ADDR, (reg << 16));
1522 I915_WRITE(SBI_DATA, value);
1523
1524 if (destination == SBI_ICLK)
1525 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1526 else
1527 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1528 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1529
39fb50f6 1530 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1531 100)) {
1532 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1533 return;
a416edef 1534 }
a416edef
ED		 1535}
1536
1537static u32
988d6ee8
PZ		 1538intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1539 enum intel_sbi_destination destination)
a416edef 1540{
39fb50f6 1541 u32 value = 0;
09153000 1542 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1543
39fb50f6 1544 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1545 100)) {
1546 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1547 return 0;
a416edef
ED		 1548 }
1549
988d6ee8
PZ		 1550 I915_WRITE(SBI_ADDR, (reg << 16));
1551
1552 if (destination == SBI_ICLK)
1553 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1554 else
1555 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1556 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1557
39fb50f6 1558 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1559 100)) {
1560 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1561 return 0;
a416edef
ED		 1562 }
1563
09153000 1564 return I915_READ(SBI_DATA);
a416edef
ED		 1565}
1566
89b667f8
JB		 1567void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1568{
1569 u32 port_mask;
1570
1571 if (!port)
1572 port_mask = DPLL_PORTB_READY_MASK;
1573 else
1574 port_mask = DPLL_PORTC_READY_MASK;
1575
1576 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1577 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1578 'B' + port, I915_READ(DPLL(0)));
1579}
1580
92f2584a 1581/**
b6b4e185 1582 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1585 *
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1588 */
b6b4e185 1589static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1590{
ee7b9f93 1591 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1592 struct intel_pch_pll *pll;
92f2584a
JB		 1593 int reg;
1594 u32 val;
1595
48da64a8 1596 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1597 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1598 pll = intel_crtc->pch_pll;
1599 if (pll == NULL)
1600 return;
1601
1602 if (WARN_ON(pll->refcount == 0))
1603 return;
ee7b9f93
JB		 1604
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll->pll_reg, pll->active, pll->on,
1607 intel_crtc->base.base.id);
92f2584a
JB		 1608
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv);
1611
ee7b9f93 1612 if (pll->active++ && pll->on) {
92b27b08 1613 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1614 return;
1615 }
1616
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619 reg = pll->pll_reg;
92f2584a
JB		 1620 val = I915_READ(reg);
1621 val |= DPLL_VCO_ENABLE;
1622 I915_WRITE(reg, val);
1623 POSTING_READ(reg);
1624 udelay(200);
ee7b9f93
JB		 1625
1626 pll->on = true;
92f2584a
JB		 1627}
1628
ee7b9f93 1629static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1630{
ee7b9f93
JB		 1631 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1633 int reg;
ee7b9f93 1634 u32 val;
4c609cb8 1635
92f2584a
JB		 1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1638 if (pll == NULL)
1639 return;
92f2584a 1640
48da64a8
CW		 1641 if (WARN_ON(pll->refcount == 0))
1642 return;
7a419866 1643
ee7b9f93
JB		 1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll->pll_reg, pll->active, pll->on,
1646 intel_crtc->base.base.id);
7a419866 1647
48da64a8 1648 if (WARN_ON(pll->active == 0)) {
92b27b08 1649 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1650 return;
1651 }
1652
ee7b9f93 1653 if (--pll->active) {
92b27b08 1654 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1655 return;
ee7b9f93
JB		 1656 }
1657
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1662
ee7b9f93 1663 reg = pll->pll_reg;
92f2584a
JB		 1664 val = I915_READ(reg);
1665 val &= ~DPLL_VCO_ENABLE;
1666 I915_WRITE(reg, val);
1667 POSTING_READ(reg);
1668 udelay(200);
ee7b9f93
JB		 1669
1670 pll->on = false;
92f2584a
JB		 1671}
1672
b8a4f404
PZ		 1673static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1674 enum pipe pipe)
040484af 1675{
23670b32 1676 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1677 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1678 uint32_t reg, val, pipeconf_val;
040484af
JB		 1679
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv->info->gen < 5);
1682
1683 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1684 assert_pch_pll_enabled(dev_priv,
1685 to_intel_crtc(crtc)->pch_pll,
1686 to_intel_crtc(crtc));
040484af
JB		 1687
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv, pipe);
1690 assert_fdi_rx_enabled(dev_priv, pipe);
1691
23670b32
DV		 1692 if (HAS_PCH_CPT(dev)) {
1693 /* Workaround: Set the timing override bit before enabling the
1694 * pch transcoder. */
1695 reg = TRANS_CHICKEN2(pipe);
1696 val = I915_READ(reg);
1697 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1698 I915_WRITE(reg, val);
59c859d6 1699 }
23670b32 1700
040484af
JB		 1701 reg = TRANSCONF(pipe);
1702 val = I915_READ(reg);
5f7f726d 1703 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1704
1705 if (HAS_PCH_IBX(dev_priv->dev)) {
1706 /*
1707 * make the BPC in transcoder be consistent with
1708 * that in pipeconf reg.
1709 */
dfd07d72
DV		 1710 val &= ~PIPECONF_BPC_MASK;
1711 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1712 }
5f7f726d
PZ		 1713
1714 val &= ~TRANS_INTERLACE_MASK;
1715 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1716 if (HAS_PCH_IBX(dev_priv->dev) &&
1717 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1718 val |= TRANS_LEGACY_INTERLACED_ILK;
1719 else
1720 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1721 else
1722 val |= TRANS_PROGRESSIVE;
1723
040484af
JB		 1724 I915_WRITE(reg, val | TRANS_ENABLE);
1725 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1726 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1727}
1728
8fb033d7 1729static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1730 enum transcoder cpu_transcoder)
040484af 1731{
8fb033d7 1732 u32 val, pipeconf_val;
8fb033d7
PZ		 1733
1734 /* PCH only available on ILK+ */
1735 BUG_ON(dev_priv->info->gen < 5);
1736
8fb033d7 1737 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1738 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1739 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1740
223a6fdf
PZ		 1741 /* Workaround: set timing override bit. */
1742 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1743 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1744 I915_WRITE(_TRANSA_CHICKEN2, val);
1745
25f3ef11 1746 val = TRANS_ENABLE;
937bb610 1747 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1748
9a76b1c6
PZ		 1749 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1750 PIPECONF_INTERLACED_ILK)
a35f2679 1751 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1752 else
1753 val |= TRANS_PROGRESSIVE;
1754
25f3ef11 1755 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1756 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1757 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1758}
1759
b8a4f404
PZ		 1760static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1761 enum pipe pipe)
040484af 1762{
23670b32
DV		 1763 struct drm_device *dev = dev_priv->dev;
1764 uint32_t reg, val;
040484af
JB		 1765
1766 /* FDI relies on the transcoder */
1767 assert_fdi_tx_disabled(dev_priv, pipe);
1768 assert_fdi_rx_disabled(dev_priv, pipe);
1769
291906f1
JB		 1770 /* Ports must be off as well */
1771 assert_pch_ports_disabled(dev_priv, pipe);
1772
040484af
JB		 1773 reg = TRANSCONF(pipe);
1774 val = I915_READ(reg);
1775 val &= ~TRANS_ENABLE;
1776 I915_WRITE(reg, val);
1777 /* wait for PCH transcoder off, transcoder state */
1778 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1779 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1780
1781 if (!HAS_PCH_IBX(dev)) {
1782 /* Workaround: Clear the timing override chicken bit again. */
1783 reg = TRANS_CHICKEN2(pipe);
1784 val = I915_READ(reg);
1785 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1786 I915_WRITE(reg, val);
1787 }
040484af
JB		 1788}
1789
ab4d966c 1790static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1791{
8fb033d7
PZ		 1792 u32 val;
1793
8a52fd9f 1794 val = I915_READ(_TRANSACONF);
8fb033d7 1795 val &= ~TRANS_ENABLE;
8a52fd9f 1796 I915_WRITE(_TRANSACONF, val);
8fb033d7 1797 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1798 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1799 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1800
1801 /* Workaround: clear timing override bit. */
1802 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1803 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1804 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1805}
1806
b24e7179 1807/**
309cfea8 1808 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1809 * @dev_priv: i915 private structure
1810 * @pipe: pipe to enable
040484af 1811 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1812 *
1813 * Enable @pipe, making sure that various hardware specific requirements
1814 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1815 *
1816 * @pipe should be %PIPE_A or %PIPE_B.
1817 *
1818 * Will wait until the pipe is actually running (i.e. first vblank) before
1819 * returning.
1820 */
040484af
JB		 1821static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1822 bool pch_port)
b24e7179 1823{
702e7a56
PZ		 1824 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1825 pipe);
1a240d4d 1826 enum pipe pch_transcoder;
b24e7179
JB		 1827 int reg;
1828 u32 val;
1829
58c6eaa2
DV		 1830 assert_planes_disabled(dev_priv, pipe);
1831 assert_sprites_disabled(dev_priv, pipe);
1832
681e5811 1833 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1834 pch_transcoder = TRANSCODER_A;
1835 else
1836 pch_transcoder = pipe;
1837
b24e7179
JB		 1838 /*
1839 * A pipe without a PLL won't actually be able to drive bits from
1840 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1841 * need the check.
1842 */
1843 if (!HAS_PCH_SPLIT(dev_priv->dev))
1844 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1845 else {
1846 if (pch_port) {
1847 /* if driving the PCH, we need FDI enabled */
cc391bbb 1848 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1849 assert_fdi_tx_pll_enabled(dev_priv,
1850 (enum pipe) cpu_transcoder);
040484af
JB		 1851 }
1852 /* FIXME: assert CPU port conditions for SNB+ */
1853 }
b24e7179 1854
702e7a56 1855 reg = PIPECONF(cpu_transcoder);
b24e7179 1856 val = I915_READ(reg);
00d70b15
CW		 1857 if (val & PIPECONF_ENABLE)
1858 return;
1859
1860 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1861 intel_wait_for_vblank(dev_priv->dev, pipe);
1862}
1863
1864/**
309cfea8 1865 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1866 * @dev_priv: i915 private structure
1867 * @pipe: pipe to disable
1868 *
1869 * Disable @pipe, making sure that various hardware specific requirements
1870 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1871 *
1872 * @pipe should be %PIPE_A or %PIPE_B.
1873 *
1874 * Will wait until the pipe has shut down before returning.
1875 */
1876static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1877 enum pipe pipe)
1878{
702e7a56
PZ		 1879 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1880 pipe);
b24e7179
JB		 1881 int reg;
1882 u32 val;
1883
1884 /*
1885 * Make sure planes won't keep trying to pump pixels to us,
1886 * or we might hang the display.
1887 */
1888 assert_planes_disabled(dev_priv, pipe);
19332d7a 1889 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1890
1891 /* Don't disable pipe A or pipe A PLLs if needed */
1892 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1893 return;
1894
702e7a56 1895 reg = PIPECONF(cpu_transcoder);
b24e7179 1896 val = I915_READ(reg);
00d70b15
CW		 1897 if ((val & PIPECONF_ENABLE) == 0)
1898 return;
1899
1900 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1901 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1902}
1903
d74362c9
KP		 1904/*
1905 * Plane regs are double buffered, going from enabled->disabled needs a
1906 * trigger in order to latch. The display address reg provides this.
1907 */
6f1d69b0 1908void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1909 enum plane plane)
1910{
14f86147
DL		 1911 if (dev_priv->info->gen >= 4)
1912 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1913 else
1914 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1915}
1916
b24e7179
JB		 1917/**
1918 * intel_enable_plane - enable a display plane on a given pipe
1919 * @dev_priv: i915 private structure
1920 * @plane: plane to enable
1921 * @pipe: pipe being fed
1922 *
1923 * Enable @plane on @pipe, making sure that @pipe is running first.
1924 */
1925static void intel_enable_plane(struct drm_i915_private *dev_priv,
1926 enum plane plane, enum pipe pipe)
1927{
1928 int reg;
1929 u32 val;
1930
1931 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1932 assert_pipe_enabled(dev_priv, pipe);
1933
1934 reg = DSPCNTR(plane);
1935 val = I915_READ(reg);
00d70b15
CW		 1936 if (val & DISPLAY_PLANE_ENABLE)
1937 return;
1938
1939 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1940 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1941 intel_wait_for_vblank(dev_priv->dev, pipe);
1942}
1943
b24e7179
JB		 1944/**
1945 * intel_disable_plane - disable a display plane
1946 * @dev_priv: i915 private structure
1947 * @plane: plane to disable
1948 * @pipe: pipe consuming the data
1949 *
1950 * Disable @plane; should be an independent operation.
1951 */
1952static void intel_disable_plane(struct drm_i915_private *dev_priv,
1953 enum plane plane, enum pipe pipe)
1954{
1955 int reg;
1956 u32 val;
1957
1958 reg = DSPCNTR(plane);
1959 val = I915_READ(reg);
00d70b15
CW		 1960 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1961 return;
1962
1963 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1964 intel_flush_display_plane(dev_priv, plane);
1965 intel_wait_for_vblank(dev_priv->dev, pipe);
1966}
1967
693db184
CW		 1968static bool need_vtd_wa(struct drm_device *dev)
1969{
1970#ifdef CONFIG_INTEL_IOMMU
1971 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1972 return true;
1973#endif
1974 return false;
1975}
1976
127bd2ac 1977int
48b956c5 1978intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1979 struct drm_i915_gem_object *obj,
919926ae 1980 struct intel_ring_buffer *pipelined)
6b95a207 1981{
ce453d81 1982 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1983 u32 alignment;
1984 int ret;
1985
05394f39 1986 switch (obj->tiling_mode) {
6b95a207 1987 case I915_TILING_NONE:
534843da
CW		 1988 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1989 alignment = 128 * 1024;
a6c45cf0 1990 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1991 alignment = 4 * 1024;
1992 else
1993 alignment = 64 * 1024;
6b95a207
KH		 1994 break;
1995 case I915_TILING_X:
1996 /* pin() will align the object as required by fence */
1997 alignment = 0;
1998 break;
1999 case I915_TILING_Y:
8bb6e959
DV		 2000 /* Despite that we check this in framebuffer_init userspace can
2001 * screw us over and change the tiling after the fact. Only
2002 * pinned buffers can't change their tiling. */
2003 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 2004 return -EINVAL;
2005 default:
2006 BUG();
2007 }
2008
693db184
CW		 2009 /* Note that the w/a also requires 64 PTE of padding following the
2010 * bo. We currently fill all unused PTE with the shadow page and so
2011 * we should always have valid PTE following the scanout preventing
2012 * the VT-d warning.
2013 */
2014 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2015 alignment = 256 * 1024;
2016
ce453d81 2017 dev_priv->mm.interruptible = false;
2da3b9b9 2018 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2019 if (ret)
ce453d81 2020 goto err_interruptible;
6b95a207
KH		 2021
2022 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2023 * fence, whereas 965+ only requires a fence if using
2024 * framebuffer compression. For simplicity, we always install
2025 * a fence as the cost is not that onerous.
2026 */
06d98131 2027 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2028 if (ret)
2029 goto err_unpin;
1690e1eb 2030
9a5a53b3 2031 i915_gem_object_pin_fence(obj);
6b95a207 2032
ce453d81 2033 dev_priv->mm.interruptible = true;
6b95a207 2034 return 0;
48b956c5
CW		 2035
2036err_unpin:
2037 i915_gem_object_unpin(obj);
ce453d81
CW		 2038err_interruptible:
2039 dev_priv->mm.interruptible = true;
48b956c5 2040 return ret;
6b95a207
KH		 2041}
2042
1690e1eb
CW		 2043void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2044{
2045 i915_gem_object_unpin_fence(obj);
2046 i915_gem_object_unpin(obj);
2047}
2048
c2c75131
DV		 2049/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2050 * is assumed to be a power-of-two. */
bc752862
CW		 2051unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2052 unsigned int tiling_mode,
2053 unsigned int cpp,
2054 unsigned int pitch)
c2c75131 2055{
bc752862
CW		 2056 if (tiling_mode != I915_TILING_NONE) {
2057 unsigned int tile_rows, tiles;
c2c75131 2058
bc752862
CW		 2059 tile_rows = *y / 8;
2060 *y %= 8;
c2c75131 2061
bc752862
CW		 2062 tiles = *x / (512/cpp);
2063 *x %= 512/cpp;
2064
2065 return tile_rows * pitch * 8 + tiles * 4096;
2066 } else {
2067 unsigned int offset;
2068
2069 offset = *y * pitch + *x * cpp;
2070 *y = 0;
2071 *x = (offset & 4095) / cpp;
2072 return offset & -4096;
2073 }
c2c75131
DV		 2074}
2075
17638cd6
JB		 2076static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2077 int x, int y)
81255565
JB		 2078{
2079 struct drm_device *dev = crtc->dev;
2080 struct drm_i915_private *dev_priv = dev->dev_private;
2081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2082 struct intel_framebuffer *intel_fb;
05394f39 2083 struct drm_i915_gem_object *obj;
81255565 2084 int plane = intel_crtc->plane;
e506a0c6 2085 unsigned long linear_offset;
81255565 2086 u32 dspcntr;
5eddb70b 2087 u32 reg;
81255565
JB		 2088
2089 switch (plane) {
2090 case 0:
2091 case 1:
2092 break;
2093 default:
84f44ce7 2094 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2095 return -EINVAL;
2096 }
2097
2098 intel_fb = to_intel_framebuffer(fb);
2099 obj = intel_fb->obj;
81255565 2100
5eddb70b
CW		 2101 reg = DSPCNTR(plane);
2102 dspcntr = I915_READ(reg);
81255565
JB		 2103 /* Mask out pixel format bits in case we change it */
2104 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2105 switch (fb->pixel_format) {
2106 case DRM_FORMAT_C8:
81255565
JB		 2107 dspcntr |= DISPPLANE_8BPP;
2108 break;
57779d06
VS		 2109 case DRM_FORMAT_XRGB1555:
2110 case DRM_FORMAT_ARGB1555:
2111 dspcntr |= DISPPLANE_BGRX555;
81255565 2112 break;
57779d06
VS		 2113 case DRM_FORMAT_RGB565:
2114 dspcntr |= DISPPLANE_BGRX565;
2115 break;
2116 case DRM_FORMAT_XRGB8888:
2117 case DRM_FORMAT_ARGB8888:
2118 dspcntr |= DISPPLANE_BGRX888;
2119 break;
2120 case DRM_FORMAT_XBGR8888:
2121 case DRM_FORMAT_ABGR8888:
2122 dspcntr |= DISPPLANE_RGBX888;
2123 break;
2124 case DRM_FORMAT_XRGB2101010:
2125 case DRM_FORMAT_ARGB2101010:
2126 dspcntr |= DISPPLANE_BGRX101010;
2127 break;
2128 case DRM_FORMAT_XBGR2101010:
2129 case DRM_FORMAT_ABGR2101010:
2130 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2131 break;
2132 default:
baba133a 2133 BUG();
81255565 2134 }
57779d06 2135
a6c45cf0 2136 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2137 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2138 dspcntr |= DISPPLANE_TILED;
2139 else
2140 dspcntr &= ~DISPPLANE_TILED;
2141 }
2142
5eddb70b 2143 I915_WRITE(reg, dspcntr);
81255565 2144
e506a0c6 2145 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2146
c2c75131
DV		 2147 if (INTEL_INFO(dev)->gen >= 4) {
2148 intel_crtc->dspaddr_offset =
bc752862
CW		 2149 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2150 fb->bits_per_pixel / 8,
2151 fb->pitches[0]);
c2c75131
DV		 2152 linear_offset -= intel_crtc->dspaddr_offset;
2153 } else {
e506a0c6 2154 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2155 }
e506a0c6
DV		 2156
2157 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2158 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2159 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2160 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2161 I915_MODIFY_DISPBASE(DSPSURF(plane),
2162 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2163 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2164 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2165 } else
e506a0c6 2166 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2167 POSTING_READ(reg);
81255565 2168
17638cd6
JB		 2169 return 0;
2170}
2171
2172static int ironlake_update_plane(struct drm_crtc *crtc,
2173 struct drm_framebuffer *fb, int x, int y)
2174{
2175 struct drm_device *dev = crtc->dev;
2176 struct drm_i915_private *dev_priv = dev->dev_private;
2177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2178 struct intel_framebuffer *intel_fb;
2179 struct drm_i915_gem_object *obj;
2180 int plane = intel_crtc->plane;
e506a0c6 2181 unsigned long linear_offset;
17638cd6
JB		 2182 u32 dspcntr;
2183 u32 reg;
2184
2185 switch (plane) {
2186 case 0:
2187 case 1:
27f8227b 2188 case 2:
17638cd6
JB		 2189 break;
2190 default:
84f44ce7 2191 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2192 return -EINVAL;
2193 }
2194
2195 intel_fb = to_intel_framebuffer(fb);
2196 obj = intel_fb->obj;
2197
2198 reg = DSPCNTR(plane);
2199 dspcntr = I915_READ(reg);
2200 /* Mask out pixel format bits in case we change it */
2201 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2202 switch (fb->pixel_format) {
2203 case DRM_FORMAT_C8:
17638cd6
JB		 2204 dspcntr |= DISPPLANE_8BPP;
2205 break;
57779d06
VS		 2206 case DRM_FORMAT_RGB565:
2207 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2208 break;
57779d06
VS		 2209 case DRM_FORMAT_XRGB8888:
2210 case DRM_FORMAT_ARGB8888:
2211 dspcntr |= DISPPLANE_BGRX888;
2212 break;
2213 case DRM_FORMAT_XBGR8888:
2214 case DRM_FORMAT_ABGR8888:
2215 dspcntr |= DISPPLANE_RGBX888;
2216 break;
2217 case DRM_FORMAT_XRGB2101010:
2218 case DRM_FORMAT_ARGB2101010:
2219 dspcntr |= DISPPLANE_BGRX101010;
2220 break;
2221 case DRM_FORMAT_XBGR2101010:
2222 case DRM_FORMAT_ABGR2101010:
2223 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2224 break;
2225 default:
baba133a 2226 BUG();
17638cd6
JB		 2227 }
2228
2229 if (obj->tiling_mode != I915_TILING_NONE)
2230 dspcntr |= DISPPLANE_TILED;
2231 else
2232 dspcntr &= ~DISPPLANE_TILED;
2233
2234 /* must disable */
2235 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2236
2237 I915_WRITE(reg, dspcntr);
2238
e506a0c6 2239 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2240 intel_crtc->dspaddr_offset =
bc752862
CW		 2241 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2242 fb->bits_per_pixel / 8,
2243 fb->pitches[0]);
c2c75131 2244 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2245
e506a0c6
DV		 2246 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2247 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2248 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2249 I915_MODIFY_DISPBASE(DSPSURF(plane),
2250 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2251 if (IS_HASWELL(dev)) {
2252 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2253 } else {
2254 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2255 I915_WRITE(DSPLINOFF(plane), linear_offset);
2256 }
17638cd6
JB		 2257 POSTING_READ(reg);
2258
2259 return 0;
2260}
2261
2262/* Assume fb object is pinned & idle & fenced and just update base pointers */
2263static int
2264intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2265 int x, int y, enum mode_set_atomic state)
2266{
2267 struct drm_device *dev = crtc->dev;
2268 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2269
6b8e6ed0
CW		 2270 if (dev_priv->display.disable_fbc)
2271 dev_priv->display.disable_fbc(dev);
3dec0095 2272 intel_increase_pllclock(crtc);
81255565 2273
6b8e6ed0 2274 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2275}
2276
96a02917
VS		 2277void intel_display_handle_reset(struct drm_device *dev)
2278{
2279 struct drm_i915_private *dev_priv = dev->dev_private;
2280 struct drm_crtc *crtc;
2281
2282 /*
2283 * Flips in the rings have been nuked by the reset,
2284 * so complete all pending flips so that user space
2285 * will get its events and not get stuck.
2286 *
2287 * Also update the base address of all primary
2288 * planes to the the last fb to make sure we're
2289 * showing the correct fb after a reset.
2290 *
2291 * Need to make two loops over the crtcs so that we
2292 * don't try to grab a crtc mutex before the
2293 * pending_flip_queue really got woken up.
2294 */
2295
2296 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2298 enum plane plane = intel_crtc->plane;
2299
2300 intel_prepare_page_flip(dev, plane);
2301 intel_finish_page_flip_plane(dev, plane);
2302 }
2303
2304 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2306
2307 mutex_lock(&crtc->mutex);
2308 if (intel_crtc->active)
2309 dev_priv->display.update_plane(crtc, crtc->fb,
2310 crtc->x, crtc->y);
2311 mutex_unlock(&crtc->mutex);
2312 }
2313}
2314
14667a4b
CW		 2315static int
2316intel_finish_fb(struct drm_framebuffer *old_fb)
2317{
2318 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2319 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2320 bool was_interruptible = dev_priv->mm.interruptible;
2321 int ret;
2322
14667a4b
CW		 2323 /* Big Hammer, we also need to ensure that any pending
2324 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2325 * current scanout is retired before unpinning the old
2326 * framebuffer.
2327 *
2328 * This should only fail upon a hung GPU, in which case we
2329 * can safely continue.
2330 */
2331 dev_priv->mm.interruptible = false;
2332 ret = i915_gem_object_finish_gpu(obj);
2333 dev_priv->mm.interruptible = was_interruptible;
2334
2335 return ret;
2336}
2337
198598d0
VS		 2338static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2339{
2340 struct drm_device *dev = crtc->dev;
2341 struct drm_i915_master_private *master_priv;
2342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2343
2344 if (!dev->primary->master)
2345 return;
2346
2347 master_priv = dev->primary->master->driver_priv;
2348 if (!master_priv->sarea_priv)
2349 return;
2350
2351 switch (intel_crtc->pipe) {
2352 case 0:
2353 master_priv->sarea_priv->pipeA_x = x;
2354 master_priv->sarea_priv->pipeA_y = y;
2355 break;
2356 case 1:
2357 master_priv->sarea_priv->pipeB_x = x;
2358 master_priv->sarea_priv->pipeB_y = y;
2359 break;
2360 default:
2361 break;
2362 }
2363}
2364
5c3b82e2 2365static int
3c4fdcfb 2366intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2367 struct drm_framebuffer *fb)
79e53945
JB		 2368{
2369 struct drm_device *dev = crtc->dev;
6b8e6ed0 2370 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2372 struct drm_framebuffer *old_fb;
5c3b82e2 2373 int ret;
79e53945
JB		 2374
2375 /* no fb bound */
94352cf9 2376 if (!fb) {
a5071c2f 2377 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2378 return 0;
2379 }
2380
7eb552ae 2381 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2382 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2383 plane_name(intel_crtc->plane),
2384 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2385 return -EINVAL;
79e53945
JB		 2386 }
2387
5c3b82e2 2388 mutex_lock(&dev->struct_mutex);
265db958 2389 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2390 to_intel_framebuffer(fb)->obj,
919926ae 2391 NULL);
5c3b82e2
CW		 2392 if (ret != 0) {
2393 mutex_unlock(&dev->struct_mutex);
a5071c2f 2394 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2395 return ret;
2396 }
79e53945 2397
94352cf9 2398 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2399 if (ret) {
94352cf9 2400 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2401 mutex_unlock(&dev->struct_mutex);
a5071c2f 2402 DRM_ERROR("failed to update base address\n");
4e6cfefc 2403 return ret;
79e53945 2404 }
3c4fdcfb 2405
94352cf9
DV		 2406 old_fb = crtc->fb;
2407 crtc->fb = fb;
6c4c86f5
DV		 2408 crtc->x = x;
2409 crtc->y = y;
94352cf9 2410
b7f1de28
CW		 2411 if (old_fb) {
2412 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2413 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2414 }
652c393a 2415
6b8e6ed0 2416 intel_update_fbc(dev);
5c3b82e2 2417 mutex_unlock(&dev->struct_mutex);
79e53945 2418
198598d0 2419 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2420
2421 return 0;
79e53945
JB		 2422}
2423
5e84e1a4
ZW		 2424static void intel_fdi_normal_train(struct drm_crtc *crtc)
2425{
2426 struct drm_device *dev = crtc->dev;
2427 struct drm_i915_private *dev_priv = dev->dev_private;
2428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2429 int pipe = intel_crtc->pipe;
2430 u32 reg, temp;
2431
2432 /* enable normal train */
2433 reg = FDI_TX_CTL(pipe);
2434 temp = I915_READ(reg);
61e499bf 2435 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2436 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2437 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2438 } else {
2439 temp &= ~FDI_LINK_TRAIN_NONE;
2440 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2441 }
5e84e1a4
ZW		 2442 I915_WRITE(reg, temp);
2443
2444 reg = FDI_RX_CTL(pipe);
2445 temp = I915_READ(reg);
2446 if (HAS_PCH_CPT(dev)) {
2447 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2448 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2449 } else {
2450 temp &= ~FDI_LINK_TRAIN_NONE;
2451 temp |= FDI_LINK_TRAIN_NONE;
2452 }
2453 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2454
2455 /* wait one idle pattern time */
2456 POSTING_READ(reg);
2457 udelay(1000);
357555c0
JB		 2458
2459 /* IVB wants error correction enabled */
2460 if (IS_IVYBRIDGE(dev))
2461 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2462 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2463}
2464
01a415fd
DV		 2465static void ivb_modeset_global_resources(struct drm_device *dev)
2466{
2467 struct drm_i915_private *dev_priv = dev->dev_private;
2468 struct intel_crtc *pipe_B_crtc =
2469 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2470 struct intel_crtc *pipe_C_crtc =
2471 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2472 uint32_t temp;
2473
2474 /* When everything is off disable fdi C so that we could enable fdi B
2475 * with all lanes. XXX: This misses the case where a pipe is not using
2476 * any pch resources and so doesn't need any fdi lanes. */
2477 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2478 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2479 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2480
2481 temp = I915_READ(SOUTH_CHICKEN1);
2482 temp &= ~FDI_BC_BIFURCATION_SELECT;
2483 DRM_DEBUG_KMS("disabling fdi C rx\n");
2484 I915_WRITE(SOUTH_CHICKEN1, temp);
2485 }
2486}
2487
8db9d77b
ZW		 2488/* The FDI link training functions for ILK/Ibexpeak. */
2489static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2490{
2491 struct drm_device *dev = crtc->dev;
2492 struct drm_i915_private *dev_priv = dev->dev_private;
2493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2494 int pipe = intel_crtc->pipe;
0fc932b8 2495 int plane = intel_crtc->plane;
5eddb70b 2496 u32 reg, temp, tries;
8db9d77b 2497
0fc932b8
JB		 2498 /* FDI needs bits from pipe & plane first */
2499 assert_pipe_enabled(dev_priv, pipe);
2500 assert_plane_enabled(dev_priv, plane);
2501
e1a44743
AJ		 2502 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2503 for train result */
5eddb70b
CW		 2504 reg = FDI_RX_IMR(pipe);
2505 temp = I915_READ(reg);
e1a44743
AJ		 2506 temp &= ~FDI_RX_SYMBOL_LOCK;
2507 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2508 I915_WRITE(reg, temp);
2509 I915_READ(reg);
e1a44743
AJ		 2510 udelay(150);
2511
8db9d77b 2512 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2513 reg = FDI_TX_CTL(pipe);
2514 temp = I915_READ(reg);
77ffb597
AJ		 2515 temp &= ~(7 << 19);
2516 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2517 temp &= ~FDI_LINK_TRAIN_NONE;
2518 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2519 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2520
5eddb70b
CW		 2521 reg = FDI_RX_CTL(pipe);
2522 temp = I915_READ(reg);
8db9d77b
ZW		 2523 temp &= ~FDI_LINK_TRAIN_NONE;
2524 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2525 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2526
2527 POSTING_READ(reg);
8db9d77b
ZW		 2528 udelay(150);
2529
5b2adf89 2530 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2531 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2532 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2533 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2534
5eddb70b 2535 reg = FDI_RX_IIR(pipe);
e1a44743 2536 for (tries = 0; tries < 5; tries++) {
5eddb70b 2537 temp = I915_READ(reg);
8db9d77b
ZW		 2538 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2539
2540 if ((temp & FDI_RX_BIT_LOCK)) {
2541 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2542 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2543 break;
2544 }
8db9d77b 2545 }
e1a44743 2546 if (tries == 5)
5eddb70b 2547 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2548
2549 /* Train 2 */
5eddb70b
CW		 2550 reg = FDI_TX_CTL(pipe);
2551 temp = I915_READ(reg);
8db9d77b
ZW		 2552 temp &= ~FDI_LINK_TRAIN_NONE;
2553 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2554 I915_WRITE(reg, temp);
8db9d77b 2555
5eddb70b
CW		 2556 reg = FDI_RX_CTL(pipe);
2557 temp = I915_READ(reg);
8db9d77b
ZW		 2558 temp &= ~FDI_LINK_TRAIN_NONE;
2559 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2560 I915_WRITE(reg, temp);
8db9d77b 2561
5eddb70b
CW		 2562 POSTING_READ(reg);
2563 udelay(150);
8db9d77b 2564
5eddb70b 2565 reg = FDI_RX_IIR(pipe);
e1a44743 2566 for (tries = 0; tries < 5; tries++) {
5eddb70b 2567 temp = I915_READ(reg);
8db9d77b
ZW		 2568 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2569
2570 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2571 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2572 DRM_DEBUG_KMS("FDI train 2 done.\n");
2573 break;
2574 }
8db9d77b 2575 }
e1a44743 2576 if (tries == 5)
5eddb70b 2577 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2578
2579 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2580
8db9d77b
ZW		 2581}
2582
0206e353 2583static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2584 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2585 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2586 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2587 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2588};
2589
2590/* The FDI link training functions for SNB/Cougarpoint. */
2591static void gen6_fdi_link_train(struct drm_crtc *crtc)
2592{
2593 struct drm_device *dev = crtc->dev;
2594 struct drm_i915_private *dev_priv = dev->dev_private;
2595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2596 int pipe = intel_crtc->pipe;
fa37d39e 2597 u32 reg, temp, i, retry;
8db9d77b 2598
e1a44743
AJ		 2599 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2600 for train result */
5eddb70b
CW		 2601 reg = FDI_RX_IMR(pipe);
2602 temp = I915_READ(reg);
e1a44743
AJ		 2603 temp &= ~FDI_RX_SYMBOL_LOCK;
2604 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2605 I915_WRITE(reg, temp);
2606
2607 POSTING_READ(reg);
e1a44743
AJ		 2608 udelay(150);
2609
8db9d77b 2610 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
77ffb597
AJ		 2613 temp &= ~(7 << 19);
2614 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2615 temp &= ~FDI_LINK_TRAIN_NONE;
2616 temp |= FDI_LINK_TRAIN_PATTERN_1;
2617 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2618 /* SNB-B */
2619 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2620 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2621
d74cf324
DV		 2622 I915_WRITE(FDI_RX_MISC(pipe),
2623 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2624
5eddb70b
CW		 2625 reg = FDI_RX_CTL(pipe);
2626 temp = I915_READ(reg);
8db9d77b
ZW		 2627 if (HAS_PCH_CPT(dev)) {
2628 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2629 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2630 } else {
2631 temp &= ~FDI_LINK_TRAIN_NONE;
2632 temp |= FDI_LINK_TRAIN_PATTERN_1;
2633 }
5eddb70b
CW		 2634 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2635
2636 POSTING_READ(reg);
8db9d77b
ZW		 2637 udelay(150);
2638
0206e353 2639 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2640 reg = FDI_TX_CTL(pipe);
2641 temp = I915_READ(reg);
8db9d77b
ZW		 2642 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2643 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2644 I915_WRITE(reg, temp);
2645
2646 POSTING_READ(reg);
8db9d77b
ZW		 2647 udelay(500);
2648
fa37d39e
SP		 2649 for (retry = 0; retry < 5; retry++) {
2650 reg = FDI_RX_IIR(pipe);
2651 temp = I915_READ(reg);
2652 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2653 if (temp & FDI_RX_BIT_LOCK) {
2654 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2655 DRM_DEBUG_KMS("FDI train 1 done.\n");
2656 break;
2657 }
2658 udelay(50);
8db9d77b 2659 }
fa37d39e
SP		 2660 if (retry < 5)
2661 break;
8db9d77b
ZW		 2662 }
2663 if (i == 4)
5eddb70b 2664 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2665
2666 /* Train 2 */
5eddb70b
CW		 2667 reg = FDI_TX_CTL(pipe);
2668 temp = I915_READ(reg);
8db9d77b
ZW		 2669 temp &= ~FDI_LINK_TRAIN_NONE;
2670 temp |= FDI_LINK_TRAIN_PATTERN_2;
2671 if (IS_GEN6(dev)) {
2672 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2673 /* SNB-B */
2674 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2675 }
5eddb70b 2676 I915_WRITE(reg, temp);
8db9d77b 2677
5eddb70b
CW		 2678 reg = FDI_RX_CTL(pipe);
2679 temp = I915_READ(reg);
8db9d77b
ZW		 2680 if (HAS_PCH_CPT(dev)) {
2681 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2682 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2683 } else {
2684 temp &= ~FDI_LINK_TRAIN_NONE;
2685 temp |= FDI_LINK_TRAIN_PATTERN_2;
2686 }
5eddb70b
CW		 2687 I915_WRITE(reg, temp);
2688
2689 POSTING_READ(reg);
8db9d77b
ZW		 2690 udelay(150);
2691
0206e353 2692 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2693 reg = FDI_TX_CTL(pipe);
2694 temp = I915_READ(reg);
8db9d77b
ZW		 2695 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2696 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2697 I915_WRITE(reg, temp);
2698
2699 POSTING_READ(reg);
8db9d77b
ZW		 2700 udelay(500);
2701
fa37d39e
SP		 2702 for (retry = 0; retry < 5; retry++) {
2703 reg = FDI_RX_IIR(pipe);
2704 temp = I915_READ(reg);
2705 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2706 if (temp & FDI_RX_SYMBOL_LOCK) {
2707 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2708 DRM_DEBUG_KMS("FDI train 2 done.\n");
2709 break;
2710 }
2711 udelay(50);
8db9d77b 2712 }
fa37d39e
SP		 2713 if (retry < 5)
2714 break;
8db9d77b
ZW		 2715 }
2716 if (i == 4)
5eddb70b 2717 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2718
2719 DRM_DEBUG_KMS("FDI train done.\n");
2720}
2721
357555c0
JB		 2722/* Manual link training for Ivy Bridge A0 parts */
2723static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2724{
2725 struct drm_device *dev = crtc->dev;
2726 struct drm_i915_private *dev_priv = dev->dev_private;
2727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2728 int pipe = intel_crtc->pipe;
2729 u32 reg, temp, i;
2730
2731 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2732 for train result */
2733 reg = FDI_RX_IMR(pipe);
2734 temp = I915_READ(reg);
2735 temp &= ~FDI_RX_SYMBOL_LOCK;
2736 temp &= ~FDI_RX_BIT_LOCK;
2737 I915_WRITE(reg, temp);
2738
2739 POSTING_READ(reg);
2740 udelay(150);
2741
01a415fd
DV		 2742 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2743 I915_READ(FDI_RX_IIR(pipe)));
2744
357555c0
JB		 2745 /* enable CPU FDI TX and PCH FDI RX */
2746 reg = FDI_TX_CTL(pipe);
2747 temp = I915_READ(reg);
2748 temp &= ~(7 << 19);
2749 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2750 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2751 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2752 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2753 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2754 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2755 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2756
d74cf324
DV		 2757 I915_WRITE(FDI_RX_MISC(pipe),
2758 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2759
357555c0
JB		 2760 reg = FDI_RX_CTL(pipe);
2761 temp = I915_READ(reg);
2762 temp &= ~FDI_LINK_TRAIN_AUTO;
2763 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2764 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2765 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2766 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2767
2768 POSTING_READ(reg);
2769 udelay(150);
2770
0206e353 2771 for (i = 0; i < 4; i++) {
357555c0
JB		 2772 reg = FDI_TX_CTL(pipe);
2773 temp = I915_READ(reg);
2774 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2775 temp |= snb_b_fdi_train_param[i];
2776 I915_WRITE(reg, temp);
2777
2778 POSTING_READ(reg);
2779 udelay(500);
2780
2781 reg = FDI_RX_IIR(pipe);
2782 temp = I915_READ(reg);
2783 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2784
2785 if (temp & FDI_RX_BIT_LOCK ||
2786 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2787 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2788 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2789 break;
2790 }
2791 }
2792 if (i == 4)
2793 DRM_ERROR("FDI train 1 fail!\n");
2794
2795 /* Train 2 */
2796 reg = FDI_TX_CTL(pipe);
2797 temp = I915_READ(reg);
2798 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2799 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2800 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2801 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2802 I915_WRITE(reg, temp);
2803
2804 reg = FDI_RX_CTL(pipe);
2805 temp = I915_READ(reg);
2806 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2807 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2808 I915_WRITE(reg, temp);
2809
2810 POSTING_READ(reg);
2811 udelay(150);
2812
0206e353 2813 for (i = 0; i < 4; i++) {
357555c0
JB		 2814 reg = FDI_TX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2817 temp |= snb_b_fdi_train_param[i];
2818 I915_WRITE(reg, temp);
2819
2820 POSTING_READ(reg);
2821 udelay(500);
2822
2823 reg = FDI_RX_IIR(pipe);
2824 temp = I915_READ(reg);
2825 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2826
2827 if (temp & FDI_RX_SYMBOL_LOCK) {
2828 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2829 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2830 break;
2831 }
2832 }
2833 if (i == 4)
2834 DRM_ERROR("FDI train 2 fail!\n");
2835
2836 DRM_DEBUG_KMS("FDI train done.\n");
2837}
2838
88cefb6c 2839static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2840{
88cefb6c 2841 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2842 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2843 int pipe = intel_crtc->pipe;
5eddb70b 2844 u32 reg, temp;
79e53945 2845
c64e311e 2846
c98e9dcf 2847 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2848 reg = FDI_RX_CTL(pipe);
2849 temp = I915_READ(reg);
2850 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2851 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2852 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2853 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2854
2855 POSTING_READ(reg);
c98e9dcf
JB		 2856 udelay(200);
2857
2858 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2859 temp = I915_READ(reg);
2860 I915_WRITE(reg, temp | FDI_PCDCLK);
2861
2862 POSTING_READ(reg);
c98e9dcf
JB		 2863 udelay(200);
2864
20749730
PZ		 2865 /* Enable CPU FDI TX PLL, always on for Ironlake */
2866 reg = FDI_TX_CTL(pipe);
2867 temp = I915_READ(reg);
2868 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2869 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2870
20749730
PZ		 2871 POSTING_READ(reg);
2872 udelay(100);
6be4a607 2873 }
0e23b99d
JB		 2874}
2875
88cefb6c
DV		 2876static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2877{
2878 struct drm_device *dev = intel_crtc->base.dev;
2879 struct drm_i915_private *dev_priv = dev->dev_private;
2880 int pipe = intel_crtc->pipe;
2881 u32 reg, temp;
2882
2883 /* Switch from PCDclk to Rawclk */
2884 reg = FDI_RX_CTL(pipe);
2885 temp = I915_READ(reg);
2886 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2887
2888 /* Disable CPU FDI TX PLL */
2889 reg = FDI_TX_CTL(pipe);
2890 temp = I915_READ(reg);
2891 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2892
2893 POSTING_READ(reg);
2894 udelay(100);
2895
2896 reg = FDI_RX_CTL(pipe);
2897 temp = I915_READ(reg);
2898 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2899
2900 /* Wait for the clocks to turn off. */
2901 POSTING_READ(reg);
2902 udelay(100);
2903}
2904
0fc932b8
JB		 2905static void ironlake_fdi_disable(struct drm_crtc *crtc)
2906{
2907 struct drm_device *dev = crtc->dev;
2908 struct drm_i915_private *dev_priv = dev->dev_private;
2909 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2910 int pipe = intel_crtc->pipe;
2911 u32 reg, temp;
2912
2913 /* disable CPU FDI tx and PCH FDI rx */
2914 reg = FDI_TX_CTL(pipe);
2915 temp = I915_READ(reg);
2916 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2917 POSTING_READ(reg);
2918
2919 reg = FDI_RX_CTL(pipe);
2920 temp = I915_READ(reg);
2921 temp &= ~(0x7 << 16);
dfd07d72 2922 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2923 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2924
2925 POSTING_READ(reg);
2926 udelay(100);
2927
2928 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2929 if (HAS_PCH_IBX(dev)) {
2930 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2931 }
0fc932b8
JB		 2932
2933 /* still set train pattern 1 */
2934 reg = FDI_TX_CTL(pipe);
2935 temp = I915_READ(reg);
2936 temp &= ~FDI_LINK_TRAIN_NONE;
2937 temp |= FDI_LINK_TRAIN_PATTERN_1;
2938 I915_WRITE(reg, temp);
2939
2940 reg = FDI_RX_CTL(pipe);
2941 temp = I915_READ(reg);
2942 if (HAS_PCH_CPT(dev)) {
2943 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2944 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2945 } else {
2946 temp &= ~FDI_LINK_TRAIN_NONE;
2947 temp |= FDI_LINK_TRAIN_PATTERN_1;
2948 }
2949 /* BPC in FDI rx is consistent with that in PIPECONF */
2950 temp &= ~(0x07 << 16);
dfd07d72 2951 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2952 I915_WRITE(reg, temp);
2953
2954 POSTING_READ(reg);
2955 udelay(100);
2956}
2957
5bb61643
CW		 2958static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2959{
2960 struct drm_device *dev = crtc->dev;
2961 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2963 unsigned long flags;
2964 bool pending;
2965
10d83730
VS		 2966 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2967 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2968 return false;
2969
2970 spin_lock_irqsave(&dev->event_lock, flags);
2971 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2972 spin_unlock_irqrestore(&dev->event_lock, flags);
2973
2974 return pending;
2975}
2976
e6c3a2a6
CW		 2977static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2978{
0f91128d 2979 struct drm_device *dev = crtc->dev;
5bb61643 2980 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2981
2982 if (crtc->fb == NULL)
2983 return;
2984
2c10d571
DV		 2985 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2986
5bb61643
CW		 2987 wait_event(dev_priv->pending_flip_queue,
2988 !intel_crtc_has_pending_flip(crtc));
2989
0f91128d
CW		 2990 mutex_lock(&dev->struct_mutex);
2991 intel_finish_fb(crtc->fb);
2992 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2993}
2994
e615efe4
ED		 2995/* Program iCLKIP clock to the desired frequency */
2996static void lpt_program_iclkip(struct drm_crtc *crtc)
2997{
2998 struct drm_device *dev = crtc->dev;
2999 struct drm_i915_private *dev_priv = dev->dev_private;
3000 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3001 u32 temp;
3002
09153000
DV		 3003 mutex_lock(&dev_priv->dpio_lock);
3004
e615efe4
ED		 3005 /* It is necessary to ungate the pixclk gate prior to programming
3006 * the divisors, and gate it back when it is done.
3007 */
3008 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3009
3010 /* Disable SSCCTL */
3011 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3012 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3013 SBI_SSCCTL_DISABLE,
3014 SBI_ICLK);
e615efe4
ED		 3015
3016 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3017 if (crtc->mode.clock == 20000) {
3018 auxdiv = 1;
3019 divsel = 0x41;
3020 phaseinc = 0x20;
3021 } else {
3022 /* The iCLK virtual clock root frequency is in MHz,
3023 * but the crtc->mode.clock in in KHz. To get the divisors,
3024 * it is necessary to divide one by another, so we
3025 * convert the virtual clock precision to KHz here for higher
3026 * precision.
3027 */
3028 u32 iclk_virtual_root_freq = 172800 * 1000;
3029 u32 iclk_pi_range = 64;
3030 u32 desired_divisor, msb_divisor_value, pi_value;
3031
3032 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3033 msb_divisor_value = desired_divisor / iclk_pi_range;
3034 pi_value = desired_divisor % iclk_pi_range;
3035
3036 auxdiv = 0;
3037 divsel = msb_divisor_value - 2;
3038 phaseinc = pi_value;
3039 }
3040
3041 /* This should not happen with any sane values */
3042 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3043 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3044 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3045 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3046
3047 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3048 crtc->mode.clock,
3049 auxdiv,
3050 divsel,
3051 phasedir,
3052 phaseinc);
3053
3054 /* Program SSCDIVINTPHASE6 */
988d6ee8 3055 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3056 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3057 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3058 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3059 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3060 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3061 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3062 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3063
3064 /* Program SSCAUXDIV */
988d6ee8 3065 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3066 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3067 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3068 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3069
3070 /* Enable modulator and associated divider */
988d6ee8 3071 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3072 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3073 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3074
3075 /* Wait for initialization time */
3076 udelay(24);
3077
3078 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3079
3080 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3081}
3082
f67a559d
JB		 3083/*
3084 * Enable PCH resources required for PCH ports:
3085 * - PCH PLLs
3086 * - FDI training & RX/TX
3087 * - update transcoder timings
3088 * - DP transcoding bits
3089 * - transcoder
3090 */
3091static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3092{
3093 struct drm_device *dev = crtc->dev;
3094 struct drm_i915_private *dev_priv = dev->dev_private;
3095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3096 int pipe = intel_crtc->pipe;
ee7b9f93 3097 u32 reg, temp;
2c07245f 3098
e7e164db
CW		 3099 assert_transcoder_disabled(dev_priv, pipe);
3100
cd986abb
DV		 3101 /* Write the TU size bits before fdi link training, so that error
3102 * detection works. */
3103 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3104 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3105
c98e9dcf 3106 /* For PCH output, training FDI link */
674cf967 3107 dev_priv->display.fdi_link_train(crtc);
2c07245f 3108
572deb37
DV		 3109 /* XXX: pch pll's can be enabled any time before we enable the PCH
3110 * transcoder, and we actually should do this to not upset any PCH
3111 * transcoder that already use the clock when we share it.
3112 *
3113 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3114 * unconditionally resets the pll - we need that to have the right LVDS
3115 * enable sequence. */
b6b4e185 3116 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3117
303b81e0 3118 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3119 u32 sel;
4b645f14 3120
c98e9dcf 3121 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3122 switch (pipe) {
3123 default:
3124 case 0:
3125 temp |= TRANSA_DPLL_ENABLE;
3126 sel = TRANSA_DPLLB_SEL;
3127 break;
3128 case 1:
3129 temp |= TRANSB_DPLL_ENABLE;
3130 sel = TRANSB_DPLLB_SEL;
3131 break;
3132 case 2:
3133 temp |= TRANSC_DPLL_ENABLE;
3134 sel = TRANSC_DPLLB_SEL;
3135 break;
d64311ab 3136 }
ee7b9f93
JB		 3137 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3138 temp |= sel;
3139 else
3140 temp &= ~sel;
c98e9dcf 3141 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3142 }
5eddb70b 3143
d9b6cb56
JB		 3144 /* set transcoder timing, panel must allow it */
3145 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3146 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3147 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3148 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3149
5eddb70b
CW		 3150 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3151 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3152 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3153 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3154
303b81e0 3155 intel_fdi_normal_train(crtc);
5e84e1a4 3156
c98e9dcf
JB		 3157 /* For PCH DP, enable TRANS_DP_CTL */
3158 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3159 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3160 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3161 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3162 reg = TRANS_DP_CTL(pipe);
3163 temp = I915_READ(reg);
3164 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3165 TRANS_DP_SYNC_MASK |
3166 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3167 temp |= (TRANS_DP_OUTPUT_ENABLE |
3168 TRANS_DP_ENH_FRAMING);
9325c9f0 3169 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3170
3171 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3172 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3173 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3174 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3175
3176 switch (intel_trans_dp_port_sel(crtc)) {
3177 case PCH_DP_B:
5eddb70b 3178 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3179 break;
3180 case PCH_DP_C:
5eddb70b 3181 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3182 break;
3183 case PCH_DP_D:
5eddb70b 3184 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3185 break;
3186 default:
e95d41e1 3187 BUG();
32f9d658 3188 }
2c07245f 3189
5eddb70b 3190 I915_WRITE(reg, temp);
6be4a607 3191 }
b52eb4dc 3192
b8a4f404 3193 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3194}
3195
1507e5bd
PZ		 3196static void lpt_pch_enable(struct drm_crtc *crtc)
3197{
3198 struct drm_device *dev = crtc->dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3201 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3202
daed2dbb 3203 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3204
8c52b5e8 3205 lpt_program_iclkip(crtc);
1507e5bd 3206
0540e488 3207 /* Set transcoder timing. */
daed2dbb
PZ		 3208 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3209 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3210 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3211
daed2dbb
PZ		 3212 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3213 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3214 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3215 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3216
937bb610 3217 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3218}
3219
ee7b9f93
JB		 3220static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3221{
3222 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3223
3224 if (pll == NULL)
3225 return;
3226
3227 if (pll->refcount == 0) {
3228 WARN(1, "bad PCH PLL refcount\n");
3229 return;
3230 }
3231
3232 --pll->refcount;
3233 intel_crtc->pch_pll = NULL;
3234}
3235
3236static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3237{
3238 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3239 struct intel_pch_pll *pll;
3240 int i;
3241
3242 pll = intel_crtc->pch_pll;
3243 if (pll) {
3244 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3245 intel_crtc->base.base.id, pll->pll_reg);
3246 goto prepare;
3247 }
3248
98b6bd99
DV		 3249 if (HAS_PCH_IBX(dev_priv->dev)) {
3250 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3251 i = intel_crtc->pipe;
3252 pll = &dev_priv->pch_plls[i];
3253
3254 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3255 intel_crtc->base.base.id, pll->pll_reg);
3256
3257 goto found;
3258 }
3259
ee7b9f93
JB		 3260 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3261 pll = &dev_priv->pch_plls[i];
3262
3263 /* Only want to check enabled timings first */
3264 if (pll->refcount == 0)
3265 continue;
3266
3267 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3268 fp == I915_READ(pll->fp0_reg)) {
3269 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3270 intel_crtc->base.base.id,
3271 pll->pll_reg, pll->refcount, pll->active);
3272
3273 goto found;
3274 }
3275 }
3276
3277 /* Ok no matching timings, maybe there's a free one? */
3278 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3279 pll = &dev_priv->pch_plls[i];
3280 if (pll->refcount == 0) {
3281 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3282 intel_crtc->base.base.id, pll->pll_reg);
3283 goto found;
3284 }
3285 }
3286
3287 return NULL;
3288
3289found:
3290 intel_crtc->pch_pll = pll;
3291 pll->refcount++;
84f44ce7 3292 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3293prepare: /* separate function? */
3294 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3295
e04c7350
CW		 3296 /* Wait for the clocks to stabilize before rewriting the regs */
3297 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3298 POSTING_READ(pll->pll_reg);
3299 udelay(150);
e04c7350
CW		 3300
3301 I915_WRITE(pll->fp0_reg, fp);
3302 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3303 pll->on = false;
3304 return pll;
3305}
3306
d4270e57
JB		 3307void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3308{
3309 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3310 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3311 u32 temp;
3312
3313 temp = I915_READ(dslreg);
3314 udelay(500);
3315 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3316 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3317 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3318 }
3319}
3320
f67a559d
JB		 3321static void ironlake_crtc_enable(struct drm_crtc *crtc)
3322{
3323 struct drm_device *dev = crtc->dev;
3324 struct drm_i915_private *dev_priv = dev->dev_private;
3325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3326 struct intel_encoder *encoder;
f67a559d
JB		 3327 int pipe = intel_crtc->pipe;
3328 int plane = intel_crtc->plane;
3329 u32 temp;
f67a559d 3330
08a48469
DV		 3331 WARN_ON(!crtc->enabled);
3332
f67a559d
JB		 3333 if (intel_crtc->active)
3334 return;
3335
3336 intel_crtc->active = true;
8664281b
PZ		 3337
3338 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3339 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3340
f67a559d
JB		 3341 intel_update_watermarks(dev);
3342
3343 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3344 temp = I915_READ(PCH_LVDS);
3345 if ((temp & LVDS_PORT_EN) == 0)
3346 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3347 }
3348
f67a559d 3349
5bfe2ac0 3350 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3351 /* Note: FDI PLL enabling _must_ be done before we enable the
3352 * cpu pipes, hence this is separate from all the other fdi/pch
3353 * enabling. */
88cefb6c 3354 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3355 } else {
3356 assert_fdi_tx_disabled(dev_priv, pipe);
3357 assert_fdi_rx_disabled(dev_priv, pipe);
3358 }
f67a559d 3359
bf49ec8c
DV		 3360 for_each_encoder_on_crtc(dev, crtc, encoder)
3361 if (encoder->pre_enable)
3362 encoder->pre_enable(encoder);
f67a559d
JB		 3363
3364 /* Enable panel fitting for LVDS */
3365 if (dev_priv->pch_pf_size &&
547dc041
JN		 3366 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3367 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3368 /* Force use of hard-coded filter coefficients
3369 * as some pre-programmed values are broken,
3370 * e.g. x201.
3371 */
13888d78
PZ		 3372 if (IS_IVYBRIDGE(dev))
3373 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3374 PF_PIPE_SEL_IVB(pipe));
3375 else
3376 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3377 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3378 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3379 }
3380
9c54c0dd
JB		 3381 /*
3382 * On ILK+ LUT must be loaded before the pipe is running but with
3383 * clocks enabled
3384 */
3385 intel_crtc_load_lut(crtc);
3386
5bfe2ac0
DV		 3387 intel_enable_pipe(dev_priv, pipe,
3388 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3389 intel_enable_plane(dev_priv, plane, pipe);
3390
5bfe2ac0 3391 if (intel_crtc->config.has_pch_encoder)
f67a559d 3392 ironlake_pch_enable(crtc);
c98e9dcf 3393
d1ebd816 3394 mutex_lock(&dev->struct_mutex);
bed4a673 3395 intel_update_fbc(dev);
d1ebd816
BW		 3396 mutex_unlock(&dev->struct_mutex);
3397
6b383a7f 3398 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3399
fa5c73b1
DV		 3400 for_each_encoder_on_crtc(dev, crtc, encoder)
3401 encoder->enable(encoder);
61b77ddd
DV		 3402
3403 if (HAS_PCH_CPT(dev))
3404 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3405
3406 /*
3407 * There seems to be a race in PCH platform hw (at least on some
3408 * outputs) where an enabled pipe still completes any pageflip right
3409 * away (as if the pipe is off) instead of waiting for vblank. As soon
3410 * as the first vblank happend, everything works as expected. Hence just
3411 * wait for one vblank before returning to avoid strange things
3412 * happening.
3413 */
3414 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3415}
3416
4f771f10
PZ		 3417static void haswell_crtc_enable(struct drm_crtc *crtc)
3418{
3419 struct drm_device *dev = crtc->dev;
3420 struct drm_i915_private *dev_priv = dev->dev_private;
3421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3422 struct intel_encoder *encoder;
3423 int pipe = intel_crtc->pipe;
3424 int plane = intel_crtc->plane;
4f771f10
PZ		 3425
3426 WARN_ON(!crtc->enabled);
3427
3428 if (intel_crtc->active)
3429 return;
3430
3431 intel_crtc->active = true;
8664281b
PZ		 3432
3433 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3434 if (intel_crtc->config.has_pch_encoder)
3435 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3436
4f771f10
PZ		 3437 intel_update_watermarks(dev);
3438
5bfe2ac0 3439 if (intel_crtc->config.has_pch_encoder)
04945641 3440 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3441
3442 for_each_encoder_on_crtc(dev, crtc, encoder)
3443 if (encoder->pre_enable)
3444 encoder->pre_enable(encoder);
3445
1f544388 3446 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3447
1f544388 3448 /* Enable panel fitting for eDP */
547dc041
JN		 3449 if (dev_priv->pch_pf_size &&
3450 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3451 /* Force use of hard-coded filter coefficients
3452 * as some pre-programmed values are broken,
3453 * e.g. x201.
3454 */
54075a7d
PZ		 3455 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3456 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3457 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3458 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3459 }
3460
3461 /*
3462 * On ILK+ LUT must be loaded before the pipe is running but with
3463 * clocks enabled
3464 */
3465 intel_crtc_load_lut(crtc);
3466
1f544388 3467 intel_ddi_set_pipe_settings(crtc);
8228c251 3468 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3469
5bfe2ac0
DV		 3470 intel_enable_pipe(dev_priv, pipe,
3471 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3472 intel_enable_plane(dev_priv, plane, pipe);
3473
5bfe2ac0 3474 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3475 lpt_pch_enable(crtc);
4f771f10
PZ		 3476
3477 mutex_lock(&dev->struct_mutex);
3478 intel_update_fbc(dev);
3479 mutex_unlock(&dev->struct_mutex);
3480
3481 intel_crtc_update_cursor(crtc, true);
3482
3483 for_each_encoder_on_crtc(dev, crtc, encoder)
3484 encoder->enable(encoder);
3485
4f771f10
PZ		 3486 /*
3487 * There seems to be a race in PCH platform hw (at least on some
3488 * outputs) where an enabled pipe still completes any pageflip right
3489 * away (as if the pipe is off) instead of waiting for vblank. As soon
3490 * as the first vblank happend, everything works as expected. Hence just
3491 * wait for one vblank before returning to avoid strange things
3492 * happening.
3493 */
3494 intel_wait_for_vblank(dev, intel_crtc->pipe);
3495}
3496
6be4a607
JB		 3497static void ironlake_crtc_disable(struct drm_crtc *crtc)
3498{
3499 struct drm_device *dev = crtc->dev;
3500 struct drm_i915_private *dev_priv = dev->dev_private;
3501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3502 struct intel_encoder *encoder;
6be4a607
JB		 3503 int pipe = intel_crtc->pipe;
3504 int plane = intel_crtc->plane;
5eddb70b 3505 u32 reg, temp;
b52eb4dc 3506
ef9c3aee 3507
f7abfe8b
CW		 3508 if (!intel_crtc->active)
3509 return;
3510
ea9d758d
DV		 3511 for_each_encoder_on_crtc(dev, crtc, encoder)
3512 encoder->disable(encoder);
3513
e6c3a2a6 3514 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3515 drm_vblank_off(dev, pipe);
6b383a7f 3516 intel_crtc_update_cursor(crtc, false);
5eddb70b 3517
b24e7179 3518 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3519
973d04f9
CW		 3520 if (dev_priv->cfb_plane == plane)
3521 intel_disable_fbc(dev);
2c07245f 3522
8664281b 3523 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3524 intel_disable_pipe(dev_priv, pipe);
32f9d658 3525
6be4a607 3526 /* Disable PF */
9db4a9c7
JB		 3527 I915_WRITE(PF_CTL(pipe), 0);
3528 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3529
bf49ec8c
DV		 3530 for_each_encoder_on_crtc(dev, crtc, encoder)
3531 if (encoder->post_disable)
3532 encoder->post_disable(encoder);
2c07245f 3533
0fc932b8 3534 ironlake_fdi_disable(crtc);
249c0e64 3535
b8a4f404 3536 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3537 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3538
6be4a607
JB		 3539 if (HAS_PCH_CPT(dev)) {
3540 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3541 reg = TRANS_DP_CTL(pipe);
3542 temp = I915_READ(reg);
3543 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3544 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3545 I915_WRITE(reg, temp);
6be4a607
JB		 3546
3547 /* disable DPLL_SEL */
3548 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3549 switch (pipe) {
3550 case 0:
d64311ab 3551 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3552 break;
3553 case 1:
6be4a607 3554 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3555 break;
3556 case 2:
4b645f14 3557 /* C shares PLL A or B */
d64311ab 3558 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3559 break;
3560 default:
3561 BUG(); /* wtf */
3562 }
6be4a607 3563 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3564 }
e3421a18 3565
6be4a607 3566 /* disable PCH DPLL */
ee7b9f93 3567 intel_disable_pch_pll(intel_crtc);
8db9d77b 3568
88cefb6c 3569 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3570
f7abfe8b 3571 intel_crtc->active = false;
6b383a7f 3572 intel_update_watermarks(dev);
d1ebd816
BW		 3573
3574 mutex_lock(&dev->struct_mutex);
6b383a7f 3575 intel_update_fbc(dev);
d1ebd816 3576 mutex_unlock(&dev->struct_mutex);
6be4a607 3577}
1b3c7a47 3578
4f771f10 3579static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3580{
4f771f10
PZ		 3581 struct drm_device *dev = crtc->dev;
3582 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3584 struct intel_encoder *encoder;
3585 int pipe = intel_crtc->pipe;
3586 int plane = intel_crtc->plane;
3b117c8f 3587 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3588
4f771f10
PZ		 3589 if (!intel_crtc->active)
3590 return;
3591
3592 for_each_encoder_on_crtc(dev, crtc, encoder)
3593 encoder->disable(encoder);
3594
3595 intel_crtc_wait_for_pending_flips(crtc);
3596 drm_vblank_off(dev, pipe);
3597 intel_crtc_update_cursor(crtc, false);
3598
3599 intel_disable_plane(dev_priv, plane, pipe);
3600
3601 if (dev_priv->cfb_plane == plane)
3602 intel_disable_fbc(dev);
3603
8664281b
PZ		 3604 if (intel_crtc->config.has_pch_encoder)
3605 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3606 intel_disable_pipe(dev_priv, pipe);
3607
ad80a810 3608 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3609
f7708f78
PZ		 3610 /* XXX: Once we have proper panel fitter state tracking implemented with
3611 * hardware state read/check support we should switch to only disable
3612 * the panel fitter when we know it's used. */
3613 if (intel_using_power_well(dev)) {
3614 I915_WRITE(PF_CTL(pipe), 0);
3615 I915_WRITE(PF_WIN_SZ(pipe), 0);
3616 }
4f771f10 3617
1f544388 3618 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3619
3620 for_each_encoder_on_crtc(dev, crtc, encoder)
3621 if (encoder->post_disable)
3622 encoder->post_disable(encoder);
3623
88adfff1 3624 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3625 lpt_disable_pch_transcoder(dev_priv);
8664281b 3626 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3627 intel_ddi_fdi_disable(crtc);
83616634 3628 }
4f771f10
PZ		 3629
3630 intel_crtc->active = false;
3631 intel_update_watermarks(dev);
3632
3633 mutex_lock(&dev->struct_mutex);
3634 intel_update_fbc(dev);
3635 mutex_unlock(&dev->struct_mutex);
3636}
3637
ee7b9f93
JB		 3638static void ironlake_crtc_off(struct drm_crtc *crtc)
3639{
3640 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3641 intel_put_pch_pll(intel_crtc);
3642}
3643
6441ab5f
PZ		 3644static void haswell_crtc_off(struct drm_crtc *crtc)
3645{
a5c961d1
PZ		 3646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3647
3648 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3649 * start using it. */
3b117c8f 3650 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3651
6441ab5f
PZ		 3652 intel_ddi_put_crtc_pll(crtc);
3653}
3654
02e792fb
DV		 3655static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3656{
02e792fb 3657 if (!enable && intel_crtc->overlay) {
23f09ce3 3658 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3659 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3660
23f09ce3 3661 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3662 dev_priv->mm.interruptible = false;
3663 (void) intel_overlay_switch_off(intel_crtc->overlay);
3664 dev_priv->mm.interruptible = true;
23f09ce3 3665 mutex_unlock(&dev->struct_mutex);
02e792fb 3666 }
02e792fb 3667
5dcdbcb0
CW		 3668 /* Let userspace switch the overlay on again. In most cases userspace
3669 * has to recompute where to put it anyway.
3670 */
02e792fb
DV		 3671}
3672
61bc95c1
EE		 3673/**
3674 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3675 * cursor plane briefly if not already running after enabling the display
3676 * plane.
3677 * This workaround avoids occasional blank screens when self refresh is
3678 * enabled.
3679 */
3680static void
3681g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3682{
3683 u32 cntl = I915_READ(CURCNTR(pipe));
3684
3685 if ((cntl & CURSOR_MODE) == 0) {
3686 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3687
3688 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3689 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3690 intel_wait_for_vblank(dev_priv->dev, pipe);
3691 I915_WRITE(CURCNTR(pipe), cntl);
3692 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3693 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3694 }
3695}
3696
89b667f8
JB		 3697static void valleyview_crtc_enable(struct drm_crtc *crtc)
3698{
3699 struct drm_device *dev = crtc->dev;
3700 struct drm_i915_private *dev_priv = dev->dev_private;
3701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3702 struct intel_encoder *encoder;
3703 int pipe = intel_crtc->pipe;
3704 int plane = intel_crtc->plane;
3705
3706 WARN_ON(!crtc->enabled);
3707
3708 if (intel_crtc->active)
3709 return;
3710
3711 intel_crtc->active = true;
3712 intel_update_watermarks(dev);
3713
3714 mutex_lock(&dev_priv->dpio_lock);
3715
3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 if (encoder->pre_pll_enable)
3718 encoder->pre_pll_enable(encoder);
3719
3720 intel_enable_pll(dev_priv, pipe);
3721
3722 for_each_encoder_on_crtc(dev, crtc, encoder)
3723 if (encoder->pre_enable)
3724 encoder->pre_enable(encoder);
3725
3726 /* VLV wants encoder enabling _before_ the pipe is up. */
3727 for_each_encoder_on_crtc(dev, crtc, encoder)
3728 encoder->enable(encoder);
3729
3730 intel_enable_pipe(dev_priv, pipe, false);
3731 intel_enable_plane(dev_priv, plane, pipe);
3732
3733 intel_crtc_load_lut(crtc);
3734 intel_update_fbc(dev);
3735
3736 /* Give the overlay scaler a chance to enable if it's on this pipe */
3737 intel_crtc_dpms_overlay(intel_crtc, true);
3738 intel_crtc_update_cursor(crtc, true);
3739
3740 mutex_unlock(&dev_priv->dpio_lock);
3741}
3742
0b8765c6 3743static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3744{
3745 struct drm_device *dev = crtc->dev;
79e53945
JB		 3746 struct drm_i915_private *dev_priv = dev->dev_private;
3747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3748 struct intel_encoder *encoder;
79e53945 3749 int pipe = intel_crtc->pipe;
80824003 3750 int plane = intel_crtc->plane;
79e53945 3751
08a48469
DV		 3752 WARN_ON(!crtc->enabled);
3753
f7abfe8b
CW		 3754 if (intel_crtc->active)
3755 return;
3756
3757 intel_crtc->active = true;
6b383a7f
CW		 3758 intel_update_watermarks(dev);
3759
63d7bbe9 3760 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3761
3762 for_each_encoder_on_crtc(dev, crtc, encoder)
3763 if (encoder->pre_enable)
3764 encoder->pre_enable(encoder);
3765
040484af 3766 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3767 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3768 if (IS_G4X(dev))
3769 g4x_fixup_plane(dev_priv, pipe);
79e53945 3770
0b8765c6 3771 intel_crtc_load_lut(crtc);
bed4a673 3772 intel_update_fbc(dev);
79e53945 3773
0b8765c6
JB		 3774 /* Give the overlay scaler a chance to enable if it's on this pipe */
3775 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3776 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3777
fa5c73b1
DV		 3778 for_each_encoder_on_crtc(dev, crtc, encoder)
3779 encoder->enable(encoder);
0b8765c6 3780}
79e53945 3781
87476d63
DV		 3782static void i9xx_pfit_disable(struct intel_crtc *crtc)
3783{
3784 struct drm_device *dev = crtc->base.dev;
3785 struct drm_i915_private *dev_priv = dev->dev_private;
3786 enum pipe pipe;
3787 uint32_t pctl = I915_READ(PFIT_CONTROL);
3788
3789 assert_pipe_disabled(dev_priv, crtc->pipe);
3790
3791 if (INTEL_INFO(dev)->gen >= 4)
3792 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3793 else
3794 pipe = PIPE_B;
3795
3796 if (pipe == crtc->pipe) {
3797 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3798 I915_WRITE(PFIT_CONTROL, 0);
3799 }
3800}
3801
0b8765c6
JB		 3802static void i9xx_crtc_disable(struct drm_crtc *crtc)
3803{
3804 struct drm_device *dev = crtc->dev;
3805 struct drm_i915_private *dev_priv = dev->dev_private;
3806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3807 struct intel_encoder *encoder;
0b8765c6
JB		 3808 int pipe = intel_crtc->pipe;
3809 int plane = intel_crtc->plane;
ef9c3aee 3810
f7abfe8b
CW		 3811 if (!intel_crtc->active)
3812 return;
3813
ea9d758d
DV		 3814 for_each_encoder_on_crtc(dev, crtc, encoder)
3815 encoder->disable(encoder);
3816
0b8765c6 3817 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3818 intel_crtc_wait_for_pending_flips(crtc);
3819 drm_vblank_off(dev, pipe);
0b8765c6 3820 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3821 intel_crtc_update_cursor(crtc, false);
0b8765c6 3822
973d04f9
CW		 3823 if (dev_priv->cfb_plane == plane)
3824 intel_disable_fbc(dev);
79e53945 3825
b24e7179 3826 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3827 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3828
87476d63 3829 i9xx_pfit_disable(intel_crtc);
24a1f16d 3830
89b667f8
JB		 3831 for_each_encoder_on_crtc(dev, crtc, encoder)
3832 if (encoder->post_disable)
3833 encoder->post_disable(encoder);
3834
63d7bbe9 3835 intel_disable_pll(dev_priv, pipe);
0b8765c6 3836
f7abfe8b 3837 intel_crtc->active = false;
6b383a7f
CW		 3838 intel_update_fbc(dev);
3839 intel_update_watermarks(dev);
0b8765c6
JB		 3840}
3841
ee7b9f93
JB		 3842static void i9xx_crtc_off(struct drm_crtc *crtc)
3843{
3844}
3845
976f8a20
DV		 3846static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3847 bool enabled)
2c07245f
ZW		 3848{
3849 struct drm_device *dev = crtc->dev;
3850 struct drm_i915_master_private *master_priv;
3851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3852 int pipe = intel_crtc->pipe;
79e53945
JB		 3853
3854 if (!dev->primary->master)
3855 return;
3856
3857 master_priv = dev->primary->master->driver_priv;
3858 if (!master_priv->sarea_priv)
3859 return;
3860
79e53945
JB		 3861 switch (pipe) {
3862 case 0:
3863 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3864 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3865 break;
3866 case 1:
3867 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3868 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3869 break;
3870 default:
9db4a9c7 3871 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3872 break;
3873 }
79e53945
JB		 3874}
3875
976f8a20
DV		 3876/**
3877 * Sets the power management mode of the pipe and plane.
3878 */
3879void intel_crtc_update_dpms(struct drm_crtc *crtc)
3880{
3881 struct drm_device *dev = crtc->dev;
3882 struct drm_i915_private *dev_priv = dev->dev_private;
3883 struct intel_encoder *intel_encoder;
3884 bool enable = false;
3885
3886 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3887 enable |= intel_encoder->connectors_active;
3888
3889 if (enable)
3890 dev_priv->display.crtc_enable(crtc);
3891 else
3892 dev_priv->display.crtc_disable(crtc);
3893
3894 intel_crtc_update_sarea(crtc, enable);
3895}
3896
cdd59983
CW		 3897static void intel_crtc_disable(struct drm_crtc *crtc)
3898{
cdd59983 3899 struct drm_device *dev = crtc->dev;
976f8a20 3900 struct drm_connector *connector;
ee7b9f93 3901 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3903
976f8a20
DV		 3904 /* crtc should still be enabled when we disable it. */
3905 WARN_ON(!crtc->enabled);
3906
7b9f35a6 3907 intel_crtc->eld_vld = false;
976f8a20
DV		 3908 dev_priv->display.crtc_disable(crtc);
3909 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3910 dev_priv->display.off(crtc);
3911
931872fc
CW		 3912 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3913 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3914
3915 if (crtc->fb) {
3916 mutex_lock(&dev->struct_mutex);
1690e1eb 3917 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3918 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3919 crtc->fb = NULL;
3920 }
3921
3922 /* Update computed state. */
3923 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3924 if (!connector->encoder || !connector->encoder->crtc)
3925 continue;
3926
3927 if (connector->encoder->crtc != crtc)
3928 continue;
3929
3930 connector->dpms = DRM_MODE_DPMS_OFF;
3931 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3932 }
3933}
3934
a261b246 3935void intel_modeset_disable(struct drm_device *dev)
79e53945 3936{
a261b246
DV		 3937 struct drm_crtc *crtc;
3938
3939 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3940 if (crtc->enabled)
3941 intel_crtc_disable(crtc);
3942 }
79e53945
JB		 3943}
3944
ea5b213a 3945void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3946{
4ef69c7a 3947 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3948
ea5b213a
CW		 3949 drm_encoder_cleanup(encoder);
3950 kfree(intel_encoder);
7e7d76c3
JB		 3951}
3952
5ab432ef
DV		 3953/* Simple dpms helper for encodres with just one connector, no cloning and only
3954 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3955 * state of the entire output pipe. */
3956void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3957{
5ab432ef
DV		 3958 if (mode == DRM_MODE_DPMS_ON) {
3959 encoder->connectors_active = true;
3960
b2cabb0e 3961 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3962 } else {
3963 encoder->connectors_active = false;
3964
b2cabb0e 3965 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3966 }
79e53945
JB		 3967}
3968
0a91ca29
DV		 3969/* Cross check the actual hw state with our own modeset state tracking (and it's
3970 * internal consistency). */
b980514c 3971static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3972{
0a91ca29
DV		 3973 if (connector->get_hw_state(connector)) {
3974 struct intel_encoder *encoder = connector->encoder;
3975 struct drm_crtc *crtc;
3976 bool encoder_enabled;
3977 enum pipe pipe;
3978
3979 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3980 connector->base.base.id,
3981 drm_get_connector_name(&connector->base));
3982
3983 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3984 "wrong connector dpms state\n");
3985 WARN(connector->base.encoder != &encoder->base,
3986 "active connector not linked to encoder\n");
3987 WARN(!encoder->connectors_active,
3988 "encoder->connectors_active not set\n");
3989
3990 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3991 WARN(!encoder_enabled, "encoder not enabled\n");
3992 if (WARN_ON(!encoder->base.crtc))
3993 return;
3994
3995 crtc = encoder->base.crtc;
3996
3997 WARN(!crtc->enabled, "crtc not enabled\n");
3998 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3999 WARN(pipe != to_intel_crtc(crtc)->pipe,
4000 "encoder active on the wrong pipe\n");
4001 }
79e53945
JB		 4002}
4003
5ab432ef
DV		 4004/* Even simpler default implementation, if there's really no special case to
4005 * consider. */
4006void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4007{
5ab432ef 4008 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 4009
5ab432ef
DV		 4010 /* All the simple cases only support two dpms states. */
4011 if (mode != DRM_MODE_DPMS_ON)
4012 mode = DRM_MODE_DPMS_OFF;
d4270e57 4013
5ab432ef
DV		 4014 if (mode == connector->dpms)
4015 return;
4016
4017 connector->dpms = mode;
4018
4019 /* Only need to change hw state when actually enabled */
4020 if (encoder->base.crtc)
4021 intel_encoder_dpms(encoder, mode);
4022 else
8af6cf88 4023 WARN_ON(encoder->connectors_active != false);
0a91ca29 4024
b980514c 4025 intel_modeset_check_state(connector->dev);
79e53945
JB		 4026}
4027
f0947c37
DV		 4028/* Simple connector->get_hw_state implementation for encoders that support only
4029 * one connector and no cloning and hence the encoder state determines the state
4030 * of the connector. */
4031bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4032{
24929352 4033 enum pipe pipe = 0;
f0947c37 4034 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4035
f0947c37 4036 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4037}
4038
b8cecdf5
DV		 4039static bool intel_crtc_compute_config(struct drm_crtc *crtc,
4040 struct intel_crtc_config *pipe_config)
79e53945 4041{
2c07245f 4042 struct drm_device *dev = crtc->dev;
b8cecdf5 4043 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4044
bad720ff 4045 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4046 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4047 if (pipe_config->requested_mode.clock * 3
4048 > IRONLAKE_FDI_FREQ * 4)
2377b741 4049 return false;
2c07245f 4050 }
89749350 4051
f9bef081
DV		 4052 /* All interlaced capable intel hw wants timings in frames. Note though
4053 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4054 * timings, so we need to be careful not to clobber these.*/
7ae89233 4055 if (!pipe_config->timings_set)
f9bef081 4056 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4057
44f46b42
CW		 4058 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4059 * with a hsync front porch of 0.
4060 */
4061 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4062 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4063 return false;
4064
bd080ee5 4065 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4066 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4067 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4068 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4069 * for lvds. */
4070 pipe_config->pipe_bpp = 8*3;
4071 }
4072
79e53945
JB		 4073 return true;
4074}
4075
25eb05fc
JB		 4076static int valleyview_get_display_clock_speed(struct drm_device *dev)
4077{
4078 return 400000; /* FIXME */
4079}
4080
e70236a8
JB		 4081static int i945_get_display_clock_speed(struct drm_device *dev)
4082{
4083 return 400000;
4084}
79e53945 4085
e70236a8 4086static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4087{
e70236a8
JB		 4088 return 333000;
4089}
79e53945 4090
e70236a8
JB		 4091static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4092{
4093 return 200000;
4094}
79e53945 4095
e70236a8
JB		 4096static int i915gm_get_display_clock_speed(struct drm_device *dev)
4097{
4098 u16 gcfgc = 0;
79e53945 4099
e70236a8
JB		 4100 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4101
4102 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4103 return 133000;
4104 else {
4105 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4106 case GC_DISPLAY_CLOCK_333_MHZ:
4107 return 333000;
4108 default:
4109 case GC_DISPLAY_CLOCK_190_200_MHZ:
4110 return 190000;
79e53945 4111 }
e70236a8
JB		 4112 }
4113}
4114
4115static int i865_get_display_clock_speed(struct drm_device *dev)
4116{
4117 return 266000;
4118}
4119
4120static int i855_get_display_clock_speed(struct drm_device *dev)
4121{
4122 u16 hpllcc = 0;
4123 /* Assume that the hardware is in the high speed state. This
4124 * should be the default.
4125 */
4126 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4127 case GC_CLOCK_133_200:
4128 case GC_CLOCK_100_200:
4129 return 200000;
4130 case GC_CLOCK_166_250:
4131 return 250000;
4132 case GC_CLOCK_100_133:
79e53945 4133 return 133000;
e70236a8 4134 }
79e53945 4135
e70236a8
JB		 4136 /* Shouldn't happen */
4137 return 0;
4138}
79e53945 4139
e70236a8
JB		 4140static int i830_get_display_clock_speed(struct drm_device *dev)
4141{
4142 return 133000;
79e53945
JB		 4143}
4144
2c07245f 4145static void
e69d0bc1 4146intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4147{
4148 while (*num > 0xffffff || *den > 0xffffff) {
4149 *num >>= 1;
4150 *den >>= 1;
4151 }
4152}
4153
e69d0bc1
DV		 4154void
4155intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4156 int pixel_clock, int link_clock,
4157 struct intel_link_m_n *m_n)
2c07245f 4158{
e69d0bc1 4159 m_n->tu = 64;
22ed1113
CW		 4160 m_n->gmch_m = bits_per_pixel * pixel_clock;
4161 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4162 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4163 m_n->link_m = pixel_clock;
4164 m_n->link_n = link_clock;
e69d0bc1 4165 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4166}
4167
a7615030
CW		 4168static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4169{
72bbe58c
KP		 4170 if (i915_panel_use_ssc >= 0)
4171 return i915_panel_use_ssc != 0;
4172 return dev_priv->lvds_use_ssc
435793df 4173 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4174}
4175
a0c4da24
JB		 4176static int vlv_get_refclk(struct drm_crtc *crtc)
4177{
4178 struct drm_device *dev = crtc->dev;
4179 struct drm_i915_private *dev_priv = dev->dev_private;
4180 int refclk = 27000; /* for DP & HDMI */
4181
4182 return 100000; /* only one validated so far */
4183
4184 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4185 refclk = 96000;
4186 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4187 if (intel_panel_use_ssc(dev_priv))
4188 refclk = 100000;
4189 else
4190 refclk = 96000;
4191 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4192 refclk = 100000;
4193 }
4194
4195 return refclk;
4196}
4197
c65d77d8
JB		 4198static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4199{
4200 struct drm_device *dev = crtc->dev;
4201 struct drm_i915_private *dev_priv = dev->dev_private;
4202 int refclk;
4203
a0c4da24
JB		 4204 if (IS_VALLEYVIEW(dev)) {
4205 refclk = vlv_get_refclk(crtc);
4206 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4207 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4208 refclk = dev_priv->lvds_ssc_freq * 1000;
4209 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4210 refclk / 1000);
4211 } else if (!IS_GEN2(dev)) {
4212 refclk = 96000;
4213 } else {
4214 refclk = 48000;
4215 }
4216
4217 return refclk;
4218}
4219
f47709a9 4220static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
c65d77d8 4221{
f47709a9
DV		 4222 unsigned dotclock = crtc->config.adjusted_mode.clock;
4223 struct dpll *clock = &crtc->config.dpll;
4224
c65d77d8
JB		 4225 /* SDVO TV has fixed PLL values depend on its clock range,
4226 this mirrors vbios setting. */
f47709a9 4227 if (dotclock >= 100000 && dotclock < 140500) {
c65d77d8
JB		 4228 clock->p1 = 2;
4229 clock->p2 = 10;
4230 clock->n = 3;
4231 clock->m1 = 16;
4232 clock->m2 = 8;
f47709a9 4233 } else if (dotclock >= 140500 && dotclock <= 200000) {
c65d77d8
JB		 4234 clock->p1 = 1;
4235 clock->p2 = 10;
4236 clock->n = 6;
4237 clock->m1 = 12;
4238 clock->m2 = 8;
4239 }
f47709a9
DV		 4240
4241 crtc->config.clock_set = true;
c65d77d8
JB		 4242}
4243
f47709a9 4244static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4245 intel_clock_t *reduced_clock)
4246{
f47709a9 4247 struct drm_device *dev = crtc->base.dev;
a7516a05 4248 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4249 int pipe = crtc->pipe;
a7516a05 4250 u32 fp, fp2 = 0;
f47709a9 4251 struct dpll *clock = &crtc->config.dpll;
a7516a05
JB		 4252
4253 if (IS_PINEVIEW(dev)) {
4254 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4255 if (reduced_clock)
4256 fp2 = (1 << reduced_clock->n) << 16 |
4257 reduced_clock->m1 << 8 | reduced_clock->m2;
4258 } else {
4259 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4260 if (reduced_clock)
4261 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4262 reduced_clock->m2;
4263 }
4264
4265 I915_WRITE(FP0(pipe), fp);
4266
f47709a9
DV		 4267 crtc->lowfreq_avail = false;
4268 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4269 reduced_clock && i915_powersave) {
4270 I915_WRITE(FP1(pipe), fp2);
f47709a9 4271 crtc->lowfreq_avail = true;
a7516a05
JB		 4272 } else {
4273 I915_WRITE(FP1(pipe), fp);
4274 }
4275}
4276
89b667f8
JB		 4277static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4278{
4279 u32 reg_val;
4280
4281 /*
4282 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4283 * and set it to a reasonable value instead.
4284 */
4285 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4286 reg_val &= 0xffffff00;
4287 reg_val |= 0x00000030;
4288 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4289
4290 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4291 reg_val &= 0x8cffffff;
4292 reg_val = 0x8c000000;
4293 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4294
4295 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4296 reg_val &= 0xffffff00;
4297 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4298
4299 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4300 reg_val &= 0x00ffffff;
4301 reg_val |= 0xb0000000;
4302 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4303}
4304
03afc4a2
DV		 4305static void intel_dp_set_m_n(struct intel_crtc *crtc)
4306{
4307 if (crtc->config.has_pch_encoder)
4308 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4309 else
4310 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4311}
4312
f47709a9 4313static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4314{
f47709a9 4315 struct drm_device *dev = crtc->base.dev;
a0c4da24 4316 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8
JB		 4317 struct drm_display_mode *adjusted_mode =
4318 &crtc->config.adjusted_mode;
4319 struct intel_encoder *encoder;
f47709a9 4320 int pipe = crtc->pipe;
89b667f8 4321 u32 dpll, mdiv;
a0c4da24 4322 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8
JB		 4323 bool is_hdmi;
4324 u32 coreclk, reg_val, temp;
a0c4da24 4325
09153000
DV		 4326 mutex_lock(&dev_priv->dpio_lock);
4327
89b667f8 4328 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4329
f47709a9
DV		 4330 bestn = crtc->config.dpll.n;
4331 bestm1 = crtc->config.dpll.m1;
4332 bestm2 = crtc->config.dpll.m2;
4333 bestp1 = crtc->config.dpll.p1;
4334 bestp2 = crtc->config.dpll.p2;
a0c4da24 4335
89b667f8
JB		 4336 /* See eDP HDMI DPIO driver vbios notes doc */
4337
4338 /* PLL B needs special handling */
4339 if (pipe)
4340 vlv_pllb_recal_opamp(dev_priv);
4341
4342 /* Set up Tx target for periodic Rcomp update */
4343 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4344
4345 /* Disable target IRef on PLL */
4346 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4347 reg_val &= 0x00ffffff;
4348 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4349
4350 /* Disable fast lock */
4351 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4352
4353 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4354 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4355 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4356 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4357 mdiv |= (1 << DPIO_K_SHIFT);
89b667f8
JB		 4358 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
4359 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4360 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4361 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
a0c4da24
JB		 4362 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4363
89b667f8
JB		 4364 mdiv |= DPIO_ENABLE_CALIBRATION;
4365 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4366
89b667f8
JB		 4367 /* Set HBR and RBR LPF coefficients */
4368 if (adjusted_mode->clock == 162000 ||
4369 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4370 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4371 0x005f0021);
4372 else
4373 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4374 0x00d0000f);
4375
4376 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4377 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4378 /* Use SSC source */
4379 if (!pipe)
4380 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4381 0x0df40000);
4382 else
4383 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4384 0x0df70000);
4385 } else { /* HDMI or VGA */
4386 /* Use bend source */
4387 if (!pipe)
4388 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4389 0x0df70000);
4390 else
4391 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4392 0x0df40000);
4393 }
a0c4da24 4394
89b667f8
JB		 4395 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4396 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4397 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4398 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4399 coreclk |= 0x01000000;
4400 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4401
89b667f8 4402 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4403
89b667f8
JB		 4404 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4405 if (encoder->pre_pll_enable)
4406 encoder->pre_pll_enable(encoder);
2a8f64ca 4407
89b667f8
JB		 4408 /* Enable DPIO clock input */
4409 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4410 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4411 if (pipe)
4412 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4413
89b667f8 4414 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4415 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4416 POSTING_READ(DPLL(pipe));
4417 udelay(150);
a0c4da24 4418
89b667f8
JB		 4419 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4420 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4421
4422 if (is_hdmi) {
6cc5f341 4423 temp = 0;
f47709a9
DV		 4424 if (crtc->config.pixel_multiplier > 1) {
4425 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4426 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4427 }
a0c4da24 4428
89b667f8
JB		 4429 I915_WRITE(DPLL_MD(pipe), temp);
4430 POSTING_READ(DPLL_MD(pipe));
2a8f64ca 4431 }
f47709a9 4432
89b667f8
JB		 4433 if (crtc->config.has_dp_encoder)
4434 intel_dp_set_m_n(crtc);
09153000
DV		 4435
4436 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4437}
4438
f47709a9
DV		 4439static void i9xx_update_pll(struct intel_crtc *crtc,
4440 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4441 int num_connectors)
4442{
f47709a9 4443 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4444 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4445 struct intel_encoder *encoder;
f47709a9 4446 int pipe = crtc->pipe;
eb1cbe48
DV		 4447 u32 dpll;
4448 bool is_sdvo;
f47709a9 4449 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4450
f47709a9 4451 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4452
f47709a9
DV		 4453 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4454 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4455
4456 dpll = DPLL_VGA_MODE_DIS;
4457
f47709a9 4458 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4459 dpll |= DPLLB_MODE_LVDS;
4460 else
4461 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4462
eb1cbe48 4463 if (is_sdvo) {
f47709a9 4464 if ((crtc->config.pixel_multiplier > 1) &&
6cc5f341 4465 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
f47709a9 4466 dpll |= (crtc->config.pixel_multiplier - 1)
6cc5f341 4467 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48
DV		 4468 }
4469 dpll |= DPLL_DVO_HIGH_SPEED;
4470 }
f47709a9 4471 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4472 dpll |= DPLL_DVO_HIGH_SPEED;
4473
4474 /* compute bitmask from p1 value */
4475 if (IS_PINEVIEW(dev))
4476 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4477 else {
4478 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4479 if (IS_G4X(dev) && reduced_clock)
4480 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4481 }
4482 switch (clock->p2) {
4483 case 5:
4484 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4485 break;
4486 case 7:
4487 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4488 break;
4489 case 10:
4490 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4491 break;
4492 case 14:
4493 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4494 break;
4495 }
4496 if (INTEL_INFO(dev)->gen >= 4)
4497 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4498
f47709a9 4499 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48 4500 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4501 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48
DV		 4502 /* XXX: just matching BIOS for now */
4503 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4504 dpll |= 3;
f47709a9 4505 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4506 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4507 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4508 else
4509 dpll |= PLL_REF_INPUT_DREFCLK;
4510
4511 dpll |= DPLL_VCO_ENABLE;
4512 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4513 POSTING_READ(DPLL(pipe));
4514 udelay(150);
4515
f47709a9 4516 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4517 if (encoder->pre_pll_enable)
4518 encoder->pre_pll_enable(encoder);
eb1cbe48 4519
f47709a9
DV		 4520 if (crtc->config.has_dp_encoder)
4521 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4522
4523 I915_WRITE(DPLL(pipe), dpll);
4524
4525 /* Wait for the clocks to stabilize. */
4526 POSTING_READ(DPLL(pipe));
4527 udelay(150);
4528
4529 if (INTEL_INFO(dev)->gen >= 4) {
4530 u32 temp = 0;
4531 if (is_sdvo) {
6cc5f341 4532 temp = 0;
f47709a9
DV		 4533 if (crtc->config.pixel_multiplier > 1) {
4534 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4535 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4536 }
eb1cbe48
DV		 4537 }
4538 I915_WRITE(DPLL_MD(pipe), temp);
4539 } else {
4540 /* The pixel multiplier can only be updated once the
4541 * DPLL is enabled and the clocks are stable.
4542 *
4543 * So write it again.
4544 */
4545 I915_WRITE(DPLL(pipe), dpll);
4546 }
4547}
4548
f47709a9 4549static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4550 struct drm_display_mode *adjusted_mode,
f47709a9 4551 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4552 int num_connectors)
4553{
f47709a9 4554 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4555 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4556 struct intel_encoder *encoder;
f47709a9 4557 int pipe = crtc->pipe;
eb1cbe48 4558 u32 dpll;
f47709a9 4559 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4560
f47709a9 4561 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4562
eb1cbe48
DV		 4563 dpll = DPLL_VGA_MODE_DIS;
4564
f47709a9 4565 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4566 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4567 } else {
4568 if (clock->p1 == 2)
4569 dpll |= PLL_P1_DIVIDE_BY_TWO;
4570 else
4571 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4572 if (clock->p2 == 4)
4573 dpll |= PLL_P2_DIVIDE_BY_4;
4574 }
4575
f47709a9 4576 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4577 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4578 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4579 else
4580 dpll |= PLL_REF_INPUT_DREFCLK;
4581
4582 dpll |= DPLL_VCO_ENABLE;
4583 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4584 POSTING_READ(DPLL(pipe));
4585 udelay(150);
4586
f47709a9 4587 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4588 if (encoder->pre_pll_enable)
4589 encoder->pre_pll_enable(encoder);
eb1cbe48 4590
5b5896e4
DV		 4591 I915_WRITE(DPLL(pipe), dpll);
4592
4593 /* Wait for the clocks to stabilize. */
4594 POSTING_READ(DPLL(pipe));
4595 udelay(150);
4596
eb1cbe48
DV		 4597 /* The pixel multiplier can only be updated once the
4598 * DPLL is enabled and the clocks are stable.
4599 *
4600 * So write it again.
4601 */
4602 I915_WRITE(DPLL(pipe), dpll);
4603}
4604
b0e77b9c
PZ		 4605static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4606 struct drm_display_mode *mode,
4607 struct drm_display_mode *adjusted_mode)
4608{
4609 struct drm_device *dev = intel_crtc->base.dev;
4610 struct drm_i915_private *dev_priv = dev->dev_private;
4611 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4612 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
b0e77b9c
PZ		 4613 uint32_t vsyncshift;
4614
4615 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4616 /* the chip adds 2 halflines automatically */
4617 adjusted_mode->crtc_vtotal -= 1;
4618 adjusted_mode->crtc_vblank_end -= 1;
4619 vsyncshift = adjusted_mode->crtc_hsync_start
4620 - adjusted_mode->crtc_htotal / 2;
4621 } else {
4622 vsyncshift = 0;
4623 }
4624
4625 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4626 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4627
fe2b8f9d 4628 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4629 (adjusted_mode->crtc_hdisplay - 1) |
4630 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4631 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4632 (adjusted_mode->crtc_hblank_start - 1) |
4633 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4634 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4635 (adjusted_mode->crtc_hsync_start - 1) |
4636 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4637
fe2b8f9d 4638 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4639 (adjusted_mode->crtc_vdisplay - 1) |
4640 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4641 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4642 (adjusted_mode->crtc_vblank_start - 1) |
4643 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4644 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4645 (adjusted_mode->crtc_vsync_start - 1) |
4646 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4647
b5e508d4
PZ		 4648 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4649 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4650 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4651 * bits. */
4652 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4653 (pipe == PIPE_B || pipe == PIPE_C))
4654 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4655
b0e77b9c
PZ		 4656 /* pipesrc controls the size that is scaled from, which should
4657 * always be the user's requested size.
4658 */
4659 I915_WRITE(PIPESRC(pipe),
4660 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4661}
4662
84b046f3
DV		 4663static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4664{
4665 struct drm_device *dev = intel_crtc->base.dev;
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667 uint32_t pipeconf;
4668
4669 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4670
4671 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4672 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4673 * core speed.
4674 *
4675 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4676 * pipe == 0 check?
4677 */
4678 if (intel_crtc->config.requested_mode.clock >
4679 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4680 pipeconf |= PIPECONF_DOUBLE_WIDE;
4681 else
4682 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4683 }
4684
4685 /* default to 8bpc */
4686 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4687 if (intel_crtc->config.has_dp_encoder) {
4688 if (intel_crtc->config.dither) {
4689 pipeconf |= PIPECONF_6BPC |
4690 PIPECONF_DITHER_EN |
4691 PIPECONF_DITHER_TYPE_SP;
4692 }
4693 }
4694
4695 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
4696 INTEL_OUTPUT_EDP)) {
4697 if (intel_crtc->config.dither) {
4698 pipeconf |= PIPECONF_6BPC |
4699 PIPECONF_ENABLE |
4700 I965_PIPECONF_ACTIVE;
4701 }
4702 }
4703
4704 if (HAS_PIPE_CXSR(dev)) {
4705 if (intel_crtc->lowfreq_avail) {
4706 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4707 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4708 } else {
4709 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4710 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4711 }
4712 }
4713
4714 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4715 if (!IS_GEN2(dev) &&
4716 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4717 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4718 else
4719 pipeconf |= PIPECONF_PROGRESSIVE;
4720
9c8e09b7
VS		 4721 if (IS_VALLEYVIEW(dev)) {
4722 if (intel_crtc->config.limited_color_range)
4723 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4724 else
4725 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4726 }
4727
84b046f3
DV		 4728 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4729 POSTING_READ(PIPECONF(intel_crtc->pipe));
4730}
4731
f564048e 4732static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4733 int x, int y,
94352cf9 4734 struct drm_framebuffer *fb)
79e53945
JB		 4735{
4736 struct drm_device *dev = crtc->dev;
4737 struct drm_i915_private *dev_priv = dev->dev_private;
4738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4739 struct drm_display_mode *adjusted_mode =
4740 &intel_crtc->config.adjusted_mode;
4741 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4742 int pipe = intel_crtc->pipe;
80824003 4743 int plane = intel_crtc->plane;
c751ce4f 4744 int refclk, num_connectors = 0;
652c393a 4745 intel_clock_t clock, reduced_clock;
84b046f3 4746 u32 dspcntr;
eb1cbe48 4747 bool ok, has_reduced_clock = false, is_sdvo = false;
8b47047b 4748 bool is_lvds = false, is_tv = false;
5eddb70b 4749 struct intel_encoder *encoder;
d4906093 4750 const intel_limit_t *limit;
5c3b82e2 4751 int ret;
79e53945 4752
6c2b7c12 4753 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4754 switch (encoder->type) {
79e53945
JB		 4755 case INTEL_OUTPUT_LVDS:
4756 is_lvds = true;
4757 break;
4758 case INTEL_OUTPUT_SDVO:
7d57382e 4759 case INTEL_OUTPUT_HDMI:
79e53945 4760 is_sdvo = true;
5eddb70b 4761 if (encoder->needs_tv_clock)
e2f0ba97 4762 is_tv = true;
79e53945 4763 break;
79e53945
JB		 4764 case INTEL_OUTPUT_TVOUT:
4765 is_tv = true;
4766 break;
79e53945 4767 }
43565a06 4768
c751ce4f 4769 num_connectors++;
79e53945
JB		 4770 }
4771
c65d77d8 4772 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4773
d4906093
ML		 4774 /*
4775 * Returns a set of divisors for the desired target clock with the given
4776 * refclk, or FALSE. The returned values represent the clock equation:
4777 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4778 */
1b894b59 4779 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4780 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4781 &clock);
79e53945
JB		 4782 if (!ok) {
4783 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4784 return -EINVAL;
79e53945
JB		 4785 }
4786
cda4b7d3 4787 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4788 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4789
ddc9003c 4790 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4791 /*
4792 * Ensure we match the reduced clock's P to the target clock.
4793 * If the clocks don't match, we can't switch the display clock
4794 * by using the FP0/FP1. In such case we will disable the LVDS
4795 * downclock feature.
4796 */
ddc9003c 4797 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4798 dev_priv->lvds_downclock,
4799 refclk,
cec2f356 4800 &clock,
5eddb70b 4801 &reduced_clock);
7026d4ac 4802 }
f47709a9
DV		 4803 /* Compat-code for transition, will disappear. */
4804 if (!intel_crtc->config.clock_set) {
4805 intel_crtc->config.dpll.n = clock.n;
4806 intel_crtc->config.dpll.m1 = clock.m1;
4807 intel_crtc->config.dpll.m2 = clock.m2;
4808 intel_crtc->config.dpll.p1 = clock.p1;
4809 intel_crtc->config.dpll.p2 = clock.p2;
4810 }
7026d4ac 4811
c65d77d8 4812 if (is_sdvo && is_tv)
f47709a9 4813 i9xx_adjust_sdvo_tv_clock(intel_crtc);
7026d4ac 4814
eb1cbe48 4815 if (IS_GEN2(dev))
f47709a9 4816 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4817 has_reduced_clock ? &reduced_clock : NULL,
4818 num_connectors);
a0c4da24 4819 else if (IS_VALLEYVIEW(dev))
f47709a9 4820 vlv_update_pll(intel_crtc);
79e53945 4821 else
f47709a9 4822 i9xx_update_pll(intel_crtc,
eb1cbe48 4823 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4824 num_connectors);
79e53945 4825
79e53945
JB		 4826 /* Set up the display plane register */
4827 dspcntr = DISPPLANE_GAMMA_ENABLE;
4828
da6ecc5d
JB		 4829 if (!IS_VALLEYVIEW(dev)) {
4830 if (pipe == 0)
4831 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4832 else
4833 dspcntr |= DISPPLANE_SEL_PIPE_B;
4834 }
79e53945 4835
2582a850 4836 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 4837 drm_mode_debug_printmodeline(mode);
4838
b0e77b9c 4839 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4840
4841 /* pipesrc and dspsize control the size that is scaled from,
4842 * which should always be the user's requested size.
79e53945 4843 */
929c77fb
EA		 4844 I915_WRITE(DSPSIZE(plane),
4845 ((mode->vdisplay - 1) << 16) |
4846 (mode->hdisplay - 1));
4847 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4848
84b046f3
DV		 4849 i9xx_set_pipeconf(intel_crtc);
4850
f564048e
EA		 4851 I915_WRITE(DSPCNTR(plane), dspcntr);
4852 POSTING_READ(DSPCNTR(plane));
4853
94352cf9 4854 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4855
4856 intel_update_watermarks(dev);
4857
f564048e
EA		 4858 return ret;
4859}
4860
0e8ffe1b
DV		 4861static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4862 struct intel_crtc_config *pipe_config)
4863{
4864 struct drm_device *dev = crtc->base.dev;
4865 struct drm_i915_private *dev_priv = dev->dev_private;
4866 uint32_t tmp;
4867
4868 tmp = I915_READ(PIPECONF(crtc->pipe));
4869 if (!(tmp & PIPECONF_ENABLE))
4870 return false;
4871
4872 return true;
4873}
4874
dde86e2d 4875static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4876{
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4878 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4879 struct intel_encoder *encoder;
74cfd7ac 4880 u32 val, final;
13d83a67 4881 bool has_lvds = false;
199e5d79
KP		 4882 bool has_cpu_edp = false;
4883 bool has_pch_edp = false;
4884 bool has_panel = false;
99eb6a01
KP		 4885 bool has_ck505 = false;
4886 bool can_ssc = false;
13d83a67
JB		 4887
4888 /* We need to take the global config into account */
199e5d79
KP		 4889 list_for_each_entry(encoder, &mode_config->encoder_list,
4890 base.head) {
4891 switch (encoder->type) {
4892 case INTEL_OUTPUT_LVDS:
4893 has_panel = true;
4894 has_lvds = true;
4895 break;
4896 case INTEL_OUTPUT_EDP:
4897 has_panel = true;
4898 if (intel_encoder_is_pch_edp(&encoder->base))
4899 has_pch_edp = true;
4900 else
4901 has_cpu_edp = true;
4902 break;
13d83a67
JB		 4903 }
4904 }
4905
99eb6a01
KP		 4906 if (HAS_PCH_IBX(dev)) {
4907 has_ck505 = dev_priv->display_clock_mode;
4908 can_ssc = has_ck505;
4909 } else {
4910 has_ck505 = false;
4911 can_ssc = true;
4912 }
4913
4914 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4915 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4916 has_ck505);
13d83a67
JB		 4917
4918 /* Ironlake: try to setup display ref clock before DPLL
4919 * enabling. This is only under driver's control after
4920 * PCH B stepping, previous chipset stepping should be
4921 * ignoring this setting.
4922 */
74cfd7ac
CW		 4923 val = I915_READ(PCH_DREF_CONTROL);
4924
4925 /* As we must carefully and slowly disable/enable each source in turn,
4926 * compute the final state we want first and check if we need to
4927 * make any changes at all.
4928 */
4929 final = val;
4930 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4931 if (has_ck505)
4932 final |= DREF_NONSPREAD_CK505_ENABLE;
4933 else
4934 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4935
4936 final &= ~DREF_SSC_SOURCE_MASK;
4937 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4938 final &= ~DREF_SSC1_ENABLE;
4939
4940 if (has_panel) {
4941 final |= DREF_SSC_SOURCE_ENABLE;
4942
4943 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4944 final |= DREF_SSC1_ENABLE;
4945
4946 if (has_cpu_edp) {
4947 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4948 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4949 else
4950 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4951 } else
4952 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4953 } else {
4954 final |= DREF_SSC_SOURCE_DISABLE;
4955 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4956 }
4957
4958 if (final == val)
4959 return;
4960
13d83a67 4961 /* Always enable nonspread source */
74cfd7ac 4962 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4963
99eb6a01 4964 if (has_ck505)
74cfd7ac 4965 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 4966 else
74cfd7ac 4967 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4968
199e5d79 4969 if (has_panel) {
74cfd7ac
CW		 4970 val &= ~DREF_SSC_SOURCE_MASK;
4971 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4972
199e5d79 4973 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4974 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4975 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 4976 val |= DREF_SSC1_ENABLE;
e77166b5 4977 } else
74cfd7ac 4978 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4979
4980 /* Get SSC going before enabling the outputs */
74cfd7ac 4981 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4982 POSTING_READ(PCH_DREF_CONTROL);
4983 udelay(200);
4984
74cfd7ac 4985 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 4986
4987 /* Enable CPU source on CPU attached eDP */
199e5d79 4988 if (has_cpu_edp) {
99eb6a01 4989 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4990 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 4991 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4992 }
13d83a67 4993 else
74cfd7ac 4994 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 4995 } else
74cfd7ac 4996 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4997
74cfd7ac 4998 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4999 POSTING_READ(PCH_DREF_CONTROL);
5000 udelay(200);
5001 } else {
5002 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5003
74cfd7ac 5004 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5005
5006 /* Turn off CPU output */
74cfd7ac 5007 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5008
74cfd7ac 5009 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5010 POSTING_READ(PCH_DREF_CONTROL);
5011 udelay(200);
5012
5013 /* Turn off the SSC source */
74cfd7ac
CW		 5014 val &= ~DREF_SSC_SOURCE_MASK;
5015 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5016
5017 /* Turn off SSC1 */
74cfd7ac 5018 val &= ~DREF_SSC1_ENABLE;
199e5d79 5019
74cfd7ac 5020 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5021 POSTING_READ(PCH_DREF_CONTROL);
5022 udelay(200);
5023 }
74cfd7ac
CW		 5024
5025 BUG_ON(val != final);
13d83a67
JB		 5026}
5027
dde86e2d
PZ		 5028/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5029static void lpt_init_pch_refclk(struct drm_device *dev)
5030{
5031 struct drm_i915_private *dev_priv = dev->dev_private;
5032 struct drm_mode_config *mode_config = &dev->mode_config;
5033 struct intel_encoder *encoder;
5034 bool has_vga = false;
5035 bool is_sdv = false;
5036 u32 tmp;
5037
5038 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5039 switch (encoder->type) {
5040 case INTEL_OUTPUT_ANALOG:
5041 has_vga = true;
5042 break;
5043 }
5044 }
5045
5046 if (!has_vga)
5047 return;
5048
c00db246
DV		 5049 mutex_lock(&dev_priv->dpio_lock);
5050
dde86e2d
PZ		 5051 /* XXX: Rip out SDV support once Haswell ships for real. */
5052 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5053 is_sdv = true;
5054
5055 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5056 tmp &= ~SBI_SSCCTL_DISABLE;
5057 tmp |= SBI_SSCCTL_PATHALT;
5058 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5059
5060 udelay(24);
5061
5062 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5063 tmp &= ~SBI_SSCCTL_PATHALT;
5064 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5065
5066 if (!is_sdv) {
5067 tmp = I915_READ(SOUTH_CHICKEN2);
5068 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5069 I915_WRITE(SOUTH_CHICKEN2, tmp);
5070
5071 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5072 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5073 DRM_ERROR("FDI mPHY reset assert timeout\n");
5074
5075 tmp = I915_READ(SOUTH_CHICKEN2);
5076 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5077 I915_WRITE(SOUTH_CHICKEN2, tmp);
5078
5079 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5080 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5081 100))
5082 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5083 }
5084
5085 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5086 tmp &= ~(0xFF << 24);
5087 tmp |= (0x12 << 24);
5088 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5089
dde86e2d
PZ		 5090 if (is_sdv) {
5091 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5092 tmp |= 0x7FFF;
5093 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5094 }
5095
5096 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5097 tmp |= (1 << 11);
5098 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5099
5100 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5101 tmp |= (1 << 11);
5102 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5103
5104 if (is_sdv) {
5105 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5106 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5107 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5108
5109 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5110 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5111 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5112
5113 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5114 tmp |= (0x3F << 8);
5115 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5116
5117 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5118 tmp |= (0x3F << 8);
5119 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5120 }
5121
5122 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5123 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5124 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5125
5126 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5127 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5128 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5129
5130 if (!is_sdv) {
5131 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5132 tmp &= ~(7 << 13);
5133 tmp |= (5 << 13);
5134 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5135
5136 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5137 tmp &= ~(7 << 13);
5138 tmp |= (5 << 13);
5139 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5140 }
5141
5142 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5143 tmp &= ~0xFF;
5144 tmp |= 0x1C;
5145 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5146
5147 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5148 tmp &= ~0xFF;
5149 tmp |= 0x1C;
5150 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5151
5152 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5153 tmp &= ~(0xFF << 16);
5154 tmp |= (0x1C << 16);
5155 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5156
5157 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5158 tmp &= ~(0xFF << 16);
5159 tmp |= (0x1C << 16);
5160 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5161
5162 if (!is_sdv) {
5163 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5164 tmp |= (1 << 27);
5165 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5166
5167 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5168 tmp |= (1 << 27);
5169 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5170
5171 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5172 tmp &= ~(0xF << 28);
5173 tmp |= (4 << 28);
5174 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5175
5176 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5177 tmp &= ~(0xF << 28);
5178 tmp |= (4 << 28);
5179 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5180 }
5181
5182 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5183 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5184 tmp |= SBI_DBUFF0_ENABLE;
5185 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5186
5187 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5188}
5189
5190/*
5191 * Initialize reference clocks when the driver loads
5192 */
5193void intel_init_pch_refclk(struct drm_device *dev)
5194{
5195 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5196 ironlake_init_pch_refclk(dev);
5197 else if (HAS_PCH_LPT(dev))
5198 lpt_init_pch_refclk(dev);
5199}
5200
d9d444cb
JB		 5201static int ironlake_get_refclk(struct drm_crtc *crtc)
5202{
5203 struct drm_device *dev = crtc->dev;
5204 struct drm_i915_private *dev_priv = dev->dev_private;
5205 struct intel_encoder *encoder;
d9d444cb
JB		 5206 struct intel_encoder *edp_encoder = NULL;
5207 int num_connectors = 0;
5208 bool is_lvds = false;
5209
6c2b7c12 5210 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5211 switch (encoder->type) {
5212 case INTEL_OUTPUT_LVDS:
5213 is_lvds = true;
5214 break;
5215 case INTEL_OUTPUT_EDP:
5216 edp_encoder = encoder;
5217 break;
5218 }
5219 num_connectors++;
5220 }
5221
5222 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5223 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5224 dev_priv->lvds_ssc_freq);
5225 return dev_priv->lvds_ssc_freq * 1000;
5226 }
5227
5228 return 120000;
5229}
5230
c8203565 5231static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5232 struct drm_display_mode *adjusted_mode,
c8203565 5233 bool dither)
79e53945 5234{
c8203565 5235 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5237 int pipe = intel_crtc->pipe;
c8203565
PZ		 5238 uint32_t val;
5239
5240 val = I915_READ(PIPECONF(pipe));
5241
dfd07d72 5242 val &= ~PIPECONF_BPC_MASK;
965e0c48 5243 switch (intel_crtc->config.pipe_bpp) {
c8203565 5244 case 18:
dfd07d72 5245 val |= PIPECONF_6BPC;
c8203565
PZ		 5246 break;
5247 case 24:
dfd07d72 5248 val |= PIPECONF_8BPC;
c8203565
PZ		 5249 break;
5250 case 30:
dfd07d72 5251 val |= PIPECONF_10BPC;
c8203565
PZ		 5252 break;
5253 case 36:
dfd07d72 5254 val |= PIPECONF_12BPC;
c8203565
PZ		 5255 break;
5256 default:
cc769b62
PZ		 5257 /* Case prevented by intel_choose_pipe_bpp_dither. */
5258 BUG();
c8203565
PZ		 5259 }
5260
5261 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5262 if (dither)
5263 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5264
5265 val &= ~PIPECONF_INTERLACE_MASK;
5266 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5267 val |= PIPECONF_INTERLACED_ILK;
5268 else
5269 val |= PIPECONF_PROGRESSIVE;
5270
50f3b016 5271 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5272 val |= PIPECONF_COLOR_RANGE_SELECT;
5273 else
5274 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5275
c8203565
PZ		 5276 I915_WRITE(PIPECONF(pipe), val);
5277 POSTING_READ(PIPECONF(pipe));
5278}
5279
86d3efce
VS		 5280/*
5281 * Set up the pipe CSC unit.
5282 *
5283 * Currently only full range RGB to limited range RGB conversion
5284 * is supported, but eventually this should handle various
5285 * RGB<->YCbCr scenarios as well.
5286 */
50f3b016 5287static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5288{
5289 struct drm_device *dev = crtc->dev;
5290 struct drm_i915_private *dev_priv = dev->dev_private;
5291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5292 int pipe = intel_crtc->pipe;
5293 uint16_t coeff = 0x7800; /* 1.0 */
5294
5295 /*
5296 * TODO: Check what kind of values actually come out of the pipe
5297 * with these coeff/postoff values and adjust to get the best
5298 * accuracy. Perhaps we even need to take the bpc value into
5299 * consideration.
5300 */
5301
50f3b016 5302 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5303 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5304
5305 /*
5306 * GY/GU and RY/RU should be the other way around according
5307 * to BSpec, but reality doesn't agree. Just set them up in
5308 * a way that results in the correct picture.
5309 */
5310 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5311 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5312
5313 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5314 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5315
5316 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5317 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5318
5319 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5320 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5321 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5322
5323 if (INTEL_INFO(dev)->gen > 6) {
5324 uint16_t postoff = 0;
5325
50f3b016 5326 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5327 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5328
5329 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5330 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5331 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5332
5333 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5334 } else {
5335 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5336
50f3b016 5337 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5338 mode |= CSC_BLACK_SCREEN_OFFSET;
5339
5340 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5341 }
5342}
5343
ee2b0b38
PZ		 5344static void haswell_set_pipeconf(struct drm_crtc *crtc,
5345 struct drm_display_mode *adjusted_mode,
5346 bool dither)
5347{
5348 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5350 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5351 uint32_t val;
5352
702e7a56 5353 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5354
5355 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5356 if (dither)
5357 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5358
5359 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5360 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5361 val |= PIPECONF_INTERLACED_ILK;
5362 else
5363 val |= PIPECONF_PROGRESSIVE;
5364
702e7a56
PZ		 5365 I915_WRITE(PIPECONF(cpu_transcoder), val);
5366 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5367}
5368
6591c6e4
PZ		 5369static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5370 struct drm_display_mode *adjusted_mode,
5371 intel_clock_t *clock,
5372 bool *has_reduced_clock,
5373 intel_clock_t *reduced_clock)
5374{
5375 struct drm_device *dev = crtc->dev;
5376 struct drm_i915_private *dev_priv = dev->dev_private;
5377 struct intel_encoder *intel_encoder;
5378 int refclk;
d4906093 5379 const intel_limit_t *limit;
6591c6e4 5380 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5381
6591c6e4
PZ		 5382 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5383 switch (intel_encoder->type) {
79e53945
JB		 5384 case INTEL_OUTPUT_LVDS:
5385 is_lvds = true;
5386 break;
5387 case INTEL_OUTPUT_SDVO:
7d57382e 5388 case INTEL_OUTPUT_HDMI:
79e53945 5389 is_sdvo = true;
6591c6e4 5390 if (intel_encoder->needs_tv_clock)
e2f0ba97 5391 is_tv = true;
79e53945 5392 break;
79e53945
JB		 5393 case INTEL_OUTPUT_TVOUT:
5394 is_tv = true;
5395 break;
79e53945
JB		 5396 }
5397 }
5398
d9d444cb 5399 refclk = ironlake_get_refclk(crtc);
79e53945 5400
d4906093
ML		 5401 /*
5402 * Returns a set of divisors for the desired target clock with the given
5403 * refclk, or FALSE. The returned values represent the clock equation:
5404 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5405 */
1b894b59 5406 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5407 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5408 clock);
5409 if (!ret)
5410 return false;
cda4b7d3 5411
ddc9003c 5412 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5413 /*
5414 * Ensure we match the reduced clock's P to the target clock.
5415 * If the clocks don't match, we can't switch the display clock
5416 * by using the FP0/FP1. In such case we will disable the LVDS
5417 * downclock feature.
5418 */
6591c6e4
PZ		 5419 *has_reduced_clock = limit->find_pll(limit, crtc,
5420 dev_priv->lvds_downclock,
5421 refclk,
5422 clock,
5423 reduced_clock);
652c393a 5424 }
61e9653f
DV		 5425
5426 if (is_sdvo && is_tv)
f47709a9 5427 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
6591c6e4
PZ		 5428
5429 return true;
5430}
5431
01a415fd
DV		 5432static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5433{
5434 struct drm_i915_private *dev_priv = dev->dev_private;
5435 uint32_t temp;
5436
5437 temp = I915_READ(SOUTH_CHICKEN1);
5438 if (temp & FDI_BC_BIFURCATION_SELECT)
5439 return;
5440
5441 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5442 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5443
5444 temp |= FDI_BC_BIFURCATION_SELECT;
5445 DRM_DEBUG_KMS("enabling fdi C rx\n");
5446 I915_WRITE(SOUTH_CHICKEN1, temp);
5447 POSTING_READ(SOUTH_CHICKEN1);
5448}
5449
5450static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5451{
5452 struct drm_device *dev = intel_crtc->base.dev;
5453 struct drm_i915_private *dev_priv = dev->dev_private;
5454 struct intel_crtc *pipe_B_crtc =
5455 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5456
84f44ce7
VS		 5457 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5458 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd 5459 if (intel_crtc->fdi_lanes > 4) {
84f44ce7
VS		 5460 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5461 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd
DV		 5462 /* Clamp lanes to avoid programming the hw with bogus values. */
5463 intel_crtc->fdi_lanes = 4;
5464
5465 return false;
5466 }
5467
7eb552ae 5468 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5469 return true;
5470
5471 switch (intel_crtc->pipe) {
5472 case PIPE_A:
5473 return true;
5474 case PIPE_B:
5475 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5476 intel_crtc->fdi_lanes > 2) {
84f44ce7
VS		 5477 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5478 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd
DV		 5479 /* Clamp lanes to avoid programming the hw with bogus values. */
5480 intel_crtc->fdi_lanes = 2;
5481
5482 return false;
5483 }
5484
5485 if (intel_crtc->fdi_lanes > 2)
5486 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5487 else
5488 cpt_enable_fdi_bc_bifurcation(dev);
5489
5490 return true;
5491 case PIPE_C:
5492 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5493 if (intel_crtc->fdi_lanes > 2) {
84f44ce7
VS		 5494 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5495 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd
DV		 5496 /* Clamp lanes to avoid programming the hw with bogus values. */
5497 intel_crtc->fdi_lanes = 2;
5498
5499 return false;
5500 }
5501 } else {
5502 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5503 return false;
5504 }
5505
5506 cpt_enable_fdi_bc_bifurcation(dev);
5507
5508 return true;
5509 default:
5510 BUG();
5511 }
5512}
5513
d4b1931c
PZ		 5514int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5515{
5516 /*
5517 * Account for spread spectrum to avoid
5518 * oversubscribing the link. Max center spread
5519 * is 2.5%; use 5% for safety's sake.
5520 */
5521 u32 bps = target_clock * bpp * 21 / 20;
5522 return bps / (link_bw * 8) + 1;
5523}
5524
6cf86a5e
DV		 5525void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5526 struct intel_link_m_n *m_n)
79e53945 5527{
6cf86a5e
DV		 5528 struct drm_device *dev = crtc->base.dev;
5529 struct drm_i915_private *dev_priv = dev->dev_private;
5530 int pipe = crtc->pipe;
5531
5532 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5533 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5534 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5535 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5536}
5537
5538void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5539 struct intel_link_m_n *m_n)
5540{
5541 struct drm_device *dev = crtc->base.dev;
79e53945 5542 struct drm_i915_private *dev_priv = dev->dev_private;
6cf86a5e 5543 int pipe = crtc->pipe;
3b117c8f 5544 enum transcoder transcoder = crtc->config.cpu_transcoder;
6cf86a5e
DV		 5545
5546 if (INTEL_INFO(dev)->gen >= 5) {
5547 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5548 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5549 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5550 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5551 } else {
5552 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5553 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5554 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5555 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5556 }
5557}
5558
5559static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5560{
5561 struct drm_device *dev = crtc->dev;
79e53945 5562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 5563 struct drm_display_mode *adjusted_mode =
5564 &intel_crtc->config.adjusted_mode;
e69d0bc1 5565 struct intel_link_m_n m_n = {0};
6cc5f341 5566 int target_clock, lane, link_bw;
61e9653f 5567
6cf86a5e
DV		 5568 /* FDI is a binary signal running at ~2.7GHz, encoding
5569 * each output octet as 10 bits. The actual frequency
5570 * is stored as a divider into a 100MHz clock, and the
5571 * mode pixel clock is stored in units of 1KHz.
5572 * Hence the bw of each lane in terms of the mode signal
5573 * is:
5574 */
5575 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
58a27471 5576
df92b1e6
DV		 5577 if (intel_crtc->config.pixel_target_clock)
5578 target_clock = intel_crtc->config.pixel_target_clock;
94bf2ced
DV		 5579 else
5580 target_clock = adjusted_mode->clock;
5581
6cf86a5e
DV		 5582 lane = ironlake_get_lanes_required(target_clock, link_bw,
5583 intel_crtc->config.pipe_bpp);
2c07245f 5584
8febb297
EA		 5585 intel_crtc->fdi_lanes = lane;
5586
6cc5f341
DV		 5587 if (intel_crtc->config.pixel_multiplier > 1)
5588 link_bw *= intel_crtc->config.pixel_multiplier;
965e0c48
DV		 5589 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5590 link_bw, &m_n);
8febb297 5591
6cf86a5e 5592 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
f48d8f23
PZ		 5593}
5594
de13a2e3 5595static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9a7c7890
DV		 5596 intel_clock_t *clock, u32 *fp,
5597 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5598{
de13a2e3 5599 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5600 struct drm_device *dev = crtc->dev;
5601 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5602 struct intel_encoder *intel_encoder;
5603 uint32_t dpll;
6cc5f341 5604 int factor, num_connectors = 0;
de13a2e3 5605 bool is_lvds = false, is_sdvo = false, is_tv = false;
79e53945 5606
de13a2e3
PZ		 5607 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5608 switch (intel_encoder->type) {
79e53945
JB		 5609 case INTEL_OUTPUT_LVDS:
5610 is_lvds = true;
5611 break;
5612 case INTEL_OUTPUT_SDVO:
7d57382e 5613 case INTEL_OUTPUT_HDMI:
79e53945 5614 is_sdvo = true;
de13a2e3 5615 if (intel_encoder->needs_tv_clock)
e2f0ba97 5616 is_tv = true;
79e53945 5617 break;
79e53945
JB		 5618 case INTEL_OUTPUT_TVOUT:
5619 is_tv = true;
5620 break;
79e53945 5621 }
43565a06 5622
c751ce4f 5623 num_connectors++;
79e53945 5624 }
79e53945 5625
c1858123 5626 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5627 factor = 21;
5628 if (is_lvds) {
5629 if ((intel_panel_use_ssc(dev_priv) &&
5630 dev_priv->lvds_ssc_freq == 100) ||
f0b44056 5631 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297
EA		 5632 factor = 25;
5633 } else if (is_sdvo && is_tv)
5634 factor = 20;
c1858123 5635
de13a2e3 5636 if (clock->m < factor * clock->n)
7d0ac5b7 5637 *fp |= FP_CB_TUNE;
2c07245f 5638
9a7c7890
DV		 5639 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5640 *fp2 |= FP_CB_TUNE;
5641
5eddb70b 5642 dpll = 0;
2c07245f 5643
a07d6787
EA		 5644 if (is_lvds)
5645 dpll |= DPLLB_MODE_LVDS;
5646 else
5647 dpll |= DPLLB_MODE_DAC_SERIAL;
5648 if (is_sdvo) {
6cc5f341
DV		 5649 if (intel_crtc->config.pixel_multiplier > 1) {
5650 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5651 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5652 }
a07d6787
EA		 5653 dpll |= DPLL_DVO_HIGH_SPEED;
5654 }
8b47047b
DV		 5655 if (intel_crtc->config.has_dp_encoder &&
5656 intel_crtc->config.has_pch_encoder)
a07d6787 5657 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5658
a07d6787 5659 /* compute bitmask from p1 value */
de13a2e3 5660 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5661 /* also FPA1 */
de13a2e3 5662 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5663
de13a2e3 5664 switch (clock->p2) {
a07d6787
EA		 5665 case 5:
5666 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5667 break;
5668 case 7:
5669 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5670 break;
5671 case 10:
5672 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5673 break;
5674 case 14:
5675 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5676 break;
79e53945
JB		 5677 }
5678
43565a06
KH		 5679 if (is_sdvo && is_tv)
5680 dpll |= PLL_REF_INPUT_TVCLKINBC;
5681 else if (is_tv)
79e53945 5682 /* XXX: just matching BIOS for now */
43565a06 5683 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5684 dpll |= 3;
a7615030 5685 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5686 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5687 else
5688 dpll |= PLL_REF_INPUT_DREFCLK;
5689
de13a2e3
PZ		 5690 return dpll;
5691}
5692
5693static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5694 int x, int y,
5695 struct drm_framebuffer *fb)
5696{
5697 struct drm_device *dev = crtc->dev;
5698 struct drm_i915_private *dev_priv = dev->dev_private;
5699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5700 struct drm_display_mode *adjusted_mode =
5701 &intel_crtc->config.adjusted_mode;
5702 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5703 int pipe = intel_crtc->pipe;
5704 int plane = intel_crtc->plane;
5705 int num_connectors = 0;
5706 intel_clock_t clock, reduced_clock;
cbbab5bd 5707 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5708 bool ok, has_reduced_clock = false;
8b47047b 5709 bool is_lvds = false;
de13a2e3 5710 struct intel_encoder *encoder;
de13a2e3 5711 int ret;
01a415fd 5712 bool dither, fdi_config_ok;
de13a2e3
PZ		 5713
5714 for_each_encoder_on_crtc(dev, crtc, encoder) {
5715 switch (encoder->type) {
5716 case INTEL_OUTPUT_LVDS:
5717 is_lvds = true;
5718 break;
de13a2e3
PZ		 5719 }
5720
5721 num_connectors++;
a07d6787 5722 }
79e53945 5723
5dc5298b
PZ		 5724 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5725 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5726
3b117c8f 5727 intel_crtc->config.cpu_transcoder = pipe;
6cf86a5e 5728
de13a2e3
PZ		 5729 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5730 &has_reduced_clock, &reduced_clock);
5731 if (!ok) {
5732 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5733 return -EINVAL;
79e53945 5734 }
f47709a9
DV		 5735 /* Compat-code for transition, will disappear. */
5736 if (!intel_crtc->config.clock_set) {
5737 intel_crtc->config.dpll.n = clock.n;
5738 intel_crtc->config.dpll.m1 = clock.m1;
5739 intel_crtc->config.dpll.m2 = clock.m2;
5740 intel_crtc->config.dpll.p1 = clock.p1;
5741 intel_crtc->config.dpll.p2 = clock.p2;
5742 }
79e53945 5743
de13a2e3
PZ		 5744 /* Ensure that the cursor is valid for the new mode before changing... */
5745 intel_crtc_update_cursor(crtc, true);
5746
5747 /* determine panel color depth */
4e53c2e0 5748 dither = intel_crtc->config.dither;
de13a2e3
PZ		 5749 if (is_lvds && dev_priv->lvds_dither)
5750 dither = true;
5751
84f44ce7 5752 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 5753 drm_mode_debug_printmodeline(mode);
5754
5dc5298b 5755 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5756 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5757 struct intel_pch_pll *pll;
4b645f14 5758
cbbab5bd
DV		 5759 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5760 if (has_reduced_clock)
5761 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5762 reduced_clock.m2;
5763
5764 dpll = ironlake_compute_dpll(intel_crtc, &clock,
5765 &fp, &reduced_clock,
5766 has_reduced_clock ? &fp2 : NULL);
5767
ee7b9f93
JB		 5768 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5769 if (pll == NULL) {
84f44ce7
VS		 5770 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5771 pipe_name(pipe));
4b645f14
JB		 5772 return -EINVAL;
5773 }
ee7b9f93
JB		 5774 } else
5775 intel_put_pch_pll(intel_crtc);
79e53945 5776
03afc4a2
DV		 5777 if (intel_crtc->config.has_dp_encoder)
5778 intel_dp_set_m_n(intel_crtc);
79e53945 5779
dafd226c
DV		 5780 for_each_encoder_on_crtc(dev, crtc, encoder)
5781 if (encoder->pre_pll_enable)
5782 encoder->pre_pll_enable(encoder);
79e53945 5783
ee7b9f93
JB		 5784 if (intel_crtc->pch_pll) {
5785 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5786
32f9d658 5787 /* Wait for the clocks to stabilize. */
ee7b9f93 5788 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5789 udelay(150);
5790
8febb297
EA		 5791 /* The pixel multiplier can only be updated once the
5792 * DPLL is enabled and the clocks are stable.
5793 *
5794 * So write it again.
5795 */
ee7b9f93 5796 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5797 }
79e53945 5798
5eddb70b 5799 intel_crtc->lowfreq_avail = false;
ee7b9f93 5800 if (intel_crtc->pch_pll) {
4b645f14 5801 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5802 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5803 intel_crtc->lowfreq_avail = true;
4b645f14 5804 } else {
ee7b9f93 5805 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5806 }
5807 }
5808
b0e77b9c 5809 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5810
01a415fd
DV		 5811 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5812 * ironlake_check_fdi_lanes. */
6cf86a5e
DV		 5813 intel_crtc->fdi_lanes = 0;
5814 if (intel_crtc->config.has_pch_encoder)
5815 ironlake_fdi_set_m_n(crtc);
2c07245f 5816
01a415fd 5817 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5818
c8203565 5819 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5820
a1f9e77e
PZ		 5821 /* Set up the display plane register */
5822 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5823 POSTING_READ(DSPCNTR(plane));
79e53945 5824
94352cf9 5825 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5826
5827 intel_update_watermarks(dev);
5828
1f8eeabf
ED		 5829 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5830
01a415fd 5831 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5832}
5833
0e8ffe1b
DV		 5834static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5835 struct intel_crtc_config *pipe_config)
5836{
5837 struct drm_device *dev = crtc->base.dev;
5838 struct drm_i915_private *dev_priv = dev->dev_private;
5839 uint32_t tmp;
5840
5841 tmp = I915_READ(PIPECONF(crtc->pipe));
5842 if (!(tmp & PIPECONF_ENABLE))
5843 return false;
5844
88adfff1
DV		 5845 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5846 pipe_config->has_pch_encoder = true;
5847
0e8ffe1b
DV		 5848 return true;
5849}
5850
d6dd9eb1
DV		 5851static void haswell_modeset_global_resources(struct drm_device *dev)
5852{
5853 struct drm_i915_private *dev_priv = dev->dev_private;
5854 bool enable = false;
5855 struct intel_crtc *crtc;
5856 struct intel_encoder *encoder;
5857
5858 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5859 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5860 enable = true;
5861 /* XXX: Should check for edp transcoder here, but thanks to init
5862 * sequence that's not yet available. Just in case desktop eDP
5863 * on PORT D is possible on haswell, too. */
5864 }
5865
5866 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5867 base.head) {
5868 if (encoder->type != INTEL_OUTPUT_EDP &&
5869 encoder->connectors_active)
5870 enable = true;
5871 }
5872
5873 /* Even the eDP panel fitter is outside the always-on well. */
5874 if (dev_priv->pch_pf_size)
5875 enable = true;
5876
5877 intel_set_power_well(dev, enable);
5878}
5879
09b4ddf9 5880static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5881 int x, int y,
5882 struct drm_framebuffer *fb)
5883{
5884 struct drm_device *dev = crtc->dev;
5885 struct drm_i915_private *dev_priv = dev->dev_private;
5886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5887 struct drm_display_mode *adjusted_mode =
5888 &intel_crtc->config.adjusted_mode;
5889 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5890 int pipe = intel_crtc->pipe;
5891 int plane = intel_crtc->plane;
5892 int num_connectors = 0;
8b47047b 5893 bool is_cpu_edp = false;
09b4ddf9 5894 struct intel_encoder *encoder;
09b4ddf9
PZ		 5895 int ret;
5896 bool dither;
5897
5898 for_each_encoder_on_crtc(dev, crtc, encoder) {
5899 switch (encoder->type) {
09b4ddf9 5900 case INTEL_OUTPUT_EDP:
09b4ddf9
PZ		 5901 if (!intel_encoder_is_pch_edp(&encoder->base))
5902 is_cpu_edp = true;
5903 break;
5904 }
5905
5906 num_connectors++;
5907 }
5908
bba2181c 5909 if (is_cpu_edp)
3b117c8f 5910 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
bba2181c 5911 else
3b117c8f 5912 intel_crtc->config.cpu_transcoder = pipe;
bba2181c 5913
5dc5298b
PZ		 5914 /* We are not sure yet this won't happen. */
5915 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5916 INTEL_PCH_TYPE(dev));
5917
5918 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5919 num_connectors, pipe_name(pipe));
5920
3b117c8f 5921 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
1ce42920
PZ		 5922 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5923
5924 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5925
6441ab5f
PZ		 5926 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5927 return -EINVAL;
5928
09b4ddf9
PZ		 5929 /* Ensure that the cursor is valid for the new mode before changing... */
5930 intel_crtc_update_cursor(crtc, true);
5931
5932 /* determine panel color depth */
4e53c2e0 5933 dither = intel_crtc->config.dither;
09b4ddf9 5934
84f44ce7 5935 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
09b4ddf9
PZ		 5936 drm_mode_debug_printmodeline(mode);
5937
03afc4a2
DV		 5938 if (intel_crtc->config.has_dp_encoder)
5939 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5940
5941 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5942
5943 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5944
6cf86a5e
DV		 5945 if (intel_crtc->config.has_pch_encoder)
5946 ironlake_fdi_set_m_n(crtc);
09b4ddf9 5947
ee2b0b38 5948 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5949
50f3b016 5950 intel_set_pipe_csc(crtc);
86d3efce 5951
09b4ddf9 5952 /* Set up the display plane register */
86d3efce 5953 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5954 POSTING_READ(DSPCNTR(plane));
5955
5956 ret = intel_pipe_set_base(crtc, x, y, fb);
5957
5958 intel_update_watermarks(dev);
5959
5960 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5961
1f803ee5 5962 return ret;
79e53945
JB		 5963}
5964
0e8ffe1b
DV		 5965static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5966 struct intel_crtc_config *pipe_config)
5967{
5968 struct drm_device *dev = crtc->base.dev;
5969 struct drm_i915_private *dev_priv = dev->dev_private;
2bfce950 5970 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 5971 uint32_t tmp;
5972
2bfce950
PZ		 5973 if (!intel_using_power_well(dev_priv->dev) &&
5974 cpu_transcoder != TRANSCODER_EDP)
5975 return false;
5976
5977 tmp = I915_READ(PIPECONF(cpu_transcoder));
0e8ffe1b
DV		 5978 if (!(tmp & PIPECONF_ENABLE))
5979 return false;
5980
88adfff1 5981 /*
f196e6be 5982 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5983 * DDI E. So just check whether this pipe is wired to DDI E and whether
5984 * the PCH transcoder is on.
5985 */
f196e6be 5986 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
88adfff1
DV		 5987 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5988 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
5989 pipe_config->has_pch_encoder = true;
5990
0e8ffe1b
DV		 5991 return true;
5992}
5993
f564048e 5994static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5995 int x, int y,
94352cf9 5996 struct drm_framebuffer *fb)
f564048e
EA		 5997{
5998 struct drm_device *dev = crtc->dev;
5999 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6000 struct drm_encoder_helper_funcs *encoder_funcs;
6001 struct intel_encoder *encoder;
0b701d27 6002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6003 struct drm_display_mode *adjusted_mode =
6004 &intel_crtc->config.adjusted_mode;
6005 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6006 int pipe = intel_crtc->pipe;
f564048e
EA		 6007 int ret;
6008
0b701d27 6009 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6010
b8cecdf5
DV		 6011 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6012
79e53945 6013 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6014
9256aa19
DV		 6015 if (ret != 0)
6016 return ret;
6017
6018 for_each_encoder_on_crtc(dev, crtc, encoder) {
6019 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6020 encoder->base.base.id,
6021 drm_get_encoder_name(&encoder->base),
6022 mode->base.id, mode->name);
6cc5f341
DV		 6023 if (encoder->mode_set) {
6024 encoder->mode_set(encoder);
6025 } else {
6026 encoder_funcs = encoder->base.helper_private;
6027 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6028 }
9256aa19
DV		 6029 }
6030
6031 return 0;
79e53945
JB		 6032}
6033
3a9627f4
WF		 6034static bool intel_eld_uptodate(struct drm_connector *connector,
6035 int reg_eldv, uint32_t bits_eldv,
6036 int reg_elda, uint32_t bits_elda,
6037 int reg_edid)
6038{
6039 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6040 uint8_t *eld = connector->eld;
6041 uint32_t i;
6042
6043 i = I915_READ(reg_eldv);
6044 i &= bits_eldv;
6045
6046 if (!eld[0])
6047 return !i;
6048
6049 if (!i)
6050 return false;
6051
6052 i = I915_READ(reg_elda);
6053 i &= ~bits_elda;
6054 I915_WRITE(reg_elda, i);
6055
6056 for (i = 0; i < eld[2]; i++)
6057 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6058 return false;
6059
6060 return true;
6061}
6062
e0dac65e
WF		 6063static void g4x_write_eld(struct drm_connector *connector,
6064 struct drm_crtc *crtc)
6065{
6066 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6067 uint8_t *eld = connector->eld;
6068 uint32_t eldv;
6069 uint32_t len;
6070 uint32_t i;
6071
6072 i = I915_READ(G4X_AUD_VID_DID);
6073
6074 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6075 eldv = G4X_ELDV_DEVCL_DEVBLC;
6076 else
6077 eldv = G4X_ELDV_DEVCTG;
6078
3a9627f4
WF		 6079 if (intel_eld_uptodate(connector,
6080 G4X_AUD_CNTL_ST, eldv,
6081 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6082 G4X_HDMIW_HDMIEDID))
6083 return;
6084
e0dac65e
WF		 6085 i = I915_READ(G4X_AUD_CNTL_ST);
6086 i &= ~(eldv | G4X_ELD_ADDR);
6087 len = (i >> 9) & 0x1f; /* ELD buffer size */
6088 I915_WRITE(G4X_AUD_CNTL_ST, i);
6089
6090 if (!eld[0])
6091 return;
6092
6093 len = min_t(uint8_t, eld[2], len);
6094 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6095 for (i = 0; i < len; i++)
6096 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6097
6098 i = I915_READ(G4X_AUD_CNTL_ST);
6099 i |= eldv;
6100 I915_WRITE(G4X_AUD_CNTL_ST, i);
6101}
6102
83358c85
WX		 6103static void haswell_write_eld(struct drm_connector *connector,
6104 struct drm_crtc *crtc)
6105{
6106 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6107 uint8_t *eld = connector->eld;
6108 struct drm_device *dev = crtc->dev;
7b9f35a6 6109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6110 uint32_t eldv;
6111 uint32_t i;
6112 int len;
6113 int pipe = to_intel_crtc(crtc)->pipe;
6114 int tmp;
6115
6116 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6117 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6118 int aud_config = HSW_AUD_CFG(pipe);
6119 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6120
6121
6122 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6123
6124 /* Audio output enable */
6125 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6126 tmp = I915_READ(aud_cntrl_st2);
6127 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6128 I915_WRITE(aud_cntrl_st2, tmp);
6129
6130 /* Wait for 1 vertical blank */
6131 intel_wait_for_vblank(dev, pipe);
6132
6133 /* Set ELD valid state */
6134 tmp = I915_READ(aud_cntrl_st2);
6135 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6136 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6137 I915_WRITE(aud_cntrl_st2, tmp);
6138 tmp = I915_READ(aud_cntrl_st2);
6139 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6140
6141 /* Enable HDMI mode */
6142 tmp = I915_READ(aud_config);
6143 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6144 /* clear N_programing_enable and N_value_index */
6145 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6146 I915_WRITE(aud_config, tmp);
6147
6148 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6149
6150 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6151 intel_crtc->eld_vld = true;
83358c85
WX		 6152
6153 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6154 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6155 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6156 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6157 } else
6158 I915_WRITE(aud_config, 0);
6159
6160 if (intel_eld_uptodate(connector,
6161 aud_cntrl_st2, eldv,
6162 aud_cntl_st, IBX_ELD_ADDRESS,
6163 hdmiw_hdmiedid))
6164 return;
6165
6166 i = I915_READ(aud_cntrl_st2);
6167 i &= ~eldv;
6168 I915_WRITE(aud_cntrl_st2, i);
6169
6170 if (!eld[0])
6171 return;
6172
6173 i = I915_READ(aud_cntl_st);
6174 i &= ~IBX_ELD_ADDRESS;
6175 I915_WRITE(aud_cntl_st, i);
6176 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6177 DRM_DEBUG_DRIVER("port num:%d\n", i);
6178
6179 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6180 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6181 for (i = 0; i < len; i++)
6182 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6183
6184 i = I915_READ(aud_cntrl_st2);
6185 i |= eldv;
6186 I915_WRITE(aud_cntrl_st2, i);
6187
6188}
6189
e0dac65e
WF		 6190static void ironlake_write_eld(struct drm_connector *connector,
6191 struct drm_crtc *crtc)
6192{
6193 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6194 uint8_t *eld = connector->eld;
6195 uint32_t eldv;
6196 uint32_t i;
6197 int len;
6198 int hdmiw_hdmiedid;
b6daa025 6199 int aud_config;
e0dac65e
WF		 6200 int aud_cntl_st;
6201 int aud_cntrl_st2;
9b138a83 6202 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6203
b3f33cbf 6204 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6205 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6206 aud_config = IBX_AUD_CFG(pipe);
6207 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6208 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6209 } else {
9b138a83
WX		 6210 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6211 aud_config = CPT_AUD_CFG(pipe);
6212 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6213 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6214 }
6215
9b138a83 6216 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6217
6218 i = I915_READ(aud_cntl_st);
9b138a83 6219 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6220 if (!i) {
6221 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6222 /* operate blindly on all ports */
1202b4c6
WF		 6223 eldv = IBX_ELD_VALIDB;
6224 eldv |= IBX_ELD_VALIDB << 4;
6225 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6226 } else {
2582a850 6227 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6228 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6229 }
6230
3a9627f4
WF		 6231 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6232 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6233 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6234 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6235 } else
6236 I915_WRITE(aud_config, 0);
e0dac65e 6237
3a9627f4
WF		 6238 if (intel_eld_uptodate(connector,
6239 aud_cntrl_st2, eldv,
6240 aud_cntl_st, IBX_ELD_ADDRESS,
6241 hdmiw_hdmiedid))
6242 return;
6243
e0dac65e
WF		 6244 i = I915_READ(aud_cntrl_st2);
6245 i &= ~eldv;
6246 I915_WRITE(aud_cntrl_st2, i);
6247
6248 if (!eld[0])
6249 return;
6250
e0dac65e 6251 i = I915_READ(aud_cntl_st);
1202b4c6 6252 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6253 I915_WRITE(aud_cntl_st, i);
6254
6255 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6256 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6257 for (i = 0; i < len; i++)
6258 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6259
6260 i = I915_READ(aud_cntrl_st2);
6261 i |= eldv;
6262 I915_WRITE(aud_cntrl_st2, i);
6263}
6264
6265void intel_write_eld(struct drm_encoder *encoder,
6266 struct drm_display_mode *mode)
6267{
6268 struct drm_crtc *crtc = encoder->crtc;
6269 struct drm_connector *connector;
6270 struct drm_device *dev = encoder->dev;
6271 struct drm_i915_private *dev_priv = dev->dev_private;
6272
6273 connector = drm_select_eld(encoder, mode);
6274 if (!connector)
6275 return;
6276
6277 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6278 connector->base.id,
6279 drm_get_connector_name(connector),
6280 connector->encoder->base.id,
6281 drm_get_encoder_name(connector->encoder));
6282
6283 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6284
6285 if (dev_priv->display.write_eld)
6286 dev_priv->display.write_eld(connector, crtc);
6287}
6288
79e53945
JB		 6289/** Loads the palette/gamma unit for the CRTC with the prepared values */
6290void intel_crtc_load_lut(struct drm_crtc *crtc)
6291{
6292 struct drm_device *dev = crtc->dev;
6293 struct drm_i915_private *dev_priv = dev->dev_private;
6294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6295 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6296 int i;
6297
6298 /* The clocks have to be on to load the palette. */
aed3f09d 6299 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6300 return;
6301
f2b115e6 6302 /* use legacy palette for Ironlake */
bad720ff 6303 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6304 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6305
79e53945
JB		 6306 for (i = 0; i < 256; i++) {
6307 I915_WRITE(palreg + 4 * i,
6308 (intel_crtc->lut_r[i] << 16) |
6309 (intel_crtc->lut_g[i] << 8) |
6310 intel_crtc->lut_b[i]);
6311 }
6312}
6313
560b85bb
CW		 6314static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6315{
6316 struct drm_device *dev = crtc->dev;
6317 struct drm_i915_private *dev_priv = dev->dev_private;
6318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6319 bool visible = base != 0;
6320 u32 cntl;
6321
6322 if (intel_crtc->cursor_visible == visible)
6323 return;
6324
9db4a9c7 6325 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6326 if (visible) {
6327 /* On these chipsets we can only modify the base whilst
6328 * the cursor is disabled.
6329 */
9db4a9c7 6330 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6331
6332 cntl &= ~(CURSOR_FORMAT_MASK);
6333 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6334 cntl |= CURSOR_ENABLE |
6335 CURSOR_GAMMA_ENABLE |
6336 CURSOR_FORMAT_ARGB;
6337 } else
6338 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6339 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6340
6341 intel_crtc->cursor_visible = visible;
6342}
6343
6344static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6345{
6346 struct drm_device *dev = crtc->dev;
6347 struct drm_i915_private *dev_priv = dev->dev_private;
6348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6349 int pipe = intel_crtc->pipe;
6350 bool visible = base != 0;
6351
6352 if (intel_crtc->cursor_visible != visible) {
548f245b 6353 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6354 if (base) {
6355 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6356 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6357 cntl |= pipe << 28; /* Connect to correct pipe */
6358 } else {
6359 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6360 cntl |= CURSOR_MODE_DISABLE;
6361 }
9db4a9c7 6362 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6363
6364 intel_crtc->cursor_visible = visible;
6365 }
6366 /* and commit changes on next vblank */
9db4a9c7 6367 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6368}
6369
65a21cd6
JB		 6370static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6371{
6372 struct drm_device *dev = crtc->dev;
6373 struct drm_i915_private *dev_priv = dev->dev_private;
6374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6375 int pipe = intel_crtc->pipe;
6376 bool visible = base != 0;
6377
6378 if (intel_crtc->cursor_visible != visible) {
6379 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6380 if (base) {
6381 cntl &= ~CURSOR_MODE;
6382 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6383 } else {
6384 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6385 cntl |= CURSOR_MODE_DISABLE;
6386 }
86d3efce
VS		 6387 if (IS_HASWELL(dev))
6388 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6389 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6390
6391 intel_crtc->cursor_visible = visible;
6392 }
6393 /* and commit changes on next vblank */
6394 I915_WRITE(CURBASE_IVB(pipe), base);
6395}
6396
cda4b7d3 6397/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6398static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6399 bool on)
cda4b7d3
CW		 6400{
6401 struct drm_device *dev = crtc->dev;
6402 struct drm_i915_private *dev_priv = dev->dev_private;
6403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6404 int pipe = intel_crtc->pipe;
6405 int x = intel_crtc->cursor_x;
6406 int y = intel_crtc->cursor_y;
560b85bb 6407 u32 base, pos;
cda4b7d3
CW		 6408 bool visible;
6409
6410 pos = 0;
6411
6b383a7f 6412 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6413 base = intel_crtc->cursor_addr;
6414 if (x > (int) crtc->fb->width)
6415 base = 0;
6416
6417 if (y > (int) crtc->fb->height)
6418 base = 0;
6419 } else
6420 base = 0;
6421
6422 if (x < 0) {
6423 if (x + intel_crtc->cursor_width < 0)
6424 base = 0;
6425
6426 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6427 x = -x;
6428 }
6429 pos |= x << CURSOR_X_SHIFT;
6430
6431 if (y < 0) {
6432 if (y + intel_crtc->cursor_height < 0)
6433 base = 0;
6434
6435 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6436 y = -y;
6437 }
6438 pos |= y << CURSOR_Y_SHIFT;
6439
6440 visible = base != 0;
560b85bb 6441 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6442 return;
6443
0cd83aa9 6444 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6445 I915_WRITE(CURPOS_IVB(pipe), pos);
6446 ivb_update_cursor(crtc, base);
6447 } else {
6448 I915_WRITE(CURPOS(pipe), pos);
6449 if (IS_845G(dev) || IS_I865G(dev))
6450 i845_update_cursor(crtc, base);
6451 else
6452 i9xx_update_cursor(crtc, base);
6453 }
cda4b7d3
CW		 6454}
6455
79e53945 6456static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6457 struct drm_file *file,
79e53945
JB		 6458 uint32_t handle,
6459 uint32_t width, uint32_t height)
6460{
6461 struct drm_device *dev = crtc->dev;
6462 struct drm_i915_private *dev_priv = dev->dev_private;
6463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6464 struct drm_i915_gem_object *obj;
cda4b7d3 6465 uint32_t addr;
3f8bc370 6466 int ret;
79e53945 6467
79e53945
JB		 6468 /* if we want to turn off the cursor ignore width and height */
6469 if (!handle) {
28c97730 6470 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6471 addr = 0;
05394f39 6472 obj = NULL;
5004417d 6473 mutex_lock(&dev->struct_mutex);
3f8bc370 6474 goto finish;
79e53945
JB		 6475 }
6476
6477 /* Currently we only support 64x64 cursors */
6478 if (width != 64 || height != 64) {
6479 DRM_ERROR("we currently only support 64x64 cursors\n");
6480 return -EINVAL;
6481 }
6482
05394f39 6483 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6484 if (&obj->base == NULL)
79e53945
JB		 6485 return -ENOENT;
6486
05394f39 6487 if (obj->base.size < width * height * 4) {
79e53945 6488 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6489 ret = -ENOMEM;
6490 goto fail;
79e53945
JB		 6491 }
6492
71acb5eb 6493 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6494 mutex_lock(&dev->struct_mutex);
b295d1b6 6495 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6496 unsigned alignment;
6497
d9e86c0e
CW		 6498 if (obj->tiling_mode) {
6499 DRM_ERROR("cursor cannot be tiled\n");
6500 ret = -EINVAL;
6501 goto fail_locked;
6502 }
6503
693db184
CW		 6504 /* Note that the w/a also requires 2 PTE of padding following
6505 * the bo. We currently fill all unused PTE with the shadow
6506 * page and so we should always have valid PTE following the
6507 * cursor preventing the VT-d warning.
6508 */
6509 alignment = 0;
6510 if (need_vtd_wa(dev))
6511 alignment = 64*1024;
6512
6513 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6514 if (ret) {
6515 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6516 goto fail_locked;
e7b526bb
CW		 6517 }
6518
d9e86c0e
CW		 6519 ret = i915_gem_object_put_fence(obj);
6520 if (ret) {
2da3b9b9 6521 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6522 goto fail_unpin;
6523 }
6524
05394f39 6525 addr = obj->gtt_offset;
71acb5eb 6526 } else {
6eeefaf3 6527 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6528 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6529 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6530 align);
71acb5eb
DA		 6531 if (ret) {
6532 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6533 goto fail_locked;
71acb5eb 6534 }
05394f39 6535 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6536 }
6537
a6c45cf0 6538 if (IS_GEN2(dev))
14b60391
JB		 6539 I915_WRITE(CURSIZE, (height << 12) | width);
6540
3f8bc370 6541 finish:
3f8bc370 6542 if (intel_crtc->cursor_bo) {
b295d1b6 6543 if (dev_priv->info->cursor_needs_physical) {
05394f39 6544 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6545 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6546 } else
6547 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6548 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6549 }
80824003 6550
7f9872e0 6551 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6552
6553 intel_crtc->cursor_addr = addr;
05394f39 6554 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6555 intel_crtc->cursor_width = width;
6556 intel_crtc->cursor_height = height;
6557
6b383a7f 6558 intel_crtc_update_cursor(crtc, true);
3f8bc370 6559
79e53945 6560 return 0;
e7b526bb 6561fail_unpin:
05394f39 6562 i915_gem_object_unpin(obj);
7f9872e0 6563fail_locked:
34b8686e 6564 mutex_unlock(&dev->struct_mutex);
bc9025bd 6565fail:
05394f39 6566 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6567 return ret;
79e53945
JB		 6568}
6569
6570static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6571{
79e53945 6572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6573
cda4b7d3
CW		 6574 intel_crtc->cursor_x = x;
6575 intel_crtc->cursor_y = y;
652c393a 6576
6b383a7f 6577 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6578
6579 return 0;
6580}
6581
6582/** Sets the color ramps on behalf of RandR */
6583void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6584 u16 blue, int regno)
6585{
6586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6587
6588 intel_crtc->lut_r[regno] = red >> 8;
6589 intel_crtc->lut_g[regno] = green >> 8;
6590 intel_crtc->lut_b[regno] = blue >> 8;
6591}
6592
b8c00ac5
DA		 6593void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6594 u16 *blue, int regno)
6595{
6596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6597
6598 *red = intel_crtc->lut_r[regno] << 8;
6599 *green = intel_crtc->lut_g[regno] << 8;
6600 *blue = intel_crtc->lut_b[regno] << 8;
6601}
6602
79e53945 6603static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6604 u16 *blue, uint32_t start, uint32_t size)
79e53945 6605{
7203425a 6606 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6608
7203425a 6609 for (i = start; i < end; i++) {
79e53945
JB		 6610 intel_crtc->lut_r[i] = red[i] >> 8;
6611 intel_crtc->lut_g[i] = green[i] >> 8;
6612 intel_crtc->lut_b[i] = blue[i] >> 8;
6613 }
6614
6615 intel_crtc_load_lut(crtc);
6616}
6617
79e53945
JB		 6618/* VESA 640x480x72Hz mode to set on the pipe */
6619static struct drm_display_mode load_detect_mode = {
6620 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6621 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6622};
6623
d2dff872
CW		 6624static struct drm_framebuffer *
6625intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6626 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6627 struct drm_i915_gem_object *obj)
6628{
6629 struct intel_framebuffer *intel_fb;
6630 int ret;
6631
6632 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6633 if (!intel_fb) {
6634 drm_gem_object_unreference_unlocked(&obj->base);
6635 return ERR_PTR(-ENOMEM);
6636 }
6637
6638 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6639 if (ret) {
6640 drm_gem_object_unreference_unlocked(&obj->base);
6641 kfree(intel_fb);
6642 return ERR_PTR(ret);
6643 }
6644
6645 return &intel_fb->base;
6646}
6647
6648static u32
6649intel_framebuffer_pitch_for_width(int width, int bpp)
6650{
6651 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6652 return ALIGN(pitch, 64);
6653}
6654
6655static u32
6656intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6657{
6658 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6659 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6660}
6661
6662static struct drm_framebuffer *
6663intel_framebuffer_create_for_mode(struct drm_device *dev,
6664 struct drm_display_mode *mode,
6665 int depth, int bpp)
6666{
6667 struct drm_i915_gem_object *obj;
0fed39bd 6668 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6669
6670 obj = i915_gem_alloc_object(dev,
6671 intel_framebuffer_size_for_mode(mode, bpp));
6672 if (obj == NULL)
6673 return ERR_PTR(-ENOMEM);
6674
6675 mode_cmd.width = mode->hdisplay;
6676 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6677 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6678 bpp);
5ca0c34a 6679 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6680
6681 return intel_framebuffer_create(dev, &mode_cmd, obj);
6682}
6683
6684static struct drm_framebuffer *
6685mode_fits_in_fbdev(struct drm_device *dev,
6686 struct drm_display_mode *mode)
6687{
6688 struct drm_i915_private *dev_priv = dev->dev_private;
6689 struct drm_i915_gem_object *obj;
6690 struct drm_framebuffer *fb;
6691
6692 if (dev_priv->fbdev == NULL)
6693 return NULL;
6694
6695 obj = dev_priv->fbdev->ifb.obj;
6696 if (obj == NULL)
6697 return NULL;
6698
6699 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6700 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6701 fb->bits_per_pixel))
d2dff872
CW		 6702 return NULL;
6703
01f2c773 6704 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6705 return NULL;
6706
6707 return fb;
6708}
6709
d2434ab7 6710bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6711 struct drm_display_mode *mode,
8261b191 6712 struct intel_load_detect_pipe *old)
79e53945
JB		 6713{
6714 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6715 struct intel_encoder *intel_encoder =
6716 intel_attached_encoder(connector);
79e53945 6717 struct drm_crtc *possible_crtc;
4ef69c7a 6718 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6719 struct drm_crtc *crtc = NULL;
6720 struct drm_device *dev = encoder->dev;
94352cf9 6721 struct drm_framebuffer *fb;
79e53945
JB		 6722 int i = -1;
6723
d2dff872
CW		 6724 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6725 connector->base.id, drm_get_connector_name(connector),
6726 encoder->base.id, drm_get_encoder_name(encoder));
6727
79e53945
JB		 6728 /*
6729 * Algorithm gets a little messy:
7a5e4805 6730 *
79e53945
JB		 6731 * - if the connector already has an assigned crtc, use it (but make
6732 * sure it's on first)
7a5e4805 6733 *
79e53945
JB		 6734 * - try to find the first unused crtc that can drive this connector,
6735 * and use that if we find one
79e53945
JB		 6736 */
6737
6738 /* See if we already have a CRTC for this connector */
6739 if (encoder->crtc) {
6740 crtc = encoder->crtc;
8261b191 6741
7b24056b
DV		 6742 mutex_lock(&crtc->mutex);
6743
24218aac 6744 old->dpms_mode = connector->dpms;
8261b191
CW		 6745 old->load_detect_temp = false;
6746
6747 /* Make sure the crtc and connector are running */
24218aac
DV		 6748 if (connector->dpms != DRM_MODE_DPMS_ON)
6749 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6750
7173188d 6751 return true;
79e53945
JB		 6752 }
6753
6754 /* Find an unused one (if possible) */
6755 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6756 i++;
6757 if (!(encoder->possible_crtcs & (1 << i)))
6758 continue;
6759 if (!possible_crtc->enabled) {
6760 crtc = possible_crtc;
6761 break;
6762 }
79e53945
JB		 6763 }
6764
6765 /*
6766 * If we didn't find an unused CRTC, don't use any.
6767 */
6768 if (!crtc) {
7173188d
CW		 6769 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6770 return false;
79e53945
JB		 6771 }
6772
7b24056b 6773 mutex_lock(&crtc->mutex);
fc303101
DV		 6774 intel_encoder->new_crtc = to_intel_crtc(crtc);
6775 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6776
6777 intel_crtc = to_intel_crtc(crtc);
24218aac 6778 old->dpms_mode = connector->dpms;
8261b191 6779 old->load_detect_temp = true;
d2dff872 6780 old->release_fb = NULL;
79e53945 6781
6492711d
CW		 6782 if (!mode)
6783 mode = &load_detect_mode;
79e53945 6784
d2dff872
CW		 6785 /* We need a framebuffer large enough to accommodate all accesses
6786 * that the plane may generate whilst we perform load detection.
6787 * We can not rely on the fbcon either being present (we get called
6788 * during its initialisation to detect all boot displays, or it may
6789 * not even exist) or that it is large enough to satisfy the
6790 * requested mode.
6791 */
94352cf9
DV		 6792 fb = mode_fits_in_fbdev(dev, mode);
6793 if (fb == NULL) {
d2dff872 6794 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6795 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6796 old->release_fb = fb;
d2dff872
CW		 6797 } else
6798 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6799 if (IS_ERR(fb)) {
d2dff872 6800 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6801 mutex_unlock(&crtc->mutex);
0e8b3d3e 6802 return false;
79e53945 6803 }
79e53945 6804
c0c36b94 6805 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6806 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6807 if (old->release_fb)
6808 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6809 mutex_unlock(&crtc->mutex);
0e8b3d3e 6810 return false;
79e53945 6811 }
7173188d 6812
79e53945 6813 /* let the connector get through one full cycle before testing */
9d0498a2 6814 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6815 return true;
79e53945
JB		 6816}
6817
d2434ab7 6818void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6819 struct intel_load_detect_pipe *old)
79e53945 6820{
d2434ab7
DV		 6821 struct intel_encoder *intel_encoder =
6822 intel_attached_encoder(connector);
4ef69c7a 6823 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6824 struct drm_crtc *crtc = encoder->crtc;
79e53945 6825
d2dff872
CW		 6826 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6827 connector->base.id, drm_get_connector_name(connector),
6828 encoder->base.id, drm_get_encoder_name(encoder));
6829
8261b191 6830 if (old->load_detect_temp) {
fc303101
DV		 6831 to_intel_connector(connector)->new_encoder = NULL;
6832 intel_encoder->new_crtc = NULL;
6833 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6834
36206361
DV		 6835 if (old->release_fb) {
6836 drm_framebuffer_unregister_private(old->release_fb);
6837 drm_framebuffer_unreference(old->release_fb);
6838 }
d2dff872 6839
67c96400 6840 mutex_unlock(&crtc->mutex);
0622a53c 6841 return;
79e53945
JB		 6842 }
6843
c751ce4f 6844 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6845 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6846 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6847
6848 mutex_unlock(&crtc->mutex);
79e53945
JB		 6849}
6850
6851/* Returns the clock of the currently programmed mode of the given pipe. */
6852static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6853{
6854 struct drm_i915_private *dev_priv = dev->dev_private;
6855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6856 int pipe = intel_crtc->pipe;
548f245b 6857 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6858 u32 fp;
6859 intel_clock_t clock;
6860
6861 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6862 fp = I915_READ(FP0(pipe));
79e53945 6863 else
39adb7a5 6864 fp = I915_READ(FP1(pipe));
79e53945
JB		 6865
6866 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6867 if (IS_PINEVIEW(dev)) {
6868 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6869 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6870 } else {
6871 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6872 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6873 }
6874
a6c45cf0 6875 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6876 if (IS_PINEVIEW(dev))
6877 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6878 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6879 else
6880 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6881 DPLL_FPA01_P1_POST_DIV_SHIFT);
6882
6883 switch (dpll & DPLL_MODE_MASK) {
6884 case DPLLB_MODE_DAC_SERIAL:
6885 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6886 5 : 10;
6887 break;
6888 case DPLLB_MODE_LVDS:
6889 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6890 7 : 14;
6891 break;
6892 default:
28c97730 6893 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6894 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6895 return 0;
6896 }
6897
6898 /* XXX: Handle the 100Mhz refclk */
2177832f 6899 intel_clock(dev, 96000, &clock);
79e53945
JB		 6900 } else {
6901 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6902
6903 if (is_lvds) {
6904 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6905 DPLL_FPA01_P1_POST_DIV_SHIFT);
6906 clock.p2 = 14;
6907
6908 if ((dpll & PLL_REF_INPUT_MASK) ==
6909 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6910 /* XXX: might not be 66MHz */
2177832f 6911 intel_clock(dev, 66000, &clock);
79e53945 6912 } else
2177832f 6913 intel_clock(dev, 48000, &clock);
79e53945
JB		 6914 } else {
6915 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6916 clock.p1 = 2;
6917 else {
6918 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6919 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6920 }
6921 if (dpll & PLL_P2_DIVIDE_BY_4)
6922 clock.p2 = 4;
6923 else
6924 clock.p2 = 2;
6925
2177832f 6926 intel_clock(dev, 48000, &clock);
79e53945
JB		 6927 }
6928 }
6929
6930 /* XXX: It would be nice to validate the clocks, but we can't reuse
6931 * i830PllIsValid() because it relies on the xf86_config connector
6932 * configuration being accurate, which it isn't necessarily.
6933 */
6934
6935 return clock.dot;
6936}
6937
6938/** Returns the currently programmed mode of the given pipe. */
6939struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6940 struct drm_crtc *crtc)
6941{
548f245b 6942 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6944 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6945 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6946 int htot = I915_READ(HTOTAL(cpu_transcoder));
6947 int hsync = I915_READ(HSYNC(cpu_transcoder));
6948 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6949 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6950
6951 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6952 if (!mode)
6953 return NULL;
6954
6955 mode->clock = intel_crtc_clock_get(dev, crtc);
6956 mode->hdisplay = (htot & 0xffff) + 1;
6957 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6958 mode->hsync_start = (hsync & 0xffff) + 1;
6959 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6960 mode->vdisplay = (vtot & 0xffff) + 1;
6961 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6962 mode->vsync_start = (vsync & 0xffff) + 1;
6963 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6964
6965 drm_mode_set_name(mode);
79e53945
JB		 6966
6967 return mode;
6968}
6969
3dec0095 6970static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6971{
6972 struct drm_device *dev = crtc->dev;
6973 drm_i915_private_t *dev_priv = dev->dev_private;
6974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6975 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6976 int dpll_reg = DPLL(pipe);
6977 int dpll;
652c393a 6978
bad720ff 6979 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6980 return;
6981
6982 if (!dev_priv->lvds_downclock_avail)
6983 return;
6984
dbdc6479 6985 dpll = I915_READ(dpll_reg);
652c393a 6986 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6987 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6988
8ac5a6d5 6989 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6990
6991 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6992 I915_WRITE(dpll_reg, dpll);
9d0498a2 6993 intel_wait_for_vblank(dev, pipe);
dbdc6479 6994
652c393a
JB		 6995 dpll = I915_READ(dpll_reg);
6996 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6997 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6998 }
652c393a
JB		 6999}
7000
7001static void intel_decrease_pllclock(struct drm_crtc *crtc)
7002{
7003 struct drm_device *dev = crtc->dev;
7004 drm_i915_private_t *dev_priv = dev->dev_private;
7005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7006
bad720ff 7007 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7008 return;
7009
7010 if (!dev_priv->lvds_downclock_avail)
7011 return;
7012
7013 /*
7014 * Since this is called by a timer, we should never get here in
7015 * the manual case.
7016 */
7017 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7018 int pipe = intel_crtc->pipe;
7019 int dpll_reg = DPLL(pipe);
7020 int dpll;
f6e5b160 7021
44d98a61 7022 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7023
8ac5a6d5 7024 assert_panel_unlocked(dev_priv, pipe);
652c393a 7025
dc257cf1 7026 dpll = I915_READ(dpll_reg);
652c393a
JB		 7027 dpll |= DISPLAY_RATE_SELECT_FPA1;
7028 I915_WRITE(dpll_reg, dpll);
9d0498a2 7029 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7030 dpll = I915_READ(dpll_reg);
7031 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7032 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7033 }
7034
7035}
7036
f047e395
CW		 7037void intel_mark_busy(struct drm_device *dev)
7038{
f047e395
CW		 7039 i915_update_gfx_val(dev->dev_private);
7040}
7041
7042void intel_mark_idle(struct drm_device *dev)
652c393a 7043{
652c393a 7044 struct drm_crtc *crtc;
652c393a
JB		 7045
7046 if (!i915_powersave)
7047 return;
7048
652c393a 7049 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7050 if (!crtc->fb)
7051 continue;
7052
725a5b54 7053 intel_decrease_pllclock(crtc);
652c393a 7054 }
652c393a
JB		 7055}
7056
725a5b54 7057void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 7058{
f047e395
CW		 7059 struct drm_device *dev = obj->base.dev;
7060 struct drm_crtc *crtc;
652c393a 7061
f047e395 7062 if (!i915_powersave)
acb87dfb
CW		 7063 return;
7064
652c393a
JB		 7065 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7066 if (!crtc->fb)
7067 continue;
7068
f047e395 7069 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7070 intel_increase_pllclock(crtc);
652c393a
JB		 7071 }
7072}
7073
79e53945
JB		 7074static void intel_crtc_destroy(struct drm_crtc *crtc)
7075{
7076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7077 struct drm_device *dev = crtc->dev;
7078 struct intel_unpin_work *work;
7079 unsigned long flags;
7080
7081 spin_lock_irqsave(&dev->event_lock, flags);
7082 work = intel_crtc->unpin_work;
7083 intel_crtc->unpin_work = NULL;
7084 spin_unlock_irqrestore(&dev->event_lock, flags);
7085
7086 if (work) {
7087 cancel_work_sync(&work->work);
7088 kfree(work);
7089 }
79e53945
JB		 7090
7091 drm_crtc_cleanup(crtc);
67e77c5a 7092
79e53945
JB		 7093 kfree(intel_crtc);
7094}
7095
6b95a207
KH		 7096static void intel_unpin_work_fn(struct work_struct *__work)
7097{
7098 struct intel_unpin_work *work =
7099 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7100 struct drm_device *dev = work->crtc->dev;
6b95a207 7101
b4a98e57 7102 mutex_lock(&dev->struct_mutex);
1690e1eb 7103 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7104 drm_gem_object_unreference(&work->pending_flip_obj->base);
7105 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7106
b4a98e57
CW		 7107 intel_update_fbc(dev);
7108 mutex_unlock(&dev->struct_mutex);
7109
7110 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7111 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7112
6b95a207
KH		 7113 kfree(work);
7114}
7115
1afe3e9d 7116static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7117 struct drm_crtc *crtc)
6b95a207
KH		 7118{
7119 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7121 struct intel_unpin_work *work;
6b95a207
KH		 7122 unsigned long flags;
7123
7124 /* Ignore early vblank irqs */
7125 if (intel_crtc == NULL)
7126 return;
7127
7128 spin_lock_irqsave(&dev->event_lock, flags);
7129 work = intel_crtc->unpin_work;
e7d841ca
CW		 7130
7131 /* Ensure we don't miss a work->pending update ... */
7132 smp_rmb();
7133
7134 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7135 spin_unlock_irqrestore(&dev->event_lock, flags);
7136 return;
7137 }
7138
e7d841ca
CW		 7139 /* and that the unpin work is consistent wrt ->pending. */
7140 smp_rmb();
7141
6b95a207 7142 intel_crtc->unpin_work = NULL;
6b95a207 7143
45a066eb
RC		 7144 if (work->event)
7145 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7146
0af7e4df
MK		 7147 drm_vblank_put(dev, intel_crtc->pipe);
7148
6b95a207
KH		 7149 spin_unlock_irqrestore(&dev->event_lock, flags);
7150
2c10d571 7151 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7152
7153 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7154
7155 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7156}
7157
1afe3e9d
JB		 7158void intel_finish_page_flip(struct drm_device *dev, int pipe)
7159{
7160 drm_i915_private_t *dev_priv = dev->dev_private;
7161 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7162
49b14a5c 7163 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7164}
7165
7166void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7167{
7168 drm_i915_private_t *dev_priv = dev->dev_private;
7169 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7170
49b14a5c 7171 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7172}
7173
6b95a207
KH		 7174void intel_prepare_page_flip(struct drm_device *dev, int plane)
7175{
7176 drm_i915_private_t *dev_priv = dev->dev_private;
7177 struct intel_crtc *intel_crtc =
7178 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7179 unsigned long flags;
7180
e7d841ca
CW		 7181 /* NB: An MMIO update of the plane base pointer will also
7182 * generate a page-flip completion irq, i.e. every modeset
7183 * is also accompanied by a spurious intel_prepare_page_flip().
7184 */
6b95a207 7185 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7186 if (intel_crtc->unpin_work)
7187 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7188 spin_unlock_irqrestore(&dev->event_lock, flags);
7189}
7190
e7d841ca
CW		 7191inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7192{
7193 /* Ensure that the work item is consistent when activating it ... */
7194 smp_wmb();
7195 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7196 /* and that it is marked active as soon as the irq could fire. */
7197 smp_wmb();
7198}
7199
8c9f3aaf
JB		 7200static int intel_gen2_queue_flip(struct drm_device *dev,
7201 struct drm_crtc *crtc,
7202 struct drm_framebuffer *fb,
7203 struct drm_i915_gem_object *obj)
7204{
7205 struct drm_i915_private *dev_priv = dev->dev_private;
7206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7207 u32 flip_mask;
6d90c952 7208 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7209 int ret;
7210
6d90c952 7211 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7212 if (ret)
83d4092b 7213 goto err;
8c9f3aaf 7214
6d90c952 7215 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7216 if (ret)
83d4092b 7217 goto err_unpin;
8c9f3aaf
JB		 7218
7219 /* Can't queue multiple flips, so wait for the previous
7220 * one to finish before executing the next.
7221 */
7222 if (intel_crtc->plane)
7223 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7224 else
7225 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7226 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7227 intel_ring_emit(ring, MI_NOOP);
7228 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7229 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7230 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7231 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7232 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7233
7234 intel_mark_page_flip_active(intel_crtc);
6d90c952 7235 intel_ring_advance(ring);
83d4092b
CW		 7236 return 0;
7237
7238err_unpin:
7239 intel_unpin_fb_obj(obj);
7240err:
8c9f3aaf
JB		 7241 return ret;
7242}
7243
7244static int intel_gen3_queue_flip(struct drm_device *dev,
7245 struct drm_crtc *crtc,
7246 struct drm_framebuffer *fb,
7247 struct drm_i915_gem_object *obj)
7248{
7249 struct drm_i915_private *dev_priv = dev->dev_private;
7250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7251 u32 flip_mask;
6d90c952 7252 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7253 int ret;
7254
6d90c952 7255 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7256 if (ret)
83d4092b 7257 goto err;
8c9f3aaf 7258
6d90c952 7259 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7260 if (ret)
83d4092b 7261 goto err_unpin;
8c9f3aaf
JB		 7262
7263 if (intel_crtc->plane)
7264 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7265 else
7266 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7267 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7268 intel_ring_emit(ring, MI_NOOP);
7269 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7270 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7271 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7272 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7273 intel_ring_emit(ring, MI_NOOP);
7274
e7d841ca 7275 intel_mark_page_flip_active(intel_crtc);
6d90c952 7276 intel_ring_advance(ring);
83d4092b
CW		 7277 return 0;
7278
7279err_unpin:
7280 intel_unpin_fb_obj(obj);
7281err:
8c9f3aaf
JB		 7282 return ret;
7283}
7284
7285static int intel_gen4_queue_flip(struct drm_device *dev,
7286 struct drm_crtc *crtc,
7287 struct drm_framebuffer *fb,
7288 struct drm_i915_gem_object *obj)
7289{
7290 struct drm_i915_private *dev_priv = dev->dev_private;
7291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7292 uint32_t pf, pipesrc;
6d90c952 7293 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7294 int ret;
7295
6d90c952 7296 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7297 if (ret)
83d4092b 7298 goto err;
8c9f3aaf 7299
6d90c952 7300 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7301 if (ret)
83d4092b 7302 goto err_unpin;
8c9f3aaf
JB		 7303
7304 /* i965+ uses the linear or tiled offsets from the
7305 * Display Registers (which do not change across a page-flip)
7306 * so we need only reprogram the base address.
7307 */
6d90c952
DV		 7308 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7309 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7310 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7311 intel_ring_emit(ring,
7312 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7313 obj->tiling_mode);
8c9f3aaf
JB		 7314
7315 /* XXX Enabling the panel-fitter across page-flip is so far
7316 * untested on non-native modes, so ignore it for now.
7317 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7318 */
7319 pf = 0;
7320 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7321 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7322
7323 intel_mark_page_flip_active(intel_crtc);
6d90c952 7324 intel_ring_advance(ring);
83d4092b
CW		 7325 return 0;
7326
7327err_unpin:
7328 intel_unpin_fb_obj(obj);
7329err:
8c9f3aaf
JB		 7330 return ret;
7331}
7332
7333static int intel_gen6_queue_flip(struct drm_device *dev,
7334 struct drm_crtc *crtc,
7335 struct drm_framebuffer *fb,
7336 struct drm_i915_gem_object *obj)
7337{
7338 struct drm_i915_private *dev_priv = dev->dev_private;
7339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7340 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7341 uint32_t pf, pipesrc;
7342 int ret;
7343
6d90c952 7344 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7345 if (ret)
83d4092b 7346 goto err;
8c9f3aaf 7347
6d90c952 7348 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7349 if (ret)
83d4092b 7350 goto err_unpin;
8c9f3aaf 7351
6d90c952
DV		 7352 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7353 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7354 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7355 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7356
dc257cf1
DV		 7357 /* Contrary to the suggestions in the documentation,
7358 * "Enable Panel Fitter" does not seem to be required when page
7359 * flipping with a non-native mode, and worse causes a normal
7360 * modeset to fail.
7361 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7362 */
7363 pf = 0;
8c9f3aaf 7364 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7365 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7366
7367 intel_mark_page_flip_active(intel_crtc);
6d90c952 7368 intel_ring_advance(ring);
83d4092b
CW		 7369 return 0;
7370
7371err_unpin:
7372 intel_unpin_fb_obj(obj);
7373err:
8c9f3aaf
JB		 7374 return ret;
7375}
7376
7c9017e5
JB		 7377/*
7378 * On gen7 we currently use the blit ring because (in early silicon at least)
7379 * the render ring doesn't give us interrpts for page flip completion, which
7380 * means clients will hang after the first flip is queued. Fortunately the
7381 * blit ring generates interrupts properly, so use it instead.
7382 */
7383static int intel_gen7_queue_flip(struct drm_device *dev,
7384 struct drm_crtc *crtc,
7385 struct drm_framebuffer *fb,
7386 struct drm_i915_gem_object *obj)
7387{
7388 struct drm_i915_private *dev_priv = dev->dev_private;
7389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7390 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7391 uint32_t plane_bit = 0;
7c9017e5
JB		 7392 int ret;
7393
7394 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7395 if (ret)
83d4092b 7396 goto err;
7c9017e5 7397
cb05d8de
DV		 7398 switch(intel_crtc->plane) {
7399 case PLANE_A:
7400 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7401 break;
7402 case PLANE_B:
7403 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7404 break;
7405 case PLANE_C:
7406 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7407 break;
7408 default:
7409 WARN_ONCE(1, "unknown plane in flip command\n");
7410 ret = -ENODEV;
ab3951eb 7411 goto err_unpin;
cb05d8de
DV		 7412 }
7413
7c9017e5
JB		 7414 ret = intel_ring_begin(ring, 4);
7415 if (ret)
83d4092b 7416 goto err_unpin;
7c9017e5 7417
cb05d8de 7418 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7419 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7420 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7421 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7422
7423 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7424 intel_ring_advance(ring);
83d4092b
CW		 7425 return 0;
7426
7427err_unpin:
7428 intel_unpin_fb_obj(obj);
7429err:
7c9017e5
JB		 7430 return ret;
7431}
7432
8c9f3aaf
JB		 7433static int intel_default_queue_flip(struct drm_device *dev,
7434 struct drm_crtc *crtc,
7435 struct drm_framebuffer *fb,
7436 struct drm_i915_gem_object *obj)
7437{
7438 return -ENODEV;
7439}
7440
6b95a207
KH		 7441static int intel_crtc_page_flip(struct drm_crtc *crtc,
7442 struct drm_framebuffer *fb,
7443 struct drm_pending_vblank_event *event)
7444{
7445 struct drm_device *dev = crtc->dev;
7446 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7447 struct drm_framebuffer *old_fb = crtc->fb;
7448 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7450 struct intel_unpin_work *work;
8c9f3aaf 7451 unsigned long flags;
52e68630 7452 int ret;
6b95a207 7453
e6a595d2
VS		 7454 /* Can't change pixel format via MI display flips. */
7455 if (fb->pixel_format != crtc->fb->pixel_format)
7456 return -EINVAL;
7457
7458 /*
7459 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7460 * Note that pitch changes could also affect these register.
7461 */
7462 if (INTEL_INFO(dev)->gen > 3 &&
7463 (fb->offsets[0] != crtc->fb->offsets[0] ||
7464 fb->pitches[0] != crtc->fb->pitches[0]))
7465 return -EINVAL;
7466
6b95a207
KH		 7467 work = kzalloc(sizeof *work, GFP_KERNEL);
7468 if (work == NULL)
7469 return -ENOMEM;
7470
6b95a207 7471 work->event = event;
b4a98e57 7472 work->crtc = crtc;
4a35f83b 7473 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7474 INIT_WORK(&work->work, intel_unpin_work_fn);
7475
7317c75e
JB		 7476 ret = drm_vblank_get(dev, intel_crtc->pipe);
7477 if (ret)
7478 goto free_work;
7479
6b95a207
KH		 7480 /* We borrow the event spin lock for protecting unpin_work */
7481 spin_lock_irqsave(&dev->event_lock, flags);
7482 if (intel_crtc->unpin_work) {
7483 spin_unlock_irqrestore(&dev->event_lock, flags);
7484 kfree(work);
7317c75e 7485 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7486
7487 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7488 return -EBUSY;
7489 }
7490 intel_crtc->unpin_work = work;
7491 spin_unlock_irqrestore(&dev->event_lock, flags);
7492
b4a98e57
CW		 7493 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7494 flush_workqueue(dev_priv->wq);
7495
79158103
CW		 7496 ret = i915_mutex_lock_interruptible(dev);
7497 if (ret)
7498 goto cleanup;
6b95a207 7499
75dfca80 7500 /* Reference the objects for the scheduled work. */
05394f39
CW		 7501 drm_gem_object_reference(&work->old_fb_obj->base);
7502 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7503
7504 crtc->fb = fb;
96b099fd 7505
e1f99ce6 7506 work->pending_flip_obj = obj;
e1f99ce6 7507
4e5359cd
SF		 7508 work->enable_stall_check = true;
7509
b4a98e57 7510 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7511 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7512
8c9f3aaf
JB		 7513 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7514 if (ret)
7515 goto cleanup_pending;
6b95a207 7516
7782de3b 7517 intel_disable_fbc(dev);
f047e395 7518 intel_mark_fb_busy(obj);
6b95a207
KH		 7519 mutex_unlock(&dev->struct_mutex);
7520
e5510fac
JB		 7521 trace_i915_flip_request(intel_crtc->plane, obj);
7522
6b95a207 7523 return 0;
96b099fd 7524
8c9f3aaf 7525cleanup_pending:
b4a98e57 7526 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7527 crtc->fb = old_fb;
05394f39
CW		 7528 drm_gem_object_unreference(&work->old_fb_obj->base);
7529 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7530 mutex_unlock(&dev->struct_mutex);
7531
79158103 7532cleanup:
96b099fd
CW		 7533 spin_lock_irqsave(&dev->event_lock, flags);
7534 intel_crtc->unpin_work = NULL;
7535 spin_unlock_irqrestore(&dev->event_lock, flags);
7536
7317c75e
JB		 7537 drm_vblank_put(dev, intel_crtc->pipe);
7538free_work:
96b099fd
CW		 7539 kfree(work);
7540
7541 return ret;
6b95a207
KH		 7542}
7543
f6e5b160 7544static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7545 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7546 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7547};
7548
6ed0f796 7549bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7550{
6ed0f796
DV		 7551 struct intel_encoder *other_encoder;
7552 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7553
6ed0f796
DV		 7554 if (WARN_ON(!crtc))
7555 return false;
7556
7557 list_for_each_entry(other_encoder,
7558 &crtc->dev->mode_config.encoder_list,
7559 base.head) {
7560
7561 if (&other_encoder->new_crtc->base != crtc ||
7562 encoder == other_encoder)
7563 continue;
7564 else
7565 return true;
f47166d2
CW		 7566 }
7567
6ed0f796
DV		 7568 return false;
7569}
47f1c6c9 7570
50f56119
DV		 7571static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7572 struct drm_crtc *crtc)
7573{
7574 struct drm_device *dev;
7575 struct drm_crtc *tmp;
7576 int crtc_mask = 1;
47f1c6c9 7577
50f56119 7578 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7579
50f56119 7580 dev = crtc->dev;
47f1c6c9 7581
50f56119
DV		 7582 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7583 if (tmp == crtc)
7584 break;
7585 crtc_mask <<= 1;
7586 }
47f1c6c9 7587
50f56119
DV		 7588 if (encoder->possible_crtcs & crtc_mask)
7589 return true;
7590 return false;
47f1c6c9 7591}
79e53945 7592
9a935856
DV		 7593/**
7594 * intel_modeset_update_staged_output_state
7595 *
7596 * Updates the staged output configuration state, e.g. after we've read out the
7597 * current hw state.
7598 */
7599static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7600{
9a935856
DV		 7601 struct intel_encoder *encoder;
7602 struct intel_connector *connector;
f6e5b160 7603
9a935856
DV		 7604 list_for_each_entry(connector, &dev->mode_config.connector_list,
7605 base.head) {
7606 connector->new_encoder =
7607 to_intel_encoder(connector->base.encoder);
7608 }
f6e5b160 7609
9a935856
DV		 7610 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7611 base.head) {
7612 encoder->new_crtc =
7613 to_intel_crtc(encoder->base.crtc);
7614 }
f6e5b160
CW		 7615}
7616
9a935856
DV		 7617/**
7618 * intel_modeset_commit_output_state
7619 *
7620 * This function copies the stage display pipe configuration to the real one.
7621 */
7622static void intel_modeset_commit_output_state(struct drm_device *dev)
7623{
7624 struct intel_encoder *encoder;
7625 struct intel_connector *connector;
f6e5b160 7626
9a935856
DV		 7627 list_for_each_entry(connector, &dev->mode_config.connector_list,
7628 base.head) {
7629 connector->base.encoder = &connector->new_encoder->base;
7630 }
f6e5b160 7631
9a935856
DV		 7632 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7633 base.head) {
7634 encoder->base.crtc = &encoder->new_crtc->base;
7635 }
7636}
7637
4e53c2e0
DV		 7638static int
7639pipe_config_set_bpp(struct drm_crtc *crtc,
7640 struct drm_framebuffer *fb,
7641 struct intel_crtc_config *pipe_config)
7642{
7643 struct drm_device *dev = crtc->dev;
7644 struct drm_connector *connector;
7645 int bpp;
7646
d42264b1
DV		 7647 switch (fb->pixel_format) {
7648 case DRM_FORMAT_C8:
4e53c2e0
DV		 7649 bpp = 8*3; /* since we go through a colormap */
7650 break;
d42264b1
DV		 7651 case DRM_FORMAT_XRGB1555:
7652 case DRM_FORMAT_ARGB1555:
7653 /* checked in intel_framebuffer_init already */
7654 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7655 return -EINVAL;
7656 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7657 bpp = 6*3; /* min is 18bpp */
7658 break;
d42264b1
DV		 7659 case DRM_FORMAT_XBGR8888:
7660 case DRM_FORMAT_ABGR8888:
7661 /* checked in intel_framebuffer_init already */
7662 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7663 return -EINVAL;
7664 case DRM_FORMAT_XRGB8888:
7665 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7666 bpp = 8*3;
7667 break;
d42264b1
DV		 7668 case DRM_FORMAT_XRGB2101010:
7669 case DRM_FORMAT_ARGB2101010:
7670 case DRM_FORMAT_XBGR2101010:
7671 case DRM_FORMAT_ABGR2101010:
7672 /* checked in intel_framebuffer_init already */
7673 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7674 return -EINVAL;
4e53c2e0
DV		 7675 bpp = 10*3;
7676 break;
baba133a 7677 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7678 default:
7679 DRM_DEBUG_KMS("unsupported depth\n");
7680 return -EINVAL;
7681 }
7682
4e53c2e0
DV		 7683 pipe_config->pipe_bpp = bpp;
7684
7685 /* Clamp display bpp to EDID value */
7686 list_for_each_entry(connector, &dev->mode_config.connector_list,
7687 head) {
7688 if (connector->encoder && connector->encoder->crtc != crtc)
7689 continue;
7690
7691 /* Don't use an invalid EDID bpc value */
7692 if (connector->display_info.bpc &&
7693 connector->display_info.bpc * 3 < bpp) {
7694 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7695 bpp, connector->display_info.bpc*3);
7696 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7697 }
996a2239
DV		 7698
7699 /* Clamp bpp to 8 on screens without EDID 1.4 */
7700 if (connector->display_info.bpc == 0 && bpp > 24) {
7701 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7702 bpp);
7703 pipe_config->pipe_bpp = 24;
7704 }
4e53c2e0
DV		 7705 }
7706
7707 return bpp;
7708}
7709
b8cecdf5
DV		 7710static struct intel_crtc_config *
7711intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7712 struct drm_framebuffer *fb,
b8cecdf5 7713 struct drm_display_mode *mode)
ee7b9f93 7714{
7758a113 7715 struct drm_device *dev = crtc->dev;
7758a113
DV		 7716 struct drm_encoder_helper_funcs *encoder_funcs;
7717 struct intel_encoder *encoder;
b8cecdf5 7718 struct intel_crtc_config *pipe_config;
4e53c2e0 7719 int plane_bpp;
ee7b9f93 7720
b8cecdf5
DV		 7721 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7722 if (!pipe_config)
7758a113
DV		 7723 return ERR_PTR(-ENOMEM);
7724
b8cecdf5
DV		 7725 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7726 drm_mode_copy(&pipe_config->requested_mode, mode);
7727
4e53c2e0
DV		 7728 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7729 if (plane_bpp < 0)
7730 goto fail;
7731
7758a113
DV		 7732 /* Pass our mode to the connectors and the CRTC to give them a chance to
7733 * adjust it according to limitations or connector properties, and also
7734 * a chance to reject the mode entirely.
47f1c6c9 7735 */
7758a113
DV		 7736 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7737 base.head) {
47f1c6c9 7738
7758a113
DV		 7739 if (&encoder->new_crtc->base != crtc)
7740 continue;
7ae89233
DV		 7741
7742 if (encoder->compute_config) {
7743 if (!(encoder->compute_config(encoder, pipe_config))) {
7744 DRM_DEBUG_KMS("Encoder config failure\n");
7745 goto fail;
7746 }
7747
7748 continue;
7749 }
7750
7758a113 7751 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7752 if (!(encoder_funcs->mode_fixup(&encoder->base,
7753 &pipe_config->requested_mode,
7754 &pipe_config->adjusted_mode))) {
7758a113
DV		 7755 DRM_DEBUG_KMS("Encoder fixup failed\n");
7756 goto fail;
7757 }
ee7b9f93 7758 }
47f1c6c9 7759
b8cecdf5 7760 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7758a113
DV		 7761 DRM_DEBUG_KMS("CRTC fixup failed\n");
7762 goto fail;
ee7b9f93 7763 }
7758a113 7764 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7765
4e53c2e0
DV		 7766 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7767 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7768 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7769
b8cecdf5 7770 return pipe_config;
7758a113 7771fail:
b8cecdf5 7772 kfree(pipe_config);
7758a113 7773 return ERR_PTR(-EINVAL);
ee7b9f93 7774}
47f1c6c9 7775
e2e1ed41
DV		 7776/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7777 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7778static void
7779intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7780 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7781{
7782 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7783 struct drm_device *dev = crtc->dev;
7784 struct intel_encoder *encoder;
7785 struct intel_connector *connector;
7786 struct drm_crtc *tmp_crtc;
79e53945 7787
e2e1ed41 7788 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7789
e2e1ed41
DV		 7790 /* Check which crtcs have changed outputs connected to them, these need
7791 * to be part of the prepare_pipes mask. We don't (yet) support global
7792 * modeset across multiple crtcs, so modeset_pipes will only have one
7793 * bit set at most. */
7794 list_for_each_entry(connector, &dev->mode_config.connector_list,
7795 base.head) {
7796 if (connector->base.encoder == &connector->new_encoder->base)
7797 continue;
79e53945 7798
e2e1ed41
DV		 7799 if (connector->base.encoder) {
7800 tmp_crtc = connector->base.encoder->crtc;
7801
7802 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7803 }
7804
7805 if (connector->new_encoder)
7806 *prepare_pipes |=
7807 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7808 }
7809
e2e1ed41
DV		 7810 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7811 base.head) {
7812 if (encoder->base.crtc == &encoder->new_crtc->base)
7813 continue;
7814
7815 if (encoder->base.crtc) {
7816 tmp_crtc = encoder->base.crtc;
7817
7818 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7819 }
7820
7821 if (encoder->new_crtc)
7822 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7823 }
7824
e2e1ed41
DV		 7825 /* Check for any pipes that will be fully disabled ... */
7826 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7827 base.head) {
7828 bool used = false;
22fd0fab 7829
e2e1ed41
DV		 7830 /* Don't try to disable disabled crtcs. */
7831 if (!intel_crtc->base.enabled)
7832 continue;
7e7d76c3 7833
e2e1ed41
DV		 7834 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7835 base.head) {
7836 if (encoder->new_crtc == intel_crtc)
7837 used = true;
7838 }
7839
7840 if (!used)
7841 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7842 }
7843
e2e1ed41
DV		 7844
7845 /* set_mode is also used to update properties on life display pipes. */
7846 intel_crtc = to_intel_crtc(crtc);
7847 if (crtc->enabled)
7848 *prepare_pipes |= 1 << intel_crtc->pipe;
7849
b6c5164d
DV		 7850 /*
7851 * For simplicity do a full modeset on any pipe where the output routing
7852 * changed. We could be more clever, but that would require us to be
7853 * more careful with calling the relevant encoder->mode_set functions.
7854 */
e2e1ed41
DV		 7855 if (*prepare_pipes)
7856 *modeset_pipes = *prepare_pipes;
7857
7858 /* ... and mask these out. */
7859 *modeset_pipes &= ~(*disable_pipes);
7860 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7861
7862 /*
7863 * HACK: We don't (yet) fully support global modesets. intel_set_config
7864 * obies this rule, but the modeset restore mode of
7865 * intel_modeset_setup_hw_state does not.
7866 */
7867 *modeset_pipes &= 1 << intel_crtc->pipe;
7868 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7869
7870 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7871 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7872}
79e53945 7873
ea9d758d 7874static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7875{
ea9d758d 7876 struct drm_encoder *encoder;
f6e5b160 7877 struct drm_device *dev = crtc->dev;
f6e5b160 7878
ea9d758d
DV		 7879 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7880 if (encoder->crtc == crtc)
7881 return true;
7882
7883 return false;
7884}
7885
7886static void
7887intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7888{
7889 struct intel_encoder *intel_encoder;
7890 struct intel_crtc *intel_crtc;
7891 struct drm_connector *connector;
7892
7893 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7894 base.head) {
7895 if (!intel_encoder->base.crtc)
7896 continue;
7897
7898 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7899
7900 if (prepare_pipes & (1 << intel_crtc->pipe))
7901 intel_encoder->connectors_active = false;
7902 }
7903
7904 intel_modeset_commit_output_state(dev);
7905
7906 /* Update computed state. */
7907 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7908 base.head) {
7909 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7910 }
7911
7912 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7913 if (!connector->encoder || !connector->encoder->crtc)
7914 continue;
7915
7916 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7917
7918 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7919 struct drm_property *dpms_property =
7920 dev->mode_config.dpms_property;
7921
ea9d758d 7922 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7923 drm_object_property_set_value(&connector->base,
68d34720
DV		 7924 dpms_property,
7925 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7926
7927 intel_encoder = to_intel_encoder(connector->encoder);
7928 intel_encoder->connectors_active = true;
7929 }
7930 }
7931
7932}
7933
25c5b266
DV		 7934#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7935 list_for_each_entry((intel_crtc), \
7936 &(dev)->mode_config.crtc_list, \
7937 base.head) \
7938 if (mask & (1 <<(intel_crtc)->pipe)) \
7939
0e8ffe1b
DV		 7940static bool
7941intel_pipe_config_compare(struct intel_crtc_config *current_config,
7942 struct intel_crtc_config *pipe_config)
7943{
88adfff1
DV		 7944 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7945 DRM_ERROR("mismatch in has_pch_encoder "
7946 "(expected %i, found %i)\n",
7947 current_config->has_pch_encoder,
7948 pipe_config->has_pch_encoder);
7949 return false;
7950 }
7951
0e8ffe1b
DV		 7952 return true;
7953}
7954
b980514c 7955void
8af6cf88
DV		 7956intel_modeset_check_state(struct drm_device *dev)
7957{
0e8ffe1b 7958 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 7959 struct intel_crtc *crtc;
7960 struct intel_encoder *encoder;
7961 struct intel_connector *connector;
0e8ffe1b 7962 struct intel_crtc_config pipe_config;
8af6cf88
DV		 7963
7964 list_for_each_entry(connector, &dev->mode_config.connector_list,
7965 base.head) {
7966 /* This also checks the encoder/connector hw state with the
7967 * ->get_hw_state callbacks. */
7968 intel_connector_check_state(connector);
7969
7970 WARN(&connector->new_encoder->base != connector->base.encoder,
7971 "connector's staged encoder doesn't match current encoder\n");
7972 }
7973
7974 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7975 base.head) {
7976 bool enabled = false;
7977 bool active = false;
7978 enum pipe pipe, tracked_pipe;
7979
7980 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7981 encoder->base.base.id,
7982 drm_get_encoder_name(&encoder->base));
7983
7984 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7985 "encoder's stage crtc doesn't match current crtc\n");
7986 WARN(encoder->connectors_active && !encoder->base.crtc,
7987 "encoder's active_connectors set, but no crtc\n");
7988
7989 list_for_each_entry(connector, &dev->mode_config.connector_list,
7990 base.head) {
7991 if (connector->base.encoder != &encoder->base)
7992 continue;
7993 enabled = true;
7994 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7995 active = true;
7996 }
7997 WARN(!!encoder->base.crtc != enabled,
7998 "encoder's enabled state mismatch "
7999 "(expected %i, found %i)\n",
8000 !!encoder->base.crtc, enabled);
8001 WARN(active && !encoder->base.crtc,
8002 "active encoder with no crtc\n");
8003
8004 WARN(encoder->connectors_active != active,
8005 "encoder's computed active state doesn't match tracked active state "
8006 "(expected %i, found %i)\n", active, encoder->connectors_active);
8007
8008 active = encoder->get_hw_state(encoder, &pipe);
8009 WARN(active != encoder->connectors_active,
8010 "encoder's hw state doesn't match sw tracking "
8011 "(expected %i, found %i)\n",
8012 encoder->connectors_active, active);
8013
8014 if (!encoder->base.crtc)
8015 continue;
8016
8017 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8018 WARN(active && pipe != tracked_pipe,
8019 "active encoder's pipe doesn't match"
8020 "(expected %i, found %i)\n",
8021 tracked_pipe, pipe);
8022
8023 }
8024
8025 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8026 base.head) {
8027 bool enabled = false;
8028 bool active = false;
8029
8030 DRM_DEBUG_KMS("[CRTC:%d]\n",
8031 crtc->base.base.id);
8032
8033 WARN(crtc->active && !crtc->base.enabled,
8034 "active crtc, but not enabled in sw tracking\n");
8035
8036 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8037 base.head) {
8038 if (encoder->base.crtc != &crtc->base)
8039 continue;
8040 enabled = true;
8041 if (encoder->connectors_active)
8042 active = true;
8043 }
8044 WARN(active != crtc->active,
8045 "crtc's computed active state doesn't match tracked active state "
8046 "(expected %i, found %i)\n", active, crtc->active);
8047 WARN(enabled != crtc->base.enabled,
8048 "crtc's computed enabled state doesn't match tracked enabled state "
8049 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8050
88adfff1 8051 memset(&pipe_config, 0, sizeof(pipe_config));
0e8ffe1b
DV		 8052 active = dev_priv->display.get_pipe_config(crtc,
8053 &pipe_config);
8054 WARN(crtc->active != active,
8055 "crtc active state doesn't match with hw state "
8056 "(expected %i, found %i)\n", crtc->active, active);
8057
8058 WARN(active &&
8059 !intel_pipe_config_compare(&crtc->config, &pipe_config),
8060 "pipe state doesn't match!\n");
8af6cf88
DV		 8061 }
8062}
8063
f30da187
DV		 8064static int __intel_set_mode(struct drm_crtc *crtc,
8065 struct drm_display_mode *mode,
8066 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8067{
8068 struct drm_device *dev = crtc->dev;
dbf2b54e 8069 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8070 struct drm_display_mode *saved_mode, *saved_hwmode;
8071 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8072 struct intel_crtc *intel_crtc;
8073 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8074 int ret = 0;
a6778b3c 8075
3ac18232 8076 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8077 if (!saved_mode)
8078 return -ENOMEM;
3ac18232 8079 saved_hwmode = saved_mode + 1;
a6778b3c 8080
e2e1ed41 8081 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8082 &prepare_pipes, &disable_pipes);
8083
3ac18232
TG		 8084 *saved_hwmode = crtc->hwmode;
8085 *saved_mode = crtc->mode;
a6778b3c 8086
25c5b266
DV		 8087 /* Hack: Because we don't (yet) support global modeset on multiple
8088 * crtcs, we don't keep track of the new mode for more than one crtc.
8089 * Hence simply check whether any bit is set in modeset_pipes in all the
8090 * pieces of code that are not yet converted to deal with mutliple crtcs
8091 * changing their mode at the same time. */
25c5b266 8092 if (modeset_pipes) {
4e53c2e0 8093 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8094 if (IS_ERR(pipe_config)) {
8095 ret = PTR_ERR(pipe_config);
8096 pipe_config = NULL;
8097
3ac18232 8098 goto out;
25c5b266 8099 }
25c5b266 8100 }
a6778b3c 8101
460da916
DV		 8102 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8103 intel_crtc_disable(&intel_crtc->base);
8104
ea9d758d
DV		 8105 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8106 if (intel_crtc->base.enabled)
8107 dev_priv->display.crtc_disable(&intel_crtc->base);
8108 }
a6778b3c 8109
6c4c86f5
DV		 8110 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8111 * to set it here already despite that we pass it down the callchain.
f6e5b160 8112 */
b8cecdf5 8113 if (modeset_pipes) {
3b117c8f 8114 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
25c5b266 8115 crtc->mode = *mode;
b8cecdf5
DV		 8116 /* mode_set/enable/disable functions rely on a correct pipe
8117 * config. */
8118 to_intel_crtc(crtc)->config = *pipe_config;
3b117c8f 8119 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
b8cecdf5 8120 }
7758a113 8121
ea9d758d
DV		 8122 /* Only after disabling all output pipelines that will be changed can we
8123 * update the the output configuration. */
8124 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8125
47fab737
DV		 8126 if (dev_priv->display.modeset_global_resources)
8127 dev_priv->display.modeset_global_resources(dev);
8128
a6778b3c
DV		 8129 /* Set up the DPLL and any encoders state that needs to adjust or depend
8130 * on the DPLL.
f6e5b160 8131 */
25c5b266 8132 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8133 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8134 x, y, fb);
8135 if (ret)
8136 goto done;
a6778b3c
DV		 8137 }
8138
8139 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8140 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8141 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8142
25c5b266
DV		 8143 if (modeset_pipes) {
8144 /* Store real post-adjustment hardware mode. */
b8cecdf5 8145 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8146
25c5b266
DV		 8147 /* Calculate and store various constants which
8148 * are later needed by vblank and swap-completion
8149 * timestamping. They are derived from true hwmode.
8150 */
8151 drm_calc_timestamping_constants(crtc);
8152 }
a6778b3c
DV		 8153
8154 /* FIXME: add subpixel order */
8155done:
c0c36b94 8156 if (ret && crtc->enabled) {
3ac18232
TG		 8157 crtc->hwmode = *saved_hwmode;
8158 crtc->mode = *saved_mode;
a6778b3c
DV		 8159 }
8160
3ac18232 8161out:
b8cecdf5 8162 kfree(pipe_config);
3ac18232 8163 kfree(saved_mode);
a6778b3c 8164 return ret;
f6e5b160
CW		 8165}
8166
f30da187
DV		 8167int intel_set_mode(struct drm_crtc *crtc,
8168 struct drm_display_mode *mode,
8169 int x, int y, struct drm_framebuffer *fb)
8170{
8171 int ret;
8172
8173 ret = __intel_set_mode(crtc, mode, x, y, fb);
8174
8175 if (ret == 0)
8176 intel_modeset_check_state(crtc->dev);
8177
8178 return ret;
8179}
8180
c0c36b94
CW		 8181void intel_crtc_restore_mode(struct drm_crtc *crtc)
8182{
8183 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8184}
8185
25c5b266
DV		 8186#undef for_each_intel_crtc_masked
8187
d9e55608
DV		 8188static void intel_set_config_free(struct intel_set_config *config)
8189{
8190 if (!config)
8191 return;
8192
1aa4b628
DV		 8193 kfree(config->save_connector_encoders);
8194 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8195 kfree(config);
8196}
8197
85f9eb71
DV		 8198static int intel_set_config_save_state(struct drm_device *dev,
8199 struct intel_set_config *config)
8200{
85f9eb71
DV		 8201 struct drm_encoder *encoder;
8202 struct drm_connector *connector;
8203 int count;
8204
1aa4b628
DV		 8205 config->save_encoder_crtcs =
8206 kcalloc(dev->mode_config.num_encoder,
8207 sizeof(struct drm_crtc *), GFP_KERNEL);
8208 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8209 return -ENOMEM;
8210
1aa4b628
DV		 8211 config->save_connector_encoders =
8212 kcalloc(dev->mode_config.num_connector,
8213 sizeof(struct drm_encoder *), GFP_KERNEL);
8214 if (!config->save_connector_encoders)
85f9eb71
DV		 8215 return -ENOMEM;
8216
8217 /* Copy data. Note that driver private data is not affected.
8218 * Should anything bad happen only the expected state is
8219 * restored, not the drivers personal bookkeeping.
8220 */
85f9eb71
DV		 8221 count = 0;
8222 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8223 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8224 }
8225
8226 count = 0;
8227 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8228 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8229 }
8230
8231 return 0;
8232}
8233
8234static void intel_set_config_restore_state(struct drm_device *dev,
8235 struct intel_set_config *config)
8236{
9a935856
DV		 8237 struct intel_encoder *encoder;
8238 struct intel_connector *connector;
85f9eb71
DV		 8239 int count;
8240
85f9eb71 8241 count = 0;
9a935856
DV		 8242 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8243 encoder->new_crtc =
8244 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8245 }
8246
8247 count = 0;
9a935856
DV		 8248 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8249 connector->new_encoder =
8250 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8251 }
8252}
8253
5e2b584e
DV		 8254static void
8255intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8256 struct intel_set_config *config)
8257{
8258
8259 /* We should be able to check here if the fb has the same properties
8260 * and then just flip_or_move it */
8261 if (set->crtc->fb != set->fb) {
8262 /* If we have no fb then treat it as a full mode set */
8263 if (set->crtc->fb == NULL) {
8264 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8265 config->mode_changed = true;
8266 } else if (set->fb == NULL) {
8267 config->mode_changed = true;
72f4901e
DV		 8268 } else if (set->fb->pixel_format !=
8269 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8270 config->mode_changed = true;
8271 } else
8272 config->fb_changed = true;
8273 }
8274
835c5873 8275 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8276 config->fb_changed = true;
8277
8278 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8279 DRM_DEBUG_KMS("modes are different, full mode set\n");
8280 drm_mode_debug_printmodeline(&set->crtc->mode);
8281 drm_mode_debug_printmodeline(set->mode);
8282 config->mode_changed = true;
8283 }
8284}
8285
2e431051 8286static int
9a935856
DV		 8287intel_modeset_stage_output_state(struct drm_device *dev,
8288 struct drm_mode_set *set,
8289 struct intel_set_config *config)
50f56119 8290{
85f9eb71 8291 struct drm_crtc *new_crtc;
9a935856
DV		 8292 struct intel_connector *connector;
8293 struct intel_encoder *encoder;
2e431051 8294 int count, ro;
50f56119 8295
9abdda74 8296 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8297 * of connectors. For paranoia, double-check this. */
8298 WARN_ON(!set->fb && (set->num_connectors != 0));
8299 WARN_ON(set->fb && (set->num_connectors == 0));
8300
50f56119 8301 count = 0;
9a935856
DV		 8302 list_for_each_entry(connector, &dev->mode_config.connector_list,
8303 base.head) {
8304 /* Otherwise traverse passed in connector list and get encoders
8305 * for them. */
50f56119 8306 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8307 if (set->connectors[ro] == &connector->base) {
8308 connector->new_encoder = connector->encoder;
50f56119
DV		 8309 break;
8310 }
8311 }
8312
9a935856
DV		 8313 /* If we disable the crtc, disable all its connectors. Also, if
8314 * the connector is on the changing crtc but not on the new
8315 * connector list, disable it. */
8316 if ((!set->fb || ro == set->num_connectors) &&
8317 connector->base.encoder &&
8318 connector->base.encoder->crtc == set->crtc) {
8319 connector->new_encoder = NULL;
8320
8321 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8322 connector->base.base.id,
8323 drm_get_connector_name(&connector->base));
8324 }
8325
8326
8327 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8328 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8329 config->mode_changed = true;
50f56119
DV		 8330 }
8331 }
9a935856 8332 /* connector->new_encoder is now updated for all connectors. */
50f56119 8333
9a935856 8334 /* Update crtc of enabled connectors. */
50f56119 8335 count = 0;
9a935856
DV		 8336 list_for_each_entry(connector, &dev->mode_config.connector_list,
8337 base.head) {
8338 if (!connector->new_encoder)
50f56119
DV		 8339 continue;
8340
9a935856 8341 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8342
8343 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8344 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8345 new_crtc = set->crtc;
8346 }
8347
8348 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8349 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8350 new_crtc)) {
5e2b584e 8351 return -EINVAL;
50f56119 8352 }
9a935856
DV		 8353 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8354
8355 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8356 connector->base.base.id,
8357 drm_get_connector_name(&connector->base),
8358 new_crtc->base.id);
8359 }
8360
8361 /* Check for any encoders that needs to be disabled. */
8362 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8363 base.head) {
8364 list_for_each_entry(connector,
8365 &dev->mode_config.connector_list,
8366 base.head) {
8367 if (connector->new_encoder == encoder) {
8368 WARN_ON(!connector->new_encoder->new_crtc);
8369
8370 goto next_encoder;
8371 }
8372 }
8373 encoder->new_crtc = NULL;
8374next_encoder:
8375 /* Only now check for crtc changes so we don't miss encoders
8376 * that will be disabled. */
8377 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8378 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8379 config->mode_changed = true;
50f56119
DV		 8380 }
8381 }
9a935856 8382 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8383
2e431051
DV		 8384 return 0;
8385}
8386
8387static int intel_crtc_set_config(struct drm_mode_set *set)
8388{
8389 struct drm_device *dev;
2e431051
DV		 8390 struct drm_mode_set save_set;
8391 struct intel_set_config *config;
8392 int ret;
2e431051 8393
8d3e375e
DV		 8394 BUG_ON(!set);
8395 BUG_ON(!set->crtc);
8396 BUG_ON(!set->crtc->helper_private);
2e431051 8397
7e53f3a4
DV		 8398 /* Enforce sane interface api - has been abused by the fb helper. */
8399 BUG_ON(!set->mode && set->fb);
8400 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8401
2e431051
DV		 8402 if (set->fb) {
8403 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8404 set->crtc->base.id, set->fb->base.id,
8405 (int)set->num_connectors, set->x, set->y);
8406 } else {
8407 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8408 }
8409
8410 dev = set->crtc->dev;
8411
8412 ret = -ENOMEM;
8413 config = kzalloc(sizeof(*config), GFP_KERNEL);
8414 if (!config)
8415 goto out_config;
8416
8417 ret = intel_set_config_save_state(dev, config);
8418 if (ret)
8419 goto out_config;
8420
8421 save_set.crtc = set->crtc;
8422 save_set.mode = &set->crtc->mode;
8423 save_set.x = set->crtc->x;
8424 save_set.y = set->crtc->y;
8425 save_set.fb = set->crtc->fb;
8426
8427 /* Compute whether we need a full modeset, only an fb base update or no
8428 * change at all. In the future we might also check whether only the
8429 * mode changed, e.g. for LVDS where we only change the panel fitter in
8430 * such cases. */
8431 intel_set_config_compute_mode_changes(set, config);
8432
9a935856 8433 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8434 if (ret)
8435 goto fail;
8436
5e2b584e 8437 if (config->mode_changed) {
87f1faa6 8438 if (set->mode) {
50f56119
DV		 8439 DRM_DEBUG_KMS("attempting to set mode from"
8440 " userspace\n");
8441 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8442 }
8443
c0c36b94
CW		 8444 ret = intel_set_mode(set->crtc, set->mode,
8445 set->x, set->y, set->fb);
8446 if (ret) {
8447 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8448 set->crtc->base.id, ret);
87f1faa6
DV		 8449 goto fail;
8450 }
5e2b584e 8451 } else if (config->fb_changed) {
4878cae2
VS		 8452 intel_crtc_wait_for_pending_flips(set->crtc);
8453
4f660f49 8454 ret = intel_pipe_set_base(set->crtc,
94352cf9 8455 set->x, set->y, set->fb);
50f56119
DV		 8456 }
8457
d9e55608
DV		 8458 intel_set_config_free(config);
8459
50f56119
DV		 8460 return 0;
8461
8462fail:
85f9eb71 8463 intel_set_config_restore_state(dev, config);
50f56119
DV		 8464
8465 /* Try to restore the config */
5e2b584e 8466 if (config->mode_changed &&
c0c36b94
CW		 8467 intel_set_mode(save_set.crtc, save_set.mode,
8468 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8469 DRM_ERROR("failed to restore config after modeset failure\n");
8470
d9e55608
DV		 8471out_config:
8472 intel_set_config_free(config);
50f56119
DV		 8473 return ret;
8474}
f6e5b160
CW		 8475
8476static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8477 .cursor_set = intel_crtc_cursor_set,
8478 .cursor_move = intel_crtc_cursor_move,
8479 .gamma_set = intel_crtc_gamma_set,
50f56119 8480 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8481 .destroy = intel_crtc_destroy,
8482 .page_flip = intel_crtc_page_flip,
8483};
8484
79f689aa
PZ		 8485static void intel_cpu_pll_init(struct drm_device *dev)
8486{
affa9354 8487 if (HAS_DDI(dev))
79f689aa
PZ		 8488 intel_ddi_pll_init(dev);
8489}
8490
ee7b9f93
JB		 8491static void intel_pch_pll_init(struct drm_device *dev)
8492{
8493 drm_i915_private_t *dev_priv = dev->dev_private;
8494 int i;
8495
8496 if (dev_priv->num_pch_pll == 0) {
8497 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8498 return;
8499 }
8500
8501 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8502 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8503 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8504 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8505 }
8506}
8507
b358d0a6 8508static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8509{
22fd0fab 8510 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8511 struct intel_crtc *intel_crtc;
8512 int i;
8513
8514 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8515 if (intel_crtc == NULL)
8516 return;
8517
8518 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8519
8520 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8521 for (i = 0; i < 256; i++) {
8522 intel_crtc->lut_r[i] = i;
8523 intel_crtc->lut_g[i] = i;
8524 intel_crtc->lut_b[i] = i;
8525 }
8526
80824003
JB		 8527 /* Swap pipes & planes for FBC on pre-965 */
8528 intel_crtc->pipe = pipe;
8529 intel_crtc->plane = pipe;
3b117c8f 8530 intel_crtc->config.cpu_transcoder = pipe;
e2e767ab 8531 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8532 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8533 intel_crtc->plane = !pipe;
80824003
JB		 8534 }
8535
22fd0fab
JB		 8536 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8537 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8538 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8539 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8540
79e53945 8541 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8542}
8543
08d7b3d1 8544int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8545 struct drm_file *file)
08d7b3d1 8546{
08d7b3d1 8547 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8548 struct drm_mode_object *drmmode_obj;
8549 struct intel_crtc *crtc;
08d7b3d1 8550
1cff8f6b
DV		 8551 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8552 return -ENODEV;
08d7b3d1 8553
c05422d5
DV		 8554 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8555 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8556
c05422d5 8557 if (!drmmode_obj) {
08d7b3d1
CW		 8558 DRM_ERROR("no such CRTC id\n");
8559 return -EINVAL;
8560 }
8561
c05422d5
DV		 8562 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8563 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8564
c05422d5 8565 return 0;
08d7b3d1
CW		 8566}
8567
66a9278e 8568static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8569{
66a9278e
DV		 8570 struct drm_device *dev = encoder->base.dev;
8571 struct intel_encoder *source_encoder;
79e53945 8572 int index_mask = 0;
79e53945
JB		 8573 int entry = 0;
8574
66a9278e
DV		 8575 list_for_each_entry(source_encoder,
8576 &dev->mode_config.encoder_list, base.head) {
8577
8578 if (encoder == source_encoder)
79e53945 8579 index_mask |= (1 << entry);
66a9278e
DV		 8580
8581 /* Intel hw has only one MUX where enocoders could be cloned. */
8582 if (encoder->cloneable && source_encoder->cloneable)
8583 index_mask |= (1 << entry);
8584
79e53945
JB		 8585 entry++;
8586 }
4ef69c7a 8587
79e53945
JB		 8588 return index_mask;
8589}
8590
4d302442
CW		 8591static bool has_edp_a(struct drm_device *dev)
8592{
8593 struct drm_i915_private *dev_priv = dev->dev_private;
8594
8595 if (!IS_MOBILE(dev))
8596 return false;
8597
8598 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8599 return false;
8600
8601 if (IS_GEN5(dev) &&
8602 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8603 return false;
8604
8605 return true;
8606}
8607
79e53945
JB		 8608static void intel_setup_outputs(struct drm_device *dev)
8609{
725e30ad 8610 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8611 struct intel_encoder *encoder;
cb0953d7 8612 bool dpd_is_edp = false;
f3cfcba6 8613 bool has_lvds;
79e53945 8614
f3cfcba6 8615 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8616 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8617 /* disable the panel fitter on everything but LVDS */
8618 I915_WRITE(PFIT_CONTROL, 0);
8619 }
79e53945 8620
c40c0f5b 8621 if (!IS_ULT(dev))
79935fca 8622 intel_crt_init(dev);
cb0953d7 8623
affa9354 8624 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8625 int found;
8626
8627 /* Haswell uses DDI functions to detect digital outputs */
8628 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8629 /* DDI A only supports eDP */
8630 if (found)
8631 intel_ddi_init(dev, PORT_A);
8632
8633 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8634 * register */
8635 found = I915_READ(SFUSE_STRAP);
8636
8637 if (found & SFUSE_STRAP_DDIB_DETECTED)
8638 intel_ddi_init(dev, PORT_B);
8639 if (found & SFUSE_STRAP_DDIC_DETECTED)
8640 intel_ddi_init(dev, PORT_C);
8641 if (found & SFUSE_STRAP_DDID_DETECTED)
8642 intel_ddi_init(dev, PORT_D);
8643 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8644 int found;
270b3042
DV		 8645 dpd_is_edp = intel_dpd_is_edp(dev);
8646
8647 if (has_edp_a(dev))
8648 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8649
dc0fa718 8650 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8651 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8652 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8653 if (!found)
e2debe91 8654 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8655 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8656 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8657 }
8658
dc0fa718 8659 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8660 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8661
dc0fa718 8662 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8663 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8664
5eb08b69 8665 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8666 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8667
270b3042 8668 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8669 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8670 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8671 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8672 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8673 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8674
dc0fa718 8675 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8676 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8677 PORT_B);
67cfc203
VS		 8678 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8679 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8680 }
103a196f 8681 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8682 bool found = false;
7d57382e 8683
e2debe91 8684 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8685 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8686 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8687 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8688 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8689 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8690 }
27185ae1 8691
b01f2c3a
JB		 8692 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8693 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8694 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8695 }
725e30ad 8696 }
13520b05
KH		 8697
8698 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8699
e2debe91 8700 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8701 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8702 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8703 }
27185ae1 8704
e2debe91 8705 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8706
b01f2c3a
JB		 8707 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8708 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8709 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8710 }
8711 if (SUPPORTS_INTEGRATED_DP(dev)) {
8712 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8713 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8714 }
725e30ad 8715 }
27185ae1 8716
b01f2c3a
JB		 8717 if (SUPPORTS_INTEGRATED_DP(dev) &&
8718 (I915_READ(DP_D) & DP_DETECTED)) {
8719 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8720 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8721 }
bad720ff 8722 } else if (IS_GEN2(dev))
79e53945
JB		 8723 intel_dvo_init(dev);
8724
103a196f 8725 if (SUPPORTS_TV(dev))
79e53945
JB		 8726 intel_tv_init(dev);
8727
4ef69c7a
CW		 8728 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8729 encoder->base.possible_crtcs = encoder->crtc_mask;
8730 encoder->base.possible_clones =
66a9278e 8731 intel_encoder_clones(encoder);
79e53945 8732 }
47356eb6 8733
dde86e2d 8734 intel_init_pch_refclk(dev);
270b3042
DV		 8735
8736 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8737}
8738
8739static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8740{
8741 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8742
8743 drm_framebuffer_cleanup(fb);
05394f39 8744 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8745
8746 kfree(intel_fb);
8747}
8748
8749static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8750 struct drm_file *file,
79e53945
JB		 8751 unsigned int *handle)
8752{
8753 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8754 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8755
05394f39 8756 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8757}
8758
8759static const struct drm_framebuffer_funcs intel_fb_funcs = {
8760 .destroy = intel_user_framebuffer_destroy,
8761 .create_handle = intel_user_framebuffer_create_handle,
8762};
8763
38651674
DA		 8764int intel_framebuffer_init(struct drm_device *dev,
8765 struct intel_framebuffer *intel_fb,
308e5bcb 8766 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8767 struct drm_i915_gem_object *obj)
79e53945 8768{
79e53945
JB		 8769 int ret;
8770
c16ed4be
CW		 8771 if (obj->tiling_mode == I915_TILING_Y) {
8772 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8773 return -EINVAL;
c16ed4be 8774 }
57cd6508 8775
c16ed4be
CW		 8776 if (mode_cmd->pitches[0] & 63) {
8777 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8778 mode_cmd->pitches[0]);
57cd6508 8779 return -EINVAL;
c16ed4be 8780 }
57cd6508 8781
5d7bd705 8782 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8783 if (mode_cmd->pitches[0] > 32768) {
8784 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8785 mode_cmd->pitches[0]);
5d7bd705 8786 return -EINVAL;
c16ed4be 8787 }
5d7bd705
VS		 8788
8789 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8790 mode_cmd->pitches[0] != obj->stride) {
8791 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8792 mode_cmd->pitches[0], obj->stride);
5d7bd705 8793 return -EINVAL;
c16ed4be 8794 }
5d7bd705 8795
57779d06 8796 /* Reject formats not supported by any plane early. */
308e5bcb 8797 switch (mode_cmd->pixel_format) {
57779d06 8798 case DRM_FORMAT_C8:
04b3924d
VS		 8799 case DRM_FORMAT_RGB565:
8800 case DRM_FORMAT_XRGB8888:
8801 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8802 break;
8803 case DRM_FORMAT_XRGB1555:
8804 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8805 if (INTEL_INFO(dev)->gen > 3) {
8806 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8807 return -EINVAL;
c16ed4be 8808 }
57779d06
VS		 8809 break;
8810 case DRM_FORMAT_XBGR8888:
8811 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8812 case DRM_FORMAT_XRGB2101010:
8813 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8814 case DRM_FORMAT_XBGR2101010:
8815 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8816 if (INTEL_INFO(dev)->gen < 4) {
8817 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8818 return -EINVAL;
c16ed4be 8819 }
b5626747 8820 break;
04b3924d
VS		 8821 case DRM_FORMAT_YUYV:
8822 case DRM_FORMAT_UYVY:
8823 case DRM_FORMAT_YVYU:
8824 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8825 if (INTEL_INFO(dev)->gen < 5) {
8826 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8827 return -EINVAL;
c16ed4be 8828 }
57cd6508
CW		 8829 break;
8830 default:
c16ed4be 8831 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8832 return -EINVAL;
8833 }
8834
90f9a336
VS		 8835 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8836 if (mode_cmd->offsets[0] != 0)
8837 return -EINVAL;
8838
c7d73f6a
DV		 8839 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8840 intel_fb->obj = obj;
8841
79e53945
JB		 8842 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8843 if (ret) {
8844 DRM_ERROR("framebuffer init failed %d\n", ret);
8845 return ret;
8846 }
8847
79e53945
JB		 8848 return 0;
8849}
8850
79e53945
JB		 8851static struct drm_framebuffer *
8852intel_user_framebuffer_create(struct drm_device *dev,
8853 struct drm_file *filp,
308e5bcb 8854 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8855{
05394f39 8856 struct drm_i915_gem_object *obj;
79e53945 8857
308e5bcb
JB		 8858 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8859 mode_cmd->handles[0]));
c8725226 8860 if (&obj->base == NULL)
cce13ff7 8861 return ERR_PTR(-ENOENT);
79e53945 8862
d2dff872 8863 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8864}
8865
79e53945 8866static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8867 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8868 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8869};
8870
e70236a8
JB		 8871/* Set up chip specific display functions */
8872static void intel_init_display(struct drm_device *dev)
8873{
8874 struct drm_i915_private *dev_priv = dev->dev_private;
8875
affa9354 8876 if (HAS_DDI(dev)) {
0e8ffe1b 8877 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 8878 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8879 dev_priv->display.crtc_enable = haswell_crtc_enable;
8880 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8881 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8882 dev_priv->display.update_plane = ironlake_update_plane;
8883 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 8884 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 8885 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8886 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8887 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8888 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8889 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 8890 } else if (IS_VALLEYVIEW(dev)) {
8891 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8892 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8893 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8894 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8895 dev_priv->display.off = i9xx_crtc_off;
8896 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8897 } else {
0e8ffe1b 8898 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 8899 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8900 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8901 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8902 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8903 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8904 }
e70236a8 8905
e70236a8 8906 /* Returns the core display clock speed */
25eb05fc
JB		 8907 if (IS_VALLEYVIEW(dev))
8908 dev_priv->display.get_display_clock_speed =
8909 valleyview_get_display_clock_speed;
8910 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8911 dev_priv->display.get_display_clock_speed =
8912 i945_get_display_clock_speed;
8913 else if (IS_I915G(dev))
8914 dev_priv->display.get_display_clock_speed =
8915 i915_get_display_clock_speed;
f2b115e6 8916 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8917 dev_priv->display.get_display_clock_speed =
8918 i9xx_misc_get_display_clock_speed;
8919 else if (IS_I915GM(dev))
8920 dev_priv->display.get_display_clock_speed =
8921 i915gm_get_display_clock_speed;
8922 else if (IS_I865G(dev))
8923 dev_priv->display.get_display_clock_speed =
8924 i865_get_display_clock_speed;
f0f8a9ce 8925 else if (IS_I85X(dev))
e70236a8
JB		 8926 dev_priv->display.get_display_clock_speed =
8927 i855_get_display_clock_speed;
8928 else /* 852, 830 */
8929 dev_priv->display.get_display_clock_speed =
8930 i830_get_display_clock_speed;
8931
7f8a8569 8932 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8933 if (IS_GEN5(dev)) {
674cf967 8934 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8935 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8936 } else if (IS_GEN6(dev)) {
674cf967 8937 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8938 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8939 } else if (IS_IVYBRIDGE(dev)) {
8940 /* FIXME: detect B0+ stepping and use auto training */
8941 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8942 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8943 dev_priv->display.modeset_global_resources =
8944 ivb_modeset_global_resources;
c82e4d26
ED		 8945 } else if (IS_HASWELL(dev)) {
8946 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8947 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8948 dev_priv->display.modeset_global_resources =
8949 haswell_modeset_global_resources;
a0e63c22 8950 }
6067aaea 8951 } else if (IS_G4X(dev)) {
e0dac65e 8952 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8953 }
8c9f3aaf
JB		 8954
8955 /* Default just returns -ENODEV to indicate unsupported */
8956 dev_priv->display.queue_flip = intel_default_queue_flip;
8957
8958 switch (INTEL_INFO(dev)->gen) {
8959 case 2:
8960 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8961 break;
8962
8963 case 3:
8964 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8965 break;
8966
8967 case 4:
8968 case 5:
8969 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8970 break;
8971
8972 case 6:
8973 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8974 break;
7c9017e5
JB		 8975 case 7:
8976 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8977 break;
8c9f3aaf 8978 }
e70236a8
JB		 8979}
8980
b690e96c
JB		 8981/*
8982 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8983 * resume, or other times. This quirk makes sure that's the case for
8984 * affected systems.
8985 */
0206e353 8986static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8987{
8988 struct drm_i915_private *dev_priv = dev->dev_private;
8989
8990 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8991 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8992}
8993
435793df
KP		 8994/*
8995 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8996 */
8997static void quirk_ssc_force_disable(struct drm_device *dev)
8998{
8999 struct drm_i915_private *dev_priv = dev->dev_private;
9000 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9001 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9002}
9003
4dca20ef 9004/*
5a15ab5b
CE		 9005 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9006 * brightness value
4dca20ef
CE		 9007 */
9008static void quirk_invert_brightness(struct drm_device *dev)
9009{
9010 struct drm_i915_private *dev_priv = dev->dev_private;
9011 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9012 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9013}
9014
b690e96c
JB		 9015struct intel_quirk {
9016 int device;
9017 int subsystem_vendor;
9018 int subsystem_device;
9019 void (*hook)(struct drm_device *dev);
9020};
9021
5f85f176
EE		 9022/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9023struct intel_dmi_quirk {
9024 void (*hook)(struct drm_device *dev);
9025 const struct dmi_system_id (*dmi_id_list)[];
9026};
9027
9028static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9029{
9030 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9031 return 1;
9032}
9033
9034static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9035 {
9036 .dmi_id_list = &(const struct dmi_system_id[]) {
9037 {
9038 .callback = intel_dmi_reverse_brightness,
9039 .ident = "NCR Corporation",
9040 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9041 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9042 },
9043 },
9044 { } /* terminating entry */
9045 },
9046 .hook = quirk_invert_brightness,
9047 },
9048};
9049
c43b5634 9050static struct intel_quirk intel_quirks[] = {
b690e96c 9051 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9052 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9053
b690e96c
JB		 9054 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9055 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9056
b690e96c
JB		 9057 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9058 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9059
ccd0d36e 9060 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9061 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9062 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9063
9064 /* Lenovo U160 cannot use SSC on LVDS */
9065 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9066
9067 /* Sony Vaio Y cannot use SSC on LVDS */
9068 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9069
9070 /* Acer Aspire 5734Z must invert backlight brightness */
9071 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9072
9073 /* Acer/eMachines G725 */
9074 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9075
9076 /* Acer/eMachines e725 */
9077 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9078
9079 /* Acer/Packard Bell NCL20 */
9080 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9081
9082 /* Acer Aspire 4736Z */
9083 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9084};
9085
9086static void intel_init_quirks(struct drm_device *dev)
9087{
9088 struct pci_dev *d = dev->pdev;
9089 int i;
9090
9091 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9092 struct intel_quirk *q = &intel_quirks[i];
9093
9094 if (d->device == q->device &&
9095 (d->subsystem_vendor == q->subsystem_vendor ||
9096 q->subsystem_vendor == PCI_ANY_ID) &&
9097 (d->subsystem_device == q->subsystem_device ||
9098 q->subsystem_device == PCI_ANY_ID))
9099 q->hook(dev);
9100 }
5f85f176
EE		 9101 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9102 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9103 intel_dmi_quirks[i].hook(dev);
9104 }
b690e96c
JB		 9105}
9106
9cce37f4
JB		 9107/* Disable the VGA plane that we never use */
9108static void i915_disable_vga(struct drm_device *dev)
9109{
9110 struct drm_i915_private *dev_priv = dev->dev_private;
9111 u8 sr1;
766aa1c4 9112 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9113
9114 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9115 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9116 sr1 = inb(VGA_SR_DATA);
9117 outb(sr1 | 1<<5, VGA_SR_DATA);
9118 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9119 udelay(300);
9120
9121 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9122 POSTING_READ(vga_reg);
9123}
9124
f817586c
DV		 9125void intel_modeset_init_hw(struct drm_device *dev)
9126{
fa42e23c 9127 intel_init_power_well(dev);
0232e927 9128
a8f78b58
ED		 9129 intel_prepare_ddi(dev);
9130
f817586c
DV		 9131 intel_init_clock_gating(dev);
9132
79f5b2c7 9133 mutex_lock(&dev->struct_mutex);
8090c6b9 9134 intel_enable_gt_powersave(dev);
79f5b2c7 9135 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9136}
9137
79e53945
JB		 9138void intel_modeset_init(struct drm_device *dev)
9139{
652c393a 9140 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9141 int i, j, ret;
79e53945
JB		 9142
9143 drm_mode_config_init(dev);
9144
9145 dev->mode_config.min_width = 0;
9146 dev->mode_config.min_height = 0;
9147
019d96cb
DA		 9148 dev->mode_config.preferred_depth = 24;
9149 dev->mode_config.prefer_shadow = 1;
9150
e6ecefaa 9151 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9152
b690e96c
JB		 9153 intel_init_quirks(dev);
9154
1fa61106
ED		 9155 intel_init_pm(dev);
9156
e3c74757
BW		 9157 if (INTEL_INFO(dev)->num_pipes == 0)
9158 return;
9159
e70236a8
JB		 9160 intel_init_display(dev);
9161
a6c45cf0
CW		 9162 if (IS_GEN2(dev)) {
9163 dev->mode_config.max_width = 2048;
9164 dev->mode_config.max_height = 2048;
9165 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9166 dev->mode_config.max_width = 4096;
9167 dev->mode_config.max_height = 4096;
79e53945 9168 } else {
a6c45cf0
CW		 9169 dev->mode_config.max_width = 8192;
9170 dev->mode_config.max_height = 8192;
79e53945 9171 }
5d4545ae 9172 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9173
28c97730 9174 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9175 INTEL_INFO(dev)->num_pipes,
9176 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9177
7eb552ae 9178 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9179 intel_crtc_init(dev, i);
7f1f3851
JB		 9180 for (j = 0; j < dev_priv->num_plane; j++) {
9181 ret = intel_plane_init(dev, i, j);
9182 if (ret)
06da8da2
VS		 9183 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9184 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9185 }
79e53945
JB		 9186 }
9187
79f689aa 9188 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9189 intel_pch_pll_init(dev);
9190
9cce37f4
JB		 9191 /* Just disable it once at startup */
9192 i915_disable_vga(dev);
79e53945 9193 intel_setup_outputs(dev);
11be49eb
CW		 9194
9195 /* Just in case the BIOS is doing something questionable. */
9196 intel_disable_fbc(dev);
2c7111db
CW		 9197}
9198
24929352
DV		 9199static void
9200intel_connector_break_all_links(struct intel_connector *connector)
9201{
9202 connector->base.dpms = DRM_MODE_DPMS_OFF;
9203 connector->base.encoder = NULL;
9204 connector->encoder->connectors_active = false;
9205 connector->encoder->base.crtc = NULL;
9206}
9207
7fad798e
DV		 9208static void intel_enable_pipe_a(struct drm_device *dev)
9209{
9210 struct intel_connector *connector;
9211 struct drm_connector *crt = NULL;
9212 struct intel_load_detect_pipe load_detect_temp;
9213
9214 /* We can't just switch on the pipe A, we need to set things up with a
9215 * proper mode and output configuration. As a gross hack, enable pipe A
9216 * by enabling the load detect pipe once. */
9217 list_for_each_entry(connector,
9218 &dev->mode_config.connector_list,
9219 base.head) {
9220 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9221 crt = &connector->base;
9222 break;
9223 }
9224 }
9225
9226 if (!crt)
9227 return;
9228
9229 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9230 intel_release_load_detect_pipe(crt, &load_detect_temp);
9231
652c393a 9232
7fad798e
DV		 9233}
9234
fa555837
DV		 9235static bool
9236intel_check_plane_mapping(struct intel_crtc *crtc)
9237{
7eb552ae
BW		 9238 struct drm_device *dev = crtc->base.dev;
9239 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9240 u32 reg, val;
9241
7eb552ae 9242 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9243 return true;
9244
9245 reg = DSPCNTR(!crtc->plane);
9246 val = I915_READ(reg);
9247
9248 if ((val & DISPLAY_PLANE_ENABLE) &&
9249 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9250 return false;
9251
9252 return true;
9253}
9254
24929352
DV		 9255static void intel_sanitize_crtc(struct intel_crtc *crtc)
9256{
9257 struct drm_device *dev = crtc->base.dev;
9258 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9259 u32 reg;
24929352 9260
24929352 9261 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9262 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9263 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9264
9265 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9266 * disable the crtc (and hence change the state) if it is wrong. Note
9267 * that gen4+ has a fixed plane -> pipe mapping. */
9268 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9269 struct intel_connector *connector;
9270 bool plane;
9271
24929352
DV		 9272 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9273 crtc->base.base.id);
9274
9275 /* Pipe has the wrong plane attached and the plane is active.
9276 * Temporarily change the plane mapping and disable everything
9277 * ... */
9278 plane = crtc->plane;
9279 crtc->plane = !plane;
9280 dev_priv->display.crtc_disable(&crtc->base);
9281 crtc->plane = plane;
9282
9283 /* ... and break all links. */
9284 list_for_each_entry(connector, &dev->mode_config.connector_list,
9285 base.head) {
9286 if (connector->encoder->base.crtc != &crtc->base)
9287 continue;
9288
9289 intel_connector_break_all_links(connector);
9290 }
9291
9292 WARN_ON(crtc->active);
9293 crtc->base.enabled = false;
9294 }
24929352 9295
7fad798e
DV		 9296 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9297 crtc->pipe == PIPE_A && !crtc->active) {
9298 /* BIOS forgot to enable pipe A, this mostly happens after
9299 * resume. Force-enable the pipe to fix this, the update_dpms
9300 * call below we restore the pipe to the right state, but leave
9301 * the required bits on. */
9302 intel_enable_pipe_a(dev);
9303 }
9304
24929352
DV		 9305 /* Adjust the state of the output pipe according to whether we
9306 * have active connectors/encoders. */
9307 intel_crtc_update_dpms(&crtc->base);
9308
9309 if (crtc->active != crtc->base.enabled) {
9310 struct intel_encoder *encoder;
9311
9312 /* This can happen either due to bugs in the get_hw_state
9313 * functions or because the pipe is force-enabled due to the
9314 * pipe A quirk. */
9315 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9316 crtc->base.base.id,
9317 crtc->base.enabled ? "enabled" : "disabled",
9318 crtc->active ? "enabled" : "disabled");
9319
9320 crtc->base.enabled = crtc->active;
9321
9322 /* Because we only establish the connector -> encoder ->
9323 * crtc links if something is active, this means the
9324 * crtc is now deactivated. Break the links. connector
9325 * -> encoder links are only establish when things are
9326 * actually up, hence no need to break them. */
9327 WARN_ON(crtc->active);
9328
9329 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9330 WARN_ON(encoder->connectors_active);
9331 encoder->base.crtc = NULL;
9332 }
9333 }
9334}
9335
9336static void intel_sanitize_encoder(struct intel_encoder *encoder)
9337{
9338 struct intel_connector *connector;
9339 struct drm_device *dev = encoder->base.dev;
9340
9341 /* We need to check both for a crtc link (meaning that the
9342 * encoder is active and trying to read from a pipe) and the
9343 * pipe itself being active. */
9344 bool has_active_crtc = encoder->base.crtc &&
9345 to_intel_crtc(encoder->base.crtc)->active;
9346
9347 if (encoder->connectors_active && !has_active_crtc) {
9348 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9349 encoder->base.base.id,
9350 drm_get_encoder_name(&encoder->base));
9351
9352 /* Connector is active, but has no active pipe. This is
9353 * fallout from our resume register restoring. Disable
9354 * the encoder manually again. */
9355 if (encoder->base.crtc) {
9356 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9357 encoder->base.base.id,
9358 drm_get_encoder_name(&encoder->base));
9359 encoder->disable(encoder);
9360 }
9361
9362 /* Inconsistent output/port/pipe state happens presumably due to
9363 * a bug in one of the get_hw_state functions. Or someplace else
9364 * in our code, like the register restore mess on resume. Clamp
9365 * things to off as a safer default. */
9366 list_for_each_entry(connector,
9367 &dev->mode_config.connector_list,
9368 base.head) {
9369 if (connector->encoder != encoder)
9370 continue;
9371
9372 intel_connector_break_all_links(connector);
9373 }
9374 }
9375 /* Enabled encoders without active connectors will be fixed in
9376 * the crtc fixup. */
9377}
9378
44cec740 9379void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9380{
9381 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9382 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9383
9384 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9385 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9386 i915_disable_vga(dev);
0fde901f
KM		 9387 }
9388}
9389
24929352
DV		 9390/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9391 * and i915 state tracking structures. */
45e2b5f6
DV		 9392void intel_modeset_setup_hw_state(struct drm_device *dev,
9393 bool force_restore)
24929352
DV		 9394{
9395 struct drm_i915_private *dev_priv = dev->dev_private;
9396 enum pipe pipe;
9397 u32 tmp;
b5644d05 9398 struct drm_plane *plane;
24929352
DV		 9399 struct intel_crtc *crtc;
9400 struct intel_encoder *encoder;
9401 struct intel_connector *connector;
9402
affa9354 9403 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9404 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9405
9406 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9407 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9408 case TRANS_DDI_EDP_INPUT_A_ON:
9409 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9410 pipe = PIPE_A;
9411 break;
9412 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9413 pipe = PIPE_B;
9414 break;
9415 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9416 pipe = PIPE_C;
9417 break;
aaa148ec
DL		 9418 default:
9419 /* A bogus value has been programmed, disable
9420 * the transcoder */
9421 WARN(1, "Bogus eDP source %08x\n", tmp);
9422 intel_ddi_disable_transcoder_func(dev_priv,
9423 TRANSCODER_EDP);
9424 goto setup_pipes;
e28d54cb
PZ		 9425 }
9426
9427 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3b117c8f 9428 crtc->config.cpu_transcoder = TRANSCODER_EDP;
e28d54cb
PZ		 9429
9430 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9431 pipe_name(pipe));
9432 }
9433 }
9434
aaa148ec 9435setup_pipes:
0e8ffe1b
DV		 9436 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9437 base.head) {
3b117c8f 9438 enum transcoder tmp = crtc->config.cpu_transcoder;
88adfff1 9439 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f
DV		 9440 crtc->config.cpu_transcoder = tmp;
9441
0e8ffe1b
DV		 9442 crtc->active = dev_priv->display.get_pipe_config(crtc,
9443 &crtc->config);
24929352
DV		 9444
9445 crtc->base.enabled = crtc->active;
9446
9447 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9448 crtc->base.base.id,
9449 crtc->active ? "enabled" : "disabled");
9450 }
9451
affa9354 9452 if (HAS_DDI(dev))
6441ab5f
PZ		 9453 intel_ddi_setup_hw_pll_state(dev);
9454
24929352
DV		 9455 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9456 base.head) {
9457 pipe = 0;
9458
9459 if (encoder->get_hw_state(encoder, &pipe)) {
9460 encoder->base.crtc =
9461 dev_priv->pipe_to_crtc_mapping[pipe];
9462 } else {
9463 encoder->base.crtc = NULL;
9464 }
9465
9466 encoder->connectors_active = false;
9467 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9468 encoder->base.base.id,
9469 drm_get_encoder_name(&encoder->base),
9470 encoder->base.crtc ? "enabled" : "disabled",
9471 pipe);
9472 }
9473
9474 list_for_each_entry(connector, &dev->mode_config.connector_list,
9475 base.head) {
9476 if (connector->get_hw_state(connector)) {
9477 connector->base.dpms = DRM_MODE_DPMS_ON;
9478 connector->encoder->connectors_active = true;
9479 connector->base.encoder = &connector->encoder->base;
9480 } else {
9481 connector->base.dpms = DRM_MODE_DPMS_OFF;
9482 connector->base.encoder = NULL;
9483 }
9484 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9485 connector->base.base.id,
9486 drm_get_connector_name(&connector->base),
9487 connector->base.encoder ? "enabled" : "disabled");
9488 }
9489
9490 /* HW state is read out, now we need to sanitize this mess. */
9491 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9492 base.head) {
9493 intel_sanitize_encoder(encoder);
9494 }
9495
9496 for_each_pipe(pipe) {
9497 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9498 intel_sanitize_crtc(crtc);
9499 }
9a935856 9500
45e2b5f6 9501 if (force_restore) {
f30da187
DV		 9502 /*
9503 * We need to use raw interfaces for restoring state to avoid
9504 * checking (bogus) intermediate states.
9505 */
45e2b5f6 9506 for_each_pipe(pipe) {
b5644d05
JB		 9507 struct drm_crtc *crtc =
9508 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9509
9510 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9511 crtc->fb);
45e2b5f6 9512 }
b5644d05
JB		 9513 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9514 intel_plane_restore(plane);
0fde901f
KM		 9515
9516 i915_redisable_vga(dev);
45e2b5f6
DV		 9517 } else {
9518 intel_modeset_update_staged_output_state(dev);
9519 }
8af6cf88
DV		 9520
9521 intel_modeset_check_state(dev);
2e938892
DV		 9522
9523 drm_mode_config_reset(dev);
2c7111db
CW		 9524}
9525
9526void intel_modeset_gem_init(struct drm_device *dev)
9527{
1833b134 9528 intel_modeset_init_hw(dev);
02e792fb
DV		 9529
9530 intel_setup_overlay(dev);
24929352 9531
45e2b5f6 9532 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9533}
9534
9535void intel_modeset_cleanup(struct drm_device *dev)
9536{
652c393a
JB		 9537 struct drm_i915_private *dev_priv = dev->dev_private;
9538 struct drm_crtc *crtc;
9539 struct intel_crtc *intel_crtc;
9540
fd0c0642
DV		 9541 /*
9542 * Interrupts and polling as the first thing to avoid creating havoc.
9543 * Too much stuff here (turning of rps, connectors, ...) would
9544 * experience fancy races otherwise.
9545 */
9546 drm_irq_uninstall(dev);
9547 cancel_work_sync(&dev_priv->hotplug_work);
9548 /*
9549 * Due to the hpd irq storm handling the hotplug work can re-arm the
9550 * poll handlers. Hence disable polling after hpd handling is shut down.
9551 */
f87ea761 9552 drm_kms_helper_poll_fini(dev);
fd0c0642 9553
652c393a
JB		 9554 mutex_lock(&dev->struct_mutex);
9555
723bfd70
JB		 9556 intel_unregister_dsm_handler();
9557
652c393a
JB		 9558 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9559 /* Skip inactive CRTCs */
9560 if (!crtc->fb)
9561 continue;
9562
9563 intel_crtc = to_intel_crtc(crtc);
3dec0095 9564 intel_increase_pllclock(crtc);
652c393a
JB		 9565 }
9566
973d04f9 9567 intel_disable_fbc(dev);
e70236a8 9568
8090c6b9 9569 intel_disable_gt_powersave(dev);
0cdab21f 9570
930ebb46
DV		 9571 ironlake_teardown_rc6(dev);
9572
69341a5e
KH		 9573 mutex_unlock(&dev->struct_mutex);
9574
1630fe75
CW		 9575 /* flush any delayed tasks or pending work */
9576 flush_scheduled_work();
9577
dc652f90
JN		 9578 /* destroy backlight, if any, before the connectors */
9579 intel_panel_destroy_backlight(dev);
9580
79e53945 9581 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9582
9583 intel_cleanup_overlay(dev);
79e53945
JB		 9584}
9585
f1c79df3
ZW		 9586/*
9587 * Return which encoder is currently attached for connector.
9588 */
df0e9248 9589struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9590{
df0e9248
CW		 9591 return &intel_attached_encoder(connector)->base;
9592}
f1c79df3 9593
df0e9248
CW		 9594void intel_connector_attach_encoder(struct intel_connector *connector,
9595 struct intel_encoder *encoder)
9596{
9597 connector->encoder = encoder;
9598 drm_mode_connector_attach_encoder(&connector->base,
9599 &encoder->base);
79e53945 9600}
28d52043
DA		 9601
9602/*
9603 * set vga decode state - true == enable VGA decode
9604 */
9605int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9606{
9607 struct drm_i915_private *dev_priv = dev->dev_private;
9608 u16 gmch_ctrl;
9609
9610 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9611 if (state)
9612 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9613 else
9614 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9615 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9616 return 0;
9617}
c4a1d9e4
CW		 9618
9619#ifdef CONFIG_DEBUG_FS
9620#include <linux/seq_file.h>
9621
9622struct intel_display_error_state {
9623 struct intel_cursor_error_state {
9624 u32 control;
9625 u32 position;
9626 u32 base;
9627 u32 size;
52331309 9628 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9629
9630 struct intel_pipe_error_state {
9631 u32 conf;
9632 u32 source;
9633
9634 u32 htotal;
9635 u32 hblank;
9636 u32 hsync;
9637 u32 vtotal;
9638 u32 vblank;
9639 u32 vsync;
52331309 9640 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9641
9642 struct intel_plane_error_state {
9643 u32 control;
9644 u32 stride;
9645 u32 size;
9646 u32 pos;
9647 u32 addr;
9648 u32 surface;
9649 u32 tile_offset;
52331309 9650 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9651};
9652
9653struct intel_display_error_state *
9654intel_display_capture_error_state(struct drm_device *dev)
9655{
0206e353 9656 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9657 struct intel_display_error_state *error;
702e7a56 9658 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9659 int i;
9660
9661 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9662 if (error == NULL)
9663 return NULL;
9664
52331309 9665 for_each_pipe(i) {
702e7a56
PZ		 9666 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9667
a18c4c3d
PZ		 9668 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9669 error->cursor[i].control = I915_READ(CURCNTR(i));
9670 error->cursor[i].position = I915_READ(CURPOS(i));
9671 error->cursor[i].base = I915_READ(CURBASE(i));
9672 } else {
9673 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9674 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9675 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9676 }
c4a1d9e4
CW		 9677
9678 error->plane[i].control = I915_READ(DSPCNTR(i));
9679 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9680 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9681 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9682 error->plane[i].pos = I915_READ(DSPPOS(i));
9683 }
ca291363
PZ		 9684 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9685 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9686 if (INTEL_INFO(dev)->gen >= 4) {
9687 error->plane[i].surface = I915_READ(DSPSURF(i));
9688 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9689 }
9690
702e7a56 9691 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9692 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9693 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9694 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9695 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9696 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9697 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9698 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9699 }
9700
9701 return error;
9702}
9703
9704void
9705intel_display_print_error_state(struct seq_file *m,
9706 struct drm_device *dev,
9707 struct intel_display_error_state *error)
9708{
9709 int i;
9710
7eb552ae 9711 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9712 for_each_pipe(i) {
c4a1d9e4
CW		 9713 seq_printf(m, "Pipe [%d]:\n", i);
9714 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9715 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9716 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9717 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9718 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9719 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9720 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9721 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9722
9723 seq_printf(m, "Plane [%d]:\n", i);
9724 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9725 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9726 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9727 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9728 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9729 }
4b71a570 9730 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9731 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9732 if (INTEL_INFO(dev)->gen >= 4) {
9733 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9734 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9735 }
9736
9737 seq_printf(m, "Cursor [%d]:\n", i);
9738 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9739 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9740 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9741 }
9742}
9743#endif
Linux kernel - Deliverables
This page took 1.412333 seconds and 5 git commands to generate.