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drm/i915: stop for_each_intel_crtc_masked macro from leaking
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
f4808ab8
VS		 62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
d4906093 80};
79e53945 81
2377b741
JB		 82/* FDI */
83#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
d2acd215
DV		 85int
86intel_pch_rawclk(struct drm_device *dev)
87{
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93}
94
d4906093
ML		 95static bool
96intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
d4906093
ML		 99static bool
100intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
79e53945 103
a0c4da24
JB		 104static bool
105intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
021357ac
CW		 109static inline u32 /* units of 100MHz */
110intel_fdi_link_freq(struct drm_device *dev)
111{
8b99e68c
CW		 112 if (IS_GEN5(dev)) {
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
115 } else
116 return 27;
021357ac
CW		 117}
118
e4b36699 119static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
d4906093 130 .find_pll = intel_find_best_PLL,
e4b36699
KP		 131};
132
133static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
d4906093 144 .find_pll = intel_find_best_PLL,
e4b36699 145};
273e27ca 146
e4b36699 147static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
d4906093 158 .find_pll = intel_find_best_PLL,
e4b36699
KP		 159};
160
161static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
d4906093 172 .find_pll = intel_find_best_PLL,
e4b36699
KP		 173};
174
273e27ca 175
e4b36699 176static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
186 .p2_slow = 10,
187 .p2_fast = 10
044c7c41 188 },
d4906093 189 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 190};
191
192static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
d4906093 203 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 204};
205
206static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
044c7c41 217 },
d4906093 218 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 219};
220
221static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
044c7c41 232 },
d4906093 233 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 234};
235
f2b115e6 236static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 239 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
273e27ca 242 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
6115707b 249 .find_pll = intel_find_best_PLL,
e4b36699
KP		 250};
251
f2b115e6 252static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
6115707b 263 .find_pll = intel_find_best_PLL,
e4b36699
KP		 264};
265
273e27ca
EA		 266/* Ironlake / Sandybridge
267 *
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
270 */
b91ad0ec 271static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
4547668a 282 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 283};
284
b91ad0ec 285static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 296 .find_pll = intel_g4x_find_best_PLL,
297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 310 .find_pll = intel_g4x_find_best_PLL,
311};
312
273e27ca 313/* LVDS 100mhz refclk limits. */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
0206e353 322 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 325 .find_pll = intel_g4x_find_best_PLL,
326};
327
328static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
0206e353 336 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 339 .find_pll = intel_g4x_find_best_PLL,
340};
341
a0c4da24
JB		 342static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
75e53986 350 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
354};
355
356static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
368};
369
370static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 373 .n = { .min = 1, .max = 7 },
74a4dd2e 374 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
75e53986 378 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
382};
383
57f350b6
JB		 384u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
385{
09153000 386 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 387
57f350b6
JB		 388 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
389 DRM_ERROR("DPIO idle wait timed out\n");
09153000 390 return 0;
57f350b6
JB		 391 }
392
393 I915_WRITE(DPIO_REG, reg);
394 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
395 DPIO_BYTE);
396 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
397 DRM_ERROR("DPIO read wait timed out\n");
09153000 398 return 0;
57f350b6 399 }
57f350b6 400
09153000 401 return I915_READ(DPIO_DATA);
57f350b6
JB		 402}
403
e2fa6fba 404void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
a0c4da24 405{
09153000 406 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 407
a0c4da24
JB		 408 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
409 DRM_ERROR("DPIO idle wait timed out\n");
09153000 410 return;
a0c4da24
JB		 411 }
412
413 I915_WRITE(DPIO_DATA, val);
414 I915_WRITE(DPIO_REG, reg);
415 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
416 DPIO_BYTE);
417 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
418 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 419}
420
1b894b59
CW		 421static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
422 int refclk)
2c07245f 423{
b91ad0ec 424 struct drm_device *dev = crtc->dev;
2c07245f 425 const intel_limit_t *limit;
b91ad0ec
ZW		 426
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 428 if (intel_is_dual_link_lvds(dev)) {
1b894b59 429 if (refclk == 100000)
b91ad0ec
ZW		 430 limit = &intel_limits_ironlake_dual_lvds_100m;
431 else
432 limit = &intel_limits_ironlake_dual_lvds;
433 } else {
1b894b59 434 if (refclk == 100000)
b91ad0ec
ZW		 435 limit = &intel_limits_ironlake_single_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_single_lvds;
438 }
c6bb3538 439 } else
b91ad0ec 440 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 441
442 return limit;
443}
444
044c7c41
ML		 445static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
446{
447 struct drm_device *dev = crtc->dev;
044c7c41
ML		 448 const intel_limit_t *limit;
449
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 451 if (intel_is_dual_link_lvds(dev))
e4b36699 452 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 453 else
e4b36699 454 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
456 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 457 limit = &intel_limits_g4x_hdmi;
044c7c41 458 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 459 limit = &intel_limits_g4x_sdvo;
044c7c41 460 } else /* The option is for other outputs */
e4b36699 461 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 462
463 return limit;
464}
465
1b894b59 466static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 467{
468 struct drm_device *dev = crtc->dev;
469 const intel_limit_t *limit;
470
bad720ff 471 if (HAS_PCH_SPLIT(dev))
1b894b59 472 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 473 else if (IS_G4X(dev)) {
044c7c41 474 limit = intel_g4x_limit(crtc);
f2b115e6 475 } else if (IS_PINEVIEW(dev)) {
2177832f 476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 477 limit = &intel_limits_pineview_lvds;
2177832f 478 else
f2b115e6 479 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 480 } else if (IS_VALLEYVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
482 limit = &intel_limits_vlv_dac;
483 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
484 limit = &intel_limits_vlv_hdmi;
485 else
486 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 487 } else if (!IS_GEN2(dev)) {
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
489 limit = &intel_limits_i9xx_lvds;
490 else
491 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 492 } else {
493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 494 limit = &intel_limits_i8xx_lvds;
79e53945 495 else
e4b36699 496 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 497 }
498 return limit;
499}
500
f2b115e6
AJ		 501/* m1 is reserved as 0 in Pineview, n is a ring counter */
502static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 503{
2177832f
SL		 504 clock->m = clock->m2 + 2;
505 clock->p = clock->p1 * clock->p2;
506 clock->vco = refclk * clock->m / clock->n;
507 clock->dot = clock->vco / clock->p;
508}
509
7429e9d4
DV		 510static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
511{
512 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
513}
514
2177832f
SL		 515static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
516{
f2b115e6
AJ		 517 if (IS_PINEVIEW(dev)) {
518 pineview_clock(refclk, clock);
2177832f
SL		 519 return;
520 }
7429e9d4 521 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 522 clock->p = clock->p1 * clock->p2;
523 clock->vco = refclk * clock->m / (clock->n + 2);
524 clock->dot = clock->vco / clock->p;
525}
526
79e53945
JB		 527/**
528 * Returns whether any output on the specified pipe is of the specified type
529 */
4ef69c7a 530bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 531{
4ef69c7a 532 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 533 struct intel_encoder *encoder;
534
6c2b7c12
DV		 535 for_each_encoder_on_crtc(dev, crtc, encoder)
536 if (encoder->type == type)
4ef69c7a
CW		 537 return true;
538
539 return false;
79e53945
JB		 540}
541
7c04d1d9 542#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 543/**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
1b894b59
CW		 548static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
79e53945 551{
79e53945 552 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 553 INTELPllInvalid("p1 out of range\n");
79e53945 554 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 555 INTELPllInvalid("p out of range\n");
79e53945 556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 557 INTELPllInvalid("m2 out of range\n");
79e53945 558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 559 INTELPllInvalid("m1 out of range\n");
f2b115e6 560 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 561 INTELPllInvalid("m1 <= m2\n");
79e53945 562 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 563 INTELPllInvalid("m out of range\n");
79e53945 564 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 565 INTELPllInvalid("n out of range\n");
79e53945 566 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 567 INTELPllInvalid("vco out of range\n");
79e53945
JB		 568 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
569 * connector, etc., rather than just a single range.
570 */
571 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 572 INTELPllInvalid("dot out of range\n");
79e53945
JB		 573
574 return true;
575}
576
d4906093
ML		 577static bool
578intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 579 int target, int refclk, intel_clock_t *match_clock,
580 intel_clock_t *best_clock)
d4906093 581
79e53945
JB		 582{
583 struct drm_device *dev = crtc->dev;
79e53945 584 intel_clock_t clock;
79e53945
JB		 585 int err = target;
586
a210b028 587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 588 /*
a210b028
DV		 589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
79e53945 592 */
1974cad0 593 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 594 clock.p2 = limit->p2.p2_fast;
595 else
596 clock.p2 = limit->p2.p2_slow;
597 } else {
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
600 else
601 clock.p2 = limit->p2.p2_fast;
602 }
603
0206e353 604 memset(best_clock, 0, sizeof(*best_clock));
79e53945 605
42158660
ZY		 606 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
607 clock.m1++) {
608 for (clock.m2 = limit->m2.min;
609 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 610 /* m1 is always 0 in Pineview */
611 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 612 break;
613 for (clock.n = limit->n.min;
614 clock.n <= limit->n.max; clock.n++) {
615 for (clock.p1 = limit->p1.min;
616 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 617 int this_err;
618
2177832f 619 intel_clock(dev, refclk, &clock);
1b894b59
CW		 620 if (!intel_PLL_is_valid(dev, limit,
621 &clock))
79e53945 622 continue;
cec2f356
SP		 623 if (match_clock &&
624 clock.p != match_clock->p)
625 continue;
79e53945
JB		 626
627 this_err = abs(clock.dot - target);
628 if (this_err < err) {
629 *best_clock = clock;
630 err = this_err;
631 }
632 }
633 }
634 }
635 }
636
637 return (err != target);
638}
639
d4906093
ML		 640static bool
641intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
d4906093
ML		 644{
645 struct drm_device *dev = crtc->dev;
d4906093
ML		 646 intel_clock_t clock;
647 int max_n;
648 bool found;
6ba770dc
AJ		 649 /* approximately equals target * 0.00585 */
650 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 651 found = false;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 654 int lvds_reg;
655
c619eed4 656 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 657 lvds_reg = PCH_LVDS;
658 else
659 lvds_reg = LVDS;
1974cad0 660 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 661 clock.p2 = limit->p2.p2_fast;
662 else
663 clock.p2 = limit->p2.p2_slow;
664 } else {
665 if (target < limit->p2.dot_limit)
666 clock.p2 = limit->p2.p2_slow;
667 else
668 clock.p2 = limit->p2.p2_fast;
669 }
670
671 memset(best_clock, 0, sizeof(*best_clock));
672 max_n = limit->n.max;
f77f13e2 673 /* based on hardware requirement, prefer smaller n to precision */
d4906093 674 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 675 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 676 for (clock.m1 = limit->m1.max;
677 clock.m1 >= limit->m1.min; clock.m1--) {
678 for (clock.m2 = limit->m2.max;
679 clock.m2 >= limit->m2.min; clock.m2--) {
680 for (clock.p1 = limit->p1.max;
681 clock.p1 >= limit->p1.min; clock.p1--) {
682 int this_err;
683
2177832f 684 intel_clock(dev, refclk, &clock);
1b894b59
CW		 685 if (!intel_PLL_is_valid(dev, limit,
686 &clock))
d4906093 687 continue;
1b894b59
CW		 688
689 this_err = abs(clock.dot - target);
d4906093
ML		 690 if (this_err < err_most) {
691 *best_clock = clock;
692 err_most = this_err;
693 max_n = clock.n;
694 found = true;
695 }
696 }
697 }
698 }
699 }
2c07245f
ZW		 700 return found;
701}
702
a0c4da24
JB		 703static bool
704intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707{
708 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
709 u32 m, n, fastclk;
710 u32 updrate, minupdate, fracbits, p;
711 unsigned long bestppm, ppm, absppm;
712 int dotclk, flag;
713
af447bd3 714 flag = 0;
a0c4da24
JB		 715 dotclk = target * 1000;
716 bestppm = 1000000;
717 ppm = absppm = 0;
718 fastclk = dotclk / (2*100);
719 updrate = 0;
720 minupdate = 19200;
721 fracbits = 1;
722 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
723 bestm1 = bestm2 = bestp1 = bestp2 = 0;
724
725 /* based on hardware requirement, prefer smaller n to precision */
726 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
727 updrate = refclk / n;
728 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
729 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
730 if (p2 > 10)
731 p2 = p2 - 1;
732 p = p1 * p2;
733 /* based on hardware requirement, prefer bigger m1,m2 values */
734 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
735 m2 = (((2*(fastclk * p * n / m1 )) +
736 refclk) / (2*refclk));
737 m = m1 * m2;
738 vco = updrate * m;
739 if (vco >= limit->vco.min && vco < limit->vco.max) {
740 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
741 absppm = (ppm > 0) ? ppm : (-ppm);
742 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
743 bestppm = 0;
744 flag = 1;
745 }
746 if (absppm < bestppm - 10) {
747 bestppm = absppm;
748 flag = 1;
749 }
750 if (flag) {
751 bestn = n;
752 bestm1 = m1;
753 bestm2 = m2;
754 bestp1 = p1;
755 bestp2 = p2;
756 flag = 0;
757 }
758 }
759 }
760 }
761 }
762 }
763 best_clock->n = bestn;
764 best_clock->m1 = bestm1;
765 best_clock->m2 = bestm2;
766 best_clock->p1 = bestp1;
767 best_clock->p2 = bestp2;
768
769 return true;
770}
a4fc5ed6 771
a5c961d1
PZ		 772enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
773 enum pipe pipe)
774{
775 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
777
3b117c8f 778 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 779}
780
a928d536
PZ		 781static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
782{
783 struct drm_i915_private *dev_priv = dev->dev_private;
784 u32 frame, frame_reg = PIPEFRAME(pipe);
785
786 frame = I915_READ(frame_reg);
787
788 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
789 DRM_DEBUG_KMS("vblank wait timed out\n");
790}
791
9d0498a2
JB		 792/**
793 * intel_wait_for_vblank - wait for vblank on a given pipe
794 * @dev: drm device
795 * @pipe: pipe to wait for
796 *
797 * Wait for vblank to occur on a given pipe. Needed for various bits of
798 * mode setting code.
799 */
800void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 801{
9d0498a2 802 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 803 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 804
a928d536
PZ		 805 if (INTEL_INFO(dev)->gen >= 5) {
806 ironlake_wait_for_vblank(dev, pipe);
807 return;
808 }
809
300387c0
CW		 810 /* Clear existing vblank status. Note this will clear any other
811 * sticky status fields as well.
812 *
813 * This races with i915_driver_irq_handler() with the result
814 * that either function could miss a vblank event. Here it is not
815 * fatal, as we will either wait upon the next vblank interrupt or
816 * timeout. Generally speaking intel_wait_for_vblank() is only
817 * called during modeset at which time the GPU should be idle and
818 * should *not* be performing page flips and thus not waiting on
819 * vblanks...
820 * Currently, the result of us stealing a vblank from the irq
821 * handler is that a single frame will be skipped during swapbuffers.
822 */
823 I915_WRITE(pipestat_reg,
824 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
825
9d0498a2 826 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 827 if (wait_for(I915_READ(pipestat_reg) &
828 PIPE_VBLANK_INTERRUPT_STATUS,
829 50))
9d0498a2
JB		 830 DRM_DEBUG_KMS("vblank wait timed out\n");
831}
832
ab7ad7f6
KP		 833/*
834 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 835 * @dev: drm device
836 * @pipe: pipe to wait for
837 *
838 * After disabling a pipe, we can't wait for vblank in the usual way,
839 * spinning on the vblank interrupt status bit, since we won't actually
840 * see an interrupt when the pipe is disabled.
841 *
ab7ad7f6
KP		 842 * On Gen4 and above:
843 * wait for the pipe register state bit to turn off
844 *
845 * Otherwise:
846 * wait for the display line value to settle (it usually
847 * ends up stopping at the start of the next frame).
58e10eb9 848 *
9d0498a2 849 */
58e10eb9 850void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 851{
852 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 853 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
854 pipe);
ab7ad7f6
KP		 855
856 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 857 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 858
859 /* Wait for the Pipe State to go off */
58e10eb9
CW		 860 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
861 100))
284637d9 862 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 863 } else {
837ba00f 864 u32 last_line, line_mask;
58e10eb9 865 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 866 unsigned long timeout = jiffies + msecs_to_jiffies(100);
867
837ba00f
PZ		 868 if (IS_GEN2(dev))
869 line_mask = DSL_LINEMASK_GEN2;
870 else
871 line_mask = DSL_LINEMASK_GEN3;
872
ab7ad7f6
KP		 873 /* Wait for the display line to settle */
874 do {
837ba00f 875 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 876 mdelay(5);
837ba00f 877 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 878 time_after(timeout, jiffies));
879 if (time_after(jiffies, timeout))
284637d9 880 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 881 }
79e53945
JB		 882}
883
b0ea7d37
DL		 884/*
885 * ibx_digital_port_connected - is the specified port connected?
886 * @dev_priv: i915 private structure
887 * @port: the port to test
888 *
889 * Returns true if @port is connected, false otherwise.
890 */
891bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
892 struct intel_digital_port *port)
893{
894 u32 bit;
895
c36346e3
DL		 896 if (HAS_PCH_IBX(dev_priv->dev)) {
897 switch(port->port) {
898 case PORT_B:
899 bit = SDE_PORTB_HOTPLUG;
900 break;
901 case PORT_C:
902 bit = SDE_PORTC_HOTPLUG;
903 break;
904 case PORT_D:
905 bit = SDE_PORTD_HOTPLUG;
906 break;
907 default:
908 return true;
909 }
910 } else {
911 switch(port->port) {
912 case PORT_B:
913 bit = SDE_PORTB_HOTPLUG_CPT;
914 break;
915 case PORT_C:
916 bit = SDE_PORTC_HOTPLUG_CPT;
917 break;
918 case PORT_D:
919 bit = SDE_PORTD_HOTPLUG_CPT;
920 break;
921 default:
922 return true;
923 }
b0ea7d37
DL		 924 }
925
926 return I915_READ(SDEISR) & bit;
927}
928
b24e7179
JB		 929static const char *state_string(bool enabled)
930{
931 return enabled ? "on" : "off";
932}
933
934/* Only for pre-ILK configs */
935static void assert_pll(struct drm_i915_private *dev_priv,
936 enum pipe pipe, bool state)
937{
938 int reg;
939 u32 val;
940 bool cur_state;
941
942 reg = DPLL(pipe);
943 val = I915_READ(reg);
944 cur_state = !!(val & DPLL_VCO_ENABLE);
945 WARN(cur_state != state,
946 "PLL state assertion failure (expected %s, current %s)\n",
947 state_string(state), state_string(cur_state));
948}
949#define assert_pll_enabled(d, p) assert_pll(d, p, true)
950#define assert_pll_disabled(d, p) assert_pll(d, p, false)
951
040484af
JB		 952/* For ILK+ */
953static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 954 struct intel_pch_pll *pll,
955 struct intel_crtc *crtc,
956 bool state)
040484af 957{
040484af
JB		 958 u32 val;
959 bool cur_state;
960
9d82aa17
ED		 961 if (HAS_PCH_LPT(dev_priv->dev)) {
962 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
963 return;
964 }
965
92b27b08
CW		 966 if (WARN (!pll,
967 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 968 return;
ee7b9f93 969
92b27b08
CW		 970 val = I915_READ(pll->pll_reg);
971 cur_state = !!(val & DPLL_VCO_ENABLE);
972 WARN(cur_state != state,
973 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
974 pll->pll_reg, state_string(state), state_string(cur_state), val);
975
976 /* Make sure the selected PLL is correctly attached to the transcoder */
977 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 978 u32 pch_dpll;
979
980 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 981 cur_state = pll->pll_reg == _PCH_DPLL_B;
982 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 983 "PLL[%d] not attached to this transcoder %c: %08x\n",
984 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 985 cur_state = !!(val >> (4*crtc->pipe + 3));
986 WARN(cur_state != state,
4bb6f1f3 987 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 988 pll->pll_reg == _PCH_DPLL_B,
989 state_string(state),
4bb6f1f3 990 pipe_name(crtc->pipe),
92b27b08
CW		 991 val);
992 }
d3ccbe86 993 }
040484af 994}
92b27b08
CW		 995#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
996#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 997
998static void assert_fdi_tx(struct drm_i915_private *dev_priv,
999 enum pipe pipe, bool state)
1000{
1001 int reg;
1002 u32 val;
1003 bool cur_state;
ad80a810
PZ		 1004 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1005 pipe);
040484af 1006
affa9354
PZ		 1007 if (HAS_DDI(dev_priv->dev)) {
1008 /* DDI does not have a specific FDI_TX register */
ad80a810 1009 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1010 val = I915_READ(reg);
ad80a810 1011 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1012 } else {
1013 reg = FDI_TX_CTL(pipe);
1014 val = I915_READ(reg);
1015 cur_state = !!(val & FDI_TX_ENABLE);
1016 }
040484af
JB		 1017 WARN(cur_state != state,
1018 "FDI TX state assertion failure (expected %s, current %s)\n",
1019 state_string(state), state_string(cur_state));
1020}
1021#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1022#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1023
1024static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, bool state)
1026{
1027 int reg;
1028 u32 val;
1029 bool cur_state;
1030
d63fa0dc
PZ		 1031 reg = FDI_RX_CTL(pipe);
1032 val = I915_READ(reg);
1033 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1034 WARN(cur_state != state,
1035 "FDI RX state assertion failure (expected %s, current %s)\n",
1036 state_string(state), state_string(cur_state));
1037}
1038#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1039#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1040
1041static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1042 enum pipe pipe)
1043{
1044 int reg;
1045 u32 val;
1046
1047 /* ILK FDI PLL is always enabled */
1048 if (dev_priv->info->gen == 5)
1049 return;
1050
bf507ef7 1051 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1052 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1053 return;
1054
040484af
JB		 1055 reg = FDI_TX_CTL(pipe);
1056 val = I915_READ(reg);
1057 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1058}
1059
1060static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int reg;
1064 u32 val;
1065
1066 reg = FDI_RX_CTL(pipe);
1067 val = I915_READ(reg);
1068 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1069}
1070
ea0760cf
JB		 1071static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1072 enum pipe pipe)
1073{
1074 int pp_reg, lvds_reg;
1075 u32 val;
1076 enum pipe panel_pipe = PIPE_A;
0de3b485 1077 bool locked = true;
ea0760cf
JB		 1078
1079 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1080 pp_reg = PCH_PP_CONTROL;
1081 lvds_reg = PCH_LVDS;
1082 } else {
1083 pp_reg = PP_CONTROL;
1084 lvds_reg = LVDS;
1085 }
1086
1087 val = I915_READ(pp_reg);
1088 if (!(val & PANEL_POWER_ON) ||
1089 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1090 locked = false;
1091
1092 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1093 panel_pipe = PIPE_B;
1094
1095 WARN(panel_pipe == pipe && locked,
1096 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1097 pipe_name(pipe));
ea0760cf
JB		 1098}
1099
b840d907
JB		 1100void assert_pipe(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
b24e7179
JB		 1102{
1103 int reg;
1104 u32 val;
63d7bbe9 1105 bool cur_state;
702e7a56
PZ		 1106 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1107 pipe);
b24e7179 1108
8e636784
DV		 1109 /* if we need the pipe A quirk it must be always on */
1110 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1111 state = true;
1112
15d199ea
PZ		 1113 if (!intel_using_power_well(dev_priv->dev) &&
1114 cpu_transcoder != TRANSCODER_EDP) {
69310161
PZ		 1115 cur_state = false;
1116 } else {
1117 reg = PIPECONF(cpu_transcoder);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & PIPECONF_ENABLE);
1120 }
1121
63d7bbe9
JB		 1122 WARN(cur_state != state,
1123 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1124 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1125}
1126
931872fc
CW		 1127static void assert_plane(struct drm_i915_private *dev_priv,
1128 enum plane plane, bool state)
b24e7179
JB		 1129{
1130 int reg;
1131 u32 val;
931872fc 1132 bool cur_state;
b24e7179
JB		 1133
1134 reg = DSPCNTR(plane);
1135 val = I915_READ(reg);
931872fc
CW		 1136 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1137 WARN(cur_state != state,
1138 "plane %c assertion failure (expected %s, current %s)\n",
1139 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1140}
1141
931872fc
CW		 1142#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1143#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1144
b24e7179
JB		 1145static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
1148 int reg, i;
1149 u32 val;
1150 int cur_pipe;
1151
19ec1358 1152 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1153 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1154 reg = DSPCNTR(pipe);
1155 val = I915_READ(reg);
1156 WARN((val & DISPLAY_PLANE_ENABLE),
1157 "plane %c assertion failure, should be disabled but not\n",
1158 plane_name(pipe));
19ec1358 1159 return;
28c05794 1160 }
19ec1358 1161
b24e7179
JB		 1162 /* Need to check both planes against the pipe */
1163 for (i = 0; i < 2; i++) {
1164 reg = DSPCNTR(i);
1165 val = I915_READ(reg);
1166 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1167 DISPPLANE_SEL_PIPE_SHIFT;
1168 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1169 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1170 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1171 }
1172}
1173
19332d7a
JB		 1174static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1175 enum pipe pipe)
1176{
1177 int reg, i;
1178 u32 val;
1179
1180 if (!IS_VALLEYVIEW(dev_priv->dev))
1181 return;
1182
1183 /* Need to check both planes against the pipe */
1184 for (i = 0; i < dev_priv->num_plane; i++) {
1185 reg = SPCNTR(pipe, i);
1186 val = I915_READ(reg);
1187 WARN((val & SP_ENABLE),
06da8da2
VS		 1188 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1189 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1190 }
1191}
1192
92f2584a
JB		 1193static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1194{
1195 u32 val;
1196 bool enabled;
1197
9d82aa17
ED		 1198 if (HAS_PCH_LPT(dev_priv->dev)) {
1199 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1200 return;
1201 }
1202
92f2584a
JB		 1203 val = I915_READ(PCH_DREF_CONTROL);
1204 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1205 DREF_SUPERSPREAD_SOURCE_MASK));
1206 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1207}
1208
1209static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
1211{
1212 int reg;
1213 u32 val;
1214 bool enabled;
1215
1216 reg = TRANSCONF(pipe);
1217 val = I915_READ(reg);
1218 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1219 WARN(enabled,
1220 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1221 pipe_name(pipe));
92f2584a
JB		 1222}
1223
4e634389
KP		 1224static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1226{
1227 if ((val & DP_PORT_EN) == 0)
1228 return false;
1229
1230 if (HAS_PCH_CPT(dev_priv->dev)) {
1231 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1232 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1233 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1234 return false;
1235 } else {
1236 if ((val & DP_PIPE_MASK) != (pipe << 30))
1237 return false;
1238 }
1239 return true;
1240}
1241
1519b995
KP		 1242static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 val)
1244{
dc0fa718 1245 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1246 return false;
1247
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1249 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1250 return false;
1251 } else {
dc0fa718 1252 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1253 return false;
1254 }
1255 return true;
1256}
1257
1258static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, u32 val)
1260{
1261 if ((val & LVDS_PORT_EN) == 0)
1262 return false;
1263
1264 if (HAS_PCH_CPT(dev_priv->dev)) {
1265 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1266 return false;
1267 } else {
1268 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1269 return false;
1270 }
1271 return true;
1272}
1273
1274static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, u32 val)
1276{
1277 if ((val & ADPA_DAC_ENABLE) == 0)
1278 return false;
1279 if (HAS_PCH_CPT(dev_priv->dev)) {
1280 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281 return false;
1282 } else {
1283 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1284 return false;
1285 }
1286 return true;
1287}
1288
291906f1 1289static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1290 enum pipe pipe, int reg, u32 port_sel)
291906f1 1291{
47a05eca 1292 u32 val = I915_READ(reg);
4e634389 1293 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1294 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1295 reg, pipe_name(pipe));
de9a35ab 1296
75c5da27
DV		 1297 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1298 && (val & DP_PIPEB_SELECT),
de9a35ab 1299 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1300}
1301
1302static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1303 enum pipe pipe, int reg)
1304{
47a05eca 1305 u32 val = I915_READ(reg);
b70ad586 1306 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1307 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1308 reg, pipe_name(pipe));
de9a35ab 1309
dc0fa718 1310 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1311 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1312 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1313}
1314
1315static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1316 enum pipe pipe)
1317{
1318 int reg;
1319 u32 val;
291906f1 1320
f0575e92
KP		 1321 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1322 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1323 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1324
1325 reg = PCH_ADPA;
1326 val = I915_READ(reg);
b70ad586 1327 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1328 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 pipe_name(pipe));
291906f1
JB		 1330
1331 reg = PCH_LVDS;
1332 val = I915_READ(reg);
b70ad586 1333 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1334 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1335 pipe_name(pipe));
291906f1 1336
e2debe91
PZ		 1337 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1338 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1339 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1340}
1341
63d7bbe9
JB		 1342/**
1343 * intel_enable_pll - enable a PLL
1344 * @dev_priv: i915 private structure
1345 * @pipe: pipe PLL to enable
1346 *
1347 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1348 * make sure the PLL reg is writable first though, since the panel write
1349 * protect mechanism may be enabled.
1350 *
1351 * Note! This is for pre-ILK only.
7434a255
TR		 1352 *
1353 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1354 */
1355static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1356{
1357 int reg;
1358 u32 val;
1359
58c6eaa2
DV		 1360 assert_pipe_disabled(dev_priv, pipe);
1361
63d7bbe9 1362 /* No really, not for ILK+ */
a0c4da24 1363 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1364
1365 /* PLL is protected by panel, make sure we can write it */
1366 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1367 assert_panel_unlocked(dev_priv, pipe);
1368
1369 reg = DPLL(pipe);
1370 val = I915_READ(reg);
1371 val |= DPLL_VCO_ENABLE;
1372
1373 /* We do this three times for luck */
1374 I915_WRITE(reg, val);
1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
1377 I915_WRITE(reg, val);
1378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
1380 I915_WRITE(reg, val);
1381 POSTING_READ(reg);
1382 udelay(150); /* wait for warmup */
1383}
1384
1385/**
1386 * intel_disable_pll - disable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to disable
1389 *
1390 * Disable the PLL for @pipe, making sure the pipe is off first.
1391 *
1392 * Note! This is for pre-ILK only.
1393 */
1394static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395{
1396 int reg;
1397 u32 val;
1398
1399 /* Don't disable pipe A or pipe A PLLs if needed */
1400 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401 return;
1402
1403 /* Make sure the pipe isn't still relying on us */
1404 assert_pipe_disabled(dev_priv, pipe);
1405
1406 reg = DPLL(pipe);
1407 val = I915_READ(reg);
1408 val &= ~DPLL_VCO_ENABLE;
1409 I915_WRITE(reg, val);
1410 POSTING_READ(reg);
1411}
1412
a416edef
ED		 1413/* SBI access */
1414static void
988d6ee8
PZ		 1415intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1416 enum intel_sbi_destination destination)
a416edef 1417{
988d6ee8 1418 u32 tmp;
a416edef 1419
09153000 1420 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1421
39fb50f6 1422 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1423 100)) {
1424 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1425 return;
a416edef
ED		 1426 }
1427
988d6ee8
PZ		 1428 I915_WRITE(SBI_ADDR, (reg << 16));
1429 I915_WRITE(SBI_DATA, value);
1430
1431 if (destination == SBI_ICLK)
1432 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1433 else
1434 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1435 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1436
39fb50f6 1437 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1438 100)) {
1439 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1440 return;
a416edef 1441 }
a416edef
ED		 1442}
1443
1444static u32
988d6ee8
PZ		 1445intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1446 enum intel_sbi_destination destination)
a416edef 1447{
39fb50f6 1448 u32 value = 0;
09153000 1449 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1450
39fb50f6 1451 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1452 100)) {
1453 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1454 return 0;
a416edef
ED		 1455 }
1456
988d6ee8
PZ		 1457 I915_WRITE(SBI_ADDR, (reg << 16));
1458
1459 if (destination == SBI_ICLK)
1460 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1461 else
1462 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1463 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1464
39fb50f6 1465 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1466 100)) {
1467 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1468 return 0;
a416edef
ED		 1469 }
1470
09153000 1471 return I915_READ(SBI_DATA);
a416edef
ED		 1472}
1473
89b667f8
JB		 1474void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1475{
1476 u32 port_mask;
1477
1478 if (!port)
1479 port_mask = DPLL_PORTB_READY_MASK;
1480 else
1481 port_mask = DPLL_PORTC_READY_MASK;
1482
1483 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1484 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1485 'B' + port, I915_READ(DPLL(0)));
1486}
1487
92f2584a 1488/**
b6b4e185 1489 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1490 * @dev_priv: i915 private structure
1491 * @pipe: pipe PLL to enable
1492 *
1493 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1494 * drives the transcoder clock.
1495 */
b6b4e185 1496static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1497{
ee7b9f93 1498 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1499 struct intel_pch_pll *pll;
92f2584a
JB		 1500 int reg;
1501 u32 val;
1502
48da64a8 1503 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1504 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1505 pll = intel_crtc->pch_pll;
1506 if (pll == NULL)
1507 return;
1508
1509 if (WARN_ON(pll->refcount == 0))
1510 return;
ee7b9f93
JB		 1511
1512 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1513 pll->pll_reg, pll->active, pll->on,
1514 intel_crtc->base.base.id);
92f2584a
JB		 1515
1516 /* PCH refclock must be enabled first */
1517 assert_pch_refclk_enabled(dev_priv);
1518
ee7b9f93 1519 if (pll->active++ && pll->on) {
92b27b08 1520 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1521 return;
1522 }
1523
1524 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1525
1526 reg = pll->pll_reg;
92f2584a
JB		 1527 val = I915_READ(reg);
1528 val |= DPLL_VCO_ENABLE;
1529 I915_WRITE(reg, val);
1530 POSTING_READ(reg);
1531 udelay(200);
ee7b9f93
JB		 1532
1533 pll->on = true;
92f2584a
JB		 1534}
1535
ee7b9f93 1536static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1537{
ee7b9f93
JB		 1538 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1539 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1540 int reg;
ee7b9f93 1541 u32 val;
4c609cb8 1542
92f2584a
JB		 1543 /* PCH only available on ILK+ */
1544 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1545 if (pll == NULL)
1546 return;
92f2584a 1547
48da64a8
CW		 1548 if (WARN_ON(pll->refcount == 0))
1549 return;
7a419866 1550
ee7b9f93
JB		 1551 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1552 pll->pll_reg, pll->active, pll->on,
1553 intel_crtc->base.base.id);
7a419866 1554
48da64a8 1555 if (WARN_ON(pll->active == 0)) {
92b27b08 1556 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1557 return;
1558 }
1559
ee7b9f93 1560 if (--pll->active) {
92b27b08 1561 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1562 return;
ee7b9f93
JB		 1563 }
1564
1565 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1566
1567 /* Make sure transcoder isn't still depending on us */
1568 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1569
ee7b9f93 1570 reg = pll->pll_reg;
92f2584a
JB		 1571 val = I915_READ(reg);
1572 val &= ~DPLL_VCO_ENABLE;
1573 I915_WRITE(reg, val);
1574 POSTING_READ(reg);
1575 udelay(200);
ee7b9f93
JB		 1576
1577 pll->on = false;
92f2584a
JB		 1578}
1579
b8a4f404
PZ		 1580static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581 enum pipe pipe)
040484af 1582{
23670b32 1583 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1584 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1585 uint32_t reg, val, pipeconf_val;
040484af
JB		 1586
1587 /* PCH only available on ILK+ */
1588 BUG_ON(dev_priv->info->gen < 5);
1589
1590 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1591 assert_pch_pll_enabled(dev_priv,
1592 to_intel_crtc(crtc)->pch_pll,
1593 to_intel_crtc(crtc));
040484af
JB		 1594
1595 /* FDI must be feeding us bits for PCH ports */
1596 assert_fdi_tx_enabled(dev_priv, pipe);
1597 assert_fdi_rx_enabled(dev_priv, pipe);
1598
23670b32
DV		 1599 if (HAS_PCH_CPT(dev)) {
1600 /* Workaround: Set the timing override bit before enabling the
1601 * pch transcoder. */
1602 reg = TRANS_CHICKEN2(pipe);
1603 val = I915_READ(reg);
1604 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605 I915_WRITE(reg, val);
59c859d6 1606 }
23670b32 1607
040484af
JB		 1608 reg = TRANSCONF(pipe);
1609 val = I915_READ(reg);
5f7f726d 1610 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1611
1612 if (HAS_PCH_IBX(dev_priv->dev)) {
1613 /*
1614 * make the BPC in transcoder be consistent with
1615 * that in pipeconf reg.
1616 */
dfd07d72
DV		 1617 val &= ~PIPECONF_BPC_MASK;
1618 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1619 }
5f7f726d
PZ		 1620
1621 val &= ~TRANS_INTERLACE_MASK;
1622 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1623 if (HAS_PCH_IBX(dev_priv->dev) &&
1624 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625 val |= TRANS_LEGACY_INTERLACED_ILK;
1626 else
1627 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1628 else
1629 val |= TRANS_PROGRESSIVE;
1630
040484af
JB		 1631 I915_WRITE(reg, val | TRANS_ENABLE);
1632 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1633 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1634}
1635
8fb033d7 1636static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1637 enum transcoder cpu_transcoder)
040484af 1638{
8fb033d7 1639 u32 val, pipeconf_val;
8fb033d7
PZ		 1640
1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv->info->gen < 5);
1643
8fb033d7 1644 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1645 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1646 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1647
223a6fdf
PZ		 1648 /* Workaround: set timing override bit. */
1649 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1650 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1651 I915_WRITE(_TRANSA_CHICKEN2, val);
1652
25f3ef11 1653 val = TRANS_ENABLE;
937bb610 1654 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1655
9a76b1c6
PZ		 1656 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657 PIPECONF_INTERLACED_ILK)
a35f2679 1658 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1659 else
1660 val |= TRANS_PROGRESSIVE;
1661
25f3ef11 1662 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1663 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1664 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1665}
1666
b8a4f404
PZ		 1667static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668 enum pipe pipe)
040484af 1669{
23670b32
DV		 1670 struct drm_device *dev = dev_priv->dev;
1671 uint32_t reg, val;
040484af
JB		 1672
1673 /* FDI relies on the transcoder */
1674 assert_fdi_tx_disabled(dev_priv, pipe);
1675 assert_fdi_rx_disabled(dev_priv, pipe);
1676
291906f1
JB		 1677 /* Ports must be off as well */
1678 assert_pch_ports_disabled(dev_priv, pipe);
1679
040484af
JB		 1680 reg = TRANSCONF(pipe);
1681 val = I915_READ(reg);
1682 val &= ~TRANS_ENABLE;
1683 I915_WRITE(reg, val);
1684 /* wait for PCH transcoder off, transcoder state */
1685 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1686 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1687
1688 if (!HAS_PCH_IBX(dev)) {
1689 /* Workaround: Clear the timing override chicken bit again. */
1690 reg = TRANS_CHICKEN2(pipe);
1691 val = I915_READ(reg);
1692 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693 I915_WRITE(reg, val);
1694 }
040484af
JB		 1695}
1696
ab4d966c 1697static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1698{
8fb033d7
PZ		 1699 u32 val;
1700
8a52fd9f 1701 val = I915_READ(_TRANSACONF);
8fb033d7 1702 val &= ~TRANS_ENABLE;
8a52fd9f 1703 I915_WRITE(_TRANSACONF, val);
8fb033d7 1704 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1705 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1706 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1707
1708 /* Workaround: clear timing override bit. */
1709 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1710 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1711 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1712}
1713
b24e7179 1714/**
309cfea8 1715 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1716 * @dev_priv: i915 private structure
1717 * @pipe: pipe to enable
040484af 1718 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1719 *
1720 * Enable @pipe, making sure that various hardware specific requirements
1721 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722 *
1723 * @pipe should be %PIPE_A or %PIPE_B.
1724 *
1725 * Will wait until the pipe is actually running (i.e. first vblank) before
1726 * returning.
1727 */
040484af
JB		 1728static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729 bool pch_port)
b24e7179 1730{
702e7a56
PZ		 1731 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732 pipe);
1a240d4d 1733 enum pipe pch_transcoder;
b24e7179
JB		 1734 int reg;
1735 u32 val;
1736
58c6eaa2
DV		 1737 assert_planes_disabled(dev_priv, pipe);
1738 assert_sprites_disabled(dev_priv, pipe);
1739
681e5811 1740 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1741 pch_transcoder = TRANSCODER_A;
1742 else
1743 pch_transcoder = pipe;
1744
b24e7179
JB		 1745 /*
1746 * A pipe without a PLL won't actually be able to drive bits from
1747 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1748 * need the check.
1749 */
1750 if (!HAS_PCH_SPLIT(dev_priv->dev))
1751 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1752 else {
1753 if (pch_port) {
1754 /* if driving the PCH, we need FDI enabled */
cc391bbb 1755 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1756 assert_fdi_tx_pll_enabled(dev_priv,
1757 (enum pipe) cpu_transcoder);
040484af
JB		 1758 }
1759 /* FIXME: assert CPU port conditions for SNB+ */
1760 }
b24e7179 1761
702e7a56 1762 reg = PIPECONF(cpu_transcoder);
b24e7179 1763 val = I915_READ(reg);
00d70b15
CW		 1764 if (val & PIPECONF_ENABLE)
1765 return;
1766
1767 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1768 intel_wait_for_vblank(dev_priv->dev, pipe);
1769}
1770
1771/**
309cfea8 1772 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1773 * @dev_priv: i915 private structure
1774 * @pipe: pipe to disable
1775 *
1776 * Disable @pipe, making sure that various hardware specific requirements
1777 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1778 *
1779 * @pipe should be %PIPE_A or %PIPE_B.
1780 *
1781 * Will wait until the pipe has shut down before returning.
1782 */
1783static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1784 enum pipe pipe)
1785{
702e7a56
PZ		 1786 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1787 pipe);
b24e7179
JB		 1788 int reg;
1789 u32 val;
1790
1791 /*
1792 * Make sure planes won't keep trying to pump pixels to us,
1793 * or we might hang the display.
1794 */
1795 assert_planes_disabled(dev_priv, pipe);
19332d7a 1796 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1797
1798 /* Don't disable pipe A or pipe A PLLs if needed */
1799 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1800 return;
1801
702e7a56 1802 reg = PIPECONF(cpu_transcoder);
b24e7179 1803 val = I915_READ(reg);
00d70b15
CW		 1804 if ((val & PIPECONF_ENABLE) == 0)
1805 return;
1806
1807 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1808 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1809}
1810
d74362c9
KP		 1811/*
1812 * Plane regs are double buffered, going from enabled->disabled needs a
1813 * trigger in order to latch. The display address reg provides this.
1814 */
6f1d69b0 1815void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1816 enum plane plane)
1817{
14f86147
DL		 1818 if (dev_priv->info->gen >= 4)
1819 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1820 else
1821 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1822}
1823
b24e7179
JB		 1824/**
1825 * intel_enable_plane - enable a display plane on a given pipe
1826 * @dev_priv: i915 private structure
1827 * @plane: plane to enable
1828 * @pipe: pipe being fed
1829 *
1830 * Enable @plane on @pipe, making sure that @pipe is running first.
1831 */
1832static void intel_enable_plane(struct drm_i915_private *dev_priv,
1833 enum plane plane, enum pipe pipe)
1834{
1835 int reg;
1836 u32 val;
1837
1838 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839 assert_pipe_enabled(dev_priv, pipe);
1840
1841 reg = DSPCNTR(plane);
1842 val = I915_READ(reg);
00d70b15
CW		 1843 if (val & DISPLAY_PLANE_ENABLE)
1844 return;
1845
1846 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1847 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1848 intel_wait_for_vblank(dev_priv->dev, pipe);
1849}
1850
b24e7179
JB		 1851/**
1852 * intel_disable_plane - disable a display plane
1853 * @dev_priv: i915 private structure
1854 * @plane: plane to disable
1855 * @pipe: pipe consuming the data
1856 *
1857 * Disable @plane; should be an independent operation.
1858 */
1859static void intel_disable_plane(struct drm_i915_private *dev_priv,
1860 enum plane plane, enum pipe pipe)
1861{
1862 int reg;
1863 u32 val;
1864
1865 reg = DSPCNTR(plane);
1866 val = I915_READ(reg);
00d70b15
CW		 1867 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1868 return;
1869
1870 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1871 intel_flush_display_plane(dev_priv, plane);
1872 intel_wait_for_vblank(dev_priv->dev, pipe);
1873}
1874
693db184
CW		 1875static bool need_vtd_wa(struct drm_device *dev)
1876{
1877#ifdef CONFIG_INTEL_IOMMU
1878 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1879 return true;
1880#endif
1881 return false;
1882}
1883
127bd2ac 1884int
48b956c5 1885intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1886 struct drm_i915_gem_object *obj,
919926ae 1887 struct intel_ring_buffer *pipelined)
6b95a207 1888{
ce453d81 1889 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1890 u32 alignment;
1891 int ret;
1892
05394f39 1893 switch (obj->tiling_mode) {
6b95a207 1894 case I915_TILING_NONE:
534843da
CW		 1895 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1896 alignment = 128 * 1024;
a6c45cf0 1897 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1898 alignment = 4 * 1024;
1899 else
1900 alignment = 64 * 1024;
6b95a207
KH		 1901 break;
1902 case I915_TILING_X:
1903 /* pin() will align the object as required by fence */
1904 alignment = 0;
1905 break;
1906 case I915_TILING_Y:
8bb6e959
DV		 1907 /* Despite that we check this in framebuffer_init userspace can
1908 * screw us over and change the tiling after the fact. Only
1909 * pinned buffers can't change their tiling. */
1910 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1911 return -EINVAL;
1912 default:
1913 BUG();
1914 }
1915
693db184
CW		 1916 /* Note that the w/a also requires 64 PTE of padding following the
1917 * bo. We currently fill all unused PTE with the shadow page and so
1918 * we should always have valid PTE following the scanout preventing
1919 * the VT-d warning.
1920 */
1921 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1922 alignment = 256 * 1024;
1923
ce453d81 1924 dev_priv->mm.interruptible = false;
2da3b9b9 1925 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1926 if (ret)
ce453d81 1927 goto err_interruptible;
6b95a207
KH		 1928
1929 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930 * fence, whereas 965+ only requires a fence if using
1931 * framebuffer compression. For simplicity, we always install
1932 * a fence as the cost is not that onerous.
1933 */
06d98131 1934 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1935 if (ret)
1936 goto err_unpin;
1690e1eb 1937
9a5a53b3 1938 i915_gem_object_pin_fence(obj);
6b95a207 1939
ce453d81 1940 dev_priv->mm.interruptible = true;
6b95a207 1941 return 0;
48b956c5
CW		 1942
1943err_unpin:
1944 i915_gem_object_unpin(obj);
ce453d81
CW		 1945err_interruptible:
1946 dev_priv->mm.interruptible = true;
48b956c5 1947 return ret;
6b95a207
KH		 1948}
1949
1690e1eb
CW		 1950void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951{
1952 i915_gem_object_unpin_fence(obj);
1953 i915_gem_object_unpin(obj);
1954}
1955
c2c75131
DV		 1956/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957 * is assumed to be a power-of-two. */
bc752862
CW		 1958unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1959 unsigned int tiling_mode,
1960 unsigned int cpp,
1961 unsigned int pitch)
c2c75131 1962{
bc752862
CW		 1963 if (tiling_mode != I915_TILING_NONE) {
1964 unsigned int tile_rows, tiles;
c2c75131 1965
bc752862
CW		 1966 tile_rows = *y / 8;
1967 *y %= 8;
c2c75131 1968
bc752862
CW		 1969 tiles = *x / (512/cpp);
1970 *x %= 512/cpp;
1971
1972 return tile_rows * pitch * 8 + tiles * 4096;
1973 } else {
1974 unsigned int offset;
1975
1976 offset = *y * pitch + *x * cpp;
1977 *y = 0;
1978 *x = (offset & 4095) / cpp;
1979 return offset & -4096;
1980 }
c2c75131
DV		 1981}
1982
17638cd6
JB		 1983static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1984 int x, int y)
81255565
JB		 1985{
1986 struct drm_device *dev = crtc->dev;
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1989 struct intel_framebuffer *intel_fb;
05394f39 1990 struct drm_i915_gem_object *obj;
81255565 1991 int plane = intel_crtc->plane;
e506a0c6 1992 unsigned long linear_offset;
81255565 1993 u32 dspcntr;
5eddb70b 1994 u32 reg;
81255565
JB		 1995
1996 switch (plane) {
1997 case 0:
1998 case 1:
1999 break;
2000 default:
84f44ce7 2001 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2002 return -EINVAL;
2003 }
2004
2005 intel_fb = to_intel_framebuffer(fb);
2006 obj = intel_fb->obj;
81255565 2007
5eddb70b
CW		 2008 reg = DSPCNTR(plane);
2009 dspcntr = I915_READ(reg);
81255565
JB		 2010 /* Mask out pixel format bits in case we change it */
2011 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2012 switch (fb->pixel_format) {
2013 case DRM_FORMAT_C8:
81255565
JB		 2014 dspcntr |= DISPPLANE_8BPP;
2015 break;
57779d06
VS		 2016 case DRM_FORMAT_XRGB1555:
2017 case DRM_FORMAT_ARGB1555:
2018 dspcntr |= DISPPLANE_BGRX555;
81255565 2019 break;
57779d06
VS		 2020 case DRM_FORMAT_RGB565:
2021 dspcntr |= DISPPLANE_BGRX565;
2022 break;
2023 case DRM_FORMAT_XRGB8888:
2024 case DRM_FORMAT_ARGB8888:
2025 dspcntr |= DISPPLANE_BGRX888;
2026 break;
2027 case DRM_FORMAT_XBGR8888:
2028 case DRM_FORMAT_ABGR8888:
2029 dspcntr |= DISPPLANE_RGBX888;
2030 break;
2031 case DRM_FORMAT_XRGB2101010:
2032 case DRM_FORMAT_ARGB2101010:
2033 dspcntr |= DISPPLANE_BGRX101010;
2034 break;
2035 case DRM_FORMAT_XBGR2101010:
2036 case DRM_FORMAT_ABGR2101010:
2037 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2038 break;
2039 default:
baba133a 2040 BUG();
81255565 2041 }
57779d06 2042
a6c45cf0 2043 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2044 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2045 dspcntr |= DISPPLANE_TILED;
2046 else
2047 dspcntr &= ~DISPPLANE_TILED;
2048 }
2049
5eddb70b 2050 I915_WRITE(reg, dspcntr);
81255565 2051
e506a0c6 2052 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2053
c2c75131
DV		 2054 if (INTEL_INFO(dev)->gen >= 4) {
2055 intel_crtc->dspaddr_offset =
bc752862
CW		 2056 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2057 fb->bits_per_pixel / 8,
2058 fb->pitches[0]);
c2c75131
DV		 2059 linear_offset -= intel_crtc->dspaddr_offset;
2060 } else {
e506a0c6 2061 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2062 }
e506a0c6
DV		 2063
2064 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2065 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2066 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2067 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2068 I915_MODIFY_DISPBASE(DSPSURF(plane),
2069 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2070 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2071 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2072 } else
e506a0c6 2073 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2074 POSTING_READ(reg);
81255565 2075
17638cd6
JB		 2076 return 0;
2077}
2078
2079static int ironlake_update_plane(struct drm_crtc *crtc,
2080 struct drm_framebuffer *fb, int x, int y)
2081{
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
2086 struct drm_i915_gem_object *obj;
2087 int plane = intel_crtc->plane;
e506a0c6 2088 unsigned long linear_offset;
17638cd6
JB		 2089 u32 dspcntr;
2090 u32 reg;
2091
2092 switch (plane) {
2093 case 0:
2094 case 1:
27f8227b 2095 case 2:
17638cd6
JB		 2096 break;
2097 default:
84f44ce7 2098 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2099 return -EINVAL;
2100 }
2101
2102 intel_fb = to_intel_framebuffer(fb);
2103 obj = intel_fb->obj;
2104
2105 reg = DSPCNTR(plane);
2106 dspcntr = I915_READ(reg);
2107 /* Mask out pixel format bits in case we change it */
2108 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2109 switch (fb->pixel_format) {
2110 case DRM_FORMAT_C8:
17638cd6
JB		 2111 dspcntr |= DISPPLANE_8BPP;
2112 break;
57779d06
VS		 2113 case DRM_FORMAT_RGB565:
2114 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2115 break;
57779d06
VS		 2116 case DRM_FORMAT_XRGB8888:
2117 case DRM_FORMAT_ARGB8888:
2118 dspcntr |= DISPPLANE_BGRX888;
2119 break;
2120 case DRM_FORMAT_XBGR8888:
2121 case DRM_FORMAT_ABGR8888:
2122 dspcntr |= DISPPLANE_RGBX888;
2123 break;
2124 case DRM_FORMAT_XRGB2101010:
2125 case DRM_FORMAT_ARGB2101010:
2126 dspcntr |= DISPPLANE_BGRX101010;
2127 break;
2128 case DRM_FORMAT_XBGR2101010:
2129 case DRM_FORMAT_ABGR2101010:
2130 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2131 break;
2132 default:
baba133a 2133 BUG();
17638cd6
JB		 2134 }
2135
2136 if (obj->tiling_mode != I915_TILING_NONE)
2137 dspcntr |= DISPPLANE_TILED;
2138 else
2139 dspcntr &= ~DISPPLANE_TILED;
2140
2141 /* must disable */
2142 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2143
2144 I915_WRITE(reg, dspcntr);
2145
e506a0c6 2146 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2147 intel_crtc->dspaddr_offset =
bc752862
CW		 2148 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2149 fb->bits_per_pixel / 8,
2150 fb->pitches[0]);
c2c75131 2151 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2152
e506a0c6
DV		 2153 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2154 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2155 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2156 I915_MODIFY_DISPBASE(DSPSURF(plane),
2157 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2158 if (IS_HASWELL(dev)) {
2159 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2160 } else {
2161 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2162 I915_WRITE(DSPLINOFF(plane), linear_offset);
2163 }
17638cd6
JB		 2164 POSTING_READ(reg);
2165
2166 return 0;
2167}
2168
2169/* Assume fb object is pinned & idle & fenced and just update base pointers */
2170static int
2171intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2172 int x, int y, enum mode_set_atomic state)
2173{
2174 struct drm_device *dev = crtc->dev;
2175 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2176
6b8e6ed0
CW		 2177 if (dev_priv->display.disable_fbc)
2178 dev_priv->display.disable_fbc(dev);
3dec0095 2179 intel_increase_pllclock(crtc);
81255565 2180
6b8e6ed0 2181 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2182}
2183
96a02917
VS		 2184void intel_display_handle_reset(struct drm_device *dev)
2185{
2186 struct drm_i915_private *dev_priv = dev->dev_private;
2187 struct drm_crtc *crtc;
2188
2189 /*
2190 * Flips in the rings have been nuked by the reset,
2191 * so complete all pending flips so that user space
2192 * will get its events and not get stuck.
2193 *
2194 * Also update the base address of all primary
2195 * planes to the the last fb to make sure we're
2196 * showing the correct fb after a reset.
2197 *
2198 * Need to make two loops over the crtcs so that we
2199 * don't try to grab a crtc mutex before the
2200 * pending_flip_queue really got woken up.
2201 */
2202
2203 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2205 enum plane plane = intel_crtc->plane;
2206
2207 intel_prepare_page_flip(dev, plane);
2208 intel_finish_page_flip_plane(dev, plane);
2209 }
2210
2211 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2213
2214 mutex_lock(&crtc->mutex);
2215 if (intel_crtc->active)
2216 dev_priv->display.update_plane(crtc, crtc->fb,
2217 crtc->x, crtc->y);
2218 mutex_unlock(&crtc->mutex);
2219 }
2220}
2221
14667a4b
CW		 2222static int
2223intel_finish_fb(struct drm_framebuffer *old_fb)
2224{
2225 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2226 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2227 bool was_interruptible = dev_priv->mm.interruptible;
2228 int ret;
2229
14667a4b
CW		 2230 /* Big Hammer, we also need to ensure that any pending
2231 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2232 * current scanout is retired before unpinning the old
2233 * framebuffer.
2234 *
2235 * This should only fail upon a hung GPU, in which case we
2236 * can safely continue.
2237 */
2238 dev_priv->mm.interruptible = false;
2239 ret = i915_gem_object_finish_gpu(obj);
2240 dev_priv->mm.interruptible = was_interruptible;
2241
2242 return ret;
2243}
2244
198598d0
VS		 2245static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2246{
2247 struct drm_device *dev = crtc->dev;
2248 struct drm_i915_master_private *master_priv;
2249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2250
2251 if (!dev->primary->master)
2252 return;
2253
2254 master_priv = dev->primary->master->driver_priv;
2255 if (!master_priv->sarea_priv)
2256 return;
2257
2258 switch (intel_crtc->pipe) {
2259 case 0:
2260 master_priv->sarea_priv->pipeA_x = x;
2261 master_priv->sarea_priv->pipeA_y = y;
2262 break;
2263 case 1:
2264 master_priv->sarea_priv->pipeB_x = x;
2265 master_priv->sarea_priv->pipeB_y = y;
2266 break;
2267 default:
2268 break;
2269 }
2270}
2271
5c3b82e2 2272static int
3c4fdcfb 2273intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2274 struct drm_framebuffer *fb)
79e53945
JB		 2275{
2276 struct drm_device *dev = crtc->dev;
6b8e6ed0 2277 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2279 struct drm_framebuffer *old_fb;
5c3b82e2 2280 int ret;
79e53945
JB		 2281
2282 /* no fb bound */
94352cf9 2283 if (!fb) {
a5071c2f 2284 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2285 return 0;
2286 }
2287
7eb552ae 2288 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2289 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2290 plane_name(intel_crtc->plane),
2291 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2292 return -EINVAL;
79e53945
JB		 2293 }
2294
5c3b82e2 2295 mutex_lock(&dev->struct_mutex);
265db958 2296 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2297 to_intel_framebuffer(fb)->obj,
919926ae 2298 NULL);
5c3b82e2
CW		 2299 if (ret != 0) {
2300 mutex_unlock(&dev->struct_mutex);
a5071c2f 2301 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2302 return ret;
2303 }
79e53945 2304
94352cf9 2305 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2306 if (ret) {
94352cf9 2307 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2308 mutex_unlock(&dev->struct_mutex);
a5071c2f 2309 DRM_ERROR("failed to update base address\n");
4e6cfefc 2310 return ret;
79e53945 2311 }
3c4fdcfb 2312
94352cf9
DV		 2313 old_fb = crtc->fb;
2314 crtc->fb = fb;
6c4c86f5
DV		 2315 crtc->x = x;
2316 crtc->y = y;
94352cf9 2317
b7f1de28
CW		 2318 if (old_fb) {
2319 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2320 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2321 }
652c393a 2322
6b8e6ed0 2323 intel_update_fbc(dev);
5c3b82e2 2324 mutex_unlock(&dev->struct_mutex);
79e53945 2325
198598d0 2326 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2327
2328 return 0;
79e53945
JB		 2329}
2330
5e84e1a4
ZW		 2331static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332{
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2337 u32 reg, temp;
2338
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
61e499bf 2342 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2345 } else {
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2348 }
5e84e1a4
ZW		 2349 I915_WRITE(reg, temp);
2350
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356 } else {
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2359 }
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362 /* wait one idle pattern time */
2363 POSTING_READ(reg);
2364 udelay(1000);
357555c0
JB		 2365
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2370}
2371
1e833f40
DV		 2372static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2373{
2374 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2375}
2376
01a415fd
DV		 2377static void ivb_modeset_global_resources(struct drm_device *dev)
2378{
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct intel_crtc *pipe_B_crtc =
2381 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382 struct intel_crtc *pipe_C_crtc =
2383 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2384 uint32_t temp;
2385
1e833f40
DV		 2386 /*
2387 * When everything is off disable fdi C so that we could enable fdi B
2388 * with all lanes. Note that we don't care about enabled pipes without
2389 * an enabled pch encoder.
2390 */
2391 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2393 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396 temp = I915_READ(SOUTH_CHICKEN1);
2397 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399 I915_WRITE(SOUTH_CHICKEN1, temp);
2400 }
2401}
2402
8db9d77b
ZW		 2403/* The FDI link training functions for ILK/Ibexpeak. */
2404static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405{
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 int pipe = intel_crtc->pipe;
0fc932b8 2410 int plane = intel_crtc->plane;
5eddb70b 2411 u32 reg, temp, tries;
8db9d77b 2412
0fc932b8
JB		 2413 /* FDI needs bits from pipe & plane first */
2414 assert_pipe_enabled(dev_priv, pipe);
2415 assert_plane_enabled(dev_priv, plane);
2416
e1a44743
AJ		 2417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418 for train result */
5eddb70b
CW		 2419 reg = FDI_RX_IMR(pipe);
2420 temp = I915_READ(reg);
e1a44743
AJ		 2421 temp &= ~FDI_RX_SYMBOL_LOCK;
2422 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2423 I915_WRITE(reg, temp);
2424 I915_READ(reg);
e1a44743
AJ		 2425 udelay(150);
2426
8db9d77b 2427 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2428 reg = FDI_TX_CTL(pipe);
2429 temp = I915_READ(reg);
627eb5a3
DV		 2430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2435
5eddb70b
CW		 2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
8db9d77b
ZW		 2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442 POSTING_READ(reg);
8db9d77b
ZW		 2443 udelay(150);
2444
5b2adf89 2445 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2449
5eddb70b 2450 reg = FDI_RX_IIR(pipe);
e1a44743 2451 for (tries = 0; tries < 5; tries++) {
5eddb70b 2452 temp = I915_READ(reg);
8db9d77b
ZW		 2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if ((temp & FDI_RX_BIT_LOCK)) {
2456 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2458 break;
2459 }
8db9d77b 2460 }
e1a44743 2461 if (tries == 5)
5eddb70b 2462 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2463
2464 /* Train 2 */
5eddb70b
CW		 2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2469 I915_WRITE(reg, temp);
8db9d77b 2470
5eddb70b
CW		 2471 reg = FDI_RX_CTL(pipe);
2472 temp = I915_READ(reg);
8db9d77b
ZW		 2473 temp &= ~FDI_LINK_TRAIN_NONE;
2474 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2475 I915_WRITE(reg, temp);
8db9d77b 2476
5eddb70b
CW		 2477 POSTING_READ(reg);
2478 udelay(150);
8db9d77b 2479
5eddb70b 2480 reg = FDI_RX_IIR(pipe);
e1a44743 2481 for (tries = 0; tries < 5; tries++) {
5eddb70b 2482 temp = I915_READ(reg);
8db9d77b
ZW		 2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2487 DRM_DEBUG_KMS("FDI train 2 done.\n");
2488 break;
2489 }
8db9d77b 2490 }
e1a44743 2491 if (tries == 5)
5eddb70b 2492 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2493
2494 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2495
8db9d77b
ZW		 2496}
2497
0206e353 2498static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503};
2504
2505/* The FDI link training functions for SNB/Cougarpoint. */
2506static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507{
2508 struct drm_device *dev = crtc->dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511 int pipe = intel_crtc->pipe;
fa37d39e 2512 u32 reg, temp, i, retry;
8db9d77b 2513
e1a44743
AJ		 2514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515 for train result */
5eddb70b
CW		 2516 reg = FDI_RX_IMR(pipe);
2517 temp = I915_READ(reg);
e1a44743
AJ		 2518 temp &= ~FDI_RX_SYMBOL_LOCK;
2519 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
e1a44743
AJ		 2523 udelay(150);
2524
8db9d77b 2525 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2526 reg = FDI_TX_CTL(pipe);
2527 temp = I915_READ(reg);
627eb5a3
DV		 2528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_1;
2532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533 /* SNB-B */
2534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2536
d74cf324
DV		 2537 I915_WRITE(FDI_RX_MISC(pipe),
2538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
5eddb70b
CW		 2540 reg = FDI_RX_CTL(pipe);
2541 temp = I915_READ(reg);
8db9d77b
ZW		 2542 if (HAS_PCH_CPT(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545 } else {
2546 temp &= ~FDI_LINK_TRAIN_NONE;
2547 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548 }
5eddb70b
CW		 2549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551 POSTING_READ(reg);
8db9d77b
ZW		 2552 udelay(150);
2553
0206e353 2554 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
8db9d77b
ZW		 2557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2559 I915_WRITE(reg, temp);
2560
2561 POSTING_READ(reg);
8db9d77b
ZW		 2562 udelay(500);
2563
fa37d39e
SP		 2564 for (retry = 0; retry < 5; retry++) {
2565 reg = FDI_RX_IIR(pipe);
2566 temp = I915_READ(reg);
2567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568 if (temp & FDI_RX_BIT_LOCK) {
2569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571 break;
2572 }
2573 udelay(50);
8db9d77b 2574 }
fa37d39e
SP		 2575 if (retry < 5)
2576 break;
8db9d77b
ZW		 2577 }
2578 if (i == 4)
5eddb70b 2579 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2580
2581 /* Train 2 */
5eddb70b
CW		 2582 reg = FDI_TX_CTL(pipe);
2583 temp = I915_READ(reg);
8db9d77b
ZW		 2584 temp &= ~FDI_LINK_TRAIN_NONE;
2585 temp |= FDI_LINK_TRAIN_PATTERN_2;
2586 if (IS_GEN6(dev)) {
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 /* SNB-B */
2589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590 }
5eddb70b 2591 I915_WRITE(reg, temp);
8db9d77b 2592
5eddb70b
CW		 2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
8db9d77b
ZW		 2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601 }
5eddb70b
CW		 2602 I915_WRITE(reg, temp);
2603
2604 POSTING_READ(reg);
8db9d77b
ZW		 2605 udelay(150);
2606
0206e353 2607 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
8db9d77b
ZW		 2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
8db9d77b
ZW		 2615 udelay(500);
2616
fa37d39e
SP		 2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_SYMBOL_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624 break;
2625 }
2626 udelay(50);
8db9d77b 2627 }
fa37d39e
SP		 2628 if (retry < 5)
2629 break;
8db9d77b
ZW		 2630 }
2631 if (i == 4)
5eddb70b 2632 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2633
2634 DRM_DEBUG_KMS("FDI train done.\n");
2635}
2636
357555c0
JB		 2637/* Manual link training for Ivy Bridge A0 parts */
2638static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639{
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 int pipe = intel_crtc->pipe;
2644 u32 reg, temp, i;
2645
2646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647 for train result */
2648 reg = FDI_RX_IMR(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_RX_SYMBOL_LOCK;
2651 temp &= ~FDI_RX_BIT_LOCK;
2652 I915_WRITE(reg, temp);
2653
2654 POSTING_READ(reg);
2655 udelay(150);
2656
01a415fd
DV		 2657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658 I915_READ(FDI_RX_IIR(pipe)));
2659
357555c0
JB		 2660 /* enable CPU FDI TX and PCH FDI RX */
2661 reg = FDI_TX_CTL(pipe);
2662 temp = I915_READ(reg);
627eb5a3
DV		 2663 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2664 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2667 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2668 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2669 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2670 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2671
d74cf324
DV		 2672 I915_WRITE(FDI_RX_MISC(pipe),
2673 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2674
357555c0
JB		 2675 reg = FDI_RX_CTL(pipe);
2676 temp = I915_READ(reg);
2677 temp &= ~FDI_LINK_TRAIN_AUTO;
2678 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2679 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2680 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2681 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2682
2683 POSTING_READ(reg);
2684 udelay(150);
2685
0206e353 2686 for (i = 0; i < 4; i++) {
357555c0
JB		 2687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= snb_b_fdi_train_param[i];
2691 I915_WRITE(reg, temp);
2692
2693 POSTING_READ(reg);
2694 udelay(500);
2695
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700 if (temp & FDI_RX_BIT_LOCK ||
2701 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2702 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2703 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2704 break;
2705 }
2706 }
2707 if (i == 4)
2708 DRM_ERROR("FDI train 1 fail!\n");
2709
2710 /* Train 2 */
2711 reg = FDI_TX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2714 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2715 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2716 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2717 I915_WRITE(reg, temp);
2718
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2722 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2723 I915_WRITE(reg, temp);
2724
2725 POSTING_READ(reg);
2726 udelay(150);
2727
0206e353 2728 for (i = 0; i < 4; i++) {
357555c0
JB		 2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732 temp |= snb_b_fdi_train_param[i];
2733 I915_WRITE(reg, temp);
2734
2735 POSTING_READ(reg);
2736 udelay(500);
2737
2738 reg = FDI_RX_IIR(pipe);
2739 temp = I915_READ(reg);
2740 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2741
2742 if (temp & FDI_RX_SYMBOL_LOCK) {
2743 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2744 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2745 break;
2746 }
2747 }
2748 if (i == 4)
2749 DRM_ERROR("FDI train 2 fail!\n");
2750
2751 DRM_DEBUG_KMS("FDI train done.\n");
2752}
2753
88cefb6c 2754static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2755{
88cefb6c 2756 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2757 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2758 int pipe = intel_crtc->pipe;
5eddb70b 2759 u32 reg, temp;
79e53945 2760
c64e311e 2761
c98e9dcf 2762 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
627eb5a3
DV		 2765 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2766 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2767 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2768 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2769
2770 POSTING_READ(reg);
c98e9dcf
JB		 2771 udelay(200);
2772
2773 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2774 temp = I915_READ(reg);
2775 I915_WRITE(reg, temp | FDI_PCDCLK);
2776
2777 POSTING_READ(reg);
c98e9dcf
JB		 2778 udelay(200);
2779
20749730
PZ		 2780 /* Enable CPU FDI TX PLL, always on for Ironlake */
2781 reg = FDI_TX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2784 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2785
20749730
PZ		 2786 POSTING_READ(reg);
2787 udelay(100);
6be4a607 2788 }
0e23b99d
JB		 2789}
2790
88cefb6c
DV		 2791static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2792{
2793 struct drm_device *dev = intel_crtc->base.dev;
2794 struct drm_i915_private *dev_priv = dev->dev_private;
2795 int pipe = intel_crtc->pipe;
2796 u32 reg, temp;
2797
2798 /* Switch from PCDclk to Rawclk */
2799 reg = FDI_RX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2802
2803 /* Disable CPU FDI TX PLL */
2804 reg = FDI_TX_CTL(pipe);
2805 temp = I915_READ(reg);
2806 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2807
2808 POSTING_READ(reg);
2809 udelay(100);
2810
2811 reg = FDI_RX_CTL(pipe);
2812 temp = I915_READ(reg);
2813 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2814
2815 /* Wait for the clocks to turn off. */
2816 POSTING_READ(reg);
2817 udelay(100);
2818}
2819
0fc932b8
JB		 2820static void ironlake_fdi_disable(struct drm_crtc *crtc)
2821{
2822 struct drm_device *dev = crtc->dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2825 int pipe = intel_crtc->pipe;
2826 u32 reg, temp;
2827
2828 /* disable CPU FDI tx and PCH FDI rx */
2829 reg = FDI_TX_CTL(pipe);
2830 temp = I915_READ(reg);
2831 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2832 POSTING_READ(reg);
2833
2834 reg = FDI_RX_CTL(pipe);
2835 temp = I915_READ(reg);
2836 temp &= ~(0x7 << 16);
dfd07d72 2837 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2838 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2839
2840 POSTING_READ(reg);
2841 udelay(100);
2842
2843 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2844 if (HAS_PCH_IBX(dev)) {
2845 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2846 }
0fc932b8
JB		 2847
2848 /* still set train pattern 1 */
2849 reg = FDI_TX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 temp &= ~FDI_LINK_TRAIN_NONE;
2852 temp |= FDI_LINK_TRAIN_PATTERN_1;
2853 I915_WRITE(reg, temp);
2854
2855 reg = FDI_RX_CTL(pipe);
2856 temp = I915_READ(reg);
2857 if (HAS_PCH_CPT(dev)) {
2858 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2859 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2860 } else {
2861 temp &= ~FDI_LINK_TRAIN_NONE;
2862 temp |= FDI_LINK_TRAIN_PATTERN_1;
2863 }
2864 /* BPC in FDI rx is consistent with that in PIPECONF */
2865 temp &= ~(0x07 << 16);
dfd07d72 2866 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2867 I915_WRITE(reg, temp);
2868
2869 POSTING_READ(reg);
2870 udelay(100);
2871}
2872
5bb61643
CW		 2873static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2874{
2875 struct drm_device *dev = crtc->dev;
2876 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2878 unsigned long flags;
2879 bool pending;
2880
10d83730
VS		 2881 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2882 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2883 return false;
2884
2885 spin_lock_irqsave(&dev->event_lock, flags);
2886 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2887 spin_unlock_irqrestore(&dev->event_lock, flags);
2888
2889 return pending;
2890}
2891
e6c3a2a6
CW		 2892static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2893{
0f91128d 2894 struct drm_device *dev = crtc->dev;
5bb61643 2895 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2896
2897 if (crtc->fb == NULL)
2898 return;
2899
2c10d571
DV		 2900 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2901
5bb61643
CW		 2902 wait_event(dev_priv->pending_flip_queue,
2903 !intel_crtc_has_pending_flip(crtc));
2904
0f91128d
CW		 2905 mutex_lock(&dev->struct_mutex);
2906 intel_finish_fb(crtc->fb);
2907 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2908}
2909
e615efe4
ED		 2910/* Program iCLKIP clock to the desired frequency */
2911static void lpt_program_iclkip(struct drm_crtc *crtc)
2912{
2913 struct drm_device *dev = crtc->dev;
2914 struct drm_i915_private *dev_priv = dev->dev_private;
2915 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2916 u32 temp;
2917
09153000
DV		 2918 mutex_lock(&dev_priv->dpio_lock);
2919
e615efe4
ED		 2920 /* It is necessary to ungate the pixclk gate prior to programming
2921 * the divisors, and gate it back when it is done.
2922 */
2923 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2924
2925 /* Disable SSCCTL */
2926 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2927 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2928 SBI_SSCCTL_DISABLE,
2929 SBI_ICLK);
e615efe4
ED		 2930
2931 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2932 if (crtc->mode.clock == 20000) {
2933 auxdiv = 1;
2934 divsel = 0x41;
2935 phaseinc = 0x20;
2936 } else {
2937 /* The iCLK virtual clock root frequency is in MHz,
2938 * but the crtc->mode.clock in in KHz. To get the divisors,
2939 * it is necessary to divide one by another, so we
2940 * convert the virtual clock precision to KHz here for higher
2941 * precision.
2942 */
2943 u32 iclk_virtual_root_freq = 172800 * 1000;
2944 u32 iclk_pi_range = 64;
2945 u32 desired_divisor, msb_divisor_value, pi_value;
2946
2947 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2948 msb_divisor_value = desired_divisor / iclk_pi_range;
2949 pi_value = desired_divisor % iclk_pi_range;
2950
2951 auxdiv = 0;
2952 divsel = msb_divisor_value - 2;
2953 phaseinc = pi_value;
2954 }
2955
2956 /* This should not happen with any sane values */
2957 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2958 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2959 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2960 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2961
2962 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2963 crtc->mode.clock,
2964 auxdiv,
2965 divsel,
2966 phasedir,
2967 phaseinc);
2968
2969 /* Program SSCDIVINTPHASE6 */
988d6ee8 2970 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2971 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2972 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2973 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2974 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2975 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2976 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2977 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2978
2979 /* Program SSCAUXDIV */
988d6ee8 2980 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2981 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2982 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2983 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2984
2985 /* Enable modulator and associated divider */
988d6ee8 2986 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2987 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2988 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2989
2990 /* Wait for initialization time */
2991 udelay(24);
2992
2993 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2994
2995 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2996}
2997
f67a559d
JB		 2998/*
2999 * Enable PCH resources required for PCH ports:
3000 * - PCH PLLs
3001 * - FDI training & RX/TX
3002 * - update transcoder timings
3003 * - DP transcoding bits
3004 * - transcoder
3005 */
3006static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3007{
3008 struct drm_device *dev = crtc->dev;
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3011 int pipe = intel_crtc->pipe;
ee7b9f93 3012 u32 reg, temp;
2c07245f 3013
e7e164db
CW		 3014 assert_transcoder_disabled(dev_priv, pipe);
3015
cd986abb
DV		 3016 /* Write the TU size bits before fdi link training, so that error
3017 * detection works. */
3018 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3019 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3020
c98e9dcf 3021 /* For PCH output, training FDI link */
674cf967 3022 dev_priv->display.fdi_link_train(crtc);
2c07245f 3023
572deb37
DV		 3024 /* XXX: pch pll's can be enabled any time before we enable the PCH
3025 * transcoder, and we actually should do this to not upset any PCH
3026 * transcoder that already use the clock when we share it.
3027 *
3028 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3029 * unconditionally resets the pll - we need that to have the right LVDS
3030 * enable sequence. */
b6b4e185 3031 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3032
303b81e0 3033 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3034 u32 sel;
4b645f14 3035
c98e9dcf 3036 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3037 switch (pipe) {
3038 default:
3039 case 0:
3040 temp |= TRANSA_DPLL_ENABLE;
3041 sel = TRANSA_DPLLB_SEL;
3042 break;
3043 case 1:
3044 temp |= TRANSB_DPLL_ENABLE;
3045 sel = TRANSB_DPLLB_SEL;
3046 break;
3047 case 2:
3048 temp |= TRANSC_DPLL_ENABLE;
3049 sel = TRANSC_DPLLB_SEL;
3050 break;
d64311ab 3051 }
ee7b9f93
JB		 3052 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3053 temp |= sel;
3054 else
3055 temp &= ~sel;
c98e9dcf 3056 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3057 }
5eddb70b 3058
d9b6cb56
JB		 3059 /* set transcoder timing, panel must allow it */
3060 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3061 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3062 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3063 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3064
5eddb70b
CW		 3065 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3066 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3067 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3068 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3069
303b81e0 3070 intel_fdi_normal_train(crtc);
5e84e1a4 3071
c98e9dcf
JB		 3072 /* For PCH DP, enable TRANS_DP_CTL */
3073 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3074 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3075 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3076 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3077 reg = TRANS_DP_CTL(pipe);
3078 temp = I915_READ(reg);
3079 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3080 TRANS_DP_SYNC_MASK |
3081 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3082 temp |= (TRANS_DP_OUTPUT_ENABLE |
3083 TRANS_DP_ENH_FRAMING);
9325c9f0 3084 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3085
3086 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3087 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3088 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3089 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3090
3091 switch (intel_trans_dp_port_sel(crtc)) {
3092 case PCH_DP_B:
5eddb70b 3093 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3094 break;
3095 case PCH_DP_C:
5eddb70b 3096 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3097 break;
3098 case PCH_DP_D:
5eddb70b 3099 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3100 break;
3101 default:
e95d41e1 3102 BUG();
32f9d658 3103 }
2c07245f 3104
5eddb70b 3105 I915_WRITE(reg, temp);
6be4a607 3106 }
b52eb4dc 3107
b8a4f404 3108 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3109}
3110
1507e5bd
PZ		 3111static void lpt_pch_enable(struct drm_crtc *crtc)
3112{
3113 struct drm_device *dev = crtc->dev;
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3116 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3117
daed2dbb 3118 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3119
8c52b5e8 3120 lpt_program_iclkip(crtc);
1507e5bd 3121
0540e488 3122 /* Set transcoder timing. */
daed2dbb
PZ		 3123 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3124 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3125 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3126
daed2dbb
PZ		 3127 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3128 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3129 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3130 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3131
937bb610 3132 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3133}
3134
ee7b9f93
JB		 3135static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3136{
3137 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3138
3139 if (pll == NULL)
3140 return;
3141
3142 if (pll->refcount == 0) {
3143 WARN(1, "bad PCH PLL refcount\n");
3144 return;
3145 }
3146
3147 --pll->refcount;
3148 intel_crtc->pch_pll = NULL;
3149}
3150
3151static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3152{
3153 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3154 struct intel_pch_pll *pll;
3155 int i;
3156
3157 pll = intel_crtc->pch_pll;
3158 if (pll) {
3159 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3160 intel_crtc->base.base.id, pll->pll_reg);
3161 goto prepare;
3162 }
3163
98b6bd99
DV		 3164 if (HAS_PCH_IBX(dev_priv->dev)) {
3165 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3166 i = intel_crtc->pipe;
3167 pll = &dev_priv->pch_plls[i];
3168
3169 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3170 intel_crtc->base.base.id, pll->pll_reg);
3171
3172 goto found;
3173 }
3174
ee7b9f93
JB		 3175 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3176 pll = &dev_priv->pch_plls[i];
3177
3178 /* Only want to check enabled timings first */
3179 if (pll->refcount == 0)
3180 continue;
3181
3182 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3183 fp == I915_READ(pll->fp0_reg)) {
3184 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3185 intel_crtc->base.base.id,
3186 pll->pll_reg, pll->refcount, pll->active);
3187
3188 goto found;
3189 }
3190 }
3191
3192 /* Ok no matching timings, maybe there's a free one? */
3193 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3194 pll = &dev_priv->pch_plls[i];
3195 if (pll->refcount == 0) {
3196 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3197 intel_crtc->base.base.id, pll->pll_reg);
3198 goto found;
3199 }
3200 }
3201
3202 return NULL;
3203
3204found:
3205 intel_crtc->pch_pll = pll;
3206 pll->refcount++;
84f44ce7 3207 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3208prepare: /* separate function? */
3209 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3210
e04c7350
CW		 3211 /* Wait for the clocks to stabilize before rewriting the regs */
3212 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3213 POSTING_READ(pll->pll_reg);
3214 udelay(150);
e04c7350
CW		 3215
3216 I915_WRITE(pll->fp0_reg, fp);
3217 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3218 pll->on = false;
3219 return pll;
3220}
3221
d4270e57
JB		 3222void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3223{
3224 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3225 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3226 u32 temp;
3227
3228 temp = I915_READ(dslreg);
3229 udelay(500);
3230 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3231 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3232 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3233 }
3234}
3235
b074cec8
JB		 3236static void ironlake_pfit_enable(struct intel_crtc *crtc)
3237{
3238 struct drm_device *dev = crtc->base.dev;
3239 struct drm_i915_private *dev_priv = dev->dev_private;
3240 int pipe = crtc->pipe;
3241
3242 if (crtc->config.pch_pfit.size &&
3243 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
3244 /* Force use of hard-coded filter coefficients
3245 * as some pre-programmed values are broken,
3246 * e.g. x201.
3247 */
3248 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3249 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3250 PF_PIPE_SEL_IVB(pipe));
3251 else
3252 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3253 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3254 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3255 }
3256}
3257
f67a559d
JB		 3258static void ironlake_crtc_enable(struct drm_crtc *crtc)
3259{
3260 struct drm_device *dev = crtc->dev;
3261 struct drm_i915_private *dev_priv = dev->dev_private;
3262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3263 struct intel_encoder *encoder;
f67a559d
JB		 3264 int pipe = intel_crtc->pipe;
3265 int plane = intel_crtc->plane;
3266 u32 temp;
f67a559d 3267
08a48469
DV		 3268 WARN_ON(!crtc->enabled);
3269
f67a559d
JB		 3270 if (intel_crtc->active)
3271 return;
3272
3273 intel_crtc->active = true;
8664281b
PZ		 3274
3275 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3276 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3277
f67a559d
JB		 3278 intel_update_watermarks(dev);
3279
3280 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3281 temp = I915_READ(PCH_LVDS);
3282 if ((temp & LVDS_PORT_EN) == 0)
3283 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3284 }
3285
f67a559d 3286
5bfe2ac0 3287 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3288 /* Note: FDI PLL enabling _must_ be done before we enable the
3289 * cpu pipes, hence this is separate from all the other fdi/pch
3290 * enabling. */
88cefb6c 3291 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3292 } else {
3293 assert_fdi_tx_disabled(dev_priv, pipe);
3294 assert_fdi_rx_disabled(dev_priv, pipe);
3295 }
f67a559d 3296
bf49ec8c
DV		 3297 for_each_encoder_on_crtc(dev, crtc, encoder)
3298 if (encoder->pre_enable)
3299 encoder->pre_enable(encoder);
f67a559d
JB		 3300
3301 /* Enable panel fitting for LVDS */
b074cec8 3302 ironlake_pfit_enable(intel_crtc);
f67a559d 3303
9c54c0dd
JB		 3304 /*
3305 * On ILK+ LUT must be loaded before the pipe is running but with
3306 * clocks enabled
3307 */
3308 intel_crtc_load_lut(crtc);
3309
5bfe2ac0
DV		 3310 intel_enable_pipe(dev_priv, pipe,
3311 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3312 intel_enable_plane(dev_priv, plane, pipe);
3313
5bfe2ac0 3314 if (intel_crtc->config.has_pch_encoder)
f67a559d 3315 ironlake_pch_enable(crtc);
c98e9dcf 3316
d1ebd816 3317 mutex_lock(&dev->struct_mutex);
bed4a673 3318 intel_update_fbc(dev);
d1ebd816
BW		 3319 mutex_unlock(&dev->struct_mutex);
3320
6b383a7f 3321 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3322
fa5c73b1
DV		 3323 for_each_encoder_on_crtc(dev, crtc, encoder)
3324 encoder->enable(encoder);
61b77ddd
DV		 3325
3326 if (HAS_PCH_CPT(dev))
3327 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3328
3329 /*
3330 * There seems to be a race in PCH platform hw (at least on some
3331 * outputs) where an enabled pipe still completes any pageflip right
3332 * away (as if the pipe is off) instead of waiting for vblank. As soon
3333 * as the first vblank happend, everything works as expected. Hence just
3334 * wait for one vblank before returning to avoid strange things
3335 * happening.
3336 */
3337 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3338}
3339
4f771f10
PZ		 3340static void haswell_crtc_enable(struct drm_crtc *crtc)
3341{
3342 struct drm_device *dev = crtc->dev;
3343 struct drm_i915_private *dev_priv = dev->dev_private;
3344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3345 struct intel_encoder *encoder;
3346 int pipe = intel_crtc->pipe;
3347 int plane = intel_crtc->plane;
4f771f10
PZ		 3348
3349 WARN_ON(!crtc->enabled);
3350
3351 if (intel_crtc->active)
3352 return;
3353
3354 intel_crtc->active = true;
8664281b
PZ		 3355
3356 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3357 if (intel_crtc->config.has_pch_encoder)
3358 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3359
4f771f10
PZ		 3360 intel_update_watermarks(dev);
3361
5bfe2ac0 3362 if (intel_crtc->config.has_pch_encoder)
04945641 3363 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3364
3365 for_each_encoder_on_crtc(dev, crtc, encoder)
3366 if (encoder->pre_enable)
3367 encoder->pre_enable(encoder);
3368
1f544388 3369 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3370
1f544388 3371 /* Enable panel fitting for eDP */
b074cec8 3372 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3373
3374 /*
3375 * On ILK+ LUT must be loaded before the pipe is running but with
3376 * clocks enabled
3377 */
3378 intel_crtc_load_lut(crtc);
3379
1f544388 3380 intel_ddi_set_pipe_settings(crtc);
8228c251 3381 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3382
5bfe2ac0
DV		 3383 intel_enable_pipe(dev_priv, pipe,
3384 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3385 intel_enable_plane(dev_priv, plane, pipe);
3386
5bfe2ac0 3387 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3388 lpt_pch_enable(crtc);
4f771f10
PZ		 3389
3390 mutex_lock(&dev->struct_mutex);
3391 intel_update_fbc(dev);
3392 mutex_unlock(&dev->struct_mutex);
3393
3394 intel_crtc_update_cursor(crtc, true);
3395
3396 for_each_encoder_on_crtc(dev, crtc, encoder)
3397 encoder->enable(encoder);
3398
4f771f10
PZ		 3399 /*
3400 * There seems to be a race in PCH platform hw (at least on some
3401 * outputs) where an enabled pipe still completes any pageflip right
3402 * away (as if the pipe is off) instead of waiting for vblank. As soon
3403 * as the first vblank happend, everything works as expected. Hence just
3404 * wait for one vblank before returning to avoid strange things
3405 * happening.
3406 */
3407 intel_wait_for_vblank(dev, intel_crtc->pipe);
3408}
3409
6be4a607
JB		 3410static void ironlake_crtc_disable(struct drm_crtc *crtc)
3411{
3412 struct drm_device *dev = crtc->dev;
3413 struct drm_i915_private *dev_priv = dev->dev_private;
3414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3415 struct intel_encoder *encoder;
6be4a607
JB		 3416 int pipe = intel_crtc->pipe;
3417 int plane = intel_crtc->plane;
5eddb70b 3418 u32 reg, temp;
b52eb4dc 3419
ef9c3aee 3420
f7abfe8b
CW		 3421 if (!intel_crtc->active)
3422 return;
3423
ea9d758d
DV		 3424 for_each_encoder_on_crtc(dev, crtc, encoder)
3425 encoder->disable(encoder);
3426
e6c3a2a6 3427 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3428 drm_vblank_off(dev, pipe);
6b383a7f 3429 intel_crtc_update_cursor(crtc, false);
5eddb70b 3430
b24e7179 3431 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3432
973d04f9
CW		 3433 if (dev_priv->cfb_plane == plane)
3434 intel_disable_fbc(dev);
2c07245f 3435
8664281b 3436 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3437 intel_disable_pipe(dev_priv, pipe);
32f9d658 3438
6be4a607 3439 /* Disable PF */
9db4a9c7
JB		 3440 I915_WRITE(PF_CTL(pipe), 0);
3441 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3442
bf49ec8c
DV		 3443 for_each_encoder_on_crtc(dev, crtc, encoder)
3444 if (encoder->post_disable)
3445 encoder->post_disable(encoder);
2c07245f 3446
0fc932b8 3447 ironlake_fdi_disable(crtc);
249c0e64 3448
b8a4f404 3449 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3450 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3451
6be4a607
JB		 3452 if (HAS_PCH_CPT(dev)) {
3453 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3454 reg = TRANS_DP_CTL(pipe);
3455 temp = I915_READ(reg);
3456 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3457 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3458 I915_WRITE(reg, temp);
6be4a607
JB		 3459
3460 /* disable DPLL_SEL */
3461 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3462 switch (pipe) {
3463 case 0:
d64311ab 3464 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3465 break;
3466 case 1:
6be4a607 3467 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3468 break;
3469 case 2:
4b645f14 3470 /* C shares PLL A or B */
d64311ab 3471 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3472 break;
3473 default:
3474 BUG(); /* wtf */
3475 }
6be4a607 3476 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3477 }
e3421a18 3478
6be4a607 3479 /* disable PCH DPLL */
ee7b9f93 3480 intel_disable_pch_pll(intel_crtc);
8db9d77b 3481
88cefb6c 3482 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3483
f7abfe8b 3484 intel_crtc->active = false;
6b383a7f 3485 intel_update_watermarks(dev);
d1ebd816
BW		 3486
3487 mutex_lock(&dev->struct_mutex);
6b383a7f 3488 intel_update_fbc(dev);
d1ebd816 3489 mutex_unlock(&dev->struct_mutex);
6be4a607 3490}
1b3c7a47 3491
4f771f10 3492static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3493{
4f771f10
PZ		 3494 struct drm_device *dev = crtc->dev;
3495 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3497 struct intel_encoder *encoder;
3498 int pipe = intel_crtc->pipe;
3499 int plane = intel_crtc->plane;
3b117c8f 3500 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3501
4f771f10
PZ		 3502 if (!intel_crtc->active)
3503 return;
3504
3505 for_each_encoder_on_crtc(dev, crtc, encoder)
3506 encoder->disable(encoder);
3507
3508 intel_crtc_wait_for_pending_flips(crtc);
3509 drm_vblank_off(dev, pipe);
3510 intel_crtc_update_cursor(crtc, false);
3511
3512 intel_disable_plane(dev_priv, plane, pipe);
3513
3514 if (dev_priv->cfb_plane == plane)
3515 intel_disable_fbc(dev);
3516
8664281b
PZ		 3517 if (intel_crtc->config.has_pch_encoder)
3518 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3519 intel_disable_pipe(dev_priv, pipe);
3520
ad80a810 3521 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3522
f7708f78
PZ		 3523 /* XXX: Once we have proper panel fitter state tracking implemented with
3524 * hardware state read/check support we should switch to only disable
3525 * the panel fitter when we know it's used. */
3526 if (intel_using_power_well(dev)) {
3527 I915_WRITE(PF_CTL(pipe), 0);
3528 I915_WRITE(PF_WIN_SZ(pipe), 0);
3529 }
4f771f10 3530
1f544388 3531 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3532
3533 for_each_encoder_on_crtc(dev, crtc, encoder)
3534 if (encoder->post_disable)
3535 encoder->post_disable(encoder);
3536
88adfff1 3537 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3538 lpt_disable_pch_transcoder(dev_priv);
8664281b 3539 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3540 intel_ddi_fdi_disable(crtc);
83616634 3541 }
4f771f10
PZ		 3542
3543 intel_crtc->active = false;
3544 intel_update_watermarks(dev);
3545
3546 mutex_lock(&dev->struct_mutex);
3547 intel_update_fbc(dev);
3548 mutex_unlock(&dev->struct_mutex);
3549}
3550
ee7b9f93
JB		 3551static void ironlake_crtc_off(struct drm_crtc *crtc)
3552{
3553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3554 intel_put_pch_pll(intel_crtc);
3555}
3556
6441ab5f
PZ		 3557static void haswell_crtc_off(struct drm_crtc *crtc)
3558{
a5c961d1
PZ		 3559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3560
3561 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3562 * start using it. */
3b117c8f 3563 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3564
6441ab5f
PZ		 3565 intel_ddi_put_crtc_pll(crtc);
3566}
3567
02e792fb
DV		 3568static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3569{
02e792fb 3570 if (!enable && intel_crtc->overlay) {
23f09ce3 3571 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3572 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3573
23f09ce3 3574 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3575 dev_priv->mm.interruptible = false;
3576 (void) intel_overlay_switch_off(intel_crtc->overlay);
3577 dev_priv->mm.interruptible = true;
23f09ce3 3578 mutex_unlock(&dev->struct_mutex);
02e792fb 3579 }
02e792fb 3580
5dcdbcb0
CW		 3581 /* Let userspace switch the overlay on again. In most cases userspace
3582 * has to recompute where to put it anyway.
3583 */
02e792fb
DV		 3584}
3585
61bc95c1
EE		 3586/**
3587 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3588 * cursor plane briefly if not already running after enabling the display
3589 * plane.
3590 * This workaround avoids occasional blank screens when self refresh is
3591 * enabled.
3592 */
3593static void
3594g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3595{
3596 u32 cntl = I915_READ(CURCNTR(pipe));
3597
3598 if ((cntl & CURSOR_MODE) == 0) {
3599 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3600
3601 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3602 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3603 intel_wait_for_vblank(dev_priv->dev, pipe);
3604 I915_WRITE(CURCNTR(pipe), cntl);
3605 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3606 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3607 }
3608}
3609
2dd24552
JB		 3610static void i9xx_pfit_enable(struct intel_crtc *crtc)
3611{
3612 struct drm_device *dev = crtc->base.dev;
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614 struct intel_crtc_config *pipe_config = &crtc->config;
3615
3616 if (!(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
3617 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)))
3618 return;
3619
3620 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3621 assert_pipe_disabled(dev_priv, crtc->pipe);
3622
3623 /*
3624 * Enable automatic panel scaling so that non-native modes
3625 * fill the screen. The panel fitter should only be
3626 * adjusted whilst the pipe is disabled, according to
3627 * register description and PRM.
3628 */
3629 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
b074cec8
JB		 3630 pipe_config->gmch_pfit.control,
3631 pipe_config->gmch_pfit.pgm_ratios);
2dd24552 3632
b074cec8
JB		 3633 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3634 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
2dd24552
JB		 3635}
3636
89b667f8
JB		 3637static void valleyview_crtc_enable(struct drm_crtc *crtc)
3638{
3639 struct drm_device *dev = crtc->dev;
3640 struct drm_i915_private *dev_priv = dev->dev_private;
3641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3642 struct intel_encoder *encoder;
3643 int pipe = intel_crtc->pipe;
3644 int plane = intel_crtc->plane;
3645
3646 WARN_ON(!crtc->enabled);
3647
3648 if (intel_crtc->active)
3649 return;
3650
3651 intel_crtc->active = true;
3652 intel_update_watermarks(dev);
3653
3654 mutex_lock(&dev_priv->dpio_lock);
3655
3656 for_each_encoder_on_crtc(dev, crtc, encoder)
3657 if (encoder->pre_pll_enable)
3658 encoder->pre_pll_enable(encoder);
3659
3660 intel_enable_pll(dev_priv, pipe);
3661
3662 for_each_encoder_on_crtc(dev, crtc, encoder)
3663 if (encoder->pre_enable)
3664 encoder->pre_enable(encoder);
3665
3666 /* VLV wants encoder enabling _before_ the pipe is up. */
3667 for_each_encoder_on_crtc(dev, crtc, encoder)
3668 encoder->enable(encoder);
3669
2dd24552
JB		 3670 /* Enable panel fitting for eDP */
3671 i9xx_pfit_enable(intel_crtc);
3672
89b667f8
JB		 3673 intel_enable_pipe(dev_priv, pipe, false);
3674 intel_enable_plane(dev_priv, plane, pipe);
3675
3676 intel_crtc_load_lut(crtc);
3677 intel_update_fbc(dev);
3678
3679 /* Give the overlay scaler a chance to enable if it's on this pipe */
3680 intel_crtc_dpms_overlay(intel_crtc, true);
3681 intel_crtc_update_cursor(crtc, true);
3682
3683 mutex_unlock(&dev_priv->dpio_lock);
3684}
3685
0b8765c6 3686static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3687{
3688 struct drm_device *dev = crtc->dev;
79e53945
JB		 3689 struct drm_i915_private *dev_priv = dev->dev_private;
3690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3691 struct intel_encoder *encoder;
79e53945 3692 int pipe = intel_crtc->pipe;
80824003 3693 int plane = intel_crtc->plane;
79e53945 3694
08a48469
DV		 3695 WARN_ON(!crtc->enabled);
3696
f7abfe8b
CW		 3697 if (intel_crtc->active)
3698 return;
3699
3700 intel_crtc->active = true;
6b383a7f
CW		 3701 intel_update_watermarks(dev);
3702
63d7bbe9 3703 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3704
3705 for_each_encoder_on_crtc(dev, crtc, encoder)
3706 if (encoder->pre_enable)
3707 encoder->pre_enable(encoder);
3708
2dd24552
JB		 3709 /* Enable panel fitting for LVDS */
3710 i9xx_pfit_enable(intel_crtc);
3711
040484af 3712 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3713 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3714 if (IS_G4X(dev))
3715 g4x_fixup_plane(dev_priv, pipe);
79e53945 3716
0b8765c6 3717 intel_crtc_load_lut(crtc);
bed4a673 3718 intel_update_fbc(dev);
79e53945 3719
0b8765c6
JB		 3720 /* Give the overlay scaler a chance to enable if it's on this pipe */
3721 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3722 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3723
fa5c73b1
DV		 3724 for_each_encoder_on_crtc(dev, crtc, encoder)
3725 encoder->enable(encoder);
0b8765c6 3726}
79e53945 3727
87476d63
DV		 3728static void i9xx_pfit_disable(struct intel_crtc *crtc)
3729{
3730 struct drm_device *dev = crtc->base.dev;
3731 struct drm_i915_private *dev_priv = dev->dev_private;
3732 enum pipe pipe;
3733 uint32_t pctl = I915_READ(PFIT_CONTROL);
3734
3735 assert_pipe_disabled(dev_priv, crtc->pipe);
3736
3737 if (INTEL_INFO(dev)->gen >= 4)
3738 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3739 else
3740 pipe = PIPE_B;
3741
3742 if (pipe == crtc->pipe) {
3743 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3744 I915_WRITE(PFIT_CONTROL, 0);
3745 }
3746}
3747
0b8765c6
JB		 3748static void i9xx_crtc_disable(struct drm_crtc *crtc)
3749{
3750 struct drm_device *dev = crtc->dev;
3751 struct drm_i915_private *dev_priv = dev->dev_private;
3752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3753 struct intel_encoder *encoder;
0b8765c6
JB		 3754 int pipe = intel_crtc->pipe;
3755 int plane = intel_crtc->plane;
ef9c3aee 3756
f7abfe8b
CW		 3757 if (!intel_crtc->active)
3758 return;
3759
ea9d758d
DV		 3760 for_each_encoder_on_crtc(dev, crtc, encoder)
3761 encoder->disable(encoder);
3762
0b8765c6 3763 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3764 intel_crtc_wait_for_pending_flips(crtc);
3765 drm_vblank_off(dev, pipe);
0b8765c6 3766 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3767 intel_crtc_update_cursor(crtc, false);
0b8765c6 3768
973d04f9
CW		 3769 if (dev_priv->cfb_plane == plane)
3770 intel_disable_fbc(dev);
79e53945 3771
b24e7179 3772 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3773 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3774
87476d63 3775 i9xx_pfit_disable(intel_crtc);
24a1f16d 3776
89b667f8
JB		 3777 for_each_encoder_on_crtc(dev, crtc, encoder)
3778 if (encoder->post_disable)
3779 encoder->post_disable(encoder);
3780
63d7bbe9 3781 intel_disable_pll(dev_priv, pipe);
0b8765c6 3782
f7abfe8b 3783 intel_crtc->active = false;
6b383a7f
CW		 3784 intel_update_fbc(dev);
3785 intel_update_watermarks(dev);
0b8765c6
JB		 3786}
3787
ee7b9f93
JB		 3788static void i9xx_crtc_off(struct drm_crtc *crtc)
3789{
3790}
3791
976f8a20
DV		 3792static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3793 bool enabled)
2c07245f
ZW		 3794{
3795 struct drm_device *dev = crtc->dev;
3796 struct drm_i915_master_private *master_priv;
3797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3798 int pipe = intel_crtc->pipe;
79e53945
JB		 3799
3800 if (!dev->primary->master)
3801 return;
3802
3803 master_priv = dev->primary->master->driver_priv;
3804 if (!master_priv->sarea_priv)
3805 return;
3806
79e53945
JB		 3807 switch (pipe) {
3808 case 0:
3809 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3810 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3811 break;
3812 case 1:
3813 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3814 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3815 break;
3816 default:
9db4a9c7 3817 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3818 break;
3819 }
79e53945
JB		 3820}
3821
976f8a20
DV		 3822/**
3823 * Sets the power management mode of the pipe and plane.
3824 */
3825void intel_crtc_update_dpms(struct drm_crtc *crtc)
3826{
3827 struct drm_device *dev = crtc->dev;
3828 struct drm_i915_private *dev_priv = dev->dev_private;
3829 struct intel_encoder *intel_encoder;
3830 bool enable = false;
3831
3832 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3833 enable |= intel_encoder->connectors_active;
3834
3835 if (enable)
3836 dev_priv->display.crtc_enable(crtc);
3837 else
3838 dev_priv->display.crtc_disable(crtc);
3839
3840 intel_crtc_update_sarea(crtc, enable);
3841}
3842
cdd59983
CW		 3843static void intel_crtc_disable(struct drm_crtc *crtc)
3844{
cdd59983 3845 struct drm_device *dev = crtc->dev;
976f8a20 3846 struct drm_connector *connector;
ee7b9f93 3847 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3849
976f8a20
DV		 3850 /* crtc should still be enabled when we disable it. */
3851 WARN_ON(!crtc->enabled);
3852
7b9f35a6 3853 intel_crtc->eld_vld = false;
976f8a20
DV		 3854 dev_priv->display.crtc_disable(crtc);
3855 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3856 dev_priv->display.off(crtc);
3857
931872fc
CW		 3858 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3859 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3860
3861 if (crtc->fb) {
3862 mutex_lock(&dev->struct_mutex);
1690e1eb 3863 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3864 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3865 crtc->fb = NULL;
3866 }
3867
3868 /* Update computed state. */
3869 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3870 if (!connector->encoder || !connector->encoder->crtc)
3871 continue;
3872
3873 if (connector->encoder->crtc != crtc)
3874 continue;
3875
3876 connector->dpms = DRM_MODE_DPMS_OFF;
3877 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3878 }
3879}
3880
a261b246 3881void intel_modeset_disable(struct drm_device *dev)
79e53945 3882{
a261b246
DV		 3883 struct drm_crtc *crtc;
3884
3885 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3886 if (crtc->enabled)
3887 intel_crtc_disable(crtc);
3888 }
79e53945
JB		 3889}
3890
ea5b213a 3891void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3892{
4ef69c7a 3893 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3894
ea5b213a
CW		 3895 drm_encoder_cleanup(encoder);
3896 kfree(intel_encoder);
7e7d76c3
JB		 3897}
3898
5ab432ef
DV		 3899/* Simple dpms helper for encodres with just one connector, no cloning and only
3900 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3901 * state of the entire output pipe. */
3902void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3903{
5ab432ef
DV		 3904 if (mode == DRM_MODE_DPMS_ON) {
3905 encoder->connectors_active = true;
3906
b2cabb0e 3907 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3908 } else {
3909 encoder->connectors_active = false;
3910
b2cabb0e 3911 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3912 }
79e53945
JB		 3913}
3914
0a91ca29
DV		 3915/* Cross check the actual hw state with our own modeset state tracking (and it's
3916 * internal consistency). */
b980514c 3917static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3918{
0a91ca29
DV		 3919 if (connector->get_hw_state(connector)) {
3920 struct intel_encoder *encoder = connector->encoder;
3921 struct drm_crtc *crtc;
3922 bool encoder_enabled;
3923 enum pipe pipe;
3924
3925 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3926 connector->base.base.id,
3927 drm_get_connector_name(&connector->base));
3928
3929 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3930 "wrong connector dpms state\n");
3931 WARN(connector->base.encoder != &encoder->base,
3932 "active connector not linked to encoder\n");
3933 WARN(!encoder->connectors_active,
3934 "encoder->connectors_active not set\n");
3935
3936 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3937 WARN(!encoder_enabled, "encoder not enabled\n");
3938 if (WARN_ON(!encoder->base.crtc))
3939 return;
3940
3941 crtc = encoder->base.crtc;
3942
3943 WARN(!crtc->enabled, "crtc not enabled\n");
3944 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3945 WARN(pipe != to_intel_crtc(crtc)->pipe,
3946 "encoder active on the wrong pipe\n");
3947 }
79e53945
JB		 3948}
3949
5ab432ef
DV		 3950/* Even simpler default implementation, if there's really no special case to
3951 * consider. */
3952void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3953{
5ab432ef 3954 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3955
5ab432ef
DV		 3956 /* All the simple cases only support two dpms states. */
3957 if (mode != DRM_MODE_DPMS_ON)
3958 mode = DRM_MODE_DPMS_OFF;
d4270e57 3959
5ab432ef
DV		 3960 if (mode == connector->dpms)
3961 return;
3962
3963 connector->dpms = mode;
3964
3965 /* Only need to change hw state when actually enabled */
3966 if (encoder->base.crtc)
3967 intel_encoder_dpms(encoder, mode);
3968 else
8af6cf88 3969 WARN_ON(encoder->connectors_active != false);
0a91ca29 3970
b980514c 3971 intel_modeset_check_state(connector->dev);
79e53945
JB		 3972}
3973
f0947c37
DV		 3974/* Simple connector->get_hw_state implementation for encoders that support only
3975 * one connector and no cloning and hence the encoder state determines the state
3976 * of the connector. */
3977bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3978{
24929352 3979 enum pipe pipe = 0;
f0947c37 3980 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3981
f0947c37 3982 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3983}
3984
1857e1da
DV		 3985static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3986 struct intel_crtc_config *pipe_config)
3987{
3988 struct drm_i915_private *dev_priv = dev->dev_private;
3989 struct intel_crtc *pipe_B_crtc =
3990 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3991
3992 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3993 pipe_name(pipe), pipe_config->fdi_lanes);
3994 if (pipe_config->fdi_lanes > 4) {
3995 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3996 pipe_name(pipe), pipe_config->fdi_lanes);
3997 return false;
3998 }
3999
4000 if (IS_HASWELL(dev)) {
4001 if (pipe_config->fdi_lanes > 2) {
4002 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4003 pipe_config->fdi_lanes);
4004 return false;
4005 } else {
4006 return true;
4007 }
4008 }
4009
4010 if (INTEL_INFO(dev)->num_pipes == 2)
4011 return true;
4012
4013 /* Ivybridge 3 pipe is really complicated */
4014 switch (pipe) {
4015 case PIPE_A:
4016 return true;
4017 case PIPE_B:
4018 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4019 pipe_config->fdi_lanes > 2) {
4020 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4021 pipe_name(pipe), pipe_config->fdi_lanes);
4022 return false;
4023 }
4024 return true;
4025 case PIPE_C:
1e833f40 4026 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4027 pipe_B_crtc->config.fdi_lanes <= 2) {
4028 if (pipe_config->fdi_lanes > 2) {
4029 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4030 pipe_name(pipe), pipe_config->fdi_lanes);
4031 return false;
4032 }
4033 } else {
4034 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4035 return false;
4036 }
4037 return true;
4038 default:
4039 BUG();
4040 }
4041}
4042
e29c22c0
DV		 4043#define RETRY 1
4044static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4045 struct intel_crtc_config *pipe_config)
877d48d5 4046{
1857e1da 4047 struct drm_device *dev = intel_crtc->base.dev;
877d48d5
DV		 4048 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4049 int target_clock, lane, link_bw;
e29c22c0 4050 bool setup_ok, needs_recompute = false;
877d48d5 4051
e29c22c0 4052retry:
877d48d5
DV		 4053 /* FDI is a binary signal running at ~2.7GHz, encoding
4054 * each output octet as 10 bits. The actual frequency
4055 * is stored as a divider into a 100MHz clock, and the
4056 * mode pixel clock is stored in units of 1KHz.
4057 * Hence the bw of each lane in terms of the mode signal
4058 * is:
4059 */
4060 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4061
4062 if (pipe_config->pixel_target_clock)
4063 target_clock = pipe_config->pixel_target_clock;
4064 else
4065 target_clock = adjusted_mode->clock;
4066
4067 lane = ironlake_get_lanes_required(target_clock, link_bw,
4068 pipe_config->pipe_bpp);
4069
4070 pipe_config->fdi_lanes = lane;
4071
4072 if (pipe_config->pixel_multiplier > 1)
4073 link_bw *= pipe_config->pixel_multiplier;
4074 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4075 link_bw, &pipe_config->fdi_m_n);
1857e1da 4076
e29c22c0
DV		 4077 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4078 intel_crtc->pipe, pipe_config);
4079 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4080 pipe_config->pipe_bpp -= 2*3;
4081 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4082 pipe_config->pipe_bpp);
4083 needs_recompute = true;
4084 pipe_config->bw_constrained = true;
4085
4086 goto retry;
4087 }
4088
4089 if (needs_recompute)
4090 return RETRY;
4091
4092 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4093}
4094
e29c22c0
DV		 4095static int intel_crtc_compute_config(struct drm_crtc *crtc,
4096 struct intel_crtc_config *pipe_config)
79e53945 4097{
2c07245f 4098 struct drm_device *dev = crtc->dev;
b8cecdf5 4099 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4100
bad720ff 4101 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4102 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4103 if (pipe_config->requested_mode.clock * 3
4104 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4105 return -EINVAL;
2c07245f 4106 }
89749350 4107
f9bef081
DV		 4108 /* All interlaced capable intel hw wants timings in frames. Note though
4109 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4110 * timings, so we need to be careful not to clobber these.*/
7ae89233 4111 if (!pipe_config->timings_set)
f9bef081 4112 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4113
44f46b42
CW		 4114 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4115 * with a hsync front porch of 0.
4116 */
4117 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4118 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4119 return -EINVAL;
44f46b42 4120
bd080ee5 4121 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4122 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4123 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4124 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4125 * for lvds. */
4126 pipe_config->pipe_bpp = 8*3;
4127 }
4128
877d48d5 4129 if (pipe_config->has_pch_encoder)
1857e1da 4130 return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config);
877d48d5 4131
e29c22c0 4132 return 0;
79e53945
JB		 4133}
4134
25eb05fc
JB		 4135static int valleyview_get_display_clock_speed(struct drm_device *dev)
4136{
4137 return 400000; /* FIXME */
4138}
4139
e70236a8
JB		 4140static int i945_get_display_clock_speed(struct drm_device *dev)
4141{
4142 return 400000;
4143}
79e53945 4144
e70236a8 4145static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4146{
e70236a8
JB		 4147 return 333000;
4148}
79e53945 4149
e70236a8
JB		 4150static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4151{
4152 return 200000;
4153}
79e53945 4154
e70236a8
JB		 4155static int i915gm_get_display_clock_speed(struct drm_device *dev)
4156{
4157 u16 gcfgc = 0;
79e53945 4158
e70236a8
JB		 4159 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4160
4161 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4162 return 133000;
4163 else {
4164 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4165 case GC_DISPLAY_CLOCK_333_MHZ:
4166 return 333000;
4167 default:
4168 case GC_DISPLAY_CLOCK_190_200_MHZ:
4169 return 190000;
79e53945 4170 }
e70236a8
JB		 4171 }
4172}
4173
4174static int i865_get_display_clock_speed(struct drm_device *dev)
4175{
4176 return 266000;
4177}
4178
4179static int i855_get_display_clock_speed(struct drm_device *dev)
4180{
4181 u16 hpllcc = 0;
4182 /* Assume that the hardware is in the high speed state. This
4183 * should be the default.
4184 */
4185 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4186 case GC_CLOCK_133_200:
4187 case GC_CLOCK_100_200:
4188 return 200000;
4189 case GC_CLOCK_166_250:
4190 return 250000;
4191 case GC_CLOCK_100_133:
79e53945 4192 return 133000;
e70236a8 4193 }
79e53945 4194
e70236a8
JB		 4195 /* Shouldn't happen */
4196 return 0;
4197}
79e53945 4198
e70236a8
JB		 4199static int i830_get_display_clock_speed(struct drm_device *dev)
4200{
4201 return 133000;
79e53945
JB		 4202}
4203
2c07245f 4204static void
e69d0bc1 4205intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4206{
4207 while (*num > 0xffffff || *den > 0xffffff) {
4208 *num >>= 1;
4209 *den >>= 1;
4210 }
4211}
4212
e69d0bc1
DV		 4213void
4214intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4215 int pixel_clock, int link_clock,
4216 struct intel_link_m_n *m_n)
2c07245f 4217{
e69d0bc1 4218 m_n->tu = 64;
22ed1113
CW		 4219 m_n->gmch_m = bits_per_pixel * pixel_clock;
4220 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4221 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4222 m_n->link_m = pixel_clock;
4223 m_n->link_n = link_clock;
e69d0bc1 4224 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4225}
4226
a7615030
CW		 4227static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4228{
72bbe58c
KP		 4229 if (i915_panel_use_ssc >= 0)
4230 return i915_panel_use_ssc != 0;
4231 return dev_priv->lvds_use_ssc
435793df 4232 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4233}
4234
a0c4da24
JB		 4235static int vlv_get_refclk(struct drm_crtc *crtc)
4236{
4237 struct drm_device *dev = crtc->dev;
4238 struct drm_i915_private *dev_priv = dev->dev_private;
4239 int refclk = 27000; /* for DP & HDMI */
4240
4241 return 100000; /* only one validated so far */
4242
4243 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4244 refclk = 96000;
4245 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4246 if (intel_panel_use_ssc(dev_priv))
4247 refclk = 100000;
4248 else
4249 refclk = 96000;
4250 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4251 refclk = 100000;
4252 }
4253
4254 return refclk;
4255}
4256
c65d77d8
JB		 4257static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4258{
4259 struct drm_device *dev = crtc->dev;
4260 struct drm_i915_private *dev_priv = dev->dev_private;
4261 int refclk;
4262
a0c4da24
JB		 4263 if (IS_VALLEYVIEW(dev)) {
4264 refclk = vlv_get_refclk(crtc);
4265 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4266 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4267 refclk = dev_priv->lvds_ssc_freq * 1000;
4268 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4269 refclk / 1000);
4270 } else if (!IS_GEN2(dev)) {
4271 refclk = 96000;
4272 } else {
4273 refclk = 48000;
4274 }
4275
4276 return refclk;
4277}
4278
f47709a9 4279static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
c65d77d8 4280{
f47709a9
DV		 4281 unsigned dotclock = crtc->config.adjusted_mode.clock;
4282 struct dpll *clock = &crtc->config.dpll;
4283
c65d77d8
JB		 4284 /* SDVO TV has fixed PLL values depend on its clock range,
4285 this mirrors vbios setting. */
f47709a9 4286 if (dotclock >= 100000 && dotclock < 140500) {
c65d77d8
JB		 4287 clock->p1 = 2;
4288 clock->p2 = 10;
4289 clock->n = 3;
4290 clock->m1 = 16;
4291 clock->m2 = 8;
f47709a9 4292 } else if (dotclock >= 140500 && dotclock <= 200000) {
c65d77d8
JB		 4293 clock->p1 = 1;
4294 clock->p2 = 10;
4295 clock->n = 6;
4296 clock->m1 = 12;
4297 clock->m2 = 8;
4298 }
f47709a9
DV		 4299
4300 crtc->config.clock_set = true;
c65d77d8
JB		 4301}
4302
7429e9d4
DV		 4303static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4304{
4305 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4306}
4307
4308static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4309{
4310 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4311}
4312
f47709a9 4313static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4314 intel_clock_t *reduced_clock)
4315{
f47709a9 4316 struct drm_device *dev = crtc->base.dev;
a7516a05 4317 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4318 int pipe = crtc->pipe;
a7516a05
JB		 4319 u32 fp, fp2 = 0;
4320
4321 if (IS_PINEVIEW(dev)) {
7429e9d4 4322 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4323 if (reduced_clock)
7429e9d4 4324 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4325 } else {
7429e9d4 4326 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4327 if (reduced_clock)
7429e9d4 4328 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4329 }
4330
4331 I915_WRITE(FP0(pipe), fp);
4332
f47709a9
DV		 4333 crtc->lowfreq_avail = false;
4334 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4335 reduced_clock && i915_powersave) {
4336 I915_WRITE(FP1(pipe), fp2);
f47709a9 4337 crtc->lowfreq_avail = true;
a7516a05
JB		 4338 } else {
4339 I915_WRITE(FP1(pipe), fp);
4340 }
4341}
4342
89b667f8
JB		 4343static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4344{
4345 u32 reg_val;
4346
4347 /*
4348 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4349 * and set it to a reasonable value instead.
4350 */
4351 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4352 reg_val &= 0xffffff00;
4353 reg_val |= 0x00000030;
4354 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4355
4356 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4357 reg_val &= 0x8cffffff;
4358 reg_val = 0x8c000000;
4359 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4360
4361 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4362 reg_val &= 0xffffff00;
4363 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4364
4365 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4366 reg_val &= 0x00ffffff;
4367 reg_val |= 0xb0000000;
4368 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4369}
4370
03afc4a2
DV		 4371static void intel_dp_set_m_n(struct intel_crtc *crtc)
4372{
4373 if (crtc->config.has_pch_encoder)
4374 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4375 else
4376 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4377}
4378
f47709a9 4379static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4380{
f47709a9 4381 struct drm_device *dev = crtc->base.dev;
a0c4da24 4382 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8
JB		 4383 struct drm_display_mode *adjusted_mode =
4384 &crtc->config.adjusted_mode;
4385 struct intel_encoder *encoder;
f47709a9 4386 int pipe = crtc->pipe;
89b667f8 4387 u32 dpll, mdiv;
a0c4da24 4388 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4389 bool is_hdmi;
198a037f 4390 u32 coreclk, reg_val, dpll_md;
a0c4da24 4391
09153000
DV		 4392 mutex_lock(&dev_priv->dpio_lock);
4393
89b667f8 4394 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4395
f47709a9
DV		 4396 bestn = crtc->config.dpll.n;
4397 bestm1 = crtc->config.dpll.m1;
4398 bestm2 = crtc->config.dpll.m2;
4399 bestp1 = crtc->config.dpll.p1;
4400 bestp2 = crtc->config.dpll.p2;
a0c4da24 4401
89b667f8
JB		 4402 /* See eDP HDMI DPIO driver vbios notes doc */
4403
4404 /* PLL B needs special handling */
4405 if (pipe)
4406 vlv_pllb_recal_opamp(dev_priv);
4407
4408 /* Set up Tx target for periodic Rcomp update */
4409 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4410
4411 /* Disable target IRef on PLL */
4412 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4413 reg_val &= 0x00ffffff;
4414 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4415
4416 /* Disable fast lock */
4417 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4418
4419 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4420 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4421 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4422 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4423 mdiv |= (1 << DPIO_K_SHIFT);
89b667f8
JB		 4424 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
4425 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4426 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4427 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
a0c4da24
JB		 4428 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4429
89b667f8
JB		 4430 mdiv |= DPIO_ENABLE_CALIBRATION;
4431 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4432
89b667f8
JB		 4433 /* Set HBR and RBR LPF coefficients */
4434 if (adjusted_mode->clock == 162000 ||
4435 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4436 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4437 0x005f0021);
4438 else
4439 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4440 0x00d0000f);
4441
4442 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4443 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4444 /* Use SSC source */
4445 if (!pipe)
4446 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4447 0x0df40000);
4448 else
4449 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4450 0x0df70000);
4451 } else { /* HDMI or VGA */
4452 /* Use bend source */
4453 if (!pipe)
4454 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4455 0x0df70000);
4456 else
4457 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4458 0x0df40000);
4459 }
a0c4da24 4460
89b667f8
JB		 4461 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4462 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4463 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4464 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4465 coreclk |= 0x01000000;
4466 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4467
89b667f8 4468 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4469
89b667f8
JB		 4470 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4471 if (encoder->pre_pll_enable)
4472 encoder->pre_pll_enable(encoder);
2a8f64ca 4473
89b667f8
JB		 4474 /* Enable DPIO clock input */
4475 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4476 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4477 if (pipe)
4478 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4479
89b667f8 4480 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4481 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4482 POSTING_READ(DPLL(pipe));
4483 udelay(150);
a0c4da24 4484
89b667f8
JB		 4485 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4486 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4487
198a037f
DV		 4488 dpll_md = 0;
4489 if (crtc->config.pixel_multiplier > 1) {
4490 dpll_md = (crtc->config.pixel_multiplier - 1)
4491 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
2a8f64ca 4492 }
198a037f
DV		 4493 I915_WRITE(DPLL_MD(pipe), dpll_md);
4494 POSTING_READ(DPLL_MD(pipe));
f47709a9 4495
89b667f8
JB		 4496 if (crtc->config.has_dp_encoder)
4497 intel_dp_set_m_n(crtc);
09153000
DV		 4498
4499 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4500}
4501
f47709a9
DV		 4502static void i9xx_update_pll(struct intel_crtc *crtc,
4503 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4504 int num_connectors)
4505{
f47709a9 4506 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4507 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4508 struct intel_encoder *encoder;
f47709a9 4509 int pipe = crtc->pipe;
eb1cbe48
DV		 4510 u32 dpll;
4511 bool is_sdvo;
f47709a9 4512 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4513
f47709a9 4514 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4515
f47709a9
DV		 4516 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4517 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4518
4519 dpll = DPLL_VGA_MODE_DIS;
4520
f47709a9 4521 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4522 dpll |= DPLLB_MODE_LVDS;
4523 else
4524 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4525
198a037f
DV		 4526 if ((crtc->config.pixel_multiplier > 1) &&
4527 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4528 dpll |= (crtc->config.pixel_multiplier - 1)
4529 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4530 }
198a037f
DV		 4531
4532 if (is_sdvo)
4533 dpll |= DPLL_DVO_HIGH_SPEED;
4534
f47709a9 4535 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4536 dpll |= DPLL_DVO_HIGH_SPEED;
4537
4538 /* compute bitmask from p1 value */
4539 if (IS_PINEVIEW(dev))
4540 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4541 else {
4542 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4543 if (IS_G4X(dev) && reduced_clock)
4544 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4545 }
4546 switch (clock->p2) {
4547 case 5:
4548 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4549 break;
4550 case 7:
4551 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4552 break;
4553 case 10:
4554 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4555 break;
4556 case 14:
4557 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4558 break;
4559 }
4560 if (INTEL_INFO(dev)->gen >= 4)
4561 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4562
f47709a9 4563 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48 4564 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4565 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48
DV		 4566 /* XXX: just matching BIOS for now */
4567 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4568 dpll |= 3;
f47709a9 4569 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4570 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4571 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4572 else
4573 dpll |= PLL_REF_INPUT_DREFCLK;
4574
4575 dpll |= DPLL_VCO_ENABLE;
4576 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4577 POSTING_READ(DPLL(pipe));
4578 udelay(150);
4579
f47709a9 4580 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4581 if (encoder->pre_pll_enable)
4582 encoder->pre_pll_enable(encoder);
eb1cbe48 4583
f47709a9
DV		 4584 if (crtc->config.has_dp_encoder)
4585 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4586
4587 I915_WRITE(DPLL(pipe), dpll);
4588
4589 /* Wait for the clocks to stabilize. */
4590 POSTING_READ(DPLL(pipe));
4591 udelay(150);
4592
4593 if (INTEL_INFO(dev)->gen >= 4) {
198a037f
DV		 4594 u32 dpll_md = 0;
4595 if (crtc->config.pixel_multiplier > 1) {
4596 dpll_md = (crtc->config.pixel_multiplier - 1)
4597 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
eb1cbe48 4598 }
198a037f 4599 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4600 } else {
4601 /* The pixel multiplier can only be updated once the
4602 * DPLL is enabled and the clocks are stable.
4603 *
4604 * So write it again.
4605 */
4606 I915_WRITE(DPLL(pipe), dpll);
4607 }
4608}
4609
f47709a9 4610static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4611 struct drm_display_mode *adjusted_mode,
f47709a9 4612 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4613 int num_connectors)
4614{
f47709a9 4615 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4616 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4617 struct intel_encoder *encoder;
f47709a9 4618 int pipe = crtc->pipe;
eb1cbe48 4619 u32 dpll;
f47709a9 4620 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4621
f47709a9 4622 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4623
eb1cbe48
DV		 4624 dpll = DPLL_VGA_MODE_DIS;
4625
f47709a9 4626 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4627 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4628 } else {
4629 if (clock->p1 == 2)
4630 dpll |= PLL_P1_DIVIDE_BY_TWO;
4631 else
4632 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4633 if (clock->p2 == 4)
4634 dpll |= PLL_P2_DIVIDE_BY_4;
4635 }
4636
f47709a9 4637 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4638 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4639 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4640 else
4641 dpll |= PLL_REF_INPUT_DREFCLK;
4642
4643 dpll |= DPLL_VCO_ENABLE;
4644 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4645 POSTING_READ(DPLL(pipe));
4646 udelay(150);
4647
f47709a9 4648 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4649 if (encoder->pre_pll_enable)
4650 encoder->pre_pll_enable(encoder);
eb1cbe48 4651
5b5896e4
DV		 4652 I915_WRITE(DPLL(pipe), dpll);
4653
4654 /* Wait for the clocks to stabilize. */
4655 POSTING_READ(DPLL(pipe));
4656 udelay(150);
4657
eb1cbe48
DV		 4658 /* The pixel multiplier can only be updated once the
4659 * DPLL is enabled and the clocks are stable.
4660 *
4661 * So write it again.
4662 */
4663 I915_WRITE(DPLL(pipe), dpll);
4664}
4665
b0e77b9c
PZ		 4666static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4667 struct drm_display_mode *mode,
4668 struct drm_display_mode *adjusted_mode)
4669{
4670 struct drm_device *dev = intel_crtc->base.dev;
4671 struct drm_i915_private *dev_priv = dev->dev_private;
4672 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4673 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
b0e77b9c
PZ		 4674 uint32_t vsyncshift;
4675
4676 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4677 /* the chip adds 2 halflines automatically */
4678 adjusted_mode->crtc_vtotal -= 1;
4679 adjusted_mode->crtc_vblank_end -= 1;
4680 vsyncshift = adjusted_mode->crtc_hsync_start
4681 - adjusted_mode->crtc_htotal / 2;
4682 } else {
4683 vsyncshift = 0;
4684 }
4685
4686 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4687 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4688
fe2b8f9d 4689 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4690 (adjusted_mode->crtc_hdisplay - 1) |
4691 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4692 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4693 (adjusted_mode->crtc_hblank_start - 1) |
4694 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4695 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4696 (adjusted_mode->crtc_hsync_start - 1) |
4697 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4698
fe2b8f9d 4699 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4700 (adjusted_mode->crtc_vdisplay - 1) |
4701 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4702 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4703 (adjusted_mode->crtc_vblank_start - 1) |
4704 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4705 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4706 (adjusted_mode->crtc_vsync_start - 1) |
4707 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4708
b5e508d4
PZ		 4709 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4710 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4711 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4712 * bits. */
4713 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4714 (pipe == PIPE_B || pipe == PIPE_C))
4715 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4716
b0e77b9c
PZ		 4717 /* pipesrc controls the size that is scaled from, which should
4718 * always be the user's requested size.
4719 */
4720 I915_WRITE(PIPESRC(pipe),
4721 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4722}
4723
84b046f3
DV		 4724static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4725{
4726 struct drm_device *dev = intel_crtc->base.dev;
4727 struct drm_i915_private *dev_priv = dev->dev_private;
4728 uint32_t pipeconf;
4729
4730 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4731
4732 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4733 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4734 * core speed.
4735 *
4736 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4737 * pipe == 0 check?
4738 */
4739 if (intel_crtc->config.requested_mode.clock >
4740 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4741 pipeconf |= PIPECONF_DOUBLE_WIDE;
4742 else
4743 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4744 }
4745
ff9ce46e
DV		 4746 /* only g4x and later have fancy bpc/dither controls */
4747 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4748 pipeconf &= ~(PIPECONF_BPC_MASK |
4749 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4750
4751 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4752 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4753 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4754 PIPECONF_DITHER_TYPE_SP;
84b046f3 4755
ff9ce46e
DV		 4756 switch (intel_crtc->config.pipe_bpp) {
4757 case 18:
4758 pipeconf |= PIPECONF_6BPC;
4759 break;
4760 case 24:
4761 pipeconf |= PIPECONF_8BPC;
4762 break;
4763 case 30:
4764 pipeconf |= PIPECONF_10BPC;
4765 break;
4766 default:
4767 /* Case prevented by intel_choose_pipe_bpp_dither. */
4768 BUG();
84b046f3
DV		 4769 }
4770 }
4771
4772 if (HAS_PIPE_CXSR(dev)) {
4773 if (intel_crtc->lowfreq_avail) {
4774 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4775 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4776 } else {
4777 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4778 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4779 }
4780 }
4781
4782 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4783 if (!IS_GEN2(dev) &&
4784 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4785 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4786 else
4787 pipeconf |= PIPECONF_PROGRESSIVE;
4788
9c8e09b7
VS		 4789 if (IS_VALLEYVIEW(dev)) {
4790 if (intel_crtc->config.limited_color_range)
4791 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4792 else
4793 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4794 }
4795
84b046f3
DV		 4796 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4797 POSTING_READ(PIPECONF(intel_crtc->pipe));
4798}
4799
f564048e 4800static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4801 int x, int y,
94352cf9 4802 struct drm_framebuffer *fb)
79e53945
JB		 4803{
4804 struct drm_device *dev = crtc->dev;
4805 struct drm_i915_private *dev_priv = dev->dev_private;
4806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4807 struct drm_display_mode *adjusted_mode =
4808 &intel_crtc->config.adjusted_mode;
4809 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4810 int pipe = intel_crtc->pipe;
80824003 4811 int plane = intel_crtc->plane;
c751ce4f 4812 int refclk, num_connectors = 0;
652c393a 4813 intel_clock_t clock, reduced_clock;
84b046f3 4814 u32 dspcntr;
eb1cbe48 4815 bool ok, has_reduced_clock = false, is_sdvo = false;
8b47047b 4816 bool is_lvds = false, is_tv = false;
5eddb70b 4817 struct intel_encoder *encoder;
d4906093 4818 const intel_limit_t *limit;
5c3b82e2 4819 int ret;
79e53945 4820
6c2b7c12 4821 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4822 switch (encoder->type) {
79e53945
JB		 4823 case INTEL_OUTPUT_LVDS:
4824 is_lvds = true;
4825 break;
4826 case INTEL_OUTPUT_SDVO:
7d57382e 4827 case INTEL_OUTPUT_HDMI:
79e53945 4828 is_sdvo = true;
5eddb70b 4829 if (encoder->needs_tv_clock)
e2f0ba97 4830 is_tv = true;
79e53945 4831 break;
79e53945
JB		 4832 case INTEL_OUTPUT_TVOUT:
4833 is_tv = true;
4834 break;
79e53945 4835 }
43565a06 4836
c751ce4f 4837 num_connectors++;
79e53945
JB		 4838 }
4839
c65d77d8 4840 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4841
d4906093
ML		 4842 /*
4843 * Returns a set of divisors for the desired target clock with the given
4844 * refclk, or FALSE. The returned values represent the clock equation:
4845 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4846 */
1b894b59 4847 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4848 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4849 &clock);
79e53945
JB		 4850 if (!ok) {
4851 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4852 return -EINVAL;
79e53945
JB		 4853 }
4854
cda4b7d3 4855 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4856 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4857
ddc9003c 4858 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4859 /*
4860 * Ensure we match the reduced clock's P to the target clock.
4861 * If the clocks don't match, we can't switch the display clock
4862 * by using the FP0/FP1. In such case we will disable the LVDS
4863 * downclock feature.
4864 */
ddc9003c 4865 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4866 dev_priv->lvds_downclock,
4867 refclk,
cec2f356 4868 &clock,
5eddb70b 4869 &reduced_clock);
7026d4ac 4870 }
f47709a9
DV		 4871 /* Compat-code for transition, will disappear. */
4872 if (!intel_crtc->config.clock_set) {
4873 intel_crtc->config.dpll.n = clock.n;
4874 intel_crtc->config.dpll.m1 = clock.m1;
4875 intel_crtc->config.dpll.m2 = clock.m2;
4876 intel_crtc->config.dpll.p1 = clock.p1;
4877 intel_crtc->config.dpll.p2 = clock.p2;
4878 }
7026d4ac 4879
c65d77d8 4880 if (is_sdvo && is_tv)
f47709a9 4881 i9xx_adjust_sdvo_tv_clock(intel_crtc);
7026d4ac 4882
eb1cbe48 4883 if (IS_GEN2(dev))
f47709a9 4884 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4885 has_reduced_clock ? &reduced_clock : NULL,
4886 num_connectors);
a0c4da24 4887 else if (IS_VALLEYVIEW(dev))
f47709a9 4888 vlv_update_pll(intel_crtc);
79e53945 4889 else
f47709a9 4890 i9xx_update_pll(intel_crtc,
eb1cbe48 4891 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4892 num_connectors);
79e53945 4893
79e53945
JB		 4894 /* Set up the display plane register */
4895 dspcntr = DISPPLANE_GAMMA_ENABLE;
4896
da6ecc5d
JB		 4897 if (!IS_VALLEYVIEW(dev)) {
4898 if (pipe == 0)
4899 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4900 else
4901 dspcntr |= DISPPLANE_SEL_PIPE_B;
4902 }
79e53945 4903
2582a850 4904 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 4905 drm_mode_debug_printmodeline(mode);
4906
b0e77b9c 4907 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4908
4909 /* pipesrc and dspsize control the size that is scaled from,
4910 * which should always be the user's requested size.
79e53945 4911 */
929c77fb
EA		 4912 I915_WRITE(DSPSIZE(plane),
4913 ((mode->vdisplay - 1) << 16) |
4914 (mode->hdisplay - 1));
4915 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4916
84b046f3
DV		 4917 i9xx_set_pipeconf(intel_crtc);
4918
f564048e
EA		 4919 I915_WRITE(DSPCNTR(plane), dspcntr);
4920 POSTING_READ(DSPCNTR(plane));
4921
94352cf9 4922 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4923
4924 intel_update_watermarks(dev);
4925
f564048e
EA		 4926 return ret;
4927}
4928
0e8ffe1b
DV		 4929static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4930 struct intel_crtc_config *pipe_config)
4931{
4932 struct drm_device *dev = crtc->base.dev;
4933 struct drm_i915_private *dev_priv = dev->dev_private;
4934 uint32_t tmp;
4935
4936 tmp = I915_READ(PIPECONF(crtc->pipe));
4937 if (!(tmp & PIPECONF_ENABLE))
4938 return false;
4939
4940 return true;
4941}
4942
dde86e2d 4943static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4944{
4945 struct drm_i915_private *dev_priv = dev->dev_private;
4946 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4947 struct intel_encoder *encoder;
74cfd7ac 4948 u32 val, final;
13d83a67 4949 bool has_lvds = false;
199e5d79
KP		 4950 bool has_cpu_edp = false;
4951 bool has_pch_edp = false;
4952 bool has_panel = false;
99eb6a01
KP		 4953 bool has_ck505 = false;
4954 bool can_ssc = false;
13d83a67
JB		 4955
4956 /* We need to take the global config into account */
199e5d79
KP		 4957 list_for_each_entry(encoder, &mode_config->encoder_list,
4958 base.head) {
4959 switch (encoder->type) {
4960 case INTEL_OUTPUT_LVDS:
4961 has_panel = true;
4962 has_lvds = true;
4963 break;
4964 case INTEL_OUTPUT_EDP:
4965 has_panel = true;
4966 if (intel_encoder_is_pch_edp(&encoder->base))
4967 has_pch_edp = true;
4968 else
4969 has_cpu_edp = true;
4970 break;
13d83a67
JB		 4971 }
4972 }
4973
99eb6a01
KP		 4974 if (HAS_PCH_IBX(dev)) {
4975 has_ck505 = dev_priv->display_clock_mode;
4976 can_ssc = has_ck505;
4977 } else {
4978 has_ck505 = false;
4979 can_ssc = true;
4980 }
4981
4982 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4983 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4984 has_ck505);
13d83a67
JB		 4985
4986 /* Ironlake: try to setup display ref clock before DPLL
4987 * enabling. This is only under driver's control after
4988 * PCH B stepping, previous chipset stepping should be
4989 * ignoring this setting.
4990 */
74cfd7ac
CW		 4991 val = I915_READ(PCH_DREF_CONTROL);
4992
4993 /* As we must carefully and slowly disable/enable each source in turn,
4994 * compute the final state we want first and check if we need to
4995 * make any changes at all.
4996 */
4997 final = val;
4998 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4999 if (has_ck505)
5000 final |= DREF_NONSPREAD_CK505_ENABLE;
5001 else
5002 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5003
5004 final &= ~DREF_SSC_SOURCE_MASK;
5005 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5006 final &= ~DREF_SSC1_ENABLE;
5007
5008 if (has_panel) {
5009 final |= DREF_SSC_SOURCE_ENABLE;
5010
5011 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5012 final |= DREF_SSC1_ENABLE;
5013
5014 if (has_cpu_edp) {
5015 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5016 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5017 else
5018 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5019 } else
5020 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5021 } else {
5022 final |= DREF_SSC_SOURCE_DISABLE;
5023 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5024 }
5025
5026 if (final == val)
5027 return;
5028
13d83a67 5029 /* Always enable nonspread source */
74cfd7ac 5030 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5031
99eb6a01 5032 if (has_ck505)
74cfd7ac 5033 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5034 else
74cfd7ac 5035 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5036
199e5d79 5037 if (has_panel) {
74cfd7ac
CW		 5038 val &= ~DREF_SSC_SOURCE_MASK;
5039 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5040
199e5d79 5041 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5042 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5043 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5044 val |= DREF_SSC1_ENABLE;
e77166b5 5045 } else
74cfd7ac 5046 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5047
5048 /* Get SSC going before enabling the outputs */
74cfd7ac 5049 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5050 POSTING_READ(PCH_DREF_CONTROL);
5051 udelay(200);
5052
74cfd7ac 5053 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5054
5055 /* Enable CPU source on CPU attached eDP */
199e5d79 5056 if (has_cpu_edp) {
99eb6a01 5057 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5058 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5059 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5060 }
13d83a67 5061 else
74cfd7ac 5062 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5063 } else
74cfd7ac 5064 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5065
74cfd7ac 5066 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5067 POSTING_READ(PCH_DREF_CONTROL);
5068 udelay(200);
5069 } else {
5070 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5071
74cfd7ac 5072 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5073
5074 /* Turn off CPU output */
74cfd7ac 5075 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5076
74cfd7ac 5077 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5078 POSTING_READ(PCH_DREF_CONTROL);
5079 udelay(200);
5080
5081 /* Turn off the SSC source */
74cfd7ac
CW		 5082 val &= ~DREF_SSC_SOURCE_MASK;
5083 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5084
5085 /* Turn off SSC1 */
74cfd7ac 5086 val &= ~DREF_SSC1_ENABLE;
199e5d79 5087
74cfd7ac 5088 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5089 POSTING_READ(PCH_DREF_CONTROL);
5090 udelay(200);
5091 }
74cfd7ac
CW		 5092
5093 BUG_ON(val != final);
13d83a67
JB		 5094}
5095
dde86e2d
PZ		 5096/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5097static void lpt_init_pch_refclk(struct drm_device *dev)
5098{
5099 struct drm_i915_private *dev_priv = dev->dev_private;
5100 struct drm_mode_config *mode_config = &dev->mode_config;
5101 struct intel_encoder *encoder;
5102 bool has_vga = false;
5103 bool is_sdv = false;
5104 u32 tmp;
5105
5106 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5107 switch (encoder->type) {
5108 case INTEL_OUTPUT_ANALOG:
5109 has_vga = true;
5110 break;
5111 }
5112 }
5113
5114 if (!has_vga)
5115 return;
5116
c00db246
DV		 5117 mutex_lock(&dev_priv->dpio_lock);
5118
dde86e2d
PZ		 5119 /* XXX: Rip out SDV support once Haswell ships for real. */
5120 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5121 is_sdv = true;
5122
5123 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5124 tmp &= ~SBI_SSCCTL_DISABLE;
5125 tmp |= SBI_SSCCTL_PATHALT;
5126 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5127
5128 udelay(24);
5129
5130 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5131 tmp &= ~SBI_SSCCTL_PATHALT;
5132 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5133
5134 if (!is_sdv) {
5135 tmp = I915_READ(SOUTH_CHICKEN2);
5136 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5137 I915_WRITE(SOUTH_CHICKEN2, tmp);
5138
5139 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5140 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5141 DRM_ERROR("FDI mPHY reset assert timeout\n");
5142
5143 tmp = I915_READ(SOUTH_CHICKEN2);
5144 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5145 I915_WRITE(SOUTH_CHICKEN2, tmp);
5146
5147 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5148 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5149 100))
5150 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5151 }
5152
5153 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5154 tmp &= ~(0xFF << 24);
5155 tmp |= (0x12 << 24);
5156 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5157
dde86e2d
PZ		 5158 if (is_sdv) {
5159 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5160 tmp |= 0x7FFF;
5161 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5162 }
5163
5164 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5165 tmp |= (1 << 11);
5166 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5167
5168 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5169 tmp |= (1 << 11);
5170 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5171
5172 if (is_sdv) {
5173 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5174 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5175 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5176
5177 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5178 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5179 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5180
5181 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5182 tmp |= (0x3F << 8);
5183 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5184
5185 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5186 tmp |= (0x3F << 8);
5187 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5188 }
5189
5190 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5191 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5192 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5193
5194 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5195 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5196 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5197
5198 if (!is_sdv) {
5199 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5200 tmp &= ~(7 << 13);
5201 tmp |= (5 << 13);
5202 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5203
5204 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5205 tmp &= ~(7 << 13);
5206 tmp |= (5 << 13);
5207 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5208 }
5209
5210 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5211 tmp &= ~0xFF;
5212 tmp |= 0x1C;
5213 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5214
5215 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5216 tmp &= ~0xFF;
5217 tmp |= 0x1C;
5218 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5219
5220 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5221 tmp &= ~(0xFF << 16);
5222 tmp |= (0x1C << 16);
5223 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5224
5225 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5226 tmp &= ~(0xFF << 16);
5227 tmp |= (0x1C << 16);
5228 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5229
5230 if (!is_sdv) {
5231 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5232 tmp |= (1 << 27);
5233 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5234
5235 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5236 tmp |= (1 << 27);
5237 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5238
5239 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5240 tmp &= ~(0xF << 28);
5241 tmp |= (4 << 28);
5242 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5243
5244 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5245 tmp &= ~(0xF << 28);
5246 tmp |= (4 << 28);
5247 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5248 }
5249
5250 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5251 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5252 tmp |= SBI_DBUFF0_ENABLE;
5253 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5254
5255 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5256}
5257
5258/*
5259 * Initialize reference clocks when the driver loads
5260 */
5261void intel_init_pch_refclk(struct drm_device *dev)
5262{
5263 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5264 ironlake_init_pch_refclk(dev);
5265 else if (HAS_PCH_LPT(dev))
5266 lpt_init_pch_refclk(dev);
5267}
5268
d9d444cb
JB		 5269static int ironlake_get_refclk(struct drm_crtc *crtc)
5270{
5271 struct drm_device *dev = crtc->dev;
5272 struct drm_i915_private *dev_priv = dev->dev_private;
5273 struct intel_encoder *encoder;
d9d444cb
JB		 5274 struct intel_encoder *edp_encoder = NULL;
5275 int num_connectors = 0;
5276 bool is_lvds = false;
5277
6c2b7c12 5278 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5279 switch (encoder->type) {
5280 case INTEL_OUTPUT_LVDS:
5281 is_lvds = true;
5282 break;
5283 case INTEL_OUTPUT_EDP:
5284 edp_encoder = encoder;
5285 break;
5286 }
5287 num_connectors++;
5288 }
5289
5290 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5291 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5292 dev_priv->lvds_ssc_freq);
5293 return dev_priv->lvds_ssc_freq * 1000;
5294 }
5295
5296 return 120000;
5297}
5298
6ff93609 5299static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5300{
c8203565 5301 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5303 int pipe = intel_crtc->pipe;
c8203565
PZ		 5304 uint32_t val;
5305
5306 val = I915_READ(PIPECONF(pipe));
5307
dfd07d72 5308 val &= ~PIPECONF_BPC_MASK;
965e0c48 5309 switch (intel_crtc->config.pipe_bpp) {
c8203565 5310 case 18:
dfd07d72 5311 val |= PIPECONF_6BPC;
c8203565
PZ		 5312 break;
5313 case 24:
dfd07d72 5314 val |= PIPECONF_8BPC;
c8203565
PZ		 5315 break;
5316 case 30:
dfd07d72 5317 val |= PIPECONF_10BPC;
c8203565
PZ		 5318 break;
5319 case 36:
dfd07d72 5320 val |= PIPECONF_12BPC;
c8203565
PZ		 5321 break;
5322 default:
cc769b62
PZ		 5323 /* Case prevented by intel_choose_pipe_bpp_dither. */
5324 BUG();
c8203565
PZ		 5325 }
5326
5327 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5328 if (intel_crtc->config.dither)
c8203565
PZ		 5329 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5330
5331 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5332 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5333 val |= PIPECONF_INTERLACED_ILK;
5334 else
5335 val |= PIPECONF_PROGRESSIVE;
5336
50f3b016 5337 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5338 val |= PIPECONF_COLOR_RANGE_SELECT;
5339 else
5340 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5341
c8203565
PZ		 5342 I915_WRITE(PIPECONF(pipe), val);
5343 POSTING_READ(PIPECONF(pipe));
5344}
5345
86d3efce
VS		 5346/*
5347 * Set up the pipe CSC unit.
5348 *
5349 * Currently only full range RGB to limited range RGB conversion
5350 * is supported, but eventually this should handle various
5351 * RGB<->YCbCr scenarios as well.
5352 */
50f3b016 5353static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5354{
5355 struct drm_device *dev = crtc->dev;
5356 struct drm_i915_private *dev_priv = dev->dev_private;
5357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5358 int pipe = intel_crtc->pipe;
5359 uint16_t coeff = 0x7800; /* 1.0 */
5360
5361 /*
5362 * TODO: Check what kind of values actually come out of the pipe
5363 * with these coeff/postoff values and adjust to get the best
5364 * accuracy. Perhaps we even need to take the bpc value into
5365 * consideration.
5366 */
5367
50f3b016 5368 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5369 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5370
5371 /*
5372 * GY/GU and RY/RU should be the other way around according
5373 * to BSpec, but reality doesn't agree. Just set them up in
5374 * a way that results in the correct picture.
5375 */
5376 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5377 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5378
5379 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5380 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5381
5382 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5383 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5384
5385 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5386 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5387 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5388
5389 if (INTEL_INFO(dev)->gen > 6) {
5390 uint16_t postoff = 0;
5391
50f3b016 5392 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5393 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5394
5395 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5396 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5397 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5398
5399 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5400 } else {
5401 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5402
50f3b016 5403 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5404 mode |= CSC_BLACK_SCREEN_OFFSET;
5405
5406 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5407 }
5408}
5409
6ff93609 5410static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5411{
5412 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5414 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5415 uint32_t val;
5416
702e7a56 5417 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5418
5419 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5420 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5421 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5422
5423 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5424 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5425 val |= PIPECONF_INTERLACED_ILK;
5426 else
5427 val |= PIPECONF_PROGRESSIVE;
5428
702e7a56
PZ		 5429 I915_WRITE(PIPECONF(cpu_transcoder), val);
5430 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5431}
5432
6591c6e4
PZ		 5433static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5434 struct drm_display_mode *adjusted_mode,
5435 intel_clock_t *clock,
5436 bool *has_reduced_clock,
5437 intel_clock_t *reduced_clock)
5438{
5439 struct drm_device *dev = crtc->dev;
5440 struct drm_i915_private *dev_priv = dev->dev_private;
5441 struct intel_encoder *intel_encoder;
5442 int refclk;
d4906093 5443 const intel_limit_t *limit;
6591c6e4 5444 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5445
6591c6e4
PZ		 5446 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5447 switch (intel_encoder->type) {
79e53945
JB		 5448 case INTEL_OUTPUT_LVDS:
5449 is_lvds = true;
5450 break;
5451 case INTEL_OUTPUT_SDVO:
7d57382e 5452 case INTEL_OUTPUT_HDMI:
79e53945 5453 is_sdvo = true;
6591c6e4 5454 if (intel_encoder->needs_tv_clock)
e2f0ba97 5455 is_tv = true;
79e53945 5456 break;
79e53945
JB		 5457 case INTEL_OUTPUT_TVOUT:
5458 is_tv = true;
5459 break;
79e53945
JB		 5460 }
5461 }
5462
d9d444cb 5463 refclk = ironlake_get_refclk(crtc);
79e53945 5464
d4906093
ML		 5465 /*
5466 * Returns a set of divisors for the desired target clock with the given
5467 * refclk, or FALSE. The returned values represent the clock equation:
5468 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5469 */
1b894b59 5470 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5471 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5472 clock);
5473 if (!ret)
5474 return false;
cda4b7d3 5475
ddc9003c 5476 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5477 /*
5478 * Ensure we match the reduced clock's P to the target clock.
5479 * If the clocks don't match, we can't switch the display clock
5480 * by using the FP0/FP1. In such case we will disable the LVDS
5481 * downclock feature.
5482 */
6591c6e4
PZ		 5483 *has_reduced_clock = limit->find_pll(limit, crtc,
5484 dev_priv->lvds_downclock,
5485 refclk,
5486 clock,
5487 reduced_clock);
652c393a 5488 }
61e9653f
DV		 5489
5490 if (is_sdvo && is_tv)
f47709a9 5491 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
6591c6e4
PZ		 5492
5493 return true;
5494}
5495
01a415fd
DV		 5496static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5497{
5498 struct drm_i915_private *dev_priv = dev->dev_private;
5499 uint32_t temp;
5500
5501 temp = I915_READ(SOUTH_CHICKEN1);
5502 if (temp & FDI_BC_BIFURCATION_SELECT)
5503 return;
5504
5505 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5506 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5507
5508 temp |= FDI_BC_BIFURCATION_SELECT;
5509 DRM_DEBUG_KMS("enabling fdi C rx\n");
5510 I915_WRITE(SOUTH_CHICKEN1, temp);
5511 POSTING_READ(SOUTH_CHICKEN1);
5512}
5513
ebfd86fd
DV		 5514static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5515{
5516 struct drm_device *dev = intel_crtc->base.dev;
5517 struct drm_i915_private *dev_priv = dev->dev_private;
5518
5519 switch (intel_crtc->pipe) {
5520 case PIPE_A:
5521 break;
5522 case PIPE_B:
5523 if (intel_crtc->config.fdi_lanes > 2)
5524 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5525 else
5526 cpt_enable_fdi_bc_bifurcation(dev);
5527
5528 break;
5529 case PIPE_C:
01a415fd
DV		 5530 cpt_enable_fdi_bc_bifurcation(dev);
5531
ebfd86fd 5532 break;
01a415fd
DV		 5533 default:
5534 BUG();
5535 }
5536}
5537
d4b1931c
PZ		 5538int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5539{
5540 /*
5541 * Account for spread spectrum to avoid
5542 * oversubscribing the link. Max center spread
5543 * is 2.5%; use 5% for safety's sake.
5544 */
5545 u32 bps = target_clock * bpp * 21 / 20;
5546 return bps / (link_bw * 8) + 1;
5547}
5548
6cf86a5e
DV		 5549void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5550 struct intel_link_m_n *m_n)
79e53945 5551{
6cf86a5e
DV		 5552 struct drm_device *dev = crtc->base.dev;
5553 struct drm_i915_private *dev_priv = dev->dev_private;
5554 int pipe = crtc->pipe;
5555
5556 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5557 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5558 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5559 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5560}
5561
5562void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5563 struct intel_link_m_n *m_n)
5564{
5565 struct drm_device *dev = crtc->base.dev;
79e53945 5566 struct drm_i915_private *dev_priv = dev->dev_private;
6cf86a5e 5567 int pipe = crtc->pipe;
3b117c8f 5568 enum transcoder transcoder = crtc->config.cpu_transcoder;
6cf86a5e
DV		 5569
5570 if (INTEL_INFO(dev)->gen >= 5) {
5571 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5572 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5573 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5574 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5575 } else {
5576 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5577 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5578 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5579 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5580 }
5581}
5582
7429e9d4
DV		 5583static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5584{
5585 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5586}
5587
de13a2e3 5588static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5589 u32 *fp,
9a7c7890 5590 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5591{
de13a2e3 5592 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5593 struct drm_device *dev = crtc->dev;
5594 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5595 struct intel_encoder *intel_encoder;
5596 uint32_t dpll;
6cc5f341 5597 int factor, num_connectors = 0;
de13a2e3 5598 bool is_lvds = false, is_sdvo = false, is_tv = false;
79e53945 5599
de13a2e3
PZ		 5600 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5601 switch (intel_encoder->type) {
79e53945
JB		 5602 case INTEL_OUTPUT_LVDS:
5603 is_lvds = true;
5604 break;
5605 case INTEL_OUTPUT_SDVO:
7d57382e 5606 case INTEL_OUTPUT_HDMI:
79e53945 5607 is_sdvo = true;
de13a2e3 5608 if (intel_encoder->needs_tv_clock)
e2f0ba97 5609 is_tv = true;
79e53945 5610 break;
79e53945
JB		 5611 case INTEL_OUTPUT_TVOUT:
5612 is_tv = true;
5613 break;
79e53945 5614 }
43565a06 5615
c751ce4f 5616 num_connectors++;
79e53945 5617 }
79e53945 5618
c1858123 5619 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5620 factor = 21;
5621 if (is_lvds) {
5622 if ((intel_panel_use_ssc(dev_priv) &&
5623 dev_priv->lvds_ssc_freq == 100) ||
f0b44056 5624 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297
EA		 5625 factor = 25;
5626 } else if (is_sdvo && is_tv)
5627 factor = 20;
c1858123 5628
7429e9d4 5629 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5630 *fp |= FP_CB_TUNE;
2c07245f 5631
9a7c7890
DV		 5632 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5633 *fp2 |= FP_CB_TUNE;
5634
5eddb70b 5635 dpll = 0;
2c07245f 5636
a07d6787
EA		 5637 if (is_lvds)
5638 dpll |= DPLLB_MODE_LVDS;
5639 else
5640 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f
DV		 5641
5642 if (intel_crtc->config.pixel_multiplier > 1) {
5643 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5644 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
a07d6787 5645 }
198a037f
DV		 5646
5647 if (is_sdvo)
5648 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5649 if (intel_crtc->config.has_dp_encoder)
a07d6787 5650 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5651
a07d6787 5652 /* compute bitmask from p1 value */
7429e9d4 5653 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5654 /* also FPA1 */
7429e9d4 5655 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5656
7429e9d4 5657 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5658 case 5:
5659 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5660 break;
5661 case 7:
5662 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5663 break;
5664 case 10:
5665 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5666 break;
5667 case 14:
5668 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5669 break;
79e53945
JB		 5670 }
5671
43565a06
KH		 5672 if (is_sdvo && is_tv)
5673 dpll |= PLL_REF_INPUT_TVCLKINBC;
5674 else if (is_tv)
79e53945 5675 /* XXX: just matching BIOS for now */
43565a06 5676 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5677 dpll |= 3;
a7615030 5678 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5679 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5680 else
5681 dpll |= PLL_REF_INPUT_DREFCLK;
5682
de13a2e3
PZ		 5683 return dpll;
5684}
5685
5686static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5687 int x, int y,
5688 struct drm_framebuffer *fb)
5689{
5690 struct drm_device *dev = crtc->dev;
5691 struct drm_i915_private *dev_priv = dev->dev_private;
5692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5693 struct drm_display_mode *adjusted_mode =
5694 &intel_crtc->config.adjusted_mode;
5695 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5696 int pipe = intel_crtc->pipe;
5697 int plane = intel_crtc->plane;
5698 int num_connectors = 0;
5699 intel_clock_t clock, reduced_clock;
cbbab5bd 5700 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5701 bool ok, has_reduced_clock = false;
8b47047b 5702 bool is_lvds = false;
de13a2e3 5703 struct intel_encoder *encoder;
de13a2e3 5704 int ret;
de13a2e3
PZ		 5705
5706 for_each_encoder_on_crtc(dev, crtc, encoder) {
5707 switch (encoder->type) {
5708 case INTEL_OUTPUT_LVDS:
5709 is_lvds = true;
5710 break;
de13a2e3
PZ		 5711 }
5712
5713 num_connectors++;
a07d6787 5714 }
79e53945 5715
5dc5298b
PZ		 5716 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5717 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5718
3b117c8f 5719 intel_crtc->config.cpu_transcoder = pipe;
6cf86a5e 5720
de13a2e3
PZ		 5721 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5722 &has_reduced_clock, &reduced_clock);
5723 if (!ok) {
5724 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5725 return -EINVAL;
79e53945 5726 }
f47709a9
DV		 5727 /* Compat-code for transition, will disappear. */
5728 if (!intel_crtc->config.clock_set) {
5729 intel_crtc->config.dpll.n = clock.n;
5730 intel_crtc->config.dpll.m1 = clock.m1;
5731 intel_crtc->config.dpll.m2 = clock.m2;
5732 intel_crtc->config.dpll.p1 = clock.p1;
5733 intel_crtc->config.dpll.p2 = clock.p2;
5734 }
79e53945 5735
de13a2e3
PZ		 5736 /* Ensure that the cursor is valid for the new mode before changing... */
5737 intel_crtc_update_cursor(crtc, true);
5738
84f44ce7 5739 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 5740 drm_mode_debug_printmodeline(mode);
5741
5dc5298b 5742 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5743 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5744 struct intel_pch_pll *pll;
4b645f14 5745
7429e9d4 5746 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5747 if (has_reduced_clock)
7429e9d4 5748 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5749
7429e9d4 5750 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5751 &fp, &reduced_clock,
5752 has_reduced_clock ? &fp2 : NULL);
5753
ee7b9f93
JB		 5754 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5755 if (pll == NULL) {
84f44ce7
VS		 5756 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5757 pipe_name(pipe));
4b645f14
JB		 5758 return -EINVAL;
5759 }
ee7b9f93
JB		 5760 } else
5761 intel_put_pch_pll(intel_crtc);
79e53945 5762
03afc4a2
DV		 5763 if (intel_crtc->config.has_dp_encoder)
5764 intel_dp_set_m_n(intel_crtc);
79e53945 5765
dafd226c
DV		 5766 for_each_encoder_on_crtc(dev, crtc, encoder)
5767 if (encoder->pre_pll_enable)
5768 encoder->pre_pll_enable(encoder);
79e53945 5769
ee7b9f93
JB		 5770 if (intel_crtc->pch_pll) {
5771 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5772
32f9d658 5773 /* Wait for the clocks to stabilize. */
ee7b9f93 5774 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5775 udelay(150);
5776
8febb297
EA		 5777 /* The pixel multiplier can only be updated once the
5778 * DPLL is enabled and the clocks are stable.
5779 *
5780 * So write it again.
5781 */
ee7b9f93 5782 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5783 }
79e53945 5784
5eddb70b 5785 intel_crtc->lowfreq_avail = false;
ee7b9f93 5786 if (intel_crtc->pch_pll) {
4b645f14 5787 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5788 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5789 intel_crtc->lowfreq_avail = true;
4b645f14 5790 } else {
ee7b9f93 5791 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5792 }
5793 }
5794
b0e77b9c 5795 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5796
ca3a0ff8 5797 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5798 intel_cpu_transcoder_set_m_n(intel_crtc,
5799 &intel_crtc->config.fdi_m_n);
5800 }
2c07245f 5801
ebfd86fd
DV		 5802 if (IS_IVYBRIDGE(dev))
5803 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5804
6ff93609 5805 ironlake_set_pipeconf(crtc);
79e53945 5806
a1f9e77e
PZ		 5807 /* Set up the display plane register */
5808 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5809 POSTING_READ(DSPCNTR(plane));
79e53945 5810
94352cf9 5811 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5812
5813 intel_update_watermarks(dev);
5814
1f8eeabf
ED		 5815 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5816
1857e1da 5817 return ret;
79e53945
JB		 5818}
5819
0e8ffe1b
DV		 5820static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5821 struct intel_crtc_config *pipe_config)
5822{
5823 struct drm_device *dev = crtc->base.dev;
5824 struct drm_i915_private *dev_priv = dev->dev_private;
5825 uint32_t tmp;
5826
5827 tmp = I915_READ(PIPECONF(crtc->pipe));
5828 if (!(tmp & PIPECONF_ENABLE))
5829 return false;
5830
627eb5a3 5831 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5832 pipe_config->has_pch_encoder = true;
5833
627eb5a3
DV		 5834 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5835 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5836 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5837 }
5838
0e8ffe1b
DV		 5839 return true;
5840}
5841
d6dd9eb1
DV		 5842static void haswell_modeset_global_resources(struct drm_device *dev)
5843{
5844 struct drm_i915_private *dev_priv = dev->dev_private;
5845 bool enable = false;
5846 struct intel_crtc *crtc;
5847 struct intel_encoder *encoder;
5848
5849 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5850 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5851 enable = true;
5852 /* XXX: Should check for edp transcoder here, but thanks to init
5853 * sequence that's not yet available. Just in case desktop eDP
5854 * on PORT D is possible on haswell, too. */
b074cec8
JB		 5855 /* Even the eDP panel fitter is outside the always-on well. */
5856 if (I915_READ(PF_WIN_SZ(crtc->pipe)))
5857 enable = true;
d6dd9eb1
DV		 5858 }
5859
5860 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5861 base.head) {
5862 if (encoder->type != INTEL_OUTPUT_EDP &&
5863 encoder->connectors_active)
5864 enable = true;
5865 }
5866
d6dd9eb1
DV		 5867 intel_set_power_well(dev, enable);
5868}
5869
09b4ddf9 5870static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5871 int x, int y,
5872 struct drm_framebuffer *fb)
5873{
5874 struct drm_device *dev = crtc->dev;
5875 struct drm_i915_private *dev_priv = dev->dev_private;
5876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5877 struct drm_display_mode *adjusted_mode =
5878 &intel_crtc->config.adjusted_mode;
5879 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5880 int pipe = intel_crtc->pipe;
5881 int plane = intel_crtc->plane;
5882 int num_connectors = 0;
8b47047b 5883 bool is_cpu_edp = false;
09b4ddf9 5884 struct intel_encoder *encoder;
09b4ddf9 5885 int ret;
09b4ddf9
PZ		 5886
5887 for_each_encoder_on_crtc(dev, crtc, encoder) {
5888 switch (encoder->type) {
09b4ddf9 5889 case INTEL_OUTPUT_EDP:
09b4ddf9
PZ		 5890 if (!intel_encoder_is_pch_edp(&encoder->base))
5891 is_cpu_edp = true;
5892 break;
5893 }
5894
5895 num_connectors++;
5896 }
5897
bba2181c 5898 if (is_cpu_edp)
3b117c8f 5899 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
bba2181c 5900 else
3b117c8f 5901 intel_crtc->config.cpu_transcoder = pipe;
bba2181c 5902
5dc5298b
PZ		 5903 /* We are not sure yet this won't happen. */
5904 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5905 INTEL_PCH_TYPE(dev));
5906
5907 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5908 num_connectors, pipe_name(pipe));
5909
3b117c8f 5910 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
1ce42920
PZ		 5911 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5912
5913 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5914
6441ab5f
PZ		 5915 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5916 return -EINVAL;
5917
09b4ddf9
PZ		 5918 /* Ensure that the cursor is valid for the new mode before changing... */
5919 intel_crtc_update_cursor(crtc, true);
5920
84f44ce7 5921 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
09b4ddf9
PZ		 5922 drm_mode_debug_printmodeline(mode);
5923
03afc4a2
DV		 5924 if (intel_crtc->config.has_dp_encoder)
5925 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5926
5927 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5928
5929 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5930
ca3a0ff8 5931 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5932 intel_cpu_transcoder_set_m_n(intel_crtc,
5933 &intel_crtc->config.fdi_m_n);
5934 }
09b4ddf9 5935
6ff93609 5936 haswell_set_pipeconf(crtc);
09b4ddf9 5937
50f3b016 5938 intel_set_pipe_csc(crtc);
86d3efce 5939
09b4ddf9 5940 /* Set up the display plane register */
86d3efce 5941 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5942 POSTING_READ(DSPCNTR(plane));
5943
5944 ret = intel_pipe_set_base(crtc, x, y, fb);
5945
5946 intel_update_watermarks(dev);
5947
5948 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5949
1f803ee5 5950 return ret;
79e53945
JB		 5951}
5952
0e8ffe1b
DV		 5953static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5954 struct intel_crtc_config *pipe_config)
5955{
5956 struct drm_device *dev = crtc->base.dev;
5957 struct drm_i915_private *dev_priv = dev->dev_private;
2bfce950 5958 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 5959 uint32_t tmp;
5960
2bfce950
PZ		 5961 if (!intel_using_power_well(dev_priv->dev) &&
5962 cpu_transcoder != TRANSCODER_EDP)
5963 return false;
5964
5965 tmp = I915_READ(PIPECONF(cpu_transcoder));
0e8ffe1b
DV		 5966 if (!(tmp & PIPECONF_ENABLE))
5967 return false;
5968
88adfff1 5969 /*
f196e6be 5970 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5971 * DDI E. So just check whether this pipe is wired to DDI E and whether
5972 * the PCH transcoder is on.
5973 */
f196e6be 5974 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
88adfff1 5975 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
627eb5a3 5976 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE) {
88adfff1
DV		 5977 pipe_config->has_pch_encoder = true;
5978
627eb5a3
DV		 5979 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5980 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5981 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5982 }
5983
0e8ffe1b
DV		 5984 return true;
5985}
5986
f564048e 5987static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5988 int x, int y,
94352cf9 5989 struct drm_framebuffer *fb)
f564048e
EA		 5990{
5991 struct drm_device *dev = crtc->dev;
5992 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5993 struct drm_encoder_helper_funcs *encoder_funcs;
5994 struct intel_encoder *encoder;
0b701d27 5995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5996 struct drm_display_mode *adjusted_mode =
5997 &intel_crtc->config.adjusted_mode;
5998 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5999 int pipe = intel_crtc->pipe;
f564048e
EA		 6000 int ret;
6001
0b701d27 6002 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6003
b8cecdf5
DV		 6004 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6005
79e53945 6006 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6007
9256aa19
DV		 6008 if (ret != 0)
6009 return ret;
6010
6011 for_each_encoder_on_crtc(dev, crtc, encoder) {
6012 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6013 encoder->base.base.id,
6014 drm_get_encoder_name(&encoder->base),
6015 mode->base.id, mode->name);
6cc5f341
DV		 6016 if (encoder->mode_set) {
6017 encoder->mode_set(encoder);
6018 } else {
6019 encoder_funcs = encoder->base.helper_private;
6020 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6021 }
9256aa19
DV		 6022 }
6023
6024 return 0;
79e53945
JB		 6025}
6026
3a9627f4
WF		 6027static bool intel_eld_uptodate(struct drm_connector *connector,
6028 int reg_eldv, uint32_t bits_eldv,
6029 int reg_elda, uint32_t bits_elda,
6030 int reg_edid)
6031{
6032 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6033 uint8_t *eld = connector->eld;
6034 uint32_t i;
6035
6036 i = I915_READ(reg_eldv);
6037 i &= bits_eldv;
6038
6039 if (!eld[0])
6040 return !i;
6041
6042 if (!i)
6043 return false;
6044
6045 i = I915_READ(reg_elda);
6046 i &= ~bits_elda;
6047 I915_WRITE(reg_elda, i);
6048
6049 for (i = 0; i < eld[2]; i++)
6050 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6051 return false;
6052
6053 return true;
6054}
6055
e0dac65e
WF		 6056static void g4x_write_eld(struct drm_connector *connector,
6057 struct drm_crtc *crtc)
6058{
6059 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6060 uint8_t *eld = connector->eld;
6061 uint32_t eldv;
6062 uint32_t len;
6063 uint32_t i;
6064
6065 i = I915_READ(G4X_AUD_VID_DID);
6066
6067 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6068 eldv = G4X_ELDV_DEVCL_DEVBLC;
6069 else
6070 eldv = G4X_ELDV_DEVCTG;
6071
3a9627f4
WF		 6072 if (intel_eld_uptodate(connector,
6073 G4X_AUD_CNTL_ST, eldv,
6074 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6075 G4X_HDMIW_HDMIEDID))
6076 return;
6077
e0dac65e
WF		 6078 i = I915_READ(G4X_AUD_CNTL_ST);
6079 i &= ~(eldv | G4X_ELD_ADDR);
6080 len = (i >> 9) & 0x1f; /* ELD buffer size */
6081 I915_WRITE(G4X_AUD_CNTL_ST, i);
6082
6083 if (!eld[0])
6084 return;
6085
6086 len = min_t(uint8_t, eld[2], len);
6087 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6088 for (i = 0; i < len; i++)
6089 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6090
6091 i = I915_READ(G4X_AUD_CNTL_ST);
6092 i |= eldv;
6093 I915_WRITE(G4X_AUD_CNTL_ST, i);
6094}
6095
83358c85
WX		 6096static void haswell_write_eld(struct drm_connector *connector,
6097 struct drm_crtc *crtc)
6098{
6099 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6100 uint8_t *eld = connector->eld;
6101 struct drm_device *dev = crtc->dev;
7b9f35a6 6102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6103 uint32_t eldv;
6104 uint32_t i;
6105 int len;
6106 int pipe = to_intel_crtc(crtc)->pipe;
6107 int tmp;
6108
6109 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6110 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6111 int aud_config = HSW_AUD_CFG(pipe);
6112 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6113
6114
6115 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6116
6117 /* Audio output enable */
6118 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6119 tmp = I915_READ(aud_cntrl_st2);
6120 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6121 I915_WRITE(aud_cntrl_st2, tmp);
6122
6123 /* Wait for 1 vertical blank */
6124 intel_wait_for_vblank(dev, pipe);
6125
6126 /* Set ELD valid state */
6127 tmp = I915_READ(aud_cntrl_st2);
6128 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6129 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6130 I915_WRITE(aud_cntrl_st2, tmp);
6131 tmp = I915_READ(aud_cntrl_st2);
6132 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6133
6134 /* Enable HDMI mode */
6135 tmp = I915_READ(aud_config);
6136 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6137 /* clear N_programing_enable and N_value_index */
6138 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6139 I915_WRITE(aud_config, tmp);
6140
6141 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6142
6143 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6144 intel_crtc->eld_vld = true;
83358c85
WX		 6145
6146 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6147 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6148 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6149 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6150 } else
6151 I915_WRITE(aud_config, 0);
6152
6153 if (intel_eld_uptodate(connector,
6154 aud_cntrl_st2, eldv,
6155 aud_cntl_st, IBX_ELD_ADDRESS,
6156 hdmiw_hdmiedid))
6157 return;
6158
6159 i = I915_READ(aud_cntrl_st2);
6160 i &= ~eldv;
6161 I915_WRITE(aud_cntrl_st2, i);
6162
6163 if (!eld[0])
6164 return;
6165
6166 i = I915_READ(aud_cntl_st);
6167 i &= ~IBX_ELD_ADDRESS;
6168 I915_WRITE(aud_cntl_st, i);
6169 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6170 DRM_DEBUG_DRIVER("port num:%d\n", i);
6171
6172 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6173 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6174 for (i = 0; i < len; i++)
6175 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6176
6177 i = I915_READ(aud_cntrl_st2);
6178 i |= eldv;
6179 I915_WRITE(aud_cntrl_st2, i);
6180
6181}
6182
e0dac65e
WF		 6183static void ironlake_write_eld(struct drm_connector *connector,
6184 struct drm_crtc *crtc)
6185{
6186 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6187 uint8_t *eld = connector->eld;
6188 uint32_t eldv;
6189 uint32_t i;
6190 int len;
6191 int hdmiw_hdmiedid;
b6daa025 6192 int aud_config;
e0dac65e
WF		 6193 int aud_cntl_st;
6194 int aud_cntrl_st2;
9b138a83 6195 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6196
b3f33cbf 6197 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6198 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6199 aud_config = IBX_AUD_CFG(pipe);
6200 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6201 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6202 } else {
9b138a83
WX		 6203 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6204 aud_config = CPT_AUD_CFG(pipe);
6205 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6206 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6207 }
6208
9b138a83 6209 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6210
6211 i = I915_READ(aud_cntl_st);
9b138a83 6212 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6213 if (!i) {
6214 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6215 /* operate blindly on all ports */
1202b4c6
WF		 6216 eldv = IBX_ELD_VALIDB;
6217 eldv |= IBX_ELD_VALIDB << 4;
6218 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6219 } else {
2582a850 6220 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6221 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6222 }
6223
3a9627f4
WF		 6224 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6225 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6226 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6227 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6228 } else
6229 I915_WRITE(aud_config, 0);
e0dac65e 6230
3a9627f4
WF		 6231 if (intel_eld_uptodate(connector,
6232 aud_cntrl_st2, eldv,
6233 aud_cntl_st, IBX_ELD_ADDRESS,
6234 hdmiw_hdmiedid))
6235 return;
6236
e0dac65e
WF		 6237 i = I915_READ(aud_cntrl_st2);
6238 i &= ~eldv;
6239 I915_WRITE(aud_cntrl_st2, i);
6240
6241 if (!eld[0])
6242 return;
6243
e0dac65e 6244 i = I915_READ(aud_cntl_st);
1202b4c6 6245 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6246 I915_WRITE(aud_cntl_st, i);
6247
6248 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6249 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6250 for (i = 0; i < len; i++)
6251 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6252
6253 i = I915_READ(aud_cntrl_st2);
6254 i |= eldv;
6255 I915_WRITE(aud_cntrl_st2, i);
6256}
6257
6258void intel_write_eld(struct drm_encoder *encoder,
6259 struct drm_display_mode *mode)
6260{
6261 struct drm_crtc *crtc = encoder->crtc;
6262 struct drm_connector *connector;
6263 struct drm_device *dev = encoder->dev;
6264 struct drm_i915_private *dev_priv = dev->dev_private;
6265
6266 connector = drm_select_eld(encoder, mode);
6267 if (!connector)
6268 return;
6269
6270 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6271 connector->base.id,
6272 drm_get_connector_name(connector),
6273 connector->encoder->base.id,
6274 drm_get_encoder_name(connector->encoder));
6275
6276 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6277
6278 if (dev_priv->display.write_eld)
6279 dev_priv->display.write_eld(connector, crtc);
6280}
6281
79e53945
JB		 6282/** Loads the palette/gamma unit for the CRTC with the prepared values */
6283void intel_crtc_load_lut(struct drm_crtc *crtc)
6284{
6285 struct drm_device *dev = crtc->dev;
6286 struct drm_i915_private *dev_priv = dev->dev_private;
6287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6288 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6289 int i;
6290
6291 /* The clocks have to be on to load the palette. */
aed3f09d 6292 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6293 return;
6294
f2b115e6 6295 /* use legacy palette for Ironlake */
bad720ff 6296 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6297 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6298
79e53945
JB		 6299 for (i = 0; i < 256; i++) {
6300 I915_WRITE(palreg + 4 * i,
6301 (intel_crtc->lut_r[i] << 16) |
6302 (intel_crtc->lut_g[i] << 8) |
6303 intel_crtc->lut_b[i]);
6304 }
6305}
6306
560b85bb
CW		 6307static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6308{
6309 struct drm_device *dev = crtc->dev;
6310 struct drm_i915_private *dev_priv = dev->dev_private;
6311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6312 bool visible = base != 0;
6313 u32 cntl;
6314
6315 if (intel_crtc->cursor_visible == visible)
6316 return;
6317
9db4a9c7 6318 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6319 if (visible) {
6320 /* On these chipsets we can only modify the base whilst
6321 * the cursor is disabled.
6322 */
9db4a9c7 6323 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6324
6325 cntl &= ~(CURSOR_FORMAT_MASK);
6326 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6327 cntl |= CURSOR_ENABLE |
6328 CURSOR_GAMMA_ENABLE |
6329 CURSOR_FORMAT_ARGB;
6330 } else
6331 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6332 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6333
6334 intel_crtc->cursor_visible = visible;
6335}
6336
6337static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6338{
6339 struct drm_device *dev = crtc->dev;
6340 struct drm_i915_private *dev_priv = dev->dev_private;
6341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6342 int pipe = intel_crtc->pipe;
6343 bool visible = base != 0;
6344
6345 if (intel_crtc->cursor_visible != visible) {
548f245b 6346 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6347 if (base) {
6348 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6349 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6350 cntl |= pipe << 28; /* Connect to correct pipe */
6351 } else {
6352 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6353 cntl |= CURSOR_MODE_DISABLE;
6354 }
9db4a9c7 6355 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6356
6357 intel_crtc->cursor_visible = visible;
6358 }
6359 /* and commit changes on next vblank */
9db4a9c7 6360 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6361}
6362
65a21cd6
JB		 6363static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6364{
6365 struct drm_device *dev = crtc->dev;
6366 struct drm_i915_private *dev_priv = dev->dev_private;
6367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6368 int pipe = intel_crtc->pipe;
6369 bool visible = base != 0;
6370
6371 if (intel_crtc->cursor_visible != visible) {
6372 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6373 if (base) {
6374 cntl &= ~CURSOR_MODE;
6375 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6376 } else {
6377 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6378 cntl |= CURSOR_MODE_DISABLE;
6379 }
86d3efce
VS		 6380 if (IS_HASWELL(dev))
6381 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6382 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6383
6384 intel_crtc->cursor_visible = visible;
6385 }
6386 /* and commit changes on next vblank */
6387 I915_WRITE(CURBASE_IVB(pipe), base);
6388}
6389
cda4b7d3 6390/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6391static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6392 bool on)
cda4b7d3
CW		 6393{
6394 struct drm_device *dev = crtc->dev;
6395 struct drm_i915_private *dev_priv = dev->dev_private;
6396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6397 int pipe = intel_crtc->pipe;
6398 int x = intel_crtc->cursor_x;
6399 int y = intel_crtc->cursor_y;
560b85bb 6400 u32 base, pos;
cda4b7d3
CW		 6401 bool visible;
6402
6403 pos = 0;
6404
6b383a7f 6405 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6406 base = intel_crtc->cursor_addr;
6407 if (x > (int) crtc->fb->width)
6408 base = 0;
6409
6410 if (y > (int) crtc->fb->height)
6411 base = 0;
6412 } else
6413 base = 0;
6414
6415 if (x < 0) {
6416 if (x + intel_crtc->cursor_width < 0)
6417 base = 0;
6418
6419 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6420 x = -x;
6421 }
6422 pos |= x << CURSOR_X_SHIFT;
6423
6424 if (y < 0) {
6425 if (y + intel_crtc->cursor_height < 0)
6426 base = 0;
6427
6428 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6429 y = -y;
6430 }
6431 pos |= y << CURSOR_Y_SHIFT;
6432
6433 visible = base != 0;
560b85bb 6434 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6435 return;
6436
0cd83aa9 6437 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6438 I915_WRITE(CURPOS_IVB(pipe), pos);
6439 ivb_update_cursor(crtc, base);
6440 } else {
6441 I915_WRITE(CURPOS(pipe), pos);
6442 if (IS_845G(dev) || IS_I865G(dev))
6443 i845_update_cursor(crtc, base);
6444 else
6445 i9xx_update_cursor(crtc, base);
6446 }
cda4b7d3
CW		 6447}
6448
79e53945 6449static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6450 struct drm_file *file,
79e53945
JB		 6451 uint32_t handle,
6452 uint32_t width, uint32_t height)
6453{
6454 struct drm_device *dev = crtc->dev;
6455 struct drm_i915_private *dev_priv = dev->dev_private;
6456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6457 struct drm_i915_gem_object *obj;
cda4b7d3 6458 uint32_t addr;
3f8bc370 6459 int ret;
79e53945 6460
79e53945
JB		 6461 /* if we want to turn off the cursor ignore width and height */
6462 if (!handle) {
28c97730 6463 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6464 addr = 0;
05394f39 6465 obj = NULL;
5004417d 6466 mutex_lock(&dev->struct_mutex);
3f8bc370 6467 goto finish;
79e53945
JB		 6468 }
6469
6470 /* Currently we only support 64x64 cursors */
6471 if (width != 64 || height != 64) {
6472 DRM_ERROR("we currently only support 64x64 cursors\n");
6473 return -EINVAL;
6474 }
6475
05394f39 6476 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6477 if (&obj->base == NULL)
79e53945
JB		 6478 return -ENOENT;
6479
05394f39 6480 if (obj->base.size < width * height * 4) {
79e53945 6481 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6482 ret = -ENOMEM;
6483 goto fail;
79e53945
JB		 6484 }
6485
71acb5eb 6486 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6487 mutex_lock(&dev->struct_mutex);
b295d1b6 6488 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6489 unsigned alignment;
6490
d9e86c0e
CW		 6491 if (obj->tiling_mode) {
6492 DRM_ERROR("cursor cannot be tiled\n");
6493 ret = -EINVAL;
6494 goto fail_locked;
6495 }
6496
693db184
CW		 6497 /* Note that the w/a also requires 2 PTE of padding following
6498 * the bo. We currently fill all unused PTE with the shadow
6499 * page and so we should always have valid PTE following the
6500 * cursor preventing the VT-d warning.
6501 */
6502 alignment = 0;
6503 if (need_vtd_wa(dev))
6504 alignment = 64*1024;
6505
6506 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6507 if (ret) {
6508 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6509 goto fail_locked;
e7b526bb
CW		 6510 }
6511
d9e86c0e
CW		 6512 ret = i915_gem_object_put_fence(obj);
6513 if (ret) {
2da3b9b9 6514 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6515 goto fail_unpin;
6516 }
6517
05394f39 6518 addr = obj->gtt_offset;
71acb5eb 6519 } else {
6eeefaf3 6520 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6521 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6522 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6523 align);
71acb5eb
DA		 6524 if (ret) {
6525 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6526 goto fail_locked;
71acb5eb 6527 }
05394f39 6528 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6529 }
6530
a6c45cf0 6531 if (IS_GEN2(dev))
14b60391
JB		 6532 I915_WRITE(CURSIZE, (height << 12) | width);
6533
3f8bc370 6534 finish:
3f8bc370 6535 if (intel_crtc->cursor_bo) {
b295d1b6 6536 if (dev_priv->info->cursor_needs_physical) {
05394f39 6537 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6538 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6539 } else
6540 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6541 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6542 }
80824003 6543
7f9872e0 6544 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6545
6546 intel_crtc->cursor_addr = addr;
05394f39 6547 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6548 intel_crtc->cursor_width = width;
6549 intel_crtc->cursor_height = height;
6550
6b383a7f 6551 intel_crtc_update_cursor(crtc, true);
3f8bc370 6552
79e53945 6553 return 0;
e7b526bb 6554fail_unpin:
05394f39 6555 i915_gem_object_unpin(obj);
7f9872e0 6556fail_locked:
34b8686e 6557 mutex_unlock(&dev->struct_mutex);
bc9025bd 6558fail:
05394f39 6559 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6560 return ret;
79e53945
JB		 6561}
6562
6563static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6564{
79e53945 6565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6566
cda4b7d3
CW		 6567 intel_crtc->cursor_x = x;
6568 intel_crtc->cursor_y = y;
652c393a 6569
6b383a7f 6570 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6571
6572 return 0;
6573}
6574
6575/** Sets the color ramps on behalf of RandR */
6576void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6577 u16 blue, int regno)
6578{
6579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6580
6581 intel_crtc->lut_r[regno] = red >> 8;
6582 intel_crtc->lut_g[regno] = green >> 8;
6583 intel_crtc->lut_b[regno] = blue >> 8;
6584}
6585
b8c00ac5
DA		 6586void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6587 u16 *blue, int regno)
6588{
6589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6590
6591 *red = intel_crtc->lut_r[regno] << 8;
6592 *green = intel_crtc->lut_g[regno] << 8;
6593 *blue = intel_crtc->lut_b[regno] << 8;
6594}
6595
79e53945 6596static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6597 u16 *blue, uint32_t start, uint32_t size)
79e53945 6598{
7203425a 6599 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6601
7203425a 6602 for (i = start; i < end; i++) {
79e53945
JB		 6603 intel_crtc->lut_r[i] = red[i] >> 8;
6604 intel_crtc->lut_g[i] = green[i] >> 8;
6605 intel_crtc->lut_b[i] = blue[i] >> 8;
6606 }
6607
6608 intel_crtc_load_lut(crtc);
6609}
6610
79e53945
JB		 6611/* VESA 640x480x72Hz mode to set on the pipe */
6612static struct drm_display_mode load_detect_mode = {
6613 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6614 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6615};
6616
d2dff872
CW		 6617static struct drm_framebuffer *
6618intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6619 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6620 struct drm_i915_gem_object *obj)
6621{
6622 struct intel_framebuffer *intel_fb;
6623 int ret;
6624
6625 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6626 if (!intel_fb) {
6627 drm_gem_object_unreference_unlocked(&obj->base);
6628 return ERR_PTR(-ENOMEM);
6629 }
6630
6631 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6632 if (ret) {
6633 drm_gem_object_unreference_unlocked(&obj->base);
6634 kfree(intel_fb);
6635 return ERR_PTR(ret);
6636 }
6637
6638 return &intel_fb->base;
6639}
6640
6641static u32
6642intel_framebuffer_pitch_for_width(int width, int bpp)
6643{
6644 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6645 return ALIGN(pitch, 64);
6646}
6647
6648static u32
6649intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6650{
6651 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6652 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6653}
6654
6655static struct drm_framebuffer *
6656intel_framebuffer_create_for_mode(struct drm_device *dev,
6657 struct drm_display_mode *mode,
6658 int depth, int bpp)
6659{
6660 struct drm_i915_gem_object *obj;
0fed39bd 6661 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6662
6663 obj = i915_gem_alloc_object(dev,
6664 intel_framebuffer_size_for_mode(mode, bpp));
6665 if (obj == NULL)
6666 return ERR_PTR(-ENOMEM);
6667
6668 mode_cmd.width = mode->hdisplay;
6669 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6670 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6671 bpp);
5ca0c34a 6672 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6673
6674 return intel_framebuffer_create(dev, &mode_cmd, obj);
6675}
6676
6677static struct drm_framebuffer *
6678mode_fits_in_fbdev(struct drm_device *dev,
6679 struct drm_display_mode *mode)
6680{
6681 struct drm_i915_private *dev_priv = dev->dev_private;
6682 struct drm_i915_gem_object *obj;
6683 struct drm_framebuffer *fb;
6684
6685 if (dev_priv->fbdev == NULL)
6686 return NULL;
6687
6688 obj = dev_priv->fbdev->ifb.obj;
6689 if (obj == NULL)
6690 return NULL;
6691
6692 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6693 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6694 fb->bits_per_pixel))
d2dff872
CW		 6695 return NULL;
6696
01f2c773 6697 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6698 return NULL;
6699
6700 return fb;
6701}
6702
d2434ab7 6703bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6704 struct drm_display_mode *mode,
8261b191 6705 struct intel_load_detect_pipe *old)
79e53945
JB		 6706{
6707 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6708 struct intel_encoder *intel_encoder =
6709 intel_attached_encoder(connector);
79e53945 6710 struct drm_crtc *possible_crtc;
4ef69c7a 6711 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6712 struct drm_crtc *crtc = NULL;
6713 struct drm_device *dev = encoder->dev;
94352cf9 6714 struct drm_framebuffer *fb;
79e53945
JB		 6715 int i = -1;
6716
d2dff872
CW		 6717 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6718 connector->base.id, drm_get_connector_name(connector),
6719 encoder->base.id, drm_get_encoder_name(encoder));
6720
79e53945
JB		 6721 /*
6722 * Algorithm gets a little messy:
7a5e4805 6723 *
79e53945
JB		 6724 * - if the connector already has an assigned crtc, use it (but make
6725 * sure it's on first)
7a5e4805 6726 *
79e53945
JB		 6727 * - try to find the first unused crtc that can drive this connector,
6728 * and use that if we find one
79e53945
JB		 6729 */
6730
6731 /* See if we already have a CRTC for this connector */
6732 if (encoder->crtc) {
6733 crtc = encoder->crtc;
8261b191 6734
7b24056b
DV		 6735 mutex_lock(&crtc->mutex);
6736
24218aac 6737 old->dpms_mode = connector->dpms;
8261b191
CW		 6738 old->load_detect_temp = false;
6739
6740 /* Make sure the crtc and connector are running */
24218aac
DV		 6741 if (connector->dpms != DRM_MODE_DPMS_ON)
6742 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6743
7173188d 6744 return true;
79e53945
JB		 6745 }
6746
6747 /* Find an unused one (if possible) */
6748 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6749 i++;
6750 if (!(encoder->possible_crtcs & (1 << i)))
6751 continue;
6752 if (!possible_crtc->enabled) {
6753 crtc = possible_crtc;
6754 break;
6755 }
79e53945
JB		 6756 }
6757
6758 /*
6759 * If we didn't find an unused CRTC, don't use any.
6760 */
6761 if (!crtc) {
7173188d
CW		 6762 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6763 return false;
79e53945
JB		 6764 }
6765
7b24056b 6766 mutex_lock(&crtc->mutex);
fc303101
DV		 6767 intel_encoder->new_crtc = to_intel_crtc(crtc);
6768 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6769
6770 intel_crtc = to_intel_crtc(crtc);
24218aac 6771 old->dpms_mode = connector->dpms;
8261b191 6772 old->load_detect_temp = true;
d2dff872 6773 old->release_fb = NULL;
79e53945 6774
6492711d
CW		 6775 if (!mode)
6776 mode = &load_detect_mode;
79e53945 6777
d2dff872
CW		 6778 /* We need a framebuffer large enough to accommodate all accesses
6779 * that the plane may generate whilst we perform load detection.
6780 * We can not rely on the fbcon either being present (we get called
6781 * during its initialisation to detect all boot displays, or it may
6782 * not even exist) or that it is large enough to satisfy the
6783 * requested mode.
6784 */
94352cf9
DV		 6785 fb = mode_fits_in_fbdev(dev, mode);
6786 if (fb == NULL) {
d2dff872 6787 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6788 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6789 old->release_fb = fb;
d2dff872
CW		 6790 } else
6791 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6792 if (IS_ERR(fb)) {
d2dff872 6793 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6794 mutex_unlock(&crtc->mutex);
0e8b3d3e 6795 return false;
79e53945 6796 }
79e53945 6797
c0c36b94 6798 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6799 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6800 if (old->release_fb)
6801 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6802 mutex_unlock(&crtc->mutex);
0e8b3d3e 6803 return false;
79e53945 6804 }
7173188d 6805
79e53945 6806 /* let the connector get through one full cycle before testing */
9d0498a2 6807 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6808 return true;
79e53945
JB		 6809}
6810
d2434ab7 6811void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6812 struct intel_load_detect_pipe *old)
79e53945 6813{
d2434ab7
DV		 6814 struct intel_encoder *intel_encoder =
6815 intel_attached_encoder(connector);
4ef69c7a 6816 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6817 struct drm_crtc *crtc = encoder->crtc;
79e53945 6818
d2dff872
CW		 6819 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6820 connector->base.id, drm_get_connector_name(connector),
6821 encoder->base.id, drm_get_encoder_name(encoder));
6822
8261b191 6823 if (old->load_detect_temp) {
fc303101
DV		 6824 to_intel_connector(connector)->new_encoder = NULL;
6825 intel_encoder->new_crtc = NULL;
6826 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6827
36206361
DV		 6828 if (old->release_fb) {
6829 drm_framebuffer_unregister_private(old->release_fb);
6830 drm_framebuffer_unreference(old->release_fb);
6831 }
d2dff872 6832
67c96400 6833 mutex_unlock(&crtc->mutex);
0622a53c 6834 return;
79e53945
JB		 6835 }
6836
c751ce4f 6837 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6838 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6839 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6840
6841 mutex_unlock(&crtc->mutex);
79e53945
JB		 6842}
6843
6844/* Returns the clock of the currently programmed mode of the given pipe. */
6845static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6846{
6847 struct drm_i915_private *dev_priv = dev->dev_private;
6848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6849 int pipe = intel_crtc->pipe;
548f245b 6850 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6851 u32 fp;
6852 intel_clock_t clock;
6853
6854 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6855 fp = I915_READ(FP0(pipe));
79e53945 6856 else
39adb7a5 6857 fp = I915_READ(FP1(pipe));
79e53945
JB		 6858
6859 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6860 if (IS_PINEVIEW(dev)) {
6861 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6862 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6863 } else {
6864 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6865 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6866 }
6867
a6c45cf0 6868 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6869 if (IS_PINEVIEW(dev))
6870 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6871 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6872 else
6873 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6874 DPLL_FPA01_P1_POST_DIV_SHIFT);
6875
6876 switch (dpll & DPLL_MODE_MASK) {
6877 case DPLLB_MODE_DAC_SERIAL:
6878 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6879 5 : 10;
6880 break;
6881 case DPLLB_MODE_LVDS:
6882 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6883 7 : 14;
6884 break;
6885 default:
28c97730 6886 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6887 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6888 return 0;
6889 }
6890
6891 /* XXX: Handle the 100Mhz refclk */
2177832f 6892 intel_clock(dev, 96000, &clock);
79e53945
JB		 6893 } else {
6894 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6895
6896 if (is_lvds) {
6897 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6898 DPLL_FPA01_P1_POST_DIV_SHIFT);
6899 clock.p2 = 14;
6900
6901 if ((dpll & PLL_REF_INPUT_MASK) ==
6902 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6903 /* XXX: might not be 66MHz */
2177832f 6904 intel_clock(dev, 66000, &clock);
79e53945 6905 } else
2177832f 6906 intel_clock(dev, 48000, &clock);
79e53945
JB		 6907 } else {
6908 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6909 clock.p1 = 2;
6910 else {
6911 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6912 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6913 }
6914 if (dpll & PLL_P2_DIVIDE_BY_4)
6915 clock.p2 = 4;
6916 else
6917 clock.p2 = 2;
6918
2177832f 6919 intel_clock(dev, 48000, &clock);
79e53945
JB		 6920 }
6921 }
6922
6923 /* XXX: It would be nice to validate the clocks, but we can't reuse
6924 * i830PllIsValid() because it relies on the xf86_config connector
6925 * configuration being accurate, which it isn't necessarily.
6926 */
6927
6928 return clock.dot;
6929}
6930
6931/** Returns the currently programmed mode of the given pipe. */
6932struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6933 struct drm_crtc *crtc)
6934{
548f245b 6935 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6937 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6938 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6939 int htot = I915_READ(HTOTAL(cpu_transcoder));
6940 int hsync = I915_READ(HSYNC(cpu_transcoder));
6941 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6942 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6943
6944 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6945 if (!mode)
6946 return NULL;
6947
6948 mode->clock = intel_crtc_clock_get(dev, crtc);
6949 mode->hdisplay = (htot & 0xffff) + 1;
6950 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6951 mode->hsync_start = (hsync & 0xffff) + 1;
6952 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6953 mode->vdisplay = (vtot & 0xffff) + 1;
6954 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6955 mode->vsync_start = (vsync & 0xffff) + 1;
6956 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6957
6958 drm_mode_set_name(mode);
79e53945
JB		 6959
6960 return mode;
6961}
6962
3dec0095 6963static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6964{
6965 struct drm_device *dev = crtc->dev;
6966 drm_i915_private_t *dev_priv = dev->dev_private;
6967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6968 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6969 int dpll_reg = DPLL(pipe);
6970 int dpll;
652c393a 6971
bad720ff 6972 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6973 return;
6974
6975 if (!dev_priv->lvds_downclock_avail)
6976 return;
6977
dbdc6479 6978 dpll = I915_READ(dpll_reg);
652c393a 6979 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6980 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6981
8ac5a6d5 6982 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6983
6984 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6985 I915_WRITE(dpll_reg, dpll);
9d0498a2 6986 intel_wait_for_vblank(dev, pipe);
dbdc6479 6987
652c393a
JB		 6988 dpll = I915_READ(dpll_reg);
6989 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6990 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6991 }
652c393a
JB		 6992}
6993
6994static void intel_decrease_pllclock(struct drm_crtc *crtc)
6995{
6996 struct drm_device *dev = crtc->dev;
6997 drm_i915_private_t *dev_priv = dev->dev_private;
6998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6999
bad720ff 7000 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7001 return;
7002
7003 if (!dev_priv->lvds_downclock_avail)
7004 return;
7005
7006 /*
7007 * Since this is called by a timer, we should never get here in
7008 * the manual case.
7009 */
7010 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7011 int pipe = intel_crtc->pipe;
7012 int dpll_reg = DPLL(pipe);
7013 int dpll;
f6e5b160 7014
44d98a61 7015 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7016
8ac5a6d5 7017 assert_panel_unlocked(dev_priv, pipe);
652c393a 7018
dc257cf1 7019 dpll = I915_READ(dpll_reg);
652c393a
JB		 7020 dpll |= DISPLAY_RATE_SELECT_FPA1;
7021 I915_WRITE(dpll_reg, dpll);
9d0498a2 7022 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7023 dpll = I915_READ(dpll_reg);
7024 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7025 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7026 }
7027
7028}
7029
f047e395
CW		 7030void intel_mark_busy(struct drm_device *dev)
7031{
f047e395
CW		 7032 i915_update_gfx_val(dev->dev_private);
7033}
7034
7035void intel_mark_idle(struct drm_device *dev)
652c393a 7036{
652c393a 7037 struct drm_crtc *crtc;
652c393a
JB		 7038
7039 if (!i915_powersave)
7040 return;
7041
652c393a 7042 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7043 if (!crtc->fb)
7044 continue;
7045
725a5b54 7046 intel_decrease_pllclock(crtc);
652c393a 7047 }
652c393a
JB		 7048}
7049
725a5b54 7050void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 7051{
f047e395
CW		 7052 struct drm_device *dev = obj->base.dev;
7053 struct drm_crtc *crtc;
652c393a 7054
f047e395 7055 if (!i915_powersave)
acb87dfb
CW		 7056 return;
7057
652c393a
JB		 7058 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7059 if (!crtc->fb)
7060 continue;
7061
f047e395 7062 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7063 intel_increase_pllclock(crtc);
652c393a
JB		 7064 }
7065}
7066
79e53945
JB		 7067static void intel_crtc_destroy(struct drm_crtc *crtc)
7068{
7069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7070 struct drm_device *dev = crtc->dev;
7071 struct intel_unpin_work *work;
7072 unsigned long flags;
7073
7074 spin_lock_irqsave(&dev->event_lock, flags);
7075 work = intel_crtc->unpin_work;
7076 intel_crtc->unpin_work = NULL;
7077 spin_unlock_irqrestore(&dev->event_lock, flags);
7078
7079 if (work) {
7080 cancel_work_sync(&work->work);
7081 kfree(work);
7082 }
79e53945
JB		 7083
7084 drm_crtc_cleanup(crtc);
67e77c5a 7085
79e53945
JB		 7086 kfree(intel_crtc);
7087}
7088
6b95a207
KH		 7089static void intel_unpin_work_fn(struct work_struct *__work)
7090{
7091 struct intel_unpin_work *work =
7092 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7093 struct drm_device *dev = work->crtc->dev;
6b95a207 7094
b4a98e57 7095 mutex_lock(&dev->struct_mutex);
1690e1eb 7096 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7097 drm_gem_object_unreference(&work->pending_flip_obj->base);
7098 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7099
b4a98e57
CW		 7100 intel_update_fbc(dev);
7101 mutex_unlock(&dev->struct_mutex);
7102
7103 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7104 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7105
6b95a207
KH		 7106 kfree(work);
7107}
7108
1afe3e9d 7109static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7110 struct drm_crtc *crtc)
6b95a207
KH		 7111{
7112 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7114 struct intel_unpin_work *work;
6b95a207
KH		 7115 unsigned long flags;
7116
7117 /* Ignore early vblank irqs */
7118 if (intel_crtc == NULL)
7119 return;
7120
7121 spin_lock_irqsave(&dev->event_lock, flags);
7122 work = intel_crtc->unpin_work;
e7d841ca
CW		 7123
7124 /* Ensure we don't miss a work->pending update ... */
7125 smp_rmb();
7126
7127 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7128 spin_unlock_irqrestore(&dev->event_lock, flags);
7129 return;
7130 }
7131
e7d841ca
CW		 7132 /* and that the unpin work is consistent wrt ->pending. */
7133 smp_rmb();
7134
6b95a207 7135 intel_crtc->unpin_work = NULL;
6b95a207 7136
45a066eb
RC		 7137 if (work->event)
7138 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7139
0af7e4df
MK		 7140 drm_vblank_put(dev, intel_crtc->pipe);
7141
6b95a207
KH		 7142 spin_unlock_irqrestore(&dev->event_lock, flags);
7143
2c10d571 7144 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7145
7146 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7147
7148 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7149}
7150
1afe3e9d
JB		 7151void intel_finish_page_flip(struct drm_device *dev, int pipe)
7152{
7153 drm_i915_private_t *dev_priv = dev->dev_private;
7154 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7155
49b14a5c 7156 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7157}
7158
7159void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7160{
7161 drm_i915_private_t *dev_priv = dev->dev_private;
7162 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7163
49b14a5c 7164 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7165}
7166
6b95a207
KH		 7167void intel_prepare_page_flip(struct drm_device *dev, int plane)
7168{
7169 drm_i915_private_t *dev_priv = dev->dev_private;
7170 struct intel_crtc *intel_crtc =
7171 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7172 unsigned long flags;
7173
e7d841ca
CW		 7174 /* NB: An MMIO update of the plane base pointer will also
7175 * generate a page-flip completion irq, i.e. every modeset
7176 * is also accompanied by a spurious intel_prepare_page_flip().
7177 */
6b95a207 7178 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7179 if (intel_crtc->unpin_work)
7180 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7181 spin_unlock_irqrestore(&dev->event_lock, flags);
7182}
7183
e7d841ca
CW		 7184inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7185{
7186 /* Ensure that the work item is consistent when activating it ... */
7187 smp_wmb();
7188 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7189 /* and that it is marked active as soon as the irq could fire. */
7190 smp_wmb();
7191}
7192
8c9f3aaf
JB		 7193static int intel_gen2_queue_flip(struct drm_device *dev,
7194 struct drm_crtc *crtc,
7195 struct drm_framebuffer *fb,
7196 struct drm_i915_gem_object *obj)
7197{
7198 struct drm_i915_private *dev_priv = dev->dev_private;
7199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7200 u32 flip_mask;
6d90c952 7201 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7202 int ret;
7203
6d90c952 7204 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7205 if (ret)
83d4092b 7206 goto err;
8c9f3aaf 7207
6d90c952 7208 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7209 if (ret)
83d4092b 7210 goto err_unpin;
8c9f3aaf
JB		 7211
7212 /* Can't queue multiple flips, so wait for the previous
7213 * one to finish before executing the next.
7214 */
7215 if (intel_crtc->plane)
7216 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7217 else
7218 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7219 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7220 intel_ring_emit(ring, MI_NOOP);
7221 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7222 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7223 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7224 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7225 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7226
7227 intel_mark_page_flip_active(intel_crtc);
6d90c952 7228 intel_ring_advance(ring);
83d4092b
CW		 7229 return 0;
7230
7231err_unpin:
7232 intel_unpin_fb_obj(obj);
7233err:
8c9f3aaf
JB		 7234 return ret;
7235}
7236
7237static int intel_gen3_queue_flip(struct drm_device *dev,
7238 struct drm_crtc *crtc,
7239 struct drm_framebuffer *fb,
7240 struct drm_i915_gem_object *obj)
7241{
7242 struct drm_i915_private *dev_priv = dev->dev_private;
7243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7244 u32 flip_mask;
6d90c952 7245 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7246 int ret;
7247
6d90c952 7248 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7249 if (ret)
83d4092b 7250 goto err;
8c9f3aaf 7251
6d90c952 7252 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7253 if (ret)
83d4092b 7254 goto err_unpin;
8c9f3aaf
JB		 7255
7256 if (intel_crtc->plane)
7257 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7258 else
7259 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7260 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7261 intel_ring_emit(ring, MI_NOOP);
7262 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7263 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7264 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7265 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7266 intel_ring_emit(ring, MI_NOOP);
7267
e7d841ca 7268 intel_mark_page_flip_active(intel_crtc);
6d90c952 7269 intel_ring_advance(ring);
83d4092b
CW		 7270 return 0;
7271
7272err_unpin:
7273 intel_unpin_fb_obj(obj);
7274err:
8c9f3aaf
JB		 7275 return ret;
7276}
7277
7278static int intel_gen4_queue_flip(struct drm_device *dev,
7279 struct drm_crtc *crtc,
7280 struct drm_framebuffer *fb,
7281 struct drm_i915_gem_object *obj)
7282{
7283 struct drm_i915_private *dev_priv = dev->dev_private;
7284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7285 uint32_t pf, pipesrc;
6d90c952 7286 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7287 int ret;
7288
6d90c952 7289 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7290 if (ret)
83d4092b 7291 goto err;
8c9f3aaf 7292
6d90c952 7293 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7294 if (ret)
83d4092b 7295 goto err_unpin;
8c9f3aaf
JB		 7296
7297 /* i965+ uses the linear or tiled offsets from the
7298 * Display Registers (which do not change across a page-flip)
7299 * so we need only reprogram the base address.
7300 */
6d90c952
DV		 7301 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7302 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7303 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7304 intel_ring_emit(ring,
7305 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7306 obj->tiling_mode);
8c9f3aaf
JB		 7307
7308 /* XXX Enabling the panel-fitter across page-flip is so far
7309 * untested on non-native modes, so ignore it for now.
7310 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7311 */
7312 pf = 0;
7313 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7314 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7315
7316 intel_mark_page_flip_active(intel_crtc);
6d90c952 7317 intel_ring_advance(ring);
83d4092b
CW		 7318 return 0;
7319
7320err_unpin:
7321 intel_unpin_fb_obj(obj);
7322err:
8c9f3aaf
JB		 7323 return ret;
7324}
7325
7326static int intel_gen6_queue_flip(struct drm_device *dev,
7327 struct drm_crtc *crtc,
7328 struct drm_framebuffer *fb,
7329 struct drm_i915_gem_object *obj)
7330{
7331 struct drm_i915_private *dev_priv = dev->dev_private;
7332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7333 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7334 uint32_t pf, pipesrc;
7335 int ret;
7336
6d90c952 7337 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7338 if (ret)
83d4092b 7339 goto err;
8c9f3aaf 7340
6d90c952 7341 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7342 if (ret)
83d4092b 7343 goto err_unpin;
8c9f3aaf 7344
6d90c952
DV		 7345 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7346 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7347 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7348 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7349
dc257cf1
DV		 7350 /* Contrary to the suggestions in the documentation,
7351 * "Enable Panel Fitter" does not seem to be required when page
7352 * flipping with a non-native mode, and worse causes a normal
7353 * modeset to fail.
7354 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7355 */
7356 pf = 0;
8c9f3aaf 7357 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7358 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7359
7360 intel_mark_page_flip_active(intel_crtc);
6d90c952 7361 intel_ring_advance(ring);
83d4092b
CW		 7362 return 0;
7363
7364err_unpin:
7365 intel_unpin_fb_obj(obj);
7366err:
8c9f3aaf
JB		 7367 return ret;
7368}
7369
7c9017e5
JB		 7370/*
7371 * On gen7 we currently use the blit ring because (in early silicon at least)
7372 * the render ring doesn't give us interrpts for page flip completion, which
7373 * means clients will hang after the first flip is queued. Fortunately the
7374 * blit ring generates interrupts properly, so use it instead.
7375 */
7376static int intel_gen7_queue_flip(struct drm_device *dev,
7377 struct drm_crtc *crtc,
7378 struct drm_framebuffer *fb,
7379 struct drm_i915_gem_object *obj)
7380{
7381 struct drm_i915_private *dev_priv = dev->dev_private;
7382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7383 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7384 uint32_t plane_bit = 0;
7c9017e5
JB		 7385 int ret;
7386
7387 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7388 if (ret)
83d4092b 7389 goto err;
7c9017e5 7390
cb05d8de
DV		 7391 switch(intel_crtc->plane) {
7392 case PLANE_A:
7393 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7394 break;
7395 case PLANE_B:
7396 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7397 break;
7398 case PLANE_C:
7399 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7400 break;
7401 default:
7402 WARN_ONCE(1, "unknown plane in flip command\n");
7403 ret = -ENODEV;
ab3951eb 7404 goto err_unpin;
cb05d8de
DV		 7405 }
7406
7c9017e5
JB		 7407 ret = intel_ring_begin(ring, 4);
7408 if (ret)
83d4092b 7409 goto err_unpin;
7c9017e5 7410
cb05d8de 7411 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7412 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7413 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7414 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7415
7416 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7417 intel_ring_advance(ring);
83d4092b
CW		 7418 return 0;
7419
7420err_unpin:
7421 intel_unpin_fb_obj(obj);
7422err:
7c9017e5
JB		 7423 return ret;
7424}
7425
8c9f3aaf
JB		 7426static int intel_default_queue_flip(struct drm_device *dev,
7427 struct drm_crtc *crtc,
7428 struct drm_framebuffer *fb,
7429 struct drm_i915_gem_object *obj)
7430{
7431 return -ENODEV;
7432}
7433
6b95a207
KH		 7434static int intel_crtc_page_flip(struct drm_crtc *crtc,
7435 struct drm_framebuffer *fb,
7436 struct drm_pending_vblank_event *event)
7437{
7438 struct drm_device *dev = crtc->dev;
7439 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7440 struct drm_framebuffer *old_fb = crtc->fb;
7441 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7443 struct intel_unpin_work *work;
8c9f3aaf 7444 unsigned long flags;
52e68630 7445 int ret;
6b95a207 7446
e6a595d2
VS		 7447 /* Can't change pixel format via MI display flips. */
7448 if (fb->pixel_format != crtc->fb->pixel_format)
7449 return -EINVAL;
7450
7451 /*
7452 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7453 * Note that pitch changes could also affect these register.
7454 */
7455 if (INTEL_INFO(dev)->gen > 3 &&
7456 (fb->offsets[0] != crtc->fb->offsets[0] ||
7457 fb->pitches[0] != crtc->fb->pitches[0]))
7458 return -EINVAL;
7459
6b95a207
KH		 7460 work = kzalloc(sizeof *work, GFP_KERNEL);
7461 if (work == NULL)
7462 return -ENOMEM;
7463
6b95a207 7464 work->event = event;
b4a98e57 7465 work->crtc = crtc;
4a35f83b 7466 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7467 INIT_WORK(&work->work, intel_unpin_work_fn);
7468
7317c75e
JB		 7469 ret = drm_vblank_get(dev, intel_crtc->pipe);
7470 if (ret)
7471 goto free_work;
7472
6b95a207
KH		 7473 /* We borrow the event spin lock for protecting unpin_work */
7474 spin_lock_irqsave(&dev->event_lock, flags);
7475 if (intel_crtc->unpin_work) {
7476 spin_unlock_irqrestore(&dev->event_lock, flags);
7477 kfree(work);
7317c75e 7478 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7479
7480 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7481 return -EBUSY;
7482 }
7483 intel_crtc->unpin_work = work;
7484 spin_unlock_irqrestore(&dev->event_lock, flags);
7485
b4a98e57
CW		 7486 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7487 flush_workqueue(dev_priv->wq);
7488
79158103
CW		 7489 ret = i915_mutex_lock_interruptible(dev);
7490 if (ret)
7491 goto cleanup;
6b95a207 7492
75dfca80 7493 /* Reference the objects for the scheduled work. */
05394f39
CW		 7494 drm_gem_object_reference(&work->old_fb_obj->base);
7495 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7496
7497 crtc->fb = fb;
96b099fd 7498
e1f99ce6 7499 work->pending_flip_obj = obj;
e1f99ce6 7500
4e5359cd
SF		 7501 work->enable_stall_check = true;
7502
b4a98e57 7503 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7504 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7505
8c9f3aaf
JB		 7506 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7507 if (ret)
7508 goto cleanup_pending;
6b95a207 7509
7782de3b 7510 intel_disable_fbc(dev);
f047e395 7511 intel_mark_fb_busy(obj);
6b95a207
KH		 7512 mutex_unlock(&dev->struct_mutex);
7513
e5510fac
JB		 7514 trace_i915_flip_request(intel_crtc->plane, obj);
7515
6b95a207 7516 return 0;
96b099fd 7517
8c9f3aaf 7518cleanup_pending:
b4a98e57 7519 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7520 crtc->fb = old_fb;
05394f39
CW		 7521 drm_gem_object_unreference(&work->old_fb_obj->base);
7522 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7523 mutex_unlock(&dev->struct_mutex);
7524
79158103 7525cleanup:
96b099fd
CW		 7526 spin_lock_irqsave(&dev->event_lock, flags);
7527 intel_crtc->unpin_work = NULL;
7528 spin_unlock_irqrestore(&dev->event_lock, flags);
7529
7317c75e
JB		 7530 drm_vblank_put(dev, intel_crtc->pipe);
7531free_work:
96b099fd
CW		 7532 kfree(work);
7533
7534 return ret;
6b95a207
KH		 7535}
7536
f6e5b160 7537static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7538 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7539 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7540};
7541
6ed0f796 7542bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7543{
6ed0f796
DV		 7544 struct intel_encoder *other_encoder;
7545 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7546
6ed0f796
DV		 7547 if (WARN_ON(!crtc))
7548 return false;
7549
7550 list_for_each_entry(other_encoder,
7551 &crtc->dev->mode_config.encoder_list,
7552 base.head) {
7553
7554 if (&other_encoder->new_crtc->base != crtc ||
7555 encoder == other_encoder)
7556 continue;
7557 else
7558 return true;
f47166d2
CW		 7559 }
7560
6ed0f796
DV		 7561 return false;
7562}
47f1c6c9 7563
50f56119
DV		 7564static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7565 struct drm_crtc *crtc)
7566{
7567 struct drm_device *dev;
7568 struct drm_crtc *tmp;
7569 int crtc_mask = 1;
47f1c6c9 7570
50f56119 7571 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7572
50f56119 7573 dev = crtc->dev;
47f1c6c9 7574
50f56119
DV		 7575 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7576 if (tmp == crtc)
7577 break;
7578 crtc_mask <<= 1;
7579 }
47f1c6c9 7580
50f56119
DV		 7581 if (encoder->possible_crtcs & crtc_mask)
7582 return true;
7583 return false;
47f1c6c9 7584}
79e53945 7585
9a935856
DV		 7586/**
7587 * intel_modeset_update_staged_output_state
7588 *
7589 * Updates the staged output configuration state, e.g. after we've read out the
7590 * current hw state.
7591 */
7592static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7593{
9a935856
DV		 7594 struct intel_encoder *encoder;
7595 struct intel_connector *connector;
f6e5b160 7596
9a935856
DV		 7597 list_for_each_entry(connector, &dev->mode_config.connector_list,
7598 base.head) {
7599 connector->new_encoder =
7600 to_intel_encoder(connector->base.encoder);
7601 }
f6e5b160 7602
9a935856
DV		 7603 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7604 base.head) {
7605 encoder->new_crtc =
7606 to_intel_crtc(encoder->base.crtc);
7607 }
f6e5b160
CW		 7608}
7609
9a935856
DV		 7610/**
7611 * intel_modeset_commit_output_state
7612 *
7613 * This function copies the stage display pipe configuration to the real one.
7614 */
7615static void intel_modeset_commit_output_state(struct drm_device *dev)
7616{
7617 struct intel_encoder *encoder;
7618 struct intel_connector *connector;
f6e5b160 7619
9a935856
DV		 7620 list_for_each_entry(connector, &dev->mode_config.connector_list,
7621 base.head) {
7622 connector->base.encoder = &connector->new_encoder->base;
7623 }
f6e5b160 7624
9a935856
DV		 7625 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7626 base.head) {
7627 encoder->base.crtc = &encoder->new_crtc->base;
7628 }
7629}
7630
4e53c2e0
DV		 7631static int
7632pipe_config_set_bpp(struct drm_crtc *crtc,
7633 struct drm_framebuffer *fb,
7634 struct intel_crtc_config *pipe_config)
7635{
7636 struct drm_device *dev = crtc->dev;
7637 struct drm_connector *connector;
7638 int bpp;
7639
d42264b1
DV		 7640 switch (fb->pixel_format) {
7641 case DRM_FORMAT_C8:
4e53c2e0
DV		 7642 bpp = 8*3; /* since we go through a colormap */
7643 break;
d42264b1
DV		 7644 case DRM_FORMAT_XRGB1555:
7645 case DRM_FORMAT_ARGB1555:
7646 /* checked in intel_framebuffer_init already */
7647 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7648 return -EINVAL;
7649 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7650 bpp = 6*3; /* min is 18bpp */
7651 break;
d42264b1
DV		 7652 case DRM_FORMAT_XBGR8888:
7653 case DRM_FORMAT_ABGR8888:
7654 /* checked in intel_framebuffer_init already */
7655 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7656 return -EINVAL;
7657 case DRM_FORMAT_XRGB8888:
7658 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7659 bpp = 8*3;
7660 break;
d42264b1
DV		 7661 case DRM_FORMAT_XRGB2101010:
7662 case DRM_FORMAT_ARGB2101010:
7663 case DRM_FORMAT_XBGR2101010:
7664 case DRM_FORMAT_ABGR2101010:
7665 /* checked in intel_framebuffer_init already */
7666 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7667 return -EINVAL;
4e53c2e0
DV		 7668 bpp = 10*3;
7669 break;
baba133a 7670 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7671 default:
7672 DRM_DEBUG_KMS("unsupported depth\n");
7673 return -EINVAL;
7674 }
7675
4e53c2e0
DV		 7676 pipe_config->pipe_bpp = bpp;
7677
7678 /* Clamp display bpp to EDID value */
7679 list_for_each_entry(connector, &dev->mode_config.connector_list,
7680 head) {
7681 if (connector->encoder && connector->encoder->crtc != crtc)
7682 continue;
7683
7684 /* Don't use an invalid EDID bpc value */
7685 if (connector->display_info.bpc &&
7686 connector->display_info.bpc * 3 < bpp) {
7687 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7688 bpp, connector->display_info.bpc*3);
7689 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7690 }
996a2239
DV		 7691
7692 /* Clamp bpp to 8 on screens without EDID 1.4 */
7693 if (connector->display_info.bpc == 0 && bpp > 24) {
7694 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7695 bpp);
7696 pipe_config->pipe_bpp = 24;
7697 }
4e53c2e0
DV		 7698 }
7699
7700 return bpp;
7701}
7702
b8cecdf5
DV		 7703static struct intel_crtc_config *
7704intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7705 struct drm_framebuffer *fb,
b8cecdf5 7706 struct drm_display_mode *mode)
ee7b9f93 7707{
7758a113 7708 struct drm_device *dev = crtc->dev;
7758a113
DV		 7709 struct drm_encoder_helper_funcs *encoder_funcs;
7710 struct intel_encoder *encoder;
b8cecdf5 7711 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7712 int plane_bpp, ret = -EINVAL;
7713 bool retry = true;
ee7b9f93 7714
b8cecdf5
DV		 7715 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7716 if (!pipe_config)
7758a113
DV		 7717 return ERR_PTR(-ENOMEM);
7718
b8cecdf5
DV		 7719 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7720 drm_mode_copy(&pipe_config->requested_mode, mode);
7721
4e53c2e0
DV		 7722 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7723 if (plane_bpp < 0)
7724 goto fail;
7725
e29c22c0 7726encoder_retry:
7758a113
DV		 7727 /* Pass our mode to the connectors and the CRTC to give them a chance to
7728 * adjust it according to limitations or connector properties, and also
7729 * a chance to reject the mode entirely.
47f1c6c9 7730 */
7758a113
DV		 7731 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7732 base.head) {
47f1c6c9 7733
7758a113
DV		 7734 if (&encoder->new_crtc->base != crtc)
7735 continue;
7ae89233
DV		 7736
7737 if (encoder->compute_config) {
7738 if (!(encoder->compute_config(encoder, pipe_config))) {
7739 DRM_DEBUG_KMS("Encoder config failure\n");
7740 goto fail;
7741 }
7742
7743 continue;
7744 }
7745
7758a113 7746 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7747 if (!(encoder_funcs->mode_fixup(&encoder->base,
7748 &pipe_config->requested_mode,
7749 &pipe_config->adjusted_mode))) {
7758a113
DV		 7750 DRM_DEBUG_KMS("Encoder fixup failed\n");
7751 goto fail;
7752 }
ee7b9f93 7753 }
47f1c6c9 7754
e29c22c0
DV		 7755 ret = intel_crtc_compute_config(crtc, pipe_config);
7756 if (ret < 0) {
7758a113
DV		 7757 DRM_DEBUG_KMS("CRTC fixup failed\n");
7758 goto fail;
ee7b9f93 7759 }
e29c22c0
DV		 7760
7761 if (ret == RETRY) {
7762 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7763 ret = -EINVAL;
7764 goto fail;
7765 }
7766
7767 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7768 retry = false;
7769 goto encoder_retry;
7770 }
7771
7758a113 7772 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7773
4e53c2e0
DV		 7774 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7775 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7776 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7777
b8cecdf5 7778 return pipe_config;
7758a113 7779fail:
b8cecdf5 7780 kfree(pipe_config);
e29c22c0 7781 return ERR_PTR(ret);
ee7b9f93 7782}
47f1c6c9 7783
e2e1ed41
DV		 7784/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7785 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7786static void
7787intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7788 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7789{
7790 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7791 struct drm_device *dev = crtc->dev;
7792 struct intel_encoder *encoder;
7793 struct intel_connector *connector;
7794 struct drm_crtc *tmp_crtc;
79e53945 7795
e2e1ed41 7796 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7797
e2e1ed41
DV		 7798 /* Check which crtcs have changed outputs connected to them, these need
7799 * to be part of the prepare_pipes mask. We don't (yet) support global
7800 * modeset across multiple crtcs, so modeset_pipes will only have one
7801 * bit set at most. */
7802 list_for_each_entry(connector, &dev->mode_config.connector_list,
7803 base.head) {
7804 if (connector->base.encoder == &connector->new_encoder->base)
7805 continue;
79e53945 7806
e2e1ed41
DV		 7807 if (connector->base.encoder) {
7808 tmp_crtc = connector->base.encoder->crtc;
7809
7810 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7811 }
7812
7813 if (connector->new_encoder)
7814 *prepare_pipes |=
7815 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7816 }
7817
e2e1ed41
DV		 7818 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7819 base.head) {
7820 if (encoder->base.crtc == &encoder->new_crtc->base)
7821 continue;
7822
7823 if (encoder->base.crtc) {
7824 tmp_crtc = encoder->base.crtc;
7825
7826 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7827 }
7828
7829 if (encoder->new_crtc)
7830 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7831 }
7832
e2e1ed41
DV		 7833 /* Check for any pipes that will be fully disabled ... */
7834 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7835 base.head) {
7836 bool used = false;
22fd0fab 7837
e2e1ed41
DV		 7838 /* Don't try to disable disabled crtcs. */
7839 if (!intel_crtc->base.enabled)
7840 continue;
7e7d76c3 7841
e2e1ed41
DV		 7842 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7843 base.head) {
7844 if (encoder->new_crtc == intel_crtc)
7845 used = true;
7846 }
7847
7848 if (!used)
7849 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7850 }
7851
e2e1ed41
DV		 7852
7853 /* set_mode is also used to update properties on life display pipes. */
7854 intel_crtc = to_intel_crtc(crtc);
7855 if (crtc->enabled)
7856 *prepare_pipes |= 1 << intel_crtc->pipe;
7857
b6c5164d
DV		 7858 /*
7859 * For simplicity do a full modeset on any pipe where the output routing
7860 * changed. We could be more clever, but that would require us to be
7861 * more careful with calling the relevant encoder->mode_set functions.
7862 */
e2e1ed41
DV		 7863 if (*prepare_pipes)
7864 *modeset_pipes = *prepare_pipes;
7865
7866 /* ... and mask these out. */
7867 *modeset_pipes &= ~(*disable_pipes);
7868 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7869
7870 /*
7871 * HACK: We don't (yet) fully support global modesets. intel_set_config
7872 * obies this rule, but the modeset restore mode of
7873 * intel_modeset_setup_hw_state does not.
7874 */
7875 *modeset_pipes &= 1 << intel_crtc->pipe;
7876 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7877
7878 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7879 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7880}
79e53945 7881
ea9d758d 7882static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7883{
ea9d758d 7884 struct drm_encoder *encoder;
f6e5b160 7885 struct drm_device *dev = crtc->dev;
f6e5b160 7886
ea9d758d
DV		 7887 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7888 if (encoder->crtc == crtc)
7889 return true;
7890
7891 return false;
7892}
7893
7894static void
7895intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7896{
7897 struct intel_encoder *intel_encoder;
7898 struct intel_crtc *intel_crtc;
7899 struct drm_connector *connector;
7900
7901 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7902 base.head) {
7903 if (!intel_encoder->base.crtc)
7904 continue;
7905
7906 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7907
7908 if (prepare_pipes & (1 << intel_crtc->pipe))
7909 intel_encoder->connectors_active = false;
7910 }
7911
7912 intel_modeset_commit_output_state(dev);
7913
7914 /* Update computed state. */
7915 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7916 base.head) {
7917 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7918 }
7919
7920 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7921 if (!connector->encoder || !connector->encoder->crtc)
7922 continue;
7923
7924 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7925
7926 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7927 struct drm_property *dpms_property =
7928 dev->mode_config.dpms_property;
7929
ea9d758d 7930 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7931 drm_object_property_set_value(&connector->base,
68d34720
DV		 7932 dpms_property,
7933 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7934
7935 intel_encoder = to_intel_encoder(connector->encoder);
7936 intel_encoder->connectors_active = true;
7937 }
7938 }
7939
7940}
7941
25c5b266
DV		 7942#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7943 list_for_each_entry((intel_crtc), \
7944 &(dev)->mode_config.crtc_list, \
7945 base.head) \
0973f18f 7946 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 7947
0e8ffe1b
DV		 7948static bool
7949intel_pipe_config_compare(struct intel_crtc_config *current_config,
7950 struct intel_crtc_config *pipe_config)
7951{
88adfff1
DV		 7952 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7953 DRM_ERROR("mismatch in has_pch_encoder "
7954 "(expected %i, found %i)\n",
7955 current_config->has_pch_encoder,
7956 pipe_config->has_pch_encoder);
7957 return false;
7958 }
7959
627eb5a3
DV		 7960 if (current_config->fdi_lanes != pipe_config->fdi_lanes) {
7961 DRM_ERROR("mismatch in fdi_lanes "
7962 "(expected %i, found %i)\n",
7963 current_config->fdi_lanes,
7964 pipe_config->fdi_lanes);
7965 return false;
7966 }
7967
0e8ffe1b
DV		 7968 return true;
7969}
7970
b980514c 7971void
8af6cf88
DV		 7972intel_modeset_check_state(struct drm_device *dev)
7973{
0e8ffe1b 7974 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 7975 struct intel_crtc *crtc;
7976 struct intel_encoder *encoder;
7977 struct intel_connector *connector;
0e8ffe1b 7978 struct intel_crtc_config pipe_config;
8af6cf88
DV		 7979
7980 list_for_each_entry(connector, &dev->mode_config.connector_list,
7981 base.head) {
7982 /* This also checks the encoder/connector hw state with the
7983 * ->get_hw_state callbacks. */
7984 intel_connector_check_state(connector);
7985
7986 WARN(&connector->new_encoder->base != connector->base.encoder,
7987 "connector's staged encoder doesn't match current encoder\n");
7988 }
7989
7990 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7991 base.head) {
7992 bool enabled = false;
7993 bool active = false;
7994 enum pipe pipe, tracked_pipe;
7995
7996 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7997 encoder->base.base.id,
7998 drm_get_encoder_name(&encoder->base));
7999
8000 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8001 "encoder's stage crtc doesn't match current crtc\n");
8002 WARN(encoder->connectors_active && !encoder->base.crtc,
8003 "encoder's active_connectors set, but no crtc\n");
8004
8005 list_for_each_entry(connector, &dev->mode_config.connector_list,
8006 base.head) {
8007 if (connector->base.encoder != &encoder->base)
8008 continue;
8009 enabled = true;
8010 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8011 active = true;
8012 }
8013 WARN(!!encoder->base.crtc != enabled,
8014 "encoder's enabled state mismatch "
8015 "(expected %i, found %i)\n",
8016 !!encoder->base.crtc, enabled);
8017 WARN(active && !encoder->base.crtc,
8018 "active encoder with no crtc\n");
8019
8020 WARN(encoder->connectors_active != active,
8021 "encoder's computed active state doesn't match tracked active state "
8022 "(expected %i, found %i)\n", active, encoder->connectors_active);
8023
8024 active = encoder->get_hw_state(encoder, &pipe);
8025 WARN(active != encoder->connectors_active,
8026 "encoder's hw state doesn't match sw tracking "
8027 "(expected %i, found %i)\n",
8028 encoder->connectors_active, active);
8029
8030 if (!encoder->base.crtc)
8031 continue;
8032
8033 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8034 WARN(active && pipe != tracked_pipe,
8035 "active encoder's pipe doesn't match"
8036 "(expected %i, found %i)\n",
8037 tracked_pipe, pipe);
8038
8039 }
8040
8041 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8042 base.head) {
8043 bool enabled = false;
8044 bool active = false;
8045
8046 DRM_DEBUG_KMS("[CRTC:%d]\n",
8047 crtc->base.base.id);
8048
8049 WARN(crtc->active && !crtc->base.enabled,
8050 "active crtc, but not enabled in sw tracking\n");
8051
8052 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8053 base.head) {
8054 if (encoder->base.crtc != &crtc->base)
8055 continue;
8056 enabled = true;
8057 if (encoder->connectors_active)
8058 active = true;
8059 }
8060 WARN(active != crtc->active,
8061 "crtc's computed active state doesn't match tracked active state "
8062 "(expected %i, found %i)\n", active, crtc->active);
8063 WARN(enabled != crtc->base.enabled,
8064 "crtc's computed enabled state doesn't match tracked enabled state "
8065 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8066
88adfff1 8067 memset(&pipe_config, 0, sizeof(pipe_config));
60c4ae10 8068 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 8069 active = dev_priv->display.get_pipe_config(crtc,
8070 &pipe_config);
8071 WARN(crtc->active != active,
8072 "crtc active state doesn't match with hw state "
8073 "(expected %i, found %i)\n", crtc->active, active);
8074
8075 WARN(active &&
8076 !intel_pipe_config_compare(&crtc->config, &pipe_config),
8077 "pipe state doesn't match!\n");
8af6cf88
DV		 8078 }
8079}
8080
f30da187
DV		 8081static int __intel_set_mode(struct drm_crtc *crtc,
8082 struct drm_display_mode *mode,
8083 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8084{
8085 struct drm_device *dev = crtc->dev;
dbf2b54e 8086 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8087 struct drm_display_mode *saved_mode, *saved_hwmode;
8088 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8089 struct intel_crtc *intel_crtc;
8090 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8091 int ret = 0;
a6778b3c 8092
3ac18232 8093 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8094 if (!saved_mode)
8095 return -ENOMEM;
3ac18232 8096 saved_hwmode = saved_mode + 1;
a6778b3c 8097
e2e1ed41 8098 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8099 &prepare_pipes, &disable_pipes);
8100
3ac18232
TG		 8101 *saved_hwmode = crtc->hwmode;
8102 *saved_mode = crtc->mode;
a6778b3c 8103
25c5b266
DV		 8104 /* Hack: Because we don't (yet) support global modeset on multiple
8105 * crtcs, we don't keep track of the new mode for more than one crtc.
8106 * Hence simply check whether any bit is set in modeset_pipes in all the
8107 * pieces of code that are not yet converted to deal with mutliple crtcs
8108 * changing their mode at the same time. */
25c5b266 8109 if (modeset_pipes) {
4e53c2e0 8110 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8111 if (IS_ERR(pipe_config)) {
8112 ret = PTR_ERR(pipe_config);
8113 pipe_config = NULL;
8114
3ac18232 8115 goto out;
25c5b266 8116 }
25c5b266 8117 }
a6778b3c 8118
460da916
DV		 8119 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8120 intel_crtc_disable(&intel_crtc->base);
8121
ea9d758d
DV		 8122 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8123 if (intel_crtc->base.enabled)
8124 dev_priv->display.crtc_disable(&intel_crtc->base);
8125 }
a6778b3c 8126
6c4c86f5
DV		 8127 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8128 * to set it here already despite that we pass it down the callchain.
f6e5b160 8129 */
b8cecdf5 8130 if (modeset_pipes) {
3b117c8f 8131 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
25c5b266 8132 crtc->mode = *mode;
b8cecdf5
DV		 8133 /* mode_set/enable/disable functions rely on a correct pipe
8134 * config. */
8135 to_intel_crtc(crtc)->config = *pipe_config;
3b117c8f 8136 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
b8cecdf5 8137 }
7758a113 8138
ea9d758d
DV		 8139 /* Only after disabling all output pipelines that will be changed can we
8140 * update the the output configuration. */
8141 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8142
47fab737
DV		 8143 if (dev_priv->display.modeset_global_resources)
8144 dev_priv->display.modeset_global_resources(dev);
8145
a6778b3c
DV		 8146 /* Set up the DPLL and any encoders state that needs to adjust or depend
8147 * on the DPLL.
f6e5b160 8148 */
25c5b266 8149 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8150 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8151 x, y, fb);
8152 if (ret)
8153 goto done;
a6778b3c
DV		 8154 }
8155
8156 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8157 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8158 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8159
25c5b266
DV		 8160 if (modeset_pipes) {
8161 /* Store real post-adjustment hardware mode. */
b8cecdf5 8162 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8163
25c5b266
DV		 8164 /* Calculate and store various constants which
8165 * are later needed by vblank and swap-completion
8166 * timestamping. They are derived from true hwmode.
8167 */
8168 drm_calc_timestamping_constants(crtc);
8169 }
a6778b3c
DV		 8170
8171 /* FIXME: add subpixel order */
8172done:
c0c36b94 8173 if (ret && crtc->enabled) {
3ac18232
TG		 8174 crtc->hwmode = *saved_hwmode;
8175 crtc->mode = *saved_mode;
a6778b3c
DV		 8176 }
8177
3ac18232 8178out:
b8cecdf5 8179 kfree(pipe_config);
3ac18232 8180 kfree(saved_mode);
a6778b3c 8181 return ret;
f6e5b160
CW		 8182}
8183
f30da187
DV		 8184int intel_set_mode(struct drm_crtc *crtc,
8185 struct drm_display_mode *mode,
8186 int x, int y, struct drm_framebuffer *fb)
8187{
8188 int ret;
8189
8190 ret = __intel_set_mode(crtc, mode, x, y, fb);
8191
8192 if (ret == 0)
8193 intel_modeset_check_state(crtc->dev);
8194
8195 return ret;
8196}
8197
c0c36b94
CW		 8198void intel_crtc_restore_mode(struct drm_crtc *crtc)
8199{
8200 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8201}
8202
25c5b266
DV		 8203#undef for_each_intel_crtc_masked
8204
d9e55608
DV		 8205static void intel_set_config_free(struct intel_set_config *config)
8206{
8207 if (!config)
8208 return;
8209
1aa4b628
DV		 8210 kfree(config->save_connector_encoders);
8211 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8212 kfree(config);
8213}
8214
85f9eb71
DV		 8215static int intel_set_config_save_state(struct drm_device *dev,
8216 struct intel_set_config *config)
8217{
85f9eb71
DV		 8218 struct drm_encoder *encoder;
8219 struct drm_connector *connector;
8220 int count;
8221
1aa4b628
DV		 8222 config->save_encoder_crtcs =
8223 kcalloc(dev->mode_config.num_encoder,
8224 sizeof(struct drm_crtc *), GFP_KERNEL);
8225 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8226 return -ENOMEM;
8227
1aa4b628
DV		 8228 config->save_connector_encoders =
8229 kcalloc(dev->mode_config.num_connector,
8230 sizeof(struct drm_encoder *), GFP_KERNEL);
8231 if (!config->save_connector_encoders)
85f9eb71
DV		 8232 return -ENOMEM;
8233
8234 /* Copy data. Note that driver private data is not affected.
8235 * Should anything bad happen only the expected state is
8236 * restored, not the drivers personal bookkeeping.
8237 */
85f9eb71
DV		 8238 count = 0;
8239 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8240 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8241 }
8242
8243 count = 0;
8244 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8245 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8246 }
8247
8248 return 0;
8249}
8250
8251static void intel_set_config_restore_state(struct drm_device *dev,
8252 struct intel_set_config *config)
8253{
9a935856
DV		 8254 struct intel_encoder *encoder;
8255 struct intel_connector *connector;
85f9eb71
DV		 8256 int count;
8257
85f9eb71 8258 count = 0;
9a935856
DV		 8259 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8260 encoder->new_crtc =
8261 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8262 }
8263
8264 count = 0;
9a935856
DV		 8265 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8266 connector->new_encoder =
8267 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8268 }
8269}
8270
5e2b584e
DV		 8271static void
8272intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8273 struct intel_set_config *config)
8274{
8275
8276 /* We should be able to check here if the fb has the same properties
8277 * and then just flip_or_move it */
8278 if (set->crtc->fb != set->fb) {
8279 /* If we have no fb then treat it as a full mode set */
8280 if (set->crtc->fb == NULL) {
8281 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8282 config->mode_changed = true;
8283 } else if (set->fb == NULL) {
8284 config->mode_changed = true;
72f4901e
DV		 8285 } else if (set->fb->pixel_format !=
8286 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8287 config->mode_changed = true;
8288 } else
8289 config->fb_changed = true;
8290 }
8291
835c5873 8292 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8293 config->fb_changed = true;
8294
8295 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8296 DRM_DEBUG_KMS("modes are different, full mode set\n");
8297 drm_mode_debug_printmodeline(&set->crtc->mode);
8298 drm_mode_debug_printmodeline(set->mode);
8299 config->mode_changed = true;
8300 }
8301}
8302
2e431051 8303static int
9a935856
DV		 8304intel_modeset_stage_output_state(struct drm_device *dev,
8305 struct drm_mode_set *set,
8306 struct intel_set_config *config)
50f56119 8307{
85f9eb71 8308 struct drm_crtc *new_crtc;
9a935856
DV		 8309 struct intel_connector *connector;
8310 struct intel_encoder *encoder;
2e431051 8311 int count, ro;
50f56119 8312
9abdda74 8313 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8314 * of connectors. For paranoia, double-check this. */
8315 WARN_ON(!set->fb && (set->num_connectors != 0));
8316 WARN_ON(set->fb && (set->num_connectors == 0));
8317
50f56119 8318 count = 0;
9a935856
DV		 8319 list_for_each_entry(connector, &dev->mode_config.connector_list,
8320 base.head) {
8321 /* Otherwise traverse passed in connector list and get encoders
8322 * for them. */
50f56119 8323 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8324 if (set->connectors[ro] == &connector->base) {
8325 connector->new_encoder = connector->encoder;
50f56119
DV		 8326 break;
8327 }
8328 }
8329
9a935856
DV		 8330 /* If we disable the crtc, disable all its connectors. Also, if
8331 * the connector is on the changing crtc but not on the new
8332 * connector list, disable it. */
8333 if ((!set->fb || ro == set->num_connectors) &&
8334 connector->base.encoder &&
8335 connector->base.encoder->crtc == set->crtc) {
8336 connector->new_encoder = NULL;
8337
8338 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8339 connector->base.base.id,
8340 drm_get_connector_name(&connector->base));
8341 }
8342
8343
8344 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8345 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8346 config->mode_changed = true;
50f56119
DV		 8347 }
8348 }
9a935856 8349 /* connector->new_encoder is now updated for all connectors. */
50f56119 8350
9a935856 8351 /* Update crtc of enabled connectors. */
50f56119 8352 count = 0;
9a935856
DV		 8353 list_for_each_entry(connector, &dev->mode_config.connector_list,
8354 base.head) {
8355 if (!connector->new_encoder)
50f56119
DV		 8356 continue;
8357
9a935856 8358 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8359
8360 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8361 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8362 new_crtc = set->crtc;
8363 }
8364
8365 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8366 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8367 new_crtc)) {
5e2b584e 8368 return -EINVAL;
50f56119 8369 }
9a935856
DV		 8370 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8371
8372 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8373 connector->base.base.id,
8374 drm_get_connector_name(&connector->base),
8375 new_crtc->base.id);
8376 }
8377
8378 /* Check for any encoders that needs to be disabled. */
8379 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8380 base.head) {
8381 list_for_each_entry(connector,
8382 &dev->mode_config.connector_list,
8383 base.head) {
8384 if (connector->new_encoder == encoder) {
8385 WARN_ON(!connector->new_encoder->new_crtc);
8386
8387 goto next_encoder;
8388 }
8389 }
8390 encoder->new_crtc = NULL;
8391next_encoder:
8392 /* Only now check for crtc changes so we don't miss encoders
8393 * that will be disabled. */
8394 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8395 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8396 config->mode_changed = true;
50f56119
DV		 8397 }
8398 }
9a935856 8399 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8400
2e431051
DV		 8401 return 0;
8402}
8403
8404static int intel_crtc_set_config(struct drm_mode_set *set)
8405{
8406 struct drm_device *dev;
2e431051
DV		 8407 struct drm_mode_set save_set;
8408 struct intel_set_config *config;
8409 int ret;
2e431051 8410
8d3e375e
DV		 8411 BUG_ON(!set);
8412 BUG_ON(!set->crtc);
8413 BUG_ON(!set->crtc->helper_private);
2e431051 8414
7e53f3a4
DV		 8415 /* Enforce sane interface api - has been abused by the fb helper. */
8416 BUG_ON(!set->mode && set->fb);
8417 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8418
2e431051
DV		 8419 if (set->fb) {
8420 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8421 set->crtc->base.id, set->fb->base.id,
8422 (int)set->num_connectors, set->x, set->y);
8423 } else {
8424 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8425 }
8426
8427 dev = set->crtc->dev;
8428
8429 ret = -ENOMEM;
8430 config = kzalloc(sizeof(*config), GFP_KERNEL);
8431 if (!config)
8432 goto out_config;
8433
8434 ret = intel_set_config_save_state(dev, config);
8435 if (ret)
8436 goto out_config;
8437
8438 save_set.crtc = set->crtc;
8439 save_set.mode = &set->crtc->mode;
8440 save_set.x = set->crtc->x;
8441 save_set.y = set->crtc->y;
8442 save_set.fb = set->crtc->fb;
8443
8444 /* Compute whether we need a full modeset, only an fb base update or no
8445 * change at all. In the future we might also check whether only the
8446 * mode changed, e.g. for LVDS where we only change the panel fitter in
8447 * such cases. */
8448 intel_set_config_compute_mode_changes(set, config);
8449
9a935856 8450 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8451 if (ret)
8452 goto fail;
8453
5e2b584e 8454 if (config->mode_changed) {
87f1faa6 8455 if (set->mode) {
50f56119
DV		 8456 DRM_DEBUG_KMS("attempting to set mode from"
8457 " userspace\n");
8458 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8459 }
8460
c0c36b94
CW		 8461 ret = intel_set_mode(set->crtc, set->mode,
8462 set->x, set->y, set->fb);
8463 if (ret) {
8464 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8465 set->crtc->base.id, ret);
87f1faa6
DV		 8466 goto fail;
8467 }
5e2b584e 8468 } else if (config->fb_changed) {
4878cae2
VS		 8469 intel_crtc_wait_for_pending_flips(set->crtc);
8470
4f660f49 8471 ret = intel_pipe_set_base(set->crtc,
94352cf9 8472 set->x, set->y, set->fb);
50f56119
DV		 8473 }
8474
d9e55608
DV		 8475 intel_set_config_free(config);
8476
50f56119
DV		 8477 return 0;
8478
8479fail:
85f9eb71 8480 intel_set_config_restore_state(dev, config);
50f56119
DV		 8481
8482 /* Try to restore the config */
5e2b584e 8483 if (config->mode_changed &&
c0c36b94
CW		 8484 intel_set_mode(save_set.crtc, save_set.mode,
8485 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8486 DRM_ERROR("failed to restore config after modeset failure\n");
8487
d9e55608
DV		 8488out_config:
8489 intel_set_config_free(config);
50f56119
DV		 8490 return ret;
8491}
f6e5b160
CW		 8492
8493static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8494 .cursor_set = intel_crtc_cursor_set,
8495 .cursor_move = intel_crtc_cursor_move,
8496 .gamma_set = intel_crtc_gamma_set,
50f56119 8497 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8498 .destroy = intel_crtc_destroy,
8499 .page_flip = intel_crtc_page_flip,
8500};
8501
79f689aa
PZ		 8502static void intel_cpu_pll_init(struct drm_device *dev)
8503{
affa9354 8504 if (HAS_DDI(dev))
79f689aa
PZ		 8505 intel_ddi_pll_init(dev);
8506}
8507
ee7b9f93
JB		 8508static void intel_pch_pll_init(struct drm_device *dev)
8509{
8510 drm_i915_private_t *dev_priv = dev->dev_private;
8511 int i;
8512
8513 if (dev_priv->num_pch_pll == 0) {
8514 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8515 return;
8516 }
8517
8518 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8519 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8520 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8521 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8522 }
8523}
8524
b358d0a6 8525static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8526{
22fd0fab 8527 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8528 struct intel_crtc *intel_crtc;
8529 int i;
8530
8531 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8532 if (intel_crtc == NULL)
8533 return;
8534
8535 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8536
8537 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8538 for (i = 0; i < 256; i++) {
8539 intel_crtc->lut_r[i] = i;
8540 intel_crtc->lut_g[i] = i;
8541 intel_crtc->lut_b[i] = i;
8542 }
8543
80824003
JB		 8544 /* Swap pipes & planes for FBC on pre-965 */
8545 intel_crtc->pipe = pipe;
8546 intel_crtc->plane = pipe;
3b117c8f 8547 intel_crtc->config.cpu_transcoder = pipe;
e2e767ab 8548 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8549 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8550 intel_crtc->plane = !pipe;
80824003
JB		 8551 }
8552
22fd0fab
JB		 8553 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8554 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8555 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8556 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8557
79e53945 8558 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8559}
8560
08d7b3d1 8561int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8562 struct drm_file *file)
08d7b3d1 8563{
08d7b3d1 8564 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8565 struct drm_mode_object *drmmode_obj;
8566 struct intel_crtc *crtc;
08d7b3d1 8567
1cff8f6b
DV		 8568 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8569 return -ENODEV;
08d7b3d1 8570
c05422d5
DV		 8571 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8572 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8573
c05422d5 8574 if (!drmmode_obj) {
08d7b3d1
CW		 8575 DRM_ERROR("no such CRTC id\n");
8576 return -EINVAL;
8577 }
8578
c05422d5
DV		 8579 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8580 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8581
c05422d5 8582 return 0;
08d7b3d1
CW		 8583}
8584
66a9278e 8585static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8586{
66a9278e
DV		 8587 struct drm_device *dev = encoder->base.dev;
8588 struct intel_encoder *source_encoder;
79e53945 8589 int index_mask = 0;
79e53945
JB		 8590 int entry = 0;
8591
66a9278e
DV		 8592 list_for_each_entry(source_encoder,
8593 &dev->mode_config.encoder_list, base.head) {
8594
8595 if (encoder == source_encoder)
79e53945 8596 index_mask |= (1 << entry);
66a9278e
DV		 8597
8598 /* Intel hw has only one MUX where enocoders could be cloned. */
8599 if (encoder->cloneable && source_encoder->cloneable)
8600 index_mask |= (1 << entry);
8601
79e53945
JB		 8602 entry++;
8603 }
4ef69c7a 8604
79e53945
JB		 8605 return index_mask;
8606}
8607
4d302442
CW		 8608static bool has_edp_a(struct drm_device *dev)
8609{
8610 struct drm_i915_private *dev_priv = dev->dev_private;
8611
8612 if (!IS_MOBILE(dev))
8613 return false;
8614
8615 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8616 return false;
8617
8618 if (IS_GEN5(dev) &&
8619 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8620 return false;
8621
8622 return true;
8623}
8624
79e53945
JB		 8625static void intel_setup_outputs(struct drm_device *dev)
8626{
725e30ad 8627 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8628 struct intel_encoder *encoder;
cb0953d7 8629 bool dpd_is_edp = false;
f3cfcba6 8630 bool has_lvds;
79e53945 8631
f3cfcba6 8632 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8633 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8634 /* disable the panel fitter on everything but LVDS */
8635 I915_WRITE(PFIT_CONTROL, 0);
8636 }
79e53945 8637
c40c0f5b 8638 if (!IS_ULT(dev))
79935fca 8639 intel_crt_init(dev);
cb0953d7 8640
affa9354 8641 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8642 int found;
8643
8644 /* Haswell uses DDI functions to detect digital outputs */
8645 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8646 /* DDI A only supports eDP */
8647 if (found)
8648 intel_ddi_init(dev, PORT_A);
8649
8650 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8651 * register */
8652 found = I915_READ(SFUSE_STRAP);
8653
8654 if (found & SFUSE_STRAP_DDIB_DETECTED)
8655 intel_ddi_init(dev, PORT_B);
8656 if (found & SFUSE_STRAP_DDIC_DETECTED)
8657 intel_ddi_init(dev, PORT_C);
8658 if (found & SFUSE_STRAP_DDID_DETECTED)
8659 intel_ddi_init(dev, PORT_D);
8660 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8661 int found;
270b3042
DV		 8662 dpd_is_edp = intel_dpd_is_edp(dev);
8663
8664 if (has_edp_a(dev))
8665 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8666
dc0fa718 8667 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8668 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8669 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8670 if (!found)
e2debe91 8671 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8672 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8673 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8674 }
8675
dc0fa718 8676 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8677 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8678
dc0fa718 8679 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8680 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8681
5eb08b69 8682 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8683 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8684
270b3042 8685 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8686 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8687 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8688 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8689 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8690 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8691
dc0fa718 8692 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8693 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8694 PORT_B);
67cfc203
VS		 8695 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8696 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8697 }
103a196f 8698 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8699 bool found = false;
7d57382e 8700
e2debe91 8701 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8702 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8703 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8704 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8705 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8706 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8707 }
27185ae1 8708
b01f2c3a
JB		 8709 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8710 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8711 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8712 }
725e30ad 8713 }
13520b05
KH		 8714
8715 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8716
e2debe91 8717 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8718 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8719 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8720 }
27185ae1 8721
e2debe91 8722 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8723
b01f2c3a
JB		 8724 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8725 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8726 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8727 }
8728 if (SUPPORTS_INTEGRATED_DP(dev)) {
8729 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8730 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8731 }
725e30ad 8732 }
27185ae1 8733
b01f2c3a
JB		 8734 if (SUPPORTS_INTEGRATED_DP(dev) &&
8735 (I915_READ(DP_D) & DP_DETECTED)) {
8736 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8737 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8738 }
bad720ff 8739 } else if (IS_GEN2(dev))
79e53945
JB		 8740 intel_dvo_init(dev);
8741
103a196f 8742 if (SUPPORTS_TV(dev))
79e53945
JB		 8743 intel_tv_init(dev);
8744
4ef69c7a
CW		 8745 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8746 encoder->base.possible_crtcs = encoder->crtc_mask;
8747 encoder->base.possible_clones =
66a9278e 8748 intel_encoder_clones(encoder);
79e53945 8749 }
47356eb6 8750
dde86e2d 8751 intel_init_pch_refclk(dev);
270b3042
DV		 8752
8753 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8754}
8755
8756static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8757{
8758 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8759
8760 drm_framebuffer_cleanup(fb);
05394f39 8761 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8762
8763 kfree(intel_fb);
8764}
8765
8766static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8767 struct drm_file *file,
79e53945
JB		 8768 unsigned int *handle)
8769{
8770 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8771 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8772
05394f39 8773 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8774}
8775
8776static const struct drm_framebuffer_funcs intel_fb_funcs = {
8777 .destroy = intel_user_framebuffer_destroy,
8778 .create_handle = intel_user_framebuffer_create_handle,
8779};
8780
38651674
DA		 8781int intel_framebuffer_init(struct drm_device *dev,
8782 struct intel_framebuffer *intel_fb,
308e5bcb 8783 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8784 struct drm_i915_gem_object *obj)
79e53945 8785{
79e53945
JB		 8786 int ret;
8787
c16ed4be
CW		 8788 if (obj->tiling_mode == I915_TILING_Y) {
8789 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8790 return -EINVAL;
c16ed4be 8791 }
57cd6508 8792
c16ed4be
CW		 8793 if (mode_cmd->pitches[0] & 63) {
8794 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8795 mode_cmd->pitches[0]);
57cd6508 8796 return -EINVAL;
c16ed4be 8797 }
57cd6508 8798
5d7bd705 8799 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8800 if (mode_cmd->pitches[0] > 32768) {
8801 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8802 mode_cmd->pitches[0]);
5d7bd705 8803 return -EINVAL;
c16ed4be 8804 }
5d7bd705
VS		 8805
8806 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8807 mode_cmd->pitches[0] != obj->stride) {
8808 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8809 mode_cmd->pitches[0], obj->stride);
5d7bd705 8810 return -EINVAL;
c16ed4be 8811 }
5d7bd705 8812
57779d06 8813 /* Reject formats not supported by any plane early. */
308e5bcb 8814 switch (mode_cmd->pixel_format) {
57779d06 8815 case DRM_FORMAT_C8:
04b3924d
VS		 8816 case DRM_FORMAT_RGB565:
8817 case DRM_FORMAT_XRGB8888:
8818 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8819 break;
8820 case DRM_FORMAT_XRGB1555:
8821 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8822 if (INTEL_INFO(dev)->gen > 3) {
8823 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8824 return -EINVAL;
c16ed4be 8825 }
57779d06
VS		 8826 break;
8827 case DRM_FORMAT_XBGR8888:
8828 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8829 case DRM_FORMAT_XRGB2101010:
8830 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8831 case DRM_FORMAT_XBGR2101010:
8832 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8833 if (INTEL_INFO(dev)->gen < 4) {
8834 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8835 return -EINVAL;
c16ed4be 8836 }
b5626747 8837 break;
04b3924d
VS		 8838 case DRM_FORMAT_YUYV:
8839 case DRM_FORMAT_UYVY:
8840 case DRM_FORMAT_YVYU:
8841 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8842 if (INTEL_INFO(dev)->gen < 5) {
8843 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8844 return -EINVAL;
c16ed4be 8845 }
57cd6508
CW		 8846 break;
8847 default:
c16ed4be 8848 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8849 return -EINVAL;
8850 }
8851
90f9a336
VS		 8852 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8853 if (mode_cmd->offsets[0] != 0)
8854 return -EINVAL;
8855
c7d73f6a
DV		 8856 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8857 intel_fb->obj = obj;
8858
79e53945
JB		 8859 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8860 if (ret) {
8861 DRM_ERROR("framebuffer init failed %d\n", ret);
8862 return ret;
8863 }
8864
79e53945
JB		 8865 return 0;
8866}
8867
79e53945
JB		 8868static struct drm_framebuffer *
8869intel_user_framebuffer_create(struct drm_device *dev,
8870 struct drm_file *filp,
308e5bcb 8871 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8872{
05394f39 8873 struct drm_i915_gem_object *obj;
79e53945 8874
308e5bcb
JB		 8875 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8876 mode_cmd->handles[0]));
c8725226 8877 if (&obj->base == NULL)
cce13ff7 8878 return ERR_PTR(-ENOENT);
79e53945 8879
d2dff872 8880 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8881}
8882
79e53945 8883static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8884 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8885 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8886};
8887
e70236a8
JB		 8888/* Set up chip specific display functions */
8889static void intel_init_display(struct drm_device *dev)
8890{
8891 struct drm_i915_private *dev_priv = dev->dev_private;
8892
affa9354 8893 if (HAS_DDI(dev)) {
0e8ffe1b 8894 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 8895 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8896 dev_priv->display.crtc_enable = haswell_crtc_enable;
8897 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8898 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8899 dev_priv->display.update_plane = ironlake_update_plane;
8900 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 8901 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 8902 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8903 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8904 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8905 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8906 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 8907 } else if (IS_VALLEYVIEW(dev)) {
8908 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8909 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8910 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8911 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8912 dev_priv->display.off = i9xx_crtc_off;
8913 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8914 } else {
0e8ffe1b 8915 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 8916 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8917 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8918 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8919 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8920 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8921 }
e70236a8 8922
e70236a8 8923 /* Returns the core display clock speed */
25eb05fc
JB		 8924 if (IS_VALLEYVIEW(dev))
8925 dev_priv->display.get_display_clock_speed =
8926 valleyview_get_display_clock_speed;
8927 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8928 dev_priv->display.get_display_clock_speed =
8929 i945_get_display_clock_speed;
8930 else if (IS_I915G(dev))
8931 dev_priv->display.get_display_clock_speed =
8932 i915_get_display_clock_speed;
f2b115e6 8933 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8934 dev_priv->display.get_display_clock_speed =
8935 i9xx_misc_get_display_clock_speed;
8936 else if (IS_I915GM(dev))
8937 dev_priv->display.get_display_clock_speed =
8938 i915gm_get_display_clock_speed;
8939 else if (IS_I865G(dev))
8940 dev_priv->display.get_display_clock_speed =
8941 i865_get_display_clock_speed;
f0f8a9ce 8942 else if (IS_I85X(dev))
e70236a8
JB		 8943 dev_priv->display.get_display_clock_speed =
8944 i855_get_display_clock_speed;
8945 else /* 852, 830 */
8946 dev_priv->display.get_display_clock_speed =
8947 i830_get_display_clock_speed;
8948
7f8a8569 8949 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8950 if (IS_GEN5(dev)) {
674cf967 8951 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8952 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8953 } else if (IS_GEN6(dev)) {
674cf967 8954 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8955 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8956 } else if (IS_IVYBRIDGE(dev)) {
8957 /* FIXME: detect B0+ stepping and use auto training */
8958 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8959 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8960 dev_priv->display.modeset_global_resources =
8961 ivb_modeset_global_resources;
c82e4d26
ED		 8962 } else if (IS_HASWELL(dev)) {
8963 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8964 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8965 dev_priv->display.modeset_global_resources =
8966 haswell_modeset_global_resources;
a0e63c22 8967 }
6067aaea 8968 } else if (IS_G4X(dev)) {
e0dac65e 8969 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8970 }
8c9f3aaf
JB		 8971
8972 /* Default just returns -ENODEV to indicate unsupported */
8973 dev_priv->display.queue_flip = intel_default_queue_flip;
8974
8975 switch (INTEL_INFO(dev)->gen) {
8976 case 2:
8977 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8978 break;
8979
8980 case 3:
8981 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8982 break;
8983
8984 case 4:
8985 case 5:
8986 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8987 break;
8988
8989 case 6:
8990 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8991 break;
7c9017e5
JB		 8992 case 7:
8993 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8994 break;
8c9f3aaf 8995 }
e70236a8
JB		 8996}
8997
b690e96c
JB		 8998/*
8999 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9000 * resume, or other times. This quirk makes sure that's the case for
9001 * affected systems.
9002 */
0206e353 9003static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9004{
9005 struct drm_i915_private *dev_priv = dev->dev_private;
9006
9007 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9008 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9009}
9010
435793df
KP		 9011/*
9012 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9013 */
9014static void quirk_ssc_force_disable(struct drm_device *dev)
9015{
9016 struct drm_i915_private *dev_priv = dev->dev_private;
9017 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9018 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9019}
9020
4dca20ef 9021/*
5a15ab5b
CE		 9022 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9023 * brightness value
4dca20ef
CE		 9024 */
9025static void quirk_invert_brightness(struct drm_device *dev)
9026{
9027 struct drm_i915_private *dev_priv = dev->dev_private;
9028 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9029 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9030}
9031
b690e96c
JB		 9032struct intel_quirk {
9033 int device;
9034 int subsystem_vendor;
9035 int subsystem_device;
9036 void (*hook)(struct drm_device *dev);
9037};
9038
5f85f176
EE		 9039/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9040struct intel_dmi_quirk {
9041 void (*hook)(struct drm_device *dev);
9042 const struct dmi_system_id (*dmi_id_list)[];
9043};
9044
9045static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9046{
9047 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9048 return 1;
9049}
9050
9051static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9052 {
9053 .dmi_id_list = &(const struct dmi_system_id[]) {
9054 {
9055 .callback = intel_dmi_reverse_brightness,
9056 .ident = "NCR Corporation",
9057 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9058 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9059 },
9060 },
9061 { } /* terminating entry */
9062 },
9063 .hook = quirk_invert_brightness,
9064 },
9065};
9066
c43b5634 9067static struct intel_quirk intel_quirks[] = {
b690e96c 9068 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9069 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9070
b690e96c
JB		 9071 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9072 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9073
b690e96c
JB		 9074 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9075 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9076
ccd0d36e 9077 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9078 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9079 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9080
9081 /* Lenovo U160 cannot use SSC on LVDS */
9082 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9083
9084 /* Sony Vaio Y cannot use SSC on LVDS */
9085 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9086
9087 /* Acer Aspire 5734Z must invert backlight brightness */
9088 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9089
9090 /* Acer/eMachines G725 */
9091 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9092
9093 /* Acer/eMachines e725 */
9094 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9095
9096 /* Acer/Packard Bell NCL20 */
9097 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9098
9099 /* Acer Aspire 4736Z */
9100 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9101};
9102
9103static void intel_init_quirks(struct drm_device *dev)
9104{
9105 struct pci_dev *d = dev->pdev;
9106 int i;
9107
9108 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9109 struct intel_quirk *q = &intel_quirks[i];
9110
9111 if (d->device == q->device &&
9112 (d->subsystem_vendor == q->subsystem_vendor ||
9113 q->subsystem_vendor == PCI_ANY_ID) &&
9114 (d->subsystem_device == q->subsystem_device ||
9115 q->subsystem_device == PCI_ANY_ID))
9116 q->hook(dev);
9117 }
5f85f176
EE		 9118 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9119 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9120 intel_dmi_quirks[i].hook(dev);
9121 }
b690e96c
JB		 9122}
9123
9cce37f4
JB		 9124/* Disable the VGA plane that we never use */
9125static void i915_disable_vga(struct drm_device *dev)
9126{
9127 struct drm_i915_private *dev_priv = dev->dev_private;
9128 u8 sr1;
766aa1c4 9129 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9130
9131 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9132 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9133 sr1 = inb(VGA_SR_DATA);
9134 outb(sr1 | 1<<5, VGA_SR_DATA);
9135 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9136 udelay(300);
9137
9138 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9139 POSTING_READ(vga_reg);
9140}
9141
f817586c
DV		 9142void intel_modeset_init_hw(struct drm_device *dev)
9143{
fa42e23c 9144 intel_init_power_well(dev);
0232e927 9145
a8f78b58
ED		 9146 intel_prepare_ddi(dev);
9147
f817586c
DV		 9148 intel_init_clock_gating(dev);
9149
79f5b2c7 9150 mutex_lock(&dev->struct_mutex);
8090c6b9 9151 intel_enable_gt_powersave(dev);
79f5b2c7 9152 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9153}
9154
79e53945
JB		 9155void intel_modeset_init(struct drm_device *dev)
9156{
652c393a 9157 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9158 int i, j, ret;
79e53945
JB		 9159
9160 drm_mode_config_init(dev);
9161
9162 dev->mode_config.min_width = 0;
9163 dev->mode_config.min_height = 0;
9164
019d96cb
DA		 9165 dev->mode_config.preferred_depth = 24;
9166 dev->mode_config.prefer_shadow = 1;
9167
e6ecefaa 9168 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9169
b690e96c
JB		 9170 intel_init_quirks(dev);
9171
1fa61106
ED		 9172 intel_init_pm(dev);
9173
e3c74757
BW		 9174 if (INTEL_INFO(dev)->num_pipes == 0)
9175 return;
9176
e70236a8
JB		 9177 intel_init_display(dev);
9178
a6c45cf0
CW		 9179 if (IS_GEN2(dev)) {
9180 dev->mode_config.max_width = 2048;
9181 dev->mode_config.max_height = 2048;
9182 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9183 dev->mode_config.max_width = 4096;
9184 dev->mode_config.max_height = 4096;
79e53945 9185 } else {
a6c45cf0
CW		 9186 dev->mode_config.max_width = 8192;
9187 dev->mode_config.max_height = 8192;
79e53945 9188 }
5d4545ae 9189 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9190
28c97730 9191 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9192 INTEL_INFO(dev)->num_pipes,
9193 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9194
7eb552ae 9195 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9196 intel_crtc_init(dev, i);
7f1f3851
JB		 9197 for (j = 0; j < dev_priv->num_plane; j++) {
9198 ret = intel_plane_init(dev, i, j);
9199 if (ret)
06da8da2
VS		 9200 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9201 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9202 }
79e53945
JB		 9203 }
9204
79f689aa 9205 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9206 intel_pch_pll_init(dev);
9207
9cce37f4
JB		 9208 /* Just disable it once at startup */
9209 i915_disable_vga(dev);
79e53945 9210 intel_setup_outputs(dev);
11be49eb
CW		 9211
9212 /* Just in case the BIOS is doing something questionable. */
9213 intel_disable_fbc(dev);
2c7111db
CW		 9214}
9215
24929352
DV		 9216static void
9217intel_connector_break_all_links(struct intel_connector *connector)
9218{
9219 connector->base.dpms = DRM_MODE_DPMS_OFF;
9220 connector->base.encoder = NULL;
9221 connector->encoder->connectors_active = false;
9222 connector->encoder->base.crtc = NULL;
9223}
9224
7fad798e
DV		 9225static void intel_enable_pipe_a(struct drm_device *dev)
9226{
9227 struct intel_connector *connector;
9228 struct drm_connector *crt = NULL;
9229 struct intel_load_detect_pipe load_detect_temp;
9230
9231 /* We can't just switch on the pipe A, we need to set things up with a
9232 * proper mode and output configuration. As a gross hack, enable pipe A
9233 * by enabling the load detect pipe once. */
9234 list_for_each_entry(connector,
9235 &dev->mode_config.connector_list,
9236 base.head) {
9237 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9238 crt = &connector->base;
9239 break;
9240 }
9241 }
9242
9243 if (!crt)
9244 return;
9245
9246 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9247 intel_release_load_detect_pipe(crt, &load_detect_temp);
9248
652c393a 9249
7fad798e
DV		 9250}
9251
fa555837
DV		 9252static bool
9253intel_check_plane_mapping(struct intel_crtc *crtc)
9254{
7eb552ae
BW		 9255 struct drm_device *dev = crtc->base.dev;
9256 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9257 u32 reg, val;
9258
7eb552ae 9259 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9260 return true;
9261
9262 reg = DSPCNTR(!crtc->plane);
9263 val = I915_READ(reg);
9264
9265 if ((val & DISPLAY_PLANE_ENABLE) &&
9266 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9267 return false;
9268
9269 return true;
9270}
9271
24929352
DV		 9272static void intel_sanitize_crtc(struct intel_crtc *crtc)
9273{
9274 struct drm_device *dev = crtc->base.dev;
9275 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9276 u32 reg;
24929352 9277
24929352 9278 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9279 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9280 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9281
9282 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9283 * disable the crtc (and hence change the state) if it is wrong. Note
9284 * that gen4+ has a fixed plane -> pipe mapping. */
9285 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9286 struct intel_connector *connector;
9287 bool plane;
9288
24929352
DV		 9289 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9290 crtc->base.base.id);
9291
9292 /* Pipe has the wrong plane attached and the plane is active.
9293 * Temporarily change the plane mapping and disable everything
9294 * ... */
9295 plane = crtc->plane;
9296 crtc->plane = !plane;
9297 dev_priv->display.crtc_disable(&crtc->base);
9298 crtc->plane = plane;
9299
9300 /* ... and break all links. */
9301 list_for_each_entry(connector, &dev->mode_config.connector_list,
9302 base.head) {
9303 if (connector->encoder->base.crtc != &crtc->base)
9304 continue;
9305
9306 intel_connector_break_all_links(connector);
9307 }
9308
9309 WARN_ON(crtc->active);
9310 crtc->base.enabled = false;
9311 }
24929352 9312
7fad798e
DV		 9313 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9314 crtc->pipe == PIPE_A && !crtc->active) {
9315 /* BIOS forgot to enable pipe A, this mostly happens after
9316 * resume. Force-enable the pipe to fix this, the update_dpms
9317 * call below we restore the pipe to the right state, but leave
9318 * the required bits on. */
9319 intel_enable_pipe_a(dev);
9320 }
9321
24929352
DV		 9322 /* Adjust the state of the output pipe according to whether we
9323 * have active connectors/encoders. */
9324 intel_crtc_update_dpms(&crtc->base);
9325
9326 if (crtc->active != crtc->base.enabled) {
9327 struct intel_encoder *encoder;
9328
9329 /* This can happen either due to bugs in the get_hw_state
9330 * functions or because the pipe is force-enabled due to the
9331 * pipe A quirk. */
9332 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9333 crtc->base.base.id,
9334 crtc->base.enabled ? "enabled" : "disabled",
9335 crtc->active ? "enabled" : "disabled");
9336
9337 crtc->base.enabled = crtc->active;
9338
9339 /* Because we only establish the connector -> encoder ->
9340 * crtc links if something is active, this means the
9341 * crtc is now deactivated. Break the links. connector
9342 * -> encoder links are only establish when things are
9343 * actually up, hence no need to break them. */
9344 WARN_ON(crtc->active);
9345
9346 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9347 WARN_ON(encoder->connectors_active);
9348 encoder->base.crtc = NULL;
9349 }
9350 }
9351}
9352
9353static void intel_sanitize_encoder(struct intel_encoder *encoder)
9354{
9355 struct intel_connector *connector;
9356 struct drm_device *dev = encoder->base.dev;
9357
9358 /* We need to check both for a crtc link (meaning that the
9359 * encoder is active and trying to read from a pipe) and the
9360 * pipe itself being active. */
9361 bool has_active_crtc = encoder->base.crtc &&
9362 to_intel_crtc(encoder->base.crtc)->active;
9363
9364 if (encoder->connectors_active && !has_active_crtc) {
9365 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9366 encoder->base.base.id,
9367 drm_get_encoder_name(&encoder->base));
9368
9369 /* Connector is active, but has no active pipe. This is
9370 * fallout from our resume register restoring. Disable
9371 * the encoder manually again. */
9372 if (encoder->base.crtc) {
9373 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9374 encoder->base.base.id,
9375 drm_get_encoder_name(&encoder->base));
9376 encoder->disable(encoder);
9377 }
9378
9379 /* Inconsistent output/port/pipe state happens presumably due to
9380 * a bug in one of the get_hw_state functions. Or someplace else
9381 * in our code, like the register restore mess on resume. Clamp
9382 * things to off as a safer default. */
9383 list_for_each_entry(connector,
9384 &dev->mode_config.connector_list,
9385 base.head) {
9386 if (connector->encoder != encoder)
9387 continue;
9388
9389 intel_connector_break_all_links(connector);
9390 }
9391 }
9392 /* Enabled encoders without active connectors will be fixed in
9393 * the crtc fixup. */
9394}
9395
44cec740 9396void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9397{
9398 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9399 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9400
9401 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9402 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9403 i915_disable_vga(dev);
0fde901f
KM		 9404 }
9405}
9406
24929352
DV		 9407/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9408 * and i915 state tracking structures. */
45e2b5f6
DV		 9409void intel_modeset_setup_hw_state(struct drm_device *dev,
9410 bool force_restore)
24929352
DV		 9411{
9412 struct drm_i915_private *dev_priv = dev->dev_private;
9413 enum pipe pipe;
9414 u32 tmp;
b5644d05 9415 struct drm_plane *plane;
24929352
DV		 9416 struct intel_crtc *crtc;
9417 struct intel_encoder *encoder;
9418 struct intel_connector *connector;
9419
affa9354 9420 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9421 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9422
9423 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9424 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9425 case TRANS_DDI_EDP_INPUT_A_ON:
9426 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9427 pipe = PIPE_A;
9428 break;
9429 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9430 pipe = PIPE_B;
9431 break;
9432 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9433 pipe = PIPE_C;
9434 break;
aaa148ec
DL		 9435 default:
9436 /* A bogus value has been programmed, disable
9437 * the transcoder */
9438 WARN(1, "Bogus eDP source %08x\n", tmp);
9439 intel_ddi_disable_transcoder_func(dev_priv,
9440 TRANSCODER_EDP);
9441 goto setup_pipes;
e28d54cb
PZ		 9442 }
9443
9444 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3b117c8f 9445 crtc->config.cpu_transcoder = TRANSCODER_EDP;
e28d54cb
PZ		 9446
9447 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9448 pipe_name(pipe));
9449 }
9450 }
9451
aaa148ec 9452setup_pipes:
0e8ffe1b
DV		 9453 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9454 base.head) {
3b117c8f 9455 enum transcoder tmp = crtc->config.cpu_transcoder;
88adfff1 9456 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f
DV		 9457 crtc->config.cpu_transcoder = tmp;
9458
0e8ffe1b
DV		 9459 crtc->active = dev_priv->display.get_pipe_config(crtc,
9460 &crtc->config);
24929352
DV		 9461
9462 crtc->base.enabled = crtc->active;
9463
9464 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9465 crtc->base.base.id,
9466 crtc->active ? "enabled" : "disabled");
9467 }
9468
affa9354 9469 if (HAS_DDI(dev))
6441ab5f
PZ		 9470 intel_ddi_setup_hw_pll_state(dev);
9471
24929352
DV		 9472 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9473 base.head) {
9474 pipe = 0;
9475
9476 if (encoder->get_hw_state(encoder, &pipe)) {
9477 encoder->base.crtc =
9478 dev_priv->pipe_to_crtc_mapping[pipe];
9479 } else {
9480 encoder->base.crtc = NULL;
9481 }
9482
9483 encoder->connectors_active = false;
9484 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9485 encoder->base.base.id,
9486 drm_get_encoder_name(&encoder->base),
9487 encoder->base.crtc ? "enabled" : "disabled",
9488 pipe);
9489 }
9490
9491 list_for_each_entry(connector, &dev->mode_config.connector_list,
9492 base.head) {
9493 if (connector->get_hw_state(connector)) {
9494 connector->base.dpms = DRM_MODE_DPMS_ON;
9495 connector->encoder->connectors_active = true;
9496 connector->base.encoder = &connector->encoder->base;
9497 } else {
9498 connector->base.dpms = DRM_MODE_DPMS_OFF;
9499 connector->base.encoder = NULL;
9500 }
9501 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9502 connector->base.base.id,
9503 drm_get_connector_name(&connector->base),
9504 connector->base.encoder ? "enabled" : "disabled");
9505 }
9506
9507 /* HW state is read out, now we need to sanitize this mess. */
9508 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9509 base.head) {
9510 intel_sanitize_encoder(encoder);
9511 }
9512
9513 for_each_pipe(pipe) {
9514 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9515 intel_sanitize_crtc(crtc);
9516 }
9a935856 9517
45e2b5f6 9518 if (force_restore) {
f30da187
DV		 9519 /*
9520 * We need to use raw interfaces for restoring state to avoid
9521 * checking (bogus) intermediate states.
9522 */
45e2b5f6 9523 for_each_pipe(pipe) {
b5644d05
JB		 9524 struct drm_crtc *crtc =
9525 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9526
9527 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9528 crtc->fb);
45e2b5f6 9529 }
b5644d05
JB		 9530 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9531 intel_plane_restore(plane);
0fde901f
KM		 9532
9533 i915_redisable_vga(dev);
45e2b5f6
DV		 9534 } else {
9535 intel_modeset_update_staged_output_state(dev);
9536 }
8af6cf88
DV		 9537
9538 intel_modeset_check_state(dev);
2e938892
DV		 9539
9540 drm_mode_config_reset(dev);
2c7111db
CW		 9541}
9542
9543void intel_modeset_gem_init(struct drm_device *dev)
9544{
1833b134 9545 intel_modeset_init_hw(dev);
02e792fb
DV		 9546
9547 intel_setup_overlay(dev);
24929352 9548
45e2b5f6 9549 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9550}
9551
9552void intel_modeset_cleanup(struct drm_device *dev)
9553{
652c393a
JB		 9554 struct drm_i915_private *dev_priv = dev->dev_private;
9555 struct drm_crtc *crtc;
9556 struct intel_crtc *intel_crtc;
9557
fd0c0642
DV		 9558 /*
9559 * Interrupts and polling as the first thing to avoid creating havoc.
9560 * Too much stuff here (turning of rps, connectors, ...) would
9561 * experience fancy races otherwise.
9562 */
9563 drm_irq_uninstall(dev);
9564 cancel_work_sync(&dev_priv->hotplug_work);
9565 /*
9566 * Due to the hpd irq storm handling the hotplug work can re-arm the
9567 * poll handlers. Hence disable polling after hpd handling is shut down.
9568 */
f87ea761 9569 drm_kms_helper_poll_fini(dev);
fd0c0642 9570
652c393a
JB		 9571 mutex_lock(&dev->struct_mutex);
9572
723bfd70
JB		 9573 intel_unregister_dsm_handler();
9574
652c393a
JB		 9575 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9576 /* Skip inactive CRTCs */
9577 if (!crtc->fb)
9578 continue;
9579
9580 intel_crtc = to_intel_crtc(crtc);
3dec0095 9581 intel_increase_pllclock(crtc);
652c393a
JB		 9582 }
9583
973d04f9 9584 intel_disable_fbc(dev);
e70236a8 9585
8090c6b9 9586 intel_disable_gt_powersave(dev);
0cdab21f 9587
930ebb46
DV		 9588 ironlake_teardown_rc6(dev);
9589
69341a5e
KH		 9590 mutex_unlock(&dev->struct_mutex);
9591
1630fe75
CW		 9592 /* flush any delayed tasks or pending work */
9593 flush_scheduled_work();
9594
dc652f90
JN		 9595 /* destroy backlight, if any, before the connectors */
9596 intel_panel_destroy_backlight(dev);
9597
79e53945 9598 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9599
9600 intel_cleanup_overlay(dev);
79e53945
JB		 9601}
9602
f1c79df3
ZW		 9603/*
9604 * Return which encoder is currently attached for connector.
9605 */
df0e9248 9606struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9607{
df0e9248
CW		 9608 return &intel_attached_encoder(connector)->base;
9609}
f1c79df3 9610
df0e9248
CW		 9611void intel_connector_attach_encoder(struct intel_connector *connector,
9612 struct intel_encoder *encoder)
9613{
9614 connector->encoder = encoder;
9615 drm_mode_connector_attach_encoder(&connector->base,
9616 &encoder->base);
79e53945 9617}
28d52043
DA		 9618
9619/*
9620 * set vga decode state - true == enable VGA decode
9621 */
9622int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9623{
9624 struct drm_i915_private *dev_priv = dev->dev_private;
9625 u16 gmch_ctrl;
9626
9627 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9628 if (state)
9629 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9630 else
9631 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9632 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9633 return 0;
9634}
c4a1d9e4
CW		 9635
9636#ifdef CONFIG_DEBUG_FS
9637#include <linux/seq_file.h>
9638
9639struct intel_display_error_state {
9640 struct intel_cursor_error_state {
9641 u32 control;
9642 u32 position;
9643 u32 base;
9644 u32 size;
52331309 9645 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9646
9647 struct intel_pipe_error_state {
9648 u32 conf;
9649 u32 source;
9650
9651 u32 htotal;
9652 u32 hblank;
9653 u32 hsync;
9654 u32 vtotal;
9655 u32 vblank;
9656 u32 vsync;
52331309 9657 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9658
9659 struct intel_plane_error_state {
9660 u32 control;
9661 u32 stride;
9662 u32 size;
9663 u32 pos;
9664 u32 addr;
9665 u32 surface;
9666 u32 tile_offset;
52331309 9667 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9668};
9669
9670struct intel_display_error_state *
9671intel_display_capture_error_state(struct drm_device *dev)
9672{
0206e353 9673 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9674 struct intel_display_error_state *error;
702e7a56 9675 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9676 int i;
9677
9678 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9679 if (error == NULL)
9680 return NULL;
9681
52331309 9682 for_each_pipe(i) {
702e7a56
PZ		 9683 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9684
a18c4c3d
PZ		 9685 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9686 error->cursor[i].control = I915_READ(CURCNTR(i));
9687 error->cursor[i].position = I915_READ(CURPOS(i));
9688 error->cursor[i].base = I915_READ(CURBASE(i));
9689 } else {
9690 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9691 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9692 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9693 }
c4a1d9e4
CW		 9694
9695 error->plane[i].control = I915_READ(DSPCNTR(i));
9696 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9697 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9698 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9699 error->plane[i].pos = I915_READ(DSPPOS(i));
9700 }
ca291363
PZ		 9701 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9702 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9703 if (INTEL_INFO(dev)->gen >= 4) {
9704 error->plane[i].surface = I915_READ(DSPSURF(i));
9705 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9706 }
9707
702e7a56 9708 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9709 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9710 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9711 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9712 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9713 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9714 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9715 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9716 }
9717
9718 return error;
9719}
9720
9721void
9722intel_display_print_error_state(struct seq_file *m,
9723 struct drm_device *dev,
9724 struct intel_display_error_state *error)
9725{
9726 int i;
9727
7eb552ae 9728 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9729 for_each_pipe(i) {
c4a1d9e4
CW		 9730 seq_printf(m, "Pipe [%d]:\n", i);
9731 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9732 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9733 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9734 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9735 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9736 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9737 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9738 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9739
9740 seq_printf(m, "Plane [%d]:\n", i);
9741 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9742 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9743 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9744 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9745 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9746 }
4b71a570 9747 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9748 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9749 if (INTEL_INFO(dev)->gen >= 4) {
9750 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9751 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9752 }
9753
9754 seq_printf(m, "Cursor [%d]:\n", i);
9755 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9756 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9757 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9758 }
9759}
9760#endif
Linux kernel - Deliverables
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