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drm/i915: make SDVO TV-out work for multifunction devices
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
f4808ab8
VS		 62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
d4906093 80};
79e53945 81
2377b741
JB		 82/* FDI */
83#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
d2acd215
DV		 85int
86intel_pch_rawclk(struct drm_device *dev)
87{
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93}
94
d4906093
ML		 95static bool
96intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
d4906093
ML		 99static bool
100intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
79e53945 103
a0c4da24
JB		 104static bool
105intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
021357ac
CW		 109static inline u32 /* units of 100MHz */
110intel_fdi_link_freq(struct drm_device *dev)
111{
8b99e68c
CW		 112 if (IS_GEN5(dev)) {
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
115 } else
116 return 27;
021357ac
CW		 117}
118
e4b36699 119static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
d4906093 130 .find_pll = intel_find_best_PLL,
e4b36699
KP		 131};
132
133static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
d4906093 144 .find_pll = intel_find_best_PLL,
e4b36699 145};
273e27ca 146
e4b36699 147static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
d4906093 158 .find_pll = intel_find_best_PLL,
e4b36699
KP		 159};
160
161static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
d4906093 172 .find_pll = intel_find_best_PLL,
e4b36699
KP		 173};
174
273e27ca 175
e4b36699 176static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
186 .p2_slow = 10,
187 .p2_fast = 10
044c7c41 188 },
d4906093 189 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 190};
191
192static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
d4906093 203 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 204};
205
206static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
044c7c41 217 },
d4906093 218 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 219};
220
221static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
044c7c41 232 },
d4906093 233 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 234};
235
f2b115e6 236static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 239 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
273e27ca 242 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
6115707b 249 .find_pll = intel_find_best_PLL,
e4b36699
KP		 250};
251
f2b115e6 252static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
6115707b 263 .find_pll = intel_find_best_PLL,
e4b36699
KP		 264};
265
273e27ca
EA		 266/* Ironlake / Sandybridge
267 *
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
270 */
b91ad0ec 271static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
4547668a 282 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 283};
284
b91ad0ec 285static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 296 .find_pll = intel_g4x_find_best_PLL,
297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 310 .find_pll = intel_g4x_find_best_PLL,
311};
312
273e27ca 313/* LVDS 100mhz refclk limits. */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
0206e353 322 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 325 .find_pll = intel_g4x_find_best_PLL,
326};
327
328static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
0206e353 336 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 339 .find_pll = intel_g4x_find_best_PLL,
340};
341
a0c4da24
JB		 342static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
75e53986 350 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
354};
355
356static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
368};
369
370static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 373 .n = { .min = 1, .max = 7 },
74a4dd2e 374 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
75e53986 378 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
382};
383
57f350b6
JB		 384u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
385{
09153000 386 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 387
57f350b6
JB		 388 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
389 DRM_ERROR("DPIO idle wait timed out\n");
09153000 390 return 0;
57f350b6
JB		 391 }
392
393 I915_WRITE(DPIO_REG, reg);
394 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
395 DPIO_BYTE);
396 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
397 DRM_ERROR("DPIO read wait timed out\n");
09153000 398 return 0;
57f350b6 399 }
57f350b6 400
09153000 401 return I915_READ(DPIO_DATA);
57f350b6
JB		 402}
403
e2fa6fba 404void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
a0c4da24 405{
09153000 406 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 407
a0c4da24
JB		 408 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
409 DRM_ERROR("DPIO idle wait timed out\n");
09153000 410 return;
a0c4da24
JB		 411 }
412
413 I915_WRITE(DPIO_DATA, val);
414 I915_WRITE(DPIO_REG, reg);
415 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
416 DPIO_BYTE);
417 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
418 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 419}
420
1b894b59
CW		 421static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
422 int refclk)
2c07245f 423{
b91ad0ec 424 struct drm_device *dev = crtc->dev;
2c07245f 425 const intel_limit_t *limit;
b91ad0ec
ZW		 426
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 428 if (intel_is_dual_link_lvds(dev)) {
1b894b59 429 if (refclk == 100000)
b91ad0ec
ZW		 430 limit = &intel_limits_ironlake_dual_lvds_100m;
431 else
432 limit = &intel_limits_ironlake_dual_lvds;
433 } else {
1b894b59 434 if (refclk == 100000)
b91ad0ec
ZW		 435 limit = &intel_limits_ironlake_single_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_single_lvds;
438 }
c6bb3538 439 } else
b91ad0ec 440 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 441
442 return limit;
443}
444
044c7c41
ML		 445static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
446{
447 struct drm_device *dev = crtc->dev;
044c7c41
ML		 448 const intel_limit_t *limit;
449
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 451 if (intel_is_dual_link_lvds(dev))
e4b36699 452 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 453 else
e4b36699 454 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
456 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 457 limit = &intel_limits_g4x_hdmi;
044c7c41 458 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 459 limit = &intel_limits_g4x_sdvo;
044c7c41 460 } else /* The option is for other outputs */
e4b36699 461 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 462
463 return limit;
464}
465
1b894b59 466static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 467{
468 struct drm_device *dev = crtc->dev;
469 const intel_limit_t *limit;
470
bad720ff 471 if (HAS_PCH_SPLIT(dev))
1b894b59 472 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 473 else if (IS_G4X(dev)) {
044c7c41 474 limit = intel_g4x_limit(crtc);
f2b115e6 475 } else if (IS_PINEVIEW(dev)) {
2177832f 476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 477 limit = &intel_limits_pineview_lvds;
2177832f 478 else
f2b115e6 479 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 480 } else if (IS_VALLEYVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
482 limit = &intel_limits_vlv_dac;
483 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
484 limit = &intel_limits_vlv_hdmi;
485 else
486 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 487 } else if (!IS_GEN2(dev)) {
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
489 limit = &intel_limits_i9xx_lvds;
490 else
491 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 492 } else {
493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 494 limit = &intel_limits_i8xx_lvds;
79e53945 495 else
e4b36699 496 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 497 }
498 return limit;
499}
500
f2b115e6
AJ		 501/* m1 is reserved as 0 in Pineview, n is a ring counter */
502static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 503{
2177832f
SL		 504 clock->m = clock->m2 + 2;
505 clock->p = clock->p1 * clock->p2;
506 clock->vco = refclk * clock->m / clock->n;
507 clock->dot = clock->vco / clock->p;
508}
509
7429e9d4
DV		 510static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
511{
512 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
513}
514
2177832f
SL		 515static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
516{
f2b115e6
AJ		 517 if (IS_PINEVIEW(dev)) {
518 pineview_clock(refclk, clock);
2177832f
SL		 519 return;
520 }
7429e9d4 521 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 522 clock->p = clock->p1 * clock->p2;
523 clock->vco = refclk * clock->m / (clock->n + 2);
524 clock->dot = clock->vco / clock->p;
525}
526
79e53945
JB		 527/**
528 * Returns whether any output on the specified pipe is of the specified type
529 */
4ef69c7a 530bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 531{
4ef69c7a 532 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 533 struct intel_encoder *encoder;
534
6c2b7c12
DV		 535 for_each_encoder_on_crtc(dev, crtc, encoder)
536 if (encoder->type == type)
4ef69c7a
CW		 537 return true;
538
539 return false;
79e53945
JB		 540}
541
7c04d1d9 542#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 543/**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
1b894b59
CW		 548static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
79e53945 551{
79e53945 552 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 553 INTELPllInvalid("p1 out of range\n");
79e53945 554 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 555 INTELPllInvalid("p out of range\n");
79e53945 556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 557 INTELPllInvalid("m2 out of range\n");
79e53945 558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 559 INTELPllInvalid("m1 out of range\n");
f2b115e6 560 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 561 INTELPllInvalid("m1 <= m2\n");
79e53945 562 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 563 INTELPllInvalid("m out of range\n");
79e53945 564 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 565 INTELPllInvalid("n out of range\n");
79e53945 566 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 567 INTELPllInvalid("vco out of range\n");
79e53945
JB		 568 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
569 * connector, etc., rather than just a single range.
570 */
571 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 572 INTELPllInvalid("dot out of range\n");
79e53945
JB		 573
574 return true;
575}
576
d4906093
ML		 577static bool
578intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 579 int target, int refclk, intel_clock_t *match_clock,
580 intel_clock_t *best_clock)
d4906093 581
79e53945
JB		 582{
583 struct drm_device *dev = crtc->dev;
79e53945 584 intel_clock_t clock;
79e53945
JB		 585 int err = target;
586
a210b028 587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 588 /*
a210b028
DV		 589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
79e53945 592 */
1974cad0 593 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 594 clock.p2 = limit->p2.p2_fast;
595 else
596 clock.p2 = limit->p2.p2_slow;
597 } else {
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
600 else
601 clock.p2 = limit->p2.p2_fast;
602 }
603
0206e353 604 memset(best_clock, 0, sizeof(*best_clock));
79e53945 605
42158660
ZY		 606 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
607 clock.m1++) {
608 for (clock.m2 = limit->m2.min;
609 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 610 /* m1 is always 0 in Pineview */
611 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 612 break;
613 for (clock.n = limit->n.min;
614 clock.n <= limit->n.max; clock.n++) {
615 for (clock.p1 = limit->p1.min;
616 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 617 int this_err;
618
2177832f 619 intel_clock(dev, refclk, &clock);
1b894b59
CW		 620 if (!intel_PLL_is_valid(dev, limit,
621 &clock))
79e53945 622 continue;
cec2f356
SP		 623 if (match_clock &&
624 clock.p != match_clock->p)
625 continue;
79e53945
JB		 626
627 this_err = abs(clock.dot - target);
628 if (this_err < err) {
629 *best_clock = clock;
630 err = this_err;
631 }
632 }
633 }
634 }
635 }
636
637 return (err != target);
638}
639
d4906093
ML		 640static bool
641intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
d4906093
ML		 644{
645 struct drm_device *dev = crtc->dev;
d4906093
ML		 646 intel_clock_t clock;
647 int max_n;
648 bool found;
6ba770dc
AJ		 649 /* approximately equals target * 0.00585 */
650 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 651 found = false;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 654 int lvds_reg;
655
c619eed4 656 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 657 lvds_reg = PCH_LVDS;
658 else
659 lvds_reg = LVDS;
1974cad0 660 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 661 clock.p2 = limit->p2.p2_fast;
662 else
663 clock.p2 = limit->p2.p2_slow;
664 } else {
665 if (target < limit->p2.dot_limit)
666 clock.p2 = limit->p2.p2_slow;
667 else
668 clock.p2 = limit->p2.p2_fast;
669 }
670
671 memset(best_clock, 0, sizeof(*best_clock));
672 max_n = limit->n.max;
f77f13e2 673 /* based on hardware requirement, prefer smaller n to precision */
d4906093 674 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 675 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 676 for (clock.m1 = limit->m1.max;
677 clock.m1 >= limit->m1.min; clock.m1--) {
678 for (clock.m2 = limit->m2.max;
679 clock.m2 >= limit->m2.min; clock.m2--) {
680 for (clock.p1 = limit->p1.max;
681 clock.p1 >= limit->p1.min; clock.p1--) {
682 int this_err;
683
2177832f 684 intel_clock(dev, refclk, &clock);
1b894b59
CW		 685 if (!intel_PLL_is_valid(dev, limit,
686 &clock))
d4906093 687 continue;
1b894b59
CW		 688
689 this_err = abs(clock.dot - target);
d4906093
ML		 690 if (this_err < err_most) {
691 *best_clock = clock;
692 err_most = this_err;
693 max_n = clock.n;
694 found = true;
695 }
696 }
697 }
698 }
699 }
2c07245f
ZW		 700 return found;
701}
702
a0c4da24
JB		 703static bool
704intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707{
708 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
709 u32 m, n, fastclk;
710 u32 updrate, minupdate, fracbits, p;
711 unsigned long bestppm, ppm, absppm;
712 int dotclk, flag;
713
af447bd3 714 flag = 0;
a0c4da24
JB		 715 dotclk = target * 1000;
716 bestppm = 1000000;
717 ppm = absppm = 0;
718 fastclk = dotclk / (2*100);
719 updrate = 0;
720 minupdate = 19200;
721 fracbits = 1;
722 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
723 bestm1 = bestm2 = bestp1 = bestp2 = 0;
724
725 /* based on hardware requirement, prefer smaller n to precision */
726 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
727 updrate = refclk / n;
728 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
729 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
730 if (p2 > 10)
731 p2 = p2 - 1;
732 p = p1 * p2;
733 /* based on hardware requirement, prefer bigger m1,m2 values */
734 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
735 m2 = (((2*(fastclk * p * n / m1 )) +
736 refclk) / (2*refclk));
737 m = m1 * m2;
738 vco = updrate * m;
739 if (vco >= limit->vco.min && vco < limit->vco.max) {
740 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
741 absppm = (ppm > 0) ? ppm : (-ppm);
742 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
743 bestppm = 0;
744 flag = 1;
745 }
746 if (absppm < bestppm - 10) {
747 bestppm = absppm;
748 flag = 1;
749 }
750 if (flag) {
751 bestn = n;
752 bestm1 = m1;
753 bestm2 = m2;
754 bestp1 = p1;
755 bestp2 = p2;
756 flag = 0;
757 }
758 }
759 }
760 }
761 }
762 }
763 best_clock->n = bestn;
764 best_clock->m1 = bestm1;
765 best_clock->m2 = bestm2;
766 best_clock->p1 = bestp1;
767 best_clock->p2 = bestp2;
768
769 return true;
770}
a4fc5ed6 771
a5c961d1
PZ		 772enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
773 enum pipe pipe)
774{
775 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
777
3b117c8f 778 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 779}
780
a928d536
PZ		 781static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
782{
783 struct drm_i915_private *dev_priv = dev->dev_private;
784 u32 frame, frame_reg = PIPEFRAME(pipe);
785
786 frame = I915_READ(frame_reg);
787
788 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
789 DRM_DEBUG_KMS("vblank wait timed out\n");
790}
791
9d0498a2
JB		 792/**
793 * intel_wait_for_vblank - wait for vblank on a given pipe
794 * @dev: drm device
795 * @pipe: pipe to wait for
796 *
797 * Wait for vblank to occur on a given pipe. Needed for various bits of
798 * mode setting code.
799 */
800void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 801{
9d0498a2 802 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 803 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 804
a928d536
PZ		 805 if (INTEL_INFO(dev)->gen >= 5) {
806 ironlake_wait_for_vblank(dev, pipe);
807 return;
808 }
809
300387c0
CW		 810 /* Clear existing vblank status. Note this will clear any other
811 * sticky status fields as well.
812 *
813 * This races with i915_driver_irq_handler() with the result
814 * that either function could miss a vblank event. Here it is not
815 * fatal, as we will either wait upon the next vblank interrupt or
816 * timeout. Generally speaking intel_wait_for_vblank() is only
817 * called during modeset at which time the GPU should be idle and
818 * should *not* be performing page flips and thus not waiting on
819 * vblanks...
820 * Currently, the result of us stealing a vblank from the irq
821 * handler is that a single frame will be skipped during swapbuffers.
822 */
823 I915_WRITE(pipestat_reg,
824 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
825
9d0498a2 826 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 827 if (wait_for(I915_READ(pipestat_reg) &
828 PIPE_VBLANK_INTERRUPT_STATUS,
829 50))
9d0498a2
JB		 830 DRM_DEBUG_KMS("vblank wait timed out\n");
831}
832
ab7ad7f6
KP		 833/*
834 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 835 * @dev: drm device
836 * @pipe: pipe to wait for
837 *
838 * After disabling a pipe, we can't wait for vblank in the usual way,
839 * spinning on the vblank interrupt status bit, since we won't actually
840 * see an interrupt when the pipe is disabled.
841 *
ab7ad7f6
KP		 842 * On Gen4 and above:
843 * wait for the pipe register state bit to turn off
844 *
845 * Otherwise:
846 * wait for the display line value to settle (it usually
847 * ends up stopping at the start of the next frame).
58e10eb9 848 *
9d0498a2 849 */
58e10eb9 850void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 851{
852 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 853 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
854 pipe);
ab7ad7f6
KP		 855
856 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 857 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 858
859 /* Wait for the Pipe State to go off */
58e10eb9
CW		 860 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
861 100))
284637d9 862 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 863 } else {
837ba00f 864 u32 last_line, line_mask;
58e10eb9 865 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 866 unsigned long timeout = jiffies + msecs_to_jiffies(100);
867
837ba00f
PZ		 868 if (IS_GEN2(dev))
869 line_mask = DSL_LINEMASK_GEN2;
870 else
871 line_mask = DSL_LINEMASK_GEN3;
872
ab7ad7f6
KP		 873 /* Wait for the display line to settle */
874 do {
837ba00f 875 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 876 mdelay(5);
837ba00f 877 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 878 time_after(timeout, jiffies));
879 if (time_after(jiffies, timeout))
284637d9 880 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 881 }
79e53945
JB		 882}
883
b0ea7d37
DL		 884/*
885 * ibx_digital_port_connected - is the specified port connected?
886 * @dev_priv: i915 private structure
887 * @port: the port to test
888 *
889 * Returns true if @port is connected, false otherwise.
890 */
891bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
892 struct intel_digital_port *port)
893{
894 u32 bit;
895
c36346e3
DL		 896 if (HAS_PCH_IBX(dev_priv->dev)) {
897 switch(port->port) {
898 case PORT_B:
899 bit = SDE_PORTB_HOTPLUG;
900 break;
901 case PORT_C:
902 bit = SDE_PORTC_HOTPLUG;
903 break;
904 case PORT_D:
905 bit = SDE_PORTD_HOTPLUG;
906 break;
907 default:
908 return true;
909 }
910 } else {
911 switch(port->port) {
912 case PORT_B:
913 bit = SDE_PORTB_HOTPLUG_CPT;
914 break;
915 case PORT_C:
916 bit = SDE_PORTC_HOTPLUG_CPT;
917 break;
918 case PORT_D:
919 bit = SDE_PORTD_HOTPLUG_CPT;
920 break;
921 default:
922 return true;
923 }
b0ea7d37
DL		 924 }
925
926 return I915_READ(SDEISR) & bit;
927}
928
b24e7179
JB		 929static const char *state_string(bool enabled)
930{
931 return enabled ? "on" : "off";
932}
933
934/* Only for pre-ILK configs */
935static void assert_pll(struct drm_i915_private *dev_priv,
936 enum pipe pipe, bool state)
937{
938 int reg;
939 u32 val;
940 bool cur_state;
941
942 reg = DPLL(pipe);
943 val = I915_READ(reg);
944 cur_state = !!(val & DPLL_VCO_ENABLE);
945 WARN(cur_state != state,
946 "PLL state assertion failure (expected %s, current %s)\n",
947 state_string(state), state_string(cur_state));
948}
949#define assert_pll_enabled(d, p) assert_pll(d, p, true)
950#define assert_pll_disabled(d, p) assert_pll(d, p, false)
951
040484af
JB		 952/* For ILK+ */
953static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 954 struct intel_pch_pll *pll,
955 struct intel_crtc *crtc,
956 bool state)
040484af 957{
040484af
JB		 958 u32 val;
959 bool cur_state;
960
9d82aa17
ED		 961 if (HAS_PCH_LPT(dev_priv->dev)) {
962 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
963 return;
964 }
965
92b27b08
CW		 966 if (WARN (!pll,
967 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 968 return;
ee7b9f93 969
92b27b08
CW		 970 val = I915_READ(pll->pll_reg);
971 cur_state = !!(val & DPLL_VCO_ENABLE);
972 WARN(cur_state != state,
973 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
974 pll->pll_reg, state_string(state), state_string(cur_state), val);
975
976 /* Make sure the selected PLL is correctly attached to the transcoder */
977 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 978 u32 pch_dpll;
979
980 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 981 cur_state = pll->pll_reg == _PCH_DPLL_B;
982 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 983 "PLL[%d] not attached to this transcoder %c: %08x\n",
984 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 985 cur_state = !!(val >> (4*crtc->pipe + 3));
986 WARN(cur_state != state,
4bb6f1f3 987 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 988 pll->pll_reg == _PCH_DPLL_B,
989 state_string(state),
4bb6f1f3 990 pipe_name(crtc->pipe),
92b27b08
CW		 991 val);
992 }
d3ccbe86 993 }
040484af 994}
92b27b08
CW		 995#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
996#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 997
998static void assert_fdi_tx(struct drm_i915_private *dev_priv,
999 enum pipe pipe, bool state)
1000{
1001 int reg;
1002 u32 val;
1003 bool cur_state;
ad80a810
PZ		 1004 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1005 pipe);
040484af 1006
affa9354
PZ		 1007 if (HAS_DDI(dev_priv->dev)) {
1008 /* DDI does not have a specific FDI_TX register */
ad80a810 1009 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1010 val = I915_READ(reg);
ad80a810 1011 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1012 } else {
1013 reg = FDI_TX_CTL(pipe);
1014 val = I915_READ(reg);
1015 cur_state = !!(val & FDI_TX_ENABLE);
1016 }
040484af
JB		 1017 WARN(cur_state != state,
1018 "FDI TX state assertion failure (expected %s, current %s)\n",
1019 state_string(state), state_string(cur_state));
1020}
1021#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1022#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1023
1024static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, bool state)
1026{
1027 int reg;
1028 u32 val;
1029 bool cur_state;
1030
d63fa0dc
PZ		 1031 reg = FDI_RX_CTL(pipe);
1032 val = I915_READ(reg);
1033 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1034 WARN(cur_state != state,
1035 "FDI RX state assertion failure (expected %s, current %s)\n",
1036 state_string(state), state_string(cur_state));
1037}
1038#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1039#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1040
1041static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1042 enum pipe pipe)
1043{
1044 int reg;
1045 u32 val;
1046
1047 /* ILK FDI PLL is always enabled */
1048 if (dev_priv->info->gen == 5)
1049 return;
1050
bf507ef7 1051 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1052 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1053 return;
1054
040484af
JB		 1055 reg = FDI_TX_CTL(pipe);
1056 val = I915_READ(reg);
1057 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1058}
1059
1060static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int reg;
1064 u32 val;
1065
1066 reg = FDI_RX_CTL(pipe);
1067 val = I915_READ(reg);
1068 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1069}
1070
ea0760cf
JB		 1071static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1072 enum pipe pipe)
1073{
1074 int pp_reg, lvds_reg;
1075 u32 val;
1076 enum pipe panel_pipe = PIPE_A;
0de3b485 1077 bool locked = true;
ea0760cf
JB		 1078
1079 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1080 pp_reg = PCH_PP_CONTROL;
1081 lvds_reg = PCH_LVDS;
1082 } else {
1083 pp_reg = PP_CONTROL;
1084 lvds_reg = LVDS;
1085 }
1086
1087 val = I915_READ(pp_reg);
1088 if (!(val & PANEL_POWER_ON) ||
1089 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1090 locked = false;
1091
1092 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1093 panel_pipe = PIPE_B;
1094
1095 WARN(panel_pipe == pipe && locked,
1096 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1097 pipe_name(pipe));
ea0760cf
JB		 1098}
1099
b840d907
JB		 1100void assert_pipe(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
b24e7179
JB		 1102{
1103 int reg;
1104 u32 val;
63d7bbe9 1105 bool cur_state;
702e7a56
PZ		 1106 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1107 pipe);
b24e7179 1108
8e636784
DV		 1109 /* if we need the pipe A quirk it must be always on */
1110 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1111 state = true;
1112
b97186f0
PZ		 1113 if (!intel_display_power_enabled(dev_priv->dev,
1114 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1115 cur_state = false;
1116 } else {
1117 reg = PIPECONF(cpu_transcoder);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & PIPECONF_ENABLE);
1120 }
1121
63d7bbe9
JB		 1122 WARN(cur_state != state,
1123 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1124 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1125}
1126
931872fc
CW		 1127static void assert_plane(struct drm_i915_private *dev_priv,
1128 enum plane plane, bool state)
b24e7179
JB		 1129{
1130 int reg;
1131 u32 val;
931872fc 1132 bool cur_state;
b24e7179
JB		 1133
1134 reg = DSPCNTR(plane);
1135 val = I915_READ(reg);
931872fc
CW		 1136 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1137 WARN(cur_state != state,
1138 "plane %c assertion failure (expected %s, current %s)\n",
1139 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1140}
1141
931872fc
CW		 1142#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1143#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1144
b24e7179
JB		 1145static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
1148 int reg, i;
1149 u32 val;
1150 int cur_pipe;
1151
19ec1358 1152 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1153 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1154 reg = DSPCNTR(pipe);
1155 val = I915_READ(reg);
1156 WARN((val & DISPLAY_PLANE_ENABLE),
1157 "plane %c assertion failure, should be disabled but not\n",
1158 plane_name(pipe));
19ec1358 1159 return;
28c05794 1160 }
19ec1358 1161
b24e7179
JB		 1162 /* Need to check both planes against the pipe */
1163 for (i = 0; i < 2; i++) {
1164 reg = DSPCNTR(i);
1165 val = I915_READ(reg);
1166 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1167 DISPPLANE_SEL_PIPE_SHIFT;
1168 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1169 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1170 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1171 }
1172}
1173
19332d7a
JB		 1174static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1175 enum pipe pipe)
1176{
1177 int reg, i;
1178 u32 val;
1179
1180 if (!IS_VALLEYVIEW(dev_priv->dev))
1181 return;
1182
1183 /* Need to check both planes against the pipe */
1184 for (i = 0; i < dev_priv->num_plane; i++) {
1185 reg = SPCNTR(pipe, i);
1186 val = I915_READ(reg);
1187 WARN((val & SP_ENABLE),
06da8da2
VS		 1188 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1189 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1190 }
1191}
1192
92f2584a
JB		 1193static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1194{
1195 u32 val;
1196 bool enabled;
1197
9d82aa17
ED		 1198 if (HAS_PCH_LPT(dev_priv->dev)) {
1199 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1200 return;
1201 }
1202
92f2584a
JB		 1203 val = I915_READ(PCH_DREF_CONTROL);
1204 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1205 DREF_SUPERSPREAD_SOURCE_MASK));
1206 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1207}
1208
ab9412ba
DV		 1209static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
92f2584a
JB		 1211{
1212 int reg;
1213 u32 val;
1214 bool enabled;
1215
ab9412ba 1216 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1217 val = I915_READ(reg);
1218 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1219 WARN(enabled,
1220 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1221 pipe_name(pipe));
92f2584a
JB		 1222}
1223
4e634389
KP		 1224static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1226{
1227 if ((val & DP_PORT_EN) == 0)
1228 return false;
1229
1230 if (HAS_PCH_CPT(dev_priv->dev)) {
1231 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1232 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1233 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1234 return false;
1235 } else {
1236 if ((val & DP_PIPE_MASK) != (pipe << 30))
1237 return false;
1238 }
1239 return true;
1240}
1241
1519b995
KP		 1242static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 val)
1244{
dc0fa718 1245 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1246 return false;
1247
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1249 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1250 return false;
1251 } else {
dc0fa718 1252 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1253 return false;
1254 }
1255 return true;
1256}
1257
1258static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, u32 val)
1260{
1261 if ((val & LVDS_PORT_EN) == 0)
1262 return false;
1263
1264 if (HAS_PCH_CPT(dev_priv->dev)) {
1265 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1266 return false;
1267 } else {
1268 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1269 return false;
1270 }
1271 return true;
1272}
1273
1274static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, u32 val)
1276{
1277 if ((val & ADPA_DAC_ENABLE) == 0)
1278 return false;
1279 if (HAS_PCH_CPT(dev_priv->dev)) {
1280 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281 return false;
1282 } else {
1283 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1284 return false;
1285 }
1286 return true;
1287}
1288
291906f1 1289static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1290 enum pipe pipe, int reg, u32 port_sel)
291906f1 1291{
47a05eca 1292 u32 val = I915_READ(reg);
4e634389 1293 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1294 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1295 reg, pipe_name(pipe));
de9a35ab 1296
75c5da27
DV		 1297 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1298 && (val & DP_PIPEB_SELECT),
de9a35ab 1299 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1300}
1301
1302static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1303 enum pipe pipe, int reg)
1304{
47a05eca 1305 u32 val = I915_READ(reg);
b70ad586 1306 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1307 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1308 reg, pipe_name(pipe));
de9a35ab 1309
dc0fa718 1310 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1311 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1312 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1313}
1314
1315static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1316 enum pipe pipe)
1317{
1318 int reg;
1319 u32 val;
291906f1 1320
f0575e92
KP		 1321 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1322 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1323 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1324
1325 reg = PCH_ADPA;
1326 val = I915_READ(reg);
b70ad586 1327 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1328 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 pipe_name(pipe));
291906f1
JB		 1330
1331 reg = PCH_LVDS;
1332 val = I915_READ(reg);
b70ad586 1333 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1334 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1335 pipe_name(pipe));
291906f1 1336
e2debe91
PZ		 1337 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1338 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1339 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1340}
1341
63d7bbe9
JB		 1342/**
1343 * intel_enable_pll - enable a PLL
1344 * @dev_priv: i915 private structure
1345 * @pipe: pipe PLL to enable
1346 *
1347 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1348 * make sure the PLL reg is writable first though, since the panel write
1349 * protect mechanism may be enabled.
1350 *
1351 * Note! This is for pre-ILK only.
7434a255
TR		 1352 *
1353 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1354 */
1355static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1356{
1357 int reg;
1358 u32 val;
1359
58c6eaa2
DV		 1360 assert_pipe_disabled(dev_priv, pipe);
1361
63d7bbe9 1362 /* No really, not for ILK+ */
a0c4da24 1363 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1364
1365 /* PLL is protected by panel, make sure we can write it */
1366 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1367 assert_panel_unlocked(dev_priv, pipe);
1368
1369 reg = DPLL(pipe);
1370 val = I915_READ(reg);
1371 val |= DPLL_VCO_ENABLE;
1372
1373 /* We do this three times for luck */
1374 I915_WRITE(reg, val);
1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
1377 I915_WRITE(reg, val);
1378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
1380 I915_WRITE(reg, val);
1381 POSTING_READ(reg);
1382 udelay(150); /* wait for warmup */
1383}
1384
1385/**
1386 * intel_disable_pll - disable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to disable
1389 *
1390 * Disable the PLL for @pipe, making sure the pipe is off first.
1391 *
1392 * Note! This is for pre-ILK only.
1393 */
1394static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395{
1396 int reg;
1397 u32 val;
1398
1399 /* Don't disable pipe A or pipe A PLLs if needed */
1400 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401 return;
1402
1403 /* Make sure the pipe isn't still relying on us */
1404 assert_pipe_disabled(dev_priv, pipe);
1405
1406 reg = DPLL(pipe);
1407 val = I915_READ(reg);
1408 val &= ~DPLL_VCO_ENABLE;
1409 I915_WRITE(reg, val);
1410 POSTING_READ(reg);
1411}
1412
a416edef
ED		 1413/* SBI access */
1414static void
988d6ee8
PZ		 1415intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1416 enum intel_sbi_destination destination)
a416edef 1417{
988d6ee8 1418 u32 tmp;
a416edef 1419
09153000 1420 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1421
39fb50f6 1422 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1423 100)) {
1424 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1425 return;
a416edef
ED		 1426 }
1427
988d6ee8
PZ		 1428 I915_WRITE(SBI_ADDR, (reg << 16));
1429 I915_WRITE(SBI_DATA, value);
1430
1431 if (destination == SBI_ICLK)
1432 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1433 else
1434 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1435 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1436
39fb50f6 1437 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1438 100)) {
1439 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1440 return;
a416edef 1441 }
a416edef
ED		 1442}
1443
1444static u32
988d6ee8
PZ		 1445intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1446 enum intel_sbi_destination destination)
a416edef 1447{
39fb50f6 1448 u32 value = 0;
09153000 1449 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1450
39fb50f6 1451 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1452 100)) {
1453 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1454 return 0;
a416edef
ED		 1455 }
1456
988d6ee8
PZ		 1457 I915_WRITE(SBI_ADDR, (reg << 16));
1458
1459 if (destination == SBI_ICLK)
1460 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1461 else
1462 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1463 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1464
39fb50f6 1465 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1466 100)) {
1467 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1468 return 0;
a416edef
ED		 1469 }
1470
09153000 1471 return I915_READ(SBI_DATA);
a416edef
ED		 1472}
1473
89b667f8
JB		 1474void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1475{
1476 u32 port_mask;
1477
1478 if (!port)
1479 port_mask = DPLL_PORTB_READY_MASK;
1480 else
1481 port_mask = DPLL_PORTC_READY_MASK;
1482
1483 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1484 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1485 'B' + port, I915_READ(DPLL(0)));
1486}
1487
92f2584a 1488/**
b6b4e185 1489 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1490 * @dev_priv: i915 private structure
1491 * @pipe: pipe PLL to enable
1492 *
1493 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1494 * drives the transcoder clock.
1495 */
b6b4e185 1496static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1497{
ee7b9f93 1498 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1499 struct intel_pch_pll *pll;
92f2584a
JB		 1500 int reg;
1501 u32 val;
1502
48da64a8 1503 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1504 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1505 pll = intel_crtc->pch_pll;
1506 if (pll == NULL)
1507 return;
1508
1509 if (WARN_ON(pll->refcount == 0))
1510 return;
ee7b9f93
JB		 1511
1512 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1513 pll->pll_reg, pll->active, pll->on,
1514 intel_crtc->base.base.id);
92f2584a
JB		 1515
1516 /* PCH refclock must be enabled first */
1517 assert_pch_refclk_enabled(dev_priv);
1518
ee7b9f93 1519 if (pll->active++ && pll->on) {
92b27b08 1520 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1521 return;
1522 }
1523
1524 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1525
1526 reg = pll->pll_reg;
92f2584a
JB		 1527 val = I915_READ(reg);
1528 val |= DPLL_VCO_ENABLE;
1529 I915_WRITE(reg, val);
1530 POSTING_READ(reg);
1531 udelay(200);
ee7b9f93
JB		 1532
1533 pll->on = true;
92f2584a
JB		 1534}
1535
ee7b9f93 1536static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1537{
ee7b9f93
JB		 1538 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1539 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1540 int reg;
ee7b9f93 1541 u32 val;
4c609cb8 1542
92f2584a
JB		 1543 /* PCH only available on ILK+ */
1544 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1545 if (pll == NULL)
1546 return;
92f2584a 1547
48da64a8
CW		 1548 if (WARN_ON(pll->refcount == 0))
1549 return;
7a419866 1550
ee7b9f93
JB		 1551 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1552 pll->pll_reg, pll->active, pll->on,
1553 intel_crtc->base.base.id);
7a419866 1554
48da64a8 1555 if (WARN_ON(pll->active == 0)) {
92b27b08 1556 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1557 return;
1558 }
1559
ee7b9f93 1560 if (--pll->active) {
92b27b08 1561 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1562 return;
ee7b9f93
JB		 1563 }
1564
1565 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1566
1567 /* Make sure transcoder isn't still depending on us */
ab9412ba 1568 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1569
ee7b9f93 1570 reg = pll->pll_reg;
92f2584a
JB		 1571 val = I915_READ(reg);
1572 val &= ~DPLL_VCO_ENABLE;
1573 I915_WRITE(reg, val);
1574 POSTING_READ(reg);
1575 udelay(200);
ee7b9f93
JB		 1576
1577 pll->on = false;
92f2584a
JB		 1578}
1579
b8a4f404
PZ		 1580static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581 enum pipe pipe)
040484af 1582{
23670b32 1583 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1584 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1585 uint32_t reg, val, pipeconf_val;
040484af
JB		 1586
1587 /* PCH only available on ILK+ */
1588 BUG_ON(dev_priv->info->gen < 5);
1589
1590 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1591 assert_pch_pll_enabled(dev_priv,
1592 to_intel_crtc(crtc)->pch_pll,
1593 to_intel_crtc(crtc));
040484af
JB		 1594
1595 /* FDI must be feeding us bits for PCH ports */
1596 assert_fdi_tx_enabled(dev_priv, pipe);
1597 assert_fdi_rx_enabled(dev_priv, pipe);
1598
23670b32
DV		 1599 if (HAS_PCH_CPT(dev)) {
1600 /* Workaround: Set the timing override bit before enabling the
1601 * pch transcoder. */
1602 reg = TRANS_CHICKEN2(pipe);
1603 val = I915_READ(reg);
1604 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605 I915_WRITE(reg, val);
59c859d6 1606 }
23670b32 1607
ab9412ba 1608 reg = PCH_TRANSCONF(pipe);
040484af 1609 val = I915_READ(reg);
5f7f726d 1610 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1611
1612 if (HAS_PCH_IBX(dev_priv->dev)) {
1613 /*
1614 * make the BPC in transcoder be consistent with
1615 * that in pipeconf reg.
1616 */
dfd07d72
DV		 1617 val &= ~PIPECONF_BPC_MASK;
1618 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1619 }
5f7f726d
PZ		 1620
1621 val &= ~TRANS_INTERLACE_MASK;
1622 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1623 if (HAS_PCH_IBX(dev_priv->dev) &&
1624 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625 val |= TRANS_LEGACY_INTERLACED_ILK;
1626 else
1627 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1628 else
1629 val |= TRANS_PROGRESSIVE;
1630
040484af
JB		 1631 I915_WRITE(reg, val | TRANS_ENABLE);
1632 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1633 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1634}
1635
8fb033d7 1636static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1637 enum transcoder cpu_transcoder)
040484af 1638{
8fb033d7 1639 u32 val, pipeconf_val;
8fb033d7
PZ		 1640
1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv->info->gen < 5);
1643
8fb033d7 1644 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1645 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1646 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1647
223a6fdf
PZ		 1648 /* Workaround: set timing override bit. */
1649 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1650 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1651 I915_WRITE(_TRANSA_CHICKEN2, val);
1652
25f3ef11 1653 val = TRANS_ENABLE;
937bb610 1654 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1655
9a76b1c6
PZ		 1656 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657 PIPECONF_INTERLACED_ILK)
a35f2679 1658 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1659 else
1660 val |= TRANS_PROGRESSIVE;
1661
ab9412ba
DV		 1662 I915_WRITE(LPT_TRANSCONF, val);
1663 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1664 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1665}
1666
b8a4f404
PZ		 1667static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668 enum pipe pipe)
040484af 1669{
23670b32
DV		 1670 struct drm_device *dev = dev_priv->dev;
1671 uint32_t reg, val;
040484af
JB		 1672
1673 /* FDI relies on the transcoder */
1674 assert_fdi_tx_disabled(dev_priv, pipe);
1675 assert_fdi_rx_disabled(dev_priv, pipe);
1676
291906f1
JB		 1677 /* Ports must be off as well */
1678 assert_pch_ports_disabled(dev_priv, pipe);
1679
ab9412ba 1680 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1681 val = I915_READ(reg);
1682 val &= ~TRANS_ENABLE;
1683 I915_WRITE(reg, val);
1684 /* wait for PCH transcoder off, transcoder state */
1685 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1686 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1687
1688 if (!HAS_PCH_IBX(dev)) {
1689 /* Workaround: Clear the timing override chicken bit again. */
1690 reg = TRANS_CHICKEN2(pipe);
1691 val = I915_READ(reg);
1692 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693 I915_WRITE(reg, val);
1694 }
040484af
JB		 1695}
1696
ab4d966c 1697static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1698{
8fb033d7
PZ		 1699 u32 val;
1700
ab9412ba 1701 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1702 val &= ~TRANS_ENABLE;
ab9412ba 1703 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1704 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1705 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1706 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1707
1708 /* Workaround: clear timing override bit. */
1709 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1710 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1711 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1712}
1713
b24e7179 1714/**
309cfea8 1715 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1716 * @dev_priv: i915 private structure
1717 * @pipe: pipe to enable
040484af 1718 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1719 *
1720 * Enable @pipe, making sure that various hardware specific requirements
1721 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722 *
1723 * @pipe should be %PIPE_A or %PIPE_B.
1724 *
1725 * Will wait until the pipe is actually running (i.e. first vblank) before
1726 * returning.
1727 */
040484af
JB		 1728static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729 bool pch_port)
b24e7179 1730{
702e7a56
PZ		 1731 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732 pipe);
1a240d4d 1733 enum pipe pch_transcoder;
b24e7179
JB		 1734 int reg;
1735 u32 val;
1736
58c6eaa2
DV		 1737 assert_planes_disabled(dev_priv, pipe);
1738 assert_sprites_disabled(dev_priv, pipe);
1739
681e5811 1740 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1741 pch_transcoder = TRANSCODER_A;
1742 else
1743 pch_transcoder = pipe;
1744
b24e7179
JB		 1745 /*
1746 * A pipe without a PLL won't actually be able to drive bits from
1747 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1748 * need the check.
1749 */
1750 if (!HAS_PCH_SPLIT(dev_priv->dev))
1751 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1752 else {
1753 if (pch_port) {
1754 /* if driving the PCH, we need FDI enabled */
cc391bbb 1755 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1756 assert_fdi_tx_pll_enabled(dev_priv,
1757 (enum pipe) cpu_transcoder);
040484af
JB		 1758 }
1759 /* FIXME: assert CPU port conditions for SNB+ */
1760 }
b24e7179 1761
702e7a56 1762 reg = PIPECONF(cpu_transcoder);
b24e7179 1763 val = I915_READ(reg);
00d70b15
CW		 1764 if (val & PIPECONF_ENABLE)
1765 return;
1766
1767 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1768 intel_wait_for_vblank(dev_priv->dev, pipe);
1769}
1770
1771/**
309cfea8 1772 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1773 * @dev_priv: i915 private structure
1774 * @pipe: pipe to disable
1775 *
1776 * Disable @pipe, making sure that various hardware specific requirements
1777 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1778 *
1779 * @pipe should be %PIPE_A or %PIPE_B.
1780 *
1781 * Will wait until the pipe has shut down before returning.
1782 */
1783static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1784 enum pipe pipe)
1785{
702e7a56
PZ		 1786 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1787 pipe);
b24e7179
JB		 1788 int reg;
1789 u32 val;
1790
1791 /*
1792 * Make sure planes won't keep trying to pump pixels to us,
1793 * or we might hang the display.
1794 */
1795 assert_planes_disabled(dev_priv, pipe);
19332d7a 1796 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1797
1798 /* Don't disable pipe A or pipe A PLLs if needed */
1799 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1800 return;
1801
702e7a56 1802 reg = PIPECONF(cpu_transcoder);
b24e7179 1803 val = I915_READ(reg);
00d70b15
CW		 1804 if ((val & PIPECONF_ENABLE) == 0)
1805 return;
1806
1807 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1808 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1809}
1810
d74362c9
KP		 1811/*
1812 * Plane regs are double buffered, going from enabled->disabled needs a
1813 * trigger in order to latch. The display address reg provides this.
1814 */
6f1d69b0 1815void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1816 enum plane plane)
1817{
14f86147
DL		 1818 if (dev_priv->info->gen >= 4)
1819 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1820 else
1821 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1822}
1823
b24e7179
JB		 1824/**
1825 * intel_enable_plane - enable a display plane on a given pipe
1826 * @dev_priv: i915 private structure
1827 * @plane: plane to enable
1828 * @pipe: pipe being fed
1829 *
1830 * Enable @plane on @pipe, making sure that @pipe is running first.
1831 */
1832static void intel_enable_plane(struct drm_i915_private *dev_priv,
1833 enum plane plane, enum pipe pipe)
1834{
1835 int reg;
1836 u32 val;
1837
1838 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839 assert_pipe_enabled(dev_priv, pipe);
1840
1841 reg = DSPCNTR(plane);
1842 val = I915_READ(reg);
00d70b15
CW		 1843 if (val & DISPLAY_PLANE_ENABLE)
1844 return;
1845
1846 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1847 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1848 intel_wait_for_vblank(dev_priv->dev, pipe);
1849}
1850
b24e7179
JB		 1851/**
1852 * intel_disable_plane - disable a display plane
1853 * @dev_priv: i915 private structure
1854 * @plane: plane to disable
1855 * @pipe: pipe consuming the data
1856 *
1857 * Disable @plane; should be an independent operation.
1858 */
1859static void intel_disable_plane(struct drm_i915_private *dev_priv,
1860 enum plane plane, enum pipe pipe)
1861{
1862 int reg;
1863 u32 val;
1864
1865 reg = DSPCNTR(plane);
1866 val = I915_READ(reg);
00d70b15
CW		 1867 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1868 return;
1869
1870 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1871 intel_flush_display_plane(dev_priv, plane);
1872 intel_wait_for_vblank(dev_priv->dev, pipe);
1873}
1874
693db184
CW		 1875static bool need_vtd_wa(struct drm_device *dev)
1876{
1877#ifdef CONFIG_INTEL_IOMMU
1878 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1879 return true;
1880#endif
1881 return false;
1882}
1883
127bd2ac 1884int
48b956c5 1885intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1886 struct drm_i915_gem_object *obj,
919926ae 1887 struct intel_ring_buffer *pipelined)
6b95a207 1888{
ce453d81 1889 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1890 u32 alignment;
1891 int ret;
1892
05394f39 1893 switch (obj->tiling_mode) {
6b95a207 1894 case I915_TILING_NONE:
534843da
CW		 1895 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1896 alignment = 128 * 1024;
a6c45cf0 1897 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1898 alignment = 4 * 1024;
1899 else
1900 alignment = 64 * 1024;
6b95a207
KH		 1901 break;
1902 case I915_TILING_X:
1903 /* pin() will align the object as required by fence */
1904 alignment = 0;
1905 break;
1906 case I915_TILING_Y:
8bb6e959
DV		 1907 /* Despite that we check this in framebuffer_init userspace can
1908 * screw us over and change the tiling after the fact. Only
1909 * pinned buffers can't change their tiling. */
1910 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1911 return -EINVAL;
1912 default:
1913 BUG();
1914 }
1915
693db184
CW		 1916 /* Note that the w/a also requires 64 PTE of padding following the
1917 * bo. We currently fill all unused PTE with the shadow page and so
1918 * we should always have valid PTE following the scanout preventing
1919 * the VT-d warning.
1920 */
1921 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1922 alignment = 256 * 1024;
1923
ce453d81 1924 dev_priv->mm.interruptible = false;
2da3b9b9 1925 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1926 if (ret)
ce453d81 1927 goto err_interruptible;
6b95a207
KH		 1928
1929 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930 * fence, whereas 965+ only requires a fence if using
1931 * framebuffer compression. For simplicity, we always install
1932 * a fence as the cost is not that onerous.
1933 */
06d98131 1934 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1935 if (ret)
1936 goto err_unpin;
1690e1eb 1937
9a5a53b3 1938 i915_gem_object_pin_fence(obj);
6b95a207 1939
ce453d81 1940 dev_priv->mm.interruptible = true;
6b95a207 1941 return 0;
48b956c5
CW		 1942
1943err_unpin:
1944 i915_gem_object_unpin(obj);
ce453d81
CW		 1945err_interruptible:
1946 dev_priv->mm.interruptible = true;
48b956c5 1947 return ret;
6b95a207
KH		 1948}
1949
1690e1eb
CW		 1950void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951{
1952 i915_gem_object_unpin_fence(obj);
1953 i915_gem_object_unpin(obj);
1954}
1955
c2c75131
DV		 1956/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957 * is assumed to be a power-of-two. */
bc752862
CW		 1958unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1959 unsigned int tiling_mode,
1960 unsigned int cpp,
1961 unsigned int pitch)
c2c75131 1962{
bc752862
CW		 1963 if (tiling_mode != I915_TILING_NONE) {
1964 unsigned int tile_rows, tiles;
c2c75131 1965
bc752862
CW		 1966 tile_rows = *y / 8;
1967 *y %= 8;
c2c75131 1968
bc752862
CW		 1969 tiles = *x / (512/cpp);
1970 *x %= 512/cpp;
1971
1972 return tile_rows * pitch * 8 + tiles * 4096;
1973 } else {
1974 unsigned int offset;
1975
1976 offset = *y * pitch + *x * cpp;
1977 *y = 0;
1978 *x = (offset & 4095) / cpp;
1979 return offset & -4096;
1980 }
c2c75131
DV		 1981}
1982
17638cd6
JB		 1983static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1984 int x, int y)
81255565
JB		 1985{
1986 struct drm_device *dev = crtc->dev;
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1989 struct intel_framebuffer *intel_fb;
05394f39 1990 struct drm_i915_gem_object *obj;
81255565 1991 int plane = intel_crtc->plane;
e506a0c6 1992 unsigned long linear_offset;
81255565 1993 u32 dspcntr;
5eddb70b 1994 u32 reg;
81255565
JB		 1995
1996 switch (plane) {
1997 case 0:
1998 case 1:
1999 break;
2000 default:
84f44ce7 2001 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2002 return -EINVAL;
2003 }
2004
2005 intel_fb = to_intel_framebuffer(fb);
2006 obj = intel_fb->obj;
81255565 2007
5eddb70b
CW		 2008 reg = DSPCNTR(plane);
2009 dspcntr = I915_READ(reg);
81255565
JB		 2010 /* Mask out pixel format bits in case we change it */
2011 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2012 switch (fb->pixel_format) {
2013 case DRM_FORMAT_C8:
81255565
JB		 2014 dspcntr |= DISPPLANE_8BPP;
2015 break;
57779d06
VS		 2016 case DRM_FORMAT_XRGB1555:
2017 case DRM_FORMAT_ARGB1555:
2018 dspcntr |= DISPPLANE_BGRX555;
81255565 2019 break;
57779d06
VS		 2020 case DRM_FORMAT_RGB565:
2021 dspcntr |= DISPPLANE_BGRX565;
2022 break;
2023 case DRM_FORMAT_XRGB8888:
2024 case DRM_FORMAT_ARGB8888:
2025 dspcntr |= DISPPLANE_BGRX888;
2026 break;
2027 case DRM_FORMAT_XBGR8888:
2028 case DRM_FORMAT_ABGR8888:
2029 dspcntr |= DISPPLANE_RGBX888;
2030 break;
2031 case DRM_FORMAT_XRGB2101010:
2032 case DRM_FORMAT_ARGB2101010:
2033 dspcntr |= DISPPLANE_BGRX101010;
2034 break;
2035 case DRM_FORMAT_XBGR2101010:
2036 case DRM_FORMAT_ABGR2101010:
2037 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2038 break;
2039 default:
baba133a 2040 BUG();
81255565 2041 }
57779d06 2042
a6c45cf0 2043 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2044 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2045 dspcntr |= DISPPLANE_TILED;
2046 else
2047 dspcntr &= ~DISPPLANE_TILED;
2048 }
2049
5eddb70b 2050 I915_WRITE(reg, dspcntr);
81255565 2051
e506a0c6 2052 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2053
c2c75131
DV		 2054 if (INTEL_INFO(dev)->gen >= 4) {
2055 intel_crtc->dspaddr_offset =
bc752862
CW		 2056 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2057 fb->bits_per_pixel / 8,
2058 fb->pitches[0]);
c2c75131
DV		 2059 linear_offset -= intel_crtc->dspaddr_offset;
2060 } else {
e506a0c6 2061 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2062 }
e506a0c6
DV		 2063
2064 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2065 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2066 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2067 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2068 I915_MODIFY_DISPBASE(DSPSURF(plane),
2069 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2070 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2071 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2072 } else
e506a0c6 2073 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2074 POSTING_READ(reg);
81255565 2075
17638cd6
JB		 2076 return 0;
2077}
2078
2079static int ironlake_update_plane(struct drm_crtc *crtc,
2080 struct drm_framebuffer *fb, int x, int y)
2081{
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
2086 struct drm_i915_gem_object *obj;
2087 int plane = intel_crtc->plane;
e506a0c6 2088 unsigned long linear_offset;
17638cd6
JB		 2089 u32 dspcntr;
2090 u32 reg;
2091
2092 switch (plane) {
2093 case 0:
2094 case 1:
27f8227b 2095 case 2:
17638cd6
JB		 2096 break;
2097 default:
84f44ce7 2098 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2099 return -EINVAL;
2100 }
2101
2102 intel_fb = to_intel_framebuffer(fb);
2103 obj = intel_fb->obj;
2104
2105 reg = DSPCNTR(plane);
2106 dspcntr = I915_READ(reg);
2107 /* Mask out pixel format bits in case we change it */
2108 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2109 switch (fb->pixel_format) {
2110 case DRM_FORMAT_C8:
17638cd6
JB		 2111 dspcntr |= DISPPLANE_8BPP;
2112 break;
57779d06
VS		 2113 case DRM_FORMAT_RGB565:
2114 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2115 break;
57779d06
VS		 2116 case DRM_FORMAT_XRGB8888:
2117 case DRM_FORMAT_ARGB8888:
2118 dspcntr |= DISPPLANE_BGRX888;
2119 break;
2120 case DRM_FORMAT_XBGR8888:
2121 case DRM_FORMAT_ABGR8888:
2122 dspcntr |= DISPPLANE_RGBX888;
2123 break;
2124 case DRM_FORMAT_XRGB2101010:
2125 case DRM_FORMAT_ARGB2101010:
2126 dspcntr |= DISPPLANE_BGRX101010;
2127 break;
2128 case DRM_FORMAT_XBGR2101010:
2129 case DRM_FORMAT_ABGR2101010:
2130 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2131 break;
2132 default:
baba133a 2133 BUG();
17638cd6
JB		 2134 }
2135
2136 if (obj->tiling_mode != I915_TILING_NONE)
2137 dspcntr |= DISPPLANE_TILED;
2138 else
2139 dspcntr &= ~DISPPLANE_TILED;
2140
2141 /* must disable */
2142 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2143
2144 I915_WRITE(reg, dspcntr);
2145
e506a0c6 2146 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2147 intel_crtc->dspaddr_offset =
bc752862
CW		 2148 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2149 fb->bits_per_pixel / 8,
2150 fb->pitches[0]);
c2c75131 2151 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2152
e506a0c6
DV		 2153 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2154 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2155 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2156 I915_MODIFY_DISPBASE(DSPSURF(plane),
2157 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2158 if (IS_HASWELL(dev)) {
2159 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2160 } else {
2161 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2162 I915_WRITE(DSPLINOFF(plane), linear_offset);
2163 }
17638cd6
JB		 2164 POSTING_READ(reg);
2165
2166 return 0;
2167}
2168
2169/* Assume fb object is pinned & idle & fenced and just update base pointers */
2170static int
2171intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2172 int x, int y, enum mode_set_atomic state)
2173{
2174 struct drm_device *dev = crtc->dev;
2175 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2176
6b8e6ed0
CW		 2177 if (dev_priv->display.disable_fbc)
2178 dev_priv->display.disable_fbc(dev);
3dec0095 2179 intel_increase_pllclock(crtc);
81255565 2180
6b8e6ed0 2181 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2182}
2183
96a02917
VS		 2184void intel_display_handle_reset(struct drm_device *dev)
2185{
2186 struct drm_i915_private *dev_priv = dev->dev_private;
2187 struct drm_crtc *crtc;
2188
2189 /*
2190 * Flips in the rings have been nuked by the reset,
2191 * so complete all pending flips so that user space
2192 * will get its events and not get stuck.
2193 *
2194 * Also update the base address of all primary
2195 * planes to the the last fb to make sure we're
2196 * showing the correct fb after a reset.
2197 *
2198 * Need to make two loops over the crtcs so that we
2199 * don't try to grab a crtc mutex before the
2200 * pending_flip_queue really got woken up.
2201 */
2202
2203 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2205 enum plane plane = intel_crtc->plane;
2206
2207 intel_prepare_page_flip(dev, plane);
2208 intel_finish_page_flip_plane(dev, plane);
2209 }
2210
2211 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2213
2214 mutex_lock(&crtc->mutex);
2215 if (intel_crtc->active)
2216 dev_priv->display.update_plane(crtc, crtc->fb,
2217 crtc->x, crtc->y);
2218 mutex_unlock(&crtc->mutex);
2219 }
2220}
2221
14667a4b
CW		 2222static int
2223intel_finish_fb(struct drm_framebuffer *old_fb)
2224{
2225 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2226 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2227 bool was_interruptible = dev_priv->mm.interruptible;
2228 int ret;
2229
14667a4b
CW		 2230 /* Big Hammer, we also need to ensure that any pending
2231 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2232 * current scanout is retired before unpinning the old
2233 * framebuffer.
2234 *
2235 * This should only fail upon a hung GPU, in which case we
2236 * can safely continue.
2237 */
2238 dev_priv->mm.interruptible = false;
2239 ret = i915_gem_object_finish_gpu(obj);
2240 dev_priv->mm.interruptible = was_interruptible;
2241
2242 return ret;
2243}
2244
198598d0
VS		 2245static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2246{
2247 struct drm_device *dev = crtc->dev;
2248 struct drm_i915_master_private *master_priv;
2249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2250
2251 if (!dev->primary->master)
2252 return;
2253
2254 master_priv = dev->primary->master->driver_priv;
2255 if (!master_priv->sarea_priv)
2256 return;
2257
2258 switch (intel_crtc->pipe) {
2259 case 0:
2260 master_priv->sarea_priv->pipeA_x = x;
2261 master_priv->sarea_priv->pipeA_y = y;
2262 break;
2263 case 1:
2264 master_priv->sarea_priv->pipeB_x = x;
2265 master_priv->sarea_priv->pipeB_y = y;
2266 break;
2267 default:
2268 break;
2269 }
2270}
2271
5c3b82e2 2272static int
3c4fdcfb 2273intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2274 struct drm_framebuffer *fb)
79e53945
JB		 2275{
2276 struct drm_device *dev = crtc->dev;
6b8e6ed0 2277 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2279 struct drm_framebuffer *old_fb;
5c3b82e2 2280 int ret;
79e53945
JB		 2281
2282 /* no fb bound */
94352cf9 2283 if (!fb) {
a5071c2f 2284 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2285 return 0;
2286 }
2287
7eb552ae 2288 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2289 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2290 plane_name(intel_crtc->plane),
2291 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2292 return -EINVAL;
79e53945
JB		 2293 }
2294
5c3b82e2 2295 mutex_lock(&dev->struct_mutex);
265db958 2296 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2297 to_intel_framebuffer(fb)->obj,
919926ae 2298 NULL);
5c3b82e2
CW		 2299 if (ret != 0) {
2300 mutex_unlock(&dev->struct_mutex);
a5071c2f 2301 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2302 return ret;
2303 }
79e53945 2304
94352cf9 2305 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2306 if (ret) {
94352cf9 2307 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2308 mutex_unlock(&dev->struct_mutex);
a5071c2f 2309 DRM_ERROR("failed to update base address\n");
4e6cfefc 2310 return ret;
79e53945 2311 }
3c4fdcfb 2312
94352cf9
DV		 2313 old_fb = crtc->fb;
2314 crtc->fb = fb;
6c4c86f5
DV		 2315 crtc->x = x;
2316 crtc->y = y;
94352cf9 2317
b7f1de28
CW		 2318 if (old_fb) {
2319 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2320 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2321 }
652c393a 2322
6b8e6ed0 2323 intel_update_fbc(dev);
5c3b82e2 2324 mutex_unlock(&dev->struct_mutex);
79e53945 2325
198598d0 2326 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2327
2328 return 0;
79e53945
JB		 2329}
2330
5e84e1a4
ZW		 2331static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332{
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2337 u32 reg, temp;
2338
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
61e499bf 2342 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2345 } else {
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2348 }
5e84e1a4
ZW		 2349 I915_WRITE(reg, temp);
2350
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356 } else {
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2359 }
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362 /* wait one idle pattern time */
2363 POSTING_READ(reg);
2364 udelay(1000);
357555c0
JB		 2365
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2370}
2371
1e833f40
DV		 2372static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2373{
2374 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2375}
2376
01a415fd
DV		 2377static void ivb_modeset_global_resources(struct drm_device *dev)
2378{
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct intel_crtc *pipe_B_crtc =
2381 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382 struct intel_crtc *pipe_C_crtc =
2383 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2384 uint32_t temp;
2385
1e833f40
DV		 2386 /*
2387 * When everything is off disable fdi C so that we could enable fdi B
2388 * with all lanes. Note that we don't care about enabled pipes without
2389 * an enabled pch encoder.
2390 */
2391 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2393 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396 temp = I915_READ(SOUTH_CHICKEN1);
2397 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399 I915_WRITE(SOUTH_CHICKEN1, temp);
2400 }
2401}
2402
8db9d77b
ZW		 2403/* The FDI link training functions for ILK/Ibexpeak. */
2404static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405{
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 int pipe = intel_crtc->pipe;
0fc932b8 2410 int plane = intel_crtc->plane;
5eddb70b 2411 u32 reg, temp, tries;
8db9d77b 2412
0fc932b8
JB		 2413 /* FDI needs bits from pipe & plane first */
2414 assert_pipe_enabled(dev_priv, pipe);
2415 assert_plane_enabled(dev_priv, plane);
2416
e1a44743
AJ		 2417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418 for train result */
5eddb70b
CW		 2419 reg = FDI_RX_IMR(pipe);
2420 temp = I915_READ(reg);
e1a44743
AJ		 2421 temp &= ~FDI_RX_SYMBOL_LOCK;
2422 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2423 I915_WRITE(reg, temp);
2424 I915_READ(reg);
e1a44743
AJ		 2425 udelay(150);
2426
8db9d77b 2427 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2428 reg = FDI_TX_CTL(pipe);
2429 temp = I915_READ(reg);
627eb5a3
DV		 2430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2435
5eddb70b
CW		 2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
8db9d77b
ZW		 2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442 POSTING_READ(reg);
8db9d77b
ZW		 2443 udelay(150);
2444
5b2adf89 2445 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2449
5eddb70b 2450 reg = FDI_RX_IIR(pipe);
e1a44743 2451 for (tries = 0; tries < 5; tries++) {
5eddb70b 2452 temp = I915_READ(reg);
8db9d77b
ZW		 2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if ((temp & FDI_RX_BIT_LOCK)) {
2456 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2458 break;
2459 }
8db9d77b 2460 }
e1a44743 2461 if (tries == 5)
5eddb70b 2462 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2463
2464 /* Train 2 */
5eddb70b
CW		 2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2469 I915_WRITE(reg, temp);
8db9d77b 2470
5eddb70b
CW		 2471 reg = FDI_RX_CTL(pipe);
2472 temp = I915_READ(reg);
8db9d77b
ZW		 2473 temp &= ~FDI_LINK_TRAIN_NONE;
2474 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2475 I915_WRITE(reg, temp);
8db9d77b 2476
5eddb70b
CW		 2477 POSTING_READ(reg);
2478 udelay(150);
8db9d77b 2479
5eddb70b 2480 reg = FDI_RX_IIR(pipe);
e1a44743 2481 for (tries = 0; tries < 5; tries++) {
5eddb70b 2482 temp = I915_READ(reg);
8db9d77b
ZW		 2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2487 DRM_DEBUG_KMS("FDI train 2 done.\n");
2488 break;
2489 }
8db9d77b 2490 }
e1a44743 2491 if (tries == 5)
5eddb70b 2492 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2493
2494 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2495
8db9d77b
ZW		 2496}
2497
0206e353 2498static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503};
2504
2505/* The FDI link training functions for SNB/Cougarpoint. */
2506static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507{
2508 struct drm_device *dev = crtc->dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511 int pipe = intel_crtc->pipe;
fa37d39e 2512 u32 reg, temp, i, retry;
8db9d77b 2513
e1a44743
AJ		 2514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515 for train result */
5eddb70b
CW		 2516 reg = FDI_RX_IMR(pipe);
2517 temp = I915_READ(reg);
e1a44743
AJ		 2518 temp &= ~FDI_RX_SYMBOL_LOCK;
2519 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
e1a44743
AJ		 2523 udelay(150);
2524
8db9d77b 2525 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2526 reg = FDI_TX_CTL(pipe);
2527 temp = I915_READ(reg);
627eb5a3
DV		 2528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_1;
2532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533 /* SNB-B */
2534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2536
d74cf324
DV		 2537 I915_WRITE(FDI_RX_MISC(pipe),
2538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
5eddb70b
CW		 2540 reg = FDI_RX_CTL(pipe);
2541 temp = I915_READ(reg);
8db9d77b
ZW		 2542 if (HAS_PCH_CPT(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545 } else {
2546 temp &= ~FDI_LINK_TRAIN_NONE;
2547 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548 }
5eddb70b
CW		 2549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551 POSTING_READ(reg);
8db9d77b
ZW		 2552 udelay(150);
2553
0206e353 2554 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
8db9d77b
ZW		 2557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2559 I915_WRITE(reg, temp);
2560
2561 POSTING_READ(reg);
8db9d77b
ZW		 2562 udelay(500);
2563
fa37d39e
SP		 2564 for (retry = 0; retry < 5; retry++) {
2565 reg = FDI_RX_IIR(pipe);
2566 temp = I915_READ(reg);
2567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568 if (temp & FDI_RX_BIT_LOCK) {
2569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571 break;
2572 }
2573 udelay(50);
8db9d77b 2574 }
fa37d39e
SP		 2575 if (retry < 5)
2576 break;
8db9d77b
ZW		 2577 }
2578 if (i == 4)
5eddb70b 2579 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2580
2581 /* Train 2 */
5eddb70b
CW		 2582 reg = FDI_TX_CTL(pipe);
2583 temp = I915_READ(reg);
8db9d77b
ZW		 2584 temp &= ~FDI_LINK_TRAIN_NONE;
2585 temp |= FDI_LINK_TRAIN_PATTERN_2;
2586 if (IS_GEN6(dev)) {
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 /* SNB-B */
2589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590 }
5eddb70b 2591 I915_WRITE(reg, temp);
8db9d77b 2592
5eddb70b
CW		 2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
8db9d77b
ZW		 2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601 }
5eddb70b
CW		 2602 I915_WRITE(reg, temp);
2603
2604 POSTING_READ(reg);
8db9d77b
ZW		 2605 udelay(150);
2606
0206e353 2607 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
8db9d77b
ZW		 2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
8db9d77b
ZW		 2615 udelay(500);
2616
fa37d39e
SP		 2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_SYMBOL_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624 break;
2625 }
2626 udelay(50);
8db9d77b 2627 }
fa37d39e
SP		 2628 if (retry < 5)
2629 break;
8db9d77b
ZW		 2630 }
2631 if (i == 4)
5eddb70b 2632 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2633
2634 DRM_DEBUG_KMS("FDI train done.\n");
2635}
2636
357555c0
JB		 2637/* Manual link training for Ivy Bridge A0 parts */
2638static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639{
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 int pipe = intel_crtc->pipe;
2644 u32 reg, temp, i;
2645
2646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647 for train result */
2648 reg = FDI_RX_IMR(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_RX_SYMBOL_LOCK;
2651 temp &= ~FDI_RX_BIT_LOCK;
2652 I915_WRITE(reg, temp);
2653
2654 POSTING_READ(reg);
2655 udelay(150);
2656
01a415fd
DV		 2657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658 I915_READ(FDI_RX_IIR(pipe)));
2659
357555c0
JB		 2660 /* enable CPU FDI TX and PCH FDI RX */
2661 reg = FDI_TX_CTL(pipe);
2662 temp = I915_READ(reg);
627eb5a3
DV		 2663 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2664 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2667 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2668 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2669 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2670 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2671
d74cf324
DV		 2672 I915_WRITE(FDI_RX_MISC(pipe),
2673 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2674
357555c0
JB		 2675 reg = FDI_RX_CTL(pipe);
2676 temp = I915_READ(reg);
2677 temp &= ~FDI_LINK_TRAIN_AUTO;
2678 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2679 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2680 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2681 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2682
2683 POSTING_READ(reg);
2684 udelay(150);
2685
0206e353 2686 for (i = 0; i < 4; i++) {
357555c0
JB		 2687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= snb_b_fdi_train_param[i];
2691 I915_WRITE(reg, temp);
2692
2693 POSTING_READ(reg);
2694 udelay(500);
2695
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700 if (temp & FDI_RX_BIT_LOCK ||
2701 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2702 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2703 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2704 break;
2705 }
2706 }
2707 if (i == 4)
2708 DRM_ERROR("FDI train 1 fail!\n");
2709
2710 /* Train 2 */
2711 reg = FDI_TX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2714 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2715 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2716 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2717 I915_WRITE(reg, temp);
2718
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2722 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2723 I915_WRITE(reg, temp);
2724
2725 POSTING_READ(reg);
2726 udelay(150);
2727
0206e353 2728 for (i = 0; i < 4; i++) {
357555c0
JB		 2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732 temp |= snb_b_fdi_train_param[i];
2733 I915_WRITE(reg, temp);
2734
2735 POSTING_READ(reg);
2736 udelay(500);
2737
2738 reg = FDI_RX_IIR(pipe);
2739 temp = I915_READ(reg);
2740 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2741
2742 if (temp & FDI_RX_SYMBOL_LOCK) {
2743 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2744 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2745 break;
2746 }
2747 }
2748 if (i == 4)
2749 DRM_ERROR("FDI train 2 fail!\n");
2750
2751 DRM_DEBUG_KMS("FDI train done.\n");
2752}
2753
88cefb6c 2754static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2755{
88cefb6c 2756 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2757 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2758 int pipe = intel_crtc->pipe;
5eddb70b 2759 u32 reg, temp;
79e53945 2760
c64e311e 2761
c98e9dcf 2762 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
627eb5a3
DV		 2765 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2766 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2767 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2768 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2769
2770 POSTING_READ(reg);
c98e9dcf
JB		 2771 udelay(200);
2772
2773 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2774 temp = I915_READ(reg);
2775 I915_WRITE(reg, temp | FDI_PCDCLK);
2776
2777 POSTING_READ(reg);
c98e9dcf
JB		 2778 udelay(200);
2779
20749730
PZ		 2780 /* Enable CPU FDI TX PLL, always on for Ironlake */
2781 reg = FDI_TX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2784 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2785
20749730
PZ		 2786 POSTING_READ(reg);
2787 udelay(100);
6be4a607 2788 }
0e23b99d
JB		 2789}
2790
88cefb6c
DV		 2791static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2792{
2793 struct drm_device *dev = intel_crtc->base.dev;
2794 struct drm_i915_private *dev_priv = dev->dev_private;
2795 int pipe = intel_crtc->pipe;
2796 u32 reg, temp;
2797
2798 /* Switch from PCDclk to Rawclk */
2799 reg = FDI_RX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2802
2803 /* Disable CPU FDI TX PLL */
2804 reg = FDI_TX_CTL(pipe);
2805 temp = I915_READ(reg);
2806 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2807
2808 POSTING_READ(reg);
2809 udelay(100);
2810
2811 reg = FDI_RX_CTL(pipe);
2812 temp = I915_READ(reg);
2813 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2814
2815 /* Wait for the clocks to turn off. */
2816 POSTING_READ(reg);
2817 udelay(100);
2818}
2819
0fc932b8
JB		 2820static void ironlake_fdi_disable(struct drm_crtc *crtc)
2821{
2822 struct drm_device *dev = crtc->dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2825 int pipe = intel_crtc->pipe;
2826 u32 reg, temp;
2827
2828 /* disable CPU FDI tx and PCH FDI rx */
2829 reg = FDI_TX_CTL(pipe);
2830 temp = I915_READ(reg);
2831 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2832 POSTING_READ(reg);
2833
2834 reg = FDI_RX_CTL(pipe);
2835 temp = I915_READ(reg);
2836 temp &= ~(0x7 << 16);
dfd07d72 2837 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2838 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2839
2840 POSTING_READ(reg);
2841 udelay(100);
2842
2843 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2844 if (HAS_PCH_IBX(dev)) {
2845 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2846 }
0fc932b8
JB		 2847
2848 /* still set train pattern 1 */
2849 reg = FDI_TX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 temp &= ~FDI_LINK_TRAIN_NONE;
2852 temp |= FDI_LINK_TRAIN_PATTERN_1;
2853 I915_WRITE(reg, temp);
2854
2855 reg = FDI_RX_CTL(pipe);
2856 temp = I915_READ(reg);
2857 if (HAS_PCH_CPT(dev)) {
2858 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2859 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2860 } else {
2861 temp &= ~FDI_LINK_TRAIN_NONE;
2862 temp |= FDI_LINK_TRAIN_PATTERN_1;
2863 }
2864 /* BPC in FDI rx is consistent with that in PIPECONF */
2865 temp &= ~(0x07 << 16);
dfd07d72 2866 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2867 I915_WRITE(reg, temp);
2868
2869 POSTING_READ(reg);
2870 udelay(100);
2871}
2872
5bb61643
CW		 2873static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2874{
2875 struct drm_device *dev = crtc->dev;
2876 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2878 unsigned long flags;
2879 bool pending;
2880
10d83730
VS		 2881 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2882 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2883 return false;
2884
2885 spin_lock_irqsave(&dev->event_lock, flags);
2886 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2887 spin_unlock_irqrestore(&dev->event_lock, flags);
2888
2889 return pending;
2890}
2891
e6c3a2a6
CW		 2892static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2893{
0f91128d 2894 struct drm_device *dev = crtc->dev;
5bb61643 2895 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2896
2897 if (crtc->fb == NULL)
2898 return;
2899
2c10d571
DV		 2900 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2901
5bb61643
CW		 2902 wait_event(dev_priv->pending_flip_queue,
2903 !intel_crtc_has_pending_flip(crtc));
2904
0f91128d
CW		 2905 mutex_lock(&dev->struct_mutex);
2906 intel_finish_fb(crtc->fb);
2907 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2908}
2909
e615efe4
ED		 2910/* Program iCLKIP clock to the desired frequency */
2911static void lpt_program_iclkip(struct drm_crtc *crtc)
2912{
2913 struct drm_device *dev = crtc->dev;
2914 struct drm_i915_private *dev_priv = dev->dev_private;
2915 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2916 u32 temp;
2917
09153000
DV		 2918 mutex_lock(&dev_priv->dpio_lock);
2919
e615efe4
ED		 2920 /* It is necessary to ungate the pixclk gate prior to programming
2921 * the divisors, and gate it back when it is done.
2922 */
2923 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2924
2925 /* Disable SSCCTL */
2926 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2927 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2928 SBI_SSCCTL_DISABLE,
2929 SBI_ICLK);
e615efe4
ED		 2930
2931 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2932 if (crtc->mode.clock == 20000) {
2933 auxdiv = 1;
2934 divsel = 0x41;
2935 phaseinc = 0x20;
2936 } else {
2937 /* The iCLK virtual clock root frequency is in MHz,
2938 * but the crtc->mode.clock in in KHz. To get the divisors,
2939 * it is necessary to divide one by another, so we
2940 * convert the virtual clock precision to KHz here for higher
2941 * precision.
2942 */
2943 u32 iclk_virtual_root_freq = 172800 * 1000;
2944 u32 iclk_pi_range = 64;
2945 u32 desired_divisor, msb_divisor_value, pi_value;
2946
2947 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2948 msb_divisor_value = desired_divisor / iclk_pi_range;
2949 pi_value = desired_divisor % iclk_pi_range;
2950
2951 auxdiv = 0;
2952 divsel = msb_divisor_value - 2;
2953 phaseinc = pi_value;
2954 }
2955
2956 /* This should not happen with any sane values */
2957 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2958 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2959 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2960 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2961
2962 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2963 crtc->mode.clock,
2964 auxdiv,
2965 divsel,
2966 phasedir,
2967 phaseinc);
2968
2969 /* Program SSCDIVINTPHASE6 */
988d6ee8 2970 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2971 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2972 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2973 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2974 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2975 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2976 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2977 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2978
2979 /* Program SSCAUXDIV */
988d6ee8 2980 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2981 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2982 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2983 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2984
2985 /* Enable modulator and associated divider */
988d6ee8 2986 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2987 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2988 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2989
2990 /* Wait for initialization time */
2991 udelay(24);
2992
2993 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2994
2995 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2996}
2997
275f01b2
DV		 2998static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2999 enum pipe pch_transcoder)
3000{
3001 struct drm_device *dev = crtc->base.dev;
3002 struct drm_i915_private *dev_priv = dev->dev_private;
3003 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3004
3005 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3006 I915_READ(HTOTAL(cpu_transcoder)));
3007 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3008 I915_READ(HBLANK(cpu_transcoder)));
3009 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3010 I915_READ(HSYNC(cpu_transcoder)));
3011
3012 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3013 I915_READ(VTOTAL(cpu_transcoder)));
3014 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3015 I915_READ(VBLANK(cpu_transcoder)));
3016 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3017 I915_READ(VSYNC(cpu_transcoder)));
3018 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3019 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3020}
3021
f67a559d
JB		 3022/*
3023 * Enable PCH resources required for PCH ports:
3024 * - PCH PLLs
3025 * - FDI training & RX/TX
3026 * - update transcoder timings
3027 * - DP transcoding bits
3028 * - transcoder
3029 */
3030static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3031{
3032 struct drm_device *dev = crtc->dev;
3033 struct drm_i915_private *dev_priv = dev->dev_private;
3034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3035 int pipe = intel_crtc->pipe;
ee7b9f93 3036 u32 reg, temp;
2c07245f 3037
ab9412ba 3038 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3039
cd986abb
DV		 3040 /* Write the TU size bits before fdi link training, so that error
3041 * detection works. */
3042 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3043 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3044
c98e9dcf 3045 /* For PCH output, training FDI link */
674cf967 3046 dev_priv->display.fdi_link_train(crtc);
2c07245f 3047
572deb37
DV		 3048 /* XXX: pch pll's can be enabled any time before we enable the PCH
3049 * transcoder, and we actually should do this to not upset any PCH
3050 * transcoder that already use the clock when we share it.
3051 *
3052 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3053 * unconditionally resets the pll - we need that to have the right LVDS
3054 * enable sequence. */
b6b4e185 3055 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3056
303b81e0 3057 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3058 u32 sel;
4b645f14 3059
c98e9dcf 3060 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3061 switch (pipe) {
3062 default:
3063 case 0:
3064 temp |= TRANSA_DPLL_ENABLE;
3065 sel = TRANSA_DPLLB_SEL;
3066 break;
3067 case 1:
3068 temp |= TRANSB_DPLL_ENABLE;
3069 sel = TRANSB_DPLLB_SEL;
3070 break;
3071 case 2:
3072 temp |= TRANSC_DPLL_ENABLE;
3073 sel = TRANSC_DPLLB_SEL;
3074 break;
d64311ab 3075 }
ee7b9f93
JB		 3076 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3077 temp |= sel;
3078 else
3079 temp &= ~sel;
c98e9dcf 3080 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3081 }
5eddb70b 3082
d9b6cb56
JB		 3083 /* set transcoder timing, panel must allow it */
3084 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3085 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3086
303b81e0 3087 intel_fdi_normal_train(crtc);
5e84e1a4 3088
c98e9dcf
JB		 3089 /* For PCH DP, enable TRANS_DP_CTL */
3090 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3091 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3092 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3093 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3094 reg = TRANS_DP_CTL(pipe);
3095 temp = I915_READ(reg);
3096 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3097 TRANS_DP_SYNC_MASK |
3098 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3099 temp |= (TRANS_DP_OUTPUT_ENABLE |
3100 TRANS_DP_ENH_FRAMING);
9325c9f0 3101 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3102
3103 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3104 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3105 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3106 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3107
3108 switch (intel_trans_dp_port_sel(crtc)) {
3109 case PCH_DP_B:
5eddb70b 3110 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3111 break;
3112 case PCH_DP_C:
5eddb70b 3113 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3114 break;
3115 case PCH_DP_D:
5eddb70b 3116 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3117 break;
3118 default:
e95d41e1 3119 BUG();
32f9d658 3120 }
2c07245f 3121
5eddb70b 3122 I915_WRITE(reg, temp);
6be4a607 3123 }
b52eb4dc 3124
b8a4f404 3125 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3126}
3127
1507e5bd
PZ		 3128static void lpt_pch_enable(struct drm_crtc *crtc)
3129{
3130 struct drm_device *dev = crtc->dev;
3131 struct drm_i915_private *dev_priv = dev->dev_private;
3132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3133 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3134
ab9412ba 3135 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3136
8c52b5e8 3137 lpt_program_iclkip(crtc);
1507e5bd 3138
0540e488 3139 /* Set transcoder timing. */
275f01b2 3140 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3141
937bb610 3142 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3143}
3144
ee7b9f93
JB		 3145static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3146{
3147 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3148
3149 if (pll == NULL)
3150 return;
3151
3152 if (pll->refcount == 0) {
3153 WARN(1, "bad PCH PLL refcount\n");
3154 return;
3155 }
3156
3157 --pll->refcount;
3158 intel_crtc->pch_pll = NULL;
3159}
3160
3161static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3162{
3163 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3164 struct intel_pch_pll *pll;
3165 int i;
3166
3167 pll = intel_crtc->pch_pll;
3168 if (pll) {
3169 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3170 intel_crtc->base.base.id, pll->pll_reg);
3171 goto prepare;
3172 }
3173
98b6bd99
DV		 3174 if (HAS_PCH_IBX(dev_priv->dev)) {
3175 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3176 i = intel_crtc->pipe;
3177 pll = &dev_priv->pch_plls[i];
3178
3179 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3180 intel_crtc->base.base.id, pll->pll_reg);
3181
3182 goto found;
3183 }
3184
ee7b9f93
JB		 3185 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3186 pll = &dev_priv->pch_plls[i];
3187
3188 /* Only want to check enabled timings first */
3189 if (pll->refcount == 0)
3190 continue;
3191
3192 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3193 fp == I915_READ(pll->fp0_reg)) {
3194 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3195 intel_crtc->base.base.id,
3196 pll->pll_reg, pll->refcount, pll->active);
3197
3198 goto found;
3199 }
3200 }
3201
3202 /* Ok no matching timings, maybe there's a free one? */
3203 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3204 pll = &dev_priv->pch_plls[i];
3205 if (pll->refcount == 0) {
3206 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3207 intel_crtc->base.base.id, pll->pll_reg);
3208 goto found;
3209 }
3210 }
3211
3212 return NULL;
3213
3214found:
3215 intel_crtc->pch_pll = pll;
3216 pll->refcount++;
84f44ce7 3217 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3218prepare: /* separate function? */
3219 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3220
e04c7350
CW		 3221 /* Wait for the clocks to stabilize before rewriting the regs */
3222 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3223 POSTING_READ(pll->pll_reg);
3224 udelay(150);
e04c7350
CW		 3225
3226 I915_WRITE(pll->fp0_reg, fp);
3227 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3228 pll->on = false;
3229 return pll;
3230}
3231
a1520318 3232static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3233{
3234 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3235 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3236 u32 temp;
3237
3238 temp = I915_READ(dslreg);
3239 udelay(500);
3240 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3241 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3242 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3243 }
3244}
3245
b074cec8
JB		 3246static void ironlake_pfit_enable(struct intel_crtc *crtc)
3247{
3248 struct drm_device *dev = crtc->base.dev;
3249 struct drm_i915_private *dev_priv = dev->dev_private;
3250 int pipe = crtc->pipe;
3251
0ef37f3f 3252 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3253 /* Force use of hard-coded filter coefficients
3254 * as some pre-programmed values are broken,
3255 * e.g. x201.
3256 */
3257 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3258 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3259 PF_PIPE_SEL_IVB(pipe));
3260 else
3261 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3262 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3263 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3264 }
3265}
3266
f67a559d
JB		 3267static void ironlake_crtc_enable(struct drm_crtc *crtc)
3268{
3269 struct drm_device *dev = crtc->dev;
3270 struct drm_i915_private *dev_priv = dev->dev_private;
3271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3272 struct intel_encoder *encoder;
f67a559d
JB		 3273 int pipe = intel_crtc->pipe;
3274 int plane = intel_crtc->plane;
3275 u32 temp;
f67a559d 3276
08a48469
DV		 3277 WARN_ON(!crtc->enabled);
3278
f67a559d
JB		 3279 if (intel_crtc->active)
3280 return;
3281
3282 intel_crtc->active = true;
8664281b
PZ		 3283
3284 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3285 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3286
f67a559d
JB		 3287 intel_update_watermarks(dev);
3288
3289 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3290 temp = I915_READ(PCH_LVDS);
3291 if ((temp & LVDS_PORT_EN) == 0)
3292 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3293 }
3294
f67a559d 3295
5bfe2ac0 3296 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3297 /* Note: FDI PLL enabling _must_ be done before we enable the
3298 * cpu pipes, hence this is separate from all the other fdi/pch
3299 * enabling. */
88cefb6c 3300 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3301 } else {
3302 assert_fdi_tx_disabled(dev_priv, pipe);
3303 assert_fdi_rx_disabled(dev_priv, pipe);
3304 }
f67a559d 3305
bf49ec8c
DV		 3306 for_each_encoder_on_crtc(dev, crtc, encoder)
3307 if (encoder->pre_enable)
3308 encoder->pre_enable(encoder);
f67a559d
JB		 3309
3310 /* Enable panel fitting for LVDS */
b074cec8 3311 ironlake_pfit_enable(intel_crtc);
f67a559d 3312
9c54c0dd
JB		 3313 /*
3314 * On ILK+ LUT must be loaded before the pipe is running but with
3315 * clocks enabled
3316 */
3317 intel_crtc_load_lut(crtc);
3318
5bfe2ac0
DV		 3319 intel_enable_pipe(dev_priv, pipe,
3320 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3321 intel_enable_plane(dev_priv, plane, pipe);
3322
5bfe2ac0 3323 if (intel_crtc->config.has_pch_encoder)
f67a559d 3324 ironlake_pch_enable(crtc);
c98e9dcf 3325
d1ebd816 3326 mutex_lock(&dev->struct_mutex);
bed4a673 3327 intel_update_fbc(dev);
d1ebd816
BW		 3328 mutex_unlock(&dev->struct_mutex);
3329
6b383a7f 3330 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3331
fa5c73b1
DV		 3332 for_each_encoder_on_crtc(dev, crtc, encoder)
3333 encoder->enable(encoder);
61b77ddd
DV		 3334
3335 if (HAS_PCH_CPT(dev))
a1520318 3336 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3337
3338 /*
3339 * There seems to be a race in PCH platform hw (at least on some
3340 * outputs) where an enabled pipe still completes any pageflip right
3341 * away (as if the pipe is off) instead of waiting for vblank. As soon
3342 * as the first vblank happend, everything works as expected. Hence just
3343 * wait for one vblank before returning to avoid strange things
3344 * happening.
3345 */
3346 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3347}
3348
4f771f10
PZ		 3349static void haswell_crtc_enable(struct drm_crtc *crtc)
3350{
3351 struct drm_device *dev = crtc->dev;
3352 struct drm_i915_private *dev_priv = dev->dev_private;
3353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3354 struct intel_encoder *encoder;
3355 int pipe = intel_crtc->pipe;
3356 int plane = intel_crtc->plane;
4f771f10
PZ		 3357
3358 WARN_ON(!crtc->enabled);
3359
3360 if (intel_crtc->active)
3361 return;
3362
3363 intel_crtc->active = true;
8664281b
PZ		 3364
3365 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3366 if (intel_crtc->config.has_pch_encoder)
3367 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3368
4f771f10
PZ		 3369 intel_update_watermarks(dev);
3370
5bfe2ac0 3371 if (intel_crtc->config.has_pch_encoder)
04945641 3372 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3373
3374 for_each_encoder_on_crtc(dev, crtc, encoder)
3375 if (encoder->pre_enable)
3376 encoder->pre_enable(encoder);
3377
1f544388 3378 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3379
1f544388 3380 /* Enable panel fitting for eDP */
b074cec8 3381 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3382
3383 /*
3384 * On ILK+ LUT must be loaded before the pipe is running but with
3385 * clocks enabled
3386 */
3387 intel_crtc_load_lut(crtc);
3388
1f544388 3389 intel_ddi_set_pipe_settings(crtc);
8228c251 3390 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3391
5bfe2ac0
DV		 3392 intel_enable_pipe(dev_priv, pipe,
3393 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3394 intel_enable_plane(dev_priv, plane, pipe);
3395
5bfe2ac0 3396 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3397 lpt_pch_enable(crtc);
4f771f10
PZ		 3398
3399 mutex_lock(&dev->struct_mutex);
3400 intel_update_fbc(dev);
3401 mutex_unlock(&dev->struct_mutex);
3402
3403 intel_crtc_update_cursor(crtc, true);
3404
3405 for_each_encoder_on_crtc(dev, crtc, encoder)
3406 encoder->enable(encoder);
3407
4f771f10
PZ		 3408 /*
3409 * There seems to be a race in PCH platform hw (at least on some
3410 * outputs) where an enabled pipe still completes any pageflip right
3411 * away (as if the pipe is off) instead of waiting for vblank. As soon
3412 * as the first vblank happend, everything works as expected. Hence just
3413 * wait for one vblank before returning to avoid strange things
3414 * happening.
3415 */
3416 intel_wait_for_vblank(dev, intel_crtc->pipe);
3417}
3418
6be4a607
JB		 3419static void ironlake_crtc_disable(struct drm_crtc *crtc)
3420{
3421 struct drm_device *dev = crtc->dev;
3422 struct drm_i915_private *dev_priv = dev->dev_private;
3423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3424 struct intel_encoder *encoder;
6be4a607
JB		 3425 int pipe = intel_crtc->pipe;
3426 int plane = intel_crtc->plane;
5eddb70b 3427 u32 reg, temp;
b52eb4dc 3428
ef9c3aee 3429
f7abfe8b
CW		 3430 if (!intel_crtc->active)
3431 return;
3432
ea9d758d
DV		 3433 for_each_encoder_on_crtc(dev, crtc, encoder)
3434 encoder->disable(encoder);
3435
e6c3a2a6 3436 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3437 drm_vblank_off(dev, pipe);
6b383a7f 3438 intel_crtc_update_cursor(crtc, false);
5eddb70b 3439
b24e7179 3440 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3441
973d04f9
CW		 3442 if (dev_priv->cfb_plane == plane)
3443 intel_disable_fbc(dev);
2c07245f 3444
8664281b 3445 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3446 intel_disable_pipe(dev_priv, pipe);
32f9d658 3447
6be4a607 3448 /* Disable PF */
9db4a9c7
JB		 3449 I915_WRITE(PF_CTL(pipe), 0);
3450 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3451
bf49ec8c
DV		 3452 for_each_encoder_on_crtc(dev, crtc, encoder)
3453 if (encoder->post_disable)
3454 encoder->post_disable(encoder);
2c07245f 3455
0fc932b8 3456 ironlake_fdi_disable(crtc);
249c0e64 3457
b8a4f404 3458 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3459 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3460
6be4a607
JB		 3461 if (HAS_PCH_CPT(dev)) {
3462 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3463 reg = TRANS_DP_CTL(pipe);
3464 temp = I915_READ(reg);
3465 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3466 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3467 I915_WRITE(reg, temp);
6be4a607
JB		 3468
3469 /* disable DPLL_SEL */
3470 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3471 switch (pipe) {
3472 case 0:
d64311ab 3473 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3474 break;
3475 case 1:
6be4a607 3476 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3477 break;
3478 case 2:
4b645f14 3479 /* C shares PLL A or B */
d64311ab 3480 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3481 break;
3482 default:
3483 BUG(); /* wtf */
3484 }
6be4a607 3485 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3486 }
e3421a18 3487
6be4a607 3488 /* disable PCH DPLL */
ee7b9f93 3489 intel_disable_pch_pll(intel_crtc);
8db9d77b 3490
88cefb6c 3491 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3492
f7abfe8b 3493 intel_crtc->active = false;
6b383a7f 3494 intel_update_watermarks(dev);
d1ebd816
BW		 3495
3496 mutex_lock(&dev->struct_mutex);
6b383a7f 3497 intel_update_fbc(dev);
d1ebd816 3498 mutex_unlock(&dev->struct_mutex);
6be4a607 3499}
1b3c7a47 3500
4f771f10 3501static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3502{
4f771f10
PZ		 3503 struct drm_device *dev = crtc->dev;
3504 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3506 struct intel_encoder *encoder;
3507 int pipe = intel_crtc->pipe;
3508 int plane = intel_crtc->plane;
3b117c8f 3509 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3510
4f771f10
PZ		 3511 if (!intel_crtc->active)
3512 return;
3513
3514 for_each_encoder_on_crtc(dev, crtc, encoder)
3515 encoder->disable(encoder);
3516
3517 intel_crtc_wait_for_pending_flips(crtc);
3518 drm_vblank_off(dev, pipe);
3519 intel_crtc_update_cursor(crtc, false);
3520
3521 intel_disable_plane(dev_priv, plane, pipe);
3522
3523 if (dev_priv->cfb_plane == plane)
3524 intel_disable_fbc(dev);
3525
8664281b
PZ		 3526 if (intel_crtc->config.has_pch_encoder)
3527 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3528 intel_disable_pipe(dev_priv, pipe);
3529
ad80a810 3530 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3531
f7708f78
PZ		 3532 /* XXX: Once we have proper panel fitter state tracking implemented with
3533 * hardware state read/check support we should switch to only disable
3534 * the panel fitter when we know it's used. */
b97186f0
PZ		 3535 if (intel_display_power_enabled(dev,
3536 POWER_DOMAIN_PIPE_PANEL_FITTER(pipe))) {
f7708f78
PZ		 3537 I915_WRITE(PF_CTL(pipe), 0);
3538 I915_WRITE(PF_WIN_SZ(pipe), 0);
3539 }
4f771f10 3540
1f544388 3541 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3542
3543 for_each_encoder_on_crtc(dev, crtc, encoder)
3544 if (encoder->post_disable)
3545 encoder->post_disable(encoder);
3546
88adfff1 3547 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3548 lpt_disable_pch_transcoder(dev_priv);
8664281b 3549 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3550 intel_ddi_fdi_disable(crtc);
83616634 3551 }
4f771f10
PZ		 3552
3553 intel_crtc->active = false;
3554 intel_update_watermarks(dev);
3555
3556 mutex_lock(&dev->struct_mutex);
3557 intel_update_fbc(dev);
3558 mutex_unlock(&dev->struct_mutex);
3559}
3560
ee7b9f93
JB		 3561static void ironlake_crtc_off(struct drm_crtc *crtc)
3562{
3563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3564 intel_put_pch_pll(intel_crtc);
3565}
3566
6441ab5f
PZ		 3567static void haswell_crtc_off(struct drm_crtc *crtc)
3568{
a5c961d1
PZ		 3569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3570
3571 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3572 * start using it. */
3b117c8f 3573 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3574
6441ab5f
PZ		 3575 intel_ddi_put_crtc_pll(crtc);
3576}
3577
02e792fb
DV		 3578static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3579{
02e792fb 3580 if (!enable && intel_crtc->overlay) {
23f09ce3 3581 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3582 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3583
23f09ce3 3584 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3585 dev_priv->mm.interruptible = false;
3586 (void) intel_overlay_switch_off(intel_crtc->overlay);
3587 dev_priv->mm.interruptible = true;
23f09ce3 3588 mutex_unlock(&dev->struct_mutex);
02e792fb 3589 }
02e792fb 3590
5dcdbcb0
CW		 3591 /* Let userspace switch the overlay on again. In most cases userspace
3592 * has to recompute where to put it anyway.
3593 */
02e792fb
DV		 3594}
3595
61bc95c1
EE		 3596/**
3597 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3598 * cursor plane briefly if not already running after enabling the display
3599 * plane.
3600 * This workaround avoids occasional blank screens when self refresh is
3601 * enabled.
3602 */
3603static void
3604g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3605{
3606 u32 cntl = I915_READ(CURCNTR(pipe));
3607
3608 if ((cntl & CURSOR_MODE) == 0) {
3609 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3610
3611 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3612 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3613 intel_wait_for_vblank(dev_priv->dev, pipe);
3614 I915_WRITE(CURCNTR(pipe), cntl);
3615 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3616 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3617 }
3618}
3619
2dd24552
JB		 3620static void i9xx_pfit_enable(struct intel_crtc *crtc)
3621{
3622 struct drm_device *dev = crtc->base.dev;
3623 struct drm_i915_private *dev_priv = dev->dev_private;
3624 struct intel_crtc_config *pipe_config = &crtc->config;
3625
3626 if (!(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
3627 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)))
3628 return;
3629
3630 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3631 assert_pipe_disabled(dev_priv, crtc->pipe);
3632
3633 /*
3634 * Enable automatic panel scaling so that non-native modes
3635 * fill the screen. The panel fitter should only be
3636 * adjusted whilst the pipe is disabled, according to
3637 * register description and PRM.
3638 */
3639 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
b074cec8
JB		 3640 pipe_config->gmch_pfit.control,
3641 pipe_config->gmch_pfit.pgm_ratios);
2dd24552 3642
b074cec8
JB		 3643 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3644 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3645
3646 /* Border color in case we don't scale up to the full screen. Black by
3647 * default, change to something else for debugging. */
3648 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3649}
3650
89b667f8
JB		 3651static void valleyview_crtc_enable(struct drm_crtc *crtc)
3652{
3653 struct drm_device *dev = crtc->dev;
3654 struct drm_i915_private *dev_priv = dev->dev_private;
3655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3656 struct intel_encoder *encoder;
3657 int pipe = intel_crtc->pipe;
3658 int plane = intel_crtc->plane;
3659
3660 WARN_ON(!crtc->enabled);
3661
3662 if (intel_crtc->active)
3663 return;
3664
3665 intel_crtc->active = true;
3666 intel_update_watermarks(dev);
3667
3668 mutex_lock(&dev_priv->dpio_lock);
3669
3670 for_each_encoder_on_crtc(dev, crtc, encoder)
3671 if (encoder->pre_pll_enable)
3672 encoder->pre_pll_enable(encoder);
3673
3674 intel_enable_pll(dev_priv, pipe);
3675
3676 for_each_encoder_on_crtc(dev, crtc, encoder)
3677 if (encoder->pre_enable)
3678 encoder->pre_enable(encoder);
3679
3680 /* VLV wants encoder enabling _before_ the pipe is up. */
3681 for_each_encoder_on_crtc(dev, crtc, encoder)
3682 encoder->enable(encoder);
3683
2dd24552
JB		 3684 /* Enable panel fitting for eDP */
3685 i9xx_pfit_enable(intel_crtc);
3686
89b667f8
JB		 3687 intel_enable_pipe(dev_priv, pipe, false);
3688 intel_enable_plane(dev_priv, plane, pipe);
3689
3690 intel_crtc_load_lut(crtc);
3691 intel_update_fbc(dev);
3692
3693 /* Give the overlay scaler a chance to enable if it's on this pipe */
3694 intel_crtc_dpms_overlay(intel_crtc, true);
3695 intel_crtc_update_cursor(crtc, true);
3696
3697 mutex_unlock(&dev_priv->dpio_lock);
3698}
3699
0b8765c6 3700static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3701{
3702 struct drm_device *dev = crtc->dev;
79e53945
JB		 3703 struct drm_i915_private *dev_priv = dev->dev_private;
3704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3705 struct intel_encoder *encoder;
79e53945 3706 int pipe = intel_crtc->pipe;
80824003 3707 int plane = intel_crtc->plane;
79e53945 3708
08a48469
DV		 3709 WARN_ON(!crtc->enabled);
3710
f7abfe8b
CW		 3711 if (intel_crtc->active)
3712 return;
3713
3714 intel_crtc->active = true;
6b383a7f
CW		 3715 intel_update_watermarks(dev);
3716
63d7bbe9 3717 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3718
3719 for_each_encoder_on_crtc(dev, crtc, encoder)
3720 if (encoder->pre_enable)
3721 encoder->pre_enable(encoder);
3722
2dd24552
JB		 3723 /* Enable panel fitting for LVDS */
3724 i9xx_pfit_enable(intel_crtc);
3725
040484af 3726 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3727 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3728 if (IS_G4X(dev))
3729 g4x_fixup_plane(dev_priv, pipe);
79e53945 3730
0b8765c6 3731 intel_crtc_load_lut(crtc);
bed4a673 3732 intel_update_fbc(dev);
79e53945 3733
0b8765c6
JB		 3734 /* Give the overlay scaler a chance to enable if it's on this pipe */
3735 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3736 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3737
fa5c73b1
DV		 3738 for_each_encoder_on_crtc(dev, crtc, encoder)
3739 encoder->enable(encoder);
0b8765c6 3740}
79e53945 3741
87476d63
DV		 3742static void i9xx_pfit_disable(struct intel_crtc *crtc)
3743{
3744 struct drm_device *dev = crtc->base.dev;
3745 struct drm_i915_private *dev_priv = dev->dev_private;
3746 enum pipe pipe;
3747 uint32_t pctl = I915_READ(PFIT_CONTROL);
3748
3749 assert_pipe_disabled(dev_priv, crtc->pipe);
3750
3751 if (INTEL_INFO(dev)->gen >= 4)
3752 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3753 else
3754 pipe = PIPE_B;
3755
3756 if (pipe == crtc->pipe) {
3757 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3758 I915_WRITE(PFIT_CONTROL, 0);
3759 }
3760}
3761
0b8765c6
JB		 3762static void i9xx_crtc_disable(struct drm_crtc *crtc)
3763{
3764 struct drm_device *dev = crtc->dev;
3765 struct drm_i915_private *dev_priv = dev->dev_private;
3766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3767 struct intel_encoder *encoder;
0b8765c6
JB		 3768 int pipe = intel_crtc->pipe;
3769 int plane = intel_crtc->plane;
ef9c3aee 3770
f7abfe8b
CW		 3771 if (!intel_crtc->active)
3772 return;
3773
ea9d758d
DV		 3774 for_each_encoder_on_crtc(dev, crtc, encoder)
3775 encoder->disable(encoder);
3776
0b8765c6 3777 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3778 intel_crtc_wait_for_pending_flips(crtc);
3779 drm_vblank_off(dev, pipe);
0b8765c6 3780 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3781 intel_crtc_update_cursor(crtc, false);
0b8765c6 3782
973d04f9
CW		 3783 if (dev_priv->cfb_plane == plane)
3784 intel_disable_fbc(dev);
79e53945 3785
b24e7179 3786 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3787 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3788
87476d63 3789 i9xx_pfit_disable(intel_crtc);
24a1f16d 3790
89b667f8
JB		 3791 for_each_encoder_on_crtc(dev, crtc, encoder)
3792 if (encoder->post_disable)
3793 encoder->post_disable(encoder);
3794
63d7bbe9 3795 intel_disable_pll(dev_priv, pipe);
0b8765c6 3796
f7abfe8b 3797 intel_crtc->active = false;
6b383a7f
CW		 3798 intel_update_fbc(dev);
3799 intel_update_watermarks(dev);
0b8765c6
JB		 3800}
3801
ee7b9f93
JB		 3802static void i9xx_crtc_off(struct drm_crtc *crtc)
3803{
3804}
3805
976f8a20
DV		 3806static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3807 bool enabled)
2c07245f
ZW		 3808{
3809 struct drm_device *dev = crtc->dev;
3810 struct drm_i915_master_private *master_priv;
3811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3812 int pipe = intel_crtc->pipe;
79e53945
JB		 3813
3814 if (!dev->primary->master)
3815 return;
3816
3817 master_priv = dev->primary->master->driver_priv;
3818 if (!master_priv->sarea_priv)
3819 return;
3820
79e53945
JB		 3821 switch (pipe) {
3822 case 0:
3823 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3824 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3825 break;
3826 case 1:
3827 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3828 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3829 break;
3830 default:
9db4a9c7 3831 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3832 break;
3833 }
79e53945
JB		 3834}
3835
976f8a20
DV		 3836/**
3837 * Sets the power management mode of the pipe and plane.
3838 */
3839void intel_crtc_update_dpms(struct drm_crtc *crtc)
3840{
3841 struct drm_device *dev = crtc->dev;
3842 struct drm_i915_private *dev_priv = dev->dev_private;
3843 struct intel_encoder *intel_encoder;
3844 bool enable = false;
3845
3846 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3847 enable |= intel_encoder->connectors_active;
3848
3849 if (enable)
3850 dev_priv->display.crtc_enable(crtc);
3851 else
3852 dev_priv->display.crtc_disable(crtc);
3853
3854 intel_crtc_update_sarea(crtc, enable);
3855}
3856
cdd59983
CW		 3857static void intel_crtc_disable(struct drm_crtc *crtc)
3858{
cdd59983 3859 struct drm_device *dev = crtc->dev;
976f8a20 3860 struct drm_connector *connector;
ee7b9f93 3861 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3863
976f8a20
DV		 3864 /* crtc should still be enabled when we disable it. */
3865 WARN_ON(!crtc->enabled);
3866
3867 dev_priv->display.crtc_disable(crtc);
c77bf565 3868 intel_crtc->eld_vld = false;
976f8a20 3869 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3870 dev_priv->display.off(crtc);
3871
931872fc
CW		 3872 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3873 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3874
3875 if (crtc->fb) {
3876 mutex_lock(&dev->struct_mutex);
1690e1eb 3877 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3878 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3879 crtc->fb = NULL;
3880 }
3881
3882 /* Update computed state. */
3883 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3884 if (!connector->encoder || !connector->encoder->crtc)
3885 continue;
3886
3887 if (connector->encoder->crtc != crtc)
3888 continue;
3889
3890 connector->dpms = DRM_MODE_DPMS_OFF;
3891 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3892 }
3893}
3894
a261b246 3895void intel_modeset_disable(struct drm_device *dev)
79e53945 3896{
a261b246
DV		 3897 struct drm_crtc *crtc;
3898
3899 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3900 if (crtc->enabled)
3901 intel_crtc_disable(crtc);
3902 }
79e53945
JB		 3903}
3904
ea5b213a 3905void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3906{
4ef69c7a 3907 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3908
ea5b213a
CW		 3909 drm_encoder_cleanup(encoder);
3910 kfree(intel_encoder);
7e7d76c3
JB		 3911}
3912
5ab432ef
DV		 3913/* Simple dpms helper for encodres with just one connector, no cloning and only
3914 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3915 * state of the entire output pipe. */
3916void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3917{
5ab432ef
DV		 3918 if (mode == DRM_MODE_DPMS_ON) {
3919 encoder->connectors_active = true;
3920
b2cabb0e 3921 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3922 } else {
3923 encoder->connectors_active = false;
3924
b2cabb0e 3925 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3926 }
79e53945
JB		 3927}
3928
0a91ca29
DV		 3929/* Cross check the actual hw state with our own modeset state tracking (and it's
3930 * internal consistency). */
b980514c 3931static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3932{
0a91ca29
DV		 3933 if (connector->get_hw_state(connector)) {
3934 struct intel_encoder *encoder = connector->encoder;
3935 struct drm_crtc *crtc;
3936 bool encoder_enabled;
3937 enum pipe pipe;
3938
3939 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3940 connector->base.base.id,
3941 drm_get_connector_name(&connector->base));
3942
3943 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3944 "wrong connector dpms state\n");
3945 WARN(connector->base.encoder != &encoder->base,
3946 "active connector not linked to encoder\n");
3947 WARN(!encoder->connectors_active,
3948 "encoder->connectors_active not set\n");
3949
3950 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3951 WARN(!encoder_enabled, "encoder not enabled\n");
3952 if (WARN_ON(!encoder->base.crtc))
3953 return;
3954
3955 crtc = encoder->base.crtc;
3956
3957 WARN(!crtc->enabled, "crtc not enabled\n");
3958 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3959 WARN(pipe != to_intel_crtc(crtc)->pipe,
3960 "encoder active on the wrong pipe\n");
3961 }
79e53945
JB		 3962}
3963
5ab432ef
DV		 3964/* Even simpler default implementation, if there's really no special case to
3965 * consider. */
3966void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3967{
5ab432ef 3968 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3969
5ab432ef
DV		 3970 /* All the simple cases only support two dpms states. */
3971 if (mode != DRM_MODE_DPMS_ON)
3972 mode = DRM_MODE_DPMS_OFF;
d4270e57 3973
5ab432ef
DV		 3974 if (mode == connector->dpms)
3975 return;
3976
3977 connector->dpms = mode;
3978
3979 /* Only need to change hw state when actually enabled */
3980 if (encoder->base.crtc)
3981 intel_encoder_dpms(encoder, mode);
3982 else
8af6cf88 3983 WARN_ON(encoder->connectors_active != false);
0a91ca29 3984
b980514c 3985 intel_modeset_check_state(connector->dev);
79e53945
JB		 3986}
3987
f0947c37
DV		 3988/* Simple connector->get_hw_state implementation for encoders that support only
3989 * one connector and no cloning and hence the encoder state determines the state
3990 * of the connector. */
3991bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3992{
24929352 3993 enum pipe pipe = 0;
f0947c37 3994 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3995
f0947c37 3996 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3997}
3998
1857e1da
DV		 3999static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4000 struct intel_crtc_config *pipe_config)
4001{
4002 struct drm_i915_private *dev_priv = dev->dev_private;
4003 struct intel_crtc *pipe_B_crtc =
4004 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4005
4006 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4007 pipe_name(pipe), pipe_config->fdi_lanes);
4008 if (pipe_config->fdi_lanes > 4) {
4009 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4010 pipe_name(pipe), pipe_config->fdi_lanes);
4011 return false;
4012 }
4013
4014 if (IS_HASWELL(dev)) {
4015 if (pipe_config->fdi_lanes > 2) {
4016 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4017 pipe_config->fdi_lanes);
4018 return false;
4019 } else {
4020 return true;
4021 }
4022 }
4023
4024 if (INTEL_INFO(dev)->num_pipes == 2)
4025 return true;
4026
4027 /* Ivybridge 3 pipe is really complicated */
4028 switch (pipe) {
4029 case PIPE_A:
4030 return true;
4031 case PIPE_B:
4032 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4033 pipe_config->fdi_lanes > 2) {
4034 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4035 pipe_name(pipe), pipe_config->fdi_lanes);
4036 return false;
4037 }
4038 return true;
4039 case PIPE_C:
1e833f40 4040 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4041 pipe_B_crtc->config.fdi_lanes <= 2) {
4042 if (pipe_config->fdi_lanes > 2) {
4043 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4044 pipe_name(pipe), pipe_config->fdi_lanes);
4045 return false;
4046 }
4047 } else {
4048 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4049 return false;
4050 }
4051 return true;
4052 default:
4053 BUG();
4054 }
4055}
4056
e29c22c0
DV		 4057#define RETRY 1
4058static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4059 struct intel_crtc_config *pipe_config)
877d48d5 4060{
1857e1da 4061 struct drm_device *dev = intel_crtc->base.dev;
877d48d5
DV		 4062 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4063 int target_clock, lane, link_bw;
e29c22c0 4064 bool setup_ok, needs_recompute = false;
877d48d5 4065
e29c22c0 4066retry:
877d48d5
DV		 4067 /* FDI is a binary signal running at ~2.7GHz, encoding
4068 * each output octet as 10 bits. The actual frequency
4069 * is stored as a divider into a 100MHz clock, and the
4070 * mode pixel clock is stored in units of 1KHz.
4071 * Hence the bw of each lane in terms of the mode signal
4072 * is:
4073 */
4074 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4075
4076 if (pipe_config->pixel_target_clock)
4077 target_clock = pipe_config->pixel_target_clock;
4078 else
4079 target_clock = adjusted_mode->clock;
4080
4081 lane = ironlake_get_lanes_required(target_clock, link_bw,
4082 pipe_config->pipe_bpp);
4083
4084 pipe_config->fdi_lanes = lane;
4085
4086 if (pipe_config->pixel_multiplier > 1)
4087 link_bw *= pipe_config->pixel_multiplier;
4088 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4089 link_bw, &pipe_config->fdi_m_n);
1857e1da 4090
e29c22c0
DV		 4091 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4092 intel_crtc->pipe, pipe_config);
4093 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4094 pipe_config->pipe_bpp -= 2*3;
4095 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4096 pipe_config->pipe_bpp);
4097 needs_recompute = true;
4098 pipe_config->bw_constrained = true;
4099
4100 goto retry;
4101 }
4102
4103 if (needs_recompute)
4104 return RETRY;
4105
4106 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4107}
4108
e29c22c0
DV		 4109static int intel_crtc_compute_config(struct drm_crtc *crtc,
4110 struct intel_crtc_config *pipe_config)
79e53945 4111{
2c07245f 4112 struct drm_device *dev = crtc->dev;
b8cecdf5 4113 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4114
bad720ff 4115 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4116 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4117 if (pipe_config->requested_mode.clock * 3
4118 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4119 return -EINVAL;
2c07245f 4120 }
89749350 4121
f9bef081
DV		 4122 /* All interlaced capable intel hw wants timings in frames. Note though
4123 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4124 * timings, so we need to be careful not to clobber these.*/
7ae89233 4125 if (!pipe_config->timings_set)
f9bef081 4126 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4127
8693a824
DL		 4128 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4129 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4130 */
4131 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4132 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4133 return -EINVAL;
44f46b42 4134
bd080ee5 4135 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4136 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4137 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4138 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4139 * for lvds. */
4140 pipe_config->pipe_bpp = 8*3;
4141 }
4142
877d48d5 4143 if (pipe_config->has_pch_encoder)
1857e1da 4144 return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config);
877d48d5 4145
e29c22c0 4146 return 0;
79e53945
JB		 4147}
4148
25eb05fc
JB		 4149static int valleyview_get_display_clock_speed(struct drm_device *dev)
4150{
4151 return 400000; /* FIXME */
4152}
4153
e70236a8
JB		 4154static int i945_get_display_clock_speed(struct drm_device *dev)
4155{
4156 return 400000;
4157}
79e53945 4158
e70236a8 4159static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4160{
e70236a8
JB		 4161 return 333000;
4162}
79e53945 4163
e70236a8
JB		 4164static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4165{
4166 return 200000;
4167}
79e53945 4168
e70236a8
JB		 4169static int i915gm_get_display_clock_speed(struct drm_device *dev)
4170{
4171 u16 gcfgc = 0;
79e53945 4172
e70236a8
JB		 4173 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4174
4175 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4176 return 133000;
4177 else {
4178 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4179 case GC_DISPLAY_CLOCK_333_MHZ:
4180 return 333000;
4181 default:
4182 case GC_DISPLAY_CLOCK_190_200_MHZ:
4183 return 190000;
79e53945 4184 }
e70236a8
JB		 4185 }
4186}
4187
4188static int i865_get_display_clock_speed(struct drm_device *dev)
4189{
4190 return 266000;
4191}
4192
4193static int i855_get_display_clock_speed(struct drm_device *dev)
4194{
4195 u16 hpllcc = 0;
4196 /* Assume that the hardware is in the high speed state. This
4197 * should be the default.
4198 */
4199 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4200 case GC_CLOCK_133_200:
4201 case GC_CLOCK_100_200:
4202 return 200000;
4203 case GC_CLOCK_166_250:
4204 return 250000;
4205 case GC_CLOCK_100_133:
79e53945 4206 return 133000;
e70236a8 4207 }
79e53945 4208
e70236a8
JB		 4209 /* Shouldn't happen */
4210 return 0;
4211}
79e53945 4212
e70236a8
JB		 4213static int i830_get_display_clock_speed(struct drm_device *dev)
4214{
4215 return 133000;
79e53945
JB		 4216}
4217
2c07245f 4218static void
e69d0bc1 4219intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4220{
4221 while (*num > 0xffffff || *den > 0xffffff) {
4222 *num >>= 1;
4223 *den >>= 1;
4224 }
4225}
4226
e69d0bc1
DV		 4227void
4228intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4229 int pixel_clock, int link_clock,
4230 struct intel_link_m_n *m_n)
2c07245f 4231{
e69d0bc1 4232 m_n->tu = 64;
22ed1113
CW		 4233 m_n->gmch_m = bits_per_pixel * pixel_clock;
4234 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4235 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4236 m_n->link_m = pixel_clock;
4237 m_n->link_n = link_clock;
e69d0bc1 4238 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4239}
4240
a7615030
CW		 4241static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4242{
72bbe58c
KP		 4243 if (i915_panel_use_ssc >= 0)
4244 return i915_panel_use_ssc != 0;
4245 return dev_priv->lvds_use_ssc
435793df 4246 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4247}
4248
a0c4da24
JB		 4249static int vlv_get_refclk(struct drm_crtc *crtc)
4250{
4251 struct drm_device *dev = crtc->dev;
4252 struct drm_i915_private *dev_priv = dev->dev_private;
4253 int refclk = 27000; /* for DP & HDMI */
4254
4255 return 100000; /* only one validated so far */
4256
4257 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4258 refclk = 96000;
4259 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4260 if (intel_panel_use_ssc(dev_priv))
4261 refclk = 100000;
4262 else
4263 refclk = 96000;
4264 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4265 refclk = 100000;
4266 }
4267
4268 return refclk;
4269}
4270
c65d77d8
JB		 4271static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4272{
4273 struct drm_device *dev = crtc->dev;
4274 struct drm_i915_private *dev_priv = dev->dev_private;
4275 int refclk;
4276
a0c4da24
JB		 4277 if (IS_VALLEYVIEW(dev)) {
4278 refclk = vlv_get_refclk(crtc);
4279 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4280 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4281 refclk = dev_priv->lvds_ssc_freq * 1000;
4282 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4283 refclk / 1000);
4284 } else if (!IS_GEN2(dev)) {
4285 refclk = 96000;
4286 } else {
4287 refclk = 48000;
4288 }
4289
4290 return refclk;
4291}
4292
7429e9d4
DV		 4293static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4294{
4295 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4296}
4297
4298static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4299{
4300 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4301}
4302
f47709a9 4303static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4304 intel_clock_t *reduced_clock)
4305{
f47709a9 4306 struct drm_device *dev = crtc->base.dev;
a7516a05 4307 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4308 int pipe = crtc->pipe;
a7516a05
JB		 4309 u32 fp, fp2 = 0;
4310
4311 if (IS_PINEVIEW(dev)) {
7429e9d4 4312 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4313 if (reduced_clock)
7429e9d4 4314 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4315 } else {
7429e9d4 4316 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4317 if (reduced_clock)
7429e9d4 4318 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4319 }
4320
4321 I915_WRITE(FP0(pipe), fp);
4322
f47709a9
DV		 4323 crtc->lowfreq_avail = false;
4324 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4325 reduced_clock && i915_powersave) {
4326 I915_WRITE(FP1(pipe), fp2);
f47709a9 4327 crtc->lowfreq_avail = true;
a7516a05
JB		 4328 } else {
4329 I915_WRITE(FP1(pipe), fp);
4330 }
4331}
4332
89b667f8
JB		 4333static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4334{
4335 u32 reg_val;
4336
4337 /*
4338 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4339 * and set it to a reasonable value instead.
4340 */
4341 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4342 reg_val &= 0xffffff00;
4343 reg_val |= 0x00000030;
4344 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4345
4346 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4347 reg_val &= 0x8cffffff;
4348 reg_val = 0x8c000000;
4349 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4350
4351 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4352 reg_val &= 0xffffff00;
4353 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4354
4355 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4356 reg_val &= 0x00ffffff;
4357 reg_val |= 0xb0000000;
4358 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4359}
4360
b551842d
DV		 4361static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4362 struct intel_link_m_n *m_n)
4363{
4364 struct drm_device *dev = crtc->base.dev;
4365 struct drm_i915_private *dev_priv = dev->dev_private;
4366 int pipe = crtc->pipe;
4367
e3b95f1e
DV		 4368 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4369 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4370 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4371 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4372}
4373
4374static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4375 struct intel_link_m_n *m_n)
4376{
4377 struct drm_device *dev = crtc->base.dev;
4378 struct drm_i915_private *dev_priv = dev->dev_private;
4379 int pipe = crtc->pipe;
4380 enum transcoder transcoder = crtc->config.cpu_transcoder;
4381
4382 if (INTEL_INFO(dev)->gen >= 5) {
4383 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4384 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4385 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4386 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4387 } else {
e3b95f1e
DV		 4388 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4389 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4390 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4391 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4392 }
4393}
4394
03afc4a2
DV		 4395static void intel_dp_set_m_n(struct intel_crtc *crtc)
4396{
4397 if (crtc->config.has_pch_encoder)
4398 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4399 else
4400 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4401}
4402
f47709a9 4403static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4404{
f47709a9 4405 struct drm_device *dev = crtc->base.dev;
a0c4da24 4406 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8
JB		 4407 struct drm_display_mode *adjusted_mode =
4408 &crtc->config.adjusted_mode;
4409 struct intel_encoder *encoder;
f47709a9 4410 int pipe = crtc->pipe;
89b667f8 4411 u32 dpll, mdiv;
a0c4da24 4412 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4413 bool is_hdmi;
198a037f 4414 u32 coreclk, reg_val, dpll_md;
a0c4da24 4415
09153000
DV		 4416 mutex_lock(&dev_priv->dpio_lock);
4417
89b667f8 4418 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4419
f47709a9
DV		 4420 bestn = crtc->config.dpll.n;
4421 bestm1 = crtc->config.dpll.m1;
4422 bestm2 = crtc->config.dpll.m2;
4423 bestp1 = crtc->config.dpll.p1;
4424 bestp2 = crtc->config.dpll.p2;
a0c4da24 4425
89b667f8
JB		 4426 /* See eDP HDMI DPIO driver vbios notes doc */
4427
4428 /* PLL B needs special handling */
4429 if (pipe)
4430 vlv_pllb_recal_opamp(dev_priv);
4431
4432 /* Set up Tx target for periodic Rcomp update */
4433 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4434
4435 /* Disable target IRef on PLL */
4436 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4437 reg_val &= 0x00ffffff;
4438 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4439
4440 /* Disable fast lock */
4441 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4442
4443 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4444 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4445 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4446 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4447 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4448
4449 /*
4450 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4451 * but we don't support that).
4452 * Note: don't use the DAC post divider as it seems unstable.
4453 */
4454 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
a0c4da24
JB		 4455 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4456
89b667f8
JB		 4457 mdiv |= DPIO_ENABLE_CALIBRATION;
4458 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4459
89b667f8
JB		 4460 /* Set HBR and RBR LPF coefficients */
4461 if (adjusted_mode->clock == 162000 ||
4462 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4463 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4464 0x005f0021);
4465 else
4466 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4467 0x00d0000f);
4468
4469 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4470 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4471 /* Use SSC source */
4472 if (!pipe)
4473 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4474 0x0df40000);
4475 else
4476 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4477 0x0df70000);
4478 } else { /* HDMI or VGA */
4479 /* Use bend source */
4480 if (!pipe)
4481 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4482 0x0df70000);
4483 else
4484 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4485 0x0df40000);
4486 }
a0c4da24 4487
89b667f8
JB		 4488 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4489 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4490 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4491 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4492 coreclk |= 0x01000000;
4493 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4494
89b667f8 4495 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4496
89b667f8
JB		 4497 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4498 if (encoder->pre_pll_enable)
4499 encoder->pre_pll_enable(encoder);
2a8f64ca 4500
89b667f8
JB		 4501 /* Enable DPIO clock input */
4502 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4503 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4504 if (pipe)
4505 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4506
89b667f8 4507 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4508 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4509 POSTING_READ(DPLL(pipe));
4510 udelay(150);
a0c4da24 4511
89b667f8
JB		 4512 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4513 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4514
198a037f
DV		 4515 dpll_md = 0;
4516 if (crtc->config.pixel_multiplier > 1) {
4517 dpll_md = (crtc->config.pixel_multiplier - 1)
4518 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
2a8f64ca 4519 }
198a037f
DV		 4520 I915_WRITE(DPLL_MD(pipe), dpll_md);
4521 POSTING_READ(DPLL_MD(pipe));
f47709a9 4522
89b667f8
JB		 4523 if (crtc->config.has_dp_encoder)
4524 intel_dp_set_m_n(crtc);
09153000
DV		 4525
4526 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4527}
4528
f47709a9
DV		 4529static void i9xx_update_pll(struct intel_crtc *crtc,
4530 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4531 int num_connectors)
4532{
f47709a9 4533 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4534 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4535 struct intel_encoder *encoder;
f47709a9 4536 int pipe = crtc->pipe;
eb1cbe48
DV		 4537 u32 dpll;
4538 bool is_sdvo;
f47709a9 4539 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4540
f47709a9 4541 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4542
f47709a9
DV		 4543 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4544 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4545
4546 dpll = DPLL_VGA_MODE_DIS;
4547
f47709a9 4548 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4549 dpll |= DPLLB_MODE_LVDS;
4550 else
4551 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4552
198a037f
DV		 4553 if ((crtc->config.pixel_multiplier > 1) &&
4554 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4555 dpll |= (crtc->config.pixel_multiplier - 1)
4556 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4557 }
198a037f
DV		 4558
4559 if (is_sdvo)
4560 dpll |= DPLL_DVO_HIGH_SPEED;
4561
f47709a9 4562 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4563 dpll |= DPLL_DVO_HIGH_SPEED;
4564
4565 /* compute bitmask from p1 value */
4566 if (IS_PINEVIEW(dev))
4567 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4568 else {
4569 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4570 if (IS_G4X(dev) && reduced_clock)
4571 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4572 }
4573 switch (clock->p2) {
4574 case 5:
4575 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4576 break;
4577 case 7:
4578 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4579 break;
4580 case 10:
4581 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4582 break;
4583 case 14:
4584 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4585 break;
4586 }
4587 if (INTEL_INFO(dev)->gen >= 4)
4588 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4589
09ede541 4590 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4591 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4592 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4593 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4594 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4595 else
4596 dpll |= PLL_REF_INPUT_DREFCLK;
4597
4598 dpll |= DPLL_VCO_ENABLE;
4599 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4600 POSTING_READ(DPLL(pipe));
4601 udelay(150);
4602
f47709a9 4603 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4604 if (encoder->pre_pll_enable)
4605 encoder->pre_pll_enable(encoder);
eb1cbe48 4606
f47709a9
DV		 4607 if (crtc->config.has_dp_encoder)
4608 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4609
4610 I915_WRITE(DPLL(pipe), dpll);
4611
4612 /* Wait for the clocks to stabilize. */
4613 POSTING_READ(DPLL(pipe));
4614 udelay(150);
4615
4616 if (INTEL_INFO(dev)->gen >= 4) {
198a037f
DV		 4617 u32 dpll_md = 0;
4618 if (crtc->config.pixel_multiplier > 1) {
4619 dpll_md = (crtc->config.pixel_multiplier - 1)
4620 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
eb1cbe48 4621 }
198a037f 4622 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4623 } else {
4624 /* The pixel multiplier can only be updated once the
4625 * DPLL is enabled and the clocks are stable.
4626 *
4627 * So write it again.
4628 */
4629 I915_WRITE(DPLL(pipe), dpll);
4630 }
4631}
4632
f47709a9 4633static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4634 struct drm_display_mode *adjusted_mode,
f47709a9 4635 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4636 int num_connectors)
4637{
f47709a9 4638 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4639 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4640 struct intel_encoder *encoder;
f47709a9 4641 int pipe = crtc->pipe;
eb1cbe48 4642 u32 dpll;
f47709a9 4643 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4644
f47709a9 4645 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4646
eb1cbe48
DV		 4647 dpll = DPLL_VGA_MODE_DIS;
4648
f47709a9 4649 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4650 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4651 } else {
4652 if (clock->p1 == 2)
4653 dpll |= PLL_P1_DIVIDE_BY_TWO;
4654 else
4655 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4656 if (clock->p2 == 4)
4657 dpll |= PLL_P2_DIVIDE_BY_4;
4658 }
4659
f47709a9 4660 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4661 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4662 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4663 else
4664 dpll |= PLL_REF_INPUT_DREFCLK;
4665
4666 dpll |= DPLL_VCO_ENABLE;
4667 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4668 POSTING_READ(DPLL(pipe));
4669 udelay(150);
4670
f47709a9 4671 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4672 if (encoder->pre_pll_enable)
4673 encoder->pre_pll_enable(encoder);
eb1cbe48 4674
5b5896e4
DV		 4675 I915_WRITE(DPLL(pipe), dpll);
4676
4677 /* Wait for the clocks to stabilize. */
4678 POSTING_READ(DPLL(pipe));
4679 udelay(150);
4680
eb1cbe48
DV		 4681 /* The pixel multiplier can only be updated once the
4682 * DPLL is enabled and the clocks are stable.
4683 *
4684 * So write it again.
4685 */
4686 I915_WRITE(DPLL(pipe), dpll);
4687}
4688
b0e77b9c
PZ		 4689static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4690 struct drm_display_mode *mode,
4691 struct drm_display_mode *adjusted_mode)
4692{
4693 struct drm_device *dev = intel_crtc->base.dev;
4694 struct drm_i915_private *dev_priv = dev->dev_private;
4695 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4696 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4d8a62ea
DV		 4697 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4698
4699 /* We need to be careful not to changed the adjusted mode, for otherwise
4700 * the hw state checker will get angry at the mismatch. */
4701 crtc_vtotal = adjusted_mode->crtc_vtotal;
4702 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4703
4704 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4705 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4706 crtc_vtotal -= 1;
4707 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4708 vsyncshift = adjusted_mode->crtc_hsync_start
4709 - adjusted_mode->crtc_htotal / 2;
4710 } else {
4711 vsyncshift = 0;
4712 }
4713
4714 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4715 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4716
fe2b8f9d 4717 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4718 (adjusted_mode->crtc_hdisplay - 1) |
4719 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4720 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4721 (adjusted_mode->crtc_hblank_start - 1) |
4722 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4723 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4724 (adjusted_mode->crtc_hsync_start - 1) |
4725 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4726
fe2b8f9d 4727 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4728 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4729 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4730 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4731 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4732 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4733 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4734 (adjusted_mode->crtc_vsync_start - 1) |
4735 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4736
b5e508d4
PZ		 4737 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4738 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4739 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4740 * bits. */
4741 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4742 (pipe == PIPE_B || pipe == PIPE_C))
4743 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4744
b0e77b9c
PZ		 4745 /* pipesrc controls the size that is scaled from, which should
4746 * always be the user's requested size.
4747 */
4748 I915_WRITE(PIPESRC(pipe),
4749 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4750}
4751
1bd1bd80
DV		 4752static void intel_get_pipe_timings(struct intel_crtc *crtc,
4753 struct intel_crtc_config *pipe_config)
4754{
4755 struct drm_device *dev = crtc->base.dev;
4756 struct drm_i915_private *dev_priv = dev->dev_private;
4757 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4758 uint32_t tmp;
4759
4760 tmp = I915_READ(HTOTAL(cpu_transcoder));
4761 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4762 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4763 tmp = I915_READ(HBLANK(cpu_transcoder));
4764 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4765 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4766 tmp = I915_READ(HSYNC(cpu_transcoder));
4767 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4768 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4769
4770 tmp = I915_READ(VTOTAL(cpu_transcoder));
4771 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4772 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4773 tmp = I915_READ(VBLANK(cpu_transcoder));
4774 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4775 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4776 tmp = I915_READ(VSYNC(cpu_transcoder));
4777 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4778 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4779
4780 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4781 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4782 pipe_config->adjusted_mode.crtc_vtotal += 1;
4783 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4784 }
4785
4786 tmp = I915_READ(PIPESRC(crtc->pipe));
4787 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4788 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4789}
4790
84b046f3
DV		 4791static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4792{
4793 struct drm_device *dev = intel_crtc->base.dev;
4794 struct drm_i915_private *dev_priv = dev->dev_private;
4795 uint32_t pipeconf;
4796
4797 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4798
4799 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4800 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4801 * core speed.
4802 *
4803 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4804 * pipe == 0 check?
4805 */
4806 if (intel_crtc->config.requested_mode.clock >
4807 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4808 pipeconf |= PIPECONF_DOUBLE_WIDE;
4809 else
4810 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4811 }
4812
ff9ce46e
DV		 4813 /* only g4x and later have fancy bpc/dither controls */
4814 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4815 pipeconf &= ~(PIPECONF_BPC_MASK |
4816 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4817
4818 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4819 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4820 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4821 PIPECONF_DITHER_TYPE_SP;
84b046f3 4822
ff9ce46e
DV		 4823 switch (intel_crtc->config.pipe_bpp) {
4824 case 18:
4825 pipeconf |= PIPECONF_6BPC;
4826 break;
4827 case 24:
4828 pipeconf |= PIPECONF_8BPC;
4829 break;
4830 case 30:
4831 pipeconf |= PIPECONF_10BPC;
4832 break;
4833 default:
4834 /* Case prevented by intel_choose_pipe_bpp_dither. */
4835 BUG();
84b046f3
DV		 4836 }
4837 }
4838
4839 if (HAS_PIPE_CXSR(dev)) {
4840 if (intel_crtc->lowfreq_avail) {
4841 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4842 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4843 } else {
4844 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4845 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4846 }
4847 }
4848
4849 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4850 if (!IS_GEN2(dev) &&
4851 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4852 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4853 else
4854 pipeconf |= PIPECONF_PROGRESSIVE;
4855
9c8e09b7
VS		 4856 if (IS_VALLEYVIEW(dev)) {
4857 if (intel_crtc->config.limited_color_range)
4858 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4859 else
4860 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4861 }
4862
84b046f3
DV		 4863 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4864 POSTING_READ(PIPECONF(intel_crtc->pipe));
4865}
4866
f564048e 4867static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4868 int x, int y,
94352cf9 4869 struct drm_framebuffer *fb)
79e53945
JB		 4870{
4871 struct drm_device *dev = crtc->dev;
4872 struct drm_i915_private *dev_priv = dev->dev_private;
4873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4874 struct drm_display_mode *adjusted_mode =
4875 &intel_crtc->config.adjusted_mode;
4876 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4877 int pipe = intel_crtc->pipe;
80824003 4878 int plane = intel_crtc->plane;
c751ce4f 4879 int refclk, num_connectors = 0;
652c393a 4880 intel_clock_t clock, reduced_clock;
84b046f3 4881 u32 dspcntr;
a16af721
DV		 4882 bool ok, has_reduced_clock = false;
4883 bool is_lvds = false;
5eddb70b 4884 struct intel_encoder *encoder;
d4906093 4885 const intel_limit_t *limit;
5c3b82e2 4886 int ret;
79e53945 4887
6c2b7c12 4888 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4889 switch (encoder->type) {
79e53945
JB		 4890 case INTEL_OUTPUT_LVDS:
4891 is_lvds = true;
4892 break;
79e53945 4893 }
43565a06 4894
c751ce4f 4895 num_connectors++;
79e53945
JB		 4896 }
4897
c65d77d8 4898 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4899
d4906093
ML		 4900 /*
4901 * Returns a set of divisors for the desired target clock with the given
4902 * refclk, or FALSE. The returned values represent the clock equation:
4903 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4904 */
1b894b59 4905 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4906 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4907 &clock);
79e53945
JB		 4908 if (!ok) {
4909 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4910 return -EINVAL;
79e53945
JB		 4911 }
4912
cda4b7d3 4913 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4914 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4915
ddc9003c 4916 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4917 /*
4918 * Ensure we match the reduced clock's P to the target clock.
4919 * If the clocks don't match, we can't switch the display clock
4920 * by using the FP0/FP1. In such case we will disable the LVDS
4921 * downclock feature.
4922 */
ddc9003c 4923 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4924 dev_priv->lvds_downclock,
4925 refclk,
cec2f356 4926 &clock,
5eddb70b 4927 &reduced_clock);
7026d4ac 4928 }
f47709a9
DV		 4929 /* Compat-code for transition, will disappear. */
4930 if (!intel_crtc->config.clock_set) {
4931 intel_crtc->config.dpll.n = clock.n;
4932 intel_crtc->config.dpll.m1 = clock.m1;
4933 intel_crtc->config.dpll.m2 = clock.m2;
4934 intel_crtc->config.dpll.p1 = clock.p1;
4935 intel_crtc->config.dpll.p2 = clock.p2;
4936 }
7026d4ac 4937
eb1cbe48 4938 if (IS_GEN2(dev))
f47709a9 4939 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4940 has_reduced_clock ? &reduced_clock : NULL,
4941 num_connectors);
a0c4da24 4942 else if (IS_VALLEYVIEW(dev))
f47709a9 4943 vlv_update_pll(intel_crtc);
79e53945 4944 else
f47709a9 4945 i9xx_update_pll(intel_crtc,
eb1cbe48 4946 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4947 num_connectors);
79e53945 4948
79e53945
JB		 4949 /* Set up the display plane register */
4950 dspcntr = DISPPLANE_GAMMA_ENABLE;
4951
da6ecc5d
JB		 4952 if (!IS_VALLEYVIEW(dev)) {
4953 if (pipe == 0)
4954 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4955 else
4956 dspcntr |= DISPPLANE_SEL_PIPE_B;
4957 }
79e53945 4958
2582a850 4959 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 4960 drm_mode_debug_printmodeline(mode);
4961
b0e77b9c 4962 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4963
4964 /* pipesrc and dspsize control the size that is scaled from,
4965 * which should always be the user's requested size.
79e53945 4966 */
929c77fb
EA		 4967 I915_WRITE(DSPSIZE(plane),
4968 ((mode->vdisplay - 1) << 16) |
4969 (mode->hdisplay - 1));
4970 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4971
84b046f3
DV		 4972 i9xx_set_pipeconf(intel_crtc);
4973
f564048e
EA		 4974 I915_WRITE(DSPCNTR(plane), dspcntr);
4975 POSTING_READ(DSPCNTR(plane));
4976
94352cf9 4977 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4978
4979 intel_update_watermarks(dev);
4980
f564048e
EA		 4981 return ret;
4982}
4983
0e8ffe1b
DV		 4984static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4985 struct intel_crtc_config *pipe_config)
4986{
4987 struct drm_device *dev = crtc->base.dev;
4988 struct drm_i915_private *dev_priv = dev->dev_private;
4989 uint32_t tmp;
4990
4991 tmp = I915_READ(PIPECONF(crtc->pipe));
4992 if (!(tmp & PIPECONF_ENABLE))
4993 return false;
4994
1bd1bd80
DV		 4995 intel_get_pipe_timings(crtc, pipe_config);
4996
0e8ffe1b
DV		 4997 return true;
4998}
4999
dde86e2d 5000static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5001{
5002 struct drm_i915_private *dev_priv = dev->dev_private;
5003 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5004 struct intel_encoder *encoder;
74cfd7ac 5005 u32 val, final;
13d83a67 5006 bool has_lvds = false;
199e5d79 5007 bool has_cpu_edp = false;
199e5d79 5008 bool has_panel = false;
99eb6a01
KP		 5009 bool has_ck505 = false;
5010 bool can_ssc = false;
13d83a67
JB		 5011
5012 /* We need to take the global config into account */
199e5d79
KP		 5013 list_for_each_entry(encoder, &mode_config->encoder_list,
5014 base.head) {
5015 switch (encoder->type) {
5016 case INTEL_OUTPUT_LVDS:
5017 has_panel = true;
5018 has_lvds = true;
5019 break;
5020 case INTEL_OUTPUT_EDP:
5021 has_panel = true;
2de6905f 5022 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5023 has_cpu_edp = true;
5024 break;
13d83a67
JB		 5025 }
5026 }
5027
99eb6a01
KP		 5028 if (HAS_PCH_IBX(dev)) {
5029 has_ck505 = dev_priv->display_clock_mode;
5030 can_ssc = has_ck505;
5031 } else {
5032 has_ck505 = false;
5033 can_ssc = true;
5034 }
5035
2de6905f
ID		 5036 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5037 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5038
5039 /* Ironlake: try to setup display ref clock before DPLL
5040 * enabling. This is only under driver's control after
5041 * PCH B stepping, previous chipset stepping should be
5042 * ignoring this setting.
5043 */
74cfd7ac
CW		 5044 val = I915_READ(PCH_DREF_CONTROL);
5045
5046 /* As we must carefully and slowly disable/enable each source in turn,
5047 * compute the final state we want first and check if we need to
5048 * make any changes at all.
5049 */
5050 final = val;
5051 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5052 if (has_ck505)
5053 final |= DREF_NONSPREAD_CK505_ENABLE;
5054 else
5055 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5056
5057 final &= ~DREF_SSC_SOURCE_MASK;
5058 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5059 final &= ~DREF_SSC1_ENABLE;
5060
5061 if (has_panel) {
5062 final |= DREF_SSC_SOURCE_ENABLE;
5063
5064 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5065 final |= DREF_SSC1_ENABLE;
5066
5067 if (has_cpu_edp) {
5068 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5069 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5070 else
5071 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5072 } else
5073 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5074 } else {
5075 final |= DREF_SSC_SOURCE_DISABLE;
5076 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5077 }
5078
5079 if (final == val)
5080 return;
5081
13d83a67 5082 /* Always enable nonspread source */
74cfd7ac 5083 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5084
99eb6a01 5085 if (has_ck505)
74cfd7ac 5086 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5087 else
74cfd7ac 5088 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5089
199e5d79 5090 if (has_panel) {
74cfd7ac
CW		 5091 val &= ~DREF_SSC_SOURCE_MASK;
5092 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5093
199e5d79 5094 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5095 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5096 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5097 val |= DREF_SSC1_ENABLE;
e77166b5 5098 } else
74cfd7ac 5099 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5100
5101 /* Get SSC going before enabling the outputs */
74cfd7ac 5102 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5103 POSTING_READ(PCH_DREF_CONTROL);
5104 udelay(200);
5105
74cfd7ac 5106 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5107
5108 /* Enable CPU source on CPU attached eDP */
199e5d79 5109 if (has_cpu_edp) {
99eb6a01 5110 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5111 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5112 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5113 }
13d83a67 5114 else
74cfd7ac 5115 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5116 } else
74cfd7ac 5117 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5118
74cfd7ac 5119 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5120 POSTING_READ(PCH_DREF_CONTROL);
5121 udelay(200);
5122 } else {
5123 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5124
74cfd7ac 5125 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5126
5127 /* Turn off CPU output */
74cfd7ac 5128 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5129
74cfd7ac 5130 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5131 POSTING_READ(PCH_DREF_CONTROL);
5132 udelay(200);
5133
5134 /* Turn off the SSC source */
74cfd7ac
CW		 5135 val &= ~DREF_SSC_SOURCE_MASK;
5136 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5137
5138 /* Turn off SSC1 */
74cfd7ac 5139 val &= ~DREF_SSC1_ENABLE;
199e5d79 5140
74cfd7ac 5141 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5142 POSTING_READ(PCH_DREF_CONTROL);
5143 udelay(200);
5144 }
74cfd7ac
CW		 5145
5146 BUG_ON(val != final);
13d83a67
JB		 5147}
5148
dde86e2d
PZ		 5149/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5150static void lpt_init_pch_refclk(struct drm_device *dev)
5151{
5152 struct drm_i915_private *dev_priv = dev->dev_private;
5153 struct drm_mode_config *mode_config = &dev->mode_config;
5154 struct intel_encoder *encoder;
5155 bool has_vga = false;
5156 bool is_sdv = false;
5157 u32 tmp;
5158
5159 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5160 switch (encoder->type) {
5161 case INTEL_OUTPUT_ANALOG:
5162 has_vga = true;
5163 break;
5164 }
5165 }
5166
5167 if (!has_vga)
5168 return;
5169
c00db246
DV		 5170 mutex_lock(&dev_priv->dpio_lock);
5171
dde86e2d
PZ		 5172 /* XXX: Rip out SDV support once Haswell ships for real. */
5173 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5174 is_sdv = true;
5175
5176 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5177 tmp &= ~SBI_SSCCTL_DISABLE;
5178 tmp |= SBI_SSCCTL_PATHALT;
5179 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5180
5181 udelay(24);
5182
5183 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5184 tmp &= ~SBI_SSCCTL_PATHALT;
5185 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5186
5187 if (!is_sdv) {
5188 tmp = I915_READ(SOUTH_CHICKEN2);
5189 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5190 I915_WRITE(SOUTH_CHICKEN2, tmp);
5191
5192 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5193 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5194 DRM_ERROR("FDI mPHY reset assert timeout\n");
5195
5196 tmp = I915_READ(SOUTH_CHICKEN2);
5197 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5198 I915_WRITE(SOUTH_CHICKEN2, tmp);
5199
5200 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5201 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5202 100))
5203 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5204 }
5205
5206 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5207 tmp &= ~(0xFF << 24);
5208 tmp |= (0x12 << 24);
5209 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5210
dde86e2d
PZ		 5211 if (is_sdv) {
5212 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5213 tmp |= 0x7FFF;
5214 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5215 }
5216
5217 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5218 tmp |= (1 << 11);
5219 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5220
5221 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5222 tmp |= (1 << 11);
5223 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5224
5225 if (is_sdv) {
5226 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5227 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5228 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5229
5230 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5231 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5232 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5233
5234 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5235 tmp |= (0x3F << 8);
5236 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5237
5238 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5239 tmp |= (0x3F << 8);
5240 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5241 }
5242
5243 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5244 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5245 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5246
5247 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5248 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5249 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5250
5251 if (!is_sdv) {
5252 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5253 tmp &= ~(7 << 13);
5254 tmp |= (5 << 13);
5255 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5256
5257 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5258 tmp &= ~(7 << 13);
5259 tmp |= (5 << 13);
5260 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5261 }
5262
5263 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5264 tmp &= ~0xFF;
5265 tmp |= 0x1C;
5266 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5267
5268 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5269 tmp &= ~0xFF;
5270 tmp |= 0x1C;
5271 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5272
5273 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5274 tmp &= ~(0xFF << 16);
5275 tmp |= (0x1C << 16);
5276 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5277
5278 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5279 tmp &= ~(0xFF << 16);
5280 tmp |= (0x1C << 16);
5281 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5282
5283 if (!is_sdv) {
5284 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5285 tmp |= (1 << 27);
5286 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5287
5288 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5289 tmp |= (1 << 27);
5290 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5291
5292 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5293 tmp &= ~(0xF << 28);
5294 tmp |= (4 << 28);
5295 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5296
5297 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5298 tmp &= ~(0xF << 28);
5299 tmp |= (4 << 28);
5300 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5301 }
5302
5303 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5304 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5305 tmp |= SBI_DBUFF0_ENABLE;
5306 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5307
5308 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5309}
5310
5311/*
5312 * Initialize reference clocks when the driver loads
5313 */
5314void intel_init_pch_refclk(struct drm_device *dev)
5315{
5316 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5317 ironlake_init_pch_refclk(dev);
5318 else if (HAS_PCH_LPT(dev))
5319 lpt_init_pch_refclk(dev);
5320}
5321
d9d444cb
JB		 5322static int ironlake_get_refclk(struct drm_crtc *crtc)
5323{
5324 struct drm_device *dev = crtc->dev;
5325 struct drm_i915_private *dev_priv = dev->dev_private;
5326 struct intel_encoder *encoder;
d9d444cb
JB		 5327 int num_connectors = 0;
5328 bool is_lvds = false;
5329
6c2b7c12 5330 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5331 switch (encoder->type) {
5332 case INTEL_OUTPUT_LVDS:
5333 is_lvds = true;
5334 break;
d9d444cb
JB		 5335 }
5336 num_connectors++;
5337 }
5338
5339 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5340 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5341 dev_priv->lvds_ssc_freq);
5342 return dev_priv->lvds_ssc_freq * 1000;
5343 }
5344
5345 return 120000;
5346}
5347
6ff93609 5348static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5349{
c8203565 5350 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5352 int pipe = intel_crtc->pipe;
c8203565
PZ		 5353 uint32_t val;
5354
5355 val = I915_READ(PIPECONF(pipe));
5356
dfd07d72 5357 val &= ~PIPECONF_BPC_MASK;
965e0c48 5358 switch (intel_crtc->config.pipe_bpp) {
c8203565 5359 case 18:
dfd07d72 5360 val |= PIPECONF_6BPC;
c8203565
PZ		 5361 break;
5362 case 24:
dfd07d72 5363 val |= PIPECONF_8BPC;
c8203565
PZ		 5364 break;
5365 case 30:
dfd07d72 5366 val |= PIPECONF_10BPC;
c8203565
PZ		 5367 break;
5368 case 36:
dfd07d72 5369 val |= PIPECONF_12BPC;
c8203565
PZ		 5370 break;
5371 default:
cc769b62
PZ		 5372 /* Case prevented by intel_choose_pipe_bpp_dither. */
5373 BUG();
c8203565
PZ		 5374 }
5375
5376 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5377 if (intel_crtc->config.dither)
c8203565
PZ		 5378 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5379
5380 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5381 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5382 val |= PIPECONF_INTERLACED_ILK;
5383 else
5384 val |= PIPECONF_PROGRESSIVE;
5385
50f3b016 5386 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5387 val |= PIPECONF_COLOR_RANGE_SELECT;
5388 else
5389 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5390
c8203565
PZ		 5391 I915_WRITE(PIPECONF(pipe), val);
5392 POSTING_READ(PIPECONF(pipe));
5393}
5394
86d3efce
VS		 5395/*
5396 * Set up the pipe CSC unit.
5397 *
5398 * Currently only full range RGB to limited range RGB conversion
5399 * is supported, but eventually this should handle various
5400 * RGB<->YCbCr scenarios as well.
5401 */
50f3b016 5402static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5403{
5404 struct drm_device *dev = crtc->dev;
5405 struct drm_i915_private *dev_priv = dev->dev_private;
5406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5407 int pipe = intel_crtc->pipe;
5408 uint16_t coeff = 0x7800; /* 1.0 */
5409
5410 /*
5411 * TODO: Check what kind of values actually come out of the pipe
5412 * with these coeff/postoff values and adjust to get the best
5413 * accuracy. Perhaps we even need to take the bpc value into
5414 * consideration.
5415 */
5416
50f3b016 5417 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5418 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5419
5420 /*
5421 * GY/GU and RY/RU should be the other way around according
5422 * to BSpec, but reality doesn't agree. Just set them up in
5423 * a way that results in the correct picture.
5424 */
5425 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5426 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5427
5428 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5429 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5430
5431 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5432 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5433
5434 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5435 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5436 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5437
5438 if (INTEL_INFO(dev)->gen > 6) {
5439 uint16_t postoff = 0;
5440
50f3b016 5441 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5442 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5443
5444 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5445 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5446 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5447
5448 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5449 } else {
5450 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5451
50f3b016 5452 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5453 mode |= CSC_BLACK_SCREEN_OFFSET;
5454
5455 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5456 }
5457}
5458
6ff93609 5459static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5460{
5461 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5463 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5464 uint32_t val;
5465
702e7a56 5466 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5467
5468 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5469 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5470 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5471
5472 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5473 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5474 val |= PIPECONF_INTERLACED_ILK;
5475 else
5476 val |= PIPECONF_PROGRESSIVE;
5477
702e7a56
PZ		 5478 I915_WRITE(PIPECONF(cpu_transcoder), val);
5479 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5480}
5481
6591c6e4
PZ		 5482static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5483 struct drm_display_mode *adjusted_mode,
5484 intel_clock_t *clock,
5485 bool *has_reduced_clock,
5486 intel_clock_t *reduced_clock)
5487{
5488 struct drm_device *dev = crtc->dev;
5489 struct drm_i915_private *dev_priv = dev->dev_private;
5490 struct intel_encoder *intel_encoder;
5491 int refclk;
d4906093 5492 const intel_limit_t *limit;
a16af721 5493 bool ret, is_lvds = false;
79e53945 5494
6591c6e4
PZ		 5495 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5496 switch (intel_encoder->type) {
79e53945
JB		 5497 case INTEL_OUTPUT_LVDS:
5498 is_lvds = true;
5499 break;
79e53945
JB		 5500 }
5501 }
5502
d9d444cb 5503 refclk = ironlake_get_refclk(crtc);
79e53945 5504
d4906093
ML		 5505 /*
5506 * Returns a set of divisors for the desired target clock with the given
5507 * refclk, or FALSE. The returned values represent the clock equation:
5508 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5509 */
1b894b59 5510 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5511 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5512 clock);
5513 if (!ret)
5514 return false;
cda4b7d3 5515
ddc9003c 5516 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5517 /*
5518 * Ensure we match the reduced clock's P to the target clock.
5519 * If the clocks don't match, we can't switch the display clock
5520 * by using the FP0/FP1. In such case we will disable the LVDS
5521 * downclock feature.
5522 */
6591c6e4
PZ		 5523 *has_reduced_clock = limit->find_pll(limit, crtc,
5524 dev_priv->lvds_downclock,
5525 refclk,
5526 clock,
5527 reduced_clock);
652c393a 5528 }
61e9653f 5529
6591c6e4
PZ		 5530 return true;
5531}
5532
01a415fd
DV		 5533static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5534{
5535 struct drm_i915_private *dev_priv = dev->dev_private;
5536 uint32_t temp;
5537
5538 temp = I915_READ(SOUTH_CHICKEN1);
5539 if (temp & FDI_BC_BIFURCATION_SELECT)
5540 return;
5541
5542 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5543 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5544
5545 temp |= FDI_BC_BIFURCATION_SELECT;
5546 DRM_DEBUG_KMS("enabling fdi C rx\n");
5547 I915_WRITE(SOUTH_CHICKEN1, temp);
5548 POSTING_READ(SOUTH_CHICKEN1);
5549}
5550
ebfd86fd
DV		 5551static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5552{
5553 struct drm_device *dev = intel_crtc->base.dev;
5554 struct drm_i915_private *dev_priv = dev->dev_private;
5555
5556 switch (intel_crtc->pipe) {
5557 case PIPE_A:
5558 break;
5559 case PIPE_B:
5560 if (intel_crtc->config.fdi_lanes > 2)
5561 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5562 else
5563 cpt_enable_fdi_bc_bifurcation(dev);
5564
5565 break;
5566 case PIPE_C:
01a415fd
DV		 5567 cpt_enable_fdi_bc_bifurcation(dev);
5568
ebfd86fd 5569 break;
01a415fd
DV		 5570 default:
5571 BUG();
5572 }
5573}
5574
d4b1931c
PZ		 5575int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5576{
5577 /*
5578 * Account for spread spectrum to avoid
5579 * oversubscribing the link. Max center spread
5580 * is 2.5%; use 5% for safety's sake.
5581 */
5582 u32 bps = target_clock * bpp * 21 / 20;
5583 return bps / (link_bw * 8) + 1;
5584}
5585
7429e9d4
DV		 5586static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5587{
5588 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5589}
5590
de13a2e3 5591static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5592 u32 *fp,
9a7c7890 5593 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5594{
de13a2e3 5595 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5596 struct drm_device *dev = crtc->dev;
5597 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5598 struct intel_encoder *intel_encoder;
5599 uint32_t dpll;
6cc5f341 5600 int factor, num_connectors = 0;
09ede541 5601 bool is_lvds = false, is_sdvo = false;
79e53945 5602
de13a2e3
PZ		 5603 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5604 switch (intel_encoder->type) {
79e53945
JB		 5605 case INTEL_OUTPUT_LVDS:
5606 is_lvds = true;
5607 break;
5608 case INTEL_OUTPUT_SDVO:
7d57382e 5609 case INTEL_OUTPUT_HDMI:
79e53945
JB		 5610 is_sdvo = true;
5611 break;
79e53945 5612 }
43565a06 5613
c751ce4f 5614 num_connectors++;
79e53945 5615 }
79e53945 5616
c1858123 5617 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5618 factor = 21;
5619 if (is_lvds) {
5620 if ((intel_panel_use_ssc(dev_priv) &&
5621 dev_priv->lvds_ssc_freq == 100) ||
f0b44056 5622 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5623 factor = 25;
09ede541 5624 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5625 factor = 20;
c1858123 5626
7429e9d4 5627 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5628 *fp |= FP_CB_TUNE;
2c07245f 5629
9a7c7890
DV		 5630 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5631 *fp2 |= FP_CB_TUNE;
5632
5eddb70b 5633 dpll = 0;
2c07245f 5634
a07d6787
EA		 5635 if (is_lvds)
5636 dpll |= DPLLB_MODE_LVDS;
5637 else
5638 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f
DV		 5639
5640 if (intel_crtc->config.pixel_multiplier > 1) {
5641 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5642 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
a07d6787 5643 }
198a037f
DV		 5644
5645 if (is_sdvo)
5646 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5647 if (intel_crtc->config.has_dp_encoder)
a07d6787 5648 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5649
a07d6787 5650 /* compute bitmask from p1 value */
7429e9d4 5651 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5652 /* also FPA1 */
7429e9d4 5653 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5654
7429e9d4 5655 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5656 case 5:
5657 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5658 break;
5659 case 7:
5660 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5661 break;
5662 case 10:
5663 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5664 break;
5665 case 14:
5666 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5667 break;
79e53945
JB		 5668 }
5669
b4c09f3b 5670 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5671 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5672 else
5673 dpll |= PLL_REF_INPUT_DREFCLK;
5674
de13a2e3
PZ		 5675 return dpll;
5676}
5677
5678static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5679 int x, int y,
5680 struct drm_framebuffer *fb)
5681{
5682 struct drm_device *dev = crtc->dev;
5683 struct drm_i915_private *dev_priv = dev->dev_private;
5684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5685 struct drm_display_mode *adjusted_mode =
5686 &intel_crtc->config.adjusted_mode;
5687 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5688 int pipe = intel_crtc->pipe;
5689 int plane = intel_crtc->plane;
5690 int num_connectors = 0;
5691 intel_clock_t clock, reduced_clock;
cbbab5bd 5692 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5693 bool ok, has_reduced_clock = false;
8b47047b 5694 bool is_lvds = false;
de13a2e3 5695 struct intel_encoder *encoder;
de13a2e3 5696 int ret;
de13a2e3
PZ		 5697
5698 for_each_encoder_on_crtc(dev, crtc, encoder) {
5699 switch (encoder->type) {
5700 case INTEL_OUTPUT_LVDS:
5701 is_lvds = true;
5702 break;
de13a2e3
PZ		 5703 }
5704
5705 num_connectors++;
a07d6787 5706 }
79e53945 5707
5dc5298b
PZ		 5708 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5709 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5710
3b117c8f 5711 intel_crtc->config.cpu_transcoder = pipe;
6cf86a5e 5712
de13a2e3
PZ		 5713 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5714 &has_reduced_clock, &reduced_clock);
5715 if (!ok) {
5716 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5717 return -EINVAL;
79e53945 5718 }
f47709a9
DV		 5719 /* Compat-code for transition, will disappear. */
5720 if (!intel_crtc->config.clock_set) {
5721 intel_crtc->config.dpll.n = clock.n;
5722 intel_crtc->config.dpll.m1 = clock.m1;
5723 intel_crtc->config.dpll.m2 = clock.m2;
5724 intel_crtc->config.dpll.p1 = clock.p1;
5725 intel_crtc->config.dpll.p2 = clock.p2;
5726 }
79e53945 5727
de13a2e3
PZ		 5728 /* Ensure that the cursor is valid for the new mode before changing... */
5729 intel_crtc_update_cursor(crtc, true);
5730
84f44ce7 5731 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 5732 drm_mode_debug_printmodeline(mode);
5733
5dc5298b 5734 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5735 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5736 struct intel_pch_pll *pll;
4b645f14 5737
7429e9d4 5738 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5739 if (has_reduced_clock)
7429e9d4 5740 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5741
7429e9d4 5742 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5743 &fp, &reduced_clock,
5744 has_reduced_clock ? &fp2 : NULL);
5745
ee7b9f93
JB		 5746 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5747 if (pll == NULL) {
84f44ce7
VS		 5748 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5749 pipe_name(pipe));
4b645f14
JB		 5750 return -EINVAL;
5751 }
ee7b9f93
JB		 5752 } else
5753 intel_put_pch_pll(intel_crtc);
79e53945 5754
03afc4a2
DV		 5755 if (intel_crtc->config.has_dp_encoder)
5756 intel_dp_set_m_n(intel_crtc);
79e53945 5757
dafd226c
DV		 5758 for_each_encoder_on_crtc(dev, crtc, encoder)
5759 if (encoder->pre_pll_enable)
5760 encoder->pre_pll_enable(encoder);
79e53945 5761
ee7b9f93
JB		 5762 if (intel_crtc->pch_pll) {
5763 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5764
32f9d658 5765 /* Wait for the clocks to stabilize. */
ee7b9f93 5766 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5767 udelay(150);
5768
8febb297
EA		 5769 /* The pixel multiplier can only be updated once the
5770 * DPLL is enabled and the clocks are stable.
5771 *
5772 * So write it again.
5773 */
ee7b9f93 5774 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5775 }
79e53945 5776
5eddb70b 5777 intel_crtc->lowfreq_avail = false;
ee7b9f93 5778 if (intel_crtc->pch_pll) {
4b645f14 5779 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5780 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5781 intel_crtc->lowfreq_avail = true;
4b645f14 5782 } else {
ee7b9f93 5783 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5784 }
5785 }
5786
b0e77b9c 5787 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5788
ca3a0ff8 5789 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5790 intel_cpu_transcoder_set_m_n(intel_crtc,
5791 &intel_crtc->config.fdi_m_n);
5792 }
2c07245f 5793
ebfd86fd
DV		 5794 if (IS_IVYBRIDGE(dev))
5795 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5796
6ff93609 5797 ironlake_set_pipeconf(crtc);
79e53945 5798
a1f9e77e
PZ		 5799 /* Set up the display plane register */
5800 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5801 POSTING_READ(DSPCNTR(plane));
79e53945 5802
94352cf9 5803 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5804
5805 intel_update_watermarks(dev);
5806
1f8eeabf
ED		 5807 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5808
1857e1da 5809 return ret;
79e53945
JB		 5810}
5811
72419203
DV		 5812static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5813 struct intel_crtc_config *pipe_config)
5814{
5815 struct drm_device *dev = crtc->base.dev;
5816 struct drm_i915_private *dev_priv = dev->dev_private;
5817 enum transcoder transcoder = pipe_config->cpu_transcoder;
5818
5819 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5820 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5821 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5822 & ~TU_SIZE_MASK;
5823 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5824 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5825 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5826}
5827
0e8ffe1b
DV		 5828static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5829 struct intel_crtc_config *pipe_config)
5830{
5831 struct drm_device *dev = crtc->base.dev;
5832 struct drm_i915_private *dev_priv = dev->dev_private;
5833 uint32_t tmp;
5834
5835 tmp = I915_READ(PIPECONF(crtc->pipe));
5836 if (!(tmp & PIPECONF_ENABLE))
5837 return false;
5838
ab9412ba 5839 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5840 pipe_config->has_pch_encoder = true;
5841
627eb5a3
DV		 5842 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5843 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5844 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5845
5846 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5847 }
5848
1bd1bd80
DV		 5849 intel_get_pipe_timings(crtc, pipe_config);
5850
0e8ffe1b
DV		 5851 return true;
5852}
5853
d6dd9eb1
DV		 5854static void haswell_modeset_global_resources(struct drm_device *dev)
5855{
d6dd9eb1
DV		 5856 bool enable = false;
5857 struct intel_crtc *crtc;
5858 struct intel_encoder *encoder;
5859
5860 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5861 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5862 enable = true;
5863 /* XXX: Should check for edp transcoder here, but thanks to init
5864 * sequence that's not yet available. Just in case desktop eDP
5865 * on PORT D is possible on haswell, too. */
b074cec8 5866 /* Even the eDP panel fitter is outside the always-on well. */
2b87f3b1 5867 if (crtc->config.pch_pfit.size && crtc->base.enabled)
b074cec8 5868 enable = true;
d6dd9eb1
DV		 5869 }
5870
5871 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5872 base.head) {
5873 if (encoder->type != INTEL_OUTPUT_EDP &&
5874 encoder->connectors_active)
5875 enable = true;
5876 }
5877
d6dd9eb1
DV		 5878 intel_set_power_well(dev, enable);
5879}
5880
09b4ddf9 5881static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5882 int x, int y,
5883 struct drm_framebuffer *fb)
5884{
5885 struct drm_device *dev = crtc->dev;
5886 struct drm_i915_private *dev_priv = dev->dev_private;
5887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5888 struct drm_display_mode *adjusted_mode =
5889 &intel_crtc->config.adjusted_mode;
5890 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5891 int pipe = intel_crtc->pipe;
5892 int plane = intel_crtc->plane;
5893 int num_connectors = 0;
8b47047b 5894 bool is_cpu_edp = false;
09b4ddf9 5895 struct intel_encoder *encoder;
09b4ddf9 5896 int ret;
09b4ddf9
PZ		 5897
5898 for_each_encoder_on_crtc(dev, crtc, encoder) {
5899 switch (encoder->type) {
09b4ddf9 5900 case INTEL_OUTPUT_EDP:
d8e8b582 5901 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
09b4ddf9
PZ		 5902 is_cpu_edp = true;
5903 break;
5904 }
5905
5906 num_connectors++;
5907 }
5908
bba2181c 5909 if (is_cpu_edp)
3b117c8f 5910 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
bba2181c 5911 else
3b117c8f 5912 intel_crtc->config.cpu_transcoder = pipe;
bba2181c 5913
5dc5298b
PZ		 5914 /* We are not sure yet this won't happen. */
5915 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5916 INTEL_PCH_TYPE(dev));
5917
5918 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5919 num_connectors, pipe_name(pipe));
5920
3b117c8f 5921 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
1ce42920
PZ		 5922 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5923
5924 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5925
6441ab5f
PZ		 5926 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5927 return -EINVAL;
5928
09b4ddf9
PZ		 5929 /* Ensure that the cursor is valid for the new mode before changing... */
5930 intel_crtc_update_cursor(crtc, true);
5931
84f44ce7 5932 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
09b4ddf9
PZ		 5933 drm_mode_debug_printmodeline(mode);
5934
03afc4a2
DV		 5935 if (intel_crtc->config.has_dp_encoder)
5936 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5937
5938 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5939
5940 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5941
ca3a0ff8 5942 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5943 intel_cpu_transcoder_set_m_n(intel_crtc,
5944 &intel_crtc->config.fdi_m_n);
5945 }
09b4ddf9 5946
6ff93609 5947 haswell_set_pipeconf(crtc);
09b4ddf9 5948
50f3b016 5949 intel_set_pipe_csc(crtc);
86d3efce 5950
09b4ddf9 5951 /* Set up the display plane register */
86d3efce 5952 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5953 POSTING_READ(DSPCNTR(plane));
5954
5955 ret = intel_pipe_set_base(crtc, x, y, fb);
5956
5957 intel_update_watermarks(dev);
5958
5959 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5960
1f803ee5 5961 return ret;
79e53945
JB		 5962}
5963
0e8ffe1b
DV		 5964static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5965 struct intel_crtc_config *pipe_config)
5966{
5967 struct drm_device *dev = crtc->base.dev;
5968 struct drm_i915_private *dev_priv = dev->dev_private;
2bfce950 5969 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 5970 uint32_t tmp;
5971
b97186f0
PZ		 5972 if (!intel_display_power_enabled(dev,
5973 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
2bfce950
PZ		 5974 return false;
5975
5976 tmp = I915_READ(PIPECONF(cpu_transcoder));
0e8ffe1b
DV		 5977 if (!(tmp & PIPECONF_ENABLE))
5978 return false;
5979
88adfff1 5980 /*
f196e6be 5981 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5982 * DDI E. So just check whether this pipe is wired to DDI E and whether
5983 * the PCH transcoder is on.
5984 */
f196e6be 5985 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
88adfff1 5986 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5987 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 5988 pipe_config->has_pch_encoder = true;
5989
627eb5a3
DV		 5990 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5991 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5992 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5993
5994 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5995 }
5996
1bd1bd80
DV		 5997 intel_get_pipe_timings(crtc, pipe_config);
5998
0e8ffe1b
DV		 5999 return true;
6000}
6001
f564048e 6002static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6003 int x, int y,
94352cf9 6004 struct drm_framebuffer *fb)
f564048e
EA		 6005{
6006 struct drm_device *dev = crtc->dev;
6007 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6008 struct drm_encoder_helper_funcs *encoder_funcs;
6009 struct intel_encoder *encoder;
0b701d27 6010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6011 struct drm_display_mode *adjusted_mode =
6012 &intel_crtc->config.adjusted_mode;
6013 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6014 int pipe = intel_crtc->pipe;
f564048e
EA		 6015 int ret;
6016
0b701d27 6017 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6018
b8cecdf5
DV		 6019 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6020
79e53945 6021 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6022
9256aa19
DV		 6023 if (ret != 0)
6024 return ret;
6025
6026 for_each_encoder_on_crtc(dev, crtc, encoder) {
6027 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6028 encoder->base.base.id,
6029 drm_get_encoder_name(&encoder->base),
6030 mode->base.id, mode->name);
6cc5f341
DV		 6031 if (encoder->mode_set) {
6032 encoder->mode_set(encoder);
6033 } else {
6034 encoder_funcs = encoder->base.helper_private;
6035 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6036 }
9256aa19
DV		 6037 }
6038
6039 return 0;
79e53945
JB		 6040}
6041
3a9627f4
WF		 6042static bool intel_eld_uptodate(struct drm_connector *connector,
6043 int reg_eldv, uint32_t bits_eldv,
6044 int reg_elda, uint32_t bits_elda,
6045 int reg_edid)
6046{
6047 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6048 uint8_t *eld = connector->eld;
6049 uint32_t i;
6050
6051 i = I915_READ(reg_eldv);
6052 i &= bits_eldv;
6053
6054 if (!eld[0])
6055 return !i;
6056
6057 if (!i)
6058 return false;
6059
6060 i = I915_READ(reg_elda);
6061 i &= ~bits_elda;
6062 I915_WRITE(reg_elda, i);
6063
6064 for (i = 0; i < eld[2]; i++)
6065 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6066 return false;
6067
6068 return true;
6069}
6070
e0dac65e
WF		 6071static void g4x_write_eld(struct drm_connector *connector,
6072 struct drm_crtc *crtc)
6073{
6074 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6075 uint8_t *eld = connector->eld;
6076 uint32_t eldv;
6077 uint32_t len;
6078 uint32_t i;
6079
6080 i = I915_READ(G4X_AUD_VID_DID);
6081
6082 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6083 eldv = G4X_ELDV_DEVCL_DEVBLC;
6084 else
6085 eldv = G4X_ELDV_DEVCTG;
6086
3a9627f4
WF		 6087 if (intel_eld_uptodate(connector,
6088 G4X_AUD_CNTL_ST, eldv,
6089 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6090 G4X_HDMIW_HDMIEDID))
6091 return;
6092
e0dac65e
WF		 6093 i = I915_READ(G4X_AUD_CNTL_ST);
6094 i &= ~(eldv | G4X_ELD_ADDR);
6095 len = (i >> 9) & 0x1f; /* ELD buffer size */
6096 I915_WRITE(G4X_AUD_CNTL_ST, i);
6097
6098 if (!eld[0])
6099 return;
6100
6101 len = min_t(uint8_t, eld[2], len);
6102 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6103 for (i = 0; i < len; i++)
6104 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6105
6106 i = I915_READ(G4X_AUD_CNTL_ST);
6107 i |= eldv;
6108 I915_WRITE(G4X_AUD_CNTL_ST, i);
6109}
6110
83358c85
WX		 6111static void haswell_write_eld(struct drm_connector *connector,
6112 struct drm_crtc *crtc)
6113{
6114 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6115 uint8_t *eld = connector->eld;
6116 struct drm_device *dev = crtc->dev;
7b9f35a6 6117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6118 uint32_t eldv;
6119 uint32_t i;
6120 int len;
6121 int pipe = to_intel_crtc(crtc)->pipe;
6122 int tmp;
6123
6124 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6125 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6126 int aud_config = HSW_AUD_CFG(pipe);
6127 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6128
6129
6130 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6131
6132 /* Audio output enable */
6133 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6134 tmp = I915_READ(aud_cntrl_st2);
6135 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6136 I915_WRITE(aud_cntrl_st2, tmp);
6137
6138 /* Wait for 1 vertical blank */
6139 intel_wait_for_vblank(dev, pipe);
6140
6141 /* Set ELD valid state */
6142 tmp = I915_READ(aud_cntrl_st2);
6143 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6144 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6145 I915_WRITE(aud_cntrl_st2, tmp);
6146 tmp = I915_READ(aud_cntrl_st2);
6147 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6148
6149 /* Enable HDMI mode */
6150 tmp = I915_READ(aud_config);
6151 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6152 /* clear N_programing_enable and N_value_index */
6153 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6154 I915_WRITE(aud_config, tmp);
6155
6156 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6157
6158 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6159 intel_crtc->eld_vld = true;
83358c85
WX		 6160
6161 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6162 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6163 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6164 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6165 } else
6166 I915_WRITE(aud_config, 0);
6167
6168 if (intel_eld_uptodate(connector,
6169 aud_cntrl_st2, eldv,
6170 aud_cntl_st, IBX_ELD_ADDRESS,
6171 hdmiw_hdmiedid))
6172 return;
6173
6174 i = I915_READ(aud_cntrl_st2);
6175 i &= ~eldv;
6176 I915_WRITE(aud_cntrl_st2, i);
6177
6178 if (!eld[0])
6179 return;
6180
6181 i = I915_READ(aud_cntl_st);
6182 i &= ~IBX_ELD_ADDRESS;
6183 I915_WRITE(aud_cntl_st, i);
6184 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6185 DRM_DEBUG_DRIVER("port num:%d\n", i);
6186
6187 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6188 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6189 for (i = 0; i < len; i++)
6190 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6191
6192 i = I915_READ(aud_cntrl_st2);
6193 i |= eldv;
6194 I915_WRITE(aud_cntrl_st2, i);
6195
6196}
6197
e0dac65e
WF		 6198static void ironlake_write_eld(struct drm_connector *connector,
6199 struct drm_crtc *crtc)
6200{
6201 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6202 uint8_t *eld = connector->eld;
6203 uint32_t eldv;
6204 uint32_t i;
6205 int len;
6206 int hdmiw_hdmiedid;
b6daa025 6207 int aud_config;
e0dac65e
WF		 6208 int aud_cntl_st;
6209 int aud_cntrl_st2;
9b138a83 6210 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6211
b3f33cbf 6212 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6213 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6214 aud_config = IBX_AUD_CFG(pipe);
6215 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6216 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6217 } else {
9b138a83
WX		 6218 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6219 aud_config = CPT_AUD_CFG(pipe);
6220 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6221 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6222 }
6223
9b138a83 6224 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6225
6226 i = I915_READ(aud_cntl_st);
9b138a83 6227 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6228 if (!i) {
6229 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6230 /* operate blindly on all ports */
1202b4c6
WF		 6231 eldv = IBX_ELD_VALIDB;
6232 eldv |= IBX_ELD_VALIDB << 4;
6233 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6234 } else {
2582a850 6235 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6236 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6237 }
6238
3a9627f4
WF		 6239 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6240 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6241 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6242 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6243 } else
6244 I915_WRITE(aud_config, 0);
e0dac65e 6245
3a9627f4
WF		 6246 if (intel_eld_uptodate(connector,
6247 aud_cntrl_st2, eldv,
6248 aud_cntl_st, IBX_ELD_ADDRESS,
6249 hdmiw_hdmiedid))
6250 return;
6251
e0dac65e
WF		 6252 i = I915_READ(aud_cntrl_st2);
6253 i &= ~eldv;
6254 I915_WRITE(aud_cntrl_st2, i);
6255
6256 if (!eld[0])
6257 return;
6258
e0dac65e 6259 i = I915_READ(aud_cntl_st);
1202b4c6 6260 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6261 I915_WRITE(aud_cntl_st, i);
6262
6263 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6264 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6265 for (i = 0; i < len; i++)
6266 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6267
6268 i = I915_READ(aud_cntrl_st2);
6269 i |= eldv;
6270 I915_WRITE(aud_cntrl_st2, i);
6271}
6272
6273void intel_write_eld(struct drm_encoder *encoder,
6274 struct drm_display_mode *mode)
6275{
6276 struct drm_crtc *crtc = encoder->crtc;
6277 struct drm_connector *connector;
6278 struct drm_device *dev = encoder->dev;
6279 struct drm_i915_private *dev_priv = dev->dev_private;
6280
6281 connector = drm_select_eld(encoder, mode);
6282 if (!connector)
6283 return;
6284
6285 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6286 connector->base.id,
6287 drm_get_connector_name(connector),
6288 connector->encoder->base.id,
6289 drm_get_encoder_name(connector->encoder));
6290
6291 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6292
6293 if (dev_priv->display.write_eld)
6294 dev_priv->display.write_eld(connector, crtc);
6295}
6296
79e53945
JB		 6297/** Loads the palette/gamma unit for the CRTC with the prepared values */
6298void intel_crtc_load_lut(struct drm_crtc *crtc)
6299{
6300 struct drm_device *dev = crtc->dev;
6301 struct drm_i915_private *dev_priv = dev->dev_private;
6302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6303 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6304 int i;
6305
6306 /* The clocks have to be on to load the palette. */
aed3f09d 6307 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6308 return;
6309
f2b115e6 6310 /* use legacy palette for Ironlake */
bad720ff 6311 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6312 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6313
79e53945
JB		 6314 for (i = 0; i < 256; i++) {
6315 I915_WRITE(palreg + 4 * i,
6316 (intel_crtc->lut_r[i] << 16) |
6317 (intel_crtc->lut_g[i] << 8) |
6318 intel_crtc->lut_b[i]);
6319 }
6320}
6321
560b85bb
CW		 6322static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6323{
6324 struct drm_device *dev = crtc->dev;
6325 struct drm_i915_private *dev_priv = dev->dev_private;
6326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6327 bool visible = base != 0;
6328 u32 cntl;
6329
6330 if (intel_crtc->cursor_visible == visible)
6331 return;
6332
9db4a9c7 6333 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6334 if (visible) {
6335 /* On these chipsets we can only modify the base whilst
6336 * the cursor is disabled.
6337 */
9db4a9c7 6338 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6339
6340 cntl &= ~(CURSOR_FORMAT_MASK);
6341 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6342 cntl |= CURSOR_ENABLE |
6343 CURSOR_GAMMA_ENABLE |
6344 CURSOR_FORMAT_ARGB;
6345 } else
6346 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6347 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6348
6349 intel_crtc->cursor_visible = visible;
6350}
6351
6352static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6353{
6354 struct drm_device *dev = crtc->dev;
6355 struct drm_i915_private *dev_priv = dev->dev_private;
6356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6357 int pipe = intel_crtc->pipe;
6358 bool visible = base != 0;
6359
6360 if (intel_crtc->cursor_visible != visible) {
548f245b 6361 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6362 if (base) {
6363 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6364 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6365 cntl |= pipe << 28; /* Connect to correct pipe */
6366 } else {
6367 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6368 cntl |= CURSOR_MODE_DISABLE;
6369 }
9db4a9c7 6370 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6371
6372 intel_crtc->cursor_visible = visible;
6373 }
6374 /* and commit changes on next vblank */
9db4a9c7 6375 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6376}
6377
65a21cd6
JB		 6378static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6379{
6380 struct drm_device *dev = crtc->dev;
6381 struct drm_i915_private *dev_priv = dev->dev_private;
6382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6383 int pipe = intel_crtc->pipe;
6384 bool visible = base != 0;
6385
6386 if (intel_crtc->cursor_visible != visible) {
6387 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6388 if (base) {
6389 cntl &= ~CURSOR_MODE;
6390 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6391 } else {
6392 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6393 cntl |= CURSOR_MODE_DISABLE;
6394 }
86d3efce
VS		 6395 if (IS_HASWELL(dev))
6396 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6397 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6398
6399 intel_crtc->cursor_visible = visible;
6400 }
6401 /* and commit changes on next vblank */
6402 I915_WRITE(CURBASE_IVB(pipe), base);
6403}
6404
cda4b7d3 6405/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6406static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6407 bool on)
cda4b7d3
CW		 6408{
6409 struct drm_device *dev = crtc->dev;
6410 struct drm_i915_private *dev_priv = dev->dev_private;
6411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6412 int pipe = intel_crtc->pipe;
6413 int x = intel_crtc->cursor_x;
6414 int y = intel_crtc->cursor_y;
560b85bb 6415 u32 base, pos;
cda4b7d3
CW		 6416 bool visible;
6417
6418 pos = 0;
6419
6b383a7f 6420 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6421 base = intel_crtc->cursor_addr;
6422 if (x > (int) crtc->fb->width)
6423 base = 0;
6424
6425 if (y > (int) crtc->fb->height)
6426 base = 0;
6427 } else
6428 base = 0;
6429
6430 if (x < 0) {
6431 if (x + intel_crtc->cursor_width < 0)
6432 base = 0;
6433
6434 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6435 x = -x;
6436 }
6437 pos |= x << CURSOR_X_SHIFT;
6438
6439 if (y < 0) {
6440 if (y + intel_crtc->cursor_height < 0)
6441 base = 0;
6442
6443 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6444 y = -y;
6445 }
6446 pos |= y << CURSOR_Y_SHIFT;
6447
6448 visible = base != 0;
560b85bb 6449 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6450 return;
6451
0cd83aa9 6452 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6453 I915_WRITE(CURPOS_IVB(pipe), pos);
6454 ivb_update_cursor(crtc, base);
6455 } else {
6456 I915_WRITE(CURPOS(pipe), pos);
6457 if (IS_845G(dev) || IS_I865G(dev))
6458 i845_update_cursor(crtc, base);
6459 else
6460 i9xx_update_cursor(crtc, base);
6461 }
cda4b7d3
CW		 6462}
6463
79e53945 6464static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6465 struct drm_file *file,
79e53945
JB		 6466 uint32_t handle,
6467 uint32_t width, uint32_t height)
6468{
6469 struct drm_device *dev = crtc->dev;
6470 struct drm_i915_private *dev_priv = dev->dev_private;
6471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6472 struct drm_i915_gem_object *obj;
cda4b7d3 6473 uint32_t addr;
3f8bc370 6474 int ret;
79e53945 6475
79e53945
JB		 6476 /* if we want to turn off the cursor ignore width and height */
6477 if (!handle) {
28c97730 6478 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6479 addr = 0;
05394f39 6480 obj = NULL;
5004417d 6481 mutex_lock(&dev->struct_mutex);
3f8bc370 6482 goto finish;
79e53945
JB		 6483 }
6484
6485 /* Currently we only support 64x64 cursors */
6486 if (width != 64 || height != 64) {
6487 DRM_ERROR("we currently only support 64x64 cursors\n");
6488 return -EINVAL;
6489 }
6490
05394f39 6491 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6492 if (&obj->base == NULL)
79e53945
JB		 6493 return -ENOENT;
6494
05394f39 6495 if (obj->base.size < width * height * 4) {
79e53945 6496 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6497 ret = -ENOMEM;
6498 goto fail;
79e53945
JB		 6499 }
6500
71acb5eb 6501 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6502 mutex_lock(&dev->struct_mutex);
b295d1b6 6503 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6504 unsigned alignment;
6505
d9e86c0e
CW		 6506 if (obj->tiling_mode) {
6507 DRM_ERROR("cursor cannot be tiled\n");
6508 ret = -EINVAL;
6509 goto fail_locked;
6510 }
6511
693db184
CW		 6512 /* Note that the w/a also requires 2 PTE of padding following
6513 * the bo. We currently fill all unused PTE with the shadow
6514 * page and so we should always have valid PTE following the
6515 * cursor preventing the VT-d warning.
6516 */
6517 alignment = 0;
6518 if (need_vtd_wa(dev))
6519 alignment = 64*1024;
6520
6521 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6522 if (ret) {
6523 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6524 goto fail_locked;
e7b526bb
CW		 6525 }
6526
d9e86c0e
CW		 6527 ret = i915_gem_object_put_fence(obj);
6528 if (ret) {
2da3b9b9 6529 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6530 goto fail_unpin;
6531 }
6532
05394f39 6533 addr = obj->gtt_offset;
71acb5eb 6534 } else {
6eeefaf3 6535 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6536 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6537 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6538 align);
71acb5eb
DA		 6539 if (ret) {
6540 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6541 goto fail_locked;
71acb5eb 6542 }
05394f39 6543 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6544 }
6545
a6c45cf0 6546 if (IS_GEN2(dev))
14b60391
JB		 6547 I915_WRITE(CURSIZE, (height << 12) | width);
6548
3f8bc370 6549 finish:
3f8bc370 6550 if (intel_crtc->cursor_bo) {
b295d1b6 6551 if (dev_priv->info->cursor_needs_physical) {
05394f39 6552 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6553 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6554 } else
6555 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6556 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6557 }
80824003 6558
7f9872e0 6559 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6560
6561 intel_crtc->cursor_addr = addr;
05394f39 6562 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6563 intel_crtc->cursor_width = width;
6564 intel_crtc->cursor_height = height;
6565
6b383a7f 6566 intel_crtc_update_cursor(crtc, true);
3f8bc370 6567
79e53945 6568 return 0;
e7b526bb 6569fail_unpin:
05394f39 6570 i915_gem_object_unpin(obj);
7f9872e0 6571fail_locked:
34b8686e 6572 mutex_unlock(&dev->struct_mutex);
bc9025bd 6573fail:
05394f39 6574 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6575 return ret;
79e53945
JB		 6576}
6577
6578static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6579{
79e53945 6580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6581
cda4b7d3
CW		 6582 intel_crtc->cursor_x = x;
6583 intel_crtc->cursor_y = y;
652c393a 6584
6b383a7f 6585 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6586
6587 return 0;
6588}
6589
6590/** Sets the color ramps on behalf of RandR */
6591void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6592 u16 blue, int regno)
6593{
6594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6595
6596 intel_crtc->lut_r[regno] = red >> 8;
6597 intel_crtc->lut_g[regno] = green >> 8;
6598 intel_crtc->lut_b[regno] = blue >> 8;
6599}
6600
b8c00ac5
DA		 6601void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6602 u16 *blue, int regno)
6603{
6604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6605
6606 *red = intel_crtc->lut_r[regno] << 8;
6607 *green = intel_crtc->lut_g[regno] << 8;
6608 *blue = intel_crtc->lut_b[regno] << 8;
6609}
6610
79e53945 6611static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6612 u16 *blue, uint32_t start, uint32_t size)
79e53945 6613{
7203425a 6614 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6616
7203425a 6617 for (i = start; i < end; i++) {
79e53945
JB		 6618 intel_crtc->lut_r[i] = red[i] >> 8;
6619 intel_crtc->lut_g[i] = green[i] >> 8;
6620 intel_crtc->lut_b[i] = blue[i] >> 8;
6621 }
6622
6623 intel_crtc_load_lut(crtc);
6624}
6625
79e53945
JB		 6626/* VESA 640x480x72Hz mode to set on the pipe */
6627static struct drm_display_mode load_detect_mode = {
6628 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6629 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6630};
6631
d2dff872
CW		 6632static struct drm_framebuffer *
6633intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6634 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6635 struct drm_i915_gem_object *obj)
6636{
6637 struct intel_framebuffer *intel_fb;
6638 int ret;
6639
6640 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6641 if (!intel_fb) {
6642 drm_gem_object_unreference_unlocked(&obj->base);
6643 return ERR_PTR(-ENOMEM);
6644 }
6645
6646 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6647 if (ret) {
6648 drm_gem_object_unreference_unlocked(&obj->base);
6649 kfree(intel_fb);
6650 return ERR_PTR(ret);
6651 }
6652
6653 return &intel_fb->base;
6654}
6655
6656static u32
6657intel_framebuffer_pitch_for_width(int width, int bpp)
6658{
6659 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6660 return ALIGN(pitch, 64);
6661}
6662
6663static u32
6664intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6665{
6666 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6667 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6668}
6669
6670static struct drm_framebuffer *
6671intel_framebuffer_create_for_mode(struct drm_device *dev,
6672 struct drm_display_mode *mode,
6673 int depth, int bpp)
6674{
6675 struct drm_i915_gem_object *obj;
0fed39bd 6676 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6677
6678 obj = i915_gem_alloc_object(dev,
6679 intel_framebuffer_size_for_mode(mode, bpp));
6680 if (obj == NULL)
6681 return ERR_PTR(-ENOMEM);
6682
6683 mode_cmd.width = mode->hdisplay;
6684 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6685 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6686 bpp);
5ca0c34a 6687 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6688
6689 return intel_framebuffer_create(dev, &mode_cmd, obj);
6690}
6691
6692static struct drm_framebuffer *
6693mode_fits_in_fbdev(struct drm_device *dev,
6694 struct drm_display_mode *mode)
6695{
6696 struct drm_i915_private *dev_priv = dev->dev_private;
6697 struct drm_i915_gem_object *obj;
6698 struct drm_framebuffer *fb;
6699
6700 if (dev_priv->fbdev == NULL)
6701 return NULL;
6702
6703 obj = dev_priv->fbdev->ifb.obj;
6704 if (obj == NULL)
6705 return NULL;
6706
6707 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6708 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6709 fb->bits_per_pixel))
d2dff872
CW		 6710 return NULL;
6711
01f2c773 6712 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6713 return NULL;
6714
6715 return fb;
6716}
6717
d2434ab7 6718bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6719 struct drm_display_mode *mode,
8261b191 6720 struct intel_load_detect_pipe *old)
79e53945
JB		 6721{
6722 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6723 struct intel_encoder *intel_encoder =
6724 intel_attached_encoder(connector);
79e53945 6725 struct drm_crtc *possible_crtc;
4ef69c7a 6726 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6727 struct drm_crtc *crtc = NULL;
6728 struct drm_device *dev = encoder->dev;
94352cf9 6729 struct drm_framebuffer *fb;
79e53945
JB		 6730 int i = -1;
6731
d2dff872
CW		 6732 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6733 connector->base.id, drm_get_connector_name(connector),
6734 encoder->base.id, drm_get_encoder_name(encoder));
6735
79e53945
JB		 6736 /*
6737 * Algorithm gets a little messy:
7a5e4805 6738 *
79e53945
JB		 6739 * - if the connector already has an assigned crtc, use it (but make
6740 * sure it's on first)
7a5e4805 6741 *
79e53945
JB		 6742 * - try to find the first unused crtc that can drive this connector,
6743 * and use that if we find one
79e53945
JB		 6744 */
6745
6746 /* See if we already have a CRTC for this connector */
6747 if (encoder->crtc) {
6748 crtc = encoder->crtc;
8261b191 6749
7b24056b
DV		 6750 mutex_lock(&crtc->mutex);
6751
24218aac 6752 old->dpms_mode = connector->dpms;
8261b191
CW		 6753 old->load_detect_temp = false;
6754
6755 /* Make sure the crtc and connector are running */
24218aac
DV		 6756 if (connector->dpms != DRM_MODE_DPMS_ON)
6757 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6758
7173188d 6759 return true;
79e53945
JB		 6760 }
6761
6762 /* Find an unused one (if possible) */
6763 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6764 i++;
6765 if (!(encoder->possible_crtcs & (1 << i)))
6766 continue;
6767 if (!possible_crtc->enabled) {
6768 crtc = possible_crtc;
6769 break;
6770 }
79e53945
JB		 6771 }
6772
6773 /*
6774 * If we didn't find an unused CRTC, don't use any.
6775 */
6776 if (!crtc) {
7173188d
CW		 6777 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6778 return false;
79e53945
JB		 6779 }
6780
7b24056b 6781 mutex_lock(&crtc->mutex);
fc303101
DV		 6782 intel_encoder->new_crtc = to_intel_crtc(crtc);
6783 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6784
6785 intel_crtc = to_intel_crtc(crtc);
24218aac 6786 old->dpms_mode = connector->dpms;
8261b191 6787 old->load_detect_temp = true;
d2dff872 6788 old->release_fb = NULL;
79e53945 6789
6492711d
CW		 6790 if (!mode)
6791 mode = &load_detect_mode;
79e53945 6792
d2dff872
CW		 6793 /* We need a framebuffer large enough to accommodate all accesses
6794 * that the plane may generate whilst we perform load detection.
6795 * We can not rely on the fbcon either being present (we get called
6796 * during its initialisation to detect all boot displays, or it may
6797 * not even exist) or that it is large enough to satisfy the
6798 * requested mode.
6799 */
94352cf9
DV		 6800 fb = mode_fits_in_fbdev(dev, mode);
6801 if (fb == NULL) {
d2dff872 6802 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6803 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6804 old->release_fb = fb;
d2dff872
CW		 6805 } else
6806 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6807 if (IS_ERR(fb)) {
d2dff872 6808 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6809 mutex_unlock(&crtc->mutex);
0e8b3d3e 6810 return false;
79e53945 6811 }
79e53945 6812
c0c36b94 6813 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6814 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6815 if (old->release_fb)
6816 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6817 mutex_unlock(&crtc->mutex);
0e8b3d3e 6818 return false;
79e53945 6819 }
7173188d 6820
79e53945 6821 /* let the connector get through one full cycle before testing */
9d0498a2 6822 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6823 return true;
79e53945
JB		 6824}
6825
d2434ab7 6826void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6827 struct intel_load_detect_pipe *old)
79e53945 6828{
d2434ab7
DV		 6829 struct intel_encoder *intel_encoder =
6830 intel_attached_encoder(connector);
4ef69c7a 6831 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6832 struct drm_crtc *crtc = encoder->crtc;
79e53945 6833
d2dff872
CW		 6834 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6835 connector->base.id, drm_get_connector_name(connector),
6836 encoder->base.id, drm_get_encoder_name(encoder));
6837
8261b191 6838 if (old->load_detect_temp) {
fc303101
DV		 6839 to_intel_connector(connector)->new_encoder = NULL;
6840 intel_encoder->new_crtc = NULL;
6841 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6842
36206361
DV		 6843 if (old->release_fb) {
6844 drm_framebuffer_unregister_private(old->release_fb);
6845 drm_framebuffer_unreference(old->release_fb);
6846 }
d2dff872 6847
67c96400 6848 mutex_unlock(&crtc->mutex);
0622a53c 6849 return;
79e53945
JB		 6850 }
6851
c751ce4f 6852 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6853 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6854 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6855
6856 mutex_unlock(&crtc->mutex);
79e53945
JB		 6857}
6858
6859/* Returns the clock of the currently programmed mode of the given pipe. */
6860static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6861{
6862 struct drm_i915_private *dev_priv = dev->dev_private;
6863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6864 int pipe = intel_crtc->pipe;
548f245b 6865 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6866 u32 fp;
6867 intel_clock_t clock;
6868
6869 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6870 fp = I915_READ(FP0(pipe));
79e53945 6871 else
39adb7a5 6872 fp = I915_READ(FP1(pipe));
79e53945
JB		 6873
6874 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6875 if (IS_PINEVIEW(dev)) {
6876 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6877 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6878 } else {
6879 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6880 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6881 }
6882
a6c45cf0 6883 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6884 if (IS_PINEVIEW(dev))
6885 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6886 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6887 else
6888 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6889 DPLL_FPA01_P1_POST_DIV_SHIFT);
6890
6891 switch (dpll & DPLL_MODE_MASK) {
6892 case DPLLB_MODE_DAC_SERIAL:
6893 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6894 5 : 10;
6895 break;
6896 case DPLLB_MODE_LVDS:
6897 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6898 7 : 14;
6899 break;
6900 default:
28c97730 6901 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6902 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6903 return 0;
6904 }
6905
6906 /* XXX: Handle the 100Mhz refclk */
2177832f 6907 intel_clock(dev, 96000, &clock);
79e53945
JB		 6908 } else {
6909 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6910
6911 if (is_lvds) {
6912 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6913 DPLL_FPA01_P1_POST_DIV_SHIFT);
6914 clock.p2 = 14;
6915
6916 if ((dpll & PLL_REF_INPUT_MASK) ==
6917 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6918 /* XXX: might not be 66MHz */
2177832f 6919 intel_clock(dev, 66000, &clock);
79e53945 6920 } else
2177832f 6921 intel_clock(dev, 48000, &clock);
79e53945
JB		 6922 } else {
6923 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6924 clock.p1 = 2;
6925 else {
6926 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6927 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6928 }
6929 if (dpll & PLL_P2_DIVIDE_BY_4)
6930 clock.p2 = 4;
6931 else
6932 clock.p2 = 2;
6933
2177832f 6934 intel_clock(dev, 48000, &clock);
79e53945
JB		 6935 }
6936 }
6937
6938 /* XXX: It would be nice to validate the clocks, but we can't reuse
6939 * i830PllIsValid() because it relies on the xf86_config connector
6940 * configuration being accurate, which it isn't necessarily.
6941 */
6942
6943 return clock.dot;
6944}
6945
6946/** Returns the currently programmed mode of the given pipe. */
6947struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6948 struct drm_crtc *crtc)
6949{
548f245b 6950 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6952 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6953 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6954 int htot = I915_READ(HTOTAL(cpu_transcoder));
6955 int hsync = I915_READ(HSYNC(cpu_transcoder));
6956 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6957 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6958
6959 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6960 if (!mode)
6961 return NULL;
6962
6963 mode->clock = intel_crtc_clock_get(dev, crtc);
6964 mode->hdisplay = (htot & 0xffff) + 1;
6965 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6966 mode->hsync_start = (hsync & 0xffff) + 1;
6967 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6968 mode->vdisplay = (vtot & 0xffff) + 1;
6969 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6970 mode->vsync_start = (vsync & 0xffff) + 1;
6971 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6972
6973 drm_mode_set_name(mode);
79e53945
JB		 6974
6975 return mode;
6976}
6977
3dec0095 6978static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6979{
6980 struct drm_device *dev = crtc->dev;
6981 drm_i915_private_t *dev_priv = dev->dev_private;
6982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6983 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6984 int dpll_reg = DPLL(pipe);
6985 int dpll;
652c393a 6986
bad720ff 6987 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6988 return;
6989
6990 if (!dev_priv->lvds_downclock_avail)
6991 return;
6992
dbdc6479 6993 dpll = I915_READ(dpll_reg);
652c393a 6994 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6995 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6996
8ac5a6d5 6997 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6998
6999 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7000 I915_WRITE(dpll_reg, dpll);
9d0498a2 7001 intel_wait_for_vblank(dev, pipe);
dbdc6479 7002
652c393a
JB		 7003 dpll = I915_READ(dpll_reg);
7004 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7005 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7006 }
652c393a
JB		 7007}
7008
7009static void intel_decrease_pllclock(struct drm_crtc *crtc)
7010{
7011 struct drm_device *dev = crtc->dev;
7012 drm_i915_private_t *dev_priv = dev->dev_private;
7013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7014
bad720ff 7015 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7016 return;
7017
7018 if (!dev_priv->lvds_downclock_avail)
7019 return;
7020
7021 /*
7022 * Since this is called by a timer, we should never get here in
7023 * the manual case.
7024 */
7025 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7026 int pipe = intel_crtc->pipe;
7027 int dpll_reg = DPLL(pipe);
7028 int dpll;
f6e5b160 7029
44d98a61 7030 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7031
8ac5a6d5 7032 assert_panel_unlocked(dev_priv, pipe);
652c393a 7033
dc257cf1 7034 dpll = I915_READ(dpll_reg);
652c393a
JB		 7035 dpll |= DISPLAY_RATE_SELECT_FPA1;
7036 I915_WRITE(dpll_reg, dpll);
9d0498a2 7037 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7038 dpll = I915_READ(dpll_reg);
7039 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7040 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7041 }
7042
7043}
7044
f047e395
CW		 7045void intel_mark_busy(struct drm_device *dev)
7046{
f047e395
CW		 7047 i915_update_gfx_val(dev->dev_private);
7048}
7049
7050void intel_mark_idle(struct drm_device *dev)
652c393a 7051{
652c393a 7052 struct drm_crtc *crtc;
652c393a
JB		 7053
7054 if (!i915_powersave)
7055 return;
7056
652c393a 7057 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7058 if (!crtc->fb)
7059 continue;
7060
725a5b54 7061 intel_decrease_pllclock(crtc);
652c393a 7062 }
652c393a
JB		 7063}
7064
725a5b54 7065void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 7066{
f047e395
CW		 7067 struct drm_device *dev = obj->base.dev;
7068 struct drm_crtc *crtc;
652c393a 7069
f047e395 7070 if (!i915_powersave)
acb87dfb
CW		 7071 return;
7072
652c393a
JB		 7073 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7074 if (!crtc->fb)
7075 continue;
7076
f047e395 7077 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7078 intel_increase_pllclock(crtc);
652c393a
JB		 7079 }
7080}
7081
79e53945
JB		 7082static void intel_crtc_destroy(struct drm_crtc *crtc)
7083{
7084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7085 struct drm_device *dev = crtc->dev;
7086 struct intel_unpin_work *work;
7087 unsigned long flags;
7088
7089 spin_lock_irqsave(&dev->event_lock, flags);
7090 work = intel_crtc->unpin_work;
7091 intel_crtc->unpin_work = NULL;
7092 spin_unlock_irqrestore(&dev->event_lock, flags);
7093
7094 if (work) {
7095 cancel_work_sync(&work->work);
7096 kfree(work);
7097 }
79e53945
JB		 7098
7099 drm_crtc_cleanup(crtc);
67e77c5a 7100
79e53945
JB		 7101 kfree(intel_crtc);
7102}
7103
6b95a207
KH		 7104static void intel_unpin_work_fn(struct work_struct *__work)
7105{
7106 struct intel_unpin_work *work =
7107 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7108 struct drm_device *dev = work->crtc->dev;
6b95a207 7109
b4a98e57 7110 mutex_lock(&dev->struct_mutex);
1690e1eb 7111 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7112 drm_gem_object_unreference(&work->pending_flip_obj->base);
7113 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7114
b4a98e57
CW		 7115 intel_update_fbc(dev);
7116 mutex_unlock(&dev->struct_mutex);
7117
7118 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7119 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7120
6b95a207
KH		 7121 kfree(work);
7122}
7123
1afe3e9d 7124static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7125 struct drm_crtc *crtc)
6b95a207
KH		 7126{
7127 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7129 struct intel_unpin_work *work;
6b95a207
KH		 7130 unsigned long flags;
7131
7132 /* Ignore early vblank irqs */
7133 if (intel_crtc == NULL)
7134 return;
7135
7136 spin_lock_irqsave(&dev->event_lock, flags);
7137 work = intel_crtc->unpin_work;
e7d841ca
CW		 7138
7139 /* Ensure we don't miss a work->pending update ... */
7140 smp_rmb();
7141
7142 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7143 spin_unlock_irqrestore(&dev->event_lock, flags);
7144 return;
7145 }
7146
e7d841ca
CW		 7147 /* and that the unpin work is consistent wrt ->pending. */
7148 smp_rmb();
7149
6b95a207 7150 intel_crtc->unpin_work = NULL;
6b95a207 7151
45a066eb
RC		 7152 if (work->event)
7153 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7154
0af7e4df
MK		 7155 drm_vblank_put(dev, intel_crtc->pipe);
7156
6b95a207
KH		 7157 spin_unlock_irqrestore(&dev->event_lock, flags);
7158
2c10d571 7159 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7160
7161 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7162
7163 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7164}
7165
1afe3e9d
JB		 7166void intel_finish_page_flip(struct drm_device *dev, int pipe)
7167{
7168 drm_i915_private_t *dev_priv = dev->dev_private;
7169 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7170
49b14a5c 7171 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7172}
7173
7174void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7175{
7176 drm_i915_private_t *dev_priv = dev->dev_private;
7177 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7178
49b14a5c 7179 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7180}
7181
6b95a207
KH		 7182void intel_prepare_page_flip(struct drm_device *dev, int plane)
7183{
7184 drm_i915_private_t *dev_priv = dev->dev_private;
7185 struct intel_crtc *intel_crtc =
7186 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7187 unsigned long flags;
7188
e7d841ca
CW		 7189 /* NB: An MMIO update of the plane base pointer will also
7190 * generate a page-flip completion irq, i.e. every modeset
7191 * is also accompanied by a spurious intel_prepare_page_flip().
7192 */
6b95a207 7193 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7194 if (intel_crtc->unpin_work)
7195 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7196 spin_unlock_irqrestore(&dev->event_lock, flags);
7197}
7198
e7d841ca
CW		 7199inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7200{
7201 /* Ensure that the work item is consistent when activating it ... */
7202 smp_wmb();
7203 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7204 /* and that it is marked active as soon as the irq could fire. */
7205 smp_wmb();
7206}
7207
8c9f3aaf
JB		 7208static int intel_gen2_queue_flip(struct drm_device *dev,
7209 struct drm_crtc *crtc,
7210 struct drm_framebuffer *fb,
7211 struct drm_i915_gem_object *obj)
7212{
7213 struct drm_i915_private *dev_priv = dev->dev_private;
7214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7215 u32 flip_mask;
6d90c952 7216 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7217 int ret;
7218
6d90c952 7219 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7220 if (ret)
83d4092b 7221 goto err;
8c9f3aaf 7222
6d90c952 7223 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7224 if (ret)
83d4092b 7225 goto err_unpin;
8c9f3aaf
JB		 7226
7227 /* Can't queue multiple flips, so wait for the previous
7228 * one to finish before executing the next.
7229 */
7230 if (intel_crtc->plane)
7231 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7232 else
7233 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7234 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7235 intel_ring_emit(ring, MI_NOOP);
7236 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7237 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7238 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7239 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7240 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7241
7242 intel_mark_page_flip_active(intel_crtc);
6d90c952 7243 intel_ring_advance(ring);
83d4092b
CW		 7244 return 0;
7245
7246err_unpin:
7247 intel_unpin_fb_obj(obj);
7248err:
8c9f3aaf
JB		 7249 return ret;
7250}
7251
7252static int intel_gen3_queue_flip(struct drm_device *dev,
7253 struct drm_crtc *crtc,
7254 struct drm_framebuffer *fb,
7255 struct drm_i915_gem_object *obj)
7256{
7257 struct drm_i915_private *dev_priv = dev->dev_private;
7258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7259 u32 flip_mask;
6d90c952 7260 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7261 int ret;
7262
6d90c952 7263 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7264 if (ret)
83d4092b 7265 goto err;
8c9f3aaf 7266
6d90c952 7267 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7268 if (ret)
83d4092b 7269 goto err_unpin;
8c9f3aaf
JB		 7270
7271 if (intel_crtc->plane)
7272 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7273 else
7274 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7275 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7276 intel_ring_emit(ring, MI_NOOP);
7277 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7278 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7279 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7280 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7281 intel_ring_emit(ring, MI_NOOP);
7282
e7d841ca 7283 intel_mark_page_flip_active(intel_crtc);
6d90c952 7284 intel_ring_advance(ring);
83d4092b
CW		 7285 return 0;
7286
7287err_unpin:
7288 intel_unpin_fb_obj(obj);
7289err:
8c9f3aaf
JB		 7290 return ret;
7291}
7292
7293static int intel_gen4_queue_flip(struct drm_device *dev,
7294 struct drm_crtc *crtc,
7295 struct drm_framebuffer *fb,
7296 struct drm_i915_gem_object *obj)
7297{
7298 struct drm_i915_private *dev_priv = dev->dev_private;
7299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7300 uint32_t pf, pipesrc;
6d90c952 7301 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7302 int ret;
7303
6d90c952 7304 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7305 if (ret)
83d4092b 7306 goto err;
8c9f3aaf 7307
6d90c952 7308 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7309 if (ret)
83d4092b 7310 goto err_unpin;
8c9f3aaf
JB		 7311
7312 /* i965+ uses the linear or tiled offsets from the
7313 * Display Registers (which do not change across a page-flip)
7314 * so we need only reprogram the base address.
7315 */
6d90c952
DV		 7316 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7317 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7318 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7319 intel_ring_emit(ring,
7320 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7321 obj->tiling_mode);
8c9f3aaf
JB		 7322
7323 /* XXX Enabling the panel-fitter across page-flip is so far
7324 * untested on non-native modes, so ignore it for now.
7325 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7326 */
7327 pf = 0;
7328 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7329 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7330
7331 intel_mark_page_flip_active(intel_crtc);
6d90c952 7332 intel_ring_advance(ring);
83d4092b
CW		 7333 return 0;
7334
7335err_unpin:
7336 intel_unpin_fb_obj(obj);
7337err:
8c9f3aaf
JB		 7338 return ret;
7339}
7340
7341static int intel_gen6_queue_flip(struct drm_device *dev,
7342 struct drm_crtc *crtc,
7343 struct drm_framebuffer *fb,
7344 struct drm_i915_gem_object *obj)
7345{
7346 struct drm_i915_private *dev_priv = dev->dev_private;
7347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7348 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7349 uint32_t pf, pipesrc;
7350 int ret;
7351
6d90c952 7352 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7353 if (ret)
83d4092b 7354 goto err;
8c9f3aaf 7355
6d90c952 7356 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7357 if (ret)
83d4092b 7358 goto err_unpin;
8c9f3aaf 7359
6d90c952
DV		 7360 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7361 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7362 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7363 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7364
dc257cf1
DV		 7365 /* Contrary to the suggestions in the documentation,
7366 * "Enable Panel Fitter" does not seem to be required when page
7367 * flipping with a non-native mode, and worse causes a normal
7368 * modeset to fail.
7369 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7370 */
7371 pf = 0;
8c9f3aaf 7372 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7373 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7374
7375 intel_mark_page_flip_active(intel_crtc);
6d90c952 7376 intel_ring_advance(ring);
83d4092b
CW		 7377 return 0;
7378
7379err_unpin:
7380 intel_unpin_fb_obj(obj);
7381err:
8c9f3aaf
JB		 7382 return ret;
7383}
7384
7c9017e5
JB		 7385/*
7386 * On gen7 we currently use the blit ring because (in early silicon at least)
7387 * the render ring doesn't give us interrpts for page flip completion, which
7388 * means clients will hang after the first flip is queued. Fortunately the
7389 * blit ring generates interrupts properly, so use it instead.
7390 */
7391static int intel_gen7_queue_flip(struct drm_device *dev,
7392 struct drm_crtc *crtc,
7393 struct drm_framebuffer *fb,
7394 struct drm_i915_gem_object *obj)
7395{
7396 struct drm_i915_private *dev_priv = dev->dev_private;
7397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7398 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7399 uint32_t plane_bit = 0;
7c9017e5
JB		 7400 int ret;
7401
7402 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7403 if (ret)
83d4092b 7404 goto err;
7c9017e5 7405
cb05d8de
DV		 7406 switch(intel_crtc->plane) {
7407 case PLANE_A:
7408 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7409 break;
7410 case PLANE_B:
7411 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7412 break;
7413 case PLANE_C:
7414 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7415 break;
7416 default:
7417 WARN_ONCE(1, "unknown plane in flip command\n");
7418 ret = -ENODEV;
ab3951eb 7419 goto err_unpin;
cb05d8de
DV		 7420 }
7421
7c9017e5
JB		 7422 ret = intel_ring_begin(ring, 4);
7423 if (ret)
83d4092b 7424 goto err_unpin;
7c9017e5 7425
cb05d8de 7426 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7427 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7428 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7429 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7430
7431 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7432 intel_ring_advance(ring);
83d4092b
CW		 7433 return 0;
7434
7435err_unpin:
7436 intel_unpin_fb_obj(obj);
7437err:
7c9017e5
JB		 7438 return ret;
7439}
7440
8c9f3aaf
JB		 7441static int intel_default_queue_flip(struct drm_device *dev,
7442 struct drm_crtc *crtc,
7443 struct drm_framebuffer *fb,
7444 struct drm_i915_gem_object *obj)
7445{
7446 return -ENODEV;
7447}
7448
6b95a207
KH		 7449static int intel_crtc_page_flip(struct drm_crtc *crtc,
7450 struct drm_framebuffer *fb,
7451 struct drm_pending_vblank_event *event)
7452{
7453 struct drm_device *dev = crtc->dev;
7454 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7455 struct drm_framebuffer *old_fb = crtc->fb;
7456 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7458 struct intel_unpin_work *work;
8c9f3aaf 7459 unsigned long flags;
52e68630 7460 int ret;
6b95a207 7461
e6a595d2
VS		 7462 /* Can't change pixel format via MI display flips. */
7463 if (fb->pixel_format != crtc->fb->pixel_format)
7464 return -EINVAL;
7465
7466 /*
7467 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7468 * Note that pitch changes could also affect these register.
7469 */
7470 if (INTEL_INFO(dev)->gen > 3 &&
7471 (fb->offsets[0] != crtc->fb->offsets[0] ||
7472 fb->pitches[0] != crtc->fb->pitches[0]))
7473 return -EINVAL;
7474
6b95a207
KH		 7475 work = kzalloc(sizeof *work, GFP_KERNEL);
7476 if (work == NULL)
7477 return -ENOMEM;
7478
6b95a207 7479 work->event = event;
b4a98e57 7480 work->crtc = crtc;
4a35f83b 7481 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7482 INIT_WORK(&work->work, intel_unpin_work_fn);
7483
7317c75e
JB		 7484 ret = drm_vblank_get(dev, intel_crtc->pipe);
7485 if (ret)
7486 goto free_work;
7487
6b95a207
KH		 7488 /* We borrow the event spin lock for protecting unpin_work */
7489 spin_lock_irqsave(&dev->event_lock, flags);
7490 if (intel_crtc->unpin_work) {
7491 spin_unlock_irqrestore(&dev->event_lock, flags);
7492 kfree(work);
7317c75e 7493 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7494
7495 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7496 return -EBUSY;
7497 }
7498 intel_crtc->unpin_work = work;
7499 spin_unlock_irqrestore(&dev->event_lock, flags);
7500
b4a98e57
CW		 7501 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7502 flush_workqueue(dev_priv->wq);
7503
79158103
CW		 7504 ret = i915_mutex_lock_interruptible(dev);
7505 if (ret)
7506 goto cleanup;
6b95a207 7507
75dfca80 7508 /* Reference the objects for the scheduled work. */
05394f39
CW		 7509 drm_gem_object_reference(&work->old_fb_obj->base);
7510 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7511
7512 crtc->fb = fb;
96b099fd 7513
e1f99ce6 7514 work->pending_flip_obj = obj;
e1f99ce6 7515
4e5359cd
SF		 7516 work->enable_stall_check = true;
7517
b4a98e57 7518 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7519 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7520
8c9f3aaf
JB		 7521 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7522 if (ret)
7523 goto cleanup_pending;
6b95a207 7524
7782de3b 7525 intel_disable_fbc(dev);
f047e395 7526 intel_mark_fb_busy(obj);
6b95a207
KH		 7527 mutex_unlock(&dev->struct_mutex);
7528
e5510fac
JB		 7529 trace_i915_flip_request(intel_crtc->plane, obj);
7530
6b95a207 7531 return 0;
96b099fd 7532
8c9f3aaf 7533cleanup_pending:
b4a98e57 7534 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7535 crtc->fb = old_fb;
05394f39
CW		 7536 drm_gem_object_unreference(&work->old_fb_obj->base);
7537 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7538 mutex_unlock(&dev->struct_mutex);
7539
79158103 7540cleanup:
96b099fd
CW		 7541 spin_lock_irqsave(&dev->event_lock, flags);
7542 intel_crtc->unpin_work = NULL;
7543 spin_unlock_irqrestore(&dev->event_lock, flags);
7544
7317c75e
JB		 7545 drm_vblank_put(dev, intel_crtc->pipe);
7546free_work:
96b099fd
CW		 7547 kfree(work);
7548
7549 return ret;
6b95a207
KH		 7550}
7551
f6e5b160 7552static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7553 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7554 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7555};
7556
6ed0f796 7557bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7558{
6ed0f796
DV		 7559 struct intel_encoder *other_encoder;
7560 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7561
6ed0f796
DV		 7562 if (WARN_ON(!crtc))
7563 return false;
7564
7565 list_for_each_entry(other_encoder,
7566 &crtc->dev->mode_config.encoder_list,
7567 base.head) {
7568
7569 if (&other_encoder->new_crtc->base != crtc ||
7570 encoder == other_encoder)
7571 continue;
7572 else
7573 return true;
f47166d2
CW		 7574 }
7575
6ed0f796
DV		 7576 return false;
7577}
47f1c6c9 7578
50f56119
DV		 7579static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7580 struct drm_crtc *crtc)
7581{
7582 struct drm_device *dev;
7583 struct drm_crtc *tmp;
7584 int crtc_mask = 1;
47f1c6c9 7585
50f56119 7586 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7587
50f56119 7588 dev = crtc->dev;
47f1c6c9 7589
50f56119
DV		 7590 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7591 if (tmp == crtc)
7592 break;
7593 crtc_mask <<= 1;
7594 }
47f1c6c9 7595
50f56119
DV		 7596 if (encoder->possible_crtcs & crtc_mask)
7597 return true;
7598 return false;
47f1c6c9 7599}
79e53945 7600
9a935856
DV		 7601/**
7602 * intel_modeset_update_staged_output_state
7603 *
7604 * Updates the staged output configuration state, e.g. after we've read out the
7605 * current hw state.
7606 */
7607static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7608{
9a935856
DV		 7609 struct intel_encoder *encoder;
7610 struct intel_connector *connector;
f6e5b160 7611
9a935856
DV		 7612 list_for_each_entry(connector, &dev->mode_config.connector_list,
7613 base.head) {
7614 connector->new_encoder =
7615 to_intel_encoder(connector->base.encoder);
7616 }
f6e5b160 7617
9a935856
DV		 7618 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7619 base.head) {
7620 encoder->new_crtc =
7621 to_intel_crtc(encoder->base.crtc);
7622 }
f6e5b160
CW		 7623}
7624
9a935856
DV		 7625/**
7626 * intel_modeset_commit_output_state
7627 *
7628 * This function copies the stage display pipe configuration to the real one.
7629 */
7630static void intel_modeset_commit_output_state(struct drm_device *dev)
7631{
7632 struct intel_encoder *encoder;
7633 struct intel_connector *connector;
f6e5b160 7634
9a935856
DV		 7635 list_for_each_entry(connector, &dev->mode_config.connector_list,
7636 base.head) {
7637 connector->base.encoder = &connector->new_encoder->base;
7638 }
f6e5b160 7639
9a935856
DV		 7640 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7641 base.head) {
7642 encoder->base.crtc = &encoder->new_crtc->base;
7643 }
7644}
7645
4e53c2e0
DV		 7646static int
7647pipe_config_set_bpp(struct drm_crtc *crtc,
7648 struct drm_framebuffer *fb,
7649 struct intel_crtc_config *pipe_config)
7650{
7651 struct drm_device *dev = crtc->dev;
7652 struct drm_connector *connector;
7653 int bpp;
7654
d42264b1
DV		 7655 switch (fb->pixel_format) {
7656 case DRM_FORMAT_C8:
4e53c2e0
DV		 7657 bpp = 8*3; /* since we go through a colormap */
7658 break;
d42264b1
DV		 7659 case DRM_FORMAT_XRGB1555:
7660 case DRM_FORMAT_ARGB1555:
7661 /* checked in intel_framebuffer_init already */
7662 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7663 return -EINVAL;
7664 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7665 bpp = 6*3; /* min is 18bpp */
7666 break;
d42264b1
DV		 7667 case DRM_FORMAT_XBGR8888:
7668 case DRM_FORMAT_ABGR8888:
7669 /* checked in intel_framebuffer_init already */
7670 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7671 return -EINVAL;
7672 case DRM_FORMAT_XRGB8888:
7673 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7674 bpp = 8*3;
7675 break;
d42264b1
DV		 7676 case DRM_FORMAT_XRGB2101010:
7677 case DRM_FORMAT_ARGB2101010:
7678 case DRM_FORMAT_XBGR2101010:
7679 case DRM_FORMAT_ABGR2101010:
7680 /* checked in intel_framebuffer_init already */
7681 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7682 return -EINVAL;
4e53c2e0
DV		 7683 bpp = 10*3;
7684 break;
baba133a 7685 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7686 default:
7687 DRM_DEBUG_KMS("unsupported depth\n");
7688 return -EINVAL;
7689 }
7690
4e53c2e0
DV		 7691 pipe_config->pipe_bpp = bpp;
7692
7693 /* Clamp display bpp to EDID value */
7694 list_for_each_entry(connector, &dev->mode_config.connector_list,
7695 head) {
7696 if (connector->encoder && connector->encoder->crtc != crtc)
7697 continue;
7698
7699 /* Don't use an invalid EDID bpc value */
7700 if (connector->display_info.bpc &&
7701 connector->display_info.bpc * 3 < bpp) {
7702 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7703 bpp, connector->display_info.bpc*3);
7704 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7705 }
996a2239
DV		 7706
7707 /* Clamp bpp to 8 on screens without EDID 1.4 */
7708 if (connector->display_info.bpc == 0 && bpp > 24) {
7709 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7710 bpp);
7711 pipe_config->pipe_bpp = 24;
7712 }
4e53c2e0
DV		 7713 }
7714
7715 return bpp;
7716}
7717
b8cecdf5
DV		 7718static struct intel_crtc_config *
7719intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7720 struct drm_framebuffer *fb,
b8cecdf5 7721 struct drm_display_mode *mode)
ee7b9f93 7722{
7758a113 7723 struct drm_device *dev = crtc->dev;
7758a113
DV		 7724 struct drm_encoder_helper_funcs *encoder_funcs;
7725 struct intel_encoder *encoder;
b8cecdf5 7726 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7727 int plane_bpp, ret = -EINVAL;
7728 bool retry = true;
ee7b9f93 7729
b8cecdf5
DV		 7730 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7731 if (!pipe_config)
7758a113
DV		 7732 return ERR_PTR(-ENOMEM);
7733
b8cecdf5
DV		 7734 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7735 drm_mode_copy(&pipe_config->requested_mode, mode);
7736
4e53c2e0
DV		 7737 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7738 if (plane_bpp < 0)
7739 goto fail;
7740
e29c22c0 7741encoder_retry:
7758a113
DV		 7742 /* Pass our mode to the connectors and the CRTC to give them a chance to
7743 * adjust it according to limitations or connector properties, and also
7744 * a chance to reject the mode entirely.
47f1c6c9 7745 */
7758a113
DV		 7746 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7747 base.head) {
47f1c6c9 7748
7758a113
DV		 7749 if (&encoder->new_crtc->base != crtc)
7750 continue;
7ae89233
DV		 7751
7752 if (encoder->compute_config) {
7753 if (!(encoder->compute_config(encoder, pipe_config))) {
7754 DRM_DEBUG_KMS("Encoder config failure\n");
7755 goto fail;
7756 }
7757
7758 continue;
7759 }
7760
7758a113 7761 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7762 if (!(encoder_funcs->mode_fixup(&encoder->base,
7763 &pipe_config->requested_mode,
7764 &pipe_config->adjusted_mode))) {
7758a113
DV		 7765 DRM_DEBUG_KMS("Encoder fixup failed\n");
7766 goto fail;
7767 }
ee7b9f93 7768 }
47f1c6c9 7769
e29c22c0
DV		 7770 ret = intel_crtc_compute_config(crtc, pipe_config);
7771 if (ret < 0) {
7758a113
DV		 7772 DRM_DEBUG_KMS("CRTC fixup failed\n");
7773 goto fail;
ee7b9f93 7774 }
e29c22c0
DV		 7775
7776 if (ret == RETRY) {
7777 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7778 ret = -EINVAL;
7779 goto fail;
7780 }
7781
7782 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7783 retry = false;
7784 goto encoder_retry;
7785 }
7786
7758a113 7787 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7788
4e53c2e0
DV		 7789 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7790 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7791 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7792
b8cecdf5 7793 return pipe_config;
7758a113 7794fail:
b8cecdf5 7795 kfree(pipe_config);
e29c22c0 7796 return ERR_PTR(ret);
ee7b9f93 7797}
47f1c6c9 7798
e2e1ed41
DV		 7799/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7800 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7801static void
7802intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7803 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7804{
7805 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7806 struct drm_device *dev = crtc->dev;
7807 struct intel_encoder *encoder;
7808 struct intel_connector *connector;
7809 struct drm_crtc *tmp_crtc;
79e53945 7810
e2e1ed41 7811 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7812
e2e1ed41
DV		 7813 /* Check which crtcs have changed outputs connected to them, these need
7814 * to be part of the prepare_pipes mask. We don't (yet) support global
7815 * modeset across multiple crtcs, so modeset_pipes will only have one
7816 * bit set at most. */
7817 list_for_each_entry(connector, &dev->mode_config.connector_list,
7818 base.head) {
7819 if (connector->base.encoder == &connector->new_encoder->base)
7820 continue;
79e53945 7821
e2e1ed41
DV		 7822 if (connector->base.encoder) {
7823 tmp_crtc = connector->base.encoder->crtc;
7824
7825 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7826 }
7827
7828 if (connector->new_encoder)
7829 *prepare_pipes |=
7830 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7831 }
7832
e2e1ed41
DV		 7833 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7834 base.head) {
7835 if (encoder->base.crtc == &encoder->new_crtc->base)
7836 continue;
7837
7838 if (encoder->base.crtc) {
7839 tmp_crtc = encoder->base.crtc;
7840
7841 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7842 }
7843
7844 if (encoder->new_crtc)
7845 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7846 }
7847
e2e1ed41
DV		 7848 /* Check for any pipes that will be fully disabled ... */
7849 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7850 base.head) {
7851 bool used = false;
22fd0fab 7852
e2e1ed41
DV		 7853 /* Don't try to disable disabled crtcs. */
7854 if (!intel_crtc->base.enabled)
7855 continue;
7e7d76c3 7856
e2e1ed41
DV		 7857 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7858 base.head) {
7859 if (encoder->new_crtc == intel_crtc)
7860 used = true;
7861 }
7862
7863 if (!used)
7864 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7865 }
7866
e2e1ed41
DV		 7867
7868 /* set_mode is also used to update properties on life display pipes. */
7869 intel_crtc = to_intel_crtc(crtc);
7870 if (crtc->enabled)
7871 *prepare_pipes |= 1 << intel_crtc->pipe;
7872
b6c5164d
DV		 7873 /*
7874 * For simplicity do a full modeset on any pipe where the output routing
7875 * changed. We could be more clever, but that would require us to be
7876 * more careful with calling the relevant encoder->mode_set functions.
7877 */
e2e1ed41
DV		 7878 if (*prepare_pipes)
7879 *modeset_pipes = *prepare_pipes;
7880
7881 /* ... and mask these out. */
7882 *modeset_pipes &= ~(*disable_pipes);
7883 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7884
7885 /*
7886 * HACK: We don't (yet) fully support global modesets. intel_set_config
7887 * obies this rule, but the modeset restore mode of
7888 * intel_modeset_setup_hw_state does not.
7889 */
7890 *modeset_pipes &= 1 << intel_crtc->pipe;
7891 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7892
7893 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7894 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7895}
79e53945 7896
ea9d758d 7897static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7898{
ea9d758d 7899 struct drm_encoder *encoder;
f6e5b160 7900 struct drm_device *dev = crtc->dev;
f6e5b160 7901
ea9d758d
DV		 7902 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7903 if (encoder->crtc == crtc)
7904 return true;
7905
7906 return false;
7907}
7908
7909static void
7910intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7911{
7912 struct intel_encoder *intel_encoder;
7913 struct intel_crtc *intel_crtc;
7914 struct drm_connector *connector;
7915
7916 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7917 base.head) {
7918 if (!intel_encoder->base.crtc)
7919 continue;
7920
7921 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7922
7923 if (prepare_pipes & (1 << intel_crtc->pipe))
7924 intel_encoder->connectors_active = false;
7925 }
7926
7927 intel_modeset_commit_output_state(dev);
7928
7929 /* Update computed state. */
7930 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7931 base.head) {
7932 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7933 }
7934
7935 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7936 if (!connector->encoder || !connector->encoder->crtc)
7937 continue;
7938
7939 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7940
7941 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7942 struct drm_property *dpms_property =
7943 dev->mode_config.dpms_property;
7944
ea9d758d 7945 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7946 drm_object_property_set_value(&connector->base,
68d34720
DV		 7947 dpms_property,
7948 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7949
7950 intel_encoder = to_intel_encoder(connector->encoder);
7951 intel_encoder->connectors_active = true;
7952 }
7953 }
7954
7955}
7956
25c5b266
DV		 7957#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7958 list_for_each_entry((intel_crtc), \
7959 &(dev)->mode_config.crtc_list, \
7960 base.head) \
0973f18f 7961 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 7962
0e8ffe1b
DV		 7963static bool
7964intel_pipe_config_compare(struct intel_crtc_config *current_config,
7965 struct intel_crtc_config *pipe_config)
7966{
08a24034
DV		 7967#define PIPE_CONF_CHECK_I(name) \
7968 if (current_config->name != pipe_config->name) { \
7969 DRM_ERROR("mismatch in " #name " " \
7970 "(expected %i, found %i)\n", \
7971 current_config->name, \
7972 pipe_config->name); \
7973 return false; \
88adfff1
DV		 7974 }
7975
1bd1bd80
DV		 7976#define PIPE_CONF_CHECK_FLAGS(name, mask) \
7977 if ((current_config->name ^ pipe_config->name) & (mask)) { \
7978 DRM_ERROR("mismatch in " #name " " \
7979 "(expected %i, found %i)\n", \
7980 current_config->name & (mask), \
7981 pipe_config->name & (mask)); \
7982 return false; \
7983 }
7984
08a24034
DV		 7985 PIPE_CONF_CHECK_I(has_pch_encoder);
7986 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 7987 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
7988 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
7989 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
7990 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
7991 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 7992
1bd1bd80
DV		 7993 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
7994 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
7995 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
7996 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
7997 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
7998 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
7999
8000 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8001 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8002 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8003 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8004 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8005 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8006
8007 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8008 DRM_MODE_FLAG_INTERLACE);
8009
8010 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8011 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8012
08a24034 8013#undef PIPE_CONF_CHECK_I
1bd1bd80 8014#undef PIPE_CONF_CHECK_FLAGS
627eb5a3 8015
0e8ffe1b
DV		 8016 return true;
8017}
8018
b980514c 8019void
8af6cf88
DV		 8020intel_modeset_check_state(struct drm_device *dev)
8021{
0e8ffe1b 8022 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8023 struct intel_crtc *crtc;
8024 struct intel_encoder *encoder;
8025 struct intel_connector *connector;
0e8ffe1b 8026 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8027
8028 list_for_each_entry(connector, &dev->mode_config.connector_list,
8029 base.head) {
8030 /* This also checks the encoder/connector hw state with the
8031 * ->get_hw_state callbacks. */
8032 intel_connector_check_state(connector);
8033
8034 WARN(&connector->new_encoder->base != connector->base.encoder,
8035 "connector's staged encoder doesn't match current encoder\n");
8036 }
8037
8038 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8039 base.head) {
8040 bool enabled = false;
8041 bool active = false;
8042 enum pipe pipe, tracked_pipe;
8043
8044 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8045 encoder->base.base.id,
8046 drm_get_encoder_name(&encoder->base));
8047
8048 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8049 "encoder's stage crtc doesn't match current crtc\n");
8050 WARN(encoder->connectors_active && !encoder->base.crtc,
8051 "encoder's active_connectors set, but no crtc\n");
8052
8053 list_for_each_entry(connector, &dev->mode_config.connector_list,
8054 base.head) {
8055 if (connector->base.encoder != &encoder->base)
8056 continue;
8057 enabled = true;
8058 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8059 active = true;
8060 }
8061 WARN(!!encoder->base.crtc != enabled,
8062 "encoder's enabled state mismatch "
8063 "(expected %i, found %i)\n",
8064 !!encoder->base.crtc, enabled);
8065 WARN(active && !encoder->base.crtc,
8066 "active encoder with no crtc\n");
8067
8068 WARN(encoder->connectors_active != active,
8069 "encoder's computed active state doesn't match tracked active state "
8070 "(expected %i, found %i)\n", active, encoder->connectors_active);
8071
8072 active = encoder->get_hw_state(encoder, &pipe);
8073 WARN(active != encoder->connectors_active,
8074 "encoder's hw state doesn't match sw tracking "
8075 "(expected %i, found %i)\n",
8076 encoder->connectors_active, active);
8077
8078 if (!encoder->base.crtc)
8079 continue;
8080
8081 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8082 WARN(active && pipe != tracked_pipe,
8083 "active encoder's pipe doesn't match"
8084 "(expected %i, found %i)\n",
8085 tracked_pipe, pipe);
8086
8087 }
8088
8089 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8090 base.head) {
8091 bool enabled = false;
8092 bool active = false;
8093
8094 DRM_DEBUG_KMS("[CRTC:%d]\n",
8095 crtc->base.base.id);
8096
8097 WARN(crtc->active && !crtc->base.enabled,
8098 "active crtc, but not enabled in sw tracking\n");
8099
8100 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8101 base.head) {
8102 if (encoder->base.crtc != &crtc->base)
8103 continue;
8104 enabled = true;
8105 if (encoder->connectors_active)
8106 active = true;
8107 }
8108 WARN(active != crtc->active,
8109 "crtc's computed active state doesn't match tracked active state "
8110 "(expected %i, found %i)\n", active, crtc->active);
8111 WARN(enabled != crtc->base.enabled,
8112 "crtc's computed enabled state doesn't match tracked enabled state "
8113 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8114
88adfff1 8115 memset(&pipe_config, 0, sizeof(pipe_config));
60c4ae10 8116 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 8117 active = dev_priv->display.get_pipe_config(crtc,
8118 &pipe_config);
8119 WARN(crtc->active != active,
8120 "crtc active state doesn't match with hw state "
8121 "(expected %i, found %i)\n", crtc->active, active);
8122
8123 WARN(active &&
8124 !intel_pipe_config_compare(&crtc->config, &pipe_config),
8125 "pipe state doesn't match!\n");
8af6cf88
DV		 8126 }
8127}
8128
f30da187
DV		 8129static int __intel_set_mode(struct drm_crtc *crtc,
8130 struct drm_display_mode *mode,
8131 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8132{
8133 struct drm_device *dev = crtc->dev;
dbf2b54e 8134 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8135 struct drm_display_mode *saved_mode, *saved_hwmode;
8136 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8137 struct intel_crtc *intel_crtc;
8138 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8139 int ret = 0;
a6778b3c 8140
3ac18232 8141 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8142 if (!saved_mode)
8143 return -ENOMEM;
3ac18232 8144 saved_hwmode = saved_mode + 1;
a6778b3c 8145
e2e1ed41 8146 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8147 &prepare_pipes, &disable_pipes);
8148
3ac18232
TG		 8149 *saved_hwmode = crtc->hwmode;
8150 *saved_mode = crtc->mode;
a6778b3c 8151
25c5b266
DV		 8152 /* Hack: Because we don't (yet) support global modeset on multiple
8153 * crtcs, we don't keep track of the new mode for more than one crtc.
8154 * Hence simply check whether any bit is set in modeset_pipes in all the
8155 * pieces of code that are not yet converted to deal with mutliple crtcs
8156 * changing their mode at the same time. */
25c5b266 8157 if (modeset_pipes) {
4e53c2e0 8158 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8159 if (IS_ERR(pipe_config)) {
8160 ret = PTR_ERR(pipe_config);
8161 pipe_config = NULL;
8162
3ac18232 8163 goto out;
25c5b266 8164 }
25c5b266 8165 }
a6778b3c 8166
460da916
DV		 8167 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8168 intel_crtc_disable(&intel_crtc->base);
8169
ea9d758d
DV		 8170 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8171 if (intel_crtc->base.enabled)
8172 dev_priv->display.crtc_disable(&intel_crtc->base);
8173 }
a6778b3c 8174
6c4c86f5
DV		 8175 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8176 * to set it here already despite that we pass it down the callchain.
f6e5b160 8177 */
b8cecdf5 8178 if (modeset_pipes) {
3b117c8f 8179 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
25c5b266 8180 crtc->mode = *mode;
b8cecdf5
DV		 8181 /* mode_set/enable/disable functions rely on a correct pipe
8182 * config. */
8183 to_intel_crtc(crtc)->config = *pipe_config;
3b117c8f 8184 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
b8cecdf5 8185 }
7758a113 8186
ea9d758d
DV		 8187 /* Only after disabling all output pipelines that will be changed can we
8188 * update the the output configuration. */
8189 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8190
47fab737
DV		 8191 if (dev_priv->display.modeset_global_resources)
8192 dev_priv->display.modeset_global_resources(dev);
8193
a6778b3c
DV		 8194 /* Set up the DPLL and any encoders state that needs to adjust or depend
8195 * on the DPLL.
f6e5b160 8196 */
25c5b266 8197 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8198 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8199 x, y, fb);
8200 if (ret)
8201 goto done;
a6778b3c
DV		 8202 }
8203
8204 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8205 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8206 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8207
25c5b266
DV		 8208 if (modeset_pipes) {
8209 /* Store real post-adjustment hardware mode. */
b8cecdf5 8210 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8211
25c5b266
DV		 8212 /* Calculate and store various constants which
8213 * are later needed by vblank and swap-completion
8214 * timestamping. They are derived from true hwmode.
8215 */
8216 drm_calc_timestamping_constants(crtc);
8217 }
a6778b3c
DV		 8218
8219 /* FIXME: add subpixel order */
8220done:
c0c36b94 8221 if (ret && crtc->enabled) {
3ac18232
TG		 8222 crtc->hwmode = *saved_hwmode;
8223 crtc->mode = *saved_mode;
a6778b3c
DV		 8224 }
8225
3ac18232 8226out:
b8cecdf5 8227 kfree(pipe_config);
3ac18232 8228 kfree(saved_mode);
a6778b3c 8229 return ret;
f6e5b160
CW		 8230}
8231
f30da187
DV		 8232int intel_set_mode(struct drm_crtc *crtc,
8233 struct drm_display_mode *mode,
8234 int x, int y, struct drm_framebuffer *fb)
8235{
8236 int ret;
8237
8238 ret = __intel_set_mode(crtc, mode, x, y, fb);
8239
8240 if (ret == 0)
8241 intel_modeset_check_state(crtc->dev);
8242
8243 return ret;
8244}
8245
c0c36b94
CW		 8246void intel_crtc_restore_mode(struct drm_crtc *crtc)
8247{
8248 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8249}
8250
25c5b266
DV		 8251#undef for_each_intel_crtc_masked
8252
d9e55608
DV		 8253static void intel_set_config_free(struct intel_set_config *config)
8254{
8255 if (!config)
8256 return;
8257
1aa4b628
DV		 8258 kfree(config->save_connector_encoders);
8259 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8260 kfree(config);
8261}
8262
85f9eb71
DV		 8263static int intel_set_config_save_state(struct drm_device *dev,
8264 struct intel_set_config *config)
8265{
85f9eb71
DV		 8266 struct drm_encoder *encoder;
8267 struct drm_connector *connector;
8268 int count;
8269
1aa4b628
DV		 8270 config->save_encoder_crtcs =
8271 kcalloc(dev->mode_config.num_encoder,
8272 sizeof(struct drm_crtc *), GFP_KERNEL);
8273 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8274 return -ENOMEM;
8275
1aa4b628
DV		 8276 config->save_connector_encoders =
8277 kcalloc(dev->mode_config.num_connector,
8278 sizeof(struct drm_encoder *), GFP_KERNEL);
8279 if (!config->save_connector_encoders)
85f9eb71
DV		 8280 return -ENOMEM;
8281
8282 /* Copy data. Note that driver private data is not affected.
8283 * Should anything bad happen only the expected state is
8284 * restored, not the drivers personal bookkeeping.
8285 */
85f9eb71
DV		 8286 count = 0;
8287 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8288 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8289 }
8290
8291 count = 0;
8292 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8293 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8294 }
8295
8296 return 0;
8297}
8298
8299static void intel_set_config_restore_state(struct drm_device *dev,
8300 struct intel_set_config *config)
8301{
9a935856
DV		 8302 struct intel_encoder *encoder;
8303 struct intel_connector *connector;
85f9eb71
DV		 8304 int count;
8305
85f9eb71 8306 count = 0;
9a935856
DV		 8307 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8308 encoder->new_crtc =
8309 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8310 }
8311
8312 count = 0;
9a935856
DV		 8313 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8314 connector->new_encoder =
8315 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8316 }
8317}
8318
5e2b584e
DV		 8319static void
8320intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8321 struct intel_set_config *config)
8322{
8323
8324 /* We should be able to check here if the fb has the same properties
8325 * and then just flip_or_move it */
8326 if (set->crtc->fb != set->fb) {
8327 /* If we have no fb then treat it as a full mode set */
8328 if (set->crtc->fb == NULL) {
8329 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8330 config->mode_changed = true;
8331 } else if (set->fb == NULL) {
8332 config->mode_changed = true;
72f4901e
DV		 8333 } else if (set->fb->pixel_format !=
8334 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8335 config->mode_changed = true;
8336 } else
8337 config->fb_changed = true;
8338 }
8339
835c5873 8340 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8341 config->fb_changed = true;
8342
8343 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8344 DRM_DEBUG_KMS("modes are different, full mode set\n");
8345 drm_mode_debug_printmodeline(&set->crtc->mode);
8346 drm_mode_debug_printmodeline(set->mode);
8347 config->mode_changed = true;
8348 }
8349}
8350
2e431051 8351static int
9a935856
DV		 8352intel_modeset_stage_output_state(struct drm_device *dev,
8353 struct drm_mode_set *set,
8354 struct intel_set_config *config)
50f56119 8355{
85f9eb71 8356 struct drm_crtc *new_crtc;
9a935856
DV		 8357 struct intel_connector *connector;
8358 struct intel_encoder *encoder;
2e431051 8359 int count, ro;
50f56119 8360
9abdda74 8361 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8362 * of connectors. For paranoia, double-check this. */
8363 WARN_ON(!set->fb && (set->num_connectors != 0));
8364 WARN_ON(set->fb && (set->num_connectors == 0));
8365
50f56119 8366 count = 0;
9a935856
DV		 8367 list_for_each_entry(connector, &dev->mode_config.connector_list,
8368 base.head) {
8369 /* Otherwise traverse passed in connector list and get encoders
8370 * for them. */
50f56119 8371 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8372 if (set->connectors[ro] == &connector->base) {
8373 connector->new_encoder = connector->encoder;
50f56119
DV		 8374 break;
8375 }
8376 }
8377
9a935856
DV		 8378 /* If we disable the crtc, disable all its connectors. Also, if
8379 * the connector is on the changing crtc but not on the new
8380 * connector list, disable it. */
8381 if ((!set->fb || ro == set->num_connectors) &&
8382 connector->base.encoder &&
8383 connector->base.encoder->crtc == set->crtc) {
8384 connector->new_encoder = NULL;
8385
8386 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8387 connector->base.base.id,
8388 drm_get_connector_name(&connector->base));
8389 }
8390
8391
8392 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8393 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8394 config->mode_changed = true;
50f56119
DV		 8395 }
8396 }
9a935856 8397 /* connector->new_encoder is now updated for all connectors. */
50f56119 8398
9a935856 8399 /* Update crtc of enabled connectors. */
50f56119 8400 count = 0;
9a935856
DV		 8401 list_for_each_entry(connector, &dev->mode_config.connector_list,
8402 base.head) {
8403 if (!connector->new_encoder)
50f56119
DV		 8404 continue;
8405
9a935856 8406 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8407
8408 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8409 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8410 new_crtc = set->crtc;
8411 }
8412
8413 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8414 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8415 new_crtc)) {
5e2b584e 8416 return -EINVAL;
50f56119 8417 }
9a935856
DV		 8418 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8419
8420 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8421 connector->base.base.id,
8422 drm_get_connector_name(&connector->base),
8423 new_crtc->base.id);
8424 }
8425
8426 /* Check for any encoders that needs to be disabled. */
8427 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8428 base.head) {
8429 list_for_each_entry(connector,
8430 &dev->mode_config.connector_list,
8431 base.head) {
8432 if (connector->new_encoder == encoder) {
8433 WARN_ON(!connector->new_encoder->new_crtc);
8434
8435 goto next_encoder;
8436 }
8437 }
8438 encoder->new_crtc = NULL;
8439next_encoder:
8440 /* Only now check for crtc changes so we don't miss encoders
8441 * that will be disabled. */
8442 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8443 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8444 config->mode_changed = true;
50f56119
DV		 8445 }
8446 }
9a935856 8447 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8448
2e431051
DV		 8449 return 0;
8450}
8451
8452static int intel_crtc_set_config(struct drm_mode_set *set)
8453{
8454 struct drm_device *dev;
2e431051
DV		 8455 struct drm_mode_set save_set;
8456 struct intel_set_config *config;
8457 int ret;
2e431051 8458
8d3e375e
DV		 8459 BUG_ON(!set);
8460 BUG_ON(!set->crtc);
8461 BUG_ON(!set->crtc->helper_private);
2e431051 8462
7e53f3a4
DV		 8463 /* Enforce sane interface api - has been abused by the fb helper. */
8464 BUG_ON(!set->mode && set->fb);
8465 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8466
2e431051
DV		 8467 if (set->fb) {
8468 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8469 set->crtc->base.id, set->fb->base.id,
8470 (int)set->num_connectors, set->x, set->y);
8471 } else {
8472 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8473 }
8474
8475 dev = set->crtc->dev;
8476
8477 ret = -ENOMEM;
8478 config = kzalloc(sizeof(*config), GFP_KERNEL);
8479 if (!config)
8480 goto out_config;
8481
8482 ret = intel_set_config_save_state(dev, config);
8483 if (ret)
8484 goto out_config;
8485
8486 save_set.crtc = set->crtc;
8487 save_set.mode = &set->crtc->mode;
8488 save_set.x = set->crtc->x;
8489 save_set.y = set->crtc->y;
8490 save_set.fb = set->crtc->fb;
8491
8492 /* Compute whether we need a full modeset, only an fb base update or no
8493 * change at all. In the future we might also check whether only the
8494 * mode changed, e.g. for LVDS where we only change the panel fitter in
8495 * such cases. */
8496 intel_set_config_compute_mode_changes(set, config);
8497
9a935856 8498 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8499 if (ret)
8500 goto fail;
8501
5e2b584e 8502 if (config->mode_changed) {
87f1faa6 8503 if (set->mode) {
50f56119
DV		 8504 DRM_DEBUG_KMS("attempting to set mode from"
8505 " userspace\n");
8506 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8507 }
8508
c0c36b94
CW		 8509 ret = intel_set_mode(set->crtc, set->mode,
8510 set->x, set->y, set->fb);
8511 if (ret) {
8512 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8513 set->crtc->base.id, ret);
87f1faa6
DV		 8514 goto fail;
8515 }
5e2b584e 8516 } else if (config->fb_changed) {
4878cae2
VS		 8517 intel_crtc_wait_for_pending_flips(set->crtc);
8518
4f660f49 8519 ret = intel_pipe_set_base(set->crtc,
94352cf9 8520 set->x, set->y, set->fb);
50f56119
DV		 8521 }
8522
d9e55608
DV		 8523 intel_set_config_free(config);
8524
50f56119
DV		 8525 return 0;
8526
8527fail:
85f9eb71 8528 intel_set_config_restore_state(dev, config);
50f56119
DV		 8529
8530 /* Try to restore the config */
5e2b584e 8531 if (config->mode_changed &&
c0c36b94
CW		 8532 intel_set_mode(save_set.crtc, save_set.mode,
8533 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8534 DRM_ERROR("failed to restore config after modeset failure\n");
8535
d9e55608
DV		 8536out_config:
8537 intel_set_config_free(config);
50f56119
DV		 8538 return ret;
8539}
f6e5b160
CW		 8540
8541static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8542 .cursor_set = intel_crtc_cursor_set,
8543 .cursor_move = intel_crtc_cursor_move,
8544 .gamma_set = intel_crtc_gamma_set,
50f56119 8545 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8546 .destroy = intel_crtc_destroy,
8547 .page_flip = intel_crtc_page_flip,
8548};
8549
79f689aa
PZ		 8550static void intel_cpu_pll_init(struct drm_device *dev)
8551{
affa9354 8552 if (HAS_DDI(dev))
79f689aa
PZ		 8553 intel_ddi_pll_init(dev);
8554}
8555
ee7b9f93
JB		 8556static void intel_pch_pll_init(struct drm_device *dev)
8557{
8558 drm_i915_private_t *dev_priv = dev->dev_private;
8559 int i;
8560
8561 if (dev_priv->num_pch_pll == 0) {
8562 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8563 return;
8564 }
8565
8566 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8567 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8568 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8569 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8570 }
8571}
8572
b358d0a6 8573static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8574{
22fd0fab 8575 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8576 struct intel_crtc *intel_crtc;
8577 int i;
8578
8579 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8580 if (intel_crtc == NULL)
8581 return;
8582
8583 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8584
8585 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8586 for (i = 0; i < 256; i++) {
8587 intel_crtc->lut_r[i] = i;
8588 intel_crtc->lut_g[i] = i;
8589 intel_crtc->lut_b[i] = i;
8590 }
8591
80824003
JB		 8592 /* Swap pipes & planes for FBC on pre-965 */
8593 intel_crtc->pipe = pipe;
8594 intel_crtc->plane = pipe;
3b117c8f 8595 intel_crtc->config.cpu_transcoder = pipe;
e2e767ab 8596 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8597 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8598 intel_crtc->plane = !pipe;
80824003
JB		 8599 }
8600
22fd0fab
JB		 8601 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8602 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8603 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8604 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8605
79e53945 8606 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8607}
8608
08d7b3d1 8609int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8610 struct drm_file *file)
08d7b3d1 8611{
08d7b3d1 8612 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8613 struct drm_mode_object *drmmode_obj;
8614 struct intel_crtc *crtc;
08d7b3d1 8615
1cff8f6b
DV		 8616 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8617 return -ENODEV;
08d7b3d1 8618
c05422d5
DV		 8619 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8620 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8621
c05422d5 8622 if (!drmmode_obj) {
08d7b3d1
CW		 8623 DRM_ERROR("no such CRTC id\n");
8624 return -EINVAL;
8625 }
8626
c05422d5
DV		 8627 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8628 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8629
c05422d5 8630 return 0;
08d7b3d1
CW		 8631}
8632
66a9278e 8633static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8634{
66a9278e
DV		 8635 struct drm_device *dev = encoder->base.dev;
8636 struct intel_encoder *source_encoder;
79e53945 8637 int index_mask = 0;
79e53945
JB		 8638 int entry = 0;
8639
66a9278e
DV		 8640 list_for_each_entry(source_encoder,
8641 &dev->mode_config.encoder_list, base.head) {
8642
8643 if (encoder == source_encoder)
79e53945 8644 index_mask |= (1 << entry);
66a9278e
DV		 8645
8646 /* Intel hw has only one MUX where enocoders could be cloned. */
8647 if (encoder->cloneable && source_encoder->cloneable)
8648 index_mask |= (1 << entry);
8649
79e53945
JB		 8650 entry++;
8651 }
4ef69c7a 8652
79e53945
JB		 8653 return index_mask;
8654}
8655
4d302442
CW		 8656static bool has_edp_a(struct drm_device *dev)
8657{
8658 struct drm_i915_private *dev_priv = dev->dev_private;
8659
8660 if (!IS_MOBILE(dev))
8661 return false;
8662
8663 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8664 return false;
8665
8666 if (IS_GEN5(dev) &&
8667 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8668 return false;
8669
8670 return true;
8671}
8672
79e53945
JB		 8673static void intel_setup_outputs(struct drm_device *dev)
8674{
725e30ad 8675 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8676 struct intel_encoder *encoder;
cb0953d7 8677 bool dpd_is_edp = false;
f3cfcba6 8678 bool has_lvds;
79e53945 8679
f3cfcba6 8680 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8681 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8682 /* disable the panel fitter on everything but LVDS */
8683 I915_WRITE(PFIT_CONTROL, 0);
8684 }
79e53945 8685
c40c0f5b 8686 if (!IS_ULT(dev))
79935fca 8687 intel_crt_init(dev);
cb0953d7 8688
affa9354 8689 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8690 int found;
8691
8692 /* Haswell uses DDI functions to detect digital outputs */
8693 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8694 /* DDI A only supports eDP */
8695 if (found)
8696 intel_ddi_init(dev, PORT_A);
8697
8698 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8699 * register */
8700 found = I915_READ(SFUSE_STRAP);
8701
8702 if (found & SFUSE_STRAP_DDIB_DETECTED)
8703 intel_ddi_init(dev, PORT_B);
8704 if (found & SFUSE_STRAP_DDIC_DETECTED)
8705 intel_ddi_init(dev, PORT_C);
8706 if (found & SFUSE_STRAP_DDID_DETECTED)
8707 intel_ddi_init(dev, PORT_D);
8708 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8709 int found;
270b3042
DV		 8710 dpd_is_edp = intel_dpd_is_edp(dev);
8711
8712 if (has_edp_a(dev))
8713 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8714
dc0fa718 8715 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8716 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8717 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8718 if (!found)
e2debe91 8719 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8720 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8721 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8722 }
8723
dc0fa718 8724 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8725 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8726
dc0fa718 8727 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8728 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8729
5eb08b69 8730 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8731 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8732
270b3042 8733 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8734 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8735 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8736 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8737 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8738 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8739
dc0fa718 8740 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8741 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8742 PORT_B);
67cfc203
VS		 8743 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8744 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8745 }
103a196f 8746 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8747 bool found = false;
7d57382e 8748
e2debe91 8749 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8750 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8751 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8752 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8753 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8754 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8755 }
27185ae1 8756
e7281eab 8757 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8758 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 8759 }
13520b05
KH		 8760
8761 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8762
e2debe91 8763 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8764 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8765 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8766 }
27185ae1 8767
e2debe91 8768 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8769
b01f2c3a
JB		 8770 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8771 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8772 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 8773 }
e7281eab 8774 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8775 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 8776 }
27185ae1 8777
b01f2c3a 8778 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 8779 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 8780 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 8781 } else if (IS_GEN2(dev))
79e53945
JB		 8782 intel_dvo_init(dev);
8783
103a196f 8784 if (SUPPORTS_TV(dev))
79e53945
JB		 8785 intel_tv_init(dev);
8786
4ef69c7a
CW		 8787 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8788 encoder->base.possible_crtcs = encoder->crtc_mask;
8789 encoder->base.possible_clones =
66a9278e 8790 intel_encoder_clones(encoder);
79e53945 8791 }
47356eb6 8792
dde86e2d 8793 intel_init_pch_refclk(dev);
270b3042
DV		 8794
8795 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8796}
8797
8798static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8799{
8800 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8801
8802 drm_framebuffer_cleanup(fb);
05394f39 8803 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8804
8805 kfree(intel_fb);
8806}
8807
8808static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8809 struct drm_file *file,
79e53945
JB		 8810 unsigned int *handle)
8811{
8812 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8813 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8814
05394f39 8815 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8816}
8817
8818static const struct drm_framebuffer_funcs intel_fb_funcs = {
8819 .destroy = intel_user_framebuffer_destroy,
8820 .create_handle = intel_user_framebuffer_create_handle,
8821};
8822
38651674
DA		 8823int intel_framebuffer_init(struct drm_device *dev,
8824 struct intel_framebuffer *intel_fb,
308e5bcb 8825 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8826 struct drm_i915_gem_object *obj)
79e53945 8827{
79e53945
JB		 8828 int ret;
8829
c16ed4be
CW		 8830 if (obj->tiling_mode == I915_TILING_Y) {
8831 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8832 return -EINVAL;
c16ed4be 8833 }
57cd6508 8834
c16ed4be
CW		 8835 if (mode_cmd->pitches[0] & 63) {
8836 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8837 mode_cmd->pitches[0]);
57cd6508 8838 return -EINVAL;
c16ed4be 8839 }
57cd6508 8840
5d7bd705 8841 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8842 if (mode_cmd->pitches[0] > 32768) {
8843 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8844 mode_cmd->pitches[0]);
5d7bd705 8845 return -EINVAL;
c16ed4be 8846 }
5d7bd705
VS		 8847
8848 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8849 mode_cmd->pitches[0] != obj->stride) {
8850 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8851 mode_cmd->pitches[0], obj->stride);
5d7bd705 8852 return -EINVAL;
c16ed4be 8853 }
5d7bd705 8854
57779d06 8855 /* Reject formats not supported by any plane early. */
308e5bcb 8856 switch (mode_cmd->pixel_format) {
57779d06 8857 case DRM_FORMAT_C8:
04b3924d
VS		 8858 case DRM_FORMAT_RGB565:
8859 case DRM_FORMAT_XRGB8888:
8860 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8861 break;
8862 case DRM_FORMAT_XRGB1555:
8863 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8864 if (INTEL_INFO(dev)->gen > 3) {
8865 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8866 return -EINVAL;
c16ed4be 8867 }
57779d06
VS		 8868 break;
8869 case DRM_FORMAT_XBGR8888:
8870 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8871 case DRM_FORMAT_XRGB2101010:
8872 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8873 case DRM_FORMAT_XBGR2101010:
8874 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8875 if (INTEL_INFO(dev)->gen < 4) {
8876 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8877 return -EINVAL;
c16ed4be 8878 }
b5626747 8879 break;
04b3924d
VS		 8880 case DRM_FORMAT_YUYV:
8881 case DRM_FORMAT_UYVY:
8882 case DRM_FORMAT_YVYU:
8883 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8884 if (INTEL_INFO(dev)->gen < 5) {
8885 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8886 return -EINVAL;
c16ed4be 8887 }
57cd6508
CW		 8888 break;
8889 default:
c16ed4be 8890 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8891 return -EINVAL;
8892 }
8893
90f9a336
VS		 8894 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8895 if (mode_cmd->offsets[0] != 0)
8896 return -EINVAL;
8897
c7d73f6a
DV		 8898 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8899 intel_fb->obj = obj;
8900
79e53945
JB		 8901 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8902 if (ret) {
8903 DRM_ERROR("framebuffer init failed %d\n", ret);
8904 return ret;
8905 }
8906
79e53945
JB		 8907 return 0;
8908}
8909
79e53945
JB		 8910static struct drm_framebuffer *
8911intel_user_framebuffer_create(struct drm_device *dev,
8912 struct drm_file *filp,
308e5bcb 8913 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8914{
05394f39 8915 struct drm_i915_gem_object *obj;
79e53945 8916
308e5bcb
JB		 8917 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8918 mode_cmd->handles[0]));
c8725226 8919 if (&obj->base == NULL)
cce13ff7 8920 return ERR_PTR(-ENOENT);
79e53945 8921
d2dff872 8922 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8923}
8924
79e53945 8925static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8926 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8927 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8928};
8929
e70236a8
JB		 8930/* Set up chip specific display functions */
8931static void intel_init_display(struct drm_device *dev)
8932{
8933 struct drm_i915_private *dev_priv = dev->dev_private;
8934
affa9354 8935 if (HAS_DDI(dev)) {
0e8ffe1b 8936 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 8937 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8938 dev_priv->display.crtc_enable = haswell_crtc_enable;
8939 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8940 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8941 dev_priv->display.update_plane = ironlake_update_plane;
8942 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 8943 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 8944 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8945 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8946 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8947 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8948 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 8949 } else if (IS_VALLEYVIEW(dev)) {
8950 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8951 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8952 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8953 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8954 dev_priv->display.off = i9xx_crtc_off;
8955 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8956 } else {
0e8ffe1b 8957 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 8958 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8959 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8960 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8961 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8962 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8963 }
e70236a8 8964
e70236a8 8965 /* Returns the core display clock speed */
25eb05fc
JB		 8966 if (IS_VALLEYVIEW(dev))
8967 dev_priv->display.get_display_clock_speed =
8968 valleyview_get_display_clock_speed;
8969 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8970 dev_priv->display.get_display_clock_speed =
8971 i945_get_display_clock_speed;
8972 else if (IS_I915G(dev))
8973 dev_priv->display.get_display_clock_speed =
8974 i915_get_display_clock_speed;
f2b115e6 8975 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8976 dev_priv->display.get_display_clock_speed =
8977 i9xx_misc_get_display_clock_speed;
8978 else if (IS_I915GM(dev))
8979 dev_priv->display.get_display_clock_speed =
8980 i915gm_get_display_clock_speed;
8981 else if (IS_I865G(dev))
8982 dev_priv->display.get_display_clock_speed =
8983 i865_get_display_clock_speed;
f0f8a9ce 8984 else if (IS_I85X(dev))
e70236a8
JB		 8985 dev_priv->display.get_display_clock_speed =
8986 i855_get_display_clock_speed;
8987 else /* 852, 830 */
8988 dev_priv->display.get_display_clock_speed =
8989 i830_get_display_clock_speed;
8990
7f8a8569 8991 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8992 if (IS_GEN5(dev)) {
674cf967 8993 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8994 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8995 } else if (IS_GEN6(dev)) {
674cf967 8996 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8997 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8998 } else if (IS_IVYBRIDGE(dev)) {
8999 /* FIXME: detect B0+ stepping and use auto training */
9000 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9001 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9002 dev_priv->display.modeset_global_resources =
9003 ivb_modeset_global_resources;
c82e4d26
ED		 9004 } else if (IS_HASWELL(dev)) {
9005 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9006 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9007 dev_priv->display.modeset_global_resources =
9008 haswell_modeset_global_resources;
a0e63c22 9009 }
6067aaea 9010 } else if (IS_G4X(dev)) {
e0dac65e 9011 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9012 }
8c9f3aaf
JB		 9013
9014 /* Default just returns -ENODEV to indicate unsupported */
9015 dev_priv->display.queue_flip = intel_default_queue_flip;
9016
9017 switch (INTEL_INFO(dev)->gen) {
9018 case 2:
9019 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9020 break;
9021
9022 case 3:
9023 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9024 break;
9025
9026 case 4:
9027 case 5:
9028 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9029 break;
9030
9031 case 6:
9032 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9033 break;
7c9017e5
JB		 9034 case 7:
9035 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9036 break;
8c9f3aaf 9037 }
e70236a8
JB		 9038}
9039
b690e96c
JB		 9040/*
9041 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9042 * resume, or other times. This quirk makes sure that's the case for
9043 * affected systems.
9044 */
0206e353 9045static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9046{
9047 struct drm_i915_private *dev_priv = dev->dev_private;
9048
9049 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9050 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9051}
9052
435793df
KP		 9053/*
9054 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9055 */
9056static void quirk_ssc_force_disable(struct drm_device *dev)
9057{
9058 struct drm_i915_private *dev_priv = dev->dev_private;
9059 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9060 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9061}
9062
4dca20ef 9063/*
5a15ab5b
CE		 9064 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9065 * brightness value
4dca20ef
CE		 9066 */
9067static void quirk_invert_brightness(struct drm_device *dev)
9068{
9069 struct drm_i915_private *dev_priv = dev->dev_private;
9070 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9071 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9072}
9073
b690e96c
JB		 9074struct intel_quirk {
9075 int device;
9076 int subsystem_vendor;
9077 int subsystem_device;
9078 void (*hook)(struct drm_device *dev);
9079};
9080
5f85f176
EE		 9081/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9082struct intel_dmi_quirk {
9083 void (*hook)(struct drm_device *dev);
9084 const struct dmi_system_id (*dmi_id_list)[];
9085};
9086
9087static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9088{
9089 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9090 return 1;
9091}
9092
9093static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9094 {
9095 .dmi_id_list = &(const struct dmi_system_id[]) {
9096 {
9097 .callback = intel_dmi_reverse_brightness,
9098 .ident = "NCR Corporation",
9099 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9100 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9101 },
9102 },
9103 { } /* terminating entry */
9104 },
9105 .hook = quirk_invert_brightness,
9106 },
9107};
9108
c43b5634 9109static struct intel_quirk intel_quirks[] = {
b690e96c 9110 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9111 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9112
b690e96c
JB		 9113 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9114 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9115
b690e96c
JB		 9116 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9117 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9118
ccd0d36e 9119 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9120 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9121 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9122
9123 /* Lenovo U160 cannot use SSC on LVDS */
9124 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9125
9126 /* Sony Vaio Y cannot use SSC on LVDS */
9127 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9128
9129 /* Acer Aspire 5734Z must invert backlight brightness */
9130 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9131
9132 /* Acer/eMachines G725 */
9133 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9134
9135 /* Acer/eMachines e725 */
9136 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9137
9138 /* Acer/Packard Bell NCL20 */
9139 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9140
9141 /* Acer Aspire 4736Z */
9142 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9143};
9144
9145static void intel_init_quirks(struct drm_device *dev)
9146{
9147 struct pci_dev *d = dev->pdev;
9148 int i;
9149
9150 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9151 struct intel_quirk *q = &intel_quirks[i];
9152
9153 if (d->device == q->device &&
9154 (d->subsystem_vendor == q->subsystem_vendor ||
9155 q->subsystem_vendor == PCI_ANY_ID) &&
9156 (d->subsystem_device == q->subsystem_device ||
9157 q->subsystem_device == PCI_ANY_ID))
9158 q->hook(dev);
9159 }
5f85f176
EE		 9160 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9161 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9162 intel_dmi_quirks[i].hook(dev);
9163 }
b690e96c
JB		 9164}
9165
9cce37f4
JB		 9166/* Disable the VGA plane that we never use */
9167static void i915_disable_vga(struct drm_device *dev)
9168{
9169 struct drm_i915_private *dev_priv = dev->dev_private;
9170 u8 sr1;
766aa1c4 9171 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9172
9173 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9174 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9175 sr1 = inb(VGA_SR_DATA);
9176 outb(sr1 | 1<<5, VGA_SR_DATA);
9177 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9178 udelay(300);
9179
9180 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9181 POSTING_READ(vga_reg);
9182}
9183
f817586c
DV		 9184void intel_modeset_init_hw(struct drm_device *dev)
9185{
fa42e23c 9186 intel_init_power_well(dev);
0232e927 9187
a8f78b58
ED		 9188 intel_prepare_ddi(dev);
9189
f817586c
DV		 9190 intel_init_clock_gating(dev);
9191
79f5b2c7 9192 mutex_lock(&dev->struct_mutex);
8090c6b9 9193 intel_enable_gt_powersave(dev);
79f5b2c7 9194 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9195}
9196
7d708ee4
ID		 9197void intel_modeset_suspend_hw(struct drm_device *dev)
9198{
9199 intel_suspend_hw(dev);
9200}
9201
79e53945
JB		 9202void intel_modeset_init(struct drm_device *dev)
9203{
652c393a 9204 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9205 int i, j, ret;
79e53945
JB		 9206
9207 drm_mode_config_init(dev);
9208
9209 dev->mode_config.min_width = 0;
9210 dev->mode_config.min_height = 0;
9211
019d96cb
DA		 9212 dev->mode_config.preferred_depth = 24;
9213 dev->mode_config.prefer_shadow = 1;
9214
e6ecefaa 9215 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9216
b690e96c
JB		 9217 intel_init_quirks(dev);
9218
1fa61106
ED		 9219 intel_init_pm(dev);
9220
e3c74757
BW		 9221 if (INTEL_INFO(dev)->num_pipes == 0)
9222 return;
9223
e70236a8
JB		 9224 intel_init_display(dev);
9225
a6c45cf0
CW		 9226 if (IS_GEN2(dev)) {
9227 dev->mode_config.max_width = 2048;
9228 dev->mode_config.max_height = 2048;
9229 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9230 dev->mode_config.max_width = 4096;
9231 dev->mode_config.max_height = 4096;
79e53945 9232 } else {
a6c45cf0
CW		 9233 dev->mode_config.max_width = 8192;
9234 dev->mode_config.max_height = 8192;
79e53945 9235 }
5d4545ae 9236 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9237
28c97730 9238 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9239 INTEL_INFO(dev)->num_pipes,
9240 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9241
7eb552ae 9242 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9243 intel_crtc_init(dev, i);
7f1f3851
JB		 9244 for (j = 0; j < dev_priv->num_plane; j++) {
9245 ret = intel_plane_init(dev, i, j);
9246 if (ret)
06da8da2
VS		 9247 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9248 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9249 }
79e53945
JB		 9250 }
9251
79f689aa 9252 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9253 intel_pch_pll_init(dev);
9254
9cce37f4
JB		 9255 /* Just disable it once at startup */
9256 i915_disable_vga(dev);
79e53945 9257 intel_setup_outputs(dev);
11be49eb
CW		 9258
9259 /* Just in case the BIOS is doing something questionable. */
9260 intel_disable_fbc(dev);
2c7111db
CW		 9261}
9262
24929352
DV		 9263static void
9264intel_connector_break_all_links(struct intel_connector *connector)
9265{
9266 connector->base.dpms = DRM_MODE_DPMS_OFF;
9267 connector->base.encoder = NULL;
9268 connector->encoder->connectors_active = false;
9269 connector->encoder->base.crtc = NULL;
9270}
9271
7fad798e
DV		 9272static void intel_enable_pipe_a(struct drm_device *dev)
9273{
9274 struct intel_connector *connector;
9275 struct drm_connector *crt = NULL;
9276 struct intel_load_detect_pipe load_detect_temp;
9277
9278 /* We can't just switch on the pipe A, we need to set things up with a
9279 * proper mode and output configuration. As a gross hack, enable pipe A
9280 * by enabling the load detect pipe once. */
9281 list_for_each_entry(connector,
9282 &dev->mode_config.connector_list,
9283 base.head) {
9284 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9285 crt = &connector->base;
9286 break;
9287 }
9288 }
9289
9290 if (!crt)
9291 return;
9292
9293 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9294 intel_release_load_detect_pipe(crt, &load_detect_temp);
9295
652c393a 9296
7fad798e
DV		 9297}
9298
fa555837
DV		 9299static bool
9300intel_check_plane_mapping(struct intel_crtc *crtc)
9301{
7eb552ae
BW		 9302 struct drm_device *dev = crtc->base.dev;
9303 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9304 u32 reg, val;
9305
7eb552ae 9306 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9307 return true;
9308
9309 reg = DSPCNTR(!crtc->plane);
9310 val = I915_READ(reg);
9311
9312 if ((val & DISPLAY_PLANE_ENABLE) &&
9313 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9314 return false;
9315
9316 return true;
9317}
9318
24929352
DV		 9319static void intel_sanitize_crtc(struct intel_crtc *crtc)
9320{
9321 struct drm_device *dev = crtc->base.dev;
9322 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9323 u32 reg;
24929352 9324
24929352 9325 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9326 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9327 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9328
9329 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9330 * disable the crtc (and hence change the state) if it is wrong. Note
9331 * that gen4+ has a fixed plane -> pipe mapping. */
9332 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9333 struct intel_connector *connector;
9334 bool plane;
9335
24929352
DV		 9336 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9337 crtc->base.base.id);
9338
9339 /* Pipe has the wrong plane attached and the plane is active.
9340 * Temporarily change the plane mapping and disable everything
9341 * ... */
9342 plane = crtc->plane;
9343 crtc->plane = !plane;
9344 dev_priv->display.crtc_disable(&crtc->base);
9345 crtc->plane = plane;
9346
9347 /* ... and break all links. */
9348 list_for_each_entry(connector, &dev->mode_config.connector_list,
9349 base.head) {
9350 if (connector->encoder->base.crtc != &crtc->base)
9351 continue;
9352
9353 intel_connector_break_all_links(connector);
9354 }
9355
9356 WARN_ON(crtc->active);
9357 crtc->base.enabled = false;
9358 }
24929352 9359
7fad798e
DV		 9360 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9361 crtc->pipe == PIPE_A && !crtc->active) {
9362 /* BIOS forgot to enable pipe A, this mostly happens after
9363 * resume. Force-enable the pipe to fix this, the update_dpms
9364 * call below we restore the pipe to the right state, but leave
9365 * the required bits on. */
9366 intel_enable_pipe_a(dev);
9367 }
9368
24929352
DV		 9369 /* Adjust the state of the output pipe according to whether we
9370 * have active connectors/encoders. */
9371 intel_crtc_update_dpms(&crtc->base);
9372
9373 if (crtc->active != crtc->base.enabled) {
9374 struct intel_encoder *encoder;
9375
9376 /* This can happen either due to bugs in the get_hw_state
9377 * functions or because the pipe is force-enabled due to the
9378 * pipe A quirk. */
9379 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9380 crtc->base.base.id,
9381 crtc->base.enabled ? "enabled" : "disabled",
9382 crtc->active ? "enabled" : "disabled");
9383
9384 crtc->base.enabled = crtc->active;
9385
9386 /* Because we only establish the connector -> encoder ->
9387 * crtc links if something is active, this means the
9388 * crtc is now deactivated. Break the links. connector
9389 * -> encoder links are only establish when things are
9390 * actually up, hence no need to break them. */
9391 WARN_ON(crtc->active);
9392
9393 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9394 WARN_ON(encoder->connectors_active);
9395 encoder->base.crtc = NULL;
9396 }
9397 }
9398}
9399
9400static void intel_sanitize_encoder(struct intel_encoder *encoder)
9401{
9402 struct intel_connector *connector;
9403 struct drm_device *dev = encoder->base.dev;
9404
9405 /* We need to check both for a crtc link (meaning that the
9406 * encoder is active and trying to read from a pipe) and the
9407 * pipe itself being active. */
9408 bool has_active_crtc = encoder->base.crtc &&
9409 to_intel_crtc(encoder->base.crtc)->active;
9410
9411 if (encoder->connectors_active && !has_active_crtc) {
9412 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9413 encoder->base.base.id,
9414 drm_get_encoder_name(&encoder->base));
9415
9416 /* Connector is active, but has no active pipe. This is
9417 * fallout from our resume register restoring. Disable
9418 * the encoder manually again. */
9419 if (encoder->base.crtc) {
9420 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9421 encoder->base.base.id,
9422 drm_get_encoder_name(&encoder->base));
9423 encoder->disable(encoder);
9424 }
9425
9426 /* Inconsistent output/port/pipe state happens presumably due to
9427 * a bug in one of the get_hw_state functions. Or someplace else
9428 * in our code, like the register restore mess on resume. Clamp
9429 * things to off as a safer default. */
9430 list_for_each_entry(connector,
9431 &dev->mode_config.connector_list,
9432 base.head) {
9433 if (connector->encoder != encoder)
9434 continue;
9435
9436 intel_connector_break_all_links(connector);
9437 }
9438 }
9439 /* Enabled encoders without active connectors will be fixed in
9440 * the crtc fixup. */
9441}
9442
44cec740 9443void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9444{
9445 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9446 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9447
9448 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9449 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9450 i915_disable_vga(dev);
0fde901f
KM		 9451 }
9452}
9453
24929352
DV		 9454/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9455 * and i915 state tracking structures. */
45e2b5f6
DV		 9456void intel_modeset_setup_hw_state(struct drm_device *dev,
9457 bool force_restore)
24929352
DV		 9458{
9459 struct drm_i915_private *dev_priv = dev->dev_private;
9460 enum pipe pipe;
9461 u32 tmp;
b5644d05 9462 struct drm_plane *plane;
24929352
DV		 9463 struct intel_crtc *crtc;
9464 struct intel_encoder *encoder;
9465 struct intel_connector *connector;
9466
affa9354 9467 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9468 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9469
9470 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9471 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9472 case TRANS_DDI_EDP_INPUT_A_ON:
9473 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9474 pipe = PIPE_A;
9475 break;
9476 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9477 pipe = PIPE_B;
9478 break;
9479 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9480 pipe = PIPE_C;
9481 break;
aaa148ec
DL		 9482 default:
9483 /* A bogus value has been programmed, disable
9484 * the transcoder */
9485 WARN(1, "Bogus eDP source %08x\n", tmp);
9486 intel_ddi_disable_transcoder_func(dev_priv,
9487 TRANSCODER_EDP);
9488 goto setup_pipes;
e28d54cb
PZ		 9489 }
9490
9491 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3b117c8f 9492 crtc->config.cpu_transcoder = TRANSCODER_EDP;
e28d54cb
PZ		 9493
9494 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9495 pipe_name(pipe));
9496 }
9497 }
9498
aaa148ec 9499setup_pipes:
0e8ffe1b
DV		 9500 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9501 base.head) {
3b117c8f 9502 enum transcoder tmp = crtc->config.cpu_transcoder;
88adfff1 9503 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f
DV		 9504 crtc->config.cpu_transcoder = tmp;
9505
0e8ffe1b
DV		 9506 crtc->active = dev_priv->display.get_pipe_config(crtc,
9507 &crtc->config);
24929352
DV		 9508
9509 crtc->base.enabled = crtc->active;
9510
9511 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9512 crtc->base.base.id,
9513 crtc->active ? "enabled" : "disabled");
9514 }
9515
affa9354 9516 if (HAS_DDI(dev))
6441ab5f
PZ		 9517 intel_ddi_setup_hw_pll_state(dev);
9518
24929352
DV		 9519 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9520 base.head) {
9521 pipe = 0;
9522
9523 if (encoder->get_hw_state(encoder, &pipe)) {
9524 encoder->base.crtc =
9525 dev_priv->pipe_to_crtc_mapping[pipe];
9526 } else {
9527 encoder->base.crtc = NULL;
9528 }
9529
9530 encoder->connectors_active = false;
9531 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9532 encoder->base.base.id,
9533 drm_get_encoder_name(&encoder->base),
9534 encoder->base.crtc ? "enabled" : "disabled",
9535 pipe);
9536 }
9537
9538 list_for_each_entry(connector, &dev->mode_config.connector_list,
9539 base.head) {
9540 if (connector->get_hw_state(connector)) {
9541 connector->base.dpms = DRM_MODE_DPMS_ON;
9542 connector->encoder->connectors_active = true;
9543 connector->base.encoder = &connector->encoder->base;
9544 } else {
9545 connector->base.dpms = DRM_MODE_DPMS_OFF;
9546 connector->base.encoder = NULL;
9547 }
9548 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9549 connector->base.base.id,
9550 drm_get_connector_name(&connector->base),
9551 connector->base.encoder ? "enabled" : "disabled");
9552 }
9553
9554 /* HW state is read out, now we need to sanitize this mess. */
9555 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9556 base.head) {
9557 intel_sanitize_encoder(encoder);
9558 }
9559
9560 for_each_pipe(pipe) {
9561 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9562 intel_sanitize_crtc(crtc);
9563 }
9a935856 9564
45e2b5f6 9565 if (force_restore) {
f30da187
DV		 9566 /*
9567 * We need to use raw interfaces for restoring state to avoid
9568 * checking (bogus) intermediate states.
9569 */
45e2b5f6 9570 for_each_pipe(pipe) {
b5644d05
JB		 9571 struct drm_crtc *crtc =
9572 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9573
9574 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9575 crtc->fb);
45e2b5f6 9576 }
b5644d05
JB		 9577 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9578 intel_plane_restore(plane);
0fde901f
KM		 9579
9580 i915_redisable_vga(dev);
45e2b5f6
DV		 9581 } else {
9582 intel_modeset_update_staged_output_state(dev);
9583 }
8af6cf88
DV		 9584
9585 intel_modeset_check_state(dev);
2e938892
DV		 9586
9587 drm_mode_config_reset(dev);
2c7111db
CW		 9588}
9589
9590void intel_modeset_gem_init(struct drm_device *dev)
9591{
1833b134 9592 intel_modeset_init_hw(dev);
02e792fb
DV		 9593
9594 intel_setup_overlay(dev);
24929352 9595
45e2b5f6 9596 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9597}
9598
9599void intel_modeset_cleanup(struct drm_device *dev)
9600{
652c393a
JB		 9601 struct drm_i915_private *dev_priv = dev->dev_private;
9602 struct drm_crtc *crtc;
9603 struct intel_crtc *intel_crtc;
9604
fd0c0642
DV		 9605 /*
9606 * Interrupts and polling as the first thing to avoid creating havoc.
9607 * Too much stuff here (turning of rps, connectors, ...) would
9608 * experience fancy races otherwise.
9609 */
9610 drm_irq_uninstall(dev);
9611 cancel_work_sync(&dev_priv->hotplug_work);
9612 /*
9613 * Due to the hpd irq storm handling the hotplug work can re-arm the
9614 * poll handlers. Hence disable polling after hpd handling is shut down.
9615 */
f87ea761 9616 drm_kms_helper_poll_fini(dev);
fd0c0642 9617
652c393a
JB		 9618 mutex_lock(&dev->struct_mutex);
9619
723bfd70
JB		 9620 intel_unregister_dsm_handler();
9621
652c393a
JB		 9622 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9623 /* Skip inactive CRTCs */
9624 if (!crtc->fb)
9625 continue;
9626
9627 intel_crtc = to_intel_crtc(crtc);
3dec0095 9628 intel_increase_pllclock(crtc);
652c393a
JB		 9629 }
9630
973d04f9 9631 intel_disable_fbc(dev);
e70236a8 9632
8090c6b9 9633 intel_disable_gt_powersave(dev);
0cdab21f 9634
930ebb46
DV		 9635 ironlake_teardown_rc6(dev);
9636
69341a5e
KH		 9637 mutex_unlock(&dev->struct_mutex);
9638
1630fe75
CW		 9639 /* flush any delayed tasks or pending work */
9640 flush_scheduled_work();
9641
dc652f90
JN		 9642 /* destroy backlight, if any, before the connectors */
9643 intel_panel_destroy_backlight(dev);
9644
79e53945 9645 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9646
9647 intel_cleanup_overlay(dev);
79e53945
JB		 9648}
9649
f1c79df3
ZW		 9650/*
9651 * Return which encoder is currently attached for connector.
9652 */
df0e9248 9653struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9654{
df0e9248
CW		 9655 return &intel_attached_encoder(connector)->base;
9656}
f1c79df3 9657
df0e9248
CW		 9658void intel_connector_attach_encoder(struct intel_connector *connector,
9659 struct intel_encoder *encoder)
9660{
9661 connector->encoder = encoder;
9662 drm_mode_connector_attach_encoder(&connector->base,
9663 &encoder->base);
79e53945 9664}
28d52043
DA		 9665
9666/*
9667 * set vga decode state - true == enable VGA decode
9668 */
9669int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9670{
9671 struct drm_i915_private *dev_priv = dev->dev_private;
9672 u16 gmch_ctrl;
9673
9674 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9675 if (state)
9676 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9677 else
9678 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9679 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9680 return 0;
9681}
c4a1d9e4
CW		 9682
9683#ifdef CONFIG_DEBUG_FS
9684#include <linux/seq_file.h>
9685
9686struct intel_display_error_state {
ff57f1b0
PZ		 9687
9688 u32 power_well_driver;
9689
c4a1d9e4
CW		 9690 struct intel_cursor_error_state {
9691 u32 control;
9692 u32 position;
9693 u32 base;
9694 u32 size;
52331309 9695 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9696
9697 struct intel_pipe_error_state {
ff57f1b0 9698 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9699 u32 conf;
9700 u32 source;
9701
9702 u32 htotal;
9703 u32 hblank;
9704 u32 hsync;
9705 u32 vtotal;
9706 u32 vblank;
9707 u32 vsync;
52331309 9708 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9709
9710 struct intel_plane_error_state {
9711 u32 control;
9712 u32 stride;
9713 u32 size;
9714 u32 pos;
9715 u32 addr;
9716 u32 surface;
9717 u32 tile_offset;
52331309 9718 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9719};
9720
9721struct intel_display_error_state *
9722intel_display_capture_error_state(struct drm_device *dev)
9723{
0206e353 9724 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9725 struct intel_display_error_state *error;
702e7a56 9726 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9727 int i;
9728
9729 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9730 if (error == NULL)
9731 return NULL;
9732
ff57f1b0
PZ		 9733 if (HAS_POWER_WELL(dev))
9734 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9735
52331309 9736 for_each_pipe(i) {
702e7a56 9737 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 9738 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 9739
a18c4c3d
PZ		 9740 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9741 error->cursor[i].control = I915_READ(CURCNTR(i));
9742 error->cursor[i].position = I915_READ(CURPOS(i));
9743 error->cursor[i].base = I915_READ(CURBASE(i));
9744 } else {
9745 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9746 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9747 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9748 }
c4a1d9e4
CW		 9749
9750 error->plane[i].control = I915_READ(DSPCNTR(i));
9751 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9752 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9753 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9754 error->plane[i].pos = I915_READ(DSPPOS(i));
9755 }
ca291363
PZ		 9756 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9757 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9758 if (INTEL_INFO(dev)->gen >= 4) {
9759 error->plane[i].surface = I915_READ(DSPSURF(i));
9760 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9761 }
9762
702e7a56 9763 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9764 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9765 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9766 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9767 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9768 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9769 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9770 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9771 }
9772
12d217c7
PZ		 9773 /* In the code above we read the registers without checking if the power
9774 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9775 * prevent the next I915_WRITE from detecting it and printing an error
9776 * message. */
9777 if (HAS_POWER_WELL(dev))
9778 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9779
c4a1d9e4
CW		 9780 return error;
9781}
9782
9783void
9784intel_display_print_error_state(struct seq_file *m,
9785 struct drm_device *dev,
9786 struct intel_display_error_state *error)
9787{
9788 int i;
9789
7eb552ae 9790 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0
PZ		 9791 if (HAS_POWER_WELL(dev))
9792 seq_printf(m, "PWR_WELL_CTL2: %08x\n",
9793 error->power_well_driver);
52331309 9794 for_each_pipe(i) {
c4a1d9e4 9795 seq_printf(m, "Pipe [%d]:\n", i);
ff57f1b0
PZ		 9796 seq_printf(m, " CPU transcoder: %c\n",
9797 transcoder_name(error->pipe[i].cpu_transcoder));
c4a1d9e4
CW		 9798 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9799 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9800 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9801 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9802 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9803 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9804 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9805 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9806
9807 seq_printf(m, "Plane [%d]:\n", i);
9808 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9809 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9810 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9811 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9812 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9813 }
4b71a570 9814 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9815 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9816 if (INTEL_INFO(dev)->gen >= 4) {
9817 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9818 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9819 }
9820
9821 seq_printf(m, "Cursor [%d]:\n", i);
9822 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9823 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9824 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9825 }
9826}
9827#endif
Linux kernel - Deliverables
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