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drm/i915: Simplify DP vs. eDP detection
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
3dec0095 44static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 45static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 46
f1f644dc
JB		 47static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
18442d08
VS		 49static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
f1f644dc 51
e7457a9a
DL		 52static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
79e53945 56typedef struct {
0206e353 57 int min, max;
79e53945
JB		 58} intel_range_t;
59
60typedef struct {
0206e353
AJ		 61 int dot_limit;
62 int p2_slow, p2_fast;
79e53945
JB		 63} intel_p2_t;
64
d4906093
ML		 65typedef struct intel_limit intel_limit_t;
66struct intel_limit {
0206e353
AJ		 67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
d4906093 69};
79e53945 70
d2acd215
DV		 71int
72intel_pch_rawclk(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79}
80
021357ac
CW		 81static inline u32 /* units of 100MHz */
82intel_fdi_link_freq(struct drm_device *dev)
83{
8b99e68c
CW		 84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
021357ac
CW		 89}
90
5d536e28 91static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 102};
103
5d536e28
DV		 104static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115};
116
e4b36699 117static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
e4b36699 128};
273e27ca 129
e4b36699 130static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 141};
142
143static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 154};
155
273e27ca 156
e4b36699 157static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
044c7c41 169 },
e4b36699
KP		 170};
171
172static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
044c7c41 196 },
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
044c7c41 210 },
e4b36699
KP		 211};
212
f2b115e6 213static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 216 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
273e27ca 219 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 226};
227
f2b115e6 228static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 239};
240
273e27ca
EA		 241/* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
b91ad0ec 246static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 257};
258
b91ad0ec 259static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 270};
271
272static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 283};
284
273e27ca 285/* LVDS 100mhz refclk limits. */
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
0206e353 294 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
0206e353 307 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 310};
311
dc730512 312static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 313 /*
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
318 */
319 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 320 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 321 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 322 .m1 = { .min = 2, .max = 3 },
323 .m2 = { .min = 11, .max = 156 },
b99ab663 324 .p1 = { .min = 2, .max = 3 },
5fdc9c49 325 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 326};
327
6b4bf1c4
VS		 328static void vlv_clock(int refclk, intel_clock_t *clock)
329{
330 clock->m = clock->m1 * clock->m2;
331 clock->p = clock->p1 * clock->p2;
fb03ac01
VS		 332 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
333 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 334}
335
e0638cdf
PZ		 336/**
337 * Returns whether any output on the specified pipe is of the specified type
338 */
339static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
340{
341 struct drm_device *dev = crtc->dev;
342 struct intel_encoder *encoder;
343
344 for_each_encoder_on_crtc(dev, crtc, encoder)
345 if (encoder->type == type)
346 return true;
347
348 return false;
349}
350
1b894b59
CW		 351static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
352 int refclk)
2c07245f 353{
b91ad0ec 354 struct drm_device *dev = crtc->dev;
2c07245f 355 const intel_limit_t *limit;
b91ad0ec
ZW		 356
357 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 358 if (intel_is_dual_link_lvds(dev)) {
1b894b59 359 if (refclk == 100000)
b91ad0ec
ZW		 360 limit = &intel_limits_ironlake_dual_lvds_100m;
361 else
362 limit = &intel_limits_ironlake_dual_lvds;
363 } else {
1b894b59 364 if (refclk == 100000)
b91ad0ec
ZW		 365 limit = &intel_limits_ironlake_single_lvds_100m;
366 else
367 limit = &intel_limits_ironlake_single_lvds;
368 }
c6bb3538 369 } else
b91ad0ec 370 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 371
372 return limit;
373}
374
044c7c41
ML		 375static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
376{
377 struct drm_device *dev = crtc->dev;
044c7c41
ML		 378 const intel_limit_t *limit;
379
380 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 381 if (intel_is_dual_link_lvds(dev))
e4b36699 382 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 383 else
e4b36699 384 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 385 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
386 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 387 limit = &intel_limits_g4x_hdmi;
044c7c41 388 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 389 limit = &intel_limits_g4x_sdvo;
044c7c41 390 } else /* The option is for other outputs */
e4b36699 391 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 392
393 return limit;
394}
395
1b894b59 396static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 397{
398 struct drm_device *dev = crtc->dev;
399 const intel_limit_t *limit;
400
bad720ff 401 if (HAS_PCH_SPLIT(dev))
1b894b59 402 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 403 else if (IS_G4X(dev)) {
044c7c41 404 limit = intel_g4x_limit(crtc);
f2b115e6 405 } else if (IS_PINEVIEW(dev)) {
2177832f 406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 407 limit = &intel_limits_pineview_lvds;
2177832f 408 else
f2b115e6 409 limit = &intel_limits_pineview_sdvo;
a0c4da24 410 } else if (IS_VALLEYVIEW(dev)) {
dc730512 411 limit = &intel_limits_vlv;
a6c45cf0
CW		 412 } else if (!IS_GEN2(dev)) {
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
414 limit = &intel_limits_i9xx_lvds;
415 else
416 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 417 } else {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 419 limit = &intel_limits_i8xx_lvds;
5d536e28 420 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 421 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 422 else
423 limit = &intel_limits_i8xx_dac;
79e53945
JB		 424 }
425 return limit;
426}
427
f2b115e6
AJ		 428/* m1 is reserved as 0 in Pineview, n is a ring counter */
429static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 430{
2177832f
SL		 431 clock->m = clock->m2 + 2;
432 clock->p = clock->p1 * clock->p2;
fb03ac01
VS		 433 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
434 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 435}
436
7429e9d4
DV		 437static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
438{
439 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
440}
441
ac58c3f0 442static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 443{
7429e9d4 444 clock->m = i9xx_dpll_compute_m(clock);
79e53945 445 clock->p = clock->p1 * clock->p2;
fb03ac01
VS		 446 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
447 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 448}
449
7c04d1d9 450#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 451/**
452 * Returns whether the given set of divisors are valid for a given refclk with
453 * the given connectors.
454 */
455
1b894b59
CW		 456static bool intel_PLL_is_valid(struct drm_device *dev,
457 const intel_limit_t *limit,
458 const intel_clock_t *clock)
79e53945 459{
f01b7962
VS		 460 if (clock->n < limit->n.min || limit->n.max < clock->n)
461 INTELPllInvalid("n out of range\n");
79e53945 462 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 463 INTELPllInvalid("p1 out of range\n");
79e53945 464 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 465 INTELPllInvalid("m2 out of range\n");
79e53945 466 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 467 INTELPllInvalid("m1 out of range\n");
f01b7962
VS		 468
469 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
470 if (clock->m1 <= clock->m2)
471 INTELPllInvalid("m1 <= m2\n");
472
473 if (!IS_VALLEYVIEW(dev)) {
474 if (clock->p < limit->p.min || limit->p.max < clock->p)
475 INTELPllInvalid("p out of range\n");
476 if (clock->m < limit->m.min || limit->m.max < clock->m)
477 INTELPllInvalid("m out of range\n");
478 }
479
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24 672{
f01b7962 673 struct drm_device *dev = crtc->dev;
6b4bf1c4 674 intel_clock_t clock;
69e4f900 675 unsigned int bestppm = 1000000;
27e639bf
VS		 676 /* min update 19.2 MHz */
677 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 678 bool found = false;
a0c4da24 679
6b4bf1c4
VS		 680 target *= 5; /* fast clock */
681
682 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 683
684 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 685 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 686 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 687 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 688 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 689 clock.p = clock.p1 * clock.p2;
a0c4da24 690 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
69e4f900
VS		 692 unsigned int ppm, diff;
693
6b4bf1c4
VS		 694 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
695 refclk * clock.m1);
696
697 vlv_clock(refclk, &clock);
43b0ac53 698
f01b7962
VS		 699 if (!intel_PLL_is_valid(dev, limit,
700 &clock))
43b0ac53
VS		 701 continue;
702
6b4bf1c4
VS		 703 diff = abs(clock.dot - target);
704 ppm = div_u64(1000000ULL * diff, target);
705
706 if (ppm < 100 && clock.p > best_clock->p) {
43b0ac53 707 bestppm = 0;
6b4bf1c4 708 *best_clock = clock;
49e497ef 709 found = true;
43b0ac53 710 }
6b4bf1c4 711
c686122c 712 if (bestppm >= 10 && ppm < bestppm - 10) {
69e4f900 713 bestppm = ppm;
6b4bf1c4 714 *best_clock = clock;
49e497ef 715 found = true;
a0c4da24
JB		 716 }
717 }
718 }
719 }
720 }
a0c4da24 721
49e497ef 722 return found;
a0c4da24 723}
a4fc5ed6 724
20ddf665
VS		 725bool intel_crtc_active(struct drm_crtc *crtc)
726{
727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
728
729 /* Be paranoid as we can arrive here with only partial
730 * state retrieved from the hardware during setup.
731 *
241bfc38 732 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 733 * as Haswell has gained clock readout/fastboot support.
734 *
735 * We can ditch the crtc->fb check as soon as we can
736 * properly reconstruct framebuffers.
737 */
738 return intel_crtc->active && crtc->fb &&
241bfc38 739 intel_crtc->config.adjusted_mode.crtc_clock;
20ddf665
VS		 740}
741
a5c961d1
PZ		 742enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
743 enum pipe pipe)
744{
745 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
747
3b117c8f 748 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 749}
750
a928d536
PZ		 751static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
752{
753 struct drm_i915_private *dev_priv = dev->dev_private;
754 u32 frame, frame_reg = PIPEFRAME(pipe);
755
756 frame = I915_READ(frame_reg);
757
758 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
759 DRM_DEBUG_KMS("vblank wait timed out\n");
760}
761
9d0498a2
JB		 762/**
763 * intel_wait_for_vblank - wait for vblank on a given pipe
764 * @dev: drm device
765 * @pipe: pipe to wait for
766 *
767 * Wait for vblank to occur on a given pipe. Needed for various bits of
768 * mode setting code.
769 */
770void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 771{
9d0498a2 772 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 773 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 774
a928d536
PZ		 775 if (INTEL_INFO(dev)->gen >= 5) {
776 ironlake_wait_for_vblank(dev, pipe);
777 return;
778 }
779
300387c0
CW		 780 /* Clear existing vblank status. Note this will clear any other
781 * sticky status fields as well.
782 *
783 * This races with i915_driver_irq_handler() with the result
784 * that either function could miss a vblank event. Here it is not
785 * fatal, as we will either wait upon the next vblank interrupt or
786 * timeout. Generally speaking intel_wait_for_vblank() is only
787 * called during modeset at which time the GPU should be idle and
788 * should *not* be performing page flips and thus not waiting on
789 * vblanks...
790 * Currently, the result of us stealing a vblank from the irq
791 * handler is that a single frame will be skipped during swapbuffers.
792 */
793 I915_WRITE(pipestat_reg,
794 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
795
9d0498a2 796 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 797 if (wait_for(I915_READ(pipestat_reg) &
798 PIPE_VBLANK_INTERRUPT_STATUS,
799 50))
9d0498a2
JB		 800 DRM_DEBUG_KMS("vblank wait timed out\n");
801}
802
fbf49ea2
VS		 803static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
804{
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 u32 reg = PIPEDSL(pipe);
807 u32 line1, line2;
808 u32 line_mask;
809
810 if (IS_GEN2(dev))
811 line_mask = DSL_LINEMASK_GEN2;
812 else
813 line_mask = DSL_LINEMASK_GEN3;
814
815 line1 = I915_READ(reg) & line_mask;
816 mdelay(5);
817 line2 = I915_READ(reg) & line_mask;
818
819 return line1 == line2;
820}
821
ab7ad7f6
KP		 822/*
823 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 824 * @dev: drm device
825 * @pipe: pipe to wait for
826 *
827 * After disabling a pipe, we can't wait for vblank in the usual way,
828 * spinning on the vblank interrupt status bit, since we won't actually
829 * see an interrupt when the pipe is disabled.
830 *
ab7ad7f6
KP		 831 * On Gen4 and above:
832 * wait for the pipe register state bit to turn off
833 *
834 * Otherwise:
835 * wait for the display line value to settle (it usually
836 * ends up stopping at the start of the next frame).
58e10eb9 837 *
9d0498a2 838 */
58e10eb9 839void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 840{
841 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 842 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
843 pipe);
ab7ad7f6
KP		 844
845 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 846 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 847
848 /* Wait for the Pipe State to go off */
58e10eb9
CW		 849 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
850 100))
284637d9 851 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 852 } else {
ab7ad7f6 853 /* Wait for the display line to settle */
fbf49ea2 854 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 855 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 856 }
79e53945
JB		 857}
858
b0ea7d37
DL		 859/*
860 * ibx_digital_port_connected - is the specified port connected?
861 * @dev_priv: i915 private structure
862 * @port: the port to test
863 *
864 * Returns true if @port is connected, false otherwise.
865 */
866bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
867 struct intel_digital_port *port)
868{
869 u32 bit;
870
c36346e3
DL		 871 if (HAS_PCH_IBX(dev_priv->dev)) {
872 switch(port->port) {
873 case PORT_B:
874 bit = SDE_PORTB_HOTPLUG;
875 break;
876 case PORT_C:
877 bit = SDE_PORTC_HOTPLUG;
878 break;
879 case PORT_D:
880 bit = SDE_PORTD_HOTPLUG;
881 break;
882 default:
883 return true;
884 }
885 } else {
886 switch(port->port) {
887 case PORT_B:
888 bit = SDE_PORTB_HOTPLUG_CPT;
889 break;
890 case PORT_C:
891 bit = SDE_PORTC_HOTPLUG_CPT;
892 break;
893 case PORT_D:
894 bit = SDE_PORTD_HOTPLUG_CPT;
895 break;
896 default:
897 return true;
898 }
b0ea7d37
DL		 899 }
900
901 return I915_READ(SDEISR) & bit;
902}
903
b24e7179
JB		 904static const char *state_string(bool enabled)
905{
906 return enabled ? "on" : "off";
907}
908
909/* Only for pre-ILK configs */
55607e8a
DV		 910void assert_pll(struct drm_i915_private *dev_priv,
911 enum pipe pipe, bool state)
b24e7179
JB		 912{
913 int reg;
914 u32 val;
915 bool cur_state;
916
917 reg = DPLL(pipe);
918 val = I915_READ(reg);
919 cur_state = !!(val & DPLL_VCO_ENABLE);
920 WARN(cur_state != state,
921 "PLL state assertion failure (expected %s, current %s)\n",
922 state_string(state), state_string(cur_state));
923}
b24e7179 924
23538ef1
JN		 925/* XXX: the dsi pll is shared between MIPI DSI ports */
926static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
927{
928 u32 val;
929 bool cur_state;
930
931 mutex_lock(&dev_priv->dpio_lock);
932 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
933 mutex_unlock(&dev_priv->dpio_lock);
934
935 cur_state = val & DSI_PLL_VCO_EN;
936 WARN(cur_state != state,
937 "DSI PLL state assertion failure (expected %s, current %s)\n",
938 state_string(state), state_string(cur_state));
939}
940#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
941#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
942
55607e8a 943struct intel_shared_dpll *
e2b78267
DV		 944intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
945{
946 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
947
a43f6e0f 948 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 949 return NULL;
950
a43f6e0f 951 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 952}
953
040484af 954/* For ILK+ */
55607e8a
DV		 955void assert_shared_dpll(struct drm_i915_private *dev_priv,
956 struct intel_shared_dpll *pll,
957 bool state)
040484af 958{
040484af 959 bool cur_state;
5358901f 960 struct intel_dpll_hw_state hw_state;
040484af 961
9d82aa17
ED		 962 if (HAS_PCH_LPT(dev_priv->dev)) {
963 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
964 return;
965 }
966
92b27b08 967 if (WARN (!pll,
46edb027 968 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 969 return;
ee7b9f93 970
5358901f 971 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 972 WARN(cur_state != state,
5358901f
DV		 973 "%s assertion failure (expected %s, current %s)\n",
974 pll->name, state_string(state), state_string(cur_state));
040484af 975}
040484af
JB		 976
977static void assert_fdi_tx(struct drm_i915_private *dev_priv,
978 enum pipe pipe, bool state)
979{
980 int reg;
981 u32 val;
982 bool cur_state;
ad80a810
PZ		 983 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
984 pipe);
040484af 985
affa9354
PZ		 986 if (HAS_DDI(dev_priv->dev)) {
987 /* DDI does not have a specific FDI_TX register */
ad80a810 988 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 989 val = I915_READ(reg);
ad80a810 990 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 991 } else {
992 reg = FDI_TX_CTL(pipe);
993 val = I915_READ(reg);
994 cur_state = !!(val & FDI_TX_ENABLE);
995 }
040484af
JB		 996 WARN(cur_state != state,
997 "FDI TX state assertion failure (expected %s, current %s)\n",
998 state_string(state), state_string(cur_state));
999}
1000#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1001#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1002
1003static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1004 enum pipe pipe, bool state)
1005{
1006 int reg;
1007 u32 val;
1008 bool cur_state;
1009
d63fa0dc
PZ		 1010 reg = FDI_RX_CTL(pipe);
1011 val = I915_READ(reg);
1012 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1013 WARN(cur_state != state,
1014 "FDI RX state assertion failure (expected %s, current %s)\n",
1015 state_string(state), state_string(cur_state));
1016}
1017#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1018#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1019
1020static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1021 enum pipe pipe)
1022{
1023 int reg;
1024 u32 val;
1025
1026 /* ILK FDI PLL is always enabled */
1027 if (dev_priv->info->gen == 5)
1028 return;
1029
bf507ef7 1030 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1031 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1032 return;
1033
040484af
JB		 1034 reg = FDI_TX_CTL(pipe);
1035 val = I915_READ(reg);
1036 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1037}
1038
55607e8a
DV		 1039void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1040 enum pipe pipe, bool state)
040484af
JB		 1041{
1042 int reg;
1043 u32 val;
55607e8a 1044 bool cur_state;
040484af
JB		 1045
1046 reg = FDI_RX_CTL(pipe);
1047 val = I915_READ(reg);
55607e8a
DV		 1048 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1049 WARN(cur_state != state,
1050 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1051 state_string(state), state_string(cur_state));
040484af
JB		 1052}
1053
ea0760cf
JB		 1054static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1055 enum pipe pipe)
1056{
1057 int pp_reg, lvds_reg;
1058 u32 val;
1059 enum pipe panel_pipe = PIPE_A;
0de3b485 1060 bool locked = true;
ea0760cf
JB		 1061
1062 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1063 pp_reg = PCH_PP_CONTROL;
1064 lvds_reg = PCH_LVDS;
1065 } else {
1066 pp_reg = PP_CONTROL;
1067 lvds_reg = LVDS;
1068 }
1069
1070 val = I915_READ(pp_reg);
1071 if (!(val & PANEL_POWER_ON) ||
1072 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1073 locked = false;
1074
1075 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1076 panel_pipe = PIPE_B;
1077
1078 WARN(panel_pipe == pipe && locked,
1079 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1080 pipe_name(pipe));
ea0760cf
JB		 1081}
1082
93ce0ba6
JN		 1083static void assert_cursor(struct drm_i915_private *dev_priv,
1084 enum pipe pipe, bool state)
1085{
1086 struct drm_device *dev = dev_priv->dev;
1087 bool cur_state;
1088
1089 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1090 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1091 else if (IS_845G(dev) || IS_I865G(dev))
1092 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1093 else
1094 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1095
1096 WARN(cur_state != state,
1097 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1098 pipe_name(pipe), state_string(state), state_string(cur_state));
1099}
1100#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1101#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1102
b840d907
JB		 1103void assert_pipe(struct drm_i915_private *dev_priv,
1104 enum pipe pipe, bool state)
b24e7179
JB		 1105{
1106 int reg;
1107 u32 val;
63d7bbe9 1108 bool cur_state;
702e7a56
PZ		 1109 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1110 pipe);
b24e7179 1111
8e636784
DV		 1112 /* if we need the pipe A quirk it must be always on */
1113 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1114 state = true;
1115
b97186f0
PZ		 1116 if (!intel_display_power_enabled(dev_priv->dev,
1117 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1118 cur_state = false;
1119 } else {
1120 reg = PIPECONF(cpu_transcoder);
1121 val = I915_READ(reg);
1122 cur_state = !!(val & PIPECONF_ENABLE);
1123 }
1124
63d7bbe9
JB		 1125 WARN(cur_state != state,
1126 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1127 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1128}
1129
931872fc
CW		 1130static void assert_plane(struct drm_i915_private *dev_priv,
1131 enum plane plane, bool state)
b24e7179
JB		 1132{
1133 int reg;
1134 u32 val;
931872fc 1135 bool cur_state;
b24e7179
JB		 1136
1137 reg = DSPCNTR(plane);
1138 val = I915_READ(reg);
931872fc
CW		 1139 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1140 WARN(cur_state != state,
1141 "plane %c assertion failure (expected %s, current %s)\n",
1142 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1143}
1144
931872fc
CW		 1145#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1146#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1147
b24e7179
JB		 1148static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1149 enum pipe pipe)
1150{
653e1026 1151 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1152 int reg, i;
1153 u32 val;
1154 int cur_pipe;
1155
653e1026
VS		 1156 /* Primary planes are fixed to pipes on gen4+ */
1157 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1158 reg = DSPCNTR(pipe);
1159 val = I915_READ(reg);
1160 WARN((val & DISPLAY_PLANE_ENABLE),
1161 "plane %c assertion failure, should be disabled but not\n",
1162 plane_name(pipe));
19ec1358 1163 return;
28c05794 1164 }
19ec1358 1165
b24e7179 1166 /* Need to check both planes against the pipe */
08e2a7de 1167 for_each_pipe(i) {
b24e7179
JB		 1168 reg = DSPCNTR(i);
1169 val = I915_READ(reg);
1170 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1171 DISPPLANE_SEL_PIPE_SHIFT;
1172 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1173 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1174 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1175 }
1176}
1177
19332d7a
JB		 1178static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1179 enum pipe pipe)
1180{
20674eef 1181 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1182 int reg, i;
1183 u32 val;
1184
20674eef
VS		 1185 if (IS_VALLEYVIEW(dev)) {
1186 for (i = 0; i < dev_priv->num_plane; i++) {
1187 reg = SPCNTR(pipe, i);
1188 val = I915_READ(reg);
1189 WARN((val & SP_ENABLE),
1190 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1191 sprite_name(pipe, i), pipe_name(pipe));
1192 }
1193 } else if (INTEL_INFO(dev)->gen >= 7) {
1194 reg = SPRCTL(pipe);
19332d7a 1195 val = I915_READ(reg);
20674eef 1196 WARN((val & SPRITE_ENABLE),
06da8da2 1197 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1198 plane_name(pipe), pipe_name(pipe));
1199 } else if (INTEL_INFO(dev)->gen >= 5) {
1200 reg = DVSCNTR(pipe);
19332d7a 1201 val = I915_READ(reg);
20674eef 1202 WARN((val & DVS_ENABLE),
06da8da2 1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1204 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1205 }
1206}
1207
92f2584a
JB		 1208static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1209{
1210 u32 val;
1211 bool enabled;
1212
9d82aa17
ED		 1213 if (HAS_PCH_LPT(dev_priv->dev)) {
1214 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1215 return;
1216 }
1217
92f2584a
JB		 1218 val = I915_READ(PCH_DREF_CONTROL);
1219 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1220 DREF_SUPERSPREAD_SOURCE_MASK));
1221 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1222}
1223
ab9412ba
DV		 1224static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe)
92f2584a
JB		 1226{
1227 int reg;
1228 u32 val;
1229 bool enabled;
1230
ab9412ba 1231 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1232 val = I915_READ(reg);
1233 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1234 WARN(enabled,
1235 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1236 pipe_name(pipe));
92f2584a
JB		 1237}
1238
4e634389
KP		 1239static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1241{
1242 if ((val & DP_PORT_EN) == 0)
1243 return false;
1244
1245 if (HAS_PCH_CPT(dev_priv->dev)) {
1246 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1247 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1248 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1249 return false;
1250 } else {
1251 if ((val & DP_PIPE_MASK) != (pipe << 30))
1252 return false;
1253 }
1254 return true;
1255}
1256
1519b995
KP		 1257static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1258 enum pipe pipe, u32 val)
1259{
dc0fa718 1260 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1261 return false;
1262
1263 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1264 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1265 return false;
1266 } else {
dc0fa718 1267 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1268 return false;
1269 }
1270 return true;
1271}
1272
1273static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1274 enum pipe pipe, u32 val)
1275{
1276 if ((val & LVDS_PORT_EN) == 0)
1277 return false;
1278
1279 if (HAS_PCH_CPT(dev_priv->dev)) {
1280 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281 return false;
1282 } else {
1283 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1284 return false;
1285 }
1286 return true;
1287}
1288
1289static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1290 enum pipe pipe, u32 val)
1291{
1292 if ((val & ADPA_DAC_ENABLE) == 0)
1293 return false;
1294 if (HAS_PCH_CPT(dev_priv->dev)) {
1295 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1296 return false;
1297 } else {
1298 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1299 return false;
1300 }
1301 return true;
1302}
1303
291906f1 1304static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1305 enum pipe pipe, int reg, u32 port_sel)
291906f1 1306{
47a05eca 1307 u32 val = I915_READ(reg);
4e634389 1308 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1309 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1310 reg, pipe_name(pipe));
de9a35ab 1311
75c5da27
DV		 1312 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1313 && (val & DP_PIPEB_SELECT),
de9a35ab 1314 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1315}
1316
1317static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, int reg)
1319{
47a05eca 1320 u32 val = I915_READ(reg);
b70ad586 1321 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1322 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1323 reg, pipe_name(pipe));
de9a35ab 1324
dc0fa718 1325 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1326 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1327 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1328}
1329
1330static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1331 enum pipe pipe)
1332{
1333 int reg;
1334 u32 val;
291906f1 1335
f0575e92
KP		 1336 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1337 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1338 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1339
1340 reg = PCH_ADPA;
1341 val = I915_READ(reg);
b70ad586 1342 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1343 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1344 pipe_name(pipe));
291906f1
JB		 1345
1346 reg = PCH_LVDS;
1347 val = I915_READ(reg);
b70ad586 1348 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1349 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1350 pipe_name(pipe));
291906f1 1351
e2debe91
PZ		 1352 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1353 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1354 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1355}
1356
40e9cf64
JB		 1357static void intel_init_dpio(struct drm_device *dev)
1358{
1359 struct drm_i915_private *dev_priv = dev->dev_private;
1360
1361 if (!IS_VALLEYVIEW(dev))
1362 return;
1363
1364 /*
1365 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1366 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1367 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1368 * b. The other bits such as sfr settings / modesel may all be set
1369 * to 0.
1370 *
1371 * This should only be done on init and resume from S3 with both
1372 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1373 */
1374 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1375}
1376
426115cf 1377static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1378{
426115cf
DV		 1379 struct drm_device *dev = crtc->base.dev;
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 int reg = DPLL(crtc->pipe);
1382 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1383
426115cf 1384 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1385
1386 /* No really, not for ILK+ */
1387 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1388
1389 /* PLL is protected by panel, make sure we can write it */
1390 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1391 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1392
426115cf
DV		 1393 I915_WRITE(reg, dpll);
1394 POSTING_READ(reg);
1395 udelay(150);
1396
1397 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1398 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1399
1400 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1401 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1402
1403 /* We do this three times for luck */
426115cf 1404 I915_WRITE(reg, dpll);
87442f73
DV		 1405 POSTING_READ(reg);
1406 udelay(150); /* wait for warmup */
426115cf 1407 I915_WRITE(reg, dpll);
87442f73
DV		 1408 POSTING_READ(reg);
1409 udelay(150); /* wait for warmup */
426115cf 1410 I915_WRITE(reg, dpll);
87442f73
DV		 1411 POSTING_READ(reg);
1412 udelay(150); /* wait for warmup */
1413}
1414
66e3d5c0 1415static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1416{
66e3d5c0
DV		 1417 struct drm_device *dev = crtc->base.dev;
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1419 int reg = DPLL(crtc->pipe);
1420 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1421
66e3d5c0 1422 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1423
63d7bbe9 1424 /* No really, not for ILK+ */
87442f73 1425 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1426
1427 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1428 if (IS_MOBILE(dev) && !IS_I830(dev))
1429 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1430
66e3d5c0
DV		 1431 I915_WRITE(reg, dpll);
1432
1433 /* Wait for the clocks to stabilize. */
1434 POSTING_READ(reg);
1435 udelay(150);
1436
1437 if (INTEL_INFO(dev)->gen >= 4) {
1438 I915_WRITE(DPLL_MD(crtc->pipe),
1439 crtc->config.dpll_hw_state.dpll_md);
1440 } else {
1441 /* The pixel multiplier can only be updated once the
1442 * DPLL is enabled and the clocks are stable.
1443 *
1444 * So write it again.
1445 */
1446 I915_WRITE(reg, dpll);
1447 }
63d7bbe9
JB		 1448
1449 /* We do this three times for luck */
66e3d5c0 1450 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1451 POSTING_READ(reg);
1452 udelay(150); /* wait for warmup */
66e3d5c0 1453 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1454 POSTING_READ(reg);
1455 udelay(150); /* wait for warmup */
66e3d5c0 1456 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1457 POSTING_READ(reg);
1458 udelay(150); /* wait for warmup */
1459}
1460
1461/**
50b44a44 1462 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1463 * @dev_priv: i915 private structure
1464 * @pipe: pipe PLL to disable
1465 *
1466 * Disable the PLL for @pipe, making sure the pipe is off first.
1467 *
1468 * Note! This is for pre-ILK only.
1469 */
50b44a44 1470static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1471{
63d7bbe9
JB		 1472 /* Don't disable pipe A or pipe A PLLs if needed */
1473 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1474 return;
1475
1476 /* Make sure the pipe isn't still relying on us */
1477 assert_pipe_disabled(dev_priv, pipe);
1478
50b44a44
DV		 1479 I915_WRITE(DPLL(pipe), 0);
1480 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1481}
1482
f6071166
JB		 1483static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1484{
1485 u32 val = 0;
1486
1487 /* Make sure the pipe isn't still relying on us */
1488 assert_pipe_disabled(dev_priv, pipe);
1489
1490 /* Leave integrated clock source enabled */
1491 if (pipe == PIPE_B)
1492 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1493 I915_WRITE(DPLL(pipe), val);
1494 POSTING_READ(DPLL(pipe));
1495}
1496
89b667f8
JB		 1497void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1498{
1499 u32 port_mask;
1500
1501 if (!port)
1502 port_mask = DPLL_PORTB_READY_MASK;
1503 else
1504 port_mask = DPLL_PORTC_READY_MASK;
1505
1506 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1507 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1508 'B' + port, I915_READ(DPLL(0)));
1509}
1510
92f2584a 1511/**
e72f9fbf 1512 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1513 * @dev_priv: i915 private structure
1514 * @pipe: pipe PLL to enable
1515 *
1516 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1517 * drives the transcoder clock.
1518 */
e2b78267 1519static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1520{
e2b78267
DV		 1521 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1522 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1523
48da64a8 1524 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1525 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1526 if (WARN_ON(pll == NULL))
48da64a8
CW		 1527 return;
1528
1529 if (WARN_ON(pll->refcount == 0))
1530 return;
ee7b9f93 1531
46edb027
DV		 1532 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1533 pll->name, pll->active, pll->on,
e2b78267 1534 crtc->base.base.id);
92f2584a 1535
cdbd2316
DV		 1536 if (pll->active++) {
1537 WARN_ON(!pll->on);
e9d6944e 1538 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1539 return;
1540 }
f4a091c7 1541 WARN_ON(pll->on);
ee7b9f93 1542
46edb027 1543 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1544 pll->enable(dev_priv, pll);
ee7b9f93 1545 pll->on = true;
92f2584a
JB		 1546}
1547
e2b78267 1548static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1549{
e2b78267
DV		 1550 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1551 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1552
92f2584a
JB		 1553 /* PCH only available on ILK+ */
1554 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1555 if (WARN_ON(pll == NULL))
ee7b9f93 1556 return;
92f2584a 1557
48da64a8
CW		 1558 if (WARN_ON(pll->refcount == 0))
1559 return;
7a419866 1560
46edb027
DV		 1561 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1562 pll->name, pll->active, pll->on,
e2b78267 1563 crtc->base.base.id);
7a419866 1564
48da64a8 1565 if (WARN_ON(pll->active == 0)) {
e9d6944e 1566 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1567 return;
1568 }
1569
e9d6944e 1570 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1571 WARN_ON(!pll->on);
cdbd2316 1572 if (--pll->active)
7a419866 1573 return;
ee7b9f93 1574
46edb027 1575 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1576 pll->disable(dev_priv, pll);
ee7b9f93 1577 pll->on = false;
92f2584a
JB		 1578}
1579
b8a4f404
PZ		 1580static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581 enum pipe pipe)
040484af 1582{
23670b32 1583 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1584 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1586 uint32_t reg, val, pipeconf_val;
040484af
JB		 1587
1588 /* PCH only available on ILK+ */
1589 BUG_ON(dev_priv->info->gen < 5);
1590
1591 /* Make sure PCH DPLL is enabled */
e72f9fbf 1592 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1593 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1594
1595 /* FDI must be feeding us bits for PCH ports */
1596 assert_fdi_tx_enabled(dev_priv, pipe);
1597 assert_fdi_rx_enabled(dev_priv, pipe);
1598
23670b32
DV		 1599 if (HAS_PCH_CPT(dev)) {
1600 /* Workaround: Set the timing override bit before enabling the
1601 * pch transcoder. */
1602 reg = TRANS_CHICKEN2(pipe);
1603 val = I915_READ(reg);
1604 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605 I915_WRITE(reg, val);
59c859d6 1606 }
23670b32 1607
ab9412ba 1608 reg = PCH_TRANSCONF(pipe);
040484af 1609 val = I915_READ(reg);
5f7f726d 1610 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1611
1612 if (HAS_PCH_IBX(dev_priv->dev)) {
1613 /*
1614 * make the BPC in transcoder be consistent with
1615 * that in pipeconf reg.
1616 */
dfd07d72
DV		 1617 val &= ~PIPECONF_BPC_MASK;
1618 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1619 }
5f7f726d
PZ		 1620
1621 val &= ~TRANS_INTERLACE_MASK;
1622 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1623 if (HAS_PCH_IBX(dev_priv->dev) &&
1624 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625 val |= TRANS_LEGACY_INTERLACED_ILK;
1626 else
1627 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1628 else
1629 val |= TRANS_PROGRESSIVE;
1630
040484af
JB		 1631 I915_WRITE(reg, val | TRANS_ENABLE);
1632 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1633 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1634}
1635
8fb033d7 1636static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1637 enum transcoder cpu_transcoder)
040484af 1638{
8fb033d7 1639 u32 val, pipeconf_val;
8fb033d7
PZ		 1640
1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv->info->gen < 5);
1643
8fb033d7 1644 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1645 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1646 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1647
223a6fdf
PZ		 1648 /* Workaround: set timing override bit. */
1649 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1650 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1651 I915_WRITE(_TRANSA_CHICKEN2, val);
1652
25f3ef11 1653 val = TRANS_ENABLE;
937bb610 1654 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1655
9a76b1c6
PZ		 1656 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657 PIPECONF_INTERLACED_ILK)
a35f2679 1658 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1659 else
1660 val |= TRANS_PROGRESSIVE;
1661
ab9412ba
DV		 1662 I915_WRITE(LPT_TRANSCONF, val);
1663 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1664 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1665}
1666
b8a4f404
PZ		 1667static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668 enum pipe pipe)
040484af 1669{
23670b32
DV		 1670 struct drm_device *dev = dev_priv->dev;
1671 uint32_t reg, val;
040484af
JB		 1672
1673 /* FDI relies on the transcoder */
1674 assert_fdi_tx_disabled(dev_priv, pipe);
1675 assert_fdi_rx_disabled(dev_priv, pipe);
1676
291906f1
JB		 1677 /* Ports must be off as well */
1678 assert_pch_ports_disabled(dev_priv, pipe);
1679
ab9412ba 1680 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1681 val = I915_READ(reg);
1682 val &= ~TRANS_ENABLE;
1683 I915_WRITE(reg, val);
1684 /* wait for PCH transcoder off, transcoder state */
1685 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1686 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1687
1688 if (!HAS_PCH_IBX(dev)) {
1689 /* Workaround: Clear the timing override chicken bit again. */
1690 reg = TRANS_CHICKEN2(pipe);
1691 val = I915_READ(reg);
1692 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693 I915_WRITE(reg, val);
1694 }
040484af
JB		 1695}
1696
ab4d966c 1697static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1698{
8fb033d7
PZ		 1699 u32 val;
1700
ab9412ba 1701 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1702 val &= ~TRANS_ENABLE;
ab9412ba 1703 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1704 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1705 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1706 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1707
1708 /* Workaround: clear timing override bit. */
1709 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1710 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1711 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1712}
1713
b24e7179 1714/**
309cfea8 1715 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1716 * @dev_priv: i915 private structure
1717 * @pipe: pipe to enable
040484af 1718 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1719 *
1720 * Enable @pipe, making sure that various hardware specific requirements
1721 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722 *
1723 * @pipe should be %PIPE_A or %PIPE_B.
1724 *
1725 * Will wait until the pipe is actually running (i.e. first vblank) before
1726 * returning.
1727 */
040484af 1728static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1729 bool pch_port, bool dsi)
b24e7179 1730{
702e7a56
PZ		 1731 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732 pipe);
1a240d4d 1733 enum pipe pch_transcoder;
b24e7179
JB		 1734 int reg;
1735 u32 val;
1736
58c6eaa2 1737 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1738 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1739 assert_sprites_disabled(dev_priv, pipe);
1740
681e5811 1741 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1742 pch_transcoder = TRANSCODER_A;
1743 else
1744 pch_transcoder = pipe;
1745
b24e7179
JB		 1746 /*
1747 * A pipe without a PLL won't actually be able to drive bits from
1748 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1749 * need the check.
1750 */
1751 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1752 if (dsi)
1753 assert_dsi_pll_enabled(dev_priv);
1754 else
1755 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1756 else {
1757 if (pch_port) {
1758 /* if driving the PCH, we need FDI enabled */
cc391bbb 1759 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1760 assert_fdi_tx_pll_enabled(dev_priv,
1761 (enum pipe) cpu_transcoder);
040484af
JB		 1762 }
1763 /* FIXME: assert CPU port conditions for SNB+ */
1764 }
b24e7179 1765
702e7a56 1766 reg = PIPECONF(cpu_transcoder);
b24e7179 1767 val = I915_READ(reg);
00d70b15
CW		 1768 if (val & PIPECONF_ENABLE)
1769 return;
1770
1771 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1772 intel_wait_for_vblank(dev_priv->dev, pipe);
1773}
1774
1775/**
309cfea8 1776 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1777 * @dev_priv: i915 private structure
1778 * @pipe: pipe to disable
1779 *
1780 * Disable @pipe, making sure that various hardware specific requirements
1781 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1782 *
1783 * @pipe should be %PIPE_A or %PIPE_B.
1784 *
1785 * Will wait until the pipe has shut down before returning.
1786 */
1787static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1788 enum pipe pipe)
1789{
702e7a56
PZ		 1790 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1791 pipe);
b24e7179
JB		 1792 int reg;
1793 u32 val;
1794
1795 /*
1796 * Make sure planes won't keep trying to pump pixels to us,
1797 * or we might hang the display.
1798 */
1799 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1800 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1801 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1802
1803 /* Don't disable pipe A or pipe A PLLs if needed */
1804 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1805 return;
1806
702e7a56 1807 reg = PIPECONF(cpu_transcoder);
b24e7179 1808 val = I915_READ(reg);
00d70b15
CW		 1809 if ((val & PIPECONF_ENABLE) == 0)
1810 return;
1811
1812 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1813 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1814}
1815
d74362c9
KP		 1816/*
1817 * Plane regs are double buffered, going from enabled->disabled needs a
1818 * trigger in order to latch. The display address reg provides this.
1819 */
1dba99f4
VS		 1820void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane)
d74362c9 1822{
1dba99f4
VS		 1823 u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1824
1825 I915_WRITE(reg, I915_READ(reg));
1826 POSTING_READ(reg);
d74362c9
KP		 1827}
1828
b24e7179 1829/**
d1de00ef 1830 * intel_enable_primary_plane - enable the primary plane on a given pipe
b24e7179
JB		 1831 * @dev_priv: i915 private structure
1832 * @plane: plane to enable
1833 * @pipe: pipe being fed
1834 *
1835 * Enable @plane on @pipe, making sure that @pipe is running first.
1836 */
d1de00ef
VS		 1837static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1838 enum plane plane, enum pipe pipe)
b24e7179 1839{
939c2fe8
VS		 1840 struct intel_crtc *intel_crtc =
1841 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
b24e7179
JB		 1842 int reg;
1843 u32 val;
1844
1845 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1846 assert_pipe_enabled(dev_priv, pipe);
1847
4c445e0e 1848 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
0037f71c 1849
4c445e0e 1850 intel_crtc->primary_enabled = true;
939c2fe8 1851
b24e7179
JB		 1852 reg = DSPCNTR(plane);
1853 val = I915_READ(reg);
00d70b15
CW		 1854 if (val & DISPLAY_PLANE_ENABLE)
1855 return;
1856
1857 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1dba99f4 1858 intel_flush_primary_plane(dev_priv, plane);
b24e7179
JB		 1859 intel_wait_for_vblank(dev_priv->dev, pipe);
1860}
1861
b24e7179 1862/**
d1de00ef 1863 * intel_disable_primary_plane - disable the primary plane
b24e7179
JB		 1864 * @dev_priv: i915 private structure
1865 * @plane: plane to disable
1866 * @pipe: pipe consuming the data
1867 *
1868 * Disable @plane; should be an independent operation.
1869 */
d1de00ef
VS		 1870static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1871 enum plane plane, enum pipe pipe)
b24e7179 1872{
939c2fe8
VS		 1873 struct intel_crtc *intel_crtc =
1874 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
b24e7179
JB		 1875 int reg;
1876 u32 val;
1877
4c445e0e 1878 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
0037f71c 1879
4c445e0e 1880 intel_crtc->primary_enabled = false;
939c2fe8 1881
b24e7179
JB		 1882 reg = DSPCNTR(plane);
1883 val = I915_READ(reg);
00d70b15
CW		 1884 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1885 return;
1886
1887 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1dba99f4 1888 intel_flush_primary_plane(dev_priv, plane);
b24e7179
JB		 1889 intel_wait_for_vblank(dev_priv->dev, pipe);
1890}
1891
693db184
CW		 1892static bool need_vtd_wa(struct drm_device *dev)
1893{
1894#ifdef CONFIG_INTEL_IOMMU
1895 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1896 return true;
1897#endif
1898 return false;
1899}
1900
127bd2ac 1901int
48b956c5 1902intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1903 struct drm_i915_gem_object *obj,
919926ae 1904 struct intel_ring_buffer *pipelined)
6b95a207 1905{
ce453d81 1906 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1907 u32 alignment;
1908 int ret;
1909
05394f39 1910 switch (obj->tiling_mode) {
6b95a207 1911 case I915_TILING_NONE:
534843da
CW		 1912 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1913 alignment = 128 * 1024;
a6c45cf0 1914 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1915 alignment = 4 * 1024;
1916 else
1917 alignment = 64 * 1024;
6b95a207
KH		 1918 break;
1919 case I915_TILING_X:
1920 /* pin() will align the object as required by fence */
1921 alignment = 0;
1922 break;
1923 case I915_TILING_Y:
80075d49 1924 WARN(1, "Y tiled bo slipped through, driver bug!\n");
6b95a207
KH		 1925 return -EINVAL;
1926 default:
1927 BUG();
1928 }
1929
693db184
CW		 1930 /* Note that the w/a also requires 64 PTE of padding following the
1931 * bo. We currently fill all unused PTE with the shadow page and so
1932 * we should always have valid PTE following the scanout preventing
1933 * the VT-d warning.
1934 */
1935 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1936 alignment = 256 * 1024;
1937
ce453d81 1938 dev_priv->mm.interruptible = false;
2da3b9b9 1939 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1940 if (ret)
ce453d81 1941 goto err_interruptible;
6b95a207
KH		 1942
1943 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1944 * fence, whereas 965+ only requires a fence if using
1945 * framebuffer compression. For simplicity, we always install
1946 * a fence as the cost is not that onerous.
1947 */
06d98131 1948 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1949 if (ret)
1950 goto err_unpin;
1690e1eb 1951
9a5a53b3 1952 i915_gem_object_pin_fence(obj);
6b95a207 1953
ce453d81 1954 dev_priv->mm.interruptible = true;
6b95a207 1955 return 0;
48b956c5
CW		 1956
1957err_unpin:
cc98b413 1958 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1959err_interruptible:
1960 dev_priv->mm.interruptible = true;
48b956c5 1961 return ret;
6b95a207
KH		 1962}
1963
1690e1eb
CW		 1964void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1965{
1966 i915_gem_object_unpin_fence(obj);
cc98b413 1967 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1968}
1969
c2c75131
DV		 1970/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1971 * is assumed to be a power-of-two. */
bc752862
CW		 1972unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1973 unsigned int tiling_mode,
1974 unsigned int cpp,
1975 unsigned int pitch)
c2c75131 1976{
bc752862
CW		 1977 if (tiling_mode != I915_TILING_NONE) {
1978 unsigned int tile_rows, tiles;
c2c75131 1979
bc752862
CW		 1980 tile_rows = *y / 8;
1981 *y %= 8;
c2c75131 1982
bc752862
CW		 1983 tiles = *x / (512/cpp);
1984 *x %= 512/cpp;
1985
1986 return tile_rows * pitch * 8 + tiles * 4096;
1987 } else {
1988 unsigned int offset;
1989
1990 offset = *y * pitch + *x * cpp;
1991 *y = 0;
1992 *x = (offset & 4095) / cpp;
1993 return offset & -4096;
1994 }
c2c75131
DV		 1995}
1996
17638cd6
JB		 1997static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1998 int x, int y)
81255565
JB		 1999{
2000 struct drm_device *dev = crtc->dev;
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2003 struct intel_framebuffer *intel_fb;
05394f39 2004 struct drm_i915_gem_object *obj;
81255565 2005 int plane = intel_crtc->plane;
e506a0c6 2006 unsigned long linear_offset;
81255565 2007 u32 dspcntr;
5eddb70b 2008 u32 reg;
81255565
JB		 2009
2010 switch (plane) {
2011 case 0:
2012 case 1:
2013 break;
2014 default:
84f44ce7 2015 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2016 return -EINVAL;
2017 }
2018
2019 intel_fb = to_intel_framebuffer(fb);
2020 obj = intel_fb->obj;
81255565 2021
5eddb70b
CW		 2022 reg = DSPCNTR(plane);
2023 dspcntr = I915_READ(reg);
81255565
JB		 2024 /* Mask out pixel format bits in case we change it */
2025 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2026 switch (fb->pixel_format) {
2027 case DRM_FORMAT_C8:
81255565
JB		 2028 dspcntr |= DISPPLANE_8BPP;
2029 break;
57779d06
VS		 2030 case DRM_FORMAT_XRGB1555:
2031 case DRM_FORMAT_ARGB1555:
2032 dspcntr |= DISPPLANE_BGRX555;
81255565 2033 break;
57779d06
VS		 2034 case DRM_FORMAT_RGB565:
2035 dspcntr |= DISPPLANE_BGRX565;
2036 break;
2037 case DRM_FORMAT_XRGB8888:
2038 case DRM_FORMAT_ARGB8888:
2039 dspcntr |= DISPPLANE_BGRX888;
2040 break;
2041 case DRM_FORMAT_XBGR8888:
2042 case DRM_FORMAT_ABGR8888:
2043 dspcntr |= DISPPLANE_RGBX888;
2044 break;
2045 case DRM_FORMAT_XRGB2101010:
2046 case DRM_FORMAT_ARGB2101010:
2047 dspcntr |= DISPPLANE_BGRX101010;
2048 break;
2049 case DRM_FORMAT_XBGR2101010:
2050 case DRM_FORMAT_ABGR2101010:
2051 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2052 break;
2053 default:
baba133a 2054 BUG();
81255565 2055 }
57779d06 2056
a6c45cf0 2057 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2058 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2059 dspcntr |= DISPPLANE_TILED;
2060 else
2061 dspcntr &= ~DISPPLANE_TILED;
2062 }
2063
de1aa629
VS		 2064 if (IS_G4X(dev))
2065 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2066
5eddb70b 2067 I915_WRITE(reg, dspcntr);
81255565 2068
e506a0c6 2069 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2070
c2c75131
DV		 2071 if (INTEL_INFO(dev)->gen >= 4) {
2072 intel_crtc->dspaddr_offset =
bc752862
CW		 2073 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2074 fb->bits_per_pixel / 8,
2075 fb->pitches[0]);
c2c75131
DV		 2076 linear_offset -= intel_crtc->dspaddr_offset;
2077 } else {
e506a0c6 2078 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2079 }
e506a0c6 2080
f343c5f6
BW		 2081 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2082 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2083 fb->pitches[0]);
01f2c773 2084 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2085 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2086 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2087 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2088 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2089 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2090 } else
f343c5f6 2091 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2092 POSTING_READ(reg);
81255565 2093
17638cd6
JB		 2094 return 0;
2095}
2096
2097static int ironlake_update_plane(struct drm_crtc *crtc,
2098 struct drm_framebuffer *fb, int x, int y)
2099{
2100 struct drm_device *dev = crtc->dev;
2101 struct drm_i915_private *dev_priv = dev->dev_private;
2102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2103 struct intel_framebuffer *intel_fb;
2104 struct drm_i915_gem_object *obj;
2105 int plane = intel_crtc->plane;
e506a0c6 2106 unsigned long linear_offset;
17638cd6
JB		 2107 u32 dspcntr;
2108 u32 reg;
2109
2110 switch (plane) {
2111 case 0:
2112 case 1:
27f8227b 2113 case 2:
17638cd6
JB		 2114 break;
2115 default:
84f44ce7 2116 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2117 return -EINVAL;
2118 }
2119
2120 intel_fb = to_intel_framebuffer(fb);
2121 obj = intel_fb->obj;
2122
2123 reg = DSPCNTR(plane);
2124 dspcntr = I915_READ(reg);
2125 /* Mask out pixel format bits in case we change it */
2126 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2127 switch (fb->pixel_format) {
2128 case DRM_FORMAT_C8:
17638cd6
JB		 2129 dspcntr |= DISPPLANE_8BPP;
2130 break;
57779d06
VS		 2131 case DRM_FORMAT_RGB565:
2132 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2133 break;
57779d06
VS		 2134 case DRM_FORMAT_XRGB8888:
2135 case DRM_FORMAT_ARGB8888:
2136 dspcntr |= DISPPLANE_BGRX888;
2137 break;
2138 case DRM_FORMAT_XBGR8888:
2139 case DRM_FORMAT_ABGR8888:
2140 dspcntr |= DISPPLANE_RGBX888;
2141 break;
2142 case DRM_FORMAT_XRGB2101010:
2143 case DRM_FORMAT_ARGB2101010:
2144 dspcntr |= DISPPLANE_BGRX101010;
2145 break;
2146 case DRM_FORMAT_XBGR2101010:
2147 case DRM_FORMAT_ABGR2101010:
2148 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2149 break;
2150 default:
baba133a 2151 BUG();
17638cd6
JB		 2152 }
2153
2154 if (obj->tiling_mode != I915_TILING_NONE)
2155 dspcntr |= DISPPLANE_TILED;
2156 else
2157 dspcntr &= ~DISPPLANE_TILED;
2158
b42c6009 2159 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1f5d76db
PZ		 2160 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2161 else
2162 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2163
2164 I915_WRITE(reg, dspcntr);
2165
e506a0c6 2166 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2167 intel_crtc->dspaddr_offset =
bc752862
CW		 2168 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2169 fb->bits_per_pixel / 8,
2170 fb->pitches[0]);
c2c75131 2171 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2172
f343c5f6
BW		 2173 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2174 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2175 fb->pitches[0]);
01f2c773 2176 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2177 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2178 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2179 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2180 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2181 } else {
2182 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2183 I915_WRITE(DSPLINOFF(plane), linear_offset);
2184 }
17638cd6
JB		 2185 POSTING_READ(reg);
2186
2187 return 0;
2188}
2189
2190/* Assume fb object is pinned & idle & fenced and just update base pointers */
2191static int
2192intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2193 int x, int y, enum mode_set_atomic state)
2194{
2195 struct drm_device *dev = crtc->dev;
2196 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2197
6b8e6ed0
CW		 2198 if (dev_priv->display.disable_fbc)
2199 dev_priv->display.disable_fbc(dev);
3dec0095 2200 intel_increase_pllclock(crtc);
81255565 2201
6b8e6ed0 2202 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2203}
2204
96a02917
VS		 2205void intel_display_handle_reset(struct drm_device *dev)
2206{
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct drm_crtc *crtc;
2209
2210 /*
2211 * Flips in the rings have been nuked by the reset,
2212 * so complete all pending flips so that user space
2213 * will get its events and not get stuck.
2214 *
2215 * Also update the base address of all primary
2216 * planes to the the last fb to make sure we're
2217 * showing the correct fb after a reset.
2218 *
2219 * Need to make two loops over the crtcs so that we
2220 * don't try to grab a crtc mutex before the
2221 * pending_flip_queue really got woken up.
2222 */
2223
2224 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2226 enum plane plane = intel_crtc->plane;
2227
2228 intel_prepare_page_flip(dev, plane);
2229 intel_finish_page_flip_plane(dev, plane);
2230 }
2231
2232 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235 mutex_lock(&crtc->mutex);
2236 if (intel_crtc->active)
2237 dev_priv->display.update_plane(crtc, crtc->fb,
2238 crtc->x, crtc->y);
2239 mutex_unlock(&crtc->mutex);
2240 }
2241}
2242
14667a4b
CW		 2243static int
2244intel_finish_fb(struct drm_framebuffer *old_fb)
2245{
2246 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2247 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2248 bool was_interruptible = dev_priv->mm.interruptible;
2249 int ret;
2250
14667a4b
CW		 2251 /* Big Hammer, we also need to ensure that any pending
2252 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2253 * current scanout is retired before unpinning the old
2254 * framebuffer.
2255 *
2256 * This should only fail upon a hung GPU, in which case we
2257 * can safely continue.
2258 */
2259 dev_priv->mm.interruptible = false;
2260 ret = i915_gem_object_finish_gpu(obj);
2261 dev_priv->mm.interruptible = was_interruptible;
2262
2263 return ret;
2264}
2265
198598d0
VS		 2266static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2267{
2268 struct drm_device *dev = crtc->dev;
2269 struct drm_i915_master_private *master_priv;
2270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2271
2272 if (!dev->primary->master)
2273 return;
2274
2275 master_priv = dev->primary->master->driver_priv;
2276 if (!master_priv->sarea_priv)
2277 return;
2278
2279 switch (intel_crtc->pipe) {
2280 case 0:
2281 master_priv->sarea_priv->pipeA_x = x;
2282 master_priv->sarea_priv->pipeA_y = y;
2283 break;
2284 case 1:
2285 master_priv->sarea_priv->pipeB_x = x;
2286 master_priv->sarea_priv->pipeB_y = y;
2287 break;
2288 default:
2289 break;
2290 }
2291}
2292
5c3b82e2 2293static int
3c4fdcfb 2294intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2295 struct drm_framebuffer *fb)
79e53945
JB		 2296{
2297 struct drm_device *dev = crtc->dev;
6b8e6ed0 2298 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2300 struct drm_framebuffer *old_fb;
5c3b82e2 2301 int ret;
79e53945
JB		 2302
2303 /* no fb bound */
94352cf9 2304 if (!fb) {
a5071c2f 2305 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2306 return 0;
2307 }
2308
7eb552ae 2309 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2310 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2311 plane_name(intel_crtc->plane),
2312 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2313 return -EINVAL;
79e53945
JB		 2314 }
2315
5c3b82e2 2316 mutex_lock(&dev->struct_mutex);
265db958 2317 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2318 to_intel_framebuffer(fb)->obj,
919926ae 2319 NULL);
5c3b82e2
CW		 2320 if (ret != 0) {
2321 mutex_unlock(&dev->struct_mutex);
a5071c2f 2322 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2323 return ret;
2324 }
79e53945 2325
bb2043de
DL		 2326 /*
2327 * Update pipe size and adjust fitter if needed: the reason for this is
2328 * that in compute_mode_changes we check the native mode (not the pfit
2329 * mode) to see if we can flip rather than do a full mode set. In the
2330 * fastboot case, we'll flip, but if we don't update the pipesrc and
2331 * pfit state, we'll end up with a big fb scanned out into the wrong
2332 * sized surface.
2333 *
2334 * To fix this properly, we need to hoist the checks up into
2335 * compute_mode_changes (or above), check the actual pfit state and
2336 * whether the platform allows pfit disable with pipe active, and only
2337 * then update the pipesrc and pfit state, even on the flip path.
2338 */
4d6a3e63 2339 if (i915_fastboot) {
d7bf63f2
DL		 2340 const struct drm_display_mode *adjusted_mode =
2341 &intel_crtc->config.adjusted_mode;
2342
4d6a3e63 2343 I915_WRITE(PIPESRC(intel_crtc->pipe),
d7bf63f2
DL		 2344 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2345 (adjusted_mode->crtc_vdisplay - 1));
fd4daa9c 2346 if (!intel_crtc->config.pch_pfit.enabled &&
4d6a3e63
JB		 2347 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2348 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2349 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2350 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2351 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2352 }
2353 }
2354
94352cf9 2355 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2356 if (ret) {
94352cf9 2357 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2358 mutex_unlock(&dev->struct_mutex);
a5071c2f 2359 DRM_ERROR("failed to update base address\n");
4e6cfefc 2360 return ret;
79e53945 2361 }
3c4fdcfb 2362
94352cf9
DV		 2363 old_fb = crtc->fb;
2364 crtc->fb = fb;
6c4c86f5
DV		 2365 crtc->x = x;
2366 crtc->y = y;
94352cf9 2367
b7f1de28 2368 if (old_fb) {
d7697eea
DV		 2369 if (intel_crtc->active && old_fb != fb)
2370 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2371 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2372 }
652c393a 2373
6b8e6ed0 2374 intel_update_fbc(dev);
4906557e 2375 intel_edp_psr_update(dev);
5c3b82e2 2376 mutex_unlock(&dev->struct_mutex);
79e53945 2377
198598d0 2378 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2379
2380 return 0;
79e53945
JB		 2381}
2382
5e84e1a4
ZW		 2383static void intel_fdi_normal_train(struct drm_crtc *crtc)
2384{
2385 struct drm_device *dev = crtc->dev;
2386 struct drm_i915_private *dev_priv = dev->dev_private;
2387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2388 int pipe = intel_crtc->pipe;
2389 u32 reg, temp;
2390
2391 /* enable normal train */
2392 reg = FDI_TX_CTL(pipe);
2393 temp = I915_READ(reg);
61e499bf 2394 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2395 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2396 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2397 } else {
2398 temp &= ~FDI_LINK_TRAIN_NONE;
2399 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2400 }
5e84e1a4
ZW		 2401 I915_WRITE(reg, temp);
2402
2403 reg = FDI_RX_CTL(pipe);
2404 temp = I915_READ(reg);
2405 if (HAS_PCH_CPT(dev)) {
2406 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2407 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2408 } else {
2409 temp &= ~FDI_LINK_TRAIN_NONE;
2410 temp |= FDI_LINK_TRAIN_NONE;
2411 }
2412 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2413
2414 /* wait one idle pattern time */
2415 POSTING_READ(reg);
2416 udelay(1000);
357555c0
JB		 2417
2418 /* IVB wants error correction enabled */
2419 if (IS_IVYBRIDGE(dev))
2420 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2421 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2422}
2423
1fbc0d78 2424static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
1e833f40 2425{
1fbc0d78
DV		 2426 return crtc->base.enabled && crtc->active &&
2427 crtc->config.has_pch_encoder;
1e833f40
DV		 2428}
2429
01a415fd
DV		 2430static void ivb_modeset_global_resources(struct drm_device *dev)
2431{
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 struct intel_crtc *pipe_B_crtc =
2434 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2435 struct intel_crtc *pipe_C_crtc =
2436 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2437 uint32_t temp;
2438
1e833f40
DV		 2439 /*
2440 * When everything is off disable fdi C so that we could enable fdi B
2441 * with all lanes. Note that we don't care about enabled pipes without
2442 * an enabled pch encoder.
2443 */
2444 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2445 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2446 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2447 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2448
2449 temp = I915_READ(SOUTH_CHICKEN1);
2450 temp &= ~FDI_BC_BIFURCATION_SELECT;
2451 DRM_DEBUG_KMS("disabling fdi C rx\n");
2452 I915_WRITE(SOUTH_CHICKEN1, temp);
2453 }
2454}
2455
8db9d77b
ZW		 2456/* The FDI link training functions for ILK/Ibexpeak. */
2457static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2458{
2459 struct drm_device *dev = crtc->dev;
2460 struct drm_i915_private *dev_priv = dev->dev_private;
2461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2462 int pipe = intel_crtc->pipe;
0fc932b8 2463 int plane = intel_crtc->plane;
5eddb70b 2464 u32 reg, temp, tries;
8db9d77b 2465
0fc932b8
JB		 2466 /* FDI needs bits from pipe & plane first */
2467 assert_pipe_enabled(dev_priv, pipe);
2468 assert_plane_enabled(dev_priv, plane);
2469
e1a44743
AJ		 2470 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2471 for train result */
5eddb70b
CW		 2472 reg = FDI_RX_IMR(pipe);
2473 temp = I915_READ(reg);
e1a44743
AJ		 2474 temp &= ~FDI_RX_SYMBOL_LOCK;
2475 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2476 I915_WRITE(reg, temp);
2477 I915_READ(reg);
e1a44743
AJ		 2478 udelay(150);
2479
8db9d77b 2480 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2481 reg = FDI_TX_CTL(pipe);
2482 temp = I915_READ(reg);
627eb5a3
DV		 2483 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2484 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2485 temp &= ~FDI_LINK_TRAIN_NONE;
2486 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2487 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2488
5eddb70b
CW		 2489 reg = FDI_RX_CTL(pipe);
2490 temp = I915_READ(reg);
8db9d77b
ZW		 2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2493 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2494
2495 POSTING_READ(reg);
8db9d77b
ZW		 2496 udelay(150);
2497
5b2adf89 2498 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2499 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2500 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2501 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2502
5eddb70b 2503 reg = FDI_RX_IIR(pipe);
e1a44743 2504 for (tries = 0; tries < 5; tries++) {
5eddb70b 2505 temp = I915_READ(reg);
8db9d77b
ZW		 2506 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2507
2508 if ((temp & FDI_RX_BIT_LOCK)) {
2509 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2510 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2511 break;
2512 }
8db9d77b 2513 }
e1a44743 2514 if (tries == 5)
5eddb70b 2515 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2516
2517 /* Train 2 */
5eddb70b
CW		 2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
8db9d77b
ZW		 2520 temp &= ~FDI_LINK_TRAIN_NONE;
2521 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2522 I915_WRITE(reg, temp);
8db9d77b 2523
5eddb70b
CW		 2524 reg = FDI_RX_CTL(pipe);
2525 temp = I915_READ(reg);
8db9d77b
ZW		 2526 temp &= ~FDI_LINK_TRAIN_NONE;
2527 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2528 I915_WRITE(reg, temp);
8db9d77b 2529
5eddb70b
CW		 2530 POSTING_READ(reg);
2531 udelay(150);
8db9d77b 2532
5eddb70b 2533 reg = FDI_RX_IIR(pipe);
e1a44743 2534 for (tries = 0; tries < 5; tries++) {
5eddb70b 2535 temp = I915_READ(reg);
8db9d77b
ZW		 2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537
2538 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2539 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2540 DRM_DEBUG_KMS("FDI train 2 done.\n");
2541 break;
2542 }
8db9d77b 2543 }
e1a44743 2544 if (tries == 5)
5eddb70b 2545 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2546
2547 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2548
8db9d77b
ZW		 2549}
2550
0206e353 2551static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2552 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2553 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2554 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2555 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2556};
2557
2558/* The FDI link training functions for SNB/Cougarpoint. */
2559static void gen6_fdi_link_train(struct drm_crtc *crtc)
2560{
2561 struct drm_device *dev = crtc->dev;
2562 struct drm_i915_private *dev_priv = dev->dev_private;
2563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2564 int pipe = intel_crtc->pipe;
fa37d39e 2565 u32 reg, temp, i, retry;
8db9d77b 2566
e1a44743
AJ		 2567 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2568 for train result */
5eddb70b
CW		 2569 reg = FDI_RX_IMR(pipe);
2570 temp = I915_READ(reg);
e1a44743
AJ		 2571 temp &= ~FDI_RX_SYMBOL_LOCK;
2572 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
e1a44743
AJ		 2576 udelay(150);
2577
8db9d77b 2578 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2579 reg = FDI_TX_CTL(pipe);
2580 temp = I915_READ(reg);
627eb5a3
DV		 2581 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2582 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2583 temp &= ~FDI_LINK_TRAIN_NONE;
2584 temp |= FDI_LINK_TRAIN_PATTERN_1;
2585 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2586 /* SNB-B */
2587 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2588 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2589
d74cf324
DV		 2590 I915_WRITE(FDI_RX_MISC(pipe),
2591 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2592
5eddb70b
CW		 2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
8db9d77b
ZW		 2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_1;
2601 }
5eddb70b
CW		 2602 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2603
2604 POSTING_READ(reg);
8db9d77b
ZW		 2605 udelay(150);
2606
0206e353 2607 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
8db9d77b
ZW		 2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
8db9d77b
ZW		 2615 udelay(500);
2616
fa37d39e
SP		 2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_BIT_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2623 DRM_DEBUG_KMS("FDI train 1 done.\n");
2624 break;
2625 }
2626 udelay(50);
8db9d77b 2627 }
fa37d39e
SP		 2628 if (retry < 5)
2629 break;
8db9d77b
ZW		 2630 }
2631 if (i == 4)
5eddb70b 2632 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2633
2634 /* Train 2 */
5eddb70b
CW		 2635 reg = FDI_TX_CTL(pipe);
2636 temp = I915_READ(reg);
8db9d77b
ZW		 2637 temp &= ~FDI_LINK_TRAIN_NONE;
2638 temp |= FDI_LINK_TRAIN_PATTERN_2;
2639 if (IS_GEN6(dev)) {
2640 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2641 /* SNB-B */
2642 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2643 }
5eddb70b 2644 I915_WRITE(reg, temp);
8db9d77b 2645
5eddb70b
CW		 2646 reg = FDI_RX_CTL(pipe);
2647 temp = I915_READ(reg);
8db9d77b
ZW		 2648 if (HAS_PCH_CPT(dev)) {
2649 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2650 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2651 } else {
2652 temp &= ~FDI_LINK_TRAIN_NONE;
2653 temp |= FDI_LINK_TRAIN_PATTERN_2;
2654 }
5eddb70b
CW		 2655 I915_WRITE(reg, temp);
2656
2657 POSTING_READ(reg);
8db9d77b
ZW		 2658 udelay(150);
2659
0206e353 2660 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2661 reg = FDI_TX_CTL(pipe);
2662 temp = I915_READ(reg);
8db9d77b
ZW		 2663 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2664 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2665 I915_WRITE(reg, temp);
2666
2667 POSTING_READ(reg);
8db9d77b
ZW		 2668 udelay(500);
2669
fa37d39e
SP		 2670 for (retry = 0; retry < 5; retry++) {
2671 reg = FDI_RX_IIR(pipe);
2672 temp = I915_READ(reg);
2673 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2674 if (temp & FDI_RX_SYMBOL_LOCK) {
2675 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2676 DRM_DEBUG_KMS("FDI train 2 done.\n");
2677 break;
2678 }
2679 udelay(50);
8db9d77b 2680 }
fa37d39e
SP		 2681 if (retry < 5)
2682 break;
8db9d77b
ZW		 2683 }
2684 if (i == 4)
5eddb70b 2685 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2686
2687 DRM_DEBUG_KMS("FDI train done.\n");
2688}
2689
357555c0
JB		 2690/* Manual link training for Ivy Bridge A0 parts */
2691static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2692{
2693 struct drm_device *dev = crtc->dev;
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2696 int pipe = intel_crtc->pipe;
139ccd3f 2697 u32 reg, temp, i, j;
357555c0
JB		 2698
2699 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2700 for train result */
2701 reg = FDI_RX_IMR(pipe);
2702 temp = I915_READ(reg);
2703 temp &= ~FDI_RX_SYMBOL_LOCK;
2704 temp &= ~FDI_RX_BIT_LOCK;
2705 I915_WRITE(reg, temp);
2706
2707 POSTING_READ(reg);
2708 udelay(150);
2709
01a415fd
DV		 2710 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2711 I915_READ(FDI_RX_IIR(pipe)));
2712
139ccd3f
JB		 2713 /* Try each vswing and preemphasis setting twice before moving on */
2714 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2715 /* disable first in case we need to retry */
2716 reg = FDI_TX_CTL(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2719 temp &= ~FDI_TX_ENABLE;
2720 I915_WRITE(reg, temp);
357555c0 2721
139ccd3f
JB		 2722 reg = FDI_RX_CTL(pipe);
2723 temp = I915_READ(reg);
2724 temp &= ~FDI_LINK_TRAIN_AUTO;
2725 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2726 temp &= ~FDI_RX_ENABLE;
2727 I915_WRITE(reg, temp);
357555c0 2728
139ccd3f 2729 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2730 reg = FDI_TX_CTL(pipe);
2731 temp = I915_READ(reg);
139ccd3f
JB		 2732 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2733 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2734 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2735 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2736 temp |= snb_b_fdi_train_param[j/2];
2737 temp |= FDI_COMPOSITE_SYNC;
2738 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2739
139ccd3f
JB		 2740 I915_WRITE(FDI_RX_MISC(pipe),
2741 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2742
139ccd3f 2743 reg = FDI_RX_CTL(pipe);
357555c0 2744 temp = I915_READ(reg);
139ccd3f
JB		 2745 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2746 temp |= FDI_COMPOSITE_SYNC;
2747 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2748
139ccd3f
JB		 2749 POSTING_READ(reg);
2750 udelay(1); /* should be 0.5us */
357555c0 2751
139ccd3f
JB		 2752 for (i = 0; i < 4; i++) {
2753 reg = FDI_RX_IIR(pipe);
2754 temp = I915_READ(reg);
2755 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2756
139ccd3f
JB		 2757 if (temp & FDI_RX_BIT_LOCK ||
2758 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2759 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2760 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2761 i);
2762 break;
2763 }
2764 udelay(1); /* should be 0.5us */
2765 }
2766 if (i == 4) {
2767 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2768 continue;
2769 }
357555c0 2770
139ccd3f 2771 /* Train 2 */
357555c0
JB		 2772 reg = FDI_TX_CTL(pipe);
2773 temp = I915_READ(reg);
139ccd3f
JB		 2774 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2775 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2776 I915_WRITE(reg, temp);
2777
2778 reg = FDI_RX_CTL(pipe);
2779 temp = I915_READ(reg);
2780 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2781 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2782 I915_WRITE(reg, temp);
2783
2784 POSTING_READ(reg);
139ccd3f 2785 udelay(2); /* should be 1.5us */
357555c0 2786
139ccd3f
JB		 2787 for (i = 0; i < 4; i++) {
2788 reg = FDI_RX_IIR(pipe);
2789 temp = I915_READ(reg);
2790 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2791
139ccd3f
JB		 2792 if (temp & FDI_RX_SYMBOL_LOCK ||
2793 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2794 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2795 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2796 i);
2797 goto train_done;
2798 }
2799 udelay(2); /* should be 1.5us */
357555c0 2800 }
139ccd3f
JB		 2801 if (i == 4)
2802 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2803 }
357555c0 2804
139ccd3f 2805train_done:
357555c0
JB		 2806 DRM_DEBUG_KMS("FDI train done.\n");
2807}
2808
88cefb6c 2809static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2810{
88cefb6c 2811 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2812 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2813 int pipe = intel_crtc->pipe;
5eddb70b 2814 u32 reg, temp;
79e53945 2815
c64e311e 2816
c98e9dcf 2817 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2818 reg = FDI_RX_CTL(pipe);
2819 temp = I915_READ(reg);
627eb5a3
DV		 2820 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2821 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2822 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2823 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2824
2825 POSTING_READ(reg);
c98e9dcf
JB		 2826 udelay(200);
2827
2828 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2829 temp = I915_READ(reg);
2830 I915_WRITE(reg, temp | FDI_PCDCLK);
2831
2832 POSTING_READ(reg);
c98e9dcf
JB		 2833 udelay(200);
2834
20749730
PZ		 2835 /* Enable CPU FDI TX PLL, always on for Ironlake */
2836 reg = FDI_TX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2839 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2840
20749730
PZ		 2841 POSTING_READ(reg);
2842 udelay(100);
6be4a607 2843 }
0e23b99d
JB		 2844}
2845
88cefb6c
DV		 2846static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2847{
2848 struct drm_device *dev = intel_crtc->base.dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 int pipe = intel_crtc->pipe;
2851 u32 reg, temp;
2852
2853 /* Switch from PCDclk to Rawclk */
2854 reg = FDI_RX_CTL(pipe);
2855 temp = I915_READ(reg);
2856 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2857
2858 /* Disable CPU FDI TX PLL */
2859 reg = FDI_TX_CTL(pipe);
2860 temp = I915_READ(reg);
2861 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2862
2863 POSTING_READ(reg);
2864 udelay(100);
2865
2866 reg = FDI_RX_CTL(pipe);
2867 temp = I915_READ(reg);
2868 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2869
2870 /* Wait for the clocks to turn off. */
2871 POSTING_READ(reg);
2872 udelay(100);
2873}
2874
0fc932b8
JB		 2875static void ironlake_fdi_disable(struct drm_crtc *crtc)
2876{
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880 int pipe = intel_crtc->pipe;
2881 u32 reg, temp;
2882
2883 /* disable CPU FDI tx and PCH FDI rx */
2884 reg = FDI_TX_CTL(pipe);
2885 temp = I915_READ(reg);
2886 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2887 POSTING_READ(reg);
2888
2889 reg = FDI_RX_CTL(pipe);
2890 temp = I915_READ(reg);
2891 temp &= ~(0x7 << 16);
dfd07d72 2892 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2893 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2894
2895 POSTING_READ(reg);
2896 udelay(100);
2897
2898 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2899 if (HAS_PCH_IBX(dev)) {
2900 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2901 }
0fc932b8
JB		 2902
2903 /* still set train pattern 1 */
2904 reg = FDI_TX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~FDI_LINK_TRAIN_NONE;
2907 temp |= FDI_LINK_TRAIN_PATTERN_1;
2908 I915_WRITE(reg, temp);
2909
2910 reg = FDI_RX_CTL(pipe);
2911 temp = I915_READ(reg);
2912 if (HAS_PCH_CPT(dev)) {
2913 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2914 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2915 } else {
2916 temp &= ~FDI_LINK_TRAIN_NONE;
2917 temp |= FDI_LINK_TRAIN_PATTERN_1;
2918 }
2919 /* BPC in FDI rx is consistent with that in PIPECONF */
2920 temp &= ~(0x07 << 16);
dfd07d72 2921 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2922 I915_WRITE(reg, temp);
2923
2924 POSTING_READ(reg);
2925 udelay(100);
2926}
2927
5bb61643
CW		 2928static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2929{
2930 struct drm_device *dev = crtc->dev;
2931 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2933 unsigned long flags;
2934 bool pending;
2935
10d83730
VS		 2936 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2937 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2938 return false;
2939
2940 spin_lock_irqsave(&dev->event_lock, flags);
2941 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2942 spin_unlock_irqrestore(&dev->event_lock, flags);
2943
2944 return pending;
2945}
2946
e6c3a2a6
CW		 2947static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2948{
0f91128d 2949 struct drm_device *dev = crtc->dev;
5bb61643 2950 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2951
2952 if (crtc->fb == NULL)
2953 return;
2954
2c10d571
DV		 2955 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2956
5bb61643
CW		 2957 wait_event(dev_priv->pending_flip_queue,
2958 !intel_crtc_has_pending_flip(crtc));
2959
0f91128d
CW		 2960 mutex_lock(&dev->struct_mutex);
2961 intel_finish_fb(crtc->fb);
2962 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2963}
2964
e615efe4
ED		 2965/* Program iCLKIP clock to the desired frequency */
2966static void lpt_program_iclkip(struct drm_crtc *crtc)
2967{
2968 struct drm_device *dev = crtc->dev;
2969 struct drm_i915_private *dev_priv = dev->dev_private;
241bfc38 2970 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
e615efe4
ED		 2971 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2972 u32 temp;
2973
09153000
DV		 2974 mutex_lock(&dev_priv->dpio_lock);
2975
e615efe4
ED		 2976 /* It is necessary to ungate the pixclk gate prior to programming
2977 * the divisors, and gate it back when it is done.
2978 */
2979 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2980
2981 /* Disable SSCCTL */
2982 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2983 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2984 SBI_SSCCTL_DISABLE,
2985 SBI_ICLK);
e615efe4
ED		 2986
2987 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2988 if (clock == 20000) {
e615efe4
ED		 2989 auxdiv = 1;
2990 divsel = 0x41;
2991 phaseinc = 0x20;
2992 } else {
2993 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 2994 * but the adjusted_mode->crtc_clock in in KHz. To get the
2995 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 2996 * convert the virtual clock precision to KHz here for higher
2997 * precision.
2998 */
2999 u32 iclk_virtual_root_freq = 172800 * 1000;
3000 u32 iclk_pi_range = 64;
3001 u32 desired_divisor, msb_divisor_value, pi_value;
3002
12d7ceed 3003 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3004 msb_divisor_value = desired_divisor / iclk_pi_range;
3005 pi_value = desired_divisor % iclk_pi_range;
3006
3007 auxdiv = 0;
3008 divsel = msb_divisor_value - 2;
3009 phaseinc = pi_value;
3010 }
3011
3012 /* This should not happen with any sane values */
3013 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3014 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3015 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3016 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3017
3018 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3019 clock,
e615efe4
ED		 3020 auxdiv,
3021 divsel,
3022 phasedir,
3023 phaseinc);
3024
3025 /* Program SSCDIVINTPHASE6 */
988d6ee8 3026 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3027 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3028 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3029 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3030 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3031 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3032 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3033 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3034
3035 /* Program SSCAUXDIV */
988d6ee8 3036 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3037 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3038 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3039 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3040
3041 /* Enable modulator and associated divider */
988d6ee8 3042 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3043 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3044 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3045
3046 /* Wait for initialization time */
3047 udelay(24);
3048
3049 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3050
3051 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3052}
3053
275f01b2
DV		 3054static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3055 enum pipe pch_transcoder)
3056{
3057 struct drm_device *dev = crtc->base.dev;
3058 struct drm_i915_private *dev_priv = dev->dev_private;
3059 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3060
3061 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3062 I915_READ(HTOTAL(cpu_transcoder)));
3063 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3064 I915_READ(HBLANK(cpu_transcoder)));
3065 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3066 I915_READ(HSYNC(cpu_transcoder)));
3067
3068 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3069 I915_READ(VTOTAL(cpu_transcoder)));
3070 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3071 I915_READ(VBLANK(cpu_transcoder)));
3072 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3073 I915_READ(VSYNC(cpu_transcoder)));
3074 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3075 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3076}
3077
1fbc0d78
DV		 3078static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3079{
3080 struct drm_i915_private *dev_priv = dev->dev_private;
3081 uint32_t temp;
3082
3083 temp = I915_READ(SOUTH_CHICKEN1);
3084 if (temp & FDI_BC_BIFURCATION_SELECT)
3085 return;
3086
3087 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3088 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3089
3090 temp |= FDI_BC_BIFURCATION_SELECT;
3091 DRM_DEBUG_KMS("enabling fdi C rx\n");
3092 I915_WRITE(SOUTH_CHICKEN1, temp);
3093 POSTING_READ(SOUTH_CHICKEN1);
3094}
3095
3096static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3097{
3098 struct drm_device *dev = intel_crtc->base.dev;
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3100
3101 switch (intel_crtc->pipe) {
3102 case PIPE_A:
3103 break;
3104 case PIPE_B:
3105 if (intel_crtc->config.fdi_lanes > 2)
3106 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3107 else
3108 cpt_enable_fdi_bc_bifurcation(dev);
3109
3110 break;
3111 case PIPE_C:
3112 cpt_enable_fdi_bc_bifurcation(dev);
3113
3114 break;
3115 default:
3116 BUG();
3117 }
3118}
3119
f67a559d
JB		 3120/*
3121 * Enable PCH resources required for PCH ports:
3122 * - PCH PLLs
3123 * - FDI training & RX/TX
3124 * - update transcoder timings
3125 * - DP transcoding bits
3126 * - transcoder
3127 */
3128static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3129{
3130 struct drm_device *dev = crtc->dev;
3131 struct drm_i915_private *dev_priv = dev->dev_private;
3132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3133 int pipe = intel_crtc->pipe;
ee7b9f93 3134 u32 reg, temp;
2c07245f 3135
ab9412ba 3136 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3137
1fbc0d78
DV		 3138 if (IS_IVYBRIDGE(dev))
3139 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3140
cd986abb
DV		 3141 /* Write the TU size bits before fdi link training, so that error
3142 * detection works. */
3143 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3144 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3145
c98e9dcf 3146 /* For PCH output, training FDI link */
674cf967 3147 dev_priv->display.fdi_link_train(crtc);
2c07245f 3148
3ad8a208
DV		 3149 /* We need to program the right clock selection before writing the pixel
3150 * mutliplier into the DPLL. */
303b81e0 3151 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3152 u32 sel;
4b645f14 3153
c98e9dcf 3154 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3155 temp |= TRANS_DPLL_ENABLE(pipe);
3156 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3157 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3158 temp |= sel;
3159 else
3160 temp &= ~sel;
c98e9dcf 3161 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3162 }
5eddb70b 3163
3ad8a208
DV		 3164 /* XXX: pch pll's can be enabled any time before we enable the PCH
3165 * transcoder, and we actually should do this to not upset any PCH
3166 * transcoder that already use the clock when we share it.
3167 *
3168 * Note that enable_shared_dpll tries to do the right thing, but
3169 * get_shared_dpll unconditionally resets the pll - we need that to have
3170 * the right LVDS enable sequence. */
3171 ironlake_enable_shared_dpll(intel_crtc);
3172
d9b6cb56
JB		 3173 /* set transcoder timing, panel must allow it */
3174 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3175 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3176
303b81e0 3177 intel_fdi_normal_train(crtc);
5e84e1a4 3178
c98e9dcf
JB		 3179 /* For PCH DP, enable TRANS_DP_CTL */
3180 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3181 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3182 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3183 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3184 reg = TRANS_DP_CTL(pipe);
3185 temp = I915_READ(reg);
3186 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3187 TRANS_DP_SYNC_MASK |
3188 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3189 temp |= (TRANS_DP_OUTPUT_ENABLE |
3190 TRANS_DP_ENH_FRAMING);
9325c9f0 3191 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3192
3193 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3194 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3195 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3196 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3197
3198 switch (intel_trans_dp_port_sel(crtc)) {
3199 case PCH_DP_B:
5eddb70b 3200 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3201 break;
3202 case PCH_DP_C:
5eddb70b 3203 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3204 break;
3205 case PCH_DP_D:
5eddb70b 3206 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3207 break;
3208 default:
e95d41e1 3209 BUG();
32f9d658 3210 }
2c07245f 3211
5eddb70b 3212 I915_WRITE(reg, temp);
6be4a607 3213 }
b52eb4dc 3214
b8a4f404 3215 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3216}
3217
1507e5bd
PZ		 3218static void lpt_pch_enable(struct drm_crtc *crtc)
3219{
3220 struct drm_device *dev = crtc->dev;
3221 struct drm_i915_private *dev_priv = dev->dev_private;
3222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3223 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3224
ab9412ba 3225 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3226
8c52b5e8 3227 lpt_program_iclkip(crtc);
1507e5bd 3228
0540e488 3229 /* Set transcoder timing. */
275f01b2 3230 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3231
937bb610 3232 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3233}
3234
e2b78267 3235static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3236{
e2b78267 3237 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3238
3239 if (pll == NULL)
3240 return;
3241
3242 if (pll->refcount == 0) {
46edb027 3243 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3244 return;
3245 }
3246
f4a091c7
DV		 3247 if (--pll->refcount == 0) {
3248 WARN_ON(pll->on);
3249 WARN_ON(pll->active);
3250 }
3251
a43f6e0f 3252 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3253}
3254
b89a1d39 3255static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3256{
e2b78267
DV		 3257 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3258 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3259 enum intel_dpll_id i;
ee7b9f93 3260
ee7b9f93 3261 if (pll) {
46edb027
DV		 3262 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3263 crtc->base.base.id, pll->name);
e2b78267 3264 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3265 }
3266
98b6bd99
DV		 3267 if (HAS_PCH_IBX(dev_priv->dev)) {
3268 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3269 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3270 pll = &dev_priv->shared_dplls[i];
98b6bd99 3271
46edb027
DV		 3272 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3273 crtc->base.base.id, pll->name);
98b6bd99
DV		 3274
3275 goto found;
3276 }
3277
e72f9fbf
DV		 3278 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3279 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3280
3281 /* Only want to check enabled timings first */
3282 if (pll->refcount == 0)
3283 continue;
3284
b89a1d39
DV		 3285 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3286 sizeof(pll->hw_state)) == 0) {
46edb027 3287 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3288 crtc->base.base.id,
46edb027 3289 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3290
3291 goto found;
3292 }
3293 }
3294
3295 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3296 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3297 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3298 if (pll->refcount == 0) {
46edb027
DV		 3299 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3300 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3301 goto found;
3302 }
3303 }
3304
3305 return NULL;
3306
3307found:
a43f6e0f 3308 crtc->config.shared_dpll = i;
46edb027
DV		 3309 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3310 pipe_name(crtc->pipe));
ee7b9f93 3311
cdbd2316 3312 if (pll->active == 0) {
66e985c0
DV		 3313 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3314 sizeof(pll->hw_state));
3315
46edb027 3316 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3317 WARN_ON(pll->on);
e9d6944e 3318 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3319
15bdd4cf 3320 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3321 }
3322 pll->refcount++;
e04c7350 3323
ee7b9f93
JB		 3324 return pll;
3325}
3326
a1520318 3327static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3328{
3329 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3330 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3331 u32 temp;
3332
3333 temp = I915_READ(dslreg);
3334 udelay(500);
3335 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3336 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3337 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3338 }
3339}
3340
b074cec8
JB		 3341static void ironlake_pfit_enable(struct intel_crtc *crtc)
3342{
3343 struct drm_device *dev = crtc->base.dev;
3344 struct drm_i915_private *dev_priv = dev->dev_private;
3345 int pipe = crtc->pipe;
3346
fd4daa9c 3347 if (crtc->config.pch_pfit.enabled) {
b074cec8
JB		 3348 /* Force use of hard-coded filter coefficients
3349 * as some pre-programmed values are broken,
3350 * e.g. x201.
3351 */
3352 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3353 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3354 PF_PIPE_SEL_IVB(pipe));
3355 else
3356 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3357 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3358 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3359 }
3360}
3361
bb53d4ae
VS		 3362static void intel_enable_planes(struct drm_crtc *crtc)
3363{
3364 struct drm_device *dev = crtc->dev;
3365 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3366 struct intel_plane *intel_plane;
3367
3368 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3369 if (intel_plane->pipe == pipe)
3370 intel_plane_restore(&intel_plane->base);
3371}
3372
3373static void intel_disable_planes(struct drm_crtc *crtc)
3374{
3375 struct drm_device *dev = crtc->dev;
3376 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3377 struct intel_plane *intel_plane;
3378
3379 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3380 if (intel_plane->pipe == pipe)
3381 intel_plane_disable(&intel_plane->base);
3382}
3383
20bc8673 3384void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 3385{
3386 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3387
3388 if (!crtc->config.ips_enabled)
3389 return;
3390
3391 /* We can only enable IPS after we enable a plane and wait for a vblank.
3392 * We guarantee that the plane is enabled by calling intel_enable_ips
3393 * only after intel_enable_plane. And intel_enable_plane already waits
3394 * for a vblank, so all we need to do here is to enable the IPS bit. */
3395 assert_plane_enabled(dev_priv, crtc->plane);
2a114cc1
BW		 3396 if (IS_BROADWELL(crtc->base.dev)) {
3397 mutex_lock(&dev_priv->rps.hw_lock);
3398 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3399 mutex_unlock(&dev_priv->rps.hw_lock);
3400 /* Quoting Art Runyan: "its not safe to expect any particular
3401 * value in IPS_CTL bit 31 after enabling IPS through the
3402 * mailbox." Therefore we need to defer waiting on the state
3403 * change.
3404 * TODO: need to fix this for state checker
3405 */
3406 } else {
3407 I915_WRITE(IPS_CTL, IPS_ENABLE);
3408 /* The bit only becomes 1 in the next vblank, so this wait here
3409 * is essentially intel_wait_for_vblank. If we don't have this
3410 * and don't wait for vblanks until the end of crtc_enable, then
3411 * the HW state readout code will complain that the expected
3412 * IPS_CTL value is not the one we read. */
3413 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3414 DRM_ERROR("Timed out waiting for IPS enable\n");
3415 }
d77e4531
PZ		 3416}
3417
20bc8673 3418void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 3419{
3420 struct drm_device *dev = crtc->base.dev;
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422
3423 if (!crtc->config.ips_enabled)
3424 return;
3425
3426 assert_plane_enabled(dev_priv, crtc->plane);
2a114cc1
BW		 3427 if (IS_BROADWELL(crtc->base.dev)) {
3428 mutex_lock(&dev_priv->rps.hw_lock);
3429 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3430 mutex_unlock(&dev_priv->rps.hw_lock);
3431 } else
3432 I915_WRITE(IPS_CTL, 0);
d77e4531
PZ		 3433 POSTING_READ(IPS_CTL);
3434
3435 /* We need to wait for a vblank before we can disable the plane. */
3436 intel_wait_for_vblank(dev, crtc->pipe);
3437}
3438
3439/** Loads the palette/gamma unit for the CRTC with the prepared values */
3440static void intel_crtc_load_lut(struct drm_crtc *crtc)
3441{
3442 struct drm_device *dev = crtc->dev;
3443 struct drm_i915_private *dev_priv = dev->dev_private;
3444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3445 enum pipe pipe = intel_crtc->pipe;
3446 int palreg = PALETTE(pipe);
3447 int i;
3448 bool reenable_ips = false;
3449
3450 /* The clocks have to be on to load the palette. */
3451 if (!crtc->enabled || !intel_crtc->active)
3452 return;
3453
3454 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3456 assert_dsi_pll_enabled(dev_priv);
3457 else
3458 assert_pll_enabled(dev_priv, pipe);
3459 }
3460
3461 /* use legacy palette for Ironlake */
3462 if (HAS_PCH_SPLIT(dev))
3463 palreg = LGC_PALETTE(pipe);
3464
3465 /* Workaround : Do not read or write the pipe palette/gamma data while
3466 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3467 */
3468 if (intel_crtc->config.ips_enabled &&
3469 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3470 GAMMA_MODE_MODE_SPLIT)) {
3471 hsw_disable_ips(intel_crtc);
3472 reenable_ips = true;
3473 }
3474
3475 for (i = 0; i < 256; i++) {
3476 I915_WRITE(palreg + 4 * i,
3477 (intel_crtc->lut_r[i] << 16) |
3478 (intel_crtc->lut_g[i] << 8) |
3479 intel_crtc->lut_b[i]);
3480 }
3481
3482 if (reenable_ips)
3483 hsw_enable_ips(intel_crtc);
3484}
3485
f67a559d
JB		 3486static void ironlake_crtc_enable(struct drm_crtc *crtc)
3487{
3488 struct drm_device *dev = crtc->dev;
3489 struct drm_i915_private *dev_priv = dev->dev_private;
3490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3491 struct intel_encoder *encoder;
f67a559d
JB		 3492 int pipe = intel_crtc->pipe;
3493 int plane = intel_crtc->plane;
f67a559d 3494
08a48469
DV		 3495 WARN_ON(!crtc->enabled);
3496
f67a559d
JB		 3497 if (intel_crtc->active)
3498 return;
3499
3500 intel_crtc->active = true;
8664281b
PZ		 3501
3502 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3503 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3504
f6736a1a 3505 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3506 if (encoder->pre_enable)
3507 encoder->pre_enable(encoder);
f67a559d 3508
5bfe2ac0 3509 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3510 /* Note: FDI PLL enabling _must_ be done before we enable the
3511 * cpu pipes, hence this is separate from all the other fdi/pch
3512 * enabling. */
88cefb6c 3513 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3514 } else {
3515 assert_fdi_tx_disabled(dev_priv, pipe);
3516 assert_fdi_rx_disabled(dev_priv, pipe);
3517 }
f67a559d 3518
b074cec8 3519 ironlake_pfit_enable(intel_crtc);
f67a559d 3520
9c54c0dd
JB		 3521 /*
3522 * On ILK+ LUT must be loaded before the pipe is running but with
3523 * clocks enabled
3524 */
3525 intel_crtc_load_lut(crtc);
3526
f37fcc2a 3527 intel_update_watermarks(crtc);
5bfe2ac0 3528 intel_enable_pipe(dev_priv, pipe,
23538ef1 3529 intel_crtc->config.has_pch_encoder, false);
d1de00ef 3530 intel_enable_primary_plane(dev_priv, plane, pipe);
bb53d4ae 3531 intel_enable_planes(crtc);
5c38d48c 3532 intel_crtc_update_cursor(crtc, true);
f67a559d 3533
5bfe2ac0 3534 if (intel_crtc->config.has_pch_encoder)
f67a559d 3535 ironlake_pch_enable(crtc);
c98e9dcf 3536
d1ebd816 3537 mutex_lock(&dev->struct_mutex);
bed4a673 3538 intel_update_fbc(dev);
d1ebd816
BW		 3539 mutex_unlock(&dev->struct_mutex);
3540
fa5c73b1
DV		 3541 for_each_encoder_on_crtc(dev, crtc, encoder)
3542 encoder->enable(encoder);
61b77ddd
DV		 3543
3544 if (HAS_PCH_CPT(dev))
a1520318 3545 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3546
3547 /*
3548 * There seems to be a race in PCH platform hw (at least on some
3549 * outputs) where an enabled pipe still completes any pageflip right
3550 * away (as if the pipe is off) instead of waiting for vblank. As soon
3551 * as the first vblank happend, everything works as expected. Hence just
3552 * wait for one vblank before returning to avoid strange things
3553 * happening.
3554 */
3555 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3556}
3557
42db64ef
PZ		 3558/* IPS only exists on ULT machines and is tied to pipe A. */
3559static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3560{
f5adf94e 3561 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3562}
3563
dda9a66a
VS		 3564static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3565{
3566 struct drm_device *dev = crtc->dev;
3567 struct drm_i915_private *dev_priv = dev->dev_private;
3568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3569 int pipe = intel_crtc->pipe;
3570 int plane = intel_crtc->plane;
3571
d1de00ef 3572 intel_enable_primary_plane(dev_priv, plane, pipe);
dda9a66a
VS		 3573 intel_enable_planes(crtc);
3574 intel_crtc_update_cursor(crtc, true);
3575
3576 hsw_enable_ips(intel_crtc);
3577
3578 mutex_lock(&dev->struct_mutex);
3579 intel_update_fbc(dev);
3580 mutex_unlock(&dev->struct_mutex);
3581}
3582
3583static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3584{
3585 struct drm_device *dev = crtc->dev;
3586 struct drm_i915_private *dev_priv = dev->dev_private;
3587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3588 int pipe = intel_crtc->pipe;
3589 int plane = intel_crtc->plane;
3590
3591 intel_crtc_wait_for_pending_flips(crtc);
3592 drm_vblank_off(dev, pipe);
3593
3594 /* FBC must be disabled before disabling the plane on HSW. */
3595 if (dev_priv->fbc.plane == plane)
3596 intel_disable_fbc(dev);
3597
3598 hsw_disable_ips(intel_crtc);
3599
3600 intel_crtc_update_cursor(crtc, false);
3601 intel_disable_planes(crtc);
d1de00ef 3602 intel_disable_primary_plane(dev_priv, plane, pipe);
dda9a66a
VS		 3603}
3604
e4916946
PZ		 3605/*
3606 * This implements the workaround described in the "notes" section of the mode
3607 * set sequence documentation. When going from no pipes or single pipe to
3608 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3609 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3610 */
3611static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3612{
3613 struct drm_device *dev = crtc->base.dev;
3614 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3615
3616 /* We want to get the other_active_crtc only if there's only 1 other
3617 * active crtc. */
3618 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3619 if (!crtc_it->active || crtc_it == crtc)
3620 continue;
3621
3622 if (other_active_crtc)
3623 return;
3624
3625 other_active_crtc = crtc_it;
3626 }
3627 if (!other_active_crtc)
3628 return;
3629
3630 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3631 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3632}
3633
4f771f10
PZ		 3634static void haswell_crtc_enable(struct drm_crtc *crtc)
3635{
3636 struct drm_device *dev = crtc->dev;
3637 struct drm_i915_private *dev_priv = dev->dev_private;
3638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3639 struct intel_encoder *encoder;
3640 int pipe = intel_crtc->pipe;
4f771f10
PZ		 3641
3642 WARN_ON(!crtc->enabled);
3643
3644 if (intel_crtc->active)
3645 return;
3646
3647 intel_crtc->active = true;
8664281b
PZ		 3648
3649 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3650 if (intel_crtc->config.has_pch_encoder)
3651 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3652
5bfe2ac0 3653 if (intel_crtc->config.has_pch_encoder)
04945641 3654 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3655
3656 for_each_encoder_on_crtc(dev, crtc, encoder)
3657 if (encoder->pre_enable)
3658 encoder->pre_enable(encoder);
3659
1f544388 3660 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3661
b074cec8 3662 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3663
3664 /*
3665 * On ILK+ LUT must be loaded before the pipe is running but with
3666 * clocks enabled
3667 */
3668 intel_crtc_load_lut(crtc);
3669
1f544388 3670 intel_ddi_set_pipe_settings(crtc);
8228c251 3671 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3672
f37fcc2a 3673 intel_update_watermarks(crtc);
5bfe2ac0 3674 intel_enable_pipe(dev_priv, pipe,
23538ef1 3675 intel_crtc->config.has_pch_encoder, false);
42db64ef 3676
5bfe2ac0 3677 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3678 lpt_pch_enable(crtc);
4f771f10 3679
8807e55b 3680 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3681 encoder->enable(encoder);
8807e55b
JN		 3682 intel_opregion_notify_encoder(encoder, true);
3683 }
4f771f10 3684
e4916946
PZ		 3685 /* If we change the relative order between pipe/planes enabling, we need
3686 * to change the workaround. */
3687 haswell_mode_set_planes_workaround(intel_crtc);
dda9a66a
VS		 3688 haswell_crtc_enable_planes(crtc);
3689
4f771f10
PZ		 3690 /*
3691 * There seems to be a race in PCH platform hw (at least on some
3692 * outputs) where an enabled pipe still completes any pageflip right
3693 * away (as if the pipe is off) instead of waiting for vblank. As soon
3694 * as the first vblank happend, everything works as expected. Hence just
3695 * wait for one vblank before returning to avoid strange things
3696 * happening.
3697 */
3698 intel_wait_for_vblank(dev, intel_crtc->pipe);
3699}
3700
3f8dce3a
DV		 3701static void ironlake_pfit_disable(struct intel_crtc *crtc)
3702{
3703 struct drm_device *dev = crtc->base.dev;
3704 struct drm_i915_private *dev_priv = dev->dev_private;
3705 int pipe = crtc->pipe;
3706
3707 /* To avoid upsetting the power well on haswell only disable the pfit if
3708 * it's in use. The hw state code will make sure we get this right. */
fd4daa9c 3709 if (crtc->config.pch_pfit.enabled) {
3f8dce3a
DV		 3710 I915_WRITE(PF_CTL(pipe), 0);
3711 I915_WRITE(PF_WIN_POS(pipe), 0);
3712 I915_WRITE(PF_WIN_SZ(pipe), 0);
3713 }
3714}
3715
6be4a607
JB		 3716static void ironlake_crtc_disable(struct drm_crtc *crtc)
3717{
3718 struct drm_device *dev = crtc->dev;
3719 struct drm_i915_private *dev_priv = dev->dev_private;
3720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3721 struct intel_encoder *encoder;
6be4a607
JB		 3722 int pipe = intel_crtc->pipe;
3723 int plane = intel_crtc->plane;
5eddb70b 3724 u32 reg, temp;
b52eb4dc 3725
ef9c3aee 3726
f7abfe8b
CW		 3727 if (!intel_crtc->active)
3728 return;
3729
ea9d758d
DV		 3730 for_each_encoder_on_crtc(dev, crtc, encoder)
3731 encoder->disable(encoder);
3732
e6c3a2a6 3733 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3734 drm_vblank_off(dev, pipe);
913d8d11 3735
5c3fe8b0 3736 if (dev_priv->fbc.plane == plane)
973d04f9 3737 intel_disable_fbc(dev);
2c07245f 3738
0d5b8c61 3739 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3740 intel_disable_planes(crtc);
d1de00ef 3741 intel_disable_primary_plane(dev_priv, plane, pipe);
0d5b8c61 3742
d925c59a
DV		 3743 if (intel_crtc->config.has_pch_encoder)
3744 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3745
b24e7179 3746 intel_disable_pipe(dev_priv, pipe);
32f9d658 3747
3f8dce3a 3748 ironlake_pfit_disable(intel_crtc);
2c07245f 3749
bf49ec8c
DV		 3750 for_each_encoder_on_crtc(dev, crtc, encoder)
3751 if (encoder->post_disable)
3752 encoder->post_disable(encoder);
2c07245f 3753
d925c59a
DV		 3754 if (intel_crtc->config.has_pch_encoder) {
3755 ironlake_fdi_disable(crtc);
913d8d11 3756
d925c59a
DV		 3757 ironlake_disable_pch_transcoder(dev_priv, pipe);
3758 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3759
d925c59a
DV		 3760 if (HAS_PCH_CPT(dev)) {
3761 /* disable TRANS_DP_CTL */
3762 reg = TRANS_DP_CTL(pipe);
3763 temp = I915_READ(reg);
3764 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3765 TRANS_DP_PORT_SEL_MASK);
3766 temp |= TRANS_DP_PORT_SEL_NONE;
3767 I915_WRITE(reg, temp);
3768
3769 /* disable DPLL_SEL */
3770 temp = I915_READ(PCH_DPLL_SEL);
11887397 3771 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3772 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3773 }
e3421a18 3774
d925c59a 3775 /* disable PCH DPLL */
e72f9fbf 3776 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3777
d925c59a
DV		 3778 ironlake_fdi_pll_disable(intel_crtc);
3779 }
6b383a7f 3780
f7abfe8b 3781 intel_crtc->active = false;
46ba614c 3782 intel_update_watermarks(crtc);
d1ebd816
BW		 3783
3784 mutex_lock(&dev->struct_mutex);
6b383a7f 3785 intel_update_fbc(dev);
d1ebd816 3786 mutex_unlock(&dev->struct_mutex);
6be4a607 3787}
1b3c7a47 3788
4f771f10 3789static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3790{
4f771f10
PZ		 3791 struct drm_device *dev = crtc->dev;
3792 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3794 struct intel_encoder *encoder;
3795 int pipe = intel_crtc->pipe;
3b117c8f 3796 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3797
4f771f10
PZ		 3798 if (!intel_crtc->active)
3799 return;
3800
dda9a66a
VS		 3801 haswell_crtc_disable_planes(crtc);
3802
8807e55b
JN		 3803 for_each_encoder_on_crtc(dev, crtc, encoder) {
3804 intel_opregion_notify_encoder(encoder, false);
4f771f10 3805 encoder->disable(encoder);
8807e55b 3806 }
4f771f10 3807
8664281b
PZ		 3808 if (intel_crtc->config.has_pch_encoder)
3809 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3810 intel_disable_pipe(dev_priv, pipe);
3811
ad80a810 3812 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3813
3f8dce3a 3814 ironlake_pfit_disable(intel_crtc);
4f771f10 3815
1f544388 3816 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3817
3818 for_each_encoder_on_crtc(dev, crtc, encoder)
3819 if (encoder->post_disable)
3820 encoder->post_disable(encoder);
3821
88adfff1 3822 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3823 lpt_disable_pch_transcoder(dev_priv);
8664281b 3824 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3825 intel_ddi_fdi_disable(crtc);
83616634 3826 }
4f771f10
PZ		 3827
3828 intel_crtc->active = false;
46ba614c 3829 intel_update_watermarks(crtc);
4f771f10
PZ		 3830
3831 mutex_lock(&dev->struct_mutex);
3832 intel_update_fbc(dev);
3833 mutex_unlock(&dev->struct_mutex);
3834}
3835
ee7b9f93
JB		 3836static void ironlake_crtc_off(struct drm_crtc *crtc)
3837{
3838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3839 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3840}
3841
6441ab5f
PZ		 3842static void haswell_crtc_off(struct drm_crtc *crtc)
3843{
3844 intel_ddi_put_crtc_pll(crtc);
3845}
3846
02e792fb
DV		 3847static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3848{
02e792fb 3849 if (!enable && intel_crtc->overlay) {
23f09ce3 3850 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3851 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3852
23f09ce3 3853 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3854 dev_priv->mm.interruptible = false;
3855 (void) intel_overlay_switch_off(intel_crtc->overlay);
3856 dev_priv->mm.interruptible = true;
23f09ce3 3857 mutex_unlock(&dev->struct_mutex);
02e792fb 3858 }
02e792fb 3859
5dcdbcb0
CW		 3860 /* Let userspace switch the overlay on again. In most cases userspace
3861 * has to recompute where to put it anyway.
3862 */
02e792fb
DV		 3863}
3864
61bc95c1
EE		 3865/**
3866 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3867 * cursor plane briefly if not already running after enabling the display
3868 * plane.
3869 * This workaround avoids occasional blank screens when self refresh is
3870 * enabled.
3871 */
3872static void
3873g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3874{
3875 u32 cntl = I915_READ(CURCNTR(pipe));
3876
3877 if ((cntl & CURSOR_MODE) == 0) {
3878 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3879
3880 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3881 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3882 intel_wait_for_vblank(dev_priv->dev, pipe);
3883 I915_WRITE(CURCNTR(pipe), cntl);
3884 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3885 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3886 }
3887}
3888
2dd24552
JB		 3889static void i9xx_pfit_enable(struct intel_crtc *crtc)
3890{
3891 struct drm_device *dev = crtc->base.dev;
3892 struct drm_i915_private *dev_priv = dev->dev_private;
3893 struct intel_crtc_config *pipe_config = &crtc->config;
3894
328d8e82 3895 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3896 return;
3897
2dd24552 3898 /*
c0b03411
DV		 3899 * The panel fitter should only be adjusted whilst the pipe is disabled,
3900 * according to register description and PRM.
2dd24552 3901 */
c0b03411
DV		 3902 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3903 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3904
b074cec8
JB		 3905 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3906 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3907
3908 /* Border color in case we don't scale up to the full screen. Black by
3909 * default, change to something else for debugging. */
3910 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3911}
3912
89b667f8
JB		 3913static void valleyview_crtc_enable(struct drm_crtc *crtc)
3914{
3915 struct drm_device *dev = crtc->dev;
3916 struct drm_i915_private *dev_priv = dev->dev_private;
3917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3918 struct intel_encoder *encoder;
3919 int pipe = intel_crtc->pipe;
3920 int plane = intel_crtc->plane;
23538ef1 3921 bool is_dsi;
89b667f8
JB		 3922
3923 WARN_ON(!crtc->enabled);
3924
3925 if (intel_crtc->active)
3926 return;
3927
3928 intel_crtc->active = true;
89b667f8 3929
89b667f8
JB		 3930 for_each_encoder_on_crtc(dev, crtc, encoder)
3931 if (encoder->pre_pll_enable)
3932 encoder->pre_pll_enable(encoder);
3933
23538ef1
JN		 3934 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3935
e9fd1c02
JN		 3936 if (!is_dsi)
3937 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3938
3939 for_each_encoder_on_crtc(dev, crtc, encoder)
3940 if (encoder->pre_enable)
3941 encoder->pre_enable(encoder);
3942
2dd24552
JB		 3943 i9xx_pfit_enable(intel_crtc);
3944
63cbb074
VS		 3945 intel_crtc_load_lut(crtc);
3946
f37fcc2a 3947 intel_update_watermarks(crtc);
23538ef1 3948 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
d1de00ef 3949 intel_enable_primary_plane(dev_priv, plane, pipe);
bb53d4ae 3950 intel_enable_planes(crtc);
5c38d48c 3951 intel_crtc_update_cursor(crtc, true);
89b667f8 3952
89b667f8 3953 intel_update_fbc(dev);
5004945f
JN		 3954
3955 for_each_encoder_on_crtc(dev, crtc, encoder)
3956 encoder->enable(encoder);
89b667f8
JB		 3957}
3958
0b8765c6 3959static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3960{
3961 struct drm_device *dev = crtc->dev;
79e53945
JB		 3962 struct drm_i915_private *dev_priv = dev->dev_private;
3963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3964 struct intel_encoder *encoder;
79e53945 3965 int pipe = intel_crtc->pipe;
80824003 3966 int plane = intel_crtc->plane;
79e53945 3967
08a48469
DV		 3968 WARN_ON(!crtc->enabled);
3969
f7abfe8b
CW		 3970 if (intel_crtc->active)
3971 return;
3972
3973 intel_crtc->active = true;
6b383a7f 3974
9d6d9f19
MK		 3975 for_each_encoder_on_crtc(dev, crtc, encoder)
3976 if (encoder->pre_enable)
3977 encoder->pre_enable(encoder);
3978
f6736a1a
DV		 3979 i9xx_enable_pll(intel_crtc);
3980
2dd24552
JB		 3981 i9xx_pfit_enable(intel_crtc);
3982
63cbb074
VS		 3983 intel_crtc_load_lut(crtc);
3984
f37fcc2a 3985 intel_update_watermarks(crtc);
23538ef1 3986 intel_enable_pipe(dev_priv, pipe, false, false);
d1de00ef 3987 intel_enable_primary_plane(dev_priv, plane, pipe);
bb53d4ae 3988 intel_enable_planes(crtc);
22e407d7 3989 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3990 if (IS_G4X(dev))
3991 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3992 intel_crtc_update_cursor(crtc, true);
79e53945 3993
0b8765c6
JB		 3994 /* Give the overlay scaler a chance to enable if it's on this pipe */
3995 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3996
f440eb13 3997 intel_update_fbc(dev);
ef9c3aee 3998
fa5c73b1
DV		 3999 for_each_encoder_on_crtc(dev, crtc, encoder)
4000 encoder->enable(encoder);
0b8765c6 4001}
79e53945 4002
87476d63
DV		 4003static void i9xx_pfit_disable(struct intel_crtc *crtc)
4004{
4005 struct drm_device *dev = crtc->base.dev;
4006 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 4007
328d8e82
DV		 4008 if (!crtc->config.gmch_pfit.control)
4009 return;
87476d63 4010
328d8e82 4011 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 4012
328d8e82
DV		 4013 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4014 I915_READ(PFIT_CONTROL));
4015 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 4016}
4017
0b8765c6
JB		 4018static void i9xx_crtc_disable(struct drm_crtc *crtc)
4019{
4020 struct drm_device *dev = crtc->dev;
4021 struct drm_i915_private *dev_priv = dev->dev_private;
4022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4023 struct intel_encoder *encoder;
0b8765c6
JB		 4024 int pipe = intel_crtc->pipe;
4025 int plane = intel_crtc->plane;
ef9c3aee 4026
f7abfe8b
CW		 4027 if (!intel_crtc->active)
4028 return;
4029
ea9d758d
DV		 4030 for_each_encoder_on_crtc(dev, crtc, encoder)
4031 encoder->disable(encoder);
4032
0b8765c6 4033 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 4034 intel_crtc_wait_for_pending_flips(crtc);
4035 drm_vblank_off(dev, pipe);
0b8765c6 4036
5c3fe8b0 4037 if (dev_priv->fbc.plane == plane)
973d04f9 4038 intel_disable_fbc(dev);
79e53945 4039
0d5b8c61
VS		 4040 intel_crtc_dpms_overlay(intel_crtc, false);
4041 intel_crtc_update_cursor(crtc, false);
bb53d4ae 4042 intel_disable_planes(crtc);
d1de00ef 4043 intel_disable_primary_plane(dev_priv, plane, pipe);
0d5b8c61 4044
b24e7179 4045 intel_disable_pipe(dev_priv, pipe);
24a1f16d 4046
87476d63 4047 i9xx_pfit_disable(intel_crtc);
24a1f16d 4048
89b667f8
JB		 4049 for_each_encoder_on_crtc(dev, crtc, encoder)
4050 if (encoder->post_disable)
4051 encoder->post_disable(encoder);
4052
f6071166
JB		 4053 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4054 vlv_disable_pll(dev_priv, pipe);
4055 else if (!IS_VALLEYVIEW(dev))
e9fd1c02 4056 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 4057
f7abfe8b 4058 intel_crtc->active = false;
46ba614c 4059 intel_update_watermarks(crtc);
f37fcc2a 4060
6b383a7f 4061 intel_update_fbc(dev);
0b8765c6
JB		 4062}
4063
ee7b9f93
JB		 4064static void i9xx_crtc_off(struct drm_crtc *crtc)
4065{
4066}
4067
976f8a20
DV		 4068static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4069 bool enabled)
2c07245f
ZW		 4070{
4071 struct drm_device *dev = crtc->dev;
4072 struct drm_i915_master_private *master_priv;
4073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4074 int pipe = intel_crtc->pipe;
79e53945
JB		 4075
4076 if (!dev->primary->master)
4077 return;
4078
4079 master_priv = dev->primary->master->driver_priv;
4080 if (!master_priv->sarea_priv)
4081 return;
4082
79e53945
JB		 4083 switch (pipe) {
4084 case 0:
4085 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4086 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4087 break;
4088 case 1:
4089 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4090 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4091 break;
4092 default:
9db4a9c7 4093 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 4094 break;
4095 }
79e53945
JB		 4096}
4097
976f8a20
DV		 4098/**
4099 * Sets the power management mode of the pipe and plane.
4100 */
4101void intel_crtc_update_dpms(struct drm_crtc *crtc)
4102{
4103 struct drm_device *dev = crtc->dev;
4104 struct drm_i915_private *dev_priv = dev->dev_private;
4105 struct intel_encoder *intel_encoder;
4106 bool enable = false;
4107
4108 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4109 enable |= intel_encoder->connectors_active;
4110
4111 if (enable)
4112 dev_priv->display.crtc_enable(crtc);
4113 else
4114 dev_priv->display.crtc_disable(crtc);
4115
4116 intel_crtc_update_sarea(crtc, enable);
4117}
4118
cdd59983
CW		 4119static void intel_crtc_disable(struct drm_crtc *crtc)
4120{
cdd59983 4121 struct drm_device *dev = crtc->dev;
976f8a20 4122 struct drm_connector *connector;
ee7b9f93 4123 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 4124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 4125
976f8a20
DV		 4126 /* crtc should still be enabled when we disable it. */
4127 WARN_ON(!crtc->enabled);
4128
4129 dev_priv->display.crtc_disable(crtc);
c77bf565 4130 intel_crtc->eld_vld = false;
976f8a20 4131 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 4132 dev_priv->display.off(crtc);
4133
931872fc 4134 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 4135 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 4136 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 4137
4138 if (crtc->fb) {
4139 mutex_lock(&dev->struct_mutex);
1690e1eb 4140 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 4141 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 4142 crtc->fb = NULL;
4143 }
4144
4145 /* Update computed state. */
4146 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4147 if (!connector->encoder || !connector->encoder->crtc)
4148 continue;
4149
4150 if (connector->encoder->crtc != crtc)
4151 continue;
4152
4153 connector->dpms = DRM_MODE_DPMS_OFF;
4154 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 4155 }
4156}
4157
ea5b213a 4158void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 4159{
4ef69c7a 4160 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 4161
ea5b213a
CW		 4162 drm_encoder_cleanup(encoder);
4163 kfree(intel_encoder);
7e7d76c3
JB		 4164}
4165
9237329d 4166/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 4167 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4168 * state of the entire output pipe. */
9237329d 4169static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 4170{
5ab432ef
DV		 4171 if (mode == DRM_MODE_DPMS_ON) {
4172 encoder->connectors_active = true;
4173
b2cabb0e 4174 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 4175 } else {
4176 encoder->connectors_active = false;
4177
b2cabb0e 4178 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 4179 }
79e53945
JB		 4180}
4181
0a91ca29
DV		 4182/* Cross check the actual hw state with our own modeset state tracking (and it's
4183 * internal consistency). */
b980514c 4184static void intel_connector_check_state(struct intel_connector *connector)
79e53945 4185{
0a91ca29
DV		 4186 if (connector->get_hw_state(connector)) {
4187 struct intel_encoder *encoder = connector->encoder;
4188 struct drm_crtc *crtc;
4189 bool encoder_enabled;
4190 enum pipe pipe;
4191
4192 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4193 connector->base.base.id,
4194 drm_get_connector_name(&connector->base));
4195
4196 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4197 "wrong connector dpms state\n");
4198 WARN(connector->base.encoder != &encoder->base,
4199 "active connector not linked to encoder\n");
4200 WARN(!encoder->connectors_active,
4201 "encoder->connectors_active not set\n");
4202
4203 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4204 WARN(!encoder_enabled, "encoder not enabled\n");
4205 if (WARN_ON(!encoder->base.crtc))
4206 return;
4207
4208 crtc = encoder->base.crtc;
4209
4210 WARN(!crtc->enabled, "crtc not enabled\n");
4211 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4212 WARN(pipe != to_intel_crtc(crtc)->pipe,
4213 "encoder active on the wrong pipe\n");
4214 }
79e53945
JB		 4215}
4216
5ab432ef
DV		 4217/* Even simpler default implementation, if there's really no special case to
4218 * consider. */
4219void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4220{
5ab432ef
DV		 4221 /* All the simple cases only support two dpms states. */
4222 if (mode != DRM_MODE_DPMS_ON)
4223 mode = DRM_MODE_DPMS_OFF;
d4270e57 4224
5ab432ef
DV		 4225 if (mode == connector->dpms)
4226 return;
4227
4228 connector->dpms = mode;
4229
4230 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 4231 if (connector->encoder)
4232 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 4233
b980514c 4234 intel_modeset_check_state(connector->dev);
79e53945
JB		 4235}
4236
f0947c37
DV		 4237/* Simple connector->get_hw_state implementation for encoders that support only
4238 * one connector and no cloning and hence the encoder state determines the state
4239 * of the connector. */
4240bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4241{
24929352 4242 enum pipe pipe = 0;
f0947c37 4243 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4244
f0947c37 4245 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4246}
4247
1857e1da
DV		 4248static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4249 struct intel_crtc_config *pipe_config)
4250{
4251 struct drm_i915_private *dev_priv = dev->dev_private;
4252 struct intel_crtc *pipe_B_crtc =
4253 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4254
4255 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4256 pipe_name(pipe), pipe_config->fdi_lanes);
4257 if (pipe_config->fdi_lanes > 4) {
4258 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4259 pipe_name(pipe), pipe_config->fdi_lanes);
4260 return false;
4261 }
4262
bafb6553 4263 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 4264 if (pipe_config->fdi_lanes > 2) {
4265 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4266 pipe_config->fdi_lanes);
4267 return false;
4268 } else {
4269 return true;
4270 }
4271 }
4272
4273 if (INTEL_INFO(dev)->num_pipes == 2)
4274 return true;
4275
4276 /* Ivybridge 3 pipe is really complicated */
4277 switch (pipe) {
4278 case PIPE_A:
4279 return true;
4280 case PIPE_B:
4281 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4282 pipe_config->fdi_lanes > 2) {
4283 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4284 pipe_name(pipe), pipe_config->fdi_lanes);
4285 return false;
4286 }
4287 return true;
4288 case PIPE_C:
1e833f40 4289 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4290 pipe_B_crtc->config.fdi_lanes <= 2) {
4291 if (pipe_config->fdi_lanes > 2) {
4292 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4293 pipe_name(pipe), pipe_config->fdi_lanes);
4294 return false;
4295 }
4296 } else {
4297 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4298 return false;
4299 }
4300 return true;
4301 default:
4302 BUG();
4303 }
4304}
4305
e29c22c0
DV		 4306#define RETRY 1
4307static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4308 struct intel_crtc_config *pipe_config)
877d48d5 4309{
1857e1da 4310 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4311 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4312 int lane, link_bw, fdi_dotclock;
e29c22c0 4313 bool setup_ok, needs_recompute = false;
877d48d5 4314
e29c22c0 4315retry:
877d48d5
DV		 4316 /* FDI is a binary signal running at ~2.7GHz, encoding
4317 * each output octet as 10 bits. The actual frequency
4318 * is stored as a divider into a 100MHz clock, and the
4319 * mode pixel clock is stored in units of 1KHz.
4320 * Hence the bw of each lane in terms of the mode signal
4321 * is:
4322 */
4323 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4324
241bfc38 4325 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 4326
2bd89a07 4327 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4328 pipe_config->pipe_bpp);
4329
4330 pipe_config->fdi_lanes = lane;
4331
2bd89a07 4332 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4333 link_bw, &pipe_config->fdi_m_n);
1857e1da 4334
e29c22c0
DV		 4335 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4336 intel_crtc->pipe, pipe_config);
4337 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4338 pipe_config->pipe_bpp -= 2*3;
4339 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4340 pipe_config->pipe_bpp);
4341 needs_recompute = true;
4342 pipe_config->bw_constrained = true;
4343
4344 goto retry;
4345 }
4346
4347 if (needs_recompute)
4348 return RETRY;
4349
4350 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4351}
4352
42db64ef
PZ		 4353static void hsw_compute_ips_config(struct intel_crtc *crtc,
4354 struct intel_crtc_config *pipe_config)
4355{
3c4ca58c
PZ		 4356 pipe_config->ips_enabled = i915_enable_ips &&
4357 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4358 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4359}
4360
a43f6e0f 4361static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4362 struct intel_crtc_config *pipe_config)
79e53945 4363{
a43f6e0f 4364 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4365 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4366
ad3a4479 4367 /* FIXME should check pixel clock limits on all platforms */
cf532bb2
VS		 4368 if (INTEL_INFO(dev)->gen < 4) {
4369 struct drm_i915_private *dev_priv = dev->dev_private;
4370 int clock_limit =
4371 dev_priv->display.get_display_clock_speed(dev);
4372
4373 /*
4374 * Enable pixel doubling when the dot clock
4375 * is > 90% of the (display) core speed.
4376 *
b397c96b
VS		 4377 * GDG double wide on either pipe,
4378 * otherwise pipe A only.
cf532bb2 4379 */
b397c96b 4380 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 4381 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 4382 clock_limit *= 2;
cf532bb2 4383 pipe_config->double_wide = true;
ad3a4479
VS		 4384 }
4385
241bfc38 4386 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 4387 return -EINVAL;
2c07245f 4388 }
89749350 4389
1d1d0e27
VS		 4390 /*
4391 * Pipe horizontal size must be even in:
4392 * - DVO ganged mode
4393 * - LVDS dual channel mode
4394 * - Double wide pipe
4395 */
4396 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4397 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4398 pipe_config->pipe_src_w &= ~1;
4399
8693a824
DL		 4400 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4401 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4402 */
4403 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4404 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4405 return -EINVAL;
44f46b42 4406
bd080ee5 4407 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4408 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4409 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4410 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4411 * for lvds. */
4412 pipe_config->pipe_bpp = 8*3;
4413 }
4414
f5adf94e 4415 if (HAS_IPS(dev))
a43f6e0f
DV		 4416 hsw_compute_ips_config(crtc, pipe_config);
4417
4418 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4419 * clock survives for now. */
4420 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4421 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4422
877d48d5 4423 if (pipe_config->has_pch_encoder)
a43f6e0f 4424 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4425
e29c22c0 4426 return 0;
79e53945
JB		 4427}
4428
25eb05fc
JB		 4429static int valleyview_get_display_clock_speed(struct drm_device *dev)
4430{
4431 return 400000; /* FIXME */
4432}
4433
e70236a8
JB		 4434static int i945_get_display_clock_speed(struct drm_device *dev)
4435{
4436 return 400000;
4437}
79e53945 4438
e70236a8 4439static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4440{
e70236a8
JB		 4441 return 333000;
4442}
79e53945 4443
e70236a8
JB		 4444static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4445{
4446 return 200000;
4447}
79e53945 4448
257a7ffc
DV		 4449static int pnv_get_display_clock_speed(struct drm_device *dev)
4450{
4451 u16 gcfgc = 0;
4452
4453 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4454
4455 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4456 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4457 return 267000;
4458 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4459 return 333000;
4460 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4461 return 444000;
4462 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4463 return 200000;
4464 default:
4465 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4466 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4467 return 133000;
4468 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4469 return 167000;
4470 }
4471}
4472
e70236a8
JB		 4473static int i915gm_get_display_clock_speed(struct drm_device *dev)
4474{
4475 u16 gcfgc = 0;
79e53945 4476
e70236a8
JB		 4477 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4478
4479 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4480 return 133000;
4481 else {
4482 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4483 case GC_DISPLAY_CLOCK_333_MHZ:
4484 return 333000;
4485 default:
4486 case GC_DISPLAY_CLOCK_190_200_MHZ:
4487 return 190000;
79e53945 4488 }
e70236a8
JB		 4489 }
4490}
4491
4492static int i865_get_display_clock_speed(struct drm_device *dev)
4493{
4494 return 266000;
4495}
4496
4497static int i855_get_display_clock_speed(struct drm_device *dev)
4498{
4499 u16 hpllcc = 0;
4500 /* Assume that the hardware is in the high speed state. This
4501 * should be the default.
4502 */
4503 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4504 case GC_CLOCK_133_200:
4505 case GC_CLOCK_100_200:
4506 return 200000;
4507 case GC_CLOCK_166_250:
4508 return 250000;
4509 case GC_CLOCK_100_133:
79e53945 4510 return 133000;
e70236a8 4511 }
79e53945 4512
e70236a8
JB		 4513 /* Shouldn't happen */
4514 return 0;
4515}
79e53945 4516
e70236a8
JB		 4517static int i830_get_display_clock_speed(struct drm_device *dev)
4518{
4519 return 133000;
79e53945
JB		 4520}
4521
2c07245f 4522static void
a65851af 4523intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4524{
a65851af
VS		 4525 while (*num > DATA_LINK_M_N_MASK ||
4526 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4527 *num >>= 1;
4528 *den >>= 1;
4529 }
4530}
4531
a65851af
VS		 4532static void compute_m_n(unsigned int m, unsigned int n,
4533 uint32_t *ret_m, uint32_t *ret_n)
4534{
4535 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4536 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4537 intel_reduce_m_n_ratio(ret_m, ret_n);
4538}
4539
e69d0bc1
DV		 4540void
4541intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4542 int pixel_clock, int link_clock,
4543 struct intel_link_m_n *m_n)
2c07245f 4544{
e69d0bc1 4545 m_n->tu = 64;
a65851af
VS		 4546
4547 compute_m_n(bits_per_pixel * pixel_clock,
4548 link_clock * nlanes * 8,
4549 &m_n->gmch_m, &m_n->gmch_n);
4550
4551 compute_m_n(pixel_clock, link_clock,
4552 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4553}
4554
a7615030
CW		 4555static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4556{
72bbe58c
KP		 4557 if (i915_panel_use_ssc >= 0)
4558 return i915_panel_use_ssc != 0;
41aa3448 4559 return dev_priv->vbt.lvds_use_ssc
435793df 4560 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4561}
4562
c65d77d8
JB		 4563static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4564{
4565 struct drm_device *dev = crtc->dev;
4566 struct drm_i915_private *dev_priv = dev->dev_private;
4567 int refclk;
4568
a0c4da24 4569 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4570 refclk = 100000;
a0c4da24 4571 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4572 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4573 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4574 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4575 refclk / 1000);
4576 } else if (!IS_GEN2(dev)) {
4577 refclk = 96000;
4578 } else {
4579 refclk = 48000;
4580 }
4581
4582 return refclk;
4583}
4584
7429e9d4 4585static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4586{
7df00d7a 4587 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4588}
f47709a9 4589
7429e9d4
DV		 4590static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4591{
4592 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4593}
4594
f47709a9 4595static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4596 intel_clock_t *reduced_clock)
4597{
f47709a9 4598 struct drm_device *dev = crtc->base.dev;
a7516a05 4599 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4600 int pipe = crtc->pipe;
a7516a05
JB		 4601 u32 fp, fp2 = 0;
4602
4603 if (IS_PINEVIEW(dev)) {
7429e9d4 4604 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4605 if (reduced_clock)
7429e9d4 4606 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4607 } else {
7429e9d4 4608 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4609 if (reduced_clock)
7429e9d4 4610 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4611 }
4612
4613 I915_WRITE(FP0(pipe), fp);
8bcc2795 4614 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4615
f47709a9
DV		 4616 crtc->lowfreq_avail = false;
4617 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4618 reduced_clock && i915_powersave) {
4619 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4620 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4621 crtc->lowfreq_avail = true;
a7516a05
JB		 4622 } else {
4623 I915_WRITE(FP1(pipe), fp);
8bcc2795 4624 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4625 }
4626}
4627
5e69f97f
CML		 4628static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4629 pipe)
89b667f8
JB		 4630{
4631 u32 reg_val;
4632
4633 /*
4634 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4635 * and set it to a reasonable value instead.
4636 */
5e69f97f 4637 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4638 reg_val &= 0xffffff00;
4639 reg_val |= 0x00000030;
5e69f97f 4640 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4641
5e69f97f 4642 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4643 reg_val &= 0x8cffffff;
4644 reg_val = 0x8c000000;
5e69f97f 4645 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4646
5e69f97f 4647 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4648 reg_val &= 0xffffff00;
5e69f97f 4649 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4650
5e69f97f 4651 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4652 reg_val &= 0x00ffffff;
4653 reg_val |= 0xb0000000;
5e69f97f 4654 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4655}
4656
b551842d
DV		 4657static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4658 struct intel_link_m_n *m_n)
4659{
4660 struct drm_device *dev = crtc->base.dev;
4661 struct drm_i915_private *dev_priv = dev->dev_private;
4662 int pipe = crtc->pipe;
4663
e3b95f1e
DV		 4664 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4665 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4666 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4667 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4668}
4669
4670static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4671 struct intel_link_m_n *m_n)
4672{
4673 struct drm_device *dev = crtc->base.dev;
4674 struct drm_i915_private *dev_priv = dev->dev_private;
4675 int pipe = crtc->pipe;
4676 enum transcoder transcoder = crtc->config.cpu_transcoder;
4677
4678 if (INTEL_INFO(dev)->gen >= 5) {
4679 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4680 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4681 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4682 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4683 } else {
e3b95f1e
DV		 4684 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4685 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4686 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4687 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4688 }
4689}
4690
03afc4a2
DV		 4691static void intel_dp_set_m_n(struct intel_crtc *crtc)
4692{
4693 if (crtc->config.has_pch_encoder)
4694 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4695 else
4696 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4697}
4698
f47709a9 4699static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4700{
f47709a9 4701 struct drm_device *dev = crtc->base.dev;
a0c4da24 4702 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4703 int pipe = crtc->pipe;
89b667f8 4704 u32 dpll, mdiv;
a0c4da24 4705 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4706 u32 coreclk, reg_val, dpll_md;
a0c4da24 4707
09153000
DV		 4708 mutex_lock(&dev_priv->dpio_lock);
4709
f47709a9
DV		 4710 bestn = crtc->config.dpll.n;
4711 bestm1 = crtc->config.dpll.m1;
4712 bestm2 = crtc->config.dpll.m2;
4713 bestp1 = crtc->config.dpll.p1;
4714 bestp2 = crtc->config.dpll.p2;
a0c4da24 4715
89b667f8
JB		 4716 /* See eDP HDMI DPIO driver vbios notes doc */
4717
4718 /* PLL B needs special handling */
4719 if (pipe)
5e69f97f 4720 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4721
4722 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4723 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4724
4725 /* Disable target IRef on PLL */
5e69f97f 4726 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4727 reg_val &= 0x00ffffff;
5e69f97f 4728 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4729
4730 /* Disable fast lock */
5e69f97f 4731 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4732
4733 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4734 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4735 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4736 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4737 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4738
4739 /*
4740 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4741 * but we don't support that).
4742 * Note: don't use the DAC post divider as it seems unstable.
4743 */
4744 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4745 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4746
a0c4da24 4747 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4748 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4749
89b667f8 4750 /* Set HBR and RBR LPF coefficients */
ff9a6750 4751 if (crtc->config.port_clock == 162000 ||
99750bd4 4752 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4753 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4754 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4755 0x009f0003);
89b667f8 4756 else
5e69f97f 4757 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4758 0x00d0000f);
4759
4760 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4761 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4762 /* Use SSC source */
4763 if (!pipe)
5e69f97f 4764 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4765 0x0df40000);
4766 else
5e69f97f 4767 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4768 0x0df70000);
4769 } else { /* HDMI or VGA */
4770 /* Use bend source */
4771 if (!pipe)
5e69f97f 4772 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4773 0x0df70000);
4774 else
5e69f97f 4775 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4776 0x0df40000);
4777 }
a0c4da24 4778
5e69f97f 4779 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4780 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4781 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4782 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4783 coreclk |= 0x01000000;
5e69f97f 4784 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4785
5e69f97f 4786 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4787
89b667f8
JB		 4788 /* Enable DPIO clock input */
4789 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4790 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
f6071166
JB		 4791 /* We should never disable this, set it here for state tracking */
4792 if (pipe == PIPE_B)
89b667f8 4793 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24 4794 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4795 crtc->config.dpll_hw_state.dpll = dpll;
4796
ef1b460d
DV		 4797 dpll_md = (crtc->config.pixel_multiplier - 1)
4798 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4799 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4800
89b667f8
JB		 4801 if (crtc->config.has_dp_encoder)
4802 intel_dp_set_m_n(crtc);
09153000
DV		 4803
4804 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4805}
4806
f47709a9
DV		 4807static void i9xx_update_pll(struct intel_crtc *crtc,
4808 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4809 int num_connectors)
4810{
f47709a9 4811 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4812 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4813 u32 dpll;
4814 bool is_sdvo;
f47709a9 4815 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4816
f47709a9 4817 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4818
f47709a9
DV		 4819 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4820 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4821
4822 dpll = DPLL_VGA_MODE_DIS;
4823
f47709a9 4824 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4825 dpll |= DPLLB_MODE_LVDS;
4826 else
4827 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4828
ef1b460d 4829 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4830 dpll |= (crtc->config.pixel_multiplier - 1)
4831 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4832 }
198a037f
DV		 4833
4834 if (is_sdvo)
4a33e48d 4835 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4836
f47709a9 4837 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4838 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4839
4840 /* compute bitmask from p1 value */
4841 if (IS_PINEVIEW(dev))
4842 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4843 else {
4844 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4845 if (IS_G4X(dev) && reduced_clock)
4846 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4847 }
4848 switch (clock->p2) {
4849 case 5:
4850 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4851 break;
4852 case 7:
4853 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4854 break;
4855 case 10:
4856 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4857 break;
4858 case 14:
4859 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4860 break;
4861 }
4862 if (INTEL_INFO(dev)->gen >= 4)
4863 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4864
09ede541 4865 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4866 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4867 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4868 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4869 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4870 else
4871 dpll |= PLL_REF_INPUT_DREFCLK;
4872
4873 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4874 crtc->config.dpll_hw_state.dpll = dpll;
4875
eb1cbe48 4876 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4877 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4878 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4879 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4880 }
66e3d5c0
DV		 4881
4882 if (crtc->config.has_dp_encoder)
4883 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4884}
4885
f47709a9 4886static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4887 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4888 int num_connectors)
4889{
f47709a9 4890 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4891 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4892 u32 dpll;
f47709a9 4893 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4894
f47709a9 4895 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4896
eb1cbe48
DV		 4897 dpll = DPLL_VGA_MODE_DIS;
4898
f47709a9 4899 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4900 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4901 } else {
4902 if (clock->p1 == 2)
4903 dpll |= PLL_P1_DIVIDE_BY_TWO;
4904 else
4905 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4906 if (clock->p2 == 4)
4907 dpll |= PLL_P2_DIVIDE_BY_4;
4908 }
4909
4a33e48d
DV		 4910 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4911 dpll |= DPLL_DVO_2X_MODE;
4912
f47709a9 4913 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4914 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4915 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4916 else
4917 dpll |= PLL_REF_INPUT_DREFCLK;
4918
4919 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4920 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4921}
4922
8a654f3b 4923static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4924{
4925 struct drm_device *dev = intel_crtc->base.dev;
4926 struct drm_i915_private *dev_priv = dev->dev_private;
4927 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4928 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4929 struct drm_display_mode *adjusted_mode =
4930 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4931 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4932
4933 /* We need to be careful not to changed the adjusted mode, for otherwise
4934 * the hw state checker will get angry at the mismatch. */
4935 crtc_vtotal = adjusted_mode->crtc_vtotal;
4936 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4937
4938 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4939 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4940 crtc_vtotal -= 1;
4941 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4942 vsyncshift = adjusted_mode->crtc_hsync_start
4943 - adjusted_mode->crtc_htotal / 2;
4944 } else {
4945 vsyncshift = 0;
4946 }
4947
4948 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4949 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4950
fe2b8f9d 4951 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4952 (adjusted_mode->crtc_hdisplay - 1) |
4953 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4954 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4955 (adjusted_mode->crtc_hblank_start - 1) |
4956 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4957 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4958 (adjusted_mode->crtc_hsync_start - 1) |
4959 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4960
fe2b8f9d 4961 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4962 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4963 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4964 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4965 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4966 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4967 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4968 (adjusted_mode->crtc_vsync_start - 1) |
4969 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4970
b5e508d4
PZ		 4971 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4972 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4973 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4974 * bits. */
4975 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4976 (pipe == PIPE_B || pipe == PIPE_C))
4977 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4978
b0e77b9c
PZ		 4979 /* pipesrc controls the size that is scaled from, which should
4980 * always be the user's requested size.
4981 */
4982 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4983 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4984 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4985}
4986
1bd1bd80
DV		 4987static void intel_get_pipe_timings(struct intel_crtc *crtc,
4988 struct intel_crtc_config *pipe_config)
4989{
4990 struct drm_device *dev = crtc->base.dev;
4991 struct drm_i915_private *dev_priv = dev->dev_private;
4992 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4993 uint32_t tmp;
4994
4995 tmp = I915_READ(HTOTAL(cpu_transcoder));
4996 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4997 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4998 tmp = I915_READ(HBLANK(cpu_transcoder));
4999 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5000 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5001 tmp = I915_READ(HSYNC(cpu_transcoder));
5002 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5003 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5004
5005 tmp = I915_READ(VTOTAL(cpu_transcoder));
5006 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5007 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5008 tmp = I915_READ(VBLANK(cpu_transcoder));
5009 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5010 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5011 tmp = I915_READ(VSYNC(cpu_transcoder));
5012 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5013 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5014
5015 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5016 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5017 pipe_config->adjusted_mode.crtc_vtotal += 1;
5018 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5019 }
5020
5021 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 5022 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5023 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5024
5025 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5026 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 5027}
5028
babea61d
JB		 5029static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5030 struct intel_crtc_config *pipe_config)
5031{
5032 struct drm_crtc *crtc = &intel_crtc->base;
5033
5034 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5035 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5036 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5037 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5038
5039 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5040 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5041 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5042 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5043
5044 crtc->mode.flags = pipe_config->adjusted_mode.flags;
5045
241bfc38 5046 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
babea61d
JB		 5047 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5048}
5049
84b046f3
DV		 5050static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5051{
5052 struct drm_device *dev = intel_crtc->base.dev;
5053 struct drm_i915_private *dev_priv = dev->dev_private;
5054 uint32_t pipeconf;
5055
9f11a9e4 5056 pipeconf = 0;
84b046f3 5057
67c72a12
DV		 5058 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5059 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5060 pipeconf |= PIPECONF_ENABLE;
5061
cf532bb2
VS		 5062 if (intel_crtc->config.double_wide)
5063 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 5064
ff9ce46e
DV		 5065 /* only g4x and later have fancy bpc/dither controls */
5066 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 5067 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5068 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5069 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 5070 PIPECONF_DITHER_TYPE_SP;
84b046f3 5071
ff9ce46e
DV		 5072 switch (intel_crtc->config.pipe_bpp) {
5073 case 18:
5074 pipeconf |= PIPECONF_6BPC;
5075 break;
5076 case 24:
5077 pipeconf |= PIPECONF_8BPC;
5078 break;
5079 case 30:
5080 pipeconf |= PIPECONF_10BPC;
5081 break;
5082 default:
5083 /* Case prevented by intel_choose_pipe_bpp_dither. */
5084 BUG();
84b046f3
DV		 5085 }
5086 }
5087
5088 if (HAS_PIPE_CXSR(dev)) {
5089 if (intel_crtc->lowfreq_avail) {
5090 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5091 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5092 } else {
5093 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 5094 }
5095 }
5096
84b046f3
DV		 5097 if (!IS_GEN2(dev) &&
5098 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5099 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5100 else
5101 pipeconf |= PIPECONF_PROGRESSIVE;
5102
9f11a9e4
DV		 5103 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5104 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 5105
84b046f3
DV		 5106 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5107 POSTING_READ(PIPECONF(intel_crtc->pipe));
5108}
5109
f564048e 5110static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5111 int x, int y,
94352cf9 5112 struct drm_framebuffer *fb)
79e53945
JB		 5113{
5114 struct drm_device *dev = crtc->dev;
5115 struct drm_i915_private *dev_priv = dev->dev_private;
5116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5117 int pipe = intel_crtc->pipe;
80824003 5118 int plane = intel_crtc->plane;
c751ce4f 5119 int refclk, num_connectors = 0;
652c393a 5120 intel_clock_t clock, reduced_clock;
84b046f3 5121 u32 dspcntr;
a16af721 5122 bool ok, has_reduced_clock = false;
e9fd1c02 5123 bool is_lvds = false, is_dsi = false;
5eddb70b 5124 struct intel_encoder *encoder;
d4906093 5125 const intel_limit_t *limit;
5c3b82e2 5126 int ret;
79e53945 5127
6c2b7c12 5128 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 5129 switch (encoder->type) {
79e53945
JB		 5130 case INTEL_OUTPUT_LVDS:
5131 is_lvds = true;
5132 break;
e9fd1c02
JN		 5133 case INTEL_OUTPUT_DSI:
5134 is_dsi = true;
5135 break;
79e53945 5136 }
43565a06 5137
c751ce4f 5138 num_connectors++;
79e53945
JB		 5139 }
5140
f2335330
JN		 5141 if (is_dsi)
5142 goto skip_dpll;
5143
5144 if (!intel_crtc->config.clock_set) {
5145 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5146
e9fd1c02
JN		 5147 /*
5148 * Returns a set of divisors for the desired target clock with
5149 * the given refclk, or FALSE. The returned values represent
5150 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5151 * 2) / p1 / p2.
5152 */
5153 limit = intel_limit(crtc, refclk);
5154 ok = dev_priv->display.find_dpll(limit, crtc,
5155 intel_crtc->config.port_clock,
5156 refclk, NULL, &clock);
f2335330 5157 if (!ok) {
e9fd1c02
JN		 5158 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5159 return -EINVAL;
5160 }
79e53945 5161
f2335330
JN		 5162 if (is_lvds && dev_priv->lvds_downclock_avail) {
5163 /*
5164 * Ensure we match the reduced clock's P to the target
5165 * clock. If the clocks don't match, we can't switch
5166 * the display clock by using the FP0/FP1. In such case
5167 * we will disable the LVDS downclock feature.
5168 */
5169 has_reduced_clock =
5170 dev_priv->display.find_dpll(limit, crtc,
5171 dev_priv->lvds_downclock,
5172 refclk, &clock,
5173 &reduced_clock);
5174 }
5175 /* Compat-code for transition, will disappear. */
f47709a9
DV		 5176 intel_crtc->config.dpll.n = clock.n;
5177 intel_crtc->config.dpll.m1 = clock.m1;
5178 intel_crtc->config.dpll.m2 = clock.m2;
5179 intel_crtc->config.dpll.p1 = clock.p1;
5180 intel_crtc->config.dpll.p2 = clock.p2;
5181 }
7026d4ac 5182
e9fd1c02 5183 if (IS_GEN2(dev)) {
8a654f3b 5184 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 5185 has_reduced_clock ? &reduced_clock : NULL,
5186 num_connectors);
e9fd1c02 5187 } else if (IS_VALLEYVIEW(dev)) {
f2335330 5188 vlv_update_pll(intel_crtc);
e9fd1c02 5189 } else {
f47709a9 5190 i9xx_update_pll(intel_crtc,
eb1cbe48 5191 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 5192 num_connectors);
e9fd1c02 5193 }
79e53945 5194
f2335330 5195skip_dpll:
79e53945
JB		 5196 /* Set up the display plane register */
5197 dspcntr = DISPPLANE_GAMMA_ENABLE;
5198
da6ecc5d
JB		 5199 if (!IS_VALLEYVIEW(dev)) {
5200 if (pipe == 0)
5201 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5202 else
5203 dspcntr |= DISPPLANE_SEL_PIPE_B;
5204 }
79e53945 5205
8a654f3b 5206 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 5207
5208 /* pipesrc and dspsize control the size that is scaled from,
5209 * which should always be the user's requested size.
79e53945 5210 */
929c77fb 5211 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 5212 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5213 (intel_crtc->config.pipe_src_w - 1));
929c77fb 5214 I915_WRITE(DSPPOS(plane), 0);
2c07245f 5215
84b046f3
DV		 5216 i9xx_set_pipeconf(intel_crtc);
5217
f564048e
EA		 5218 I915_WRITE(DSPCNTR(plane), dspcntr);
5219 POSTING_READ(DSPCNTR(plane));
5220
94352cf9 5221 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 5222
f564048e
EA		 5223 return ret;
5224}
5225
2fa2fe9a
DV		 5226static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5227 struct intel_crtc_config *pipe_config)
5228{
5229 struct drm_device *dev = crtc->base.dev;
5230 struct drm_i915_private *dev_priv = dev->dev_private;
5231 uint32_t tmp;
5232
5233 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5234 if (!(tmp & PFIT_ENABLE))
5235 return;
2fa2fe9a 5236
06922821 5237 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5238 if (INTEL_INFO(dev)->gen < 4) {
5239 if (crtc->pipe != PIPE_B)
5240 return;
2fa2fe9a
DV		 5241 } else {
5242 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5243 return;
5244 }
5245
06922821 5246 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5247 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5248 if (INTEL_INFO(dev)->gen < 5)
5249 pipe_config->gmch_pfit.lvds_border_bits =
5250 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5251}
5252
acbec814
JB		 5253static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5254 struct intel_crtc_config *pipe_config)
5255{
5256 struct drm_device *dev = crtc->base.dev;
5257 struct drm_i915_private *dev_priv = dev->dev_private;
5258 int pipe = pipe_config->cpu_transcoder;
5259 intel_clock_t clock;
5260 u32 mdiv;
662c6ecb 5261 int refclk = 100000;
acbec814
JB		 5262
5263 mutex_lock(&dev_priv->dpio_lock);
5264 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5265 mutex_unlock(&dev_priv->dpio_lock);
5266
5267 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5268 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5269 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5270 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5271 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5272
f646628b 5273 vlv_clock(refclk, &clock);
acbec814 5274
f646628b
VS		 5275 /* clock.dot is the fast clock */
5276 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 5277}
5278
0e8ffe1b
DV		 5279static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5280 struct intel_crtc_config *pipe_config)
5281{
5282 struct drm_device *dev = crtc->base.dev;
5283 struct drm_i915_private *dev_priv = dev->dev_private;
5284 uint32_t tmp;
5285
e143a21c 5286 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5287 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5288
0e8ffe1b
DV		 5289 tmp = I915_READ(PIPECONF(crtc->pipe));
5290 if (!(tmp & PIPECONF_ENABLE))
5291 return false;
5292
42571aef
VS		 5293 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5294 switch (tmp & PIPECONF_BPC_MASK) {
5295 case PIPECONF_6BPC:
5296 pipe_config->pipe_bpp = 18;
5297 break;
5298 case PIPECONF_8BPC:
5299 pipe_config->pipe_bpp = 24;
5300 break;
5301 case PIPECONF_10BPC:
5302 pipe_config->pipe_bpp = 30;
5303 break;
5304 default:
5305 break;
5306 }
5307 }
5308
282740f7
VS		 5309 if (INTEL_INFO(dev)->gen < 4)
5310 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5311
1bd1bd80
DV		 5312 intel_get_pipe_timings(crtc, pipe_config);
5313
2fa2fe9a
DV		 5314 i9xx_get_pfit_config(crtc, pipe_config);
5315
6c49f241
DV		 5316 if (INTEL_INFO(dev)->gen >= 4) {
5317 tmp = I915_READ(DPLL_MD(crtc->pipe));
5318 pipe_config->pixel_multiplier =
5319 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5320 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5321 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5322 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5323 tmp = I915_READ(DPLL(crtc->pipe));
5324 pipe_config->pixel_multiplier =
5325 ((tmp & SDVO_MULTIPLIER_MASK)
5326 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5327 } else {
5328 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5329 * port and will be fixed up in the encoder->get_config
5330 * function. */
5331 pipe_config->pixel_multiplier = 1;
5332 }
8bcc2795
DV		 5333 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5334 if (!IS_VALLEYVIEW(dev)) {
5335 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5336 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5337 } else {
5338 /* Mask out read-only status bits. */
5339 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5340 DPLL_PORTC_READY_MASK |
5341 DPLL_PORTB_READY_MASK);
8bcc2795 5342 }
6c49f241 5343
acbec814
JB		 5344 if (IS_VALLEYVIEW(dev))
5345 vlv_crtc_clock_get(crtc, pipe_config);
5346 else
5347 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 5348
0e8ffe1b
DV		 5349 return true;
5350}
5351
dde86e2d 5352static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5353{
5354 struct drm_i915_private *dev_priv = dev->dev_private;
5355 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5356 struct intel_encoder *encoder;
74cfd7ac 5357 u32 val, final;
13d83a67 5358 bool has_lvds = false;
199e5d79 5359 bool has_cpu_edp = false;
199e5d79 5360 bool has_panel = false;
99eb6a01
KP		 5361 bool has_ck505 = false;
5362 bool can_ssc = false;
13d83a67
JB		 5363
5364 /* We need to take the global config into account */
199e5d79
KP		 5365 list_for_each_entry(encoder, &mode_config->encoder_list,
5366 base.head) {
5367 switch (encoder->type) {
5368 case INTEL_OUTPUT_LVDS:
5369 has_panel = true;
5370 has_lvds = true;
5371 break;
5372 case INTEL_OUTPUT_EDP:
5373 has_panel = true;
2de6905f 5374 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5375 has_cpu_edp = true;
5376 break;
13d83a67
JB		 5377 }
5378 }
5379
99eb6a01 5380 if (HAS_PCH_IBX(dev)) {
41aa3448 5381 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5382 can_ssc = has_ck505;
5383 } else {
5384 has_ck505 = false;
5385 can_ssc = true;
5386 }
5387
2de6905f
ID		 5388 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5389 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5390
5391 /* Ironlake: try to setup display ref clock before DPLL
5392 * enabling. This is only under driver's control after
5393 * PCH B stepping, previous chipset stepping should be
5394 * ignoring this setting.
5395 */
74cfd7ac
CW		 5396 val = I915_READ(PCH_DREF_CONTROL);
5397
5398 /* As we must carefully and slowly disable/enable each source in turn,
5399 * compute the final state we want first and check if we need to
5400 * make any changes at all.
5401 */
5402 final = val;
5403 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5404 if (has_ck505)
5405 final |= DREF_NONSPREAD_CK505_ENABLE;
5406 else
5407 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5408
5409 final &= ~DREF_SSC_SOURCE_MASK;
5410 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5411 final &= ~DREF_SSC1_ENABLE;
5412
5413 if (has_panel) {
5414 final |= DREF_SSC_SOURCE_ENABLE;
5415
5416 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5417 final |= DREF_SSC1_ENABLE;
5418
5419 if (has_cpu_edp) {
5420 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5421 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5422 else
5423 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5424 } else
5425 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5426 } else {
5427 final |= DREF_SSC_SOURCE_DISABLE;
5428 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5429 }
5430
5431 if (final == val)
5432 return;
5433
13d83a67 5434 /* Always enable nonspread source */
74cfd7ac 5435 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5436
99eb6a01 5437 if (has_ck505)
74cfd7ac 5438 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5439 else
74cfd7ac 5440 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5441
199e5d79 5442 if (has_panel) {
74cfd7ac
CW		 5443 val &= ~DREF_SSC_SOURCE_MASK;
5444 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5445
199e5d79 5446 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5447 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5448 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5449 val |= DREF_SSC1_ENABLE;
e77166b5 5450 } else
74cfd7ac 5451 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5452
5453 /* Get SSC going before enabling the outputs */
74cfd7ac 5454 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5455 POSTING_READ(PCH_DREF_CONTROL);
5456 udelay(200);
5457
74cfd7ac 5458 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5459
5460 /* Enable CPU source on CPU attached eDP */
199e5d79 5461 if (has_cpu_edp) {
99eb6a01 5462 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5463 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5464 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5465 }
13d83a67 5466 else
74cfd7ac 5467 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5468 } else
74cfd7ac 5469 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5470
74cfd7ac 5471 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5472 POSTING_READ(PCH_DREF_CONTROL);
5473 udelay(200);
5474 } else {
5475 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5476
74cfd7ac 5477 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5478
5479 /* Turn off CPU output */
74cfd7ac 5480 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5481
74cfd7ac 5482 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5483 POSTING_READ(PCH_DREF_CONTROL);
5484 udelay(200);
5485
5486 /* Turn off the SSC source */
74cfd7ac
CW		 5487 val &= ~DREF_SSC_SOURCE_MASK;
5488 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5489
5490 /* Turn off SSC1 */
74cfd7ac 5491 val &= ~DREF_SSC1_ENABLE;
199e5d79 5492
74cfd7ac 5493 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5494 POSTING_READ(PCH_DREF_CONTROL);
5495 udelay(200);
5496 }
74cfd7ac
CW		 5497
5498 BUG_ON(val != final);
13d83a67
JB		 5499}
5500
f31f2d55 5501static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5502{
f31f2d55 5503 uint32_t tmp;
dde86e2d 5504
0ff066a9
PZ		 5505 tmp = I915_READ(SOUTH_CHICKEN2);
5506 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5507 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5508
0ff066a9
PZ		 5509 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5510 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5511 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5512
0ff066a9
PZ		 5513 tmp = I915_READ(SOUTH_CHICKEN2);
5514 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5515 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5516
0ff066a9
PZ		 5517 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5518 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5519 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5520}
5521
5522/* WaMPhyProgramming:hsw */
5523static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5524{
5525 uint32_t tmp;
dde86e2d
PZ		 5526
5527 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5528 tmp &= ~(0xFF << 24);
5529 tmp |= (0x12 << 24);
5530 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5531
dde86e2d
PZ		 5532 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5533 tmp |= (1 << 11);
5534 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5535
5536 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5537 tmp |= (1 << 11);
5538 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5539
dde86e2d
PZ		 5540 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5541 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5542 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5543
5544 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5545 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5546 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5547
0ff066a9
PZ		 5548 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5549 tmp &= ~(7 << 13);
5550 tmp |= (5 << 13);
5551 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5552
0ff066a9
PZ		 5553 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5554 tmp &= ~(7 << 13);
5555 tmp |= (5 << 13);
5556 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5557
5558 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5559 tmp &= ~0xFF;
5560 tmp |= 0x1C;
5561 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5562
5563 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5564 tmp &= ~0xFF;
5565 tmp |= 0x1C;
5566 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5567
5568 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5569 tmp &= ~(0xFF << 16);
5570 tmp |= (0x1C << 16);
5571 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5572
5573 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5574 tmp &= ~(0xFF << 16);
5575 tmp |= (0x1C << 16);
5576 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5577
0ff066a9
PZ		 5578 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5579 tmp |= (1 << 27);
5580 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5581
0ff066a9
PZ		 5582 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5583 tmp |= (1 << 27);
5584 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5585
0ff066a9
PZ		 5586 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5587 tmp &= ~(0xF << 28);
5588 tmp |= (4 << 28);
5589 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5590
0ff066a9
PZ		 5591 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5592 tmp &= ~(0xF << 28);
5593 tmp |= (4 << 28);
5594 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5595}
5596
2fa86a1f
PZ		 5597/* Implements 3 different sequences from BSpec chapter "Display iCLK
5598 * Programming" based on the parameters passed:
5599 * - Sequence to enable CLKOUT_DP
5600 * - Sequence to enable CLKOUT_DP without spread
5601 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5602 */
5603static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5604 bool with_fdi)
f31f2d55
PZ		 5605{
5606 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5607 uint32_t reg, tmp;
5608
5609 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5610 with_spread = true;
5611 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5612 with_fdi, "LP PCH doesn't have FDI\n"))
5613 with_fdi = false;
f31f2d55
PZ		 5614
5615 mutex_lock(&dev_priv->dpio_lock);
5616
5617 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5618 tmp &= ~SBI_SSCCTL_DISABLE;
5619 tmp |= SBI_SSCCTL_PATHALT;
5620 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5621
5622 udelay(24);
5623
2fa86a1f
PZ		 5624 if (with_spread) {
5625 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5626 tmp &= ~SBI_SSCCTL_PATHALT;
5627 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5628
2fa86a1f
PZ		 5629 if (with_fdi) {
5630 lpt_reset_fdi_mphy(dev_priv);
5631 lpt_program_fdi_mphy(dev_priv);
5632 }
5633 }
dde86e2d 5634
2fa86a1f
PZ		 5635 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5636 SBI_GEN0 : SBI_DBUFF0;
5637 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5638 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5639 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5640
5641 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5642}
5643
47701c3b
PZ		 5644/* Sequence to disable CLKOUT_DP */
5645static void lpt_disable_clkout_dp(struct drm_device *dev)
5646{
5647 struct drm_i915_private *dev_priv = dev->dev_private;
5648 uint32_t reg, tmp;
5649
5650 mutex_lock(&dev_priv->dpio_lock);
5651
5652 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5653 SBI_GEN0 : SBI_DBUFF0;
5654 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5655 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5656 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5657
5658 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5659 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5660 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5661 tmp |= SBI_SSCCTL_PATHALT;
5662 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5663 udelay(32);
5664 }
5665 tmp |= SBI_SSCCTL_DISABLE;
5666 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5667 }
5668
5669 mutex_unlock(&dev_priv->dpio_lock);
5670}
5671
bf8fa3d3
PZ		 5672static void lpt_init_pch_refclk(struct drm_device *dev)
5673{
5674 struct drm_mode_config *mode_config = &dev->mode_config;
5675 struct intel_encoder *encoder;
5676 bool has_vga = false;
5677
5678 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5679 switch (encoder->type) {
5680 case INTEL_OUTPUT_ANALOG:
5681 has_vga = true;
5682 break;
5683 }
5684 }
5685
47701c3b
PZ		 5686 if (has_vga)
5687 lpt_enable_clkout_dp(dev, true, true);
5688 else
5689 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5690}
5691
dde86e2d
PZ		 5692/*
5693 * Initialize reference clocks when the driver loads
5694 */
5695void intel_init_pch_refclk(struct drm_device *dev)
5696{
5697 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5698 ironlake_init_pch_refclk(dev);
5699 else if (HAS_PCH_LPT(dev))
5700 lpt_init_pch_refclk(dev);
5701}
5702
d9d444cb
JB		 5703static int ironlake_get_refclk(struct drm_crtc *crtc)
5704{
5705 struct drm_device *dev = crtc->dev;
5706 struct drm_i915_private *dev_priv = dev->dev_private;
5707 struct intel_encoder *encoder;
d9d444cb
JB		 5708 int num_connectors = 0;
5709 bool is_lvds = false;
5710
6c2b7c12 5711 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5712 switch (encoder->type) {
5713 case INTEL_OUTPUT_LVDS:
5714 is_lvds = true;
5715 break;
d9d444cb
JB		 5716 }
5717 num_connectors++;
5718 }
5719
5720 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5721 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5722 dev_priv->vbt.lvds_ssc_freq);
5723 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5724 }
5725
5726 return 120000;
5727}
5728
6ff93609 5729static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5730{
c8203565 5731 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5733 int pipe = intel_crtc->pipe;
c8203565
PZ		 5734 uint32_t val;
5735
78114071 5736 val = 0;
c8203565 5737
965e0c48 5738 switch (intel_crtc->config.pipe_bpp) {
c8203565 5739 case 18:
dfd07d72 5740 val |= PIPECONF_6BPC;
c8203565
PZ		 5741 break;
5742 case 24:
dfd07d72 5743 val |= PIPECONF_8BPC;
c8203565
PZ		 5744 break;
5745 case 30:
dfd07d72 5746 val |= PIPECONF_10BPC;
c8203565
PZ		 5747 break;
5748 case 36:
dfd07d72 5749 val |= PIPECONF_12BPC;
c8203565
PZ		 5750 break;
5751 default:
cc769b62
PZ		 5752 /* Case prevented by intel_choose_pipe_bpp_dither. */
5753 BUG();
c8203565
PZ		 5754 }
5755
d8b32247 5756 if (intel_crtc->config.dither)
c8203565
PZ		 5757 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5758
6ff93609 5759 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5760 val |= PIPECONF_INTERLACED_ILK;
5761 else
5762 val |= PIPECONF_PROGRESSIVE;
5763
50f3b016 5764 if (intel_crtc->config.limited_color_range)
3685a8f3 5765 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5766
c8203565
PZ		 5767 I915_WRITE(PIPECONF(pipe), val);
5768 POSTING_READ(PIPECONF(pipe));
5769}
5770
86d3efce
VS		 5771/*
5772 * Set up the pipe CSC unit.
5773 *
5774 * Currently only full range RGB to limited range RGB conversion
5775 * is supported, but eventually this should handle various
5776 * RGB<->YCbCr scenarios as well.
5777 */
50f3b016 5778static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5779{
5780 struct drm_device *dev = crtc->dev;
5781 struct drm_i915_private *dev_priv = dev->dev_private;
5782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5783 int pipe = intel_crtc->pipe;
5784 uint16_t coeff = 0x7800; /* 1.0 */
5785
5786 /*
5787 * TODO: Check what kind of values actually come out of the pipe
5788 * with these coeff/postoff values and adjust to get the best
5789 * accuracy. Perhaps we even need to take the bpc value into
5790 * consideration.
5791 */
5792
50f3b016 5793 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5794 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5795
5796 /*
5797 * GY/GU and RY/RU should be the other way around according
5798 * to BSpec, but reality doesn't agree. Just set them up in
5799 * a way that results in the correct picture.
5800 */
5801 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5802 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5803
5804 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5805 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5806
5807 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5808 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5809
5810 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5811 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5812 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5813
5814 if (INTEL_INFO(dev)->gen > 6) {
5815 uint16_t postoff = 0;
5816
50f3b016 5817 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5818 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5819
5820 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5821 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5822 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5823
5824 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5825 } else {
5826 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5827
50f3b016 5828 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5829 mode |= CSC_BLACK_SCREEN_OFFSET;
5830
5831 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5832 }
5833}
5834
6ff93609 5835static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 5836{
756f85cf
PZ		 5837 struct drm_device *dev = crtc->dev;
5838 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 5839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 5840 enum pipe pipe = intel_crtc->pipe;
3b117c8f 5841 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5842 uint32_t val;
5843
3eff4faa 5844 val = 0;
ee2b0b38 5845
756f85cf 5846 if (IS_HASWELL(dev) && intel_crtc->config.dither)
ee2b0b38
PZ		 5847 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5848
6ff93609 5849 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5850 val |= PIPECONF_INTERLACED_ILK;
5851 else
5852 val |= PIPECONF_PROGRESSIVE;
5853
702e7a56
PZ		 5854 I915_WRITE(PIPECONF(cpu_transcoder), val);
5855 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5856
5857 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5858 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf
PZ		 5859
5860 if (IS_BROADWELL(dev)) {
5861 val = 0;
5862
5863 switch (intel_crtc->config.pipe_bpp) {
5864 case 18:
5865 val |= PIPEMISC_DITHER_6_BPC;
5866 break;
5867 case 24:
5868 val |= PIPEMISC_DITHER_8_BPC;
5869 break;
5870 case 30:
5871 val |= PIPEMISC_DITHER_10_BPC;
5872 break;
5873 case 36:
5874 val |= PIPEMISC_DITHER_12_BPC;
5875 break;
5876 default:
5877 /* Case prevented by pipe_config_set_bpp. */
5878 BUG();
5879 }
5880
5881 if (intel_crtc->config.dither)
5882 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
5883
5884 I915_WRITE(PIPEMISC(pipe), val);
5885 }
ee2b0b38
PZ		 5886}
5887
6591c6e4 5888static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5889 intel_clock_t *clock,
5890 bool *has_reduced_clock,
5891 intel_clock_t *reduced_clock)
5892{
5893 struct drm_device *dev = crtc->dev;
5894 struct drm_i915_private *dev_priv = dev->dev_private;
5895 struct intel_encoder *intel_encoder;
5896 int refclk;
d4906093 5897 const intel_limit_t *limit;
a16af721 5898 bool ret, is_lvds = false;
79e53945 5899
6591c6e4
PZ		 5900 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5901 switch (intel_encoder->type) {
79e53945
JB		 5902 case INTEL_OUTPUT_LVDS:
5903 is_lvds = true;
5904 break;
79e53945
JB		 5905 }
5906 }
5907
d9d444cb 5908 refclk = ironlake_get_refclk(crtc);
79e53945 5909
d4906093
ML		 5910 /*
5911 * Returns a set of divisors for the desired target clock with the given
5912 * refclk, or FALSE. The returned values represent the clock equation:
5913 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5914 */
1b894b59 5915 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5916 ret = dev_priv->display.find_dpll(limit, crtc,
5917 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5918 refclk, NULL, clock);
6591c6e4
PZ		 5919 if (!ret)
5920 return false;
cda4b7d3 5921
ddc9003c 5922 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5923 /*
5924 * Ensure we match the reduced clock's P to the target clock.
5925 * If the clocks don't match, we can't switch the display clock
5926 * by using the FP0/FP1. In such case we will disable the LVDS
5927 * downclock feature.
5928 */
ee9300bb
DV		 5929 *has_reduced_clock =
5930 dev_priv->display.find_dpll(limit, crtc,
5931 dev_priv->lvds_downclock,
5932 refclk, clock,
5933 reduced_clock);
652c393a 5934 }
61e9653f 5935
6591c6e4
PZ		 5936 return true;
5937}
5938
d4b1931c
PZ		 5939int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5940{
5941 /*
5942 * Account for spread spectrum to avoid
5943 * oversubscribing the link. Max center spread
5944 * is 2.5%; use 5% for safety's sake.
5945 */
5946 u32 bps = target_clock * bpp * 21 / 20;
5947 return bps / (link_bw * 8) + 1;
5948}
5949
7429e9d4 5950static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5951{
7429e9d4 5952 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5953}
5954
de13a2e3 5955static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5956 u32 *fp,
9a7c7890 5957 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5958{
de13a2e3 5959 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5960 struct drm_device *dev = crtc->dev;
5961 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5962 struct intel_encoder *intel_encoder;
5963 uint32_t dpll;
6cc5f341 5964 int factor, num_connectors = 0;
09ede541 5965 bool is_lvds = false, is_sdvo = false;
79e53945 5966
de13a2e3
PZ		 5967 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5968 switch (intel_encoder->type) {
79e53945
JB		 5969 case INTEL_OUTPUT_LVDS:
5970 is_lvds = true;
5971 break;
5972 case INTEL_OUTPUT_SDVO:
7d57382e 5973 case INTEL_OUTPUT_HDMI:
79e53945 5974 is_sdvo = true;
79e53945 5975 break;
79e53945 5976 }
43565a06 5977
c751ce4f 5978 num_connectors++;
79e53945 5979 }
79e53945 5980
c1858123 5981 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5982 factor = 21;
5983 if (is_lvds) {
5984 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5985 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5986 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5987 factor = 25;
09ede541 5988 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5989 factor = 20;
c1858123 5990
7429e9d4 5991 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5992 *fp |= FP_CB_TUNE;
2c07245f 5993
9a7c7890
DV		 5994 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5995 *fp2 |= FP_CB_TUNE;
5996
5eddb70b 5997 dpll = 0;
2c07245f 5998
a07d6787
EA		 5999 if (is_lvds)
6000 dpll |= DPLLB_MODE_LVDS;
6001 else
6002 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 6003
ef1b460d
DV		 6004 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6005 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 6006
6007 if (is_sdvo)
4a33e48d 6008 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 6009 if (intel_crtc->config.has_dp_encoder)
4a33e48d 6010 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 6011
a07d6787 6012 /* compute bitmask from p1 value */
7429e9d4 6013 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 6014 /* also FPA1 */
7429e9d4 6015 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 6016
7429e9d4 6017 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 6018 case 5:
6019 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6020 break;
6021 case 7:
6022 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6023 break;
6024 case 10:
6025 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6026 break;
6027 case 14:
6028 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6029 break;
79e53945
JB		 6030 }
6031
b4c09f3b 6032 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 6033 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 6034 else
6035 dpll |= PLL_REF_INPUT_DREFCLK;
6036
959e16d6 6037 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 6038}
6039
6040static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 6041 int x, int y,
6042 struct drm_framebuffer *fb)
6043{
6044 struct drm_device *dev = crtc->dev;
6045 struct drm_i915_private *dev_priv = dev->dev_private;
6046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6047 int pipe = intel_crtc->pipe;
6048 int plane = intel_crtc->plane;
6049 int num_connectors = 0;
6050 intel_clock_t clock, reduced_clock;
cbbab5bd 6051 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 6052 bool ok, has_reduced_clock = false;
8b47047b 6053 bool is_lvds = false;
de13a2e3 6054 struct intel_encoder *encoder;
e2b78267 6055 struct intel_shared_dpll *pll;
de13a2e3 6056 int ret;
de13a2e3
PZ		 6057
6058 for_each_encoder_on_crtc(dev, crtc, encoder) {
6059 switch (encoder->type) {
6060 case INTEL_OUTPUT_LVDS:
6061 is_lvds = true;
6062 break;
de13a2e3
PZ		 6063 }
6064
6065 num_connectors++;
a07d6787 6066 }
79e53945 6067
5dc5298b
PZ		 6068 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6069 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 6070
ff9a6750 6071 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 6072 &has_reduced_clock, &reduced_clock);
ee9300bb 6073 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 6074 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6075 return -EINVAL;
79e53945 6076 }
f47709a9
DV		 6077 /* Compat-code for transition, will disappear. */
6078 if (!intel_crtc->config.clock_set) {
6079 intel_crtc->config.dpll.n = clock.n;
6080 intel_crtc->config.dpll.m1 = clock.m1;
6081 intel_crtc->config.dpll.m2 = clock.m2;
6082 intel_crtc->config.dpll.p1 = clock.p1;
6083 intel_crtc->config.dpll.p2 = clock.p2;
6084 }
79e53945 6085
5dc5298b 6086 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 6087 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 6088 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 6089 if (has_reduced_clock)
7429e9d4 6090 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 6091
7429e9d4 6092 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 6093 &fp, &reduced_clock,
6094 has_reduced_clock ? &fp2 : NULL);
6095
959e16d6 6096 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 6097 intel_crtc->config.dpll_hw_state.fp0 = fp;
6098 if (has_reduced_clock)
6099 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6100 else
6101 intel_crtc->config.dpll_hw_state.fp1 = fp;
6102
b89a1d39 6103 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 6104 if (pll == NULL) {
84f44ce7
VS		 6105 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6106 pipe_name(pipe));
4b645f14
JB		 6107 return -EINVAL;
6108 }
ee7b9f93 6109 } else
e72f9fbf 6110 intel_put_shared_dpll(intel_crtc);
79e53945 6111
03afc4a2
DV		 6112 if (intel_crtc->config.has_dp_encoder)
6113 intel_dp_set_m_n(intel_crtc);
79e53945 6114
bcd644e0
DV		 6115 if (is_lvds && has_reduced_clock && i915_powersave)
6116 intel_crtc->lowfreq_avail = true;
6117 else
6118 intel_crtc->lowfreq_avail = false;
e2b78267 6119
8a654f3b 6120 intel_set_pipe_timings(intel_crtc);
5eddb70b 6121
ca3a0ff8 6122 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6123 intel_cpu_transcoder_set_m_n(intel_crtc,
6124 &intel_crtc->config.fdi_m_n);
6125 }
2c07245f 6126
6ff93609 6127 ironlake_set_pipeconf(crtc);
79e53945 6128
a1f9e77e
PZ		 6129 /* Set up the display plane register */
6130 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 6131 POSTING_READ(DSPCNTR(plane));
79e53945 6132
94352cf9 6133 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 6134
1857e1da 6135 return ret;
79e53945
JB		 6136}
6137
eb14cb74
VS		 6138static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6139 struct intel_link_m_n *m_n)
6140{
6141 struct drm_device *dev = crtc->base.dev;
6142 struct drm_i915_private *dev_priv = dev->dev_private;
6143 enum pipe pipe = crtc->pipe;
6144
6145 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6146 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6147 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6148 & ~TU_SIZE_MASK;
6149 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6150 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6151 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6152}
6153
6154static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6155 enum transcoder transcoder,
6156 struct intel_link_m_n *m_n)
72419203
DV		 6157{
6158 struct drm_device *dev = crtc->base.dev;
6159 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 6160 enum pipe pipe = crtc->pipe;
72419203 6161
eb14cb74
VS		 6162 if (INTEL_INFO(dev)->gen >= 5) {
6163 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6164 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6165 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6166 & ~TU_SIZE_MASK;
6167 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6168 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6169 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6170 } else {
6171 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6172 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6173 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6174 & ~TU_SIZE_MASK;
6175 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6176 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6177 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6178 }
6179}
6180
6181void intel_dp_get_m_n(struct intel_crtc *crtc,
6182 struct intel_crtc_config *pipe_config)
6183{
6184 if (crtc->config.has_pch_encoder)
6185 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6186 else
6187 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6188 &pipe_config->dp_m_n);
6189}
72419203 6190
eb14cb74
VS		 6191static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6192 struct intel_crtc_config *pipe_config)
6193{
6194 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6195 &pipe_config->fdi_m_n);
72419203
DV		 6196}
6197
2fa2fe9a
DV		 6198static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6199 struct intel_crtc_config *pipe_config)
6200{
6201 struct drm_device *dev = crtc->base.dev;
6202 struct drm_i915_private *dev_priv = dev->dev_private;
6203 uint32_t tmp;
6204
6205 tmp = I915_READ(PF_CTL(crtc->pipe));
6206
6207 if (tmp & PF_ENABLE) {
fd4daa9c 6208 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 6209 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6210 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 6211
6212 /* We currently do not free assignements of panel fitters on
6213 * ivb/hsw (since we don't use the higher upscaling modes which
6214 * differentiates them) so just WARN about this case for now. */
6215 if (IS_GEN7(dev)) {
6216 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6217 PF_PIPE_SEL_IVB(crtc->pipe));
6218 }
2fa2fe9a 6219 }
79e53945
JB		 6220}
6221
0e8ffe1b
DV		 6222static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6223 struct intel_crtc_config *pipe_config)
6224{
6225 struct drm_device *dev = crtc->base.dev;
6226 struct drm_i915_private *dev_priv = dev->dev_private;
6227 uint32_t tmp;
6228
e143a21c 6229 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6230 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6231
0e8ffe1b
DV		 6232 tmp = I915_READ(PIPECONF(crtc->pipe));
6233 if (!(tmp & PIPECONF_ENABLE))
6234 return false;
6235
42571aef
VS		 6236 switch (tmp & PIPECONF_BPC_MASK) {
6237 case PIPECONF_6BPC:
6238 pipe_config->pipe_bpp = 18;
6239 break;
6240 case PIPECONF_8BPC:
6241 pipe_config->pipe_bpp = 24;
6242 break;
6243 case PIPECONF_10BPC:
6244 pipe_config->pipe_bpp = 30;
6245 break;
6246 case PIPECONF_12BPC:
6247 pipe_config->pipe_bpp = 36;
6248 break;
6249 default:
6250 break;
6251 }
6252
ab9412ba 6253 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6254 struct intel_shared_dpll *pll;
6255
88adfff1
DV		 6256 pipe_config->has_pch_encoder = true;
6257
627eb5a3
DV		 6258 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6259 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6260 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6261
6262 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6263
c0d43d62 6264 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6265 pipe_config->shared_dpll =
6266 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6267 } else {
6268 tmp = I915_READ(PCH_DPLL_SEL);
6269 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6270 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6271 else
6272 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6273 }
66e985c0
DV		 6274
6275 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6276
6277 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6278 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6279
6280 tmp = pipe_config->dpll_hw_state.dpll;
6281 pipe_config->pixel_multiplier =
6282 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6283 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6284
6285 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6286 } else {
6287 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6288 }
6289
1bd1bd80
DV		 6290 intel_get_pipe_timings(crtc, pipe_config);
6291
2fa2fe9a
DV		 6292 ironlake_get_pfit_config(crtc, pipe_config);
6293
0e8ffe1b
DV		 6294 return true;
6295}
6296
be256dc7
PZ		 6297static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6298{
6299 struct drm_device *dev = dev_priv->dev;
6300 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6301 struct intel_crtc *crtc;
6302 unsigned long irqflags;
bd633a7c 6303 uint32_t val;
be256dc7
PZ		 6304
6305 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6306 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6307 pipe_name(crtc->pipe));
6308
6309 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6310 WARN(plls->spll_refcount, "SPLL enabled\n");
6311 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6312 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6313 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6314 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6315 "CPU PWM1 enabled\n");
6316 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6317 "CPU PWM2 enabled\n");
6318 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6319 "PCH PWM1 enabled\n");
6320 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6321 "Utility pin enabled\n");
6322 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6323
6324 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6325 val = I915_READ(DEIMR);
6326 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6327 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6328 val = I915_READ(SDEIMR);
bd633a7c 6329 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6330 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6331 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6332}
6333
6334/*
6335 * This function implements pieces of two sequences from BSpec:
6336 * - Sequence for display software to disable LCPLL
6337 * - Sequence for display software to allow package C8+
6338 * The steps implemented here are just the steps that actually touch the LCPLL
6339 * register. Callers should take care of disabling all the display engine
6340 * functions, doing the mode unset, fixing interrupts, etc.
6341 */
6ff58d53
PZ		 6342static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6343 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 6344{
6345 uint32_t val;
6346
6347 assert_can_disable_lcpll(dev_priv);
6348
6349 val = I915_READ(LCPLL_CTL);
6350
6351 if (switch_to_fclk) {
6352 val |= LCPLL_CD_SOURCE_FCLK;
6353 I915_WRITE(LCPLL_CTL, val);
6354
6355 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6356 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6357 DRM_ERROR("Switching to FCLK failed\n");
6358
6359 val = I915_READ(LCPLL_CTL);
6360 }
6361
6362 val |= LCPLL_PLL_DISABLE;
6363 I915_WRITE(LCPLL_CTL, val);
6364 POSTING_READ(LCPLL_CTL);
6365
6366 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6367 DRM_ERROR("LCPLL still locked\n");
6368
6369 val = I915_READ(D_COMP);
6370 val |= D_COMP_COMP_DISABLE;
515b2392
PZ		 6371 mutex_lock(&dev_priv->rps.hw_lock);
6372 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6373 DRM_ERROR("Failed to disable D_COMP\n");
6374 mutex_unlock(&dev_priv->rps.hw_lock);
be256dc7
PZ		 6375 POSTING_READ(D_COMP);
6376 ndelay(100);
6377
6378 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6379 DRM_ERROR("D_COMP RCOMP still in progress\n");
6380
6381 if (allow_power_down) {
6382 val = I915_READ(LCPLL_CTL);
6383 val |= LCPLL_POWER_DOWN_ALLOW;
6384 I915_WRITE(LCPLL_CTL, val);
6385 POSTING_READ(LCPLL_CTL);
6386 }
6387}
6388
6389/*
6390 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6391 * source.
6392 */
6ff58d53 6393static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 6394{
6395 uint32_t val;
6396
6397 val = I915_READ(LCPLL_CTL);
6398
6399 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6400 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6401 return;
6402
215733fa
PZ		 6403 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6404 * we'll hang the machine! */
6405 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6406
be256dc7
PZ		 6407 if (val & LCPLL_POWER_DOWN_ALLOW) {
6408 val &= ~LCPLL_POWER_DOWN_ALLOW;
6409 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6410 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6411 }
6412
6413 val = I915_READ(D_COMP);
6414 val |= D_COMP_COMP_FORCE;
6415 val &= ~D_COMP_COMP_DISABLE;
515b2392
PZ		 6416 mutex_lock(&dev_priv->rps.hw_lock);
6417 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6418 DRM_ERROR("Failed to enable D_COMP\n");
6419 mutex_unlock(&dev_priv->rps.hw_lock);
35d8f2eb 6420 POSTING_READ(D_COMP);
be256dc7
PZ		 6421
6422 val = I915_READ(LCPLL_CTL);
6423 val &= ~LCPLL_PLL_DISABLE;
6424 I915_WRITE(LCPLL_CTL, val);
6425
6426 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6427 DRM_ERROR("LCPLL not locked yet\n");
6428
6429 if (val & LCPLL_CD_SOURCE_FCLK) {
6430 val = I915_READ(LCPLL_CTL);
6431 val &= ~LCPLL_CD_SOURCE_FCLK;
6432 I915_WRITE(LCPLL_CTL, val);
6433
6434 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6435 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6436 DRM_ERROR("Switching back to LCPLL failed\n");
6437 }
215733fa
PZ		 6438
6439 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6440}
6441
c67a470b
PZ		 6442void hsw_enable_pc8_work(struct work_struct *__work)
6443{
6444 struct drm_i915_private *dev_priv =
6445 container_of(to_delayed_work(__work), struct drm_i915_private,
6446 pc8.enable_work);
6447 struct drm_device *dev = dev_priv->dev;
6448 uint32_t val;
6449
6450 if (dev_priv->pc8.enabled)
6451 return;
6452
6453 DRM_DEBUG_KMS("Enabling package C8+\n");
6454
6455 dev_priv->pc8.enabled = true;
6456
6457 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6458 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6459 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6460 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6461 }
6462
6463 lpt_disable_clkout_dp(dev);
6464 hsw_pc8_disable_interrupts(dev);
6465 hsw_disable_lcpll(dev_priv, true, true);
6466}
6467
6468static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6469{
6470 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6471 WARN(dev_priv->pc8.disable_count < 1,
6472 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6473
6474 dev_priv->pc8.disable_count--;
6475 if (dev_priv->pc8.disable_count != 0)
6476 return;
6477
6478 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6479 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6480}
6481
6482static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6483{
6484 struct drm_device *dev = dev_priv->dev;
6485 uint32_t val;
6486
6487 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6488 WARN(dev_priv->pc8.disable_count < 0,
6489 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6490
6491 dev_priv->pc8.disable_count++;
6492 if (dev_priv->pc8.disable_count != 1)
6493 return;
6494
6495 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6496 if (!dev_priv->pc8.enabled)
6497 return;
6498
6499 DRM_DEBUG_KMS("Disabling package C8+\n");
6500
6501 hsw_restore_lcpll(dev_priv);
6502 hsw_pc8_restore_interrupts(dev);
6503 lpt_init_pch_refclk(dev);
6504
6505 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6506 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6507 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6508 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6509 }
6510
6511 intel_prepare_ddi(dev);
6512 i915_gem_init_swizzling(dev);
6513 mutex_lock(&dev_priv->rps.hw_lock);
6514 gen6_update_ring_freq(dev);
6515 mutex_unlock(&dev_priv->rps.hw_lock);
6516 dev_priv->pc8.enabled = false;
6517}
6518
6519void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6520{
7c6c2652
CW		 6521 if (!HAS_PC8(dev_priv->dev))
6522 return;
6523
c67a470b
PZ		 6524 mutex_lock(&dev_priv->pc8.lock);
6525 __hsw_enable_package_c8(dev_priv);
6526 mutex_unlock(&dev_priv->pc8.lock);
6527}
6528
6529void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6530{
7c6c2652
CW		 6531 if (!HAS_PC8(dev_priv->dev))
6532 return;
6533
c67a470b
PZ		 6534 mutex_lock(&dev_priv->pc8.lock);
6535 __hsw_disable_package_c8(dev_priv);
6536 mutex_unlock(&dev_priv->pc8.lock);
6537}
6538
6539static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6540{
6541 struct drm_device *dev = dev_priv->dev;
6542 struct intel_crtc *crtc;
6543 uint32_t val;
6544
6545 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6546 if (crtc->base.enabled)
6547 return false;
6548
6549 /* This case is still possible since we have the i915.disable_power_well
6550 * parameter and also the KVMr or something else might be requesting the
6551 * power well. */
6552 val = I915_READ(HSW_PWR_WELL_DRIVER);
6553 if (val != 0) {
6554 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6555 return false;
6556 }
6557
6558 return true;
6559}
6560
6561/* Since we're called from modeset_global_resources there's no way to
6562 * symmetrically increase and decrease the refcount, so we use
6563 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6564 * or not.
6565 */
6566static void hsw_update_package_c8(struct drm_device *dev)
6567{
6568 struct drm_i915_private *dev_priv = dev->dev_private;
6569 bool allow;
6570
7c6c2652
CW		 6571 if (!HAS_PC8(dev_priv->dev))
6572 return;
6573
c67a470b
PZ		 6574 if (!i915_enable_pc8)
6575 return;
6576
6577 mutex_lock(&dev_priv->pc8.lock);
6578
6579 allow = hsw_can_enable_package_c8(dev_priv);
6580
6581 if (allow == dev_priv->pc8.requirements_met)
6582 goto done;
6583
6584 dev_priv->pc8.requirements_met = allow;
6585
6586 if (allow)
6587 __hsw_enable_package_c8(dev_priv);
6588 else
6589 __hsw_disable_package_c8(dev_priv);
6590
6591done:
6592 mutex_unlock(&dev_priv->pc8.lock);
6593}
6594
6595static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6596{
7c6c2652
CW		 6597 if (!HAS_PC8(dev_priv->dev))
6598 return;
6599
be1c1fe2 6600 mutex_lock(&dev_priv->pc8.lock);
c67a470b
PZ		 6601 if (!dev_priv->pc8.gpu_idle) {
6602 dev_priv->pc8.gpu_idle = true;
be1c1fe2 6603 __hsw_enable_package_c8(dev_priv);
c67a470b 6604 }
be1c1fe2 6605 mutex_unlock(&dev_priv->pc8.lock);
c67a470b
PZ		 6606}
6607
6608static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6609{
7c6c2652
CW		 6610 if (!HAS_PC8(dev_priv->dev))
6611 return;
6612
be1c1fe2 6613 mutex_lock(&dev_priv->pc8.lock);
c67a470b
PZ		 6614 if (dev_priv->pc8.gpu_idle) {
6615 dev_priv->pc8.gpu_idle = false;
be1c1fe2 6616 __hsw_disable_package_c8(dev_priv);
c67a470b 6617 }
be1c1fe2 6618 mutex_unlock(&dev_priv->pc8.lock);
be256dc7
PZ		 6619}
6620
6efdf354
ID		 6621#define for_each_power_domain(domain, mask) \
6622 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6623 if ((1 << (domain)) & (mask))
6624
6625static unsigned long get_pipe_power_domains(struct drm_device *dev,
6626 enum pipe pipe, bool pfit_enabled)
d6dd9eb1 6627{
6efdf354
ID		 6628 unsigned long mask;
6629 enum transcoder transcoder;
6630
6631 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6632
6633 mask = BIT(POWER_DOMAIN_PIPE(pipe));
6634 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6635 if (pfit_enabled)
6636 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6637
6638 return mask;
6639}
6640
baa70707
ID		 6641void intel_display_set_init_power(struct drm_device *dev, bool enable)
6642{
6643 struct drm_i915_private *dev_priv = dev->dev_private;
6644
6645 if (dev_priv->power_domains.init_power_on == enable)
6646 return;
6647
6648 if (enable)
6649 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6650 else
6651 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6652
6653 dev_priv->power_domains.init_power_on = enable;
6654}
6655
4f074129 6656static void modeset_update_power_wells(struct drm_device *dev)
d6dd9eb1 6657{
6efdf354 6658 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
d6dd9eb1 6659 struct intel_crtc *crtc;
d6dd9eb1 6660
6efdf354
ID		 6661 /*
6662 * First get all needed power domains, then put all unneeded, to avoid
6663 * any unnecessary toggling of the power wells.
6664 */
d6dd9eb1 6665 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6efdf354
ID		 6666 enum intel_display_power_domain domain;
6667
e7a639c4
DV		 6668 if (!crtc->base.enabled)
6669 continue;
d6dd9eb1 6670
6efdf354
ID		 6671 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6672 crtc->pipe,
6673 crtc->config.pch_pfit.enabled);
6674
6675 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6676 intel_display_power_get(dev, domain);
d6dd9eb1
DV		 6677 }
6678
6efdf354
ID		 6679 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6680 enum intel_display_power_domain domain;
6681
6682 for_each_power_domain(domain, crtc->enabled_power_domains)
6683 intel_display_power_put(dev, domain);
6684
6685 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
d6dd9eb1
DV		 6686 }
6687
baa70707 6688 intel_display_set_init_power(dev, false);
4f074129 6689}
c67a470b 6690
4f074129
ID		 6691static void haswell_modeset_global_resources(struct drm_device *dev)
6692{
6693 modeset_update_power_wells(dev);
c67a470b 6694 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6695}
6696
09b4ddf9 6697static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6698 int x, int y,
6699 struct drm_framebuffer *fb)
6700{
6701 struct drm_device *dev = crtc->dev;
6702 struct drm_i915_private *dev_priv = dev->dev_private;
6703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6704 int plane = intel_crtc->plane;
09b4ddf9 6705 int ret;
09b4ddf9 6706
ff9a6750 6707 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6708 return -EINVAL;
6709
03afc4a2
DV		 6710 if (intel_crtc->config.has_dp_encoder)
6711 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6712
6713 intel_crtc->lowfreq_avail = false;
09b4ddf9 6714
8a654f3b 6715 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6716
ca3a0ff8 6717 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6718 intel_cpu_transcoder_set_m_n(intel_crtc,
6719 &intel_crtc->config.fdi_m_n);
6720 }
09b4ddf9 6721
6ff93609 6722 haswell_set_pipeconf(crtc);
09b4ddf9 6723
50f3b016 6724 intel_set_pipe_csc(crtc);
86d3efce 6725
09b4ddf9 6726 /* Set up the display plane register */
86d3efce 6727 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6728 POSTING_READ(DSPCNTR(plane));
6729
6730 ret = intel_pipe_set_base(crtc, x, y, fb);
6731
1f803ee5 6732 return ret;
79e53945
JB		 6733}
6734
0e8ffe1b
DV		 6735static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6736 struct intel_crtc_config *pipe_config)
6737{
6738 struct drm_device *dev = crtc->base.dev;
6739 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6740 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6741 uint32_t tmp;
6742
e143a21c 6743 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6744 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6745
eccb140b
DV		 6746 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6747 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6748 enum pipe trans_edp_pipe;
6749 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6750 default:
6751 WARN(1, "unknown pipe linked to edp transcoder\n");
6752 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6753 case TRANS_DDI_EDP_INPUT_A_ON:
6754 trans_edp_pipe = PIPE_A;
6755 break;
6756 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6757 trans_edp_pipe = PIPE_B;
6758 break;
6759 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6760 trans_edp_pipe = PIPE_C;
6761 break;
6762 }
6763
6764 if (trans_edp_pipe == crtc->pipe)
6765 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6766 }
6767
b97186f0 6768 if (!intel_display_power_enabled(dev,
eccb140b 6769 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6770 return false;
6771
eccb140b 6772 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6773 if (!(tmp & PIPECONF_ENABLE))
6774 return false;
6775
88adfff1 6776 /*
f196e6be 6777 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6778 * DDI E. So just check whether this pipe is wired to DDI E and whether
6779 * the PCH transcoder is on.
6780 */
eccb140b 6781 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6782 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6783 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6784 pipe_config->has_pch_encoder = true;
6785
627eb5a3
DV		 6786 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6787 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6788 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6789
6790 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6791 }
6792
1bd1bd80
DV		 6793 intel_get_pipe_timings(crtc, pipe_config);
6794
2fa2fe9a
DV		 6795 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6796 if (intel_display_power_enabled(dev, pfit_domain))
6797 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6798
42db64ef
PZ		 6799 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6800 (I915_READ(IPS_CTL) & IPS_ENABLE);
6801
6c49f241
DV		 6802 pipe_config->pixel_multiplier = 1;
6803
0e8ffe1b
DV		 6804 return true;
6805}
6806
f564048e 6807static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6808 int x, int y,
94352cf9 6809 struct drm_framebuffer *fb)
f564048e
EA		 6810{
6811 struct drm_device *dev = crtc->dev;
6812 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6813 struct intel_encoder *encoder;
0b701d27 6814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6815 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6816 int pipe = intel_crtc->pipe;
f564048e
EA		 6817 int ret;
6818
0b701d27 6819 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6820
b8cecdf5
DV		 6821 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6822
79e53945 6823 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6824
9256aa19
DV		 6825 if (ret != 0)
6826 return ret;
6827
6828 for_each_encoder_on_crtc(dev, crtc, encoder) {
6829 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6830 encoder->base.base.id,
6831 drm_get_encoder_name(&encoder->base),
6832 mode->base.id, mode->name);
36f2d1f1 6833 encoder->mode_set(encoder);
9256aa19
DV		 6834 }
6835
6836 return 0;
79e53945
JB		 6837}
6838
1a91510d
JN		 6839static struct {
6840 int clock;
6841 u32 config;
6842} hdmi_audio_clock[] = {
6843 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
6844 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
6845 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
6846 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
6847 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
6848 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
6849 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
6850 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
6851 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
6852 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
6853};
6854
6855/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
6856static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
6857{
6858 int i;
6859
6860 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
6861 if (mode->clock == hdmi_audio_clock[i].clock)
6862 break;
6863 }
6864
6865 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
6866 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
6867 i = 1;
6868 }
6869
6870 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
6871 hdmi_audio_clock[i].clock,
6872 hdmi_audio_clock[i].config);
6873
6874 return hdmi_audio_clock[i].config;
6875}
6876
3a9627f4
WF		 6877static bool intel_eld_uptodate(struct drm_connector *connector,
6878 int reg_eldv, uint32_t bits_eldv,
6879 int reg_elda, uint32_t bits_elda,
6880 int reg_edid)
6881{
6882 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6883 uint8_t *eld = connector->eld;
6884 uint32_t i;
6885
6886 i = I915_READ(reg_eldv);
6887 i &= bits_eldv;
6888
6889 if (!eld[0])
6890 return !i;
6891
6892 if (!i)
6893 return false;
6894
6895 i = I915_READ(reg_elda);
6896 i &= ~bits_elda;
6897 I915_WRITE(reg_elda, i);
6898
6899 for (i = 0; i < eld[2]; i++)
6900 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6901 return false;
6902
6903 return true;
6904}
6905
e0dac65e 6906static void g4x_write_eld(struct drm_connector *connector,
34427052
JN		 6907 struct drm_crtc *crtc,
6908 struct drm_display_mode *mode)
e0dac65e
WF		 6909{
6910 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6911 uint8_t *eld = connector->eld;
6912 uint32_t eldv;
6913 uint32_t len;
6914 uint32_t i;
6915
6916 i = I915_READ(G4X_AUD_VID_DID);
6917
6918 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6919 eldv = G4X_ELDV_DEVCL_DEVBLC;
6920 else
6921 eldv = G4X_ELDV_DEVCTG;
6922
3a9627f4
WF		 6923 if (intel_eld_uptodate(connector,
6924 G4X_AUD_CNTL_ST, eldv,
6925 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6926 G4X_HDMIW_HDMIEDID))
6927 return;
6928
e0dac65e
WF		 6929 i = I915_READ(G4X_AUD_CNTL_ST);
6930 i &= ~(eldv | G4X_ELD_ADDR);
6931 len = (i >> 9) & 0x1f; /* ELD buffer size */
6932 I915_WRITE(G4X_AUD_CNTL_ST, i);
6933
6934 if (!eld[0])
6935 return;
6936
6937 len = min_t(uint8_t, eld[2], len);
6938 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6939 for (i = 0; i < len; i++)
6940 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6941
6942 i = I915_READ(G4X_AUD_CNTL_ST);
6943 i |= eldv;
6944 I915_WRITE(G4X_AUD_CNTL_ST, i);
6945}
6946
83358c85 6947static void haswell_write_eld(struct drm_connector *connector,
34427052
JN		 6948 struct drm_crtc *crtc,
6949 struct drm_display_mode *mode)
83358c85
WX		 6950{
6951 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6952 uint8_t *eld = connector->eld;
6953 struct drm_device *dev = crtc->dev;
7b9f35a6 6954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6955 uint32_t eldv;
6956 uint32_t i;
6957 int len;
6958 int pipe = to_intel_crtc(crtc)->pipe;
6959 int tmp;
6960
6961 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6962 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6963 int aud_config = HSW_AUD_CFG(pipe);
6964 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6965
6966
6967 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6968
6969 /* Audio output enable */
6970 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6971 tmp = I915_READ(aud_cntrl_st2);
6972 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6973 I915_WRITE(aud_cntrl_st2, tmp);
6974
6975 /* Wait for 1 vertical blank */
6976 intel_wait_for_vblank(dev, pipe);
6977
6978 /* Set ELD valid state */
6979 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6980 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
83358c85
WX		 6981 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6982 I915_WRITE(aud_cntrl_st2, tmp);
6983 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6984 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
83358c85
WX		 6985
6986 /* Enable HDMI mode */
6987 tmp = I915_READ(aud_config);
7e7cb34f 6988 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
83358c85
WX		 6989 /* clear N_programing_enable and N_value_index */
6990 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6991 I915_WRITE(aud_config, tmp);
6992
6993 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6994
6995 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6996 intel_crtc->eld_vld = true;
83358c85
WX		 6997
6998 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6999 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7000 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7001 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
1a91510d
JN		 7002 } else {
7003 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7004 }
83358c85
WX		 7005
7006 if (intel_eld_uptodate(connector,
7007 aud_cntrl_st2, eldv,
7008 aud_cntl_st, IBX_ELD_ADDRESS,
7009 hdmiw_hdmiedid))
7010 return;
7011
7012 i = I915_READ(aud_cntrl_st2);
7013 i &= ~eldv;
7014 I915_WRITE(aud_cntrl_st2, i);
7015
7016 if (!eld[0])
7017 return;
7018
7019 i = I915_READ(aud_cntl_st);
7020 i &= ~IBX_ELD_ADDRESS;
7021 I915_WRITE(aud_cntl_st, i);
7022 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7023 DRM_DEBUG_DRIVER("port num:%d\n", i);
7024
7025 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7026 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7027 for (i = 0; i < len; i++)
7028 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7029
7030 i = I915_READ(aud_cntrl_st2);
7031 i |= eldv;
7032 I915_WRITE(aud_cntrl_st2, i);
7033
7034}
7035
e0dac65e 7036static void ironlake_write_eld(struct drm_connector *connector,
34427052
JN		 7037 struct drm_crtc *crtc,
7038 struct drm_display_mode *mode)
e0dac65e
WF		 7039{
7040 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7041 uint8_t *eld = connector->eld;
7042 uint32_t eldv;
7043 uint32_t i;
7044 int len;
7045 int hdmiw_hdmiedid;
b6daa025 7046 int aud_config;
e0dac65e
WF		 7047 int aud_cntl_st;
7048 int aud_cntrl_st2;
9b138a83 7049 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 7050
b3f33cbf 7051 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 7052 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7053 aud_config = IBX_AUD_CFG(pipe);
7054 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 7055 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
9ca2fe73
ML		 7056 } else if (IS_VALLEYVIEW(connector->dev)) {
7057 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7058 aud_config = VLV_AUD_CFG(pipe);
7059 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7060 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
e0dac65e 7061 } else {
9b138a83
WX		 7062 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7063 aud_config = CPT_AUD_CFG(pipe);
7064 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 7065 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 7066 }
7067
9b138a83 7068 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e 7069
9ca2fe73
ML		 7070 if (IS_VALLEYVIEW(connector->dev)) {
7071 struct intel_encoder *intel_encoder;
7072 struct intel_digital_port *intel_dig_port;
7073
7074 intel_encoder = intel_attached_encoder(connector);
7075 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7076 i = intel_dig_port->port;
7077 } else {
7078 i = I915_READ(aud_cntl_st);
7079 i = (i >> 29) & DIP_PORT_SEL_MASK;
7080 /* DIP_Port_Select, 0x1 = PortB */
7081 }
7082
e0dac65e
WF		 7083 if (!i) {
7084 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7085 /* operate blindly on all ports */
1202b4c6
WF		 7086 eldv = IBX_ELD_VALIDB;
7087 eldv |= IBX_ELD_VALIDB << 4;
7088 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 7089 } else {
2582a850 7090 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 7091 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 7092 }
7093
3a9627f4
WF		 7094 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7095 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7096 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025 7097 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
1a91510d
JN		 7098 } else {
7099 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7100 }
e0dac65e 7101
3a9627f4
WF		 7102 if (intel_eld_uptodate(connector,
7103 aud_cntrl_st2, eldv,
7104 aud_cntl_st, IBX_ELD_ADDRESS,
7105 hdmiw_hdmiedid))
7106 return;
7107
e0dac65e
WF		 7108 i = I915_READ(aud_cntrl_st2);
7109 i &= ~eldv;
7110 I915_WRITE(aud_cntrl_st2, i);
7111
7112 if (!eld[0])
7113 return;
7114
e0dac65e 7115 i = I915_READ(aud_cntl_st);
1202b4c6 7116 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 7117 I915_WRITE(aud_cntl_st, i);
7118
7119 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7120 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7121 for (i = 0; i < len; i++)
7122 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7123
7124 i = I915_READ(aud_cntrl_st2);
7125 i |= eldv;
7126 I915_WRITE(aud_cntrl_st2, i);
7127}
7128
7129void intel_write_eld(struct drm_encoder *encoder,
7130 struct drm_display_mode *mode)
7131{
7132 struct drm_crtc *crtc = encoder->crtc;
7133 struct drm_connector *connector;
7134 struct drm_device *dev = encoder->dev;
7135 struct drm_i915_private *dev_priv = dev->dev_private;
7136
7137 connector = drm_select_eld(encoder, mode);
7138 if (!connector)
7139 return;
7140
7141 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7142 connector->base.id,
7143 drm_get_connector_name(connector),
7144 connector->encoder->base.id,
7145 drm_get_encoder_name(connector->encoder));
7146
7147 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7148
7149 if (dev_priv->display.write_eld)
34427052 7150 dev_priv->display.write_eld(connector, crtc, mode);
e0dac65e
WF		 7151}
7152
560b85bb
CW		 7153static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7154{
7155 struct drm_device *dev = crtc->dev;
7156 struct drm_i915_private *dev_priv = dev->dev_private;
7157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7158 bool visible = base != 0;
7159 u32 cntl;
7160
7161 if (intel_crtc->cursor_visible == visible)
7162 return;
7163
9db4a9c7 7164 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 7165 if (visible) {
7166 /* On these chipsets we can only modify the base whilst
7167 * the cursor is disabled.
7168 */
9db4a9c7 7169 I915_WRITE(_CURABASE, base);
560b85bb
CW		 7170
7171 cntl &= ~(CURSOR_FORMAT_MASK);
7172 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7173 cntl |= CURSOR_ENABLE |
7174 CURSOR_GAMMA_ENABLE |
7175 CURSOR_FORMAT_ARGB;
7176 } else
7177 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 7178 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 7179
7180 intel_crtc->cursor_visible = visible;
7181}
7182
7183static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7184{
7185 struct drm_device *dev = crtc->dev;
7186 struct drm_i915_private *dev_priv = dev->dev_private;
7187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7188 int pipe = intel_crtc->pipe;
7189 bool visible = base != 0;
7190
7191 if (intel_crtc->cursor_visible != visible) {
548f245b 7192 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 7193 if (base) {
7194 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7195 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7196 cntl |= pipe << 28; /* Connect to correct pipe */
7197 } else {
7198 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7199 cntl |= CURSOR_MODE_DISABLE;
7200 }
9db4a9c7 7201 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 7202
7203 intel_crtc->cursor_visible = visible;
7204 }
7205 /* and commit changes on next vblank */
b2ea8ef5 7206 POSTING_READ(CURCNTR(pipe));
9db4a9c7 7207 I915_WRITE(CURBASE(pipe), base);
b2ea8ef5 7208 POSTING_READ(CURBASE(pipe));
560b85bb
CW		 7209}
7210
65a21cd6
JB		 7211static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7212{
7213 struct drm_device *dev = crtc->dev;
7214 struct drm_i915_private *dev_priv = dev->dev_private;
7215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7216 int pipe = intel_crtc->pipe;
7217 bool visible = base != 0;
7218
7219 if (intel_crtc->cursor_visible != visible) {
7220 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7221 if (base) {
7222 cntl &= ~CURSOR_MODE;
7223 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7224 } else {
7225 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7226 cntl |= CURSOR_MODE_DISABLE;
7227 }
6bbfa1c5 7228 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
86d3efce 7229 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 7230 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7231 }
65a21cd6
JB		 7232 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7233
7234 intel_crtc->cursor_visible = visible;
7235 }
7236 /* and commit changes on next vblank */
b2ea8ef5 7237 POSTING_READ(CURCNTR_IVB(pipe));
65a21cd6 7238 I915_WRITE(CURBASE_IVB(pipe), base);
b2ea8ef5 7239 POSTING_READ(CURBASE_IVB(pipe));
65a21cd6
JB		 7240}
7241
cda4b7d3 7242/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 7243static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7244 bool on)
cda4b7d3
CW		 7245{
7246 struct drm_device *dev = crtc->dev;
7247 struct drm_i915_private *dev_priv = dev->dev_private;
7248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7249 int pipe = intel_crtc->pipe;
7250 int x = intel_crtc->cursor_x;
7251 int y = intel_crtc->cursor_y;
d6e4db15 7252 u32 base = 0, pos = 0;
cda4b7d3
CW		 7253 bool visible;
7254
d6e4db15 7255 if (on)
cda4b7d3 7256 base = intel_crtc->cursor_addr;
cda4b7d3 7257
d6e4db15
VS		 7258 if (x >= intel_crtc->config.pipe_src_w)
7259 base = 0;
7260
7261 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 7262 base = 0;
7263
7264 if (x < 0) {
efc9064e 7265 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 7266 base = 0;
7267
7268 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7269 x = -x;
7270 }
7271 pos |= x << CURSOR_X_SHIFT;
7272
7273 if (y < 0) {
efc9064e 7274 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 7275 base = 0;
7276
7277 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7278 y = -y;
7279 }
7280 pos |= y << CURSOR_Y_SHIFT;
7281
7282 visible = base != 0;
560b85bb 7283 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 7284 return;
7285
b3dc685e 7286 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
65a21cd6
JB		 7287 I915_WRITE(CURPOS_IVB(pipe), pos);
7288 ivb_update_cursor(crtc, base);
7289 } else {
7290 I915_WRITE(CURPOS(pipe), pos);
7291 if (IS_845G(dev) || IS_I865G(dev))
7292 i845_update_cursor(crtc, base);
7293 else
7294 i9xx_update_cursor(crtc, base);
7295 }
cda4b7d3
CW		 7296}
7297
79e53945 7298static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 7299 struct drm_file *file,
79e53945
JB		 7300 uint32_t handle,
7301 uint32_t width, uint32_t height)
7302{
7303 struct drm_device *dev = crtc->dev;
7304 struct drm_i915_private *dev_priv = dev->dev_private;
7305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 7306 struct drm_i915_gem_object *obj;
cda4b7d3 7307 uint32_t addr;
3f8bc370 7308 int ret;
79e53945 7309
79e53945
JB		 7310 /* if we want to turn off the cursor ignore width and height */
7311 if (!handle) {
28c97730 7312 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 7313 addr = 0;
05394f39 7314 obj = NULL;
5004417d 7315 mutex_lock(&dev->struct_mutex);
3f8bc370 7316 goto finish;
79e53945
JB		 7317 }
7318
7319 /* Currently we only support 64x64 cursors */
7320 if (width != 64 || height != 64) {
7321 DRM_ERROR("we currently only support 64x64 cursors\n");
7322 return -EINVAL;
7323 }
7324
05394f39 7325 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 7326 if (&obj->base == NULL)
79e53945
JB		 7327 return -ENOENT;
7328
05394f39 7329 if (obj->base.size < width * height * 4) {
79e53945 7330 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 7331 ret = -ENOMEM;
7332 goto fail;
79e53945
JB		 7333 }
7334
71acb5eb 7335 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7336 mutex_lock(&dev->struct_mutex);
b295d1b6 7337 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7338 unsigned alignment;
7339
d9e86c0e
CW		 7340 if (obj->tiling_mode) {
7341 DRM_ERROR("cursor cannot be tiled\n");
7342 ret = -EINVAL;
7343 goto fail_locked;
7344 }
7345
693db184
CW		 7346 /* Note that the w/a also requires 2 PTE of padding following
7347 * the bo. We currently fill all unused PTE with the shadow
7348 * page and so we should always have valid PTE following the
7349 * cursor preventing the VT-d warning.
7350 */
7351 alignment = 0;
7352 if (need_vtd_wa(dev))
7353 alignment = 64*1024;
7354
7355 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7356 if (ret) {
7357 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7358 goto fail_locked;
e7b526bb
CW		 7359 }
7360
d9e86c0e
CW		 7361 ret = i915_gem_object_put_fence(obj);
7362 if (ret) {
2da3b9b9 7363 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7364 goto fail_unpin;
7365 }
7366
f343c5f6 7367 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7368 } else {
6eeefaf3 7369 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7370 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7371 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7372 align);
71acb5eb
DA		 7373 if (ret) {
7374 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7375 goto fail_locked;
71acb5eb 7376 }
05394f39 7377 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7378 }
7379
a6c45cf0 7380 if (IS_GEN2(dev))
14b60391
JB		 7381 I915_WRITE(CURSIZE, (height << 12) | width);
7382
3f8bc370 7383 finish:
3f8bc370 7384 if (intel_crtc->cursor_bo) {
b295d1b6 7385 if (dev_priv->info->cursor_needs_physical) {
05394f39 7386 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7387 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7388 } else
cc98b413 7389 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7390 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7391 }
80824003 7392
7f9872e0 7393 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7394
7395 intel_crtc->cursor_addr = addr;
05394f39 7396 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7397 intel_crtc->cursor_width = width;
7398 intel_crtc->cursor_height = height;
7399
f2f5f771
VS		 7400 if (intel_crtc->active)
7401 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7402
79e53945 7403 return 0;
e7b526bb 7404fail_unpin:
cc98b413 7405 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7406fail_locked:
34b8686e 7407 mutex_unlock(&dev->struct_mutex);
bc9025bd 7408fail:
05394f39 7409 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7410 return ret;
79e53945
JB		 7411}
7412
7413static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7414{
79e53945 7415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7416
92e76c8c
VS		 7417 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7418 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
652c393a 7419
f2f5f771
VS		 7420 if (intel_crtc->active)
7421 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7422
7423 return 0;
b8c00ac5
DA		 7424}
7425
79e53945 7426static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7427 u16 *blue, uint32_t start, uint32_t size)
79e53945 7428{
7203425a 7429 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7431
7203425a 7432 for (i = start; i < end; i++) {
79e53945
JB		 7433 intel_crtc->lut_r[i] = red[i] >> 8;
7434 intel_crtc->lut_g[i] = green[i] >> 8;
7435 intel_crtc->lut_b[i] = blue[i] >> 8;
7436 }
7437
7438 intel_crtc_load_lut(crtc);
7439}
7440
79e53945
JB		 7441/* VESA 640x480x72Hz mode to set on the pipe */
7442static struct drm_display_mode load_detect_mode = {
7443 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7444 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7445};
7446
d2dff872
CW		 7447static struct drm_framebuffer *
7448intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7449 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7450 struct drm_i915_gem_object *obj)
7451{
7452 struct intel_framebuffer *intel_fb;
7453 int ret;
7454
7455 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7456 if (!intel_fb) {
7457 drm_gem_object_unreference_unlocked(&obj->base);
7458 return ERR_PTR(-ENOMEM);
7459 }
7460
dd4916c5
DV		 7461 ret = i915_mutex_lock_interruptible(dev);
7462 if (ret)
7463 goto err;
7464
d2dff872 7465 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 7466 mutex_unlock(&dev->struct_mutex);
7467 if (ret)
7468 goto err;
d2dff872
CW		 7469
7470 return &intel_fb->base;
dd4916c5
DV		 7471err:
7472 drm_gem_object_unreference_unlocked(&obj->base);
7473 kfree(intel_fb);
7474
7475 return ERR_PTR(ret);
d2dff872
CW		 7476}
7477
7478static u32
7479intel_framebuffer_pitch_for_width(int width, int bpp)
7480{
7481 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7482 return ALIGN(pitch, 64);
7483}
7484
7485static u32
7486intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7487{
7488 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7489 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7490}
7491
7492static struct drm_framebuffer *
7493intel_framebuffer_create_for_mode(struct drm_device *dev,
7494 struct drm_display_mode *mode,
7495 int depth, int bpp)
7496{
7497 struct drm_i915_gem_object *obj;
0fed39bd 7498 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7499
7500 obj = i915_gem_alloc_object(dev,
7501 intel_framebuffer_size_for_mode(mode, bpp));
7502 if (obj == NULL)
7503 return ERR_PTR(-ENOMEM);
7504
7505 mode_cmd.width = mode->hdisplay;
7506 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7507 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7508 bpp);
5ca0c34a 7509 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7510
7511 return intel_framebuffer_create(dev, &mode_cmd, obj);
7512}
7513
7514static struct drm_framebuffer *
7515mode_fits_in_fbdev(struct drm_device *dev,
7516 struct drm_display_mode *mode)
7517{
4520f53a 7518#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 7519 struct drm_i915_private *dev_priv = dev->dev_private;
7520 struct drm_i915_gem_object *obj;
7521 struct drm_framebuffer *fb;
7522
7523 if (dev_priv->fbdev == NULL)
7524 return NULL;
7525
7526 obj = dev_priv->fbdev->ifb.obj;
7527 if (obj == NULL)
7528 return NULL;
7529
7530 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7531 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7532 fb->bits_per_pixel))
d2dff872
CW		 7533 return NULL;
7534
01f2c773 7535 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7536 return NULL;
7537
7538 return fb;
4520f53a
DV		 7539#else
7540 return NULL;
7541#endif
d2dff872
CW		 7542}
7543
d2434ab7 7544bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7545 struct drm_display_mode *mode,
8261b191 7546 struct intel_load_detect_pipe *old)
79e53945
JB		 7547{
7548 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7549 struct intel_encoder *intel_encoder =
7550 intel_attached_encoder(connector);
79e53945 7551 struct drm_crtc *possible_crtc;
4ef69c7a 7552 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7553 struct drm_crtc *crtc = NULL;
7554 struct drm_device *dev = encoder->dev;
94352cf9 7555 struct drm_framebuffer *fb;
79e53945
JB		 7556 int i = -1;
7557
d2dff872
CW		 7558 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7559 connector->base.id, drm_get_connector_name(connector),
7560 encoder->base.id, drm_get_encoder_name(encoder));
7561
79e53945
JB		 7562 /*
7563 * Algorithm gets a little messy:
7a5e4805 7564 *
79e53945
JB		 7565 * - if the connector already has an assigned crtc, use it (but make
7566 * sure it's on first)
7a5e4805 7567 *
79e53945
JB		 7568 * - try to find the first unused crtc that can drive this connector,
7569 * and use that if we find one
79e53945
JB		 7570 */
7571
7572 /* See if we already have a CRTC for this connector */
7573 if (encoder->crtc) {
7574 crtc = encoder->crtc;
8261b191 7575
7b24056b
DV		 7576 mutex_lock(&crtc->mutex);
7577
24218aac 7578 old->dpms_mode = connector->dpms;
8261b191
CW		 7579 old->load_detect_temp = false;
7580
7581 /* Make sure the crtc and connector are running */
24218aac
DV		 7582 if (connector->dpms != DRM_MODE_DPMS_ON)
7583 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7584
7173188d 7585 return true;
79e53945
JB		 7586 }
7587
7588 /* Find an unused one (if possible) */
7589 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7590 i++;
7591 if (!(encoder->possible_crtcs & (1 << i)))
7592 continue;
7593 if (!possible_crtc->enabled) {
7594 crtc = possible_crtc;
7595 break;
7596 }
79e53945
JB		 7597 }
7598
7599 /*
7600 * If we didn't find an unused CRTC, don't use any.
7601 */
7602 if (!crtc) {
7173188d
CW		 7603 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7604 return false;
79e53945
JB		 7605 }
7606
7b24056b 7607 mutex_lock(&crtc->mutex);
fc303101
DV		 7608 intel_encoder->new_crtc = to_intel_crtc(crtc);
7609 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7610
7611 intel_crtc = to_intel_crtc(crtc);
24218aac 7612 old->dpms_mode = connector->dpms;
8261b191 7613 old->load_detect_temp = true;
d2dff872 7614 old->release_fb = NULL;
79e53945 7615
6492711d
CW		 7616 if (!mode)
7617 mode = &load_detect_mode;
79e53945 7618
d2dff872
CW		 7619 /* We need a framebuffer large enough to accommodate all accesses
7620 * that the plane may generate whilst we perform load detection.
7621 * We can not rely on the fbcon either being present (we get called
7622 * during its initialisation to detect all boot displays, or it may
7623 * not even exist) or that it is large enough to satisfy the
7624 * requested mode.
7625 */
94352cf9
DV		 7626 fb = mode_fits_in_fbdev(dev, mode);
7627 if (fb == NULL) {
d2dff872 7628 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7629 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7630 old->release_fb = fb;
d2dff872
CW		 7631 } else
7632 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7633 if (IS_ERR(fb)) {
d2dff872 7634 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7635 mutex_unlock(&crtc->mutex);
0e8b3d3e 7636 return false;
79e53945 7637 }
79e53945 7638
c0c36b94 7639 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7640 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7641 if (old->release_fb)
7642 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7643 mutex_unlock(&crtc->mutex);
0e8b3d3e 7644 return false;
79e53945 7645 }
7173188d 7646
79e53945 7647 /* let the connector get through one full cycle before testing */
9d0498a2 7648 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7649 return true;
79e53945
JB		 7650}
7651
d2434ab7 7652void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7653 struct intel_load_detect_pipe *old)
79e53945 7654{
d2434ab7
DV		 7655 struct intel_encoder *intel_encoder =
7656 intel_attached_encoder(connector);
4ef69c7a 7657 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7658 struct drm_crtc *crtc = encoder->crtc;
79e53945 7659
d2dff872
CW		 7660 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7661 connector->base.id, drm_get_connector_name(connector),
7662 encoder->base.id, drm_get_encoder_name(encoder));
7663
8261b191 7664 if (old->load_detect_temp) {
fc303101
DV		 7665 to_intel_connector(connector)->new_encoder = NULL;
7666 intel_encoder->new_crtc = NULL;
7667 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7668
36206361
DV		 7669 if (old->release_fb) {
7670 drm_framebuffer_unregister_private(old->release_fb);
7671 drm_framebuffer_unreference(old->release_fb);
7672 }
d2dff872 7673
67c96400 7674 mutex_unlock(&crtc->mutex);
0622a53c 7675 return;
79e53945
JB		 7676 }
7677
c751ce4f 7678 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7679 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7680 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7681
7682 mutex_unlock(&crtc->mutex);
79e53945
JB		 7683}
7684
da4a1efa
VS		 7685static int i9xx_pll_refclk(struct drm_device *dev,
7686 const struct intel_crtc_config *pipe_config)
7687{
7688 struct drm_i915_private *dev_priv = dev->dev_private;
7689 u32 dpll = pipe_config->dpll_hw_state.dpll;
7690
7691 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7692 return dev_priv->vbt.lvds_ssc_freq * 1000;
7693 else if (HAS_PCH_SPLIT(dev))
7694 return 120000;
7695 else if (!IS_GEN2(dev))
7696 return 96000;
7697 else
7698 return 48000;
7699}
7700
79e53945 7701/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7702static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7703 struct intel_crtc_config *pipe_config)
79e53945 7704{
f1f644dc 7705 struct drm_device *dev = crtc->base.dev;
79e53945 7706 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7707 int pipe = pipe_config->cpu_transcoder;
293623f7 7708 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7709 u32 fp;
7710 intel_clock_t clock;
da4a1efa 7711 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7712
7713 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7714 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7715 else
293623f7 7716 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7717
7718 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7719 if (IS_PINEVIEW(dev)) {
7720 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7721 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7722 } else {
7723 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7724 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7725 }
7726
a6c45cf0 7727 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7728 if (IS_PINEVIEW(dev))
7729 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7730 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7731 else
7732 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7733 DPLL_FPA01_P1_POST_DIV_SHIFT);
7734
7735 switch (dpll & DPLL_MODE_MASK) {
7736 case DPLLB_MODE_DAC_SERIAL:
7737 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7738 5 : 10;
7739 break;
7740 case DPLLB_MODE_LVDS:
7741 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7742 7 : 14;
7743 break;
7744 default:
28c97730 7745 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7746 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7747 return;
79e53945
JB		 7748 }
7749
ac58c3f0 7750 if (IS_PINEVIEW(dev))
da4a1efa 7751 pineview_clock(refclk, &clock);
ac58c3f0 7752 else
da4a1efa 7753 i9xx_clock(refclk, &clock);
79e53945
JB		 7754 } else {
7755 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7756
7757 if (is_lvds) {
7758 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7759 DPLL_FPA01_P1_POST_DIV_SHIFT);
7760 clock.p2 = 14;
79e53945
JB		 7761 } else {
7762 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7763 clock.p1 = 2;
7764 else {
7765 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7766 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7767 }
7768 if (dpll & PLL_P2_DIVIDE_BY_4)
7769 clock.p2 = 4;
7770 else
7771 clock.p2 = 2;
79e53945 7772 }
da4a1efa
VS		 7773
7774 i9xx_clock(refclk, &clock);
79e53945
JB		 7775 }
7776
18442d08
VS		 7777 /*
7778 * This value includes pixel_multiplier. We will use
241bfc38 7779 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 7780 * encoder's get_config() function.
7781 */
7782 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7783}
7784
6878da05
VS		 7785int intel_dotclock_calculate(int link_freq,
7786 const struct intel_link_m_n *m_n)
f1f644dc 7787{
f1f644dc
JB		 7788 /*
7789 * The calculation for the data clock is:
1041a02f 7790 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7791 * But we want to avoid losing precison if possible, so:
1041a02f 7792 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7793 *
7794 * and the link clock is simpler:
1041a02f 7795 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7796 */
7797
6878da05
VS		 7798 if (!m_n->link_n)
7799 return 0;
f1f644dc 7800
6878da05
VS		 7801 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7802}
f1f644dc 7803
18442d08
VS		 7804static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7805 struct intel_crtc_config *pipe_config)
6878da05
VS		 7806{
7807 struct drm_device *dev = crtc->base.dev;
79e53945 7808
18442d08
VS		 7809 /* read out port_clock from the DPLL */
7810 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 7811
f1f644dc 7812 /*
18442d08 7813 * This value does not include pixel_multiplier.
241bfc38 7814 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 7815 * agree once we know their relationship in the encoder's
7816 * get_config() function.
79e53945 7817 */
241bfc38 7818 pipe_config->adjusted_mode.crtc_clock =
18442d08
VS		 7819 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7820 &pipe_config->fdi_m_n);
79e53945
JB		 7821}
7822
7823/** Returns the currently programmed mode of the given pipe. */
7824struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7825 struct drm_crtc *crtc)
7826{
548f245b 7827 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7829 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7830 struct drm_display_mode *mode;
f1f644dc 7831 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7832 int htot = I915_READ(HTOTAL(cpu_transcoder));
7833 int hsync = I915_READ(HSYNC(cpu_transcoder));
7834 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7835 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7836 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7837
7838 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7839 if (!mode)
7840 return NULL;
7841
f1f644dc
JB		 7842 /*
7843 * Construct a pipe_config sufficient for getting the clock info
7844 * back out of crtc_clock_get.
7845 *
7846 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7847 * to use a real value here instead.
7848 */
293623f7 7849 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7850 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7851 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7852 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7853 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7854 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7855
773ae034 7856 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 7857 mode->hdisplay = (htot & 0xffff) + 1;
7858 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7859 mode->hsync_start = (hsync & 0xffff) + 1;
7860 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7861 mode->vdisplay = (vtot & 0xffff) + 1;
7862 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7863 mode->vsync_start = (vsync & 0xffff) + 1;
7864 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7865
7866 drm_mode_set_name(mode);
79e53945
JB		 7867
7868 return mode;
7869}
7870
3dec0095 7871static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7872{
7873 struct drm_device *dev = crtc->dev;
7874 drm_i915_private_t *dev_priv = dev->dev_private;
7875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7876 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7877 int dpll_reg = DPLL(pipe);
7878 int dpll;
652c393a 7879
bad720ff 7880 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7881 return;
7882
7883 if (!dev_priv->lvds_downclock_avail)
7884 return;
7885
dbdc6479 7886 dpll = I915_READ(dpll_reg);
652c393a 7887 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7888 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7889
8ac5a6d5 7890 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7891
7892 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7893 I915_WRITE(dpll_reg, dpll);
9d0498a2 7894 intel_wait_for_vblank(dev, pipe);
dbdc6479 7895
652c393a
JB		 7896 dpll = I915_READ(dpll_reg);
7897 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7898 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7899 }
652c393a
JB		 7900}
7901
7902static void intel_decrease_pllclock(struct drm_crtc *crtc)
7903{
7904 struct drm_device *dev = crtc->dev;
7905 drm_i915_private_t *dev_priv = dev->dev_private;
7906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7907
bad720ff 7908 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7909 return;
7910
7911 if (!dev_priv->lvds_downclock_avail)
7912 return;
7913
7914 /*
7915 * Since this is called by a timer, we should never get here in
7916 * the manual case.
7917 */
7918 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7919 int pipe = intel_crtc->pipe;
7920 int dpll_reg = DPLL(pipe);
7921 int dpll;
f6e5b160 7922
44d98a61 7923 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7924
8ac5a6d5 7925 assert_panel_unlocked(dev_priv, pipe);
652c393a 7926
dc257cf1 7927 dpll = I915_READ(dpll_reg);
652c393a
JB		 7928 dpll |= DISPLAY_RATE_SELECT_FPA1;
7929 I915_WRITE(dpll_reg, dpll);
9d0498a2 7930 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7931 dpll = I915_READ(dpll_reg);
7932 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7933 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7934 }
7935
7936}
7937
f047e395
CW		 7938void intel_mark_busy(struct drm_device *dev)
7939{
c67a470b
PZ		 7940 struct drm_i915_private *dev_priv = dev->dev_private;
7941
7942 hsw_package_c8_gpu_busy(dev_priv);
7943 i915_update_gfx_val(dev_priv);
f047e395
CW		 7944}
7945
7946void intel_mark_idle(struct drm_device *dev)
652c393a 7947{
c67a470b 7948 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7949 struct drm_crtc *crtc;
652c393a 7950
c67a470b
PZ		 7951 hsw_package_c8_gpu_idle(dev_priv);
7952
652c393a
JB		 7953 if (!i915_powersave)
7954 return;
7955
652c393a 7956 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7957 if (!crtc->fb)
7958 continue;
7959
725a5b54 7960 intel_decrease_pllclock(crtc);
652c393a 7961 }
b29c19b6
CW		 7962
7963 if (dev_priv->info->gen >= 6)
7964 gen6_rps_idle(dev->dev_private);
652c393a
JB		 7965}
7966
c65355bb
CW		 7967void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7968 struct intel_ring_buffer *ring)
652c393a 7969{
f047e395
CW		 7970 struct drm_device *dev = obj->base.dev;
7971 struct drm_crtc *crtc;
652c393a 7972
f047e395 7973 if (!i915_powersave)
acb87dfb
CW		 7974 return;
7975
652c393a
JB		 7976 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7977 if (!crtc->fb)
7978 continue;
7979
c65355bb
CW		 7980 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7981 continue;
7982
7983 intel_increase_pllclock(crtc);
7984 if (ring && intel_fbc_enabled(dev))
7985 ring->fbc_dirty = true;
652c393a
JB		 7986 }
7987}
7988
79e53945
JB		 7989static void intel_crtc_destroy(struct drm_crtc *crtc)
7990{
7991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7992 struct drm_device *dev = crtc->dev;
7993 struct intel_unpin_work *work;
7994 unsigned long flags;
7995
7996 spin_lock_irqsave(&dev->event_lock, flags);
7997 work = intel_crtc->unpin_work;
7998 intel_crtc->unpin_work = NULL;
7999 spin_unlock_irqrestore(&dev->event_lock, flags);
8000
8001 if (work) {
8002 cancel_work_sync(&work->work);
8003 kfree(work);
8004 }
79e53945 8005
40ccc72b
MK		 8006 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8007
79e53945 8008 drm_crtc_cleanup(crtc);
67e77c5a 8009
79e53945
JB		 8010 kfree(intel_crtc);
8011}
8012
6b95a207
KH		 8013static void intel_unpin_work_fn(struct work_struct *__work)
8014{
8015 struct intel_unpin_work *work =
8016 container_of(__work, struct intel_unpin_work, work);
b4a98e57 8017 struct drm_device *dev = work->crtc->dev;
6b95a207 8018
b4a98e57 8019 mutex_lock(&dev->struct_mutex);
1690e1eb 8020 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 8021 drm_gem_object_unreference(&work->pending_flip_obj->base);
8022 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 8023
b4a98e57
CW		 8024 intel_update_fbc(dev);
8025 mutex_unlock(&dev->struct_mutex);
8026
8027 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8028 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8029
6b95a207
KH		 8030 kfree(work);
8031}
8032
1afe3e9d 8033static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 8034 struct drm_crtc *crtc)
6b95a207
KH		 8035{
8036 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 8037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8038 struct intel_unpin_work *work;
6b95a207
KH		 8039 unsigned long flags;
8040
8041 /* Ignore early vblank irqs */
8042 if (intel_crtc == NULL)
8043 return;
8044
8045 spin_lock_irqsave(&dev->event_lock, flags);
8046 work = intel_crtc->unpin_work;
e7d841ca
CW		 8047
8048 /* Ensure we don't miss a work->pending update ... */
8049 smp_rmb();
8050
8051 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 8052 spin_unlock_irqrestore(&dev->event_lock, flags);
8053 return;
8054 }
8055
e7d841ca
CW		 8056 /* and that the unpin work is consistent wrt ->pending. */
8057 smp_rmb();
8058
6b95a207 8059 intel_crtc->unpin_work = NULL;
6b95a207 8060
45a066eb
RC		 8061 if (work->event)
8062 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 8063
0af7e4df
MK		 8064 drm_vblank_put(dev, intel_crtc->pipe);
8065
6b95a207
KH		 8066 spin_unlock_irqrestore(&dev->event_lock, flags);
8067
2c10d571 8068 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 8069
8070 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 8071
8072 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 8073}
8074
1afe3e9d
JB		 8075void intel_finish_page_flip(struct drm_device *dev, int pipe)
8076{
8077 drm_i915_private_t *dev_priv = dev->dev_private;
8078 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8079
49b14a5c 8080 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 8081}
8082
8083void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8084{
8085 drm_i915_private_t *dev_priv = dev->dev_private;
8086 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8087
49b14a5c 8088 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 8089}
8090
6b95a207
KH		 8091void intel_prepare_page_flip(struct drm_device *dev, int plane)
8092{
8093 drm_i915_private_t *dev_priv = dev->dev_private;
8094 struct intel_crtc *intel_crtc =
8095 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8096 unsigned long flags;
8097
e7d841ca
CW		 8098 /* NB: An MMIO update of the plane base pointer will also
8099 * generate a page-flip completion irq, i.e. every modeset
8100 * is also accompanied by a spurious intel_prepare_page_flip().
8101 */
6b95a207 8102 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 8103 if (intel_crtc->unpin_work)
8104 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 8105 spin_unlock_irqrestore(&dev->event_lock, flags);
8106}
8107
e7d841ca
CW		 8108inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8109{
8110 /* Ensure that the work item is consistent when activating it ... */
8111 smp_wmb();
8112 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8113 /* and that it is marked active as soon as the irq could fire. */
8114 smp_wmb();
8115}
8116
8c9f3aaf
JB		 8117static int intel_gen2_queue_flip(struct drm_device *dev,
8118 struct drm_crtc *crtc,
8119 struct drm_framebuffer *fb,
ed8d1975
KP		 8120 struct drm_i915_gem_object *obj,
8121 uint32_t flags)
8c9f3aaf
JB		 8122{
8123 struct drm_i915_private *dev_priv = dev->dev_private;
8124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 8125 u32 flip_mask;
6d90c952 8126 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8127 int ret;
8128
6d90c952 8129 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8130 if (ret)
83d4092b 8131 goto err;
8c9f3aaf 8132
6d90c952 8133 ret = intel_ring_begin(ring, 6);
8c9f3aaf 8134 if (ret)
83d4092b 8135 goto err_unpin;
8c9f3aaf
JB		 8136
8137 /* Can't queue multiple flips, so wait for the previous
8138 * one to finish before executing the next.
8139 */
8140 if (intel_crtc->plane)
8141 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8142 else
8143 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 8144 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8145 intel_ring_emit(ring, MI_NOOP);
8146 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8147 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8148 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 8149 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 8150 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 8151
8152 intel_mark_page_flip_active(intel_crtc);
09246732 8153 __intel_ring_advance(ring);
83d4092b
CW		 8154 return 0;
8155
8156err_unpin:
8157 intel_unpin_fb_obj(obj);
8158err:
8c9f3aaf
JB		 8159 return ret;
8160}
8161
8162static int intel_gen3_queue_flip(struct drm_device *dev,
8163 struct drm_crtc *crtc,
8164 struct drm_framebuffer *fb,
ed8d1975
KP		 8165 struct drm_i915_gem_object *obj,
8166 uint32_t flags)
8c9f3aaf
JB		 8167{
8168 struct drm_i915_private *dev_priv = dev->dev_private;
8169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 8170 u32 flip_mask;
6d90c952 8171 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8172 int ret;
8173
6d90c952 8174 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8175 if (ret)
83d4092b 8176 goto err;
8c9f3aaf 8177
6d90c952 8178 ret = intel_ring_begin(ring, 6);
8c9f3aaf 8179 if (ret)
83d4092b 8180 goto err_unpin;
8c9f3aaf
JB		 8181
8182 if (intel_crtc->plane)
8183 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8184 else
8185 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 8186 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8187 intel_ring_emit(ring, MI_NOOP);
8188 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8189 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8190 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 8191 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 8192 intel_ring_emit(ring, MI_NOOP);
8193
e7d841ca 8194 intel_mark_page_flip_active(intel_crtc);
09246732 8195 __intel_ring_advance(ring);
83d4092b
CW		 8196 return 0;
8197
8198err_unpin:
8199 intel_unpin_fb_obj(obj);
8200err:
8c9f3aaf
JB		 8201 return ret;
8202}
8203
8204static int intel_gen4_queue_flip(struct drm_device *dev,
8205 struct drm_crtc *crtc,
8206 struct drm_framebuffer *fb,
ed8d1975
KP		 8207 struct drm_i915_gem_object *obj,
8208 uint32_t flags)
8c9f3aaf
JB		 8209{
8210 struct drm_i915_private *dev_priv = dev->dev_private;
8211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8212 uint32_t pf, pipesrc;
6d90c952 8213 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8214 int ret;
8215
6d90c952 8216 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8217 if (ret)
83d4092b 8218 goto err;
8c9f3aaf 8219
6d90c952 8220 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8221 if (ret)
83d4092b 8222 goto err_unpin;
8c9f3aaf
JB		 8223
8224 /* i965+ uses the linear or tiled offsets from the
8225 * Display Registers (which do not change across a page-flip)
8226 * so we need only reprogram the base address.
8227 */
6d90c952
DV		 8228 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8229 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8230 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 8231 intel_ring_emit(ring,
f343c5f6 8232 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 8233 obj->tiling_mode);
8c9f3aaf
JB		 8234
8235 /* XXX Enabling the panel-fitter across page-flip is so far
8236 * untested on non-native modes, so ignore it for now.
8237 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8238 */
8239 pf = 0;
8240 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8241 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8242
8243 intel_mark_page_flip_active(intel_crtc);
09246732 8244 __intel_ring_advance(ring);
83d4092b
CW		 8245 return 0;
8246
8247err_unpin:
8248 intel_unpin_fb_obj(obj);
8249err:
8c9f3aaf
JB		 8250 return ret;
8251}
8252
8253static int intel_gen6_queue_flip(struct drm_device *dev,
8254 struct drm_crtc *crtc,
8255 struct drm_framebuffer *fb,
ed8d1975
KP		 8256 struct drm_i915_gem_object *obj,
8257 uint32_t flags)
8c9f3aaf
JB		 8258{
8259 struct drm_i915_private *dev_priv = dev->dev_private;
8260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 8261 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8262 uint32_t pf, pipesrc;
8263 int ret;
8264
6d90c952 8265 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8266 if (ret)
83d4092b 8267 goto err;
8c9f3aaf 8268
6d90c952 8269 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8270 if (ret)
83d4092b 8271 goto err_unpin;
8c9f3aaf 8272
6d90c952
DV		 8273 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8274 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8275 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 8276 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 8277
dc257cf1
DV		 8278 /* Contrary to the suggestions in the documentation,
8279 * "Enable Panel Fitter" does not seem to be required when page
8280 * flipping with a non-native mode, and worse causes a normal
8281 * modeset to fail.
8282 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8283 */
8284 pf = 0;
8c9f3aaf 8285 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8286 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8287
8288 intel_mark_page_flip_active(intel_crtc);
09246732 8289 __intel_ring_advance(ring);
83d4092b
CW		 8290 return 0;
8291
8292err_unpin:
8293 intel_unpin_fb_obj(obj);
8294err:
8c9f3aaf
JB		 8295 return ret;
8296}
8297
7c9017e5
JB		 8298static int intel_gen7_queue_flip(struct drm_device *dev,
8299 struct drm_crtc *crtc,
8300 struct drm_framebuffer *fb,
ed8d1975
KP		 8301 struct drm_i915_gem_object *obj,
8302 uint32_t flags)
7c9017e5
JB		 8303{
8304 struct drm_i915_private *dev_priv = dev->dev_private;
8305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 8306 struct intel_ring_buffer *ring;
cb05d8de 8307 uint32_t plane_bit = 0;
ffe74d75
CW		 8308 int len, ret;
8309
8310 ring = obj->ring;
1c5fd085 8311 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
ffe74d75 8312 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 8313
8314 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8315 if (ret)
83d4092b 8316 goto err;
7c9017e5 8317
cb05d8de
DV		 8318 switch(intel_crtc->plane) {
8319 case PLANE_A:
8320 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8321 break;
8322 case PLANE_B:
8323 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8324 break;
8325 case PLANE_C:
8326 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8327 break;
8328 default:
8329 WARN_ONCE(1, "unknown plane in flip command\n");
8330 ret = -ENODEV;
ab3951eb 8331 goto err_unpin;
cb05d8de
DV		 8332 }
8333
ffe74d75
CW		 8334 len = 4;
8335 if (ring->id == RCS)
8336 len += 6;
8337
8338 ret = intel_ring_begin(ring, len);
7c9017e5 8339 if (ret)
83d4092b 8340 goto err_unpin;
7c9017e5 8341
ffe74d75
CW		 8342 /* Unmask the flip-done completion message. Note that the bspec says that
8343 * we should do this for both the BCS and RCS, and that we must not unmask
8344 * more than one flip event at any time (or ensure that one flip message
8345 * can be sent by waiting for flip-done prior to queueing new flips).
8346 * Experimentation says that BCS works despite DERRMR masking all
8347 * flip-done completion events and that unmasking all planes at once
8348 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8349 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8350 */
8351 if (ring->id == RCS) {
8352 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8353 intel_ring_emit(ring, DERRMR);
8354 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8355 DERRMR_PIPEB_PRI_FLIP_DONE |
8356 DERRMR_PIPEC_PRI_FLIP_DONE));
8357 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8358 intel_ring_emit(ring, DERRMR);
8359 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8360 }
8361
cb05d8de 8362 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8363 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8364 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8365 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8366
8367 intel_mark_page_flip_active(intel_crtc);
09246732 8368 __intel_ring_advance(ring);
83d4092b
CW		 8369 return 0;
8370
8371err_unpin:
8372 intel_unpin_fb_obj(obj);
8373err:
7c9017e5
JB		 8374 return ret;
8375}
8376
8c9f3aaf
JB		 8377static int intel_default_queue_flip(struct drm_device *dev,
8378 struct drm_crtc *crtc,
8379 struct drm_framebuffer *fb,
ed8d1975
KP		 8380 struct drm_i915_gem_object *obj,
8381 uint32_t flags)
8c9f3aaf
JB		 8382{
8383 return -ENODEV;
8384}
8385
6b95a207
KH		 8386static int intel_crtc_page_flip(struct drm_crtc *crtc,
8387 struct drm_framebuffer *fb,
ed8d1975
KP		 8388 struct drm_pending_vblank_event *event,
8389 uint32_t page_flip_flags)
6b95a207
KH		 8390{
8391 struct drm_device *dev = crtc->dev;
8392 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8393 struct drm_framebuffer *old_fb = crtc->fb;
8394 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8396 struct intel_unpin_work *work;
8c9f3aaf 8397 unsigned long flags;
52e68630 8398 int ret;
6b95a207 8399
e6a595d2
VS		 8400 /* Can't change pixel format via MI display flips. */
8401 if (fb->pixel_format != crtc->fb->pixel_format)
8402 return -EINVAL;
8403
8404 /*
8405 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8406 * Note that pitch changes could also affect these register.
8407 */
8408 if (INTEL_INFO(dev)->gen > 3 &&
8409 (fb->offsets[0] != crtc->fb->offsets[0] ||
8410 fb->pitches[0] != crtc->fb->pitches[0]))
8411 return -EINVAL;
8412
b14c5679 8413 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 8414 if (work == NULL)
8415 return -ENOMEM;
8416
6b95a207 8417 work->event = event;
b4a98e57 8418 work->crtc = crtc;
4a35f83b 8419 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8420 INIT_WORK(&work->work, intel_unpin_work_fn);
8421
7317c75e
JB		 8422 ret = drm_vblank_get(dev, intel_crtc->pipe);
8423 if (ret)
8424 goto free_work;
8425
6b95a207
KH		 8426 /* We borrow the event spin lock for protecting unpin_work */
8427 spin_lock_irqsave(&dev->event_lock, flags);
8428 if (intel_crtc->unpin_work) {
8429 spin_unlock_irqrestore(&dev->event_lock, flags);
8430 kfree(work);
7317c75e 8431 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8432
8433 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8434 return -EBUSY;
8435 }
8436 intel_crtc->unpin_work = work;
8437 spin_unlock_irqrestore(&dev->event_lock, flags);
8438
b4a98e57
CW		 8439 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8440 flush_workqueue(dev_priv->wq);
8441
79158103
CW		 8442 ret = i915_mutex_lock_interruptible(dev);
8443 if (ret)
8444 goto cleanup;
6b95a207 8445
75dfca80 8446 /* Reference the objects for the scheduled work. */
05394f39
CW		 8447 drm_gem_object_reference(&work->old_fb_obj->base);
8448 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8449
8450 crtc->fb = fb;
96b099fd 8451
e1f99ce6 8452 work->pending_flip_obj = obj;
e1f99ce6 8453
4e5359cd
SF		 8454 work->enable_stall_check = true;
8455
b4a98e57 8456 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8457 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8458
ed8d1975 8459 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8460 if (ret)
8461 goto cleanup_pending;
6b95a207 8462
7782de3b 8463 intel_disable_fbc(dev);
c65355bb 8464 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8465 mutex_unlock(&dev->struct_mutex);
8466
e5510fac
JB		 8467 trace_i915_flip_request(intel_crtc->plane, obj);
8468
6b95a207 8469 return 0;
96b099fd 8470
8c9f3aaf 8471cleanup_pending:
b4a98e57 8472 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8473 crtc->fb = old_fb;
05394f39
CW		 8474 drm_gem_object_unreference(&work->old_fb_obj->base);
8475 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8476 mutex_unlock(&dev->struct_mutex);
8477
79158103 8478cleanup:
96b099fd
CW		 8479 spin_lock_irqsave(&dev->event_lock, flags);
8480 intel_crtc->unpin_work = NULL;
8481 spin_unlock_irqrestore(&dev->event_lock, flags);
8482
7317c75e
JB		 8483 drm_vblank_put(dev, intel_crtc->pipe);
8484free_work:
96b099fd
CW		 8485 kfree(work);
8486
8487 return ret;
6b95a207
KH		 8488}
8489
f6e5b160 8490static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8491 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8492 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8493};
8494
50f56119
DV		 8495static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8496 struct drm_crtc *crtc)
8497{
8498 struct drm_device *dev;
8499 struct drm_crtc *tmp;
8500 int crtc_mask = 1;
47f1c6c9 8501
50f56119 8502 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8503
50f56119 8504 dev = crtc->dev;
47f1c6c9 8505
50f56119
DV		 8506 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8507 if (tmp == crtc)
8508 break;
8509 crtc_mask <<= 1;
8510 }
47f1c6c9 8511
50f56119
DV		 8512 if (encoder->possible_crtcs & crtc_mask)
8513 return true;
8514 return false;
47f1c6c9 8515}
79e53945 8516
9a935856
DV		 8517/**
8518 * intel_modeset_update_staged_output_state
8519 *
8520 * Updates the staged output configuration state, e.g. after we've read out the
8521 * current hw state.
8522 */
8523static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8524{
9a935856
DV		 8525 struct intel_encoder *encoder;
8526 struct intel_connector *connector;
f6e5b160 8527
9a935856
DV		 8528 list_for_each_entry(connector, &dev->mode_config.connector_list,
8529 base.head) {
8530 connector->new_encoder =
8531 to_intel_encoder(connector->base.encoder);
8532 }
f6e5b160 8533
9a935856
DV		 8534 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8535 base.head) {
8536 encoder->new_crtc =
8537 to_intel_crtc(encoder->base.crtc);
8538 }
f6e5b160
CW		 8539}
8540
9a935856
DV		 8541/**
8542 * intel_modeset_commit_output_state
8543 *
8544 * This function copies the stage display pipe configuration to the real one.
8545 */
8546static void intel_modeset_commit_output_state(struct drm_device *dev)
8547{
8548 struct intel_encoder *encoder;
8549 struct intel_connector *connector;
f6e5b160 8550
9a935856
DV		 8551 list_for_each_entry(connector, &dev->mode_config.connector_list,
8552 base.head) {
8553 connector->base.encoder = &connector->new_encoder->base;
8554 }
f6e5b160 8555
9a935856
DV		 8556 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8557 base.head) {
8558 encoder->base.crtc = &encoder->new_crtc->base;
8559 }
8560}
8561
050f7aeb
DV		 8562static void
8563connected_sink_compute_bpp(struct intel_connector * connector,
8564 struct intel_crtc_config *pipe_config)
8565{
8566 int bpp = pipe_config->pipe_bpp;
8567
8568 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8569 connector->base.base.id,
8570 drm_get_connector_name(&connector->base));
8571
8572 /* Don't use an invalid EDID bpc value */
8573 if (connector->base.display_info.bpc &&
8574 connector->base.display_info.bpc * 3 < bpp) {
8575 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8576 bpp, connector->base.display_info.bpc*3);
8577 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8578 }
8579
8580 /* Clamp bpp to 8 on screens without EDID 1.4 */
8581 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8582 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8583 bpp);
8584 pipe_config->pipe_bpp = 24;
8585 }
8586}
8587
4e53c2e0 8588static int
050f7aeb
DV		 8589compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8590 struct drm_framebuffer *fb,
8591 struct intel_crtc_config *pipe_config)
4e53c2e0 8592{
050f7aeb
DV		 8593 struct drm_device *dev = crtc->base.dev;
8594 struct intel_connector *connector;
4e53c2e0
DV		 8595 int bpp;
8596
d42264b1
DV		 8597 switch (fb->pixel_format) {
8598 case DRM_FORMAT_C8:
4e53c2e0
DV		 8599 bpp = 8*3; /* since we go through a colormap */
8600 break;
d42264b1
DV		 8601 case DRM_FORMAT_XRGB1555:
8602 case DRM_FORMAT_ARGB1555:
8603 /* checked in intel_framebuffer_init already */
8604 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8605 return -EINVAL;
8606 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8607 bpp = 6*3; /* min is 18bpp */
8608 break;
d42264b1
DV		 8609 case DRM_FORMAT_XBGR8888:
8610 case DRM_FORMAT_ABGR8888:
8611 /* checked in intel_framebuffer_init already */
8612 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8613 return -EINVAL;
8614 case DRM_FORMAT_XRGB8888:
8615 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8616 bpp = 8*3;
8617 break;
d42264b1
DV		 8618 case DRM_FORMAT_XRGB2101010:
8619 case DRM_FORMAT_ARGB2101010:
8620 case DRM_FORMAT_XBGR2101010:
8621 case DRM_FORMAT_ABGR2101010:
8622 /* checked in intel_framebuffer_init already */
8623 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8624 return -EINVAL;
4e53c2e0
DV		 8625 bpp = 10*3;
8626 break;
baba133a 8627 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8628 default:
8629 DRM_DEBUG_KMS("unsupported depth\n");
8630 return -EINVAL;
8631 }
8632
4e53c2e0
DV		 8633 pipe_config->pipe_bpp = bpp;
8634
8635 /* Clamp display bpp to EDID value */
8636 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8637 base.head) {
1b829e05
DV		 8638 if (!connector->new_encoder ||
8639 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8640 continue;
8641
050f7aeb 8642 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8643 }
8644
8645 return bpp;
8646}
8647
644db711
DV		 8648static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8649{
8650 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8651 "type: 0x%x flags: 0x%x\n",
1342830c 8652 mode->crtc_clock,
644db711
DV		 8653 mode->crtc_hdisplay, mode->crtc_hsync_start,
8654 mode->crtc_hsync_end, mode->crtc_htotal,
8655 mode->crtc_vdisplay, mode->crtc_vsync_start,
8656 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8657}
8658
c0b03411
DV		 8659static void intel_dump_pipe_config(struct intel_crtc *crtc,
8660 struct intel_crtc_config *pipe_config,
8661 const char *context)
8662{
8663 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8664 context, pipe_name(crtc->pipe));
8665
8666 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8667 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8668 pipe_config->pipe_bpp, pipe_config->dither);
8669 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8670 pipe_config->has_pch_encoder,
8671 pipe_config->fdi_lanes,
8672 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8673 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8674 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8675 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8676 pipe_config->has_dp_encoder,
8677 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8678 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8679 pipe_config->dp_m_n.tu);
c0b03411
DV		 8680 DRM_DEBUG_KMS("requested mode:\n");
8681 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8682 DRM_DEBUG_KMS("adjusted mode:\n");
8683 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
644db711 8684 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
d71b8d4a 8685 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8686 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8687 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8688 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8689 pipe_config->gmch_pfit.control,
8690 pipe_config->gmch_pfit.pgm_ratios,
8691 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 8692 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 8693 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 8694 pipe_config->pch_pfit.size,
8695 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 8696 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 8697 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 8698}
8699
accfc0c5
DV		 8700static bool check_encoder_cloning(struct drm_crtc *crtc)
8701{
8702 int num_encoders = 0;
8703 bool uncloneable_encoders = false;
8704 struct intel_encoder *encoder;
8705
8706 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8707 base.head) {
8708 if (&encoder->new_crtc->base != crtc)
8709 continue;
8710
8711 num_encoders++;
8712 if (!encoder->cloneable)
8713 uncloneable_encoders = true;
8714 }
8715
8716 return !(num_encoders > 1 && uncloneable_encoders);
8717}
8718
b8cecdf5
DV		 8719static struct intel_crtc_config *
8720intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8721 struct drm_framebuffer *fb,
b8cecdf5 8722 struct drm_display_mode *mode)
ee7b9f93 8723{
7758a113 8724 struct drm_device *dev = crtc->dev;
7758a113 8725 struct intel_encoder *encoder;
b8cecdf5 8726 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8727 int plane_bpp, ret = -EINVAL;
8728 bool retry = true;
ee7b9f93 8729
accfc0c5
DV		 8730 if (!check_encoder_cloning(crtc)) {
8731 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8732 return ERR_PTR(-EINVAL);
8733 }
8734
b8cecdf5
DV		 8735 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8736 if (!pipe_config)
7758a113
DV		 8737 return ERR_PTR(-ENOMEM);
8738
b8cecdf5
DV		 8739 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8740 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd 8741
e143a21c
DV		 8742 pipe_config->cpu_transcoder =
8743 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8744 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8745
2960bc9c
ID		 8746 /*
8747 * Sanitize sync polarity flags based on requested ones. If neither
8748 * positive or negative polarity is requested, treat this as meaning
8749 * negative polarity.
8750 */
8751 if (!(pipe_config->adjusted_mode.flags &
8752 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8753 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8754
8755 if (!(pipe_config->adjusted_mode.flags &
8756 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8757 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8758
050f7aeb
DV		 8759 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8760 * plane pixel format and any sink constraints into account. Returns the
8761 * source plane bpp so that dithering can be selected on mismatches
8762 * after encoders and crtc also have had their say. */
8763 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8764 fb, pipe_config);
4e53c2e0
DV		 8765 if (plane_bpp < 0)
8766 goto fail;
8767
e41a56be
VS		 8768 /*
8769 * Determine the real pipe dimensions. Note that stereo modes can
8770 * increase the actual pipe size due to the frame doubling and
8771 * insertion of additional space for blanks between the frame. This
8772 * is stored in the crtc timings. We use the requested mode to do this
8773 * computation to clearly distinguish it from the adjusted mode, which
8774 * can be changed by the connectors in the below retry loop.
8775 */
8776 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8777 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8778 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8779
e29c22c0 8780encoder_retry:
ef1b460d 8781 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8782 pipe_config->port_clock = 0;
ef1b460d 8783 pipe_config->pixel_multiplier = 1;
ff9a6750 8784
135c81b8 8785 /* Fill in default crtc timings, allow encoders to overwrite them. */
6ce70f5e 8786 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
135c81b8 8787
7758a113
DV		 8788 /* Pass our mode to the connectors and the CRTC to give them a chance to
8789 * adjust it according to limitations or connector properties, and also
8790 * a chance to reject the mode entirely.
47f1c6c9 8791 */
7758a113
DV		 8792 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8793 base.head) {
47f1c6c9 8794
7758a113
DV		 8795 if (&encoder->new_crtc->base != crtc)
8796 continue;
7ae89233 8797
efea6e8e
DV		 8798 if (!(encoder->compute_config(encoder, pipe_config))) {
8799 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8800 goto fail;
8801 }
ee7b9f93 8802 }
47f1c6c9 8803
ff9a6750
DV		 8804 /* Set default port clock if not overwritten by the encoder. Needs to be
8805 * done afterwards in case the encoder adjusts the mode. */
8806 if (!pipe_config->port_clock)
241bfc38
DL		 8807 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8808 * pipe_config->pixel_multiplier;
ff9a6750 8809
a43f6e0f 8810 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8811 if (ret < 0) {
7758a113
DV		 8812 DRM_DEBUG_KMS("CRTC fixup failed\n");
8813 goto fail;
ee7b9f93 8814 }
e29c22c0
DV		 8815
8816 if (ret == RETRY) {
8817 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8818 ret = -EINVAL;
8819 goto fail;
8820 }
8821
8822 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8823 retry = false;
8824 goto encoder_retry;
8825 }
8826
4e53c2e0
DV		 8827 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8828 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8829 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8830
b8cecdf5 8831 return pipe_config;
7758a113 8832fail:
b8cecdf5 8833 kfree(pipe_config);
e29c22c0 8834 return ERR_PTR(ret);
ee7b9f93 8835}
47f1c6c9 8836
e2e1ed41
DV		 8837/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8838 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8839static void
8840intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8841 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8842{
8843 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8844 struct drm_device *dev = crtc->dev;
8845 struct intel_encoder *encoder;
8846 struct intel_connector *connector;
8847 struct drm_crtc *tmp_crtc;
79e53945 8848
e2e1ed41 8849 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8850
e2e1ed41
DV		 8851 /* Check which crtcs have changed outputs connected to them, these need
8852 * to be part of the prepare_pipes mask. We don't (yet) support global
8853 * modeset across multiple crtcs, so modeset_pipes will only have one
8854 * bit set at most. */
8855 list_for_each_entry(connector, &dev->mode_config.connector_list,
8856 base.head) {
8857 if (connector->base.encoder == &connector->new_encoder->base)
8858 continue;
79e53945 8859
e2e1ed41
DV		 8860 if (connector->base.encoder) {
8861 tmp_crtc = connector->base.encoder->crtc;
8862
8863 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8864 }
8865
8866 if (connector->new_encoder)
8867 *prepare_pipes |=
8868 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8869 }
8870
e2e1ed41
DV		 8871 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8872 base.head) {
8873 if (encoder->base.crtc == &encoder->new_crtc->base)
8874 continue;
8875
8876 if (encoder->base.crtc) {
8877 tmp_crtc = encoder->base.crtc;
8878
8879 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8880 }
8881
8882 if (encoder->new_crtc)
8883 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8884 }
8885
e2e1ed41
DV		 8886 /* Check for any pipes that will be fully disabled ... */
8887 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8888 base.head) {
8889 bool used = false;
22fd0fab 8890
e2e1ed41
DV		 8891 /* Don't try to disable disabled crtcs. */
8892 if (!intel_crtc->base.enabled)
8893 continue;
7e7d76c3 8894
e2e1ed41
DV		 8895 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8896 base.head) {
8897 if (encoder->new_crtc == intel_crtc)
8898 used = true;
8899 }
8900
8901 if (!used)
8902 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8903 }
8904
e2e1ed41
DV		 8905
8906 /* set_mode is also used to update properties on life display pipes. */
8907 intel_crtc = to_intel_crtc(crtc);
8908 if (crtc->enabled)
8909 *prepare_pipes |= 1 << intel_crtc->pipe;
8910
b6c5164d
DV		 8911 /*
8912 * For simplicity do a full modeset on any pipe where the output routing
8913 * changed. We could be more clever, but that would require us to be
8914 * more careful with calling the relevant encoder->mode_set functions.
8915 */
e2e1ed41
DV		 8916 if (*prepare_pipes)
8917 *modeset_pipes = *prepare_pipes;
8918
8919 /* ... and mask these out. */
8920 *modeset_pipes &= ~(*disable_pipes);
8921 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8922
8923 /*
8924 * HACK: We don't (yet) fully support global modesets. intel_set_config
8925 * obies this rule, but the modeset restore mode of
8926 * intel_modeset_setup_hw_state does not.
8927 */
8928 *modeset_pipes &= 1 << intel_crtc->pipe;
8929 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8930
8931 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8932 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8933}
79e53945 8934
ea9d758d 8935static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8936{
ea9d758d 8937 struct drm_encoder *encoder;
f6e5b160 8938 struct drm_device *dev = crtc->dev;
f6e5b160 8939
ea9d758d
DV		 8940 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8941 if (encoder->crtc == crtc)
8942 return true;
8943
8944 return false;
8945}
8946
8947static void
8948intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8949{
8950 struct intel_encoder *intel_encoder;
8951 struct intel_crtc *intel_crtc;
8952 struct drm_connector *connector;
8953
8954 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8955 base.head) {
8956 if (!intel_encoder->base.crtc)
8957 continue;
8958
8959 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8960
8961 if (prepare_pipes & (1 << intel_crtc->pipe))
8962 intel_encoder->connectors_active = false;
8963 }
8964
8965 intel_modeset_commit_output_state(dev);
8966
8967 /* Update computed state. */
8968 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8969 base.head) {
8970 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8971 }
8972
8973 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8974 if (!connector->encoder || !connector->encoder->crtc)
8975 continue;
8976
8977 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8978
8979 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8980 struct drm_property *dpms_property =
8981 dev->mode_config.dpms_property;
8982
ea9d758d 8983 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8984 drm_object_property_set_value(&connector->base,
68d34720
DV		 8985 dpms_property,
8986 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8987
8988 intel_encoder = to_intel_encoder(connector->encoder);
8989 intel_encoder->connectors_active = true;
8990 }
8991 }
8992
8993}
8994
3bd26263 8995static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8996{
3bd26263 8997 int diff;
f1f644dc
JB		 8998
8999 if (clock1 == clock2)
9000 return true;
9001
9002 if (!clock1 || !clock2)
9003 return false;
9004
9005 diff = abs(clock1 - clock2);
9006
9007 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9008 return true;
9009
9010 return false;
9011}
9012
25c5b266
DV		 9013#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9014 list_for_each_entry((intel_crtc), \
9015 &(dev)->mode_config.crtc_list, \
9016 base.head) \
0973f18f 9017 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 9018
0e8ffe1b 9019static bool
2fa2fe9a
DV		 9020intel_pipe_config_compare(struct drm_device *dev,
9021 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 9022 struct intel_crtc_config *pipe_config)
9023{
66e985c0
DV		 9024#define PIPE_CONF_CHECK_X(name) \
9025 if (current_config->name != pipe_config->name) { \
9026 DRM_ERROR("mismatch in " #name " " \
9027 "(expected 0x%08x, found 0x%08x)\n", \
9028 current_config->name, \
9029 pipe_config->name); \
9030 return false; \
9031 }
9032
08a24034
DV		 9033#define PIPE_CONF_CHECK_I(name) \
9034 if (current_config->name != pipe_config->name) { \
9035 DRM_ERROR("mismatch in " #name " " \
9036 "(expected %i, found %i)\n", \
9037 current_config->name, \
9038 pipe_config->name); \
9039 return false; \
88adfff1
DV		 9040 }
9041
1bd1bd80
DV		 9042#define PIPE_CONF_CHECK_FLAGS(name, mask) \
9043 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 9044 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 9045 "(expected %i, found %i)\n", \
9046 current_config->name & (mask), \
9047 pipe_config->name & (mask)); \
9048 return false; \
9049 }
9050
5e550656
VS		 9051#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9052 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9053 DRM_ERROR("mismatch in " #name " " \
9054 "(expected %i, found %i)\n", \
9055 current_config->name, \
9056 pipe_config->name); \
9057 return false; \
9058 }
9059
bb760063
DV		 9060#define PIPE_CONF_QUIRK(quirk) \
9061 ((current_config->quirks | pipe_config->quirks) & (quirk))
9062
eccb140b
DV		 9063 PIPE_CONF_CHECK_I(cpu_transcoder);
9064
08a24034
DV		 9065 PIPE_CONF_CHECK_I(has_pch_encoder);
9066 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 9067 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9068 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9069 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9070 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9071 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 9072
eb14cb74
VS		 9073 PIPE_CONF_CHECK_I(has_dp_encoder);
9074 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9075 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9076 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9077 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9078 PIPE_CONF_CHECK_I(dp_m_n.tu);
9079
1bd1bd80
DV		 9080 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9081 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9082 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9083 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9084 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9085 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9086
9087 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9088 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9089 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9090 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9091 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9092 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9093
c93f54cf 9094 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 9095
1bd1bd80
DV		 9096 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9097 DRM_MODE_FLAG_INTERLACE);
9098
bb760063
DV		 9099 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9100 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9101 DRM_MODE_FLAG_PHSYNC);
9102 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9103 DRM_MODE_FLAG_NHSYNC);
9104 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9105 DRM_MODE_FLAG_PVSYNC);
9106 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9107 DRM_MODE_FLAG_NVSYNC);
9108 }
045ac3b5 9109
37327abd
VS		 9110 PIPE_CONF_CHECK_I(pipe_src_w);
9111 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 9112
2fa2fe9a
DV		 9113 PIPE_CONF_CHECK_I(gmch_pfit.control);
9114 /* pfit ratios are autocomputed by the hw on gen4+ */
9115 if (INTEL_INFO(dev)->gen < 4)
9116 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9117 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
fd4daa9c
CW		 9118 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9119 if (current_config->pch_pfit.enabled) {
9120 PIPE_CONF_CHECK_I(pch_pfit.pos);
9121 PIPE_CONF_CHECK_I(pch_pfit.size);
9122 }
2fa2fe9a 9123
42db64ef
PZ		 9124 PIPE_CONF_CHECK_I(ips_enabled);
9125
282740f7
VS		 9126 PIPE_CONF_CHECK_I(double_wide);
9127
c0d43d62 9128 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 9129 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 9130 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 9131 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9132 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 9133
42571aef
VS		 9134 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9135 PIPE_CONF_CHECK_I(pipe_bpp);
9136
d71b8d4a 9137 if (!IS_HASWELL(dev)) {
241bfc38 9138 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
d71b8d4a
VS		 9139 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9140 }
5e550656 9141
66e985c0 9142#undef PIPE_CONF_CHECK_X
08a24034 9143#undef PIPE_CONF_CHECK_I
1bd1bd80 9144#undef PIPE_CONF_CHECK_FLAGS
5e550656 9145#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 9146#undef PIPE_CONF_QUIRK
88adfff1 9147
0e8ffe1b
DV		 9148 return true;
9149}
9150
91d1b4bd
DV		 9151static void
9152check_connector_state(struct drm_device *dev)
8af6cf88 9153{
8af6cf88
DV		 9154 struct intel_connector *connector;
9155
9156 list_for_each_entry(connector, &dev->mode_config.connector_list,
9157 base.head) {
9158 /* This also checks the encoder/connector hw state with the
9159 * ->get_hw_state callbacks. */
9160 intel_connector_check_state(connector);
9161
9162 WARN(&connector->new_encoder->base != connector->base.encoder,
9163 "connector's staged encoder doesn't match current encoder\n");
9164 }
91d1b4bd
DV		 9165}
9166
9167static void
9168check_encoder_state(struct drm_device *dev)
9169{
9170 struct intel_encoder *encoder;
9171 struct intel_connector *connector;
8af6cf88
DV		 9172
9173 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9174 base.head) {
9175 bool enabled = false;
9176 bool active = false;
9177 enum pipe pipe, tracked_pipe;
9178
9179 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9180 encoder->base.base.id,
9181 drm_get_encoder_name(&encoder->base));
9182
9183 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9184 "encoder's stage crtc doesn't match current crtc\n");
9185 WARN(encoder->connectors_active && !encoder->base.crtc,
9186 "encoder's active_connectors set, but no crtc\n");
9187
9188 list_for_each_entry(connector, &dev->mode_config.connector_list,
9189 base.head) {
9190 if (connector->base.encoder != &encoder->base)
9191 continue;
9192 enabled = true;
9193 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9194 active = true;
9195 }
9196 WARN(!!encoder->base.crtc != enabled,
9197 "encoder's enabled state mismatch "
9198 "(expected %i, found %i)\n",
9199 !!encoder->base.crtc, enabled);
9200 WARN(active && !encoder->base.crtc,
9201 "active encoder with no crtc\n");
9202
9203 WARN(encoder->connectors_active != active,
9204 "encoder's computed active state doesn't match tracked active state "
9205 "(expected %i, found %i)\n", active, encoder->connectors_active);
9206
9207 active = encoder->get_hw_state(encoder, &pipe);
9208 WARN(active != encoder->connectors_active,
9209 "encoder's hw state doesn't match sw tracking "
9210 "(expected %i, found %i)\n",
9211 encoder->connectors_active, active);
9212
9213 if (!encoder->base.crtc)
9214 continue;
9215
9216 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9217 WARN(active && pipe != tracked_pipe,
9218 "active encoder's pipe doesn't match"
9219 "(expected %i, found %i)\n",
9220 tracked_pipe, pipe);
9221
9222 }
91d1b4bd
DV		 9223}
9224
9225static void
9226check_crtc_state(struct drm_device *dev)
9227{
9228 drm_i915_private_t *dev_priv = dev->dev_private;
9229 struct intel_crtc *crtc;
9230 struct intel_encoder *encoder;
9231 struct intel_crtc_config pipe_config;
8af6cf88
DV		 9232
9233 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9234 base.head) {
9235 bool enabled = false;
9236 bool active = false;
9237
045ac3b5
JB		 9238 memset(&pipe_config, 0, sizeof(pipe_config));
9239
8af6cf88
DV		 9240 DRM_DEBUG_KMS("[CRTC:%d]\n",
9241 crtc->base.base.id);
9242
9243 WARN(crtc->active && !crtc->base.enabled,
9244 "active crtc, but not enabled in sw tracking\n");
9245
9246 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9247 base.head) {
9248 if (encoder->base.crtc != &crtc->base)
9249 continue;
9250 enabled = true;
9251 if (encoder->connectors_active)
9252 active = true;
9253 }
6c49f241 9254
8af6cf88
DV		 9255 WARN(active != crtc->active,
9256 "crtc's computed active state doesn't match tracked active state "
9257 "(expected %i, found %i)\n", active, crtc->active);
9258 WARN(enabled != crtc->base.enabled,
9259 "crtc's computed enabled state doesn't match tracked enabled state "
9260 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9261
0e8ffe1b
DV		 9262 active = dev_priv->display.get_pipe_config(crtc,
9263 &pipe_config);
d62cf62a
DV		 9264
9265 /* hw state is inconsistent with the pipe A quirk */
9266 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9267 active = crtc->active;
9268
6c49f241
DV		 9269 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9270 base.head) {
3eaba51c 9271 enum pipe pipe;
6c49f241
DV		 9272 if (encoder->base.crtc != &crtc->base)
9273 continue;
1d37b689 9274 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 9275 encoder->get_config(encoder, &pipe_config);
9276 }
9277
0e8ffe1b
DV		 9278 WARN(crtc->active != active,
9279 "crtc active state doesn't match with hw state "
9280 "(expected %i, found %i)\n", crtc->active, active);
9281
c0b03411
DV		 9282 if (active &&
9283 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9284 WARN(1, "pipe state doesn't match!\n");
9285 intel_dump_pipe_config(crtc, &pipe_config,
9286 "[hw state]");
9287 intel_dump_pipe_config(crtc, &crtc->config,
9288 "[sw state]");
9289 }
8af6cf88
DV		 9290 }
9291}
9292
91d1b4bd
DV		 9293static void
9294check_shared_dpll_state(struct drm_device *dev)
9295{
9296 drm_i915_private_t *dev_priv = dev->dev_private;
9297 struct intel_crtc *crtc;
9298 struct intel_dpll_hw_state dpll_hw_state;
9299 int i;
5358901f
DV		 9300
9301 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9302 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9303 int enabled_crtcs = 0, active_crtcs = 0;
9304 bool active;
9305
9306 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9307
9308 DRM_DEBUG_KMS("%s\n", pll->name);
9309
9310 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9311
9312 WARN(pll->active > pll->refcount,
9313 "more active pll users than references: %i vs %i\n",
9314 pll->active, pll->refcount);
9315 WARN(pll->active && !pll->on,
9316 "pll in active use but not on in sw tracking\n");
35c95375
DV		 9317 WARN(pll->on && !pll->active,
9318 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 9319 WARN(pll->on != active,
9320 "pll on state mismatch (expected %i, found %i)\n",
9321 pll->on, active);
9322
9323 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9324 base.head) {
9325 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9326 enabled_crtcs++;
9327 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9328 active_crtcs++;
9329 }
9330 WARN(pll->active != active_crtcs,
9331 "pll active crtcs mismatch (expected %i, found %i)\n",
9332 pll->active, active_crtcs);
9333 WARN(pll->refcount != enabled_crtcs,
9334 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9335 pll->refcount, enabled_crtcs);
66e985c0
DV		 9336
9337 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9338 sizeof(dpll_hw_state)),
9339 "pll hw state mismatch\n");
5358901f 9340 }
8af6cf88
DV		 9341}
9342
91d1b4bd
DV		 9343void
9344intel_modeset_check_state(struct drm_device *dev)
9345{
9346 check_connector_state(dev);
9347 check_encoder_state(dev);
9348 check_crtc_state(dev);
9349 check_shared_dpll_state(dev);
9350}
9351
18442d08
VS		 9352void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9353 int dotclock)
9354{
9355 /*
9356 * FDI already provided one idea for the dotclock.
9357 * Yell if the encoder disagrees.
9358 */
241bfc38 9359 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
18442d08 9360 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
241bfc38 9361 pipe_config->adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 9362}
9363
f30da187
DV		 9364static int __intel_set_mode(struct drm_crtc *crtc,
9365 struct drm_display_mode *mode,
9366 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9367{
9368 struct drm_device *dev = crtc->dev;
dbf2b54e 9369 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9370 struct drm_display_mode *saved_mode, *saved_hwmode;
9371 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9372 struct intel_crtc *intel_crtc;
9373 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9374 int ret = 0;
a6778b3c 9375
a1e22653 9376 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9377 if (!saved_mode)
9378 return -ENOMEM;
3ac18232 9379 saved_hwmode = saved_mode + 1;
a6778b3c 9380
e2e1ed41 9381 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9382 &prepare_pipes, &disable_pipes);
9383
3ac18232
TG		 9384 *saved_hwmode = crtc->hwmode;
9385 *saved_mode = crtc->mode;
a6778b3c 9386
25c5b266
DV		 9387 /* Hack: Because we don't (yet) support global modeset on multiple
9388 * crtcs, we don't keep track of the new mode for more than one crtc.
9389 * Hence simply check whether any bit is set in modeset_pipes in all the
9390 * pieces of code that are not yet converted to deal with mutliple crtcs
9391 * changing their mode at the same time. */
25c5b266 9392 if (modeset_pipes) {
4e53c2e0 9393 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9394 if (IS_ERR(pipe_config)) {
9395 ret = PTR_ERR(pipe_config);
9396 pipe_config = NULL;
9397
3ac18232 9398 goto out;
25c5b266 9399 }
c0b03411
DV		 9400 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9401 "[modeset]");
25c5b266 9402 }
a6778b3c 9403
460da916
DV		 9404 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9405 intel_crtc_disable(&intel_crtc->base);
9406
ea9d758d
DV		 9407 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9408 if (intel_crtc->base.enabled)
9409 dev_priv->display.crtc_disable(&intel_crtc->base);
9410 }
a6778b3c 9411
6c4c86f5
DV		 9412 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9413 * to set it here already despite that we pass it down the callchain.
f6e5b160 9414 */
b8cecdf5 9415 if (modeset_pipes) {
25c5b266 9416 crtc->mode = *mode;
b8cecdf5
DV		 9417 /* mode_set/enable/disable functions rely on a correct pipe
9418 * config. */
9419 to_intel_crtc(crtc)->config = *pipe_config;
9420 }
7758a113 9421
ea9d758d
DV		 9422 /* Only after disabling all output pipelines that will be changed can we
9423 * update the the output configuration. */
9424 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9425
47fab737
DV		 9426 if (dev_priv->display.modeset_global_resources)
9427 dev_priv->display.modeset_global_resources(dev);
9428
a6778b3c
DV		 9429 /* Set up the DPLL and any encoders state that needs to adjust or depend
9430 * on the DPLL.
f6e5b160 9431 */
25c5b266 9432 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9433 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9434 x, y, fb);
9435 if (ret)
9436 goto done;
a6778b3c
DV		 9437 }
9438
9439 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9440 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9441 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9442
25c5b266
DV		 9443 if (modeset_pipes) {
9444 /* Store real post-adjustment hardware mode. */
b8cecdf5 9445 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9446
25c5b266
DV		 9447 /* Calculate and store various constants which
9448 * are later needed by vblank and swap-completion
9449 * timestamping. They are derived from true hwmode.
9450 */
9451 drm_calc_timestamping_constants(crtc);
9452 }
a6778b3c
DV		 9453
9454 /* FIXME: add subpixel order */
9455done:
c0c36b94 9456 if (ret && crtc->enabled) {
3ac18232
TG		 9457 crtc->hwmode = *saved_hwmode;
9458 crtc->mode = *saved_mode;
a6778b3c
DV		 9459 }
9460
3ac18232 9461out:
b8cecdf5 9462 kfree(pipe_config);
3ac18232 9463 kfree(saved_mode);
a6778b3c 9464 return ret;
f6e5b160
CW		 9465}
9466
e7457a9a
DL		 9467static int intel_set_mode(struct drm_crtc *crtc,
9468 struct drm_display_mode *mode,
9469 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9470{
9471 int ret;
9472
9473 ret = __intel_set_mode(crtc, mode, x, y, fb);
9474
9475 if (ret == 0)
9476 intel_modeset_check_state(crtc->dev);
9477
9478 return ret;
9479}
9480
c0c36b94
CW		 9481void intel_crtc_restore_mode(struct drm_crtc *crtc)
9482{
9483 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9484}
9485
25c5b266
DV		 9486#undef for_each_intel_crtc_masked
9487
d9e55608
DV		 9488static void intel_set_config_free(struct intel_set_config *config)
9489{
9490 if (!config)
9491 return;
9492
1aa4b628
DV		 9493 kfree(config->save_connector_encoders);
9494 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9495 kfree(config);
9496}
9497
85f9eb71
DV		 9498static int intel_set_config_save_state(struct drm_device *dev,
9499 struct intel_set_config *config)
9500{
85f9eb71
DV		 9501 struct drm_encoder *encoder;
9502 struct drm_connector *connector;
9503 int count;
9504
1aa4b628
DV		 9505 config->save_encoder_crtcs =
9506 kcalloc(dev->mode_config.num_encoder,
9507 sizeof(struct drm_crtc *), GFP_KERNEL);
9508 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9509 return -ENOMEM;
9510
1aa4b628
DV		 9511 config->save_connector_encoders =
9512 kcalloc(dev->mode_config.num_connector,
9513 sizeof(struct drm_encoder *), GFP_KERNEL);
9514 if (!config->save_connector_encoders)
85f9eb71
DV		 9515 return -ENOMEM;
9516
9517 /* Copy data. Note that driver private data is not affected.
9518 * Should anything bad happen only the expected state is
9519 * restored, not the drivers personal bookkeeping.
9520 */
85f9eb71
DV		 9521 count = 0;
9522 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9523 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9524 }
9525
9526 count = 0;
9527 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9528 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9529 }
9530
9531 return 0;
9532}
9533
9534static void intel_set_config_restore_state(struct drm_device *dev,
9535 struct intel_set_config *config)
9536{
9a935856
DV		 9537 struct intel_encoder *encoder;
9538 struct intel_connector *connector;
85f9eb71
DV		 9539 int count;
9540
85f9eb71 9541 count = 0;
9a935856
DV		 9542 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9543 encoder->new_crtc =
9544 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9545 }
9546
9547 count = 0;
9a935856
DV		 9548 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9549 connector->new_encoder =
9550 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9551 }
9552}
9553
e3de42b6 9554static bool
2e57f47d 9555is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9556{
9557 int i;
9558
2e57f47d
CW		 9559 if (set->num_connectors == 0)
9560 return false;
9561
9562 if (WARN_ON(set->connectors == NULL))
9563 return false;
9564
9565 for (i = 0; i < set->num_connectors; i++)
9566 if (set->connectors[i]->encoder &&
9567 set->connectors[i]->encoder->crtc == set->crtc &&
9568 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9569 return true;
9570
9571 return false;
9572}
9573
5e2b584e
DV		 9574static void
9575intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9576 struct intel_set_config *config)
9577{
9578
9579 /* We should be able to check here if the fb has the same properties
9580 * and then just flip_or_move it */
2e57f47d
CW		 9581 if (is_crtc_connector_off(set)) {
9582 config->mode_changed = true;
e3de42b6 9583 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9584 /* If we have no fb then treat it as a full mode set */
9585 if (set->crtc->fb == NULL) {
319d9827
JB		 9586 struct intel_crtc *intel_crtc =
9587 to_intel_crtc(set->crtc);
9588
9589 if (intel_crtc->active && i915_fastboot) {
9590 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9591 config->fb_changed = true;
9592 } else {
9593 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9594 config->mode_changed = true;
9595 }
5e2b584e
DV		 9596 } else if (set->fb == NULL) {
9597 config->mode_changed = true;
72f4901e
DV		 9598 } else if (set->fb->pixel_format !=
9599 set->crtc->fb->pixel_format) {
5e2b584e 9600 config->mode_changed = true;
e3de42b6 9601 } else {
5e2b584e 9602 config->fb_changed = true;
e3de42b6 9603 }
5e2b584e
DV		 9604 }
9605
835c5873 9606 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9607 config->fb_changed = true;
9608
9609 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9610 DRM_DEBUG_KMS("modes are different, full mode set\n");
9611 drm_mode_debug_printmodeline(&set->crtc->mode);
9612 drm_mode_debug_printmodeline(set->mode);
9613 config->mode_changed = true;
9614 }
a1d95703
CW		 9615
9616 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9617 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9618}
9619
2e431051 9620static int
9a935856
DV		 9621intel_modeset_stage_output_state(struct drm_device *dev,
9622 struct drm_mode_set *set,
9623 struct intel_set_config *config)
50f56119 9624{
85f9eb71 9625 struct drm_crtc *new_crtc;
9a935856
DV		 9626 struct intel_connector *connector;
9627 struct intel_encoder *encoder;
f3f08572 9628 int ro;
50f56119 9629
9abdda74 9630 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9631 * of connectors. For paranoia, double-check this. */
9632 WARN_ON(!set->fb && (set->num_connectors != 0));
9633 WARN_ON(set->fb && (set->num_connectors == 0));
9634
9a935856
DV		 9635 list_for_each_entry(connector, &dev->mode_config.connector_list,
9636 base.head) {
9637 /* Otherwise traverse passed in connector list and get encoders
9638 * for them. */
50f56119 9639 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9640 if (set->connectors[ro] == &connector->base) {
9641 connector->new_encoder = connector->encoder;
50f56119
DV		 9642 break;
9643 }
9644 }
9645
9a935856
DV		 9646 /* If we disable the crtc, disable all its connectors. Also, if
9647 * the connector is on the changing crtc but not on the new
9648 * connector list, disable it. */
9649 if ((!set->fb || ro == set->num_connectors) &&
9650 connector->base.encoder &&
9651 connector->base.encoder->crtc == set->crtc) {
9652 connector->new_encoder = NULL;
9653
9654 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9655 connector->base.base.id,
9656 drm_get_connector_name(&connector->base));
9657 }
9658
9659
9660 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9661 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9662 config->mode_changed = true;
50f56119
DV		 9663 }
9664 }
9a935856 9665 /* connector->new_encoder is now updated for all connectors. */
50f56119 9666
9a935856 9667 /* Update crtc of enabled connectors. */
9a935856
DV		 9668 list_for_each_entry(connector, &dev->mode_config.connector_list,
9669 base.head) {
9670 if (!connector->new_encoder)
50f56119
DV		 9671 continue;
9672
9a935856 9673 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9674
9675 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9676 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9677 new_crtc = set->crtc;
9678 }
9679
9680 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9681 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9682 new_crtc)) {
5e2b584e 9683 return -EINVAL;
50f56119 9684 }
9a935856
DV		 9685 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9686
9687 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9688 connector->base.base.id,
9689 drm_get_connector_name(&connector->base),
9690 new_crtc->base.id);
9691 }
9692
9693 /* Check for any encoders that needs to be disabled. */
9694 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9695 base.head) {
9696 list_for_each_entry(connector,
9697 &dev->mode_config.connector_list,
9698 base.head) {
9699 if (connector->new_encoder == encoder) {
9700 WARN_ON(!connector->new_encoder->new_crtc);
9701
9702 goto next_encoder;
9703 }
9704 }
9705 encoder->new_crtc = NULL;
9706next_encoder:
9707 /* Only now check for crtc changes so we don't miss encoders
9708 * that will be disabled. */
9709 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9710 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9711 config->mode_changed = true;
50f56119
DV		 9712 }
9713 }
9a935856 9714 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9715
2e431051
DV		 9716 return 0;
9717}
9718
9719static int intel_crtc_set_config(struct drm_mode_set *set)
9720{
9721 struct drm_device *dev;
2e431051
DV		 9722 struct drm_mode_set save_set;
9723 struct intel_set_config *config;
9724 int ret;
2e431051 9725
8d3e375e
DV		 9726 BUG_ON(!set);
9727 BUG_ON(!set->crtc);
9728 BUG_ON(!set->crtc->helper_private);
2e431051 9729
7e53f3a4
DV		 9730 /* Enforce sane interface api - has been abused by the fb helper. */
9731 BUG_ON(!set->mode && set->fb);
9732 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9733
2e431051
DV		 9734 if (set->fb) {
9735 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9736 set->crtc->base.id, set->fb->base.id,
9737 (int)set->num_connectors, set->x, set->y);
9738 } else {
9739 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9740 }
9741
9742 dev = set->crtc->dev;
9743
9744 ret = -ENOMEM;
9745 config = kzalloc(sizeof(*config), GFP_KERNEL);
9746 if (!config)
9747 goto out_config;
9748
9749 ret = intel_set_config_save_state(dev, config);
9750 if (ret)
9751 goto out_config;
9752
9753 save_set.crtc = set->crtc;
9754 save_set.mode = &set->crtc->mode;
9755 save_set.x = set->crtc->x;
9756 save_set.y = set->crtc->y;
9757 save_set.fb = set->crtc->fb;
9758
9759 /* Compute whether we need a full modeset, only an fb base update or no
9760 * change at all. In the future we might also check whether only the
9761 * mode changed, e.g. for LVDS where we only change the panel fitter in
9762 * such cases. */
9763 intel_set_config_compute_mode_changes(set, config);
9764
9a935856 9765 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9766 if (ret)
9767 goto fail;
9768
5e2b584e 9769 if (config->mode_changed) {
c0c36b94
CW		 9770 ret = intel_set_mode(set->crtc, set->mode,
9771 set->x, set->y, set->fb);
5e2b584e 9772 } else if (config->fb_changed) {
4878cae2
VS		 9773 intel_crtc_wait_for_pending_flips(set->crtc);
9774
4f660f49 9775 ret = intel_pipe_set_base(set->crtc,
94352cf9 9776 set->x, set->y, set->fb);
50f56119
DV		 9777 }
9778
2d05eae1 9779 if (ret) {
bf67dfeb
DV		 9780 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9781 set->crtc->base.id, ret);
50f56119 9782fail:
2d05eae1 9783 intel_set_config_restore_state(dev, config);
50f56119 9784
2d05eae1
CW		 9785 /* Try to restore the config */
9786 if (config->mode_changed &&
9787 intel_set_mode(save_set.crtc, save_set.mode,
9788 save_set.x, save_set.y, save_set.fb))
9789 DRM_ERROR("failed to restore config after modeset failure\n");
9790 }
50f56119 9791
d9e55608
DV		 9792out_config:
9793 intel_set_config_free(config);
50f56119
DV		 9794 return ret;
9795}
f6e5b160
CW		 9796
9797static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9798 .cursor_set = intel_crtc_cursor_set,
9799 .cursor_move = intel_crtc_cursor_move,
9800 .gamma_set = intel_crtc_gamma_set,
50f56119 9801 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9802 .destroy = intel_crtc_destroy,
9803 .page_flip = intel_crtc_page_flip,
9804};
9805
79f689aa
PZ		 9806static void intel_cpu_pll_init(struct drm_device *dev)
9807{
affa9354 9808 if (HAS_DDI(dev))
79f689aa
PZ		 9809 intel_ddi_pll_init(dev);
9810}
9811
5358901f
DV		 9812static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9813 struct intel_shared_dpll *pll,
9814 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9815{
5358901f 9816 uint32_t val;
ee7b9f93 9817
5358901f 9818 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9819 hw_state->dpll = val;
9820 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9821 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9822
9823 return val & DPLL_VCO_ENABLE;
9824}
9825
15bdd4cf
DV		 9826static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9827 struct intel_shared_dpll *pll)
9828{
9829 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9830 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9831}
9832
e7b903d2
DV		 9833static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9834 struct intel_shared_dpll *pll)
9835{
e7b903d2
DV		 9836 /* PCH refclock must be enabled first */
9837 assert_pch_refclk_enabled(dev_priv);
9838
15bdd4cf
DV		 9839 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9840
9841 /* Wait for the clocks to stabilize. */
9842 POSTING_READ(PCH_DPLL(pll->id));
9843 udelay(150);
9844
9845 /* The pixel multiplier can only be updated once the
9846 * DPLL is enabled and the clocks are stable.
9847 *
9848 * So write it again.
9849 */
9850 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9851 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9852 udelay(200);
9853}
9854
9855static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9856 struct intel_shared_dpll *pll)
9857{
9858 struct drm_device *dev = dev_priv->dev;
9859 struct intel_crtc *crtc;
e7b903d2
DV		 9860
9861 /* Make sure no transcoder isn't still depending on us. */
9862 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9863 if (intel_crtc_to_shared_dpll(crtc) == pll)
9864 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9865 }
9866
15bdd4cf
DV		 9867 I915_WRITE(PCH_DPLL(pll->id), 0);
9868 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9869 udelay(200);
9870}
9871
46edb027
DV		 9872static char *ibx_pch_dpll_names[] = {
9873 "PCH DPLL A",
9874 "PCH DPLL B",
9875};
9876
7c74ade1 9877static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9878{
e7b903d2 9879 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9880 int i;
9881
7c74ade1 9882 dev_priv->num_shared_dpll = 2;
ee7b9f93 9883
e72f9fbf 9884 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9885 dev_priv->shared_dplls[i].id = i;
9886 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9887 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9888 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9889 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9890 dev_priv->shared_dplls[i].get_hw_state =
9891 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9892 }
9893}
9894
7c74ade1
DV		 9895static void intel_shared_dpll_init(struct drm_device *dev)
9896{
e7b903d2 9897 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9898
9899 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9900 ibx_pch_dpll_init(dev);
9901 else
9902 dev_priv->num_shared_dpll = 0;
9903
9904 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9905 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9906 dev_priv->num_shared_dpll);
9907}
9908
b358d0a6 9909static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9910{
22fd0fab 9911 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9912 struct intel_crtc *intel_crtc;
9913 int i;
9914
955382f3 9915 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 9916 if (intel_crtc == NULL)
9917 return;
9918
9919 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9920
9921 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9922 for (i = 0; i < 256; i++) {
9923 intel_crtc->lut_r[i] = i;
9924 intel_crtc->lut_g[i] = i;
9925 intel_crtc->lut_b[i] = i;
9926 }
9927
80824003
JB		 9928 /* Swap pipes & planes for FBC on pre-965 */
9929 intel_crtc->pipe = pipe;
9930 intel_crtc->plane = pipe;
e2e767ab 9931 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9932 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9933 intel_crtc->plane = !pipe;
80824003
JB		 9934 }
9935
22fd0fab
JB		 9936 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9937 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9938 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9939 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9940
79e53945 9941 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9942}
9943
752aa88a
JB		 9944enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
9945{
9946 struct drm_encoder *encoder = connector->base.encoder;
9947
9948 WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
9949
9950 if (!encoder)
9951 return INVALID_PIPE;
9952
9953 return to_intel_crtc(encoder->crtc)->pipe;
9954}
9955
08d7b3d1 9956int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9957 struct drm_file *file)
08d7b3d1 9958{
08d7b3d1 9959 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9960 struct drm_mode_object *drmmode_obj;
9961 struct intel_crtc *crtc;
08d7b3d1 9962
1cff8f6b
DV		 9963 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9964 return -ENODEV;
08d7b3d1 9965
c05422d5
DV		 9966 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9967 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9968
c05422d5 9969 if (!drmmode_obj) {
08d7b3d1 9970 DRM_ERROR("no such CRTC id\n");
3f2c2057 9971 return -ENOENT;
08d7b3d1
CW		 9972 }
9973
c05422d5
DV		 9974 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9975 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9976
c05422d5 9977 return 0;
08d7b3d1
CW		 9978}
9979
66a9278e 9980static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9981{
66a9278e
DV		 9982 struct drm_device *dev = encoder->base.dev;
9983 struct intel_encoder *source_encoder;
79e53945 9984 int index_mask = 0;
79e53945
JB		 9985 int entry = 0;
9986
66a9278e
DV		 9987 list_for_each_entry(source_encoder,
9988 &dev->mode_config.encoder_list, base.head) {
9989
9990 if (encoder == source_encoder)
79e53945 9991 index_mask |= (1 << entry);
66a9278e
DV		 9992
9993 /* Intel hw has only one MUX where enocoders could be cloned. */
9994 if (encoder->cloneable && source_encoder->cloneable)
9995 index_mask |= (1 << entry);
9996
79e53945
JB		 9997 entry++;
9998 }
4ef69c7a 9999
79e53945
JB		 10000 return index_mask;
10001}
10002
4d302442
CW		 10003static bool has_edp_a(struct drm_device *dev)
10004{
10005 struct drm_i915_private *dev_priv = dev->dev_private;
10006
10007 if (!IS_MOBILE(dev))
10008 return false;
10009
10010 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10011 return false;
10012
10013 if (IS_GEN5(dev) &&
10014 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
10015 return false;
10016
10017 return true;
10018}
10019
79e53945
JB		 10020static void intel_setup_outputs(struct drm_device *dev)
10021{
725e30ad 10022 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 10023 struct intel_encoder *encoder;
cb0953d7 10024 bool dpd_is_edp = false;
79e53945 10025
c9093354 10026 intel_lvds_init(dev);
79e53945 10027
c40c0f5b 10028 if (!IS_ULT(dev))
79935fca 10029 intel_crt_init(dev);
cb0953d7 10030
affa9354 10031 if (HAS_DDI(dev)) {
0e72a5b5
ED		 10032 int found;
10033
10034 /* Haswell uses DDI functions to detect digital outputs */
10035 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10036 /* DDI A only supports eDP */
10037 if (found)
10038 intel_ddi_init(dev, PORT_A);
10039
10040 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10041 * register */
10042 found = I915_READ(SFUSE_STRAP);
10043
10044 if (found & SFUSE_STRAP_DDIB_DETECTED)
10045 intel_ddi_init(dev, PORT_B);
10046 if (found & SFUSE_STRAP_DDIC_DETECTED)
10047 intel_ddi_init(dev, PORT_C);
10048 if (found & SFUSE_STRAP_DDID_DETECTED)
10049 intel_ddi_init(dev, PORT_D);
10050 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 10051 int found;
5d8a7752 10052 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 10053
10054 if (has_edp_a(dev))
10055 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 10056
dc0fa718 10057 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 10058 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 10059 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 10060 if (!found)
e2debe91 10061 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 10062 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 10063 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 10064 }
10065
dc0fa718 10066 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 10067 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 10068
dc0fa718 10069 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 10070 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 10071
5eb08b69 10072 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 10073 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 10074
270b3042 10075 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 10076 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 10077 } else if (IS_VALLEYVIEW(dev)) {
585a94b8
AB		 10078 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10079 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10080 PORT_B);
10081 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10082 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10083 }
10084
6f6005a5
JB		 10085 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10086 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10087 PORT_C);
10088 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
5d8a7752 10089 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
6f6005a5 10090 }
19c03924 10091
3cfca973 10092 intel_dsi_init(dev);
103a196f 10093 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 10094 bool found = false;
7d57382e 10095
e2debe91 10096 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 10097 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 10098 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 10099 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10100 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 10101 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 10102 }
27185ae1 10103
e7281eab 10104 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 10105 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 10106 }
13520b05
KH		 10107
10108 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 10109
e2debe91 10110 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 10111 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 10112 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 10113 }
27185ae1 10114
e2debe91 10115 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 10116
b01f2c3a
JB		 10117 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10118 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 10119 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 10120 }
e7281eab 10121 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 10122 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 10123 }
27185ae1 10124
b01f2c3a 10125 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 10126 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 10127 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 10128 } else if (IS_GEN2(dev))
79e53945
JB		 10129 intel_dvo_init(dev);
10130
103a196f 10131 if (SUPPORTS_TV(dev))
79e53945
JB		 10132 intel_tv_init(dev);
10133
4ef69c7a
CW		 10134 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10135 encoder->base.possible_crtcs = encoder->crtc_mask;
10136 encoder->base.possible_clones =
66a9278e 10137 intel_encoder_clones(encoder);
79e53945 10138 }
47356eb6 10139
dde86e2d 10140 intel_init_pch_refclk(dev);
270b3042
DV		 10141
10142 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 10143}
10144
ddfe1567
CW		 10145void intel_framebuffer_fini(struct intel_framebuffer *fb)
10146{
10147 drm_framebuffer_cleanup(&fb->base);
80075d49 10148 WARN_ON(!fb->obj->framebuffer_references--);
ddfe1567
CW		 10149 drm_gem_object_unreference_unlocked(&fb->obj->base);
10150}
10151
79e53945
JB		 10152static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10153{
10154 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 10155
ddfe1567 10156 intel_framebuffer_fini(intel_fb);
79e53945
JB		 10157 kfree(intel_fb);
10158}
10159
10160static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 10161 struct drm_file *file,
79e53945
JB		 10162 unsigned int *handle)
10163{
10164 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 10165 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 10166
05394f39 10167 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 10168}
10169
10170static const struct drm_framebuffer_funcs intel_fb_funcs = {
10171 .destroy = intel_user_framebuffer_destroy,
10172 .create_handle = intel_user_framebuffer_create_handle,
10173};
10174
38651674
DA		 10175int intel_framebuffer_init(struct drm_device *dev,
10176 struct intel_framebuffer *intel_fb,
308e5bcb 10177 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 10178 struct drm_i915_gem_object *obj)
79e53945 10179{
53155c0a 10180 int aligned_height, tile_height;
a35cdaa0 10181 int pitch_limit;
79e53945
JB		 10182 int ret;
10183
dd4916c5
DV		 10184 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10185
c16ed4be
CW		 10186 if (obj->tiling_mode == I915_TILING_Y) {
10187 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 10188 return -EINVAL;
c16ed4be 10189 }
57cd6508 10190
c16ed4be
CW		 10191 if (mode_cmd->pitches[0] & 63) {
10192 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10193 mode_cmd->pitches[0]);
57cd6508 10194 return -EINVAL;
c16ed4be 10195 }
57cd6508 10196
a35cdaa0
CW		 10197 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10198 pitch_limit = 32*1024;
10199 } else if (INTEL_INFO(dev)->gen >= 4) {
10200 if (obj->tiling_mode)
10201 pitch_limit = 16*1024;
10202 else
10203 pitch_limit = 32*1024;
10204 } else if (INTEL_INFO(dev)->gen >= 3) {
10205 if (obj->tiling_mode)
10206 pitch_limit = 8*1024;
10207 else
10208 pitch_limit = 16*1024;
10209 } else
10210 /* XXX DSPC is limited to 4k tiled */
10211 pitch_limit = 8*1024;
10212
10213 if (mode_cmd->pitches[0] > pitch_limit) {
10214 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10215 obj->tiling_mode ? "tiled" : "linear",
10216 mode_cmd->pitches[0], pitch_limit);
5d7bd705 10217 return -EINVAL;
c16ed4be 10218 }
5d7bd705
VS		 10219
10220 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 10221 mode_cmd->pitches[0] != obj->stride) {
10222 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10223 mode_cmd->pitches[0], obj->stride);
5d7bd705 10224 return -EINVAL;
c16ed4be 10225 }
5d7bd705 10226
57779d06 10227 /* Reject formats not supported by any plane early. */
308e5bcb 10228 switch (mode_cmd->pixel_format) {
57779d06 10229 case DRM_FORMAT_C8:
04b3924d
VS		 10230 case DRM_FORMAT_RGB565:
10231 case DRM_FORMAT_XRGB8888:
10232 case DRM_FORMAT_ARGB8888:
57779d06
VS		 10233 break;
10234 case DRM_FORMAT_XRGB1555:
10235 case DRM_FORMAT_ARGB1555:
c16ed4be 10236 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 10237 DRM_DEBUG("unsupported pixel format: %s\n",
10238 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10239 return -EINVAL;
c16ed4be 10240 }
57779d06
VS		 10241 break;
10242 case DRM_FORMAT_XBGR8888:
10243 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 10244 case DRM_FORMAT_XRGB2101010:
10245 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 10246 case DRM_FORMAT_XBGR2101010:
10247 case DRM_FORMAT_ABGR2101010:
c16ed4be 10248 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 10249 DRM_DEBUG("unsupported pixel format: %s\n",
10250 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10251 return -EINVAL;
c16ed4be 10252 }
b5626747 10253 break;
04b3924d
VS		 10254 case DRM_FORMAT_YUYV:
10255 case DRM_FORMAT_UYVY:
10256 case DRM_FORMAT_YVYU:
10257 case DRM_FORMAT_VYUY:
c16ed4be 10258 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 10259 DRM_DEBUG("unsupported pixel format: %s\n",
10260 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10261 return -EINVAL;
c16ed4be 10262 }
57cd6508
CW		 10263 break;
10264 default:
4ee62c76
VS		 10265 DRM_DEBUG("unsupported pixel format: %s\n",
10266 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 10267 return -EINVAL;
10268 }
10269
90f9a336
VS		 10270 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10271 if (mode_cmd->offsets[0] != 0)
10272 return -EINVAL;
10273
53155c0a
DV		 10274 tile_height = IS_GEN2(dev) ? 16 : 8;
10275 aligned_height = ALIGN(mode_cmd->height,
10276 obj->tiling_mode ? tile_height : 1);
10277 /* FIXME drm helper for size checks (especially planar formats)? */
10278 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10279 return -EINVAL;
10280
c7d73f6a
DV		 10281 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10282 intel_fb->obj = obj;
80075d49 10283 intel_fb->obj->framebuffer_references++;
c7d73f6a 10284
79e53945
JB		 10285 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10286 if (ret) {
10287 DRM_ERROR("framebuffer init failed %d\n", ret);
10288 return ret;
10289 }
10290
79e53945
JB		 10291 return 0;
10292}
10293
79e53945
JB		 10294static struct drm_framebuffer *
10295intel_user_framebuffer_create(struct drm_device *dev,
10296 struct drm_file *filp,
308e5bcb 10297 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 10298{
05394f39 10299 struct drm_i915_gem_object *obj;
79e53945 10300
308e5bcb
JB		 10301 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10302 mode_cmd->handles[0]));
c8725226 10303 if (&obj->base == NULL)
cce13ff7 10304 return ERR_PTR(-ENOENT);
79e53945 10305
d2dff872 10306 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 10307}
10308
4520f53a 10309#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 10310static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 10311{
10312}
10313#endif
10314
79e53945 10315static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 10316 .fb_create = intel_user_framebuffer_create,
0632fef6 10317 .output_poll_changed = intel_fbdev_output_poll_changed,
79e53945
JB		 10318};
10319
e70236a8
JB		 10320/* Set up chip specific display functions */
10321static void intel_init_display(struct drm_device *dev)
10322{
10323 struct drm_i915_private *dev_priv = dev->dev_private;
10324
ee9300bb
DV		 10325 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10326 dev_priv->display.find_dpll = g4x_find_best_dpll;
10327 else if (IS_VALLEYVIEW(dev))
10328 dev_priv->display.find_dpll = vlv_find_best_dpll;
10329 else if (IS_PINEVIEW(dev))
10330 dev_priv->display.find_dpll = pnv_find_best_dpll;
10331 else
10332 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10333
affa9354 10334 if (HAS_DDI(dev)) {
0e8ffe1b 10335 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 10336 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 10337 dev_priv->display.crtc_enable = haswell_crtc_enable;
10338 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 10339 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 10340 dev_priv->display.update_plane = ironlake_update_plane;
10341 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 10342 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 10343 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 10344 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10345 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 10346 dev_priv->display.off = ironlake_crtc_off;
17638cd6 10347 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 10348 } else if (IS_VALLEYVIEW(dev)) {
10349 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10350 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10351 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10352 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10353 dev_priv->display.off = i9xx_crtc_off;
10354 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10355 } else {
0e8ffe1b 10356 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 10357 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 10358 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10359 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 10360 dev_priv->display.off = i9xx_crtc_off;
17638cd6 10361 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10362 }
e70236a8 10363
e70236a8 10364 /* Returns the core display clock speed */
25eb05fc
JB		 10365 if (IS_VALLEYVIEW(dev))
10366 dev_priv->display.get_display_clock_speed =
10367 valleyview_get_display_clock_speed;
10368 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 10369 dev_priv->display.get_display_clock_speed =
10370 i945_get_display_clock_speed;
10371 else if (IS_I915G(dev))
10372 dev_priv->display.get_display_clock_speed =
10373 i915_get_display_clock_speed;
257a7ffc 10374 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 10375 dev_priv->display.get_display_clock_speed =
10376 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 10377 else if (IS_PINEVIEW(dev))
10378 dev_priv->display.get_display_clock_speed =
10379 pnv_get_display_clock_speed;
e70236a8
JB		 10380 else if (IS_I915GM(dev))
10381 dev_priv->display.get_display_clock_speed =
10382 i915gm_get_display_clock_speed;
10383 else if (IS_I865G(dev))
10384 dev_priv->display.get_display_clock_speed =
10385 i865_get_display_clock_speed;
f0f8a9ce 10386 else if (IS_I85X(dev))
e70236a8
JB		 10387 dev_priv->display.get_display_clock_speed =
10388 i855_get_display_clock_speed;
10389 else /* 852, 830 */
10390 dev_priv->display.get_display_clock_speed =
10391 i830_get_display_clock_speed;
10392
7f8a8569 10393 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10394 if (IS_GEN5(dev)) {
674cf967 10395 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10396 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10397 } else if (IS_GEN6(dev)) {
674cf967 10398 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10399 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10400 } else if (IS_IVYBRIDGE(dev)) {
10401 /* FIXME: detect B0+ stepping and use auto training */
10402 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10403 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10404 dev_priv->display.modeset_global_resources =
10405 ivb_modeset_global_resources;
4e0bbc31 10406 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
c82e4d26 10407 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10408 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10409 dev_priv->display.modeset_global_resources =
10410 haswell_modeset_global_resources;
a0e63c22 10411 }
6067aaea 10412 } else if (IS_G4X(dev)) {
e0dac65e 10413 dev_priv->display.write_eld = g4x_write_eld;
9ca2fe73
ML		 10414 } else if (IS_VALLEYVIEW(dev))
10415 dev_priv->display.write_eld = ironlake_write_eld;
8c9f3aaf
JB		 10416
10417 /* Default just returns -ENODEV to indicate unsupported */
10418 dev_priv->display.queue_flip = intel_default_queue_flip;
10419
10420 switch (INTEL_INFO(dev)->gen) {
10421 case 2:
10422 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10423 break;
10424
10425 case 3:
10426 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10427 break;
10428
10429 case 4:
10430 case 5:
10431 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10432 break;
10433
10434 case 6:
10435 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10436 break;
7c9017e5 10437 case 7:
4e0bbc31 10438 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 10439 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10440 break;
8c9f3aaf 10441 }
e70236a8
JB		 10442}
10443
b690e96c
JB		 10444/*
10445 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10446 * resume, or other times. This quirk makes sure that's the case for
10447 * affected systems.
10448 */
0206e353 10449static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10450{
10451 struct drm_i915_private *dev_priv = dev->dev_private;
10452
10453 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10454 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10455}
10456
435793df
KP		 10457/*
10458 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10459 */
10460static void quirk_ssc_force_disable(struct drm_device *dev)
10461{
10462 struct drm_i915_private *dev_priv = dev->dev_private;
10463 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10464 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10465}
10466
4dca20ef 10467/*
5a15ab5b
CE		 10468 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10469 * brightness value
4dca20ef
CE		 10470 */
10471static void quirk_invert_brightness(struct drm_device *dev)
10472{
10473 struct drm_i915_private *dev_priv = dev->dev_private;
10474 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10475 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10476}
10477
e85843be
KM		 10478/*
10479 * Some machines (Dell XPS13) suffer broken backlight controls if
10480 * BLM_PCH_PWM_ENABLE is set.
10481 */
10482static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10483{
10484 struct drm_i915_private *dev_priv = dev->dev_private;
10485 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10486 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10487}
10488
b690e96c
JB		 10489struct intel_quirk {
10490 int device;
10491 int subsystem_vendor;
10492 int subsystem_device;
10493 void (*hook)(struct drm_device *dev);
10494};
10495
5f85f176
EE		 10496/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10497struct intel_dmi_quirk {
10498 void (*hook)(struct drm_device *dev);
10499 const struct dmi_system_id (*dmi_id_list)[];
10500};
10501
10502static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10503{
10504 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10505 return 1;
10506}
10507
10508static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10509 {
10510 .dmi_id_list = &(const struct dmi_system_id[]) {
10511 {
10512 .callback = intel_dmi_reverse_brightness,
10513 .ident = "NCR Corporation",
10514 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10515 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10516 },
10517 },
10518 { } /* terminating entry */
10519 },
10520 .hook = quirk_invert_brightness,
10521 },
10522};
10523
c43b5634 10524static struct intel_quirk intel_quirks[] = {
b690e96c 10525 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10526 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10527
b690e96c
JB		 10528 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10529 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10530
b690e96c
JB		 10531 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10532 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10533
a4945f95 10534 /* 830 needs to leave pipe A & dpll A up */
dcdaed6e 10535 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10536
10537 /* Lenovo U160 cannot use SSC on LVDS */
10538 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10539
10540 /* Sony Vaio Y cannot use SSC on LVDS */
10541 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 10542
ee1452d7
JN		 10543 /*
10544 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10545 * seem to use inverted backlight PWM.
10546 */
10547 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
e85843be
KM		 10548
10549 /* Dell XPS13 HD Sandy Bridge */
10550 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10551 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10552 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10553};
10554
10555static void intel_init_quirks(struct drm_device *dev)
10556{
10557 struct pci_dev *d = dev->pdev;
10558 int i;
10559
10560 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10561 struct intel_quirk *q = &intel_quirks[i];
10562
10563 if (d->device == q->device &&
10564 (d->subsystem_vendor == q->subsystem_vendor ||
10565 q->subsystem_vendor == PCI_ANY_ID) &&
10566 (d->subsystem_device == q->subsystem_device ||
10567 q->subsystem_device == PCI_ANY_ID))
10568 q->hook(dev);
10569 }
5f85f176
EE		 10570 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10571 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10572 intel_dmi_quirks[i].hook(dev);
10573 }
b690e96c
JB		 10574}
10575
9cce37f4
JB		 10576/* Disable the VGA plane that we never use */
10577static void i915_disable_vga(struct drm_device *dev)
10578{
10579 struct drm_i915_private *dev_priv = dev->dev_private;
10580 u8 sr1;
766aa1c4 10581 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10582
10583 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10584 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10585 sr1 = inb(VGA_SR_DATA);
10586 outb(sr1 | 1<<5, VGA_SR_DATA);
10587 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10588 udelay(300);
10589
10590 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10591 POSTING_READ(vga_reg);
10592}
10593
f817586c
DV		 10594void intel_modeset_init_hw(struct drm_device *dev)
10595{
f6071166
JB		 10596 struct drm_i915_private *dev_priv = dev->dev_private;
10597
a8f78b58
ED		 10598 intel_prepare_ddi(dev);
10599
f817586c
DV		 10600 intel_init_clock_gating(dev);
10601
f6071166
JB		 10602 /* Enable the CRI clock source so we can get at the display */
10603 if (IS_VALLEYVIEW(dev))
10604 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10605 DPLL_INTEGRATED_CRI_CLK_VLV);
10606
40e9cf64
JB		 10607 intel_init_dpio(dev);
10608
79f5b2c7 10609 mutex_lock(&dev->struct_mutex);
8090c6b9 10610 intel_enable_gt_powersave(dev);
79f5b2c7 10611 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10612}
10613
7d708ee4
ID		 10614void intel_modeset_suspend_hw(struct drm_device *dev)
10615{
10616 intel_suspend_hw(dev);
10617}
10618
79e53945
JB		 10619void intel_modeset_init(struct drm_device *dev)
10620{
652c393a 10621 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10622 int i, j, ret;
79e53945
JB		 10623
10624 drm_mode_config_init(dev);
10625
10626 dev->mode_config.min_width = 0;
10627 dev->mode_config.min_height = 0;
10628
019d96cb
DA		 10629 dev->mode_config.preferred_depth = 24;
10630 dev->mode_config.prefer_shadow = 1;
10631
e6ecefaa 10632 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10633
b690e96c
JB		 10634 intel_init_quirks(dev);
10635
1fa61106
ED		 10636 intel_init_pm(dev);
10637
e3c74757
BW		 10638 if (INTEL_INFO(dev)->num_pipes == 0)
10639 return;
10640
e70236a8
JB		 10641 intel_init_display(dev);
10642
a6c45cf0
CW		 10643 if (IS_GEN2(dev)) {
10644 dev->mode_config.max_width = 2048;
10645 dev->mode_config.max_height = 2048;
10646 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10647 dev->mode_config.max_width = 4096;
10648 dev->mode_config.max_height = 4096;
79e53945 10649 } else {
a6c45cf0
CW		 10650 dev->mode_config.max_width = 8192;
10651 dev->mode_config.max_height = 8192;
79e53945 10652 }
5d4545ae 10653 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10654
28c97730 10655 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10656 INTEL_INFO(dev)->num_pipes,
10657 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10658
08e2a7de 10659 for_each_pipe(i) {
79e53945 10660 intel_crtc_init(dev, i);
7f1f3851
JB		 10661 for (j = 0; j < dev_priv->num_plane; j++) {
10662 ret = intel_plane_init(dev, i, j);
10663 if (ret)
06da8da2
VS		 10664 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10665 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10666 }
79e53945
JB		 10667 }
10668
79f689aa 10669 intel_cpu_pll_init(dev);
e72f9fbf 10670 intel_shared_dpll_init(dev);
ee7b9f93 10671
9cce37f4
JB		 10672 /* Just disable it once at startup */
10673 i915_disable_vga(dev);
79e53945 10674 intel_setup_outputs(dev);
11be49eb
CW		 10675
10676 /* Just in case the BIOS is doing something questionable. */
10677 intel_disable_fbc(dev);
2c7111db
CW		 10678}
10679
24929352
DV		 10680static void
10681intel_connector_break_all_links(struct intel_connector *connector)
10682{
10683 connector->base.dpms = DRM_MODE_DPMS_OFF;
10684 connector->base.encoder = NULL;
10685 connector->encoder->connectors_active = false;
10686 connector->encoder->base.crtc = NULL;
10687}
10688
7fad798e
DV		 10689static void intel_enable_pipe_a(struct drm_device *dev)
10690{
10691 struct intel_connector *connector;
10692 struct drm_connector *crt = NULL;
10693 struct intel_load_detect_pipe load_detect_temp;
10694
10695 /* We can't just switch on the pipe A, we need to set things up with a
10696 * proper mode and output configuration. As a gross hack, enable pipe A
10697 * by enabling the load detect pipe once. */
10698 list_for_each_entry(connector,
10699 &dev->mode_config.connector_list,
10700 base.head) {
10701 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10702 crt = &connector->base;
10703 break;
10704 }
10705 }
10706
10707 if (!crt)
10708 return;
10709
10710 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10711 intel_release_load_detect_pipe(crt, &load_detect_temp);
10712
652c393a 10713
7fad798e
DV		 10714}
10715
fa555837
DV		 10716static bool
10717intel_check_plane_mapping(struct intel_crtc *crtc)
10718{
7eb552ae
BW		 10719 struct drm_device *dev = crtc->base.dev;
10720 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10721 u32 reg, val;
10722
7eb552ae 10723 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10724 return true;
10725
10726 reg = DSPCNTR(!crtc->plane);
10727 val = I915_READ(reg);
10728
10729 if ((val & DISPLAY_PLANE_ENABLE) &&
10730 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10731 return false;
10732
10733 return true;
10734}
10735
24929352
DV		 10736static void intel_sanitize_crtc(struct intel_crtc *crtc)
10737{
10738 struct drm_device *dev = crtc->base.dev;
10739 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10740 u32 reg;
24929352 10741
24929352 10742 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10743 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10744 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10745
10746 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10747 * disable the crtc (and hence change the state) if it is wrong. Note
10748 * that gen4+ has a fixed plane -> pipe mapping. */
10749 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10750 struct intel_connector *connector;
10751 bool plane;
10752
24929352
DV		 10753 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10754 crtc->base.base.id);
10755
10756 /* Pipe has the wrong plane attached and the plane is active.
10757 * Temporarily change the plane mapping and disable everything
10758 * ... */
10759 plane = crtc->plane;
10760 crtc->plane = !plane;
10761 dev_priv->display.crtc_disable(&crtc->base);
10762 crtc->plane = plane;
10763
10764 /* ... and break all links. */
10765 list_for_each_entry(connector, &dev->mode_config.connector_list,
10766 base.head) {
10767 if (connector->encoder->base.crtc != &crtc->base)
10768 continue;
10769
10770 intel_connector_break_all_links(connector);
10771 }
10772
10773 WARN_ON(crtc->active);
10774 crtc->base.enabled = false;
10775 }
24929352 10776
7fad798e
DV		 10777 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10778 crtc->pipe == PIPE_A && !crtc->active) {
10779 /* BIOS forgot to enable pipe A, this mostly happens after
10780 * resume. Force-enable the pipe to fix this, the update_dpms
10781 * call below we restore the pipe to the right state, but leave
10782 * the required bits on. */
10783 intel_enable_pipe_a(dev);
10784 }
10785
24929352
DV		 10786 /* Adjust the state of the output pipe according to whether we
10787 * have active connectors/encoders. */
10788 intel_crtc_update_dpms(&crtc->base);
10789
10790 if (crtc->active != crtc->base.enabled) {
10791 struct intel_encoder *encoder;
10792
10793 /* This can happen either due to bugs in the get_hw_state
10794 * functions or because the pipe is force-enabled due to the
10795 * pipe A quirk. */
10796 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10797 crtc->base.base.id,
10798 crtc->base.enabled ? "enabled" : "disabled",
10799 crtc->active ? "enabled" : "disabled");
10800
10801 crtc->base.enabled = crtc->active;
10802
10803 /* Because we only establish the connector -> encoder ->
10804 * crtc links if something is active, this means the
10805 * crtc is now deactivated. Break the links. connector
10806 * -> encoder links are only establish when things are
10807 * actually up, hence no need to break them. */
10808 WARN_ON(crtc->active);
10809
10810 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10811 WARN_ON(encoder->connectors_active);
10812 encoder->base.crtc = NULL;
10813 }
10814 }
10815}
10816
10817static void intel_sanitize_encoder(struct intel_encoder *encoder)
10818{
10819 struct intel_connector *connector;
10820 struct drm_device *dev = encoder->base.dev;
10821
10822 /* We need to check both for a crtc link (meaning that the
10823 * encoder is active and trying to read from a pipe) and the
10824 * pipe itself being active. */
10825 bool has_active_crtc = encoder->base.crtc &&
10826 to_intel_crtc(encoder->base.crtc)->active;
10827
10828 if (encoder->connectors_active && !has_active_crtc) {
10829 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10830 encoder->base.base.id,
10831 drm_get_encoder_name(&encoder->base));
10832
10833 /* Connector is active, but has no active pipe. This is
10834 * fallout from our resume register restoring. Disable
10835 * the encoder manually again. */
10836 if (encoder->base.crtc) {
10837 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10838 encoder->base.base.id,
10839 drm_get_encoder_name(&encoder->base));
10840 encoder->disable(encoder);
10841 }
10842
10843 /* Inconsistent output/port/pipe state happens presumably due to
10844 * a bug in one of the get_hw_state functions. Or someplace else
10845 * in our code, like the register restore mess on resume. Clamp
10846 * things to off as a safer default. */
10847 list_for_each_entry(connector,
10848 &dev->mode_config.connector_list,
10849 base.head) {
10850 if (connector->encoder != encoder)
10851 continue;
10852
10853 intel_connector_break_all_links(connector);
10854 }
10855 }
10856 /* Enabled encoders without active connectors will be fixed in
10857 * the crtc fixup. */
10858}
10859
44cec740 10860void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10861{
10862 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10863 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10864
8dc8a27c
PZ		 10865 /* This function can be called both from intel_modeset_setup_hw_state or
10866 * at a very early point in our resume sequence, where the power well
10867 * structures are not yet restored. Since this function is at a very
10868 * paranoid "someone might have enabled VGA while we were not looking"
10869 * level, just check if the power well is enabled instead of trying to
10870 * follow the "don't touch the power well if we don't need it" policy
10871 * the rest of the driver uses. */
10872 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10873 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10874 return;
10875
e1553faa 10876 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
0fde901f 10877 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10878 i915_disable_vga(dev);
0fde901f
KM		 10879 }
10880}
10881
30e984df 10882static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10883{
10884 struct drm_i915_private *dev_priv = dev->dev_private;
10885 enum pipe pipe;
24929352
DV		 10886 struct intel_crtc *crtc;
10887 struct intel_encoder *encoder;
10888 struct intel_connector *connector;
5358901f 10889 int i;
24929352 10890
0e8ffe1b
DV		 10891 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10892 base.head) {
88adfff1 10893 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10894
0e8ffe1b
DV		 10895 crtc->active = dev_priv->display.get_pipe_config(crtc,
10896 &crtc->config);
24929352
DV		 10897
10898 crtc->base.enabled = crtc->active;
4c445e0e 10899 crtc->primary_enabled = crtc->active;
24929352
DV		 10900
10901 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10902 crtc->base.base.id,
10903 crtc->active ? "enabled" : "disabled");
10904 }
10905
5358901f 10906 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10907 if (HAS_DDI(dev))
6441ab5f
PZ		 10908 intel_ddi_setup_hw_pll_state(dev);
10909
5358901f
DV		 10910 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10911 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10912
10913 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10914 pll->active = 0;
10915 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10916 base.head) {
10917 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10918 pll->active++;
10919 }
10920 pll->refcount = pll->active;
10921
35c95375
DV		 10922 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10923 pll->name, pll->refcount, pll->on);
5358901f
DV		 10924 }
10925
24929352
DV		 10926 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10927 base.head) {
10928 pipe = 0;
10929
10930 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10931 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10932 encoder->base.crtc = &crtc->base;
1d37b689 10933 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10934 } else {
10935 encoder->base.crtc = NULL;
10936 }
10937
10938 encoder->connectors_active = false;
6f2bcceb 10939 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352
DV		 10940 encoder->base.base.id,
10941 drm_get_encoder_name(&encoder->base),
10942 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 10943 pipe_name(pipe));
24929352
DV		 10944 }
10945
10946 list_for_each_entry(connector, &dev->mode_config.connector_list,
10947 base.head) {
10948 if (connector->get_hw_state(connector)) {
10949 connector->base.dpms = DRM_MODE_DPMS_ON;
10950 connector->encoder->connectors_active = true;
10951 connector->base.encoder = &connector->encoder->base;
10952 } else {
10953 connector->base.dpms = DRM_MODE_DPMS_OFF;
10954 connector->base.encoder = NULL;
10955 }
10956 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10957 connector->base.base.id,
10958 drm_get_connector_name(&connector->base),
10959 connector->base.encoder ? "enabled" : "disabled");
10960 }
30e984df
DV		 10961}
10962
10963/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10964 * and i915 state tracking structures. */
10965void intel_modeset_setup_hw_state(struct drm_device *dev,
10966 bool force_restore)
10967{
10968 struct drm_i915_private *dev_priv = dev->dev_private;
10969 enum pipe pipe;
30e984df
DV		 10970 struct intel_crtc *crtc;
10971 struct intel_encoder *encoder;
35c95375 10972 int i;
30e984df
DV		 10973
10974 intel_modeset_readout_hw_state(dev);
24929352 10975
babea61d
JB		 10976 /*
10977 * Now that we have the config, copy it to each CRTC struct
10978 * Note that this could go away if we move to using crtc_config
10979 * checking everywhere.
10980 */
10981 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10982 base.head) {
10983 if (crtc->active && i915_fastboot) {
10984 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10985
10986 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10987 crtc->base.base.id);
10988 drm_mode_debug_printmodeline(&crtc->base.mode);
10989 }
10990 }
10991
24929352
DV		 10992 /* HW state is read out, now we need to sanitize this mess. */
10993 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10994 base.head) {
10995 intel_sanitize_encoder(encoder);
10996 }
10997
10998 for_each_pipe(pipe) {
10999 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11000 intel_sanitize_crtc(crtc);
c0b03411 11001 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 11002 }
9a935856 11003
35c95375
DV		 11004 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11005 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11006
11007 if (!pll->on || pll->active)
11008 continue;
11009
11010 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11011
11012 pll->disable(dev_priv, pll);
11013 pll->on = false;
11014 }
11015
243e6a44
VS		 11016 if (IS_HASWELL(dev))
11017 ilk_wm_get_hw_state(dev);
11018
45e2b5f6 11019 if (force_restore) {
7d0bc1ea
VS		 11020 i915_redisable_vga(dev);
11021
f30da187
DV		 11022 /*
11023 * We need to use raw interfaces for restoring state to avoid
11024 * checking (bogus) intermediate states.
11025 */
45e2b5f6 11026 for_each_pipe(pipe) {
b5644d05
JB		 11027 struct drm_crtc *crtc =
11028 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 11029
11030 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11031 crtc->fb);
45e2b5f6
DV		 11032 }
11033 } else {
11034 intel_modeset_update_staged_output_state(dev);
11035 }
8af6cf88
DV		 11036
11037 intel_modeset_check_state(dev);
2e938892
DV		 11038
11039 drm_mode_config_reset(dev);
2c7111db
CW		 11040}
11041
11042void intel_modeset_gem_init(struct drm_device *dev)
11043{
1833b134 11044 intel_modeset_init_hw(dev);
02e792fb
DV		 11045
11046 intel_setup_overlay(dev);
24929352 11047
45e2b5f6 11048 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 11049}
11050
11051void intel_modeset_cleanup(struct drm_device *dev)
11052{
652c393a
JB		 11053 struct drm_i915_private *dev_priv = dev->dev_private;
11054 struct drm_crtc *crtc;
d9255d57 11055 struct drm_connector *connector;
652c393a 11056
fd0c0642
DV		 11057 /*
11058 * Interrupts and polling as the first thing to avoid creating havoc.
11059 * Too much stuff here (turning of rps, connectors, ...) would
11060 * experience fancy races otherwise.
11061 */
11062 drm_irq_uninstall(dev);
11063 cancel_work_sync(&dev_priv->hotplug_work);
11064 /*
11065 * Due to the hpd irq storm handling the hotplug work can re-arm the
11066 * poll handlers. Hence disable polling after hpd handling is shut down.
11067 */
f87ea761 11068 drm_kms_helper_poll_fini(dev);
fd0c0642 11069
652c393a
JB		 11070 mutex_lock(&dev->struct_mutex);
11071
723bfd70
JB		 11072 intel_unregister_dsm_handler();
11073
652c393a
JB		 11074 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11075 /* Skip inactive CRTCs */
11076 if (!crtc->fb)
11077 continue;
11078
3dec0095 11079 intel_increase_pllclock(crtc);
652c393a
JB		 11080 }
11081
973d04f9 11082 intel_disable_fbc(dev);
e70236a8 11083
8090c6b9 11084 intel_disable_gt_powersave(dev);
0cdab21f 11085
930ebb46
DV		 11086 ironlake_teardown_rc6(dev);
11087
69341a5e
KH		 11088 mutex_unlock(&dev->struct_mutex);
11089
1630fe75
CW		 11090 /* flush any delayed tasks or pending work */
11091 flush_scheduled_work();
11092
dc652f90
JN		 11093 /* destroy backlight, if any, before the connectors */
11094 intel_panel_destroy_backlight(dev);
11095
d9255d57
PZ		 11096 /* destroy the sysfs files before encoders/connectors */
11097 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
11098 drm_sysfs_connector_remove(connector);
11099
79e53945 11100 drm_mode_config_cleanup(dev);
4d7bb011
DV		 11101
11102 intel_cleanup_overlay(dev);
79e53945
JB		 11103}
11104
f1c79df3
ZW		 11105/*
11106 * Return which encoder is currently attached for connector.
11107 */
df0e9248 11108struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 11109{
df0e9248
CW		 11110 return &intel_attached_encoder(connector)->base;
11111}
f1c79df3 11112
df0e9248
CW		 11113void intel_connector_attach_encoder(struct intel_connector *connector,
11114 struct intel_encoder *encoder)
11115{
11116 connector->encoder = encoder;
11117 drm_mode_connector_attach_encoder(&connector->base,
11118 &encoder->base);
79e53945 11119}
28d52043
DA		 11120
11121/*
11122 * set vga decode state - true == enable VGA decode
11123 */
11124int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11125{
11126 struct drm_i915_private *dev_priv = dev->dev_private;
11127 u16 gmch_ctrl;
11128
11129 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
11130 if (state)
11131 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11132 else
11133 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11134 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
11135 return 0;
11136}
c4a1d9e4 11137
c4a1d9e4 11138struct intel_display_error_state {
ff57f1b0
PZ		 11139
11140 u32 power_well_driver;
11141
63b66e5b
CW		 11142 int num_transcoders;
11143
c4a1d9e4
CW		 11144 struct intel_cursor_error_state {
11145 u32 control;
11146 u32 position;
11147 u32 base;
11148 u32 size;
52331309 11149 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 11150
11151 struct intel_pipe_error_state {
c4a1d9e4 11152 u32 source;
52331309 11153 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 11154
11155 struct intel_plane_error_state {
11156 u32 control;
11157 u32 stride;
11158 u32 size;
11159 u32 pos;
11160 u32 addr;
11161 u32 surface;
11162 u32 tile_offset;
52331309 11163 } plane[I915_MAX_PIPES];
63b66e5b
CW		 11164
11165 struct intel_transcoder_error_state {
11166 enum transcoder cpu_transcoder;
11167
11168 u32 conf;
11169
11170 u32 htotal;
11171 u32 hblank;
11172 u32 hsync;
11173 u32 vtotal;
11174 u32 vblank;
11175 u32 vsync;
11176 } transcoder[4];
c4a1d9e4
CW		 11177};
11178
11179struct intel_display_error_state *
11180intel_display_capture_error_state(struct drm_device *dev)
11181{
0206e353 11182 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 11183 struct intel_display_error_state *error;
63b66e5b
CW		 11184 int transcoders[] = {
11185 TRANSCODER_A,
11186 TRANSCODER_B,
11187 TRANSCODER_C,
11188 TRANSCODER_EDP,
11189 };
c4a1d9e4
CW		 11190 int i;
11191
63b66e5b
CW		 11192 if (INTEL_INFO(dev)->num_pipes == 0)
11193 return NULL;
11194
9d1cb914 11195 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 11196 if (error == NULL)
11197 return NULL;
11198
ff57f1b0
PZ		 11199 if (HAS_POWER_WELL(dev))
11200 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11201
52331309 11202 for_each_pipe(i) {
9d1cb914
PZ		 11203 if (!intel_display_power_enabled(dev, POWER_DOMAIN_PIPE(i)))
11204 continue;
11205
a18c4c3d
PZ		 11206 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11207 error->cursor[i].control = I915_READ(CURCNTR(i));
11208 error->cursor[i].position = I915_READ(CURPOS(i));
11209 error->cursor[i].base = I915_READ(CURBASE(i));
11210 } else {
11211 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11212 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11213 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11214 }
c4a1d9e4
CW		 11215
11216 error->plane[i].control = I915_READ(DSPCNTR(i));
11217 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 11218 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 11219 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 11220 error->plane[i].pos = I915_READ(DSPPOS(i));
11221 }
ca291363
PZ		 11222 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11223 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 11224 if (INTEL_INFO(dev)->gen >= 4) {
11225 error->plane[i].surface = I915_READ(DSPSURF(i));
11226 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11227 }
11228
c4a1d9e4 11229 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 11230 }
11231
11232 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11233 if (HAS_DDI(dev_priv->dev))
11234 error->num_transcoders++; /* Account for eDP. */
11235
11236 for (i = 0; i < error->num_transcoders; i++) {
11237 enum transcoder cpu_transcoder = transcoders[i];
11238
9d1cb914
PZ		 11239 if (!intel_display_power_enabled(dev,
11240 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
11241 continue;
11242
63b66e5b
CW		 11243 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11244
11245 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11246 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11247 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11248 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11249 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11250 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11251 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 11252 }
11253
11254 return error;
11255}
11256
edc3d884
MK		 11257#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11258
c4a1d9e4 11259void
edc3d884 11260intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 11261 struct drm_device *dev,
11262 struct intel_display_error_state *error)
11263{
11264 int i;
11265
63b66e5b
CW		 11266 if (!error)
11267 return;
11268
edc3d884 11269 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 11270 if (HAS_POWER_WELL(dev))
edc3d884 11271 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 11272 error->power_well_driver);
52331309 11273 for_each_pipe(i) {
edc3d884 11274 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 11275 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 11276
11277 err_printf(m, "Plane [%d]:\n", i);
11278 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11279 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 11280 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 11281 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11282 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 11283 }
4b71a570 11284 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 11285 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 11286 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 11287 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11288 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 11289 }
11290
edc3d884
MK		 11291 err_printf(m, "Cursor [%d]:\n", i);
11292 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11293 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11294 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 11295 }
63b66e5b
CW		 11296
11297 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 11298 err_printf(m, "CPU transcoder: %c\n",
63b66e5b
CW		 11299 transcoder_name(error->transcoder[i].cpu_transcoder));
11300 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11301 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11302 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11303 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11304 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11305 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11306 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11307 }
c4a1d9e4 11308}
Linux kernel - Deliverables
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